1 /* { dg-do compile { target bitint } } */
2 /* { dg-additional-options "-std=c23 -O2 -fno-stack-protector -save-temps -fno-schedule-insns -fno-schedule-insns2 -fno-late-combine-instructions" } */
3 /* { dg-final { check-function-bodies "**" "" "" } } */
6 #include "bitfield-bitint-abi.h"
8 // f1-f16 are all the same
26 /* fp seems to be unable to optimize away stack-usage, TODO: to fix. */
36 // all other f1p-f8p generate the same code, for f16p the value comes from x2
53 // g1-g16 are all the same
58 ** and x4, \1, 9223372036854775807
68 ** and x4, \1, 9223372036854775807
77 ** and x4, \1, 9223372036854775807
83 // again gp different from the rest
90 ** sbfx x([0-9]+), \1, 0, 63
93 ** and x3, x\2, 9223372036854775807
102 // g1p-g8p are all the same, g16p uses x2 to pass parameter to f16p
107 ** and x3, x0, 9223372036854775807
116 ** and x3, x0, 9223372036854775807
126 ** and x4, \1, 9223372036854775807
132 // f*_stack are all the same
135 ** ldr (x[0-9]+), \[sp, 16\]
141 ** ldr (x[0-9]+), \[sp, 16\]
147 ** ldr (x[0-9]+), \[sp, 16\]
152 // fp{,1,8}_stack are all the same but fp16_stack loads from sp+16
155 ** ldr (x[0-9]+), \[sp, 8\]
161 ** ldr (x[0-9]+), \[sp, 8\]
167 ** ldr (x[0-9]+), \[sp, 8\]
174 ** ldr (x[0-9]+), \[sp, 16\]
183 ** sxtw (x[0-9]+), w1
185 ** and x7, \2, 9223372036854775807
188 ** strb wzr, \[sp, 16\]
194 ** str xzr, \[sp, 48\]
195 ** strb \3, \[sp, 48\]
196 ** ldr (x[0-9]+), \[sp, 48\]
197 ** stp x7, \4, \[sp\]
200 ** sbfx x0, x0, 0, 63
209 ** sxtw (x[0-9]+), w1
211 ** and x7, \2, 9223372036854775807
213 ** sbfx (x[0-9]+), \1, 0, 63
215 ** stp \3, xzr, \[sp, 16\]
224 ** sbfx x0, x0, 0, 63
234 ** sxtw (x[0-9]+), w1
236 ** and x7, \2, 9223372036854775807
238 ** sbfx (x[0-9]+), \1, 0, 63
240 ** stp \3, xzr, \[sp, 16\]
249 ** sbfx x0, x0, 0, 63
258 ** sxtw (x[0-9]+), w1
260 ** and (x[0-9]+), \2, 9223372036854775807
262 ** sbfx (x[0-9]+), \1, 0, 63
264 ** stp \4, xzr, \[sp, 16\]
273 ** sbfx x0, x0, 0, 63