gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vceqz_1.c

   1 /* This file tests an intrinsic which currently has only an f16 variant and that
   2    is only available when FP16 arithmetic instructions are supported.  */
   3 /* { dg-require-effective-target arm_v8_2a_fp16_neon_hw } */
   4
   5 #define INSN_NAME vceqz
   6 #define TEST_MSG "VCEQZ/VCEQZQ"
   7
   8 #include "cmp_zero_op.inc"
   9
  10 /* Expected results.  */
  11 #if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
  12 VECT_VAR_DECL (expected_float, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
  13 VECT_VAR_DECL (expected_q_float, uint, 16, 8) [] = { 0x0, 0x0, 0x0, 0x0,
  14                                                      0x0, 0x0, 0x0, 0x0 };
  15 #endif
  16
  17 /* Extra FP tests with special values (NaN, ....).  */
  18 #if defined (__ARM_FEATURE_FP16_VECTOR_ARITHMETIC)
  19 VECT_VAR_DECL (expected_nan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0  };
  20 VECT_VAR_DECL (expected_mnan, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
  21 VECT_VAR_DECL (expected_inf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
  22 VECT_VAR_DECL (expected_minf, uint, 16, 4) [] = { 0x0, 0x0, 0x0, 0x0 };
  23 VECT_VAR_DECL (expected_zero, uint, 16, 4) [] = { 0xffff, 0xffff,
  24                                                   0xffff, 0xffff };
  25 VECT_VAR_DECL (expected_mzero, uint, 16, 4) [] = { 0xffff, 0xffff,
  26                                                    0xffff, 0xffff };
  27 #endif