RISC-V: Add testcases for signed imm SAT_ADD form1
[official-gcc.git] / gcc / testsuite / gcc.dg / vect / vect-over-widen-21.c
blob361f77081a6d0a1d30051107f37aa4a4b764af4f
1 /* { dg-require-effective-target vect_int } */
2 /* { dg-require-effective-target vect_shift } */
3 /* { dg-require-effective-target vect_pack_trunc } */
4 /* { dg-require-effective-target vect_unpack } */
6 #include "tree-vect.h"
8 #define N 111
10 /* This shouldn't be treated as an over-widening operation: it's better
11 to reuse the extensions of di and ei for di + ei than to add them
12 as shorts and introduce a third extension. */
14 void __attribute__ ((noipa))
15 f (unsigned int *restrict a, unsigned int *restrict b,
16 unsigned int *restrict c, unsigned char *restrict d,
17 unsigned char *restrict e)
19 for (__INTPTR_TYPE__ i = 0; i < N; ++i)
21 a[i] = d[i];
22 b[i] = e[i];
23 c[i] = d[i] + e[i];
27 int
28 main (void)
30 check_vect ();
32 unsigned int a[N], b[N], c[N];
33 unsigned char d[N], e[N];
34 for (int i = 0; i < N; ++i)
36 d[i] = i * 2 + 3;
37 e[i] = i + 100;
38 asm volatile ("" ::: "memory");
40 f (a, b, c, d, e);
41 #pragma GCC novector
42 for (int i = 0; i < N; ++i)
43 if (a[i] != i * 2 + 3
44 || b[i] != i + 100
45 || c[i] != i * 3 + 103)
46 __builtin_abort ();
48 return 0;
51 /* { dg-final { scan-tree-dump-not {vect_recog_over_widening_pattern: detected} "vect" } } */
52 /* { dg-final { scan-tree-dump-times "vectorized 1 loop" 1 "vect" } } */