RISC-V: Add missing mode_idx for vrol and vror
[official-gcc.git] / gcc / testsuite / gcc.dg / vect / bb-slp-24.c
blob6de8dd8affce8e6f6ad40a36d6a163fc25b3fcf9
1 /* { dg-require-effective-target vect_int } */
3 #include <stdarg.h>
4 #include "tree-vect.h"
6 #define A 3
7 #define N 256
9 short src[N], dst[N];
11 void foo (short * __restrict__ dst, short * __restrict__ src, int h,
12 int stride)
14 int i;
15 h /= 8;
16 for (i = 0; i < h; i++)
18 dst[0] += A*src[0];
19 dst[1] += A*src[1];
20 dst[2] += A*src[2];
21 dst[3] += A*src[3];
22 dst[4] += A*src[4];
23 dst[5] += A*src[5];
24 dst[6] += A*src[6];
25 dst[7] += A*src[7];
26 dst += stride;
27 src += stride;
28 asm volatile ("" ::: "memory");
33 int main (void)
35 int i;
37 check_vect ();
39 for (i = 0; i < N; i++)
41 dst[i] = 0;
42 src[i] = i;
45 foo (dst, src, N, 8);
47 #pragma GCC novector
48 for (i = 0; i < N; i++)
50 if (dst[i] != A * i)
51 abort ();
54 return 0;
57 /* Exclude POWER8 (only POWER cpu for which vect_element_align is true)
58 because loops have vectorized before SLP gets a shot. */
59 /* { dg-final { scan-tree-dump-times "optimized: basic block" 1 "slp1" { target { vect_element_align && { ! powerpc*-*-* } } } } } */