AVR: target/84211 - Add a post reload register optimization pass.
[official-gcc.git] / gcc / testsuite / gcc.dg / torture / float64x-builtin-issignaling-1.c
blobfe6420aaa95b77614a9636464c7a44bb2e5e5f0e
1 /* Test _Float64x __builtin_issignaling. */
2 /* { dg-do run } */
3 /* { dg-options "" } */
4 /* { dg-add-options float64x } */
5 /* { dg-add-options ieee } */
6 /* { dg-require-effective-target float64x_runtime } */
7 /* { dg-additional-options "-fsignaling-nans" } */
8 /* Workaround for PR57484 on ia32: */
9 /* { dg-additional-options "-msse2 -mfpmath=sse" { target { ia32 && sse2_runtime } } } */
11 #define WIDTH 64
12 #define EXT 1
13 #include "builtin-issignaling-1.c"