1 /* Definitions of target machine for GNU compiler
, for IBM RS
/6000.
2 Copyright (C
) 2002-2024 Free Software Foundation
, Inc.
3 Contributed by Richard
Kenner (kenner@vlsi1.ultra.nyu.edu
)
5 This file is part of GCC.
7 GCC is free software
; you can redistribute it and
/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation
; either version
3, or (at your
10 option
) any later version.
12 GCC is distributed in the hope that it will be useful
, but WITHOUT
13 ANY WARRANTY
; without even the implied warranty of MERCHANTABILITY
14 or FITNESS
FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC
; see the file COPYING3. If not see
19 <http
://www.gnu.org
/licenses
/>.
*/
21 /* We order the
3 128-bit floating point type modes here as KFmode
, TFmode and
22 IFmode
, it is the same as the previous order
, to make machine independent
23 parts of the compiler do not try to widen IFmode to TFmode on ISA
3.0
24 (power9
) that has hardware support for IEEE
128-bit. We set
TFmode (long
25 double mode
) in between
, and
KFmode (explicit __float128
) below it.
27 Previously
, IFmode and KFmode were defined to be fractional modes and TFmode
28 was the standard mode. Since IFmode does not define the normal arithmetic
29 insns (other than neg
/abs
), on a ISA
3.0 system
, the machine independent
30 parts of the compiler would see that TFmode has the necessary hardware
31 support
, and widen the operation from IFmode to TFmode. However
, IEEE
32 128-bit is not strictly a super
-set of IBM extended double and the
33 conversion to
/from IEEE
128-bit was a function call.
35 We now place IFmode last
, which means its values are not considered for
36 widening. Since we don
't define insns for IFmode, the IEEE 128-bit modes
37 would not widen to IFmode. */
39 /* Explicit IEEE 128-bit floating point. */
40 FLOAT_MODE (KF, 16, ieee_quad_format);
41 /* 128-bit floating point, either IBM 128-bit or IEEE 128-bit. This is
42 adjusted in rs6000_option_override_internal to be the appropriate floating
44 FLOAT_MODE (TF, 16, ieee_quad_format);
45 /* IBM 128-bit floating point. */
46 FLOAT_MODE (IF, 16, ibm_extended_format);
48 /* Add any extra modes needed to represent the condition code.
50 For the RS/6000, we need separate modes when unsigned (logical) comparisons
51 are being done and we need a separate mode for floating-point. We also
52 use a mode for the case when we are comparing the results of two
53 comparisons, as then only the EQ bit is valid in the register. */
62 VECTOR_MODES (INT, 16); /* V16QI V8HI V4SI V2DI */
63 VECTOR_MODE (INT, TI, 1); /* V1TI */
64 VECTOR_MODES (FLOAT, 16); /* V8HF V4SF V2DF */
66 /* Two VMX/VSX vectors (for permute, select, concat, etc.) */
67 VECTOR_MODES (INT, 32); /* V32QI V16HI V8SI V4DI */
68 VECTOR_MODES (FLOAT, 32); /* V16HF V8SF V4DF */
70 /* Half VMX/VSX vector (for internal use) */
71 VECTOR_MODE (FLOAT, SF, 2); /* V2SF */
72 VECTOR_MODE (INT, SI, 2); /* V2SI */
74 /* Replacement for TImode that only is allowed in GPRs. We also use PTImode
75 for quad memory atomic operations to force getting an even/odd register
77 PARTIAL_INT_MODE (TI, 128, PTI);
79 /* Modes used by __vector_pair and __vector_quad. */