1 ;; Scheduling description for XiangShan Nanhu.
3 ;; Nanhu is a 6-issue, superscalar, out-of-order processor.
5 ;; -----------------------------------------------------
7 ;; 1*jmp + 4*alu + 2*mdu + 4*fma + 2*fmisc + 2*ld + 2*st
8 ;; -----------------------------------------------------
10 (define_automaton "xiangshan")
12 (define_cpu_unit "xs_jmp" "xiangshan")
13 (define_cpu_unit "xs_i2f" "xiangshan")
14 (define_reservation "xs_jmp_rs" "xs_jmp | xs_i2f")
16 (define_cpu_unit "xs_alu_0, xs_alu_1, xs_alu_2, xs_alu_3" "xiangshan")
17 (define_reservation "xs_alu_rs"
18 "xs_alu_0 | xs_alu_1 | xs_alu_2 | xs_alu_3")
20 (define_cpu_unit "xs_mul_0, xs_mul_1" "xiangshan")
21 (define_cpu_unit "xs_div_0, xs_div_1" "xiangshan")
22 (define_reservation "xs_mdu_rs"
23 "(xs_mul_0 + xs_div_0) | (xs_mul_1 + xs_div_1)")
25 (define_cpu_unit "xs_fadd_0, xs_fadd_1, xs_fadd_2, xs_fadd_3" "xiangshan")
26 (define_cpu_unit "xs_fmul_0, xs_fmul_1, xs_fmul_2, xs_fmul_3" "xiangshan")
27 (define_reservation "xs_fma_0" "xs_fadd_0 + xs_fmul_0")
28 (define_reservation "xs_fma_1" "xs_fadd_1 + xs_fmul_1")
29 (define_reservation "xs_fma_2" "xs_fadd_2 + xs_fmul_2")
30 (define_reservation "xs_fma_3" "xs_fadd_3 + xs_fmul_3")
32 (define_cpu_unit "xs_f2f_0, xs_f2f_1" "xiangshan")
33 (define_cpu_unit "xs_f2i_0, xs_f2i_1" "xiangshan")
34 (define_cpu_unit "xs_fdiv_0, xs_fdiv_1" "xiangshan")
35 (define_reservation "xs_fmisc_rs"
36 "(xs_f2f_0 + xs_f2i_0 + xs_fdiv_0) | (xs_f2f_1 + xs_f2i_1 + xs_fdiv_1)")
38 (define_cpu_unit "xs_ld_0, xs_ld_1" "xiangshan")
39 (define_cpu_unit "xs_st_0, xs_st_1" "xiangshan")
40 (define_reservation "xs_ld_rs" "xs_ld_0 | xs_ld_1")
41 (define_reservation "xs_st_rs" "xs_st_0 | xs_st_1")
43 ;; ----------------------------------------------------
44 ;; Memory (load/store)
45 ;; ----------------------------------------------------
47 (define_insn_reservation "xiangshan_load" 3
48 (and (eq_attr "tune" "xiangshan")
49 (eq_attr "type" "load"))
52 (define_insn_reservation "xiangshan_fpload" 3
53 (and (eq_attr "tune" "xiangshan")
54 (eq_attr "type" "fpload"))
57 (define_insn_reservation "xiangshan_store" 1
58 (and (eq_attr "tune" "xiangshan")
59 (eq_attr "type" "store"))
62 (define_insn_reservation "xiangshan_fpstore" 1
63 (and (eq_attr "tune" "xiangshan")
64 (eq_attr "type" "fpstore"))
67 ;; ----------------------------------------------------
69 ;; ----------------------------------------------------
71 (define_insn_reservation "xiangshan_jump" 1
72 (and (eq_attr "tune" "xiangshan")
73 (eq_attr "type" "jump,call,auipc,unknown,branch,jalr,ret,sfb_alu"))
76 (define_insn_reservation "xiangshan_i2f" 3
77 (and (eq_attr "tune" "xiangshan")
78 (eq_attr "type" "mtc"))
81 (define_insn_reservation "xiangshan_mul" 3
82 (and (eq_attr "tune" "xiangshan")
83 (eq_attr "type" "imul"))
86 (define_insn_reservation "xiangshan_div" 21
87 (and (eq_attr "tune" "xiangshan")
88 (eq_attr "type" "idiv"))
91 (define_insn_reservation "xiangshan_alu" 1
92 (and (eq_attr "tune" "xiangshan")
93 (eq_attr "type" "nop,const,branch,arith,shift,slt,multi,logical,move,bitmanip,unknown"))
96 ;; ----------------------------------------------------
98 ;; ----------------------------------------------------
101 (define_insn_reservation "xiangshan_fma" 5
102 (and (eq_attr "tune" "xiangshan")
103 (eq_attr "type" "fmadd"))
104 "xs_fma_0 | xs_fma_1 | xs_fma_2 | xs_fma_3")
106 (define_insn_reservation "xiangshan_fadd" 3
107 (and (eq_attr "tune" "xiangshan")
108 (eq_attr "type" "fadd"))
109 "xs_fadd_0 | xs_fadd_1 | xs_fadd_2 | xs_fadd_3")
111 (define_insn_reservation "xiangshan_fmul" 3
112 (and (eq_attr "tune" "xiangshan")
113 (eq_attr "type" "fmul"))
114 "xs_fmul_0 | xs_fmul_1 | xs_fmul_2 | xs_fmul_3")
116 (define_insn_reservation "xiangshan_f2f" 3
117 (and (eq_attr "tune" "xiangshan")
118 (eq_attr "type" "fcvt,fmove"))
121 (define_insn_reservation "xiangshan_f2i" 3
122 (and (eq_attr "tune" "xiangshan")
123 (eq_attr "type" "mfc,fcmp"))
126 (define_insn_reservation "xiangshan_sfdiv" 11
127 (and (eq_attr "tune" "xiangshan")
128 (eq_attr "type" "fdiv")
129 (eq_attr "mode" "SF"))
132 (define_insn_reservation "xiangshan_sfsqrt" 17
133 (and (eq_attr "tune" "xiangshan")
134 (eq_attr "type" "fsqrt")
135 (eq_attr "mode" "SF"))
138 (define_insn_reservation "xiangshan_dfdiv" 21
139 (and (eq_attr "tune" "xiangshan")
140 (eq_attr "type" "fdiv")
141 (eq_attr "mode" "DF"))
144 (define_insn_reservation "xiangshan_dfsqrt" 37
145 (and (eq_attr "tune" "xiangshan")
146 (eq_attr "type" "fsqrt")
147 (eq_attr "mode" "DF"))