2 ;; Iterators for RISC-V 'V' Extension for GNU compiler.
3 ;; Copyright (C) 2022-2024 Free Software Foundation, Inc.
4 ;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 (define_c_enum "unspec" [
30 ;; It's used to specify ordered/unorderd operation.
34 ;; vmulh/vmulhu/vmulhsu
88 ;; Integer and Float Reduction
91 UNSPEC_REDUC_SUM_ORDERED
92 UNSPEC_REDUC_SUM_UNORDERED
103 UNSPEC_WREDUC_SUM_ORDERED
104 UNSPEC_WREDUC_SUM_UNORDERED
108 (define_c_enum "unspecv" [
109 UNSPECV_FRM_RESTORE_EXIT
112 ;; Subset of VI with fractional LMUL types
113 (define_mode_iterator VI_FRAC [
114 RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
115 RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
116 (RVVMF2SI "TARGET_MIN_VLEN > 32")
119 ;; Subset of VI with non-fractional LMUL types
120 (define_mode_iterator VI_NOFRAC [
121 RVVM8QI RVVM4QI RVVM2QI RVVM1QI
122 RVVM8HI RVVM4HI RVVM2HI RVVM1HI
123 RVVM8SI RVVM4SI RVVM2SI RVVM1SI
124 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
125 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
128 (define_mode_iterator VI [ VI_NOFRAC (VI_FRAC "!TARGET_XTHEADVECTOR") ])
130 ;; This iterator is the same as above but with TARGET_VECTOR_ELEN_FP_16
131 ;; changed to TARGET_ZVFH. TARGET_VECTOR_ELEN_FP_16 is also true for
132 ;; TARGET_ZVFHMIN while we actually want to disable all instructions apart
133 ;; from load, store and convert for it.
134 ;; It is not enough to set the "enabled" attribute to false
135 ;; since this will only disable insn alternatives in reload but still
136 ;; allow the instruction and mode to be matched during combine et al.
137 (define_mode_iterator VF [
138 (RVVM8HF "TARGET_ZVFH") (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH")
139 (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH")
140 (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
142 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
143 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
145 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
146 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
149 (define_mode_iterator VF_ZVFHMIN [
150 (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16")
151 (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16")
152 (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
154 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
155 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
157 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
158 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
161 (define_mode_iterator VLSI [
162 (V1QI "riscv_vector::vls_mode_valid_p (V1QImode)")
163 (V2QI "riscv_vector::vls_mode_valid_p (V2QImode)")
164 (V4QI "riscv_vector::vls_mode_valid_p (V4QImode)")
165 (V8QI "riscv_vector::vls_mode_valid_p (V8QImode)")
166 (V16QI "riscv_vector::vls_mode_valid_p (V16QImode)")
167 (V32QI "riscv_vector::vls_mode_valid_p (V32QImode)")
168 (V64QI "riscv_vector::vls_mode_valid_p (V64QImode) && TARGET_MIN_VLEN >= 64")
169 (V128QI "riscv_vector::vls_mode_valid_p (V128QImode) && TARGET_MIN_VLEN >= 128")
170 (V256QI "riscv_vector::vls_mode_valid_p (V256QImode) && TARGET_MIN_VLEN >= 256")
171 (V512QI "riscv_vector::vls_mode_valid_p (V512QImode) && TARGET_MIN_VLEN >= 512")
172 (V1024QI "riscv_vector::vls_mode_valid_p (V1024QImode) && TARGET_MIN_VLEN >= 1024")
173 (V2048QI "riscv_vector::vls_mode_valid_p (V2048QImode) && TARGET_MIN_VLEN >= 2048")
174 (V4096QI "riscv_vector::vls_mode_valid_p (V4096QImode) && TARGET_MIN_VLEN >= 4096")
175 (V1HI "riscv_vector::vls_mode_valid_p (V1HImode)")
176 (V2HI "riscv_vector::vls_mode_valid_p (V2HImode)")
177 (V4HI "riscv_vector::vls_mode_valid_p (V4HImode)")
178 (V8HI "riscv_vector::vls_mode_valid_p (V8HImode)")
179 (V16HI "riscv_vector::vls_mode_valid_p (V16HImode)")
180 (V32HI "riscv_vector::vls_mode_valid_p (V32HImode) && TARGET_MIN_VLEN >= 64")
181 (V64HI "riscv_vector::vls_mode_valid_p (V64HImode) && TARGET_MIN_VLEN >= 128")
182 (V128HI "riscv_vector::vls_mode_valid_p (V128HImode) && TARGET_MIN_VLEN >= 256")
183 (V256HI "riscv_vector::vls_mode_valid_p (V256HImode) && TARGET_MIN_VLEN >= 512")
184 (V512HI "riscv_vector::vls_mode_valid_p (V512HImode) && TARGET_MIN_VLEN >= 1024")
185 (V1024HI "riscv_vector::vls_mode_valid_p (V1024HImode) && TARGET_MIN_VLEN >= 2048")
186 (V2048HI "riscv_vector::vls_mode_valid_p (V2048HImode) && TARGET_MIN_VLEN >= 4096")
187 (V1SI "riscv_vector::vls_mode_valid_p (V1SImode)")
188 (V2SI "riscv_vector::vls_mode_valid_p (V2SImode)")
189 (V4SI "riscv_vector::vls_mode_valid_p (V4SImode)")
190 (V8SI "riscv_vector::vls_mode_valid_p (V8SImode)")
191 (V16SI "riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= 64")
192 (V32SI "riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= 128")
193 (V64SI "riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= 256")
194 (V128SI "riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= 512")
195 (V256SI "riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_MIN_VLEN >= 1024")
196 (V512SI "riscv_vector::vls_mode_valid_p (V512SImode) && TARGET_MIN_VLEN >= 2048")
197 (V1024SI "riscv_vector::vls_mode_valid_p (V1024SImode) && TARGET_MIN_VLEN >= 4096")
198 (V1DI "riscv_vector::vls_mode_valid_p (V1DImode) && TARGET_VECTOR_ELEN_64")
199 (V2DI "riscv_vector::vls_mode_valid_p (V2DImode) && TARGET_VECTOR_ELEN_64")
200 (V4DI "riscv_vector::vls_mode_valid_p (V4DImode) && TARGET_VECTOR_ELEN_64")
201 (V8DI "riscv_vector::vls_mode_valid_p (V8DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64")
202 (V16DI "riscv_vector::vls_mode_valid_p (V16DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
203 (V32DI "riscv_vector::vls_mode_valid_p (V32DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256")
204 (V64DI "riscv_vector::vls_mode_valid_p (V64DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512")
205 (V128DI "riscv_vector::vls_mode_valid_p (V128DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024")
206 (V256DI "riscv_vector::vls_mode_valid_p (V256DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048")
207 (V512DI "riscv_vector::vls_mode_valid_p (V512DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")])
209 (define_mode_iterator VLSF [
210 (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_ZVFH")
211 (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_ZVFH")
212 (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_ZVFH")
213 (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_ZVFH")
214 (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_ZVFH")
215 (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 64")
216 (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
217 (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 256")
218 (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 512")
219 (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024")
220 (V1024HF "riscv_vector::vls_mode_valid_p (V1024HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 2048")
221 (V2048HF "riscv_vector::vls_mode_valid_p (V2048HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 4096")
222 (V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_FP_32")
223 (V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_FP_32")
224 (V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_FP_32")
225 (V8SF "riscv_vector::vls_mode_valid_p (V8SFmode) && TARGET_VECTOR_ELEN_FP_32")
226 (V16SF "riscv_vector::vls_mode_valid_p (V16SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
227 (V32SF "riscv_vector::vls_mode_valid_p (V32SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
228 (V64SF "riscv_vector::vls_mode_valid_p (V64SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
229 (V128SF "riscv_vector::vls_mode_valid_p (V128SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
230 (V256SF "riscv_vector::vls_mode_valid_p (V256SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
231 (V512SF "riscv_vector::vls_mode_valid_p (V512SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
232 (V1024SF "riscv_vector::vls_mode_valid_p (V1024SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
233 (V1DF "riscv_vector::vls_mode_valid_p (V1DFmode) && TARGET_VECTOR_ELEN_FP_64")
234 (V2DF "riscv_vector::vls_mode_valid_p (V2DFmode) && TARGET_VECTOR_ELEN_FP_64")
235 (V4DF "riscv_vector::vls_mode_valid_p (V4DFmode) && TARGET_VECTOR_ELEN_FP_64")
236 (V8DF "riscv_vector::vls_mode_valid_p (V8DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
237 (V16DF "riscv_vector::vls_mode_valid_p (V16DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
238 (V32DF "riscv_vector::vls_mode_valid_p (V32DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
239 (V64DF "riscv_vector::vls_mode_valid_p (V64DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
240 (V128DF "riscv_vector::vls_mode_valid_p (V128DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
241 (V256DF "riscv_vector::vls_mode_valid_p (V256DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
242 (V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
245 (define_mode_iterator VLSF_ZVFHMIN [
246 (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_VECTOR_ELEN_FP_16")
247 (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_VECTOR_ELEN_FP_16")
248 (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_VECTOR_ELEN_FP_16")
249 (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_VECTOR_ELEN_FP_16")
250 (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_VECTOR_ELEN_FP_16")
251 (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64")
252 (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
253 (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 256")
254 (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 512")
255 (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 1024")
256 (V1024HF "riscv_vector::vls_mode_valid_p (V1024HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 2048")
257 (V2048HF "riscv_vector::vls_mode_valid_p (V2048HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 4096")
258 (V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_FP_32")
259 (V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_FP_32")
260 (V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_FP_32")
261 (V8SF "riscv_vector::vls_mode_valid_p (V8SFmode) && TARGET_VECTOR_ELEN_FP_32")
262 (V16SF "riscv_vector::vls_mode_valid_p (V16SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
263 (V32SF "riscv_vector::vls_mode_valid_p (V32SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
264 (V64SF "riscv_vector::vls_mode_valid_p (V64SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
265 (V128SF "riscv_vector::vls_mode_valid_p (V128SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
266 (V256SF "riscv_vector::vls_mode_valid_p (V256SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
267 (V512SF "riscv_vector::vls_mode_valid_p (V512SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
268 (V1024SF "riscv_vector::vls_mode_valid_p (V1024SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
269 (V1DF "riscv_vector::vls_mode_valid_p (V1DFmode) && TARGET_VECTOR_ELEN_FP_64")
270 (V2DF "riscv_vector::vls_mode_valid_p (V2DFmode) && TARGET_VECTOR_ELEN_FP_64")
271 (V4DF "riscv_vector::vls_mode_valid_p (V4DFmode) && TARGET_VECTOR_ELEN_FP_64")
272 (V8DF "riscv_vector::vls_mode_valid_p (V8DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
273 (V16DF "riscv_vector::vls_mode_valid_p (V16DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
274 (V32DF "riscv_vector::vls_mode_valid_p (V32DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
275 (V64DF "riscv_vector::vls_mode_valid_p (V64DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
276 (V128DF "riscv_vector::vls_mode_valid_p (V128DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
277 (V256DF "riscv_vector::vls_mode_valid_p (V256DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
278 (V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
281 (define_mode_iterator VEEWEXT2 [
282 RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
284 (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16")
285 (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16")
286 (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
288 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
290 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
291 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
293 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
294 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
296 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
297 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
300 (define_mode_iterator VEEWEXT4 [
301 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
303 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
304 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
306 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
307 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
309 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
310 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
313 (define_mode_iterator VEEWEXT8 [
314 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
315 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
317 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
318 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
321 (define_mode_iterator VEEWTRUNC2 [
322 RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
324 RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
326 (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16")
327 (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16")
328 (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
330 (RVVM4SI "TARGET_64BIT")
331 (RVVM2SI "TARGET_64BIT")
332 (RVVM1SI "TARGET_64BIT")
333 (RVVMF2SI "TARGET_MIN_VLEN > 32 && TARGET_64BIT")
335 (RVVM4SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_64BIT")
336 (RVVM2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_64BIT")
337 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_64BIT")
338 (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32 && TARGET_64BIT")
341 (define_mode_iterator VEEWTRUNC4 [
342 RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
344 (RVVM2HI "TARGET_64BIT")
345 (RVVM1HI "TARGET_64BIT")
346 (RVVMF2HI "TARGET_64BIT")
347 (RVVMF4HI "TARGET_MIN_VLEN > 32 && TARGET_64BIT")
349 (RVVM2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_64BIT")
350 (RVVM1HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_64BIT")
351 (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_64BIT")
352 (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32 && TARGET_64BIT")
355 (define_mode_iterator VEEWTRUNC8 [
356 (RVVM1QI "TARGET_64BIT")
357 (RVVMF2QI "TARGET_64BIT")
358 (RVVMF4QI "TARGET_64BIT")
359 (RVVMF8QI "TARGET_MIN_VLEN > 32 && TARGET_64BIT")
362 (define_mode_iterator VEI16 [
363 RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
365 RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
367 (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16") (RVVM2HF "TARGET_VECTOR_ELEN_FP_16")
368 (RVVM1HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16")
369 (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
371 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
373 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
374 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
376 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
377 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
379 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
380 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
382 (V1QI "riscv_vector::vls_mode_valid_p (V1QImode)")
383 (V2QI "riscv_vector::vls_mode_valid_p (V2QImode)")
384 (V4QI "riscv_vector::vls_mode_valid_p (V4QImode)")
385 (V8QI "riscv_vector::vls_mode_valid_p (V8QImode)")
386 (V16QI "riscv_vector::vls_mode_valid_p (V16QImode)")
387 (V32QI "riscv_vector::vls_mode_valid_p (V32QImode) && TARGET_MIN_VLEN >= 64")
388 (V64QI "riscv_vector::vls_mode_valid_p (V64QImode) && TARGET_MIN_VLEN >= 128")
389 (V128QI "riscv_vector::vls_mode_valid_p (V128QImode) && TARGET_MIN_VLEN >= 256")
390 (V256QI "riscv_vector::vls_mode_valid_p (V256QImode) && TARGET_MIN_VLEN >= 512")
391 (V512QI "riscv_vector::vls_mode_valid_p (V512QImode) && TARGET_MIN_VLEN >= 1024")
392 (V1024QI "riscv_vector::vls_mode_valid_p (V1024QImode) && TARGET_MIN_VLEN >= 2048")
393 (V2048QI "riscv_vector::vls_mode_valid_p (V2048QImode) && TARGET_MIN_VLEN >= 4096")
394 (V1HI "riscv_vector::vls_mode_valid_p (V1HImode)")
395 (V2HI "riscv_vector::vls_mode_valid_p (V2HImode)")
396 (V4HI "riscv_vector::vls_mode_valid_p (V4HImode)")
397 (V8HI "riscv_vector::vls_mode_valid_p (V8HImode)")
398 (V16HI "riscv_vector::vls_mode_valid_p (V16HImode)")
399 (V32HI "riscv_vector::vls_mode_valid_p (V32HImode) && TARGET_MIN_VLEN >= 64")
400 (V64HI "riscv_vector::vls_mode_valid_p (V64HImode) && TARGET_MIN_VLEN >= 128")
401 (V128HI "riscv_vector::vls_mode_valid_p (V128HImode) && TARGET_MIN_VLEN >= 256")
402 (V256HI "riscv_vector::vls_mode_valid_p (V256HImode) && TARGET_MIN_VLEN >= 512")
403 (V512HI "riscv_vector::vls_mode_valid_p (V512HImode) && TARGET_MIN_VLEN >= 1024")
404 (V1024HI "riscv_vector::vls_mode_valid_p (V1024HImode) && TARGET_MIN_VLEN >= 2048")
405 (V2048HI "riscv_vector::vls_mode_valid_p (V2048HImode) && TARGET_MIN_VLEN >= 4096")
406 (V1SI "riscv_vector::vls_mode_valid_p (V1SImode)")
407 (V2SI "riscv_vector::vls_mode_valid_p (V2SImode)")
408 (V4SI "riscv_vector::vls_mode_valid_p (V4SImode)")
409 (V8SI "riscv_vector::vls_mode_valid_p (V8SImode)")
410 (V16SI "riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= 64")
411 (V32SI "riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= 128")
412 (V64SI "riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= 256")
413 (V128SI "riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= 512")
414 (V256SI "riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_MIN_VLEN >= 1024")
415 (V512SI "riscv_vector::vls_mode_valid_p (V512SImode) && TARGET_MIN_VLEN >= 2048")
416 (V1024SI "riscv_vector::vls_mode_valid_p (V1024SImode) && TARGET_MIN_VLEN >= 4096")
417 (V1DI "riscv_vector::vls_mode_valid_p (V1DImode) && TARGET_VECTOR_ELEN_64")
418 (V2DI "riscv_vector::vls_mode_valid_p (V2DImode) && TARGET_VECTOR_ELEN_64")
419 (V4DI "riscv_vector::vls_mode_valid_p (V4DImode) && TARGET_VECTOR_ELEN_64")
420 (V8DI "riscv_vector::vls_mode_valid_p (V8DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64")
421 (V16DI "riscv_vector::vls_mode_valid_p (V16DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
422 (V32DI "riscv_vector::vls_mode_valid_p (V32DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256")
423 (V64DI "riscv_vector::vls_mode_valid_p (V64DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512")
424 (V128DI "riscv_vector::vls_mode_valid_p (V128DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024")
425 (V256DI "riscv_vector::vls_mode_valid_p (V256DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048")
426 (V512DI "riscv_vector::vls_mode_valid_p (V512DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")
427 (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_VECTOR_ELEN_FP_16")
428 (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_VECTOR_ELEN_FP_16")
429 (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_VECTOR_ELEN_FP_16")
430 (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_VECTOR_ELEN_FP_16")
431 (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_VECTOR_ELEN_FP_16")
432 (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64")
433 (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
434 (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 256")
435 (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 512")
436 (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 1024")
437 (V1024HF "riscv_vector::vls_mode_valid_p (V1024HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 2048")
438 (V2048HF "riscv_vector::vls_mode_valid_p (V2048HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 4096")
439 (V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_FP_32")
440 (V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_FP_32")
441 (V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_FP_32")
442 (V8SF "riscv_vector::vls_mode_valid_p (V8SFmode) && TARGET_VECTOR_ELEN_FP_32")
443 (V16SF "riscv_vector::vls_mode_valid_p (V16SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
444 (V32SF "riscv_vector::vls_mode_valid_p (V32SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
445 (V64SF "riscv_vector::vls_mode_valid_p (V64SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
446 (V128SF "riscv_vector::vls_mode_valid_p (V128SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
447 (V256SF "riscv_vector::vls_mode_valid_p (V256SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
448 (V512SF "riscv_vector::vls_mode_valid_p (V512SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
449 (V1024SF "riscv_vector::vls_mode_valid_p (V1024SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
450 (V1DF "riscv_vector::vls_mode_valid_p (V1DFmode) && TARGET_VECTOR_ELEN_FP_64")
451 (V2DF "riscv_vector::vls_mode_valid_p (V2DFmode) && TARGET_VECTOR_ELEN_FP_64")
452 (V4DF "riscv_vector::vls_mode_valid_p (V4DFmode) && TARGET_VECTOR_ELEN_FP_64")
453 (V8DF "riscv_vector::vls_mode_valid_p (V8DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
454 (V16DF "riscv_vector::vls_mode_valid_p (V16DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
455 (V32DF "riscv_vector::vls_mode_valid_p (V32DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
456 (V64DF "riscv_vector::vls_mode_valid_p (V64DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
457 (V128DF "riscv_vector::vls_mode_valid_p (V128DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
458 (V256DF "riscv_vector::vls_mode_valid_p (V256DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
459 (V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
462 (define_mode_iterator VFULLI [
463 RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
465 RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
467 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
469 (RVVM8DI "TARGET_FULL_V") (RVVM4DI "TARGET_FULL_V") (RVVM2DI "TARGET_FULL_V") (RVVM1DI "TARGET_FULL_V")
471 (V1QI "riscv_vector::vls_mode_valid_p (V1QImode)")
472 (V2QI "riscv_vector::vls_mode_valid_p (V2QImode)")
473 (V4QI "riscv_vector::vls_mode_valid_p (V4QImode)")
474 (V8QI "riscv_vector::vls_mode_valid_p (V8QImode)")
475 (V16QI "riscv_vector::vls_mode_valid_p (V16QImode)")
476 (V32QI "riscv_vector::vls_mode_valid_p (V32QImode)")
477 (V64QI "riscv_vector::vls_mode_valid_p (V64QImode) && TARGET_MIN_VLEN >= 64")
478 (V128QI "riscv_vector::vls_mode_valid_p (V128QImode) && TARGET_MIN_VLEN >= 128")
479 (V256QI "riscv_vector::vls_mode_valid_p (V256QImode) && TARGET_MIN_VLEN >= 256")
480 (V512QI "riscv_vector::vls_mode_valid_p (V512QImode) && TARGET_MIN_VLEN >= 512")
481 (V1024QI "riscv_vector::vls_mode_valid_p (V1024QImode) && TARGET_MIN_VLEN >= 1024")
482 (V2048QI "riscv_vector::vls_mode_valid_p (V2048QImode) && TARGET_MIN_VLEN >= 2048")
483 (V4096QI "riscv_vector::vls_mode_valid_p (V4096QImode) && TARGET_MIN_VLEN >= 4096")
484 (V1HI "riscv_vector::vls_mode_valid_p (V1HImode)")
485 (V2HI "riscv_vector::vls_mode_valid_p (V2HImode)")
486 (V4HI "riscv_vector::vls_mode_valid_p (V4HImode)")
487 (V8HI "riscv_vector::vls_mode_valid_p (V8HImode)")
488 (V16HI "riscv_vector::vls_mode_valid_p (V16HImode)")
489 (V32HI "riscv_vector::vls_mode_valid_p (V32HImode) && TARGET_MIN_VLEN >= 64")
490 (V64HI "riscv_vector::vls_mode_valid_p (V64HImode) && TARGET_MIN_VLEN >= 128")
491 (V128HI "riscv_vector::vls_mode_valid_p (V128HImode) && TARGET_MIN_VLEN >= 256")
492 (V256HI "riscv_vector::vls_mode_valid_p (V256HImode) && TARGET_MIN_VLEN >= 512")
493 (V512HI "riscv_vector::vls_mode_valid_p (V512HImode) && TARGET_MIN_VLEN >= 1024")
494 (V1024HI "riscv_vector::vls_mode_valid_p (V1024HImode) && TARGET_MIN_VLEN >= 2048")
495 (V2048HI "riscv_vector::vls_mode_valid_p (V2048HImode) && TARGET_MIN_VLEN >= 4096")
496 (V1SI "riscv_vector::vls_mode_valid_p (V1SImode)")
497 (V2SI "riscv_vector::vls_mode_valid_p (V2SImode)")
498 (V4SI "riscv_vector::vls_mode_valid_p (V4SImode)")
499 (V8SI "riscv_vector::vls_mode_valid_p (V8SImode)")
500 (V16SI "riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= 64")
501 (V32SI "riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= 128")
502 (V64SI "riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= 256")
503 (V128SI "riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= 512")
504 (V256SI "riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_MIN_VLEN >= 1024")
505 (V512SI "riscv_vector::vls_mode_valid_p (V512SImode) && TARGET_MIN_VLEN >= 2048")
506 (V1024SI "riscv_vector::vls_mode_valid_p (V1024SImode) && TARGET_MIN_VLEN >= 4096")
507 (V1DI "riscv_vector::vls_mode_valid_p (V1DImode) && TARGET_FULL_V")
508 (V2DI "riscv_vector::vls_mode_valid_p (V2DImode) && TARGET_FULL_V")
509 (V4DI "riscv_vector::vls_mode_valid_p (V4DImode) && TARGET_FULL_V")
510 (V8DI "riscv_vector::vls_mode_valid_p (V8DImode) && TARGET_FULL_V && TARGET_MIN_VLEN >= 64")
511 (V16DI "riscv_vector::vls_mode_valid_p (V16DImode) && TARGET_FULL_V && TARGET_MIN_VLEN >= 128")
512 (V32DI "riscv_vector::vls_mode_valid_p (V32DImode) && TARGET_FULL_V && TARGET_MIN_VLEN >= 256")
513 (V64DI "riscv_vector::vls_mode_valid_p (V64DImode) && TARGET_FULL_V && TARGET_MIN_VLEN >= 512")
514 (V128DI "riscv_vector::vls_mode_valid_p (V128DImode) && TARGET_FULL_V && TARGET_MIN_VLEN >= 1024")
515 (V256DI "riscv_vector::vls_mode_valid_p (V256DImode) && TARGET_FULL_V && TARGET_MIN_VLEN >= 2048")
516 (V512DI "riscv_vector::vls_mode_valid_p (V512DImode) && TARGET_FULL_V && TARGET_MIN_VLEN >= 4096")
519 (define_mode_iterator VI_QH [
520 RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
522 RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
525 (define_mode_iterator VI_QHS [
526 RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
528 RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
530 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
532 (V1QI "riscv_vector::vls_mode_valid_p (V1QImode)")
533 (V2QI "riscv_vector::vls_mode_valid_p (V2QImode)")
534 (V4QI "riscv_vector::vls_mode_valid_p (V4QImode)")
535 (V8QI "riscv_vector::vls_mode_valid_p (V8QImode)")
536 (V16QI "riscv_vector::vls_mode_valid_p (V16QImode)")
537 (V32QI "riscv_vector::vls_mode_valid_p (V32QImode)")
538 (V64QI "riscv_vector::vls_mode_valid_p (V64QImode) && TARGET_MIN_VLEN >= 64")
539 (V128QI "riscv_vector::vls_mode_valid_p (V128QImode) && TARGET_MIN_VLEN >= 128")
540 (V256QI "riscv_vector::vls_mode_valid_p (V256QImode) && TARGET_MIN_VLEN >= 256")
541 (V512QI "riscv_vector::vls_mode_valid_p (V512QImode) && TARGET_MIN_VLEN >= 512")
542 (V1024QI "riscv_vector::vls_mode_valid_p (V1024QImode) && TARGET_MIN_VLEN >= 1024")
543 (V2048QI "riscv_vector::vls_mode_valid_p (V2048QImode) && TARGET_MIN_VLEN >= 2048")
544 (V4096QI "riscv_vector::vls_mode_valid_p (V4096QImode) && TARGET_MIN_VLEN >= 4096")
545 (V1HI "riscv_vector::vls_mode_valid_p (V1HImode)")
546 (V2HI "riscv_vector::vls_mode_valid_p (V2HImode)")
547 (V4HI "riscv_vector::vls_mode_valid_p (V4HImode)")
548 (V8HI "riscv_vector::vls_mode_valid_p (V8HImode)")
549 (V16HI "riscv_vector::vls_mode_valid_p (V16HImode)")
550 (V32HI "riscv_vector::vls_mode_valid_p (V32HImode) && TARGET_MIN_VLEN >= 64")
551 (V64HI "riscv_vector::vls_mode_valid_p (V64HImode) && TARGET_MIN_VLEN >= 128")
552 (V128HI "riscv_vector::vls_mode_valid_p (V128HImode) && TARGET_MIN_VLEN >= 256")
553 (V256HI "riscv_vector::vls_mode_valid_p (V256HImode) && TARGET_MIN_VLEN >= 512")
554 (V512HI "riscv_vector::vls_mode_valid_p (V512HImode) && TARGET_MIN_VLEN >= 1024")
555 (V1024HI "riscv_vector::vls_mode_valid_p (V1024HImode) && TARGET_MIN_VLEN >= 2048")
556 (V2048HI "riscv_vector::vls_mode_valid_p (V2048HImode) && TARGET_MIN_VLEN >= 4096")
557 (V1SI "riscv_vector::vls_mode_valid_p (V1SImode)")
558 (V2SI "riscv_vector::vls_mode_valid_p (V2SImode)")
559 (V4SI "riscv_vector::vls_mode_valid_p (V4SImode)")
560 (V8SI "riscv_vector::vls_mode_valid_p (V8SImode)")
561 (V16SI "riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= 64")
562 (V32SI "riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= 128")
563 (V64SI "riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= 256")
564 (V128SI "riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= 512")
565 (V256SI "riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_MIN_VLEN >= 1024")
566 (V512SI "riscv_vector::vls_mode_valid_p (V512SImode) && TARGET_MIN_VLEN >= 2048")
567 (V1024SI "riscv_vector::vls_mode_valid_p (V1024SImode) && TARGET_MIN_VLEN >= 4096")
570 (define_mode_iterator VI_QHS_NO_M8 [
571 RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
573 RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
575 RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
577 (V1QI "riscv_vector::vls_mode_valid_p (V1QImode)")
578 (V2QI "riscv_vector::vls_mode_valid_p (V2QImode)")
579 (V4QI "riscv_vector::vls_mode_valid_p (V4QImode)")
580 (V8QI "riscv_vector::vls_mode_valid_p (V8QImode)")
581 (V16QI "riscv_vector::vls_mode_valid_p (V16QImode)")
582 (V32QI "riscv_vector::vls_mode_valid_p (V32QImode)")
583 (V64QI "riscv_vector::vls_mode_valid_p (V64QImode) && TARGET_MIN_VLEN >= 64")
584 (V128QI "riscv_vector::vls_mode_valid_p (V128QImode) && TARGET_MIN_VLEN >= 128")
585 (V256QI "riscv_vector::vls_mode_valid_p (V256QImode) && TARGET_MIN_VLEN >= 256")
586 (V512QI "riscv_vector::vls_mode_valid_p (V512QImode) && TARGET_MIN_VLEN >= 512")
587 (V1024QI "riscv_vector::vls_mode_valid_p (V1024QImode) && TARGET_MIN_VLEN >= 1024")
588 (V2048QI "riscv_vector::vls_mode_valid_p (V2048QImode) && TARGET_MIN_VLEN >= 2048")
589 (V1HI "riscv_vector::vls_mode_valid_p (V1HImode)")
590 (V2HI "riscv_vector::vls_mode_valid_p (V2HImode)")
591 (V4HI "riscv_vector::vls_mode_valid_p (V4HImode)")
592 (V8HI "riscv_vector::vls_mode_valid_p (V8HImode)")
593 (V16HI "riscv_vector::vls_mode_valid_p (V16HImode)")
594 (V32HI "riscv_vector::vls_mode_valid_p (V32HImode) && TARGET_MIN_VLEN >= 64")
595 (V64HI "riscv_vector::vls_mode_valid_p (V64HImode) && TARGET_MIN_VLEN >= 128")
596 (V128HI "riscv_vector::vls_mode_valid_p (V128HImode) && TARGET_MIN_VLEN >= 256")
597 (V256HI "riscv_vector::vls_mode_valid_p (V256HImode) && TARGET_MIN_VLEN >= 512")
598 (V512HI "riscv_vector::vls_mode_valid_p (V512HImode) && TARGET_MIN_VLEN >= 1024")
599 (V1024HI "riscv_vector::vls_mode_valid_p (V1024HImode) && TARGET_MIN_VLEN >= 2048")
600 (V1SI "riscv_vector::vls_mode_valid_p (V1SImode)")
601 (V2SI "riscv_vector::vls_mode_valid_p (V2SImode)")
602 (V4SI "riscv_vector::vls_mode_valid_p (V4SImode)")
603 (V8SI "riscv_vector::vls_mode_valid_p (V8SImode)")
604 (V16SI "riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= 64")
605 (V32SI "riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= 128")
606 (V64SI "riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= 256")
607 (V128SI "riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= 512")
608 (V256SI "riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_MIN_VLEN >= 1024")
609 (V512SI "riscv_vector::vls_mode_valid_p (V512SImode) && TARGET_MIN_VLEN >= 2048")
612 (define_mode_iterator VF_HS [
613 (RVVM8HF "TARGET_ZVFH") (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH")
614 (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH")
615 (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
617 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
618 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32") (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
620 (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_ZVFH")
621 (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_ZVFH")
622 (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_ZVFH")
623 (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_ZVFH")
624 (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_ZVFH")
625 (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 64")
626 (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
627 (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 256")
628 (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 512")
629 (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024")
630 (V1024HF "riscv_vector::vls_mode_valid_p (V1024HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 2048")
631 (V2048HF "riscv_vector::vls_mode_valid_p (V2048HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 4096")
632 (V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_FP_32")
633 (V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_FP_32")
634 (V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_FP_32")
635 (V8SF "riscv_vector::vls_mode_valid_p (V8SFmode) && TARGET_VECTOR_ELEN_FP_32")
636 (V16SF "riscv_vector::vls_mode_valid_p (V16SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
637 (V32SF "riscv_vector::vls_mode_valid_p (V32SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
638 (V64SF "riscv_vector::vls_mode_valid_p (V64SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
639 (V128SF "riscv_vector::vls_mode_valid_p (V128SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
640 (V256SF "riscv_vector::vls_mode_valid_p (V256SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
641 (V512SF "riscv_vector::vls_mode_valid_p (V512SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
642 (V1024SF "riscv_vector::vls_mode_valid_p (V1024SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
645 (define_mode_iterator VF_HS_NO_M8 [
646 (RVVM4HF "TARGET_ZVFH")
647 (RVVM2HF "TARGET_ZVFH")
648 (RVVM1HF "TARGET_ZVFH")
649 (RVVMF2HF "TARGET_ZVFH")
650 (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
651 (RVVM4SF "TARGET_VECTOR_ELEN_FP_32")
652 (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
653 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32")
654 (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
656 (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_ZVFH")
657 (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_ZVFH")
658 (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_ZVFH")
659 (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_ZVFH")
660 (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_ZVFH")
661 (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 64")
662 (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
663 (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 256")
664 (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 512")
665 (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024")
666 (V1024HF "riscv_vector::vls_mode_valid_p (V1024HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 2048")
667 (V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_FP_32")
668 (V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_FP_32")
669 (V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_FP_32")
670 (V8SF "riscv_vector::vls_mode_valid_p (V8SFmode) && TARGET_VECTOR_ELEN_FP_32")
671 (V16SF "riscv_vector::vls_mode_valid_p (V16SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
672 (V32SF "riscv_vector::vls_mode_valid_p (V32SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
673 (V64SF "riscv_vector::vls_mode_valid_p (V64SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
674 (V128SF "riscv_vector::vls_mode_valid_p (V128SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
675 (V256SF "riscv_vector::vls_mode_valid_p (V256SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
676 (V512SF "riscv_vector::vls_mode_valid_p (V512SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
679 (define_mode_iterator VF_HS_M8 [
680 (RVVM8HF "TARGET_ZVFH")
681 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32")
684 (define_mode_iterator V_VLSI_QHS [
685 RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
687 RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
689 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
691 (V1QI "riscv_vector::vls_mode_valid_p (V1QImode)")
692 (V2QI "riscv_vector::vls_mode_valid_p (V2QImode)")
693 (V4QI "riscv_vector::vls_mode_valid_p (V4QImode)")
694 (V8QI "riscv_vector::vls_mode_valid_p (V8QImode)")
695 (V16QI "riscv_vector::vls_mode_valid_p (V16QImode)")
696 (V32QI "riscv_vector::vls_mode_valid_p (V32QImode)")
697 (V64QI "riscv_vector::vls_mode_valid_p (V64QImode) && TARGET_MIN_VLEN >= 64")
698 (V128QI "riscv_vector::vls_mode_valid_p (V128QImode) && TARGET_MIN_VLEN >= 128")
699 (V256QI "riscv_vector::vls_mode_valid_p (V256QImode) && TARGET_MIN_VLEN >= 256")
700 (V512QI "riscv_vector::vls_mode_valid_p (V512QImode) && TARGET_MIN_VLEN >= 512")
701 (V1024QI "riscv_vector::vls_mode_valid_p (V1024QImode) && TARGET_MIN_VLEN >= 1024")
702 (V2048QI "riscv_vector::vls_mode_valid_p (V2048QImode) && TARGET_MIN_VLEN >= 2048")
703 (V4096QI "riscv_vector::vls_mode_valid_p (V4096QImode) && TARGET_MIN_VLEN >= 4096")
704 (V1HI "riscv_vector::vls_mode_valid_p (V1HImode)")
705 (V2HI "riscv_vector::vls_mode_valid_p (V2HImode)")
706 (V4HI "riscv_vector::vls_mode_valid_p (V4HImode)")
707 (V8HI "riscv_vector::vls_mode_valid_p (V8HImode)")
708 (V16HI "riscv_vector::vls_mode_valid_p (V16HImode)")
709 (V32HI "riscv_vector::vls_mode_valid_p (V32HImode) && TARGET_MIN_VLEN >= 64")
710 (V64HI "riscv_vector::vls_mode_valid_p (V64HImode) && TARGET_MIN_VLEN >= 128")
711 (V128HI "riscv_vector::vls_mode_valid_p (V128HImode) && TARGET_MIN_VLEN >= 256")
712 (V256HI "riscv_vector::vls_mode_valid_p (V256HImode) && TARGET_MIN_VLEN >= 512")
713 (V512HI "riscv_vector::vls_mode_valid_p (V512HImode) && TARGET_MIN_VLEN >= 1024")
714 (V1024HI "riscv_vector::vls_mode_valid_p (V1024HImode) && TARGET_MIN_VLEN >= 2048")
715 (V2048HI "riscv_vector::vls_mode_valid_p (V2048HImode) && TARGET_MIN_VLEN >= 4096")
716 (V1SI "riscv_vector::vls_mode_valid_p (V1SImode)")
717 (V2SI "riscv_vector::vls_mode_valid_p (V2SImode)")
718 (V4SI "riscv_vector::vls_mode_valid_p (V4SImode)")
719 (V8SI "riscv_vector::vls_mode_valid_p (V8SImode)")
720 (V16SI "riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= 64")
721 (V32SI "riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= 128")
722 (V64SI "riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= 256")
723 (V128SI "riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= 512")
724 (V256SI "riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_MIN_VLEN >= 1024")
725 (V512SI "riscv_vector::vls_mode_valid_p (V512SImode) && TARGET_MIN_VLEN >= 2048")
726 (V1024SI "riscv_vector::vls_mode_valid_p (V1024SImode) && TARGET_MIN_VLEN >= 4096")
729 (define_mode_iterator VI_D [
730 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
731 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
734 (define_mode_iterator V_VLSI_D [
735 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
736 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
738 (V1DI "riscv_vector::vls_mode_valid_p (V1DImode) && TARGET_VECTOR_ELEN_64")
739 (V2DI "riscv_vector::vls_mode_valid_p (V2DImode) && TARGET_VECTOR_ELEN_64")
740 (V4DI "riscv_vector::vls_mode_valid_p (V4DImode) && TARGET_VECTOR_ELEN_64")
741 (V8DI "riscv_vector::vls_mode_valid_p (V8DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64")
742 (V16DI "riscv_vector::vls_mode_valid_p (V16DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
743 (V32DI "riscv_vector::vls_mode_valid_p (V32DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256")
744 (V64DI "riscv_vector::vls_mode_valid_p (V64DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512")
745 (V128DI "riscv_vector::vls_mode_valid_p (V128DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024")
746 (V256DI "riscv_vector::vls_mode_valid_p (V256DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048")
747 (V512DI "riscv_vector::vls_mode_valid_p (V512DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")
750 (define_mode_iterator VFULLI_D [
751 (RVVM8DI "TARGET_FULL_V") (RVVM4DI "TARGET_FULL_V")
752 (RVVM2DI "TARGET_FULL_V") (RVVM1DI "TARGET_FULL_V")
755 ;; All RATIO mode iterators are used on gather/scatter vectorization.
756 ;; RISC-V V Spec 18.3:
757 ;; The V extension supports all vector load and store instructions (Section
758 ;; Vector Loads and Stores), except the V extension does not support EEW=64
759 ;; for index values when XLEN=32.
760 ;; According to RVV ISA description above, all RATIO index DI mode need TARGET_64BIT.
762 ;; In gather/scatter expand, we need to sign/zero extend the index mode into vector
763 ;; Pmode, so we need to check whether vector Pmode is available.
764 ;; E.g. when index mode = RVVM8QImde and Pmode = SImode, if it is not zero_extend or
765 ;; scalar != 1, such gather/scatter is not allowed since we don't have RVVM32SImode.
766 (define_mode_iterator RATIO64 [
767 (RVVMF8QI "TARGET_MIN_VLEN > 32")
768 (RVVMF4HI "TARGET_MIN_VLEN > 32")
769 (RVVMF2SI "TARGET_MIN_VLEN > 32")
770 (RVVM1DI "TARGET_VECTOR_ELEN_64")
771 (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
772 (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
773 (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
776 (define_mode_iterator RATIO32 [
780 (RVVM2DI "TARGET_VECTOR_ELEN_64")
781 (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16")
782 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32")
783 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64")
786 (define_mode_iterator RATIO16 [
790 (RVVM4DI "TARGET_VECTOR_ELEN_64")
791 (RVVM1HF "TARGET_VECTOR_ELEN_FP_16")
792 (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
793 (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
796 (define_mode_iterator RATIO8 [
800 (RVVM8DI "TARGET_VECTOR_ELEN_64")
801 (RVVM2HF "TARGET_VECTOR_ELEN_FP_16")
802 (RVVM4SF "TARGET_VECTOR_ELEN_FP_32")
803 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64")
806 (define_mode_iterator RATIO4 [
810 (RVVM4HF "TARGET_VECTOR_ELEN_FP_16")
811 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32")
814 (define_mode_iterator RATIO2 [
817 (RVVM8HF "TARGET_VECTOR_ELEN_FP_16")
820 (define_mode_iterator RATIO1 [
824 (define_mode_iterator RATIO64I [
825 (RVVMF8QI "TARGET_MIN_VLEN > 32")
826 (RVVMF4HI "TARGET_MIN_VLEN > 32")
827 (RVVMF2SI "TARGET_MIN_VLEN > 32")
828 (RVVM1DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT")
831 (define_mode_iterator RATIO32I [
835 (RVVM2DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT")
838 (define_mode_iterator RATIO16I [
842 (RVVM4DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT")
845 (define_mode_iterator RATIO8I [
849 (RVVM8DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT")
852 (define_mode_iterator RATIO4I [
858 (define_mode_iterator RATIO2I [
863 (define_mode_iterator V_WHOLE [
864 RVVM8QI RVVM4QI RVVM2QI RVVM1QI
866 RVVM8HI RVVM4HI RVVM2HI RVVM1HI
868 (RVVM8HF "TARGET_VECTOR_ELEN_FP_16") (RVVM4HF "TARGET_VECTOR_ELEN_FP_16")
869 (RVVM2HF "TARGET_VECTOR_ELEN_FP_16") (RVVM1HF "TARGET_VECTOR_ELEN_FP_16")
871 RVVM8SI RVVM4SI RVVM2SI RVVM1SI
873 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32")
874 (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") (RVVM1SF "TARGET_VECTOR_ELEN_FP_32")
876 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
877 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
879 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
880 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
883 (define_mode_iterator V_FRACT [
884 RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
886 RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
888 (RVVMF2HF "TARGET_VECTOR_ELEN_FP_16") (RVVMF4HF "TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN > 32")
890 (RVVMF2SI "TARGET_MIN_VLEN > 32")
892 (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
895 (define_mode_iterator VWEXTI [
896 RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
898 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
900 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
901 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
903 (V1HI "riscv_vector::vls_mode_valid_p (V1HImode)")
904 (V2HI "riscv_vector::vls_mode_valid_p (V2HImode)")
905 (V4HI "riscv_vector::vls_mode_valid_p (V4HImode)")
906 (V8HI "riscv_vector::vls_mode_valid_p (V8HImode)")
907 (V16HI "riscv_vector::vls_mode_valid_p (V16HImode)")
908 (V32HI "riscv_vector::vls_mode_valid_p (V32HImode) && TARGET_MIN_VLEN >= 64")
909 (V64HI "riscv_vector::vls_mode_valid_p (V64HImode) && TARGET_MIN_VLEN >= 128")
910 (V128HI "riscv_vector::vls_mode_valid_p (V128HImode) && TARGET_MIN_VLEN >= 256")
911 (V256HI "riscv_vector::vls_mode_valid_p (V256HImode) && TARGET_MIN_VLEN >= 512")
912 (V512HI "riscv_vector::vls_mode_valid_p (V512HImode) && TARGET_MIN_VLEN >= 1024")
913 (V1024HI "riscv_vector::vls_mode_valid_p (V1024HImode) && TARGET_MIN_VLEN >= 2048")
914 (V2048HI "riscv_vector::vls_mode_valid_p (V2048HImode) && TARGET_MIN_VLEN >= 4096")
915 (V1SI "riscv_vector::vls_mode_valid_p (V1SImode)")
916 (V2SI "riscv_vector::vls_mode_valid_p (V2SImode)")
917 (V4SI "riscv_vector::vls_mode_valid_p (V4SImode)")
918 (V8SI "riscv_vector::vls_mode_valid_p (V8SImode)")
919 (V16SI "riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= 64")
920 (V32SI "riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= 128")
921 (V64SI "riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= 256")
922 (V128SI "riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= 512")
923 (V256SI "riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_MIN_VLEN >= 1024")
924 (V512SI "riscv_vector::vls_mode_valid_p (V512SImode) && TARGET_MIN_VLEN >= 2048")
925 (V1024SI "riscv_vector::vls_mode_valid_p (V1024SImode) && TARGET_MIN_VLEN >= 4096")
926 (V1DI "riscv_vector::vls_mode_valid_p (V1DImode) && TARGET_VECTOR_ELEN_64")
927 (V2DI "riscv_vector::vls_mode_valid_p (V2DImode) && TARGET_VECTOR_ELEN_64")
928 (V4DI "riscv_vector::vls_mode_valid_p (V4DImode) && TARGET_VECTOR_ELEN_64")
929 (V8DI "riscv_vector::vls_mode_valid_p (V8DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64")
930 (V16DI "riscv_vector::vls_mode_valid_p (V16DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
931 (V32DI "riscv_vector::vls_mode_valid_p (V32DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256")
932 (V64DI "riscv_vector::vls_mode_valid_p (V64DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512")
933 (V128DI "riscv_vector::vls_mode_valid_p (V128DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024")
934 (V256DI "riscv_vector::vls_mode_valid_p (V256DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048")
935 (V512DI "riscv_vector::vls_mode_valid_p (V512DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")
938 ;; Same iterator split reason as VF_ZVFHMIN and VF.
939 (define_mode_iterator VWEXTF_ZVFHMIN [
940 (RVVM8SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
941 (RVVM4SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
942 (RVVM2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
943 (RVVM1SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
944 (RVVMF2SF "TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
946 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
947 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
949 (V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
950 (V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
951 (V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
952 (V8SF "riscv_vector::vls_mode_valid_p (V8SFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
953 (V16SF "riscv_vector::vls_mode_valid_p (V16SFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
954 (V32SF "riscv_vector::vls_mode_valid_p (V32SFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
955 (V64SF "riscv_vector::vls_mode_valid_p (V64SFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
956 (V128SF "riscv_vector::vls_mode_valid_p (V128SFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
957 (V256SF "riscv_vector::vls_mode_valid_p (V256SFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
958 (V512SF "riscv_vector::vls_mode_valid_p (V512SFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
959 (V1024SF "riscv_vector::vls_mode_valid_p (V1024SFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
960 (V1DF "riscv_vector::vls_mode_valid_p (V1DFmode) && TARGET_VECTOR_ELEN_FP_64")
961 (V2DF "riscv_vector::vls_mode_valid_p (V2DFmode) && TARGET_VECTOR_ELEN_FP_64")
962 (V4DF "riscv_vector::vls_mode_valid_p (V4DFmode) && TARGET_VECTOR_ELEN_FP_64")
963 (V8DF "riscv_vector::vls_mode_valid_p (V8DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
964 (V16DF "riscv_vector::vls_mode_valid_p (V16DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
965 (V32DF "riscv_vector::vls_mode_valid_p (V32DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
966 (V64DF "riscv_vector::vls_mode_valid_p (V64DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
967 (V128DF "riscv_vector::vls_mode_valid_p (V128DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
968 (V256DF "riscv_vector::vls_mode_valid_p (V256DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
969 (V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
972 (define_mode_iterator VWEXTF [
973 (RVVM8SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
974 (RVVM4SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
975 (RVVM2SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
976 (RVVM1SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32")
977 (RVVMF2SF "TARGET_ZVFH && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
979 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
980 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
982 (V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
983 (V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
984 (V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
985 (V8SF "riscv_vector::vls_mode_valid_p (V8SFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32")
986 (V16SF "riscv_vector::vls_mode_valid_p (V16SFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
987 (V32SF "riscv_vector::vls_mode_valid_p (V32SFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
988 (V64SF "riscv_vector::vls_mode_valid_p (V64SFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
989 (V128SF "riscv_vector::vls_mode_valid_p (V128SFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
990 (V256SF "riscv_vector::vls_mode_valid_p (V256SFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
991 (V512SF "riscv_vector::vls_mode_valid_p (V512SFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
992 (V1024SF "riscv_vector::vls_mode_valid_p (V1024SFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
993 (V1DF "riscv_vector::vls_mode_valid_p (V1DFmode) && TARGET_VECTOR_ELEN_FP_64")
994 (V2DF "riscv_vector::vls_mode_valid_p (V2DFmode) && TARGET_VECTOR_ELEN_FP_64")
995 (V4DF "riscv_vector::vls_mode_valid_p (V4DFmode) && TARGET_VECTOR_ELEN_FP_64")
996 (V8DF "riscv_vector::vls_mode_valid_p (V8DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
997 (V16DF "riscv_vector::vls_mode_valid_p (V16DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
998 (V32DF "riscv_vector::vls_mode_valid_p (V32DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
999 (V64DF "riscv_vector::vls_mode_valid_p (V64DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
1000 (V128DF "riscv_vector::vls_mode_valid_p (V128DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
1001 (V256DF "riscv_vector::vls_mode_valid_p (V256DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
1002 (V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
1005 (define_mode_iterator VWCONVERTI [
1006 (RVVM8SI "TARGET_ZVFH") (RVVM4SI "TARGET_ZVFH") (RVVM2SI "TARGET_ZVFH") (RVVM1SI "TARGET_ZVFH")
1007 (RVVMF2SI "TARGET_ZVFH")
1009 (RVVM8DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
1010 (RVVM4DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
1011 (RVVM2DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
1012 (RVVM1DI "TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
1014 (V1SI "riscv_vector::vls_mode_valid_p (V1SImode) && TARGET_ZVFH")
1015 (V2SI "riscv_vector::vls_mode_valid_p (V2SImode) && TARGET_ZVFH")
1016 (V4SI "riscv_vector::vls_mode_valid_p (V4SImode) && TARGET_ZVFH")
1017 (V8SI "riscv_vector::vls_mode_valid_p (V8SImode) && TARGET_ZVFH")
1018 (V16SI "riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 64")
1019 (V32SI "riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
1020 (V64SI "riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 256")
1021 (V128SI "riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 512")
1022 (V256SI "riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024")
1023 (V512SI "riscv_vector::vls_mode_valid_p (V512SImode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 2048")
1024 (V1024SI "riscv_vector::vls_mode_valid_p (V1024SImode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 4096")
1025 (V1DI "riscv_vector::vls_mode_valid_p (V1DImode) && TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
1026 (V2DI "riscv_vector::vls_mode_valid_p (V2DImode) && TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
1027 (V4DI "riscv_vector::vls_mode_valid_p (V4DImode) && TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32")
1028 (V8DI "riscv_vector::vls_mode_valid_p (V8DImode) && TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
1029 (V16DI "riscv_vector::vls_mode_valid_p (V16DImode) && TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
1030 (V32DI "riscv_vector::vls_mode_valid_p (V32DImode) && TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
1031 (V64DI "riscv_vector::vls_mode_valid_p (V64DImode) && TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
1032 (V128DI "riscv_vector::vls_mode_valid_p (V128DImode) && TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
1033 (V256DI "riscv_vector::vls_mode_valid_p (V256DImode) && TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
1034 (V512DI "riscv_vector::vls_mode_valid_p (V512DImode) && TARGET_VECTOR_ELEN_64 && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
1037 (define_mode_iterator VWWCONVERTI [
1038 (RVVM8DI "TARGET_VECTOR_ELEN_64 && TARGET_ZVFH")
1039 (RVVM4DI "TARGET_VECTOR_ELEN_64 && TARGET_ZVFH")
1040 (RVVM2DI "TARGET_VECTOR_ELEN_64 && TARGET_ZVFH")
1041 (RVVM1DI "TARGET_VECTOR_ELEN_64 && TARGET_ZVFH")
1043 (V1DI "riscv_vector::vls_mode_valid_p (V1DImode) && TARGET_VECTOR_ELEN_64 && TARGET_ZVFH")
1044 (V2DI "riscv_vector::vls_mode_valid_p (V2DImode) && TARGET_VECTOR_ELEN_64 && TARGET_ZVFH")
1045 (V4DI "riscv_vector::vls_mode_valid_p (V4DImode) && TARGET_VECTOR_ELEN_64 && TARGET_ZVFH")
1046 (V8DI "riscv_vector::vls_mode_valid_p (V8DImode) && TARGET_VECTOR_ELEN_64 && TARGET_ZVFH && TARGET_MIN_VLEN >= 64")
1047 (V16DI "riscv_vector::vls_mode_valid_p (V16DImode) && TARGET_VECTOR_ELEN_64 && TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
1048 (V32DI "riscv_vector::vls_mode_valid_p (V32DImode) && TARGET_VECTOR_ELEN_64 && TARGET_ZVFH && TARGET_MIN_VLEN >= 256")
1049 (V64DI "riscv_vector::vls_mode_valid_p (V64DImode) && TARGET_VECTOR_ELEN_64 && TARGET_ZVFH && TARGET_MIN_VLEN >= 512")
1050 (V128DI "riscv_vector::vls_mode_valid_p (V128DImode) && TARGET_VECTOR_ELEN_64 && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024")
1051 (V256DI "riscv_vector::vls_mode_valid_p (V256DImode) && TARGET_VECTOR_ELEN_64 && TARGET_ZVFH && TARGET_MIN_VLEN >= 2048")
1052 (V512DI "riscv_vector::vls_mode_valid_p (V512DImode) && TARGET_VECTOR_ELEN_64 && TARGET_ZVFH && TARGET_MIN_VLEN >= 4096")
1055 (define_mode_iterator VQEXTI [
1056 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
1058 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
1059 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
1061 (V1SI "riscv_vector::vls_mode_valid_p (V1SImode)")
1062 (V2SI "riscv_vector::vls_mode_valid_p (V2SImode)")
1063 (V4SI "riscv_vector::vls_mode_valid_p (V4SImode)")
1064 (V8SI "riscv_vector::vls_mode_valid_p (V8SImode)")
1065 (V16SI "riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= 64")
1066 (V32SI "riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= 128")
1067 (V64SI "riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= 256")
1068 (V128SI "riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= 512")
1069 (V256SI "riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_MIN_VLEN >= 1024")
1070 (V512SI "riscv_vector::vls_mode_valid_p (V512SImode) && TARGET_MIN_VLEN >= 2048")
1071 (V1024SI "riscv_vector::vls_mode_valid_p (V1024SImode) && TARGET_MIN_VLEN >= 4096")
1072 (V1DI "riscv_vector::vls_mode_valid_p (V1DImode) && TARGET_VECTOR_ELEN_64")
1073 (V2DI "riscv_vector::vls_mode_valid_p (V2DImode) && TARGET_VECTOR_ELEN_64")
1074 (V4DI "riscv_vector::vls_mode_valid_p (V4DImode) && TARGET_VECTOR_ELEN_64")
1075 (V8DI "riscv_vector::vls_mode_valid_p (V8DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64")
1076 (V16DI "riscv_vector::vls_mode_valid_p (V16DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
1077 (V32DI "riscv_vector::vls_mode_valid_p (V32DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256")
1078 (V64DI "riscv_vector::vls_mode_valid_p (V64DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512")
1079 (V128DI "riscv_vector::vls_mode_valid_p (V128DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024")
1080 (V256DI "riscv_vector::vls_mode_valid_p (V256DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048")
1081 (V512DI "riscv_vector::vls_mode_valid_p (V512DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")
1084 (define_mode_iterator VQEXTF [
1085 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
1086 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
1088 (V1DF "riscv_vector::vls_mode_valid_p (V1DFmode) && TARGET_VECTOR_ELEN_FP_64")
1089 (V2DF "riscv_vector::vls_mode_valid_p (V2DFmode) && TARGET_VECTOR_ELEN_FP_64")
1090 (V4DF "riscv_vector::vls_mode_valid_p (V4DFmode) && TARGET_VECTOR_ELEN_FP_64")
1091 (V8DF "riscv_vector::vls_mode_valid_p (V8DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
1092 (V16DF "riscv_vector::vls_mode_valid_p (V16DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
1093 (V32DF "riscv_vector::vls_mode_valid_p (V32DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
1094 (V64DF "riscv_vector::vls_mode_valid_p (V64DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
1095 (V128DF "riscv_vector::vls_mode_valid_p (V128DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
1096 (V256DF "riscv_vector::vls_mode_valid_p (V256DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
1097 (V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
1100 (define_mode_iterator VOEXTI [
1101 (RVVM8DI "TARGET_VECTOR_ELEN_64") (RVVM4DI "TARGET_VECTOR_ELEN_64")
1102 (RVVM2DI "TARGET_VECTOR_ELEN_64") (RVVM1DI "TARGET_VECTOR_ELEN_64")
1104 (V1DI "riscv_vector::vls_mode_valid_p (V1DImode) && TARGET_VECTOR_ELEN_64")
1105 (V2DI "riscv_vector::vls_mode_valid_p (V2DImode) && TARGET_VECTOR_ELEN_64")
1106 (V4DI "riscv_vector::vls_mode_valid_p (V4DImode) && TARGET_VECTOR_ELEN_64")
1107 (V8DI "riscv_vector::vls_mode_valid_p (V8DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64")
1108 (V16DI "riscv_vector::vls_mode_valid_p (V16DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
1109 (V32DI "riscv_vector::vls_mode_valid_p (V32DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256")
1110 (V64DI "riscv_vector::vls_mode_valid_p (V64DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512")
1111 (V128DI "riscv_vector::vls_mode_valid_p (V128DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024")
1112 (V256DI "riscv_vector::vls_mode_valid_p (V256DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048")
1113 (V512DI "riscv_vector::vls_mode_valid_p (V512DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")
1116 (define_mode_iterator V1T [
1117 (RVVMF8x2QI "TARGET_MIN_VLEN > 32")
1118 (RVVMF8x3QI "TARGET_MIN_VLEN > 32")
1119 (RVVMF8x4QI "TARGET_MIN_VLEN > 32")
1120 (RVVMF8x5QI "TARGET_MIN_VLEN > 32")
1121 (RVVMF8x6QI "TARGET_MIN_VLEN > 32")
1122 (RVVMF8x7QI "TARGET_MIN_VLEN > 32")
1123 (RVVMF8x8QI "TARGET_MIN_VLEN > 32")
1124 (RVVMF4x2HI "TARGET_MIN_VLEN > 32")
1125 (RVVMF4x3HI "TARGET_MIN_VLEN > 32")
1126 (RVVMF4x4HI "TARGET_MIN_VLEN > 32")
1127 (RVVMF4x5HI "TARGET_MIN_VLEN > 32")
1128 (RVVMF4x6HI "TARGET_MIN_VLEN > 32")
1129 (RVVMF4x7HI "TARGET_MIN_VLEN > 32")
1130 (RVVMF4x8HI "TARGET_MIN_VLEN > 32")
1131 (RVVMF2x2SI "TARGET_MIN_VLEN > 32")
1132 (RVVMF2x3SI "TARGET_MIN_VLEN > 32")
1133 (RVVMF2x4SI "TARGET_MIN_VLEN > 32")
1134 (RVVMF2x5SI "TARGET_MIN_VLEN > 32")
1135 (RVVMF2x6SI "TARGET_MIN_VLEN > 32")
1136 (RVVMF2x7SI "TARGET_MIN_VLEN > 32")
1137 (RVVMF2x8SI "TARGET_MIN_VLEN > 32")
1138 (RVVM1x2DI "TARGET_VECTOR_ELEN_64")
1139 (RVVM1x3DI "TARGET_VECTOR_ELEN_64")
1140 (RVVM1x4DI "TARGET_VECTOR_ELEN_64")
1141 (RVVM1x5DI "TARGET_VECTOR_ELEN_64")
1142 (RVVM1x6DI "TARGET_VECTOR_ELEN_64")
1143 (RVVM1x7DI "TARGET_VECTOR_ELEN_64")
1144 (RVVM1x8DI "TARGET_VECTOR_ELEN_64")
1145 (RVVMF4x2HF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
1146 (RVVMF4x3HF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
1147 (RVVMF4x4HF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
1148 (RVVMF4x5HF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
1149 (RVVMF4x6HF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
1150 (RVVMF4x7HF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
1151 (RVVMF4x8HF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_16")
1152 (RVVMF2x2SF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_32")
1153 (RVVMF2x3SF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_32")
1154 (RVVMF2x4SF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_32")
1155 (RVVMF2x5SF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_32")
1156 (RVVMF2x6SF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_32")
1157 (RVVMF2x7SF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_32")
1158 (RVVMF2x8SF "TARGET_MIN_VLEN > 32 && TARGET_VECTOR_ELEN_FP_32")
1159 (RVVM1x2DF "TARGET_VECTOR_ELEN_FP_64")
1160 (RVVM1x3DF "TARGET_VECTOR_ELEN_FP_64")
1161 (RVVM1x4DF "TARGET_VECTOR_ELEN_FP_64")
1162 (RVVM1x5DF "TARGET_VECTOR_ELEN_FP_64")
1163 (RVVM1x6DF "TARGET_VECTOR_ELEN_FP_64")
1164 (RVVM1x7DF "TARGET_VECTOR_ELEN_FP_64")
1165 (RVVM1x8DF "TARGET_VECTOR_ELEN_FP_64")
1168 (define_mode_iterator V2T [
1190 (RVVM2x2DI "TARGET_VECTOR_ELEN_64")
1191 (RVVM2x3DI "TARGET_VECTOR_ELEN_64")
1192 (RVVM2x4DI "TARGET_VECTOR_ELEN_64")
1193 (RVVMF2x2HF "TARGET_VECTOR_ELEN_FP_16")
1194 (RVVMF2x3HF "TARGET_VECTOR_ELEN_FP_16")
1195 (RVVMF2x4HF "TARGET_VECTOR_ELEN_FP_16")
1196 (RVVMF2x5HF "TARGET_VECTOR_ELEN_FP_16")
1197 (RVVMF2x6HF "TARGET_VECTOR_ELEN_FP_16")
1198 (RVVMF2x7HF "TARGET_VECTOR_ELEN_FP_16")
1199 (RVVMF2x8HF "TARGET_VECTOR_ELEN_FP_16")
1200 (RVVM1x2SF "TARGET_VECTOR_ELEN_FP_32")
1201 (RVVM1x3SF "TARGET_VECTOR_ELEN_FP_32")
1202 (RVVM1x4SF "TARGET_VECTOR_ELEN_FP_32")
1203 (RVVM1x5SF "TARGET_VECTOR_ELEN_FP_32")
1204 (RVVM1x6SF "TARGET_VECTOR_ELEN_FP_32")
1205 (RVVM1x7SF "TARGET_VECTOR_ELEN_FP_32")
1206 (RVVM1x8SF "TARGET_VECTOR_ELEN_FP_32")
1207 (RVVM2x2DF "TARGET_VECTOR_ELEN_FP_64")
1208 (RVVM2x3DF "TARGET_VECTOR_ELEN_FP_64")
1209 (RVVM2x4DF "TARGET_VECTOR_ELEN_FP_64")
1212 (define_mode_iterator V4T [
1230 (RVVM4x2DI "TARGET_VECTOR_ELEN_64")
1231 (RVVM1x2HF "TARGET_VECTOR_ELEN_FP_16")
1232 (RVVM1x3HF "TARGET_VECTOR_ELEN_FP_16")
1233 (RVVM1x4HF "TARGET_VECTOR_ELEN_FP_16")
1234 (RVVM1x5HF "TARGET_VECTOR_ELEN_FP_16")
1235 (RVVM1x6HF "TARGET_VECTOR_ELEN_FP_16")
1236 (RVVM1x7HF "TARGET_VECTOR_ELEN_FP_16")
1237 (RVVM1x8HF "TARGET_VECTOR_ELEN_FP_16")
1238 (RVVM2x2SF "TARGET_VECTOR_ELEN_FP_32")
1239 (RVVM2x3SF "TARGET_VECTOR_ELEN_FP_32")
1240 (RVVM2x4SF "TARGET_VECTOR_ELEN_FP_32")
1241 (RVVM4x2DF "TARGET_VECTOR_ELEN_FP_64")
1244 (define_mode_iterator V8T [
1256 (RVVM2x2HF "TARGET_VECTOR_ELEN_FP_16")
1257 (RVVM2x3HF "TARGET_VECTOR_ELEN_FP_16")
1258 (RVVM2x4HF "TARGET_VECTOR_ELEN_FP_16")
1259 (RVVM4x2SF "TARGET_VECTOR_ELEN_FP_32")
1262 (define_mode_iterator V16T [
1267 (RVVM4x2HF "TARGET_VECTOR_ELEN_FP_16")
1270 (define_mode_iterator V32T [
1274 (define_mode_attr V_LMUL1 [
1275 (RVVM8QI "RVVM1QI") (RVVM4QI "RVVM1QI") (RVVM2QI "RVVM1QI") (RVVM1QI "RVVM1QI") (RVVMF2QI "RVVM1QI") (RVVMF4QI "RVVM1QI") (RVVMF8QI "RVVM1QI")
1277 (RVVM8HI "RVVM1HI") (RVVM4HI "RVVM1HI") (RVVM2HI "RVVM1HI") (RVVM1HI "RVVM1HI") (RVVMF2HI "RVVM1HI") (RVVMF4HI "RVVM1HI")
1279 (RVVM8SI "RVVM1SI") (RVVM4SI "RVVM1SI") (RVVM2SI "RVVM1SI") (RVVM1SI "RVVM1SI") (RVVMF2SI "RVVM1SI")
1281 (RVVM8DI "RVVM1DI") (RVVM4DI "RVVM1DI") (RVVM2DI "RVVM1DI") (RVVM1DI "RVVM1DI")
1283 (RVVM8HF "RVVM1HF") (RVVM4HF "RVVM1HF") (RVVM2HF "RVVM1HF") (RVVM1HF "RVVM1HF") (RVVMF2HF "RVVM1HF") (RVVMF4HF "RVVM1HF")
1285 (RVVM8SF "RVVM1SF") (RVVM4SF "RVVM1SF") (RVVM2SF "RVVM1SF") (RVVM1SF "RVVM1SF") (RVVMF2SF "RVVM1SF")
1287 (RVVM8DF "RVVM1DF") (RVVM4DF "RVVM1DF") (RVVM2DF "RVVM1DF") (RVVM1DF "RVVM1DF")
1370 (define_mode_attr V_EXT_LMUL1 [
1371 (RVVM8QI "RVVM1HI") (RVVM4QI "RVVM1HI") (RVVM2QI "RVVM1HI") (RVVM1QI "RVVM1HI") (RVVMF2QI "RVVM1HI") (RVVMF4QI "RVVM1HI") (RVVMF8QI "RVVM1HI")
1373 (RVVM8HI "RVVM1SI") (RVVM4HI "RVVM1SI") (RVVM2HI "RVVM1SI") (RVVM1HI "RVVM1SI") (RVVMF2HI "RVVM1SI") (RVVMF4HI "RVVM1SI")
1375 (RVVM8SI "RVVM1DI") (RVVM4SI "RVVM1DI") (RVVM2SI "RVVM1DI") (RVVM1SI "RVVM1DI") (RVVMF2SI "RVVM1DI")
1377 (RVVM8HF "RVVM1SF") (RVVM4HF "RVVM1SF") (RVVM2HF "RVVM1SF") (RVVM1HF "RVVM1SF") (RVVMF2HF "RVVM1SF") (RVVMF4HF "RVVM1SF")
1379 (RVVM8SF "RVVM1DF") (RVVM4SF "RVVM1DF") (RVVM2SF "RVVM1DF") (RVVM1SF "RVVM1DF") (RVVMF2SF "RVVM1DF")
1442 (define_mode_iterator VLSB [
1443 (V1BI "riscv_vector::vls_mode_valid_p (V1BImode)")
1444 (V2BI "riscv_vector::vls_mode_valid_p (V2BImode)")
1445 (V4BI "riscv_vector::vls_mode_valid_p (V4BImode)")
1446 (V8BI "riscv_vector::vls_mode_valid_p (V8BImode)")
1447 (V16BI "riscv_vector::vls_mode_valid_p (V16BImode)")
1448 (V32BI "riscv_vector::vls_mode_valid_p (V32BImode)")
1449 (V64BI "riscv_vector::vls_mode_valid_p (V64BImode) && TARGET_MIN_VLEN >= 64")
1450 (V128BI "riscv_vector::vls_mode_valid_p (V128BImode) && TARGET_MIN_VLEN >= 128")
1451 (V256BI "riscv_vector::vls_mode_valid_p (V256BImode) && TARGET_MIN_VLEN >= 256")
1452 (V512BI "riscv_vector::vls_mode_valid_p (V512BImode) && TARGET_MIN_VLEN >= 512")
1453 (V1024BI "riscv_vector::vls_mode_valid_p (V1024BImode) && TARGET_MIN_VLEN >= 1024")
1454 (V2048BI "riscv_vector::vls_mode_valid_p (V2048BImode) && TARGET_MIN_VLEN >= 2048")
1455 (V4096BI "riscv_vector::vls_mode_valid_p (V4096BImode) && TARGET_MIN_VLEN >= 4096")])
1457 (define_mode_iterator VB [
1458 (RVVMF64BI "TARGET_MIN_VLEN > 32") RVVMF32BI RVVMF16BI RVVMF8BI RVVMF4BI RVVMF2BI RVVM1BI
1461 ;; Iterator for indexed loads and stores. We must disallow 64-bit indices on
1462 ;; XLEN=32 targets. TODO: Split iterators so more of them can be reused, i.e.
1463 ;; VI8, VI16, VI32, VI64 and then use
1464 ;; VINDEXED [VI8 VI16 VI32 (VI64 "TARGET_64BIT")].
1466 (define_mode_iterator VINDEXED [
1467 RVVM8QI RVVM4QI RVVM2QI RVVM1QI RVVMF2QI RVVMF4QI (RVVMF8QI "TARGET_MIN_VLEN > 32")
1469 RVVM8HI RVVM4HI RVVM2HI RVVM1HI RVVMF2HI (RVVMF4HI "TARGET_MIN_VLEN > 32")
1471 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
1473 (RVVM8DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT")
1474 (RVVM4DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT")
1475 (RVVM2DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT")
1476 (RVVM1DI "TARGET_VECTOR_ELEN_64 && TARGET_64BIT")
1478 (RVVM8HF "TARGET_ZVFH") (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH")
1479 (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH")
1480 (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
1482 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32")
1483 (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") (RVVM1SF "TARGET_VECTOR_ELEN_FP_32")
1484 (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
1486 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_64BIT")
1487 (RVVM4DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_64BIT")
1488 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_64BIT")
1489 (RVVM1DF "TARGET_VECTOR_ELEN_FP_64 && TARGET_64BIT")
1491 (V1QI "riscv_vector::vls_mode_valid_p (V1QImode)")
1492 (V2QI "riscv_vector::vls_mode_valid_p (V2QImode)")
1493 (V4QI "riscv_vector::vls_mode_valid_p (V4QImode)")
1494 (V8QI "riscv_vector::vls_mode_valid_p (V8QImode)")
1495 (V16QI "riscv_vector::vls_mode_valid_p (V16QImode)")
1496 (V32QI "riscv_vector::vls_mode_valid_p (V32QImode)")
1497 (V64QI "riscv_vector::vls_mode_valid_p (V64QImode) && TARGET_MIN_VLEN >= 64")
1498 (V128QI "riscv_vector::vls_mode_valid_p (V128QImode) && TARGET_MIN_VLEN >= 128")
1499 (V256QI "riscv_vector::vls_mode_valid_p (V256QImode) && TARGET_MIN_VLEN >= 256")
1500 (V512QI "riscv_vector::vls_mode_valid_p (V512QImode) && TARGET_MIN_VLEN >= 512")
1501 (V1024QI "riscv_vector::vls_mode_valid_p (V1024QImode) && TARGET_MIN_VLEN >= 1024")
1502 (V2048QI "riscv_vector::vls_mode_valid_p (V2048QImode) && TARGET_MIN_VLEN >= 2048")
1503 (V4096QI "riscv_vector::vls_mode_valid_p (V4096QImode) && TARGET_MIN_VLEN >= 4096")
1504 (V1HI "riscv_vector::vls_mode_valid_p (V1HImode)")
1505 (V2HI "riscv_vector::vls_mode_valid_p (V2HImode)")
1506 (V4HI "riscv_vector::vls_mode_valid_p (V4HImode)")
1507 (V8HI "riscv_vector::vls_mode_valid_p (V8HImode)")
1508 (V16HI "riscv_vector::vls_mode_valid_p (V16HImode)")
1509 (V32HI "riscv_vector::vls_mode_valid_p (V32HImode) && TARGET_MIN_VLEN >= 64")
1510 (V64HI "riscv_vector::vls_mode_valid_p (V64HImode) && TARGET_MIN_VLEN >= 128")
1511 (V128HI "riscv_vector::vls_mode_valid_p (V128HImode) && TARGET_MIN_VLEN >= 256")
1512 (V256HI "riscv_vector::vls_mode_valid_p (V256HImode) && TARGET_MIN_VLEN >= 512")
1513 (V512HI "riscv_vector::vls_mode_valid_p (V512HImode) && TARGET_MIN_VLEN >= 1024")
1514 (V1024HI "riscv_vector::vls_mode_valid_p (V1024HImode) && TARGET_MIN_VLEN >= 2048")
1515 (V2048HI "riscv_vector::vls_mode_valid_p (V2048HImode) && TARGET_MIN_VLEN >= 4096")
1516 (V1SI "riscv_vector::vls_mode_valid_p (V1SImode)")
1517 (V2SI "riscv_vector::vls_mode_valid_p (V2SImode)")
1518 (V4SI "riscv_vector::vls_mode_valid_p (V4SImode)")
1519 (V8SI "riscv_vector::vls_mode_valid_p (V8SImode)")
1520 (V16SI "riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= 64")
1521 (V32SI "riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= 128")
1522 (V64SI "riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= 256")
1523 (V128SI "riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= 512")
1524 (V256SI "riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_MIN_VLEN >= 1024")
1525 (V512SI "riscv_vector::vls_mode_valid_p (V512SImode) && TARGET_MIN_VLEN >= 2048")
1526 (V1024SI "riscv_vector::vls_mode_valid_p (V1024SImode) && TARGET_MIN_VLEN >= 4096")
1527 (V1DI "riscv_vector::vls_mode_valid_p (V1DImode) && TARGET_VECTOR_ELEN_64 && TARGET_64BIT")
1528 (V2DI "riscv_vector::vls_mode_valid_p (V2DImode) && TARGET_VECTOR_ELEN_64 && TARGET_64BIT")
1529 (V4DI "riscv_vector::vls_mode_valid_p (V4DImode) && TARGET_VECTOR_ELEN_64 && TARGET_64BIT")
1530 (V8DI "riscv_vector::vls_mode_valid_p (V8DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64 && TARGET_64BIT")
1531 (V16DI "riscv_vector::vls_mode_valid_p (V16DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128 && TARGET_64BIT")
1532 (V32DI "riscv_vector::vls_mode_valid_p (V32DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256 && TARGET_64BIT")
1533 (V64DI "riscv_vector::vls_mode_valid_p (V64DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512 && TARGET_64BIT")
1534 (V128DI "riscv_vector::vls_mode_valid_p (V128DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024 && TARGET_64BIT")
1535 (V256DI "riscv_vector::vls_mode_valid_p (V256DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048 && TARGET_64BIT")
1536 (V512DI "riscv_vector::vls_mode_valid_p (V512DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096 && TARGET_64BIT")
1538 (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_ZVFH")
1539 (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_ZVFH")
1540 (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_ZVFH")
1541 (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_ZVFH")
1542 (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_ZVFH")
1543 (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 64")
1544 (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
1545 (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 256")
1546 (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 512")
1547 (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024")
1548 (V1024HF "riscv_vector::vls_mode_valid_p (V1024HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 2048")
1549 (V2048HF "riscv_vector::vls_mode_valid_p (V2048HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 4096")
1550 (V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_FP_32")
1551 (V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_FP_32")
1552 (V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_FP_32")
1553 (V8SF "riscv_vector::vls_mode_valid_p (V8SFmode) && TARGET_VECTOR_ELEN_FP_32")
1554 (V16SF "riscv_vector::vls_mode_valid_p (V16SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
1555 (V32SF "riscv_vector::vls_mode_valid_p (V32SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
1556 (V64SF "riscv_vector::vls_mode_valid_p (V64SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
1557 (V128SF "riscv_vector::vls_mode_valid_p (V128SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
1558 (V256SF "riscv_vector::vls_mode_valid_p (V256SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
1559 (V512SF "riscv_vector::vls_mode_valid_p (V512SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
1560 (V1024SF "riscv_vector::vls_mode_valid_p (V1024SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
1561 (V1DF "riscv_vector::vls_mode_valid_p (V1DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_64BIT")
1562 (V2DF "riscv_vector::vls_mode_valid_p (V2DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_64BIT")
1563 (V4DF "riscv_vector::vls_mode_valid_p (V4DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_64BIT")
1564 (V8DF "riscv_vector::vls_mode_valid_p (V8DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64 && TARGET_64BIT")
1565 (V16DF "riscv_vector::vls_mode_valid_p (V16DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128 && TARGET_64BIT")
1566 (V32DF "riscv_vector::vls_mode_valid_p (V32DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256 && TARGET_64BIT")
1567 (V64DF "riscv_vector::vls_mode_valid_p (V64DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512 && TARGET_64BIT")
1568 (V128DF "riscv_vector::vls_mode_valid_p (V128DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024 && TARGET_64BIT")
1569 (V256DF "riscv_vector::vls_mode_valid_p (V256DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048 && TARGET_64BIT")
1570 (V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096 && TARGET_64BIT")
1573 (define_mode_iterator VB_VLS [VB VLSB])
1575 (define_mode_iterator VLS [VLSI VLSF_ZVFHMIN])
1577 (define_mode_iterator VLS_ZVFH [VLSI VLSF])
1579 (define_mode_iterator V [VI VF_ZVFHMIN])
1581 (define_mode_iterator V_ZVFH [VI VF])
1583 (define_mode_iterator V_VLS [V VLS])
1585 (define_mode_iterator V_VLS_ZVFH [V_ZVFH VLS_ZVFH])
1587 (define_mode_iterator V_VLSI [VI VLSI])
1589 (define_mode_iterator V_VLSF [VF VLSF])
1591 (define_mode_iterator V_VLSF_ZVFHMIN [VF_ZVFHMIN VLSF_ZVFHMIN])
1593 (define_mode_iterator VT [V1T V2T V4T V8T V16T V32T])
1595 (define_int_iterator ANY_REDUC [
1596 UNSPEC_REDUC_SUM UNSPEC_REDUC_MAXU UNSPEC_REDUC_MAX UNSPEC_REDUC_MINU
1597 UNSPEC_REDUC_MIN UNSPEC_REDUC_AND UNSPEC_REDUC_OR UNSPEC_REDUC_XOR
1600 (define_int_iterator ANY_WREDUC [
1601 UNSPEC_WREDUC_SUM UNSPEC_WREDUC_SUMU
1604 (define_int_iterator ANY_FREDUC [
1605 UNSPEC_REDUC_MAX UNSPEC_REDUC_MIN
1608 (define_int_iterator ANY_FREDUC_SUM [
1609 UNSPEC_REDUC_SUM_ORDERED UNSPEC_REDUC_SUM_UNORDERED
1612 (define_int_iterator ANY_FWREDUC_SUM [
1613 UNSPEC_WREDUC_SUM_ORDERED UNSPEC_WREDUC_SUM_UNORDERED
1616 (define_int_attr reduc_op [
1617 (UNSPEC_REDUC_SUM "redsum")
1618 (UNSPEC_REDUC_SUM_ORDERED "redosum") (UNSPEC_REDUC_SUM_UNORDERED "redusum")
1619 (UNSPEC_REDUC_MAXU "redmaxu") (UNSPEC_REDUC_MAX "redmax") (UNSPEC_REDUC_MINU "redminu") (UNSPEC_REDUC_MIN "redmin")
1620 (UNSPEC_REDUC_AND "redand") (UNSPEC_REDUC_OR "redor") (UNSPEC_REDUC_XOR "redxor")
1621 (UNSPEC_WREDUC_SUM "wredsum") (UNSPEC_WREDUC_SUMU "wredsumu")
1622 (UNSPEC_WREDUC_SUM_ORDERED "wredosum") (UNSPEC_WREDUC_SUM_UNORDERED "wredusum")
1625 (define_code_attr WREDUC_UNSPEC [(zero_extend "UNSPEC_WREDUC_SUMU") (sign_extend "UNSPEC_WREDUC_SUM")])
1627 (define_mode_attr VINDEX [
1628 (RVVM8QI "RVVM8QI") (RVVM4QI "RVVM4QI") (RVVM2QI "RVVM2QI") (RVVM1QI "RVVM1QI")
1629 (RVVMF2QI "RVVMF2QI") (RVVMF4QI "RVVMF4QI") (RVVMF8QI "RVVMF8QI")
1631 (RVVM8HI "RVVM8HI") (RVVM4HI "RVVM4HI") (RVVM2HI "RVVM2HI") (RVVM1HI "RVVM1HI") (RVVMF2HI "RVVMF2HI") (RVVMF4HI "RVVMF4HI")
1633 (RVVM8HF "RVVM8HI") (RVVM4HF "RVVM4HI") (RVVM2HF "RVVM2HI") (RVVM1HF "RVVM1HI") (RVVMF2HF "RVVMF2HI") (RVVMF4HF "RVVMF4HI")
1635 (RVVM8SI "RVVM8SI") (RVVM4SI "RVVM4SI") (RVVM2SI "RVVM2SI") (RVVM1SI "RVVM1SI") (RVVMF2SI "RVVMF2SI")
1637 (RVVM8SF "RVVM8SI") (RVVM4SF "RVVM4SI") (RVVM2SF "RVVM2SI") (RVVM1SF "RVVM1SI") (RVVMF2SF "RVVMF2SI")
1639 (RVVM8DI "RVVM8DI") (RVVM4DI "RVVM4DI") (RVVM2DI "RVVM2DI") (RVVM1DI "RVVM1DI")
1641 (RVVM8DF "RVVM8DI") (RVVM4DF "RVVM4DI") (RVVM2DF "RVVM2DI") (RVVM1DF "RVVM1DI")
1724 (define_mode_attr VINDEXEI16 [
1725 (RVVM4QI "RVVM8HI") (RVVM2QI "RVVM4HI") (RVVM1QI "RVVM2HI") (RVVMF2QI "RVVM1HI") (RVVMF4QI "RVVMF2HI") (RVVMF8QI "RVVMF4HI")
1727 (RVVM8HI "RVVM8HI") (RVVM4HI "RVVM4HI") (RVVM2HI "RVVM2HI") (RVVM1HI "RVVM1HI") (RVVMF2HI "RVVMF2HI") (RVVMF4HI "RVVMF4HI")
1729 (RVVM8SI "RVVM4HI") (RVVM4SI "RVVM2HI") (RVVM2SI "RVVM1HI") (RVVM1SI "RVVMF2HI") (RVVMF2SI "RVVMF4HI")
1731 (RVVM8DI "RVVM2HI") (RVVM4DI "RVVM1HI") (RVVM2DI "RVVMF2HI") (RVVM1DI "RVVMF4HI")
1733 (RVVM8HF "RVVM8HI") (RVVM4HF "RVVM4HI") (RVVM2HF "RVVM2HI") (RVVM1HF "RVVM1HI") (RVVMF2HF "RVVMF2HI") (RVVMF4HF "RVVMF4HI")
1735 (RVVM8SF "RVVM4HI") (RVVM4SF "RVVM2HI") (RVVM2SF "RVVM1HI") (RVVM1SF "RVVMF2HI") (RVVMF2SF "RVVMF4HI")
1737 (RVVM8DF "RVVM2HI") (RVVM4DF "RVVM1HI") (RVVM2DF "RVVMF2HI") (RVVM1DF "RVVMF4HI")
1819 (define_mode_attr VM [
1820 (RVVM8QI "RVVM1BI") (RVVM4QI "RVVMF2BI") (RVVM2QI "RVVMF4BI") (RVVM1QI "RVVMF8BI") (RVVMF2QI "RVVMF16BI") (RVVMF4QI "RVVMF32BI") (RVVMF8QI "RVVMF64BI")
1822 (RVVM8HI "RVVMF2BI") (RVVM4HI "RVVMF4BI") (RVVM2HI "RVVMF8BI") (RVVM1HI "RVVMF16BI") (RVVMF2HI "RVVMF32BI") (RVVMF4HI "RVVMF64BI")
1824 (RVVM8HF "RVVMF2BI") (RVVM4HF "RVVMF4BI") (RVVM2HF "RVVMF8BI") (RVVM1HF "RVVMF16BI") (RVVMF2HF "RVVMF32BI") (RVVMF4HF "RVVMF64BI")
1826 (RVVM8SI "RVVMF4BI") (RVVM4SI "RVVMF8BI") (RVVM2SI "RVVMF16BI") (RVVM1SI "RVVMF32BI") (RVVMF2SI "RVVMF64BI")
1828 (RVVM8SF "RVVMF4BI") (RVVM4SF "RVVMF8BI") (RVVM2SF "RVVMF16BI") (RVVM1SF "RVVMF32BI") (RVVMF2SF "RVVMF64BI")
1830 (RVVM8DI "RVVMF8BI") (RVVM4DI "RVVMF16BI") (RVVM2DI "RVVMF32BI") (RVVM1DI "RVVMF64BI")
1832 (RVVM8DF "RVVMF8BI") (RVVM4DF "RVVMF16BI") (RVVM2DF "RVVMF32BI") (RVVM1DF "RVVMF64BI")
1834 (RVVM1x8QI "RVVMF8BI") (RVVMF2x8QI "RVVMF16BI") (RVVMF4x8QI "RVVMF32BI") (RVVMF8x8QI "RVVMF64BI")
1835 (RVVM1x7QI "RVVMF8BI") (RVVMF2x7QI "RVVMF16BI") (RVVMF4x7QI "RVVMF32BI") (RVVMF8x7QI "RVVMF64BI")
1836 (RVVM1x6QI "RVVMF8BI") (RVVMF2x6QI "RVVMF16BI") (RVVMF4x6QI "RVVMF32BI") (RVVMF8x6QI "RVVMF64BI")
1837 (RVVM1x5QI "RVVMF8BI") (RVVMF2x5QI "RVVMF16BI") (RVVMF4x5QI "RVVMF32BI") (RVVMF8x5QI "RVVMF64BI")
1838 (RVVM2x4QI "RVVMF4BI") (RVVM1x4QI "RVVMF8BI") (RVVMF2x4QI "RVVMF16BI") (RVVMF4x4QI "RVVMF32BI") (RVVMF8x4QI "RVVMF64BI")
1839 (RVVM2x3QI "RVVMF4BI") (RVVM1x3QI "RVVMF8BI") (RVVMF2x3QI "RVVMF16BI") (RVVMF4x3QI "RVVMF32BI") (RVVMF8x3QI "RVVMF64BI")
1840 (RVVM4x2QI "RVVMF2BI") (RVVM2x2QI "RVVMF4BI") (RVVM1x2QI "RVVMF8BI") (RVVMF2x2QI "RVVMF16BI") (RVVMF4x2QI "RVVMF32BI") (RVVMF8x2QI "RVVMF64BI")
1842 (RVVM1x8HI "RVVMF16BI") (RVVMF2x8HI "RVVMF32BI") (RVVMF4x8HI "RVVMF64BI")
1843 (RVVM1x7HI "RVVMF16BI") (RVVMF2x7HI "RVVMF32BI") (RVVMF4x7HI "RVVMF64BI")
1844 (RVVM1x6HI "RVVMF16BI") (RVVMF2x6HI "RVVMF32BI") (RVVMF4x6HI "RVVMF64BI")
1845 (RVVM1x5HI "RVVMF16BI") (RVVMF2x5HI "RVVMF32BI") (RVVMF4x5HI "RVVMF64BI")
1846 (RVVM2x4HI "RVVMF8BI") (RVVM1x4HI "RVVMF16BI") (RVVMF2x4HI "RVVMF32BI") (RVVMF4x4HI "RVVMF64BI")
1847 (RVVM2x3HI "RVVMF8BI") (RVVM1x3HI "RVVMF16BI") (RVVMF2x3HI "RVVMF32BI") (RVVMF4x3HI "RVVMF64BI")
1848 (RVVM4x2HI "RVVMF4BI") (RVVM2x2HI "RVVMF8BI") (RVVM1x2HI "RVVMF16BI") (RVVMF2x2HI "RVVMF32BI") (RVVMF4x2HI "RVVMF64BI")
1850 (RVVM1x8HF "RVVMF16BI") (RVVMF2x8HF "RVVMF32BI") (RVVMF4x8HF "RVVMF64BI")
1851 (RVVM1x7HF "RVVMF16BI") (RVVMF2x7HF "RVVMF32BI") (RVVMF4x7HF "RVVMF64BI")
1852 (RVVM1x6HF "RVVMF16BI") (RVVMF2x6HF "RVVMF32BI") (RVVMF4x6HF "RVVMF64BI")
1853 (RVVM1x5HF "RVVMF16BI") (RVVMF2x5HF "RVVMF32BI") (RVVMF4x5HF "RVVMF64BI")
1854 (RVVM2x4HF "RVVMF8BI") (RVVM1x4HF "RVVMF16BI") (RVVMF2x4HF "RVVMF32BI") (RVVMF4x4HF "RVVMF64BI")
1855 (RVVM2x3HF "RVVMF8BI") (RVVM1x3HF "RVVMF16BI") (RVVMF2x3HF "RVVMF32BI") (RVVMF4x3HF "RVVMF64BI")
1856 (RVVM4x2HF "RVVMF4BI") (RVVM2x2HF "RVVMF8BI") (RVVM1x2HF "RVVMF16BI") (RVVMF2x2HF "RVVMF32BI") (RVVMF4x2HF "RVVMF64BI")
1858 (RVVM1x8SI "RVVMF32BI") (RVVMF2x8SI "RVVMF64BI")
1859 (RVVM1x7SI "RVVMF32BI") (RVVMF2x7SI "RVVMF64BI")
1860 (RVVM1x6SI "RVVMF32BI") (RVVMF2x6SI "RVVMF64BI")
1861 (RVVM1x5SI "RVVMF32BI") (RVVMF2x5SI "RVVMF64BI")
1862 (RVVM2x4SI "RVVMF16BI") (RVVM1x4SI "RVVMF32BI") (RVVMF2x4SI "RVVMF64BI")
1863 (RVVM2x3SI "RVVMF16BI") (RVVM1x3SI "RVVMF32BI") (RVVMF2x3SI "RVVMF64BI")
1864 (RVVM4x2SI "RVVMF8BI") (RVVM2x2SI "RVVMF16BI") (RVVM1x2SI "RVVMF32BI") (RVVMF2x2SI "RVVMF64BI")
1866 (RVVM1x8SF "RVVMF32BI") (RVVMF2x8SF "RVVMF64BI")
1867 (RVVM1x7SF "RVVMF32BI") (RVVMF2x7SF "RVVMF64BI")
1868 (RVVM1x6SF "RVVMF32BI") (RVVMF2x6SF "RVVMF64BI")
1869 (RVVM1x5SF "RVVMF32BI") (RVVMF2x5SF "RVVMF64BI")
1870 (RVVM2x4SF "RVVMF16BI") (RVVM1x4SF "RVVMF32BI") (RVVMF2x4SF "RVVMF64BI")
1871 (RVVM2x3SF "RVVMF16BI") (RVVM1x3SF "RVVMF32BI") (RVVMF2x3SF "RVVMF64BI")
1872 (RVVM4x2SF "RVVMF8BI") (RVVM2x2SF "RVVMF16BI") (RVVM1x2SF "RVVMF32BI") (RVVMF2x2SF "RVVMF64BI")
1874 (RVVM1x8DI "RVVMF64BI")
1875 (RVVM1x7DI "RVVMF64BI")
1876 (RVVM1x6DI "RVVMF64BI")
1877 (RVVM1x5DI "RVVMF64BI")
1878 (RVVM2x4DI "RVVMF32BI")
1879 (RVVM1x4DI "RVVMF64BI")
1880 (RVVM2x3DI "RVVMF32BI")
1881 (RVVM1x3DI "RVVMF64BI")
1882 (RVVM4x2DI "RVVMF16BI")
1883 (RVVM2x2DI "RVVMF32BI")
1884 (RVVM1x2DI "RVVMF64BI")
1886 (RVVM1x8DF "RVVMF64BI")
1887 (RVVM1x7DF "RVVMF64BI")
1888 (RVVM1x6DF "RVVMF64BI")
1889 (RVVM1x5DF "RVVMF64BI")
1890 (RVVM2x4DF "RVVMF32BI")
1891 (RVVM1x4DF "RVVMF64BI")
1892 (RVVM2x3DF "RVVMF32BI")
1893 (RVVM1x3DF "RVVMF64BI")
1894 (RVVM4x2DF "RVVMF16BI")
1895 (RVVM2x2DF "RVVMF32BI")
1896 (RVVM1x2DF "RVVMF64BI")
1899 (V1QI "V1BI") (V2QI "V2BI") (V4QI "V4BI") (V8QI "V8BI") (V16QI "V16BI") (V32QI "V32BI")
1900 (V64QI "V64BI") (V128QI "V128BI") (V256QI "V256BI") (V512QI "V512BI")
1901 (V1024QI "V1024BI") (V2048QI "V2048BI") (V4096QI "V4096BI")
1902 (V1HI "V1BI") (V2HI "V2BI") (V4HI "V4BI") (V8HI "V8BI") (V16HI "V16BI")
1903 (V32HI "V32BI") (V64HI "V64BI") (V128HI "V128BI") (V256HI "V256BI")
1904 (V512HI "V512BI") (V1024HI "V1024BI") (V2048HI "V2048BI")
1905 (V1SI "V1BI") (V2SI "V2BI") (V4SI "V4BI") (V8SI "V8BI")
1906 (V16SI "V16BI") (V32SI "V32BI") (V64SI "V64BI")
1907 (V128SI "V128BI") (V256SI "V256BI") (V512SI "V512BI") (V1024SI "V1024BI")
1908 (V1DI "V1BI") (V2DI "V2BI") (V4DI "V4BI") (V8DI "V8BI") (V16DI "V16BI") (V32DI "V32BI")
1909 (V64DI "V64BI") (V128DI "V128BI") (V256DI "V256BI") (V512DI "V512BI")
1910 (V1HF "V1BI") (V2HF "V2BI") (V4HF "V4BI") (V8HF "V8BI") (V16HF "V16BI")
1911 (V32HF "V32BI") (V64HF "V64BI") (V128HF "V128BI") (V256HF "V256BI")
1912 (V512HF "V512BI") (V1024HF "V1024BI") (V2048HF "V2048BI")
1913 (V1SF "V1BI") (V2SF "V2BI") (V4SF "V4BI") (V8SF "V8BI")
1914 (V16SF "V16BI") (V32SF "V32BI") (V64SF "V64BI")
1915 (V128SF "V128BI") (V256SF "V256BI") (V512SF "V512BI") (V1024SF "V1024BI")
1916 (V1DF "V1BI") (V2DF "V2BI") (V4DF "V4BI") (V8DF "V8BI") (V16DF "V16BI") (V32DF "V32BI")
1917 (V64DF "V64BI") (V128DF "V128BI") (V256DF "V256BI") (V512DF "V512BI")
1920 (define_mode_attr vm [
1921 (RVVM8QI "rvvm1bi") (RVVM4QI "rvvmf2bi") (RVVM2QI "rvvmf4bi") (RVVM1QI "rvvmf8bi") (RVVMF2QI "rvvmf16bi") (RVVMF4QI "rvvmf32bi") (RVVMF8QI "rvvmf64bi")
1923 (RVVM8HI "rvvmf2bi") (RVVM4HI "rvvmf4bi") (RVVM2HI "rvvmf8bi") (RVVM1HI "rvvmf16bi") (RVVMF2HI "rvvmf32bi") (RVVMF4HI "rvvmf64bi")
1925 (RVVM8HF "rvvmf2bi") (RVVM4HF "rvvmf4bi") (RVVM2HF "rvvmf8bi") (RVVM1HF "rvvmf16bi") (RVVMF2HF "rvvmf32bi") (RVVMF4HF "rvvmf64bi")
1927 (RVVM8SI "rvvmf4bi") (RVVM4SI "rvvmf8bi") (RVVM2SI "rvvmf16bi") (RVVM1SI "rvvmf32bi") (RVVMF2SI "rvvmf64bi")
1929 (RVVM8SF "rvvmf4bi") (RVVM4SF "rvvmf8bi") (RVVM2SF "rvvmf16bi") (RVVM1SF "rvvmf32bi") (RVVMF2SF "rvvmf64bi")
1931 (RVVM8DI "rvvmf8bi") (RVVM4DI "rvvmf16bi") (RVVM2DI "rvvmf32bi") (RVVM1DI "rvvmf64bi")
1933 (RVVM8DF "rvvmf8bi") (RVVM4DF "rvvmf16bi") (RVVM2DF "rvvmf32bi") (RVVM1DF "rvvmf64bi")
1935 (RVVM1x8QI "rvvmf8bi") (RVVMF2x8QI "rvvmf16bi") (RVVMF4x8QI "rvvmf32bi") (RVVMF8x8QI "rvvmf64bi")
1936 (RVVM1x7QI "rvvmf8bi") (RVVMF2x7QI "rvvmf16bi") (RVVMF4x7QI "rvvmf32bi") (RVVMF8x7QI "rvvmf64bi")
1937 (RVVM1x6QI "rvvmf8bi") (RVVMF2x6QI "rvvmf16bi") (RVVMF4x6QI "rvvmf32bi") (RVVMF8x6QI "rvvmf64bi")
1938 (RVVM1x5QI "rvvmf8bi") (RVVMF2x5QI "rvvmf16bi") (RVVMF4x5QI "rvvmf32bi") (RVVMF8x5QI "rvvmf64bi")
1939 (RVVM2x4QI "rvvmf4bi") (RVVM1x4QI "rvvmf8bi") (RVVMF2x4QI "rvvmf16bi") (RVVMF4x4QI "rvvmf32bi") (RVVMF8x4QI "rvvmf64bi")
1940 (RVVM2x3QI "rvvmf4bi") (RVVM1x3QI "rvvmf8bi") (RVVMF2x3QI "rvvmf16bi") (RVVMF4x3QI "rvvmf32bi") (RVVMF8x3QI "rvvmf64bi")
1941 (RVVM4x2QI "rvvmf2bi") (RVVM2x2QI "rvvmf4bi") (RVVM1x2QI "rvvmf8bi") (RVVMF2x2QI "rvvmf16bi") (RVVMF4x2QI "rvvmf32bi") (RVVMF8x2QI "rvvmf64bi")
1943 (RVVM1x8HI "rvvmf16bi") (RVVMF2x8HI "rvvmf32bi") (RVVMF4x8HI "rvvmf64bi")
1944 (RVVM1x7HI "rvvmf16bi") (RVVMF2x7HI "rvvmf32bi") (RVVMF4x7HI "rvvmf64bi")
1945 (RVVM1x6HI "rvvmf16bi") (RVVMF2x6HI "rvvmf32bi") (RVVMF4x6HI "rvvmf64bi")
1946 (RVVM1x5HI "rvvmf16bi") (RVVMF2x5HI "rvvmf32bi") (RVVMF4x5HI "rvvmf64bi")
1947 (RVVM2x4HI "rvvmf8bi") (RVVM1x4HI "rvvmf16bi") (RVVMF2x4HI "rvvmf32bi") (RVVMF4x4HI "rvvmf64bi")
1948 (RVVM2x3HI "rvvmf8bi") (RVVM1x3HI "rvvmf16bi") (RVVMF2x3HI "rvvmf32bi") (RVVMF4x3HI "rvvmf64bi")
1949 (RVVM4x2HI "rvvmf4bi") (RVVM2x2HI "rvvmf8bi") (RVVM1x2HI "rvvmf16bi") (RVVMF2x2HI "rvvmf32bi") (RVVMF4x2HI "rvvmf64bi")
1951 (RVVM1x8HF "rvvmf16bi") (RVVMF2x8HF "rvvmf32bi") (RVVMF4x8HF "rvvmf64bi")
1952 (RVVM1x7HF "rvvmf16bi") (RVVMF2x7HF "rvvmf32bi") (RVVMF4x7HF "rvvmf64bi")
1953 (RVVM1x6HF "rvvmf16bi") (RVVMF2x6HF "rvvmf32bi") (RVVMF4x6HF "rvvmf64bi")
1954 (RVVM1x5HF "rvvmf16bi") (RVVMF2x5HF "rvvmf32bi") (RVVMF4x5HF "rvvmf64bi")
1955 (RVVM2x4HF "rvvmf8bi") (RVVM1x4HF "rvvmf16bi") (RVVMF2x4HF "rvvmf32bi") (RVVMF4x4HF "rvvmf64bi")
1956 (RVVM2x3HF "rvvmf8bi") (RVVM1x3HF "rvvmf16bi") (RVVMF2x3HF "rvvmf32bi") (RVVMF4x3HF "rvvmf64bi")
1957 (RVVM4x2HF "rvvmf4bi") (RVVM2x2HF "rvvmf8bi") (RVVM1x2HF "rvvmf16bi") (RVVMF2x2HF "rvvmf32bi") (RVVMF4x2HF "rvvmf64bi")
1959 (RVVM1x8SI "rvvmf32bi") (RVVMF2x8SI "rvvmf64bi")
1960 (RVVM1x7SI "rvvmf32bi") (RVVMF2x7SI "rvvmf64bi")
1961 (RVVM1x6SI "rvvmf32bi") (RVVMF2x6SI "rvvmf64bi")
1962 (RVVM1x5SI "rvvmf32bi") (RVVMF2x5SI "rvvmf64bi")
1963 (RVVM2x4SI "rvvmf16bi") (RVVM1x4SI "rvvmf32bi") (RVVMF2x4SI "rvvmf64bi")
1964 (RVVM2x3SI "rvvmf16bi") (RVVM1x3SI "rvvmf32bi") (RVVMF2x3SI "rvvmf64bi")
1965 (RVVM4x2SI "rvvmf4bi") (RVVM2x2SI "rvvmf16bi") (RVVM1x2SI "rvvmf32bi") (RVVMF2x2SI "rvvmf64bi")
1967 (RVVM1x8SF "rvvmf32bi") (RVVMF2x8SF "rvvmf64bi")
1968 (RVVM1x7SF "rvvmf32bi") (RVVMF2x7SF "rvvmf64bi")
1969 (RVVM1x6SF "rvvmf32bi") (RVVMF2x6SF "rvvmf64bi")
1970 (RVVM1x5SF "rvvmf32bi") (RVVMF2x5SF "rvvmf64bi")
1971 (RVVM2x4SF "rvvmf16bi") (RVVM1x4SF "rvvmf32bi") (RVVMF2x4SF "rvvmf64bi")
1972 (RVVM2x3SF "rvvmf16bi") (RVVM1x3SF "rvvmf32bi") (RVVMF2x3SF "rvvmf64bi")
1973 (RVVM4x2SF "rvvmf4bi") (RVVM2x2SF "rvvmf16bi") (RVVM1x2SF "rvvmf32bi") (RVVMF2x2SF "rvvmf64bi")
1975 (RVVM1x8DI "rvvmf64bi")
1976 (RVVM1x7DI "rvvmf64bi")
1977 (RVVM1x6DI "rvvmf64bi")
1978 (RVVM1x5DI "rvvmf64bi")
1979 (RVVM2x4DI "rvvmf32bi")
1980 (RVVM1x4DI "rvvmf64bi")
1981 (RVVM2x3DI "rvvmf32bi")
1982 (RVVM1x3DI "rvvmf64bi")
1983 (RVVM4x2DI "rvvmf16bi")
1984 (RVVM2x2DI "rvvmf32bi")
1985 (RVVM1x2DI "rvvmf64bi")
1987 (RVVM1x8DF "rvvmf64bi")
1988 (RVVM1x7DF "rvvmf64bi")
1989 (RVVM1x6DF "rvvmf64bi")
1990 (RVVM1x5DF "rvvmf64bi")
1991 (RVVM2x4DF "rvvmf32bi")
1992 (RVVM1x4DF "rvvmf64bi")
1993 (RVVM2x3DF "rvvmf32bi")
1994 (RVVM1x3DF "rvvmf64bi")
1995 (RVVM4x2DF "rvvmf16bi")
1996 (RVVM2x2DF "rvvmf32bi")
1997 (RVVM1x2DF "rvvmf64bi")
2000 (V1QI "v1bi") (V2QI "v2bi") (V4QI "v4bi") (V8QI "v8bi") (V16QI "v16bi") (V32QI "v32bi")
2001 (V64QI "v64bi") (V128QI "v128bi") (V256QI "v256bi") (V512QI "v512bi")
2002 (V1024QI "v1024bi") (V2048QI "v2048bi") (V4096QI "v4096bi")
2003 (V1HI "v1bi") (V2HI "v2bi") (V4HI "v4bi") (V8HI "v8bi") (V16HI "v16bi")
2004 (V32HI "v32bi") (V64HI "v64bi") (V128HI "v128bi") (V256HI "v256bi")
2005 (V512HI "v512bi") (V1024HI "v1024bi") (V2048HI "v2048bi")
2006 (V1SI "v1bi") (V2SI "v2bi") (V4SI "v4bi") (V8SI "v8bi")
2007 (V16SI "v16bi") (V32SI "v32bi") (V64SI "v64bi")
2008 (V128SI "v128bi") (V256SI "v256bi") (V512SI "v512bi") (V1024SI "v1024bi")
2009 (V1DI "v1bi") (V2DI "v2bi") (V4DI "v4bi") (V8DI "v8bi") (V16DI "v16bi") (V32DI "v32bi")
2010 (V64DI "v64bi") (V128DI "v128bi") (V256DI "v256bi") (V512DI "v512bi")
2011 (V1HF "v1bi") (V2HF "v2bi") (V4HF "v4bi") (V8HF "v8bi") (V16HF "v16bi")
2012 (V32HF "v32bi") (V64HF "v64bi") (V128HF "v128bi") (V256HF "v256bi")
2013 (V512HF "v512bi") (V1024HF "v1024bi") (V2048HF "v2048bi")
2014 (V1SF "v1bi") (V2SF "v2bi") (V4SF "v4bi") (V8SF "v8bi")
2015 (V16SF "v16bi") (V32SF "v32bi") (V64SF "v64bi")
2016 (V128SF "v128bi") (V256SF "v256bi") (V512SF "v512bi") (V1024SF "v1024bi")
2017 (V1DF "v1bi") (V2DF "v2bi") (V4DF "v4bi") (V8DF "v8bi") (V16DF "v16bi") (V32DF "v32bi")
2018 (V64DF "v64bi") (V128DF "v128bi") (V256DF "v256bi") (V512DF "v512bi")
2021 (define_mode_attr VEL [
2022 (RVVM8QI "QI") (RVVM4QI "QI") (RVVM2QI "QI") (RVVM1QI "QI") (RVVMF2QI "QI") (RVVMF4QI "QI") (RVVMF8QI "QI")
2024 (RVVM8HI "HI") (RVVM4HI "HI") (RVVM2HI "HI") (RVVM1HI "HI") (RVVMF2HI "HI") (RVVMF4HI "HI")
2026 (RVVM8HF "HF") (RVVM4HF "HF") (RVVM2HF "HF") (RVVM1HF "HF") (RVVMF2HF "HF") (RVVMF4HF "HF")
2028 (RVVM8SI "SI") (RVVM4SI "SI") (RVVM2SI "SI") (RVVM1SI "SI") (RVVMF2SI "SI")
2030 (RVVM8SF "SF") (RVVM4SF "SF") (RVVM2SF "SF") (RVVM1SF "SF") (RVVMF2SF "SF")
2032 (RVVM8DI "DI") (RVVM4DI "DI") (RVVM2DI "DI") (RVVM1DI "DI")
2034 (RVVM8DF "DF") (RVVM4DF "DF") (RVVM2DF "DF") (RVVM1DF "DF")
2037 (V1QI "QI") (V2QI "QI") (V4QI "QI") (V8QI "QI") (V16QI "QI") (V32QI "QI") (V64QI "QI") (V128QI "QI") (V256QI "QI") (V512QI "QI")
2038 (V1024QI "QI") (V2048QI "QI") (V4096QI "QI")
2039 (V1HI "HI") (V2HI "HI") (V4HI "HI") (V8HI "HI") (V16HI "HI") (V32HI "HI") (V64HI "HI") (V128HI "HI") (V256HI "HI")
2040 (V512HI "HI") (V1024HI "HI") (V2048HI "HI")
2041 (V1SI "SI") (V2SI "SI") (V4SI "SI") (V8SI "SI") (V16SI "SI") (V32SI "SI") (V64SI "SI") (V128SI "SI") (V256SI "SI")
2042 (V512SI "SI") (V1024SI "SI")
2043 (V1DI "DI") (V2DI "DI") (V4DI "DI") (V8DI "DI") (V16DI "DI") (V32DI "DI") (V64DI "DI") (V128DI "DI") (V256DI "DI") (V512DI "DI")
2044 (V1HF "HF") (V2HF "HF") (V4HF "HF") (V8HF "HF") (V16HF "HF") (V32HF "HF") (V64HF "HF") (V128HF "HF") (V256HF "HF")
2045 (V512HF "HF") (V1024HF "HF") (V2048HF "HF")
2046 (V1SF "SF") (V2SF "SF") (V4SF "SF") (V8SF "SF") (V16SF "SF") (V32SF "SF") (V64SF "SF") (V128SF "SF") (V256SF "SF")
2047 (V512SF "SF") (V1024SF "SF")
2048 (V1DF "DF") (V2DF "DF") (V4DF "DF") (V8DF "DF") (V16DF "DF") (V32DF "DF") (V64DF "DF") (V128DF "DF") (V256DF "DF") (V512DF "DF")
2051 (define_mode_attr V_DOUBLE_EXTEND_VEL [
2052 (RVVM4QI "HI") (RVVM2QI "HI") (RVVM1QI "HI") (RVVMF2QI "HI") (RVVMF4QI "HI") (RVVMF8QI "HI")
2054 (RVVM4HI "SI") (RVVM2HI "SI") (RVVM1HI "SI") (RVVMF2HI "SI") (RVVMF4HI "SI")
2056 (RVVM4SI "DI") (RVVM2SI "DI") (RVVM1SI "DI") (RVVMF2SI "DI")
2058 (RVVM4HF "SF") (RVVM2HF "SF") (RVVM1HF "SF") (RVVMF2HF "SF") (RVVMF4HF "SF")
2060 (RVVM4SF "DF") (RVVM2SF "DF") (RVVM1SF "DF") (RVVMF2SF "DF")
2118 (define_mode_attr vel [
2119 (RVVM8QI "qi") (RVVM4QI "qi") (RVVM2QI "qi") (RVVM1QI "qi") (RVVMF2QI "qi") (RVVMF4QI "qi") (RVVMF8QI "qi")
2121 (RVVM8HI "hi") (RVVM4HI "hi") (RVVM2HI "hi") (RVVM1HI "hi") (RVVMF2HI "hi") (RVVMF4HI "hi")
2123 (RVVM8HF "hf") (RVVM4HF "hf") (RVVM2HF "hf") (RVVM1HF "hf") (RVVMF2HF "hf") (RVVMF4HF "hf")
2125 (RVVM8SI "si") (RVVM4SI "si") (RVVM2SI "si") (RVVM1SI "si") (RVVMF2SI "si")
2127 (RVVM8SF "sf") (RVVM4SF "sf") (RVVM2SF "sf") (RVVM1SF "sf") (RVVMF2SF "sf")
2129 (RVVM8DI "di") (RVVM4DI "di") (RVVM2DI "di") (RVVM1DI "di")
2131 (RVVM8DF "df") (RVVM4DF "df") (RVVM2DF "df") (RVVM1DF "df")
2134 (V1QI "qi") (V2QI "qi") (V4QI "qi") (V8QI "qi") (V16QI "qi") (V32QI "qi") (V64QI "qi") (V128QI "qi") (V256QI "qi") (V512QI "qi")
2135 (V1024QI "qi") (V2048QI "qi") (V4096QI "qi")
2136 (V1HI "hi") (V2HI "hi") (V4HI "hi") (V8HI "hi") (V16HI "hi") (V32HI "hi") (V64HI "hi") (V128HI "hi") (V256HI "hi")
2137 (V512HI "hi") (V1024HI "hi") (V2048HI "hi")
2138 (V1SI "si") (V2SI "si") (V4SI "si") (V8SI "si") (V16SI "si") (V32SI "si") (V64SI "si") (V128SI "si") (V256SI "si")
2139 (V512SI "si") (V1024SI "si")
2140 (V1DI "di") (V2DI "di") (V4DI "di") (V8DI "di") (V16DI "di") (V32DI "di") (V64DI "di") (V128DI "di") (V256DI "di") (V512DI "di")
2141 (V1HF "hf") (V2HF "hf") (V4HF "hf") (V8HF "hf") (V16HF "hf") (V32HF "hf") (V64HF "hf") (V128HF "hf") (V256HF "hf")
2142 (V512HF "hf") (V1024HF "hf") (V2048HF "hf")
2143 (V1SF "sf") (V2SF "sf") (V4SF "sf") (V8SF "sf") (V16SF "sf") (V32SF "sf") (V64SF "sf") (V128SF "sf") (V256SF "sf")
2144 (V512SF "sf") (V1024SF "sf")
2145 (V1DF "df") (V2DF "df") (V4DF "df") (V8DF "df") (V16DF "df") (V32DF "df") (V64DF "df") (V128DF "df") (V256DF "df") (V512DF "df")
2148 (define_mode_attr vsingle [
2149 (RVVM1x8QI "rvvm1qi") (RVVMF2x8QI "rvvmf2qi") (RVVMF4x8QI "rvvmf4qi") (RVVMF8x8QI "rvvmf8qi")
2150 (RVVM1x7QI "rvvm1qi") (RVVMF2x7QI "rvvmf2qi") (RVVMF4x7QI "rvvmf4qi") (RVVMF8x7QI "rvvmf8qi")
2151 (RVVM1x6QI "rvvm1qi") (RVVMF2x6QI "rvvmf2qi") (RVVMF4x6QI "rvvmf4qi") (RVVMF8x6QI "rvvmf8qi")
2152 (RVVM1x5QI "rvvm1qi") (RVVMF2x5QI "rvvmf2qi") (RVVMF4x5QI "rvvmf4qi") (RVVMF8x5QI "rvvmf8qi")
2153 (RVVM2x4QI "rvvm2qi") (RVVM1x4QI "rvvm1qi") (RVVMF2x4QI "rvvmf2qi") (RVVMF4x4QI "rvvmf4qi") (RVVMF8x4QI "rvvmf8qi")
2154 (RVVM2x3QI "rvvm2qi") (RVVM1x3QI "rvvm1qi") (RVVMF2x3QI "rvvmf2qi") (RVVMF4x3QI "rvvmf4qi") (RVVMF8x3QI "rvvmf8qi")
2155 (RVVM4x2QI "rvvm4qi") (RVVM2x2QI "rvvm2qi") (RVVM1x2QI "rvvm1qi") (RVVMF2x2QI "rvvmf2qi") (RVVMF4x2QI "rvvmf4qi") (RVVMF8x2QI "rvvmf8qi")
2157 (RVVM1x8HI "rvvm1hi") (RVVMF2x8HI "rvvmf2hi") (RVVMF4x8HI "rvvmf4hi")
2158 (RVVM1x7HI "rvvm1hi") (RVVMF2x7HI "rvvmf2hi") (RVVMF4x7HI "rvvmf4hi")
2159 (RVVM1x6HI "rvvm1hi") (RVVMF2x6HI "rvvmf2hi") (RVVMF4x6HI "rvvmf4hi")
2160 (RVVM1x5HI "rvvm1hi") (RVVMF2x5HI "rvvmf2hi") (RVVMF4x5HI "rvvmf4hi")
2161 (RVVM2x4HI "rvvm2hi") (RVVM1x4HI "rvvm1hi") (RVVMF2x4HI "rvvmf2hi") (RVVMF4x4HI "rvvmf4hi")
2162 (RVVM2x3HI "rvvm2hi") (RVVM1x3HI "rvvm1hi") (RVVMF2x3HI "rvvmf2hi") (RVVMF4x3HI "rvvmf4hi")
2163 (RVVM4x2HI "rvvm4hi") (RVVM2x2HI "rvvm2hi") (RVVM1x2HI "rvvm1hi") (RVVMF2x2HI "rvvmf2hi") (RVVMF4x2HI "rvvmf4hi")
2165 (RVVM1x8HF "rvvm1hf")
2166 (RVVMF2x8HF "rvvmf2hf")
2167 (RVVMF4x8HF "rvvmf4hf")
2168 (RVVM1x7HF "rvvm1hf")
2169 (RVVMF2x7HF "rvvmf2hf")
2170 (RVVMF4x7HF "rvvmf4hf")
2171 (RVVM1x6HF "rvvm1hf")
2172 (RVVMF2x6HF "rvvmf2hf")
2173 (RVVMF4x6HF "rvvmf4hf")
2174 (RVVM1x5HF "rvvm1hf")
2175 (RVVMF2x5HF "rvvmf2hf")
2176 (RVVMF4x5HF "rvvmf4hf")
2177 (RVVM2x4HF "rvvm2hf")
2178 (RVVM1x4HF "rvvm1hf")
2179 (RVVMF2x4HF "rvvmf2hf")
2180 (RVVMF4x4HF "rvvmf4hf")
2181 (RVVM2x3HF "rvvm2hf")
2182 (RVVM1x3HF "rvvm1hf")
2183 (RVVMF2x3HF "rvvmf2hf")
2184 (RVVMF4x3HF "rvvmf4hf")
2185 (RVVM4x2HF "rvvm4hf")
2186 (RVVM2x2HF "rvvm2hf")
2187 (RVVM1x2HF "rvvm1hf")
2188 (RVVMF2x2HF "rvvmf2hf")
2189 (RVVMF4x2HF "rvvmf4hf")
2191 (RVVM1x8SI "rvvm1si") (RVVMF2x8SI "rvvmf2si")
2192 (RVVM1x7SI "rvvm1si") (RVVMF2x7SI "rvvmf2si")
2193 (RVVM1x6SI "rvvm1si") (RVVMF2x6SI "rvvmf2si")
2194 (RVVM1x5SI "rvvm1si") (RVVMF2x5SI "rvvmf2si")
2195 (RVVM2x4SI "rvvm2si") (RVVM1x4SI "rvvm1si") (RVVMF2x4SI "rvvmf2si")
2196 (RVVM2x3SI "rvvm2si") (RVVM1x3SI "rvvm1si") (RVVMF2x3SI "rvvmf2si")
2197 (RVVM4x2SI "rvvm4si") (RVVM2x2SI "rvvm2si") (RVVM1x2SI "rvvm1si") (RVVMF2x2SI "rvvmf2si")
2199 (RVVM1x8SF "rvvm1sf")
2200 (RVVMF2x8SF "rvvmf2sf")
2201 (RVVM1x7SF "rvvm1sf")
2202 (RVVMF2x7SF "rvvmf2sf")
2203 (RVVM1x6SF "rvvm1sf")
2204 (RVVMF2x6SF "rvvmf2sf")
2205 (RVVM1x5SF "rvvm1sf")
2206 (RVVMF2x5SF "rvvmf2sf")
2207 (RVVM2x4SF "rvvm2sf")
2208 (RVVM1x4SF "rvvm1sf")
2209 (RVVMF2x4SF "rvvmf2sf")
2210 (RVVM2x3SF "rvvm2sf")
2211 (RVVM1x3SF "rvvm1sf")
2212 (RVVMF2x3SF "rvvmf2sf")
2213 (RVVM4x2SF "rvvm4sf")
2214 (RVVM2x2SF "rvvm2sf")
2215 (RVVM1x2SF "rvvm1sf")
2216 (RVVMF2x2SF "rvvmf2sf")
2218 (RVVM1x8DI "rvvm1di")
2219 (RVVM1x7DI "rvvm1di")
2220 (RVVM1x6DI "rvvm1di")
2221 (RVVM1x5DI "rvvm1di")
2222 (RVVM2x4DI "rvvm2di")
2223 (RVVM1x4DI "rvvm1di")
2224 (RVVM2x3DI "rvvm2di")
2225 (RVVM1x3DI "rvvm1di")
2226 (RVVM4x2DI "rvvm4di")
2227 (RVVM2x2DI "rvvm2di")
2228 (RVVM1x2DI "rvvm1di")
2230 (RVVM1x8DF "rvvm1df")
2231 (RVVM1x7DF "rvvm1df")
2232 (RVVM1x6DF "rvvm1df")
2233 (RVVM1x5DF "rvvm1df")
2234 (RVVM2x4DF "rvvm2df")
2235 (RVVM1x4DF "rvvm1df")
2236 (RVVM2x3DF "rvvm2df")
2237 (RVVM1x3DF "rvvm1df")
2238 (RVVM4x2DF "rvvm4df")
2239 (RVVM2x2DF "rvvm2df")
2240 (RVVM1x2DF "rvvm1df")
2243 (define_mode_attr VSUBEL [
2244 (RVVM8HI "QI") (RVVM4HI "QI") (RVVM2HI "QI") (RVVM1HI "QI") (RVVMF2HI "QI") (RVVMF4HI "QI")
2246 (RVVM8SI "HI") (RVVM4SI "HI") (RVVM2SI "HI") (RVVM1SI "HI") (RVVMF2SI "HI")
2248 (RVVM8SF "HF") (RVVM4SF "HF") (RVVM2SF "HF") (RVVM1SF "HF") (RVVMF2SF "HF")
2250 (RVVM8DI "SI") (RVVM4DI "SI") (RVVM2DI "SI") (RVVM1DI "SI")
2252 (RVVM8DF "SF") (RVVM4DF "SF") (RVVM2DF "SF") (RVVM1DF "SF")
2255 (V1HI "QI") (V2HI "QI") (V4HI "QI") (V8HI "QI") (V16HI "QI") (V32HI "QI") (V64HI "QI") (V128HI "QI") (V256HI "QI")
2256 (V512HI "QI") (V1024HI "QI") (V2048HI "QI")
2257 (V1SI "HI") (V2SI "HI") (V4SI "HI") (V8SI "HI") (V16SI "HI") (V32SI "HI") (V64SI "HI") (V128SI "HI") (V256SI "HI")
2258 (V512SI "HI") (V1024SI "HI")
2259 (V1DI "SI") (V2DI "SI") (V4DI "SI") (V8DI "SI") (V16DI "SI") (V32DI "SI") (V64DI "SI") (V128DI "SI") (V256DI "SI") (V512DI "SI")
2284 (define_mode_attr nf [
2285 (RVVM1x8QI "8") (RVVMF2x8QI "8") (RVVMF4x8QI "8") (RVVMF8x8QI "8")
2286 (RVVM1x7QI "7") (RVVMF2x7QI "7") (RVVMF4x7QI "7") (RVVMF8x7QI "7")
2287 (RVVM1x6QI "6") (RVVMF2x6QI "6") (RVVMF4x6QI "6") (RVVMF8x6QI "6")
2288 (RVVM1x5QI "5") (RVVMF2x5QI "5") (RVVMF4x5QI "5") (RVVMF8x5QI "5")
2289 (RVVM2x4QI "4") (RVVM1x4QI "4") (RVVMF2x4QI "4") (RVVMF4x4QI "4") (RVVMF8x4QI "4")
2290 (RVVM2x3QI "3") (RVVM1x3QI "3") (RVVMF2x3QI "3") (RVVMF4x3QI "3") (RVVMF8x3QI "3")
2291 (RVVM4x2QI "2") (RVVM2x2QI "2") (RVVM1x2QI "2") (RVVMF2x2QI "2") (RVVMF4x2QI "2") (RVVMF8x2QI "2")
2293 (RVVM1x8HI "8") (RVVMF2x8HI "8") (RVVMF4x8HI "8")
2294 (RVVM1x7HI "7") (RVVMF2x7HI "7") (RVVMF4x7HI "7")
2295 (RVVM1x6HI "6") (RVVMF2x6HI "6") (RVVMF4x6HI "6")
2296 (RVVM1x5HI "5") (RVVMF2x5HI "5") (RVVMF4x5HI "5")
2297 (RVVM2x4HI "4") (RVVM1x4HI "4") (RVVMF2x4HI "4") (RVVMF4x4HI "4")
2298 (RVVM2x3HI "3") (RVVM1x3HI "3") (RVVMF2x3HI "3") (RVVMF4x3HI "3")
2299 (RVVM4x2HI "2") (RVVM2x2HI "2") (RVVM1x2HI "2") (RVVMF2x2HI "2") (RVVMF4x2HI "2")
2301 (RVVM1x8HF "8") (RVVMF2x8HF "8") (RVVMF4x8HF "8")
2302 (RVVM1x7HF "7") (RVVMF2x7HF "7") (RVVMF4x7HF "7")
2303 (RVVM1x6HF "6") (RVVMF2x6HF "6") (RVVMF4x6HF "6")
2304 (RVVM1x5HF "5") (RVVMF2x5HF "5") (RVVMF4x5HF "5")
2305 (RVVM2x4HF "4") (RVVM1x4HF "4") (RVVMF2x4HF "4") (RVVMF4x4HF "4")
2306 (RVVM2x3HF "3") (RVVM1x3HF "3") (RVVMF2x3HF "3") (RVVMF4x3HF "3")
2307 (RVVM4x2HF "2") (RVVM2x2HF "2") (RVVM1x2HF "2") (RVVMF2x2HF "2") (RVVMF4x2HF "2")
2309 (RVVM1x8SI "8") (RVVMF2x8SI "8")
2310 (RVVM1x7SI "7") (RVVMF2x7SI "7")
2311 (RVVM1x6SI "6") (RVVMF2x6SI "6")
2312 (RVVM1x5SI "5") (RVVMF2x5SI "5")
2313 (RVVM2x4SI "4") (RVVM1x4SI "4") (RVVMF2x4SI "4")
2314 (RVVM2x3SI "3") (RVVM1x3SI "3") (RVVMF2x3SI "3")
2315 (RVVM4x2SI "2") (RVVM2x2SI "2") (RVVM1x2SI "2") (RVVMF2x2SI "2")
2317 (RVVM1x8SF "8") (RVVMF2x8SF "8")
2318 (RVVM1x7SF "7") (RVVMF2x7SF "7")
2319 (RVVM1x6SF "6") (RVVMF2x6SF "6")
2320 (RVVM1x5SF "5") (RVVMF2x5SF "5")
2321 (RVVM2x4SF "4") (RVVM1x4SF "4") (RVVMF2x4SF "4")
2322 (RVVM2x3SF "3") (RVVM1x3SF "3") (RVVMF2x3SF "3")
2323 (RVVM4x2SF "2") (RVVM2x2SF "2") (RVVM1x2SF "2") (RVVMF2x2SF "2")
2350 (define_mode_attr sew [
2351 (RVVM8QI "8") (RVVM4QI "8") (RVVM2QI "8") (RVVM1QI "8") (RVVMF2QI "8") (RVVMF4QI "8") (RVVMF8QI "8")
2353 (RVVM8HI "16") (RVVM4HI "16") (RVVM2HI "16") (RVVM1HI "16") (RVVMF2HI "16") (RVVMF4HI "16")
2355 (RVVM8HF "16") (RVVM4HF "16") (RVVM2HF "16") (RVVM1HF "16") (RVVMF2HF "16") (RVVMF4HF "16")
2357 (RVVM8SI "32") (RVVM4SI "32") (RVVM2SI "32") (RVVM1SI "32") (RVVMF2SI "32")
2359 (RVVM8SF "32") (RVVM4SF "32") (RVVM2SF "32") (RVVM1SF "32") (RVVMF2SF "32")
2361 (RVVM8DI "64") (RVVM4DI "64") (RVVM2DI "64") (RVVM1DI "64")
2363 (RVVM8DF "64") (RVVM4DF "64") (RVVM2DF "64") (RVVM1DF "64")
2365 (RVVM1x8QI "8") (RVVMF2x8QI "8") (RVVMF4x8QI "8") (RVVMF8x8QI "8")
2366 (RVVM1x7QI "8") (RVVMF2x7QI "8") (RVVMF4x7QI "8") (RVVMF8x7QI "8")
2367 (RVVM1x6QI "8") (RVVMF2x6QI "8") (RVVMF4x6QI "8") (RVVMF8x6QI "8")
2368 (RVVM1x5QI "8") (RVVMF2x5QI "8") (RVVMF4x5QI "8") (RVVMF8x5QI "8")
2369 (RVVM2x4QI "8") (RVVM1x4QI "8") (RVVMF2x4QI "8") (RVVMF4x4QI "8") (RVVMF8x4QI "8")
2370 (RVVM2x3QI "8") (RVVM1x3QI "8") (RVVMF2x3QI "8") (RVVMF4x3QI "8") (RVVMF8x3QI "8")
2371 (RVVM4x2QI "8") (RVVM2x2QI "8") (RVVM1x2QI "8") (RVVMF2x2QI "8") (RVVMF4x2QI "8") (RVVMF8x2QI "8")
2373 (RVVM1x8HI "16") (RVVMF2x8HI "16") (RVVMF4x8HI "16")
2374 (RVVM1x7HI "16") (RVVMF2x7HI "16") (RVVMF4x7HI "16")
2375 (RVVM1x6HI "16") (RVVMF2x6HI "16") (RVVMF4x6HI "16")
2376 (RVVM1x5HI "16") (RVVMF2x5HI "16") (RVVMF4x5HI "16")
2377 (RVVM2x4HI "16") (RVVM1x4HI "16") (RVVMF2x4HI "16") (RVVMF4x4HI "16")
2378 (RVVM2x3HI "16") (RVVM1x3HI "16") (RVVMF2x3HI "16") (RVVMF4x3HI "16")
2379 (RVVM4x2HI "16") (RVVM2x2HI "16") (RVVM1x2HI "16") (RVVMF2x2HI "16") (RVVMF4x2HI "16")
2381 (RVVM1x8HF "16") (RVVMF2x8HF "16") (RVVMF4x8HF "16")
2382 (RVVM1x7HF "16") (RVVMF2x7HF "16") (RVVMF4x7HF "16")
2383 (RVVM1x6HF "16") (RVVMF2x6HF "16") (RVVMF4x6HF "16")
2384 (RVVM1x5HF "16") (RVVMF2x5HF "16") (RVVMF4x5HF "16")
2385 (RVVM2x4HF "16") (RVVM1x4HF "16") (RVVMF2x4HF "16") (RVVMF4x4HF "16")
2386 (RVVM2x3HF "16") (RVVM1x3HF "16") (RVVMF2x3HF "16") (RVVMF4x3HF "16")
2387 (RVVM4x2HF "16") (RVVM2x2HF "16") (RVVM1x2HF "16") (RVVMF2x2HF "16") (RVVMF4x2HF "16")
2389 (RVVM1x8SI "32") (RVVMF2x8SI "32")
2390 (RVVM1x7SI "32") (RVVMF2x7SI "32")
2391 (RVVM1x6SI "32") (RVVMF2x6SI "32")
2392 (RVVM1x5SI "32") (RVVMF2x5SI "32")
2393 (RVVM2x4SI "32") (RVVM1x4SI "32") (RVVMF2x4SI "32")
2394 (RVVM2x3SI "32") (RVVM1x3SI "32") (RVVMF2x3SI "32")
2395 (RVVM4x2SI "32") (RVVM2x2SI "32") (RVVM1x2SI "32") (RVVMF2x2SI "32")
2397 (RVVM1x8SF "32") (RVVMF2x8SF "32")
2398 (RVVM1x7SF "32") (RVVMF2x7SF "32")
2399 (RVVM1x6SF "32") (RVVMF2x6SF "32")
2400 (RVVM1x5SF "32") (RVVMF2x5SF "32")
2401 (RVVM2x4SF "32") (RVVM1x4SF "32") (RVVMF2x4SF "32")
2402 (RVVM2x3SF "32") (RVVM1x3SF "32") (RVVMF2x3SF "32")
2403 (RVVM4x2SF "32") (RVVM2x2SF "32") (RVVM1x2SF "32") (RVVMF2x2SF "32")
2430 (V1QI "8") (V2QI "8") (V4QI "8") (V8QI "8") (V16QI "8") (V32QI "8") (V64QI "8") (V128QI "8") (V256QI "8") (V512QI "8")
2431 (V1024QI "8") (V2048QI "8") (V4096QI "8")
2432 (V1HI "16") (V2HI "16") (V4HI "16") (V8HI "16") (V16HI "16") (V32HI "16") (V64HI "16") (V128HI "16") (V256HI "16")
2433 (V512HI "16") (V1024HI "16") (V2048HI "16")
2434 (V1SI "32") (V2SI "32") (V4SI "32") (V8SI "32") (V16SI "32") (V32SI "32") (V64SI "32") (V128SI "32") (V256SI "32")
2435 (V512SI "32") (V1024SI "32")
2436 (V1DI "64") (V2DI "64") (V4DI "64") (V8DI "64") (V16DI "64") (V32DI "64") (V64DI "64") (V128DI "64") (V256DI "64") (V512DI "64")
2437 (V1HF "16") (V2HF "16") (V4HF "16") (V8HF "16") (V16HF "16") (V32HF "16") (V64HF "16") (V128HF "16") (V256HF "16")
2438 (V512HF "16") (V1024HF "16") (V2048HF "16")
2439 (V1SF "32") (V2SF "32") (V4SF "32") (V8SF "32") (V16SF "32") (V32SF "32") (V64SF "32") (V128SF "32") (V256SF "32")
2440 (V512SF "32") (V1024SF "32")
2441 (V1DF "64") (V2DF "64") (V4DF "64") (V8DF "64") (V16DF "64") (V32DF "64") (V64DF "64") (V128DF "64") (V256DF "64") (V512DF "64")
2444 (define_mode_attr double_trunc_sew [
2445 (RVVM8HI "8") (RVVM4HI "8") (RVVM2HI "8") (RVVM1HI "8") (RVVMF2HI "8") (RVVMF4HI "8")
2447 (RVVM8HF "8") (RVVM4HF "8") (RVVM2HF "8") (RVVM1HF "8") (RVVMF2HF "8") (RVVMF4HF "8")
2449 (RVVM8SI "16") (RVVM4SI "16") (RVVM2SI "16") (RVVM1SI "16") (RVVMF2SI "16")
2451 (RVVM8SF "16") (RVVM4SF "16") (RVVM2SF "16") (RVVM1SF "16") (RVVMF2SF "16")
2453 (RVVM8DI "32") (RVVM4DI "32") (RVVM2DI "32") (RVVM1DI "32")
2455 (RVVM8DF "32") (RVVM4DF "32") (RVVM2DF "32") (RVVM1DF "32")
2458 (define_mode_attr quad_trunc_sew [
2459 (RVVM8SI "8") (RVVM4SI "8") (RVVM2SI "8") (RVVM1SI "8") (RVVMF2SI "8")
2461 (RVVM8SF "8") (RVVM4SF "8") (RVVM2SF "8") (RVVM1SF "8") (RVVMF2SF "8")
2463 (RVVM8DI "16") (RVVM4DI "16") (RVVM2DI "16") (RVVM1DI "16")
2465 (RVVM8DF "16") (RVVM4DF "16") (RVVM2DF "16") (RVVM1DF "16")
2468 (define_mode_attr oct_trunc_sew [
2469 (RVVM8DI "8") (RVVM4DI "8") (RVVM2DI "8") (RVVM1DI "8")
2471 (RVVM8DF "8") (RVVM4DF "8") (RVVM2DF "8") (RVVM1DF "8")
2474 (define_mode_attr double_ext_sew [
2475 (RVVM4QI "16") (RVVM2QI "16") (RVVM1QI "16") (RVVMF2QI "16") (RVVMF4QI "16") (RVVMF8QI "16")
2477 (RVVM4HI "32") (RVVM2HI "32") (RVVM1HI "32") (RVVMF2HI "32") (RVVMF4HI "32")
2479 (RVVM4HF "32") (RVVM2HF "32") (RVVM1HF "32") (RVVMF2HF "32") (RVVMF4HF "32")
2481 (RVVM4SI "64") (RVVM2SI "64") (RVVM1SI "64") (RVVMF2SI "64")
2483 (RVVM4SF "64") (RVVM2SF "64") (RVVM1SF "64") (RVVMF2SF "64")
2486 (define_mode_attr quad_ext_sew [
2487 (RVVM2QI "32") (RVVM1QI "32") (RVVMF2QI "32") (RVVMF4QI "32") (RVVMF8QI "32")
2489 (RVVM2HI "64") (RVVM1HI "64") (RVVMF2HI "64") (RVVMF4HI "64")
2491 (RVVM2HF "64") (RVVM1HF "64") (RVVMF2HF "64") (RVVMF4HF "64")
2494 (define_mode_attr oct_ext_sew [
2495 (RVVM1QI "64") (RVVMF2QI "64") (RVVMF4QI "64") (RVVMF8QI "64")
2498 (define_mode_attr V_DOUBLE_EXTEND [
2499 (RVVM4QI "RVVM8HI") (RVVM2QI "RVVM4HI") (RVVM1QI "RVVM2HI") (RVVMF2QI "RVVM1HI") (RVVMF4QI "RVVMF2HI") (RVVMF8QI "RVVMF4HI")
2501 (RVVM4HI "RVVM8SI") (RVVM2HI "RVVM4SI") (RVVM1HI "RVVM2SI") (RVVMF2HI "RVVM1SI") (RVVMF4HI "RVVMF2SI")
2503 (RVVM4SI "RVVM8DI") (RVVM2SI "RVVM4DI") (RVVM1SI "RVVM2DI") (RVVMF2SI "RVVM1DI")
2505 (RVVM4HF "RVVM8SF") (RVVM2HF "RVVM4SF") (RVVM1HF "RVVM2SF") (RVVMF2HF "RVVM1SF") (RVVMF4HF "RVVMF2SF")
2507 (RVVM4SF "RVVM8DF") (RVVM2SF "RVVM4DF") (RVVM1SF "RVVM2DF") (RVVMF2SF "RVVM1DF")
2565 (define_mode_attr V_DOUBLE_TRUNC [
2566 (RVVM8HI "RVVM4QI") (RVVM4HI "RVVM2QI") (RVVM2HI "RVVM1QI") (RVVM1HI "RVVMF2QI") (RVVMF2HI "RVVMF4QI") (RVVMF4HI "RVVMF8QI")
2568 (RVVM8SI "RVVM4HI") (RVVM4SI "RVVM2HI") (RVVM2SI "RVVM1HI") (RVVM1SI "RVVMF2HI") (RVVMF2SI "RVVMF4HI")
2570 (RVVM8SF "RVVM4HF") (RVVM4SF "RVVM2HF") (RVVM2SF "RVVM1HF") (RVVM1SF "RVVMF2HF") (RVVMF2SF "RVVMF4HF")
2572 (RVVM8DI "RVVM4SI") (RVVM4DI "RVVM2SI") (RVVM2DI "RVVM1SI") (RVVM1DI "RVVMF2SI")
2574 (RVVM8DF "RVVM4SF") (RVVM4DF "RVVM2SF") (RVVM2DF "RVVM1SF") (RVVM1DF "RVVMF2SF")
2632 (define_mode_attr V_QUAD_TRUNC [
2633 (RVVM8SI "RVVM2QI") (RVVM4SI "RVVM1QI") (RVVM2SI "RVVMF2QI") (RVVM1SI "RVVMF4QI") (RVVMF2SI "RVVMF8QI")
2635 (RVVM8DI "RVVM2HI") (RVVM4DI "RVVM1HI") (RVVM2DI "RVVMF2HI") (RVVM1DI "RVVMF4HI")
2637 (RVVM8DF "RVVM2HF") (RVVM4DF "RVVM1HF") (RVVM2DF "RVVMF2HF") (RVVM1DF "RVVMF4HF")
2672 (define_mode_attr V_OCT_TRUNC [
2673 (RVVM8DI "RVVM1QI") (RVVM4DI "RVVMF2QI") (RVVM2DI "RVVMF4QI") (RVVM1DI "RVVMF8QI")
2687 ; Again in lower case.
2688 (define_mode_attr v_double_trunc [
2689 (RVVM8HI "rvvm4qi") (RVVM4HI "rvvm2qi") (RVVM2HI "rvvm1qi") (RVVM1HI "rvvmf2qi") (RVVMF2HI "rvvmf4qi") (RVVMF4HI "rvvmf8qi")
2691 (RVVM8SI "rvvm4hi") (RVVM4SI "rvvm2hi") (RVVM2SI "rvvm1hi") (RVVM1SI "rvvmf2hi") (RVVMF2SI "rvvmf4hi")
2693 (RVVM8SF "rvvm4hf") (RVVM4SF "rvvm2hf") (RVVM2SF "rvvm1hf") (RVVM1SF "rvvmf2hf") (RVVMF2SF "rvvmf4hf")
2695 (RVVM8DI "rvvm4si") (RVVM4DI "rvvm2si") (RVVM2DI "rvvm1si") (RVVM1DI "rvvmf2si")
2697 (RVVM8DF "rvvm4sf") (RVVM4DF "rvvm2sf") (RVVM2DF "rvvm1sf") (RVVM1DF "rvvmf2sf")
2755 (define_mode_attr v_quad_trunc [
2756 (RVVM8SI "rvvm2qi") (RVVM4SI "rvvm1qi") (RVVM2SI "rvvmf2qi") (RVVM1SI "rvvmf4qi") (RVVMF2SI "rvvmf8qi")
2758 (RVVM8DI "rvvm2hi") (RVVM4DI "rvvm1hi") (RVVM2DI "rvvmf2hi") (RVVM1DI "rvvmf4hi")
2760 (RVVM8DF "rvvm2hf") (RVVM4DF "rvvm1hf") (RVVM2DF "rvvmf2hf") (RVVM1DF "rvvmf4hf")
2795 (define_mode_attr v_oct_trunc [
2796 (RVVM8DI "rvvm1qi") (RVVM4DI "rvvmf2qi") (RVVM2DI "rvvmf4qi") (RVVM1DI "rvvmf8qi")
2810 (define_mode_attr VINDEX_DOUBLE_TRUNC [
2811 (RVVM8HI "RVVM4QI") (RVVM4HI "RVVM2QI") (RVVM2HI "RVVM1QI") (RVVM1HI "RVVMF2QI") (RVVMF2HI "RVVMF4QI") (RVVMF4HI "RVVMF8QI")
2813 (RVVM8HF "RVVM4QI") (RVVM4HF "RVVM2QI") (RVVM2HF "RVVM1QI") (RVVM1HF "RVVMF2QI") (RVVMF2HF "RVVMF4QI") (RVVMF4HF "RVVMF8QI")
2815 (RVVM8SI "RVVM4HI") (RVVM4SI "RVVM2HI") (RVVM2SI "RVVM1HI") (RVVM1SI "RVVMF2HI") (RVVMF2SI "RVVMF4HI")
2817 (RVVM8SF "RVVM4HI") (RVVM4SF "RVVM2HI") (RVVM2SF "RVVM1HI") (RVVM1SF "RVVMF2HI") (RVVMF2SF "RVVMF4HI")
2819 (RVVM8DI "RVVM4SI") (RVVM4DI "RVVM2SI") (RVVM2DI "RVVM1SI") (RVVM1DI "RVVMF2SI")
2821 (RVVM8DF "RVVM4SI") (RVVM4DF "RVVM2SI") (RVVM2DF "RVVM1SI") (RVVM1DF "RVVMF2SI")
2824 (define_mode_attr VINDEX_QUAD_TRUNC [
2825 (RVVM8SI "RVVM2QI") (RVVM4SI "RVVM1QI") (RVVM2SI "RVVMF2QI") (RVVM1SI "RVVMF4QI") (RVVMF2SI "RVVMF8QI")
2827 (RVVM8SF "RVVM2QI") (RVVM4SF "RVVM1QI") (RVVM2SF "RVVMF2QI") (RVVM1SF "RVVMF4QI") (RVVMF2SF "RVVMF8QI")
2829 (RVVM8DI "RVVM2HI") (RVVM4DI "RVVM1HI") (RVVM2DI "RVVMF2HI") (RVVM1DI "RVVMF4HI")
2831 (RVVM8DF "RVVM2HI") (RVVM4DF "RVVM1HI") (RVVM2DF "RVVMF2HI") (RVVM1DF "RVVMF4HI")
2834 (define_mode_attr VINDEX_OCT_TRUNC [
2835 (RVVM8DI "RVVM1QI") (RVVM4DI "RVVMF2QI") (RVVM2DI "RVVMF4QI") (RVVM1DI "RVVMF8QI")
2837 (RVVM8DF "RVVM1QI") (RVVM4DF "RVVMF2QI") (RVVM2DF "RVVMF4QI") (RVVM1DF "RVVMF8QI")
2840 (define_mode_attr VINDEX_DOUBLE_EXT [
2841 (RVVM4QI "RVVM8HI") (RVVM2QI "RVVM4HI") (RVVM1QI "RVVM2HI") (RVVMF2QI "RVVM1HI") (RVVMF4QI "RVVMF2HI") (RVVMF8QI "RVVMF4HI")
2843 (RVVM4HI "RVVM8SI") (RVVM2HI "RVVM4SI") (RVVM1HI "RVVM2SI") (RVVMF2HI "RVVM1SI") (RVVMF4HI "RVVMF2SI")
2845 (RVVM4HF "RVVM8SI") (RVVM2HF "RVVM4SI") (RVVM1HF "RVVM2SI") (RVVMF2HF "RVVM1SI") (RVVMF4HF "RVVMF2SI")
2847 (RVVM4SI "RVVM8DI") (RVVM2SI "RVVM4DI") (RVVM1SI "RVVM2DI") (RVVMF2SI "RVVM1DI")
2849 (RVVM4SF "RVVM8DI") (RVVM2SF "RVVM4DI") (RVVM1SF "RVVM2DI") (RVVMF2SF "RVVM1DI")
2852 (define_mode_attr VINDEX_QUAD_EXT [
2853 (RVVM2QI "RVVM8SI") (RVVM1QI "RVVM4SI") (RVVMF2QI "RVVM2SI") (RVVMF4QI "RVVM1SI") (RVVMF8QI "RVVMF2SI")
2855 (RVVM2HI "RVVM8DI") (RVVM1HI "RVVM4DI") (RVVMF2HI "RVVM2DI") (RVVMF4HI "RVVM1DI")
2857 (RVVM2HF "RVVM8DI") (RVVM1HF "RVVM4DI") (RVVMF2HF "RVVM2DI") (RVVMF4HF "RVVM1DI")
2860 (define_mode_attr VINDEX_OCT_EXT [
2861 (RVVM1QI "RVVM8DI") (RVVMF2QI "RVVM4DI") (RVVMF4QI "RVVM2DI") (RVVMF8QI "RVVM1DI")
2864 (define_mode_attr VCONVERT [
2865 (RVVM8HF "RVVM8HI") (RVVM4HF "RVVM4HI") (RVVM2HF "RVVM2HI") (RVVM1HF "RVVM1HI") (RVVMF2HF "RVVMF2HI") (RVVMF4HF "RVVMF4HI")
2866 (RVVM8SF "RVVM8SI") (RVVM4SF "RVVM4SI") (RVVM2SF "RVVM2SI") (RVVM1SF "RVVM1SI") (RVVMF2SF "RVVMF2SI")
2867 (RVVM8DF "RVVM8DI") (RVVM4DF "RVVM4DI") (RVVM2DF "RVVM2DI") (RVVM1DF "RVVM1DI")
2904 (define_mode_attr vconvert [
2905 (RVVM8HF "rvvm8hi") (RVVM4HF "rvvm4hi") (RVVM2HF "rvvm2hi") (RVVM1HF "rvvm1hi") (RVVMF2HF "rvvmf2hi") (RVVMF4HF "rvvmf4hi")
2906 (RVVM8SF "rvvm8si") (RVVM4SF "rvvm4si") (RVVM2SF "rvvm2si") (RVVM1SF "rvvm1si") (RVVMF2SF "rvvmf2si")
2907 (RVVM8DF "rvvm8di") (RVVM4DF "rvvm4di") (RVVM2DF "rvvm2di") (RVVM1DF "rvvm1di")
2944 (define_mode_attr VNCONVERT [
2945 (RVVM8HF "RVVM4QI") (RVVM4HF "RVVM2QI") (RVVM2HF "RVVM1QI") (RVVM1HF "RVVMF2QI") (RVVMF2HF "RVVMF4QI") (RVVMF4HF "RVVMF8QI")
2947 (RVVM8SI "RVVM4HF") (RVVM4SI "RVVM2HF") (RVVM2SI "RVVM1HF") (RVVM1SI "RVVMF2HF") (RVVMF2SI "RVVMF4HF")
2948 (RVVM8SF "RVVM4HI") (RVVM4SF "RVVM2HI") (RVVM2SF "RVVM1HI") (RVVM1SF "RVVMF2HI") (RVVMF2SF "RVVMF4HI")
2950 (RVVM8DI "RVVM4SF") (RVVM4DI "RVVM2SF") (RVVM2DI "RVVM1SF") (RVVM1DI "RVVMF2SF")
2951 (RVVM8DF "RVVM4SI") (RVVM4DF "RVVM2SI") (RVVM2DF "RVVM1SI") (RVVM1DF "RVVMF2SI")
3010 (define_mode_attr vnconvert [
3011 (RVVM8HF "rvvm4qi") (RVVM4HF "rvvm2qi") (RVVM2HF "rvvm1qi") (RVVM1HF "rvvmf2qi") (RVVMF2HF "rvvmf4qi") (RVVMF4HF "rvvmf8qi")
3013 (RVVM8SI "rvvm4hf") (RVVM4SI "rvvm2hf") (RVVM2SI "rvvm1hf") (RVVM1SI "rvvmf2hf") (RVVMF2SI "rvvmf4hf")
3014 (RVVM8SF "rvvm4hi") (RVVM4SF "rvvm2hi") (RVVM2SF "rvvm1hi") (RVVM1SF "rvvmf2hi") (RVVMF2SF "rvvmf4hi")
3016 (RVVM8DI "rvvm4sf") (RVVM4DI "rvvm2sf") (RVVM2DI "rvvm1sf") (RVVM1DI "rvvmf2sf")
3017 (RVVM8DF "rvvm4si") (RVVM4DF "rvvm2si") (RVVM2DF "rvvm1si") (RVVM1DF "rvvmf2si")
3076 ;; NN indicates narrow twice
3077 (define_mode_attr VNNCONVERT [
3078 (RVVM8DI "RVVM2HF") (RVVM4DI "RVVM1HF") (RVVM2DI "RVVMF2HF")
3079 (RVVM1DI "RVVMF4HF")
3081 (V1DI "V1HF") (V2DI "V2HF") (V4DI "V4HF") (V8DI "V8HF") (V16DI "V16HF")
3082 (V32DI "V32HF") (V64DI "V64HF") (V128DI "V128HF") (V256DI "V256HF")
3086 ;; nn indicates narrow twice
3087 (define_mode_attr vnnconvert [
3088 (RVVM8DI "rvvm2hf") (RVVM4DI "rvvm1hf") (RVVM2DI "rvvmf2hf")
3089 (RVVM1DI "rvvmf4hf")
3091 (V1DI "v1hf") (V2DI "v2hf") (V4DI "v4hf") (V8DI "v8hf") (V16DI "v16hf")
3092 (V32DI "v32hf") (V64DI "v64hf") (V128DI "v128hf") (V256DI "v256hf")
3097 ;; Convert float (VHF, VSF, VDF) to VSI/VDI.
3098 ;; The are sorts of rounding mode return integer (take rint as example)
3103 ;; The long type has different bitsize in RV32 and RV64 makes them even
3104 ;; more complicated, details as below.
3105 ;; +------------+------------------+------------------+
3106 ;; | builtin | RV32 | RV64 |
3107 ;; +------------+------------------+------------------+
3108 ;; | lrintf16 | HF => SI | HF => DI |
3109 ;; +------------+------------------+------------------+
3110 ;; | lrintf | SF => SI | SF => DI |
3111 ;; +------------+------------------+------------------+
3112 ;; | lrint | DF => SI | DF => DI |
3113 ;; +------------+------------------+------------------+
3114 ;; | llrintf16 | HF => DI | Same as RV32 |
3115 ;; +------------+------------------+------------------+
3116 ;; | llrintf | SF => DI | Same as RV32 |
3117 ;; +------------+------------------+------------------+
3118 ;; | llrint | DF => DI | Same as RV32 |
3119 ;; +------------+------------------+------------------+
3120 ;; | irintf16 | HF => SI | Same as RV32 |
3121 ;; +------------+------------------+------------------+
3122 ;; | irintf | SF => SI | Same as RV32 |
3123 ;; +------------+------------------+------------------+
3124 ;; | irint | DF => SI | Same as RV32 |
3125 ;; +------------+------------------+------------------+
3127 ;; The [i/l/ll]rint share the same standard name lrint<m><n>,
3128 ;; and both the RV32 and RV64 has the cases to the SI and DI.
3129 ;; For example, both RV32 and RV64 has the below convert:
3131 ;; HF => SI (RV32: lrintf16) (RV64: irintf16)
3132 ;; HF => DI (RV32: llrintf16) (RV64: lrintf16)
3134 ;; Due to we cannot define a mode_attr mapping one HF to both
3135 ;; the SI and DI, we use 2 different mode_atter to cover all
3136 ;; the combination as above, as well as the different iterator
3137 ;; for the lrint<m><n> patterns. Aka:
3139 ;; V_F2SI_CONVERT: (HF, SF, DF) => SI
3140 ;; V_F2DI_CONVERT: (HF, SF, DF) => DI
3142 (define_mode_attr V_F2SI_CONVERT [
3143 (RVVM4HF "RVVM8SI") (RVVM2HF "RVVM4SI") (RVVM1HF "RVVM2SI")
3144 (RVVMF2HF "RVVM1SI") (RVVMF4HF "RVVMF2SI")
3146 (RVVM8SF "RVVM8SI") (RVVM4SF "RVVM4SI") (RVVM2SF "RVVM2SI")
3147 (RVVM1SF "RVVM1SI") (RVVMF2SF "RVVMF2SI")
3149 (RVVM8DF "RVVM4SI") (RVVM4DF "RVVM2SI") (RVVM2DF "RVVM1SI")
3150 (RVVM1DF "RVVMF2SI")
3152 (V1HF "V1SI") (V2HF "V2SI") (V4HF "V4SI") (V8HF "V8SI") (V16HF "V16SI")
3153 (V32HF "V32SI") (V64HF "V64SI") (V128HF "V128SI") (V256HF "V256SI")
3154 (V512HF "V512SI") (V1024HF "V1024SI")
3156 (V1SF "V1SI") (V2SF "V2SI") (V4SF "V4SI") (V8SF "V8SI") (V16SF "V16SI")
3157 (V32SF "V32SI") (V64SF "V64SI") (V128SF "V128SI") (V256SF "V256SI")
3158 (V512SF "V512SI") (V1024SF "V1024SI")
3160 (V1DF "V1SI") (V2DF "V2SI") (V4DF "V4SI") (V8DF "V8SI") (V16DF "V16SI")
3161 (V32DF "V32SI") (V64DF "V64SI") (V128DF "V128SI") (V256DF "V256SI")
3165 (define_mode_attr v_f2si_convert [
3166 (RVVM4HF "rvvm8si") (RVVM2HF "rvvm4si") (RVVM1HF "rvvm2si")
3167 (RVVMF2HF "rvvm1si") (RVVMF4HF "rvvmf2si")
3169 (RVVM8SF "rvvm8si") (RVVM4SF "rvvm4si") (RVVM2SF "rvvm2si")
3170 (RVVM1SF "rvvm1si") (RVVMF2SF "rvvmf2si")
3172 (RVVM8DF "rvvm4si") (RVVM4DF "rvvm2si") (RVVM2DF "rvvm1si")
3173 (RVVM1DF "rvvmf2si")
3175 (V1HF "v1si") (V2HF "v2si") (V4HF "v4si") (V8HF "v8si") (V16HF "v16si")
3176 (V32HF "v32si") (V64HF "v64si") (V128HF "v128si") (V256HF "v256si")
3177 (V512HF "v512si") (V1024HF "v1024si")
3179 (V1SF "v1si") (V2SF "v2si") (V4SF "v4si") (V8SF "v8si") (V16SF "v16si")
3180 (V32SF "v32si") (V64SF "v64si") (V128SF "v128si") (V256SF "v256si")
3181 (V512SF "v512si") (V1024SF "v1024si")
3183 (V1DF "v1si") (V2DF "v2si") (V4DF "v4si") (V8DF "v8si") (V16DF "v16si")
3184 (V32DF "v32si") (V64DF "v64si") (V128DF "v128si") (V256DF "v256si")
3188 (define_mode_iterator V_VLS_F_CONVERT_SI [
3189 (RVVM4HF "TARGET_ZVFH") (RVVM2HF "TARGET_ZVFH") (RVVM1HF "TARGET_ZVFH")
3190 (RVVMF2HF "TARGET_ZVFH") (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
3192 (RVVM8SF "TARGET_VECTOR_ELEN_FP_32") (RVVM4SF "TARGET_VECTOR_ELEN_FP_32")
3193 (RVVM2SF "TARGET_VECTOR_ELEN_FP_32") (RVVM1SF "TARGET_VECTOR_ELEN_FP_32")
3194 (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
3196 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64")
3197 (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
3198 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64")
3199 (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
3201 (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_ZVFH")
3202 (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_ZVFH")
3203 (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_ZVFH")
3204 (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_ZVFH")
3205 (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_ZVFH")
3206 (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 64")
3207 (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
3208 (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 256")
3209 (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 512")
3210 (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024")
3211 (V1024HF "riscv_vector::vls_mode_valid_p (V1024HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 2048")
3213 (V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_FP_32")
3214 (V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_FP_32")
3215 (V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_FP_32")
3216 (V8SF "riscv_vector::vls_mode_valid_p (V8SFmode) && TARGET_VECTOR_ELEN_FP_32")
3217 (V16SF "riscv_vector::vls_mode_valid_p (V16SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
3218 (V32SF "riscv_vector::vls_mode_valid_p (V32SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
3219 (V64SF "riscv_vector::vls_mode_valid_p (V64SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
3220 (V128SF "riscv_vector::vls_mode_valid_p (V128SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
3221 (V256SF "riscv_vector::vls_mode_valid_p (V256SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
3222 (V512SF "riscv_vector::vls_mode_valid_p (V512SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
3223 (V1024SF "riscv_vector::vls_mode_valid_p (V1024SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
3225 (V1DF "riscv_vector::vls_mode_valid_p (V1DFmode) && TARGET_VECTOR_ELEN_FP_64")
3226 (V2DF "riscv_vector::vls_mode_valid_p (V2DFmode) && TARGET_VECTOR_ELEN_FP_64")
3227 (V4DF "riscv_vector::vls_mode_valid_p (V4DFmode) && TARGET_VECTOR_ELEN_FP_64")
3228 (V8DF "riscv_vector::vls_mode_valid_p (V8DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
3229 (V16DF "riscv_vector::vls_mode_valid_p (V16DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
3230 (V32DF "riscv_vector::vls_mode_valid_p (V32DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
3231 (V64DF "riscv_vector::vls_mode_valid_p (V64DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
3232 (V128DF "riscv_vector::vls_mode_valid_p (V128DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
3233 (V256DF "riscv_vector::vls_mode_valid_p (V256DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
3234 (V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
3237 (define_mode_attr V_F2DI_CONVERT [
3238 (RVVM2HF "RVVM8DI") (RVVM1HF "RVVM4DI") (RVVMF2HF "RVVM2DI")
3239 (RVVMF4HF "RVVM1DI")
3241 (RVVM4SF "RVVM8DI") (RVVM2SF "RVVM4DI") (RVVM1SF "RVVM2DI")
3242 (RVVMF2SF "RVVM1DI")
3244 (RVVM8DF "RVVM8DI") (RVVM4DF "RVVM4DI") (RVVM2DF "RVVM2DI")
3247 (V1HF "V1DI") (V2HF "V2DI") (V4HF "V4DI") (V8HF "V8DI") (V16HF "V16DI")
3248 (V32HF "V32DI") (V64HF "V64DI") (V128HF "V128DI") (V256HF "V256DI")
3251 (V1SF "V1DI") (V2SF "V2DI") (V4SF "V4DI") (V8SF "V8DI") (V16SF "V16DI")
3252 (V32SF "V32DI") (V64SF "V64DI") (V128SF "V128DI") (V256SF "V256DI")
3255 (V1DF "V1DI") (V2DF "V2DI") (V4DF "V4DI") (V8DF "V8DI") (V16DF "V16DI")
3256 (V32DF "V32DI") (V64DF "V64DI") (V128DF "V128DI") (V256DF "V256DI")
3260 (define_mode_attr v_f2di_convert [
3261 (RVVM2HF "rvvm8di") (RVVM1HF "rvvm4di") (RVVMF2HF "rvvm2di")
3262 (RVVMF4HF "rvvm1di")
3264 (RVVM4SF "rvvm8di") (RVVM2SF "rvvm4di") (RVVM1SF "rvvm2di")
3265 (RVVMF2SF "rvvm1di")
3267 (RVVM8DF "rvvm8di") (RVVM4DF "rvvm4di") (RVVM2DF "rvvm2di")
3270 (V1HF "v1di") (V2HF "v2di") (V4HF "v4di") (V8HF "v8di") (V16HF "v16di")
3271 (V32HF "v32di") (V64HF "v64di") (V128HF "v128di") (V256HF "v256di")
3274 (V1SF "v1di") (V2SF "v2di") (V4SF "v4di") (V8SF "v8di") (V16SF "v16di")
3275 (V32SF "v32di") (V64SF "v64di") (V128SF "v128di") (V256SF "v256di")
3278 (V1DF "v1di") (V2DF "v2di") (V4DF "v4di") (V8DF "v8di") (V16DF "v16di")
3279 (V32DF "v32di") (V64DF "v64di") (V128DF "v128di") (V256DF "v256di")
3283 (define_mode_attr V_F2DI_CONVERT_BRIDGE [
3284 (RVVM2HF "RVVM4SF") (RVVM1HF "RVVM2SF") (RVVMF2HF "RVVM1SF")
3285 (RVVMF4HF "RVVMF2SF")
3287 (RVVM4SF "VOID") (RVVM2SF "VOID") (RVVM1SF "VOID")
3290 (RVVM8DF "VOID") (RVVM4DF "VOID") (RVVM2DF "VOID")
3293 (V1HF "V1SF") (V2HF "V2SF") (V4HF "V4SF") (V8HF "V8SF") (V16HF "V16SF")
3294 (V32HF "V32SF") (V64HF "V64SF") (V128HF "V128SF") (V256HF "V256SF")
3297 (V1SF "VOID") (V2SF "VOID") (V4SF "VOID") (V8SF "VOID") (V16SF "VOID")
3298 (V32SF "VOID") (V64SF "VOID") (V128SF "VOID") (V256SF "VOID")
3301 (V1DF "VOID") (V2DF "VOID") (V4DF "VOID") (V8DF "VOID") (V16DF "VOID")
3302 (V32DF "VOID") (V64DF "VOID") (V128DF "VOID") (V256DF "VOID")
3306 (define_mode_iterator V_VLS_F_CONVERT_DI [
3307 (RVVM2HF "TARGET_ZVFH") (RVVM1HF "TARGET_ZVFH") (RVVMF2HF "TARGET_ZVFH")
3308 (RVVMF4HF "TARGET_ZVFH && TARGET_MIN_VLEN > 32")
3310 (RVVM4SF "TARGET_VECTOR_ELEN_FP_32") (RVVM2SF "TARGET_VECTOR_ELEN_FP_32")
3311 (RVVM1SF "TARGET_VECTOR_ELEN_FP_32")
3312 (RVVMF2SF "TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN > 32")
3314 (RVVM8DF "TARGET_VECTOR_ELEN_FP_64") (RVVM4DF "TARGET_VECTOR_ELEN_FP_64")
3315 (RVVM2DF "TARGET_VECTOR_ELEN_FP_64") (RVVM1DF "TARGET_VECTOR_ELEN_FP_64")
3317 (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_ZVFH")
3318 (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_ZVFH")
3319 (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_ZVFH")
3320 (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_ZVFH")
3321 (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_ZVFH")
3322 (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 64")
3323 (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 128")
3324 (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 256")
3325 (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 512")
3326 (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_ZVFH && TARGET_MIN_VLEN >= 1024")
3328 (V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_FP_32")
3329 (V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_FP_32")
3330 (V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_FP_32")
3331 (V8SF "riscv_vector::vls_mode_valid_p (V8SFmode) && TARGET_VECTOR_ELEN_FP_32")
3332 (V16SF "riscv_vector::vls_mode_valid_p (V16SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
3333 (V32SF "riscv_vector::vls_mode_valid_p (V32SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
3334 (V64SF "riscv_vector::vls_mode_valid_p (V64SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
3335 (V128SF "riscv_vector::vls_mode_valid_p (V128SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
3336 (V256SF "riscv_vector::vls_mode_valid_p (V256SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
3337 (V512SF "riscv_vector::vls_mode_valid_p (V512SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
3339 (V1DF "riscv_vector::vls_mode_valid_p (V1DFmode) && TARGET_VECTOR_ELEN_FP_64")
3340 (V2DF "riscv_vector::vls_mode_valid_p (V2DFmode) && TARGET_VECTOR_ELEN_FP_64")
3341 (V4DF "riscv_vector::vls_mode_valid_p (V4DFmode) && TARGET_VECTOR_ELEN_FP_64")
3342 (V8DF "riscv_vector::vls_mode_valid_p (V8DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
3343 (V16DF "riscv_vector::vls_mode_valid_p (V16DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
3344 (V32DF "riscv_vector::vls_mode_valid_p (V32DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
3345 (V64DF "riscv_vector::vls_mode_valid_p (V64DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
3346 (V128DF "riscv_vector::vls_mode_valid_p (V128DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
3347 (V256DF "riscv_vector::vls_mode_valid_p (V256DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
3348 (V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
3351 (define_mode_attr stride_predicate [
3352 (RVVM8QI "vector_eew8_stride_operand") (RVVM4QI "vector_eew8_stride_operand")
3353 (RVVM2QI "vector_eew8_stride_operand") (RVVM1QI "vector_eew8_stride_operand")
3354 (RVVMF2QI "vector_eew8_stride_operand") (RVVMF4QI "vector_eew8_stride_operand")
3355 (RVVMF8QI "vector_eew8_stride_operand")
3357 (RVVM8HI "vector_eew16_stride_operand") (RVVM4HI "vector_eew16_stride_operand")
3358 (RVVM2HI "vector_eew16_stride_operand") (RVVM1HI "vector_eew16_stride_operand")
3359 (RVVMF2HI "vector_eew16_stride_operand") (RVVMF4HI "vector_eew16_stride_operand")
3361 (RVVM8HF "vector_eew16_stride_operand") (RVVM4HF "vector_eew16_stride_operand")
3362 (RVVM2HF "vector_eew16_stride_operand") (RVVM1HF "vector_eew16_stride_operand")
3363 (RVVMF2HF "vector_eew16_stride_operand") (RVVMF4HF "vector_eew16_stride_operand")
3365 (RVVM8SI "vector_eew32_stride_operand") (RVVM4SI "vector_eew32_stride_operand")
3366 (RVVM2SI "vector_eew32_stride_operand") (RVVM1SI "vector_eew32_stride_operand")
3367 (RVVMF2SI "vector_eew32_stride_operand")
3369 (RVVM8SF "vector_eew32_stride_operand") (RVVM4SF "vector_eew32_stride_operand")
3370 (RVVM2SF "vector_eew32_stride_operand") (RVVM1SF "vector_eew32_stride_operand")
3371 (RVVMF2SF "vector_eew32_stride_operand")
3373 (RVVM8DI "vector_eew64_stride_operand") (RVVM4DI "vector_eew64_stride_operand")
3374 (RVVM2DI "vector_eew64_stride_operand") (RVVM1DI "vector_eew64_stride_operand")
3376 (RVVM8DF "vector_eew64_stride_operand") (RVVM4DF "vector_eew64_stride_operand")
3377 (RVVM2DF "vector_eew64_stride_operand") (RVVM1DF "vector_eew64_stride_operand")
3380 (define_mode_attr stride_load_constraint [
3381 (RVVM8QI "rJ,rJ,rJ,c01,c01,c01") (RVVM4QI "rJ,rJ,rJ,c01,c01,c01")
3382 (RVVM2QI "rJ,rJ,rJ,c01,c01,c01") (RVVM1QI "rJ,rJ,rJ,c01,c01,c01")
3383 (RVVMF2QI "rJ,rJ,rJ,c01,c01,c01") (RVVMF4QI "rJ,rJ,rJ,c01,c01,c01")
3384 (RVVMF8QI "rJ,rJ,rJ,c01,c01,c01")
3386 (RVVM8HI "rJ,rJ,rJ,c02,c02,c02") (RVVM4HI "rJ,rJ,rJ,c02,c02,c02")
3387 (RVVM2HI "rJ,rJ,rJ,c02,c02,c02") (RVVM1HI "rJ,rJ,rJ,c02,c02,c02")
3388 (RVVMF2HI "rJ,rJ,rJ,c02,c02,c02") (RVVMF4HI "rJ,rJ,rJ,c02,c02,c02")
3390 (RVVM8HF "rJ,rJ,rJ,c02,c02,c02") (RVVM4HF "rJ,rJ,rJ,c02,c02,c02")
3391 (RVVM2HF "rJ,rJ,rJ,c02,c02,c02") (RVVM1HF "rJ,rJ,rJ,c02,c02,c02")
3392 (RVVMF2HF "rJ,rJ,rJ,c02,c02,c02") (RVVMF4HF "rJ,rJ,rJ,c02,c02,c02")
3394 (RVVM8SI "rJ,rJ,rJ,c04,c04,c04") (RVVM4SI "rJ,rJ,rJ,c04,c04,c04")
3395 (RVVM2SI "rJ,rJ,rJ,c04,c04,c04") (RVVM1SI "rJ,rJ,rJ,c04,c04,c04")
3396 (RVVMF2SI "rJ,rJ,rJ,c04,c04,c04")
3398 (RVVM8SF "rJ,rJ,rJ,c04,c04,c04") (RVVM4SF "rJ,rJ,rJ,c04,c04,c04")
3399 (RVVM2SF "rJ,rJ,rJ,c04,c04,c04") (RVVM1SF "rJ,rJ,rJ,c04,c04,c04")
3400 (RVVMF2SF "rJ,rJ,rJ,c04,c04,c04")
3402 (RVVM8DI "rJ,rJ,rJ,c08,c08,c08") (RVVM4DI "rJ,rJ,rJ,c08,c08,c08")
3403 (RVVM2DI "rJ,rJ,rJ,c08,c08,c08") (RVVM1DI "rJ,rJ,rJ,c08,c08,c08")
3405 (RVVM8DF "rJ,rJ,rJ,c08,c08,c08") (RVVM4DF "rJ,rJ,rJ,c08,c08,c08")
3406 (RVVM2DF "rJ,rJ,rJ,c08,c08,c08") (RVVM1DF "rJ,rJ,rJ,c08,c08,c08")
3409 (define_mode_attr stride_store_constraint [
3410 (RVVM8QI "rJ,c01") (RVVM4QI "rJ,c01")
3411 (RVVM2QI "rJ,c01") (RVVM1QI "rJ,c01")
3412 (RVVMF2QI "rJ,c01") (RVVMF4QI "rJ,c01")
3415 (RVVM8HI "rJ,c02") (RVVM4HI "rJ,c02")
3416 (RVVM2HI "rJ,c02") (RVVM1HI "rJ,c02")
3417 (RVVMF2HI "rJ,c02") (RVVMF4HI "rJ,c02")
3419 (RVVM8HF "rJ,c02") (RVVM4HF "rJ,c02")
3420 (RVVM2HF "rJ,c02") (RVVM1HF "rJ,c02")
3421 (RVVMF2HF "rJ,c02") (RVVMF4HF "rJ,c02")
3423 (RVVM8SI "rJ,c04") (RVVM4SI "rJ,c04")
3424 (RVVM2SI "rJ,c04") (RVVM1SI "rJ,c04")
3427 (RVVM8SF "rJ,c04") (RVVM4SF "rJ,c04")
3428 (RVVM2SF "rJ,c04") (RVVM1SF "rJ,c04")
3431 (RVVM8DI "rJ,c08") (RVVM4DI "rJ,c08")
3432 (RVVM2DI "rJ,c08") (RVVM1DI "rJ,c08")
3434 (RVVM8DF "rJ,c08") (RVVM4DF "rJ,c08")
3435 (RVVM2DF "rJ,c08") (RVVM1DF "rJ,c08")
3438 (define_mode_attr gs_extension [
3439 (RVVM8QI "const_1_operand") (RVVM4QI "const_1_operand")
3440 (RVVM2QI "vector_gs_extension_operand") (RVVM1QI "immediate_operand") (RVVMF2QI "immediate_operand")
3441 (RVVMF4QI "immediate_operand") (RVVMF8QI "immediate_operand")
3443 (RVVM8HI "const_1_operand") (RVVM4HI "vector_gs_extension_operand")
3444 (RVVM2HI "immediate_operand") (RVVM1HI "immediate_operand")
3445 (RVVMF2HI "immediate_operand") (RVVMF4HI "immediate_operand")
3447 (RVVM8HF "const_1_operand") (RVVM4HF "vector_gs_extension_operand")
3448 (RVVM2HF "immediate_operand") (RVVM1HF "immediate_operand")
3449 (RVVMF2HF "immediate_operand") (RVVMF4HF "immediate_operand")
3451 (RVVM8SI "vector_gs_extension_operand") (RVVM4SI "immediate_operand") (RVVM2SI "immediate_operand")
3452 (RVVM1SI "immediate_operand") (RVVMF2SI "immediate_operand")
3454 (RVVM8SF "vector_gs_extension_operand") (RVVM4SF "immediate_operand") (RVVM2SF "immediate_operand")
3455 (RVVM1SF "immediate_operand") (RVVMF2SF "immediate_operand")
3457 (RVVM8DI "immediate_operand") (RVVM4DI "immediate_operand")
3458 (RVVM2DI "immediate_operand") (RVVM1DI "immediate_operand")
3460 (RVVM8DF "immediate_operand") (RVVM4DF "immediate_operand")
3461 (RVVM2DF "immediate_operand") (RVVM1DF "immediate_operand")
3464 (define_mode_attr gs_scale [
3465 (RVVM8QI "const_1_operand") (RVVM4QI "const_1_operand")
3466 (RVVM2QI "const_1_operand") (RVVM1QI "const_1_operand") (RVVMF2QI "const_1_operand")
3467 (RVVMF4QI "const_1_operand") (RVVMF8QI "const_1_operand")
3469 (RVVM8HI "const_1_operand") (RVVM4HI "vector_gs_scale_operand_16_rv32")
3470 (RVVM2HI "const_1_or_2_operand") (RVVM1HI "const_1_or_2_operand")
3471 (RVVMF2HI "const_1_or_2_operand") (RVVMF4HI "const_1_or_2_operand")
3473 (RVVM8HF "const_1_operand") (RVVM4HF "vector_gs_scale_operand_16_rv32")
3474 (RVVM2HF "const_1_or_2_operand") (RVVM1HF "const_1_or_2_operand")
3475 (RVVMF2HF "const_1_or_2_operand") (RVVMF4HF "const_1_or_2_operand")
3477 (RVVM8SI "vector_gs_scale_operand_32_rv32") (RVVM4SI "const_1_or_4_operand") (RVVM2SI "const_1_or_4_operand")
3478 (RVVM1SI "const_1_or_4_operand") (RVVMF2SI "const_1_or_4_operand")
3480 (RVVM8SF "vector_gs_scale_operand_32_rv32") (RVVM4SF "const_1_or_4_operand") (RVVM2SF "const_1_or_4_operand")
3481 (RVVM1SF "const_1_or_4_operand") (RVVMF2SF "const_1_or_4_operand")
3483 (RVVM8DI "const_1_or_8_operand") (RVVM4DI "const_1_or_8_operand")
3484 (RVVM2DI "const_1_or_8_operand") (RVVM1DI "const_1_or_8_operand")
3486 (RVVM8DF "const_1_or_8_operand") (RVVM4DF "const_1_or_8_operand")
3487 (RVVM2DF "const_1_or_8_operand") (RVVM1DF "const_1_or_8_operand")
3490 (define_int_iterator ORDER [UNSPEC_ORDERED UNSPEC_UNORDERED])
3492 (define_int_iterator VMULH [UNSPEC_VMULHS UNSPEC_VMULHU UNSPEC_VMULHSU])
3494 (define_int_iterator VNCLIP [UNSPEC_VNCLIP UNSPEC_VNCLIPU])
3496 (define_int_iterator VSLIDES [UNSPEC_VSLIDEUP UNSPEC_VSLIDEDOWN])
3497 (define_int_iterator VSLIDES1 [UNSPEC_VSLIDE1UP UNSPEC_VSLIDE1DOWN])
3498 (define_int_iterator VFSLIDES1 [UNSPEC_VFSLIDE1UP UNSPEC_VFSLIDE1DOWN])
3500 (define_int_iterator VSAT_OP [UNSPEC_VAADDU UNSPEC_VAADD
3501 UNSPEC_VASUBU UNSPEC_VASUB UNSPEC_VSMUL
3502 UNSPEC_VSSRL UNSPEC_VSSRA])
3504 (define_int_iterator VSAT_ARITH_OP [UNSPEC_VAADDU UNSPEC_VAADD
3505 UNSPEC_VASUBU UNSPEC_VASUB UNSPEC_VSMUL])
3506 (define_int_iterator VSAT_SHIFT_OP [UNSPEC_VSSRL UNSPEC_VSSRA])
3508 (define_int_iterator VMISC [UNSPEC_VMSBF UNSPEC_VMSIF UNSPEC_VMSOF])
3510 (define_int_iterator VFMISC [UNSPEC_VFRSQRT7])
3512 (define_int_iterator VFMISC_FRM [UNSPEC_VFREC7])
3514 (define_int_iterator VFCVTS [UNSPEC_VFCVT UNSPEC_UNSIGNED_VFCVT])
3516 (define_int_attr order [
3517 (UNSPEC_ORDERED "o") (UNSPEC_UNORDERED "u")
3518 (UNSPEC_REDUC_SUM_ORDERED "o") (UNSPEC_REDUC_SUM_UNORDERED "u")
3519 (UNSPEC_WREDUC_SUM_ORDERED "o") (UNSPEC_WREDUC_SUM_UNORDERED "u")
3522 (define_int_attr v_su [(UNSPEC_VMULHS "") (UNSPEC_VMULHU "u") (UNSPEC_VMULHSU "su")
3523 (UNSPEC_VNCLIP "") (UNSPEC_VNCLIPU "u")
3524 (UNSPEC_VFCVT "") (UNSPEC_UNSIGNED_VFCVT "u")])
3525 (define_int_attr sat_op [(UNSPEC_VAADDU "aaddu") (UNSPEC_VAADD "aadd")
3526 (UNSPEC_VASUBU "asubu") (UNSPEC_VASUB "asub")
3527 (UNSPEC_VSMUL "smul") (UNSPEC_VSSRL "ssrl")
3528 (UNSPEC_VSSRA "ssra")])
3529 (define_int_attr sat_insn_type [(UNSPEC_VAADDU "vaalu") (UNSPEC_VAADD "vaalu")
3530 (UNSPEC_VASUBU "vaalu") (UNSPEC_VASUB "vaalu")
3531 (UNSPEC_VSMUL "vsmul") (UNSPEC_VSSRL "vsshift")
3532 (UNSPEC_VSSRA "vsshift") (UNSPEC_VNCLIP "vnclip")
3533 (UNSPEC_VNCLIPU "vnclip")])
3535 (define_int_attr misc_op [(UNSPEC_VMSBF "sbf") (UNSPEC_VMSIF "sif") (UNSPEC_VMSOF "sof")
3536 (UNSPEC_VFRSQRT7 "rsqrt7")])
3538 (define_int_attr misc_frm_op [(UNSPEC_VFREC7 "rec7")])
3540 (define_int_attr float_insn_type [(UNSPEC_VFRSQRT7 "vfsqrt")])
3542 (define_int_attr float_frm_insn_type [(UNSPEC_VFREC7 "vfrecp")])
3544 (define_int_iterator VCOPYSIGNS [UNSPEC_VCOPYSIGN UNSPEC_VXORSIGN])
3546 (define_int_attr copysign [(UNSPEC_VCOPYSIGN "copysign") (UNSPEC_VXORSIGN "xorsign")])
3548 (define_int_attr nx [(UNSPEC_VCOPYSIGN "") (UNSPEC_VXORSIGN "x")])
3550 (define_int_attr ud [(UNSPEC_VSLIDEUP "up") (UNSPEC_VSLIDEDOWN "down")
3551 (UNSPEC_VSLIDE1UP "1up") (UNSPEC_VSLIDE1DOWN "1down")
3552 (UNSPEC_VFSLIDE1UP "1up") (UNSPEC_VFSLIDE1DOWN "1down")])
3554 (define_int_attr ud_constraint [(UNSPEC_VSLIDEUP "=&vr,&vr,&vr,&vr") (UNSPEC_VSLIDEDOWN "=vd,vd,vr,vr")
3555 (UNSPEC_VSLIDE1UP "=&vr,&vr,&vr,&vr") (UNSPEC_VSLIDE1DOWN "=vd,vd,vr,vr")
3556 (UNSPEC_VFSLIDE1UP "=&vr,&vr,&vr,&vr") (UNSPEC_VFSLIDE1DOWN "=vd,vd,vr,vr")])
3558 (define_int_attr UNSPEC [(UNSPEC_VSLIDE1UP "UNSPEC_VSLIDE1UP")
3559 (UNSPEC_VSLIDE1DOWN "UNSPEC_VSLIDE1DOWN")])
3561 (define_int_iterator UNSPEC_VFMAXMIN [UNSPEC_VFMAX UNSPEC_VFMIN])
3563 (define_int_attr ieee_fmaxmin_op [(UNSPEC_VFMAX "fmax") (UNSPEC_VFMIN "fmin")])
3564 (define_int_attr IEEE_FMAXMIN_OP [(UNSPEC_VFMAX "UNSPEC_VFMAX") (UNSPEC_VFMIN "UNSPEC_VFMIN")])
3566 (define_code_iterator any_int_binop [plus minus and ior xor ashift ashiftrt lshiftrt
3567 smax umax smin umin mult div udiv mod umod
3570 (define_code_iterator any_int_unop [neg not])
3572 (define_code_iterator any_commutative_binop [plus and ior xor
3573 smax umax smin umin mult
3576 (define_code_iterator any_non_commutative_binop [minus div udiv mod umod])
3578 (define_code_iterator any_int_binop_no_shift
3579 [plus minus and ior xor smax umax smin umin mult div udiv mod umod
3582 (define_code_iterator any_sat_int_binop [ss_plus ss_minus us_plus us_minus])
3583 (define_code_iterator sat_int_plus_binop [ss_plus us_plus])
3584 (define_code_iterator sat_int_minus_binop [ss_minus us_minus])
3586 (define_code_iterator mulh [smul_highpart umul_highpart])
3587 (define_code_attr mulh_table [(smul_highpart "smul") (umul_highpart "umul")])
3588 (define_code_attr MULH_UNSPEC [(smul_highpart "UNSPEC_VMULHS") (umul_highpart "UNSPEC_VMULHU")])
3590 (define_code_iterator any_widen_binop [plus minus mult])
3591 (define_code_iterator plus_minus [plus minus])
3593 (define_code_attr madd_msub [(plus "madd") (minus "msub")])
3594 (define_code_attr macc_msac [(plus "macc") (minus "msac")])
3595 (define_code_attr nmsub_nmadd [(plus "nmsub") (minus "nmadd")])
3596 (define_code_attr nmsac_nmacc [(plus "nmsac") (minus "nmacc")])
3598 (define_code_iterator and_ior [and ior])
3600 (define_code_iterator any_float_binop [plus mult minus div])
3601 (define_code_iterator any_float_binop_nofrm [smax smin])
3602 (define_code_iterator commutative_float_binop [plus mult])
3603 (define_code_iterator commutative_float_binop_nofrm [smax smin])
3604 (define_code_iterator non_commutative_float_binop [minus div])
3605 (define_code_iterator any_float_unop [sqrt])
3606 (define_code_iterator any_float_unop_nofrm [neg abs])
3608 (define_code_iterator any_fix [fix unsigned_fix])
3609 (define_code_iterator any_float [float unsigned_float])
3611 (define_code_attr fix_cvt [(fix "fix_trunc") (unsigned_fix "fixuns_trunc")])
3612 (define_code_attr float_cvt [(float "float") (unsigned_float "floatuns")])
3614 (define_code_attr ninsn [(and "nand") (ior "nor") (xor "xnor")])
3616 (define_code_attr binop_rhs1_predicate [
3617 (plus "register_operand")
3618 (minus "vector_arith_operand")
3619 (ior "register_operand")
3620 (xor "register_operand")
3621 (and "register_operand")
3622 (ashift "register_operand")
3623 (ashiftrt "register_operand")
3624 (lshiftrt "register_operand")
3625 (smin "register_operand")
3626 (smax "register_operand")
3627 (umin "register_operand")
3628 (umax "register_operand")
3629 (mult "register_operand")
3630 (div "register_operand")
3631 (mod "register_operand")
3632 (udiv "register_operand")
3633 (umod "register_operand")
3634 (ss_plus "register_operand")
3635 (us_plus "register_operand")
3636 (ss_minus "register_operand")
3637 (us_minus "register_operand")])
3639 (define_code_attr binop_rhs2_predicate [
3640 (plus "vector_arith_operand")
3641 (minus "vector_neg_arith_operand")
3642 (ior "vector_arith_operand")
3643 (xor "vector_arith_operand")
3644 (and "vector_arith_operand")
3645 (ashift "vector_shift_operand")
3646 (ashiftrt "vector_shift_operand")
3647 (lshiftrt "vector_shift_operand")
3648 (smin "register_operand")
3649 (smax "register_operand")
3650 (umin "register_operand")
3651 (umax "register_operand")
3652 (mult "register_operand")
3653 (div "register_operand")
3654 (mod "register_operand")
3655 (udiv "register_operand")
3656 (umod "register_operand")
3657 (ss_plus "vector_arith_operand")
3658 (us_plus "vector_arith_operand")
3659 (ss_minus "vector_neg_arith_operand")
3660 (us_minus "register_operand")])
3662 (define_code_attr binop_rhs1_constraint [
3663 (plus "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3664 (minus "vr,vr,vr,vr,vr,vr,vr,vr,vi,vi,vi,vi")
3665 (ior "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3666 (xor "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3667 (and "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3668 (ashift "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3669 (ashiftrt "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3670 (lshiftrt "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3671 (smin "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3672 (smax "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3673 (umin "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3674 (umax "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3675 (mult "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3676 (div "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3677 (mod "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3678 (udiv "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3679 (umod "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")])
3681 (define_code_attr binop_rhs2_constraint [
3682 (plus "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr")
3683 (minus "vr,vr,vr,vr,vj,vj,vj,vj,vr,vr,vr,vr")
3684 (ior "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr")
3685 (xor "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr")
3686 (and "vr,vr,vr,vr,vi,vi,vi,vi,vr,vr,vr,vr")
3687 (ashift "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr")
3688 (ashiftrt "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr")
3689 (lshiftrt "vr,vr,vr,vr,vk,vk,vk,vk,vr,vr,vr,vr")
3690 (smin "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3691 (smax "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3692 (umin "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3693 (umax "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3694 (mult "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3695 (div "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3696 (mod "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3697 (udiv "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3698 (umod "vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr,vr")
3699 (ss_plus "vr,vr,vr,vr,vi,vi,vi,vi")
3700 (us_plus "vr,vr,vr,vr,vi,vi,vi,vi")
3701 (ss_minus "vr,vr,vr,vr,vj,vj,vj,vj")
3702 (us_minus "vr,vr,vr,vr,vr,vr,vr,vr")])
3704 (define_code_attr int_binop_insn_type [
3725 (us_minus "vsalu")])
3727 (define_code_attr widen_binop_insn_type [
3732 (define_code_attr float_insn_type [
3743 ;; <binop_vi_variant_insn> expands to the insn name of binop matching constraint rhs1 is immediate.
3744 ;; minus is negated as vadd and ss_minus is negated as vsadd, others remain <insn>.
3745 (define_code_attr binop_vi_variant_insn [(ashift "sll.vi")
3763 (us_plus "saddu.vi")
3764 (ss_minus "sadd.vi")
3765 (us_minus "ssubu.vv")])
3767 ;; <binop_reverse_vi_variant_insn> expands to the insn name of binop matching constraint rhs2 is immediate.
3768 ;; minus is reversed as vrsub, others remain <insn>.
3769 (define_code_attr binop_reverse_vi_variant_insn [(ashift "sll.vv")
3787 (define_code_attr binop_vi_variant_op [(ashift "%3,%v4")
3807 (us_minus "%3,%4")])
3809 (define_code_attr binop_reverse_vi_variant_op [(ashift "%3,%4")
3827 (define_code_attr sz [(sign_extend "s") (zero_extend "z")])
3829 ;; VLS modes that has NUNITS < 32.
3830 (define_mode_iterator VLS_AVL_IMM [
3831 (V1QI "riscv_vector::vls_mode_valid_p (V1QImode)")
3832 (V2QI "riscv_vector::vls_mode_valid_p (V2QImode)")
3833 (V4QI "riscv_vector::vls_mode_valid_p (V4QImode)")
3834 (V8QI "riscv_vector::vls_mode_valid_p (V8QImode)")
3835 (V16QI "riscv_vector::vls_mode_valid_p (V16QImode)")
3836 (V1HI "riscv_vector::vls_mode_valid_p (V1HImode)")
3837 (V2HI "riscv_vector::vls_mode_valid_p (V2HImode)")
3838 (V4HI "riscv_vector::vls_mode_valid_p (V4HImode)")
3839 (V8HI "riscv_vector::vls_mode_valid_p (V8HImode)")
3840 (V16HI "riscv_vector::vls_mode_valid_p (V16HImode)")
3841 (V1SI "riscv_vector::vls_mode_valid_p (V1SImode)")
3842 (V2SI "riscv_vector::vls_mode_valid_p (V2SImode)")
3843 (V4SI "riscv_vector::vls_mode_valid_p (V4SImode)")
3844 (V8SI "riscv_vector::vls_mode_valid_p (V8SImode)")
3845 (V16SI "riscv_vector::vls_mode_valid_p (V16SImode) && TARGET_MIN_VLEN >= 64")
3846 (V1DI "riscv_vector::vls_mode_valid_p (V1DImode) && TARGET_VECTOR_ELEN_64")
3847 (V2DI "riscv_vector::vls_mode_valid_p (V2DImode) && TARGET_VECTOR_ELEN_64")
3848 (V4DI "riscv_vector::vls_mode_valid_p (V4DImode) && TARGET_VECTOR_ELEN_64")
3849 (V8DI "riscv_vector::vls_mode_valid_p (V8DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 64")
3850 (V16DI "riscv_vector::vls_mode_valid_p (V16DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 128")
3851 (V1HF "riscv_vector::vls_mode_valid_p (V1HFmode) && TARGET_VECTOR_ELEN_FP_16")
3852 (V2HF "riscv_vector::vls_mode_valid_p (V2HFmode) && TARGET_VECTOR_ELEN_FP_16")
3853 (V4HF "riscv_vector::vls_mode_valid_p (V4HFmode) && TARGET_VECTOR_ELEN_FP_16")
3854 (V8HF "riscv_vector::vls_mode_valid_p (V8HFmode) && TARGET_VECTOR_ELEN_FP_16")
3855 (V16HF "riscv_vector::vls_mode_valid_p (V16HFmode) && TARGET_VECTOR_ELEN_FP_16")
3856 (V1SF "riscv_vector::vls_mode_valid_p (V1SFmode) && TARGET_VECTOR_ELEN_FP_32")
3857 (V2SF "riscv_vector::vls_mode_valid_p (V2SFmode) && TARGET_VECTOR_ELEN_FP_32")
3858 (V4SF "riscv_vector::vls_mode_valid_p (V4SFmode) && TARGET_VECTOR_ELEN_FP_32")
3859 (V8SF "riscv_vector::vls_mode_valid_p (V8SFmode) && TARGET_VECTOR_ELEN_FP_32")
3860 (V16SF "riscv_vector::vls_mode_valid_p (V16SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 64")
3861 (V1DF "riscv_vector::vls_mode_valid_p (V1DFmode) && TARGET_VECTOR_ELEN_FP_64")
3862 (V2DF "riscv_vector::vls_mode_valid_p (V2DFmode) && TARGET_VECTOR_ELEN_FP_64")
3863 (V4DF "riscv_vector::vls_mode_valid_p (V4DFmode) && TARGET_VECTOR_ELEN_FP_64")
3864 (V8DF "riscv_vector::vls_mode_valid_p (V8DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 64")
3865 (V16DF "riscv_vector::vls_mode_valid_p (V16DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 128")
3867 (V1BI "riscv_vector::vls_mode_valid_p (V1BImode)")
3868 (V2BI "riscv_vector::vls_mode_valid_p (V2BImode)")
3869 (V4BI "riscv_vector::vls_mode_valid_p (V4BImode)")
3870 (V8BI "riscv_vector::vls_mode_valid_p (V8BImode)")
3871 (V16BI "riscv_vector::vls_mode_valid_p (V16BImode)")])
3873 ;; VLS modes that has NUNITS >= 32.
3874 (define_mode_iterator VLS_AVL_REG [
3875 (V32QI "riscv_vector::vls_mode_valid_p (V32QImode)")
3876 (V64QI "riscv_vector::vls_mode_valid_p (V64QImode) && TARGET_MIN_VLEN >= 64")
3877 (V128QI "riscv_vector::vls_mode_valid_p (V128QImode) && TARGET_MIN_VLEN >= 128")
3878 (V256QI "riscv_vector::vls_mode_valid_p (V256QImode) && TARGET_MIN_VLEN >= 256")
3879 (V512QI "riscv_vector::vls_mode_valid_p (V512QImode) && TARGET_MIN_VLEN >= 512")
3880 (V1024QI "riscv_vector::vls_mode_valid_p (V1024QImode) && TARGET_MIN_VLEN >= 1024")
3881 (V2048QI "riscv_vector::vls_mode_valid_p (V2048QImode) && TARGET_MIN_VLEN >= 2048")
3882 (V4096QI "riscv_vector::vls_mode_valid_p (V4096QImode) && TARGET_MIN_VLEN >= 4096")
3883 (V32HI "riscv_vector::vls_mode_valid_p (V32HImode) && TARGET_MIN_VLEN >= 64")
3884 (V64HI "riscv_vector::vls_mode_valid_p (V64HImode) && TARGET_MIN_VLEN >= 128")
3885 (V128HI "riscv_vector::vls_mode_valid_p (V128HImode) && TARGET_MIN_VLEN >= 256")
3886 (V256HI "riscv_vector::vls_mode_valid_p (V256HImode) && TARGET_MIN_VLEN >= 512")
3887 (V512HI "riscv_vector::vls_mode_valid_p (V512HImode) && TARGET_MIN_VLEN >= 1024")
3888 (V1024HI "riscv_vector::vls_mode_valid_p (V1024HImode) && TARGET_MIN_VLEN >= 2048")
3889 (V2048HI "riscv_vector::vls_mode_valid_p (V2048HImode) && TARGET_MIN_VLEN >= 4096")
3890 (V32SI "riscv_vector::vls_mode_valid_p (V32SImode) && TARGET_MIN_VLEN >= 128")
3891 (V64SI "riscv_vector::vls_mode_valid_p (V64SImode) && TARGET_MIN_VLEN >= 256")
3892 (V128SI "riscv_vector::vls_mode_valid_p (V128SImode) && TARGET_MIN_VLEN >= 512")
3893 (V256SI "riscv_vector::vls_mode_valid_p (V256SImode) && TARGET_MIN_VLEN >= 1024")
3894 (V512SI "riscv_vector::vls_mode_valid_p (V512SImode) && TARGET_MIN_VLEN >= 2048")
3895 (V1024SI "riscv_vector::vls_mode_valid_p (V1024SImode) && TARGET_MIN_VLEN >= 4096")
3896 (V32DI "riscv_vector::vls_mode_valid_p (V32DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 256")
3897 (V64DI "riscv_vector::vls_mode_valid_p (V64DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 512")
3898 (V128DI "riscv_vector::vls_mode_valid_p (V128DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 1024")
3899 (V256DI "riscv_vector::vls_mode_valid_p (V256DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 2048")
3900 (V512DI "riscv_vector::vls_mode_valid_p (V512DImode) && TARGET_VECTOR_ELEN_64 && TARGET_MIN_VLEN >= 4096")
3901 (V32HF "riscv_vector::vls_mode_valid_p (V32HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 64")
3902 (V64HF "riscv_vector::vls_mode_valid_p (V64HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 128")
3903 (V128HF "riscv_vector::vls_mode_valid_p (V128HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 256")
3904 (V256HF "riscv_vector::vls_mode_valid_p (V256HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 512")
3905 (V512HF "riscv_vector::vls_mode_valid_p (V512HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 1024")
3906 (V1024HF "riscv_vector::vls_mode_valid_p (V1024HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 2048")
3907 (V2048HF "riscv_vector::vls_mode_valid_p (V2048HFmode) && TARGET_VECTOR_ELEN_FP_16 && TARGET_MIN_VLEN >= 4096")
3908 (V32SF "riscv_vector::vls_mode_valid_p (V32SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 128")
3909 (V64SF "riscv_vector::vls_mode_valid_p (V64SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 256")
3910 (V128SF "riscv_vector::vls_mode_valid_p (V128SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 512")
3911 (V256SF "riscv_vector::vls_mode_valid_p (V256SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 1024")
3912 (V512SF "riscv_vector::vls_mode_valid_p (V512SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 2048")
3913 (V1024SF "riscv_vector::vls_mode_valid_p (V1024SFmode) && TARGET_VECTOR_ELEN_FP_32 && TARGET_MIN_VLEN >= 4096")
3914 (V32DF "riscv_vector::vls_mode_valid_p (V32DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 256")
3915 (V64DF "riscv_vector::vls_mode_valid_p (V64DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 512")
3916 (V128DF "riscv_vector::vls_mode_valid_p (V128DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 1024")
3917 (V256DF "riscv_vector::vls_mode_valid_p (V256DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 2048")
3918 (V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) && TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
3920 (V32BI "riscv_vector::vls_mode_valid_p (V32BImode)")
3921 (V64BI "riscv_vector::vls_mode_valid_p (V64BImode) && TARGET_MIN_VLEN >= 64")
3922 (V128BI "riscv_vector::vls_mode_valid_p (V128BImode) && TARGET_MIN_VLEN >= 128")
3923 (V256BI "riscv_vector::vls_mode_valid_p (V256BImode) && TARGET_MIN_VLEN >= 256")
3924 (V512BI "riscv_vector::vls_mode_valid_p (V512BImode) && TARGET_MIN_VLEN >= 512")
3925 (V1024BI "riscv_vector::vls_mode_valid_p (V1024BImode) && TARGET_MIN_VLEN >= 1024")
3926 (V2048BI "riscv_vector::vls_mode_valid_p (V2048BImode) && TARGET_MIN_VLEN >= 2048")
3927 (V4096BI "riscv_vector::vls_mode_valid_p (V4096BImode) && TARGET_MIN_VLEN >= 4096")])
3929 (define_mode_iterator VSI [
3930 RVVM8SI RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
3933 (define_mode_iterator VLMULX2_SI [
3934 RVVM4SI RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
3937 (define_mode_iterator VLMULX4_SI [
3938 RVVM2SI RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
3941 (define_mode_iterator VLMULX8_SI [
3942 RVVM1SI (RVVMF2SI "TARGET_MIN_VLEN > 32")
3945 (define_mode_iterator VLMULX16_SI [
3946 (RVVMF2SI "TARGET_MIN_VLEN > 32")
3949 (define_mode_attr VSIX2 [
3950 (RVVM8SI "RVVM8SI") (RVVM4SI "RVVM8SI") (RVVM2SI "RVVM4SI") (RVVM1SI "RVVM2SI") (RVVMF2SI "RVVM1SI")
3953 (define_mode_attr VSIX4 [
3954 (RVVM2SI "RVVM8SI") (RVVM1SI "RVVM4SI") (RVVMF2SI "RVVM2SI")
3957 (define_mode_attr VSIX8 [
3958 (RVVM1SI "RVVM8SI") (RVVMF2SI "RVVM4SI")
3961 (define_mode_attr VSIX16 [
3962 (RVVMF2SI "RVVM8SI")