| blob | 8ece7859945ceb5597a8abef7bd28dd7a596c59e |
1 /* Subroutines used for code generation for RISC-V.
2 Copyright (C) 2011-2024 Free Software Foundation, Inc.
3 Contributed by Andrew Waterman (andrew@sifive.com).
4 Based on MIPS target for GNU compiler.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 #define IN_TARGET_CODE 1
24 #define INCLUDE_STRING
79 /* This file should be included last. */
84 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */
85 #define UNSPEC_ADDRESS_P(X) \
86 (GET_CODE (X) == UNSPEC \
87 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \
88 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES)
90 /* Extract the symbol or label from UNSPEC wrapper X. */
91 #define UNSPEC_ADDRESS(X) \
92 XVECEXP (X, 0, 0)
94 /* Extract the symbol type from UNSPEC wrapper X. */
95 #define UNSPEC_ADDRESS_TYPE(X) \
96 ((enum riscv_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST))
98 /* Extract the backup dynamic frm rtl. */
99 #define DYNAMIC_FRM_RTL(c) ((c)->machine->mode_sw_info.dynamic_frm)
101 /* True the mode switching has static frm, or false. */
102 #define STATIC_FRM_P(c) ((c)->machine->mode_sw_info.static_frm_p)
104 /* True if we can use the instructions in the XTheadInt extension
105 to handle interrupts, or false. */
106 #define TH_INT_INTERRUPT(c) \
107 (TARGET_XTHEADINT \
109 && !TARGET_64BIT \
110 && (c)->machine->interrupt_handler_p \
112 && (c)->machine->interrupt_mode == MACHINE_MODE)
114 /* Information about a function's frame layout. */
116 /* The size of the frame in bytes. */
117 poly_int64 total_size;
119 /* Bit X is set if the function saves or restores GPR X. */
122 /* Likewise FPR X. */
125 /* Likewise for vector registers. */
128 /* How much the GPR save/restore routines adjust sp (or 0 if unused). */
131 /* the minimum number of bytes, in multiples of 16-byte address increments,
132 required to cover the registers in a multi push & pop. */
135 /* the number of additional 16-byte address increments allocated for the stack
136 frame in a multi push & pop. */
139 /* Offsets of fixed-point and floating-point save areas from frame bottom */
140 poly_int64 gp_sp_offset;
141 poly_int64 fp_sp_offset;
143 /* Top and bottom offsets of vector save areas from frame bottom. */
144 poly_int64 v_sp_offset_top;
145 poly_int64 v_sp_offset_bottom;
147 /* Offset of virtual frame pointer from stack pointer/frame bottom */
148 poly_int64 frame_pointer_offset;
150 /* Offset of hard frame pointer from stack pointer/frame bottom */
151 poly_int64 hard_frame_pointer_offset;
153 /* The offset of arg_pointer_rtx from the bottom of the frame. */
154 poly_int64 arg_pointer_offset;
156 /* Reset this struct, clean all field to zero. */
158 };
162 };
165 /* The RTL variable which stores the dynamic FRM value. We always use this
166 RTX to restore dynamic FRM rounding mode in mode switching. */
167 rtx dynamic_frm;
169 /* The boolean variables indicates there is at least one static rounding
170 mode instruction in the function or not. */
174 {
177 }
178 };
181 /* The number of extra stack bytes taken up by register varargs.
182 This area is allocated by the callee at the very top of the frame. */
185 /* True if current function is a naked function. */
188 /* True if current function is an interrupt function. */
190 /* For an interrupt handler, indicates the privilege level. */
193 /* True if attributes on current function have been checked. */
196 /* True if RA must be saved because of a far jump. */
199 /* The current frame information, calculated by riscv_compute_frame_info. */
202 /* The components already handled by separate shrink-wrapping, which should
203 not be considered by the prologue and epilogue. */
206 /* The mode switching information for the FRM rounding modes. */
208 };
210 /* Information about a single argument. */
212 /* True if the argument is at least partially passed on the stack. */
215 /* The number of integer registers allocated to this argument. */
218 /* The offset of the first register used, provided num_gprs is nonzero.
219 If passed entirely on the stack, the value is MAX_ARGS_IN_REGISTERS. */
222 /* The number of floating-point registers allocated to this argument. */
225 /* The offset of the first register used, provided num_fprs is nonzero. */
228 /* The number of vector registers allocated to this argument. */
231 /* The offset of the first register used, provided num_vrs is nonzero. */
234 /* The number of mask registers allocated to this argument. */
237 /* The offset of the first register used, provided num_mrs is nonzero. */
239 };
241 /* One stage in a constant building sequence. These sequences have
242 the form:
244 A = VALUE[0]
245 A = A CODE[1] VALUE[1]
246 A = A CODE[2] VALUE[2]
247 ...
249 where A is an accumulator, each CODE[i] is a binary rtl operation
250 and each VALUE[i] is a constant integer. CODE[0] is undefined. */
256 };
258 /* The largest number of operations needed to load an integer constant.
259 The worst case is LUI, ADDI, SLLI, ADDI, SLLI, ADDI, SLLI, ADDI. */
260 #define RISCV_MAX_INTEGER_OPS 8
262 enum riscv_fusion_pairs
263 {
275 };
277 /* Costs of various operations on the different architectures. */
279 struct riscv_tune_param
280 {
296 };
299 /* Global variables for machine-dependent things. */
301 /* Whether unaligned accesses execute very slowly. */
304 /* Whether misaligned vector accesses are supported (i.e. do not
305 throw an exception). */
308 /* Whether user explicitly passed -mstrict-align. */
311 /* Stack alignment to assume/maintain. */
314 /* Whether in riscv_output_mi_thunk. */
317 /* If non-zero, this is an offset to be added to SP to redefine the CFA
318 when restoring the FP register from the stack. Only valid when generating
319 the epilogue. */
322 /* Which tuning parameters to use. */
325 /* Which automaton to use for tuning. */
328 /* The number of chunks in a single vector register. */
329 poly_uint16 riscv_vector_chunks;
331 /* The number of bytes in a vector chunk. */
334 /* Index R is the smallest register class that contains register R. */
368 };
370 /* RVV costs for VLS vector operations. */
390 };
392 /* RVV costs for VLA vector operations. */
394 {
413 },
414 };
416 /* RVV register move cost. */
422 };
424 /* Generic costs for vector insn classes. It is supposed to be the vector cost
425 models used by default if no other cost model was specified. */
436 };
438 /* Costs to use when optimizing for rocket. */
455 };
457 /* Costs to use when optimizing for Sifive 7 Series. */
474 };
476 /* Costs to use when optimizing for Sifive p400 Series. */
493 };
495 /* Costs to use when optimizing for Sifive p600 Series. */
512 };
514 /* Costs to use when optimizing for T-HEAD c906. */
531 };
533 /* Costs to use when optimizing for xiangshan nanhu. */
550 };
552 /* Costs to use when optimizing for a generic ooo profile. */
569 };
571 /* Costs to use when optimizing for size. */
588 };
596 /* Defining target-specific uses of __attribute__. */
598 {
599 /* Syntax: { name, min_len, max_len, decl_required, type_required,
600 function_type_required, affects_type_identity, handler,
601 exclude } */
603 /* The attribute telling no prologue/epilogue. */
605 NULL},
606 /* This attribute generates prologue/epilogue for interrupt handlers. */
608 NULL},
610 /* The following two are used for the built-in properties of the Vector type
611 and are not used externally */
614 /* This attribute is used to declare a function, forcing it to use the
615 standard vector calling convention variant. Syntax:
616 __attribute__((riscv_vector_cc)). */
618 /* This attribute is used to declare a new type, to appoint the exactly
619 bits size of the type. For example:
621 typedef vint8m1_t f_vint8m1_t __attribute__((riscv_rvv_vector_bits(256)));
623 The new created type f_vint8m1_t will be exactly 256 bits. It can be
624 be used in globals, structs, unions, and arrays instead of sizeless
625 types. */
628 };
631 {
633 };
636 {
637 /* This attribute is used to declare a function, forcing it to use the
638 standard vector calling convention variant. Syntax:
639 [[riscv::vector_cc]]. */
641 /* This attribute is used to declare a new type, to appoint the exactly
642 bits size of the type. For example:
644 typedef vint8m1_t f_vint8m1_t __attribute__((riscv_rvv_vector_bits(256)));
646 The new created type f_vint8m1_t will be exactly 256 bits. It can be
647 be used in globals, structs, unions, and arrays instead of sizeless
648 types. */
651 };
654 {
656 };
659 {
661 &riscv_nongnu_attribute_table
662 };
664 /* Order for the CLOBBERs/USEs of gpr_save. */
669 S10_REGNUM, S11_REGNUM
670 };
672 /* A table describing all the processors GCC knows about. */
674 #define RISCV_TUNE(TUNE_NAME, PIPELINE_MODEL, TUNE_INFO) \
675 { TUNE_NAME, PIPELINE_MODEL, & TUNE_INFO},
677 };
679 /* Global variable to distinguish whether we should save and restore s0/fp for
680 function. */
684 {
686 POP_IDX,
687 POPRET_IDX,
688 POPRETZ_IDX,
689 ZCMP_OP_NUM
695 {
712 }
714 /* Implement TARGET_MIN_ARITHMETIC_PRECISION. */
716 static unsigned int
718 {
720 }
722 /* Get the arch string from an options object. */
727 {
729 }
734 {
741 }
743 /* Return the riscv_tune_info entry for the given name string, return nullptr
744 if NULL_P is true, otherwise return an placeholder and report error. */
748 {
763 }
765 /* Helper function for riscv_build_integer; arguments are as for
766 riscv_build_integer. */
768 static int
771 {
780 {
781 /* Simply ADDI or LUI. */
787 }
789 {
790 /* Simply BSETI. */
796 /* RISC-V sign-extends all 32bit values that live in a 32bit
797 register. To avoid paradoxes, we thus need to use the
798 sign-extended (negative) representation (-1 << 31) for the
799 value, if we want to build (1 << 31) in SImode. This will
800 then expand to an LUI instruction. */
805 }
807 /* End with ADDI. When constructing HImode constants, do not generate any
808 intermediate value that is not itself a valid HImode constant. The
809 XORI case below will handle those remaining HImode constants. */
813 {
820 {
827 }
828 }
830 /* End with XORI. */
832 {
835 {
842 }
843 }
845 /* Eliminate trailing zeros and end with SLLI. */
847 {
853 /* Don't eliminate the lower 12 bits if LUI might apply. */
857 || (TARGET_64BIT
858 && TARGET_ZBA
863 /* If X has bits 32..63 clear and bit 31 set, then go ahead and mark
864 it as desiring a "uw" operation for the shift. That way we can have
865 LUI+ADDI to generate the constant, then shift it into position
866 clearing out the undesirable bits. */
868 && TARGET_64BIT
869 && TARGET_ZBA
871 {
874 }
878 {
885 }
886 }
889 {
893 /* If all bits are one except a few that are zero, and the zero bits
894 are within a range of 11 bits, then we can synthesize a constant
895 by loading a small negative constant and rotating. */
898 {
900 /* The sign-bit might be zero, so just rotate to be safe. */
910 }
911 /* Handle the case where the 11 bit range of zero bits wraps around. */
914 {
916 /* The sign-bit might be zero, so just rotate to be safe. */
927 }
929 /* If LUI/ADDI are going to set bits 32..63 and we need a small
930 number of them cleared, we might be able to use bclri profitably.
932 Note we may allow clearing of bit 31 using bclri. There's a class
933 of constants with that bit clear where this helps. */
935 && TARGET_ZBS
937 {
938 /* Turn on all those upper bits and synthesize the result. */
942 /* Now iterate over the bits we want to clear until the cost is
943 too high or we're done. */
947 {
953 alt_cost++;
955 }
958 {
961 }
962 }
963 }
966 {
968 && (alt_cost
970 {
977 }
979 && (alt_cost
981 {
988 }
990 && (alt_cost
992 {
999 }
1000 }
1002 /* We might be able to generate a constant close to our target
1003 then a final ADDI to get the desired constant. */
1007 {
1013 {
1020 }
1021 }
1023 /* Final cases, particularly focused on bseti. */
1025 {
1028 /* First handle any bits set by LUI. Be careful of the
1029 SImode sign bit!. */
1031 {
1037 i++;
1038 }
1040 /* Next, any bits we can handle with addi. */
1042 {
1048 i++;
1049 }
1051 /* And any residuals with bseti. */
1053 {
1060 i++;
1061 }
1063 /* If LUI+ADDI+BSETI resulted in a more efficient
1064 sequence, then use it. */
1066 {
1069 }
1070 }
1074 }
1076 /* Fill CODES with a sequence of rtl operations to load VALUE.
1077 Return the number of operations needed. */
1079 static int
1081 machine_mode mode)
1082 {
1085 /* Eliminate leading zeros and end with SRLI. */
1087 {
1090 HOST_WIDE_INT shifted_val;
1092 /* Try filling trailing bits with 1s. */
1096 {
1103 }
1105 /* Try filling trailing bits with 0s. */
1109 {
1116 }
1117 }
1119 /* See if we can generate the inverted constant, then use
1120 not to get the desired constant.
1122 This can't be in riscv_build_integer_1 as it'll mutually
1123 recurse with another case in there. And it has to recurse
1124 into riscv_build_integer so we get the trailing 0s case
1125 above. */
1127 {
1134 {
1141 }
1142 }
1147 {
1156 {
1159 {
1165 }
1166 }
1167 }
1169 /* With pack we can generate a 64 bit constant with the same high
1170 and low 32 bits triviall. */
1172 {
1176 {
1182 }
1184 /* An arbitrary 64 bit constant can be synthesized in 5 instructions
1185 using zbkb. We may do better than that if the upper or lower half
1186 can be synthsized with a single LUI, ADDI or BSET. Regardless the
1187 basic steps are the same. */
1189 {
1194 /* Synthesize and get cost for each half. */
1195 lo_cost
1197 hi_cost
1200 /* If profitable, finish synthesis using zbkb. */
1202 {
1203 /* We need the low half independent of the high half. So
1204 mark it has creating a temporary we'll use later. */
1209 /* Now the high half synthesis. */
1213 /* Adjust the cost. */
1216 /* And finally (ab)use VEC_MERGE to indicate we want to
1217 put merge the two parts together. */
1222 }
1223 }
1225 }
1228 }
1230 /* Return the cost of constructing VAL in the event that a scratch
1231 register is available. */
1233 static int
1235 {
1246 }
1248 /* Return the cost of constructing the integer constant VAL. */
1250 static int
1252 {
1256 }
1258 /* Try to split a 64b integer into 32b parts, then reassemble. */
1260 static rtx
1262 {
1271 else
1272 {
1275 }
1279 }
1281 /* Return true if X is a thread-local symbol. */
1283 static bool
1285 {
1287 }
1289 /* Return true if symbol X binds locally. */
1291 static bool
1293 {
1298 else
1300 }
1302 /* Return the method that should be used to access SYMBOL_REF or
1303 LABEL_REF X. */
1305 static enum riscv_symbol_type
1307 {
1315 {
1324 }
1325 }
1327 /* Classify the base of symbolic expression X. */
1329 enum riscv_symbol_type
1331 {
1332 rtx offset;
1339 }
1341 /* Return true if X is a symbolic constant. If it is, store the type of
1342 the symbol in *SYMBOL_TYPE. */
1344 bool
1346 {
1347 rtx offset;
1351 {
1354 }
1357 else
1363 /* Nonzero offsets are only valid for references that don't use the GOT. */
1365 {
1369 /* GAS rejects offsets outside the range [-2^31, 2^31-1]. */
1374 }
1375 }
1377 /* Returns the number of instructions necessary to reference a symbol. */
1380 {
1382 {
1391 }
1392 }
1394 /* Immediate values loaded by the FLI.S instruction in Chapter 25 of the latest RISC-V ISA
1395 Manual draft. For details, please see:
1396 https://github.com/riscv/riscv-isa-manual/releases/tag/isa-449cd0c */
1399 {
1404 /* Only used for filling, ensuring that 29 and 30 of HF are the same. */
1407 };
1410 {
1415 };
1418 {
1427 };
1429 /* Display floating-point values at the assembly level, which is consistent
1430 with the zfa extension of llvm:
1431 https://reviews.llvm.org/D145645. */
1434 {
1435 "-1.0", "min", "1.52587890625e-05", "3.0517578125e-05", "0.00390625", "0.0078125", "0.0625", "0.125",
1439 };
1441 /* Return index of the FLI instruction table if rtx X is an immediate constant that can
1442 be moved using a single FLI instruction in zfa extension. Return -1 if not found. */
1444 int
1446 {
1461 /* Only support up to DF mode. */
1473 {
1478 /* When the lower 32 bits are not all 0, it is impossible to be in the table. */
1481 }
1482 else
1486 {
1498 }
1506 /* Perform a binary search to find target index. */
1513 {
1519 else
1521 }
1524 }
1526 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1528 static bool
1530 {
1532 }
1534 /* Implement TARGET_CANNOT_FORCE_CONST_MEM.
1535 Return true if X cannot (or should not) be spilled to the
1536 constant pool. */
1538 static bool
1540 {
1544 /* There's no way to calculate VL-based values using relocations. */
1550 /* There is no assembler syntax for expressing an address-sized
1551 high part. */
1560 {
1564 /* As an optimization, don't spill symbolic constants that are as
1565 cheap to rematerialize as to access in the constant pool. */
1569 /* As an optimization, avoid needlessly generate dynamic relocations. */
1572 }
1574 /* TLS symbols must be computed by riscv_legitimize_move. */
1579 }
1581 /* Return true if register REGNO is a valid base register for mode MODE.
1582 STRICT_P is true if REG_OK_STRICT is in effect. */
1584 int
1586 machine_mode mode ATTRIBUTE_UNUSED,
1588 {
1590 {
1594 }
1596 /* These fake registers will be eliminated to either the stack or
1597 hard frame pointer, both of which are usually valid base registers.
1598 Reload deals with the cases where the eliminated form isn't valid. */
1603 }
1605 /* Get valid index register class.
1606 The RISC-V base instructions don't support index registers,
1607 but extensions might support that. */
1609 enum reg_class
1611 {
1616 }
1618 /* Return true if register REGNO is a valid index register.
1619 The RISC-V base instructions don't support index registers,
1620 but extensions might support that. */
1622 int
1624 {
1629 }
1631 /* Return true if X is a valid base register for mode MODE.
1632 STRICT_P is true if REG_OK_STRICT is in effect. */
1634 bool
1636 {
1642 }
1644 /* Return true if, for every base register BASE_REG, (plus BASE_REG X)
1645 can address a value of mode MODE. */
1647 static bool
1649 {
1650 /* Check that X is a signed 12-bit number. */
1654 /* We may need to split multiword moves, so make sure that every word
1655 is accessible. */
1661 }
1663 /* Should a symbol of type SYMBOL_TYPE should be split in two? */
1665 bool
1667 {
1675 }
1677 /* Return true if a LO_SUM can address a value of mode MODE when the
1678 LO_SUM symbol has type SYM_TYPE. X is the LO_SUM second operand, which
1679 is used when the mode is BLKmode. */
1681 static bool
1683 rtx x)
1684 {
1687 /* Check that symbols of type SYMBOL_TYPE can be used to access values
1688 of mode MODE. */
1692 /* Check that there is a known low-part relocation. */
1696 /* We can't tell size or alignment when we have BLKmode, so try extracting a
1697 decl from the symbol if possible. */
1699 {
1700 rtx offset;
1702 /* Extract the symbol from the LO_SUM operand, if any. */
1705 /* Might be a CODE_LABEL. We can compute align but not size for that,
1706 so don't bother trying to handle it. */
1710 /* Use worst case assumptions if we don't have a SYMBOL_REF_DECL. */
1719 }
1720 else
1721 {
1724 }
1726 /* We may need to split multiword moves, so make sure that each word
1727 can be accessed without inducing a carry. */
1733 }
1735 /* Return true if mode is the RVV enabled mode.
1736 For example: 'RVVMF2SI' mode is disabled,
1737 whereas 'RVVM1SI' mode is enabled if MIN_VLEN == 32. */
1739 bool
1741 {
1742 #define ENTRY(MODE, REQUIREMENT, ...) \
1743 case MODE##mode: \
1744 return REQUIREMENT;
1746 {
1750 }
1753 }
1755 /* Return true if mode is the RVV enabled tuple mode. */
1757 bool
1759 {
1760 #define TUPLE_ENTRY(MODE, REQUIREMENT, ...) \
1761 case MODE##mode: \
1762 return REQUIREMENT;
1764 {
1768 }
1771 }
1773 /* Return true if mode is the RVV enabled vls mode. */
1775 bool
1777 {
1778 #define VLS_ENTRY(MODE, REQUIREMENT) \
1779 case MODE##mode: \
1780 return REQUIREMENT;
1782 {
1786 }
1789 }
1791 /* Return true if it is either of below modes.
1792 1. RVV vector mode.
1793 2. RVV tuple mode.
1794 3. RVV vls mode. */
1796 static bool
1798 {
1801 }
1803 static unsigned
1806 {
1812 /* Ensure the vls mode is exact_div by scalar_unit_size. */
1816 }
1818 static machine_mode
1820 {
1822 {
1835 }
1836 }
1838 /* Call from ADJUST_NUNITS in riscv-modes.def. Return the correct
1839 NUNITS size for corresponding machine_mode. */
1841 poly_int64
1843 {
1846 {
1850 }
1852 }
1854 /* Call from ADJUST_NUNITS in riscv-modes.def. Return the correct
1855 NUNITS size for corresponding machine_mode. */
1857 poly_int64
1859 {
1861 {
1867 else
1869 }
1870 /* Set the disabled RVV modes size as 1 by default. */
1872 }
1874 /* Call from ADJUST_BYTESIZE in riscv-modes.def. Return the correct
1875 BYTE size for corresponding machine_mode. */
1877 poly_int64
1879 {
1881 {
1891 else
1893 }
1896 }
1898 /* Call from ADJUST_PRECISION in riscv-modes.def. Return the correct
1899 PRECISION size for corresponding machine_mode. */
1901 poly_int64
1903 {
1905 }
1907 /* Return true if X is a valid address for machine mode MODE. If it is,
1908 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in
1909 effect. */
1911 static bool
1914 {
1919 {
1928 /* RVV load/store disallow any offset. */
1939 /* RVV load/store disallow LO_SUM. */
1946 /* We have to trust the creator of the LO_SUM to do something vaguely
1947 sane. Target-independent code that creates a LO_SUM should also
1948 create and verify the matching HIGH. Target-independent code that
1949 adds an offset to a LO_SUM must prove that the offset will not
1950 induce a carry. Failure to do either of these things would be
1951 a bug, and we are not required to check for it here. The RISC-V
1952 backend itself should only create LO_SUMs for valid symbolic
1953 constants, with the high part being either a HIGH or a copy
1954 of _gp. */
1955 info->symbol_type
1961 /* We only allow the const0_rtx for the RVV load/store. For example:
1962 +----------------------------------------------------------+
1963 | li a5,0 |
1964 | vsetvli zero,a1,e32,m1,ta,ma |
1965 | vle32.v v24,0(a5) <- propagate the const 0 to a5 here. |
1966 | vs1r.v v24,0(a0) |
1967 +----------------------------------------------------------+
1968 It can be folded to:
1969 +----------------------------------------------------------+
1970 | vsetvli zero,a1,e32,m1,ta,ma |
1971 | vle32.v v24,0(zero) |
1972 | vs1r.v v24,0(a0) |
1973 +----------------------------------------------------------+
1974 This behavior will benefit the underlying RVV auto vectorization. */
1978 /* Small-integer addresses don't occur very often, but they
1979 are legitimate if x0 is a valid base register. */
1985 }
1986 }
1988 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */
1990 static bool
1993 {
1994 /* Disallow RVV modes base address.
1995 E.g. (mem:SI (subreg:DI (reg:V1DI 155) 0). */
2001 }
2003 /* Return true if hard reg REGNO can be used in compressed instructions. */
2005 static bool
2007 {
2008 /* x8-x15/f8-f15 are compressible registers. */
2012 }
2014 /* Return true if x is an unsigned 5-bit immediate scaled by 4. */
2016 static bool
2018 {
2022 }
2024 /* Return true if load/store from/to address x can be compressed. */
2026 static bool
2028 {
2031 reload_completed);
2033 /* Return false if address is not compressed_reg + small_offset. */
2036 /* Before reload, assume all registers are OK. */
2037 || (reload_completed
2044 }
2046 /* Return the number of instructions needed to load or store a value
2047 of mode MODE at address X. Return 0 if X isn't valid for MODE.
2048 Assume that multiword moves may need to be split into word moves
2049 if MIGHT_SPLIT_P, otherwise assume that a single load or store is
2050 enough. */
2052 int
2054 {
2059 {
2060 /* This could be a pattern from the pic.md file. In which case we want
2061 this address to always have a cost of 3 to make it as expensive as the
2062 most expensive symbol. This prevents constant propagation from
2063 preferring symbols over register plus offset. */
2065 }
2067 /* BLKmode is used for single unaligned loads and stores and should
2068 not count as a multiword mode. */
2076 }
2078 /* Return the number of instructions needed to load constant X.
2079 Return 0 if X isn't a valid constant. */
2081 int
2083 {
2085 rtx offset;
2088 {
2094 /* This is simply an LUI. */
2098 {
2100 /* Force complicated constants to memory. */
2102 }
2105 /* See if we can use FMV directly. */
2109 /* We can use x0 to load floating-point zero. */
2112 {
2113 /* TODO: This is not accurate, we will need to
2114 adapt the COST of CONST_VECTOR in the future
2115 for the following cases:
2117 - 1. const duplicate vector with element value
2118 in range of [-16, 15].
2119 - 2. const duplicate vector with element value
2120 out range of [-16, 15].
2121 - 3. const series vector.
2122 ...etc. */
2124 {
2125 /* const series vector. */
2128 {
2129 /* This is not accurate, we will need to adapt the COST
2130 * accurately according to BASE && STEP. */
2132 }
2134 rtx elt;
2136 {
2137 /* We don't allow CONST_VECTOR for DI vector on RV32
2138 system since the ELT constant value can not held
2139 within a single register to disable reload a DI
2140 register vec_duplicate into vmv.v.x. */
2145 /* Constants from -16 to 15 can be loaded with vmv.v.i.
2146 The Wc0, Wc1 constraints are already covered by the
2147 vi constraint so we do not need to check them here
2148 separately. */
2152 /* Any int/FP constants can always be broadcast from a
2153 scalar register. Loading of a floating-point
2154 constant incurs a literal-pool access. Allow this in
2155 order to increase vectorization possibilities. */
2159 else
2160 {
2161 /* We need as many insns as it takes to load the constant
2162 into a GPR and one vmv.v.x. */
2165 else
2167 }
2168 }
2169 }
2171 /* TODO: We may support more const vector in the future. */
2173 }
2176 /* See if we can refer to X directly. */
2180 /* Otherwise try splitting the constant into a base and offset. */
2183 {
2187 }
2194 /* TODO: In RVV, we get CONST_POLY_INT by using csrr VLENB
2195 instruction and several scalar shift or mult instructions,
2196 it is so far unknown. We set it to 4 temporarily. */
2202 }
2203 }
2205 /* X is a doubleword constant that can be handled by splitting it into
2206 two words and loading each word separately. Return the number of
2207 instructions required to do this. */
2209 int
2211 {
2218 }
2220 /* Return the number of instructions needed to implement INSN,
2221 given that it loads from or stores to MEM. */
2223 int
2225 {
2226 machine_mode mode;
2228 rtx set;
2233 /* Try to prove that INSN does not need to be split. */
2238 {
2242 }
2245 }
2247 /* Emit a move from SRC to DEST. Assume that the move expanders can
2248 handle all moves if !can_create_pseudo_p (). The distinction is
2249 important because, unlike emit_move_insn, the move expanders know
2250 how to force Pmode objects into the constant pool even when the
2251 constant pool address is not itself legitimate. */
2253 rtx
2255 {
2259 }
2261 /* Emit an instruction of the form (set TARGET SRC). */
2263 static rtx
2265 {
2268 }
2270 /* Emit an instruction of the form (set DEST (CODE X)). */
2272 rtx
2274 {
2276 }
2278 /* Emit an instruction of the form (set DEST (CODE X Y)). */
2280 rtx
2282 {
2284 }
2286 /* Compute (CODE X Y) and store the result in a new register
2287 of mode MODE. Return that new register. */
2289 static rtx
2291 {
2293 }
2295 static rtx
2297 {
2302 }
2304 /* Copy VALUE to a register and return that register. If new pseudos
2305 are allowed, copy it into a new register, otherwise use DEST. */
2307 static rtx
2309 {
2312 else
2313 {
2316 }
2317 }
2319 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE,
2320 then add CONST_INT OFFSET to the result. */
2322 static rtx
2325 {
2331 }
2333 /* Return an UNSPEC address with underlying address ADDRESS and symbol
2334 type SYMBOL_TYPE. */
2336 rtx
2338 {
2343 }
2345 /* If OP is an UNSPEC address, return the address to which it refers,
2346 otherwise return OP itself. */
2348 static rtx
2350 {
2357 }
2359 /* If riscv_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the
2360 high part to BASE and return the result. Just return BASE otherwise.
2361 TEMP is as for riscv_force_temporary.
2363 The returned expression can be used as the first operand to a LO_SUM. */
2365 static rtx
2367 {
2370 }
2372 /* Load an entry from the GOT for a TLS GD access. */
2375 {
2378 else
2380 }
2382 /* Load an entry from the GOT for a TLS IE access. */
2385 {
2388 else
2390 }
2392 /* Add in the thread pointer for a TLS LE access. */
2395 {
2399 else
2401 }
2403 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise
2404 it appears in a MEM of that mode. Return true if ADDR is a legitimate
2405 constant in that context and can be split into high and low parts.
2406 If so, and if LOW_OUT is nonnull, emit the high part and store the
2407 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise.
2409 TEMP is as for riscv_force_temporary and is used to load the high
2410 part into a register.
2412 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be
2413 a legitimize SET_SRC for an .md pattern, otherwise the low part
2414 is guaranteed to be a legitimate address for mode MODE. */
2416 bool
2418 {
2429 {
2434 {
2438 }
2442 {
2445 rtx label;
2452 /* ??? Ugly hack to make weak symbols work. May need to change the
2453 RTL for the auipc and/or low patterns to get a better fix for
2454 this. */
2463 else
2468 seqno++;
2469 }
2474 }
2477 }
2479 /* Return a legitimate address for REG + OFFSET. TEMP is as for
2480 riscv_force_temporary; it is only needed when OFFSET is not a
2481 SMALL_OPERAND. */
2483 static rtx
2485 {
2487 {
2488 rtx high;
2490 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
2491 The addition inside the macro CONST_HIGH_PART may cause an
2492 overflow, so we need to force a sign-extension check. */
2497 }
2499 }
2501 /* The __tls_get_attr symbol. */
2504 /* Return an instruction sequence that calls __tls_get_addr. SYM is
2505 the TLS symbol we are referencing and TYPE is the symbol type to use
2506 (either global dynamic or local dynamic). RESULT is an RTX for the
2507 return value location. */
2511 {
2531 }
2533 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return
2534 its address. The return value will be both a valid address and a valid
2535 SET_SRC (either a REG or a LO_SUM). */
2537 static rtx
2539 {
2543 #if 0
2544 /* TLS copy relocs are now deprecated and should not be used. */
2545 /* Since we support TLS copy relocs, non-PIC TLS accesses may all use LE. */
2548 #endif
2551 {
2553 /* Rely on section anchors for the optimization that LDM TLS
2554 provides. The anchor's address is loaded with GD TLS. */
2557 {
2565 seqno++;
2566 }
2567 else
2568 {
2572 loc);
2573 }
2577 /* la.tls.ie; tp-relative add */
2595 }
2597 }
2598 \f
2599 /* If X is not a valid address for mode MODE, force it into a register. */
2601 static rtx
2603 {
2605 {
2608 else
2609 {
2610 /* It's only safe for the thunk function.
2611 Use ra as the temp register. */
2616 }
2617 }
2620 }
2622 /* Modify base + offset so that offset fits within a compressed load/store insn
2623 and the excess is added to base. */
2625 static rtx
2627 {
2629 /* Leave OFFSET as an unsigned 5-bit offset scaled by 4 and put the excess
2630 into HIGH. */
2638 }
2640 /* Helper for riscv_legitimize_address. Given X, return true if it
2641 is a left shift by 1, 2 or 3 positions or a multiply by 2, 4 or 8.
2643 This respectively represent canonical shift-add rtxs or scaled
2644 memory addresses. */
2645 static bool
2647 {
2655 }
2657 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can
2658 be legitimized in a way that the generic machinery might not expect,
2659 return a new address, otherwise return NULL. MODE is the mode of
2660 the memory being accessed. */
2662 static rtx
2664 machine_mode mode)
2665 {
2666 rtx addr;
2671 /* See if the address can split into a high part and a LO_SUM. */
2675 /* Handle BASE + OFFSET. */
2678 {
2682 /* Handle (plus (plus (mult (a) (mem_shadd_constant)) (fp)) (C)) case. */
2685 {
2689 {
2691 /* If we were given a MULT, we must fix the constant
2692 as we're going to create the ASHIFT form. */
2705 }
2706 }
2713 /* Convert BASE + LARGE_OFFSET into NEW_BASE + SMALL_OFFSET to allow
2714 possible compressed load/store. */
2716 else
2719 }
2722 }
2724 /* Load VALUE into DEST. TEMP is as for riscv_force_temporary. ORIG_MODE
2725 is the original src mode before promotion. */
2727 void
2729 machine_mode orig_mode)
2730 {
2732 machine_mode mode;
2737 /* We use the original mode for the riscv_build_integer call, because HImode
2738 values are given special treatment. */
2744 else
2745 {
2748 {
2755 {
2756 /* UNKNOWN means load the constant value into X. */
2758 }
2760 {
2761 /* If the sequence requires using a "uw" form of an insn, we're
2762 going to have to construct the RTL ourselves and put it in
2763 a register to avoid force_reg/force_operand from mucking
2764 things up. */
2768 /* Create the proper mask for the slli.uw instruction. */
2772 /* Right now the only "uw" form we use is slli, we may add more
2773 in the future. */
2778 }
2780 {
2786 }
2788 {
2795 }
2796 else
2800 /* If this entry in the code table indicates we should save away
2801 the temporary holding the current value of X, then do so. */
2803 {
2807 }
2808 }
2809 }
2812 }
2814 /* Subroutine of riscv_legitimize_move. Move constant SRC into register
2815 DEST given that SRC satisfies immediate_operand but doesn't satisfy
2816 move_operand. */
2818 static void
2820 {
2823 /* Split moves of big integers into smaller pieces. */
2825 {
2828 }
2831 {
2834 }
2836 /* Split moves of symbolic constants into high/low pairs. */
2838 {
2841 }
2843 /* Generate the appropriate access sequences for TLS symbols. */
2845 {
2848 }
2850 /* If we have (const (plus symbol offset)), and that expression cannot
2851 be forced into memory, load the symbol first and add in the offset. Also
2852 prefer to do this even if the constant _can_ be forced into memory, as it
2853 usually produces better code. */
2857 {
2861 }
2863 /* Handle below format.
2864 (const:DI
2865 (plus:DI
2866 (symbol_ref:DI ("ic") [flags 0x2] <var_decl 0x7fe57740be10 ic>) <- op_0
2867 (const_poly_int:DI [16, 16]) // <- op_1
2868 ))
2869 */
2872 {
2881 }
2885 /* When using explicit relocs, constant pool references are sometimes
2886 not legitimate addresses. */
2889 }
2891 /* Report when we try to do something that requires vector when vector is
2892 disabled. This is an error of last resort and isn't very high-quality. It
2893 usually involves attempts to measure the vector length in some way. */
2895 static void
2897 {
2900 /* Avoid reporting a slew of messages for a single oversight. */
2906 " option %<-march%>, or by using the %<target%>"
2909 }
2911 /* Helper function to operation for rtx_code CODE. */
2912 static void
2914 rtx op2)
2915 {
2917 {
2918 rtx result;
2921 else
2923 OPTAB_DIRECT);
2925 }
2926 else
2927 {
2928 rtx pat;
2929 /* The following implementation is for prologue and epilogue.
2930 Because prologue and epilogue can not use pseudo register.
2931 We can't using expand_simple_binop or expand_simple_unop. */
2934 else
2937 }
2938 }
2940 /* Expand mult operation with constant integer, multiplicand also used as a
2941 * temporary register. */
2943 static void
2945 HOST_WIDE_INT multiplier)
2946 {
2948 {
2951 }
2957 {
2960 else
2962 }
2963 else
2964 {
2966 {
2967 /*
2968 multiplicand = [BYTES_PER_RISCV_VECTOR].
2969 1. const_poly_int:P [BYTES_PER_RISCV_VECTOR * 8].
2970 Sequence:
2971 csrr a5, vlenb
2972 slli a5, a5, 3
2973 2. const_poly_int:P [-BYTES_PER_RISCV_VECTOR * 8].
2974 Sequence:
2975 csrr a5, vlenb
2976 slli a5, a5, 3
2977 neg a5, a5
2978 */
2983 }
2985 {
2986 /*
2987 multiplicand = [BYTES_PER_RISCV_VECTOR].
2988 1. const_poly_int:P [BYTES_PER_RISCV_VECTOR * 7].
2989 Sequence:
2990 csrr a5, vlenb
2991 slli a4, a5, 3
2992 sub a5, a4, a5
2993 2. const_poly_int:P [-BYTES_PER_RISCV_VECTOR * 7].
2994 Sequence:
2995 csrr a5, vlenb
2996 slli a4, a5, 3
2997 sub a5, a4, a5 + neg a5, a5 => sub a5, a5, a4
2998 */
3001 QImode));
3004 else
3006 }
3008 {
3009 /*
3010 multiplicand = [BYTES_PER_RISCV_VECTOR].
3011 1. const_poly_int:P [BYTES_PER_RISCV_VECTOR * 9].
3012 Sequence:
3013 csrr a5, vlenb
3014 slli a4, a5, 3
3015 add a5, a4, a5
3016 2. const_poly_int:P [-BYTES_PER_RISCV_VECTOR * 9].
3017 Sequence:
3018 csrr a5, vlenb
3019 slli a4, a5, 3
3020 add a5, a4, a5
3021 neg a5, a5
3022 */
3025 QImode));
3029 }
3030 else
3031 {
3032 /* We use multiplication for remaining cases. */
3034 TARGET_MUL
3039 }
3040 }
3041 }
3043 /* Analyze src and emit const_poly_int mov sequence. */
3045 void
3047 {
3049 /* It use HOST_WIDE_INT instead of int since 32bit type is not enough
3050 for e.g. (const_poly_int:DI [549755813888, 549755813888]). */
3055 /* Calculate (const_poly_int:MODE [m, n]) using scalar instructions.
3056 For any (const_poly_int:MODE [m, n]), the calculation formula is as
3057 follows.
3058 constant = m - n.
3059 When minimum VLEN = 32, poly of VLENB = (4, 4).
3060 base = vlenb(4, 4) or vlenb/2(2, 2) or vlenb/4(1, 1).
3061 When minimum VLEN > 32, poly of VLENB = (8, 8).
3062 base = vlenb(8, 8) or vlenb/2(4, 4) or vlenb/4(2, 2) or vlenb/8(1, 1).
3063 magn = (n, n) / base.
3064 (m, n) = base * magn + constant.
3065 This calculation doesn't need div operation. */
3069 else
3070 {
3074 }
3077 {
3081 }
3082 else
3083 {
3086 {
3089 {
3092 }
3093 }
3095 }
3109 else
3110 {
3111 /* Handle the constant value is not a 12-bit value. */
3112 rtx high;
3114 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH.
3115 The addition inside the macro CONST_HIGH_PART may cause an
3116 overflow, so we need to force a sign-extension check. */
3122 }
3123 }
3125 /* Adjust scalable frame of vector for prologue && epilogue. */
3127 static void
3129 {
3139 else
3146 adjust_frame_rtx
3151 NULL_RTX);
3154 }
3156 /* Take care below subreg const_poly_int move:
3158 1. (set (subreg:DI (reg:TI 237) 8)
3159 (subreg:DI (const_poly_int:TI [4, 2]) 8))
3160 =>
3161 (set (subreg:DI (reg:TI 237) 8)
3162 (const_int 0)) */
3164 static bool
3166 {
3178 {
3179 /* The const_poly_int cannot exceed int64, just set zero here. */
3182 }
3184 /* The below transform will be covered in somewhere else.
3185 Thus, ignore this here.
3186 (set (subreg:DI (reg:TI 237) 0)
3187 (subreg:DI (const_poly_int:TI [4, 2]) 0))
3188 =>
3189 (set (subreg:DI (reg:TI 237) 0)
3190 (const_poly_int:DI [4, 2])) */
3193 }
3195 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent
3196 sequence that is valid. */
3198 bool
3200 {
3202 {
3203 /*
3204 Handle:
3205 (insn 183 182 184 6 (set (mem:QI (plus:DI (reg/f:DI 156)
3206 (const_int 96 [0x60])) [0 S1 A8])
3207 (const_poly_int:QI [8, 8]))
3208 "../../../../riscv-gcc/libgcc/unwind-dw2.c":1579:3 -1 (nil))
3209 */
3211 {
3214 }
3217 {
3220 }
3226 {
3227 /* In RV32 system, handle (const_poly_int:QI [m, n])
3228 (const_poly_int:HI [m, n]).
3229 In RV64 system, handle (const_poly_int:QI [m, n])
3230 (const_poly_int:HI [m, n])
3231 (const_poly_int:SI [m, n]). */
3236 }
3237 else
3238 {
3239 /* In RV32 system, handle (const_poly_int:SI [m, n])
3240 (const_poly_int:DI [m, n]).
3241 In RV64 system, handle (const_poly_int:DI [m, n]).
3242 FIXME: Maybe we could gen SImode in RV32 and then sign-extend to
3243 DImode, the offset should not exceed 4GiB in general. */
3246 }
3248 }
3254 /* Expand
3255 (set (reg:DI target) (subreg:DI (reg:V8QI reg) 0))
3256 Expand this data movement instead of simply forbid it since
3257 we can improve the code generation for this following scenario
3258 by RVV auto-vectorization:
3259 (set (reg:V8QI 149) (vec_duplicate:V8QI (reg:QI))
3260 (set (reg:DI target) (subreg:DI (reg:V8QI reg) 0))
3261 Since RVV mode and scalar mode are in different REG_CLASS,
3262 we need to explicitly move data from V_REGS to GR_REGS by scalar move. */
3264 {
3268 /* We should be able to handle both partial and paradoxical subreg. */
3277 {
3278 /* If we want to extract 64bit value but ELEN < 64,
3279 we use RVV vector mode with EEW = 32 to extract
3280 the highpart and lowpart. */
3284 }
3287 {
3292 {
3295 }
3298 {
3299 rtx result;
3304 else
3311 {
3313 /* If Pmode = SImode and mode = DImode, we just need to
3314 extract element of index = 1 from the vector and move it
3315 into the highpart of the DEST since DEST consists of 2
3316 scalar registers. */
3318 else
3319 {
3327 }
3328 }
3329 }
3333 else
3335 }
3336 else
3340 }
3341 /* Expand
3342 (set (reg:QI target) (mem:QI (address)))
3343 to
3344 (set (reg:DI temp) (zero_extend:DI (mem:QI (address))))
3345 (set (reg:QI target) (subreg:QI (reg:DI temp) 0))
3346 with auto-sign/zero extend. */
3351 {
3352 rtx temp_reg;
3358 zero_extend_p));
3361 }
3364 {
3365 rtx reg;
3368 {
3369 /* Apply the equivalent of PROMOTE_MODE here for constants to
3370 improve cse. */
3377 {
3380 }
3381 else
3386 }
3387 else
3391 }
3393 /* In order to fit NaN boxing, expand
3394 (set FP_REG (reg:HF/BF src))
3395 to
3396 (set (reg:SI/DI mask) (const_int -65536)
3397 (set (reg:SI/DI temp) (zero_extend:SI/DI (subreg:HI (reg:HF/BF src) 0)))
3398 (set (reg:SI/DI temp) (ior:SI/DI (reg:SI/DI mask) (reg:SI/DI temp)))
3399 (set (reg:HF/BF dest) (unspec:HF/BF[ (reg:SI/DI temp) ] UNSPEC_FMV_FP16_X))
3400 */
3403 && !TARGET_ZFHMIN
3408 {
3416 else
3420 UNSPEC_FMV_FP16_X));
3423 }
3425 /* We need to deal with constants that would be legitimate
3426 immediate_operands but aren't legitimate move_operands. */
3428 {
3432 }
3434 /* RISC-V GCC may generate non-legitimate address due to we provide some
3435 pattern for optimize access PIC local symbol and it's make GCC generate
3436 unrecognizable instruction during optimizing. */
3439 reload_completed))
3440 {
3442 }
3445 reload_completed))
3446 {
3448 }
3451 }
3453 /* Return true if there is an instruction that implements CODE and accepts
3454 X as an immediate operand. */
3456 static int
3458 {
3460 {
3464 /* All shift counts are truncated to a valid constant. */
3473 /* These instructions take 12-bit signed immediates. */
3477 /* We add 1 to the immediate and use SLT. */
3481 /* Likewise SLTU, but reject the always-true case. */
3486 /* We can emulate an immediate of 1 by using GT/GTU against x0. */
3490 /* By default assume that x0 can be used for 0. */
3492 }
3493 }
3495 /* Return the cost of binary operation X, given that the instruction
3496 sequence for a word-sized or smaller operation takes SINGLE_INSNS
3497 instructions and that the sequence of a double-word operation takes
3498 DOUBLE_INSNS instructions. */
3500 static int
3502 {
3507 }
3509 /* Return the cost of sign- or zero-extending OP. */
3511 static int
3513 {
3518 /* We can use ANDI. */
3521 /* ZBA provide zext.w. */
3525 /* ZBB provide zext.h, sext.b and sext.h. */
3527 {
3533 }
3536 /* We can use SEXT.W. */
3539 /* We need to use a shift left and a shift right. */
3541 }
3543 /* Implement TARGET_RTX_COSTS. */
3545 #define SINGLE_SHIFT_COST 1
3547 static bool
3550 {
3551 /* TODO: We set RVV instruction cost as 1 by default.
3552 Cost Model need to be well analyzed and supported in the future. */
3554 {
3557 }
3563 {
3565 /* If we are called for an INSN that's a simple set of a register,
3566 then cost based on the SET_SRC alone. */
3569 {
3572 }
3574 /* Otherwise return FALSE indicating we should recurse into both the
3575 SET_DEST and SET_SRC combining the cost of both. */
3579 /* trivial constants checked using OUTER_CODE in case they are
3580 encodable in insn itself w/o need for additional insn(s). */
3582 {
3585 }
3586 /* Fall through. */
3591 /* With TARGET_SUPPORTS_WIDE_INT const int can't be in CONST_DOUBLE
3592 rtl object. Weird recheck due to switch-case fall through above. */
3595 /* Fall through. */
3598 /* Non trivial CONST_INT Fall through: check if need multiple insns. */
3600 {
3601 /* 1. Hoist will GCSE constants only if TOTAL returned is non-zero.
3602 2. For constants loaded more than once, the approach so far has
3603 been to duplicate the operation than to CSE the constant.
3604 3. TODO: make cost more accurate specially if riscv_const_insns
3605 returns > 1. */
3608 }
3614 /* If the address is legitimate, return the number of
3615 instructions it needs. */
3617 {
3618 /* When optimizing for size, make uncompressible 32-bit addresses
3619 more expensive so that compressible 32-bit addresses are
3620 preferred. */
3624 cost++;
3628 }
3629 /* Otherwise use the default handling. */
3637 {
3638 /* For predicated conditional-move operations we assume the cost
3639 of a single instruction even though there are actually two. */
3642 }
3653 {
3656 }
3658 {
3661 {
3664 }
3666 {
3669 }
3670 }
3678 /* slli.uw pattern for zba. */
3681 {
3691 }
3692 /* bclri pattern for zbs. */
3695 {
3698 }
3699 /* bclr pattern for zbs. */
3705 {
3708 }
3713 /* orn, andn and xorn pattern for zbb. */
3716 {
3719 }
3721 /* bset[i] and binv[i] pattern for zbs. */
3723 && TARGET_ZBS
3727 {
3730 }
3732 /* Double-word operations use two single-word operations. */
3737 /* This is an SImode shift. */
3743 {
3746 }
3747 /* bit extraction pattern (zbs:bext, xtheadbs:tst). */
3751 {
3754 }
3760 {
3763 }
3767 /* bset pattern for zbs. */
3771 {
3774 }
3791 /* This is an SImode shift. */
3794 {
3797 }
3798 /* Fall through. */
3808 /* Branch comparisons have VOIDmode, so use the first operand's
3809 mode instead. */
3813 else
3819 /* (FEQ(A, A) & FEQ(B, B)) compared against 0. */
3825 /* (FEQ(A, A) & FEQ(B, B)) compared against FEQ(A, B). */
3831 /* (FLT(A, A) || FGT(B, B)). */
3840 /* FLT or FLE, but guarded by an FFLAGS read and write. */
3848 else
3853 /* add.uw pattern for zba. */
3860 {
3863 }
3864 /* shNadd pattern for zba. */
3873 {
3876 }
3877 /* Before strength-reduction, the shNadd can be expressed as the addition
3878 of a multiplication with a power-of-two. If this case is not handled,
3879 the strength-reduction in expmed.c will calculate an inflated cost. */
3888 {
3891 }
3892 /* shNadd.uw pattern for zba.
3893 [(set (match_operand:DI 0 "register_operand" "=r")
3894 (plus:DI
3895 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
3896 (match_operand:QI 2 "immediate_operand" "I"))
3897 (match_operand 3 "immediate_operand" ""))
3898 (match_operand:DI 4 "register_operand" "r")))]
3899 "TARGET_64BIT && TARGET_ZBA
3900 && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)
3901 && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff"
3902 */
3907 {
3924 {
3927 }
3929 }
3933 else
3938 {
3941 {
3947 }
3948 }
3952 else
3960 /* Estimate the cost of a library call. */
3966 else
3974 {
3977 }
3978 /* Fall through. */
3983 /* Estimate the cost of a library call. */
3987 else
3992 /* This is an SImode shift. */
3994 {
3997 }
3998 /* Fall through. */
4005 {
4006 /* RISC-V only defines rev8 for XLEN, so we will need an extra
4007 shift-right instruction for smaller modes. */
4010 }
4030 {
4031 /* Make AUIPC cheap to avoid spilling its result to the stack. */
4034 }
4039 }
4040 }
4042 /* Implement TARGET_ADDRESS_COST. */
4044 static int
4046 addr_space_t as ATTRIBUTE_UNUSED,
4048 {
4049 /* When optimizing for size, make uncompressible 32-bit addresses more
4050 * expensive so that compressible 32-bit addresses are preferred. */
4056 }
4058 /* Implement TARGET_INSN_COST. We factor in the branch cost in the cost
4059 calculation for conditional branches: one unit is considered the cost
4060 of microarchitecture-dependent actual branch execution and therefore
4061 multiplied by BRANCH_COST and any remaining units are considered fixed
4062 branch overhead. Branches on a floating-point condition incur an extra
4063 instruction cost as they will be split into an FCMP operation followed
4064 by a branch on an integer condition. */
4066 static int
4068 {
4073 {
4079 {
4083 }
4084 }
4086 }
4088 /* Implement TARGET_MAX_NOCE_IFCVT_SEQ_COST. Like the default implementation,
4089 but we consider cost units of branch instructions equal to cost units of
4090 other instructions. */
4092 static unsigned int
4094 {
4098 {
4101 }
4102 else
4103 {
4106 }
4109 }
4111 /* Implement TARGET_NOCE_CONVERSION_PROFITABLE_P. We replace the cost of a
4112 conditional branch assumed by `noce_find_if_block' at `COSTS_N_INSNS (2)'
4113 by our actual conditional branch cost, observing that our branches test
4114 conditions directly, so there is no preparatory extra condition-set
4115 instruction. */
4117 static bool
4120 {
4126 /* Hack alert! When `noce_try_store_flag_mask' uses `cstore<mode>4'
4127 to emit a conditional set operation on DImode output it comes up
4128 with a sequence such as:
4130 (insn 26 0 27 (set (reg:SI 140)
4131 (eq:SI (reg/v:DI 137 [ c ])
4132 (const_int 0 [0]))) 302 {*seq_zero_disi}
4133 (nil))
4134 (insn 27 26 28 (set (reg:DI 139)
4135 (zero_extend:DI (reg:SI 140))) 116 {*zero_extendsidi2_internal}
4136 (nil))
4138 because our `cstore<mode>4' pattern expands to an insn that gives
4139 a SImode output. The output of conditional set is 0 or 1 boolean,
4140 so it is valid for input in any scalar integer mode and therefore
4141 combine later folds the zero extend operation into an equivalent
4142 conditional set operation that produces a DImode output, however
4143 this redundant zero extend operation counts towards the cost of
4144 the replacement sequence. Compensate for that by incrementing the
4145 cost of the original sequence as well as the maximum sequence cost
4146 accordingly. Likewise for sign extension. */
4149 {
4156 {
4163 {
4166 }
4173 }
4174 else
4176 }
4179 }
4181 /* Return one word of double-word value OP. HIGH_P is true to select the
4182 high part or false to select the low part. */
4184 rtx
4186 {
4200 }
4202 /* Return true if a 64-bit move from SRC to DEST should be split into two. */
4204 bool
4206 {
4210 /* There is no need to split if the FLI instruction in the `Zfa` extension can be used. */
4214 /* Allow FPR <-> FPR and FPR <-> MEM moves, and permit the special case
4215 of zeroing an FPR with FCVT.D.W. */
4224 }
4226 /* Split a doubleword move from SRC to DEST. On 32-bit targets,
4227 this function handles 64-bit moves for which riscv_split_64bit_move_p
4228 holds. For 64-bit targets, this function handles 128-bit moves. */
4230 void
4232 {
4233 /* ZFA or XTheadFmv has instructions for accessing the upper bits of a double. */
4235 {
4237 {
4243 else
4246 }
4248 {
4253 {
4257 }
4258 else
4259 {
4262 }
4264 }
4265 }
4267 /* The operation can be split into two normal moves. Decide in
4268 which order to do them. */
4271 {
4274 }
4275 else
4276 {
4279 }
4280 }
4282 /* Constant VAL is known to be sum of two S12 constants. Break it into
4283 comprising BASE and OFF.
4284 Numerically S12 is -2048 to 2047, however it uses the more conservative
4285 range -2048 to 2032 as offsets pertain to stack related registers. */
4287 void
4290 {
4292 {
4295 }
4297 {
4300 }
4301 else
4302 {
4304 }
4305 }
4307 \f
4308 /* Return the appropriate instructions to move SRC into DEST. Assume
4309 that SRC is operand 1 and DEST is operand 0. */
4313 {
4315 machine_mode mode;
4333 {
4336 {
4340 /* Using fmv.x.s + sign-extend to emulate fmv.x.h. */
4346 }
4350 {
4355 }
4358 {
4366 /* Should never reach here. */
4368 }
4375 {
4380 }
4381 }
4384 {
4386 {
4392 {
4396 /* High 16 bits should be all-1, otherwise HW will treated
4397 as a n-bit canonical NaN, but isn't matter for softfloat. */
4404 /* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w */
4407 }
4408 }
4411 {
4416 }
4417 }
4419 {
4422 {
4431 }
4435 {
4442 }
4443 }
4445 {
4448 {
4455 }
4459 {
4466 }
4467 }
4469 {
4470 /* We only want a single full vector register VLEN read after reload. */
4473 }
4475 }
4479 {
4484 }
4486 \f
4487 /* Return true if CMP1 is a suitable second operand for integer ordering
4488 test CODE. See also the *sCC patterns in riscv.md. */
4490 static bool
4492 {
4494 {
4515 }
4516 }
4518 /* Return true if *CMP1 (of mode MODE) is a valid second operand for
4519 integer ordering test *CODE, or if an equivalent combination can
4520 be formed by adjusting *CODE and *CMP1. When returning true, update
4521 *CODE and *CMP1 with the chosen code and operand, otherwise leave
4522 them alone. */
4524 static bool
4526 machine_mode mode)
4527 {
4528 HOST_WIDE_INT plus_one;
4535 {
4539 {
4543 }
4549 {
4553 }
4558 }
4560 }
4562 /* Compare CMP0 and CMP1 using ordering test CODE and store the result
4563 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR
4564 is nonnull, it's OK to set TARGET to the inverse of the result and
4565 flip *INVERT_PTR instead. */
4567 static void
4570 {
4571 machine_mode mode;
4573 /* First see if there is a RISCV instruction that can do this operation.
4574 If not, try doing the same for the inverse operation. If that also
4575 fails, force CMP1 into a register and try again. */
4579 else
4580 {
4583 {
4586 }
4588 {
4592 }
4593 else
4594 {
4597 }
4598 }
4599 }
4601 /* Return a register that is zero iff CMP0 and CMP1 are equal.
4602 The register will have the same mode as CMP0. */
4604 static rtx
4606 {
4612 }
4614 /* Helper function for riscv_extend_comparands to Sign-extend the OP.
4615 However if the OP is SI subreg promoted with an inner DI, such as
4616 (subreg/s/v:SI (reg/v:DI) 0)
4617 just peel off the SUBREG to get DI, avoiding extraneous extension. */
4619 static void
4621 {
4628 else
4630 }
4632 /* Sign- or zero-extend OP0 and OP1 for integer comparisons. */
4634 static void
4636 {
4637 /* Comparisons consider all XLEN bits, so extend sub-XLEN values. */
4639 {
4640 /* It is more profitable to zero-extend QImode values. But not if the
4641 first operand has already been sign-extended, and the second one is
4642 is a constant or has already been sign-extended also. */
4652 {
4656 else
4658 }
4659 else
4660 {
4665 }
4666 }
4667 }
4669 /* Convert a comparison into something that can be used in a branch or
4670 conditional move. On entry, *OP0 and *OP1 are the values being
4671 compared and *CODE is the code used to compare them.
4673 Update *CODE, *OP0 and *OP1 so that they describe the final comparison.
4674 If NEED_EQ_NE_P, then only EQ or NE comparisons against zero are
4675 emitted. */
4677 static void
4680 {
4682 {
4686 {
4690 }
4692 }
4695 {
4699 {
4700 /* Convert e.g. OP0 == 2048 into OP0 - 2048 == 0. */
4702 {
4706 }
4707 }
4708 else
4709 {
4712 };
4714 /* Convert e.g. (OP0 <= 0xFFF) into (OP0 < 0x1000). */
4716 {
4717 HOST_WIDE_INT new_rhs;
4727 {
4730 }
4732 }
4733 }
4734 }
4741 }
4743 /* Like riscv_emit_int_compare, but for floating-point comparisons. */
4745 static void
4748 {
4754 {
4757 /* Fall through. */
4760 /* a == a && b == b */
4768 /* ordered(a, b) > (a == b) */
4776 #define UNORDERED_COMPARISON(CODE, CMP) \
4777 case CODE: \
4778 *code = EQ; \
4779 *op0 = gen_reg_rtx (word_mode); \
4780 if (GET_MODE (cmp_op0) == SFmode && TARGET_64BIT) \
4781 emit_insn (gen_f##CMP##_quietsfdi4 (*op0, cmp_op0, cmp_op1)); \
4782 else if (GET_MODE (cmp_op0) == SFmode) \
4783 emit_insn (gen_f##CMP##_quietsfsi4 (*op0, cmp_op0, cmp_op1)); \
4784 else if (GET_MODE (cmp_op0) == DFmode && TARGET_64BIT) \
4785 emit_insn (gen_f##CMP##_quietdfdi4 (*op0, cmp_op0, cmp_op1)); \
4786 else if (GET_MODE (cmp_op0) == DFmode) \
4787 emit_insn (gen_f##CMP##_quietdfsi4 (*op0, cmp_op0, cmp_op1)); \
4788 else if (GET_MODE (cmp_op0) == HFmode && TARGET_64BIT) \
4789 emit_insn (gen_f##CMP##_quiethfdi4 (*op0, cmp_op0, cmp_op1)); \
4790 else if (GET_MODE (cmp_op0) == HFmode) \
4791 emit_insn (gen_f##CMP##_quiethfsi4 (*op0, cmp_op0, cmp_op1)); \
4792 else \
4793 gcc_unreachable (); \
4794 *op1 = const0_rtx; \
4795 break;
4808 #undef UNORDERED_COMPARISON
4814 else
4815 {
4818 }
4826 /* We have instructions for these cases. */
4833 /* (a < b) | (a > b) */
4842 }
4843 }
4845 /* CODE-compare OP0 and OP1. Store the result in TARGET. */
4847 void
4849 {
4854 {
4857 }
4858 else
4860 }
4862 /* Like riscv_expand_int_scc, but for floating-point comparisons. */
4864 void
4867 {
4872 {
4875 }
4876 else
4878 }
4880 /* Jump to LABEL if (CODE OP0 OP1) holds. */
4882 void
4884 {
4887 else
4891 {
4895 }
4899 }
4901 /* Emit a cond move: If OP holds, move CONS to DEST; else move ALT to DEST.
4902 Return 0 if expansion failed. */
4904 bool
4906 {
4916 {
4920 /* An integer comparison must be comparing WORD_MODE objects. We
4921 must enforce that so that we don't strip away a sign_extension
4922 thinking it is unnecessary. We might consider using
4923 riscv_extend_operands if they are not already properly extended. */
4928 /* In the fallback generic case use MODE rather than WORD_MODE for
4929 the output of the SCC instruction, to match the mode of the NEG
4930 operation below. The output of SCC is 0 or 1 boolean, so it is
4931 valid for input in any scalar integer mode. */
4937 /* Canonicalize the comparison. It must be an equality comparison
4938 of integer operands, or with SFB it can be any comparison of
4939 integer operands. If it isn't, then emit an SCC instruction
4940 so that we can then use an equality comparison against zero. */
4943 {
4946 /* If riscv_expand_int_scc inverts the condition, then it will
4947 flip the value of INVERT. We need to know where so that
4948 we can adjust it for our needs. */
4952 /* Emit an SCC-like instruction into a temporary so that we can
4953 use an EQ/NE comparison. We can support both FP and integer
4954 conditional moves. */
4960 else
4965 /* We've generated a new comparison. Update the local variables. */
4969 }
4974 {
4978 /* The expander is a bit loose in its specification of the true
4979 arm of the conditional move. That allows us to support more
4980 cases for extensions which are more general than SFB. But
4981 does mean we need to force CONS into a register at this point. */
4983 /* With XTheadCondMov we need to force ALT into a register too. */
4988 }
4990 {
5005 }
5006 /* 0, reg or 0, imm */
5010 {
5018 }
5019 /* imm, imm */
5022 {
5030 alt)));
5031 /* CONS might not fit into a signed 12 bit immediate suitable
5032 for an addi instruction. If that's the case, force it
5033 into a register. */
5038 }
5039 /* imm, reg */
5041 {
5042 /* Optimize for register value of 0. */
5044 {
5051 }
5059 /* TEMP2 and/or CONS might not fit into a signed 12 bit immediate
5060 suitable for an addi instruction. If that's the case, force it
5061 into a register. */
5071 temp1)));
5074 }
5075 /* reg, 0 or imm, 0 */
5079 {
5086 }
5087 /* reg, imm */
5089 {
5090 /* Optimize for register value of 0. */
5092 {
5099 }
5107 /* TEMP2 and/or ALT might not fit into a signed 12 bit immediate
5108 suitable for an addi instruction. If that's the case, force it
5109 into a register. */
5118 temp1,
5122 }
5123 /* reg, reg */
5125 {
5129 {
5136 }
5147 cons)));
5151 alt)));
5154 }
5155 }
5158 }
5160 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at
5161 least PARM_BOUNDARY bits of alignment, but will be given anything up
5162 to PREFERRED_STACK_BOUNDARY bits if the type requires it. */
5164 static unsigned int
5166 {
5169 /* Use natural alignment if the type is not aggregate data. */
5172 else
5176 }
5178 /* If MODE represents an argument that can be passed or returned in
5179 floating-point registers, return the number of registers, else 0. */
5181 static unsigned
5183 {
5185 {
5191 }
5194 }
5197 const_tree type;
5198 HOST_WIDE_INT offset;
5201 /* Identify subfields of aggregates that are candidates for passing in
5202 floating-point registers. */
5204 static int
5209 {
5211 {
5213 /* Can't handle incomplete types nor sizes that are not fixed. */
5221 {
5225 /* The C++ front end strips zero-length bit-fields from structs.
5226 So we need to ignore them in the C front end to make C code
5227 compatible with C++ code. */
5232 ;
5233 else
5234 {
5238 ignore_zero_width_bit_field_p);
5239 }
5242 }
5246 {
5247 HOST_WIDE_INT n_elts;
5253 ignore_zero_width_bit_field_p);
5255 /* Can't handle incomplete types nor sizes that are not fixed. */
5259 || !index
5273 {
5279 }
5282 }
5285 {
5286 /* Complex type need consume 2 field, so n must be 0. */
5293 {
5300 }
5303 }
5311 {
5315 }
5316 else
5318 }
5319 }
5321 /* Identify candidate aggregates for passing in floating-point registers.
5322 Candidates have at most two fields after flattening. */
5324 static int
5328 {
5333 ignore_zero_width_bit_field_p);
5334 }
5336 /* See whether TYPE is a record whose fields should be returned in one or
5337 two floating-point registers. If so, populate FIELDS accordingly. */
5339 static unsigned
5342 {
5345 /* This is the old ABI, which differs for C++ and C. */
5349 {
5352 }
5354 /* This is the new ABI, which is the same for C++ and C. */
5358 {
5361 }
5364 {
5368 }
5371 }
5373 /* See whether TYPE is a record whose fields should be returned in one or
5374 floating-point register and one integer register. If so, populate
5375 FIELDS accordingly. */
5377 static bool
5380 {
5383 /* This is the old ABI, which differs for C++ and C. */
5387 {
5390 }
5392 /* This is the new ABI, which is the same for C++ and C. */
5396 {
5399 }
5406 {
5410 }
5413 }
5415 /* Return the representation of an argument passed or returned in an FPR
5416 when the value has mode VALUE_MODE and the type has TYPE_MODE. The
5417 two modes may be different for structures like:
5419 struct __attribute__((packed)) foo { float f; }
5421 where the SFmode value "f" is passed in REGNO but the struct itself
5422 has mode BLKmode. */
5424 static rtx
5426 machine_mode value_mode,
5427 HOST_WIDE_INT offset)
5428 {
5432 {
5435 }
5437 }
5439 /* Pass or return a composite value in the FPR pair REGNO and REGNO + 1.
5440 MODE is the mode of the composite. MODE1 and OFFSET1 are the mode and
5441 byte offset for the first value, likewise MODE2 and OFFSET2 for the
5442 second value. */
5444 static rtx
5448 HOST_WIDE_INT offset2)
5449 {
5450 return gen_rtx_PARALLEL
5459 }
5461 static rtx
5464 {
5474 {
5478 {
5482 }
5483 }
5494 }
5496 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5497 for a call to a function whose data type is FNTYPE.
5498 For a library call, FNTYPE is 0. */
5500 void
5502 {
5507 else
5509 }
5511 /* Return true if TYPE is a vector type that can be passed in vector registers.
5512 */
5514 static bool
5516 {
5517 /* Currently, only builtin scalabler vector type is allowed, in the future,
5518 more vector types may be allowed, such as GNU vector type, etc. */
5520 }
5522 static unsigned int
5525 /* Subroutine of riscv_get_arg_info. */
5527 static rtx
5530 {
5535 {
5536 /* For scalable mask return value. */
5540 /* For the first scalable mask argument. */
5542 {
5545 }
5546 else
5547 {
5548 /* Rest scalable mask arguments are treated as scalable data
5549 arguments. */
5550 }
5551 }
5553 /* The number and alignment of vector registers need for this scalable vector
5554 argument. When the mode size is less than a full vector, we use 1 vector
5555 register to pass. Just call TARGET_HARD_REGNO_NREGS for the number
5556 information. */
5565 /* For scalable data and scalable tuple return value. */
5569 /* Iterate through the USED_VRS array to find vector register groups that have
5570 not been allocated and the first register is aligned with LMUL. */
5572 {
5573 /* The index in USED_VRS array. */
5575 /* Find the first register unused. */
5577 {
5579 /* Ensure there are NREGS continuous unused registers. */
5582 {
5584 /* Update I to the last aligned register which
5585 cannot be used and the next iteration will add
5586 LMUL step to I. */
5589 }
5592 {
5596 }
5597 }
5598 }
5601 }
5603 /* Fill INFO with information about a single argument, and return an RTL
5604 pattern to pass or return the argument. Return NULL_RTX if argument cannot
5605 pass or return in registers, then the argument may be passed by reference or
5606 through the stack or . CUM is the cumulative state for earlier arguments.
5607 MODE is the mode of this argument and TYPE is its type (if known). NAMED is
5608 true if this is a named (fixed) argument rather than a variable one. RETURN_P
5609 is true if returning the argument, or false if passing the argument. */
5611 static rtx
5615 {
5625 /* Passed by reference when the scalable vector argument is anonymous. */
5630 {
5635 /* Pass one- or two-element floating-point aggregates in FPRs. */
5639 {
5655 }
5657 /* Pass real and complex floating-point numbers in FPRs. */
5661 {
5672 }
5674 /* Pass structs with one float and one integer in an FPR and a GPR. */
5678 {
5689 }
5691 /* For scalable vector argument. */
5695 /* For vls mode aggregated in gpr. */
5698 }
5700 /* Work out the size of the argument. */
5704 /* Doubleword-aligned varargs start on an even register boundary. */
5708 /* Partition the argument between registers and stack. */
5717 }
5719 /* Implement TARGET_FUNCTION_ARG. */
5721 static rtx
5723 {
5728 /* Return the calling convention that used by the current function. */
5732 }
5734 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */
5736 static void
5739 {
5745 /* Set the corresponding register in USED_VRS to used status. */
5747 {
5750 }
5753 {
5756 /* Avoid repeating the message */
5758 }
5760 /* Advance the register count. This has the effect of setting
5761 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned
5762 argument required us to skip the final GPR and pass the whole
5763 argument on the stack. */
5767 }
5769 /* Implement TARGET_ARG_PARTIAL_BYTES. */
5771 static int
5774 {
5780 }
5782 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls,
5783 VALTYPE is the return type and MODE is VOIDmode. For libcalls,
5784 VALTYPE is null and MODE is the mode of the return value. */
5786 rtx
5788 {
5790 CUMULATIVE_ARGS args;
5793 {
5798 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes,
5799 return values, promote the mode here too. */
5801 }
5806 }
5808 /* Implement TARGET_PASS_BY_REFERENCE. */
5810 static bool
5812 {
5817 /* ??? std_gimplify_va_arg_expr passes NULL for cum. Fortunately, we
5818 never pass variadic arguments in floating-point and vector registers,
5819 so we can avoid the call to riscv_get_arg_info in this case. */
5821 {
5824 /* Don't pass by reference if we can use a floating-point register. */
5828 /* Don't pass by reference if we can use general register(s) for vls. */
5832 /* Don't pass by reference if we can use vector register groups. */
5835 }
5837 /* Passed by reference when:
5838 1. The scalable vector argument is anonymous.
5839 2. Args cannot be passed through vector registers. */
5843 /* Pass by reference if the data do not fit in two integer registers. */
5845 }
5847 /* Implement TARGET_RETURN_IN_MEMORY. */
5849 static bool
5851 {
5852 CUMULATIVE_ARGS args;
5855 /* The rules for returning in memory are the same as for passing the
5856 first named argument by reference. */
5860 }
5862 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
5864 static void
5868 {
5869 CUMULATIVE_ARGS local_cum;
5872 /* The caller has advanced CUM up to, but not beyond, the last named
5873 argument. Advance a local copy of CUM past the last "real" named
5874 argument, to find out how many registers are left over. */
5880 /* Found out how many registers we need to save. */
5884 {
5893 }
5896 }
5898 /* Return the descriptor of the Standard Vector Calling Convention Variant. */
5902 {
5905 {
5906 HARD_REG_SET full_reg_clobbers
5908 /* Callee-saved vector registers: v1-v7, v24-v31. */
5914 }
5916 }
5918 static bool
5920 {
5928 }
5930 static bool
5932 {
5940 }
5942 static int
5944 {
5964 }
5966 static int
5968 {
5998 }
6000 static void
6002 {
6006 {
6010 }
6017 {
6022 }
6029 {
6036 }
6040 {
6045 }
6049 {
6053 }
6058 {
6060 input_location,
6064 }
6065 }
6067 /* Return true if a function with type FNTYPE returns its value in
6068 RISC-V V registers. */
6070 static bool
6072 {
6076 {
6079 }
6080 else
6082 }
6084 /* Return true if a function with type FNTYPE takes arguments in
6085 RISC-V V registers. */
6087 static bool
6089 {
6092 {
6095 {
6098 }
6099 }
6102 }
6104 /* Return true if FUNC is a riscv_vector_cc function.
6105 For more details please reference the below link.
6106 https://github.com/riscv-non-isa/riscv-c-api-doc/pull/67 */
6107 static bool
6109 {
6120 }
6122 /* Implement TARGET_FNTYPE_ABI. */
6126 {
6127 /* Implement the vector calling convention. For more details please
6128 reference the below link.
6129 https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/389 */
6136 }
6138 /* Return riscv calling convention of call_insn. */
6139 riscv_cc
6141 {
6149 }
6151 /* Implement TARGET_INSN_CALLEE_ABI. */
6155 {
6160 }
6162 /* Handle an attribute requiring a FUNCTION_DECL;
6163 arguments as in struct attribute_spec.handler. */
6164 static tree
6166 tree args ATTRIBUTE_UNUSED,
6168 {
6170 {
6172 name);
6174 }
6177 }
6179 /* Verify type based attributes. NODE is the what the attribute is being
6180 applied to. NAME is the attribute name. ARGS are the attribute args.
6181 FLAGS gives info about the context. NO_ADD_ATTRS should be set to true if
6182 the attribute should be ignored. */
6184 static tree
6187 {
6188 /* Check for an argument. */
6190 {
6192 {
6197 {
6200 name);
6203 }
6208 {
6213 }
6214 }
6215 }
6218 }
6220 static tree
6224 {
6231 {
6236 }
6241 {
6244 }
6249 {
6252 }
6255 unsigned HOST_WIDE_INT type_mode_bits
6259 {
6264 }
6271 /* The operations like alu/cmp on vbool*_t is not well defined,
6272 continue to treat vbool*_t as indivisible. */
6279 }
6281 /* Return true if function TYPE is an interrupt function. */
6282 static bool
6284 {
6286 }
6288 /* Return true if FUNC is a naked function. */
6289 static bool
6291 {
6296 }
6298 /* Implement TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS. */
6299 static bool
6301 {
6302 /* Naked functions should not allocate stack slots for arguments. */
6304 }
6306 /* Implement TARGET_WARN_FUNC_RETURN. */
6307 static bool
6309 {
6310 /* Naked functions are implemented entirely in assembly, including the
6311 return sequence, so suppress warnings about this. */
6313 }
6315 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
6317 static void
6319 {
6322 }
6324 /* Make ADDR suitable for use as a call or sibcall target. */
6326 rtx
6328 {
6330 {
6334 }
6336 }
6338 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM
6339 in context CONTEXT. HI_RELOC indicates a high-part reloc. */
6341 static void
6343 {
6347 {
6363 }
6368 }
6370 /* Return the memory model that encapsulates both given models. */
6372 enum memmodel
6374 {
6382 {
6389 else
6397 }
6398 }
6400 /* Return true if the .AQ suffix should be added to an AMO to implement the
6401 acquire portion of memory model MODEL. */
6403 static bool
6405 {
6406 /* ZTSO amo mappings require no annotations. */
6411 {
6424 }
6425 }
6427 /* Return true if the .RL suffix should be added to an AMO to implement the
6428 release portion of memory model MODEL. */
6430 static bool
6432 {
6433 /* ZTSO amo mappings require no annotations. */
6438 {
6451 }
6452 }
6454 /* Get REGNO alignment of vector mode.
6455 The alignment = LMUL when the LMUL >= 1.
6456 Otherwise, alignment = 1. */
6457 int
6459 {
6460 /* 3.3.2. LMUL = 2,4,8, register numbers should be multiple of 2,4,8.
6461 but for mask vector register, register numbers can be any number. */
6465 {
6469 else
6471 }
6478 }
6480 /* Define ASM_OUTPUT_OPCODE to do anything special before
6481 emitting an opcode. */
6484 {
6489 }
6491 /* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are:
6493 'h' Print the high-part relocation associated with OP, after stripping
6494 any outermost HIGH.
6495 'R' Print the low-part relocation associated with OP.
6496 'C' Print the integer branch condition for comparison OP.
6497 'N' Print the inverse of the integer branch condition for comparison OP.
6498 'A' Print the atomic operation suffix for memory model OP.
6499 'I' Print the LR suffix for memory model OP.
6500 'J' Print the SC suffix for memory model OP.
6501 'L' Print a non-temporal locality hints instruction.
6502 'z' Print x0 if OP is zero, otherwise print OP normally.
6503 'i' Print i if the operand is not a register.
6504 'S' Print shift-index of single-bit mask OP.
6505 'T' Print shift-index of inverted single-bit mask OP.
6506 '~' Print w if TARGET_64BIT is true; otherwise not print anything.
6508 Note please keep this list and the list in riscv.md in sync. */
6510 static void
6512 {
6513 /* `~` does not take an operand so op will be null
6514 Check for before accessing op.
6515 */
6517 {
6521 }
6526 {
6528 /* Print 'OP' variant for RVV instructions.
6529 1. If the operand is VECTOR REG, we print 'v'(vnsrl.wv).
6530 2. If the operand is CONST_INT/CONST_VECTOR, we print 'i'(vnsrl.wi).
6531 3. If the operand is SCALAR REG, we print 'x'(vnsrl.wx). */
6533 {
6538 else
6540 }
6541 else
6542 {
6545 else
6547 }
6549 }
6551 rtx elt;
6555 else
6556 {
6565 else
6567 }
6569 }
6571 rtx elt;
6576 else
6579 }
6582 {
6583 /* Calculate lmul according to mode and print the value. */
6586 }
6588 {
6589 /* If it is a const_int value, it denotes the VLMUL field enum. */
6592 {
6616 }
6617 }
6618 else
6621 }
6624 {
6625 /* Print for RVV mask operand.
6626 If op is reg, print ",v0.t".
6627 Otherwise, don't print anything. */
6630 }
6632 {
6633 /* Tail && Mask policy. */
6635 }
6636 else
6639 }
6651 /* The RTL names match the instruction names. */
6656 /* The RTL names match the instruction names. */
6670 }
6675 /* LR ops only have an annotation for SEQ_CST in the Ztso mapping. */
6682 }
6687 /* SC ops only have an annotation for SEQ_CST in the Ztso mapping. */
6694 }
6697 {
6700 {
6710 }
6715 }
6727 {
6731 }
6733 {
6737 }
6739 {
6744 }
6746 {
6752 }
6755 {
6765 else
6770 {
6772 {
6775 }
6779 {
6782 }
6785 }
6792 else
6795 }
6796 }
6797 }
6799 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P */
6800 static bool
6802 {
6804 }
6806 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */
6808 static void
6810 {
6818 {
6840 }
6843 }
6845 static bool
6847 {
6849 }
6851 /* Return true if EXP should be placed in the small data section. */
6853 static bool
6855 {
6856 /* Because default_use_anchors_for_symbol_p doesn't gather small data to use
6857 the anchor symbol to address nearby objects. In large model, it can get
6858 the better result using the anchor optimization. */
6866 {
6869 }
6872 }
6874 /* Switch to the appropriate section for output of DECL. */
6879 {
6881 {
6887 }
6888 }
6890 /* Switch to the appropriate section for output of DECL. */
6892 static void
6894 {
6899 {
6906 }
6908 {
6915 /* If we're using one_only, then there needs to be a .gnu.linkonce
6916 prefix to the section name. */
6923 }
6925 }
6927 /* Constant pools are per-function when in large code model. */
6931 {
6933 }
6935 static bool
6937 {
6938 /* We can't use blocks for constants when we're using a per-function
6939 constant pool. */
6941 }
6943 /* Return a section for X, handling small data. */
6948 {
6949 /* The literal pool stays with the function. */
6956 {
6958 {
6959 /* Rename .rodata.cst* to .srodata.cst*. */
6963 }
6967 }
6970 }
6972 /* Make the last instruction frame-related and note that it performs
6973 the operation described by FRAME_PATTERN. */
6975 static void
6977 {
6978 rtx insn;
6983 frame_pattern,
6985 }
6987 /* Return a frame-related rtx that stores REG at MEM.
6988 REG must be a single register. */
6990 static rtx
6992 {
6996 }
6998 /* Returns true if the current function might contain a far jump. */
7000 static bool
7002 {
7008 /* We can't change far_jump_used during or after reload, as there is
7009 no chance to change stack frame layout. So we must rely on the
7010 conservative heuristic below having done the right thing. */
7014 /* Estimate the function length. */
7018 /* Conservatively determine whether some jump might exceed 1 MiB
7019 displacement. */
7024 }
7026 /* Return true, if the current function must save the incoming return
7027 address. */
7029 static bool
7031 {
7032 /* The $ra register is call-clobbered: if this is not a leaf function,
7033 save it. */
7037 /* We need to save the incoming return address if __builtin_eh_return
7038 is being used to set a different return address. */
7042 /* Far jumps/branches use $ra as a temporary to set up the target jump
7043 location (clobbering the incoming return address). */
7047 /* We need to save it if anyone has used that. */
7051 /* Need not to use ra for leaf when frame pointer is turned off by
7052 option whatever the omit-leaf-frame's value. */
7058 }
7060 /* Return true if the current function must save register REGNO. */
7062 static bool
7064 {
7072 /* Save callee-saved V registers. */
7083 /* If this is an interrupt handler, then must save extra registers. */
7085 {
7086 /* zero register is always zero. */
7090 /* The function will return the stack pointer to its original value. */
7094 /* By convention, we assume that gp and tp are safe. */
7098 /* We must save every register used in this function. If this is not a
7099 leaf function, then we must save all temporary registers. */
7103 }
7106 }
7108 /* Return TRUE if Zcmp push and pop insns should be
7109 avoided. FALSE otherwise.
7110 Only use multi push & pop if all GPRs masked can be covered,
7111 and stack access is SP based,
7112 and GPRs are at top of the stack frame,
7113 and no conflicts in stack allocation with other features */
7114 static bool
7116 {
7126 }
7128 /* Determine whether to use multi push insn. */
7129 static bool
7131 {
7136 }
7138 /* Return TRUE if a libcall to save/restore GPRs should be
7139 avoided. FALSE otherwise. */
7140 static bool
7142 {
7145 || frame_pointer_needed
7152 }
7154 /* Determine whether to call GPR save/restore routines. */
7155 static bool
7157 {
7162 }
7164 /* Determine which GPR save/restore routine to call. */
7166 static unsigned
7168 {
7173 }
7175 /* calculate number of s regs in multi push and pop.
7176 Note that {s0-s10} is not valid in Zcmp, use {s0-s11} instead. */
7177 static unsigned
7179 {
7183 }
7185 /* calculate number of regs(ra, s0-sx) in multi push and pop. */
7186 static unsigned
7188 {
7189 /* 1 is for ra */
7191 }
7193 /* Handle 16 bytes align for poly_int. */
7194 static poly_int64
7196 {
7198 }
7200 static HOST_WIDE_INT
7202 {
7204 }
7206 /* Handle stack align for poly_int. */
7207 static poly_int64
7209 {
7211 }
7213 static HOST_WIDE_INT
7215 {
7217 }
7219 /* Populate the current function's riscv_frame_info structure.
7221 RISC-V stack frames grown downward. High addresses are at the top.
7223 +-------------------------------+
7224 | |
7225 | incoming stack arguments |
7226 | |
7227 +-------------------------------+ <-- incoming stack pointer
7228 | |
7229 | callee-allocated save area |
7230 | for arguments that are |
7231 | split between registers and |
7232 | the stack |
7233 | |
7234 +-------------------------------+ <-- arg_pointer_rtx
7235 | |
7236 | callee-allocated save area |
7237 | for register varargs |
7238 | |
7239 +-------------------------------+ <-- hard_frame_pointer_rtx;
7240 | | stack_pointer_rtx + gp_sp_offset
7241 | GPR save area | + UNITS_PER_WORD
7242 | |
7243 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset
7244 | | + UNITS_PER_FP_REG
7245 | FPR save area |
7246 | |
7247 +-------------------------------+ <-- stack_pointer_rtx
7248 | | + v_sp_offset_top
7249 | Vector Registers save area |
7250 | |
7251 | ----------------------------- | <-- stack_pointer_rtx
7252 | padding | + v_sp_offset_bottom
7253 +-------------------------------+ <-- frame_pointer_rtx (virtual)
7254 | |
7255 | local variables |
7256 | |
7257 P +-------------------------------+
7258 | |
7259 | outgoing stack arguments |
7260 | |
7261 +-------------------------------+ <-- stack_pointer_rtx
7263 Dynamic stack allocations such as alloca insert data at point P.
7264 They decrease stack_pointer_rtx but leave frame_pointer_rtx and
7265 hard_frame_pointer_rtx unchanged. */
7267 static HOST_WIDE_INT riscv_first_stack_step (struct riscv_frame_info *frame, poly_int64 remaining_size);
7269 static void
7271 {
7273 poly_int64 offset;
7280 /* In an interrupt function, there are two cases in which t0 needs to be used:
7281 1, If we have a large frame, then we need to save/restore t0. We check for
7282 this before clearing the frame struct.
7283 2, Need to save and restore some CSRs in the frame. */
7285 {
7290 }
7295 {
7296 /* Find out which GPRs we need to save. */
7299 || (interrupt_save_prologue_temp
7303 /* If this function calls eh_return, we must also save and restore the
7304 EH data registers. */
7309 /* Find out which FPRs we need to save. This loop must iterate over
7310 the same space as its companion in riscv_for_each_saved_reg. */
7316 /* Find out which V registers we need to save. */
7320 {
7322 num_v_saved++;
7323 }
7324 }
7327 {
7330 /* 1 is for ra */
7332 /* Only use save/restore routines if they don't alter the stack size. */
7335 {
7336 /* Libcall saves/restores 3 registers at once, so we need to
7337 allocate 12 bytes for callee-saved register. */
7342 }
7345 {
7346 /* num(ra, s0-sx) */
7350 }
7351 }
7353 /* In an interrupt function, we need extra space for the initial saves of CSRs. */
7356 || (TARGET_ZFINX
7357 /* Except for RISCV_PROLOGUE_TEMP_REGNUM. */
7359 /* Save and restore FCSR. */
7360 /* TODO: When P or V extensions support interrupts, some of their CSRs
7361 may also need to be saved and restored. */
7364 /* At the bottom of the frame are any outgoing stack arguments. */
7366 /* Next are local stack variables. */
7368 /* The virtual frame pointer points above the local variables. */
7370 /* Next are the callee-saved VRs. */
7374 frame->v_sp_offset_bottom
7376 /* Next are the callee-saved FPRs. */
7380 /* Next are the callee-saved GPRs. */
7382 {
7384 /* align to 16 bytes and add paddings to GPR part to honor
7385 both stack alignment and zcmp pus/pop size alignment. */
7390 }
7392 /* The hard frame pointer points above the callee-saved GPRs. */
7394 /* Above the hard frame pointer is the callee-allocated varags save area. */
7396 /* Next is the callee-allocated area for pretend stack arguments. */
7398 /* Arg pointer must be below pretend args, but must be above alignment
7399 padding. */
7403 /* Next points the incoming stack pointer and any incoming arguments. */
7404 }
7406 /* Make sure that we're not trying to eliminate to the wrong hard frame
7407 pointer. */
7409 static bool
7411 {
7413 }
7415 /* Helper to determine if reg X pertains to stack. */
7416 bool
7418 {
7424 }
7426 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer
7427 or argument pointer. TO is either the stack pointer or hard frame
7428 pointer. */
7430 poly_int64
7432 {
7441 else
7448 else
7452 }
7454 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
7455 previous frame. */
7457 rtx
7459 {
7464 }
7466 /* Emit code to change the current function's return address to
7467 ADDRESS. SCRATCH is available as a scratch register, if needed.
7468 ADDRESS and SCRATCH are both word-mode GPRs. */
7470 void
7472 {
7473 rtx slot_address;
7479 }
7481 /* Save register REG to MEM. Make the instruction frame-related. */
7483 static void
7485 {
7488 }
7490 /* Restore register REG from MEM. */
7492 static void
7494 {
7501 {
7502 rtx cfa_adjust_rtx
7506 }
7510 }
7512 /* A function to save or store a register. The first argument is the
7513 register and the second is the stack slot. */
7516 /* Use FN to save or restore register REGNO. MODE is the register's
7517 mode and OFFSET is the offset of its save slot from the current
7518 stack pointer. */
7520 static void
7523 {
7524 rtx mem;
7528 }
7530 /* Return the next register up from REGNO up to LIMIT for the callee
7531 to save or restore. OFFSET will be adjusted accordingly.
7532 If INC is set, then REGNO will be incremented first.
7533 Returns INVALID_REGNUM if there is no such next register. */
7535 static unsigned int
7538 {
7540 regno++;
7543 {
7545 {
7548 }
7550 regno++;
7551 }
7553 }
7555 /* Return TRUE if provided REGNO is eh return data register. */
7557 static bool
7559 {
7567 {
7569 }
7572 }
7574 /* Call FN for each register that is saved by the current function.
7575 SP_OFFSET is the offset of the current stack pointer from the start
7576 of the frame. */
7578 static void
7581 {
7587 /* Save the link register and s-registers. */
7593 {
7597 /* If this is a normal return in a function that calls the eh_return
7598 builtin, then do not restore the eh return data registers as that
7599 would clobber the return value. But we do still need to save them
7600 in the prologue, and restore them for an exception return, so we
7601 need special handling here. */
7606 /* In an interrupt function, save and restore some necessary CSRs in the stack
7607 to avoid changes in CSRs. */
7611 || (TARGET_ZFINX
7613 {
7614 /* Always assume FCSR occupy UNITS_PER_WORD to prevent stack
7615 offset misaligned later. */
7618 {
7624 }
7625 else
7626 {
7632 }
7634 }
7637 {
7638 /* Get the next reg/offset pair. */
7642 /* Validate everything before emitting a mempair instruction. */
7647 {
7655 /* If the operands fit into a mempair insn, then emit one. */
7657 {
7662 }
7663 }
7664 }
7667 }
7669 /* This loop must iterate over the same space as its companion in
7670 riscv_compute_frame_info. */
7671 first_fp_offset
7675 {
7684 num_masked_fp++;
7685 }
7686 }
7688 /* Call FN for each V register that is saved by the current function. */
7690 static void
7693 {
7696 {
7700 else
7701 {
7703 rtx insn
7706 }
7707 }
7709 /* Select the mode where LMUL is 1 and SEW is largest. */
7713 {
7714 /* This loop must iterate over the same space as its companion in
7715 riscv_compute_frame_info. */
7718 {
7721 {
7724 {
7727 stack_pointer_rtx,
7729 }
7730 else
7737 }
7738 }
7739 }
7740 else
7741 {
7742 /* This loop must iterate over the same space as its companion in
7743 riscv_compute_frame_info. */
7746 {
7749 {
7756 }
7757 }
7758 }
7759 }
7761 /* For stack frames that can't be allocated with a single ADDI instruction,
7762 compute the best value to initially allocate. It must at a minimum
7763 allocate enough space to spill the callee-saved registers. If TARGET_RVC,
7764 try to pick a value that will allow compression of the register saves
7765 without adding extra instructions. */
7767 static HOST_WIDE_INT
7769 {
7770 HOST_WIDE_INT remaining_const_size;
7772 remaining_const_size
7775 else
7778 /* First step must be set to the top of vector registers save area if any
7779 vector registers need be preserved. */
7786 poly_int64 callee_saved_first_step =
7789 HOST_WIDE_INT min_first_step =
7795 /* As an optimization, use the least-significant bits of the total frame
7796 size, so that the second adjustment step is just LUI + ADD. */
7803 {
7804 /* If we need two subtracts, and one is small enough to allow compressed
7805 loads and stores, then put that one first. */
7810 /* If we need LUI + ADDI + ADD for the second adjustment step, then start
7811 with the minimum first step, so that we can get compressed loads and
7812 stores. */
7815 }
7818 }
7820 static rtx
7822 {
7830 {
7831 /* The save order is ra, s0, s1, s2 to s11. */
7838 else
7843 stack_pointer_rtx,
7844 offset));
7848 }
7850 /* Debug info for adjust sp. */
7851 adjust_sp_rtx =
7855 dwarf);
7857 }
7859 static rtx
7861 {
7873 {
7874 /* The save order is s11-s0, ra
7875 from high to low addr. */
7884 }
7886 /* Debug info for adjust sp. */
7887 adjust_sp_rtx
7892 }
7894 static void
7896 {
7899 else
7901 }
7903 /*zcmp multi push and pop code_for_push_pop function ptr array */
7929 code_for_gpr_multi_popret_up_to_s11,
7930 code_for_gpr_multi_popretz_up_to_s11}};
7932 static rtx
7935 {
7941 }
7943 static unsigned
7945 {
7952 }
7954 /* Expand the "prologue" pattern. */
7956 void
7958 {
7973 /* prefer multi-push to save-restore libcall. */
7975 {
7977 /* If there are vector registers that need to be saved, then it can only
7978 be reduced to the frame->v_sp_offset_top position at most, since the
7979 vector registers will need to be saved one by one by decreasing the SP
7980 later. */
7981 poly_int64 remaining_size_above_varea
7992 else
7998 /* emit multi push insn & dwarf along with it. */
8006 /* Temporarily fib that we need not save GPRs. */
8009 /* push FPRs into the additional reserved space by cm.push. */
8011 {
8012 unsigned mask_fprs_push
8018 }
8019 }
8020 /* When optimizing for size, call a subroutine to save the registers. */
8022 {
8032 }
8036 {
8039 /* RISCV_PROLOGUE_TEMP may be used to handle some CSR for
8040 interrupts, such as fcsr. */
8054 }
8056 /* Save the GP, FP registers. */
8058 {
8060 {
8066 }
8068 }
8070 /* Undo the above fib. */
8074 /* Set up the frame pointer, if we're using one. */
8076 {
8082 }
8084 /* Save the V registers. */
8088 /* Allocate the rest of the frame. */
8090 {
8091 /* Two step adjustment:
8092 1.scalable frame. 2.constant frame. */
8095 {
8096 /* First for scalable frame. */
8101 }
8103 /* Second step for constant frame. */
8106 {
8107 /* We must have allocated stack space for the scalable frame.
8108 Emit a stack tie if we have a frame pointer so that the
8109 allocation is ordered WRT fp setup and subsequent writes
8110 into the frame. */
8114 }
8117 {
8121 }
8123 {
8132 }
8133 else
8134 {
8137 stack_pointer_rtx,
8140 /* Describe the effect of the previous instructions. */
8144 }
8146 /* We must have allocated the remainder of the stack frame.
8147 Emit a stack tie if we have a frame pointer so that the
8148 allocation is ordered WRT fp setup and subsequent writes
8149 into the frame. */
8152 }
8153 }
8155 static rtx
8157 {
8165 /* Debug info for adjust sp. */
8166 adjust_sp_rtx
8173 {
8176 }
8179 }
8181 static rtx
8183 {
8188 /* Debug info for adjust sp. */
8189 adjust_sp_rtx =
8193 dwarf);
8197 {
8200 }
8203 }
8205 static void
8208 {
8209 rtx insn;
8215 else
8222 }
8224 /* Expand an "epilogue", "sibcall_epilogue", or "eh_return_internal" pattern;
8225 style says which. */
8227 void
8229 {
8230 /* Split the frame into 3 steps. STEP1 is the amount of stack we should
8231 deallocate before restoring the registers. STEP2 is the amount we
8232 should deallocate afterwards including the callee saved regs. STEP3
8233 is the amount deallocated by save-restore libcall.
8235 Start off by assuming that no registers need to be restored. */
8241 bool use_multi_pop_normal
8243 bool use_multi_pop_sibcall
8247 bool use_restore_libcall
8248 = !use_multi_pop
8253 unsigned multipop_size
8258 rtx insn;
8260 /* We need to add memory barrier to prevent read from deallocated stack. */
8265 {
8271 }
8274 {
8277 }
8279 /* Reset the epilogue cfa info before starting to emit the epilogue. */
8282 /* Move past any dynamic stack allocations. */
8284 {
8285 /* Emit a barrier to prevent loads from a deallocated stack. */
8296 {
8302 }
8303 else
8304 {
8307 {
8309 }
8311 {
8315 }
8316 else
8317 {
8321 }
8322 }
8326 adjust));
8330 dwarf_adj);
8339 {
8343 }
8344 }
8349 /* If we need to restore registers, deallocate as much stack as
8350 possible in the second step without going out of range. */
8352 {
8356 step2
8358 }
8365 poly_int64 step1;
8366 /* STEP1 must be set to the bottom of vector registers save area if any
8367 vector registers need be preserved. */
8369 {
8372 }
8373 else
8376 /* Set TARGET to BASE + STEP1. */
8378 {
8379 /* Emit a barrier to prevent loads from a deallocated stack. */
8383 /* Restore the scalable frame which is assigned in prologue. */
8385 {
8391 }
8393 /* Get an rtx for STEP1 that we can add to BASE.
8394 Skip if adjust equal to zero. */
8397 {
8400 {
8404 stack_pointer_rtx,
8408 }
8410 {
8413 }
8416 stack_pointer_rtx,
8417 adjust));
8419 rtx cfa_adjust_rtx
8422 Pmode));
8428 }
8429 }
8431 {
8432 /* Tell riscv_restore_reg to emit dwarf to redefine CFA when restoring
8433 old value of FP. */
8435 }
8438 {
8441 {
8445 }
8446 }
8452 {
8455 /* RISCV_PROLOGUE_TEMP may be used to handle some CSR for
8456 interrupts, such as fcsr. */
8460 }
8462 /* Restore the registers. */
8469 {
8474 }
8482 /* Deallocate the final bit of the frame. */
8484 {
8489 rtx cfa_adjust_rtx
8496 }
8499 {
8500 /* restore FPRs pushed by cm.push. */
8507 /* Undo the above fib. */
8511 multipop_size);
8514 }
8516 {
8524 }
8526 /* Add in the __builtin_eh_return stack adjustment. */
8529 EH_RETURN_STACKADJ_RTX));
8531 /* Return from interrupt. */
8533 {
8544 else
8546 }
8549 }
8551 /* Implement EPILOGUE_USES. */
8553 bool
8555 {
8560 {
8561 /* An interrupt function restores temp regs, so we must indicate that
8562 they are live at function end. */
8566 }
8569 }
8571 static bool
8573 {
8580 }
8582 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
8584 static sbitmap
8586 {
8587 HOST_WIDE_INT offset;
8597 {
8598 /* We can only wrap registers that have small operand offsets.
8599 For large offsets a pseudo register might be needed which
8600 cannot be created during the shrink wrapping pass. */
8605 }
8610 {
8613 /* We can only wrap registers that have small operand offsets.
8614 For large offsets a pseudo register might be needed which
8615 cannot be created during the shrink wrapping pass. */
8620 }
8622 /* Don't mess with the hard frame pointer. */
8629 }
8631 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
8633 static sbitmap
8635 {
8643 function_abi_aggregator callee_abis;
8650 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
8670 }
8672 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS. */
8674 static void
8676 {
8677 /* Nothing to do for riscv. */
8678 }
8680 static void
8682 {
8683 HOST_WIDE_INT offset;
8689 {
8694 }
8699 {
8706 }
8707 }
8709 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
8711 static void
8713 {
8715 }
8717 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
8719 static void
8721 {
8723 }
8725 static void
8727 {
8735 }
8737 /* Return nonzero if this function is known to have a null epilogue.
8738 This allows the optimizer to omit jumps to jumps if no stack
8739 was created. */
8741 bool
8743 {
8746 }
8748 /* Given that there exists at least one variable that is set (produced)
8749 by OUT_INSN and read (consumed) by IN_INSN, return true iff
8750 IN_INSN represents one or more memory store operations and none of
8751 the variables set by OUT_INSN is used by IN_INSN as the address of a
8752 store operation. If either IN_INSN or OUT_INSN does not represent
8753 a "single" RTL SET expression (as loosely defined by the
8754 implementation of the single_set function) or a PARALLEL with only
8755 SETs, CLOBBERs, and USEs inside, this function returns false.
8757 Borrowed from rs6000, riscv_store_data_bypass_p checks for certain
8758 conditions that result in assertion failures in the generic
8759 store_data_bypass_p function and returns FALSE in such cases.
8761 This is required to make -msave-restore work with the sifive-7
8762 pipeline description. */
8764 bool
8766 {
8774 {
8776 {
8779 {
8782 {
8784 {
8791 }
8792 }
8793 }
8794 }
8795 }
8796 else
8797 {
8803 {
8811 {
8814 {
8819 {
8826 }
8827 }
8828 }
8829 }
8830 }
8833 }
8835 /* Implement TARGET_SECONDARY_MEMORY_NEEDED.
8837 When floating-point registers are wider than integer ones, moves between
8838 them must go through memory. */
8840 static bool
8842 reg_class_t class2)
8843 {
8847 && !TARGET_XTHEADFMV
8849 }
8851 /* Implement TARGET_REGISTER_MOVE_COST. */
8853 static int
8856 {
8862 }
8864 /* Implement TARGET_HARD_REGNO_NREGS. */
8866 static unsigned int
8868 {
8870 {
8871 /* Handle fractional LMUL, it only occupy part of vector register but
8872 still need one vector register to hold. */
8877 }
8879 /* For tuple modes, the number of register = NF * LMUL. */
8881 {
8888 else
8889 {
8892 }
8893 }
8895 /* For VLS modes, we allocate registers according to TARGET_MIN_VLEN. */
8897 {
8901 else
8903 }
8905 /* mode for VL or VTYPE are just a marker, not holding value,
8906 so it always consume one register. */
8911 /* Assume every valid non-vector mode fits in one vector register. */
8918 /* All other registers are word-sized. */
8920 }
8922 /* Implement TARGET_HARD_REGNO_MODE_OK. */
8924 static bool
8926 {
8930 {
8936 }
8938 {
8949 /* Only use callee-saved registers if a potential callee is guaranteed
8950 to spill the requisite width. */
8955 }
8957 {
8967 }
8971 else
8974 /* Require same callee-savedness for all registers. */
8980 /* Only use even registers in RV32 ZDINX */
8985 }
8988 }
8990 /* Implement TARGET_MODES_TIEABLE_P.
8992 Don't allow floating-point modes to be tied, since type punning of
8993 single-precision and double-precision is implementation defined. */
8995 static bool
8997 {
8998 /* We don't allow different REG_CLASS modes tieable since it
8999 will cause ICE in register allocation (RA).
9000 E.g. V2SI and DI are not tieable. */
9006 }
9008 /* Implement TARGET_CLASS_MAX_NREGS. */
9010 static unsigned char
9012 {
9023 }
9025 /* Implement TARGET_MEMORY_MOVE_COST. */
9027 static int
9029 {
9032 }
9034 /* Return the number of instructions that can be issued per cycle. */
9036 static int
9038 {
9040 }
9042 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
9043 static int
9045 {
9053 /* GHOST insns are used for blockage and similar cases which
9054 effectively end a cycle. */
9058 /* If we ever encounter an insn with an unknown type, trip
9059 an assert so we can find and fix this problem. */
9062 /* If we ever encounter an insn without an insn reservation, trip
9063 an assert so we can find and fix this problem. */
9067 }
9069 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
9070 instruction fusion of some sort. */
9072 static bool
9074 {
9076 }
9078 /* Return true iff the instruction fusion described by OP is enabled. */
9080 static bool
9082 {
9084 }
9086 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
9087 should be kept together during scheduling. */
9089 static bool
9091 {
9094 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
9103 {
9104 /* We are trying to match the following:
9105 prev (slli) == (set (reg:DI rD)
9106 (ashift:DI (reg:DI rS) (const_int 32)))
9107 curr (slri) == (set (reg:DI rD)
9108 (lshiftrt:DI (reg:DI rD) (const_int <shift>)))
9109 with <shift> being either 32 for FUSE_ZEXTW, or
9110 `less than 32 for FUSE_ZEXTWS. */
9126 }
9129 {
9130 /* We are trying to match the following:
9131 prev (slli) == (set (reg:DI rD)
9132 (ashift:DI (reg:DI rS) (const_int 48)))
9133 curr (slri) == (set (reg:DI rD)
9134 (lshiftrt:DI (reg:DI rD) (const_int 48))) */
9147 }
9150 {
9151 /* We are trying to match the following:
9152 prev (add) == (set (reg:DI rD)
9153 (plus:DI (reg:DI rS1) (reg:DI rS2))
9154 curr (ld) == (set (reg:DI rD)
9155 (mem:DI (reg:DI rD))) */
9165 /* We are trying to match the following:
9166 prev (add) == (set (reg:DI rD)
9167 (plus:DI (reg:DI rS1) (reg:DI rS2)))
9168 curr (lw) == (set (any_extend:DI (mem:SUBX (reg:DI rD)))) */
9179 }
9182 {
9183 /* We are trying to match the following:
9184 prev (add) == (set (reg:DI rS)
9185 (plus:DI (reg:DI rS) (const_int))
9186 curr (ld) == (set (reg:DI rD)
9187 (mem:DI (reg:DI rS))) */
9196 }
9199 {
9200 /* We are trying to match the following:
9201 prev (lui) == (set (reg:DI rD) (const_int UPPER_IMM_20))
9202 curr (addi) == (set (reg:DI rD)
9203 (plus:DI (reg:DI rD) (const_int IMM12))) */
9213 }
9216 {
9217 /* We are trying to match the following:
9218 prev (auipc) == (set (reg:DI rD) (unspec:DI [...] UNSPEC_AUIPC))
9219 curr (addi) == (set (reg:DI rD)
9220 (plus:DI (reg:DI rD) (const_int IMM12)))
9221 and
9222 prev (auipc) == (set (reg:DI rD) (unspec:DI [...] UNSPEC_AUIPC))
9223 curr (addi) == (set (reg:DI rD)
9224 (lo_sum:DI (reg:DI rD) (const_int IMM12))) */
9234 }
9237 {
9238 /* We are trying to match the following:
9239 prev (lui) == (set (reg:DI rD) (const_int UPPER_IMM_20))
9240 curr (ld) == (set (reg:DI rD)
9241 (mem:DI (plus:DI (reg:DI rD) (const_int IMM12)))) */
9262 }
9265 {
9266 /* We are trying to match the following:
9267 prev (auipc) == (set (reg:DI rD) (unspec:DI [...] UNSPEC_AUIPC))
9268 curr (ld) == (set (reg:DI rD)
9269 (mem:DI (plus:DI (reg:DI rD) (const_int IMM12)))) */
9276 }
9279 {
9280 /* We are trying to match the following:
9281 prev (sd) == (set (mem (plus (reg sp|fp) (const_int)))
9282 (reg rS1))
9283 curr (sd) == (set (mem (plus (reg sp|fp) (const_int)))
9284 (reg rS2)) */
9288 /* We can probably relax this condition. The documentation is a bit
9289 unclear about sub-word cases. So we just model DImode for now. */
9292 {
9298 /* Fail if we did not find both bases. */
9302 /* Fail if either base is not a register. */
9306 /* Fail if the bases are not the same register. */
9310 /* Originally the thought was to check MEM_ALIGN, but that was
9311 reporting incorrect alignments, even for SP/FP accesses, so we
9312 gave up on that approach. Instead just check for stack/hfp
9313 which we know are aligned. */
9318 /* The two stores must be contained within opposite halves of the
9319 same 16 byte aligned block of memory. We know that the stack
9320 pointer and the frame pointer have suitable alignment. So we
9321 just need to check the offsets of the two stores for suitable
9322 alignment. */
9323 /* Get the smaller offset into OFFSET_PREV. */
9327 /* If the smaller offset (OFFSET_PREV) is not 16 byte aligned,
9328 then fail. */
9332 /* The higher offset must be 8 bytes more than the lower
9333 offset. */
9335 }
9336 }
9339 }
9341 /* Adjust the cost/latency of instructions for scheduling.
9342 For now this is just used to change the latency of vector instructions
9343 according to their LMUL. We assume that an insn with LMUL == 8 requires
9344 eight times more execution cycles than the same insn with LMUL == 1.
9345 As this may cause very high latencies which lead to scheduling artifacts
9346 we currently only perform the adjustment when -madjust-lmul-cost is given.
9347 */
9348 static int
9351 {
9352 /* Only do adjustments for the generic out-of-order scheduling model. */
9362 {
9363 /* TODO: For ordered reductions scale the base cost relative to the
9364 number of units. */
9365 ;
9366 }
9368 /* Don't do any LMUL-based latency adjustment unless explicitly asked to. */
9372 /* vsetvl has a vlmul attribute but its latency does not depend on it. */
9381 {
9402 }
9404 /* If the latency was nonzero, keep it that way. */
9408 }
9410 /* Auxiliary function to emit RISC-V ELF attribute. */
9411 static void
9413 {
9422 }
9424 /* Output .variant_cc for function symbol which follows vector calling
9425 convention. */
9427 static void
9429 {
9431 {
9434 {
9438 }
9439 }
9440 }
9442 /* Implement ASM_DECLARE_FUNCTION_NAME. */
9444 void
9446 {
9451 {
9461 ? local_arch_str
9468 }
9469 }
9471 void
9473 {
9478 {
9480 }
9481 }
9483 /* Implement ASM_OUTPUT_DEF_FROM_DECLS. */
9485 void
9487 {
9492 }
9494 /* Implement ASM_OUTPUT_EXTERNAL. */
9496 void
9498 {
9501 }
9503 /* Implement TARGET_ASM_FILE_START. */
9505 static void
9507 {
9510 /* Instruct GAS to generate position-[in]dependent code. */
9513 /* If the user specifies "-mno-relax" on the command line then disable linker
9514 relaxation in the assembler. */
9518 /* If the user specifies "-mcsr-check" on the command line then enable csr
9519 check in the assembler. */
9525 }
9527 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
9528 in order to avoid duplicating too much logic from elsewhere. */
9530 static void
9533 tree function)
9534 {
9541 /* Pretend to be a post-reload pass while generating rtl. */
9544 /* Mark the end of the (empty) prologue. */
9547 /* Determine if we can use a sibcall to call FUNCTION directly. */
9550 /* We need two temporary registers in some cases. */
9554 /* Find out which register contains the "this" pointer. */
9557 else
9560 /* Add DELTA to THIS_RTX. */
9562 {
9565 {
9568 }
9570 }
9572 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */
9574 {
9575 rtx addr;
9577 /* Set TEMP1 to *THIS_RTX. */
9580 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */
9583 /* Load the offset and add it to THIS_RTX. */
9586 }
9588 /* Jump to the target function. */
9593 /* Run just enough of rest_of_compilation. This sequence was
9594 "borrowed" from alpha.cc. */
9604 /* Clean up the vars set above. Note that final_end_function resets
9605 the global pointer for us. */
9608 }
9610 /* Allocate a chunk of memory for per-function machine-dependent data. */
9614 {
9616 }
9618 /* Return the VLEN value associated with -march and -mwrvv-vector-bits.
9619 TODO: So far we only support length-agnostic value. */
9620 static poly_uint16
9622 {
9626 {
9627 /* When targeting minimum VLEN > 32, we should use 64-bit chunk size.
9628 Otherwise we can not include SEW = 64bits.
9629 Runtime invariant: The single indeterminate represent the
9630 number of 64-bit chunks in a vector beyond minimum length of 64 bits.
9631 Thus the number of bytes in a vector is 8 + 8 * x1 which is
9632 riscv_vector_chunks * 8 = poly_int (8, 8). */
9634 /* Adjust BYTES_PER_RISCV_VECTOR according to TARGET_MIN_VLEN:
9635 - TARGET_MIN_VLEN = 64bit: [8,8]
9636 - TARGET_MIN_VLEN = 128bit: [16,16]
9637 - TARGET_MIN_VLEN = 256bit: [32,32]
9638 - TARGET_MIN_VLEN = 512bit: [64,64]
9639 - TARGET_MIN_VLEN = 1024bit: [128,128]
9640 - TARGET_MIN_VLEN = 2048bit: [256,256]
9641 - TARGET_MIN_VLEN = 4096bit: [512,512]
9642 FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096bit. */
9644 }
9645 else
9646 {
9647 /* When targeting minimum VLEN = 32, we should use 32-bit
9648 chunk size. Runtime invariant: The single indeterminate represent the
9649 number of 32-bit chunks in a vector beyond minimum length of 32 bits.
9650 Thus the number of bytes in a vector is 4 + 4 * x1 which is
9651 riscv_vector_chunks * 4 = poly_int (4, 4). */
9654 }
9656 /* Set riscv_vector_chunks as poly (1, 1) run-time constant if TARGET_VECTOR
9657 is enabled. Set riscv_vector_chunks as 1 compile-time constant if
9658 TARGET_VECTOR is disabled. riscv_vector_chunks is used in "riscv-modes.def"
9659 to set RVV mode size. The RVV machine modes size are run-time constant if
9660 TARGET_VECTOR is enabled. The RVV machine modes size remains default
9661 compile-time constant if TARGET_VECTOR is disabled. */
9663 {
9665 {
9672 }
9673 }
9674 else
9676 }
9678 /* 'Unpack' up the internal tuning structs and update the options
9679 in OPTS. The caller must have set up selected_tune and selected_arch
9680 as all the other target-specific codegen decisions are
9681 derived from them. */
9682 void
9684 {
9687 /* The presence of the M extension implies that division instructions
9688 are present, so include them unless explicitly disabled. */
9694 /* We might use a multiplication to calculate the scalable vector length at
9695 runtime. Therefore, require the M extension. */
9699 /* Likewise floating-point division and square root. */
9704 /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune
9705 if both -mtune and -mcpu are not given. */
9710 ? &optimize_size_tune_info
9713 /* Use -mtune's setting for slow_unaligned_access, even when optimizing
9714 for size. For architectures that trap and emulate unaligned accesses,
9715 the performance cost is too great, even for -Os. Similarly, if
9716 -m[no-]strict-align is left unspecified, heed -mtune's advice. */
9720 /* By default, when -mno-vector-strict-align is not specified, do not allow
9721 unaligned vector memory accesses except if -mtune's setting explicitly
9722 allows it. */
9726 /* Make a note if user explicitly passed -mstrict-align for later
9727 builtin macro generation. Can't use target_flags_explicitly since
9728 it is set even for -mno-strict-align. */
9735 /* If the user hasn't specified a branch cost, use the processor's
9736 default. */
9740 /* FIXME: We don't allow TARGET_MIN_VLEN > 4096 since the datatypes of
9741 both GET_MODE_SIZE and GET_MODE_BITSIZE are poly_uint16.
9743 We can only allow TARGET_MIN_VLEN * 8 (LMUL) < 65535. */
9748 /* FIXME: We don't support RVV in big-endian for now, we may enable RVV with
9749 big-endian after finishing full coverage testing. */
9753 /* Convert -march and -mrvv-vector-bits to a chunks count. */
9755 }
9757 /* Implement TARGET_OPTION_OVERRIDE. */
9759 void
9761 {
9762 #ifdef SUBTARGET_OVERRIDE_OPTIONS
9763 SUBTARGET_OVERRIDE_OPTIONS;
9764 #endif
9771 /* Always prefer medlow than medany for RV32 since medlow can access
9772 full address space. */
9786 /* We need to save the fp with ra for non-leaf functions with no fp and ra
9787 for leaf functions while no-omit-frame-pointer with
9788 omit-leaf-frame-pointer. The x_flag_omit_frame_pointer has the first
9789 priority to determine whether the frame pointer is needed. If we do not
9790 override it, the fp and ra will be stored for leaf functions, which is not
9791 our wanted. */
9794 {
9799 }
9801 /* We get better code with explicit relocs for CM_MEDLOW, but
9802 worse code for the others (for now). Pick the best default. */
9807 /* Require that the ISA supports the requested floating-point ABI. */
9812 /* RVE requires specific ABI. */
9814 {
9819 }
9821 /* Zfinx require abi ilp32, ilp32e, lp64 or lp64e. */
9827 /* We do not yet support ILP32 on RV64. */
9831 /* Validate -mpreferred-stack-boundary= value. */
9834 {
9843 }
9846 #ifdef HAVE_AS_RISCV_ATTRIBUTE
9848 #else
9854 #endif
9858 {
9861 riscv_stack_protector_guard_offset_str);
9862 }
9867 {
9869 "%<-mstack-protector-guard-reg%> must be used "
9871 }
9874 {
9883 }
9886 {
9901 }
9904 param_sched_pressure_algorithm,
9905 SCHED_PRESSURE_MODEL);
9907 /* Function to allocate machine-dependent function status. */
9912 /* Save these options as the default ones in case we push and pop them later
9913 while processing functions with potential target attributes. */
9914 target_option_default_node = target_option_current_node
9916 }
9918 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
9919 Used by riscv_set_current_function to
9920 make sure optab availability predicates are recomputed when necessary. */
9922 void
9924 {
9929 else
9931 }
9933 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
9934 using the information saved in PTR. */
9936 static void
9940 {
9942 }
9946 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
9948 static void
9950 {
9951 /* We have only x0~x15 on RV32E/RV64E. */
9953 {
9956 }
9959 {
9962 }
9965 {
9968 }
9970 /* In the soft-float ABI, there are no callee-saved FP registers. */
9972 {
9975 }
9978 {
9986 }
9987 }
9989 /* Return a register priority for hard reg REGNO. */
9991 static int
9993 {
9994 /* Favor compressed registers to improve the odds of RVC instruction
9995 selection. */
10000 }
10002 /* Implement TARGET_TRAMPOLINE_INIT. */
10004 static void
10006 {
10012 /* Work out the offsets of the pointers from the start of the
10013 trampoline code. */
10016 /* Get pointers to the beginning and end of the code block. */
10023 {
10027 /* lui t2, hi(chain)
10028 lui t0, hi(func)
10029 addi t2, t2, lo(chain)
10030 jr t0, lo(func)
10031 */
10037 /* 0xfff. */
10043 /* Gen lui t2, hi(chain). */
10045 fixup_value);
10047 uimm_mask);
10055 /* Gen lui t0, hi(func). */
10057 fixup_value);
10059 uimm_mask);
10067 /* Gen addi t2, t2, lo(chain). */
10069 imm12_mask);
10072 lo_chain_code = OPCODE_ADDI
10082 /* Gen jr t0, lo(func). */
10084 imm12_mask);
10094 }
10095 else
10096 {
10100 /* auipc t2, 0
10101 l[wd] t0, target_function_offset(t2)
10102 l[wd] t2, static_chain_offset(t2)
10103 jr t0
10104 */
10116 /* Copy the trampoline code. */
10118 {
10123 }
10125 /* Set up the static chain pointer field. */
10129 /* Set up the target function field. */
10132 }
10134 /* Flush the code part of the trampoline. */
10137 }
10139 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */
10141 static bool
10143 tree exp ATTRIBUTE_UNUSED)
10144 {
10145 /* Don't use sibcalls when use save-restore routine. */
10149 /* Don't use sibcall for naked functions. */
10153 /* Don't use sibcall for interrupt functions. */
10157 /* Don't use sibcalls in the large model, because a sibcall instruction
10158 expanding and a epilogue expanding both use RISCV_PROLOGUE_TEMP
10159 register. */
10164 }
10166 /* Get the interrupt type, return UNKNOWN_MODE if it's not
10167 interrupt function. */
10168 static enum riscv_privilege_levels
10170 {
10177 tree attr_args
10182 {
10191 }
10192 else
10193 /* Interrupt attributes are machine mode by default. */
10195 }
10197 /* Implement `TARGET_SET_CURRENT_FUNCTION'. Unpack the codegen decisions
10198 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
10199 of the function, if such exists. This function may be called multiple
10200 times on a single function so use aarch64_previous_fndecl to avoid
10201 setting up identical state. */
10203 /* Sanity checking for above function attributes. */
10204 static void
10206 {
10214 {
10224 {
10237 }
10239 /* Don't print the above diagnostics more than once. */
10241 }
10246 tree old_tree = (riscv_previous_fndecl
10252 /* If current function has no attributes but the previous one did,
10253 use the default node. */
10257 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
10258 the default have been handled by aarch64_save_restore_target_globals from
10259 aarch64_pragma_target_parse. */
10265 /* First set the target options. */
10269 /* The ISA extension can vary based on the function extension like target.
10270 Thus, make sure that the machine modes are reflected correctly here. */
10274 }
10276 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */
10277 static tree
10279 {
10280 tree combined_attrs;
10282 enum riscv_privilege_levels old_interrupt_type
10284 enum riscv_privilege_levels new_interrupt_type
10287 /* Check old and new has same interrupt type. */
10293 /* Create combined attributes. */
10298 }
10300 /* Implement TARGET_CANNOT_COPY_INSN_P. */
10302 static bool
10304 {
10306 }
10308 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. */
10310 static bool
10312 {
10315 }
10317 static bool
10319 {
10321 }
10323 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
10325 static bool
10327 reg_class_t rclass)
10328 {
10329 /* We have RVV VLS modes and VLA modes sharing same REG_CLASS.
10330 In 'cprop_hardreg' stage, we will try to do hard reg copy propagation
10331 between wider mode (FROM) and narrow mode (TO).
10333 E.g. We should not allow copy propagation
10334 - RVVMF8BI (precision = [16, 16]) -> V32BI (precision = [32, 0])
10335 since we can't order their size which will cause ICE in regcprop.
10337 TODO: Even though they are have different size, they always change
10338 the whole register. We may enhance such case in regcprop to optimize
10339 it in the future. */
10344 }
10346 /* Implement TARGET_CONSTANT_ALIGNMENT. */
10348 static HOST_WIDE_INT
10350 {
10355 }
10357 /* Implement TARGET_PROMOTE_FUNCTION_MODE. */
10359 /* This function is equivalent to default_promote_function_mode_always_promote
10360 except that it returns a promoted mode even if type is NULL_TREE. This is
10361 needed by libcalls which have no type (only a mode) such as fixed conversion
10362 routines that take a signed or unsigned char/short/int argument and convert
10363 it to a fixed type. */
10365 static machine_mode
10367 machine_mode mode,
10369 const_tree fntype ATTRIBUTE_UNUSED,
10371 {
10382 }
10384 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */
10386 static void
10388 {
10389 /* Do nothing unless we have -msave-restore */
10392 }
10394 /* Return nonzero if register FROM_REGNO can be renamed to register
10395 TO_REGNO. */
10397 bool
10400 {
10401 /* Interrupt functions can only use registers that have already been
10402 saved by the prologue, even if they would normally be
10403 call-clobbered. */
10405 }
10407 /* Implement TARGET_NEW_ADDRESS_PROFITABLE_P. */
10409 bool
10411 {
10412 /* Prefer old address if it is less expensive. */
10418 }
10420 /* Helper function for generating gpr_save pattern. */
10422 rtx
10424 {
10426 /* 1 for unspec 2 for clobber t0/t1 and 1 for ra. */
10437 {
10440 rtx elt;
10442 /* t0 and t1 are CLOBBERs, others are USEs. */
10445 else
10449 }
10451 /* Largest number of caller-save register must set in mask if we are
10452 not using __riscv_save_0. */
10457 }
10459 static HOST_WIDE_INT
10461 {
10463 }
10465 static HOST_WIDE_INT
10467 {
10469 }
10471 bool
10473 {
10478 }
10480 /* Return true if it's valid gpr_save pattern. */
10482 bool
10484 {
10491 {
10494 {
10495 /* First element in parallel is unspec. */
10500 }
10501 else
10502 {
10503 /* Two CLOBBER and USEs, must check the order. */
10509 }
10511 }
10513 }
10515 /* Implement TARGET_ASAN_SHADOW_OFFSET. */
10517 static unsigned HOST_WIDE_INT
10519 {
10520 /* We only have libsanitizer support for RV64 at present.
10522 This number must match ASAN_SHADOW_OFFSET_CONST in the file
10523 libsanitizer/asan/asan_mapping.h. */
10525 }
10527 /* Implement TARGET_MANGLE_TYPE. */
10531 {
10532 /* Half-precision float, _Float16 is "DF16_" and __bf16 is "DF16b". */
10534 {
10542 }
10544 /* Mangle all vector type for vector extension. */
10545 /* The mangle name follows the rule of RVV LLVM
10546 that is "u" + length of (abi_name) + abi_name. */
10548 {
10552 }
10554 /* Use the default mangling. */
10556 }
10558 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
10560 static bool
10562 {
10565 else
10567 }
10569 /* Implement TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P - return TRUE
10570 if MODE is HFmode or BFmode, and punt to the generic implementation
10571 otherwise. */
10573 static bool
10575 {
10578 else
10580 }
10582 /* Set the value of FLT_EVAL_METHOD.
10583 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
10585 0: evaluate all operations and constants, whose semantic type has at
10586 most the range and precision of type float, to the range and
10587 precision of float; evaluate all other operations and constants to
10588 the range and precision of the semantic type;
10590 N, where _FloatN is a supported interchange floating type
10591 evaluate all operations and constants, whose semantic type has at
10592 most the range and precision of _FloatN type, to the range and
10593 precision of the _FloatN type; evaluate all other operations and
10594 constants to the range and precision of the semantic type;
10596 If we have the zfh/zhinx/zvfh extensions then we support _Float16
10597 in native precision, so we should set this to 16. */
10598 static enum flt_eval_method
10600 {
10602 {
10606 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
10613 }
10615 }
10617 /* Implement TARGET_FLOATN_MODE. */
10618 static opt_scalar_float_mode
10620 {
10625 }
10627 /* Record that we have no arithmetic or comparison libfuncs for
10628 machine_mode MODE. */
10629 static void
10631 {
10632 /* Half-precision float or Brain float operations. The compiler handles all
10633 operations with NULL libfuncs by converting to SFmode. */
10635 /* Arithmetic. */
10642 /* Comparisons. */
10650 }
10652 static void
10654 {
10658 /* Convert between BFmode and HFmode using only trunc libfunc if needed. */
10663 }
10665 #if CHECKING_P
10666 void
10668 {
10674 }
10675 #endif
10677 #if CHECKING_P
10678 #undef TARGET_RUN_TARGET_SELFTESTS
10679 #define TARGET_RUN_TARGET_SELFTESTS selftest::riscv_run_selftests
10682 /* Implement TARGET_VECTOR_MODE_SUPPORTED_P. */
10684 static bool
10686 {
10691 }
10693 /* Implement TARGET_VERIFY_TYPE_CONTEXT. */
10695 static bool
10698 {
10700 }
10702 /* Implement TARGET_VECTOR_ALIGNMENT. */
10704 static HOST_WIDE_INT
10706 {
10707 /* ??? Checking the mode isn't ideal, but VECTOR_BOOLEAN_TYPE_P can
10708 be set for non-predicate vectors of booleans. Modes are the most
10709 direct way we have of identifying real RVV predicate types. */
10710 /* FIXME: RVV didn't mention the alignment of bool, we uses
10711 one byte align. */
10715 widest_int min_size
10718 }
10720 /* Implement REGMODE_NATURAL_SIZE. */
10722 poly_uint64
10724 {
10725 /* The natural size for RVV data modes is one RVV data vector,
10726 and similarly for predicates. We can't independently modify
10727 anything smaller than that. */
10728 /* ??? For now, only do this for variable-width RVV registers.
10729 Doing it for constant-sized registers breaks lower-subreg.c. */
10732 {
10735 {
10739 }
10741 {
10742 /* RVV mask modes always consume a single register. */
10745 }
10749 /* For -march=rv64gc_zve32f, the natural vector register size
10750 is 32bits which is smaller than scalar register size, so we
10751 return minimum size between vector register size and scalar
10752 register size. */
10754 }
10756 }
10758 /* Implement the TARGET_DWARF_POLY_INDETERMINATE_VALUE hook. */
10760 static unsigned int
10763 {
10764 /* Polynomial invariant 1 == (VLENB / riscv_bytes_per_vector_chunk) - 1.
10765 1. TARGET_MIN_VLEN == 32, polynomial invariant 1 == (VLENB / 4) - 1.
10766 2. TARGET_MIN_VLEN > 32, polynomial invariant 1 == (VLENB / 8) - 1.
10767 */
10772 }
10774 /* Implement TARGET_ESTIMATED_POLY_VALUE. */
10776 static HOST_WIDE_INT
10779 {
10783 }
10785 /* Return true if the vector misalignment factor is supported by the
10786 target. */
10787 bool
10789 const_tree type ATTRIBUTE_UNUSED,
10792 {
10793 /* Depend on movmisalign pattern. */
10795 is_packed);
10796 }
10798 /* Implement TARGET_VECTORIZE_GET_MASK_MODE. */
10800 static opt_machine_mode
10802 {
10807 }
10809 /* Implement TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE. Assume for now that
10810 it isn't worth branching around empty masked ops (including masked
10811 stores). */
10813 static bool
10815 {
10817 }
10819 /* Return true if a shift-amount matches the trailing cleared bits on
10820 a bitmask. */
10822 bool
10824 {
10826 }
10828 static HARD_REG_SET
10830 {
10831 HARD_REG_SET zeroed_hardregs;
10834 /* Find a register to hold vl. */
10836 /* Skip the first GPR, otherwise the existing vl is kept due to the same
10837 between vl and avl. */
10839 {
10841 {
10844 }
10845 }
10851 /* Vector configurations need not be saved and restored here. The
10852 -fzero-call-used-regs=* option will zero all vector registers and
10853 return. So there's no vector operations between them. */
10858 {
10860 {
10865 {
10868 }
10875 }
10876 }
10879 }
10881 /* Generate a sequence of instructions that zero registers specified by
10882 NEED_ZEROED_HARDREGS. Return the ZEROED_HARDREGS that are actually
10883 zeroed. */
10884 HARD_REG_SET
10886 {
10887 HARD_REG_SET zeroed_hardregs;
10895 }
10897 /* Implement target hook TARGET_ARRAY_MODE. */
10899 static opt_machine_mode
10901 {
10902 machine_mode vmode;
10908 }
10910 /* Given memory reference MEM, expand code to compute the aligned
10911 memory address, shift and mask values and store them into
10912 *ALIGNED_MEM, *SHIFT, *MASK and *NOT_MASK. */
10914 void
10917 {
10918 /* Align the memory address to a word. */
10928 /* Calculate the shift amount. */
10934 /* Calculate the mask. */
10943 }
10945 /* Leftshift a subword within an SImode register. */
10947 void
10950 {
10957 }
10959 /* Return TRUE if we should use the divmod expander, FALSE otherwise. This
10960 allows the behavior to be tuned for specific implementations as well as
10961 when optimizing for size. */
10963 bool
10965 {
10967 }
10969 /* Implement TARGET_VECTORIZE_PREFERRED_SIMD_MODE. */
10971 static machine_mode
10973 {
10978 }
10980 /* Implement target hook TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT. */
10982 static poly_uint64
10984 {
10988 }
10990 /* Return true if it is static FRM rounding mode. */
10992 static bool
10994 {
10996 {
11005 }
11008 }
11010 /* Implement the floating-point Mode Switching. */
11012 static void
11014 {
11021 {
11026 /* No need to emit when prev mode is DYN already. */
11031 /* No need to emit when prev mode is DYN or DYN_CALL already. */
11035 /* Restore frm value from backup when switch to DYN mode. */
11038 /* Set frm value when switch to static mode. */
11040 }
11041 }
11043 /* Implement Mode switching. */
11045 static void
11047 HARD_REG_SET regs_live ATTRIBUTE_UNUSED)
11048 {
11050 {
11060 }
11061 }
11063 /* Adjust the FRM_NONE insn after a call to FRM_DYN for the
11064 underlying emit. */
11066 static int
11068 {
11075 }
11077 /* Insert the backup frm insn to the end of the bb if and only if the call
11078 is the last insn of this bb. */
11080 static void
11082 {
11083 edge eg;
11085 edge_iterator eg_iterator;
11089 {
11092 else
11093 {
11100 }
11101 }
11104 {
11111 }
11114 }
11116 /* Return mode that frm must be switched into
11117 prior to the execution of insn. */
11119 static int
11121 {
11123 {
11124 /* The dynamic frm will be initialized only onece during cfun. */
11127 }
11130 {
11137 }
11142 /* After meet a call, we need to backup the frm because it may be
11143 updated during the call. Here, for each insn, we will check if
11144 the previous insn is a call or not. When previous insn is call,
11145 there will be 2 cases for the emit mode set.
11147 1. Current insn is not MODE_NONE, then the mode switch framework
11148 will do the mode switch from MODE_CALL to MODE_NONE natively.
11149 2. Current insn is MODE_NONE, we need to adjust the MODE_NONE to
11150 the MODE_DYN, and leave the mode switch itself to perform
11151 the emit mode set.
11152 */
11156 }
11158 /* Return mode that entity must be switched into
11159 prior to the execution of insn. */
11161 static int
11163 {
11167 {
11174 }
11175 }
11177 /* Return TRUE that an insn is asm. */
11179 static bool
11181 {
11185 }
11187 /* Return TRUE that an insn is unknown for VXRM. */
11189 static bool
11191 {
11192 /* Return true if there is a definition of VXRM. */
11196 /* A CALL function may contain an instruction that modifies the VXRM,
11197 return true in this situation. */
11201 /* Return true for all assembly since users may hardcode a assembly
11202 like this: asm volatile ("csrwi vxrm, 0"). */
11207 }
11209 /* Return TRUE that an insn is unknown dynamic for FRM. */
11211 static bool
11213 {
11214 /* Return true if there is a definition of FRM. */
11219 }
11221 /* Return the mode that an insn results in for VXRM. */
11223 static int
11225 {
11234 else
11236 }
11238 /* Return the mode that an insn results in for FRM. */
11240 static int
11242 {
11256 else
11258 }
11260 /* Return the mode that an insn results in. */
11262 static int
11264 {
11266 {
11273 }
11274 }
11276 /* Return a mode that ENTITY is assumed to be
11277 switched to at function entry. */
11279 static int
11281 {
11283 {
11287 {
11288 /* According to RVV 1.0 spec, all vector floating-point operations use
11289 the dynamic rounding mode in the frm register. Likewise in other
11290 similar places. */
11292 }
11295 }
11296 }
11298 /* Return a mode that ENTITY is assumed to be
11299 switched to at function exit. */
11301 static int
11303 {
11305 {
11312 }
11313 }
11315 static int
11317 {
11319 }
11321 /* Implement TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES. */
11322 unsigned int
11324 {
11329 }
11331 /* Implement TARGET_VECTORIZE_RELATED_MODE. */
11332 opt_machine_mode
11334 poly_uint64 nunits)
11335 {
11338 nunits);
11340 }
11342 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
11344 static bool
11348 {
11354 }
11356 static bool
11358 {
11360 }
11362 /* Return the appropriate common costs according to VECTYPE from COSTS. */
11365 {
11371 }
11373 /* Return the CPU vector costs according to -mtune if tune info has non-NULL
11374 vector cost. Otherwise, return the default generic vector costs. */
11377 {
11382 }
11384 /* Implement targetm.vectorize.builtin_vectorization_cost. */
11386 static int
11389 {
11399 {
11451 }
11454 }
11456 /* Implement targetm.vectorize.create_costs. */
11460 {
11463 /* Default vector costs. */
11465 }
11467 /* Implement TARGET_PREFERRED_ELSE_VALUE. */
11469 static tree
11472 {
11474 {
11478 }
11481 }
11483 /* If MEM is in the form of "base+offset", extract the two parts
11484 of address and set to BASE and OFFSET, otherwise return false
11485 after clearing BASE and OFFSET. */
11487 bool
11489 {
11490 rtx addr;
11497 {
11501 }
11505 {
11509 }
11515 }
11517 /* Implements target hook vector_mode_supported_any_target_p. */
11519 static bool
11521 {
11525 }
11527 /* Implements hook TARGET_FUNCTION_VALUE_REGNO_P. */
11529 static bool
11531 {
11542 }
11544 /* Implements hook TARGET_GET_RAW_RESULT_MODE. */
11546 static fixed_size_mode
11548 {
11553 }
11555 /* Implements the unsigned saturation add standard name usadd for int mode.
11557 z = SAT_ADD(x, y).
11558 =>
11559 1. sum = x + y.
11560 2. sum = truncate (sum) for QI and HI only.
11561 3. lt = sum < x.
11562 4. lt = -lt.
11563 5. z = sum | lt. */
11565 void
11567 {
11575 /* Step-1: sum = x + y */
11581 }
11582 else
11585 /* Step-1.1: truncate sum for HI and QI as we have no insn for add QI/HI. */
11587 {
11595 }
11597 /* Step-2: lt = sum < x */
11600 /* Step-3: lt = -lt */
11603 /* Step-4: xmode_dest = sum | lt */
11606 /* Step-5: dest = xmode_dest */
11608 }
11610 /* Implements the unsigned saturation sub standard name usadd for int mode.
11612 z = SAT_SUB(x, y).
11613 =>
11614 1. minus = x - y.
11615 2. lt = x < y.
11616 3. lt = lt - 1.
11617 4. z = minus & lt. */
11619 void
11621 {
11629 /* Step-1: minus = x - y */
11632 /* Step-2: lt = x < y */
11635 /* Step-3: lt = lt - 1 (lt + (-1)) */
11638 /* Step-4: xmode_dest = minus & lt */
11641 /* Step-5: dest = xmode_dest */
11643 }
11645 /* Implement the unsigned saturation truncation for int mode.
11647 b = SAT_TRUNC (a);
11648 =>
11649 1. max = half truncated max
11650 2. lt = a < max
11651 3. lt = lt - 1 (lt 0, ge -1)
11652 4. d = a | lt
11653 5. b = (trunc)d */
11655 void
11657 {
11669 /* Step-1: max = half truncated max */
11672 /* Step-2: lt = src < max */
11675 /* Step-3: lt = lt - 1 */
11678 /* Step-4: xmode_dest = lt | src */
11681 /* Step-5: dest = xmode_dest */
11683 }
11685 /* Implement TARGET_C_MODE_FOR_FLOATING_TYPE. Return TFmode for
11686 TI_LONG_DOUBLE_TYPE which is for long double type, go with the
11687 default one for the others. */
11689 static machine_mode
11691 {
11695 }
11697 /* Initialize the GCC target structure. */
11698 #undef TARGET_ASM_ALIGNED_HI_OP
11700 #undef TARGET_ASM_ALIGNED_SI_OP
11702 #undef TARGET_ASM_ALIGNED_DI_OP
11705 #undef TARGET_OPTION_OVERRIDE
11706 #define TARGET_OPTION_OVERRIDE riscv_option_override
11708 #undef TARGET_OPTION_RESTORE
11709 #define TARGET_OPTION_RESTORE riscv_option_restore
11711 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
11712 #define TARGET_OPTION_VALID_ATTRIBUTE_P riscv_option_valid_attribute_p
11714 #undef TARGET_LEGITIMIZE_ADDRESS
11715 #define TARGET_LEGITIMIZE_ADDRESS riscv_legitimize_address
11717 #undef TARGET_SCHED_ISSUE_RATE
11718 #define TARGET_SCHED_ISSUE_RATE riscv_issue_rate
11719 #undef TARGET_SCHED_MACRO_FUSION_P
11720 #define TARGET_SCHED_MACRO_FUSION_P riscv_macro_fusion_p
11721 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
11722 #define TARGET_SCHED_MACRO_FUSION_PAIR_P riscv_macro_fusion_pair_p
11724 #undef TARGET_SCHED_VARIABLE_ISSUE
11725 #define TARGET_SCHED_VARIABLE_ISSUE riscv_sched_variable_issue
11727 #undef TARGET_SCHED_ADJUST_COST
11728 #define TARGET_SCHED_ADJUST_COST riscv_sched_adjust_cost
11730 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
11731 #define TARGET_FUNCTION_OK_FOR_SIBCALL riscv_function_ok_for_sibcall
11733 #undef TARGET_SET_CURRENT_FUNCTION
11734 #define TARGET_SET_CURRENT_FUNCTION riscv_set_current_function
11736 #undef TARGET_REGISTER_MOVE_COST
11737 #define TARGET_REGISTER_MOVE_COST riscv_register_move_cost
11738 #undef TARGET_MEMORY_MOVE_COST
11739 #define TARGET_MEMORY_MOVE_COST riscv_memory_move_cost
11740 #undef TARGET_RTX_COSTS
11741 #define TARGET_RTX_COSTS riscv_rtx_costs
11742 #undef TARGET_ADDRESS_COST
11743 #define TARGET_ADDRESS_COST riscv_address_cost
11744 #undef TARGET_INSN_COST
11745 #define TARGET_INSN_COST riscv_insn_cost
11747 #undef TARGET_MAX_NOCE_IFCVT_SEQ_COST
11748 #define TARGET_MAX_NOCE_IFCVT_SEQ_COST riscv_max_noce_ifcvt_seq_cost
11749 #undef TARGET_NOCE_CONVERSION_PROFITABLE_P
11750 #define TARGET_NOCE_CONVERSION_PROFITABLE_P riscv_noce_conversion_profitable_p
11752 #undef TARGET_ASM_FILE_START
11753 #define TARGET_ASM_FILE_START riscv_file_start
11754 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
11755 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
11756 #undef TARGET_ASM_FILE_END
11757 #define TARGET_ASM_FILE_END file_end_indicate_exec_stack
11759 #undef TARGET_EXPAND_BUILTIN_VA_START
11760 #define TARGET_EXPAND_BUILTIN_VA_START riscv_va_start
11762 #undef TARGET_PROMOTE_FUNCTION_MODE
11763 #define TARGET_PROMOTE_FUNCTION_MODE riscv_promote_function_mode
11765 #undef TARGET_RETURN_IN_MEMORY
11766 #define TARGET_RETURN_IN_MEMORY riscv_return_in_memory
11768 #undef TARGET_ASM_OUTPUT_MI_THUNK
11769 #define TARGET_ASM_OUTPUT_MI_THUNK riscv_output_mi_thunk
11770 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
11771 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
11773 #undef TARGET_PRINT_OPERAND
11774 #define TARGET_PRINT_OPERAND riscv_print_operand
11775 #undef TARGET_PRINT_OPERAND_ADDRESS
11776 #define TARGET_PRINT_OPERAND_ADDRESS riscv_print_operand_address
11777 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
11778 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P riscv_print_operand_punct_valid_p
11780 #undef TARGET_SETUP_INCOMING_VARARGS
11781 #define TARGET_SETUP_INCOMING_VARARGS riscv_setup_incoming_varargs
11782 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS
11783 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS riscv_allocate_stack_slots_for_args
11784 #undef TARGET_STRICT_ARGUMENT_NAMING
11785 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
11786 #undef TARGET_MUST_PASS_IN_STACK
11787 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
11788 #undef TARGET_PASS_BY_REFERENCE
11789 #define TARGET_PASS_BY_REFERENCE riscv_pass_by_reference
11790 #undef TARGET_ARG_PARTIAL_BYTES
11791 #define TARGET_ARG_PARTIAL_BYTES riscv_arg_partial_bytes
11792 #undef TARGET_FUNCTION_ARG
11793 #define TARGET_FUNCTION_ARG riscv_function_arg
11794 #undef TARGET_FUNCTION_ARG_ADVANCE
11795 #define TARGET_FUNCTION_ARG_ADVANCE riscv_function_arg_advance
11796 #undef TARGET_FUNCTION_ARG_BOUNDARY
11797 #define TARGET_FUNCTION_ARG_BOUNDARY riscv_function_arg_boundary
11798 #undef TARGET_FNTYPE_ABI
11799 #define TARGET_FNTYPE_ABI riscv_fntype_abi
11800 #undef TARGET_INSN_CALLEE_ABI
11801 #define TARGET_INSN_CALLEE_ABI riscv_insn_callee_abi
11803 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
11804 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
11805 riscv_get_separate_components
11807 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
11808 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
11809 riscv_components_for_bb
11811 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
11812 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
11813 riscv_disqualify_components
11815 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
11816 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
11817 riscv_emit_prologue_components
11819 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
11820 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
11821 riscv_emit_epilogue_components
11823 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
11824 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
11825 riscv_set_handled_components
11827 /* The generic ELF target does not always have TLS support. */
11828 #ifdef HAVE_AS_TLS
11829 #undef TARGET_HAVE_TLS
11830 #define TARGET_HAVE_TLS true
11831 #endif
11833 #undef TARGET_CANNOT_FORCE_CONST_MEM
11834 #define TARGET_CANNOT_FORCE_CONST_MEM riscv_cannot_force_const_mem
11836 #undef TARGET_LEGITIMATE_CONSTANT_P
11837 #define TARGET_LEGITIMATE_CONSTANT_P riscv_legitimate_constant_p
11839 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
11840 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P riscv_use_blocks_for_constant_p
11842 #undef TARGET_LEGITIMATE_ADDRESS_P
11843 #define TARGET_LEGITIMATE_ADDRESS_P riscv_legitimate_address_p
11845 #undef TARGET_CAN_ELIMINATE
11846 #define TARGET_CAN_ELIMINATE riscv_can_eliminate
11848 #undef TARGET_CONDITIONAL_REGISTER_USAGE
11849 #define TARGET_CONDITIONAL_REGISTER_USAGE riscv_conditional_register_usage
11851 #undef TARGET_CLASS_MAX_NREGS
11852 #define TARGET_CLASS_MAX_NREGS riscv_class_max_nregs
11854 #undef TARGET_TRAMPOLINE_INIT
11855 #define TARGET_TRAMPOLINE_INIT riscv_trampoline_init
11857 #undef TARGET_IN_SMALL_DATA_P
11858 #define TARGET_IN_SMALL_DATA_P riscv_in_small_data_p
11860 #undef TARGET_HAVE_SRODATA_SECTION
11861 #define TARGET_HAVE_SRODATA_SECTION true
11863 #undef TARGET_ASM_SELECT_SECTION
11864 #define TARGET_ASM_SELECT_SECTION riscv_select_section
11866 #undef TARGET_ASM_UNIQUE_SECTION
11867 #define TARGET_ASM_UNIQUE_SECTION riscv_unique_section
11869 #undef TARGET_ASM_SELECT_RTX_SECTION
11870 #define TARGET_ASM_SELECT_RTX_SECTION riscv_elf_select_rtx_section
11872 #undef TARGET_MIN_ANCHOR_OFFSET
11873 #define TARGET_MIN_ANCHOR_OFFSET (-IMM_REACH/2)
11875 #undef TARGET_MAX_ANCHOR_OFFSET
11876 #define TARGET_MAX_ANCHOR_OFFSET (IMM_REACH/2-1)
11878 #undef TARGET_REGISTER_PRIORITY
11879 #define TARGET_REGISTER_PRIORITY riscv_register_priority
11881 #undef TARGET_CANNOT_COPY_INSN_P
11882 #define TARGET_CANNOT_COPY_INSN_P riscv_cannot_copy_insn_p
11884 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
11885 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV riscv_atomic_assign_expand_fenv
11887 #undef TARGET_INIT_BUILTINS
11888 #define TARGET_INIT_BUILTINS riscv_init_builtins
11890 #undef TARGET_BUILTIN_DECL
11891 #define TARGET_BUILTIN_DECL riscv_builtin_decl
11893 #undef TARGET_GIMPLE_FOLD_BUILTIN
11894 #define TARGET_GIMPLE_FOLD_BUILTIN riscv_gimple_fold_builtin
11896 #undef TARGET_EXPAND_BUILTIN
11897 #define TARGET_EXPAND_BUILTIN riscv_expand_builtin
11899 #undef TARGET_HARD_REGNO_NREGS
11900 #define TARGET_HARD_REGNO_NREGS riscv_hard_regno_nregs
11901 #undef TARGET_HARD_REGNO_MODE_OK
11902 #define TARGET_HARD_REGNO_MODE_OK riscv_hard_regno_mode_ok
11904 #undef TARGET_MODES_TIEABLE_P
11905 #define TARGET_MODES_TIEABLE_P riscv_modes_tieable_p
11907 #undef TARGET_SLOW_UNALIGNED_ACCESS
11908 #define TARGET_SLOW_UNALIGNED_ACCESS riscv_slow_unaligned_access
11910 #undef TARGET_OVERLAP_OP_BY_PIECES_P
11911 #define TARGET_OVERLAP_OP_BY_PIECES_P riscv_overlap_op_by_pieces
11913 #undef TARGET_SECONDARY_MEMORY_NEEDED
11914 #define TARGET_SECONDARY_MEMORY_NEEDED riscv_secondary_memory_needed
11916 #undef TARGET_CAN_CHANGE_MODE_CLASS
11917 #define TARGET_CAN_CHANGE_MODE_CLASS riscv_can_change_mode_class
11919 #undef TARGET_CONSTANT_ALIGNMENT
11920 #define TARGET_CONSTANT_ALIGNMENT riscv_constant_alignment
11922 #undef TARGET_MERGE_DECL_ATTRIBUTES
11923 #define TARGET_MERGE_DECL_ATTRIBUTES riscv_merge_decl_attributes
11925 #undef TARGET_ATTRIBUTE_TABLE
11926 #define TARGET_ATTRIBUTE_TABLE riscv_attribute_table
11928 #undef TARGET_WARN_FUNC_RETURN
11929 #define TARGET_WARN_FUNC_RETURN riscv_warn_func_return
11931 /* The low bit is ignored by jump instructions so is safe to use. */
11932 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
11933 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
11935 #undef TARGET_MACHINE_DEPENDENT_REORG
11936 #define TARGET_MACHINE_DEPENDENT_REORG riscv_reorg
11938 #undef TARGET_NEW_ADDRESS_PROFITABLE_P
11939 #define TARGET_NEW_ADDRESS_PROFITABLE_P riscv_new_address_profitable_p
11941 #undef TARGET_MANGLE_TYPE
11942 #define TARGET_MANGLE_TYPE riscv_mangle_type
11944 #undef TARGET_SCALAR_MODE_SUPPORTED_P
11945 #define TARGET_SCALAR_MODE_SUPPORTED_P riscv_scalar_mode_supported_p
11947 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
11948 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
11949 riscv_libgcc_floating_mode_supported_p
11951 #undef TARGET_INIT_LIBFUNCS
11952 #define TARGET_INIT_LIBFUNCS riscv_init_libfuncs
11954 #undef TARGET_C_EXCESS_PRECISION
11955 #define TARGET_C_EXCESS_PRECISION riscv_excess_precision
11957 #undef TARGET_FLOATN_MODE
11958 #define TARGET_FLOATN_MODE riscv_floatn_mode
11960 #undef TARGET_ASAN_SHADOW_OFFSET
11961 #define TARGET_ASAN_SHADOW_OFFSET riscv_asan_shadow_offset
11963 #ifdef TARGET_BIG_ENDIAN_DEFAULT
11964 #undef TARGET_DEFAULT_TARGET_FLAGS
11965 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_ENDIAN)
11966 #endif
11968 #undef TARGET_VECTOR_MODE_SUPPORTED_P
11969 #define TARGET_VECTOR_MODE_SUPPORTED_P riscv_vector_mode_supported_p
11971 #undef TARGET_VERIFY_TYPE_CONTEXT
11972 #define TARGET_VERIFY_TYPE_CONTEXT riscv_verify_type_context
11974 #undef TARGET_ESTIMATED_POLY_VALUE
11975 #define TARGET_ESTIMATED_POLY_VALUE riscv_estimated_poly_value
11977 #undef TARGET_VECTORIZE_GET_MASK_MODE
11978 #define TARGET_VECTORIZE_GET_MASK_MODE riscv_get_mask_mode
11980 #undef TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE
11981 #define TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE riscv_empty_mask_is_expensive
11983 #undef TARGET_VECTOR_ALIGNMENT
11984 #define TARGET_VECTOR_ALIGNMENT riscv_vector_alignment
11986 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
11987 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT riscv_support_vector_misalignment
11989 #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
11990 #define TARGET_DWARF_POLY_INDETERMINATE_VALUE riscv_dwarf_poly_indeterminate_value
11992 #undef TARGET_ZERO_CALL_USED_REGS
11993 #define TARGET_ZERO_CALL_USED_REGS riscv_zero_call_used_regs
11995 #undef TARGET_ARRAY_MODE
11996 #define TARGET_ARRAY_MODE riscv_array_mode
11998 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
11999 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE riscv_preferred_simd_mode
12001 #undef TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT
12002 #define TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT \
12003 riscv_vectorize_preferred_vector_alignment
12005 /* Mode switching hooks. */
12007 #undef TARGET_MODE_EMIT
12008 #define TARGET_MODE_EMIT riscv_emit_mode_set
12009 #undef TARGET_MODE_NEEDED
12010 #define TARGET_MODE_NEEDED riscv_mode_needed
12011 #undef TARGET_MODE_AFTER
12012 #define TARGET_MODE_AFTER riscv_mode_after
12013 #undef TARGET_MODE_ENTRY
12014 #define TARGET_MODE_ENTRY riscv_mode_entry
12015 #undef TARGET_MODE_EXIT
12016 #define TARGET_MODE_EXIT riscv_mode_exit
12017 #undef TARGET_MODE_PRIORITY
12018 #define TARGET_MODE_PRIORITY riscv_mode_priority
12020 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES
12021 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES \
12022 riscv_autovectorize_vector_modes
12024 #undef TARGET_VECTORIZE_RELATED_MODE
12025 #define TARGET_VECTORIZE_RELATED_MODE riscv_vectorize_related_mode
12027 #undef TARGET_VECTORIZE_VEC_PERM_CONST
12028 #define TARGET_VECTORIZE_VEC_PERM_CONST riscv_vectorize_vec_perm_const
12030 #undef TARGET_FRAME_POINTER_REQUIRED
12031 #define TARGET_FRAME_POINTER_REQUIRED riscv_frame_pointer_required
12033 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
12034 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
12035 riscv_builtin_vectorization_cost
12037 #undef TARGET_VECTORIZE_CREATE_COSTS
12038 #define TARGET_VECTORIZE_CREATE_COSTS riscv_vectorize_create_costs
12040 #undef TARGET_PREFERRED_ELSE_VALUE
12041 #define TARGET_PREFERRED_ELSE_VALUE riscv_preferred_else_value
12043 #undef TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P
12044 #define TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P riscv_vector_mode_supported_any_target_p
12046 #undef TARGET_FUNCTION_VALUE_REGNO_P
12047 #define TARGET_FUNCTION_VALUE_REGNO_P riscv_function_value_regno_p
12049 #undef TARGET_GET_RAW_RESULT_MODE
12050 #define TARGET_GET_RAW_RESULT_MODE riscv_get_raw_result_mode
12052 #undef TARGET_C_MODE_FOR_FLOATING_TYPE
12053 #define TARGET_C_MODE_FOR_FLOATING_TYPE riscv_c_mode_for_floating_type