gcc/config/riscv/riscv-v.h

   1 /* Subroutines used for code generation for RISC-V 'V' Extension for
   2    GNU compiler.
   3    Copyright (C) 2022-2024 Free Software Foundation, Inc.
   4    Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
   5
   6    This file is part of GCC.
   7
   8    GCC is free software; you can redistribute it and/or modify it
   9    under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3, or (at your option)
  11    any later version.
  12
  13    GCC is distributed in the hope that it will be useful, but
  14    WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16    General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with GCC; see the file COPYING3.  If not see
  20    <http://www.gnu.org/licenses/>.  */
  21
  22 #ifndef GCC_RISCV_V_H
  23 #define GCC_RISCV_V_H
  24
  25 #include "rtx-vector-builder.h"
  26
  27 using namespace riscv_vector;
  28
  29 namespace riscv_vector {
  30
  31 extern machine_mode get_mask_mode (machine_mode);
  32 extern opt_machine_mode get_vector_mode (scalar_mode, poly_uint64);
  33
  34 class rvv_builder : public rtx_vector_builder
  35 {
  36 public:
  37   rvv_builder () : rtx_vector_builder () {}
  38   rvv_builder (machine_mode mode, unsigned int npatterns,
  39                unsigned int nelts_per_pattern)
  40     : rtx_vector_builder (mode, npatterns, nelts_per_pattern)
  41   {
  42     m_inner_mode = GET_MODE_INNER (mode);
  43     m_inner_bits_size = GET_MODE_BITSIZE (m_inner_mode);
  44     m_inner_bytes_size = GET_MODE_SIZE (m_inner_mode);
  45     m_mask_mode = get_mask_mode (mode);
  46
  47     gcc_assert (
  48       int_mode_for_size (inner_bits_size (), 0).exists (&m_inner_int_mode));
  49     m_int_mode
  50       = get_vector_mode (m_inner_int_mode, GET_MODE_NUNITS (mode)).require ();
  51   }
  52
  53   bool can_duplicate_repeating_sequence_p ();
  54   bool is_repeating_sequence ();
  55   rtx get_merged_repeating_sequence ();
  56
  57   bool repeating_sequence_use_merge_profitable_p ();
  58   bool combine_sequence_use_slideup_profitable_p ();
  59   bool combine_sequence_use_merge_profitable_p ();
  60   rtx get_merge_scalar_mask (unsigned int, machine_mode) const;
  61
  62   bool single_step_npatterns_p () const;
  63   bool npatterns_all_equal_p () const;
  64   bool interleaved_stepped_npatterns_p () const;
  65   bool npatterns_vid_diff_repeated_p () const;
  66
  67   machine_mode new_mode () const { return m_new_mode; }
  68   scalar_mode inner_mode () const { return m_inner_mode; }
  69   scalar_int_mode inner_int_mode () const { return m_inner_int_mode; }
  70   machine_mode mask_mode () const { return m_mask_mode; }
  71   machine_mode int_mode () const { return m_int_mode; }
  72   unsigned int inner_bits_size () const { return m_inner_bits_size; }
  73   unsigned int inner_bytes_size () const { return m_inner_bytes_size; }
  74
  75 private:
  76   scalar_mode m_inner_mode;
  77   scalar_int_mode m_inner_int_mode;
  78   machine_mode m_new_mode;
  79   scalar_int_mode m_new_inner_mode;
  80   machine_mode m_mask_mode;
  81   machine_mode m_int_mode;
  82   unsigned int m_inner_bits_size;
  83   unsigned int m_inner_bytes_size;
  84 };
  85
  86 extern bool valid_vec_immediate_p(rtx);
  87
  88 } // namespace riscv_vector
  89
  90 #endif // GCC_RISCV_V_H