| blob | e2db8f3113079d26fe2c0076ab3ebab72270402a |
1 ;; Machine description for CORE-V vendor extensions.
2 ;; Copyright (C) 2023-2024 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
9 ;; any later version.
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 (define_c_enum "unspec" [
22 ;;CORE-V ALU
23 UNSPEC_CV_ALU_CLIP
24 UNSPEC_CV_ALU_CLIPR
25 UNSPEC_CV_ALU_CLIPU
26 UNSPEC_CV_ALU_CLIPUR
28 ;;CORE-V EVENT LOAD
29 UNSPECV_CV_ELW
31 ;;CORE-V SIMD
32 ;;CORE-V SIMD ALU
33 UNSPEC_CV_ADD_H
34 UNSPEC_CV_ADD_B
35 UNSPEC_CV_ADD_SC_H
36 UNSPEC_CV_ADD_SC_B
37 UNSPEC_CV_SUB_H
38 UNSPEC_CV_SUB_B
39 UNSPEC_CV_SUB_SC_H
40 UNSPEC_CV_SUB_SC_B
41 UNSPEC_CV_AVG_H
42 UNSPEC_CV_AVG_B
43 UNSPEC_CV_AVG_SC_H
44 UNSPEC_CV_AVG_SC_B
45 UNSPEC_CV_AVGU_H
46 UNSPEC_CV_AVGU_B
47 UNSPEC_CV_AVGU_SC_H
48 UNSPEC_CV_AVGU_SC_B
49 UNSPEC_CV_MIN_H
50 UNSPEC_CV_MIN_B
51 UNSPEC_CV_MIN_SC_H
52 UNSPEC_CV_MIN_SC_B
53 UNSPEC_CV_MINU_H
54 UNSPEC_CV_MINU_B
55 UNSPEC_CV_MINU_SC_H
56 UNSPEC_CV_MINU_SC_B
57 UNSPEC_CV_MAX_H
58 UNSPEC_CV_MAX_B
59 UNSPEC_CV_MAX_SC_H
60 UNSPEC_CV_MAX_SC_B
61 UNSPEC_CV_MAXU_H
62 UNSPEC_CV_MAXU_B
63 UNSPEC_CV_MAXU_SC_H
64 UNSPEC_CV_MAXU_SC_B
65 UNSPEC_CV_SRL_H
66 UNSPEC_CV_SRL_B
67 UNSPEC_CV_SRL_SC_H
68 UNSPEC_CV_SRL_SC_B
69 UNSPEC_CV_SRA_H
70 UNSPEC_CV_SRA_B
71 UNSPEC_CV_SRA_SC_H
72 UNSPEC_CV_SRA_SC_B
73 UNSPEC_CV_SLL_H
74 UNSPEC_CV_SLL_B
75 UNSPEC_CV_SLL_SC_H
76 UNSPEC_CV_SLL_SC_B
77 UNSPEC_CV_OR_H
78 UNSPEC_CV_OR_B
79 UNSPEC_CV_OR_SC_H
80 UNSPEC_CV_OR_SC_B
81 UNSPEC_CV_XOR_H
82 UNSPEC_CV_XOR_B
83 UNSPEC_CV_XOR_SC_H
84 UNSPEC_CV_XOR_SC_B
85 UNSPEC_CV_AND_H
86 UNSPEC_CV_AND_B
87 UNSPEC_CV_AND_SC_H
88 UNSPEC_CV_AND_SC_B
89 UNSPEC_CV_ABS_H
90 UNSPEC_CV_ABS_B
91 UNSPEC_CV_NEG_H
92 UNSPEC_CV_NEG_B
94 ;;CORE-V SIMD BIT MANIPULATION
95 UNSPEC_CV_EXTRACT_H
96 UNSPEC_CV_EXTRACT_B
97 UNSPEC_CV_EXTRACTU_H
98 UNSPEC_CV_EXTRACTU_B
99 UNSPEC_CV_INSERT_H
100 UNSPEC_CV_INSERT_B
102 ;;CORE-V SIMD DOT PRODUCT
103 UNSPEC_CV_DOTUP_H
104 UNSPEC_CV_DOTUP_B
105 UNSPEC_CV_DOTUP_SC_H
106 UNSPEC_CV_DOTUP_SC_B
107 UNSPEC_CV_DOTUSP_H
108 UNSPEC_CV_DOTUSP_B
109 UNSPEC_CV_DOTUSP_SC_H
110 UNSPEC_CV_DOTUSP_SC_B
111 UNSPEC_CV_DOTSP_H
112 UNSPEC_CV_DOTSP_B
113 UNSPEC_CV_DOTSP_SC_H
114 UNSPEC_CV_DOTSP_SC_B
115 UNSPEC_CV_SDOTUP_H
116 UNSPEC_CV_SDOTUP_B
117 UNSPEC_CV_SDOTUP_SC_H
118 UNSPEC_CV_SDOTUP_SC_B
119 UNSPEC_CV_SDOTUSP_H
120 UNSPEC_CV_SDOTUSP_B
121 UNSPEC_CV_SDOTUSP_SC_H
122 UNSPEC_CV_SDOTUSP_SC_B
123 UNSPEC_CV_SDOTSP_H
124 UNSPEC_CV_SDOTSP_B
125 UNSPEC_CV_SDOTSP_SC_H
126 UNSPEC_CV_SDOTSP_SC_B
128 ;;CORE-V SIMD SHUFFLE AND PACK
129 UNSPEC_CV_SHUFFLE_H
130 UNSPEC_CV_SHUFFLE_SCI_H
131 UNSPEC_CV_SHUFFLE_B
132 UNSPEC_CV_SHUFFLE_SCI_B
133 UNSPEC_CV_SHUFFLE2_H
134 UNSPEC_CV_SHUFFLE2_B
135 UNSPEC_CV_PACKHI_H
136 UNSPEC_CV_PACKLO_H
137 UNSPEC_CV_PACKHI_B
138 UNSPEC_CV_PACKLO_B
140 ;;CORE-V SIMD COMPARISON
141 UNSPEC_CV_CMPEQ_H
142 UNSPEC_CV_CMPEQ_B
143 UNSPEC_CV_CMPEQ_SC_H
144 UNSPEC_CV_CMPEQ_SC_B
145 UNSPEC_CV_CMPNE_H
146 UNSPEC_CV_CMPNE_B
147 UNSPEC_CV_CMPNE_SC_H
148 UNSPEC_CV_CMPNE_SC_B
149 UNSPEC_CV_CMPGT_H
150 UNSPEC_CV_CMPGT_B
151 UNSPEC_CV_CMPGT_SC_H
152 UNSPEC_CV_CMPGT_SC_B
153 UNSPEC_CV_CMPGE_H
154 UNSPEC_CV_CMPGE_B
155 UNSPEC_CV_CMPGE_SC_H
156 UNSPEC_CV_CMPGE_SC_B
157 UNSPEC_CV_CMPLT_H
158 UNSPEC_CV_CMPLT_B
159 UNSPEC_CV_CMPLT_SC_H
160 UNSPEC_CV_CMPLT_SC_B
161 UNSPEC_CV_CMPLE_H
162 UNSPEC_CV_CMPLE_B
163 UNSPEC_CV_CMPLE_SC_H
164 UNSPEC_CV_CMPLE_SC_B
165 UNSPEC_CV_CMPGTU_H
166 UNSPEC_CV_CMPGTU_B
167 UNSPEC_CV_CMPGTU_SC_H
168 UNSPEC_CV_CMPGTU_SC_B
169 UNSPEC_CV_CMPGEU_H
170 UNSPEC_CV_CMPGEU_B
171 UNSPEC_CV_CMPGEU_SC_H
172 UNSPEC_CV_CMPGEU_SC_B
173 UNSPEC_CV_CMPLTU_H
174 UNSPEC_CV_CMPLTU_B
175 UNSPEC_CV_CMPLTU_SC_H
176 UNSPEC_CV_CMPLTU_SC_B
177 UNSPEC_CV_CMPLEU_H
178 UNSPEC_CV_CMPLEU_B
179 UNSPEC_CV_CMPLEU_SC_H
180 UNSPEC_CV_CMPLEU_SC_B
182 ;;CORE-V SIMD COMPLEX
183 UNSPEC_CV_CPLXMUL_R
184 UNSPEC_CV_CPLXMUL_I
185 UNSPEC_CV_CPLXCONJ
186 UNSPEC_CV_SUBROTMJ
188 ])
190 ;; XCVMAC extension.
192 (define_insn "riscv_cv_mac_mac"
193 [(set (match_operand:SI 0 "register_operand" "=r")
194 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
195 (match_operand:SI 2 "register_operand" "r"))
196 (match_operand:SI 3 "register_operand" "0")))]
198 "TARGET_XCVMAC && !TARGET_64BIT"
199 "cv.mac\t%0,%1,%2"
200 [(set_attr "type" "arith")
201 (set_attr "mode" "SI")])
203 (define_insn "riscv_cv_mac_msu"
204 [(set (match_operand:SI 0 "register_operand" "=r")
205 (minus:SI (match_operand:SI 3 "register_operand" "0")
206 (mult:SI (match_operand:SI 1 "register_operand" "r")
207 (match_operand:SI 2 "register_operand" "r"))))]
209 "TARGET_XCVMAC && !TARGET_64BIT"
210 "cv.msu\t%0,%1,%2"
211 [(set_attr "type" "arith")
212 (set_attr "mode" "SI")])
214 (define_insn "riscv_cv_mac_muluN"
215 [(set (match_operand:SI 0 "register_operand" "=r")
216 (lshiftrt:SI
217 (mult:SI
218 (zero_extend:SI
219 (truncate:HI
220 (match_operand:SI 1 "register_operand" "r")))
221 (zero_extend:SI
222 (truncate:HI
223 (match_operand:SI 2 "register_operand" "r"))))
224 (match_operand:QI 3 "const_csr_operand" "K")))]
226 "TARGET_XCVMAC && !TARGET_64BIT"
227 "cv.mulun\t%0,%1,%2,%3"
228 [(set_attr "type" "arith")
229 (set_attr "mode" "SI")])
231 (define_insn "riscv_cv_mac_mulhhuN"
232 [(set (match_operand:SI 0 "register_operand" "=r")
233 (lshiftrt:SI
234 (mult:SI
235 (zero_extend:SI
236 (truncate:HI
237 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
238 (const_int 16))))
239 (zero_extend:SI
240 (truncate:HI
241 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
242 (const_int 16)))))
243 (match_operand:QI 3 "const_csr_operand" "K")))]
245 "TARGET_XCVMAC && !TARGET_64BIT"
246 "cv.mulhhun\t%0,%1,%2,%3"
247 [(set_attr "type" "arith")
248 (set_attr "mode" "SI")])
250 (define_insn "riscv_cv_mac_mulsN"
251 [(set (match_operand:SI 0 "register_operand" "=r")
252 (ashiftrt:SI
253 (mult:SI
254 (sign_extend:SI
255 (truncate:HI
256 (match_operand:SI 1 "register_operand" "r")))
257 (sign_extend:SI
258 (truncate:HI
259 (match_operand:SI 2 "register_operand" "r"))))
260 (match_operand:QI 3 "const_csr_operand" "K")))]
262 "TARGET_XCVMAC && !TARGET_64BIT"
263 "cv.mulsn\t%0,%1,%2,%3"
264 [(set_attr "type" "arith")
265 (set_attr "mode" "SI")])
267 (define_insn "riscv_cv_mac_mulhhsN"
268 [(set (match_operand:SI 0 "register_operand" "=r")
269 (ashiftrt:SI
270 (mult:SI
271 (sign_extend:SI
272 (truncate:HI
273 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
274 (const_int 16))))
275 (sign_extend:SI
276 (truncate:HI
277 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
278 (const_int 16)))))
279 (match_operand:QI 3 "const_csr_operand" "K")))]
281 "TARGET_XCVMAC && !TARGET_64BIT"
282 "cv.mulhhsn\t%0,%1,%2,%3"
283 [(set_attr "type" "arith")
284 (set_attr "mode" "SI")])
286 (define_insn "riscv_cv_mac_muluRN"
287 [(set (match_operand:SI 0 "register_operand" "=r")
288 (lshiftrt:SI
289 (fma:SI
290 (zero_extend:SI
291 (truncate:HI
292 (match_operand:SI 1 "register_operand" "r")))
293 (zero_extend:SI
294 (truncate:HI
295 (match_operand:SI 2 "register_operand" "r")))
296 (if_then_else
297 (ne:QI (match_operand:QI 3 "const_csr_operand" "K") (const_int 0))
298 (ashift:SI (const_int 1)
299 (minus:QI (match_dup 3)
300 (const_int 1)))
301 (const_int 0)))
302 (match_dup 3)))]
304 "TARGET_XCVMAC && !TARGET_64BIT"
305 "cv.mulurn\t%0,%1,%2,%3"
306 [(set_attr "type" "arith")
307 (set_attr "mode" "SI")])
309 (define_insn "riscv_cv_mac_mulhhuRN"
310 [(set (match_operand:SI 0 "register_operand" "=r")
311 (lshiftrt:SI
312 (fma:SI
313 (zero_extend:SI
314 (truncate:HI
315 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
316 (const_int 16))))
317 (zero_extend:SI
318 (truncate:HI
319 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
320 (const_int 16))))
321 (if_then_else
322 (ne:QI (match_operand:QI 3 "const_csr_operand" "K") (const_int 0))
323 (ashift:SI (const_int 1)
324 (minus:QI (match_dup 3)
325 (const_int 1)))
326 (const_int 0)))
327 (match_dup 3)))]
329 "TARGET_XCVMAC && !TARGET_64BIT"
330 "cv.mulhhurn\t%0,%1,%2,%3"
331 [(set_attr "type" "arith")
332 (set_attr "mode" "SI")])
334 (define_insn "riscv_cv_mac_mulsRN"
335 [(set (match_operand:SI 0 "register_operand" "=r")
336 (ashiftrt:SI
337 (fma:SI
338 (sign_extend:SI
339 (truncate:HI
340 (match_operand:SI 1 "register_operand" "r")))
341 (sign_extend:SI
342 (truncate:HI
343 (match_operand:SI 2 "register_operand" "r")))
344 (if_then_else
345 (ne:QI (match_operand:QI 3 "const_csr_operand" "K") (const_int 0))
346 (ashift:SI (const_int 1)
347 (minus:QI (match_dup 3)
348 (const_int 1)))
349 (const_int 0)))
350 (match_dup 3)))]
352 "TARGET_XCVMAC && !TARGET_64BIT"
353 "cv.mulsrn\t%0,%1,%2,%3"
354 [(set_attr "type" "arith")
355 (set_attr "mode" "SI")])
357 (define_insn "riscv_cv_mac_mulhhsRN"
358 [(set (match_operand:SI 0 "register_operand" "=r")
359 (ashiftrt:SI
360 (fma:SI
361 (sign_extend:SI
362 (truncate:HI
363 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
364 (const_int 16))))
365 (sign_extend:SI
366 (truncate:HI
367 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
368 (const_int 16))))
369 (if_then_else
370 (ne:QI (match_operand:QI 3 "const_csr_operand" "K") (const_int 0))
371 (ashift:SI (const_int 1)
372 (minus:QI (match_dup 3)
373 (const_int 1)))
374 (const_int 0)))
375 (match_dup 3)))]
377 "TARGET_XCVMAC && !TARGET_64BIT"
378 "cv.mulhhsrn\t%0,%1,%2,%3"
379 [(set_attr "type" "arith")
380 (set_attr "mode" "SI")])
382 (define_insn "riscv_cv_mac_macuN"
383 [(set (match_operand:SI 0 "register_operand" "=r")
384 (lshiftrt:SI
385 (fma:SI
386 (zero_extend:SI
387 (truncate:HI
388 (match_operand:SI 1 "register_operand" "r")))
389 (zero_extend:SI
390 (truncate:HI
391 (match_operand:SI 2 "register_operand" "r")))
392 (match_operand:SI 3 "register_operand" "0"))
393 (match_operand:QI 4 "const_csr_operand" "K")))]
395 "TARGET_XCVMAC && !TARGET_64BIT"
396 "cv.macun\t%0,%1,%2,%4"
397 [(set_attr "type" "arith")
398 (set_attr "mode" "SI")])
400 (define_insn "riscv_cv_mac_machhuN"
401 [(set (match_operand:SI 0 "register_operand" "=r")
402 (lshiftrt:SI
403 (fma:SI
404 (zero_extend:SI
405 (truncate:HI
406 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
407 (const_int 16))))
408 (zero_extend:SI
409 (truncate:HI
410 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
411 (const_int 16))))
412 (match_operand:SI 3 "register_operand" "0"))
413 (match_operand:QI 4 "const_csr_operand" "K")))]
415 "TARGET_XCVMAC && !TARGET_64BIT"
416 "cv.machhun\t%0,%1,%2,%4"
417 [(set_attr "type" "arith")
418 (set_attr "mode" "SI")])
420 (define_insn "riscv_cv_mac_macsN"
421 [(set (match_operand:SI 0 "register_operand" "=r")
422 (ashiftrt:SI
423 (fma:SI
424 (sign_extend:SI
425 (truncate:HI
426 (match_operand:SI 1 "register_operand" "r")))
427 (sign_extend:SI
428 (truncate:HI
429 (match_operand:SI 2 "register_operand" "r")))
430 (match_operand:SI 3 "register_operand" "0"))
431 (match_operand:QI 4 "const_csr_operand" "K")))]
433 "TARGET_XCVMAC && !TARGET_64BIT"
434 "cv.macsn\t%0,%1,%2,%4"
435 [(set_attr "type" "arith")
436 (set_attr "mode" "SI")])
438 (define_insn "riscv_cv_mac_machhsN"
439 [(set (match_operand:SI 0 "register_operand" "=r")
440 (ashiftrt:SI
441 (fma:SI
442 (sign_extend:SI
443 (truncate:HI
444 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
445 (const_int 16))))
446 (sign_extend:SI
447 (truncate:HI
448 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
449 (const_int 16))))
450 (match_operand:SI 3 "register_operand" "0"))
451 (match_operand:QI 4 "const_csr_operand" "K")))]
453 "TARGET_XCVMAC && !TARGET_64BIT"
454 "cv.machhsn\t%0,%1,%2,%4"
455 [(set_attr "type" "arith")
456 (set_attr "mode" "SI")])
458 (define_insn "riscv_cv_mac_macuRN"
459 [(set (match_operand:SI 0 "register_operand" "=r")
460 (lshiftrt:SI
461 (plus:SI
462 (fma:SI
463 (zero_extend:SI
464 (truncate:HI
465 (match_operand:SI 1 "register_operand" "r")))
466 (zero_extend:SI
467 (truncate:HI
468 (match_operand:SI 2 "register_operand" "r")))
469 (match_operand:SI 3 "register_operand" "0"))
470 (if_then_else
471 (ne:QI (match_operand:QI 4 "const_csr_operand" "K") (const_int 0))
472 (ashift:SI (const_int 1)
473 (minus:QI (match_dup 4)
474 (const_int 1)))
475 (const_int 0)))
476 (match_dup 4)))]
478 "TARGET_XCVMAC && !TARGET_64BIT"
479 "cv.macurn\t%0,%1,%2,%4"
480 [(set_attr "type" "arith")
481 (set_attr "mode" "SI")])
483 (define_insn "riscv_cv_mac_machhuRN"
484 [(set (match_operand:SI 0 "register_operand" "=r")
485 (lshiftrt:SI
486 (plus:SI
487 (fma:SI
488 (zero_extend:SI
489 (truncate:HI
490 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
491 (const_int 16))))
492 (zero_extend:SI
493 (truncate:HI
494 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
495 (const_int 16))))
496 (match_operand:SI 3 "register_operand" "0"))
497 (if_then_else
498 (ne:QI (match_operand:QI 4 "const_csr_operand" "K") (const_int 0))
499 (ashift:SI (const_int 1)
500 (minus:QI (match_dup 4)
501 (const_int 1)))
502 (const_int 0)))
503 (match_dup 4)))]
505 "TARGET_XCVMAC && !TARGET_64BIT"
506 "cv.machhurn\t%0,%1,%2,%4"
507 [(set_attr "type" "arith")
508 (set_attr "mode" "SI")])
510 (define_insn "riscv_cv_mac_macsRN"
511 [(set (match_operand:SI 0 "register_operand" "=r")
512 (ashiftrt:SI
513 (plus:SI
514 (fma:SI
515 (sign_extend:SI
516 (truncate:HI
517 (match_operand:SI 1 "register_operand" "r")))
518 (sign_extend:SI
519 (truncate:HI
520 (match_operand:SI 2 "register_operand" "r")))
521 (match_operand:SI 3 "register_operand" "0"))
522 (if_then_else
523 (ne:QI (match_operand:QI 4 "const_csr_operand" "K") (const_int 0))
524 (ashift:SI (const_int 1)
525 (minus:QI (match_dup 4)
526 (const_int 1)))
527 (const_int 0)))
528 (match_dup 4)))]
530 "TARGET_XCVMAC && !TARGET_64BIT"
531 "cv.macsrn\t%0,%1,%2,%4"
532 [(set_attr "type" "arith")
533 (set_attr "mode" "SI")])
535 (define_insn "riscv_cv_mac_machhsRN"
536 [(set (match_operand:SI 0 "register_operand" "=r")
537 (ashiftrt:SI
538 (plus:SI
539 (fma:SI
540 (sign_extend:SI
541 (truncate:HI
542 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
543 (const_int 16))))
544 (sign_extend:SI
545 (truncate:HI
546 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
547 (const_int 16))))
548 (match_operand:SI 3 "register_operand" "0"))
549 (if_then_else
550 (ne:QI (match_operand:QI 4 "const_csr_operand" "K") (const_int 0))
551 (ashift:SI (const_int 1)
552 (minus:QI (match_dup 4)
553 (const_int 1)))
554 (const_int 0)))
555 (match_dup 4)))]
557 "TARGET_XCVMAC && !TARGET_64BIT"
558 "cv.machhsrn\t%0,%1,%2,%4"
559 [(set_attr "type" "arith")
560 (set_attr "mode" "SI")])
562 ;; XCVALU builtins
564 (define_insn "riscv_cv_alu_slet"
565 [(set (match_operand:SI 0 "register_operand" "=r")
566 (le:SI
567 (match_operand:SI 1 "register_operand" "r")
568 (match_operand:SI 2 "register_operand" "r")))]
570 "TARGET_XCVALU && !TARGET_64BIT"
571 "cv.sle\t%0, %1, %2"
572 [(set_attr "type" "arith")
573 (set_attr "mode" "SI")])
575 (define_insn "riscv_cv_alu_sletu"
576 [(set (match_operand:SI 0 "register_operand" "=r")
577 (leu:SI
578 (match_operand:SI 1 "register_operand" "r")
579 (match_operand:SI 2 "register_operand" "r")))]
581 "TARGET_XCVALU && !TARGET_64BIT"
582 "cv.sleu\t%0, %1, %2"
583 [(set_attr "type" "arith")
584 (set_attr "mode" "SI")])
586 (define_insn "riscv_cv_alu_min"
587 [(set (match_operand:SI 0 "register_operand" "=r")
588 (smin:SI
589 (match_operand:SI 1 "register_operand" "r")
590 (match_operand:SI 2 "register_operand" "r")))]
592 "TARGET_XCVALU && !TARGET_64BIT"
593 "cv.min\t%0, %1, %2"
594 [(set_attr "type" "arith")
595 (set_attr "mode" "SI")])
597 (define_insn "riscv_cv_alu_minu"
598 [(set (match_operand:SI 0 "register_operand" "=r")
599 (umin:SI
600 (match_operand:SI 1 "register_operand" "r")
601 (match_operand:SI 2 "register_operand" "r")))]
603 "TARGET_XCVALU && !TARGET_64BIT"
604 "cv.minu\t%0, %1, %2"
605 [(set_attr "type" "arith")
606 (set_attr "mode" "SI")])
608 (define_insn "riscv_cv_alu_max"
609 [(set (match_operand:SI 0 "register_operand" "=r")
610 (smax:SI
611 (match_operand:SI 1 "register_operand" "r")
612 (match_operand:SI 2 "register_operand" "r")))]
614 "TARGET_XCVALU && !TARGET_64BIT"
615 "cv.max\t%0, %1, %2"
616 [(set_attr "type" "arith")
617 (set_attr "mode" "SI")])
619 (define_insn "riscv_cv_alu_maxu"
620 [(set (match_operand:SI 0 "register_operand" "=r")
621 (umax:SI
622 (match_operand:SI 1 "register_operand" "r")
623 (match_operand:SI 2 "register_operand" "r")))]
625 "TARGET_XCVALU && !TARGET_64BIT"
626 "cv.maxu\t%0, %1, %2"
627 [(set_attr "type" "arith")
628 (set_attr "mode" "SI")])
630 (define_insn "riscv_cv_alu_exths"
631 [(set (match_operand:SI 0 "register_operand" "=r")
632 (sign_extend:SI
633 (truncate:HI
634 (match_operand:HI 1 "register_operand" "r"))))]
636 "TARGET_XCVALU && !TARGET_64BIT"
637 "cv.exths\t%0, %1"
638 [(set_attr "type" "arith")
639 (set_attr "mode" "SI")])
641 (define_insn "riscv_cv_alu_exthz"
642 [(set (match_operand:SI 0 "register_operand" "=r")
643 (zero_extend:SI
644 (truncate:HI
645 (match_operand:HI 1 "register_operand" "r"))))]
647 "TARGET_XCVALU && !TARGET_64BIT"
648 "cv.exthz\t%0, %1"
649 [(set_attr "type" "arith")
650 (set_attr "mode" "SI")])
652 (define_insn "riscv_cv_alu_extbs"
653 [(set (match_operand:SI 0 "register_operand" "=r")
654 (sign_extend:SI
655 (truncate:QI
656 (match_operand:QI 1 "register_operand" "r"))))]
658 "TARGET_XCVALU && !TARGET_64BIT"
659 "cv.extbs\t%0, %1"
660 [(set_attr "type" "arith")
661 (set_attr "mode" "SI")])
663 (define_insn "riscv_cv_alu_extbz"
664 [(set (match_operand:SI 0 "register_operand" "=r")
665 (zero_extend:SI
666 (truncate:QI
667 (match_operand:QI 1 "register_operand" "r"))))]
669 "TARGET_XCVALU && !TARGET_64BIT"
670 "cv.extbz\t%0, %1"
671 [(set_attr "type" "arith")
672 (set_attr "mode" "SI")])
674 (define_insn "riscv_cv_alu_clip"
675 [(set (match_operand:SI 0 "register_operand" "=r,r")
676 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
677 (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")]
678 UNSPEC_CV_ALU_CLIP))]
680 "TARGET_XCVALU && !TARGET_64BIT"
681 "@
682 cv.clip\t%0,%1,%X2
683 cv.clipr\t%0,%1,%2"
684 [(set_attr "type" "arith")
685 (set_attr "mode" "SI")])
687 (define_insn "riscv_cv_alu_clipu"
688 [(set (match_operand:SI 0 "register_operand" "=r,r")
689 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
690 (match_operand:SI 2 "immediate_register_operand" "CV_alu_pow2,r")]
691 UNSPEC_CV_ALU_CLIPU))]
693 "TARGET_XCVALU && !TARGET_64BIT"
694 "@
695 cv.clipu\t%0,%1,%X2
696 cv.clipur\t%0,%1,%2"
697 [(set_attr "type" "arith")
698 (set_attr "mode" "SI")])
700 (define_insn "riscv_cv_alu_addN"
701 [(set (match_operand:SI 0 "register_operand" "=r,r")
702 (ashiftrt:SI
703 (plus:SI
704 (match_operand:SI 1 "register_operand" "r,0")
705 (match_operand:SI 2 "register_operand" "r,r"))
706 (and:SI (match_operand:QI 3 "csr_operand" "K,r")
707 (const_int 31))))]
709 "TARGET_XCVALU && !TARGET_64BIT"
710 "@
711 cv.addn\t%0,%1,%2,%3
712 cv.addnr\t%0,%2,%3"
713 [(set_attr "type" "arith")
714 (set_attr "mode" "SI")])
716 (define_insn "riscv_cv_alu_adduN"
717 [(set (match_operand:SI 0 "register_operand" "=r,r")
718 (lshiftrt:SI
719 (plus:SI
720 (match_operand:SI 1 "register_operand" "r,0")
721 (match_operand:SI 2 "register_operand" "r,r"))
722 (and:SI (match_operand:QI 3 "csr_operand" "K,r")
723 (const_int 31))))]
725 "TARGET_XCVALU && !TARGET_64BIT"
726 "@
727 cv.addun\t%0,%1,%2,%3
728 cv.addunr\t%0,%2,%3"
729 [(set_attr "type" "arith")
730 (set_attr "mode" "SI")])
732 (define_insn "riscv_cv_alu_addRN"
733 [(set (match_operand:SI 0 "register_operand" "=r,r")
734 (ashiftrt:SI
735 (plus:SI
736 (plus:SI
737 (match_operand:SI 1 "register_operand" "r,0")
738 (match_operand:SI 2 "register_operand" "r,r"))
739 (if_then_else (eq (match_operand:QI 3 "csr_operand" "K,r")
740 (const_int 0))
741 (const_int 1)
742 (ashift:SI (const_int 1)
743 (minus:QI (match_dup 3)
744 (const_int 1)))))
745 (and:SI (match_dup 3)
746 (const_int 31))))]
748 "TARGET_XCVALU && !TARGET_64BIT"
749 "@
750 cv.addrn\t%0,%1,%2,%3
751 cv.addrnr\t%0,%2,%3"
752 [(set_attr "type" "arith")
753 (set_attr "mode" "SI")])
755 (define_insn "riscv_cv_alu_adduRN"
756 [(set (match_operand:SI 0 "register_operand" "=r,r")
757 (lshiftrt:SI
758 (plus:SI
759 (plus:SI
760 (match_operand:SI 1 "register_operand" "r,0")
761 (match_operand:SI 2 "register_operand" "r,r"))
762 (if_then_else (eq (match_operand:QI 3 "csr_operand" "K,r")
763 (const_int 0))
764 (const_int 1)
765 (ashift:SI (const_int 1)
766 (minus:QI (match_dup 3)
767 (const_int 1)))))
768 (and:SI (match_dup 3)
769 (const_int 31))))]
771 "TARGET_XCVALU && !TARGET_64BIT"
772 "@
773 cv.addurn\t%0,%1,%2,%3
774 cv.addurnr\t%0,%2,%3"
775 [(set_attr "type" "arith")
776 (set_attr "mode" "SI")])
778 (define_insn "riscv_cv_alu_subN"
779 [(set (match_operand:SI 0 "register_operand" "=r,r")
780 (ashiftrt:SI
781 (minus:SI
782 (match_operand:SI 1 "register_operand" "r,0")
783 (match_operand:SI 2 "register_operand" "r,r"))
784 (and:SI (match_operand:QI 3 "csr_operand" "K,r")
785 (const_int 31))))]
787 "TARGET_XCVALU && !TARGET_64BIT"
788 "@
789 cv.subn\t%0,%1,%2,%3
790 cv.subnr\t%0,%2,%3"
791 [(set_attr "type" "arith")
792 (set_attr "mode" "SI")])
794 (define_insn "riscv_cv_alu_subuN"
795 [(set (match_operand:SI 0 "register_operand" "=r,r")
796 (lshiftrt:SI
797 (minus:SI
798 (match_operand:SI 1 "register_operand" "r,0")
799 (match_operand:SI 2 "register_operand" "r,r"))
800 (and:SI (match_operand:QI 3 "csr_operand" "K,r")
801 (const_int 31))))]
803 "TARGET_XCVALU && !TARGET_64BIT"
804 "@
805 cv.subun\t%0,%1,%2,%3
806 cv.subunr\t%0,%2,%3"
807 [(set_attr "type" "arith")
808 (set_attr "mode" "SI")])
810 (define_insn "riscv_cv_alu_subRN"
811 [(set (match_operand:SI 0 "register_operand" "=r,r")
812 (ashiftrt:SI
813 (plus:SI
814 (minus:SI
815 (match_operand:SI 1 "register_operand" "r,0")
816 (match_operand:SI 2 "register_operand" "r,r"))
817 (if_then_else (eq (match_operand:QI 3 "csr_operand" "K,r")
818 (const_int 0))
819 (const_int 1)
820 (ashift:SI (const_int 1)
821 (minus:QI (match_dup 3)
822 (const_int 1)))))
823 (and:SI (match_dup 3)
824 (const_int 31))))]
826 "TARGET_XCVALU && !TARGET_64BIT"
827 "@
828 cv.subrn\t%0,%1,%2,%3
829 cv.subrnr\t%0,%2,%3"
830 [(set_attr "type" "arith")
831 (set_attr "mode" "SI")])
833 (define_insn "riscv_cv_alu_subuRN"
834 [(set (match_operand:SI 0 "register_operand" "=r,r")
835 (lshiftrt:SI
836 (plus:SI
837 (minus:SI
838 (match_operand:SI 1 "register_operand" "r,0")
839 (match_operand:SI 2 "register_operand" "r,r"))
840 (if_then_else (eq (match_operand:QI 3 "csr_operand" "K,r")
841 (const_int 0))
842 (const_int 1)
843 (ashift:SI (const_int 1)
844 (minus:QI (match_dup 3)
845 (const_int 1)))))
846 (and:SI (match_dup 3)
847 (const_int 31))))]
849 "TARGET_XCVALU && !TARGET_64BIT"
850 "@
851 cv.suburn\t%0,%1,%2,%3
852 cv.suburnr\t%0,%2,%3"
853 [(set_attr "type" "arith")
854 (set_attr "mode" "SI")])
856 ;; XCVELW builtins
857 (define_insn "riscv_cv_elw_elw_si"
858 [(set (match_operand:SI 0 "register_operand" "=r")
859 (unspec_volatile [(match_operand:SI 1 "move_operand" "p")]
860 UNSPECV_CV_ELW))]
862 "TARGET_XCVELW && !TARGET_64BIT"
863 "cv.elw\t%0,%a1"
865 [(set_attr "type" "load")
866 (set_attr "mode" "SI")])
868 ;;CORE-V SIMD
869 ;;CORE-V SIMD ALU
870 (define_insn "riscv_cv_simd_add_h_si"
871 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
872 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r")
873 (match_operand:SI 2 "register_operand" "r,r,r,r")
874 (match_operand:QI 3 "const_int2_operand" "J,c01,c02,c03")]
875 UNSPEC_CV_ADD_H))]
876 "TARGET_XCVSIMD && !TARGET_64BIT"
877 "@
878 cv.add.h\t%0,%1,%2
879 cv.add.div2\t%0,%1,%2
880 cv.add.div4\t%0,%1,%2
881 cv.add.div8\t%0,%1,%2"
882 [(set_attr "type" "arith")
883 (set_attr "mode" "SI")])
886 (define_insn "riscv_cv_simd_add_b_si"
887 [(set (match_operand:SI 0 "register_operand" "=r")
888 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
889 (match_operand:SI 2 "register_operand" "r")]
890 UNSPEC_CV_ADD_B))]
891 "TARGET_XCVSIMD && !TARGET_64BIT"
892 "cv.add.b\t%0,%1,%2"
893 [(set_attr "type" "arith")
894 (set_attr "mode" "SI")])
897 (define_insn "riscv_cv_simd_add_sc_h_si"
898 [(set (match_operand:SI 0 "register_operand" "=r,r")
899 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
900 (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")]
901 UNSPEC_CV_ADD_SC_H))]
902 "TARGET_XCVSIMD && !TARGET_64BIT"
903 "@
904 cv.add.sci.h\t%0,%1,%2
905 cv.add.sc.h\t%0,%1,%2"
906 [(set_attr "type" "arith")
907 (set_attr "mode" "SI")])
910 (define_insn "riscv_cv_simd_add_sc_b_si"
911 [(set (match_operand:SI 0 "register_operand" "=r,r")
912 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
913 (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")]
914 UNSPEC_CV_ADD_SC_B))]
915 "TARGET_XCVSIMD && !TARGET_64BIT"
916 "@
917 cv.add.sci.b\t%0,%1,%2
918 cv.add.sc.b\t%0,%1,%2"
919 [(set_attr "type" "arith")
920 (set_attr "mode" "SI")])
923 (define_insn "riscv_cv_simd_sub_h_si"
924 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
925 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r")
926 (match_operand:SI 2 "register_operand" "r,r,r,r")
927 (match_operand:QI 3 "const_int2_operand" "J,c01,c02,c03")]
928 UNSPEC_CV_SUB_H))]
929 "TARGET_XCVSIMD && !TARGET_64BIT"
930 "@
931 cv.sub.h\t%0,%1,%2
932 cv.sub.div2\t%0,%1,%2
933 cv.sub.div4\t%0,%1,%2
934 cv.sub.div8\t%0,%1,%2"
935 [(set_attr "type" "arith")
936 (set_attr "mode" "SI")])
939 (define_insn "riscv_cv_simd_sub_b_si"
940 [(set (match_operand:SI 0 "register_operand" "=r")
941 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
942 (match_operand:SI 2 "register_operand" "r")]
943 UNSPEC_CV_SUB_B))]
944 "TARGET_XCVSIMD && !TARGET_64BIT"
945 "cv.sub.b\t%0,%1,%2"
946 [(set_attr "type" "arith")
947 (set_attr "mode" "SI")])
950 (define_insn "riscv_cv_simd_sub_sc_h_si"
951 [(set (match_operand:SI 0 "register_operand" "=r,r")
952 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
953 (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")]
954 UNSPEC_CV_SUB_SC_H))]
955 "TARGET_XCVSIMD && !TARGET_64BIT"
956 "@
957 cv.sub.sci.h\t%0,%1,%2
958 cv.sub.sc.h\t%0,%1,%2"
959 [(set_attr "type" "arith")
960 (set_attr "mode" "SI")])
963 (define_insn "riscv_cv_simd_sub_sc_b_si"
964 [(set (match_operand:SI 0 "register_operand" "=r,r")
965 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
966 (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")]
967 UNSPEC_CV_SUB_SC_B))]
968 "TARGET_XCVSIMD && !TARGET_64BIT"
969 "@
970 cv.sub.sci.b\t%0,%1,%2
971 cv.sub.sc.b\t%0,%1,%2"
972 [(set_attr "type" "arith")
973 (set_attr "mode" "SI")])
976 (define_insn "riscv_cv_simd_avg_h_si"
977 [(set (match_operand:SI 0 "register_operand" "=r")
978 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
979 (match_operand:SI 2 "register_operand" "r")]
980 UNSPEC_CV_AVG_H))]
981 "TARGET_XCVSIMD && !TARGET_64BIT"
982 "cv.avg.h\t%0,%1,%2"
983 [(set_attr "type" "arith")
984 (set_attr "mode" "SI")])
987 (define_insn "riscv_cv_simd_avg_b_si"
988 [(set (match_operand:SI 0 "register_operand" "=r")
989 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
990 (match_operand:SI 2 "register_operand" "r")]
991 UNSPEC_CV_AVG_B))]
992 "TARGET_XCVSIMD && !TARGET_64BIT"
993 "cv.avg.b\t%0,%1,%2"
994 [(set_attr "type" "arith")
995 (set_attr "mode" "SI")])
998 (define_insn "riscv_cv_simd_avg_sc_h_si"
999 [(set (match_operand:SI 0 "register_operand" "=r,r")
1000 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1001 (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")]
1002 UNSPEC_CV_AVG_SC_H))]
1003 "TARGET_XCVSIMD && !TARGET_64BIT"
1004 "@
1005 cv.avg.sci.h\t%0,%1,%2
1006 cv.avg.sc.h\t%0,%1,%2"
1007 [(set_attr "type" "arith")
1008 (set_attr "mode" "SI")])
1011 (define_insn "riscv_cv_simd_avg_sc_b_si"
1012 [(set (match_operand:SI 0 "register_operand" "=r,r")
1013 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1014 (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")]
1015 UNSPEC_CV_AVG_SC_B))]
1016 "TARGET_XCVSIMD && !TARGET_64BIT"
1017 "@
1018 cv.avg.sci.b\t%0,%1,%2
1019 cv.avg.sc.b\t%0,%1,%2"
1020 [(set_attr "type" "arith")
1021 (set_attr "mode" "SI")])
1024 (define_insn "riscv_cv_simd_avgu_h_si"
1025 [(set (match_operand:SI 0 "register_operand" "=r")
1026 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1027 (match_operand:SI 2 "register_operand" "r")]
1028 UNSPEC_CV_AVGU_H))]
1029 "TARGET_XCVSIMD && !TARGET_64BIT"
1030 "cv.avgu.h\t%0,%1,%2"
1031 [(set_attr "type" "arith")
1032 (set_attr "mode" "SI")])
1035 (define_insn "riscv_cv_simd_avgu_b_si"
1036 [(set (match_operand:SI 0 "register_operand" "=r")
1037 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1038 (match_operand:SI 2 "register_operand" "r")]
1039 UNSPEC_CV_AVGU_B))]
1040 "TARGET_XCVSIMD && !TARGET_64BIT"
1041 "cv.avgu.b\t%0,%1,%2"
1042 [(set_attr "type" "arith")
1043 (set_attr "mode" "SI")])
1046 (define_insn "riscv_cv_simd_avgu_sc_h_si"
1047 [(set (match_operand:SI 0 "register_operand" "=r,r")
1048 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1049 (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")]
1050 UNSPEC_CV_AVGU_SC_H))]
1051 "TARGET_XCVSIMD && !TARGET_64BIT"
1052 "@
1053 cv.avgu.sci.h\t%0,%1,%2
1054 cv.avgu.sc.h\t%0,%1,%2"
1055 [(set_attr "type" "arith")
1056 (set_attr "mode" "SI")])
1059 (define_insn "riscv_cv_simd_avgu_sc_b_si"
1060 [(set (match_operand:SI 0 "register_operand" "=r,r")
1061 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1062 (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")]
1063 UNSPEC_CV_AVGU_SC_B))]
1064 "TARGET_XCVSIMD && !TARGET_64BIT"
1065 "@
1066 cv.avgu.sci.b\t%0,%1,%2
1067 cv.avgu.sc.b\t%0,%1,%2"
1068 [(set_attr "type" "arith")
1069 (set_attr "mode" "SI")])
1072 (define_insn "riscv_cv_simd_min_h_si"
1073 [(set (match_operand:SI 0 "register_operand" "=r")
1074 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1075 (match_operand:SI 2 "register_operand" "r")]
1076 UNSPEC_CV_MIN_H))]
1077 "TARGET_XCVSIMD && !TARGET_64BIT"
1078 "cv.min.h\t%0,%1,%2"
1079 [(set_attr "type" "arith")
1080 (set_attr "mode" "SI")])
1083 (define_insn "riscv_cv_simd_min_b_si"
1084 [(set (match_operand:SI 0 "register_operand" "=r")
1085 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1086 (match_operand:SI 2 "register_operand" "r")]
1087 UNSPEC_CV_MIN_B))]
1088 "TARGET_XCVSIMD && !TARGET_64BIT"
1089 "cv.min.b\t%0,%1,%2"
1090 [(set_attr "type" "arith")
1091 (set_attr "mode" "SI")])
1094 (define_insn "riscv_cv_simd_min_sc_h_si"
1095 [(set (match_operand:SI 0 "register_operand" "=r,r")
1096 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1097 (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")]
1098 UNSPEC_CV_MIN_SC_H))]
1099 "TARGET_XCVSIMD && !TARGET_64BIT"
1100 "@
1101 cv.min.sci.h\t%0,%1,%2
1102 cv.min.sc.h\t%0,%1,%2"
1103 [(set_attr "type" "arith")
1104 (set_attr "mode" "SI")])
1107 (define_insn "riscv_cv_simd_min_sc_b_si"
1108 [(set (match_operand:SI 0 "register_operand" "=r,r")
1109 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1110 (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")]
1111 UNSPEC_CV_MIN_SC_B))]
1112 "TARGET_XCVSIMD && !TARGET_64BIT"
1113 "@
1114 cv.min.sci.b\t%0,%1,%2
1115 cv.min.sc.b\t%0,%1,%2"
1116 [(set_attr "type" "arith")
1117 (set_attr "mode" "SI")])
1120 (define_insn "riscv_cv_simd_minu_h_si"
1121 [(set (match_operand:SI 0 "register_operand" "=r")
1122 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1123 (match_operand:SI 2 "register_operand" "r")]
1124 UNSPEC_CV_MINU_H))]
1125 "TARGET_XCVSIMD && !TARGET_64BIT"
1126 "cv.minu.h\t%0,%1,%2"
1127 [(set_attr "type" "arith")
1128 (set_attr "mode" "SI")])
1131 (define_insn "riscv_cv_simd_minu_b_si"
1132 [(set (match_operand:SI 0 "register_operand" "=r")
1133 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1134 (match_operand:SI 2 "register_operand" "r")]
1135 UNSPEC_CV_MINU_B))]
1136 "TARGET_XCVSIMD && !TARGET_64BIT"
1137 "cv.minu.b\t%0,%1,%2"
1138 [(set_attr "type" "arith")
1139 (set_attr "mode" "SI")])
1142 (define_insn "riscv_cv_simd_minu_sc_h_si"
1143 [(set (match_operand:SI 0 "register_operand" "=r,r")
1144 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1145 (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")]
1146 UNSPEC_CV_MINU_SC_H))]
1147 "TARGET_XCVSIMD && !TARGET_64BIT"
1148 "@
1149 cv.minu.sci.h\t%0,%1,%2
1150 cv.minu.sc.h\t%0,%1,%2"
1151 [(set_attr "type" "arith")
1152 (set_attr "mode" "SI")])
1155 (define_insn "riscv_cv_simd_minu_sc_b_si"
1156 [(set (match_operand:SI 0 "register_operand" "=r,r")
1157 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1158 (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")]
1159 UNSPEC_CV_MINU_SC_B))]
1160 "TARGET_XCVSIMD && !TARGET_64BIT"
1161 "@
1162 cv.minu.sci.b\t%0,%1,%2
1163 cv.minu.sc.b\t%0,%1,%2"
1164 [(set_attr "type" "arith")
1165 (set_attr "mode" "SI")])
1168 (define_insn "riscv_cv_simd_max_h_si"
1169 [(set (match_operand:SI 0 "register_operand" "=r")
1170 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1171 (match_operand:SI 2 "register_operand" "r")]
1172 UNSPEC_CV_MAX_H))]
1173 "TARGET_XCVSIMD && !TARGET_64BIT"
1174 "cv.max.h\t%0,%1,%2"
1175 [(set_attr "type" "arith")
1176 (set_attr "mode" "SI")])
1179 (define_insn "riscv_cv_simd_max_b_si"
1180 [(set (match_operand:SI 0 "register_operand" "=r")
1181 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1182 (match_operand:SI 2 "register_operand" "r")]
1183 UNSPEC_CV_MAX_B))]
1184 "TARGET_XCVSIMD && !TARGET_64BIT"
1185 "cv.max.b\t%0,%1,%2"
1186 [(set_attr "type" "arith")
1187 (set_attr "mode" "SI")])
1190 (define_insn "riscv_cv_simd_max_sc_h_si"
1191 [(set (match_operand:SI 0 "register_operand" "=r,r")
1192 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1193 (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")]
1194 UNSPEC_CV_MAX_SC_H))]
1195 "TARGET_XCVSIMD && !TARGET_64BIT"
1196 "@
1197 cv.max.sci.h\t%0,%1,%2
1198 cv.max.sc.h\t%0,%1,%2"
1199 [(set_attr "type" "arith")
1200 (set_attr "mode" "SI")])
1203 (define_insn "riscv_cv_simd_max_sc_b_si"
1204 [(set (match_operand:SI 0 "register_operand" "=r,r")
1205 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1206 (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")]
1207 UNSPEC_CV_MAX_SC_B))]
1208 "TARGET_XCVSIMD && !TARGET_64BIT"
1209 "@
1210 cv.max.sci.b\t%0,%1,%2
1211 cv.max.sc.b\t%0,%1,%2"
1212 [(set_attr "type" "arith")
1213 (set_attr "mode" "SI")])
1216 (define_insn "riscv_cv_simd_maxu_h_si"
1217 [(set (match_operand:SI 0 "register_operand" "=r")
1218 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1219 (match_operand:SI 2 "register_operand" "r")]
1220 UNSPEC_CV_MAXU_H))]
1221 "TARGET_XCVSIMD && !TARGET_64BIT"
1222 "cv.maxu.h\t%0,%1,%2"
1223 [(set_attr "type" "arith")
1224 (set_attr "mode" "SI")])
1227 (define_insn "riscv_cv_simd_maxu_b_si"
1228 [(set (match_operand:SI 0 "register_operand" "=r")
1229 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1230 (match_operand:SI 2 "register_operand" "r")]
1231 UNSPEC_CV_MAXU_B))]
1232 "TARGET_XCVSIMD && !TARGET_64BIT"
1233 "cv.maxu.b\t%0,%1,%2"
1234 [(set_attr "type" "arith")
1235 (set_attr "mode" "SI")])
1238 (define_insn "riscv_cv_simd_maxu_sc_h_si"
1239 [(set (match_operand:SI 0 "register_operand" "=r,r")
1240 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1241 (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")]
1242 UNSPEC_CV_MAXU_SC_H))]
1243 "TARGET_XCVSIMD && !TARGET_64BIT"
1244 "@
1245 cv.maxu.sci.h\t%0,%1,%2
1246 cv.maxu.sc.h\t%0,%1,%2"
1247 [(set_attr "type" "arith")
1248 (set_attr "mode" "SI")])
1251 (define_insn "riscv_cv_simd_maxu_sc_b_si"
1252 [(set (match_operand:SI 0 "register_operand" "=r,r")
1253 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1254 (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")]
1255 UNSPEC_CV_MAXU_SC_B))]
1256 "TARGET_XCVSIMD && !TARGET_64BIT"
1257 "@
1258 cv.maxu.sci.b\t%0,%1,%2
1259 cv.maxu.sc.b\t%0,%1,%2"
1260 [(set_attr "type" "arith")
1261 (set_attr "mode" "SI")])
1264 (define_insn "riscv_cv_simd_srl_h_si"
1265 [(set (match_operand:SI 0 "register_operand" "=r")
1266 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1267 (match_operand:SI 2 "register_operand" "r")]
1268 UNSPEC_CV_SRL_H))]
1269 "TARGET_XCVSIMD && !TARGET_64BIT"
1270 "cv.srl.h\t%0,%1,%2"
1271 [(set_attr "type" "arith")
1272 (set_attr "mode" "SI")])
1275 (define_insn "riscv_cv_simd_srl_b_si"
1276 [(set (match_operand:SI 0 "register_operand" "=r")
1277 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1278 (match_operand:SI 2 "register_operand" "r")]
1279 UNSPEC_CV_SRL_B))]
1280 "TARGET_XCVSIMD && !TARGET_64BIT"
1281 "cv.srl.b\t%0,%1,%2"
1282 [(set_attr "type" "arith")
1283 (set_attr "mode" "SI")])
1286 (define_insn "riscv_cv_simd_srl_sc_h_si"
1287 [(set (match_operand:SI 0 "register_operand" "=r,r")
1288 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1289 (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")]
1290 UNSPEC_CV_SRL_SC_H))]
1291 "TARGET_XCVSIMD && !TARGET_64BIT"
1292 "@
1293 cv.srl.sci.h\t%0,%1,%2
1294 cv.srl.sc.h\t%0,%1,%2"
1295 [(set_attr "type" "arith")
1296 (set_attr "mode" "SI")])
1299 (define_insn "riscv_cv_simd_srl_sc_b_si"
1300 [(set (match_operand:SI 0 "register_operand" "=r,r")
1301 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1302 (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")]
1303 UNSPEC_CV_SRL_SC_B))]
1304 "TARGET_XCVSIMD && !TARGET_64BIT"
1305 "@
1306 cv.srl.sci.b\t%0,%1,%2
1307 cv.srl.sc.b\t%0,%1,%2"
1308 [(set_attr "type" "arith")
1309 (set_attr "mode" "SI")])
1312 (define_insn "riscv_cv_simd_sra_h_si"
1313 [(set (match_operand:SI 0 "register_operand" "=r")
1314 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1315 (match_operand:SI 2 "register_operand" "r")]
1316 UNSPEC_CV_SRA_H))]
1317 "TARGET_XCVSIMD && !TARGET_64BIT"
1318 "cv.sra.h\t%0,%1,%2"
1319 [(set_attr "type" "arith")
1320 (set_attr "mode" "SI")])
1323 (define_insn "riscv_cv_simd_sra_b_si"
1324 [(set (match_operand:SI 0 "register_operand" "=r")
1325 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1326 (match_operand:SI 2 "register_operand" "r")]
1327 UNSPEC_CV_SRA_B))]
1328 "TARGET_XCVSIMD && !TARGET_64BIT"
1329 "cv.sra.b\t%0,%1,%2"
1330 [(set_attr "type" "arith")
1331 (set_attr "mode" "SI")])
1334 (define_insn "riscv_cv_simd_sra_sc_h_si"
1335 [(set (match_operand:SI 0 "register_operand" "=r,r")
1336 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1337 (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")]
1338 UNSPEC_CV_SRA_SC_H))]
1339 "TARGET_XCVSIMD && !TARGET_64BIT"
1340 "@
1341 cv.sra.sci.h\t%0,%1,%2
1342 cv.sra.sc.h\t%0,%1,%2"
1343 [(set_attr "type" "arith")
1344 (set_attr "mode" "SI")])
1347 (define_insn "riscv_cv_simd_sra_sc_b_si"
1348 [(set (match_operand:SI 0 "register_operand" "=r,r")
1349 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1350 (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")]
1351 UNSPEC_CV_SRA_SC_B))]
1352 "TARGET_XCVSIMD && !TARGET_64BIT"
1353 "@
1354 cv.sra.sci.b\t%0,%1,%2
1355 cv.sra.sc.b\t%0,%1,%2"
1356 [(set_attr "type" "arith")
1357 (set_attr "mode" "SI")])
1360 (define_insn "riscv_cv_simd_sll_h_si"
1361 [(set (match_operand:SI 0 "register_operand" "=r")
1362 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1363 (match_operand:SI 2 "register_operand" "r")]
1364 UNSPEC_CV_SLL_H))]
1365 "TARGET_XCVSIMD && !TARGET_64BIT"
1366 "cv.sll.h\t%0,%1,%2"
1367 [(set_attr "type" "arith")
1368 (set_attr "mode" "SI")])
1371 (define_insn "riscv_cv_simd_sll_b_si"
1372 [(set (match_operand:SI 0 "register_operand" "=r")
1373 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1374 (match_operand:SI 2 "register_operand" "r")]
1375 UNSPEC_CV_SLL_B))]
1376 "TARGET_XCVSIMD && !TARGET_64BIT"
1377 "cv.sll.b\t%0,%1,%2"
1378 [(set_attr "type" "arith")
1379 (set_attr "mode" "SI")])
1382 (define_insn "riscv_cv_simd_sll_sc_h_si"
1383 [(set (match_operand:SI 0 "register_operand" "=r,r")
1384 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1385 (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")]
1386 UNSPEC_CV_SLL_SC_H))]
1387 "TARGET_XCVSIMD && !TARGET_64BIT"
1388 "@
1389 cv.sll.sci.h\t%0,%1,%2
1390 cv.sll.sc.h\t%0,%1,%2"
1391 [(set_attr "type" "arith")
1392 (set_attr "mode" "SI")])
1395 (define_insn "riscv_cv_simd_sll_sc_b_si"
1396 [(set (match_operand:SI 0 "register_operand" "=r,r")
1397 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1398 (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")]
1399 UNSPEC_CV_SLL_SC_B))]
1400 "TARGET_XCVSIMD && !TARGET_64BIT"
1401 "@
1402 cv.sll.sci.b\t%0,%1,%2
1403 cv.sll.sc.b\t%0,%1,%2"
1404 [(set_attr "type" "arith")
1405 (set_attr "mode" "SI")])
1408 (define_insn "riscv_cv_simd_or_h_si"
1409 [(set (match_operand:SI 0 "register_operand" "=r")
1410 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1411 (match_operand:SI 2 "register_operand" "r")]
1412 UNSPEC_CV_OR_H))]
1413 "TARGET_XCVSIMD && !TARGET_64BIT"
1414 "cv.or.h\t%0,%1,%2"
1415 [(set_attr "type" "arith")
1416 (set_attr "mode" "SI")])
1419 (define_insn "riscv_cv_simd_or_b_si"
1420 [(set (match_operand:SI 0 "register_operand" "=r")
1421 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1422 (match_operand:SI 2 "register_operand" "r")]
1423 UNSPEC_CV_OR_B))]
1424 "TARGET_XCVSIMD && !TARGET_64BIT"
1425 "cv.or.b\t%0,%1,%2"
1426 [(set_attr "type" "arith")
1427 (set_attr "mode" "SI")])
1430 (define_insn "riscv_cv_simd_or_sc_h_si"
1431 [(set (match_operand:SI 0 "register_operand" "=r,r")
1432 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1433 (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")]
1434 UNSPEC_CV_OR_SC_H))]
1435 "TARGET_XCVSIMD && !TARGET_64BIT"
1436 "@
1437 cv.or.sci.h\t%0,%1,%2
1438 cv.or.sc.h\t%0,%1,%2"
1439 [(set_attr "type" "arith")
1440 (set_attr "mode" "SI")])
1443 (define_insn "riscv_cv_simd_or_sc_b_si"
1444 [(set (match_operand:SI 0 "register_operand" "=r,r")
1445 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1446 (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")]
1447 UNSPEC_CV_OR_SC_B))]
1448 "TARGET_XCVSIMD && !TARGET_64BIT"
1449 "@
1450 cv.or.sci.b\t%0,%1,%2
1451 cv.or.sc.b\t%0,%1,%2"
1452 [(set_attr "type" "arith")
1453 (set_attr "mode" "SI")])
1456 (define_insn "riscv_cv_simd_xor_h_si"
1457 [(set (match_operand:SI 0 "register_operand" "=r")
1458 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1459 (match_operand:SI 2 "register_operand" "r")]
1460 UNSPEC_CV_XOR_H))]
1461 "TARGET_XCVSIMD && !TARGET_64BIT"
1462 "cv.xor.h\t%0,%1,%2"
1463 [(set_attr "type" "arith")
1464 (set_attr "mode" "SI")])
1467 (define_insn "riscv_cv_simd_xor_b_si"
1468 [(set (match_operand:SI 0 "register_operand" "=r")
1469 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1470 (match_operand:SI 2 "register_operand" "r")]
1471 UNSPEC_CV_XOR_B))]
1472 "TARGET_XCVSIMD && !TARGET_64BIT"
1473 "cv.xor.b\t%0,%1,%2"
1474 [(set_attr "type" "arith")
1475 (set_attr "mode" "SI")])
1478 (define_insn "riscv_cv_simd_xor_sc_h_si"
1479 [(set (match_operand:SI 0 "register_operand" "=r,r")
1480 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1481 (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")]
1482 UNSPEC_CV_XOR_SC_H))]
1483 "TARGET_XCVSIMD && !TARGET_64BIT"
1484 "@
1485 cv.xor.sci.h\t%0,%1,%2
1486 cv.xor.sc.h\t%0,%1,%2"
1487 [(set_attr "type" "arith")
1488 (set_attr "mode" "SI")])
1491 (define_insn "riscv_cv_simd_xor_sc_b_si"
1492 [(set (match_operand:SI 0 "register_operand" "=r,r")
1493 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1494 (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")]
1495 UNSPEC_CV_XOR_SC_B))]
1496 "TARGET_XCVSIMD && !TARGET_64BIT"
1497 "@
1498 cv.xor.sci.b\t%0,%1,%2
1499 cv.xor.sc.b\t%0,%1,%2"
1500 [(set_attr "type" "arith")
1501 (set_attr "mode" "SI")])
1504 (define_insn "riscv_cv_simd_and_h_si"
1505 [(set (match_operand:SI 0 "register_operand" "=r")
1506 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1507 (match_operand:SI 2 "register_operand" "r")]
1508 UNSPEC_CV_AND_H))]
1509 "TARGET_XCVSIMD && !TARGET_64BIT"
1510 "cv.and.h\t%0,%1,%2"
1511 [(set_attr "type" "arith")
1512 (set_attr "mode" "SI")])
1515 (define_insn "riscv_cv_simd_and_b_si"
1516 [(set (match_operand:SI 0 "register_operand" "=r")
1517 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1518 (match_operand:SI 2 "register_operand" "r")]
1519 UNSPEC_CV_AND_B))]
1520 "TARGET_XCVSIMD && !TARGET_64BIT"
1521 "cv.and.b\t%0,%1,%2"
1522 [(set_attr "type" "arith")
1523 (set_attr "mode" "SI")])
1526 (define_insn "riscv_cv_simd_and_sc_h_si"
1527 [(set (match_operand:SI 0 "register_operand" "=r,r")
1528 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1529 (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")]
1530 UNSPEC_CV_AND_SC_H))]
1531 "TARGET_XCVSIMD && !TARGET_64BIT"
1532 "@
1533 cv.and.sci.h\t%0,%1,%2
1534 cv.and.sc.h\t%0,%1,%2"
1535 [(set_attr "type" "arith")
1536 (set_attr "mode" "SI")])
1539 (define_insn "riscv_cv_simd_and_sc_b_si"
1540 [(set (match_operand:SI 0 "register_operand" "=r,r")
1541 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1542 (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")]
1543 UNSPEC_CV_AND_SC_B))]
1544 "TARGET_XCVSIMD && !TARGET_64BIT"
1545 "@
1546 cv.and.sci.b\t%0,%1,%2
1547 cv.and.sc.b\t%0,%1,%2"
1548 [(set_attr "type" "arith")
1549 (set_attr "mode" "SI")])
1552 (define_insn "riscv_cv_simd_abs_h_si"
1553 [(set (match_operand:SI 0 "register_operand" "=r")
1554 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]UNSPEC_CV_ABS_H))]
1555 "TARGET_XCVSIMD && !TARGET_64BIT"
1556 "cv.abs.h\t%0,%1"
1557 [(set_attr "type" "arith")
1558 (set_attr "mode" "SI")])
1561 (define_insn "riscv_cv_simd_abs_b_si"
1562 [(set (match_operand:SI 0 "register_operand" "=r")
1563 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]UNSPEC_CV_ABS_B))]
1564 "TARGET_XCVSIMD && !TARGET_64BIT"
1565 "cv.abs.b\t%0,%1"
1566 [(set_attr "type" "arith")
1567 (set_attr "mode" "SI")])
1570 (define_insn "riscv_cv_simd_neg_h_si"
1571 [(set (match_operand:SI 0 "register_operand" "=r")
1572 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]UNSPEC_CV_NEG_H))]
1573 "TARGET_XCVSIMD && !TARGET_64BIT"
1574 "cv.sub.h\t%0,zero,%1"
1575 [(set_attr "type" "arith")
1576 (set_attr "mode" "SI")])
1579 (define_insn "riscv_cv_simd_neg_b_si"
1580 [(set (match_operand:SI 0 "register_operand" "=r")
1581 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]UNSPEC_CV_NEG_B))]
1582 "TARGET_XCVSIMD && !TARGET_64BIT"
1583 "cv.sub.b\t%0,zero,%1"
1584 [(set_attr "type" "arith")
1585 (set_attr "mode" "SI")])
1588 ;;CORE-V SIMD BIT MANIPULATION
1589 (define_insn "riscv_cv_simd_extract_h_si"
1590 [(set (match_operand:SI 0 "register_operand" "=r")
1591 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1592 (match_operand:QI 2 "immediate_operand" "CV_simd_si6")]
1593 UNSPEC_CV_EXTRACT_H))]
1594 "TARGET_XCVSIMD && !TARGET_64BIT"
1595 "cv.extract.h\t%0,%1,%2"
1596 [(set_attr "type" "arith")
1597 (set_attr "mode" "SI")])
1600 (define_insn "riscv_cv_simd_extract_b_si"
1601 [(set (match_operand:SI 0 "register_operand" "=r")
1602 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1603 (match_operand:QI 2 "immediate_operand" "CV_simd_si6")]
1604 UNSPEC_CV_EXTRACT_B))]
1605 "TARGET_XCVSIMD && !TARGET_64BIT"
1606 "cv.extract.b\t%0,%1,%2"
1607 [(set_attr "type" "arith")
1608 (set_attr "mode" "SI")])
1611 (define_insn "riscv_cv_simd_extractu_h_si"
1612 [(set (match_operand:SI 0 "register_operand" "=r")
1613 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1614 (match_operand:QI 2 "immediate_operand" "CV_simd_si6")]
1615 UNSPEC_CV_EXTRACTU_H))]
1616 "TARGET_XCVSIMD && !TARGET_64BIT"
1617 "cv.extractu.h\t%0,%1,%2"
1618 [(set_attr "type" "arith")
1619 (set_attr "mode" "SI")])
1622 (define_insn "riscv_cv_simd_extractu_b_si"
1623 [(set (match_operand:SI 0 "register_operand" "=r")
1624 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1625 (match_operand:QI 2 "immediate_operand" "CV_simd_si6")]
1626 UNSPEC_CV_EXTRACTU_B))]
1627 "TARGET_XCVSIMD && !TARGET_64BIT"
1628 "cv.extractu.b\t%0,%1,%2"
1629 [(set_attr "type" "arith")
1630 (set_attr "mode" "SI")])
1633 (define_insn "riscv_cv_simd_insert_h_si"
1634 [(set (match_operand:SI 0 "register_operand" "=r")
1635 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1636 (match_operand:SI 2 "register_operand" "0")
1637 (match_operand:QI 3 "immediate_operand" "CV_simd_si6")]
1638 UNSPEC_CV_INSERT_H))]
1639 "TARGET_XCVSIMD && !TARGET_64BIT"
1640 "cv.insert.h\t%0,%1,%3"
1641 [(set_attr "type" "arith")
1642 (set_attr "mode" "SI")])
1645 (define_insn "riscv_cv_simd_insert_b_si"
1646 [(set (match_operand:SI 0 "register_operand" "=r")
1647 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1648 (match_operand:SI 2 "register_operand" "0")
1649 (match_operand:QI 3 "immediate_operand" "CV_simd_si6")]
1650 UNSPEC_CV_INSERT_B))]
1651 "TARGET_XCVSIMD && !TARGET_64BIT"
1652 "cv.insert.b\t%0,%1,%3"
1653 [(set_attr "type" "arith")
1654 (set_attr "mode" "SI")])
1657 ;;CORE-V SIMD DOT PRODUCT
1658 (define_insn "riscv_cv_simd_dotup_h_si"
1659 [(set (match_operand:SI 0 "register_operand" "=r")
1660 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1661 (match_operand:SI 2 "register_operand" "r")]
1662 UNSPEC_CV_DOTUP_H))]
1663 "TARGET_XCVSIMD && !TARGET_64BIT"
1664 "cv.dotup.h\t%0,%1,%2"
1665 [(set_attr "type" "arith")
1666 (set_attr "mode" "SI")])
1669 (define_insn "riscv_cv_simd_dotup_b_si"
1670 [(set (match_operand:SI 0 "register_operand" "=r")
1671 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1672 (match_operand:SI 2 "register_operand" "r")]
1673 UNSPEC_CV_DOTUP_B))]
1674 "TARGET_XCVSIMD && !TARGET_64BIT"
1675 "cv.dotup.b\t%0,%1,%2"
1676 [(set_attr "type" "arith")
1677 (set_attr "mode" "SI")])
1680 (define_insn "riscv_cv_simd_dotup_sc_h_si"
1681 [(set (match_operand:SI 0 "register_operand" "=r,r")
1682 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1683 (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")]
1684 UNSPEC_CV_DOTUP_SC_H))]
1685 "TARGET_XCVSIMD && !TARGET_64BIT"
1686 "@
1687 cv.dotup.sci.h\t%0,%1,%2
1688 cv.dotup.sc.h\t%0,%1,%2"
1689 [(set_attr "type" "arith")
1690 (set_attr "mode" "SI")])
1693 (define_insn "riscv_cv_simd_dotup_sc_b_si"
1694 [(set (match_operand:SI 0 "register_operand" "=r,r")
1695 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1696 (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")]
1697 UNSPEC_CV_DOTUP_SC_B))]
1698 "TARGET_XCVSIMD && !TARGET_64BIT"
1699 "@
1700 cv.dotup.sci.b\t%0,%1,%2
1701 cv.dotup.sc.b\t%0,%1,%2"
1702 [(set_attr "type" "arith")
1703 (set_attr "mode" "SI")])
1706 (define_insn "riscv_cv_simd_dotusp_h_si"
1707 [(set (match_operand:SI 0 "register_operand" "=r")
1708 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1709 (match_operand:SI 2 "register_operand" "r")]
1710 UNSPEC_CV_DOTUSP_H))]
1711 "TARGET_XCVSIMD && !TARGET_64BIT"
1712 "cv.dotusp.h\t%0,%1,%2"
1713 [(set_attr "type" "arith")
1714 (set_attr "mode" "SI")])
1717 (define_insn "riscv_cv_simd_dotusp_b_si"
1718 [(set (match_operand:SI 0 "register_operand" "=r")
1719 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1720 (match_operand:SI 2 "register_operand" "r")]
1721 UNSPEC_CV_DOTUSP_B))]
1722 "TARGET_XCVSIMD && !TARGET_64BIT"
1723 "cv.dotusp.b\t%0,%1,%2"
1724 [(set_attr "type" "arith")
1725 (set_attr "mode" "SI")])
1728 (define_insn "riscv_cv_simd_dotusp_sc_h_si"
1729 [(set (match_operand:SI 0 "register_operand" "=r,r")
1730 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1731 (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")]
1732 UNSPEC_CV_DOTUSP_SC_H))]
1733 "TARGET_XCVSIMD && !TARGET_64BIT"
1734 "@
1735 cv.dotusp.sci.h\t%0,%1,%2
1736 cv.dotusp.sc.h\t%0,%1,%2"
1737 [(set_attr "type" "arith")
1738 (set_attr "mode" "SI")])
1741 (define_insn "riscv_cv_simd_dotusp_sc_b_si"
1742 [(set (match_operand:SI 0 "register_operand" "=r,r")
1743 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1744 (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")]
1745 UNSPEC_CV_DOTUSP_SC_B))]
1746 "TARGET_XCVSIMD && !TARGET_64BIT"
1747 "@
1748 cv.dotusp.sci.b\t%0,%1,%2
1749 cv.dotusp.sc.b\t%0,%1,%2"
1750 [(set_attr "type" "arith")
1751 (set_attr "mode" "SI")])
1754 (define_insn "riscv_cv_simd_dotsp_h_si"
1755 [(set (match_operand:SI 0 "register_operand" "=r")
1756 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1757 (match_operand:SI 2 "register_operand" "r")]
1758 UNSPEC_CV_DOTSP_H))]
1759 "TARGET_XCVSIMD && !TARGET_64BIT"
1760 "cv.dotsp.h\t%0,%1,%2"
1761 [(set_attr "type" "arith")
1762 (set_attr "mode" "SI")])
1765 (define_insn "riscv_cv_simd_dotsp_b_si"
1766 [(set (match_operand:SI 0 "register_operand" "=r")
1767 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1768 (match_operand:SI 2 "register_operand" "r")]
1769 UNSPEC_CV_DOTSP_B))]
1770 "TARGET_XCVSIMD && !TARGET_64BIT"
1771 "cv.dotsp.b\t%0,%1,%2"
1772 [(set_attr "type" "arith")
1773 (set_attr "mode" "SI")])
1776 (define_insn "riscv_cv_simd_dotsp_sc_h_si"
1777 [(set (match_operand:SI 0 "register_operand" "=r,r")
1778 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1779 (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")]
1780 UNSPEC_CV_DOTSP_SC_H))]
1781 "TARGET_XCVSIMD && !TARGET_64BIT"
1782 "@
1783 cv.dotsp.sci.h\t%0,%1,%2
1784 cv.dotsp.sc.h\t%0,%1,%2"
1785 [(set_attr "type" "arith")
1786 (set_attr "mode" "SI")])
1789 (define_insn "riscv_cv_simd_dotsp_sc_b_si"
1790 [(set (match_operand:SI 0 "register_operand" "=r,r")
1791 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1792 (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")]
1793 UNSPEC_CV_DOTSP_SC_B))]
1794 "TARGET_XCVSIMD && !TARGET_64BIT"
1795 "@
1796 cv.dotsp.sci.b\t%0,%1,%2
1797 cv.dotsp.sc.b\t%0,%1,%2"
1798 [(set_attr "type" "arith")
1799 (set_attr "mode" "SI")])
1802 (define_insn "riscv_cv_simd_sdotup_h_si"
1803 [(set (match_operand:SI 0 "register_operand" "=r")
1804 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1805 (match_operand:SI 2 "register_operand" "r")
1806 (match_operand:SI 3 "register_operand" "0")]
1807 UNSPEC_CV_SDOTUP_H))]
1808 "TARGET_XCVSIMD && !TARGET_64BIT"
1809 "cv.sdotup.h\t%0,%1,%2"
1810 [(set_attr "type" "arith")
1811 (set_attr "mode" "SI")])
1814 (define_insn "riscv_cv_simd_sdotup_b_si"
1815 [(set (match_operand:SI 0 "register_operand" "=r")
1816 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1817 (match_operand:SI 2 "register_operand" "r")
1818 (match_operand:SI 3 "register_operand" "0")]
1819 UNSPEC_CV_SDOTUP_B))]
1820 "TARGET_XCVSIMD && !TARGET_64BIT"
1821 "cv.sdotup.b\t%0,%1,%2"
1822 [(set_attr "type" "arith")
1823 (set_attr "mode" "SI")])
1826 (define_insn "riscv_cv_simd_sdotup_sc_h_si"
1827 [(set (match_operand:SI 0 "register_operand" "=r,r")
1828 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1829 (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")
1830 (match_operand:SI 3 "register_operand" "0,0")]
1831 UNSPEC_CV_SDOTUP_SC_H))]
1832 "TARGET_XCVSIMD && !TARGET_64BIT"
1833 "@
1834 cv.sdotup.sci.h\t%0,%1,%2
1835 cv.sdotup.sc.h\t%0,%1,%2"
1836 [(set_attr "type" "arith")
1837 (set_attr "mode" "SI")])
1840 (define_insn "riscv_cv_simd_sdotup_sc_b_si"
1841 [(set (match_operand:SI 0 "register_operand" "=r,r")
1842 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1843 (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")
1844 (match_operand:SI 3 "register_operand" "0,0")]
1845 UNSPEC_CV_SDOTUP_SC_B))]
1846 "TARGET_XCVSIMD && !TARGET_64BIT"
1847 "@
1848 cv.sdotup.sci.b\t%0,%1,%2
1849 cv.sdotup.sc.b\t%0,%1,%2"
1850 [(set_attr "type" "arith")
1851 (set_attr "mode" "SI")])
1854 (define_insn "riscv_cv_simd_sdotusp_h_si"
1855 [(set (match_operand:SI 0 "register_operand" "=r")
1856 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1857 (match_operand:SI 2 "register_operand" "r")
1858 (match_operand:SI 3 "register_operand" "0")]
1859 UNSPEC_CV_SDOTUSP_H))]
1860 "TARGET_XCVSIMD && !TARGET_64BIT"
1861 "cv.sdotusp.h\t%0,%1,%2"
1862 [(set_attr "type" "arith")
1863 (set_attr "mode" "SI")])
1866 (define_insn "riscv_cv_simd_sdotusp_b_si"
1867 [(set (match_operand:SI 0 "register_operand" "=r")
1868 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1869 (match_operand:SI 2 "register_operand" "r")
1870 (match_operand:SI 3 "register_operand" "0")]
1871 UNSPEC_CV_SDOTUSP_B))]
1872 "TARGET_XCVSIMD && !TARGET_64BIT"
1873 "cv.sdotusp.b\t%0,%1,%2"
1874 [(set_attr "type" "arith")
1875 (set_attr "mode" "SI")])
1878 (define_insn "riscv_cv_simd_sdotusp_sc_h_si"
1879 [(set (match_operand:SI 0 "register_operand" "=r,r")
1880 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1881 (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")
1882 (match_operand:SI 3 "register_operand" "0,0")]
1883 UNSPEC_CV_SDOTUSP_SC_H))]
1884 "TARGET_XCVSIMD && !TARGET_64BIT"
1885 "@
1886 cv.sdotusp.sci.h\t%0,%1,%2
1887 cv.sdotusp.sc.h\t%0,%1,%2"
1888 [(set_attr "type" "arith")
1889 (set_attr "mode" "SI")])
1892 (define_insn "riscv_cv_simd_sdotusp_sc_b_si"
1893 [(set (match_operand:SI 0 "register_operand" "=r,r")
1894 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1895 (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")
1896 (match_operand:SI 3 "register_operand" "0,0")]
1897 UNSPEC_CV_SDOTUSP_SC_B))]
1898 "TARGET_XCVSIMD && !TARGET_64BIT"
1899 "@
1900 cv.sdotusp.sci.b\t%0,%1,%2
1901 cv.sdotusp.sc.b\t%0,%1,%2"
1902 [(set_attr "type" "arith")
1903 (set_attr "mode" "SI")])
1906 (define_insn "riscv_cv_simd_sdotsp_h_si"
1907 [(set (match_operand:SI 0 "register_operand" "=r")
1908 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1909 (match_operand:SI 2 "register_operand" "r")
1910 (match_operand:SI 3 "register_operand" "0")]
1911 UNSPEC_CV_SDOTSP_H))]
1912 "TARGET_XCVSIMD && !TARGET_64BIT"
1913 "cv.sdotsp.h\t%0,%1,%2"
1914 [(set_attr "type" "arith")
1915 (set_attr "mode" "SI")])
1918 (define_insn "riscv_cv_simd_sdotsp_b_si"
1919 [(set (match_operand:SI 0 "register_operand" "=r")
1920 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1921 (match_operand:SI 2 "register_operand" "r")
1922 (match_operand:SI 3 "register_operand" "0")]
1923 UNSPEC_CV_SDOTSP_B))]
1924 "TARGET_XCVSIMD && !TARGET_64BIT"
1925 "cv.sdotsp.b\t%0,%1,%2"
1926 [(set_attr "type" "arith")
1927 (set_attr "mode" "SI")])
1930 (define_insn "riscv_cv_simd_sdotsp_sc_h_si"
1931 [(set (match_operand:SI 0 "register_operand" "=r,r")
1932 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1933 (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")
1934 (match_operand:SI 3 "register_operand" "0,0")]
1935 UNSPEC_CV_SDOTSP_SC_H))]
1936 "TARGET_XCVSIMD && !TARGET_64BIT"
1937 "@
1938 cv.sdotsp.sci.h\t%0,%1,%2
1939 cv.sdotsp.sc.h\t%0,%1,%2"
1940 [(set_attr "type" "arith")
1941 (set_attr "mode" "SI")])
1944 (define_insn "riscv_cv_simd_sdotsp_sc_b_si"
1945 [(set (match_operand:SI 0 "register_operand" "=r,r")
1946 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
1947 (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")
1948 (match_operand:SI 3 "register_operand" "0,0")]
1949 UNSPEC_CV_SDOTSP_SC_B))]
1950 "TARGET_XCVSIMD && !TARGET_64BIT"
1951 "@
1952 cv.sdotsp.sci.b\t%0,%1,%2
1953 cv.sdotsp.sc.b\t%0,%1,%2"
1954 [(set_attr "type" "arith")
1955 (set_attr "mode" "SI")])
1958 ;;CORE-V SIMD SHUFFLE AND PACK
1959 (define_insn "riscv_cv_simd_shuffle_h_si"
1960 [(set (match_operand:SI 0 "register_operand" "=r")
1961 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1962 (match_operand:SI 2 "register_operand" "r")]
1963 UNSPEC_CV_SHUFFLE_H))]
1964 "TARGET_XCVSIMD && !TARGET_64BIT"
1965 "cv.shuffle.h\t%0,%1,%2"
1966 [(set_attr "type" "arith")
1967 (set_attr "mode" "SI")])
1970 (define_insn "riscv_cv_simd_shuffle_sci_h_si"
1971 [(set (match_operand:SI 0 "register_operand" "=r")
1972 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1973 (match_operand:QI 2 "const_int6_operand" "CV_simd_un6")]
1974 UNSPEC_CV_SHUFFLE_SCI_H))]
1975 "TARGET_XCVSIMD && !TARGET_64BIT"
1976 "cv.shuffle.sci.h\t%0,%1,%2"
1977 [(set_attr "type" "arith")
1978 (set_attr "mode" "SI")])
1981 (define_insn "riscv_cv_simd_shuffle_b_si"
1982 [(set (match_operand:SI 0 "register_operand" "=r")
1983 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1984 (match_operand:SI 2 "register_operand" "r")]
1985 UNSPEC_CV_SHUFFLE_B))]
1986 "TARGET_XCVSIMD && !TARGET_64BIT"
1987 "cv.shuffle.b\t%0,%1,%2"
1988 [(set_attr "type" "arith")
1989 (set_attr "mode" "SI")])
1992 (define_insn "riscv_cv_simd_shuffle_sci_b_si"
1993 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1994 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r")
1995 (match_operand:QI 2 "const_int_operand" "CV_simd_un6,CV_simd_i01,CV_simd_i02,CV_simd_i03")]
1996 UNSPEC_CV_SHUFFLE_SCI_B))]
1997 "TARGET_XCVSIMD && !TARGET_64BIT"
1998 "@
1999 cv.shufflei0.sci.b\t%0,%1,%Y2
2000 cv.shufflei1.sci.b\t%0,%1,%Y2
2001 cv.shufflei2.sci.b\t%0,%1,%Y2
2002 cv.shufflei3.sci.b\t%0,%1,%Y2"
2003 [(set_attr "type" "arith")
2004 (set_attr "mode" "SI")])
2007 (define_insn "riscv_cv_simd_shuffle2_h_si"
2008 [(set (match_operand:SI 0 "register_operand" "=r")
2009 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2010 (match_operand:SI 2 "register_operand" "r")
2011 (match_operand:SI 3 "register_operand" "0")]
2012 UNSPEC_CV_SHUFFLE2_H))]
2013 "TARGET_XCVSIMD && !TARGET_64BIT"
2014 "cv.shuffle2.h\t%0,%1,%2"
2015 [(set_attr "type" "arith")
2016 (set_attr "mode" "SI")])
2019 (define_insn "riscv_cv_simd_shuffle2_b_si"
2020 [(set (match_operand:SI 0 "register_operand" "=r")
2021 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2022 (match_operand:SI 2 "register_operand" "r")
2023 (match_operand:SI 3 "register_operand" "0")]
2024 UNSPEC_CV_SHUFFLE2_B))]
2025 "TARGET_XCVSIMD && !TARGET_64BIT"
2026 "cv.shuffle2.b\t%0,%1,%2"
2027 [(set_attr "type" "arith")
2028 (set_attr "mode" "SI")])
2031 (define_insn "riscv_cv_simd_packhi_h_si"
2032 [(set (match_operand:SI 0 "register_operand" "=r")
2033 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2034 (match_operand:SI 2 "register_operand" "r")]
2035 UNSPEC_CV_PACKHI_H))]
2036 "TARGET_XCVSIMD && !TARGET_64BIT"
2037 "cv.pack.h\t%0,%1,%2"
2038 [(set_attr "type" "arith")
2039 (set_attr "mode" "SI")])
2042 (define_insn "riscv_cv_simd_packlo_h_si"
2043 [(set (match_operand:SI 0 "register_operand" "=r")
2044 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2045 (match_operand:SI 2 "register_operand" "r")]
2046 UNSPEC_CV_PACKLO_H))]
2047 "TARGET_XCVSIMD && !TARGET_64BIT"
2048 "cv.pack\t%0,%1,%2"
2049 [(set_attr "type" "arith")
2050 (set_attr "mode" "SI")])
2053 (define_insn "riscv_cv_simd_packhi_b_si"
2054 [(set (match_operand:SI 0 "register_operand" "=r")
2055 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2056 (match_operand:SI 2 "register_operand" "r")
2057 (match_operand:SI 3 "register_operand" "0")]
2058 UNSPEC_CV_PACKHI_B))]
2059 "TARGET_XCVSIMD && !TARGET_64BIT"
2060 "cv.packhi.b\t%0,%1,%2"
2061 [(set_attr "type" "arith")
2062 (set_attr "mode" "SI")])
2065 (define_insn "riscv_cv_simd_packlo_b_si"
2066 [(set (match_operand:SI 0 "register_operand" "=r")
2067 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2068 (match_operand:SI 2 "register_operand" "r")
2069 (match_operand:SI 3 "register_operand" "0")]
2070 UNSPEC_CV_PACKLO_B))]
2071 "TARGET_XCVSIMD && !TARGET_64BIT"
2072 "cv.packlo.b\t%0,%1,%2"
2073 [(set_attr "type" "arith")
2074 (set_attr "mode" "SI")])
2077 ;;CORE-V SIMD COMPARISON
2078 (define_insn "riscv_cv_simd_cmpeq_h_si"
2079 [(set (match_operand:SI 0 "register_operand" "=r")
2080 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2081 (match_operand:SI 2 "register_operand" "r")]
2082 UNSPEC_CV_CMPEQ_H))]
2083 "TARGET_XCVSIMD && !TARGET_64BIT"
2084 "cv.cmpeq.h\t%0,%1,%2"
2085 [(set_attr "type" "arith")
2086 (set_attr "mode" "SI")])
2089 (define_insn "riscv_cv_simd_cmpeq_b_si"
2090 [(set (match_operand:SI 0 "register_operand" "=r")
2091 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2092 (match_operand:SI 2 "register_operand" "r")]
2093 UNSPEC_CV_CMPEQ_B))]
2094 "TARGET_XCVSIMD && !TARGET_64BIT"
2095 "cv.cmpeq.b\t%0,%1,%2"
2096 [(set_attr "type" "arith")
2097 (set_attr "mode" "SI")])
2100 (define_insn "riscv_cv_simd_cmpeq_sc_h_si"
2101 [(set (match_operand:SI 0 "register_operand" "=r,r")
2102 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
2103 (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")]
2104 UNSPEC_CV_CMPEQ_SC_H))]
2105 "TARGET_XCVSIMD && !TARGET_64BIT"
2106 "@
2107 cv.cmpeq.sci.h\t%0,%1,%2
2108 cv.cmpeq.sc.h\t%0,%1,%2"
2109 [(set_attr "type" "arith")
2110 (set_attr "mode" "SI")])
2113 (define_insn "riscv_cv_simd_cmpeq_sc_b_si"
2114 [(set (match_operand:SI 0 "register_operand" "=r,r")
2115 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
2116 (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")]
2117 UNSPEC_CV_CMPEQ_SC_B))]
2118 "TARGET_XCVSIMD && !TARGET_64BIT"
2119 "@
2120 cv.cmpeq.sci.b\t%0,%1,%2
2121 cv.cmpeq.sc.b\t%0,%1,%2"
2122 [(set_attr "type" "arith")
2123 (set_attr "mode" "SI")])
2126 (define_insn "riscv_cv_simd_cmpne_h_si"
2127 [(set (match_operand:SI 0 "register_operand" "=r")
2128 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2129 (match_operand:SI 2 "register_operand" "r")]
2130 UNSPEC_CV_CMPNE_H))]
2131 "TARGET_XCVSIMD && !TARGET_64BIT"
2132 "cv.cmpne.h\t%0,%1,%2"
2133 [(set_attr "type" "arith")
2134 (set_attr "mode" "SI")])
2137 (define_insn "riscv_cv_simd_cmpne_b_si"
2138 [(set (match_operand:SI 0 "register_operand" "=r")
2139 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2140 (match_operand:SI 2 "register_operand" "r")]
2141 UNSPEC_CV_CMPNE_B))]
2142 "TARGET_XCVSIMD && !TARGET_64BIT"
2143 "cv.cmpne.b\t%0,%1,%2"
2144 [(set_attr "type" "arith")
2145 (set_attr "mode" "SI")])
2148 (define_insn "riscv_cv_simd_cmpne_sc_h_si"
2149 [(set (match_operand:SI 0 "register_operand" "=r,r")
2150 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
2151 (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")]
2152 UNSPEC_CV_CMPNE_SC_H))]
2153 "TARGET_XCVSIMD && !TARGET_64BIT"
2154 "@
2155 cv.cmpne.sci.h\t%0,%1,%2
2156 cv.cmpne.sc.h\t%0,%1,%2"
2157 [(set_attr "type" "arith")
2158 (set_attr "mode" "SI")])
2161 (define_insn "riscv_cv_simd_cmpne_sc_b_si"
2162 [(set (match_operand:SI 0 "register_operand" "=r,r")
2163 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
2164 (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")]
2165 UNSPEC_CV_CMPNE_SC_B))]
2166 "TARGET_XCVSIMD && !TARGET_64BIT"
2167 "@
2168 cv.cmpne.sci.b\t%0,%1,%2
2169 cv.cmpne.sc.b\t%0,%1,%2"
2170 [(set_attr "type" "arith")
2171 (set_attr "mode" "SI")])
2174 (define_insn "riscv_cv_simd_cmpgt_h_si"
2175 [(set (match_operand:SI 0 "register_operand" "=r")
2176 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2177 (match_operand:SI 2 "register_operand" "r")]
2178 UNSPEC_CV_CMPGT_H))]
2179 "TARGET_XCVSIMD && !TARGET_64BIT"
2180 "cv.cmpgt.h\t%0,%1,%2"
2181 [(set_attr "type" "arith")
2182 (set_attr "mode" "SI")])
2185 (define_insn "riscv_cv_simd_cmpgt_b_si"
2186 [(set (match_operand:SI 0 "register_operand" "=r")
2187 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2188 (match_operand:SI 2 "register_operand" "r")]
2189 UNSPEC_CV_CMPGT_B))]
2190 "TARGET_XCVSIMD && !TARGET_64BIT"
2191 "cv.cmpgt.b\t%0,%1,%2"
2192 [(set_attr "type" "arith")
2193 (set_attr "mode" "SI")])
2196 (define_insn "riscv_cv_simd_cmpgt_sc_h_si"
2197 [(set (match_operand:SI 0 "register_operand" "=r,r")
2198 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
2199 (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")]
2200 UNSPEC_CV_CMPGT_SC_H))]
2201 "TARGET_XCVSIMD && !TARGET_64BIT"
2202 "@
2203 cv.cmpgt.sci.h\t%0,%1,%2
2204 cv.cmpgt.sc.h\t%0,%1,%2"
2205 [(set_attr "type" "arith")
2206 (set_attr "mode" "SI")])
2209 (define_insn "riscv_cv_simd_cmpgt_sc_b_si"
2210 [(set (match_operand:SI 0 "register_operand" "=r,r")
2211 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
2212 (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")]
2213 UNSPEC_CV_CMPGT_SC_B))]
2214 "TARGET_XCVSIMD && !TARGET_64BIT"
2215 "@
2216 cv.cmpgt.sci.b\t%0,%1,%2
2217 cv.cmpgt.sc.b\t%0,%1,%2"
2218 [(set_attr "type" "arith")
2219 (set_attr "mode" "SI")])
2222 (define_insn "riscv_cv_simd_cmpge_h_si"
2223 [(set (match_operand:SI 0 "register_operand" "=r")
2224 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2225 (match_operand:SI 2 "register_operand" "r")]
2226 UNSPEC_CV_CMPGE_H))]
2227 "TARGET_XCVSIMD && !TARGET_64BIT"
2228 "cv.cmpge.h\t%0,%1,%2"
2229 [(set_attr "type" "arith")
2230 (set_attr "mode" "SI")])
2233 (define_insn "riscv_cv_simd_cmpge_b_si"
2234 [(set (match_operand:SI 0 "register_operand" "=r")
2235 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2236 (match_operand:SI 2 "register_operand" "r")]
2237 UNSPEC_CV_CMPGE_B))]
2238 "TARGET_XCVSIMD && !TARGET_64BIT"
2239 "cv.cmpge.b\t%0,%1,%2"
2240 [(set_attr "type" "arith")
2241 (set_attr "mode" "SI")])
2244 (define_insn "riscv_cv_simd_cmpge_sc_h_si"
2245 [(set (match_operand:SI 0 "register_operand" "=r,r")
2246 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
2247 (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")]
2248 UNSPEC_CV_CMPGE_SC_H))]
2249 "TARGET_XCVSIMD && !TARGET_64BIT"
2250 "@
2251 cv.cmpge.sci.h\t%0,%1,%2
2252 cv.cmpge.sc.h\t%0,%1,%2"
2253 [(set_attr "type" "arith")
2254 (set_attr "mode" "SI")])
2257 (define_insn "riscv_cv_simd_cmpge_sc_b_si"
2258 [(set (match_operand:SI 0 "register_operand" "=r,r")
2259 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
2260 (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")]
2261 UNSPEC_CV_CMPGE_SC_B))]
2262 "TARGET_XCVSIMD && !TARGET_64BIT"
2263 "@
2264 cv.cmpge.sci.b\t%0,%1,%2
2265 cv.cmpge.sc.b\t%0,%1,%2"
2266 [(set_attr "type" "arith")
2267 (set_attr "mode" "SI")])
2270 (define_insn "riscv_cv_simd_cmplt_h_si"
2271 [(set (match_operand:SI 0 "register_operand" "=r")
2272 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2273 (match_operand:SI 2 "register_operand" "r")]
2274 UNSPEC_CV_CMPLT_H))]
2275 "TARGET_XCVSIMD && !TARGET_64BIT"
2276 "cv.cmplt.h\t%0,%1,%2"
2277 [(set_attr "type" "arith")
2278 (set_attr "mode" "SI")])
2281 (define_insn "riscv_cv_simd_cmplt_b_si"
2282 [(set (match_operand:SI 0 "register_operand" "=r")
2283 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2284 (match_operand:SI 2 "register_operand" "r")]
2285 UNSPEC_CV_CMPLT_B))]
2286 "TARGET_XCVSIMD && !TARGET_64BIT"
2287 "cv.cmplt.b\t%0,%1,%2"
2288 [(set_attr "type" "arith")
2289 (set_attr "mode" "SI")])
2292 (define_insn "riscv_cv_simd_cmplt_sc_h_si"
2293 [(set (match_operand:SI 0 "register_operand" "=r,r")
2294 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
2295 (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")]
2296 UNSPEC_CV_CMPLT_SC_H))]
2297 "TARGET_XCVSIMD && !TARGET_64BIT"
2298 "@
2299 cv.cmplt.sci.h\t%0,%1,%2
2300 cv.cmplt.sc.h\t%0,%1,%2"
2301 [(set_attr "type" "arith")
2302 (set_attr "mode" "SI")])
2305 (define_insn "riscv_cv_simd_cmplt_sc_b_si"
2306 [(set (match_operand:SI 0 "register_operand" "=r,r")
2307 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
2308 (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")]
2309 UNSPEC_CV_CMPLT_SC_B))]
2310 "TARGET_XCVSIMD && !TARGET_64BIT"
2311 "@
2312 cv.cmplt.sci.b\t%0,%1,%2
2313 cv.cmplt.sc.b\t%0,%1,%2"
2314 [(set_attr "type" "arith")
2315 (set_attr "mode" "SI")])
2318 (define_insn "riscv_cv_simd_cmple_h_si"
2319 [(set (match_operand:SI 0 "register_operand" "=r")
2320 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2321 (match_operand:SI 2 "register_operand" "r")]
2322 UNSPEC_CV_CMPLE_H))]
2323 "TARGET_XCVSIMD && !TARGET_64BIT"
2324 "cv.cmple.h\t%0,%1,%2"
2325 [(set_attr "type" "arith")
2326 (set_attr "mode" "SI")])
2329 (define_insn "riscv_cv_simd_cmple_b_si"
2330 [(set (match_operand:SI 0 "register_operand" "=r")
2331 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2332 (match_operand:SI 2 "register_operand" "r")]
2333 UNSPEC_CV_CMPLE_B))]
2334 "TARGET_XCVSIMD && !TARGET_64BIT"
2335 "cv.cmple.b\t%0,%1,%2"
2336 [(set_attr "type" "arith")
2337 (set_attr "mode" "SI")])
2340 (define_insn "riscv_cv_simd_cmple_sc_h_si"
2341 [(set (match_operand:SI 0 "register_operand" "=r,r")
2342 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
2343 (match_operand:HI 2 "int6s_operand" "CV_simd_si6,r")]
2344 UNSPEC_CV_CMPLE_SC_H))]
2345 "TARGET_XCVSIMD && !TARGET_64BIT"
2346 "@
2347 cv.cmple.sci.h\t%0,%1,%2
2348 cv.cmple.sc.h\t%0,%1,%2"
2349 [(set_attr "type" "arith")
2350 (set_attr "mode" "SI")])
2353 (define_insn "riscv_cv_simd_cmple_sc_b_si"
2354 [(set (match_operand:SI 0 "register_operand" "=r,r")
2355 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
2356 (match_operand:QI 2 "int6s_operand" "CV_simd_si6,r")]
2357 UNSPEC_CV_CMPLE_SC_B))]
2358 "TARGET_XCVSIMD && !TARGET_64BIT"
2359 "@
2360 cv.cmple.sci.b\t%0,%1,%2
2361 cv.cmple.sc.b\t%0,%1,%2"
2362 [(set_attr "type" "arith")
2363 (set_attr "mode" "SI")])
2366 (define_insn "riscv_cv_simd_cmpgtu_h_si"
2367 [(set (match_operand:SI 0 "register_operand" "=r")
2368 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2369 (match_operand:SI 2 "register_operand" "r")]
2370 UNSPEC_CV_CMPGTU_H))]
2371 "TARGET_XCVSIMD && !TARGET_64BIT"
2372 "cv.cmpgtu.h\t%0,%1,%2"
2373 [(set_attr "type" "arith")
2374 (set_attr "mode" "SI")])
2377 (define_insn "riscv_cv_simd_cmpgtu_b_si"
2378 [(set (match_operand:SI 0 "register_operand" "=r")
2379 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2380 (match_operand:SI 2 "register_operand" "r")]
2381 UNSPEC_CV_CMPGTU_B))]
2382 "TARGET_XCVSIMD && !TARGET_64BIT"
2383 "cv.cmpgtu.b\t%0,%1,%2"
2384 [(set_attr "type" "arith")
2385 (set_attr "mode" "SI")])
2388 (define_insn "riscv_cv_simd_cmpgtu_sc_h_si"
2389 [(set (match_operand:SI 0 "register_operand" "=r,r")
2390 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
2391 (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")]
2392 UNSPEC_CV_CMPGTU_SC_H))]
2393 "TARGET_XCVSIMD && !TARGET_64BIT"
2394 "@
2395 cv.cmpgtu.sci.h\t%0,%1,%2
2396 cv.cmpgtu.sc.h\t%0,%1,%2"
2397 [(set_attr "type" "arith")
2398 (set_attr "mode" "SI")])
2401 (define_insn "riscv_cv_simd_cmpgtu_sc_b_si"
2402 [(set (match_operand:SI 0 "register_operand" "=r,r")
2403 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
2404 (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")]
2405 UNSPEC_CV_CMPGTU_SC_B))]
2406 "TARGET_XCVSIMD && !TARGET_64BIT"
2407 "@
2408 cv.cmpgtu.sci.b\t%0,%1,%2
2409 cv.cmpgtu.sc.b\t%0,%1,%2"
2410 [(set_attr "type" "arith")
2411 (set_attr "mode" "SI")])
2414 (define_insn "riscv_cv_simd_cmpgeu_h_si"
2415 [(set (match_operand:SI 0 "register_operand" "=r")
2416 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2417 (match_operand:SI 2 "register_operand" "r")]
2418 UNSPEC_CV_CMPGEU_H))]
2419 "TARGET_XCVSIMD && !TARGET_64BIT"
2420 "cv.cmpgeu.h\t%0,%1,%2"
2421 [(set_attr "type" "arith")
2422 (set_attr "mode" "SI")])
2425 (define_insn "riscv_cv_simd_cmpgeu_b_si"
2426 [(set (match_operand:SI 0 "register_operand" "=r")
2427 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2428 (match_operand:SI 2 "register_operand" "r")]
2429 UNSPEC_CV_CMPGEU_B))]
2430 "TARGET_XCVSIMD && !TARGET_64BIT"
2431 "cv.cmpgeu.b\t%0,%1,%2"
2432 [(set_attr "type" "arith")
2433 (set_attr "mode" "SI")])
2436 (define_insn "riscv_cv_simd_cmpgeu_sc_h_si"
2437 [(set (match_operand:SI 0 "register_operand" "=r,r")
2438 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
2439 (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")]
2440 UNSPEC_CV_CMPGEU_SC_H))]
2441 "TARGET_XCVSIMD && !TARGET_64BIT"
2442 "@
2443 cv.cmpgeu.sci.h\t%0,%1,%2
2444 cv.cmpgeu.sc.h\t%0,%1,%2"
2445 [(set_attr "type" "arith")
2446 (set_attr "mode" "SI")])
2449 (define_insn "riscv_cv_simd_cmpgeu_sc_b_si"
2450 [(set (match_operand:SI 0 "register_operand" "=r,r")
2451 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
2452 (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")]
2453 UNSPEC_CV_CMPGEU_SC_B))]
2454 "TARGET_XCVSIMD && !TARGET_64BIT"
2455 "@
2456 cv.cmpgeu.sci.b\t%0,%1,%2
2457 cv.cmpgeu.sc.b\t%0,%1,%2"
2458 [(set_attr "type" "arith")
2459 (set_attr "mode" "SI")])
2462 (define_insn "riscv_cv_simd_cmpltu_h_si"
2463 [(set (match_operand:SI 0 "register_operand" "=r")
2464 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2465 (match_operand:SI 2 "register_operand" "r")]
2466 UNSPEC_CV_CMPLTU_H))]
2467 "TARGET_XCVSIMD && !TARGET_64BIT"
2468 "cv.cmpltu.h\t%0,%1,%2"
2469 [(set_attr "type" "arith")
2470 (set_attr "mode" "SI")])
2473 (define_insn "riscv_cv_simd_cmpltu_b_si"
2474 [(set (match_operand:SI 0 "register_operand" "=r")
2475 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2476 (match_operand:SI 2 "register_operand" "r")]
2477 UNSPEC_CV_CMPLTU_B))]
2478 "TARGET_XCVSIMD && !TARGET_64BIT"
2479 "cv.cmpltu.b\t%0,%1,%2"
2480 [(set_attr "type" "arith")
2481 (set_attr "mode" "SI")])
2484 (define_insn "riscv_cv_simd_cmpltu_sc_h_si"
2485 [(set (match_operand:SI 0 "register_operand" "=r,r")
2486 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
2487 (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")]
2488 UNSPEC_CV_CMPLTU_SC_H))]
2489 "TARGET_XCVSIMD && !TARGET_64BIT"
2490 "@
2491 cv.cmpltu.sci.h\t%0,%1,%2
2492 cv.cmpltu.sc.h\t%0,%1,%2"
2493 [(set_attr "type" "arith")
2494 (set_attr "mode" "SI")])
2497 (define_insn "riscv_cv_simd_cmpltu_sc_b_si"
2498 [(set (match_operand:SI 0 "register_operand" "=r,r")
2499 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
2500 (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")]
2501 UNSPEC_CV_CMPLTU_SC_B))]
2502 "TARGET_XCVSIMD && !TARGET_64BIT"
2503 "@
2504 cv.cmpltu.sci.b\t%0,%1,%2
2505 cv.cmpltu.sc.b\t%0,%1,%2"
2506 [(set_attr "type" "arith")
2507 (set_attr "mode" "SI")])
2510 (define_insn "riscv_cv_simd_cmpleu_h_si"
2511 [(set (match_operand:SI 0 "register_operand" "=r")
2512 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2513 (match_operand:SI 2 "register_operand" "r")]
2514 UNSPEC_CV_CMPLEU_H))]
2515 "TARGET_XCVSIMD && !TARGET_64BIT"
2516 "cv.cmpleu.h\t%0,%1,%2"
2517 [(set_attr "type" "arith")
2518 (set_attr "mode" "SI")])
2521 (define_insn "riscv_cv_simd_cmpleu_b_si"
2522 [(set (match_operand:SI 0 "register_operand" "=r")
2523 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
2524 (match_operand:SI 2 "register_operand" "r")]
2525 UNSPEC_CV_CMPLEU_B))]
2526 "TARGET_XCVSIMD && !TARGET_64BIT"
2527 "cv.cmpleu.b\t%0,%1,%2"
2528 [(set_attr "type" "arith")
2529 (set_attr "mode" "SI")])
2532 (define_insn "riscv_cv_simd_cmpleu_sc_h_si"
2533 [(set (match_operand:SI 0 "register_operand" "=r,r")
2534 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
2535 (match_operand:HI 2 "int6_operand" "CV_simd_un6,r")]
2536 UNSPEC_CV_CMPLEU_SC_H))]
2537 "TARGET_XCVSIMD && !TARGET_64BIT"
2538 "@
2539 cv.cmpleu.sci.h\t%0,%1,%2
2540 cv.cmpleu.sc.h\t%0,%1,%2"
2541 [(set_attr "type" "arith")
2542 (set_attr "mode" "SI")])
2545 (define_insn "riscv_cv_simd_cmpleu_sc_b_si"
2546 [(set (match_operand:SI 0 "register_operand" "=r,r")
2547 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r")
2548 (match_operand:QI 2 "int6_operand" "CV_simd_un6,r")]
2549 UNSPEC_CV_CMPLEU_SC_B))]
2550 "TARGET_XCVSIMD && !TARGET_64BIT"
2551 "@
2552 cv.cmpleu.sci.b\t%0,%1,%2
2553 cv.cmpleu.sc.b\t%0,%1,%2"
2554 [(set_attr "type" "arith")
2555 (set_attr "mode" "SI")])
2558 ;;CORE-V SIMD COMPLEX
2559 (define_insn "riscv_cv_simd_cplxmul_r_si"
2560 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2561 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r")
2562 (match_operand:SI 2 "register_operand" "r,r,r,r")
2563 (match_operand:SI 3 "register_operand" "0,0,0,0")
2564 (match_operand:QI 4 "const_int2_operand" "J,c01,c02,c03")]
2565 UNSPEC_CV_CPLXMUL_R))]
2566 "TARGET_XCVSIMD && !TARGET_64BIT"
2567 "@
2568 cv.cplxmul.r\t%0,%1,%2
2569 cv.cplxmul.r.div2\t%0,%1,%2
2570 cv.cplxmul.r.div4\t%0,%1,%2
2571 cv.cplxmul.r.div8\t%0,%1,%2"
2572 [(set_attr "type" "arith")
2573 (set_attr "mode" "SI")])
2576 (define_insn "riscv_cv_simd_cplxmul_i_si"
2577 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2578 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r")
2579 (match_operand:SI 2 "register_operand" "r,r,r,r")
2580 (match_operand:SI 3 "register_operand" "0,0,0,0")
2581 (match_operand:QI 4 "const_int2_operand" "J,c01,c02,c03")]
2582 UNSPEC_CV_CPLXMUL_I))]
2583 "TARGET_XCVSIMD && !TARGET_64BIT"
2584 "@
2585 cv.cplxmul.i\t%0,%1,%2
2586 cv.cplxmul.i.div2\t%0,%1,%2
2587 cv.cplxmul.i.div4\t%0,%1,%2
2588 cv.cplxmul.i.div8\t%0,%1,%2"
2589 [(set_attr "type" "arith")
2590 (set_attr "mode" "SI")])
2593 (define_insn "riscv_cv_simd_cplxconj_si"
2594 [(set (match_operand:SI 0 "register_operand" "=r")
2595 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
2596 UNSPEC_CV_CPLXCONJ))]
2597 "TARGET_XCVSIMD && !TARGET_64BIT"
2598 "cv.cplxconj\t%0,%1"
2599 [(set_attr "type" "arith")
2600 (set_attr "mode" "SI")])
2603 (define_insn "riscv_cv_simd_subrotmj_si"
2604 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
2605 (unspec:SI [(match_operand:SI 1 "register_operand" "r,r,r,r")
2606 (match_operand:SI 2 "register_operand" "r,r,r,r")
2607 (match_operand:QI 3 "const_int2_operand" "J,c01,c02,c03")]
2608 UNSPEC_CV_SUBROTMJ))]
2609 "TARGET_XCVSIMD && !TARGET_64BIT"
2610 "@
2611 cv.subrotmj\t%0,%1,%2
2612 cv.subrotmj.div2\t%0,%1,%2
2613 cv.subrotmj.div4\t%0,%1,%2
2614 cv.subrotmj.div8\t%0,%1,%2"
2615 [(set_attr "type" "arith")
2616 (set_attr "mode" "SI")])
2618 ;; XCVBI Instructions
2619 (define_insn "*cv_branch<mode>"
2620 [(set (pc)
2621 (if_then_else
2622 (match_operator 1 "equality_operator"
2623 [(match_operand:X 2 "register_operand" "r")
2624 (match_operand:X 3 "const_int5s_operand" "CV_bi_sign5")])
2625 (label_ref (match_operand 0 "" ""))
2626 (pc)))]
2627 "TARGET_XCVBI"
2628 {
2629 if (get_attr_length (insn) == 12)
2630 return "cv.b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:";
2632 return "cv.b%C1imm\t%2,%3,%0";
2633 }
2634 [(set_attr "type" "branch")
2635 (set_attr "mode" "none")])
2637 (define_insn "*branch<mode>"
2638 [(set (pc)
2639 (if_then_else
2640 (match_operator 1 "ordered_comparison_operator"
2641 [(match_operand:X 2 "register_operand" "r")
2642 (match_operand:X 3 "reg_or_0_operand" "rJ")])
2643 (label_ref (match_operand 0 "" ""))
2644 (pc)))]
2645 "TARGET_XCVBI"
2646 {
2647 if (get_attr_length (insn) == 12)
2648 return "b%N1\t%2,%z3,1f; jump\t%l0,ra; 1:";
2650 return "b%C1\t%2,%z3,%l0";
2651 }
2652 [(set_attr "type" "branch")
2653 (set_attr "mode" "none")])