1 ;; GCC machine description for Matsushita MN10300
2 ;; Copyright (C) 1996-2024 Free Software Foundation, Inc.
3 ;; Contributed by Jeff Law (law@cygnus.com).
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;; The original PO technology requires these to be ordered by speed,
22 ;; so that assigner will pick the fastest.
24 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
41 ;; This is used to encode LIW patterns.
43 ;; This is for the low overhead loop instructions.
47 (include "predicates.md")
48 (include "constraints.md")
50 ;; Processor type. This attribute must exactly match the processor_type
51 ;; enumeration in mn10300.h.
52 (define_attr "cpu" "mn10300,am33,am33_2,am34"
53 (const (symbol_ref "(enum attr_cpu) mn10300_tune_cpu")))
55 ;; Used to control the "enabled" attribute on a per-instruction basis.
56 (define_attr "isa" "base,am33,am33_2,am34"
57 (const_string "base"))
59 (define_attr "enabled" ""
60 (cond [(eq_attr "isa" "base")
63 (and (eq_attr "isa" "am33")
64 (match_test "TARGET_AM33"))
67 (and (eq_attr "isa" "am33_2")
68 (match_test "TARGET_AM33_2"))
71 (and (eq_attr "isa" "am34")
72 (match_test "TARGET_AM34"))
78 (define_mode_iterator INT [QI HI SI])
81 ;; Bundling of smaller insns into a long instruction word (LIW)
82 (define_automaton "liw_bundling")
83 (automata_option "ndfa")
85 (define_cpu_unit "liw_op1_u,liw_op2_u" "liw_bundling")
87 (define_attr "liw" "op1,op2,both,either"
88 (const_string "both"))
89 ;; Note: this list must match the one defined for liw_op_names[].
90 (define_attr "liw_op" "add,cmp,sub,mov,and,or,xor,asr,lsr,asl,none,max"
91 (const_string "none"))
93 (define_insn_reservation "liw_op1" 1
94 (and (ior (eq_attr "cpu" "am33")
95 (eq_attr "cpu" "am33_2")
96 (eq_attr "cpu" "am34"))
97 (eq_attr "liw" "op1"))
99 (define_insn_reservation "liw_op2" 1
100 (and (ior (eq_attr "cpu" "am33")
101 (eq_attr "cpu" "am33_2")
102 (eq_attr "cpu" "am34"))
103 (eq_attr "liw" "op2"))
105 (define_insn_reservation "liw_both" 1
106 (and (ior (eq_attr "cpu" "am33")
107 (eq_attr "cpu" "am33_2")
108 (eq_attr "cpu" "am34"))
109 (eq_attr "liw" "both"))
110 "liw_op1_u + liw_op2_u");
111 (define_insn_reservation "liw_either" 1
112 (and (ior (eq_attr "cpu" "am33")
113 (eq_attr "cpu" "am33_2")
114 (eq_attr "cpu" "am34"))
115 (eq_attr "liw" "either"))
116 "liw_op1_u | liw_op2_u");
118 ;; ----------------------------------------------------------------------
119 ;; Pipeline description.
120 ;; ----------------------------------------------------------------------
122 ;; The AM33 only has a single pipeline. It has five stages (fetch,
123 ;; decode, execute, memory access, writeback) each of which normally
124 ;; takes a single CPU clock cycle.
126 ;; The timings attribute consists of two numbers, the first is the
127 ;; throughput, which is the number of cycles the instruction takes
128 ;; to execute and generate a result. The second is the latency
129 ;; which is the effective number of cycles the instruction takes to
130 ;; execute if its result is used by the following instruction. The
131 ;; latency is always greater than or equal to the throughput.
132 ;; These values were taken from the Appendix of the "MN103E Series
133 ;; Instruction Manual" and the timings for the AM34.
135 ;; Note - it would be nice to use strings rather than integers for
136 ;; the possible values of this attribute, so that we can have the
137 ;; gcc build mechanism check for values that are not supported by
138 ;; the reservations below. But this will not work because the code
139 ;; in mn10300_adjust_sched_cost() needs integers not strings.
141 (define_attr "timings" "" (const_int 11))
143 (define_automaton "pipelining")
144 (define_cpu_unit "throughput" "pipelining")
146 (define_insn_reservation "throughput__1_latency__1" 1
147 (eq_attr "timings" "11") "throughput")
148 (define_insn_reservation "throughput__1_latency__2" 2
149 (eq_attr "timings" "12") "throughput,nothing")
150 (define_insn_reservation "throughput__1_latency__3" 3
151 (eq_attr "timings" "13") "throughput,nothing*2")
152 (define_insn_reservation "throughput__1_latency__4" 4
153 (eq_attr "timings" "14") "throughput,nothing*3")
154 (define_insn_reservation "throughput__2_latency__2" 2
155 (eq_attr "timings" "22") "throughput*2")
156 (define_insn_reservation "throughput__2_latency__3" 3
157 (eq_attr "timings" "23") "throughput*2,nothing")
158 (define_insn_reservation "throughput__2_latency__4" 4
159 (eq_attr "timings" "24") "throughput*2,nothing*2")
160 (define_insn_reservation "throughput__2_latency__5" 5
161 (eq_attr "timings" "25") "throughput*2,nothing*3")
162 (define_insn_reservation "throughput__3_latency__3" 3
163 (eq_attr "timings" "33") "throughput*3")
164 (define_insn_reservation "throughput__3_latency__7" 7
165 (eq_attr "timings" "37") "throughput*3,nothing*4")
166 (define_insn_reservation "throughput__4_latency__4" 4
167 (eq_attr "timings" "44") "throughput*4")
168 (define_insn_reservation "throughput__4_latency__7" 7
169 (eq_attr "timings" "47") "throughput*4,nothing*3")
170 (define_insn_reservation "throughput__4_latency__8" 8
171 (eq_attr "timings" "48") "throughput*4,nothing*4")
172 (define_insn_reservation "throughput__5_latency__5" 5
173 (eq_attr "timings" "55") "throughput*5")
174 (define_insn_reservation "throughput__6_latency__6" 6
175 (eq_attr "timings" "66") "throughput*6")
176 (define_insn_reservation "throughput__7_latency__7" 7
177 (eq_attr "timings" "77") "throughput*7")
178 (define_insn_reservation "throughput__7_latency__8" 8
179 (eq_attr "timings" "78") "throughput*7,nothing")
180 (define_insn_reservation "throughput__8_latency__8" 8
181 (eq_attr "timings" "88") "throughput*8")
182 (define_insn_reservation "throughput__9_latency__9" 9
183 (eq_attr "timings" "99") "throughput*9")
184 (define_insn_reservation "throughput__8_latency_14" 14
185 (eq_attr "timings" "814") "throughput*8,nothing*6")
186 (define_insn_reservation "throughput__9_latency_10" 10
187 (eq_attr "timings" "910") "throughput*9,nothing")
188 (define_insn_reservation "throughput_10_latency_10" 10
189 (eq_attr "timings" "1010") "throughput*10")
190 (define_insn_reservation "throughput_12_latency_16" 16
191 (eq_attr "timings" "1216") "throughput*12,nothing*4")
192 (define_insn_reservation "throughput_13_latency_13" 13
193 (eq_attr "timings" "1313") "throughput*13")
194 (define_insn_reservation "throughput_14_latency_14" 14
195 (eq_attr "timings" "1414") "throughput*14")
196 (define_insn_reservation "throughput_13_latency_17" 17
197 (eq_attr "timings" "1317") "throughput*13,nothing*4")
198 (define_insn_reservation "throughput_23_latency_27" 27
199 (eq_attr "timings" "2327") "throughput*23,nothing*4")
200 (define_insn_reservation "throughput_25_latency_31" 31
201 (eq_attr "timings" "2531") "throughput*25,nothing*6")
202 (define_insn_reservation "throughput_38_latency_39" 39
203 (eq_attr "timings" "3839") "throughput*38,nothing")
204 (define_insn_reservation "throughput_39_latency_40" 40
205 (eq_attr "timings" "3940") "throughput*39,nothing")
206 (define_insn_reservation "throughput_40_latency_40" 40
207 (eq_attr "timings" "4040") "throughput*40")
208 (define_insn_reservation "throughput_41_latency_42" 42
209 (eq_attr "timings" "4142") "throughput*41,nothing")
210 (define_insn_reservation "throughput_42_latency_43" 44
211 (eq_attr "timings" "4243") "throughput*42,nothing")
212 (define_insn_reservation "throughput_43_latency_44" 44
213 (eq_attr "timings" "4344") "throughput*43,nothing")
214 (define_insn_reservation "throughput_45_latency_46" 46
215 (eq_attr "timings" "4546") "throughput*45,nothing")
216 (define_insn_reservation "throughput_47_latency_53" 53
217 (eq_attr "timings" "4753") "throughput*47,nothing*6")
219 ;; Note - the conflict between memory load/store instructions
220 ;; and floating point instructions described in section 1-7-4
221 ;; of Chapter 3 of the MN103E Series Instruction Manual is
222 ;; handled by the mn10300_adjust_sched_cost function.
224 ;; ----------------------------------------------------------------------
226 ;; ----------------------------------------------------------------------
230 (define_expand "movqi"
231 [(set (match_operand:QI 0 "nonimmediate_operand")
232 (match_operand:QI 1 "general_operand"))]
235 /* One of the ops has to be in a register. */
236 if (!register_operand (operand0, QImode)
237 && !register_operand (operand1, QImode))
238 operands[1] = force_reg (QImode, operand1);
241 (define_insn "*movqi_internal"
242 [(set (match_operand:QI 0 "nonimmediate_operand" "=*r,D*r,D*r,D,m,*z,d")
243 (match_operand:QI 1 "general_operand" " 0,D*r, i,m,D,d,*z"))]
244 "(register_operand (operands[0], QImode)
245 || register_operand (operands[1], QImode))"
247 switch (which_alternative)
258 return "movbu %1,%0";
263 [(set_attr_alternative "timings"
267 (if_then_else (eq_attr "cpu" "am34")
268 (const_int 13) (const_int 24))
269 (if_then_else (eq_attr "cpu" "am34")
270 (const_int 11) (const_int 22))
278 (define_expand "movhi"
279 [(set (match_operand:HI 0 "nonimmediate_operand")
280 (match_operand:HI 1 "general_operand"))]
283 /* One of the ops has to be in a register. */
284 if (!register_operand (operand1, HImode)
285 && !register_operand (operand0, HImode))
286 operands[1] = force_reg (HImode, operand1);
289 (define_insn "*movhi_internal"
290 [(set (match_operand:HI 0 "nonimmediate_operand" "=*r,D*r,D*r,D,m,*z,d")
291 (match_operand:HI 1 "general_operand" " 0, i,D*r,m,D,d,*z"))]
292 "(register_operand (operands[0], HImode)
293 || register_operand (operands[1], HImode))"
295 switch (which_alternative)
300 /* Note that "MOV imm8,An" is already zero-extending, and is 2 bytes.
301 We have "MOV imm16,Dn" at 3 bytes. The only win for the 4 byte
302 movu is for an 8-bit unsigned move into Rn. */
304 && CONST_INT_P (operands[1])
305 && IN_RANGE (INTVAL (operands[1]), 0x80, 0xff)
306 && REGNO_EXTENDED_P (REGNO (operands[0]), 1))
315 return "movhu %1,%0";
320 [(set_attr_alternative "timings"
323 (if_then_else (eq_attr "cpu" "am34")
324 (const_int 11) (const_int 22))
325 (if_then_else (eq_attr "cpu" "am34")
326 (const_int 13) (const_int 24))
327 (if_then_else (eq_attr "cpu" "am34")
328 (const_int 11) (const_int 22))
329 (if_then_else (eq_attr "cpu" "am34")
330 (const_int 11) (const_int 22))
331 (if_then_else (eq_attr "cpu" "am34")
332 (const_int 11) (const_int 22))
338 ;; We use this to handle addition of two values when one operand is the
339 ;; stack pointer and the other is a memory reference of some kind. Reload
340 ;; does not handle them correctly without this expander.
341 (define_expand "reload_plus_sp_const"
342 [(set (match_operand:SI 0 "register_operand" "=r")
343 (match_operand:SI 1 "impossible_plus_operand" ""))
344 (clobber (match_operand:SI 2 "register_operand" "=&A"))]
347 rtx dest, scratch, other;
350 scratch = operands[2];
352 other = XEXP (operands[1], 1);
353 if (other == stack_pointer_rtx)
354 other = XEXP (operands[1], 0);
356 if (true_regnum (other) == true_regnum (dest))
358 gcc_assert (true_regnum (scratch) != true_regnum (dest));
359 emit_move_insn (scratch, stack_pointer_rtx);
360 emit_insn (gen_addsi3 (dest, dest, scratch));
362 else if (TARGET_AM33 || REGNO_REG_CLASS (true_regnum (dest)) == ADDRESS_REGS)
364 emit_move_insn (dest, stack_pointer_rtx);
365 if (other == stack_pointer_rtx)
366 emit_insn (gen_addsi3 (dest, dest, dest));
367 else if (other != const0_rtx)
368 emit_insn (gen_addsi3 (dest, dest, other));
372 emit_move_insn (scratch, stack_pointer_rtx);
373 if (other == stack_pointer_rtx)
375 emit_move_insn (dest, scratch);
376 emit_insn (gen_addsi3 (dest, dest, dest));
378 else if (other != const0_rtx)
380 emit_move_insn (dest, other);
381 emit_insn (gen_addsi3 (dest, dest, scratch));
384 emit_move_insn (dest, scratch);
389 (define_expand "movsi"
390 [(set (match_operand:SI 0 "nonimmediate_operand")
391 (match_operand:SI 1 "general_operand"))]
394 /* One of the ops has to be in a register. */
395 if (!register_operand (operand1, SImode)
396 && !register_operand (operand0, SImode))
397 operands[1] = force_reg (SImode, operand1);
401 if (SYMBOLIC_CONST_P (operands[1]))
403 if (MEM_P (operands[0]))
404 operands[1] = force_reg (Pmode, operands[1]);
407 temp = (!can_create_pseudo_p ()
409 : gen_reg_rtx (Pmode));
410 operands[1] = mn10300_legitimize_pic_address (operands[1], temp);
413 else if (GET_CODE (operands[1]) == CONST
414 && GET_CODE (XEXP (operands[1], 0)) == PLUS
415 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
417 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
418 temp = mn10300_legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
420 operands[1] = expand_binop (SImode, add_optab, temp,
421 XEXP (XEXP (operands[1], 0), 1),
422 (!can_create_pseudo_p ()
424 : gen_reg_rtx (Pmode)),
430 (define_insn "*movsi_internal"
431 [(set (match_operand:SI 0 "nonimmediate_operand"
432 "=r,r,r,r,m,r, A,*y,*y,*z,*d")
433 (match_operand:SI 1 "general_operand"
434 " 0,O,i,r,r,m,*y, A, i,*d,*z"))]
435 "register_operand (operands[0], SImode)
436 || register_operand (operands[1], SImode)"
438 switch (which_alternative)
442 case 1: /* imm-reg. */
444 /* See movhi for a discussion of sizes for 8-bit movu. Note that the
445 24-bit movu is 6 bytes, which is the same size as the full 32-bit
446 mov form for An and Dn. So again movu is only a win for Rn. */
448 && CONST_INT_P (operands[1])
449 && REGNO_EXTENDED_P (REGNO (operands[0]), 1))
451 HOST_WIDE_INT val = INTVAL (operands[1]);
452 if (IN_RANGE (val, 0x80, 0xff)
453 || IN_RANGE (val, 0x800000, 0xffffff))
457 case 3: /* reg-reg */
458 case 4: /* reg-mem */
459 case 5: /* mem-reg */
463 case 9: /* reg-mdr */
464 case 10: /* mdr-reg */
470 [(set_attr "isa" "*,*,*,*,*,*,*,*,am33,*,*")
471 (set_attr "liw" "*,either,*,either,*,*,*,*,*,*,*")
472 (set_attr "liw_op" "mov")
473 (set_attr_alternative "timings"
478 (if_then_else (eq_attr "cpu" "am34")
479 (const_int 11) (const_int 22))
480 (if_then_else (eq_attr "cpu" "am34")
481 (const_int 13) (const_int 24))
482 (if_then_else (eq_attr "cpu" "am34")
483 (const_int 11) (const_int 22))
484 (if_then_else (eq_attr "cpu" "am34")
485 (const_int 13) (const_int 24))
492 (define_expand "movsf"
493 [(set (match_operand:SF 0 "nonimmediate_operand")
494 (match_operand:SF 1 "general_operand"))]
497 /* One of the ops has to be in a register. */
498 if (!register_operand (operand1, SFmode)
499 && !register_operand (operand0, SFmode))
500 operands[1] = force_reg (SFmode, operand1);
503 (define_insn "*movsf_internal"
504 [(set (match_operand:SF 0 "nonimmediate_operand" "=rf,r,f,r,f,r,f,r,m,f,Q,z,d")
505 (match_operand:SF 1 "general_operand" " 0,F,F,r,f,f,r,m,r,Q,f,d,z"))]
507 && (register_operand (operands[0], SFmode)
508 || register_operand (operands[1], SFmode))"
510 switch (which_alternative)
532 [(set_attr_alternative "timings"
535 (if_then_else (eq_attr "cpu" "am34")
536 (const_int 47) (const_int 25))
538 (if_then_else (eq_attr "cpu" "am34")
539 (const_int 13) (const_int 14))
540 (if_then_else (eq_attr "cpu" "am34")
541 (const_int 13) (const_int 12))
542 (if_then_else (eq_attr "cpu" "am34")
543 (const_int 13) (const_int 14))
544 (if_then_else (eq_attr "cpu" "am34")
545 (const_int 13) (const_int 24))
546 (if_then_else (eq_attr "cpu" "am34")
547 (const_int 13) (const_int 24))
548 (if_then_else (eq_attr "cpu" "am34")
549 (const_int 13) (const_int 24))
550 (if_then_else (eq_attr "cpu" "am34")
551 (const_int 13) (const_int 24))
557 ;; If the flags register is not live, generate CLR instead of MOV 0.
558 ;; For MN103, this is only legal for DATA_REGS; for AM33 this is legal
559 ;; but not a win for ADDRESS_REGS.
561 [(set (match_operand:INT 0 "register_operand" "") (const_int 0))]
562 "peep2_regno_dead_p (0, CC_REG)
563 && (REGNO_DATA_P (REGNO (operands[0]), 1)
564 || REGNO_EXTENDED_P (REGNO (operands[0]), 1))"
565 [(parallel [(set (match_dup 0) (const_int 0))
566 (clobber (reg:CC CC_REG))])]
569 (define_insn "*mov<mode>_clr"
570 [(set (match_operand:INT 0 "register_operand" "=D")
572 (clobber (reg:CC CC_REG))]
577 ;; ----------------------------------------------------------------------
579 ;; ----------------------------------------------------------------------
581 (define_insn "addsi3"
582 [(set (match_operand:SI 0 "register_operand" "=r,r,r,!*y,!r")
583 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0, r")
584 (match_operand:SI 2 "nonmemory_operand" "r,O,i, i, r")))
585 (clobber (reg:CC CC_REG))]
587 { return mn10300_output_add (operands, false); }
588 [(set_attr "timings" "11,11,11,11,22")
589 (set_attr "liw" "either,either,*,*,*")
590 (set_attr "liw_op" "add")]
593 ;; Note that ADD IMM,SP does not set the flags, so omit that here.
594 (define_insn "*addsi3_flags"
596 (compare (plus:SI (match_operand:SI 1 "register_operand" "%0, r")
597 (match_operand:SI 2 "nonmemory_operand" "ri, r"))
599 (set (match_operand:SI 0 "register_operand" "=r,!r")
600 (plus:SI (match_dup 1) (match_dup 2)))]
601 "reload_completed && mn10300_match_ccmode (insn, CCZNCmode)"
602 { return mn10300_output_add (operands, true); }
603 [(set_attr "timings" "11,22")]
606 ;; A helper to expand the above, with the CC_MODE filled in.
607 (define_expand "addsi3_flags"
608 [(parallel [(set (reg:CCZNC CC_REG)
609 (compare:CCZNC (plus:SI (match_dup 1) (match_dup 2))
611 (set (match_operand:SI 0 "register_operand")
612 (plus:SI (match_operand:SI 1 "register_operand")
613 (match_operand:SI 2 "nonmemory_operand")))])]
617 (define_insn "addc_internal"
618 [(set (match_operand:SI 0 "register_operand" "=D,r,r")
621 (ltu:SI (reg:CC CC_REG) (const_int 0))
622 (match_operand:SI 1 "register_operand" "%0,0,r"))
623 (match_operand:SI 2 "reg_or_am33_const_operand" " D,i,r")))
624 (clobber (reg:CC CC_REG))]
630 [(set_attr "isa" "*,am33,am33")]
633 (define_expand "adddi3"
634 [(set (match_operand:DI 0 "register_operand" "")
635 (plus:DI (match_operand:DI 1 "register_operand" "")
636 (match_operand:DI 2 "nonmemory_operand" "")))]
639 rtx op0l, op0h, op1l, op1h, op2l, op2h;
641 op0l = gen_lowpart (SImode, operands[0]);
642 op1l = gen_lowpart (SImode, operands[1]);
643 op2l = gen_lowpart (SImode, operands[2]);
644 op0h = gen_highpart (SImode, operands[0]);
645 op1h = gen_highpart (SImode, operands[1]);
646 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
648 if (!reg_or_am33_const_operand (op2h, SImode))
649 op2h = force_reg (SImode, op2h);
651 emit_insn (gen_adddi3_internal (op0l, op0h, op1l, op2l, op1h, op2h));
655 ;; Note that reload only supports one commutative operand. Thus we cannot
656 ;; auto-swap both the high and low outputs with their matching constraints.
657 ;; For MN103, we're strapped for registers but thankfully the alternatives
658 ;; are few. For AM33, it becomes much easier to not represent the early
659 ;; clobber and 6 permutations of immediate and three-operand adds, but
660 ;; instead allocate a scratch register and do the expansion by hand.
662 (define_insn_and_split "adddi3_internal"
663 [(set (match_operand:SI 0 "register_operand" "=r, r, r")
664 (plus:SI (match_operand:SI 2 "register_operand" "%0, 0, r")
665 (match_operand:SI 3 "nonmemory_operand" "ri,ri,ri")))
666 (set (match_operand:SI 1 "register_operand" "=D, D, r")
669 (ltu:SI (plus:SI (match_dup 2) (match_dup 3)) (match_dup 2))
670 (match_operand:SI 4 "register_operand" " 1, D, r"))
671 (match_operand:SI 5 "reg_or_am33_const_operand" " D, 1,ri")))
672 (clobber (match_scratch:SI 6 "=X, X,&r"))
673 (clobber (reg:CC CC_REG))]
679 rtx op0l = operands[0];
680 rtx op0h = operands[1];
681 rtx op1l = operands[2];
682 rtx op2l = operands[3];
683 rtx op1h = operands[4];
684 rtx op2h = operands[5];
685 rtx scratch = operands[6];
688 if (reg_overlap_mentioned_p (op0l, op1h))
690 emit_move_insn (scratch, op0l);
692 if (reg_overlap_mentioned_p (op0l, op2h))
695 else if (reg_overlap_mentioned_p (op0l, op2h))
697 emit_move_insn (scratch, op0l);
701 if (rtx_equal_p (op0l, op1l))
703 else if (rtx_equal_p (op0l, op2l))
704 x = op1l, op1l = op2l, op2l = x;
707 gcc_assert (TARGET_AM33);
710 emit_move_insn (op0l, op2l);
715 emit_insn (gen_addsi3_flags (op0l, op1l, op2l));
717 if (rtx_equal_p (op0h, op1h))
719 else if (rtx_equal_p (op0h, op2h))
720 x = op1h, op1h = op2h, op2h = x;
723 gcc_assert (TARGET_AM33);
726 emit_move_insn (op0h, op2h);
731 emit_insn (gen_addc_internal (op0h, op1h, op2h));
734 [(set_attr "isa" "*,*,am33")]
737 ;; The following pattern is generated by combine when it proves that one
738 ;; of the inputs to the low-part of the double-word add is zero, and thus
739 ;; no carry is generated into the high-part.
741 (define_insn_and_split "*adddi3_degenerate"
742 [(set (match_operand:SI 0 "register_operand" "=&r,&r")
743 (match_operand:SI 2 "nonmemory_operand" " 0, 0"))
744 (set (match_operand:SI 1 "register_operand" "=r , r")
745 (plus:SI (match_operand:SI 3 "register_operand" "%1 , r")
746 (match_operand:SI 4 "nonmemory_operand" "ri, r")))
747 (clobber (reg:CC CC_REG))]
753 rtx scratch = NULL_RTX;
754 if (!rtx_equal_p (operands[0], operands[2]))
756 if (reg_overlap_mentioned_p (operands[0], operands[3])
757 || reg_overlap_mentioned_p (operands[0], operands[4]))
759 scratch = gen_reg_rtx (SImode);
760 emit_move_insn (scratch, operands[2]);
763 emit_move_insn (operands[0], operands[2]);
765 emit_insn (gen_addsi3 (operands[1], operands[3], operands[4]));
767 emit_move_insn (operands[0], scratch);
771 ;; ----------------------------------------------------------------------
772 ;; SUBTRACT INSTRUCTIONS
773 ;; ----------------------------------------------------------------------
775 (define_insn "subsi3"
776 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
777 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r")
778 (match_operand:SI 2 "nonmemory_operand" "r,O,i,r")))
779 (clobber (reg:CC CC_REG))]
786 [(set_attr "isa" "*,*,*,am33")
787 (set_attr "liw" "either,either,*,*")
788 (set_attr "liw_op" "sub")
789 (set_attr "timings" "11,11,11,22")]
792 (define_insn "*subsi3_flags"
794 (compare (minus:SI (match_operand:SI 1 "register_operand" "0, r")
795 (match_operand:SI 2 "nonmemory_operand" "ri,r"))
797 (set (match_operand:SI 0 "register_operand" "=r, r")
798 (minus:SI (match_dup 1) (match_dup 2)))]
799 "reload_completed && mn10300_match_ccmode (insn, CCZNCmode)"
803 [(set_attr "isa" "*,am33")
804 (set_attr "timings" "11,22")]
807 ;; A helper to expand the above, with the CC_MODE filled in.
808 (define_expand "subsi3_flags"
809 [(parallel [(set (reg:CCZNC CC_REG)
810 (compare:CCZNC (minus:SI (match_dup 1) (match_dup 2))
812 (set (match_operand:SI 0 "register_operand")
813 (minus:SI (match_operand:SI 1 "register_operand")
814 (match_operand:SI 2 "nonmemory_operand")))])]
818 (define_insn "subc_internal"
819 [(set (match_operand:SI 0 "register_operand" "=D,r,r")
821 (minus:SI (match_operand:SI 1 "register_operand" " 0,0,r")
822 (match_operand:SI 2 "reg_or_am33_const_operand" " D,i,r"))
823 (geu:SI (reg:CC CC_REG) (const_int 0))))
824 (clobber (reg:CC CC_REG))]
830 [(set_attr "isa" "*,am33,am33")]
833 (define_expand "subdi3"
834 [(set (match_operand:DI 0 "register_operand" "")
835 (minus:DI (match_operand:DI 1 "register_operand" "")
836 (match_operand:DI 2 "nonmemory_operand" "")))]
839 rtx op0l, op0h, op1l, op1h, op2l, op2h;
841 op0l = gen_lowpart (SImode, operands[0]);
842 op1l = gen_lowpart (SImode, operands[1]);
843 op2l = gen_lowpart (SImode, operands[2]);
844 op0h = gen_highpart (SImode, operands[0]);
845 op1h = gen_highpart (SImode, operands[1]);
846 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
848 if (!reg_or_am33_const_operand (op2h, SImode))
849 op2h = force_reg (SImode, op2h);
851 emit_insn (gen_subdi3_internal (op0l, op0h, op1l, op1h, op2l, op2h));
855 ;; As with adddi3, the use of the scratch register helps reduce the
856 ;; number of permutations for AM33.
857 ;; ??? The early clobber on op0 avoids a reload bug wherein both output
858 ;; registers are set the same. Consider negate, where both op2 and op3
859 ;; are 0, are csed to the same input register, and reload fails to undo
860 ;; the cse when satisfying the matching constraints.
862 (define_insn_and_split "subdi3_internal"
863 [(set (match_operand:SI 0 "register_operand" "=&r, r")
865 (match_operand:SI 2 "register_operand" " 0, r")
866 (match_operand:SI 4 "nonmemory_operand" " ri,ri")))
867 (set (match_operand:SI 1 "register_operand" "=D , r")
870 (match_operand:SI 3 "register_operand" " 1, r")
871 (match_operand:SI 5 "reg_or_am33_const_operand" " D,ri"))
872 (ltu:SI (match_dup 2) (match_dup 4))))
873 (clobber (match_scratch:SI 6 "=X ,&r"))
874 (clobber (reg:CC CC_REG))]
880 rtx op0l = operands[0];
881 rtx op0h = operands[1];
882 rtx op1l = operands[2];
883 rtx op1h = operands[3];
884 rtx op2l = operands[4];
885 rtx op2h = operands[5];
886 rtx scratch = operands[6];
888 if (reg_overlap_mentioned_p (op0l, op1h))
890 emit_move_insn (scratch, op0l);
892 if (reg_overlap_mentioned_p (op0l, op2h))
895 else if (reg_overlap_mentioned_p (op0l, op2h))
897 emit_move_insn (scratch, op0l);
901 if (!rtx_equal_p (op0l, op1l))
903 gcc_assert (TARGET_AM33);
906 emit_move_insn (op0l, op1l);
910 emit_insn (gen_subsi3_flags (op0l, op1l, op2l));
912 if (!rtx_equal_p (op0h, op1h))
914 gcc_assert (TARGET_AM33);
917 emit_move_insn (op0h, op1h);
921 emit_insn (gen_subc_internal (op0h, op1h, op2h));
924 [(set_attr "isa" "*,am33")]
927 ;; The following pattern is generated by combine when it proves that one
928 ;; of the inputs to the low-part of the double-word sub is zero, and thus
929 ;; no carry is generated into the high-part.
931 (define_insn_and_split "*subdi3_degenerate"
932 [(set (match_operand:SI 0 "register_operand" "=&r,&r")
933 (match_operand:SI 2 "nonmemory_operand" " 0, 0"))
934 (set (match_operand:SI 1 "register_operand" "=r , r")
935 (minus:SI (match_operand:SI 3 "register_operand" " 1, r")
936 (match_operand:SI 4 "nonmemory_operand" " ri, r")))
937 (clobber (reg:CC CC_REG))]
943 rtx scratch = NULL_RTX;
944 if (!rtx_equal_p (operands[0], operands[2]))
946 gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1]));
947 if (reg_overlap_mentioned_p (operands[0], operands[3])
948 || reg_overlap_mentioned_p (operands[0], operands[4]))
950 scratch = gen_reg_rtx (SImode);
951 emit_move_insn (scratch, operands[2]);
954 emit_move_insn (operands[0], operands[2]);
956 emit_insn (gen_subsi3 (operands[1], operands[3], operands[4]));
958 emit_move_insn (operands[0], scratch);
961 [(set_attr "isa" "*,am33")])
964 (define_insn_and_split "negsi2"
965 [(set (match_operand:SI 0 "register_operand" "=D,&r")
966 (neg:SI (match_operand:SI 1 "register_operand" " 0, r")))
967 (clobber (reg:CC CC_REG))]
970 "&& reload_completed"
973 /* Recall that twos-compliment is ones-compliment plus one. When
974 allocated in DATA_REGS this is 2+1 bytes; otherwise (for am33)
977 For AM33, it would have been possible to load zero and use the
978 three-address subtract to have a total size of 3+4*N bytes for
979 multiple negations, plus increased throughput. Not attempted here. */
981 if (true_regnum (operands[0]) == true_regnum (operands[1]))
983 emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));
984 emit_insn (gen_addsi3 (operands[0], operands[0], const1_rtx));
988 emit_move_insn (operands[0], const0_rtx);
989 emit_insn (gen_subsi3 (operands[0], operands[0], operands[1]));
994 ;; ----------------------------------------------------------------------
995 ;; MULTIPLY INSTRUCTIONS
996 ;; ----------------------------------------------------------------------
998 ;; ??? Note that AM33 has a third multiply variant that puts the high part
999 ;; into the MDRQ register, however this variant also constrains the inputs
1000 ;; to be in DATA_REGS and thus isn't as helpful as it might be considering
1001 ;; the existence of the 4-operand multiply. Nor is there a set of divide
1002 ;; insns that use MDRQ. Given that there is an IMM->MDRQ insn, this would
1003 ;; have been very handy for starting udivmodsi4...
1005 (define_expand "mulsidi3"
1006 [(set (match_operand:DI 0 "register_operand" "")
1007 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
1008 (sign_extend:DI (match_operand:SI 2 "register_operand" ""))))]
1011 emit_insn (gen_mulsidi3_internal (gen_lowpart (SImode, operands[0]),
1012 gen_highpart (SImode, operands[0]),
1013 operands[1], operands[2]));
1017 (define_insn "mulsidi3_internal"
1018 [(set (match_operand:SI 0 "register_operand" "=D,r")
1019 (mult:SI (match_operand:SI 2 "register_operand" "%0,r")
1020 (match_operand:SI 3 "register_operand" " D,r")))
1021 (set (match_operand:SI 1 "register_operand" "=z,r")
1024 (mult:DI (sign_extend:DI (match_dup 2))
1025 (sign_extend:DI (match_dup 3)))
1027 (clobber (reg:CC CC_REG))]
1030 if (which_alternative == 1)
1031 return "mul %2,%3,%1,%0";
1032 else if (TARGET_MULT_BUG)
1033 return "nop\;nop\;mul %3,%0";
1037 [(set_attr "isa" "*,am33")
1038 (set (attr "timings")
1039 (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))]
1042 (define_expand "umulsidi3"
1043 [(set (match_operand:DI 0 "register_operand" "")
1044 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
1045 (zero_extend:DI (match_operand:SI 2 "register_operand" ""))))
1046 (clobber (reg:CC CC_REG))]
1049 emit_insn (gen_umulsidi3_internal (gen_lowpart (SImode, operands[0]),
1050 gen_highpart (SImode, operands[0]),
1051 operands[1], operands[2]));
1055 (define_insn "umulsidi3_internal"
1056 [(set (match_operand:SI 0 "register_operand" "=D,r")
1057 (mult:SI (match_operand:SI 2 "register_operand" "%0,r")
1058 (match_operand:SI 3 "register_operand" " D,r")))
1059 (set (match_operand:SI 1 "register_operand" "=z,r")
1062 (mult:DI (zero_extend:DI (match_dup 2))
1063 (zero_extend:DI (match_dup 3)))
1065 (clobber (reg:CC CC_REG))]
1068 if (which_alternative == 1)
1069 return "mulu %2,%3,%1,%0";
1070 else if (TARGET_MULT_BUG)
1071 return "nop\;nop\;mulu %3,%0";
1073 return "mulu %3,%0";
1075 [(set_attr "isa" "*,am33")
1076 (set (attr "timings")
1077 (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))]
1080 (define_expand "mulsi3"
1081 [(parallel [(set (match_operand:SI 0 "register_operand")
1082 (mult:SI (match_operand:SI 1 "register_operand")
1083 (match_operand:SI 2 "reg_or_am33_const_operand")))
1084 (clobber (match_scratch:SI 3))
1085 (clobber (reg:CC CC_REG))])]
1089 (define_insn "*mulsi3"
1090 [(set (match_operand:SI 0 "register_operand" "=D, r,r")
1091 (mult:SI (match_operand:SI 2 "register_operand" "%0, 0,r")
1092 (match_operand:SI 3 "reg_or_am33_const_operand" " D,ri,r")))
1093 (clobber (match_scratch:SI 1 "=z, z,r"))
1094 (clobber (reg:CC CC_REG))]
1097 if (which_alternative == 2)
1098 return "mul %2,%3,%1,%0";
1099 else if (TARGET_MULT_BUG)
1100 return "nop\;nop\;mul %3,%0";
1104 [(set_attr "isa" "*,am33,am33")
1105 (set (attr "timings")
1106 (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))]
1109 (define_expand "udivmodsi4"
1110 [(parallel [(set (match_operand:SI 0 "register_operand")
1111 (udiv:SI (match_operand:SI 1 "register_operand")
1112 (match_operand:SI 2 "register_operand")))
1113 (set (match_operand:SI 3 "register_operand")
1114 (umod:SI (match_dup 1) (match_dup 2)))
1116 (clobber (reg:CC CC_REG))])]
1120 ;; Note the trick to get reload to put the zero into the MDR register,
1121 ;; rather than exposing the load early and letting CSE or someone try
1122 ;; to share the zeros between division insns. Which tends to result
1123 ;; in sequences like 0->r0->d0->mdr.
1125 (define_insn "*udivmodsi4"
1126 [(set (match_operand:SI 0 "register_operand" "=D")
1127 (udiv:SI (match_operand:SI 2 "register_operand" " 0")
1128 (match_operand:SI 3 "register_operand" " D")))
1129 (set (match_operand:SI 1 "register_operand" "=z")
1130 (umod:SI (match_dup 2) (match_dup 3)))
1131 (use (match_operand:SI 4 "nonmemory_operand" " 1"))
1132 (clobber (reg:CC CC_REG))]
1135 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1136 (const_int 3839) (const_int 4243)))]
1139 (define_expand "divmodsi4"
1140 [(parallel [(set (match_operand:SI 0 "register_operand" "")
1141 (div:SI (match_operand:SI 1 "register_operand" "")
1142 (match_operand:SI 2 "register_operand" "")))
1143 (set (match_operand:SI 3 "register_operand" "")
1144 (mod:SI (match_dup 1) (match_dup 2)))
1146 (clobber (reg:CC CC_REG))])]
1149 operands[4] = gen_reg_rtx (SImode);
1150 emit_insn (gen_ext_internal (operands[4], operands[1]));
1153 ;; ??? Ideally we'd represent this via shift, but it seems like adding a
1154 ;; special-case pattern for (ashiftrt x 31) is just as likely to result
1155 ;; in poor register allocation choices.
1156 (define_insn "ext_internal"
1157 [(set (match_operand:SI 0 "register_operand" "=z")
1158 (unspec:SI [(match_operand:SI 1 "register_operand" "D")] UNSPEC_EXT))]
1163 (define_insn "*divmodsi4"
1164 [(set (match_operand:SI 0 "register_operand" "=D")
1165 (div:SI (match_operand:SI 2 "register_operand" " 0")
1166 (match_operand:SI 3 "register_operand" " D")))
1167 (set (match_operand:SI 1 "register_operand" "=z")
1168 (mod:SI (match_dup 2) (match_dup 3)))
1169 (use (match_operand:SI 4 "register_operand" " 1"))
1170 (clobber (reg:CC CC_REG))]
1173 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1174 (const_int 3839) (const_int 4243)))]
1178 ;; ----------------------------------------------------------------------
1180 ;; ----------------------------------------------------------------------
1182 (define_insn "andsi3"
1183 [(set (match_operand:SI 0 "register_operand" "=D,D,r")
1184 (and:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1185 (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
1186 (clobber (reg:CC CC_REG))]
1192 [(set_attr "isa" "*,*,am33")
1193 (set_attr "liw" "*,op1,*")
1194 (set_attr "liw_op" "and")
1195 (set_attr "timings" "22,11,11")]
1198 (define_insn "*andsi3_flags"
1200 (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1201 (match_operand:SI 2 "nonmemory_operand" " i,D,r"))
1203 (set (match_operand:SI 0 "register_operand" "=D,D,r")
1204 (and:SI (match_dup 1) (match_dup 2)))]
1205 "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
1210 [(set_attr "isa" "*,*,am33")
1211 (set_attr "timings" "22,11,11")]
1214 ;; Make sure we generate extensions instead of ANDs.
1217 [(parallel [(set (match_operand:SI 0 "register_operand" "")
1218 (and:SI (match_operand:SI 1 "register_operand" "")
1220 (clobber (reg:CC CC_REG))])]
1222 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))]
1223 { operands[1] = gen_lowpart (QImode, operands[1]); }
1227 [(parallel [(set (match_operand:SI 0 "register_operand" "")
1228 (and:SI (match_operand:SI 1 "register_operand" "")
1230 (clobber (reg:CC CC_REG))])]
1232 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))]
1233 { operands[1] = gen_lowpart (HImode, operands[1]); }
1236 ;; Split AND by an appropriate constant into two shifts. Recall that
1237 ;; operations with a full 32-bit immediate require an extra cycle, so
1238 ;; this is a size optimization with no speed penalty. This only applies
1239 ;; do DATA_REGS; the shift insns that AM33 adds are too large for a win.
1242 [(parallel [(set (match_operand:SI 0 "register_operand" "")
1243 (and:SI (match_dup 0)
1244 (match_operand:SI 1 "const_int_operand" "")))
1245 (clobber (reg:CC CC_REG))])]
1247 && REGNO_DATA_P (true_regnum (operands[0]), 1)
1248 && mn10300_split_and_operand_count (operands[1]) != 0"
1251 int count = mn10300_split_and_operand_count (operands[1]);
1254 emit_insn (gen_lshrsi3 (operands[0], operands[0], GEN_INT (count)));
1255 emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (count)));
1259 emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (-count)));
1260 emit_insn (gen_lshrsi3 (operands[0], operands[0], GEN_INT (-count)));
1265 ;; ----------------------------------------------------------------------
1267 ;; ----------------------------------------------------------------------
1269 (define_insn "iorsi3"
1270 [(set (match_operand:SI 0 "register_operand" "=D,D,r")
1271 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1272 (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
1273 (clobber (reg:CC CC_REG))]
1279 [(set_attr "isa" "*,*,am33")
1280 (set_attr "liw" "*,op1,*")
1281 (set_attr "liw_op" "or")
1282 (set_attr "timings" "22,11,11")]
1285 (define_insn "*iorsi3_flags"
1287 (compare (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1288 (match_operand:SI 2 "nonmemory_operand" " i,D,r"))
1290 (set (match_operand:SI 0 "register_operand" "=D,D,r")
1291 (ior:SI (match_dup 1) (match_dup 2)))]
1292 "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
1297 [(set_attr "isa" "*,*,am33")
1298 (set_attr "timings" "22,11,11")]
1301 ;; ----------------------------------------------------------------------
1303 ;; ----------------------------------------------------------------------
1305 (define_insn "xorsi3"
1306 [(set (match_operand:SI 0 "register_operand" "=D,D,r")
1307 (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1308 (match_operand:SI 2 "nonmemory_operand" " i,D,r")))
1309 (clobber (reg:CC CC_REG))]
1315 [(set_attr "isa" "*,*,am33")
1316 (set_attr "liw" "*,op1,*")
1317 (set_attr "liw_op" "xor")
1318 (set_attr "timings" "22,11,11")]
1321 (define_insn "*xorsi3_flags"
1323 (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1324 (match_operand:SI 2 "nonmemory_operand" " i,D,r"))
1326 (set (match_operand:SI 0 "register_operand" "=D,D,r")
1327 (xor:SI (match_dup 1) (match_dup 2)))]
1328 "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
1333 [(set_attr "isa" "*,*,am33")
1334 (set_attr "timings" "22,11,11")]
1337 ;; ----------------------------------------------------------------------
1339 ;; ----------------------------------------------------------------------
1341 (define_insn "one_cmplsi2"
1342 [(set (match_operand:SI 0 "register_operand" "=D")
1343 (not:SI (match_operand:SI 1 "register_operand" " 0")))
1344 (clobber (reg:CC CC_REG))]
1349 (define_insn "*one_cmplsi2_flags"
1351 (compare (not:SI (match_operand:SI 1 "register_operand" "0"))
1353 (set (match_operand:SI 0 "register_operand" "=D")
1354 (not:SI (match_dup 1)))]
1355 "reload_completed && mn10300_match_ccmode (insn, CCZNmode)"
1359 ;; ----------------------------------------------------------------------
1360 ;; COMPARE AND BRANCH INSTRUCTIONS
1361 ;; ----------------------------------------------------------------------
1363 ;; We expand the comparison into a single insn so that it will not be split
1365 (define_expand "cbranchsi4"
1368 (match_operator 0 "ordered_comparison_operator"
1369 [(match_operand:SI 1 "register_operand")
1370 (match_operand:SI 2 "nonmemory_operand")])
1371 (label_ref (match_operand 3 ""))
1377 (define_insn_and_split "*cbranchsi4_cmp"
1379 (if_then_else (match_operator 3 "ordered_comparison_operator"
1380 [(match_operand:SI 0 "register_operand" "r")
1381 (match_operand:SI 1 "nonmemory_operand" "ri")])
1382 (match_operand 2 "label_ref_operand" "")
1389 mn10300_split_cbranch (CCmode, operands[3], operands[2]);
1393 (define_insn "cmpsi"
1395 (compare (match_operand:SI 0 "register_operand" "r,r,r")
1396 (match_operand:SI 1 "nonmemory_operand" "r,O,i")))]
1399 /* The operands of CMP must be distinct registers. In the case where
1400 we've failed to optimize the comparison of a register to itself, we
1401 must use another method to set the Z flag. We can achieve this
1402 effect with a BTST 0,D0. This will not alter the contents of D0;
1403 the use of d0 is arbitrary; any data register would work. */
1404 if (rtx_equal_p (operands[0], operands[1]))
1409 [(set_attr_alternative "timings"
1410 [(if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22))
1411 (if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22))
1412 (if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22))])
1413 (set_attr "liw" "either,either,*")
1414 (set_attr "liw_op" "cmp")]
1417 (define_insn "*integer_conditional_branch"
1419 (if_then_else (match_operator 0 "comparison_operator"
1420 [(match_operand 2 "int_mode_flags" "")
1422 (label_ref (match_operand 1 "" ""))
1428 (define_insn_and_split "*cbranchsi4_btst"
1431 (match_operator 3 "CCZN_comparison_operator"
1432 [(and:SI (match_operand:SI 0 "register_operand" "D")
1433 (match_operand:SI 1 "immediate_operand" "i"))
1435 (match_operand 2 "label_ref_operand" "")
1442 mn10300_split_cbranch (CCZNmode, operands[3], operands[2]);
1446 (define_insn "*btstsi"
1447 [(set (reg:CCZN CC_REG)
1449 (and:SI (match_operand:SI 0 "register_operand" "D")
1450 (match_operand:SI 1 "immediate_operand" "i"))
1456 (define_expand "cbranchsf4"
1459 (match_operator 0 "ordered_comparison_operator"
1460 [(match_operand:SF 1 "register_operand")
1461 (match_operand:SF 2 "nonmemory_operand")])
1462 (label_ref (match_operand 3 ""))
1468 (define_insn_and_split "*cbranchsf4_cmp"
1470 (if_then_else (match_operator 3 "ordered_comparison_operator"
1471 [(match_operand:SF 0 "register_operand" "f")
1472 (match_operand:SF 1 "nonmemory_operand" "fF")])
1473 (match_operand 2 "label_ref_operand" "")
1478 "&& reload_completed"
1481 mn10300_split_cbranch (CC_FLOATmode, operands[3], operands[2]);
1485 (define_insn "*am33_cmpsf"
1486 [(set (reg:CC_FLOAT CC_REG)
1487 (compare:CC_FLOAT (match_operand:SF 0 "register_operand" "f")
1488 (match_operand:SF 1 "nonmemory_operand" "fF")))]
1489 "TARGET_AM33_2 && reload_completed"
1491 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1492 (const_int 17) (const_int 25)))]
1495 (define_insn "*float_conditional_branch"
1497 (if_then_else (match_operator 0 "comparison_operator"
1498 [(reg:CC_FLOAT CC_REG) (const_int 0)])
1499 (label_ref (match_operand 1 "" ""))
1501 "TARGET_AM33_2 && reload_completed"
1503 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1504 (const_int 44) (const_int 33)))]
1507 ;; Unconditional and other jump instructions.
1511 (label_ref (match_operand 0 "" "")))]
1514 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1515 (const_int 11) (const_int 44)))]
1518 (define_insn "indirect_jump"
1519 [(set (pc) (match_operand:SI 0 "register_operand" "a"))]
1522 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1523 (const_int 11) (const_int 33)))]
1526 (define_expand "builtin_setjmp_receiver"
1527 [(match_operand 0 "" "")]
1530 emit_insn (gen_load_pic ());
1534 (define_expand "casesi"
1535 [(match_operand:SI 0 "register_operand")
1536 (match_operand:SI 1 "immediate_operand")
1537 (match_operand:SI 2 "immediate_operand")
1538 (match_operand 3 "" "") (match_operand 4 "")]
1541 rtx table = gen_reg_rtx (SImode);
1542 rtx index = gen_reg_rtx (SImode);
1543 rtx addr = gen_reg_rtx (Pmode);
1546 emit_move_insn (table, gen_rtx_LABEL_REF (VOIDmode, operands[3]));
1547 emit_insn (gen_addsi3 (index, operands[0], GEN_INT (- INTVAL (operands[1]))));
1548 test = gen_rtx_fmt_ee (GTU, VOIDmode, index, operands[2]);
1549 emit_jump_insn (gen_cbranchsi4 (test, index, operands[2], operands[4]));
1551 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
1552 emit_move_insn (addr, gen_rtx_MEM (SImode,
1553 gen_rtx_PLUS (SImode, table, index)));
1555 emit_insn (gen_addsi3 (addr, addr, table));
1557 emit_jump_insn (gen_tablejump (addr, operands[3]));
1561 (define_insn "tablejump"
1562 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
1563 (use (label_ref (match_operand 1 "" "")))]
1566 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1567 (const_int 11) (const_int 33)))]
1570 ;; Call subroutine with no return value.
1572 (define_expand "call"
1573 [(call (match_operand:QI 0 "general_operand")
1574 (match_operand:SI 1 "general_operand"))]
1577 rtx fn = XEXP (operands[0], 0);
1579 if (flag_pic && GET_CODE (fn) == SYMBOL_REF)
1581 if (MN10300_GLOBAL_P (fn))
1583 /* The PLT code won't run on AM30, but then, there's no
1584 shared library support for AM30 either, so we just assume
1585 the linker is going to adjust all @PLT relocs to the
1587 emit_use (pic_offset_table_rtx);
1588 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PLT);
1591 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PIC);
1593 if (! call_address_operand (fn, VOIDmode))
1594 fn = force_reg (SImode, fn);
1596 XEXP (operands[0], 0) = fn;
1599 (define_insn "*call_internal"
1600 [(call (mem:QI (match_operand:SI 0 "call_address_operand" "a,S"))
1601 (match_operand:SI 1 "" ""))]
1606 [(set_attr_alternative "timings"
1607 [(if_then_else (eq_attr "cpu" "am34")
1608 (const_int 33) (const_int 44))
1609 (if_then_else (eq_attr "cpu" "am34")
1610 (const_int 55) (const_int 33))
1615 ;; Call subroutine, returning value in operand 0
1616 ;; (which must be a hard register).
1618 (define_expand "call_value"
1619 [(set (match_operand 0 "")
1620 (call (match_operand:QI 1 "general_operand")
1621 (match_operand:SI 2 "general_operand")))]
1624 rtx fn = XEXP (operands[1], 0);
1626 if (flag_pic && GET_CODE (fn) == SYMBOL_REF)
1628 if (MN10300_GLOBAL_P (fn))
1630 /* The PLT code won't run on AM30, but then, there's no
1631 shared library support for AM30 either, so we just assume
1632 the linker is going to adjust all @PLT relocs to the
1634 emit_use (pic_offset_table_rtx);
1635 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PLT);
1638 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PIC);
1640 if (! call_address_operand (fn, VOIDmode))
1641 fn = force_reg (SImode, fn);
1643 XEXP (operands[1], 0) = fn;
1646 (define_insn "call_value_internal"
1647 [(set (match_operand 0 "" "")
1648 (call (mem:QI (match_operand:SI 1 "call_address_operand" "a,S"))
1649 (match_operand:SI 2 "" "")))]
1654 [(set_attr_alternative "timings"
1655 [(if_then_else (eq_attr "cpu" "am34")
1656 (const_int 33) (const_int 44))
1657 (if_then_else (eq_attr "cpu" "am34")
1658 (const_int 55) (const_int 33))
1663 (define_expand "untyped_call"
1664 [(parallel [(call (match_operand 0 "")
1666 (match_operand 1 "")
1667 (match_operand 2 "")])]
1672 emit_call_insn (gen_call (operands[0], const0_rtx));
1674 for (i = 0; i < XVECLEN (operands[2], 0); i++)
1676 rtx set = XVECEXP (operands[2], 0, i);
1677 emit_move_insn (SET_DEST (set), SET_SRC (set));
1688 ;; ----------------------------------------------------------------------
1689 ;; EXTEND INSTRUCTIONS
1690 ;; ----------------------------------------------------------------------
1692 (define_insn "zero_extendqisi2"
1693 [(set (match_operand:SI 0 "register_operand" "=D,D,r")
1695 (match_operand:QI 1 "nonimmediate_operand" " 0,m,r")))]
1701 [(set_attr "isa" "*,*,am33")
1702 (set_attr_alternative "timings"
1704 (if_then_else (eq_attr "cpu" "am34")
1705 (const_int 13) (const_int 24))
1710 (define_insn "zero_extendhisi2"
1711 [(set (match_operand:SI 0 "register_operand" "=D,D,r")
1713 (match_operand:HI 1 "nonimmediate_operand" " 0,m,r")))]
1719 [(set_attr "isa" "*,*,am33")
1720 (set_attr_alternative "timings"
1722 (if_then_else (eq_attr "cpu" "am34")
1723 (const_int 13) (const_int 24))
1727 (define_insn "extendqisi2"
1728 [(set (match_operand:SI 0 "register_operand" "=D,r")
1730 (match_operand:QI 1 "register_operand" "0,r")))]
1735 [(set_attr "isa" "*,am33")]
1738 (define_insn "extendhisi2"
1739 [(set (match_operand:SI 0 "register_operand" "=D,r")
1741 (match_operand:HI 1 "register_operand" "0,r")))]
1746 [(set_attr "isa" "*,am33")]
1749 ;; ----------------------------------------------------------------------
1751 ;; ----------------------------------------------------------------------
1753 (define_insn "ashlsi3"
1754 [(set (match_operand:SI 0 "register_operand" "=r,D,d,d,D,D,D,r")
1756 (match_operand:SI 1 "register_operand" " 0,0,0,0,0,0,0,r")
1757 (match_operand:QI 2 "nonmemory_operand" " J,K,M,L,D,O,i,r")))
1758 (clobber (reg:CC CC_REG))]
1769 [(set_attr "isa" "*,*,*,*,*,*,*,am33")
1770 (set_attr "liw" "op2,op2,op2,op2,op2,op2,*,*")
1771 (set_attr "liw_op" "asl")
1772 (set_attr "timings" "11,11,22,22,11,11,11,11")]
1775 (define_insn "lshrsi3"
1776 [(set (match_operand:SI 0 "register_operand" "=D,D,D,r")
1778 (match_operand:SI 1 "register_operand" "0,0,0,r")
1779 (match_operand:QI 2 "nonmemory_operand" "D,O,i,r")))
1780 (clobber (reg:CC CC_REG))]
1787 [(set_attr "isa" "*,*,*,am33")
1788 (set_attr "liw" "op2,op2,*,*")
1789 (set_attr "liw_op" "lsr")]
1792 (define_insn "ashrsi3"
1793 [(set (match_operand:SI 0 "register_operand" "=D,D,D,r")
1795 (match_operand:SI 1 "register_operand" "0,0,0,r")
1796 (match_operand:QI 2 "nonmemory_operand" "D,O,i,r")))
1797 (clobber (reg:CC CC_REG))]
1804 [(set_attr "isa" "*,*,*,am33")
1805 (set_attr "liw" "op2,op2,*,*")
1806 (set_attr "liw_op" "asr")]
1809 ;; ----------------------------------------------------------------------
1811 ;; ----------------------------------------------------------------------
1813 ;; Note the use of the (const_int 0) when generating the insn that matches
1814 ;; the bsch pattern. This ensures that the destination register is
1815 ;; initialised with 0 which will make the BSCH instruction set searching
1818 ;; The XOR in the instruction sequence below is there because the BSCH
1819 ;; instruction returns the bit number of the highest set bit and we want
1820 ;; the number of zero bits above that bit. The AM33 does not have a
1821 ;; reverse subtraction instruction, but we can use a simple xor instead
1822 ;; since we know that the top 27 bits are clear.
1823 (define_expand "clzsi2"
1824 [(parallel [(set (match_operand:SI 0 "register_operand")
1825 (unspec:SI [(match_operand:SI 1 "register_operand")
1826 (const_int 0)] UNSPEC_BSCH))
1827 (clobber (reg:CC CC_REG))])
1828 (parallel [(set (match_dup 0)
1829 (xor:SI (match_dup 0)
1831 (clobber (reg:CC CC_REG))])]
1835 (define_insn "*bsch"
1836 [(set (match_operand:SI 0 "register_operand" "=r")
1837 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
1838 (match_operand:SI 2 "nonmemory_operand" "0")]
1840 (clobber (reg:CC CC_REG))]
1845 ;; ----------------------------------------------------------------------
1847 ;; ----------------------------------------------------------------------
1849 (define_insn "abssf2"
1850 [(set (match_operand:SF 0 "register_operand" "=f,f")
1851 (abs:SF (match_operand:SF 1 "register_operand" "0,?f")))]
1856 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1857 (const_int 17) (const_int 14)))]
1860 (define_insn "negsf2"
1861 [(set (match_operand:SF 0 "register_operand" "=f,f")
1862 (neg:SF (match_operand:SF 1 "register_operand" "0,?f")))]
1867 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1868 (const_int 17) (const_int 14)))]
1871 (define_expand "sqrtsf2"
1872 [(set (match_operand:SF 0 "register_operand" "")
1873 (sqrt:SF (match_operand:SF 1 "register_operand" "")))]
1874 "TARGET_AM33_2 && flag_unsafe_math_optimizations"
1876 rtx scratch = gen_reg_rtx (SFmode);
1877 emit_insn (gen_rsqrtsf2 (scratch, operands[1], CONST1_RTX (SFmode)));
1878 emit_insn (gen_divsf3 (operands[0], force_reg (SFmode, CONST1_RTX (SFmode)),
1883 (define_insn "rsqrtsf2"
1884 [(set (match_operand:SF 0 "register_operand" "=f,f")
1885 (div:SF (match_operand:SF 2 "const_1f_operand" "F,F")
1886 (sqrt:SF (match_operand:SF 1 "register_operand" "0,?f"))))
1887 (clobber (reg:CC_FLOAT CC_REG))]
1892 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1893 (const_int 4753) (const_int 2327)))]
1896 (define_insn "addsf3"
1897 [(set (match_operand:SF 0 "register_operand" "=f,f")
1898 (plus:SF (match_operand:SF 1 "register_operand" "%0,f")
1899 (match_operand:SF 2 "nonmemory_operand" "f,?fF")))
1900 (clobber (reg:CC_FLOAT CC_REG))]
1905 [(set_attr_alternative "timings"
1906 [(if_then_else (eq_attr "cpu" "am34")
1907 (const_int 17) (const_int 14))
1908 (if_then_else (eq_attr "cpu" "am34")
1909 (const_int 17) (const_int 25))
1913 (define_insn "subsf3"
1914 [(set (match_operand:SF 0 "register_operand" "=f,f")
1915 (minus:SF (match_operand:SF 1 "register_operand" "0,f")
1916 (match_operand:SF 2 "nonmemory_operand" "f,?fF")))
1917 (clobber (reg:CC_FLOAT CC_REG))]
1922 [(set_attr_alternative "timings"
1923 [(if_then_else (eq_attr "cpu" "am34")
1924 (const_int 17) (const_int 14))
1925 (if_then_else (eq_attr "cpu" "am34")
1926 (const_int 17) (const_int 25))
1930 (define_insn "mulsf3"
1931 [(set (match_operand:SF 0 "register_operand" "=f,f")
1932 (mult:SF (match_operand:SF 1 "register_operand" "%0,f")
1933 (match_operand:SF 2 "nonmemory_operand" "f,?fF")))
1934 (clobber (reg:CC_FLOAT CC_REG))
1940 [(set_attr_alternative "timings"
1941 [(if_then_else (eq_attr "cpu" "am34")
1942 (const_int 17) (const_int 14))
1943 (if_then_else (eq_attr "cpu" "am34")
1944 (const_int 17) (const_int 25))
1948 (define_insn "divsf3"
1949 [(set (match_operand:SF 0 "register_operand" "=f,f")
1950 (div:SF (match_operand:SF 1 "register_operand" "0,f")
1951 (match_operand:SF 2 "nonmemory_operand" "f,?fF")))
1952 (clobber (reg:CC_FLOAT CC_REG))]
1957 [(set_attr_alternative "timings"
1958 [(if_then_else (eq_attr "cpu" "am34")
1959 (const_int 2531) (const_int 1216))
1960 (if_then_else (eq_attr "cpu" "am34")
1961 (const_int 2531) (const_int 1317))
1965 (define_insn "fmasf4"
1966 [(set (match_operand:SF 0 "register_operand" "=c")
1967 (fma:SF (match_operand:SF 1 "register_operand" "f")
1968 (match_operand:SF 2 "register_operand" "f")
1969 (match_operand:SF 3 "register_operand" "f")))
1970 (clobber (reg:CC_FLOAT CC_REG))
1973 "fmadd %1, %2, %3, %0"
1974 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1975 (const_int 17) (const_int 24)))]
1978 (define_insn "fmssf4"
1979 [(set (match_operand:SF 0 "register_operand" "=c")
1980 (fma:SF (match_operand:SF 1 "register_operand" "f")
1981 (match_operand:SF 2 "register_operand" "f")
1982 (neg:SF (match_operand:SF 3 "register_operand" "f"))))
1983 (clobber (reg:CC_FLOAT CC_REG))
1986 "fmsub %1, %2, %3, %0"
1987 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
1988 (const_int 17) (const_int 24)))]
1991 (define_insn "fnmasf4"
1992 [(set (match_operand:SF 0 "register_operand" "=c")
1993 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
1994 (match_operand:SF 2 "register_operand" "f")
1995 (match_operand:SF 3 "register_operand" "f")))
1996 (clobber (reg:CC_FLOAT CC_REG))
1999 "fnmadd %1, %2, %3, %0"
2000 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2001 (const_int 17) (const_int 24)))]
2004 (define_insn "fnmssf4"
2005 [(set (match_operand:SF 0 "register_operand" "=c")
2006 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f"))
2007 (match_operand:SF 2 "register_operand" "f")
2008 (neg:SF (match_operand:SF 3 "register_operand" "f"))))
2009 (clobber (reg:CC_FLOAT CC_REG))
2012 "fnmsub %1, %2, %3, %0"
2013 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2014 (const_int 17) (const_int 24)))]
2017 ;; ----------------------------------------------------------------------
2018 ;; PROLOGUE/EPILOGUE
2019 ;; ----------------------------------------------------------------------
2020 (define_expand "prologue"
2023 { mn10300_expand_prologue (); DONE; }
2026 (define_expand "epilogue"
2029 { mn10300_expand_epilogue (); DONE; }
2032 (define_insn "return"
2034 "mn10300_can_use_rets_insn ()"
2036 /* The RETF insn is 4 cycles faster than RETS, though 1 byte larger. */
2037 if (optimize_insn_for_speed_p () && mn10300_can_use_retf_insn ())
2043 (define_insn "return_ret"
2045 (use (match_operand:SI 0 "const_int_operand" ""))]
2048 /* The RETF insn is up to 3 cycles faster than RET. */
2049 fputs ((mn10300_can_use_retf_insn () ? "\tretf " : "\tret "), asm_out_file);
2050 mn10300_print_reg_list (asm_out_file, mn10300_get_live_callee_saved_regs (NULL));
2051 fprintf (asm_out_file, ",%d\n", (int) INTVAL (operands[0]));
2055 ;; This instruction matches one generated by mn10300_gen_multiple_store()
2056 (define_insn "store_movm"
2057 [(match_parallel 0 "mn10300_store_multiple_operation"
2058 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand 1 "" "")))])]
2061 fputs ("\tmovm ", asm_out_file);
2062 mn10300_print_reg_list (asm_out_file,
2063 mn10300_store_multiple_regs (operands[0]));
2064 fprintf (asm_out_file, ",(sp)\n");
2067 ;; Assume that no more than 8 registers will be pushed.
2068 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2069 (const_int 99) (const_int 88)))]
2072 (define_expand "load_pic"
2077 emit_insn (gen_am33_load_pic (pic_offset_table_rtx));
2078 else if (mn10300_frame_size () == 0)
2079 emit_insn (gen_mn10300_load_pic0 (pic_offset_table_rtx));
2081 emit_insn (gen_mn10300_load_pic1 (pic_offset_table_rtx));
2085 (define_insn "am33_load_pic"
2086 [(set (match_operand:SI 0 "register_operand" "=a")
2087 (unspec:SI [(const_int 0)] UNSPEC_GOT))
2088 (clobber (reg:CC CC_REG))]
2091 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
2092 return ".LPIC%=:\;mov pc,%0\;add %1-(.LPIC%=-.),%0";
2094 [(set_attr "timings" "33")]
2097 ;; Load pic register with push/pop of stack.
2098 (define_insn "mn10300_load_pic0"
2099 [(set (match_operand:SI 0 "register_operand" "=a")
2100 (unspec:SI [(const_int 0)] UNSPEC_GOT))
2101 (clobber (reg:SI MDR_REG))
2102 (clobber (reg:CC CC_REG))]
2105 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
2106 return ("add -4,sp\;"
2110 "add %1-(.LPIC%=-.),%0");
2112 [(set_attr "timings" "88")]
2115 ;; Load pic register re-using existing stack space.
2116 (define_insn "mn10300_load_pic1"
2117 [(set (match_operand:SI 0 "register_operand" "=a")
2118 (unspec:SI [(const_int 0)] UNSPEC_GOT))
2119 (clobber (mem:SI (reg:SI SP_REG)))
2120 (clobber (reg:SI MDR_REG))
2121 (clobber (reg:CC CC_REG))]
2124 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
2125 return ("calls .LPIC%=\n"
2128 "add %1-(.LPIC%=-.),%0");
2130 [(set_attr "timings" "66")]
2133 ;; The mode on operand 3 has been deliberately omitted because it
2134 ;; can be either SI (for arithmetic operations) or QI (for shifts).
2136 [(set (match_operand:SI 0 "register_operand" "=r")
2137 (unspec:SI [(match_dup 0)
2138 (match_operand 2 "liw_operand" "rO")
2139 (match_operand:SI 4 "const_int_operand" "")]
2141 (set (match_operand:SI 1 "register_operand" "=r")
2142 (unspec:SI [(match_dup 1)
2143 (match_operand 3 "liw_operand" "rO")
2144 (match_operand:SI 5 "const_int_operand" "")]
2147 "%W4_%W5 %2, %0, %3, %1"
2148 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2149 (const_int 13) (const_int 12)))]
2152 ;; The mode on operand 1 has been deliberately omitted because it
2153 ;; can be either SI (for arithmetic operations) or QI (for shifts).
2154 (define_insn "cmp_liw"
2155 [(set (reg:CC CC_REG)
2156 (compare:CC (match_operand:SI 2 "register_operand" "r")
2157 (match_operand 3 "liw_operand" "rO")))
2158 (set (match_operand:SI 0 "register_operand" "=r")
2159 (unspec:SI [(match_dup 0)
2160 (match_operand 1 "liw_operand" "rO")
2161 (match_operand:SI 4 "const_int_operand" "")]
2164 "cmp_%W4 %3, %2, %1, %0"
2165 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2166 (const_int 13) (const_int 12)))]
2169 (define_insn "liw_cmp"
2170 [(set (match_operand:SI 0 "register_operand" "=r")
2171 (unspec:SI [(match_dup 0)
2172 (match_operand 1 "liw_operand" "rO")
2173 (match_operand:SI 4 "const_int_operand" "")]
2175 (set (reg:CC CC_REG)
2176 (compare:CC (match_operand:SI 2 "register_operand" "r")
2177 (match_operand 3 "liw_operand" "rO")))]
2179 "%W4_cmp %1, %0, %3, %2"
2180 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34")
2181 (const_int 13) (const_int 12)))]
2184 ;; Note - in theory the doloop patterns could be used here to express
2185 ;; the SETLB and Lcc instructions. In practice this does not work because
2186 ;; the acceptable forms of the doloop patterns do not include UNSPECs
2187 ;; and without them gcc's basic block reordering code can duplicate the
2188 ;; doloop_end pattern, leading to bogus multiple decrements of the loop
2191 (define_insn "setlb"
2192 [(unspec [(const_int 0)] UNSPEC_SETLB)]
2193 "TARGET_AM33 && TARGET_ALLOW_SETLB"
2199 (if_then_else (match_operator 0 "comparison_operator"
2200 [(reg:CC CC_REG) (const_int 0)])
2201 (label_ref (match_operand 1 "" ""))
2203 (unspec [(const_int 1)] UNSPEC_SETLB)]
2204 "TARGET_AM33 && TARGET_ALLOW_SETLB"
2205 "L%b0 # loop back to: %1"
2210 (if_then_else (match_operator 0 "comparison_operator"
2211 [(reg:CC_FLOAT CC_REG) (const_int 0)])
2212 (label_ref (match_operand 1 "" ""))
2214 (unspec [(const_int 2)] UNSPEC_SETLB)]
2215 "TARGET_AM33_2 && TARGET_ALLOW_SETLB"
2216 "FL%b0 # loop back to: %1"
2217 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") (const_int 44) (const_int 11)))]