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Daily bump.
[official-gcc.git] / gcc / config / microblaze / microblaze.h
bloba56b9de8c89ed2aa684dfa9859fed368d486b182
1 /* Definitions of target machine for GNU compiler for Xilinx MicroBlaze.
2 Copyright (C) 2009-2024 Free Software Foundation, Inc.
3
4 Contributed by Michael Eager <eager@eagercon.com>.
5
6 This file is part of GCC.
7
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 3, or (at your
11 option) any later version.
12
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
21
22 /* Standard GCC variables that we reference. */
23
24 /* MicroBlaze external variables defined in microblaze.cc. */
25
26 /* Which pipeline to schedule for. */
27 enum pipeline_type
28 {
29 MICROBLAZE_PIPE_3 = 0,
30 MICROBLAZE_PIPE_5 = 1
31 };
32
33 #define MICROBLAZE_MASK_NO_UNSAFE_DELAY 0x00000001
34
35 /* print_operand punctuation chars */
36 extern char microblaze_print_operand_punct[];
37
38 /* # bytes of data/sdata cutoff */
39 extern int microblaze_section_threshold;
40
41 /* Map register # to debug register # */
42 extern int microblaze_debugger_regno[];
43
44 extern int microblaze_no_unsafe_delay;
45 extern int microblaze_has_clz;
46 extern enum pipeline_type microblaze_pipe;
47
48 #define OBJECT_FORMAT_ELF
49
50 #if TARGET_BIG_ENDIAN_DEFAULT
51 #define TARGET_ENDIAN_DEFAULT 0
52 #define TARGET_ENDIAN_OPTION "mbig-endian"
53 #else
54 #define TARGET_ENDIAN_DEFAULT MASK_LITTLE_ENDIAN
55 #define TARGET_ENDIAN_OPTION "mlittle-endian"
56 #endif
57
58 /* Default target_flags if no switches are specified */
59 #define TARGET_DEFAULT (MASK_SOFT_MUL | MASK_SOFT_DIV | MASK_SOFT_FLOAT \
60 | TARGET_ENDIAN_DEFAULT)
61
62 /* Do we have CLZ? */
63 #define TARGET_HAS_CLZ (TARGET_PATTERN_COMPARE && microblaze_has_clz)
64
65 /* The default is to support PIC. */
66 #define TARGET_SUPPORTS_PIC 1
67
68 /* The default is to not need GOT for TLS. */
69 #define TLS_NEEDS_GOT 0
70
71 /* What is the default setting for -mcpu= . We set it to v4.00.a even though
72 we are actually ahead. This is safest version that has generate code
73 compatible for the original ISA */
74 #define MICROBLAZE_DEFAULT_CPU "v4.00.a"
75
76 /* Macros to decide whether certain features are available or not,
77 depending on the instruction set architecture level. */
78
79 #define DRIVER_SELF_SPECS \
80 "%{mxl-soft-mul:%<mno-xl-soft-mul}", \
81 "%{mno-xl-barrel-shift:%<mxl-barrel-shift}", \
82 "%{mno-xl-pattern-compare:%<mxl-pattern-compare}", \
83 "%{mxl-soft-div:%<mno-xl-soft-div}", \
84 "%{mxl-reorder:%<mno-xl-reorder}", \
85 "%{msoft-float:%<mhard-float}"
86
87 /* Tell collect what flags to pass to nm. */
88 #ifndef NM_FLAGS
89 #define NM_FLAGS "-Bn"
90 #endif
91
92 /* Names to predefine in the preprocessor for this target machine. */
93 #define TARGET_CPU_CPP_BUILTINS() microblaze_cpp_define (pfile)
94
95 /* Assembler specs. */
96
97 #define TARGET_ASM_SPEC ""
98
99 #define ASM_SPEC "\
100 %(target_asm_spec) \
101 %{mbig-endian:-EB} \
102 %{mlittle-endian:-EL}"
103
104 /* Extra switches sometimes passed to the linker. */
105 /* -xl-mode-xmdstub translated to -Zxl-mode-xmdstub -- deprecated. */
106
107 #define LINK_SPEC "%{shared:-shared} -N -relax \
108 %{mbig-endian:-EB --oformat=elf32-microblaze} \
109 %{mlittle-endian:-EL --oformat=elf32-microblazeel} \
110 %{Zxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
111 %{mxl-mode-xmdstub:-defsym _TEXT_START_ADDR=0x800} \
112 %{mxl-gp-opt:%{G*}} %{!mxl-gp-opt: -G 0} \
113 %{!T*: -dT xilinx.ld%s}"
114
115 /* Specs for the compiler proper */
116
117 #ifndef CC1_SPEC
118 #define CC1_SPEC " \
119 %{G*} \
120 %(subtarget_cc1_spec) \
121 %{mxl-multiply-high:-mcpu=v6.00.a} \
122 "
123 #endif
124
125 #define EXTRA_SPECS \
126 { "target_asm_spec", TARGET_ASM_SPEC }, \
127 SUBTARGET_EXTRA_SPECS
128
129 /* Local compiler-generated symbols must have a prefix that the assembler
130 understands. */
131
132 #ifndef LOCAL_LABEL_PREFIX
133 #define LOCAL_LABEL_PREFIX "$"
134 #endif
135
136 /* fixed registers. */
137 #define MB_ABI_BASE_REGNUM 0
138 #define MB_ABI_STACK_POINTER_REGNUM 1
139 #define MB_ABI_GPRO_REGNUM 2
140 #define MB_ABI_GPRW_REGNUM 13
141 #define MB_ABI_INTR_RETURN_ADDR_REGNUM 14
142 #define MB_ABI_SUB_RETURN_ADDR_REGNUM 15
143 #define MB_ABI_DEBUG_RETURN_ADDR_REGNUM 16
144 #define MB_ABI_EXCEPTION_RETURN_ADDR_REGNUM 17
145 #define MB_ABI_ASM_TEMP_REGNUM 18
146 /* This is our temp register. */
147 #define MB_ABI_FRAME_POINTER_REGNUM 19
148 #define MB_ABI_PIC_ADDR_REGNUM 20
149 #define MB_ABI_PIC_FUNC_REGNUM 21
150 /* Volatile registers. */
151 #define MB_ABI_INT_RETURN_VAL_REGNUM 3
152 #define MB_ABI_INT_RETURN_VAL2_REGNUM 4
153 #define MB_ABI_FIRST_ARG_REGNUM 5
154 #define MB_ABI_LAST_ARG_REGNUM 10
155 #define MB_ABI_MAX_ARG_REGS (MB_ABI_LAST_ARG_REGNUM \
156 - MB_ABI_FIRST_ARG_REGNUM + 1)
157 #define MB_ABI_STATIC_CHAIN_REGNUM 3
158 #define MB_ABI_TEMP1_REGNUM 11
159 #define MB_ABI_TEMP2_REGNUM 12
160 #define MB_ABI_MSR_SAVE_REG 11
161 /* Volatile register used to save MSR in interrupt handlers. */
162
163
164 /* Debug stuff. */
165
166 /* How to renumber registers for gdb. */
167 #define DEBUGGER_REGNO(REGNO) microblaze_debugger_regno[(REGNO)]
168
169 /* Generate DWARF exception handling info. */
170 #define DWARF2_UNWIND_INFO 1
171
172 /* Don't generate .loc operations. */
173 #define DWARF2_ASM_LINE_DEBUG_INFO 0
174
175 /* The DWARF 2 CFA column which tracks the return address. */
176 #define DWARF_FRAME_RETURN_COLUMN \
177 (GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)
178
179 /* Initial state of return address on entry to func = R15.
180 Actually, the RA is at R15+8, but gcc doesn't know how
181 to generate this.
182 NOTE: GDB has a workaround and expects this incorrect value.
183 If this is fixed, a corresponding fix to GDB is needed. */
184 #define INCOMING_RETURN_ADDR_RTX \
185 gen_rtx_REG (Pmode, GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM)
186
187 /* Specifies the offset from INCOMING_RETURN_ADDR_RTX and the actual return PC. */
188 #define RETURN_ADDR_OFFSET (8)
189
190 /* Describe how we implement __builtin_eh_return. */
191 #define EH_RETURN_DATA_REGNO(N) \
192 (((N) < 2) ? MB_ABI_FIRST_ARG_REGNUM + (N) : INVALID_REGNUM)
193
194 #define MB_EH_STACKADJ_REGNUM MB_ABI_INT_RETURN_VAL2_REGNUM
195 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, MB_EH_STACKADJ_REGNUM)
196
197 /* Select a format to encode pointers in exception handling data. CODE
198 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
199 true if the symbol may be affected by dynamic relocations. */
200 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
201 ((flag_pic || GLOBAL) ? DW_EH_PE_aligned : DW_EH_PE_absptr)
202
203 /* Use DWARF 2 debugging information by default. */
204 #define DWARF2_DEBUGGING_INFO
205 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
206
207 /* Target machine storage layout */
208
209 #define BITS_BIG_ENDIAN 0
210 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0)
211 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN)
212 #define BITS_PER_WORD 32
213 #define UNITS_PER_WORD 4
214 #define MIN_UNITS_PER_WORD 4
215 #define INT_TYPE_SIZE 32
216 #define SHORT_TYPE_SIZE 16
217 #define LONG_TYPE_SIZE 32
218 #define LONG_LONG_TYPE_SIZE 64
219 #define POINTER_SIZE 32
220 #define PARM_BOUNDARY 32
221 #define FUNCTION_BOUNDARY 32
222 #define EMPTY_FIELD_BOUNDARY 32
223 #define STRUCTURE_SIZE_BOUNDARY 8
224 #define BIGGEST_ALIGNMENT 32
225 #define STRICT_ALIGNMENT 1
226 #define PCC_BITFIELD_TYPE_MATTERS 1
227
228 #undef SIZE_TYPE
229 #define SIZE_TYPE "unsigned int"
230
231 #undef PTRDIFF_TYPE
232 #define PTRDIFF_TYPE "int"
233
234 #define DATA_ALIGNMENT(TYPE, ALIGN) \
235 ((((ALIGN) < BITS_PER_WORD) \
236 && (TREE_CODE (TYPE) == ARRAY_TYPE \
237 || TREE_CODE (TYPE) == UNION_TYPE \
238 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
239
240 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \
241 (((TREE_CODE (TYPE) == ARRAY_TYPE \
242 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode) \
243 && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN))
244
245 #define WORD_REGISTER_OPERATIONS 1
246
247 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
248
249 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
250 if (GET_MODE_CLASS (MODE) == MODE_INT \
251 && GET_MODE_SIZE (MODE) < 4) \
252 (MODE) = SImode;
253
254 /* Standard register usage. */
255
256 /* On the MicroBlaze, we have 32 integer registers */
257
258 #define FIRST_PSEUDO_REGISTER 36
259
260 #define FIXED_REGISTERS \
261 { \
262 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, \
263 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
264 1, 1, 1, 1 \
265 }
266
267 #define CALL_USED_REGISTERS \
268 { \
269 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
270 1, 1, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
271 1, 1, 1, 1 \
272 }
273 #define GP_REG_FIRST 0
274 #define GP_REG_LAST 31
275 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
276 #define GP_DEBUGGER_FIRST 0
277
278 #define ST_REG 32
279 #define AP_REG_NUM 33
280 #define RAP_REG_NUM 34
281 #define FRP_REG_NUM 35
282
283 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
284 #define ST_REG_P(REGNO) ((REGNO) == ST_REG)
285
286 #define STACK_POINTER_REGNUM (GP_REG_FIRST + MB_ABI_STACK_POINTER_REGNUM)
287
288 #define STACK_POINTER_OFFSET FIRST_PARM_OFFSET(FNDECL)
289
290 /* Base register for access to local variables of the function. We
291 pretend that the frame pointer is
292 MB_ABI_INTR_RETURN_ADDR_REGNUM, and then eliminate it
293 to HARD_FRAME_POINTER_REGNUM. We can get away with this because
294 rMB_ABI_INTR_RETUREN_ADDR_REGNUM is a fixed
295 register(return address for interrupt), and will not be used for
296 anything else. */
297
298 #define FRAME_POINTER_REGNUM FRP_REG_NUM
299 #define HARD_FRAME_POINTER_REGNUM \
300 (GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM)
301 #define ARG_POINTER_REGNUM AP_REG_NUM
302 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
303 #define STATIC_CHAIN_REGNUM \
304 (GP_REG_FIRST + MB_ABI_STATIC_CHAIN_REGNUM)
305
306 /* registers used in prologue/epilogue code when the stack frame
307 is larger than 32K bytes. These registers must come from the
308 scratch register set, and not used for passing and returning
309 arguments and any other information used in the calling sequence
310 (such as pic). */
311
312 #define MICROBLAZE_TEMP1_REGNUM \
313 (GP_REG_FIRST + MB_ABI_TEMP1_REGNUM)
314
315 #define MICROBLAZE_TEMP2_REGNUM \
316 (GP_REG_FIRST + MB_ABI_TEMP2_REGNUM)
317
318 #define NO_FUNCTION_CSE 1
319
320 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + MB_ABI_PIC_ADDR_REGNUM)
321
322 enum reg_class
323 {
324 NO_REGS, /* no registers in set. */
325 GR_REGS, /* integer registers. */
326 ST_REGS, /* status register. */
327 ALL_REGS, /* all registers. */
328 LIM_REG_CLASSES /* max value + 1. */
329 };
330
331 #define N_REG_CLASSES (int) LIM_REG_CLASSES
332
333 #define GENERAL_REGS GR_REGS
334
335 #define REG_CLASS_NAMES \
336 { \
337 "NO_REGS", \
338 "GR_REGS", \
339 "ST_REGS", \
340 "ALL_REGS" \
341 }
342
343 #define REG_CLASS_CONTENTS \
344 { \
345 { 0x00000000, 0x00000000 }, /* no registers. */ \
346 { 0xffffffff, 0x00000000 }, /* integer registers. */ \
347 { 0x00000000, 0x00000001 }, /* status registers. */ \
348 { 0xffffffff, 0x0000000f } /* all registers. */ \
349 }
350
351 extern enum reg_class microblaze_regno_to_class[];
352
353 #define REGNO_REG_CLASS(REGNO) microblaze_regno_to_class[ (REGNO) ]
354
355 #define BASE_REG_CLASS GR_REGS
356
357 #define INDEX_REG_CLASS GR_REGS
358
359 #define GR_REG_CLASS_P(CLASS) ((CLASS) == GR_REGS)
360
361 /* REGISTER AND CONSTANT CLASSES */
362
363 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
364 #define LARGE_INT(X) \
365 (INTVAL (X) > 0 && UINTVAL (X) >= 0x80000000 && UINTVAL (X) <= 0xffffffff)
366 #define PLT_ADDR_P(X) (GET_CODE (X) == UNSPEC && XINT (X,1) == UNSPEC_PLT)
367 /* Test for a valid operand for a call instruction.
368 Don't allow the arg pointer register or virtual regs
369 since they may change into reg + const, which the patterns
370 can't handle yet. */
371 #define CALL_INSN_OP(X) (CONSTANT_ADDRESS_P (X) \
372 || (GET_CODE (X) == REG && X != arg_pointer_rtx \
373 && ! VIRTUAL_REGISTER_P (X)))
374
375 /* True if VALUE is a signed 16-bit number. */
376 #define SMALL_OPERAND(VALUE) \
377 ((unsigned HOST_WIDE_INT) (VALUE) + 0x8000 < 0x10000)
378
379 /* Constant which cannot be loaded in one instruction. */
380 #define LARGE_OPERAND(VALUE) \
381 ((((VALUE) & ~0x0000ffff) != 0) \
382 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
383 && (((VALUE) & 0x0000ffff) != 0 \
384 || (((VALUE) & ~2147483647) != 0 \
385 && ((VALUE) & ~2147483647) != ~2147483647)))
386
387 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
388 ((CLASS) != ALL_REGS \
389 ? (CLASS) \
390 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
391 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
392 ? (GR_REGS) \
393 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
394 || GET_MODE (X) == VOIDmode) \
395 ? (GR_REGS) : (CLASS))))
396
397 /* Stack layout; function entry, exit and calling. */
398
399 #define STACK_GROWS_DOWNWARD 1
400
401 /* The return address for the current frame is in r31 if this is a leaf
402 function. Otherwise, it is on the stack. It is at a variable offset
403 from sp/fp/ap, so we define a fake hard register rap which is a
404 poiner to the return address on the stack. This always gets eliminated
405 during reload to be either the frame pointer or the stack pointer plus
406 an offset. */
407
408 #define RETURN_ADDR_RTX(count, frame) \
409 microblaze_return_addr(count,frame)
410
411 extern struct microblaze_frame_info current_frame_info;
412
413 #define ELIMINABLE_REGS \
414 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
415 { ARG_POINTER_REGNUM, GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}, \
416 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
417 { RETURN_ADDRESS_POINTER_REGNUM, \
418 GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}, \
419 { RETURN_ADDRESS_POINTER_REGNUM, \
420 GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM}, \
421 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
422 { FRAME_POINTER_REGNUM, GP_REG_FIRST + MB_ABI_FRAME_POINTER_REGNUM}}
423
424 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
425 (OFFSET) = microblaze_initial_elimination_offset ((FROM), (TO))
426
427 #define ACCUMULATE_OUTGOING_ARGS 1
428
429 #define FIRST_PARM_OFFSET(FNDECL) (UNITS_PER_WORD)
430
431 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
432
433 #define REG_PARM_STACK_SPACE(FNDECL) (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)
434
435 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
436
437 #define STACK_BOUNDARY 32
438
439 #define NUM_OF_ARGS 6
440
441 #define GP_RETURN (GP_REG_FIRST + MB_ABI_INT_RETURN_VAL_REGNUM)
442
443 #define GP_ARG_FIRST (GP_REG_FIRST + MB_ABI_FIRST_ARG_REGNUM)
444 #define GP_ARG_LAST (GP_REG_FIRST + MB_ABI_LAST_ARG_REGNUM)
445
446 #define MAX_ARGS_IN_REGISTERS MB_ABI_MAX_ARG_REGS
447
448 #define LIBCALL_VALUE(MODE) \
449 gen_rtx_REG ( \
450 ((GET_MODE_CLASS (MODE) != MODE_INT \
451 || GET_MODE_SIZE (MODE) >= 4) \
452 ? (MODE) \
453 : SImode), GP_RETURN)
454
455 /* 1 if N is a possible register number for a function value.
456 On the MicroBlaze, R2 R3 are the only register thus used.
457 Currently, R2 are only implemented here (C has no complex type) */
458
459 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN)
460
461 #define FUNCTION_ARG_REGNO_P(N) (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST))
462
463 typedef struct microblaze_args
464 {
465 int gp_reg_found; /* whether a gp register was found yet */
466 int arg_number; /* argument number */
467 int arg_words; /* # total words the arguments take */
468 int fp_arg_words; /* # words for FP args */
469 int last_arg_fp; /* nonzero if last arg was FP (EABI only) */
470 int fp_code; /* Mode of FP arguments */
471 int num_adjusts; /* number of adjustments made */
472 /* Adjustments made to args pass in regs. */
473 /* ??? The size is doubled to work around a bug in the code that sets the
474 adjustments in function_arg. */
475 rtx adjust[MAX_ARGS_IN_REGISTERS * 2];
476 } CUMULATIVE_ARGS;
477
478 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \
479 init_cumulative_args (&CUM, FNTYPE, LIBNAME)
480
481 #define NO_PROFILE_COUNTERS 1
482
483 #define FUNCTION_PROFILER(FILE, LABELNO) { \
484 { \
485 fprintf (FILE, "\tbrki\tr16,_mcount\n"); \
486 } \
487 }
488
489 #define EXIT_IGNORE_STACK 1
490
491 /* 4 insns + 2 words of data. */
492 #define TRAMPOLINE_SIZE (6 * 4)
493
494 #define TRAMPOLINE_ALIGNMENT 32
495
496 #define REGNO_OK_FOR_BASE_P(regno) microblaze_regno_ok_for_base_p ((regno), 1)
497
498 #define REGNO_OK_FOR_INDEX_P(regno) microblaze_regno_ok_for_base_p ((regno), 1)
499
500 #ifndef REG_OK_STRICT
501 #define REG_STRICT_FLAG 0
502 #else
503 #define REG_STRICT_FLAG 1
504 #endif
505
506 #define REG_OK_FOR_BASE_P(X) \
507 microblaze_regno_ok_for_base_p (REGNO (X), REG_STRICT_FLAG)
508
509 #define REG_OK_FOR_INDEX_P(X) \
510 microblaze_regno_ok_for_base_p (REGNO (X), REG_STRICT_FLAG)
511
512 #define MAX_REGS_PER_ADDRESS 2
513
514
515 /* Identify valid constant addresses. Exclude if PIC addr which
516 needs scratch register. */
517 #define CONSTANT_ADDRESS_P(X) microblaze_constant_address_p(X)
518
519 /* Define this, so that when PIC, reload won't try to reload invalid
520 addresses which require two reload registers. */
521 #define LEGITIMATE_PIC_OPERAND_P(X) microblaze_legitimate_pic_operand (X)
522
523 #define CASE_VECTOR_MODE (SImode)
524
525 #ifndef DEFAULT_SIGNED_CHAR
526 #define DEFAULT_SIGNED_CHAR 1
527 #endif
528
529 #define MOVE_MAX 4
530 #define MAX_MOVE_MAX 8
531
532 #define SLOW_BYTE_ACCESS 1
533
534 /* sCOND operations return 1. */
535 #define STORE_FLAG_VALUE 1
536
537 #define SHIFT_COUNT_TRUNCATED 1
538
539 #define Pmode SImode
540
541 #define FUNCTION_MODE SImode
542
543 /* Mode should always be SImode */
544 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
545 ( GR_REG_CLASS_P (FROM) && GR_REG_CLASS_P (TO) ? 2 \
546 : (FROM) == ST_REGS && GR_REG_CLASS_P (TO) ? 4 \
547 : 12)
548
549 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
550 (4 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
551
552 #define BRANCH_COST(speed_p, predictable_p) 2
553
554 /* Control the assembler format that we output. */
555 #define ASM_APP_ON " #APP\n"
556 #define ASM_APP_OFF " #NO_APP\n"
557
558 #define REGISTER_NAMES { \
559 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
560 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
561 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \
562 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
563 "rmsr", "$ap", "$rap", "$frp" }
564
565 #define ADDITIONAL_REGISTER_NAMES \
566 { \
567 { "r0", 0 + GP_REG_FIRST }, \
568 { "r1", 1 + GP_REG_FIRST }, \
569 { "r2", 2 + GP_REG_FIRST }, \
570 { "r3", 3 + GP_REG_FIRST }, \
571 { "r4", 4 + GP_REG_FIRST }, \
572 { "r5", 5 + GP_REG_FIRST }, \
573 { "r6", 6 + GP_REG_FIRST }, \
574 { "r7", 7 + GP_REG_FIRST }, \
575 { "r8", 8 + GP_REG_FIRST }, \
576 { "r9", 9 + GP_REG_FIRST }, \
577 { "r10", 10 + GP_REG_FIRST }, \
578 { "r11", 11 + GP_REG_FIRST }, \
579 { "r12", 12 + GP_REG_FIRST }, \
580 { "r13", 13 + GP_REG_FIRST }, \
581 { "r14", 14 + GP_REG_FIRST }, \
582 { "r15", 15 + GP_REG_FIRST }, \
583 { "r16", 16 + GP_REG_FIRST }, \
584 { "r17", 17 + GP_REG_FIRST }, \
585 { "r18", 18 + GP_REG_FIRST }, \
586 { "r19", 19 + GP_REG_FIRST }, \
587 { "r20", 20 + GP_REG_FIRST }, \
588 { "r21", 21 + GP_REG_FIRST }, \
589 { "r22", 22 + GP_REG_FIRST }, \
590 { "r23", 23 + GP_REG_FIRST }, \
591 { "r24", 24 + GP_REG_FIRST }, \
592 { "r25", 25 + GP_REG_FIRST }, \
593 { "r26", 26 + GP_REG_FIRST }, \
594 { "r27", 27 + GP_REG_FIRST }, \
595 { "r28", 28 + GP_REG_FIRST }, \
596 { "r29", 29 + GP_REG_FIRST }, \
597 { "r30", 30 + GP_REG_FIRST }, \
598 { "r31", 31 + GP_REG_FIRST }, \
599 { "rmsr", ST_REG} \
600 }
601
602 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
603
604 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) microblaze_print_operand_punct[CODE]
605
606 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
607
608 /* ASM_OUTPUT_ALIGNED_COMMON and ASM_OUTPUT_ALIGNED_LOCAL
609
610 Unfortunately, we still need to set the section explicitly. Somehow,
611 our binutils assign .comm and .lcomm variables to the "current" section
612 in the assembly file, rather than where they implicitly belong. We need to
613 remove this explicit setting in GCC when binutils can understand sections
614 better. */
615 #undef ASM_OUTPUT_ALIGNED_COMMON
616 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
617 do { \
618 if ((SIZE) > 0 && (SIZE) <= INT_MAX \
619 && (int) (SIZE) <= microblaze_section_threshold \
620 && TARGET_XLGPOPT) \
621 { \
622 switch_to_section (sbss_section); \
623 } \
624 else \
625 { \
626 switch_to_section (bss_section); \
627 } \
628 fprintf (FILE, "%s", COMMON_ASM_OP); \
629 assemble_name ((FILE), (NAME)); \
630 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \
631 (SIZE), (ALIGN) / BITS_PER_UNIT); \
632 ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \
633 } while (0)
634
635 #undef ASM_OUTPUT_ALIGNED_LOCAL
636 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
637 do { \
638 if ((SIZE) > 0 && (SIZE) <= INT_MAX \
639 && (int) (SIZE) <= microblaze_section_threshold \
640 && TARGET_XLGPOPT) \
641 { \
642 switch_to_section (sbss_section); \
643 } \
644 else \
645 { \
646 switch_to_section (bss_section); \
647 } \
648 fprintf (FILE, "%s", LCOMMON_ASM_OP); \
649 assemble_name ((FILE), (NAME)); \
650 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \
651 (SIZE), (ALIGN) / BITS_PER_UNIT); \
652 ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \
653 } while (0)
654
655 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
656 do { \
657 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \
658 } while (0)
659
660 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
661 { \
662 }
663
664 #undef TARGET_ASM_CONSTRUCTOR
665 #define TARGET_ASM_CONSTRUCTOR microblaze_elf_asm_constructor
666
667 #undef TARGET_ASM_DESTRUCTOR
668 #define TARGET_ASM_DESTRUCTOR microblaze_elf_asm_destructor
669
670 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
671 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
672
673 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
674 fprintf (STREAM, "\t%s\t%sL%d\n", \
675 ".gpword", \
676 LOCAL_LABEL_PREFIX, VALUE)
677
678 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
679 do { \
680 if (flag_pic == 2) \
681 fprintf (STREAM, "\t%s\t%sL%d@GOTOFF\n", \
682 ".gpword", \
683 LOCAL_LABEL_PREFIX, VALUE); \
684 else \
685 fprintf (STREAM, "\t%s\t%sL%d\n", \
686 ".gpword", \
687 LOCAL_LABEL_PREFIX, VALUE); \
688 } while (0)
689
690 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
691 fprintf (STREAM, "\t.align\t%d\n", (LOG))
692
693 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
694 fprintf (STREAM, "\t.space\t" HOST_WIDE_INT_PRINT_UNSIGNED "\n", (SIZE))
695
696 #define ASCII_DATA_ASM_OP "\t.ascii\t"
697 #define STRING_ASM_OP "\t.asciz\t"
698
699 #undef TARGET_ASM_OUTPUT_IDENT
700 #define TARGET_ASM_OUTPUT_IDENT microblaze_asm_output_ident
701
702 /* Default to -G 8 */
703 #ifndef MICROBLAZE_DEFAULT_GVALUE
704 #define MICROBLAZE_DEFAULT_GVALUE 8
705 #endif
706
707 /* Given a decl node or constant node, choose the section to output it in
708 and select that section. */
709
710 /* Store in OUTPUT a string (made with alloca) containing
711 an assembler-name for a local static variable named NAME.
712 LABELNO is an integer which is different for each call. */
713 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
714 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 13), \
715 sprintf ((OUTPUT), "%s.%lu", (NAME), (unsigned long)(LABELNO)))
716
717 /* How to start an assembler comment.
718 The leading space is important (the microblaze assembler requires it). */
719 #ifndef ASM_COMMENT_START
720 #define ASM_COMMENT_START " #"
721 #endif
722
723 #define BSS_VAR 1
724 #define SBSS_VAR 2
725 #define DATA_VAR 4
726 #define SDATA_VAR 5
727 #define RODATA_VAR 6
728 #define SDATA2_VAR 7
729
730 /* These definitions are used in with the shift_type flag in the rtl. */
731 #define SHIFT_CONST 1
732 #define SHIFT_REG 2
733 #define USE_ADDK 3
734
735 /* Handle interrupt attribute. */
736 extern int interrupt_handler;
737 extern int fast_interrupt;
738 extern int save_volatiles;
739
740 #define INTERRUPT_HANDLER_NAME "_interrupt_handler"
741 /* The function name for the function tagged with attribute break_handler
742 has been set in the RTL as _break_handler. This function name is used
743 in the generation of directives .ent .end and .global. */
744 #define BREAK_HANDLER_NAME "_break_handler"
745 #define FAST_INTERRUPT_NAME "_fast_interrupt"
746
747 /* The following #defines are used in the headers files. Always retain these. */
748
749 /* Added for declaring size at the end of the function. */
750 #undef ASM_DECLARE_FUNCTION_SIZE
751 #define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
752 do { \
753 if (!flag_inhibit_size_directive) \
754 { \
755 char label[256]; \
756 static int labelno; \
757 labelno++; \
758 ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno); \
759 (*targetm.asm_out.internal_label) (FILE, "Lfe", labelno); \
760 fprintf (FILE, "%s", SIZE_ASM_OP); \
761 assemble_name (FILE, (FNAME)); \
762 fprintf (FILE, ","); \
763 assemble_name (FILE, label); \
764 fprintf (FILE, "-"); \
765 assemble_name (FILE, (FNAME)); \
766 putc ('\n', FILE); \
767 } \
768 } while (0)
769
770 #define GLOBAL_ASM_OP "\t.globl\t"
771 #define TYPE_ASM_OP "\t.type\t"
772 #define SIZE_ASM_OP "\t.size\t"
773 #define COMMON_ASM_OP "\t.comm\t"
774 #define LCOMMON_ASM_OP "\t.lcomm\t"
775
776 #define MAX_OFILE_ALIGNMENT (32768*8)
777
778 #define TYPE_OPERAND_FMT "@%s"
779
780 /* Write the extra assembler code needed to declare an object properly. */
781 #undef ASM_DECLARE_OBJECT_NAME
782 #define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL) \
783 do { \
784 fprintf (FILE, "%s", TYPE_ASM_OP); \
785 assemble_name (FILE, NAME); \
786 putc (',', FILE); \
787 fprintf (FILE, TYPE_OPERAND_FMT, "object"); \
788 putc ('\n', FILE); \
789 size_directive_output = 0; \
790 if (!flag_inhibit_size_directive && DECL_SIZE (DECL)) \
791 { \
792 size_directive_output = 1; \
793 fprintf (FILE, "%s", SIZE_ASM_OP); \
794 assemble_name (FILE, NAME); \
795 fprintf (FILE, "," HOST_WIDE_INT_PRINT_DEC "\n", \
796 int_size_in_bytes (TREE_TYPE (DECL))); \
797 } \
798 microblaze_declare_object (FILE, NAME, "", ":\n", 0); \
799 } while (0)
800
801 #undef ASM_FINISH_DECLARE_OBJECT
802 #define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \
803 do { \
804 const char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \
805 if (!flag_inhibit_size_directive && DECL_SIZE (DECL) \
806 && ! AT_END && TOP_LEVEL \
807 && DECL_INITIAL (DECL) == error_mark_node \
808 && !size_directive_output) \
809 { \
810 size_directive_output = 1; \
811 fprintf (FILE, "%s", SIZE_ASM_OP); \
812 assemble_name (FILE, name); \
813 fprintf (FILE, "," HOST_WIDE_INT_PRINT_DEC "\n", \
814 int_size_in_bytes (TREE_TYPE (DECL))); \
815 } \
816 } while (0)
817
818 #define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \
819 do { fputc ( '\t', FILE); \
820 assemble_name (FILE, LABEL1); \
821 fputs ( " = ", FILE); \
822 assemble_name (FILE, LABEL2); \
823 fputc ( '\n', FILE); \
824 } while (0)
825
826 #define ASM_WEAKEN_LABEL(FILE,NAME) \
827 do { fputs ("\t.weakext\t", FILE); \
828 assemble_name (FILE, NAME); \
829 fputc ('\n', FILE); \
830 } while (0)
831
832 #define MAKE_DECL_ONE_ONLY(DECL) (DECL_WEAK (DECL) = 1)
833 #undef UNIQUE_SECTION_P
834 #define UNIQUE_SECTION_P(DECL) (DECL_ONE_ONLY (DECL))
835
836 #undef TARGET_ASM_NAMED_SECTION
837 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
838
839 /* Define the strings to put out for each section in the object file.
840
841 Note: For ctors/dtors, we want to give these sections the SHF_WRITE
842 attribute to allow shared libraries to patch/resolve addresses into
843 these locations. On Microblaze, there is no concept of shared libraries
844 yet, so this is for future use. */
845 #define TEXT_SECTION_ASM_OP "\t.text"
846 #define DATA_SECTION_ASM_OP "\t.data"
847 #define READONLY_DATA_SECTION_ASM_OP \
848 "\t.rodata"
849 #define BSS_SECTION_ASM_OP "\t.bss"
850 #define CTORS_SECTION_ASM_OP "\t.section\t.ctors,\"aw\""
851 #define DTORS_SECTION_ASM_OP "\t.section\t.dtors,\"aw\""
852 #define INIT_SECTION_ASM_OP "\t.section\t.init,\"ax\""
853 #define FINI_SECTION_ASM_OP "\t.section\t.fini,\"ax\""
854
855 #define SDATA_SECTION_ASM_OP "\t.sdata" /* Small RW initialized data */
856 #define SDATA2_SECTION_ASM_OP "\t.sdata2" /* Small RO initialized data */
857 #define SBSS_SECTION_ASM_OP "\t.sbss" /* Small RW uninitialized data */
858 #define SBSS2_SECTION_ASM_OP "\t.sbss2" /* Small RO uninitialized data */
859
860 /* We do this to save a few 10s of code space that would be taken up
861 by the call_FUNC () wrappers, used by the generic CRT_CALL_STATIC_FUNCTION
862 definition in crtstuff.c. */
863 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
864 asm ( SECTION_OP "\n" \
865 "\tbrlid r15, " #FUNC "\n\t nop\n" \
866 TEXT_SECTION_ASM_OP);
867
868 /* We need to group -lm as well, since some Newlib math functions
869 reference __errno! */
870 #undef LIB_SPEC
871 #define LIB_SPEC \
872 "%{!nostdlib: \
873 %{pg:-start-group -lxilprofile -lgloss -lxil -lc -lm -end-group } \
874 %{!pg:-start-group -lgloss -lxil -lc -lm -end-group }} "
875
876 /* microblaze-unknown-elf target has no support of C99 runtime */
877 #undef TARGET_LIBC_HAS_FUNCTION
878 #define TARGET_LIBC_HAS_FUNCTION no_c99_libc_has_function
879
880 #undef ENDFILE_SPEC
881 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
882
883 #define STARTFILE_EXECUTABLE_SPEC "crt0.o%s crti.o%s crtbegin.o%s"
884 #define STARTFILE_XMDSTUB_SPEC "crt1.o%s crti.o%s crtbegin.o%s"
885 #define STARTFILE_BOOTSTRAP_SPEC "crt2.o%s crti.o%s crtbegin.o%s"
886 #define STARTFILE_NOVECTORS_SPEC "crt3.o%s crti.o%s crtbegin.o%s"
887 #define STARTFILE_CRTINIT_SPEC "%{!pg: %{!mno-clearbss: crtinit.o%s} \
888 %{mno-clearbss: sim-crtinit.o%s}} \
889 %{pg: %{!mno-clearbss: pgcrtinit.o%s} %{mno-clearbss: sim-pgcrtinit.o%s}}"
890
891 #define STARTFILE_DEFAULT_SPEC STARTFILE_EXECUTABLE_SPEC
892
893 #undef SUBTARGET_EXTRA_SPECS
894 #define SUBTARGET_EXTRA_SPECS \
895 { "startfile_executable", STARTFILE_EXECUTABLE_SPEC }, \
896 { "startfile_xmdstub", STARTFILE_XMDSTUB_SPEC }, \
897 { "startfile_bootstrap", STARTFILE_BOOTSTRAP_SPEC }, \
898 { "startfile_novectors", STARTFILE_NOVECTORS_SPEC }, \
899 { "startfile_crtinit", STARTFILE_CRTINIT_SPEC }, \
900 { "startfile_default", STARTFILE_DEFAULT_SPEC },
901
902 #undef STARTFILE_SPEC
903 #define STARTFILE_SPEC "\
904 %{Zxl-mode-executable : %(startfile_executable) ; \
905 mxl-mode-executable : %(startfile_executable) ; \
906 Zxl-mode-xmdstub : %(startfile_xmdstub) ; \
907 mxl-mode-xmdstub : %(startfile_xmdstub) ; \
908 Zxl-mode-bootstrap : %(startfile_bootstrap) ; \
909 mxl-mode-bootstrap : %(startfile_bootstrap) ; \
910 Zxl-mode-novectors : %(startfile_novectors) ; \
911 mxl-mode-novectors : %(startfile_novectors) ; \
912 Zxl-mode-xilkernel : %(startfile_xilkernel) ; \
913 mxl-mode-xilkernel : %(startfile_xilkernel) ; \
914 : %(startfile_default) \
915 } \
916 %(startfile_crtinit)"
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