RISC-V: Move mode assertion out of conditional branch in emit_insn
[official-gcc.git] / gcc / config / gcn / gcn-opts.h
blob1091035a69afea0ba330138f4e83bacc28bc2ca6
1 /* Copyright (C) 2016-2024 Free Software Foundation, Inc.
3 This file is free software; you can redistribute it and/or modify it under
4 the terms of the GNU General Public License as published by the Free
5 Software Foundation; either version 3 of the License, or (at your option)
6 any later version.
8 This file is distributed in the hope that it will be useful, but WITHOUT
9 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 for more details.
13 You should have received a copy of the GNU General Public License
14 along with GCC; see the file COPYING3. If not see
15 <http://www.gnu.org/licenses/>. */
17 #ifndef GCN_OPTS_H
18 #define GCN_OPTS_H
20 /* Which processor to generate code or schedule for. */
21 enum processor_type
23 PROCESSOR_FIJI, // gfx803
24 PROCESSOR_VEGA10, // gfx900
25 PROCESSOR_VEGA20, // gfx906
26 PROCESSOR_GFX908,
27 PROCESSOR_GFX90a,
28 PROCESSOR_GFX90c,
29 PROCESSOR_GFX1030,
30 PROCESSOR_GFX1036,
31 PROCESSOR_GFX1100,
32 PROCESSOR_GFX1103
35 #define TARGET_FIJI (gcn_arch == PROCESSOR_FIJI)
36 #define TARGET_VEGA10 (gcn_arch == PROCESSOR_VEGA10)
37 #define TARGET_VEGA20 (gcn_arch == PROCESSOR_VEGA20)
38 #define TARGET_GFX908 (gcn_arch == PROCESSOR_GFX908)
39 #define TARGET_GFX90a (gcn_arch == PROCESSOR_GFX90a)
40 #define TARGET_GFX90c (gcn_arch == PROCESSOR_GFX90c)
41 #define TARGET_GFX1030 (gcn_arch == PROCESSOR_GFX1030)
42 #define TARGET_GFX1036 (gcn_arch == PROCESSOR_GFX1036)
43 #define TARGET_GFX1100 (gcn_arch == PROCESSOR_GFX1100)
44 #define TARGET_GFX1103 (gcn_arch == PROCESSOR_GFX1103)
46 /* Set in gcn_option_override. */
47 extern enum gcn_isa {
48 ISA_UNKNOWN,
49 ISA_GCN3,
50 ISA_GCN5,
51 ISA_RDNA2,
52 ISA_RDNA3,
53 ISA_CDNA1,
54 ISA_CDNA2
55 } gcn_isa;
57 #define TARGET_GCN3 (gcn_isa == ISA_GCN3)
58 #define TARGET_GCN3_PLUS (gcn_isa >= ISA_GCN3)
59 #define TARGET_GCN5 (gcn_isa == ISA_GCN5)
60 #define TARGET_GCN5_PLUS (gcn_isa >= ISA_GCN5)
61 #define TARGET_CDNA1 (gcn_isa == ISA_CDNA1)
62 #define TARGET_CDNA1_PLUS (gcn_isa >= ISA_CDNA1)
63 #define TARGET_CDNA2 (gcn_isa == ISA_CDNA2)
64 #define TARGET_CDNA2_PLUS (gcn_isa >= ISA_CDNA2)
65 #define TARGET_RDNA2 (gcn_isa == ISA_RDNA2)
66 #define TARGET_RDNA2_PLUS (gcn_isa >= ISA_RDNA2 && gcn_isa < ISA_CDNA1)
67 #define TARGET_RDNA3 (gcn_isa == ISA_RDNA3)
70 #define TARGET_M0_LDS_LIMIT (TARGET_GCN3)
71 #define TARGET_PACKED_WORK_ITEMS (TARGET_CDNA2_PLUS || TARGET_RDNA3)
73 #define TARGET_XNACK (flag_xnack != HSACO_ATTR_OFF)
75 enum hsaco_attr_type
77 HSACO_ATTR_OFF,
78 HSACO_ATTR_ON,
79 HSACO_ATTR_ANY,
80 HSACO_ATTR_DEFAULT
83 #endif