1 /* Definitions of target machine for GNU compiler, Argonaut EPIPHANY cpu.
2 Copyright (C) 1994-2024 Free Software Foundation, Inc.
3 Contributed by Embecosm on behalf of Adapteva, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #ifndef GCC_EPIPHANY_H
22 #define GCC_EPIPHANY_H
30 #undef WCHAR_TYPE_SIZE
32 /* Names to predefine in the preprocessor for this target machine. */
33 #define TARGET_CPU_CPP_BUILTINS() \
36 builtin_define ("__epiphany__"); \
37 builtin_define ("__little_endian__"); \
38 builtin_define_with_int_value ("__EPIPHANY_STACK_OFFSET__", \
39 epiphany_stack_offset); \
40 builtin_assert ("cpu=epiphany"); \
41 builtin_assert ("machine=epiphany"); \
44 /* Pick up the libgloss library. One day we may do this by linker script, but
46 libgloss might use errno/__errno, which might not have been needed when we
47 saw libc the first time, so link with libc a second time. */
49 #define LIB_SPEC "%{!shared:%{g*:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}} -lepiphany %{!shared:%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}}"
51 #define LINK_SPEC "%{v}"
53 #define STARTFILE_SPEC "%{!shared:crt0.o%s} crti.o%s " \
54 "%{mfp-mode=int:crtint.o%s} %{mfp-mode=truncate:crtrunc.o%s} " \
55 "%{m1reg-r43:crtm1reg-r43.o%s} %{m1reg-r63:crtm1reg-r63.o%s} " \
58 #define ENDFILE_SPEC "crtend.o%s crtn.o%s"
60 #define EPIPHANY_LIBRARY_EXTRA_SPEC \
61 "-ffixed-r40 -ffixed-r41 -ffixed-r42 -ffixed-r43"
63 /* In the "spec:" rule,, t-epiphany changes this to epiphany_library_stub_spec
64 and epiphany_library_extra_spec, respectively. */
66 { "epiphany_library_extra_spec", "" }, \
67 { "epiphany_library_build_spec", EPIPHANY_LIBRARY_EXTRA_SPEC }, \
69 #define DRIVER_SELF_SPECS " %(epiphany_library_extra_spec) "
71 #undef USER_LABEL_PREFIX
72 #define USER_LABEL_PREFIX "_"
74 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
76 mov r0,%low(" USER_LABEL_PREFIX #FUNC")\n\
77 movt r0,%high(" USER_LABEL_PREFIX #FUNC")\n\
81 #if 0 /* We would like to use Posix for profiling, but the simulator
82 interface still lacks mkdir. */
83 #define TARGET_POSIX_IO
86 /* Target machine storage layout. */
88 /* Define this if most significant bit is lowest numbered
89 in instructions that operate on numbered bit-fields. */
90 #define BITS_BIG_ENDIAN 0
92 /* Define this if most significant byte of a word is the lowest numbered. */
93 #define BYTES_BIG_ENDIAN 0
95 /* Define this if most significant word of a multiword number is the lowest
97 #define WORDS_BIG_ENDIAN 0
99 /* Width of a word, in units (bytes). */
100 #define UNITS_PER_WORD 4
102 /* Define this macro if it is advisable to hold scalars in registers
103 in a wider mode than that declared by the program. In such cases,
104 the value is constrained to be within the bounds of the declared
105 type, but kept valid in the wider mode. The signedness of the
106 extension may differ from that of the type. */
107 /* It is far faster to zero extend chars than to sign extend them */
109 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
110 if (GET_MODE_CLASS (MODE) == MODE_INT \
111 && GET_MODE_SIZE (MODE) < 4) \
113 if (MODE == QImode) \
115 else if (MODE == HImode) \
120 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
121 #define PARM_BOUNDARY 32
123 /* Boundary (in *bits*) on which stack pointer should be aligned. */
124 #define STACK_BOUNDARY 64
126 /* ALIGN FRAMES on word boundaries */
127 #define EPIPHANY_STACK_ALIGN(LOC) (((LOC)+7) & ~7)
129 /* Allocation boundary (in *bits*) for the code of a function. */
130 #define FUNCTION_BOUNDARY 32
132 /* Every structure's size must be a multiple of this. */
133 #define STRUCTURE_SIZE_BOUNDARY 8
135 /* A bit-field declared as `int' forces `int' alignment for the struct. */
136 #define PCC_BITFIELD_TYPE_MATTERS 1
138 /* No data type wants to be aligned rounder than this. */
139 /* This is bigger than currently necessary for the EPIPHANY. If 8 byte floats are
140 ever added it's not clear whether they'll need such alignment or not. For
141 now we assume they will. We can always relax it if necessary but the
142 reverse isn't true. */
143 #define BIGGEST_ALIGNMENT 64
145 /* The best alignment to use in cases where we have a choice. */
146 #define FASTEST_ALIGNMENT 64
148 #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT
150 /* Make arrays of chars dword-aligned for the same reasons.
151 Also, align arrays of SImode items. */
152 #define DATA_ALIGNMENT(TYPE, ALIGN) \
153 (TREE_CODE (TYPE) == ARRAY_TYPE \
154 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
155 && (ALIGN) < FASTEST_ALIGNMENT \
156 ? FASTEST_ALIGNMENT \
157 : (TREE_CODE (TYPE) == ARRAY_TYPE \
158 && TYPE_MODE (TREE_TYPE (TYPE)) == SImode \
159 && (ALIGN) < FASTEST_ALIGNMENT) \
160 ? FASTEST_ALIGNMENT \
163 /* Set this nonzero if move instructions will actually fail to work
164 when given unaligned data. */
165 /* On the EPIPHANY the lower address bits are masked to 0 as necessary. The chip
166 won't croak when given an unaligned address, but the insn will still fail
167 to produce the correct result. */
168 #define STRICT_ALIGNMENT 1
170 /* layout_type overrides our ADJUST_ALIGNMENT settings from epiphany-modes.def
171 for vector modes, so we have to override it back. */
172 #define ROUND_TYPE_ALIGN(TYPE, MANGLED_ALIGN, SPECIFIED_ALIGN) \
173 (VECTOR_TYPE_P (TYPE) && !TYPE_USER_ALIGN (TYPE) \
174 && SPECIFIED_ALIGN <= GET_MODE_ALIGNMENT (TYPE_MODE (TYPE)) \
175 ? GET_MODE_ALIGNMENT (TYPE_MODE (TYPE)) \
176 : (RECORD_OR_UNION_TYPE_P (TYPE) \
177 && !TYPE_PACKED (TYPE)) \
178 ? epiphany_special_round_type_align ((TYPE), (MANGLED_ALIGN), \
180 : MAX ((MANGLED_ALIGN), (SPECIFIED_ALIGN)))
182 #define ADJUST_FIELD_ALIGN(FIELD, TYPE, COMPUTED) \
183 epiphany_adjust_field_align((TYPE), (COMPUTED))
185 /* Layout of source language data types. */
187 #define SHORT_TYPE_SIZE 16
188 #define INT_TYPE_SIZE 32
189 #define LONG_TYPE_SIZE 32
190 #define LONG_LONG_TYPE_SIZE 64
192 /* Define this as 1 if `char' should by default be signed; else as 0. */
193 #define DEFAULT_SIGNED_CHAR 0
195 #define SIZE_TYPE "long unsigned int"
196 #define PTRDIFF_TYPE "long int"
197 #define WCHAR_TYPE "unsigned int"
198 #define WCHAR_TYPE_SIZE BITS_PER_WORD
200 /* Standard register usage. */
202 /* Number of actual hardware registers.
203 The hardware registers are assigned numbers for the compiler
204 from 0 to just below FIRST_PSEUDO_REGISTER.
205 All registers that the compiler knows about must be given numbers,
206 even those that are not normally considered general registers. */
208 #define FIRST_PSEUDO_REGISTER 78
211 /* General purpose registers. */
212 #define GPR_FIRST 0 /* First gpr */
214 #define PIC_REGNO (GPR_FIRST + 28) /* PIC register. */
215 #define GPR_LAST (GPR_FIRST + 63) /* Last gpr */
216 #define CORE_CONTROL_FIRST CONFIG_REGNUM
217 #define CORE_CONTROL_LAST IRET_REGNUM
219 #define GPR_P(R) IN_RANGE (R, GPR_FIRST, GPR_LAST)
220 #define GPR_OR_AP_P(R) (GPR_P (R) || (R) == ARG_POINTER_REGNUM)
222 #define GPR_OR_PSEUDO_P(R) (GPR_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
223 #define GPR_AP_OR_PSEUDO_P(R) (GPR_OR_AP_P (R) || (R) >= FIRST_PSEUDO_REGISTER)
225 #define FIXED_REGISTERS \
226 { /* Integer Registers */ \
227 0, 0, 0, 0, 0, 0, 0, 0, /* 000-007, gr0 - gr7 */ \
228 0, 0, 0, 0, 0, 1, 0, 0, /* 008-015, gr8 - gr15 */ \
229 0, 0, 0, 0, 0, 0, 0, 0, /* 016-023, gr16 - gr23 */ \
230 0, 0, 0, 0, 1, 1, 1, 1, /* 024-031, gr24 - gr31 */ \
231 0, 0, 0, 0, 0, 0, 0, 0, /* 032-039, gr32 - gr39 */ \
232 0, 0, 0, 0, 0, 0, 0, 0, /* 040-047, gr40 - gr47 */ \
233 0, 0, 0, 0, 0, 0, 0, 0, /* 048-055, gr48 - gr55 */ \
234 0, 0, 0, 0, 0, 0, 0, 0, /* 056-063, gr56 - gr63 */ \
235 /* Other registers */ \
236 1, /* 64 AP - fake arg ptr */ \
237 1, /* soft frame pointer */ \
238 1, /* CC_REGNUM - integer conditions */\
239 1, /* CCFP_REGNUM - fp conditions */\
240 1, 1, 1, 1, 1, 1, /* Core Control Registers. */ \
241 1, 1, 1, /* FP_{NEAREST,...}_REGNUM */\
242 1, /* UNKNOWN_REGNUM - placeholder. */\
245 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered (in
246 general) by function calls as well as for fixed registers. This macro
247 therefore identifies the registers that are not available for general
248 allocation of values that must live across function calls.
250 If a register has 0 in `CALL_USED_REGISTERS', the compiler automatically
251 saves it on function entry and restores it on function exit, if the register
252 is used within the function. */
254 #define CALL_USED_REGISTERS \
255 { /* Integer Registers */ \
256 1, 1, 1, 1, 0, 0, 0, 0, /* 000-007, gr0 - gr7 */ \
257 0, 0, 0, 0, 1, 1, 1, 0, /* 008-015, gr8 - gr15 */ \
258 1, 1, 1, 1, 1, 1, 1, 1, /* 016-023, gr16 - gr23 */ \
259 1, 1, 1, 1, 1, 1, 1, 1, /* 024-031, gr24 - gr31 */ \
260 0, 0, 0, 0, 0, 0, 0, 0, /* 032-039, gr32 - gr38 */ \
261 0, 0, 0, 0, 1, 1, 1, 1, /* 040-047, gr40 - gr47 */ \
262 1, 1, 1, 1, 1, 1, 1, 1, /* 048-055, gr48 - gr55 */ \
263 1, 1, 1, 1, 1, 1, 1, 1, /* 056-063, gr56 - gr63 */ \
264 1, /* 64 AP - fake arg ptr */ \
265 1, /* soft frame pointer */ \
266 1, /* 66 CC_REGNUM */ \
267 1, /* 67 CCFP_REGNUM */ \
268 1, 1, 1, 1, 1, 1, /* Core Control Registers. */ \
269 1, 1, 1, /* FP_{NEAREST,...}_REGNUM */\
270 1, /* UNKNOWN_REGNUM - placeholder. */\
273 #define REG_ALLOC_ORDER \
275 0, 1, 2, 3, /* Caller-saved 'small' registers. */ \
276 12, /* Caller-saved unpaired register. */ \
277 /* Caller-saved registers. */ \
278 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \
280 48, 49, 50, 51, 52, 53, 54, 55, \
281 56, 57, 58, 59, 60, 61, 62, 63, \
282 4, 5, 6, 7, /* Calle-saved 'small' registers. */ \
283 15, /* Calle-saved unpaired register. */ \
284 8, 9, 10, 11, /* Calle-saved registers. */ \
285 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, \
286 14, 13, /* Link register, stack pointer. */ \
287 /* Can't allocate, but must name these... */ \
289 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77 \
292 #define HARD_REGNO_RENAME_OK(SRC, DST) epiphany_regno_rename_ok (SRC, DST)
294 /* Register classes and constants. */
296 /* Define the classes of registers for register constraints in the
297 machine description. Also define ranges of constants.
299 One of the classes must always be named ALL_REGS and include all hard regs.
300 If there is more than one class, another class must be named NO_REGS
301 and contain no registers.
303 The name GENERAL_REGS must be the name of a class (or an alias for
304 another name such as ALL_REGS). This is the class of registers
305 that is allowed by "g" or "r" in a register constraint.
306 Also, registers outside this class are allocated only when
307 instructions express preferences for them.
309 The classes must be numbered in nondecreasing order; that is,
310 a larger-numbered class must never be contained completely
311 in a smaller-numbered class.
313 For any two classes, it is very desirable that there be another
314 class that represents their union.
316 It is important that any condition codes have class NO_REGS.
317 See `register_operand'. */
330 #define N_REG_CLASSES ((int) LIM_REG_CLASSES)
332 /* Give names of register classes as strings for dump file. */
333 #define REG_CLASS_NAMES \
340 "CORE_CONTROL_REGS", \
344 /* Define which registers fit in which classes.
345 This is an initializer for a vector of HARD_REG_SET
346 of length N_REG_CLASSES. */
348 #define REG_CLASS_CONTENTS \
349 { /* r0-r31 r32-r63 ap/sfp/cc1/cc2/iret/status */ \
350 { 0x00000000,0x00000000,0x0}, /* NO_REGS */ \
351 { 0x00004000,0x00000000,0x0}, /* LR_REGS */ \
352 { 0x000000ff,0x00000000,0x0}, /* SHORT_INSN_REGS */ \
353 { 0xffff100f,0xffffff00,0x0}, /* SIBCALL_REGS */ \
354 { 0xffffffff,0xffffffff,0x0003}, /* GENERAL_REGS */ \
355 { 0x00000000,0x00000000,0x03f0}, /* CORE_CONTROL_REGS */ \
356 { 0xffffffff,0xffffffff,0x3fff}, /* ALL_REGS */ \
360 /* The same information, inverted:
361 Return the class number of the smallest class containing
362 reg number REGNO. This could be a conditional expression
363 or could index an array. */
364 extern enum reg_class epiphany_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
365 #define REGNO_REG_CLASS(REGNO) \
366 (epiphany_regno_reg_class[REGNO])
368 /* The class value for index registers, and the one for base regs. */
369 #define BASE_REG_CLASS GENERAL_REGS
370 #define INDEX_REG_CLASS GENERAL_REGS
372 /* These assume that REGNO is a hard or pseudo reg number.
373 They give nonzero only if REGNO is a hard reg of the suitable class
374 or a pseudo reg currently allocated to a suitable hard reg.
375 Since they use reg_renumber, they are safe only once reg_renumber
376 has been allocated, which happens in reginfo.cc during register
378 #define REGNO_OK_FOR_BASE_P(REGNO) \
379 ((REGNO) < FIRST_PSEUDO_REGISTER || (unsigned) reg_renumber[REGNO] < FIRST_PSEUDO_REGISTER)
380 #define REGNO_OK_FOR_INDEX_P(REGNO) \
381 ((REGNO) < FIRST_PSEUDO_REGISTER || (unsigned) reg_renumber[REGNO] < FIRST_PSEUDO_REGISTER)
385 /* Given an rtx X being reloaded into a reg required to be
386 in class CLASS, return the class of reg to actually use.
387 In general this is just CLASS; but on some machines
388 in some cases it is preferable to use a more restrictive class. */
389 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
392 /* Return the maximum number of consecutive registers
393 needed to represent mode MODE in a register of class CLASS. */
394 #define CLASS_MAX_NREGS(CLASS, MODE) \
395 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
397 /* The letters I, J, K, L, M, N, O, P in a register constraint string
398 can be used to stand for particular ranges of immediate operands.
399 This macro defines what the ranges are.
400 C is the letter, and VALUE is a constant value.
401 Return 1 if VALUE is in the range specified by C. */
403 /* 'I' is used for 16 bit unsigned.
404 'Cal' is used for long immediates (32 bits)
405 'K' is used for any constant up to 5 bits.
406 'L' is used for any 11 bit signed.
409 #define IMM16(X) (IN_RANGE ((X), 0, 0xFFFF))
410 #define SIMM16(X) (IN_RANGE ((X), -65536, 65535))
411 #define SIMM11(X) (IN_RANGE ((X), -1024, 1023))
412 #define IMM5(X) (IN_RANGE ((X), 0, 0x1F))
414 typedef struct GTY (()) machine_function
416 unsigned args_parsed
: 1;
417 unsigned pretend_args_odd
: 1;
418 unsigned lr_clobbered
: 1;
419 unsigned control_use_inserted
: 1;
420 unsigned lr_slot_known
: 1;
421 unsigned sw_entities_processed
: 6;
425 unsigned unknown_mode_uses
;
426 unsigned unknown_mode_sets
;
427 } machine_function_t
;
429 #define MACHINE_FUNCTION(fun) (fun)->machine
431 #define INIT_EXPANDERS epiphany_init_expanders ()
433 /* Stack layout and stack pointer usage. */
435 /* Define this macro if pushing a word onto the stack moves the stack
436 pointer to a smaller address. */
437 #define STACK_GROWS_DOWNWARD 1
439 /* Define this to nonzero if the nominal address of the stack frame
440 is at the high-address end of the local variables;
441 that is, each additional local variable allocated
442 goes at a more negative offset in the frame. */
443 #define FRAME_GROWS_DOWNWARD 1
445 /* Offset from the stack pointer register to the first location at which
446 outgoing arguments are placed. */
447 #define STACK_POINTER_OFFSET epiphany_stack_offset
449 /* Offset of first parameter from the argument pointer register value. */
450 /* 4 bytes for each of previous fp, return address, and previous gp.
451 4 byte reserved area for future considerations. */
452 #define FIRST_PARM_OFFSET(FNDECL) \
453 (epiphany_stack_offset \
454 + (MACHINE_FUNCTION (DECL_STRUCT_FUNCTION (FNDECL))->pretend_args_odd \
457 #define INCOMING_FRAME_SP_OFFSET epiphany_stack_offset
459 /* Register to use for pushing function arguments. */
460 #define STACK_POINTER_REGNUM GPR_SP
462 /* Base register for access to local variables of the function. */
463 #define HARD_FRAME_POINTER_REGNUM GPR_FP
465 /* Register in which static-chain is passed to a function. This must
466 not be a register used by the prologue. */
467 #define STATIC_CHAIN_REGNUM GPR_IP
469 /* Define the offset between two registers, one to be eliminated, and the other
470 its replacement, at the start of a routine. */
472 #define ELIMINABLE_REGS \
473 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
474 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
475 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
476 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
479 /* Define the offset between two registers, one to be eliminated, and the other
480 its replacement, at the start of a routine. */
482 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
483 ((OFFSET) = epiphany_initial_elimination_offset ((FROM), (TO)))
485 /* Function argument passing. */
487 /* If defined, the maximum amount of space required for outgoing
488 arguments will be computed and placed into the variable
489 `current_function_outgoing_args_size'. No space will be pushed
490 onto the stack for each call; instead, the function prologue should
491 increase the stack frame size by this amount. */
492 #define ACCUMULATE_OUTGOING_ARGS 1
494 /* Define a data type for recording info about an argument list
495 during the scan of that argument list. This data type should
496 hold all necessary information about the function itself
497 and about the args processed so far, enough to enable macros
498 such as FUNCTION_ARG to determine where the next arg should go. */
499 #define CUMULATIVE_ARGS int
501 /* Initialize a variable CUM of type CUMULATIVE_ARGS
502 for a call to a function whose data type is FNTYPE.
503 For a library call, FNTYPE is 0. */
504 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \
507 /* The number of registers used for parameter passing. Local to this file. */
508 #define MAX_EPIPHANY_PARM_REGS 4
510 /* 1 if N is a possible register number for function argument passing. */
511 #define FUNCTION_ARG_REGNO_P(N) \
512 ((unsigned) (N) < MAX_EPIPHANY_PARM_REGS)
514 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in
515 a reg. This includes arguments that have to be passed by reference as the
516 pointer to them is passed in a reg if one is available (and that is what
518 This macro is only used in this file. */
519 /* We must use partial argument passing because of the chosen mode
520 of varargs handling. */
521 #define PASS_IN_REG_P(CUM, MODE, TYPE) \
522 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < MAX_EPIPHANY_PARM_REGS)
524 /* Tell GCC to use TARGET_RETURN_IN_MEMORY. */
525 #define DEFAULT_PCC_STRUCT_RETURN 0
527 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
528 the stack pointer does not matter. The value is tested only in
529 functions that have frame pointers.
530 No definition is equivalent to always zero. */
531 #define EXIT_IGNORE_STACK 1
533 #define EPILOGUE_USES(REGNO) epiphany_epilogue_uses (REGNO)
535 /* Output assembler code to FILE to increment profiler label # LABELNO
536 for profiling a function entry. */
537 #define FUNCTION_PROFILER(FILE, LABELNO)
539 /* Given an rtx for the frame pointer,
540 return an rtx for the address of the frame. */
541 #define FRAME_ADDR_RTX(frame) \
542 ((frame) == hard_frame_pointer_rtx ? arg_pointer_rtx : NULL)
544 #define EPIPHANY_RETURN_REGNO \
545 ((current_function_decl != NULL \
546 && epiphany_is_interrupt_p (current_function_decl)) \
547 ? IRET_REGNUM : GPR_LR)
548 /* This is not only for dwarf unwind info, but also for the benefit of
549 df-scan.cc to tell it that LR is live at the function start. */
550 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, EPIPHANY_RETURN_REGNO)
552 /* However, we haven't implemented the rest needed for dwarf2 unwind info. */
553 #define DWARF2_UNWIND_INFO 0
555 #define RETURN_ADDR_RTX(count, frame) \
557 : gen_rtx_UNSPEC (SImode, gen_rtvec (1, const0_rtx), UNSPEC_RETURN_ADDR))
559 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (EPIPHANY_RETURN_REGNO)
562 An epiphany trampoline looks like this:
564 movt r16,%high(fnaddr)
569 /* Length in units of the trampoline for entering a nested function. */
570 #define TRAMPOLINE_SIZE 20
572 /* Addressing modes, and classification of registers for them. */
574 /* Maximum number of registers that can appear in a valid memory address. */
575 #define MAX_REGS_PER_ADDRESS 2
577 /* We have post_modify (load/store with update). */
578 #define HAVE_POST_INCREMENT TARGET_POST_INC
579 #define HAVE_POST_DECREMENT TARGET_POST_INC
580 #define HAVE_POST_MODIFY_DISP TARGET_POST_MODIFY
581 #define HAVE_POST_MODIFY_REG TARGET_POST_MODIFY
583 /* Currently, the only users of the USE_*CREMENT macros are
584 move_by_pieces / store_by_pieces_1 . We don't want them to use
585 POST_MODIFY modes, because we got ample addressing range for the
586 reg+offset addressing mode; besides, there are short index+offset loads,
587 but the only short post-modify load uses POST_MODIFY_REG.
588 Moreover, using auto-increment in move_by_pieces from structure copying
589 in the prologue causes confused debug output.
590 If another pass starts using these macros where the use of these
591 addressing modes would make more sense, we can try checking the
593 #define USE_LOAD_POST_INCREMENT(MODE) 0
594 #define USE_LOAD_POST_DECREMENT(MODE) 0
595 #define USE_STORE_POST_INCREMENT(MODE) 0
596 #define USE_STORE_POST_DECREMENT(MODE) 0
598 /* Recognize any constant value that is a valid address. */
599 #define CONSTANT_ADDRESS_P(X) \
600 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
601 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)
603 #define RTX_OK_FOR_OFFSET_P(MODE, X) \
604 RTX_OK_FOR_OFFSET_1 (GET_MODE_CLASS (MODE) == MODE_VECTOR_INT \
605 && epiphany_vect_align == 4 \
606 ? (machine_mode) SImode : (machine_mode) (MODE), X)
607 #define RTX_OK_FOR_OFFSET_1(MODE, X) \
608 (GET_CODE (X) == CONST_INT \
609 && !(INTVAL (X) & (GET_MODE_SIZE (MODE) - 1)) \
610 && INTVAL (X) >= -2047 * (int) GET_MODE_SIZE (MODE) \
611 && INTVAL (X) <= 2047 * (int) GET_MODE_SIZE (MODE))
613 /* Frame offsets cannot be evaluated till the frame pointer is eliminated. */
614 #define RTX_FRAME_OFFSET_P(X) \
615 ((X) == frame_pointer_rtx \
616 || (GET_CODE (X) == PLUS && XEXP ((X), 0) == frame_pointer_rtx \
617 && CONST_INT_P (XEXP ((X), 1))))
619 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
620 return the mode to be used for the comparison. */
621 #define SELECT_CC_MODE(OP, X, Y) \
622 epiphany_select_cc_mode (OP, X, Y)
624 /* Return nonzero if SELECT_CC_MODE will never return MODE for a
625 floating point inequality comparison. */
627 #define REVERSE_CONDITION(CODE, MODE) \
628 ((MODE) == CC_FPmode || (MODE) == CC_FP_EQmode || (MODE) == CC_FP_GTEmode \
629 || (MODE) == CC_FP_ORDmode || (MODE) == CC_FP_UNEQmode \
630 ? reverse_condition_maybe_unordered (CODE) \
631 : (MODE) == CCmode ? reverse_condition (CODE) \
634 /* We can reverse all CCmodes with REVERSE_CONDITION. */
635 #define REVERSIBLE_CC_MODE(MODE) \
636 ((MODE) == CCmode || (MODE) == CC_FPmode || (MODE) == CC_FP_EQmode \
637 || (MODE) == CC_FP_GTEmode || (MODE) == CC_FP_ORDmode \
638 || (MODE) == CC_FP_UNEQmode)
642 /* The cost of a branch insn. */
643 /* ??? What's the right value here? Branches are certainly more
644 expensive than reg->reg moves. */
645 #define BRANCH_COST(speed_p, predictable_p) \
646 (speed_p ? epiphany_branch_cost : 1)
648 /* Nonzero if access to memory by bytes is slow and undesirable.
649 For RISC chips, it means that access to memory by bytes is no
650 better than access by words when possible, so grab a whole word
651 and maybe make use of that. */
652 #define SLOW_BYTE_ACCESS 1
654 /* Define this macro if it is as good or better to call a constant
655 function address than to call an address kept in a register. */
656 /* On the EPIPHANY, calling through registers is slow. */
657 #define NO_FUNCTION_CSE 1
659 /* Section selection. */
660 /* WARNING: These section names also appear in dwarf2out.cc. */
662 #define TEXT_SECTION_ASM_OP "\t.section .text"
663 #define DATA_SECTION_ASM_OP "\t.section .data"
665 #undef READONLY_DATA_SECTION_ASM_OP
666 #define READONLY_DATA_SECTION_ASM_OP "\t.section .rodata"
668 #define BSS_SECTION_ASM_OP "\t.section .bss"
670 /* Define this macro if jump tables (for tablejump insns) should be
671 output in the text section, along with the assembler instructions.
672 Otherwise, the readonly data section is used.
673 This macro is irrelevant if there is no separate readonly data section. */
674 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
678 /* The register number of the register used to address a table of static
679 data addresses in memory. In some cases this register is defined by a
680 processor's ``application binary interface'' (ABI). When this macro
681 is defined, RTL is generated for this register once, as with the stack
682 pointer and frame pointer registers. If this macro is not defined, it
683 is up to the machine-dependent files to allocate such a register (if
685 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REGNO : INVALID_REGNUM)
687 /* Control the assembler format that we output. */
689 /* A C string constant describing how to begin a comment in the target
690 assembler language. The compiler assumes that the comment will
691 end at the end of the line. */
692 #define ASM_COMMENT_START ";"
694 /* Output to assembler file text saying following lines
695 may contain character constants, extra white space, comments, etc. */
696 #define ASM_APP_ON ""
698 /* Output to assembler file text saying following lines
699 no longer contain unusual constructs. */
700 #define ASM_APP_OFF ""
702 /* Globalizing directive for a label. */
703 #define GLOBAL_ASM_OP "\t.global\t"
705 /* How to refer to registers in assembler output.
706 This sequence is indexed by compiler's hard-register-number (see above). */
708 #define REGISTER_NAMES \
710 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
711 "r8", "r9", "r10", "fp", "ip", "sp", "lr", "r15", \
712 "r16", "r17","r18", "r19", "r20", "r21", "r22", "r23", \
713 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \
714 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \
715 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \
716 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \
717 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \
718 "ap", "sfp", "cc1", "cc2", \
719 "config", "status", "lc", "ls", "le", "iret", \
720 "fp_near", "fp_trunc", "fp_anyfp", "unknown" \
723 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
724 epiphany_final_prescan_insn (INSN, OPVEC, NOPERANDS)
726 #define LOCAL_LABEL_PREFIX "."
728 /* A C expression which evaluates to true if CODE is a valid
729 punctuation character for use in the `PRINT_OPERAND' macro. */
730 extern char epiphany_punct_chars
[256];
731 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
732 epiphany_punct_chars[(unsigned char) (CHAR)]
734 /* This is how to output an element of a case-vector that is absolute. */
735 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
737 if (CASE_VECTOR_MODE == Pmode) \
738 asm_fprintf ((FILE), "\t.word %LL%d\n", (VALUE)); \
740 asm_fprintf ((FILE), "\t.short %LL%d\n", (VALUE)); \
743 /* This is how to output an element of a case-vector that is relative. */
744 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
746 if (CASE_VECTOR_MODE == Pmode) \
747 asm_fprintf ((FILE), "\t.word"); \
749 asm_fprintf ((FILE), "\t.short"); \
750 asm_fprintf ((FILE), " %LL%d-%LL%d\n", (VALUE), (REL)); \
753 /* This is how to output an assembler line
754 that says to advance the location counter
755 to a multiple of 2**LOG bytes. */
756 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
757 do { if ((LOG) != 0) fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); } while (0)
759 /* Inside the text section, align with nops rather than zeros. */
760 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE, LOG) \
763 if ((LOG) != 0) fprintf (FILE, "\t.balignw %d,0x01a2\n", 1 << (LOG)); \
766 /* This is how to declare the size of a function. */
767 #undef ASM_DECLARE_FUNCTION_SIZE
768 #define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \
771 const char *__name = (FNAME); \
772 tree attrs = DECL_ATTRIBUTES ((DECL)); \
774 if (!flag_inhibit_size_directive) \
776 if (lookup_attribute ("forwarder_section", attrs)) \
778 const char *prefix = "__forwarder_dst_"; \
780 = (char *) alloca (strlen (prefix) + strlen (__name) + 1); \
782 strcpy (dst_name, prefix); \
783 strcat (dst_name, __name); \
786 ASM_OUTPUT_MEASURED_SIZE ((FILE), __name); \
791 /* Debugging information. */
793 /* Generate DWARF debugging information. */
794 #undef PREFERRED_DEBUGGING_TYPE
795 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
799 /* Specify the machine mode that this machine uses
800 for the index in the tablejump instruction. */
801 #define CASE_VECTOR_MODE (TARGET_SMALL16 && optimize_size ? HImode : Pmode)
803 /* Define if operations between registers always perform the operation
804 on the full register even if a narrower mode is specified. */
805 #define WORD_REGISTER_OPERATIONS 1
807 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
808 will either zero-extend or sign-extend. The value of this macro should
809 be the code that says which one of the two operations is implicitly
810 done, UNKNOWN if none. */
811 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
813 /* Max number of bytes we can move from memory to memory
814 in one reasonably fast instruction. */
817 /* Define this to be nonzero if shift instructions ignore all but the low-order
819 #define SHIFT_COUNT_TRUNCATED 1
821 /* Specify the machine mode that pointers have.
822 After generation of rtl, the compiler makes no further distinction
823 between pointers and any other objects of this machine mode. */
827 /* A function address in a call instruction. */
828 #define FUNCTION_MODE SImode
830 /* EPIPHANY function types. */
831 enum epiphany_function_type
833 EPIPHANY_FUNCTION_UNKNOWN
, EPIPHANY_FUNCTION_NORMAL
,
834 EPIPHANY_FUNCTION_INTERRUPT
837 #define EPIPHANY_INTERRUPT_P(TYPE) ((TYPE) == EPIPHANY_FUNCTION_INTERRUPT)
839 /* Compute the type of a function from its DECL. */
841 #define IMMEDIATE_PREFIX "#"
843 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \
844 (epiphany_optimize_mode_switching (ENTITY))
846 /* We have two fake entities for lazy code motion of the mask constants,
847 one entity each for round-to-nearest / truncating
848 with a different idea what FP_MODE_ROUND_UNKNOWN will be, and
849 finally an entity that runs in a second mode switching pass to
850 resolve FP_MODE_ROUND_UNKNOWN. */
851 #define NUM_MODES_FOR_MODE_SWITCHING \
853 FP_MODE_NONE, FP_MODE_NONE, FP_MODE_NONE, FP_MODE_NONE, FP_MODE_NONE }
855 #define TARGET_INSERT_MODE_SWITCH_USE epiphany_insert_mode_switch_use
857 /* Mode switching entities. */
860 EPIPHANY_MSW_ENTITY_AND
,
861 EPIPHANY_MSW_ENTITY_OR
,
862 EPIPHANY_MSW_ENTITY_CONFIG
, /* 1 means config is known or saved. */
863 EPIPHANY_MSW_ENTITY_NEAREST
,
864 EPIPHANY_MSW_ENTITY_TRUNC
,
865 EPIPHANY_MSW_ENTITY_ROUND_UNKNOWN
,
866 EPIPHANY_MSW_ENTITY_ROUND_KNOWN
,
867 EPIPHANY_MSW_ENTITY_FPU_OMNIBUS
,
868 EPIPHANY_MSW_ENTITY_NUM
871 extern int epiphany_normal_fp_rounding
;
872 #ifndef USED_FOR_TARGET
873 extern rtl_opt_pass
*make_pass_mode_switch_use (gcc::context
*ctxt
);
874 extern rtl_opt_pass
*make_pass_resolve_sw_modes (gcc::context
*ctxt
);
877 /* This will need to be adjusted when FP_CONTRACT_ON is properly
879 #define TARGET_FUSED_MADD (flag_fp_contract_mode == FP_CONTRACT_FAST)
881 #undef ASM_DECLARE_FUNCTION_NAME
882 #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
883 epiphany_start_function ((FILE), (NAME), (DECL))
885 /* This is how we tell the assembler that two symbols have the same value. */
886 #define ASM_OUTPUT_DEF(FILE, NAME1, NAME2) \
889 assemble_name (FILE, NAME1); \
890 fputs (" = ", FILE); \
891 assemble_name (FILE, NAME2); \
892 fputc ('\n', FILE); \
896 #endif /* !GCC_EPIPHANY_H */