1 /* Allocate registers within a basic block, for GNU compiler.
2 Copyright (C) 1987, 1988, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
22 /* Allocation of hard register numbers to pseudo registers is done in
23 two passes. In this pass we consider only regs that are born and
24 die once within one basic block. We do this one basic block at a
25 time. Then the next pass allocates the registers that remain.
26 Two passes are used because this pass uses methods that work only
27 on linear code, but that do a better job than the general methods
28 used in global_alloc, and more quickly too.
30 The assignments made are recorded in the vector reg_renumber
31 whose space is allocated here. The rtl code itself is not altered.
33 We assign each instruction in the basic block a number
34 which is its order from the beginning of the block.
35 Then we can represent the lifetime of a pseudo register with
36 a pair of numbers, and check for conflicts easily.
37 We can record the availability of hard registers with a
38 HARD_REG_SET for each instruction. The HARD_REG_SET
39 contains 0 or 1 for each hard reg.
41 To avoid register shuffling, we tie registers together when one
42 dies by being copied into another, or dies in an instruction that
43 does arithmetic to produce another. The tied registers are
44 allocated as one. Registers with different reg class preferences
45 can never be tied unless the class preferred by one is a subclass
46 of the one preferred by the other.
48 Tying is represented with "quantity numbers".
49 A non-tied register is given a new quantity number.
50 Tied registers have the same quantity number.
52 We have provision to exempt registers, even when they are contained
53 within the block, that can be tied to others that are not contained in it.
54 This is so that global_alloc could process them both and tie them then.
55 But this is currently disabled since tying in global_alloc is not
58 /* Pseudos allocated here can be reallocated by global.c if the hard register
59 is used as a spill register. Currently we don't allocate such pseudos
60 here if their preferred class is likely to be used by spills. */
67 #include "hard-reg-set.h"
68 #include "basic-block.h"
71 #include "insn-config.h"
72 #include "insn-attr.h"
78 /* Next quantity number available for allocation. */
82 /* Information we maitain about each quantity. */
85 /* The number of refs to quantity Q. */
89 /* The frequency of uses of quantity Q. */
93 /* Insn number (counting from head of basic block)
94 where quantity Q was born. -1 if birth has not been recorded. */
98 /* Insn number (counting from head of basic block)
99 where given quantity died. Due to the way tying is done,
100 and the fact that we consider in this pass only regs that die but once,
101 a quantity can die only once. Each quantity's life span
102 is a set of consecutive insns. -1 if death has not been recorded. */
106 /* Number of words needed to hold the data in given quantity.
107 This depends on its machine mode. It is used for these purposes:
108 1. It is used in computing the relative importances of qtys,
109 which determines the order in which we look for regs for them.
110 2. It is used in rules that prevent tying several registers of
111 different sizes in a way that is geometrically impossible
112 (see combine_regs). */
116 /* Number of times a reg tied to given qty lives across a CALL_INSN. */
120 /* The register number of one pseudo register whose reg_qty value is Q.
121 This register should be the head of the chain
122 maintained in reg_next_in_qty. */
126 /* Reg class contained in (smaller than) the preferred classes of all
127 the pseudo regs that are tied in given quantity.
128 This is the preferred class for allocating that quantity. */
130 enum reg_class min_class
;
132 /* Register class within which we allocate given qty if we can't get
133 its preferred class. */
135 enum reg_class alternate_class
;
137 /* This holds the mode of the registers that are tied to given qty,
138 or VOIDmode if registers with differing modes are tied together. */
140 enum machine_mode mode
;
142 /* the hard reg number chosen for given quantity,
143 or -1 if none was found. */
147 /* Nonzero if this quantity has been used in a SUBREG in some
148 way that is illegal. */
154 static struct qty
*qty
;
156 /* These fields are kept separately to speedup their clearing. */
158 /* We maintain two hard register sets that indicate suggested hard registers
159 for each quantity. The first, phys_copy_sugg, contains hard registers
160 that are tied to the quantity by a simple copy. The second contains all
161 hard registers that are tied to the quantity via an arithmetic operation.
163 The former register set is given priority for allocation. This tends to
164 eliminate copy insns. */
166 /* Element Q is a set of hard registers that are suggested for quantity Q by
169 static HARD_REG_SET
*qty_phys_copy_sugg
;
171 /* Element Q is a set of hard registers that are suggested for quantity Q by
174 static HARD_REG_SET
*qty_phys_sugg
;
176 /* Element Q is the number of suggested registers in qty_phys_copy_sugg. */
178 static short *qty_phys_num_copy_sugg
;
180 /* Element Q is the number of suggested registers in qty_phys_sugg. */
182 static short *qty_phys_num_sugg
;
184 /* If (REG N) has been assigned a quantity number, is a register number
185 of another register assigned the same quantity number, or -1 for the
186 end of the chain. qty->first_reg point to the head of this chain. */
188 static int *reg_next_in_qty
;
190 /* reg_qty[N] (where N is a pseudo reg number) is the qty number of that reg
192 of -1 if this register cannot be allocated by local-alloc,
193 or -2 if not known yet.
195 Note that if we see a use or death of pseudo register N with
196 reg_qty[N] == -2, register N must be local to the current block. If
197 it were used in more than one block, we would have reg_qty[N] == -1.
198 This relies on the fact that if reg_basic_block[N] is >= 0, register N
199 will not appear in any other block. We save a considerable number of
200 tests by exploiting this.
202 If N is < FIRST_PSEUDO_REGISTER, reg_qty[N] is undefined and should not
207 /* The offset (in words) of register N within its quantity.
208 This can be nonzero if register N is SImode, and has been tied
209 to a subreg of a DImode register. */
211 static char *reg_offset
;
213 /* Vector of substitutions of register numbers,
214 used to map pseudo regs into hardware regs.
215 This is set up as a result of register allocation.
216 Element N is the hard reg assigned to pseudo reg N,
217 or is -1 if no hard reg was assigned.
218 If N is a hard reg number, element N is N. */
222 /* Set of hard registers live at the current point in the scan
223 of the instructions in a basic block. */
225 static HARD_REG_SET regs_live
;
227 /* Each set of hard registers indicates registers live at a particular
228 point in the basic block. For N even, regs_live_at[N] says which
229 hard registers are needed *after* insn N/2 (i.e., they may not
230 conflict with the outputs of insn N/2 or the inputs of insn N/2 + 1.
232 If an object is to conflict with the inputs of insn J but not the
233 outputs of insn J + 1, we say it is born at index J*2 - 1. Similarly,
234 if it is to conflict with the outputs of insn J but not the inputs of
235 insn J + 1, it is said to die at index J*2 + 1. */
237 static HARD_REG_SET
*regs_live_at
;
239 /* Communicate local vars `insn_number' and `insn'
240 from `block_alloc' to `reg_is_set', `wipe_dead_reg', and `alloc_qty'. */
241 static int this_insn_number
;
242 static rtx this_insn
;
246 /* Set when an attempt should be made to replace a register
247 with the associated src entry. */
251 /* Set when a REG_EQUIV note is found or created. Use to
252 keep track of what memory accesses might be created later,
259 /* Loop depth is used to recognize equivalences which appear
260 to be present within the same loop (or in an inner loop). */
264 /* The list of each instruction which initializes this register. */
269 /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence
270 structure for that register. */
272 static struct equivalence
*reg_equiv
;
274 /* Nonzero if we recorded an equivalence for a LABEL_REF. */
275 static int recorded_label_ref
;
277 static void alloc_qty
PARAMS ((int, enum machine_mode
, int, int));
278 static void validate_equiv_mem_from_store
PARAMS ((rtx
, rtx
, void *));
279 static int validate_equiv_mem
PARAMS ((rtx
, rtx
, rtx
));
280 static int equiv_init_varies_p
PARAMS ((rtx
));
281 static int equiv_init_movable_p
PARAMS ((rtx
, int));
282 static int contains_replace_regs
PARAMS ((rtx
));
283 static int memref_referenced_p
PARAMS ((rtx
, rtx
));
284 static int memref_used_between_p
PARAMS ((rtx
, rtx
, rtx
));
285 static void update_equiv_regs
PARAMS ((void));
286 static void no_equiv
PARAMS ((rtx
, rtx
, void *));
287 static void block_alloc
PARAMS ((int));
288 static int qty_sugg_compare
PARAMS ((int, int));
289 static int qty_sugg_compare_1
PARAMS ((const PTR
, const PTR
));
290 static int qty_compare
PARAMS ((int, int));
291 static int qty_compare_1
PARAMS ((const PTR
, const PTR
));
292 static int combine_regs
PARAMS ((rtx
, rtx
, int, int, rtx
, int));
293 static int reg_meets_class_p
PARAMS ((int, enum reg_class
));
294 static void update_qty_class
PARAMS ((int, int));
295 static void reg_is_set
PARAMS ((rtx
, rtx
, void *));
296 static void reg_is_born
PARAMS ((rtx
, int));
297 static void wipe_dead_reg
PARAMS ((rtx
, int));
298 static int find_free_reg
PARAMS ((enum reg_class
, enum machine_mode
,
299 int, int, int, int, int));
300 static void mark_life
PARAMS ((int, enum machine_mode
, int));
301 static void post_mark_life
PARAMS ((int, enum machine_mode
, int, int, int));
302 static int no_conflict_p
PARAMS ((rtx
, rtx
, rtx
));
303 static int requires_inout
PARAMS ((const char *));
305 /* Allocate a new quantity (new within current basic block)
306 for register number REGNO which is born at index BIRTH
307 within the block. MODE and SIZE are info on reg REGNO. */
310 alloc_qty (regno
, mode
, size
, birth
)
312 enum machine_mode mode
;
315 register int qtyno
= next_qty
++;
317 reg_qty
[regno
] = qtyno
;
318 reg_offset
[regno
] = 0;
319 reg_next_in_qty
[regno
] = -1;
321 qty
[qtyno
].first_reg
= regno
;
322 qty
[qtyno
].size
= size
;
323 qty
[qtyno
].mode
= mode
;
324 qty
[qtyno
].birth
= birth
;
325 qty
[qtyno
].n_calls_crossed
= REG_N_CALLS_CROSSED (regno
);
326 qty
[qtyno
].min_class
= reg_preferred_class (regno
);
327 qty
[qtyno
].alternate_class
= reg_alternate_class (regno
);
328 qty
[qtyno
].n_refs
= REG_N_REFS (regno
);
329 qty
[qtyno
].freq
= REG_FREQ (regno
);
330 qty
[qtyno
].changes_mode
= REG_CHANGES_MODE (regno
);
333 /* Main entry point of this file. */
341 /* We need to keep track of whether or not we recorded a LABEL_REF so
342 that we know if the jump optimizer needs to be rerun. */
343 recorded_label_ref
= 0;
345 /* Leaf functions and non-leaf functions have different needs.
346 If defined, let the machine say what kind of ordering we
348 #ifdef ORDER_REGS_FOR_LOCAL_ALLOC
349 ORDER_REGS_FOR_LOCAL_ALLOC
;
352 /* Promote REG_EQUAL notes to REG_EQUIV notes and adjust status of affected
354 update_equiv_regs ();
356 /* This sets the maximum number of quantities we can have. Quantity
357 numbers start at zero and we can have one for each pseudo. */
358 max_qty
= (max_regno
- FIRST_PSEUDO_REGISTER
);
360 /* Allocate vectors of temporary data.
361 See the declarations of these variables, above,
362 for what they mean. */
364 qty
= (struct qty
*) xmalloc (max_qty
* sizeof (struct qty
));
366 = (HARD_REG_SET
*) xmalloc (max_qty
* sizeof (HARD_REG_SET
));
367 qty_phys_num_copy_sugg
= (short *) xmalloc (max_qty
* sizeof (short));
368 qty_phys_sugg
= (HARD_REG_SET
*) xmalloc (max_qty
* sizeof (HARD_REG_SET
));
369 qty_phys_num_sugg
= (short *) xmalloc (max_qty
* sizeof (short));
371 reg_qty
= (int *) xmalloc (max_regno
* sizeof (int));
372 reg_offset
= (char *) xmalloc (max_regno
* sizeof (char));
373 reg_next_in_qty
= (int *) xmalloc (max_regno
* sizeof (int));
375 /* Allocate the reg_renumber array. */
376 allocate_reg_info (max_regno
, FALSE
, TRUE
);
378 /* Determine which pseudo-registers can be allocated by local-alloc.
379 In general, these are the registers used only in a single block and
382 We need not be concerned with which block actually uses the register
383 since we will never see it outside that block. */
385 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
387 if (REG_BASIC_BLOCK (i
) >= 0 && REG_N_DEATHS (i
) == 1)
393 /* Force loop below to initialize entire quantity array. */
396 /* Allocate each block's local registers, block by block. */
398 for (b
= 0; b
< n_basic_blocks
; b
++)
400 /* NEXT_QTY indicates which elements of the `qty_...'
401 vectors might need to be initialized because they were used
402 for the previous block; it is set to the entire array before
403 block 0. Initialize those, with explicit loop if there are few,
404 else with bzero and bcopy. Do not initialize vectors that are
405 explicit set by `alloc_qty'. */
409 for (i
= 0; i
< next_qty
; i
++)
411 CLEAR_HARD_REG_SET (qty_phys_copy_sugg
[i
]);
412 qty_phys_num_copy_sugg
[i
] = 0;
413 CLEAR_HARD_REG_SET (qty_phys_sugg
[i
]);
414 qty_phys_num_sugg
[i
] = 0;
419 #define CLEAR(vector) \
420 memset ((char *) (vector), 0, (sizeof (*(vector))) * next_qty);
422 CLEAR (qty_phys_copy_sugg
);
423 CLEAR (qty_phys_num_copy_sugg
);
424 CLEAR (qty_phys_sugg
);
425 CLEAR (qty_phys_num_sugg
);
434 free (qty_phys_copy_sugg
);
435 free (qty_phys_num_copy_sugg
);
436 free (qty_phys_sugg
);
437 free (qty_phys_num_sugg
);
441 free (reg_next_in_qty
);
443 return recorded_label_ref
;
446 /* Used for communication between the following two functions: contains
447 a MEM that we wish to ensure remains unchanged. */
448 static rtx equiv_mem
;
450 /* Set nonzero if EQUIV_MEM is modified. */
451 static int equiv_mem_modified
;
453 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified.
454 Called via note_stores. */
457 validate_equiv_mem_from_store (dest
, set
, data
)
459 rtx set ATTRIBUTE_UNUSED
;
460 void *data ATTRIBUTE_UNUSED
;
462 if ((GET_CODE (dest
) == REG
463 && reg_overlap_mentioned_p (dest
, equiv_mem
))
464 || (GET_CODE (dest
) == MEM
465 && true_dependence (dest
, VOIDmode
, equiv_mem
, rtx_varies_p
)))
466 equiv_mem_modified
= 1;
469 /* Verify that no store between START and the death of REG invalidates
470 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF,
471 by storing into an overlapping memory location, or with a non-const
474 Return 1 if MEMREF remains valid. */
477 validate_equiv_mem (start
, reg
, memref
)
486 equiv_mem_modified
= 0;
488 /* If the memory reference has side effects or is volatile, it isn't a
489 valid equivalence. */
490 if (side_effects_p (memref
))
493 for (insn
= start
; insn
&& ! equiv_mem_modified
; insn
= NEXT_INSN (insn
))
498 if (find_reg_note (insn
, REG_DEAD
, reg
))
501 if (GET_CODE (insn
) == CALL_INSN
&& ! RTX_UNCHANGING_P (memref
)
502 && ! CONST_OR_PURE_CALL_P (insn
))
505 note_stores (PATTERN (insn
), validate_equiv_mem_from_store
, NULL
);
507 /* If a register mentioned in MEMREF is modified via an
508 auto-increment, we lose the equivalence. Do the same if one
509 dies; although we could extend the life, it doesn't seem worth
512 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
513 if ((REG_NOTE_KIND (note
) == REG_INC
514 || REG_NOTE_KIND (note
) == REG_DEAD
)
515 && GET_CODE (XEXP (note
, 0)) == REG
516 && reg_overlap_mentioned_p (XEXP (note
, 0), memref
))
523 /* Returns zero if X is known to be invariant. */
526 equiv_init_varies_p (x
)
529 register RTX_CODE code
= GET_CODE (x
);
531 register const char *fmt
;
536 return ! RTX_UNCHANGING_P (x
) || equiv_init_varies_p (XEXP (x
, 0));
549 return reg_equiv
[REGNO (x
)].replace
== 0 && rtx_varies_p (x
, 0);
552 if (MEM_VOLATILE_P (x
))
561 fmt
= GET_RTX_FORMAT (code
);
562 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
565 if (equiv_init_varies_p (XEXP (x
, i
)))
568 else if (fmt
[i
] == 'E')
571 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
572 if (equiv_init_varies_p (XVECEXP (x
, i
, j
)))
579 /* Returns non-zero if X (used to initialize register REGNO) is movable.
580 X is only movable if the registers it uses have equivalent initializations
581 which appear to be within the same loop (or in an inner loop) and movable
582 or if they are not candidates for local_alloc and don't vary. */
585 equiv_init_movable_p (x
, regno
)
591 enum rtx_code code
= GET_CODE (x
);
596 return equiv_init_movable_p (SET_SRC (x
), regno
);
611 return (reg_equiv
[REGNO (x
)].loop_depth
>= reg_equiv
[regno
].loop_depth
612 && reg_equiv
[REGNO (x
)].replace
)
613 || (REG_BASIC_BLOCK (REGNO (x
)) < 0 && ! rtx_varies_p (x
, 0));
615 case UNSPEC_VOLATILE
:
619 if (MEM_VOLATILE_P (x
))
628 fmt
= GET_RTX_FORMAT (code
);
629 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
633 if (! equiv_init_movable_p (XEXP (x
, i
), regno
))
637 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
638 if (! equiv_init_movable_p (XVECEXP (x
, i
, j
), regno
))
646 /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is true. */
649 contains_replace_regs (x
)
654 enum rtx_code code
= GET_CODE (x
);
670 return reg_equiv
[REGNO (x
)].replace
;
676 fmt
= GET_RTX_FORMAT (code
);
677 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
681 if (contains_replace_regs (XEXP (x
, i
)))
685 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
686 if (contains_replace_regs (XVECEXP (x
, i
, j
)))
694 /* TRUE if X references a memory location that would be affected by a store
698 memref_referenced_p (memref
, x
)
704 enum rtx_code code
= GET_CODE (x
);
720 return (reg_equiv
[REGNO (x
)].replacement
721 && memref_referenced_p (memref
,
722 reg_equiv
[REGNO (x
)].replacement
));
725 if (true_dependence (memref
, VOIDmode
, x
, rtx_varies_p
))
730 /* If we are setting a MEM, it doesn't count (its address does), but any
731 other SET_DEST that has a MEM in it is referencing the MEM. */
732 if (GET_CODE (SET_DEST (x
)) == MEM
)
734 if (memref_referenced_p (memref
, XEXP (SET_DEST (x
), 0)))
737 else if (memref_referenced_p (memref
, SET_DEST (x
)))
740 return memref_referenced_p (memref
, SET_SRC (x
));
746 fmt
= GET_RTX_FORMAT (code
);
747 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
751 if (memref_referenced_p (memref
, XEXP (x
, i
)))
755 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
756 if (memref_referenced_p (memref
, XVECEXP (x
, i
, j
)))
764 /* TRUE if some insn in the range (START, END] references a memory location
765 that would be affected by a store to MEMREF. */
768 memref_used_between_p (memref
, start
, end
)
775 for (insn
= NEXT_INSN (start
); insn
!= NEXT_INSN (end
);
776 insn
= NEXT_INSN (insn
))
777 if (INSN_P (insn
) && memref_referenced_p (memref
, PATTERN (insn
)))
783 /* Return nonzero if the rtx X is invariant over the current function. */
785 function_invariant_p (x
)
790 if (x
== frame_pointer_rtx
|| x
== arg_pointer_rtx
)
792 if (GET_CODE (x
) == PLUS
793 && (XEXP (x
, 0) == frame_pointer_rtx
|| XEXP (x
, 0) == arg_pointer_rtx
)
794 && CONSTANT_P (XEXP (x
, 1)))
799 /* Find registers that are equivalent to a single value throughout the
800 compilation (either because they can be referenced in memory or are set once
801 from a single constant). Lower their priority for a register.
803 If such a register is only referenced once, try substituting its value
804 into the using insn. If it succeeds, we can eliminate the register
813 regset_head cleared_regs
;
814 int clear_regnos
= 0;
816 reg_equiv
= (struct equivalence
*) xcalloc (max_regno
, sizeof *reg_equiv
);
817 INIT_REG_SET (&cleared_regs
);
819 init_alias_analysis ();
821 /* Scan the insns and find which registers have equivalences. Do this
822 in a separate scan of the insns because (due to -fcse-follow-jumps)
823 a register can be set below its use. */
824 for (block
= 0; block
< n_basic_blocks
; block
++)
826 basic_block bb
= BASIC_BLOCK (block
);
827 loop_depth
= bb
->loop_depth
;
829 for (insn
= bb
->head
; insn
!= NEXT_INSN (bb
->end
); insn
= NEXT_INSN (insn
))
839 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
840 if (REG_NOTE_KIND (note
) == REG_INC
)
841 no_equiv (XEXP (note
, 0), note
, NULL
);
843 set
= single_set (insn
);
845 /* If this insn contains more (or less) than a single SET,
846 only mark all destinations as having no known equivalence. */
849 note_stores (PATTERN (insn
), no_equiv
, NULL
);
852 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
)
856 for (i
= XVECLEN (PATTERN (insn
), 0) - 1; i
>= 0; i
--)
858 rtx part
= XVECEXP (PATTERN (insn
), 0, i
);
860 note_stores (part
, no_equiv
, NULL
);
864 dest
= SET_DEST (set
);
867 /* If this sets a MEM to the contents of a REG that is only used
868 in a single basic block, see if the register is always equivalent
869 to that memory location and if moving the store from INSN to the
870 insn that set REG is safe. If so, put a REG_EQUIV note on the
873 Don't add a REG_EQUIV note if the insn already has one. The existing
874 REG_EQUIV is likely more useful than the one we are adding.
876 If one of the regs in the address has reg_equiv[REGNO].replace set,
877 then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace
878 optimization may move the set of this register immediately before
879 insn, which puts it after reg_equiv[REGNO].init_insns, and hence
880 the mention in the REG_EQUIV note would be to an uninitialized
882 /* ????? This test isn't good enough; we might see a MEM with a use of
883 a pseudo register before we see its setting insn that will cause
884 reg_equiv[].replace for that pseudo to be set.
885 Equivalences to MEMs should be made in another pass, after the
886 reg_equiv[].replace information has been gathered. */
888 if (GET_CODE (dest
) == MEM
&& GET_CODE (src
) == REG
889 && (regno
= REGNO (src
)) >= FIRST_PSEUDO_REGISTER
890 && REG_BASIC_BLOCK (regno
) >= 0
891 && REG_N_SETS (regno
) == 1
892 && reg_equiv
[regno
].init_insns
!= 0
893 && reg_equiv
[regno
].init_insns
!= const0_rtx
894 && ! find_reg_note (XEXP (reg_equiv
[regno
].init_insns
, 0),
896 && ! contains_replace_regs (XEXP (dest
, 0)))
898 rtx init_insn
= XEXP (reg_equiv
[regno
].init_insns
, 0);
899 if (validate_equiv_mem (init_insn
, src
, dest
)
900 && ! memref_used_between_p (dest
, init_insn
, insn
))
901 REG_NOTES (init_insn
)
902 = gen_rtx_EXPR_LIST (REG_EQUIV
, dest
, REG_NOTES (init_insn
));
905 /* We only handle the case of a pseudo register being set
906 once, or always to the same value. */
907 /* ??? The mn10200 port breaks if we add equivalences for
908 values that need an ADDRESS_REGS register and set them equivalent
909 to a MEM of a pseudo. The actual problem is in the over-conservative
910 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in
911 calculate_needs, but we traditionally work around this problem
912 here by rejecting equivalences when the destination is in a register
913 that's likely spilled. This is fragile, of course, since the
914 preferred class of a pseudo depends on all instructions that set
917 if (GET_CODE (dest
) != REG
918 || (regno
= REGNO (dest
)) < FIRST_PSEUDO_REGISTER
919 || reg_equiv
[regno
].init_insns
== const0_rtx
920 || (CLASS_LIKELY_SPILLED_P (reg_preferred_class (regno
))
921 && GET_CODE (src
) == MEM
))
923 /* This might be seting a SUBREG of a pseudo, a pseudo that is
924 also set somewhere else to a constant. */
925 note_stores (set
, no_equiv
, NULL
);
929 note
= find_reg_note (insn
, REG_EQUAL
, NULL_RTX
);
931 /* cse sometimes generates function invariants, but doesn't put a
932 REG_EQUAL note on the insn. Since this note would be redundant,
933 there's no point creating it earlier than here. */
934 if (! note
&& ! rtx_varies_p (src
, 0))
936 = note
= gen_rtx_EXPR_LIST (REG_EQUAL
, src
, REG_NOTES (insn
));
938 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST
939 since it represents a function call */
940 if (note
&& GET_CODE (XEXP (note
, 0)) == EXPR_LIST
)
943 if (REG_N_SETS (regno
) != 1
945 || rtx_varies_p (XEXP (note
, 0), 0)
946 || (reg_equiv
[regno
].replacement
947 && ! rtx_equal_p (XEXP (note
, 0),
948 reg_equiv
[regno
].replacement
))))
950 no_equiv (dest
, set
, NULL
);
953 /* Record this insn as initializing this register. */
954 reg_equiv
[regno
].init_insns
955 = gen_rtx_INSN_LIST (VOIDmode
, insn
, reg_equiv
[regno
].init_insns
);
957 /* If this register is known to be equal to a constant, record that
958 it is always equivalent to the constant. */
959 if (note
&& ! rtx_varies_p (XEXP (note
, 0), 0))
960 PUT_MODE (note
, (enum machine_mode
) REG_EQUIV
);
962 /* If this insn introduces a "constant" register, decrease the priority
963 of that register. Record this insn if the register is only used once
964 more and the equivalence value is the same as our source.
966 The latter condition is checked for two reasons: First, it is an
967 indication that it may be more efficient to actually emit the insn
968 as written (if no registers are available, reload will substitute
969 the equivalence). Secondly, it avoids problems with any registers
970 dying in this insn whose death notes would be missed.
972 If we don't have a REG_EQUIV note, see if this insn is loading
973 a register used only in one basic block from a MEM. If so, and the
974 MEM remains unchanged for the life of the register, add a REG_EQUIV
977 note
= find_reg_note (insn
, REG_EQUIV
, NULL_RTX
);
979 if (note
== 0 && REG_BASIC_BLOCK (regno
) >= 0
980 && GET_CODE (SET_SRC (set
)) == MEM
981 && validate_equiv_mem (insn
, dest
, SET_SRC (set
)))
982 REG_NOTES (insn
) = note
= gen_rtx_EXPR_LIST (REG_EQUIV
, SET_SRC (set
),
987 int regno
= REGNO (dest
);
989 /* Record whether or not we created a REG_EQUIV note for a LABEL_REF.
990 We might end up substituting the LABEL_REF for uses of the
991 pseudo here or later. That kind of transformation may turn an
992 indirect jump into a direct jump, in which case we must rerun the
993 jump optimizer to ensure that the JUMP_LABEL fields are valid. */
994 if (GET_CODE (XEXP (note
, 0)) == LABEL_REF
995 || (GET_CODE (XEXP (note
, 0)) == CONST
996 && GET_CODE (XEXP (XEXP (note
, 0), 0)) == PLUS
997 && (GET_CODE (XEXP (XEXP (XEXP (note
, 0), 0), 0))
999 recorded_label_ref
= 1;
1001 reg_equiv
[regno
].replacement
= XEXP (note
, 0);
1002 reg_equiv
[regno
].src
= src
;
1003 reg_equiv
[regno
].loop_depth
= loop_depth
;
1005 /* Don't mess with things live during setjmp. */
1006 if (REG_LIVE_LENGTH (regno
) >= 0 && optimize
)
1008 /* Note that the statement below does not affect the priority
1010 REG_LIVE_LENGTH (regno
) *= 2;
1013 /* If the register is referenced exactly twice, meaning it is
1014 set once and used once, indicate that the reference may be
1015 replaced by the equivalence we computed above. Do this
1016 even if the register is only used in one block so that
1017 dependencies can be handled where the last register is
1018 used in a different block (i.e. HIGH / LO_SUM sequences)
1019 and to reduce the number of registers alive across
1022 if (REG_N_REFS (regno
) == 2
1023 && (rtx_equal_p (XEXP (note
, 0), src
)
1024 || ! equiv_init_varies_p (src
))
1025 && GET_CODE (insn
) == INSN
1026 && equiv_init_movable_p (PATTERN (insn
), regno
))
1027 reg_equiv
[regno
].replace
= 1;
1033 /* Now scan all regs killed in an insn to see if any of them are
1034 registers only used that once. If so, see if we can replace the
1035 reference with the equivalent from. If we can, delete the
1036 initializing reference and this register will go away. If we
1037 can't replace the reference, and the initialzing reference is
1038 within the same loop (or in an inner loop), then move the register
1039 initialization just before the use, so that they are in the same
1041 for (block
= n_basic_blocks
- 1; block
>= 0; block
--)
1043 basic_block bb
= BASIC_BLOCK (block
);
1045 loop_depth
= bb
->loop_depth
;
1046 for (insn
= bb
->end
; insn
!= PREV_INSN (bb
->head
); insn
= PREV_INSN (insn
))
1050 if (! INSN_P (insn
))
1053 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1055 if (REG_NOTE_KIND (link
) == REG_DEAD
1056 /* Make sure this insn still refers to the register. */
1057 && reg_mentioned_p (XEXP (link
, 0), PATTERN (insn
)))
1059 int regno
= REGNO (XEXP (link
, 0));
1062 if (! reg_equiv
[regno
].replace
1063 || reg_equiv
[regno
].loop_depth
< loop_depth
)
1066 /* reg_equiv[REGNO].replace gets set only when
1067 REG_N_REFS[REGNO] is 2, i.e. the register is set
1068 once and used once. (If it were only set, but not used,
1069 flow would have deleted the setting insns.) Hence
1070 there can only be one insn in reg_equiv[REGNO].init_insns. */
1071 if (reg_equiv
[regno
].init_insns
== NULL_RTX
1072 || XEXP (reg_equiv
[regno
].init_insns
, 1) != NULL_RTX
)
1074 equiv_insn
= XEXP (reg_equiv
[regno
].init_insns
, 0);
1076 /* We may not move instructions that can throw, since
1077 that changes basic block boundaries and we are not
1078 prepared to adjust the CFG to match. */
1079 if (can_throw_internal (equiv_insn
))
1082 if (asm_noperands (PATTERN (equiv_insn
)) < 0
1083 && validate_replace_rtx (regno_reg_rtx
[regno
],
1084 reg_equiv
[regno
].src
, insn
))
1090 /* Find the last note. */
1091 for (last_link
= link
; XEXP (last_link
, 1);
1092 last_link
= XEXP (last_link
, 1))
1095 /* Append the REG_DEAD notes from equiv_insn. */
1096 equiv_link
= REG_NOTES (equiv_insn
);
1100 equiv_link
= XEXP (equiv_link
, 1);
1101 if (REG_NOTE_KIND (note
) == REG_DEAD
)
1103 remove_note (equiv_insn
, note
);
1104 XEXP (last_link
, 1) = note
;
1105 XEXP (note
, 1) = NULL_RTX
;
1110 remove_death (regno
, insn
);
1111 REG_N_REFS (regno
) = 0;
1112 REG_FREQ (regno
) = 0;
1113 PUT_CODE (equiv_insn
, NOTE
);
1114 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
1115 NOTE_SOURCE_FILE (equiv_insn
) = 0;
1117 reg_equiv
[regno
].init_insns
1118 = XEXP (reg_equiv
[regno
].init_insns
, 1);
1120 /* Move the initialization of the register to just before
1121 INSN. Update the flow information. */
1122 else if (PREV_INSN (insn
) != equiv_insn
)
1126 new_insn
= emit_insn_before (PATTERN (equiv_insn
), insn
);
1127 REG_NOTES (new_insn
) = REG_NOTES (equiv_insn
);
1128 REG_NOTES (equiv_insn
) = 0;
1130 /* Make sure this insn is recognized before reload begins,
1131 otherwise eliminate_regs_in_insn will abort. */
1132 INSN_CODE (new_insn
) = INSN_CODE (equiv_insn
);
1134 PUT_CODE (equiv_insn
, NOTE
);
1135 NOTE_LINE_NUMBER (equiv_insn
) = NOTE_INSN_DELETED
;
1136 NOTE_SOURCE_FILE (equiv_insn
) = 0;
1138 XEXP (reg_equiv
[regno
].init_insns
, 0) = new_insn
;
1140 REG_BASIC_BLOCK (regno
) = block
>= 0 ? block
: 0;
1141 REG_N_CALLS_CROSSED (regno
) = 0;
1142 REG_LIVE_LENGTH (regno
) = 2;
1144 if (block
>= 0 && insn
== BLOCK_HEAD (block
))
1145 BLOCK_HEAD (block
) = PREV_INSN (insn
);
1147 /* Remember to clear REGNO from all basic block's live
1149 SET_REGNO_REG_SET (&cleared_regs
, regno
);
1157 /* Clear all dead REGNOs from all basic block's live info. */
1161 if (clear_regnos
> 8)
1163 for (l
= 0; l
< n_basic_blocks
; l
++)
1165 AND_COMPL_REG_SET (BASIC_BLOCK (l
)->global_live_at_start
,
1167 AND_COMPL_REG_SET (BASIC_BLOCK (l
)->global_live_at_end
,
1172 EXECUTE_IF_SET_IN_REG_SET (&cleared_regs
, 0, j
,
1174 for (l
= 0; l
< n_basic_blocks
; l
++)
1176 CLEAR_REGNO_REG_SET (BASIC_BLOCK (l
)->global_live_at_start
, j
);
1177 CLEAR_REGNO_REG_SET (BASIC_BLOCK (l
)->global_live_at_end
, j
);
1183 end_alias_analysis ();
1184 CLEAR_REG_SET (&cleared_regs
);
1188 /* Mark REG as having no known equivalence.
1189 Some instructions might have been proceessed before and furnished
1190 with REG_EQUIV notes for this register; these notes will have to be
1192 STORE is the piece of RTL that does the non-constant / conflicting
1193 assignment - a SET, CLOBBER or REG_INC note. It is currently not used,
1194 but needs to be there because this function is called from note_stores. */
1196 no_equiv (reg
, store
, data
)
1197 rtx reg
, store ATTRIBUTE_UNUSED
;
1198 void *data ATTRIBUTE_UNUSED
;
1203 if (GET_CODE (reg
) != REG
)
1205 regno
= REGNO (reg
);
1206 list
= reg_equiv
[regno
].init_insns
;
1207 if (list
== const0_rtx
)
1209 for (; list
; list
= XEXP (list
, 1))
1211 rtx insn
= XEXP (list
, 0);
1212 remove_note (insn
, find_reg_note (insn
, REG_EQUIV
, NULL_RTX
));
1214 reg_equiv
[regno
].init_insns
= const0_rtx
;
1215 reg_equiv
[regno
].replacement
= NULL_RTX
;
1218 /* Allocate hard regs to the pseudo regs used only within block number B.
1219 Only the pseudos that die but once can be handled. */
1228 int insn_number
= 0;
1230 int max_uid
= get_max_uid ();
1232 int no_conflict_combined_regno
= -1;
1234 /* Count the instructions in the basic block. */
1236 insn
= BLOCK_END (b
);
1239 if (GET_CODE (insn
) != NOTE
)
1240 if (++insn_count
> max_uid
)
1242 if (insn
== BLOCK_HEAD (b
))
1244 insn
= PREV_INSN (insn
);
1247 /* +2 to leave room for a post_mark_life at the last insn and for
1248 the birth of a CLOBBER in the first insn. */
1249 regs_live_at
= (HARD_REG_SET
*) xcalloc ((2 * insn_count
+ 2),
1250 sizeof (HARD_REG_SET
));
1252 /* Initialize table of hardware registers currently live. */
1254 REG_SET_TO_HARD_REG_SET (regs_live
, BASIC_BLOCK (b
)->global_live_at_start
);
1256 /* This loop scans the instructions of the basic block
1257 and assigns quantities to registers.
1258 It computes which registers to tie. */
1260 insn
= BLOCK_HEAD (b
);
1263 if (GET_CODE (insn
) != NOTE
)
1268 register rtx link
, set
;
1269 register int win
= 0;
1270 register rtx r0
, r1
= NULL_RTX
;
1271 int combined_regno
= -1;
1274 this_insn_number
= insn_number
;
1277 extract_insn (insn
);
1278 which_alternative
= -1;
1280 /* Is this insn suitable for tying two registers?
1281 If so, try doing that.
1282 Suitable insns are those with at least two operands and where
1283 operand 0 is an output that is a register that is not
1286 We can tie operand 0 with some operand that dies in this insn.
1287 First look for operands that are required to be in the same
1288 register as operand 0. If we find such, only try tying that
1289 operand or one that can be put into that operand if the
1290 operation is commutative. If we don't find an operand
1291 that is required to be in the same register as operand 0,
1292 we can tie with any operand.
1294 Subregs in place of regs are also ok.
1296 If tying is done, WIN is set nonzero. */
1299 && recog_data
.n_operands
> 1
1300 && recog_data
.constraints
[0][0] == '='
1301 && recog_data
.constraints
[0][1] != '&')
1303 /* If non-negative, is an operand that must match operand 0. */
1304 int must_match_0
= -1;
1305 /* Counts number of alternatives that require a match with
1307 int n_matching_alts
= 0;
1309 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1311 const char *p
= recog_data
.constraints
[i
];
1312 int this_match
= (requires_inout (p
));
1314 n_matching_alts
+= this_match
;
1315 if (this_match
== recog_data
.n_alternatives
)
1319 r0
= recog_data
.operand
[0];
1320 for (i
= 1; i
< recog_data
.n_operands
; i
++)
1322 /* Skip this operand if we found an operand that
1323 must match operand 0 and this operand isn't it
1324 and can't be made to be it by commutativity. */
1326 if (must_match_0
>= 0 && i
!= must_match_0
1327 && ! (i
== must_match_0
+ 1
1328 && recog_data
.constraints
[i
-1][0] == '%')
1329 && ! (i
== must_match_0
- 1
1330 && recog_data
.constraints
[i
][0] == '%'))
1333 /* Likewise if each alternative has some operand that
1334 must match operand zero. In that case, skip any
1335 operand that doesn't list operand 0 since we know that
1336 the operand always conflicts with operand 0. We
1337 ignore commutatity in this case to keep things simple. */
1338 if (n_matching_alts
== recog_data
.n_alternatives
1339 && 0 == requires_inout (recog_data
.constraints
[i
]))
1342 r1
= recog_data
.operand
[i
];
1344 /* If the operand is an address, find a register in it.
1345 There may be more than one register, but we only try one
1347 if (recog_data
.constraints
[i
][0] == 'p')
1348 while (GET_CODE (r1
) == PLUS
|| GET_CODE (r1
) == MULT
)
1351 if (GET_CODE (r0
) == REG
|| GET_CODE (r0
) == SUBREG
)
1353 /* We have two priorities for hard register preferences.
1354 If we have a move insn or an insn whose first input
1355 can only be in the same register as the output, give
1356 priority to an equivalence found from that insn. */
1358 = (r1
== recog_data
.operand
[i
] && must_match_0
>= 0);
1360 if (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1361 win
= combine_regs (r1
, r0
, may_save_copy
,
1362 insn_number
, insn
, 0);
1369 /* Recognize an insn sequence with an ultimate result
1370 which can safely overlap one of the inputs.
1371 The sequence begins with a CLOBBER of its result,
1372 and ends with an insn that copies the result to itself
1373 and has a REG_EQUAL note for an equivalent formula.
1374 That note indicates what the inputs are.
1375 The result and the input can overlap if each insn in
1376 the sequence either doesn't mention the input
1377 or has a REG_NO_CONFLICT note to inhibit the conflict.
1379 We do the combining test at the CLOBBER so that the
1380 destination register won't have had a quantity number
1381 assigned, since that would prevent combining. */
1384 && GET_CODE (PATTERN (insn
)) == CLOBBER
1385 && (r0
= XEXP (PATTERN (insn
), 0),
1386 GET_CODE (r0
) == REG
)
1387 && (link
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
)) != 0
1388 && XEXP (link
, 0) != 0
1389 && GET_CODE (XEXP (link
, 0)) == INSN
1390 && (set
= single_set (XEXP (link
, 0))) != 0
1391 && SET_DEST (set
) == r0
&& SET_SRC (set
) == r0
1392 && (note
= find_reg_note (XEXP (link
, 0), REG_EQUAL
,
1395 if (r1
= XEXP (note
, 0), GET_CODE (r1
) == REG
1396 /* Check that we have such a sequence. */
1397 && no_conflict_p (insn
, r0
, r1
))
1398 win
= combine_regs (r1
, r0
, 1, insn_number
, insn
, 1);
1399 else if (GET_RTX_FORMAT (GET_CODE (XEXP (note
, 0)))[0] == 'e'
1400 && (r1
= XEXP (XEXP (note
, 0), 0),
1401 GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
)
1402 && no_conflict_p (insn
, r0
, r1
))
1403 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1405 /* Here we care if the operation to be computed is
1407 else if ((GET_CODE (XEXP (note
, 0)) == EQ
1408 || GET_CODE (XEXP (note
, 0)) == NE
1409 || GET_RTX_CLASS (GET_CODE (XEXP (note
, 0))) == 'c')
1410 && (r1
= XEXP (XEXP (note
, 0), 1),
1411 (GET_CODE (r1
) == REG
|| GET_CODE (r1
) == SUBREG
))
1412 && no_conflict_p (insn
, r0
, r1
))
1413 win
= combine_regs (r1
, r0
, 0, insn_number
, insn
, 1);
1415 /* If we did combine something, show the register number
1416 in question so that we know to ignore its death. */
1418 no_conflict_combined_regno
= REGNO (r1
);
1421 /* If registers were just tied, set COMBINED_REGNO
1422 to the number of the register used in this insn
1423 that was tied to the register set in this insn.
1424 This register's qty should not be "killed". */
1428 while (GET_CODE (r1
) == SUBREG
)
1429 r1
= SUBREG_REG (r1
);
1430 combined_regno
= REGNO (r1
);
1433 /* Mark the death of everything that dies in this instruction,
1434 except for anything that was just combined. */
1436 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1437 if (REG_NOTE_KIND (link
) == REG_DEAD
1438 && GET_CODE (XEXP (link
, 0)) == REG
1439 && combined_regno
!= (int) REGNO (XEXP (link
, 0))
1440 && (no_conflict_combined_regno
!= (int) REGNO (XEXP (link
, 0))
1441 || ! find_reg_note (insn
, REG_NO_CONFLICT
,
1443 wipe_dead_reg (XEXP (link
, 0), 0);
1445 /* Allocate qty numbers for all registers local to this block
1446 that are born (set) in this instruction.
1447 A pseudo that already has a qty is not changed. */
1449 note_stores (PATTERN (insn
), reg_is_set
, NULL
);
1451 /* If anything is set in this insn and then unused, mark it as dying
1452 after this insn, so it will conflict with our outputs. This
1453 can't match with something that combined, and it doesn't matter
1454 if it did. Do this after the calls to reg_is_set since these
1455 die after, not during, the current insn. */
1457 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1458 if (REG_NOTE_KIND (link
) == REG_UNUSED
1459 && GET_CODE (XEXP (link
, 0)) == REG
)
1460 wipe_dead_reg (XEXP (link
, 0), 1);
1462 /* If this is an insn that has a REG_RETVAL note pointing at a
1463 CLOBBER insn, we have reached the end of a REG_NO_CONFLICT
1464 block, so clear any register number that combined within it. */
1465 if ((note
= find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)) != 0
1466 && GET_CODE (XEXP (note
, 0)) == INSN
1467 && GET_CODE (PATTERN (XEXP (note
, 0))) == CLOBBER
)
1468 no_conflict_combined_regno
= -1;
1471 /* Set the registers live after INSN_NUMBER. Note that we never
1472 record the registers live before the block's first insn, since no
1473 pseudos we care about are live before that insn. */
1475 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
], regs_live
);
1476 IOR_HARD_REG_SET (regs_live_at
[2 * insn_number
+ 1], regs_live
);
1478 if (insn
== BLOCK_END (b
))
1481 insn
= NEXT_INSN (insn
);
1484 /* Now every register that is local to this basic block
1485 should have been given a quantity, or else -1 meaning ignore it.
1486 Every quantity should have a known birth and death.
1488 Order the qtys so we assign them registers in order of the
1489 number of suggested registers they need so we allocate those with
1490 the most restrictive needs first. */
1492 qty_order
= (int *) xmalloc (next_qty
* sizeof (int));
1493 for (i
= 0; i
< next_qty
; i
++)
1496 #define EXCHANGE(I1, I2) \
1497 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1502 /* Make qty_order[2] be the one to allocate last. */
1503 if (qty_sugg_compare (0, 1) > 0)
1505 if (qty_sugg_compare (1, 2) > 0)
1508 /* ... Fall through ... */
1510 /* Put the best one to allocate in qty_order[0]. */
1511 if (qty_sugg_compare (0, 1) > 0)
1514 /* ... Fall through ... */
1518 /* Nothing to do here. */
1522 qsort (qty_order
, next_qty
, sizeof (int), qty_sugg_compare_1
);
1525 /* Try to put each quantity in a suggested physical register, if it has one.
1526 This may cause registers to be allocated that otherwise wouldn't be, but
1527 this seems acceptable in local allocation (unlike global allocation). */
1528 for (i
= 0; i
< next_qty
; i
++)
1531 if (qty_phys_num_sugg
[q
] != 0 || qty_phys_num_copy_sugg
[q
] != 0)
1532 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
, qty
[q
].mode
, q
,
1533 0, 1, qty
[q
].birth
, qty
[q
].death
);
1535 qty
[q
].phys_reg
= -1;
1538 /* Order the qtys so we assign them registers in order of
1539 decreasing length of life. Normally call qsort, but if we
1540 have only a very small number of quantities, sort them ourselves. */
1542 for (i
= 0; i
< next_qty
; i
++)
1545 #define EXCHANGE(I1, I2) \
1546 { i = qty_order[I1]; qty_order[I1] = qty_order[I2]; qty_order[I2] = i; }
1551 /* Make qty_order[2] be the one to allocate last. */
1552 if (qty_compare (0, 1) > 0)
1554 if (qty_compare (1, 2) > 0)
1557 /* ... Fall through ... */
1559 /* Put the best one to allocate in qty_order[0]. */
1560 if (qty_compare (0, 1) > 0)
1563 /* ... Fall through ... */
1567 /* Nothing to do here. */
1571 qsort (qty_order
, next_qty
, sizeof (int), qty_compare_1
);
1574 /* Now for each qty that is not a hardware register,
1575 look for a hardware register to put it in.
1576 First try the register class that is cheapest for this qty,
1577 if there is more than one class. */
1579 for (i
= 0; i
< next_qty
; i
++)
1582 if (qty
[q
].phys_reg
< 0)
1584 #ifdef INSN_SCHEDULING
1585 /* These values represent the adjusted lifetime of a qty so
1586 that it conflicts with qtys which appear near the start/end
1587 of this qty's lifetime.
1589 The purpose behind extending the lifetime of this qty is to
1590 discourage the register allocator from creating false
1593 The adjustment value is choosen to indicate that this qty
1594 conflicts with all the qtys in the instructions immediately
1595 before and after the lifetime of this qty.
1597 Experiments have shown that higher values tend to hurt
1598 overall code performance.
1600 If allocation using the extended lifetime fails we will try
1601 again with the qty's unadjusted lifetime. */
1602 int fake_birth
= MAX (0, qty
[q
].birth
- 2 + qty
[q
].birth
% 2);
1603 int fake_death
= MIN (insn_number
* 2 + 1,
1604 qty
[q
].death
+ 2 - qty
[q
].death
% 2);
1607 if (N_REG_CLASSES
> 1)
1609 #ifdef INSN_SCHEDULING
1610 /* We try to avoid using hard registers allocated to qtys which
1611 are born immediately after this qty or die immediately before
1614 This optimization is only appropriate when we will run
1615 a scheduling pass after reload and we are not optimizing
1617 if (flag_schedule_insns_after_reload
1619 && !SMALL_REGISTER_CLASSES
)
1621 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
,
1622 qty
[q
].mode
, q
, 0, 0,
1623 fake_birth
, fake_death
);
1624 if (qty
[q
].phys_reg
>= 0)
1628 qty
[q
].phys_reg
= find_free_reg (qty
[q
].min_class
,
1629 qty
[q
].mode
, q
, 0, 0,
1630 qty
[q
].birth
, qty
[q
].death
);
1631 if (qty
[q
].phys_reg
>= 0)
1635 #ifdef INSN_SCHEDULING
1636 /* Similarly, avoid false dependencies. */
1637 if (flag_schedule_insns_after_reload
1639 && !SMALL_REGISTER_CLASSES
1640 && qty
[q
].alternate_class
!= NO_REGS
)
1641 qty
[q
].phys_reg
= find_free_reg (qty
[q
].alternate_class
,
1642 qty
[q
].mode
, q
, 0, 0,
1643 fake_birth
, fake_death
);
1645 if (qty
[q
].alternate_class
!= NO_REGS
)
1646 qty
[q
].phys_reg
= find_free_reg (qty
[q
].alternate_class
,
1647 qty
[q
].mode
, q
, 0, 0,
1648 qty
[q
].birth
, qty
[q
].death
);
1652 /* Now propagate the register assignments
1653 to the pseudo regs belonging to the qtys. */
1655 for (q
= 0; q
< next_qty
; q
++)
1656 if (qty
[q
].phys_reg
>= 0)
1658 for (i
= qty
[q
].first_reg
; i
>= 0; i
= reg_next_in_qty
[i
])
1659 reg_renumber
[i
] = qty
[q
].phys_reg
+ reg_offset
[i
];
1663 free (regs_live_at
);
1667 /* Compare two quantities' priority for getting real registers.
1668 We give shorter-lived quantities higher priority.
1669 Quantities with more references are also preferred, as are quantities that
1670 require multiple registers. This is the identical prioritization as
1671 done by global-alloc.
1673 We used to give preference to registers with *longer* lives, but using
1674 the same algorithm in both local- and global-alloc can speed up execution
1675 of some programs by as much as a factor of three! */
1677 /* Note that the quotient will never be bigger than
1678 the value of floor_log2 times the maximum number of
1679 times a register can occur in one insn (surely less than 100)
1680 weighted by frequency (max REG_FREQ_MAX).
1681 Multiplying this by 10000/REG_FREQ_MAX can't overflow.
1682 QTY_CMP_PRI is also used by qty_sugg_compare. */
1684 #define QTY_CMP_PRI(q) \
1685 ((int) (((double) (floor_log2 (qty[q].n_refs) * qty[q].freq * qty[q].size) \
1686 / (qty[q].death - qty[q].birth)) * (10000 / REG_FREQ_MAX)))
1689 qty_compare (q1
, q2
)
1692 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1696 qty_compare_1 (q1p
, q2p
)
1700 register int q1
= *(const int *) q1p
, q2
= *(const int *) q2p
;
1701 register int tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1706 /* If qtys are equally good, sort by qty number,
1707 so that the results of qsort leave nothing to chance. */
1711 /* Compare two quantities' priority for getting real registers. This version
1712 is called for quantities that have suggested hard registers. First priority
1713 goes to quantities that have copy preferences, then to those that have
1714 normal preferences. Within those groups, quantities with the lower
1715 number of preferences have the highest priority. Of those, we use the same
1716 algorithm as above. */
1718 #define QTY_CMP_SUGG(q) \
1719 (qty_phys_num_copy_sugg[q] \
1720 ? qty_phys_num_copy_sugg[q] \
1721 : qty_phys_num_sugg[q] * FIRST_PSEUDO_REGISTER)
1724 qty_sugg_compare (q1
, q2
)
1727 register int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1732 return QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1736 qty_sugg_compare_1 (q1p
, q2p
)
1740 register int q1
= *(const int *) q1p
, q2
= *(const int *) q2p
;
1741 register int tem
= QTY_CMP_SUGG (q1
) - QTY_CMP_SUGG (q2
);
1746 tem
= QTY_CMP_PRI (q2
) - QTY_CMP_PRI (q1
);
1750 /* If qtys are equally good, sort by qty number,
1751 so that the results of qsort leave nothing to chance. */
1758 /* Attempt to combine the two registers (rtx's) USEDREG and SETREG.
1759 Returns 1 if have done so, or 0 if cannot.
1761 Combining registers means marking them as having the same quantity
1762 and adjusting the offsets within the quantity if either of
1765 We don't actually combine a hard reg with a pseudo; instead
1766 we just record the hard reg as the suggestion for the pseudo's quantity.
1767 If we really combined them, we could lose if the pseudo lives
1768 across an insn that clobbers the hard reg (eg, movstr).
1770 ALREADY_DEAD is non-zero if USEDREG is known to be dead even though
1771 there is no REG_DEAD note on INSN. This occurs during the processing
1772 of REG_NO_CONFLICT blocks.
1774 MAY_SAVE_COPYCOPY is non-zero if this insn is simply copying USEDREG to
1775 SETREG or if the input and output must share a register.
1776 In that case, we record a hard reg suggestion in QTY_PHYS_COPY_SUGG.
1778 There are elaborate checks for the validity of combining. */
1781 combine_regs (usedreg
, setreg
, may_save_copy
, insn_number
, insn
, already_dead
)
1782 rtx usedreg
, setreg
;
1788 register int ureg
, sreg
;
1789 register int offset
= 0;
1793 /* Determine the numbers and sizes of registers being used. If a subreg
1794 is present that does not change the entire register, don't consider
1795 this a copy insn. */
1797 while (GET_CODE (usedreg
) == SUBREG
)
1799 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (usedreg
))) > UNITS_PER_WORD
)
1801 if (REGNO (SUBREG_REG (usedreg
)) < FIRST_PSEUDO_REGISTER
)
1802 offset
+= subreg_regno_offset (REGNO (SUBREG_REG (usedreg
)),
1803 GET_MODE (SUBREG_REG (usedreg
)),
1804 SUBREG_BYTE (usedreg
),
1805 GET_MODE (usedreg
));
1807 offset
+= (SUBREG_BYTE (usedreg
)
1808 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg
)));
1809 usedreg
= SUBREG_REG (usedreg
);
1811 if (GET_CODE (usedreg
) != REG
)
1813 ureg
= REGNO (usedreg
);
1814 if (ureg
< FIRST_PSEUDO_REGISTER
)
1815 usize
= HARD_REGNO_NREGS (ureg
, GET_MODE (usedreg
));
1817 usize
= ((GET_MODE_SIZE (GET_MODE (usedreg
))
1818 + (REGMODE_NATURAL_SIZE (GET_MODE (usedreg
)) - 1))
1819 / REGMODE_NATURAL_SIZE (GET_MODE (usedreg
)));
1821 while (GET_CODE (setreg
) == SUBREG
)
1823 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (setreg
))) > UNITS_PER_WORD
)
1825 if (REGNO (SUBREG_REG (setreg
)) < FIRST_PSEUDO_REGISTER
)
1826 offset
-= subreg_regno_offset (REGNO (SUBREG_REG (setreg
)),
1827 GET_MODE (SUBREG_REG (setreg
)),
1828 SUBREG_BYTE (setreg
),
1831 offset
-= (SUBREG_BYTE (setreg
)
1832 / REGMODE_NATURAL_SIZE (GET_MODE (setreg
)));
1833 setreg
= SUBREG_REG (setreg
);
1835 if (GET_CODE (setreg
) != REG
)
1837 sreg
= REGNO (setreg
);
1838 if (sreg
< FIRST_PSEUDO_REGISTER
)
1839 ssize
= HARD_REGNO_NREGS (sreg
, GET_MODE (setreg
));
1841 ssize
= ((GET_MODE_SIZE (GET_MODE (setreg
))
1842 + (REGMODE_NATURAL_SIZE (GET_MODE (setreg
)) - 1))
1843 / REGMODE_NATURAL_SIZE (GET_MODE (setreg
)));
1845 /* If UREG is a pseudo-register that hasn't already been assigned a
1846 quantity number, it means that it is not local to this block or dies
1847 more than once. In either event, we can't do anything with it. */
1848 if ((ureg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[ureg
] < 0)
1849 /* Do not combine registers unless one fits within the other. */
1850 || (offset
> 0 && usize
+ offset
> ssize
)
1851 || (offset
< 0 && usize
+ offset
< ssize
)
1852 /* Do not combine with a smaller already-assigned object
1853 if that smaller object is already combined with something bigger. */
1854 || (ssize
> usize
&& ureg
>= FIRST_PSEUDO_REGISTER
1855 && usize
< qty
[reg_qty
[ureg
]].size
)
1856 /* Can't combine if SREG is not a register we can allocate. */
1857 || (sreg
>= FIRST_PSEUDO_REGISTER
&& reg_qty
[sreg
] == -1)
1858 /* Don't combine with a pseudo mentioned in a REG_NO_CONFLICT note.
1859 These have already been taken care of. This probably wouldn't
1860 combine anyway, but don't take any chances. */
1861 || (ureg
>= FIRST_PSEUDO_REGISTER
1862 && find_reg_note (insn
, REG_NO_CONFLICT
, usedreg
))
1863 /* Don't tie something to itself. In most cases it would make no
1864 difference, but it would screw up if the reg being tied to itself
1865 also dies in this insn. */
1867 /* Don't try to connect two different hardware registers. */
1868 || (ureg
< FIRST_PSEUDO_REGISTER
&& sreg
< FIRST_PSEUDO_REGISTER
)
1869 /* Don't connect two different machine modes if they have different
1870 implications as to which registers may be used. */
1871 || !MODES_TIEABLE_P (GET_MODE (usedreg
), GET_MODE (setreg
)))
1874 /* Now, if UREG is a hard reg and SREG is a pseudo, record the hard reg in
1875 qty_phys_sugg for the pseudo instead of tying them.
1877 Return "failure" so that the lifespan of UREG is terminated here;
1878 that way the two lifespans will be disjoint and nothing will prevent
1879 the pseudo reg from being given this hard reg. */
1881 if (ureg
< FIRST_PSEUDO_REGISTER
)
1883 /* Allocate a quantity number so we have a place to put our
1885 if (reg_qty
[sreg
] == -2)
1886 reg_is_born (setreg
, 2 * insn_number
);
1888 if (reg_qty
[sreg
] >= 0)
1891 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
))
1893 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[sreg
]], ureg
);
1894 qty_phys_num_copy_sugg
[reg_qty
[sreg
]]++;
1896 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
))
1898 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[sreg
]], ureg
);
1899 qty_phys_num_sugg
[reg_qty
[sreg
]]++;
1905 /* Similarly for SREG a hard register and UREG a pseudo register. */
1907 if (sreg
< FIRST_PSEUDO_REGISTER
)
1910 && ! TEST_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
))
1912 SET_HARD_REG_BIT (qty_phys_copy_sugg
[reg_qty
[ureg
]], sreg
);
1913 qty_phys_num_copy_sugg
[reg_qty
[ureg
]]++;
1915 else if (! TEST_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
))
1917 SET_HARD_REG_BIT (qty_phys_sugg
[reg_qty
[ureg
]], sreg
);
1918 qty_phys_num_sugg
[reg_qty
[ureg
]]++;
1923 /* At this point we know that SREG and UREG are both pseudos.
1924 Do nothing if SREG already has a quantity or is a register that we
1926 if (reg_qty
[sreg
] >= -1
1927 /* If we are not going to let any regs live across calls,
1928 don't tie a call-crossing reg to a non-call-crossing reg. */
1929 || (current_function_has_nonlocal_label
1930 && ((REG_N_CALLS_CROSSED (ureg
) > 0)
1931 != (REG_N_CALLS_CROSSED (sreg
) > 0))))
1934 /* We don't already know about SREG, so tie it to UREG
1935 if this is the last use of UREG, provided the classes they want
1938 if ((already_dead
|| find_regno_note (insn
, REG_DEAD
, ureg
))
1939 && reg_meets_class_p (sreg
, qty
[reg_qty
[ureg
]].min_class
))
1941 /* Add SREG to UREG's quantity. */
1942 sqty
= reg_qty
[ureg
];
1943 reg_qty
[sreg
] = sqty
;
1944 reg_offset
[sreg
] = reg_offset
[ureg
] + offset
;
1945 reg_next_in_qty
[sreg
] = qty
[sqty
].first_reg
;
1946 qty
[sqty
].first_reg
= sreg
;
1948 /* If SREG's reg class is smaller, set qty[SQTY].min_class. */
1949 update_qty_class (sqty
, sreg
);
1951 /* Update info about quantity SQTY. */
1952 qty
[sqty
].n_calls_crossed
+= REG_N_CALLS_CROSSED (sreg
);
1953 qty
[sqty
].n_refs
+= REG_N_REFS (sreg
);
1954 qty
[sqty
].freq
+= REG_FREQ (sreg
);
1959 for (i
= qty
[sqty
].first_reg
; i
>= 0; i
= reg_next_in_qty
[i
])
1960 reg_offset
[i
] -= offset
;
1962 qty
[sqty
].size
= ssize
;
1963 qty
[sqty
].mode
= GET_MODE (setreg
);
1972 /* Return 1 if the preferred class of REG allows it to be tied
1973 to a quantity or register whose class is CLASS.
1974 True if REG's reg class either contains or is contained in CLASS. */
1977 reg_meets_class_p (reg
, class)
1979 enum reg_class
class;
1981 register enum reg_class rclass
= reg_preferred_class (reg
);
1982 return (reg_class_subset_p (rclass
, class)
1983 || reg_class_subset_p (class, rclass
));
1986 /* Update the class of QTYNO assuming that REG is being tied to it. */
1989 update_qty_class (qtyno
, reg
)
1993 enum reg_class rclass
= reg_preferred_class (reg
);
1994 if (reg_class_subset_p (rclass
, qty
[qtyno
].min_class
))
1995 qty
[qtyno
].min_class
= rclass
;
1997 rclass
= reg_alternate_class (reg
);
1998 if (reg_class_subset_p (rclass
, qty
[qtyno
].alternate_class
))
1999 qty
[qtyno
].alternate_class
= rclass
;
2001 if (REG_CHANGES_MODE (reg
))
2002 qty
[qtyno
].changes_mode
= 1;
2005 /* Handle something which alters the value of an rtx REG.
2007 REG is whatever is set or clobbered. SETTER is the rtx that
2008 is modifying the register.
2010 If it is not really a register, we do nothing.
2011 The file-global variables `this_insn' and `this_insn_number'
2012 carry info from `block_alloc'. */
2015 reg_is_set (reg
, setter
, data
)
2018 void *data ATTRIBUTE_UNUSED
;
2020 /* Note that note_stores will only pass us a SUBREG if it is a SUBREG of
2021 a hard register. These may actually not exist any more. */
2023 if (GET_CODE (reg
) != SUBREG
2024 && GET_CODE (reg
) != REG
)
2027 /* Mark this register as being born. If it is used in a CLOBBER, mark
2028 it as being born halfway between the previous insn and this insn so that
2029 it conflicts with our inputs but not the outputs of the previous insn. */
2031 reg_is_born (reg
, 2 * this_insn_number
- (GET_CODE (setter
) == CLOBBER
));
2034 /* Handle beginning of the life of register REG.
2035 BIRTH is the index at which this is happening. */
2038 reg_is_born (reg
, birth
)
2044 if (GET_CODE (reg
) == SUBREG
)
2046 regno
= REGNO (SUBREG_REG (reg
));
2047 if (regno
< FIRST_PSEUDO_REGISTER
)
2048 regno
= subreg_hard_regno (reg
, 1);
2051 regno
= REGNO (reg
);
2053 if (regno
< FIRST_PSEUDO_REGISTER
)
2055 mark_life (regno
, GET_MODE (reg
), 1);
2057 /* If the register was to have been born earlier that the present
2058 insn, mark it as live where it is actually born. */
2059 if (birth
< 2 * this_insn_number
)
2060 post_mark_life (regno
, GET_MODE (reg
), 1, birth
, 2 * this_insn_number
);
2064 if (reg_qty
[regno
] == -2)
2065 alloc_qty (regno
, GET_MODE (reg
), PSEUDO_REGNO_SIZE (regno
), birth
);
2067 /* If this register has a quantity number, show that it isn't dead. */
2068 if (reg_qty
[regno
] >= 0)
2069 qty
[reg_qty
[regno
]].death
= -1;
2073 /* Record the death of REG in the current insn. If OUTPUT_P is non-zero,
2074 REG is an output that is dying (i.e., it is never used), otherwise it
2075 is an input (the normal case).
2076 If OUTPUT_P is 1, then we extend the life past the end of this insn. */
2079 wipe_dead_reg (reg
, output_p
)
2083 register int regno
= REGNO (reg
);
2085 /* If this insn has multiple results,
2086 and the dead reg is used in one of the results,
2087 extend its life to after this insn,
2088 so it won't get allocated together with any other result of this insn.
2090 It is unsafe to use !single_set here since it will ignore an unused
2091 output. Just because an output is unused does not mean the compiler
2092 can assume the side effect will not occur. Consider if REG appears
2093 in the address of an output and we reload the output. If we allocate
2094 REG to the same hard register as an unused output we could set the hard
2095 register before the output reload insn. */
2096 if (GET_CODE (PATTERN (this_insn
)) == PARALLEL
2097 && multiple_sets (this_insn
))
2100 for (i
= XVECLEN (PATTERN (this_insn
), 0) - 1; i
>= 0; i
--)
2102 rtx set
= XVECEXP (PATTERN (this_insn
), 0, i
);
2103 if (GET_CODE (set
) == SET
2104 && GET_CODE (SET_DEST (set
)) != REG
2105 && !rtx_equal_p (reg
, SET_DEST (set
))
2106 && reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
2111 /* If this register is used in an auto-increment address, then extend its
2112 life to after this insn, so that it won't get allocated together with
2113 the result of this insn. */
2114 if (! output_p
&& find_regno_note (this_insn
, REG_INC
, regno
))
2117 if (regno
< FIRST_PSEUDO_REGISTER
)
2119 mark_life (regno
, GET_MODE (reg
), 0);
2121 /* If a hard register is dying as an output, mark it as in use at
2122 the beginning of this insn (the above statement would cause this
2125 post_mark_life (regno
, GET_MODE (reg
), 1,
2126 2 * this_insn_number
, 2 * this_insn_number
+ 1);
2129 else if (reg_qty
[regno
] >= 0)
2130 qty
[reg_qty
[regno
]].death
= 2 * this_insn_number
+ output_p
;
2133 /* Find a block of SIZE words of hard regs in reg_class CLASS
2134 that can hold something of machine-mode MODE
2135 (but actually we test only the first of the block for holding MODE)
2136 and still free between insn BORN_INDEX and insn DEAD_INDEX,
2137 and return the number of the first of them.
2138 Return -1 if such a block cannot be found.
2139 If QTYNO crosses calls, insist on a register preserved by calls,
2140 unless ACCEPT_CALL_CLOBBERED is nonzero.
2142 If JUST_TRY_SUGGESTED is non-zero, only try to see if the suggested
2143 register is available. If not, return -1. */
2146 find_free_reg (class, mode
, qtyno
, accept_call_clobbered
, just_try_suggested
,
2147 born_index
, dead_index
)
2148 enum reg_class
class;
2149 enum machine_mode mode
;
2151 int accept_call_clobbered
;
2152 int just_try_suggested
;
2153 int born_index
, dead_index
;
2155 register int i
, ins
;
2157 /* Declare it register if it's a scalar. */
2160 HARD_REG_SET used
, first_used
;
2161 #ifdef ELIMINABLE_REGS
2162 static struct {int from
, to
; } eliminables
[] = ELIMINABLE_REGS
;
2165 /* Validate our parameters. */
2166 if (born_index
< 0 || born_index
> dead_index
)
2169 /* Don't let a pseudo live in a reg across a function call
2170 if we might get a nonlocal goto. */
2171 if (current_function_has_nonlocal_label
2172 && qty
[qtyno
].n_calls_crossed
> 0)
2175 if (accept_call_clobbered
)
2176 COPY_HARD_REG_SET (used
, call_fixed_reg_set
);
2177 else if (qty
[qtyno
].n_calls_crossed
== 0)
2178 COPY_HARD_REG_SET (used
, fixed_reg_set
);
2180 COPY_HARD_REG_SET (used
, call_used_reg_set
);
2182 if (accept_call_clobbered
)
2183 IOR_HARD_REG_SET (used
, losing_caller_save_reg_set
);
2185 for (ins
= born_index
; ins
< dead_index
; ins
++)
2186 IOR_HARD_REG_SET (used
, regs_live_at
[ins
]);
2188 IOR_COMPL_HARD_REG_SET (used
, reg_class_contents
[(int) class]);
2190 /* Don't use the frame pointer reg in local-alloc even if
2191 we may omit the frame pointer, because if we do that and then we
2192 need a frame pointer, reload won't know how to move the pseudo
2193 to another hard reg. It can move only regs made by global-alloc.
2195 This is true of any register that can be eliminated. */
2196 #ifdef ELIMINABLE_REGS
2197 for (i
= 0; i
< (int) ARRAY_SIZE (eliminables
); i
++)
2198 SET_HARD_REG_BIT (used
, eliminables
[i
].from
);
2199 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
2200 /* If FRAME_POINTER_REGNUM is not a real register, then protect the one
2201 that it might be eliminated into. */
2202 SET_HARD_REG_BIT (used
, HARD_FRAME_POINTER_REGNUM
);
2205 SET_HARD_REG_BIT (used
, FRAME_POINTER_REGNUM
);
2208 #ifdef CLASS_CANNOT_CHANGE_MODE
2209 if (qty
[qtyno
].changes_mode
)
2210 IOR_HARD_REG_SET (used
,
2211 reg_class_contents
[(int) CLASS_CANNOT_CHANGE_MODE
]);
2214 /* Normally, the registers that can be used for the first register in
2215 a multi-register quantity are the same as those that can be used for
2216 subsequent registers. However, if just trying suggested registers,
2217 restrict our consideration to them. If there are copy-suggested
2218 register, try them. Otherwise, try the arithmetic-suggested
2220 COPY_HARD_REG_SET (first_used
, used
);
2222 if (just_try_suggested
)
2224 if (qty_phys_num_copy_sugg
[qtyno
] != 0)
2225 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_copy_sugg
[qtyno
]);
2227 IOR_COMPL_HARD_REG_SET (first_used
, qty_phys_sugg
[qtyno
]);
2230 /* If all registers are excluded, we can't do anything. */
2231 GO_IF_HARD_REG_SUBSET (reg_class_contents
[(int) ALL_REGS
], first_used
, fail
);
2233 /* If at least one would be suitable, test each hard reg. */
2235 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2237 #ifdef REG_ALLOC_ORDER
2238 int regno
= reg_alloc_order
[i
];
2242 if (! TEST_HARD_REG_BIT (first_used
, regno
)
2243 && HARD_REGNO_MODE_OK (regno
, mode
)
2244 && (qty
[qtyno
].n_calls_crossed
== 0
2245 || accept_call_clobbered
2246 || ! HARD_REGNO_CALL_PART_CLOBBERED (regno
, mode
)))
2249 register int size1
= HARD_REGNO_NREGS (regno
, mode
);
2250 for (j
= 1; j
< size1
&& ! TEST_HARD_REG_BIT (used
, regno
+ j
); j
++);
2253 /* Mark that this register is in use between its birth and death
2255 post_mark_life (regno
, mode
, 1, born_index
, dead_index
);
2258 #ifndef REG_ALLOC_ORDER
2259 /* Skip starting points we know will lose. */
2266 /* If we are just trying suggested register, we have just tried copy-
2267 suggested registers, and there are arithmetic-suggested registers,
2270 /* If it would be profitable to allocate a call-clobbered register
2271 and save and restore it around calls, do that. */
2272 if (just_try_suggested
&& qty_phys_num_copy_sugg
[qtyno
] != 0
2273 && qty_phys_num_sugg
[qtyno
] != 0)
2275 /* Don't try the copy-suggested regs again. */
2276 qty_phys_num_copy_sugg
[qtyno
] = 0;
2277 return find_free_reg (class, mode
, qtyno
, accept_call_clobbered
, 1,
2278 born_index
, dead_index
);
2281 /* We need not check to see if the current function has nonlocal
2282 labels because we don't put any pseudos that are live over calls in
2283 registers in that case. */
2285 if (! accept_call_clobbered
2286 && flag_caller_saves
2287 && ! just_try_suggested
2288 && qty
[qtyno
].n_calls_crossed
!= 0
2289 && CALLER_SAVE_PROFITABLE (qty
[qtyno
].n_refs
,
2290 qty
[qtyno
].n_calls_crossed
))
2292 i
= find_free_reg (class, mode
, qtyno
, 1, 0, born_index
, dead_index
);
2294 caller_save_needed
= 1;
2300 /* Mark that REGNO with machine-mode MODE is live starting from the current
2301 insn (if LIFE is non-zero) or dead starting at the current insn (if LIFE
2305 mark_life (regno
, mode
, life
)
2307 enum machine_mode mode
;
2310 register int j
= HARD_REGNO_NREGS (regno
, mode
);
2313 SET_HARD_REG_BIT (regs_live
, regno
+ j
);
2316 CLEAR_HARD_REG_BIT (regs_live
, regno
+ j
);
2319 /* Mark register number REGNO (with machine-mode MODE) as live (if LIFE
2320 is non-zero) or dead (if LIFE is zero) from insn number BIRTH (inclusive)
2321 to insn number DEATH (exclusive). */
2324 post_mark_life (regno
, mode
, life
, birth
, death
)
2326 enum machine_mode mode
;
2327 int life
, birth
, death
;
2329 register int j
= HARD_REGNO_NREGS (regno
, mode
);
2331 /* Declare it register if it's a scalar. */
2334 HARD_REG_SET this_reg
;
2336 CLEAR_HARD_REG_SET (this_reg
);
2338 SET_HARD_REG_BIT (this_reg
, regno
+ j
);
2341 while (birth
< death
)
2343 IOR_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2347 while (birth
< death
)
2349 AND_COMPL_HARD_REG_SET (regs_live_at
[birth
], this_reg
);
2354 /* INSN is the CLOBBER insn that starts a REG_NO_NOCONFLICT block, R0
2355 is the register being clobbered, and R1 is a register being used in
2356 the equivalent expression.
2358 If R1 dies in the block and has a REG_NO_CONFLICT note on every insn
2359 in which it is used, return 1.
2361 Otherwise, return 0. */
2364 no_conflict_p (insn
, r0
, r1
)
2365 rtx insn
, r0 ATTRIBUTE_UNUSED
, r1
;
2368 rtx note
= find_reg_note (insn
, REG_LIBCALL
, NULL_RTX
);
2371 /* If R1 is a hard register, return 0 since we handle this case
2372 when we scan the insns that actually use it. */
2375 || (GET_CODE (r1
) == REG
&& REGNO (r1
) < FIRST_PSEUDO_REGISTER
)
2376 || (GET_CODE (r1
) == SUBREG
&& GET_CODE (SUBREG_REG (r1
)) == REG
2377 && REGNO (SUBREG_REG (r1
)) < FIRST_PSEUDO_REGISTER
))
2380 last
= XEXP (note
, 0);
2382 for (p
= NEXT_INSN (insn
); p
&& p
!= last
; p
= NEXT_INSN (p
))
2385 if (find_reg_note (p
, REG_DEAD
, r1
))
2388 /* There must be a REG_NO_CONFLICT note on every insn, otherwise
2389 some earlier optimization pass has inserted instructions into
2390 the sequence, and it is not safe to perform this optimization.
2391 Note that emit_no_conflict_block always ensures that this is
2392 true when these sequences are created. */
2393 if (! find_reg_note (p
, REG_NO_CONFLICT
, r1
))
2400 /* Return the number of alternatives for which the constraint string P
2401 indicates that the operand must be equal to operand 0 and that no register
2410 int reg_allowed
= 0;
2411 int num_matching_alts
= 0;
2416 case '=': case '+': case '?':
2417 case '#': case '&': case '!':
2419 case '1': case '2': case '3': case '4': case '5':
2420 case '6': case '7': case '8': case '9':
2421 case 'm': case '<': case '>': case 'V': case 'o':
2422 case 'E': case 'F': case 'G': case 'H':
2423 case 's': case 'i': case 'n':
2424 case 'I': case 'J': case 'K': case 'L':
2425 case 'M': case 'N': case 'O': case 'P':
2427 /* These don't say anything we care about. */
2431 if (found_zero
&& ! reg_allowed
)
2432 num_matching_alts
++;
2434 found_zero
= reg_allowed
= 0;
2442 if (REG_CLASS_FROM_LETTER (c
) == NO_REGS
)
2451 if (found_zero
&& ! reg_allowed
)
2452 num_matching_alts
++;
2454 return num_matching_alts
;
2458 dump_local_alloc (file
)
2462 for (i
= FIRST_PSEUDO_REGISTER
; i
< max_regno
; i
++)
2463 if (reg_renumber
[i
] != -1)
2464 fprintf (file
, ";; Register %d in %d.\n", i
, reg_renumber
[i
]);