1 /* Definitions for GCC. Part of the machine description for CRIS.
2 Copyright (C) 1998-2014 Free Software Foundation, Inc.
3 Contributed by Axis Communications. Written by Hans-Peter Nilsson.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
34 #include "stor-layout.h"
45 #include "diagnostic-core.h"
51 #include "tm-constrs.h"
53 #include "target-def.h"
55 #include "insn-codes.h"
57 #include "dominance.h"
63 #include "cfgcleanup.h"
65 #include "basic-block.h"
70 #include "plugin-api.h"
75 /* Usable when we have an amount to add or subtract, and want the
76 optimal size of the insn. */
77 #define ADDITIVE_SIZE_MODIFIER(size) \
78 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d")
80 #define LOSE_AND_RETURN(msgid, x) \
83 cris_operand_lossage (msgid, x); \
87 enum cris_retinsn_type
88 { CRIS_RETINSN_UNKNOWN
= 0, CRIS_RETINSN_RET
, CRIS_RETINSN_JUMP
};
90 /* Per-function machine data. */
91 struct GTY(()) machine_function
93 int needs_return_address_on_stack
;
95 /* This is the number of registers we save in the prologue due to
99 enum cris_retinsn_type return_type
;
102 /* This little fix suppresses the 'u' or 's' when '%e' in assembly
104 static char cris_output_insn_is_bound
= 0;
106 /* In code for output macros, this is how we know whether e.g. constant
107 goes in code or in a static initializer. */
108 static int in_code
= 0;
110 /* Fix for reg_overlap_mentioned_p. */
111 static int cris_reg_overlap_mentioned_p (rtx
, rtx
);
113 static machine_mode
cris_promote_function_mode (const_tree
, machine_mode
,
114 int *, const_tree
, int);
116 static unsigned int cris_atomic_align_for_mode (machine_mode
);
118 static void cris_print_base (rtx
, FILE *);
120 static void cris_print_index (rtx
, FILE *);
122 static void cris_output_addr_const (FILE *, rtx
);
124 static struct machine_function
* cris_init_machine_status (void);
126 static rtx
cris_struct_value_rtx (tree
, int);
128 static void cris_setup_incoming_varargs (cumulative_args_t
, machine_mode
,
129 tree type
, int *, int);
131 static int cris_initial_frame_pointer_offset (void);
133 static void cris_operand_lossage (const char *, rtx
);
135 static int cris_reg_saved_in_regsave_area (unsigned int, bool);
137 static void cris_print_operand (FILE *, rtx
, int);
139 static void cris_print_operand_address (FILE *, rtx
);
141 static bool cris_print_operand_punct_valid_p (unsigned char code
);
143 static bool cris_output_addr_const_extra (FILE *, rtx
);
145 static void cris_conditional_register_usage (void);
147 static void cris_asm_output_mi_thunk
148 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
150 static void cris_file_start (void);
151 static void cris_init_libfuncs (void);
153 static reg_class_t
cris_preferred_reload_class (rtx
, reg_class_t
);
155 static int cris_register_move_cost (machine_mode
, reg_class_t
, reg_class_t
);
156 static int cris_memory_move_cost (machine_mode
, reg_class_t
, bool);
157 static bool cris_rtx_costs (rtx
, int, int, int, int *, bool);
158 static int cris_address_cost (rtx
, machine_mode
, addr_space_t
, bool);
159 static bool cris_pass_by_reference (cumulative_args_t
, machine_mode
,
161 static int cris_arg_partial_bytes (cumulative_args_t
, machine_mode
,
163 static rtx
cris_function_arg (cumulative_args_t
, machine_mode
,
165 static rtx
cris_function_incoming_arg (cumulative_args_t
,
166 machine_mode
, const_tree
, bool);
167 static void cris_function_arg_advance (cumulative_args_t
, machine_mode
,
169 static tree
cris_md_asm_clobbers (tree
, tree
, tree
);
170 static bool cris_cannot_force_const_mem (machine_mode
, rtx
);
172 static void cris_option_override (void);
174 static bool cris_frame_pointer_required (void);
176 static void cris_asm_trampoline_template (FILE *);
177 static void cris_trampoline_init (rtx
, tree
, rtx
);
179 static rtx
cris_function_value(const_tree
, const_tree
, bool);
180 static rtx
cris_libcall_value (machine_mode
, const_rtx
);
181 static bool cris_function_value_regno_p (const unsigned int);
182 static void cris_file_end (void);
184 /* This is the parsed result of the "-max-stack-stackframe=" option. If
185 it (still) is zero, then there was no such option given. */
186 int cris_max_stackframe
= 0;
188 /* This is the parsed result of the "-march=" option, if given. */
189 int cris_cpu_version
= CRIS_DEFAULT_CPU_VERSION
;
191 #undef TARGET_ASM_ALIGNED_HI_OP
192 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
193 #undef TARGET_ASM_ALIGNED_SI_OP
194 #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t"
195 #undef TARGET_ASM_ALIGNED_DI_OP
196 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
198 /* We need to define these, since the 2byte, 4byte, 8byte op:s are only
199 available in ELF. These "normal" pseudos do not have any alignment
200 constraints or side-effects. */
201 #undef TARGET_ASM_UNALIGNED_HI_OP
202 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
204 #undef TARGET_ASM_UNALIGNED_SI_OP
205 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
207 #undef TARGET_ASM_UNALIGNED_DI_OP
208 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
210 #undef TARGET_PRINT_OPERAND
211 #define TARGET_PRINT_OPERAND cris_print_operand
212 #undef TARGET_PRINT_OPERAND_ADDRESS
213 #define TARGET_PRINT_OPERAND_ADDRESS cris_print_operand_address
214 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
215 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P cris_print_operand_punct_valid_p
216 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
217 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA cris_output_addr_const_extra
219 #undef TARGET_CONDITIONAL_REGISTER_USAGE
220 #define TARGET_CONDITIONAL_REGISTER_USAGE cris_conditional_register_usage
222 #undef TARGET_ASM_OUTPUT_MI_THUNK
223 #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk
224 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
225 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
227 #undef TARGET_ASM_FILE_START
228 #define TARGET_ASM_FILE_START cris_file_start
229 #undef TARGET_ASM_FILE_END
230 #define TARGET_ASM_FILE_END cris_file_end
232 #undef TARGET_INIT_LIBFUNCS
233 #define TARGET_INIT_LIBFUNCS cris_init_libfuncs
235 #undef TARGET_LEGITIMATE_ADDRESS_P
236 #define TARGET_LEGITIMATE_ADDRESS_P cris_legitimate_address_p
238 #undef TARGET_LEGITIMATE_CONSTANT_P
239 #define TARGET_LEGITIMATE_CONSTANT_P cris_legitimate_constant_p
241 #undef TARGET_PREFERRED_RELOAD_CLASS
242 #define TARGET_PREFERRED_RELOAD_CLASS cris_preferred_reload_class
244 #undef TARGET_REGISTER_MOVE_COST
245 #define TARGET_REGISTER_MOVE_COST cris_register_move_cost
246 #undef TARGET_MEMORY_MOVE_COST
247 #define TARGET_MEMORY_MOVE_COST cris_memory_move_cost
248 #undef TARGET_RTX_COSTS
249 #define TARGET_RTX_COSTS cris_rtx_costs
250 #undef TARGET_ADDRESS_COST
251 #define TARGET_ADDRESS_COST cris_address_cost
253 #undef TARGET_PROMOTE_FUNCTION_MODE
254 #define TARGET_PROMOTE_FUNCTION_MODE cris_promote_function_mode
256 #undef TARGET_ATOMIC_ALIGN_FOR_MODE
257 #define TARGET_ATOMIC_ALIGN_FOR_MODE cris_atomic_align_for_mode
259 #undef TARGET_STRUCT_VALUE_RTX
260 #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx
261 #undef TARGET_SETUP_INCOMING_VARARGS
262 #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs
263 #undef TARGET_PASS_BY_REFERENCE
264 #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference
265 #undef TARGET_ARG_PARTIAL_BYTES
266 #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes
267 #undef TARGET_FUNCTION_ARG
268 #define TARGET_FUNCTION_ARG cris_function_arg
269 #undef TARGET_FUNCTION_INCOMING_ARG
270 #define TARGET_FUNCTION_INCOMING_ARG cris_function_incoming_arg
271 #undef TARGET_FUNCTION_ARG_ADVANCE
272 #define TARGET_FUNCTION_ARG_ADVANCE cris_function_arg_advance
273 #undef TARGET_MD_ASM_CLOBBERS
274 #define TARGET_MD_ASM_CLOBBERS cris_md_asm_clobbers
276 #undef TARGET_CANNOT_FORCE_CONST_MEM
277 #define TARGET_CANNOT_FORCE_CONST_MEM cris_cannot_force_const_mem
279 #undef TARGET_FRAME_POINTER_REQUIRED
280 #define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required
282 #undef TARGET_OPTION_OVERRIDE
283 #define TARGET_OPTION_OVERRIDE cris_option_override
285 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
286 #define TARGET_ASM_TRAMPOLINE_TEMPLATE cris_asm_trampoline_template
287 #undef TARGET_TRAMPOLINE_INIT
288 #define TARGET_TRAMPOLINE_INIT cris_trampoline_init
290 #undef TARGET_FUNCTION_VALUE
291 #define TARGET_FUNCTION_VALUE cris_function_value
292 #undef TARGET_LIBCALL_VALUE
293 #define TARGET_LIBCALL_VALUE cris_libcall_value
294 #undef TARGET_FUNCTION_VALUE_REGNO_P
295 #define TARGET_FUNCTION_VALUE_REGNO_P cris_function_value_regno_p
297 struct gcc_target targetm
= TARGET_INITIALIZER
;
299 /* Helper for cris_load_multiple_op and cris_ret_movem_op. */
302 cris_movem_load_rest_p (rtx op
, int offs
)
304 unsigned int reg_count
= XVECLEN (op
, 0) - offs
;
310 unsigned int regno
= 0;
312 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
313 other than (MEM reg). */
315 || GET_CODE (XVECEXP (op
, 0, offs
)) != SET
316 || !REG_P (SET_DEST (XVECEXP (op
, 0, offs
)))
317 || !MEM_P (SET_SRC (XVECEXP (op
, 0, offs
))))
320 /* Check a possible post-inc indicator. */
321 if (GET_CODE (SET_SRC (XVECEXP (op
, 0, offs
+ 1))) == PLUS
)
323 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, offs
+ 1)), 0);
324 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, offs
+ 1)), 1);
330 || !REG_P (SET_DEST (XVECEXP (op
, 0, offs
+ 1)))
331 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, offs
+ 1)))
332 || !CONST_INT_P (inc
)
333 || INTVAL (inc
) != (HOST_WIDE_INT
) reg_count
* 4)
343 regno
= reg_count
- 1;
346 elt
= XVECEXP (op
, 0, offs
);
347 src_addr
= XEXP (SET_SRC (elt
), 0);
349 if (GET_CODE (elt
) != SET
350 || !REG_P (SET_DEST (elt
))
351 || GET_MODE (SET_DEST (elt
)) != SImode
352 || REGNO (SET_DEST (elt
)) != regno
353 || !MEM_P (SET_SRC (elt
))
354 || GET_MODE (SET_SRC (elt
)) != SImode
355 || !memory_address_p (SImode
, src_addr
))
358 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
360 rtx elt
= XVECEXP (op
, 0, i
);
363 if (GET_CODE (elt
) != SET
364 || !REG_P (SET_DEST (elt
))
365 || GET_MODE (SET_DEST (elt
)) != SImode
366 || REGNO (SET_DEST (elt
)) != regno
367 || !MEM_P (SET_SRC (elt
))
368 || GET_MODE (SET_SRC (elt
)) != SImode
369 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
370 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
371 || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt
), 0), 1))
372 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != setno
* 4)
379 /* Worker function for predicate for the parallel contents in a movem
383 cris_store_multiple_op_p (rtx op
)
385 int reg_count
= XVECLEN (op
, 0);
396 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
397 other than (MEM reg) and (MEM (PLUS reg const)). */
401 elt
= XVECEXP (op
, 0, 0);
403 if (GET_CODE (elt
) != SET
)
406 dest
= SET_DEST (elt
);
408 if (!REG_P (SET_SRC (elt
)) || !MEM_P (dest
))
411 dest_addr
= XEXP (dest
, 0);
413 /* Check a possible post-inc indicator. */
414 if (GET_CODE (SET_SRC (XVECEXP (op
, 0, 1))) == PLUS
)
416 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 0);
417 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 1);
423 || !REG_P (SET_DEST (XVECEXP (op
, 0, 1)))
424 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, 1)))
425 || !CONST_INT_P (inc
)
426 /* Support increment by number of registers, and by the offset
427 of the destination, if it has the form (MEM (PLUS reg
429 || !((REG_P (dest_addr
)
430 && REGNO (dest_addr
) == REGNO (reg
)
431 && INTVAL (inc
) == (HOST_WIDE_INT
) reg_count
* 4)
432 || (GET_CODE (dest_addr
) == PLUS
433 && REG_P (XEXP (dest_addr
, 0))
434 && REGNO (XEXP (dest_addr
, 0)) == REGNO (reg
)
435 && CONST_INT_P (XEXP (dest_addr
, 1))
436 && INTVAL (XEXP (dest_addr
, 1)) == INTVAL (inc
))))
447 regno
= reg_count
- 1;
450 if (GET_CODE (elt
) != SET
451 || !REG_P (SET_SRC (elt
))
452 || GET_MODE (SET_SRC (elt
)) != SImode
453 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
454 || !MEM_P (SET_DEST (elt
))
455 || GET_MODE (SET_DEST (elt
)) != SImode
)
458 if (REG_P (dest_addr
))
460 dest_base
= dest_addr
;
463 else if (GET_CODE (dest_addr
) == PLUS
464 && REG_P (XEXP (dest_addr
, 0))
465 && CONST_INT_P (XEXP (dest_addr
, 1)))
467 dest_base
= XEXP (dest_addr
, 0);
468 offset
= INTVAL (XEXP (dest_addr
, 1));
473 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
475 rtx elt
= XVECEXP (op
, 0, i
);
478 if (GET_CODE (elt
) != SET
479 || !REG_P (SET_SRC (elt
))
480 || GET_MODE (SET_SRC (elt
)) != SImode
481 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
482 || !MEM_P (SET_DEST (elt
))
483 || GET_MODE (SET_DEST (elt
)) != SImode
484 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
485 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_base
)
486 || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt
), 0), 1))
487 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != setno
* 4 + offset
)
494 /* The TARGET_CONDITIONAL_REGISTER_USAGE worker. */
497 cris_conditional_register_usage (void)
499 /* FIXME: This isn't nice. We should be able to use that register for
500 something else if the PIC table isn't needed. */
502 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
]
503 = call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
505 /* Allow use of ACR (PC in pre-V32) and tweak order. */
508 static const int reg_alloc_order_v32
[] = REG_ALLOC_ORDER_V32
;
511 fixed_regs
[CRIS_ACR_REGNUM
] = 0;
514 i
< sizeof (reg_alloc_order_v32
)/sizeof (reg_alloc_order_v32
[0]);
516 reg_alloc_order
[i
] = reg_alloc_order_v32
[i
];
519 if (TARGET_HAS_MUL_INSNS
)
520 fixed_regs
[CRIS_MOF_REGNUM
] = 0;
522 /* On early versions, we must use the 16-bit condition-code register,
523 which has another name. */
524 if (cris_cpu_version
< 8)
525 reg_names
[CRIS_CC0_REGNUM
] = "ccr";
528 /* Return crtl->uses_pic_offset_table. For use in cris.md,
529 since some generated files do not include function.h. */
532 cris_cfun_uses_pic_table (void)
534 return crtl
->uses_pic_offset_table
;
537 /* Worker function for TARGET_CANNOT_FORCE_CONST_MEM.
538 We can't put PIC addresses in the constant pool, not even the ones that
539 can be reached as pc-relative as we can't tell when or how to do that. */
542 cris_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
544 enum cris_symbol_type t
= cris_symbol_type_of (x
);
548 || t
== cris_got_symbol
549 || t
== cris_rel_symbol
;
552 /* Given an rtx, return the text string corresponding to the CODE of X.
553 Intended for use in the assembly language output section of a
559 cris_output_insn_is_bound
= 0;
560 switch (GET_CODE (x
))
571 /* This function is for retrieving a part of an instruction name for
572 an operator, for immediate output. If that ever happens for
573 MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure
575 internal_error ("MULT case in cris_op_str");
611 /* Used to control the sign/zero-extend character for the 'E' modifier.
613 cris_output_insn_is_bound
= 1;
618 return "Unknown operator";
623 /* Emit an error message when we're in an asm, and a fatal error for
624 "normal" insns. Formatted output isn't easily implemented, since we
625 use output_operand_lossage to output the actual message and handle the
626 categorization of the error. */
629 cris_operand_lossage (const char *msgid
, rtx op
)
632 output_operand_lossage ("%s", msgid
);
635 /* Print an index part of an address to file. */
638 cris_print_index (rtx index
, FILE *file
)
640 /* Make the index "additive" unless we'll output a negative number, in
641 which case the sign character is free (as in free beer). */
642 if (!CONST_INT_P (index
) || INTVAL (index
) >= 0)
646 fprintf (file
, "$%s.b", reg_names
[REGNO (index
)]);
647 else if (CRIS_CONSTANT_P (index
))
648 cris_output_addr_const (file
, index
);
649 else if (GET_CODE (index
) == MULT
)
651 fprintf (file
, "$%s.",
652 reg_names
[REGNO (XEXP (index
, 0))]);
654 putc (INTVAL (XEXP (index
, 1)) == 2 ? 'w' : 'd', file
);
656 else if (GET_CODE (index
) == SIGN_EXTEND
&& MEM_P (XEXP (index
, 0)))
658 rtx inner
= XEXP (index
, 0);
659 rtx inner_inner
= XEXP (inner
, 0);
661 if (GET_CODE (inner_inner
) == POST_INC
)
663 fprintf (file
, "[$%s+].",
664 reg_names
[REGNO (XEXP (inner_inner
, 0))]);
665 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
669 fprintf (file
, "[$%s].", reg_names
[REGNO (inner_inner
)]);
671 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
674 else if (MEM_P (index
))
676 rtx inner
= XEXP (index
, 0);
677 if (GET_CODE (inner
) == POST_INC
)
678 fprintf (file
, "[$%s+].d", reg_names
[REGNO (XEXP (inner
, 0))]);
680 fprintf (file
, "[$%s].d", reg_names
[REGNO (inner
)]);
683 cris_operand_lossage ("unexpected index-type in cris_print_index",
687 /* Print a base rtx of an address to file. */
690 cris_print_base (rtx base
, FILE *file
)
693 fprintf (file
, "$%s", reg_names
[REGNO (base
)]);
694 else if (GET_CODE (base
) == POST_INC
)
696 gcc_assert (REGNO (XEXP (base
, 0)) != CRIS_ACR_REGNUM
);
697 fprintf (file
, "$%s+", reg_names
[REGNO (XEXP (base
, 0))]);
700 cris_operand_lossage ("unexpected base-type in cris_print_base",
704 /* Usable as a guard in expressions. */
707 cris_fatal (char *arg
)
709 internal_error (arg
);
711 /* We'll never get here; this is just to appease compilers. */
715 /* Return nonzero if REGNO is an ordinary register that *needs* to be
716 saved together with other registers, possibly by a MOVEM instruction,
717 or is saved for target-independent reasons. There may be
718 target-dependent reasons to save the register anyway; this is just a
719 wrapper for a complicated conditional. */
722 cris_reg_saved_in_regsave_area (unsigned int regno
, bool got_really_used
)
725 (((df_regs_ever_live_p (regno
)
726 && !call_used_regs
[regno
])
727 || (regno
== PIC_OFFSET_TABLE_REGNUM
729 /* It is saved anyway, if there would be a gap. */
731 && df_regs_ever_live_p (regno
+ 1)
732 && !call_used_regs
[regno
+ 1]))))
733 && (regno
!= FRAME_POINTER_REGNUM
|| !frame_pointer_needed
)
734 && regno
!= CRIS_SRP_REGNUM
)
735 || (crtl
->calls_eh_return
736 && (regno
== EH_RETURN_DATA_REGNO (0)
737 || regno
== EH_RETURN_DATA_REGNO (1)
738 || regno
== EH_RETURN_DATA_REGNO (2)
739 || regno
== EH_RETURN_DATA_REGNO (3)));
742 /* The PRINT_OPERAND worker. */
745 cris_print_operand (FILE *file
, rtx x
, int code
)
749 /* Size-strings corresponding to MULT expressions. */
750 static const char *const mults
[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
752 /* New code entries should just be added to the switch below. If
753 handling is finished, just return. If handling was just a
754 modification of the operand, the modified operand should be put in
755 "operand", and then do a break to let default handling
756 (zero-modifier) output the operand. */
761 /* Print the unsigned supplied integer as if it were signed
762 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */
763 if (!satisfies_constraint_O (x
))
764 LOSE_AND_RETURN ("invalid operand for 'b' modifier", x
);
765 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
766 INTVAL (x
)| (INTVAL (x
) <= 255 ? ~255 : ~65535));
770 /* Print assembler code for operator. */
771 fprintf (file
, "%s", cris_op_str (operand
));
776 /* A movem modifier working on a parallel; output the register
780 if (GET_CODE (x
) != PARALLEL
)
781 LOSE_AND_RETURN ("invalid operand for 'o' modifier", x
);
783 /* The second item can be (set reg (plus reg const)) to denote a
786 = (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
788 : XVECLEN (x
, 0) - 1);
790 fprintf (file
, "$%s", reg_names
[regno
]);
796 /* A similar movem modifier; output the memory operand. */
799 if (GET_CODE (x
) != PARALLEL
)
800 LOSE_AND_RETURN ("invalid operand for 'O' modifier", x
);
802 /* The lowest mem operand is in the first item, but perhaps it
803 needs to be output as postincremented. */
804 addr
= MEM_P (SET_SRC (XVECEXP (x
, 0, 0)))
805 ? XEXP (SET_SRC (XVECEXP (x
, 0, 0)), 0)
806 : XEXP (SET_DEST (XVECEXP (x
, 0, 0)), 0);
808 /* The second item can be a (set reg (plus reg const)) to denote
810 if (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
)
812 /* It's a post-increment, if the address is a naked (reg). */
814 addr
= gen_rtx_POST_INC (SImode
, addr
);
817 /* Otherwise, it's a side-effect; RN=RN+M. */
818 fprintf (file
, "[$%s=$%s%s%d]",
819 reg_names
[REGNO (SET_DEST (XVECEXP (x
, 0, 1)))],
820 reg_names
[REGNO (XEXP (addr
, 0))],
821 INTVAL (XEXP (addr
, 1)) < 0 ? "" : "+",
822 (int) INTVAL (XEXP (addr
, 1)));
826 output_address (addr
);
831 /* Adjust a power of two to its log2. */
832 if (!CONST_INT_P (x
) || exact_log2 (INTVAL (x
)) < 0 )
833 LOSE_AND_RETURN ("invalid operand for 'p' modifier", x
);
834 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
838 /* For an integer, print 'b' or 'w' if <= 255 or <= 65535
839 respectively. This modifier also terminates the inhibiting
840 effects of the 'x' modifier. */
841 cris_output_insn_is_bound
= 0;
842 if (GET_MODE (x
) == VOIDmode
&& CONST_INT_P (x
))
846 if (INTVAL (x
) <= 255)
848 else if (INTVAL (x
) <= 65535)
858 /* For a non-integer, print the size of the operand. */
859 putc ((GET_MODE (x
) == SImode
|| GET_MODE (x
) == SFmode
)
860 ? 'd' : GET_MODE (x
) == HImode
? 'w'
861 : GET_MODE (x
) == QImode
? 'b'
862 /* If none of the above, emit an erroneous size letter. */
868 /* Const_int: print b for -127 <= x <= 255,
869 w for -32768 <= x <= 65535, else die. */
871 || INTVAL (x
) < -32768 || INTVAL (x
) > 65535)
872 LOSE_AND_RETURN ("invalid operand for 'z' modifier", x
);
873 putc (INTVAL (x
) >= -128 && INTVAL (x
) <= 255 ? 'b' : 'w', file
);
877 /* If this is a GOT-symbol, print the size-letter corresponding to
878 -fpic/-fPIC. For everything else, print "d". */
880 && GET_CODE (x
) == CONST
881 && GET_CODE (XEXP (x
, 0)) == UNSPEC
882 && XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_GOTREAD
)
887 /* Output a 'nop' if there's nothing for the delay slot.
888 This method stolen from the sparc files. */
889 if (dbr_sequence_length () == 0)
890 fputs ("\n\tnop", file
);
894 /* Output directive for alignment padded with "nop" insns.
895 Optimizing for size, it's plain 4-byte alignment, otherwise we
896 align the section to a cache-line (32 bytes) and skip at max 2
897 bytes, i.e. we skip if it's the last insn on a cache-line. The
898 latter is faster by a small amount (for two test-programs 99.6%
899 and 99.9%) and larger by a small amount (ditto 100.1% and
900 100.2%). This is supposed to be the simplest yet performance-
901 wise least intrusive way to make sure the immediately following
902 (supposed) muls/mulu insn isn't located at the end of a
906 ? ".p2alignw 2,0x050f\n\t"
907 : ".p2alignw 5,0x050f,2\n\t", file
);
911 /* The PIC register. */
913 internal_error ("invalid use of ':' modifier");
914 fprintf (file
, "$%s", reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
918 /* Print high (most significant) part of something. */
919 switch (GET_CODE (operand
))
922 /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode)
923 value is kept here, and so may be other than 0 or -1. */
924 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
925 INTVAL (operand_subword (operand
, 1, 0, DImode
)));
929 /* High part of a long long constant. */
930 if (GET_MODE (operand
) == VOIDmode
)
932 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_HIGH (x
));
936 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
939 /* Print reg + 1. Check that there's not an attempt to print
940 high-parts of registers like stack-pointer or higher, except
941 for SRP (where the "high part" is MOF). */
942 if (REGNO (operand
) > STACK_POINTER_REGNUM
- 2
943 && (REGNO (operand
) != CRIS_SRP_REGNUM
944 || CRIS_SRP_REGNUM
+ 1 != CRIS_MOF_REGNUM
945 || fixed_regs
[CRIS_MOF_REGNUM
] != 0))
946 LOSE_AND_RETURN ("bad register", operand
);
947 fprintf (file
, "$%s", reg_names
[REGNO (operand
) + 1]);
951 /* Adjust memory address to high part. */
953 rtx adj_mem
= operand
;
955 = GET_MODE_BITSIZE (GET_MODE (operand
)) / BITS_PER_UNIT
;
957 /* Adjust so we can use two SImode in DImode.
958 Calling adj_offsettable_operand will make sure it is an
959 offsettable address. Don't do this for a postincrement
960 though; it should remain as it was. */
961 if (GET_CODE (XEXP (adj_mem
, 0)) != POST_INC
)
963 = adjust_address (adj_mem
, GET_MODE (adj_mem
), size
/ 2);
965 output_address (XEXP (adj_mem
, 0));
970 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
974 /* Strip the MEM expression. */
975 operand
= XEXP (operand
, 0);
979 /* Like 'E', but ignore state set by 'x'. FIXME: Use code
980 iterators and attributes in cris.md to avoid the need for %x
981 and %E (and %e) and state passed between those modifiers. */
982 cris_output_insn_is_bound
= 0;
985 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
986 cris_output_insn_is_bound is nonzero. */
987 if (GET_CODE (operand
) != SIGN_EXTEND
988 && GET_CODE (operand
) != ZERO_EXTEND
989 && !CONST_INT_P (operand
))
990 LOSE_AND_RETURN ("invalid operand for 'e' modifier", x
);
992 if (cris_output_insn_is_bound
)
994 cris_output_insn_is_bound
= 0;
998 putc (GET_CODE (operand
) == SIGN_EXTEND
999 || (CONST_INT_P (operand
) && INTVAL (operand
) < 0)
1004 /* Print the size letter of the inner element. We can do it by
1005 calling ourselves with the 's' modifier. */
1006 if (GET_CODE (operand
) != SIGN_EXTEND
&& GET_CODE (operand
) != ZERO_EXTEND
)
1007 LOSE_AND_RETURN ("invalid operand for 'm' modifier", x
);
1008 cris_print_operand (file
, XEXP (operand
, 0), 's');
1012 /* Print the least significant part of operand. */
1013 if (GET_CODE (operand
) == CONST_DOUBLE
)
1015 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_LOW (x
));
1018 else if (HOST_BITS_PER_WIDE_INT
> 32 && CONST_INT_P (operand
))
1020 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
1021 INTVAL (x
) & ((unsigned int) 0x7fffffff * 2 + 1));
1024 /* Otherwise the least significant part equals the normal part,
1025 so handle it normally. */
1029 /* When emitting an add for the high part of a DImode constant, we
1030 want to use addq for 0 and adds.w for -1. */
1031 if (!CONST_INT_P (operand
))
1032 LOSE_AND_RETURN ("invalid operand for 'A' modifier", x
);
1033 fprintf (file
, INTVAL (operand
) < 0 ? "adds.w" : "addq");
1037 /* For const_int operands, print the additive mnemonic and the
1038 modified operand (byte-sized operands don't save anything):
1039 N=MIN_INT..-65536: add.d N
1040 -65535..-64: subu.w -N
1044 65536..MAX_INT: add.d N.
1045 (Emitted mnemonics are capitalized to simplify testing.)
1046 For anything else (N.B: only register is valid), print "add.d". */
1047 if (REG_P (operand
))
1049 fprintf (file
, "Add.d ");
1051 /* Deal with printing the operand by dropping through to the
1058 gcc_assert (CONST_INT_P (operand
));
1060 val
= INTVAL (operand
);
1061 if (!IN_RANGE (val
, -65535, 65535))
1062 fprintf (file
, "Add.d %d", val
);
1063 else if (val
<= -64)
1064 fprintf (file
, "Subu.w %d", -val
);
1066 fprintf (file
, "Subq %d", -val
);
1068 fprintf (file
, "Addq %d", val
);
1069 else if (val
<= 65535)
1070 fprintf (file
, "Addu.w %d", val
);
1076 /* If the operand is an integer -31..31, print "q" else ".d". */
1077 if (CONST_INT_P (operand
) && IN_RANGE (INTVAL (operand
), -31, 31))
1078 fprintf (file
, "q");
1080 fprintf (file
, ".d");
1084 /* If this is a GOT symbol, force it to be emitted as :GOT and
1085 :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16).
1086 Avoid making this too much of a special case. */
1087 if (flag_pic
== 1 && CRIS_CONSTANT_P (operand
))
1089 int flag_pic_save
= flag_pic
;
1092 cris_output_addr_const (file
, operand
);
1093 flag_pic
= flag_pic_save
;
1099 /* When emitting an sub for the high part of a DImode constant, we
1100 want to use subq for 0 and subs.w for -1. */
1101 if (!CONST_INT_P (operand
))
1102 LOSE_AND_RETURN ("invalid operand for 'D' modifier", x
);
1103 fprintf (file
, INTVAL (operand
) < 0 ? "subs.w" : "subq");
1107 /* Print the operand as the index-part of an address.
1108 Easiest way out is to use cris_print_index. */
1109 cris_print_index (operand
, file
);
1113 /* Print the size letter for an operand to a MULT, which must be a
1114 const_int with a suitable value. */
1115 if (!CONST_INT_P (operand
) || INTVAL (operand
) > 4)
1116 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x
);
1117 fprintf (file
, "%s", mults
[INTVAL (operand
)]);
1121 /* Print "u.w" if a GOT symbol and flag_pic == 1, else ".d". */
1123 && GET_CODE (operand
) == CONST
1124 && GET_CODE (XEXP (operand
, 0)) == UNSPEC
1125 && XINT (XEXP (operand
, 0), 1) == CRIS_UNSPEC_GOTREAD
)
1126 fprintf (file
, "u.w");
1128 fprintf (file
, ".d");
1132 /* No code, print as usual. */
1136 LOSE_AND_RETURN ("invalid operand modifier letter", x
);
1139 /* Print an operand as without a modifier letter. */
1140 switch (GET_CODE (operand
))
1143 if (REGNO (operand
) > 15
1144 && REGNO (operand
) != CRIS_MOF_REGNUM
1145 && REGNO (operand
) != CRIS_SRP_REGNUM
1146 && REGNO (operand
) != CRIS_CC0_REGNUM
)
1147 internal_error ("internal error: bad register: %d", REGNO (operand
));
1148 fprintf (file
, "$%s", reg_names
[REGNO (operand
)]);
1152 output_address (XEXP (operand
, 0));
1156 if (GET_MODE (operand
) == VOIDmode
)
1157 /* A long long constant. */
1158 output_addr_const (file
, operand
);
1161 /* Only single precision is allowed as plain operands the
1162 moment. FIXME: REAL_VALUE_FROM_CONST_DOUBLE isn't
1167 /* FIXME: Perhaps check overflow of the "single". */
1168 REAL_VALUE_FROM_CONST_DOUBLE (r
, operand
);
1169 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
1171 fprintf (file
, "0x%lx", l
);
1178 cris_output_addr_const (file
, operand
);
1184 /* For a (MULT (reg X) const_int) we output "rX.S". */
1185 int i
= CONST_INT_P (XEXP (operand
, 1))
1186 ? INTVAL (XEXP (operand
, 1)) : INTVAL (XEXP (operand
, 0));
1187 rtx reg
= CONST_INT_P (XEXP (operand
, 1))
1188 ? XEXP (operand
, 0) : XEXP (operand
, 1);
1191 || (!CONST_INT_P (XEXP (operand
, 0))
1192 && !CONST_INT_P (XEXP (operand
, 1))))
1193 LOSE_AND_RETURN ("unexpected multiplicative operand", x
);
1195 cris_print_base (reg
, file
);
1196 fprintf (file
, ".%c",
1197 i
== 0 || (i
== 1 && GET_CODE (operand
) == MULT
) ? 'b'
1199 : (i
== 2 && GET_CODE (operand
) == MULT
) || i
== 1 ? 'w'
1205 /* No need to handle all strange variants, let output_addr_const
1207 if (CRIS_CONSTANT_P (operand
))
1209 cris_output_addr_const (file
, operand
);
1213 LOSE_AND_RETURN ("unexpected operand", x
);
1218 cris_print_operand_punct_valid_p (unsigned char code
)
1220 return (code
== '#' || code
== '!' || code
== ':');
1223 /* The PRINT_OPERAND_ADDRESS worker. */
1226 cris_print_operand_address (FILE *file
, rtx x
)
1228 /* All these were inside MEM:s so output indirection characters. */
1231 if (CONSTANT_ADDRESS_P (x
))
1232 cris_output_addr_const (file
, x
);
1233 else if (cris_base_or_autoincr_p (x
, true))
1234 cris_print_base (x
, file
);
1235 else if (GET_CODE (x
) == PLUS
)
1241 if (cris_base_p (x1
, true))
1243 cris_print_base (x1
, file
);
1244 cris_print_index (x2
, file
);
1246 else if (cris_base_p (x2
, true))
1248 cris_print_base (x2
, file
);
1249 cris_print_index (x1
, file
);
1252 LOSE_AND_RETURN ("unrecognized address", x
);
1256 /* A DIP. Output more indirection characters. */
1258 cris_print_base (XEXP (x
, 0), file
);
1262 LOSE_AND_RETURN ("unrecognized address", x
);
1267 /* The RETURN_ADDR_RTX worker.
1268 We mark that the return address is used, either by EH or
1269 __builtin_return_address, for use by the function prologue and
1270 epilogue. FIXME: This isn't optimal; we just use the mark in the
1271 prologue and epilogue to say that the return address is to be stored
1272 in the stack frame. We could return SRP for leaf-functions and use the
1273 initial-value machinery. */
1276 cris_return_addr_rtx (int count
, rtx frameaddr ATTRIBUTE_UNUSED
)
1278 cfun
->machine
->needs_return_address_on_stack
= 1;
1280 /* The return-address is stored just above the saved frame-pointer (if
1281 present). Apparently we can't eliminate from the frame-pointer in
1282 that direction, so use the incoming args (maybe pretended) pointer. */
1284 ? gen_rtx_MEM (Pmode
, plus_constant (Pmode
, virtual_incoming_args_rtx
, -4))
1288 /* Accessor used in cris.md:return because cfun->machine isn't available
1292 cris_return_address_on_stack (void)
1294 return df_regs_ever_live_p (CRIS_SRP_REGNUM
)
1295 || cfun
->machine
->needs_return_address_on_stack
;
1298 /* Accessor used in cris.md:return because cfun->machine isn't available
1302 cris_return_address_on_stack_for_return (void)
1304 return cfun
->machine
->return_type
== CRIS_RETINSN_RET
? false
1305 : cris_return_address_on_stack ();
1308 /* This used to be the INITIAL_FRAME_POINTER_OFFSET worker; now only
1309 handles FP -> SP elimination offset. */
1312 cris_initial_frame_pointer_offset (void)
1316 /* Initial offset is 0 if we don't have a frame pointer. */
1318 bool got_really_used
= false;
1320 if (crtl
->uses_pic_offset_table
)
1322 push_topmost_sequence ();
1324 = reg_used_between_p (pic_offset_table_rtx
, get_insns (),
1326 pop_topmost_sequence ();
1329 /* And 4 for each register pushed. */
1330 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1331 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
1334 /* And then, last, we add the locals allocated. */
1335 offs
+= get_frame_size ();
1337 /* And more; the accumulated args size. */
1338 offs
+= crtl
->outgoing_args_size
;
1340 /* Then round it off, in case we use aligned stack. */
1341 if (TARGET_STACK_ALIGN
)
1342 offs
= TARGET_ALIGN_BY_32
? (offs
+ 3) & ~3 : (offs
+ 1) & ~1;
1347 /* The INITIAL_ELIMINATION_OFFSET worker.
1348 Calculate the difference between imaginary registers such as frame
1349 pointer and the stack pointer. Used to eliminate the frame pointer
1350 and imaginary arg pointer. */
1353 cris_initial_elimination_offset (int fromreg
, int toreg
)
1356 = cris_initial_frame_pointer_offset ();
1358 /* We should be able to use regs_ever_live and related prologue
1359 information here, or alpha should not as well. */
1360 bool return_address_on_stack
= cris_return_address_on_stack ();
1362 /* Here we act as if the frame-pointer were needed. */
1363 int ap_fp_offset
= 4 + (return_address_on_stack
? 4 : 0);
1365 if (fromreg
== ARG_POINTER_REGNUM
1366 && toreg
== FRAME_POINTER_REGNUM
)
1367 return ap_fp_offset
;
1369 /* Between the frame pointer and the stack are only "normal" stack
1370 variables and saved registers. */
1371 if (fromreg
== FRAME_POINTER_REGNUM
1372 && toreg
== STACK_POINTER_REGNUM
)
1373 return fp_sp_offset
;
1375 /* We need to balance out the frame pointer here. */
1376 if (fromreg
== ARG_POINTER_REGNUM
1377 && toreg
== STACK_POINTER_REGNUM
)
1378 return ap_fp_offset
+ fp_sp_offset
- 4;
1383 /* Nonzero if X is a hard reg that can be used as an index. */
1385 reg_ok_for_base_p (const_rtx x
, bool strict
)
1387 return ((! strict
&& ! HARD_REGISTER_P (x
))
1388 || REGNO_OK_FOR_BASE_P (REGNO (x
)));
1391 /* Nonzero if X is a hard reg that can be used as an index. */
1393 reg_ok_for_index_p (const_rtx x
, bool strict
)
1395 return reg_ok_for_base_p (x
, strict
);
1398 /* No symbol can be used as an index (or more correct, as a base) together
1399 with a register with PIC; the PIC register must be there. */
1402 cris_constant_index_p (const_rtx x
)
1404 return (CRIS_CONSTANT_P (x
) && (!flag_pic
|| cris_valid_pic_const (x
, true)));
1407 /* True if X is a valid base register. */
1410 cris_base_p (const_rtx x
, bool strict
)
1412 return (REG_P (x
) && reg_ok_for_base_p (x
, strict
));
1415 /* True if X is a valid index register. */
1418 cris_index_p (const_rtx x
, bool strict
)
1420 return (REG_P (x
) && reg_ok_for_index_p (x
, strict
));
1423 /* True if X is a valid base register with or without autoincrement. */
1426 cris_base_or_autoincr_p (const_rtx x
, bool strict
)
1428 return (cris_base_p (x
, strict
)
1429 || (GET_CODE (x
) == POST_INC
1430 && cris_base_p (XEXP (x
, 0), strict
)
1431 && REGNO (XEXP (x
, 0)) != CRIS_ACR_REGNUM
));
1434 /* True if X is a valid (register) index for BDAP, i.e. [Rs].S or [Rs+].S. */
1437 cris_bdap_index_p (const_rtx x
, bool strict
)
1440 && GET_MODE (x
) == SImode
1441 && cris_base_or_autoincr_p (XEXP (x
, 0), strict
))
1442 || (GET_CODE (x
) == SIGN_EXTEND
1443 && MEM_P (XEXP (x
, 0))
1444 && (GET_MODE (XEXP (x
, 0)) == HImode
1445 || GET_MODE (XEXP (x
, 0)) == QImode
)
1446 && cris_base_or_autoincr_p (XEXP (XEXP (x
, 0), 0), strict
)));
1449 /* True if X is a valid (register) index for BIAP, i.e. Rd.m. */
1452 cris_biap_index_p (const_rtx x
, bool strict
)
1454 return (cris_index_p (x
, strict
)
1455 || (GET_CODE (x
) == MULT
1456 && cris_index_p (XEXP (x
, 0), strict
)
1457 && cris_scale_int_operand (XEXP (x
, 1), VOIDmode
)));
1460 /* Worker function for TARGET_LEGITIMATE_ADDRESS_P.
1462 A PIC operand looks like a normal symbol here. At output we dress it
1463 in "[rPIC+symbol:GOT]" (global symbol) or "rPIC+symbol:GOTOFF" (local
1464 symbol) so we exclude all addressing modes where we can't replace a
1465 plain "symbol" with that. A global PIC symbol does not fit anywhere
1466 here (but is thankfully a general_operand in itself). A local PIC
1467 symbol is valid for the plain "symbol + offset" case. */
1470 cris_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
1474 if (cris_base_or_autoincr_p (x
, strict
))
1476 else if (TARGET_V32
)
1477 /* Nothing else is valid then. */
1479 else if (cris_constant_index_p (x
))
1482 else if (GET_CODE (x
) == PLUS
)
1487 if ((cris_base_p (x1
, strict
) && cris_constant_index_p (x2
))
1488 || (cris_base_p (x2
, strict
) && cris_constant_index_p (x1
))
1489 /* BDAP Rs[+], Rd. */
1490 || (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1491 && ((cris_base_p (x1
, strict
)
1492 && cris_bdap_index_p (x2
, strict
))
1493 || (cris_base_p (x2
, strict
)
1494 && cris_bdap_index_p (x1
, strict
))
1496 || (cris_base_p (x1
, strict
)
1497 && cris_biap_index_p (x2
, strict
))
1498 || (cris_base_p (x2
, strict
)
1499 && cris_biap_index_p (x1
, strict
)))))
1504 /* DIP (Rs). Reject [[reg+]] and [[reg]] for DImode (long long). */
1505 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1506 && cris_base_or_autoincr_p (XEXP (x
, 0), strict
))
1513 /* Worker function for TARGET_LEGITIMATE_CONSTANT_P. We have to handle
1514 PIC constants that aren't legitimized. FIXME: there used to be a
1515 guarantee that the target LEGITIMATE_CONSTANT_P didn't have to handle
1516 PIC constants, but no more (4.7 era); testcase: glibc init-first.c.
1517 While that may be seen as a bug, that guarantee seems a wart by design,
1518 so don't bother; fix the documentation instead. */
1521 cris_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1523 enum cris_symbol_type t
;
1526 return LEGITIMATE_PIC_OPERAND_P (x
);
1528 t
= cris_symbol_type_of (x
);
1532 || t
== cris_offsettable_symbol
1533 || t
== cris_unspec
;
1536 /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */
1539 cris_reload_address_legitimized (rtx x
,
1540 machine_mode mode ATTRIBUTE_UNUSED
,
1541 int opnum ATTRIBUTE_UNUSED
,
1543 int ind_levels ATTRIBUTE_UNUSED
)
1545 enum reload_type type
= (enum reload_type
) itype
;
1549 if (GET_CODE (x
) != PLUS
)
1557 op1p
= &XEXP (x
, 1);
1562 if (GET_CODE (op0
) == SIGN_EXTEND
&& MEM_P (XEXP (op0
, 0)))
1564 rtx op00
= XEXP (op0
, 0);
1565 rtx op000
= XEXP (op00
, 0);
1566 rtx
*op000p
= &XEXP (op00
, 0);
1568 if ((GET_MODE (op00
) == HImode
|| GET_MODE (op00
) == QImode
)
1570 || (GET_CODE (op000
) == POST_INC
&& REG_P (XEXP (op000
, 0)))))
1572 bool something_reloaded
= false;
1574 if (GET_CODE (op000
) == POST_INC
1575 && REG_P (XEXP (op000
, 0))
1576 && REGNO (XEXP (op000
, 0)) > CRIS_LAST_GENERAL_REGISTER
)
1577 /* No, this gets too complicated and is too rare to care
1578 about trying to improve on the general code Here.
1579 As the return-value is an all-or-nothing indicator, we
1580 punt on the other register too. */
1584 && REGNO (op000
) > CRIS_LAST_GENERAL_REGISTER
))
1586 /* The address of the inner mem is a pseudo or wrong
1587 reg: reload that. */
1588 push_reload (op000
, NULL_RTX
, op000p
, NULL
, GENERAL_REGS
,
1589 GET_MODE (x
), VOIDmode
, 0, 0, opnum
, type
);
1590 something_reloaded
= true;
1593 if (REGNO (op1
) > CRIS_LAST_GENERAL_REGISTER
)
1595 /* Base register is a pseudo or wrong reg: reload it. */
1596 push_reload (op1
, NULL_RTX
, op1p
, NULL
, GENERAL_REGS
,
1597 GET_MODE (x
), VOIDmode
, 0, 0,
1599 something_reloaded
= true;
1602 gcc_assert (something_reloaded
);
1612 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS.
1614 It seems like gcc (2.7.2 and 2.9x of 2000-03-22) may send "NO_REGS" as
1615 the class for a constant (testcase: __Mul in arit.c). To avoid forcing
1616 out a constant into the constant pool, we will trap this case and
1617 return something a bit more sane. FIXME: Check if this is a bug.
1618 Beware that we must not "override" classes that can be specified as
1619 constraint letters, or else asm operands using them will fail when
1620 they need to be reloaded. FIXME: Investigate whether that constitutes
1624 cris_preferred_reload_class (rtx x ATTRIBUTE_UNUSED
, reg_class_t rclass
)
1626 if (rclass
!= ACR_REGS
1627 && rclass
!= MOF_REGS
1628 && rclass
!= MOF_SRP_REGS
1629 && rclass
!= SRP_REGS
1630 && rclass
!= CC0_REGS
1631 && rclass
!= SPECIAL_REGS
)
1632 return GENERAL_REGS
;
1637 /* Worker function for TARGET_REGISTER_MOVE_COST. */
1640 cris_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
1641 reg_class_t from
, reg_class_t to
)
1643 /* Can't move to and from a SPECIAL_REGS register, so we have to say
1644 their move cost within that class is higher. How about 7? That's 3
1645 for a move to a GENERAL_REGS register, 3 for the move from the
1646 GENERAL_REGS register, and 1 for the increased register pressure.
1647 Also, it's higher than the memory move cost, as it should.
1648 We also do this for ALL_REGS, since we don't want that class to be
1649 preferred (even to memory) at all where GENERAL_REGS doesn't fit.
1650 Whenever it's about to be used, it's for SPECIAL_REGS. If we don't
1651 present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be
1652 used when a GENERAL_REGS should be used, even if there are call-saved
1653 GENERAL_REGS left to allocate. This is because the fall-back when
1654 the most preferred register class isn't available, isn't the next
1655 (or next good) wider register class, but the *most widest* register
1656 class. FIXME: pre-IRA comment, perhaps obsolete now. */
1658 if ((reg_classes_intersect_p (from
, SPECIAL_REGS
)
1659 && reg_classes_intersect_p (to
, SPECIAL_REGS
))
1660 || from
== ALL_REGS
|| to
== ALL_REGS
)
1663 /* Make moves to/from SPECIAL_REGS slightly more expensive, as we
1664 generally prefer GENERAL_REGS. */
1665 if (reg_classes_intersect_p (from
, SPECIAL_REGS
)
1666 || reg_classes_intersect_p (to
, SPECIAL_REGS
))
1672 /* Worker function for TARGET_MEMORY_MOVE_COST.
1674 This isn't strictly correct for v0..3 in buswidth-8bit mode, but should
1678 cris_memory_move_cost (machine_mode mode
,
1679 reg_class_t rclass ATTRIBUTE_UNUSED
,
1680 bool in ATTRIBUTE_UNUSED
)
1689 /* Worker for cris_notice_update_cc; handles the "normal" cases.
1690 FIXME: this code is historical; its functionality should be
1691 refactored to look at insn attributes and moved to
1692 cris_notice_update_cc. Except, we better lose cc0 entirely. */
1695 cris_normal_notice_update_cc (rtx exp
, rtx insn
)
1697 /* "Normal" means, for:
1702 CC is (reg) and (...) - unless (...) is 0 or reg is a special
1703 register or (v32 and (...) is -32..-1), then CC does not change.
1704 CC_NO_OVERFLOW unless (...) is reg or mem.
1713 (set (reg1) (mem (bdap/biap)))
1714 (set (reg2) (bdap/biap))):
1715 CC is (reg1) and (mem (reg2))
1718 (set (mem (bdap/biap)) (reg1)) [or 0]
1719 (set (reg2) (bdap/biap))):
1722 (where reg and mem includes strict_low_parts variants thereof)
1724 For all others, assume CC is clobbered.
1725 Note that we do not have to care about setting CC_NO_OVERFLOW,
1726 since the overflow flag is set to 0 (i.e. right) for
1727 instructions where it does not have any sane sense, but where
1728 other flags have meanings. (This includes shifts; the carry is
1731 Note that there are other parallel constructs we could match,
1732 but we don't do that yet. */
1734 if (GET_CODE (exp
) == SET
)
1736 /* FIXME: Check when this happens. It looks like we should
1737 actually do a CC_STATUS_INIT here to be safe. */
1738 if (SET_DEST (exp
) == pc_rtx
)
1741 /* Record CC0 changes, so we do not have to output multiple
1743 if (SET_DEST (exp
) == cc0_rtx
)
1747 if (GET_CODE (SET_SRC (exp
)) == COMPARE
1748 && XEXP (SET_SRC (exp
), 1) == const0_rtx
)
1749 cc_status
.value1
= XEXP (SET_SRC (exp
), 0);
1751 cc_status
.value1
= SET_SRC (exp
);
1753 /* Handle flags for the special btstq on one bit. */
1754 if (GET_CODE (cc_status
.value1
) == ZERO_EXTRACT
1755 && XEXP (cc_status
.value1
, 1) == const1_rtx
)
1757 if (CONST_INT_P (XEXP (cc_status
.value1
, 0)))
1759 cc_status
.flags
= CC_INVERTED
;
1761 /* A one-bit btstq. */
1762 cc_status
.flags
= CC_Z_IN_NOT_N
;
1765 else if (GET_CODE (SET_SRC (exp
)) == COMPARE
)
1767 if (!REG_P (XEXP (SET_SRC (exp
), 0))
1768 && XEXP (SET_SRC (exp
), 1) != const0_rtx
)
1769 /* For some reason gcc will not canonicalize compare
1770 operations, reversing the sign by itself if
1771 operands are in wrong order. */
1772 /* (But NOT inverted; eq is still eq.) */
1773 cc_status
.flags
= CC_REVERSED
;
1775 /* This seems to be overlooked by gcc. FIXME: Check again.
1776 FIXME: Is it really safe? */
1778 = gen_rtx_MINUS (GET_MODE (SET_SRC (exp
)),
1779 XEXP (SET_SRC (exp
), 0),
1780 XEXP (SET_SRC (exp
), 1));
1784 else if (REG_P (SET_DEST (exp
))
1785 || (GET_CODE (SET_DEST (exp
)) == STRICT_LOW_PART
1786 && REG_P (XEXP (SET_DEST (exp
), 0))))
1788 /* A register is set; normally CC is set to show that no
1789 test insn is needed. Catch the exceptions. */
1791 /* If not to cc0, then no "set"s in non-natural mode give
1793 if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp
))) > UNITS_PER_WORD
1794 || GET_MODE_CLASS (GET_MODE (SET_DEST (exp
))) == MODE_FLOAT
)
1796 /* ... except add:s and sub:s in DImode. */
1797 if (GET_MODE (SET_DEST (exp
)) == DImode
1798 && (GET_CODE (SET_SRC (exp
)) == PLUS
1799 || GET_CODE (SET_SRC (exp
)) == MINUS
))
1802 cc_status
.value1
= SET_DEST (exp
);
1803 cc_status
.value2
= SET_SRC (exp
);
1805 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1807 cc_status
.value2
= 0;
1809 /* Add and sub may set V, which gets us
1810 unoptimizable results in "gt" and "le" condition
1812 cc_status
.flags
|= CC_NO_OVERFLOW
;
1817 else if (SET_SRC (exp
) == const0_rtx
1818 || (REG_P (SET_SRC (exp
))
1819 && (REGNO (SET_SRC (exp
))
1820 > CRIS_LAST_GENERAL_REGISTER
))
1822 && REG_P (SET_DEST (exp
))
1823 && satisfies_constraint_I (SET_SRC (exp
))))
1825 /* There's no CC0 change for this case. Just check
1827 if (cc_status
.value1
1828 && modified_in_p (cc_status
.value1
, insn
))
1829 cc_status
.value1
= 0;
1831 if (cc_status
.value2
1832 && modified_in_p (cc_status
.value2
, insn
))
1833 cc_status
.value2
= 0;
1840 cc_status
.value1
= SET_DEST (exp
);
1841 cc_status
.value2
= SET_SRC (exp
);
1843 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1845 cc_status
.value2
= 0;
1847 /* Some operations may set V, which gets us
1848 unoptimizable results in "gt" and "le" condition
1850 if (GET_CODE (SET_SRC (exp
)) == PLUS
1851 || GET_CODE (SET_SRC (exp
)) == MINUS
1852 || GET_CODE (SET_SRC (exp
)) == NEG
)
1853 cc_status
.flags
|= CC_NO_OVERFLOW
;
1855 /* For V32, nothing with a register destination sets
1856 C and V usefully. */
1858 cc_status
.flags
|= CC_NO_OVERFLOW
;
1863 else if (MEM_P (SET_DEST (exp
))
1864 || (GET_CODE (SET_DEST (exp
)) == STRICT_LOW_PART
1865 && MEM_P (XEXP (SET_DEST (exp
), 0))))
1867 /* When SET to MEM, then CC is not changed (except for
1869 if (cc_status
.value1
1870 && modified_in_p (cc_status
.value1
, insn
))
1871 cc_status
.value1
= 0;
1873 if (cc_status
.value2
1874 && modified_in_p (cc_status
.value2
, insn
))
1875 cc_status
.value2
= 0;
1880 else if (GET_CODE (exp
) == PARALLEL
)
1882 if (GET_CODE (XVECEXP (exp
, 0, 0)) == SET
1883 && GET_CODE (XVECEXP (exp
, 0, 1)) == SET
1884 && REG_P (XEXP (XVECEXP (exp
, 0, 1), 0)))
1886 if (REG_P (XEXP (XVECEXP (exp
, 0, 0), 0))
1887 && MEM_P (XEXP (XVECEXP (exp
, 0, 0), 1)))
1891 /* For "move.S [rx=ry+o],rz", say CC reflects
1892 value1=rz and value2=[rx] */
1893 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
1895 = replace_equiv_address (XEXP (XVECEXP (exp
, 0, 0), 1),
1896 XEXP (XVECEXP (exp
, 0, 1), 0));
1898 /* Huh? A side-effect cannot change the destination
1900 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1902 internal_error ("internal error: sideeffect-insn affecting main effect");
1904 /* For V32, moves to registers don't set C and V. */
1906 cc_status
.flags
|= CC_NO_OVERFLOW
;
1909 else if ((REG_P (XEXP (XVECEXP (exp
, 0, 0), 1))
1910 || XEXP (XVECEXP (exp
, 0, 0), 1) == const0_rtx
)
1911 && MEM_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
1913 /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]",
1914 say flags are not changed, except for overlap. */
1915 if (cc_status
.value1
1916 && modified_in_p (cc_status
.value1
, insn
))
1917 cc_status
.value1
= 0;
1919 if (cc_status
.value2
1920 && modified_in_p (cc_status
.value2
, insn
))
1921 cc_status
.value2
= 0;
1928 /* If we got here, the case wasn't covered by the code above. */
1932 /* This function looks into the pattern to see how this insn affects
1935 Used when to eliminate test insns before a condition-code user,
1936 such as a "scc" insn or a conditional branch. This includes
1937 checking if the entities that cc was updated by, are changed by the
1940 Currently a jumble of the old peek-inside-the-insn and the newer
1941 check-cc-attribute methods. */
1944 cris_notice_update_cc (rtx exp
, rtx_insn
*insn
)
1946 enum attr_cc attrval
= get_attr_cc (insn
);
1948 /* Check if user specified "-mcc-init" as a bug-workaround. Remember
1949 to still set CC_REVERSED as below, since that's required by some
1950 compare insn alternatives. (FIXME: GCC should do this virtual
1951 operand swap by itself.) A test-case that may otherwise fail is
1952 gcc.c-torture/execute/20000217-1.c -O0 and -O1. */
1957 if (attrval
== CC_REV
)
1958 cc_status
.flags
= CC_REVERSED
;
1962 /* Slowly, we're converting to using attributes to control the setting
1963 of condition-code status. */
1967 /* Even if it is "none", a setting may clobber a previous
1968 cc-value, so check. */
1969 if (GET_CODE (exp
) == SET
)
1971 if (cc_status
.value1
1972 && modified_in_p (cc_status
.value1
, insn
))
1973 cc_status
.value1
= 0;
1975 if (cc_status
.value2
1976 && modified_in_p (cc_status
.value2
, insn
))
1977 cc_status
.value2
= 0;
1988 cris_normal_notice_update_cc (exp
, insn
);
1990 /* The "test" insn doesn't clear (carry and) overflow on V32. We
1991 can change bge => bpl and blt => bmi by passing on to the cc0
1992 user that V should not be considered; bgt and ble are taken
1993 care of by other methods (see {tst,cmp}{si,hi,qi}). */
1994 if (attrval
== CC_NOOV32
&& TARGET_V32
)
1995 cc_status
.flags
|= CC_NO_OVERFLOW
;
1999 internal_error ("unknown cc_attr value");
2005 /* Return != 0 if the return sequence for the current function is short,
2006 like "ret" or "jump [sp+]". Prior to reloading, we can't tell if
2007 registers must be saved, so return 0 then. */
2010 cris_simple_epilogue (void)
2013 unsigned int reglimit
= STACK_POINTER_REGNUM
;
2014 bool got_really_used
= false;
2016 if (! reload_completed
2017 || frame_pointer_needed
2018 || get_frame_size () != 0
2019 || crtl
->args
.pretend_args_size
2021 || crtl
->outgoing_args_size
2022 || crtl
->calls_eh_return
2024 /* If we're not supposed to emit prologue and epilogue, we must
2025 not emit return-type instructions. */
2026 || !TARGET_PROLOGUE_EPILOGUE
)
2029 /* Can't return from stacked return address with v32. */
2030 if (TARGET_V32
&& cris_return_address_on_stack ())
2033 if (crtl
->uses_pic_offset_table
)
2035 push_topmost_sequence ();
2037 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL
);
2038 pop_topmost_sequence ();
2041 /* No simple epilogue if there are saved registers. */
2042 for (regno
= 0; regno
< reglimit
; regno
++)
2043 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
2049 /* Emit checking that MEM is aligned for an access in MODE, failing
2050 that, executing a "break 8" (or call to abort, if "break 8" is
2054 cris_emit_trap_for_misalignment (rtx mem
)
2056 rtx addr
, reg
, ok_label
, andop
;
2058 int natural_alignment
;
2059 gcc_assert (MEM_P (mem
));
2061 natural_alignment
= GET_MODE_SIZE (GET_MODE (mem
));
2062 addr
= XEXP (mem
, 0);
2063 reg
= force_reg (Pmode
, addr
);
2064 ok_label
= gen_label_rtx ();
2066 /* This will yield a btstq without a separate register used, usually -
2067 with the exception for PRE hoisting the "and" but not the branch
2068 around the trap: see testsuite/gcc.target/cris/sync-3s.c. */
2069 andop
= gen_rtx_AND (Pmode
, reg
, GEN_INT (natural_alignment
- 1));
2070 emit_cmp_and_jump_insns (force_reg (SImode
, andop
), const0_rtx
, EQ
,
2071 NULL_RTX
, Pmode
, 1, ok_label
);
2072 jmp
= get_last_insn ();
2073 gcc_assert (JUMP_P (jmp
));
2075 predict_insn_def (jmp
, PRED_NORETURN
, TAKEN
);
2076 expand_builtin_trap ();
2077 emit_label (ok_label
);
2080 /* Expand a return insn (just one insn) marked as using SRP or stack
2081 slot depending on parameter ON_STACK. */
2084 cris_expand_return (bool on_stack
)
2086 /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to
2087 tell "ret" from "jump [sp+]". Some, but not all, other parts of
2088 GCC expect just (return) to do the right thing when optimizing, so
2089 we do that until they're fixed. Currently, all return insns in a
2090 function must be the same (not really a limiting factor) so we need
2091 to check that it doesn't change half-way through. */
2092 emit_jump_insn (ret_rtx
);
2094 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_RET
|| !on_stack
);
2095 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_JUMP
|| on_stack
);
2097 cfun
->machine
->return_type
2098 = on_stack
? CRIS_RETINSN_JUMP
: CRIS_RETINSN_RET
;
2101 /* Compute a (partial) cost for rtx X. Return true if the complete
2102 cost has been computed, and false if subexpressions should be
2103 scanned. In either case, *TOTAL contains the cost result. */
2106 cris_rtx_costs (rtx x
, int code
, int outer_code
, int opno
, int *total
,
2113 HOST_WIDE_INT val
= INTVAL (x
);
2116 else if (val
< 32 && val
>= -32)
2118 /* Eight or 16 bits are a word and cycle more expensive. */
2119 else if (val
<= 32767 && val
>= -32768)
2121 /* A 32-bit constant (or very seldom, unsigned 16 bits) costs
2122 another word. FIXME: This isn't linear to 16 bits. */
2138 if (x
!= CONST0_RTX (GET_MODE (x
) == VOIDmode
? DImode
: GET_MODE (x
)))
2141 /* Make 0.0 cheap, else test-insns will not be used. */
2146 /* If we have one arm of an ADDI, make sure it gets the cost of
2147 one insn, i.e. zero cost for this operand, and just the cost
2148 of the PLUS, as the insn is created by combine from a PLUS
2149 and an ASHIFT, and the MULT cost below would make the
2150 combined value be larger than the separate insns. The insn
2151 validity is checked elsewhere by combine.
2153 FIXME: this case is a stop-gap for 4.3 and 4.4, this whole
2154 function should be rewritten. */
2155 if (outer_code
== PLUS
&& cris_biap_index_p (x
, false))
2161 /* Identify values that are no powers of two. Powers of 2 are
2162 taken care of already and those values should not be changed. */
2163 if (!CONST_INT_P (XEXP (x
, 1))
2164 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
2166 /* If we have a multiply insn, then the cost is between
2167 1 and 2 "fast" instructions. */
2168 if (TARGET_HAS_MUL_INSNS
)
2170 *total
= COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2;
2174 /* Estimate as 4 + 4 * #ofbits. */
2175 *total
= COSTS_N_INSNS (132);
2184 if (!CONST_INT_P (XEXP (x
, 1))
2185 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
2187 /* Estimate this as 4 + 8 * #of bits. */
2188 *total
= COSTS_N_INSNS (260);
2194 if (CONST_INT_P (XEXP (x
, 1))
2195 /* Two constants may actually happen before optimization. */
2196 && !CONST_INT_P (XEXP (x
, 0))
2197 && !satisfies_constraint_I (XEXP (x
, 1)))
2200 = (rtx_cost (XEXP (x
, 0), (enum rtx_code
) outer_code
,
2202 + 2 * GET_MODE_NUNITS (GET_MODE (XEXP (x
, 0))));
2208 if (outer_code
!= COMPARE
)
2212 case ZERO_EXTEND
: case SIGN_EXTEND
:
2213 *total
= rtx_cost (XEXP (x
, 0), (enum rtx_code
) outer_code
, opno
, speed
);
2221 /* The ADDRESS_COST worker. */
2224 cris_address_cost (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
,
2225 addr_space_t as ATTRIBUTE_UNUSED
,
2226 bool speed ATTRIBUTE_UNUSED
)
2228 /* The metric to use for the cost-macros is unclear.
2229 The metric used here is (the number of cycles needed) / 2,
2230 where we consider equal a cycle for a word of code and a cycle to
2231 read memory. FIXME: Adding "+ 1" to all values would avoid
2232 returning 0, as tree-ssa-loop-ivopts.c as of r128272 "normalizes"
2233 0 to 1, thereby giving equal costs to [rN + rM] and [rN].
2234 Unfortunately(?) such a hack would expose other pessimizations,
2235 at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the
2236 loop there, without apparent reason. */
2238 /* The cheapest addressing modes get 0, since nothing extra is needed. */
2239 if (cris_base_or_autoincr_p (x
, false))
2242 /* An indirect mem must be a DIP. This means two bytes extra for code,
2243 and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */
2247 /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs
2248 an extra DIP prefix and 4 bytes of constant in most cases. */
2252 /* Handle BIAP and BDAP prefixes. */
2253 if (GET_CODE (x
) == PLUS
)
2255 rtx tem1
= XEXP (x
, 0);
2256 rtx tem2
= XEXP (x
, 1);
2258 /* Local extended canonicalization rule: the first operand must
2259 be REG, unless it's an operation (MULT). */
2260 if (!REG_P (tem1
) && GET_CODE (tem1
) != MULT
)
2261 tem1
= tem2
, tem2
= XEXP (x
, 0);
2263 /* We'll "assume" we have canonical RTX now. */
2264 gcc_assert (REG_P (tem1
) || GET_CODE (tem1
) == MULT
);
2266 /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We
2267 recognize the typical MULT which is always in tem1 because of
2268 insn canonicalization. */
2269 if ((GET_CODE (tem1
) == MULT
&& cris_biap_index_p (tem1
, false))
2273 /* A BDAP (quick) is 2 extra bytes. Any constant operand to the
2274 PLUS is always found in tem2. */
2275 if (CONST_INT_P (tem2
) && INTVAL (tem2
) < 128 && INTVAL (tem2
) >= -128)
2278 /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra
2280 if (satisfies_constraint_L (tem2
))
2283 /* A BDAP with some other constant is 2 bytes extra. */
2284 if (CRIS_CONSTANT_P (tem2
))
2285 return (2 + 2 + 2) / 2;
2287 /* BDAP with something indirect should have a higher cost than
2288 BIAP with register. FIXME: Should it cost like a MEM or more? */
2289 return (2 + 2 + 2) / 2;
2292 /* What else? Return a high cost. It matters only for valid
2293 addressing modes. */
2297 /* Check various objections to the side-effect. Used in the test-part
2298 of an anonymous insn describing an insn with a possible side-effect.
2299 Returns nonzero if the implied side-effect is ok.
2302 ops : An array of rtx:es. lreg, rreg, rval,
2303 The variables multop and other_op are indexes into this,
2304 or -1 if they are not applicable.
2305 lreg : The register that gets assigned in the side-effect.
2306 rreg : One register in the side-effect expression
2307 rval : The other register, or an int.
2308 multop : An integer to multiply rval with.
2309 other_op : One of the entities of the main effect,
2310 whose mode we must consider. */
2313 cris_side_effect_mode_ok (enum rtx_code code
, rtx
*ops
,
2314 int lreg
, int rreg
, int rval
,
2315 int multop
, int other_op
)
2317 /* Find what value to multiply with, for rx =ry + rz * n. */
2318 int mult
= multop
< 0 ? 1 : INTVAL (ops
[multop
]);
2320 rtx reg_rtx
= ops
[rreg
];
2321 rtx val_rtx
= ops
[rval
];
2323 /* The operands may be swapped. Canonicalize them in reg_rtx and
2324 val_rtx, where reg_rtx always is a reg (for this constraint to
2326 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2327 reg_rtx
= val_rtx
, val_rtx
= ops
[rreg
];
2329 /* Don't forget to check that reg_rtx really is a reg. If it isn't,
2330 we have no business. */
2331 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2334 /* Don't do this when -mno-split. */
2335 if (!TARGET_SIDE_EFFECT_PREFIXES
)
2338 /* The mult expression may be hidden in lreg. FIXME: Add more
2339 commentary about that. */
2340 if (GET_CODE (val_rtx
) == MULT
)
2342 mult
= INTVAL (XEXP (val_rtx
, 1));
2343 val_rtx
= XEXP (val_rtx
, 0);
2347 /* First check the "other operand". */
2350 if (GET_MODE_SIZE (GET_MODE (ops
[other_op
])) > UNITS_PER_WORD
)
2353 /* Check if the lvalue register is the same as the "other
2354 operand". If so, the result is undefined and we shouldn't do
2355 this. FIXME: Check again. */
2356 if ((cris_base_p (ops
[lreg
], reload_in_progress
|| reload_completed
)
2357 && cris_base_p (ops
[other_op
],
2358 reload_in_progress
|| reload_completed
)
2359 && REGNO (ops
[lreg
]) == REGNO (ops
[other_op
]))
2360 || rtx_equal_p (ops
[other_op
], ops
[lreg
]))
2364 /* Do not accept frame_pointer_rtx as any operand. */
2365 if (ops
[lreg
] == frame_pointer_rtx
|| ops
[rreg
] == frame_pointer_rtx
2366 || ops
[rval
] == frame_pointer_rtx
2367 || (other_op
>= 0 && ops
[other_op
] == frame_pointer_rtx
))
2371 && ! cris_base_p (val_rtx
, reload_in_progress
|| reload_completed
))
2374 /* Do not allow rx = rx + n if a normal add or sub with same size
2376 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2377 && CONST_INT_P (val_rtx
)
2378 && (INTVAL (val_rtx
) <= 63 && INTVAL (val_rtx
) >= -63))
2381 /* Check allowed cases, like [r(+)?].[bwd] and const. */
2382 if (CRIS_CONSTANT_P (val_rtx
))
2386 && cris_base_or_autoincr_p (XEXP (val_rtx
, 0),
2387 reload_in_progress
|| reload_completed
))
2390 if (GET_CODE (val_rtx
) == SIGN_EXTEND
2391 && MEM_P (XEXP (val_rtx
, 0))
2392 && cris_base_or_autoincr_p (XEXP (XEXP (val_rtx
, 0), 0),
2393 reload_in_progress
|| reload_completed
))
2396 /* If we got here, it's not a valid addressing mode. */
2399 else if (code
== MULT
2401 && cris_base_p (val_rtx
,
2402 reload_in_progress
|| reload_completed
)))
2404 /* Do not allow rx = rx + ry.S, since it doesn't give better code. */
2405 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2406 || (mult
== 1 && rtx_equal_p (ops
[lreg
], val_rtx
)))
2409 /* Do not allow bad multiply-values. */
2410 if (mult
!= 1 && mult
!= 2 && mult
!= 4)
2413 /* Only allow r + ... */
2414 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2417 /* If we got here, all seems ok.
2418 (All checks need to be done above). */
2422 /* If we get here, the caller got its initial tests wrong. */
2423 internal_error ("internal error: cris_side_effect_mode_ok with bad operands");
2426 /* Whether next_cc0_user of insn is LE or GT or requires a real compare
2427 insn for other reasons. */
2430 cris_cc0_user_requires_cmp (rtx insn
)
2432 rtx_insn
*cc0_user
= NULL
;
2436 gcc_assert (insn
!= NULL
);
2441 cc0_user
= next_cc0_user (insn
);
2442 if (cc0_user
== NULL
)
2445 body
= PATTERN (cc0_user
);
2446 set
= single_set (cc0_user
);
2448 /* Users can be sCC and bCC. */
2449 if (JUMP_P (cc0_user
)
2450 && GET_CODE (body
) == SET
2451 && SET_DEST (body
) == pc_rtx
2452 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
2453 && XEXP (XEXP (SET_SRC (body
), 0), 0) == cc0_rtx
)
2456 GET_CODE (XEXP (SET_SRC (body
), 0)) == GT
2457 || GET_CODE (XEXP (SET_SRC (body
), 0)) == LE
;
2462 GET_CODE (SET_SRC (body
)) == GT
2463 || GET_CODE (SET_SRC (body
)) == LE
;
2469 /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16)
2470 does not handle the case where the IN operand is strict_low_part; it
2471 does handle it for X. Test-case in Axis-20010516. This function takes
2472 care of that for THIS port. FIXME: strict_low_part is going away
2476 cris_reg_overlap_mentioned_p (rtx x
, rtx in
)
2478 /* The function reg_overlap_mentioned now handles when X is
2479 strict_low_part, but not when IN is a STRICT_LOW_PART. */
2480 if (GET_CODE (in
) == STRICT_LOW_PART
)
2483 return reg_overlap_mentioned_p (x
, in
);
2486 /* Return TRUE iff X is a CONST valid for e.g. indexing.
2487 ANY_OPERAND is 0 if X is in a CALL_P insn or movsi, 1
2491 cris_valid_pic_const (const_rtx x
, bool any_operand
)
2493 gcc_assert (flag_pic
);
2495 switch (GET_CODE (x
))
2504 if (GET_CODE (x
) != CONST
)
2509 /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */
2510 if (GET_CODE (x
) == PLUS
2511 && GET_CODE (XEXP (x
, 0)) == UNSPEC
2512 && (XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_GOTREL
2513 || XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_PCREL
)
2514 && CONST_INT_P (XEXP (x
, 1)))
2517 if (GET_CODE (x
) == UNSPEC
)
2518 switch (XINT (x
, 1))
2520 /* A PCREL operand is only valid for call and movsi. */
2521 case CRIS_UNSPEC_PLT_PCREL
:
2522 case CRIS_UNSPEC_PCREL
:
2523 return !any_operand
;
2525 case CRIS_UNSPEC_PLT_GOTREL
:
2526 case CRIS_UNSPEC_PLTGOTREAD
:
2527 case CRIS_UNSPEC_GOTREAD
:
2528 case CRIS_UNSPEC_GOTREL
:
2534 return cris_symbol_type_of (x
) == cris_no_symbol
;
2537 /* Helper function to find the right symbol-type to generate,
2538 given the original (non-PIC) representation. */
2540 enum cris_symbol_type
2541 cris_symbol_type_of (const_rtx x
)
2543 switch (GET_CODE (x
))
2547 ? (SYMBOL_REF_LOCAL_P (x
)
2548 ? cris_rel_symbol
: cris_got_symbol
)
2549 : cris_offsettable_symbol
;
2552 return flag_pic
? cris_rel_symbol
: cris_offsettable_symbol
;
2555 return cris_symbol_type_of (XEXP (x
, 0));
2560 enum cris_symbol_type t1
= cris_symbol_type_of (XEXP (x
, 0));
2561 enum cris_symbol_type t2
= cris_symbol_type_of (XEXP (x
, 1));
2563 gcc_assert (t1
== cris_no_symbol
|| t2
== cris_no_symbol
);
2565 if (t1
== cris_got_symbol
|| t2
== cris_got_symbol
)
2566 return cris_got_symbol_needing_fixup
;
2568 return t1
!= cris_no_symbol
? t1
: t2
;
2573 return cris_no_symbol
;
2579 fatal_insn ("unrecognized supposed constant", x
);
2585 /* The LEGITIMATE_PIC_OPERAND_P worker. */
2588 cris_legitimate_pic_operand (rtx x
)
2590 /* Symbols are not valid PIC operands as-is; just constants. */
2591 return cris_valid_pic_const (x
, true);
2594 /* Queue an .ident string in the queue of top-level asm statements.
2595 If the front-end is done, we must be being called from toplev.c.
2596 In that case, do nothing. */
2598 cris_asm_output_ident (const char *string
)
2600 if (symtab
->state
!= PARSING
)
2603 default_asm_output_ident_directive (string
);
2606 /* The ASM_OUTPUT_CASE_END worker. */
2609 cris_asm_output_case_end (FILE *stream
, int num
, rtx table
)
2611 /* Step back, over the label for the table, to the actual casejump and
2612 assert that we find only what's expected. */
2613 rtx whole_jump_insn
= prev_nonnote_nondebug_insn (table
);
2614 gcc_assert (whole_jump_insn
!= NULL_RTX
&& LABEL_P (whole_jump_insn
));
2615 whole_jump_insn
= prev_nonnote_nondebug_insn (whole_jump_insn
);
2616 gcc_assert (whole_jump_insn
!= NULL_RTX
2617 && (JUMP_P (whole_jump_insn
)
2618 || (TARGET_V32
&& INSN_P (whole_jump_insn
)
2619 && GET_CODE (PATTERN (whole_jump_insn
)) == SEQUENCE
)));
2620 /* Get the pattern of the casejump, so we can extract the default label. */
2621 whole_jump_insn
= PATTERN (whole_jump_insn
);
2625 /* This can be a SEQUENCE, meaning the delay-slot of the jump is
2626 filled. We also output the offset word a little differently. */
2628 = (GET_CODE (whole_jump_insn
) == SEQUENCE
2629 ? PATTERN (XVECEXP (whole_jump_insn
, 0, 0)) : whole_jump_insn
);
2631 asm_fprintf (stream
,
2632 "\t.word %LL%d-.%s\n",
2633 CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (XVECEXP
2634 (parallel_jump
, 0, 0),
2636 (TARGET_PDEBUG
? "; default" : ""));
2640 asm_fprintf (stream
,
2641 "\t.word %LL%d-%LL%d%s\n",
2642 CODE_LABEL_NUMBER (XEXP
2644 (XEXP (XVECEXP (whole_jump_insn
, 0, 0), 1),
2647 (TARGET_PDEBUG
? "; default" : ""));
2650 /* The TARGET_OPTION_OVERRIDE worker.
2651 As is the norm, this also parses -mfoo=bar type parameters. */
2654 cris_option_override (void)
2656 if (cris_max_stackframe_str
)
2658 cris_max_stackframe
= atoi (cris_max_stackframe_str
);
2660 /* Do some sanity checking. */
2661 if (cris_max_stackframe
< 0 || cris_max_stackframe
> 0x20000000)
2662 internal_error ("-max-stackframe=%d is not usable, not between 0 and %d",
2663 cris_max_stackframe
, 0x20000000);
2666 /* Let "-metrax4" and "-metrax100" change the cpu version. */
2667 if (TARGET_SVINTO
&& cris_cpu_version
< CRIS_CPU_SVINTO
)
2668 cris_cpu_version
= CRIS_CPU_SVINTO
;
2669 else if (TARGET_ETRAX4_ADD
&& cris_cpu_version
< CRIS_CPU_ETRAX4
)
2670 cris_cpu_version
= CRIS_CPU_ETRAX4
;
2672 /* Parse -march=... and its synonym, the deprecated -mcpu=... */
2676 = (*cris_cpu_str
== 'v' ? atoi (cris_cpu_str
+ 1) : -1);
2678 if (strcmp ("etrax4", cris_cpu_str
) == 0)
2679 cris_cpu_version
= 3;
2681 if (strcmp ("svinto", cris_cpu_str
) == 0
2682 || strcmp ("etrax100", cris_cpu_str
) == 0)
2683 cris_cpu_version
= 8;
2685 if (strcmp ("ng", cris_cpu_str
) == 0
2686 || strcmp ("etrax100lx", cris_cpu_str
) == 0)
2687 cris_cpu_version
= 10;
2689 if (cris_cpu_version
< 0 || cris_cpu_version
> 32)
2690 error ("unknown CRIS version specification in -march= or -mcpu= : %s",
2693 /* Set the target flags. */
2694 if (cris_cpu_version
>= CRIS_CPU_ETRAX4
)
2695 target_flags
|= MASK_ETRAX4_ADD
;
2697 /* If this is Svinto or higher, align for 32 bit accesses. */
2698 if (cris_cpu_version
>= CRIS_CPU_SVINTO
)
2700 |= (MASK_SVINTO
| MASK_ALIGN_BY_32
2701 | MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2704 /* Note that we do not add new flags when it can be completely
2705 described with a macro that uses -mcpu=X. So
2706 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */
2712 = (*cris_tune_str
== 'v' ? atoi (cris_tune_str
+ 1) : -1);
2714 if (strcmp ("etrax4", cris_tune_str
) == 0)
2717 if (strcmp ("svinto", cris_tune_str
) == 0
2718 || strcmp ("etrax100", cris_tune_str
) == 0)
2721 if (strcmp ("ng", cris_tune_str
) == 0
2722 || strcmp ("etrax100lx", cris_tune_str
) == 0)
2725 if (cris_tune
< 0 || cris_tune
> 32)
2726 error ("unknown CRIS cpu version specification in -mtune= : %s",
2729 if (cris_tune
>= CRIS_CPU_SVINTO
)
2730 /* We have currently nothing more to tune than alignment for
2733 |= (MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2734 | MASK_DATA_ALIGN
| MASK_ALIGN_BY_32
);
2737 if (cris_cpu_version
>= CRIS_CPU_V32
)
2738 target_flags
&= ~(MASK_SIDE_EFFECT_PREFIXES
|MASK_MUL_BUG
);
2742 /* Use error rather than warning, so invalid use is easily
2743 detectable. Still change to the values we expect, to avoid
2747 error ("-fPIC and -fpic are not supported in this configuration");
2751 /* Turn off function CSE. We need to have the addresses reach the
2752 call expanders to get PLT-marked, as they could otherwise be
2753 compared against zero directly or indirectly. After visiting the
2754 call expanders they will then be cse:ed, as the call expanders
2755 force_reg the addresses, effectively forcing flag_no_function_cse
2757 flag_no_function_cse
= 1;
2760 /* Set the per-function-data initializer. */
2761 init_machine_status
= cris_init_machine_status
;
2764 /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */
2767 cris_asm_output_mi_thunk (FILE *stream
,
2768 tree thunkdecl ATTRIBUTE_UNUSED
,
2769 HOST_WIDE_INT delta
,
2770 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
2773 /* Make sure unwind info is emitted for the thunk if needed. */
2774 final_start_function (emit_barrier (), stream
, 1);
2777 fprintf (stream
, "\tadd%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2778 ADDITIVE_SIZE_MODIFIER (delta
), delta
,
2779 reg_names
[CRIS_FIRST_ARG_REG
]);
2781 fprintf (stream
, "\tsub%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2782 ADDITIVE_SIZE_MODIFIER (-delta
), -delta
,
2783 reg_names
[CRIS_FIRST_ARG_REG
]);
2787 const char *name
= XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0);
2789 name
= (* targetm
.strip_name_encoding
) (name
);
2793 fprintf (stream
, "\tba ");
2794 assemble_name (stream
, name
);
2795 fprintf (stream
, "%s\n", CRIS_PLT_PCOFFSET_SUFFIX
);
2799 fprintf (stream
, "add.d ");
2800 assemble_name (stream
, name
);
2801 fprintf (stream
, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX
);
2806 fprintf (stream
, "jump ");
2807 assemble_name (stream
, XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0));
2808 fprintf (stream
, "\n");
2811 fprintf (stream
, "\tnop\n");
2814 final_end_function ();
2817 /* Boilerplate emitted at start of file.
2819 NO_APP *only at file start* means faster assembly. It also means
2820 comments are not allowed. In some cases comments will be output
2821 for debugging purposes. Make sure they are allowed then. */
2823 cris_file_start (void)
2825 /* These expressions can vary at run time, so we cannot put
2826 them into TARGET_INITIALIZER. */
2827 targetm
.asm_file_start_app_off
= !(TARGET_PDEBUG
|| flag_print_asm_name
);
2829 default_file_start ();
2832 /* Output that goes at the end of the file, similarly. */
2835 cris_file_end (void)
2837 /* For CRIS, the default is to assume *no* executable stack, so output
2838 an executable-stack-note only when needed. */
2839 if (TARGET_LINUX
&& trampolines_created
)
2840 file_end_indicate_exec_stack ();
2843 /* Rename the function calls for integer multiply and divide. */
2845 cris_init_libfuncs (void)
2847 set_optab_libfunc (smul_optab
, SImode
, "__Mul");
2848 set_optab_libfunc (sdiv_optab
, SImode
, "__Div");
2849 set_optab_libfunc (udiv_optab
, SImode
, "__Udiv");
2850 set_optab_libfunc (smod_optab
, SImode
, "__Mod");
2851 set_optab_libfunc (umod_optab
, SImode
, "__Umod");
2853 /* Atomic data being unaligned is unfortunately a reality.
2855 if (TARGET_ATOMICS_MAY_CALL_LIBFUNCS
)
2857 set_optab_libfunc (sync_compare_and_swap_optab
, SImode
,
2858 "__cris_atcmpxchgr32");
2859 set_optab_libfunc (sync_compare_and_swap_optab
, HImode
,
2860 "__cris_atcmpxchgr16");
2864 /* The INIT_EXPANDERS worker sets the per-function-data initializer and
2868 cris_init_expanders (void)
2870 /* Nothing here at the moment. */
2873 /* Zero initialization is OK for all current fields. */
2875 static struct machine_function
*
2876 cris_init_machine_status (void)
2878 return ggc_cleared_alloc
<machine_function
> ();
2881 /* Split a 2 word move (DI or presumably DF) into component parts.
2882 Originally a copy of gen_split_move_double in m32r.c. */
2885 cris_split_movdx (rtx
*operands
)
2887 machine_mode mode
= GET_MODE (operands
[0]);
2888 rtx dest
= operands
[0];
2889 rtx src
= operands
[1];
2892 /* We used to have to handle (SUBREG (MEM)) here, but that should no
2893 longer happen; after reload there are no SUBREGs any more, and we're
2894 only called after reload. */
2895 CRIS_ASSERT (GET_CODE (dest
) != SUBREG
&& GET_CODE (src
) != SUBREG
);
2900 int dregno
= REGNO (dest
);
2902 /* Reg-to-reg copy. */
2905 int sregno
= REGNO (src
);
2907 int reverse
= (dregno
== sregno
+ 1);
2909 /* We normally copy the low-numbered register first. However, if
2910 the first register operand 0 is the same as the second register of
2911 operand 1, we must copy in the opposite order. */
2912 emit_insn (gen_rtx_SET (VOIDmode
,
2913 operand_subword (dest
, reverse
, TRUE
, mode
),
2914 operand_subword (src
, reverse
, TRUE
, mode
)));
2916 emit_insn (gen_rtx_SET (VOIDmode
,
2917 operand_subword (dest
, !reverse
, TRUE
, mode
),
2918 operand_subword (src
, !reverse
, TRUE
, mode
)));
2920 /* Constant-to-reg copy. */
2921 else if (CONST_INT_P (src
) || GET_CODE (src
) == CONST_DOUBLE
)
2924 split_double (src
, &words
[0], &words
[1]);
2925 emit_insn (gen_rtx_SET (VOIDmode
,
2926 operand_subword (dest
, 0, TRUE
, mode
),
2929 emit_insn (gen_rtx_SET (VOIDmode
,
2930 operand_subword (dest
, 1, TRUE
, mode
),
2933 /* Mem-to-reg copy. */
2934 else if (MEM_P (src
))
2936 /* If the high-address word is used in the address, we must load it
2937 last. Otherwise, load it first. */
2938 rtx addr
= XEXP (src
, 0);
2940 = (refers_to_regno_p (dregno
, dregno
+ 1, addr
, NULL
) != 0);
2942 /* The original code implies that we can't do
2943 move.x [rN+],rM move.x [rN],rM+1
2944 when rN is dead, because of REG_NOTES damage. That is
2945 consistent with what I've seen, so don't try it.
2947 We have two different cases here; if the addr is POST_INC,
2948 just pass it through, otherwise add constants. */
2950 if (GET_CODE (addr
) == POST_INC
)
2955 /* Whenever we emit insns with post-incremented
2956 addresses ourselves, we must add a post-inc note
2958 mem
= change_address (src
, SImode
, addr
);
2960 = gen_rtx_SET (VOIDmode
,
2961 operand_subword (dest
, 0, TRUE
, mode
), mem
);
2962 insn
= emit_insn (insn
);
2963 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2965 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2968 mem
= copy_rtx (mem
);
2970 = gen_rtx_SET (VOIDmode
,
2971 operand_subword (dest
, 1, TRUE
, mode
), mem
);
2972 insn
= emit_insn (insn
);
2973 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2975 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2980 /* Make sure we don't get any other addresses with
2981 embedded postincrements. They should be stopped in
2982 GO_IF_LEGITIMATE_ADDRESS, but we're here for your
2984 if (side_effects_p (addr
))
2985 fatal_insn ("unexpected side-effects in address", addr
);
2987 emit_insn (gen_rtx_SET
2989 operand_subword (dest
, reverse
, TRUE
, mode
),
2992 plus_constant (Pmode
, addr
,
2993 reverse
* UNITS_PER_WORD
))));
2994 emit_insn (gen_rtx_SET
2996 operand_subword (dest
, ! reverse
, TRUE
, mode
),
2999 plus_constant (Pmode
, addr
,
3005 internal_error ("unknown src");
3007 /* Reg-to-mem copy or clear mem. */
3008 else if (MEM_P (dest
)
3010 || src
== const0_rtx
3011 || src
== CONST0_RTX (DFmode
)))
3013 rtx addr
= XEXP (dest
, 0);
3015 if (GET_CODE (addr
) == POST_INC
)
3020 /* Whenever we emit insns with post-incremented addresses
3021 ourselves, we must add a post-inc note manually. */
3022 mem
= change_address (dest
, SImode
, addr
);
3024 = gen_rtx_SET (VOIDmode
,
3025 mem
, operand_subword (src
, 0, TRUE
, mode
));
3026 insn
= emit_insn (insn
);
3027 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
3029 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
3032 mem
= copy_rtx (mem
);
3034 = gen_rtx_SET (VOIDmode
,
3036 operand_subword (src
, 1, TRUE
, mode
));
3037 insn
= emit_insn (insn
);
3038 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
3040 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
3045 /* Make sure we don't get any other addresses with embedded
3046 postincrements. They should be stopped in
3047 GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */
3048 if (side_effects_p (addr
))
3049 fatal_insn ("unexpected side-effects in address", addr
);
3051 emit_insn (gen_rtx_SET
3053 change_address (dest
, SImode
, addr
),
3054 operand_subword (src
, 0, TRUE
, mode
)));
3056 emit_insn (gen_rtx_SET
3058 change_address (dest
, SImode
,
3059 plus_constant (Pmode
, addr
,
3061 operand_subword (src
, 1, TRUE
, mode
)));
3066 internal_error ("unknown dest");
3073 /* The expander for the prologue pattern name. */
3076 cris_expand_prologue (void)
3079 int size
= get_frame_size ();
3080 /* Shorten the used name for readability. */
3081 int cfoa_size
= crtl
->outgoing_args_size
;
3082 int last_movem_reg
= -1;
3085 int return_address_on_stack
= cris_return_address_on_stack ();
3086 int got_really_used
= false;
3087 int n_movem_regs
= 0;
3088 int pretend
= crtl
->args
.pretend_args_size
;
3090 /* Don't do anything if no prologues or epilogues are wanted. */
3091 if (!TARGET_PROLOGUE_EPILOGUE
)
3094 CRIS_ASSERT (size
>= 0);
3096 if (crtl
->uses_pic_offset_table
)
3098 /* A reference may have been optimized out (like the abort () in
3099 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3101 push_topmost_sequence ();
3103 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL
);
3104 pop_topmost_sequence ();
3107 /* Align the size to what's best for the CPU model. */
3108 if (TARGET_STACK_ALIGN
)
3109 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
3113 /* See also cris_setup_incoming_varargs where
3114 cfun->machine->stdarg_regs is set. There are other setters of
3115 crtl->args.pretend_args_size than stdarg handling, like
3116 for an argument passed with parts in R13 and stack. We must
3117 not store R13 into the pretend-area for that case, as GCC does
3118 that itself. "Our" store would be marked as redundant and GCC
3119 will attempt to remove it, which will then be flagged as an
3120 internal error; trying to remove a frame-related insn. */
3121 int stdarg_regs
= cfun
->machine
->stdarg_regs
;
3123 framesize
+= pretend
;
3125 for (regno
= CRIS_FIRST_ARG_REG
+ CRIS_MAX_ARGS_IN_REGS
- 1;
3127 regno
--, pretend
-= 4, stdarg_regs
--)
3129 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3131 plus_constant (Pmode
,
3134 /* FIXME: When dwarf2 frame output and unless asynchronous
3135 exceptions, make dwarf2 bundle together all stack
3136 adjustments like it does for registers between stack
3138 RTX_FRAME_RELATED_P (insn
) = 1;
3140 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3141 set_mem_alias_set (mem
, get_varargs_alias_set ());
3142 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, regno
));
3144 /* Note the absence of RTX_FRAME_RELATED_P on the above insn:
3145 the value isn't restored, so we don't want to tell dwarf2
3146 that it's been stored to stack, else EH handling info would
3150 /* For other setters of crtl->args.pretend_args_size, we
3151 just adjust the stack by leaving the remaining size in
3152 "pretend", handled below. */
3155 /* Save SRP if not a leaf function. */
3156 if (return_address_on_stack
)
3158 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3160 plus_constant (Pmode
, stack_pointer_rtx
,
3163 RTX_FRAME_RELATED_P (insn
) = 1;
3165 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3166 set_mem_alias_set (mem
, get_frame_alias_set ());
3167 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
));
3168 RTX_FRAME_RELATED_P (insn
) = 1;
3172 /* Set up the frame pointer, if needed. */
3173 if (frame_pointer_needed
)
3175 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3177 plus_constant (Pmode
, stack_pointer_rtx
,
3180 RTX_FRAME_RELATED_P (insn
) = 1;
3182 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3183 set_mem_alias_set (mem
, get_frame_alias_set ());
3184 insn
= emit_move_insn (mem
, frame_pointer_rtx
);
3185 RTX_FRAME_RELATED_P (insn
) = 1;
3187 insn
= emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
);
3188 RTX_FRAME_RELATED_P (insn
) = 1;
3193 /* Between frame-pointer and saved registers lie the area for local
3194 variables. If we get here with "pretended" size remaining, count
3195 it into the general stack size. */
3198 /* Get a contiguous sequence of registers, starting with R0, that need
3200 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
3202 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3206 /* Check if movem may be used for registers so far. */
3207 if (regno
== last_movem_reg
+ 1)
3208 /* Yes, update next expected register. */
3209 last_movem_reg
= regno
;
3212 /* We cannot use movem for all registers. We have to flush
3213 any movem:ed registers we got so far. */
3214 if (last_movem_reg
!= -1)
3217 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
3219 /* It is a win to use a side-effect assignment for
3220 64 <= size <= 128. But side-effect on movem was
3221 not usable for CRIS v0..3. Also only do it if
3222 side-effects insns are allowed. */
3223 if ((last_movem_reg
+ 1) * 4 + size
>= 64
3224 && (last_movem_reg
+ 1) * 4 + size
<= 128
3225 && (cris_cpu_version
>= CRIS_CPU_SVINTO
|| n_saved
== 1)
3226 && TARGET_SIDE_EFFECT_PREFIXES
)
3229 = gen_rtx_MEM (SImode
,
3230 plus_constant (Pmode
, stack_pointer_rtx
,
3231 -(n_saved
* 4 + size
)));
3232 set_mem_alias_set (mem
, get_frame_alias_set ());
3234 = cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3235 -(n_saved
* 4 + size
),
3241 = gen_rtx_SET (VOIDmode
,
3243 plus_constant (Pmode
, stack_pointer_rtx
,
3244 -(n_saved
* 4 + size
)));
3245 insn
= emit_insn (insn
);
3246 RTX_FRAME_RELATED_P (insn
) = 1;
3248 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3249 set_mem_alias_set (mem
, get_frame_alias_set ());
3250 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3254 framesize
+= n_saved
* 4 + size
;
3255 last_movem_reg
= -1;
3259 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3261 plus_constant (Pmode
,
3264 RTX_FRAME_RELATED_P (insn
) = 1;
3266 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3267 set_mem_alias_set (mem
, get_frame_alias_set ());
3268 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, regno
));
3269 RTX_FRAME_RELATED_P (insn
) = 1;
3271 framesize
+= 4 + size
;
3277 /* Check after, if we could movem all registers. This is the normal case. */
3278 if (last_movem_reg
!= -1)
3281 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
3283 /* Side-effect on movem was not usable for CRIS v0..3. Also only
3284 do it if side-effects insns are allowed. */
3285 if ((last_movem_reg
+ 1) * 4 + size
>= 64
3286 && (last_movem_reg
+ 1) * 4 + size
<= 128
3287 && (cris_cpu_version
>= CRIS_CPU_SVINTO
|| n_saved
== 1)
3288 && TARGET_SIDE_EFFECT_PREFIXES
)
3291 = gen_rtx_MEM (SImode
,
3292 plus_constant (Pmode
, stack_pointer_rtx
,
3293 -(n_saved
* 4 + size
)));
3294 set_mem_alias_set (mem
, get_frame_alias_set ());
3295 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3296 -(n_saved
* 4 + size
), true);
3301 = gen_rtx_SET (VOIDmode
,
3303 plus_constant (Pmode
, stack_pointer_rtx
,
3304 -(n_saved
* 4 + size
)));
3305 insn
= emit_insn (insn
);
3306 RTX_FRAME_RELATED_P (insn
) = 1;
3308 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3309 set_mem_alias_set (mem
, get_frame_alias_set ());
3310 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
), 0, true);
3313 framesize
+= n_saved
* 4 + size
;
3314 /* We have to put outgoing argument space after regs. */
3317 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3319 plus_constant (Pmode
,
3322 RTX_FRAME_RELATED_P (insn
) = 1;
3323 framesize
+= cfoa_size
;
3326 else if ((size
+ cfoa_size
) > 0)
3328 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3330 plus_constant (Pmode
,
3332 -(cfoa_size
+ size
))));
3333 RTX_FRAME_RELATED_P (insn
) = 1;
3334 framesize
+= size
+ cfoa_size
;
3337 /* Set up the PIC register, if it is used. */
3338 if (got_really_used
)
3341 = gen_rtx_UNSPEC (SImode
, gen_rtvec (1, const0_rtx
), CRIS_UNSPEC_GOT
);
3342 emit_move_insn (pic_offset_table_rtx
, got
);
3344 /* FIXME: This is a cover-up for flow2 messing up; it doesn't
3345 follow exceptional paths and tries to delete the GOT load as
3346 unused, if it isn't used on the non-exceptional paths. Other
3347 ports have similar or other cover-ups, or plain bugs marking
3348 the GOT register load as maybe-dead. To see this, remove the
3349 line below and try libsupc++/vec.cc or a trivial
3350 "static void y (); void x () {try {y ();} catch (...) {}}". */
3351 emit_use (pic_offset_table_rtx
);
3354 if (cris_max_stackframe
&& framesize
> cris_max_stackframe
)
3355 warning (0, "stackframe too big: %d bytes", framesize
);
3358 /* The expander for the epilogue pattern. */
3361 cris_expand_epilogue (void)
3364 int size
= get_frame_size ();
3365 int last_movem_reg
= -1;
3366 int argspace_offset
= crtl
->outgoing_args_size
;
3367 int pretend
= crtl
->args
.pretend_args_size
;
3369 bool return_address_on_stack
= cris_return_address_on_stack ();
3370 /* A reference may have been optimized out
3371 (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1)
3372 so check that it's still used. */
3373 int got_really_used
= false;
3374 int n_movem_regs
= 0;
3376 if (!TARGET_PROLOGUE_EPILOGUE
)
3379 if (crtl
->uses_pic_offset_table
)
3381 /* A reference may have been optimized out (like the abort () in
3382 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3384 push_topmost_sequence ();
3386 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL
);
3387 pop_topmost_sequence ();
3390 /* Align byte count of stack frame. */
3391 if (TARGET_STACK_ALIGN
)
3392 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
3394 /* Check how many saved regs we can movem. They start at r0 and must
3397 regno
< FIRST_PSEUDO_REGISTER
;
3399 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3403 if (regno
== last_movem_reg
+ 1)
3404 last_movem_reg
= regno
;
3409 /* If there was only one register that really needed to be saved
3410 through movem, don't use movem. */
3411 if (n_movem_regs
== 1)
3412 last_movem_reg
= -1;
3414 /* Now emit "normal" move insns for all regs higher than the movem
3416 for (regno
= FIRST_PSEUDO_REGISTER
- 1;
3417 regno
> last_movem_reg
;
3419 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3423 if (argspace_offset
)
3425 /* There is an area for outgoing parameters located before
3426 the saved registers. We have to adjust for that. */
3427 emit_insn (gen_rtx_SET (VOIDmode
,
3429 plus_constant (Pmode
, stack_pointer_rtx
,
3431 /* Make sure we only do this once. */
3432 argspace_offset
= 0;
3435 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3436 stack_pointer_rtx
));
3437 set_mem_alias_set (mem
, get_frame_alias_set ());
3438 insn
= emit_move_insn (gen_rtx_raw_REG (SImode
, regno
), mem
);
3440 /* Whenever we emit insns with post-incremented addresses
3441 ourselves, we must add a post-inc note manually. */
3443 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3446 /* If we have any movem-restore, do it now. */
3447 if (last_movem_reg
!= -1)
3451 if (argspace_offset
)
3453 emit_insn (gen_rtx_SET (VOIDmode
,
3455 plus_constant (Pmode
, stack_pointer_rtx
,
3457 argspace_offset
= 0;
3460 mem
= gen_rtx_MEM (SImode
,
3461 gen_rtx_POST_INC (SImode
, stack_pointer_rtx
));
3462 set_mem_alias_set (mem
, get_frame_alias_set ());
3464 = emit_insn (cris_gen_movem_load (mem
,
3465 GEN_INT (last_movem_reg
+ 1), 0));
3466 /* Whenever we emit insns with post-incremented addresses
3467 ourselves, we must add a post-inc note manually. */
3468 if (side_effects_p (PATTERN (insn
)))
3470 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3473 /* If we don't clobber all of the allocated stack area (we've already
3474 deallocated saved registers), GCC might want to schedule loads from
3475 the stack to *after* the stack-pointer restore, which introduces an
3476 interrupt race condition. This happened for the initial-value
3477 SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of
3478 other failure for that test). It also happened for the stack slot
3479 for the return value in (one version of)
3480 linux/fs/dcache.c:__d_lookup, at least with "-O2
3481 -fno-omit-frame-pointer". */
3483 /* Restore frame pointer if necessary. */
3484 if (frame_pointer_needed
)
3488 emit_insn (gen_cris_frame_deallocated_barrier ());
3490 emit_move_insn (stack_pointer_rtx
, frame_pointer_rtx
);
3491 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3492 stack_pointer_rtx
));
3493 set_mem_alias_set (mem
, get_frame_alias_set ());
3494 insn
= emit_move_insn (frame_pointer_rtx
, mem
);
3496 /* Whenever we emit insns with post-incremented addresses
3497 ourselves, we must add a post-inc note manually. */
3499 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3501 else if ((size
+ argspace_offset
) != 0)
3503 emit_insn (gen_cris_frame_deallocated_barrier ());
3505 /* If there was no frame-pointer to restore sp from, we must
3506 explicitly deallocate local variables. */
3508 /* Handle space for outgoing parameters that hasn't been handled
3510 size
+= argspace_offset
;
3512 emit_insn (gen_rtx_SET (VOIDmode
,
3514 plus_constant (Pmode
, stack_pointer_rtx
, size
)));
3517 /* If this function has no pushed register parameters
3518 (stdargs/varargs), and if it is not a leaf function, then we have
3519 the return address on the stack. */
3520 if (return_address_on_stack
&& pretend
== 0)
3522 if (TARGET_V32
|| crtl
->calls_eh_return
)
3526 rtx srpreg
= gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3527 mem
= gen_rtx_MEM (SImode
,
3528 gen_rtx_POST_INC (SImode
,
3529 stack_pointer_rtx
));
3530 set_mem_alias_set (mem
, get_frame_alias_set ());
3531 insn
= emit_move_insn (srpreg
, mem
);
3533 /* Whenever we emit insns with post-incremented addresses
3534 ourselves, we must add a post-inc note manually. */
3536 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3538 if (crtl
->calls_eh_return
)
3539 emit_insn (gen_addsi3 (stack_pointer_rtx
,
3541 gen_rtx_raw_REG (SImode
,
3542 CRIS_STACKADJ_REG
)));
3543 cris_expand_return (false);
3546 cris_expand_return (true);
3551 /* If we pushed some register parameters, then adjust the stack for
3555 /* If SRP is stored on the way, we need to restore it first. */
3556 if (return_address_on_stack
)
3559 rtx srpreg
= gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3562 mem
= gen_rtx_MEM (SImode
,
3563 gen_rtx_POST_INC (SImode
,
3564 stack_pointer_rtx
));
3565 set_mem_alias_set (mem
, get_frame_alias_set ());
3566 insn
= emit_move_insn (srpreg
, mem
);
3568 /* Whenever we emit insns with post-incremented addresses
3569 ourselves, we must add a post-inc note manually. */
3571 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3574 emit_insn (gen_rtx_SET (VOIDmode
,
3576 plus_constant (Pmode
, stack_pointer_rtx
,
3580 /* Perform the "physical" unwinding that the EH machinery calculated. */
3581 if (crtl
->calls_eh_return
)
3582 emit_insn (gen_addsi3 (stack_pointer_rtx
,
3584 gen_rtx_raw_REG (SImode
,
3585 CRIS_STACKADJ_REG
)));
3586 cris_expand_return (false);
3589 /* Worker function for generating movem from mem for load_multiple. */
3592 cris_gen_movem_load (rtx src
, rtx nregs_rtx
, int nprefix
)
3594 int nregs
= INTVAL (nregs_rtx
);
3598 rtx srcreg
= XEXP (src
, 0);
3599 unsigned int regno
= nregs
- 1;
3608 if (GET_CODE (srcreg
) == POST_INC
)
3609 srcreg
= XEXP (srcreg
, 0);
3611 CRIS_ASSERT (REG_P (srcreg
));
3613 /* Don't use movem for just one insn. The insns are equivalent except
3614 for the pipeline hazard (on v32); movem does not forward the loaded
3615 registers so there's a three cycles penalty for their use. */
3617 return gen_movsi (gen_rtx_REG (SImode
, 0), src
);
3619 vec
= rtvec_alloc (nprefix
+ nregs
3620 + (GET_CODE (XEXP (src
, 0)) == POST_INC
));
3622 if (GET_CODE (XEXP (src
, 0)) == POST_INC
)
3624 RTVEC_ELT (vec
, nprefix
+ 1)
3625 = gen_rtx_SET (VOIDmode
, srcreg
,
3626 plus_constant (Pmode
, srcreg
, nregs
* 4));
3630 src
= replace_equiv_address (src
, srcreg
);
3631 RTVEC_ELT (vec
, nprefix
)
3632 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, regno
), src
);
3635 for (i
= 1; i
< nregs
; i
++, eltno
++)
3637 RTVEC_ELT (vec
, nprefix
+ eltno
)
3638 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, regno
),
3639 adjust_address_nv (src
, SImode
, i
* 4));
3643 return gen_rtx_PARALLEL (VOIDmode
, vec
);
3646 /* Worker function for generating movem to mem. If FRAME_RELATED, notes
3647 are added that the dwarf2 machinery understands. */
3650 cris_emit_movem_store (rtx dest
, rtx nregs_rtx
, int increment
,
3653 int nregs
= INTVAL (nregs_rtx
);
3658 rtx destreg
= XEXP (dest
, 0);
3659 unsigned int regno
= nregs
- 1;
3668 if (GET_CODE (destreg
) == POST_INC
)
3669 increment
+= nregs
* 4;
3671 if (GET_CODE (destreg
) == POST_INC
|| GET_CODE (destreg
) == PLUS
)
3672 destreg
= XEXP (destreg
, 0);
3674 CRIS_ASSERT (REG_P (destreg
));
3676 /* Don't use movem for just one insn. The insns are equivalent except
3677 for the pipeline hazard (on v32); movem does not forward the loaded
3678 registers so there's a three cycles penalty for use. */
3681 rtx mov
= gen_rtx_SET (VOIDmode
, dest
, gen_rtx_REG (SImode
, 0));
3685 insn
= emit_insn (mov
);
3687 RTX_FRAME_RELATED_P (insn
) = 1;
3691 /* If there was a request for a side-effect, create the ordinary
3693 vec
= rtvec_alloc (2);
3695 RTVEC_ELT (vec
, 0) = mov
;
3696 RTVEC_ELT (vec
, 1) = gen_rtx_SET (VOIDmode
, destreg
,
3697 plus_constant (Pmode
, destreg
,
3701 RTX_FRAME_RELATED_P (mov
) = 1;
3702 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3707 vec
= rtvec_alloc (nregs
+ (increment
!= 0 ? 1 : 0));
3709 = gen_rtx_SET (VOIDmode
,
3710 replace_equiv_address (dest
,
3711 plus_constant (Pmode
, destreg
,
3713 gen_rtx_REG (SImode
, regno
));
3716 /* The dwarf2 info wants this mark on each component in a parallel
3717 that's part of the prologue (though it's optional on the first
3720 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 0)) = 1;
3725 = gen_rtx_SET (VOIDmode
, destreg
,
3726 plus_constant (Pmode
, destreg
,
3728 ? increment
: nregs
* 4));
3732 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3734 /* Don't call adjust_address_nv on a post-incremented address if
3736 if (GET_CODE (XEXP (dest
, 0)) == POST_INC
)
3737 dest
= replace_equiv_address (dest
, destreg
);
3740 for (i
= 1; i
< nregs
; i
++, eltno
++)
3742 RTVEC_ELT (vec
, eltno
)
3743 = gen_rtx_SET (VOIDmode
, adjust_address_nv (dest
, SImode
, i
* 4),
3744 gen_rtx_REG (SImode
, regno
));
3746 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, eltno
)) = 1;
3751 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
3753 /* Because dwarf2out.c handles the insns in a parallel as a sequence,
3754 we need to keep the stack adjustment separate, after the
3755 MEM-setters. Else the stack-adjustment in the second component of
3756 the parallel would be mishandled; the offsets for the SETs that
3757 follow it would be wrong. We prepare for this by adding a
3758 REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE
3759 followed by the increment. Note that we have FRAME_RELATED_P on
3760 all the SETs, including the original stack adjustment SET in the
3766 rtx seq
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (nregs
+ 1));
3767 XVECEXP (seq
, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 0));
3768 for (i
= 1; i
< nregs
; i
++)
3770 = copy_rtx (XVECEXP (PATTERN (insn
), 0, i
+ 1));
3771 XVECEXP (seq
, 0, nregs
) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 1));
3772 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, seq
);
3775 RTX_FRAME_RELATED_P (insn
) = 1;
3781 /* Worker function for expanding the address for PIC function calls. */
3784 cris_expand_pic_call_address (rtx
*opp
, rtx
*markerp
)
3788 gcc_assert (flag_pic
&& MEM_P (op
));
3791 /* It might be that code can be generated that jumps to 0 (or to a
3792 specific address). Don't die on that. (There is a
3794 if (CONSTANT_P (op
) && !CONST_INT_P (op
))
3796 enum cris_symbol_type t
= cris_symbol_type_of (op
);
3798 CRIS_ASSERT (can_create_pseudo_p ());
3800 /* For local symbols (non-PLT), just get the plain symbol
3801 reference into a register. For symbols that can be PLT, make
3803 if (t
== cris_rel_symbol
)
3805 /* For v32, we're fine as-is; just PICify the symbol. Forcing
3806 into a register caused performance regression for 3.2.1,
3807 observable in __floatdidf and elsewhere in libgcc. */
3810 rtx sym
= GET_CODE (op
) != CONST
? op
: get_related_value (op
);
3811 HOST_WIDE_INT offs
= get_integer_term (op
);
3813 /* We can't get calls to sym+N, N integer, can we? */
3814 gcc_assert (offs
== 0);
3816 op
= gen_rtx_CONST (Pmode
,
3817 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, sym
),
3818 CRIS_UNSPEC_PCREL
));
3821 op
= force_reg (Pmode
, op
);
3824 *markerp
= const0_rtx
;
3826 else if (t
== cris_got_symbol
)
3828 if (TARGET_AVOID_GOTPLT
)
3830 /* Change a "jsr sym" into (allocate register rM, rO)
3831 "move.d (const (unspec [sym] CRIS_UNSPEC_PLT_GOTREL)),rM"
3832 "add.d rPIC,rM,rO", "jsr rO" for pre-v32 and
3833 "jsr (const (unspec [sym] CRIS_UNSPEC_PLT_PCREL))"
3837 crtl
->uses_pic_offset_table
= 1;
3838 tem
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
),
3840 ? CRIS_UNSPEC_PLT_PCREL
3841 : CRIS_UNSPEC_PLT_GOTREL
);
3842 tem
= gen_rtx_CONST (Pmode
, tem
);
3847 rm
= gen_reg_rtx (Pmode
);
3848 emit_move_insn (rm
, tem
);
3849 ro
= gen_reg_rtx (Pmode
);
3850 if (expand_binop (Pmode
, add_optab
, rm
,
3851 pic_offset_table_rtx
,
3852 ro
, 0, OPTAB_LIB_WIDEN
) != ro
)
3853 internal_error ("expand_binop failed in movsi got");
3859 /* Change a "jsr sym" into (allocate register rM, rO)
3860 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOTREAD)),rM"
3861 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access
3862 marked as not trapping and not aliasing. No "move.d
3863 [rO],rP" as that would invite to re-use of a value
3864 that should not be reused. FIXME: Need a peephole2
3865 for cases when this is cse:d from the call, to change
3866 back to just get the PLT entry address, so we don't
3867 resolve the same symbol over and over (the memory
3868 access of the PLTGOT isn't constant). */
3869 rtx tem
, mem
, rm
, ro
;
3871 gcc_assert (can_create_pseudo_p ());
3872 crtl
->uses_pic_offset_table
= 1;
3873 tem
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
),
3874 CRIS_UNSPEC_PLTGOTREAD
);
3875 rm
= gen_reg_rtx (Pmode
);
3876 emit_move_insn (rm
, gen_rtx_CONST (Pmode
, tem
));
3877 ro
= gen_reg_rtx (Pmode
);
3878 if (expand_binop (Pmode
, add_optab
, rm
,
3879 pic_offset_table_rtx
,
3880 ro
, 0, OPTAB_LIB_WIDEN
) != ro
)
3881 internal_error ("expand_binop failed in movsi got");
3882 mem
= gen_rtx_MEM (Pmode
, ro
);
3884 /* This MEM doesn't alias anything. Whether it aliases
3885 other same symbols is unimportant. */
3886 set_mem_alias_set (mem
, new_alias_set ());
3887 MEM_NOTRAP_P (mem
) = 1;
3891 /* We need to prepare this call to go through the PLT; we
3892 need to make GOT available. */
3893 *markerp
= pic_offset_table_rtx
;
3896 /* Can't possibly get anything else for a function-call, right? */
3897 fatal_insn ("unidentifiable call op", op
);
3899 /* If the validizing variant is called, it will try to validize
3900 the address as a valid any-operand constant, but as it's only
3901 valid for calls and moves, it will fail and always be forced
3903 *opp
= replace_equiv_address_nv (*opp
, op
);
3906 /* Can't tell what locality a call to a non-constant address has;
3907 better make the GOT register alive at it.
3908 FIXME: Can we see whether the register has known constant
3910 *markerp
= pic_offset_table_rtx
;
3913 /* Make sure operands are in the right order for an addsi3 insn as
3914 generated by a define_split. Nothing but REG_P as the first
3915 operand is recognized by addsi3 after reload. OPERANDS contains
3916 the operands, with the first at OPERANDS[N] and the second at
3920 cris_order_for_addsi3 (rtx
*operands
, int n
)
3922 if (!REG_P (operands
[n
]))
3924 rtx tem
= operands
[n
];
3925 operands
[n
] = operands
[n
+ 1];
3926 operands
[n
+ 1] = tem
;
3930 /* Use from within code, from e.g. PRINT_OPERAND and
3931 PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit
3932 different things depending on whether code operand or constant is
3936 cris_output_addr_const (FILE *file
, rtx x
)
3939 output_addr_const (file
, x
);
3943 /* Worker function for ASM_OUTPUT_SYMBOL_REF. */
3946 cris_asm_output_symbol_ref (FILE *file
, rtx x
)
3948 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
3950 if (flag_pic
&& in_code
> 0)
3952 const char *origstr
= XSTR (x
, 0);
3954 str
= (* targetm
.strip_name_encoding
) (origstr
);
3955 assemble_name (file
, str
);
3958 if (!TARGET_V32
&& !crtl
->uses_pic_offset_table
)
3959 output_operand_lossage ("PIC register isn't set up");
3962 assemble_name (file
, XSTR (x
, 0));
3965 /* Worker function for ASM_OUTPUT_LABEL_REF. */
3968 cris_asm_output_label_ref (FILE *file
, char *buf
)
3970 if (flag_pic
&& in_code
> 0)
3972 assemble_name (file
, buf
);
3975 if (!TARGET_V32
&& !crtl
->uses_pic_offset_table
)
3976 internal_error ("emitting PIC operand, but PIC register "
3980 assemble_name (file
, buf
);
3983 /* Worker function for TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
3986 cris_output_addr_const_extra (FILE *file
, rtx xconst
)
3988 switch (GET_CODE (xconst
))
3993 x
= XVECEXP (xconst
, 0, 0);
3994 CRIS_ASSERT (GET_CODE (x
) == SYMBOL_REF
3995 || GET_CODE (x
) == LABEL_REF
3996 || GET_CODE (x
) == CONST
);
3997 output_addr_const (file
, x
);
3998 switch (XINT (xconst
, 1))
4000 case CRIS_UNSPEC_PCREL
:
4001 /* We only get this with -fpic/PIC to tell it apart from an
4002 invalid symbol. We can't tell here, but it should only
4003 be the operand of a call or movsi. */
4004 gcc_assert (TARGET_V32
&& flag_pic
);
4007 case CRIS_UNSPEC_PLT_PCREL
:
4008 gcc_assert (TARGET_V32
);
4009 fprintf (file
, ":PLT");
4012 case CRIS_UNSPEC_PLT_GOTREL
:
4013 gcc_assert (!TARGET_V32
);
4014 fprintf (file
, ":PLTG");
4017 case CRIS_UNSPEC_GOTREL
:
4018 gcc_assert (!TARGET_V32
);
4019 fprintf (file
, ":GOTOFF");
4022 case CRIS_UNSPEC_GOTREAD
:
4024 fprintf (file
, ":GOT16");
4026 fprintf (file
, ":GOT");
4029 case CRIS_UNSPEC_PLTGOTREAD
:
4031 fprintf (file
, CRIS_GOTPLT_SUFFIX
"16");
4033 fprintf (file
, CRIS_GOTPLT_SUFFIX
);
4046 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
4049 cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
4050 int incoming ATTRIBUTE_UNUSED
)
4052 return gen_rtx_REG (Pmode
, CRIS_STRUCT_VALUE_REGNUM
);
4055 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
4058 cris_setup_incoming_varargs (cumulative_args_t ca_v
,
4059 machine_mode mode ATTRIBUTE_UNUSED
,
4060 tree type ATTRIBUTE_UNUSED
,
4061 int *pretend_arg_size
,
4064 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4066 if (ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
4068 int stdarg_regs
= CRIS_MAX_ARGS_IN_REGS
- ca
->regs
;
4069 cfun
->machine
->stdarg_regs
= stdarg_regs
;
4070 *pretend_arg_size
= stdarg_regs
* 4;
4074 fprintf (asm_out_file
,
4075 "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n",
4076 ca
->regs
, *pretend_arg_size
, second_time
);
4079 /* Return true if TYPE must be passed by invisible reference.
4080 For cris, we pass <= 8 bytes by value, others by reference. */
4083 cris_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
4084 machine_mode mode
, const_tree type
,
4085 bool named ATTRIBUTE_UNUSED
)
4087 return (targetm
.calls
.must_pass_in_stack (mode
, type
)
4088 || CRIS_FUNCTION_ARG_SIZE (mode
, type
) > 8);
4091 /* A combination of defining TARGET_PROMOTE_FUNCTION_MODE, promoting arguments
4092 and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the
4093 best code size and speed for gcc, ipps and products in gcc-2.7.2. */
4096 cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
4098 int *punsignedp ATTRIBUTE_UNUSED
,
4099 const_tree fntype ATTRIBUTE_UNUSED
,
4102 /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even
4103 when modifying TARGET_FUNCTION_VALUE to return the promoted mode).
4104 Maybe pointless as of now, but let's keep the old behavior. */
4105 if (for_return
== 1)
4107 return CRIS_PROMOTED_MODE (mode
, *punsignedp
, type
);
4110 /* Atomic types require alignment to be at least their "natural" size. */
4113 cris_atomic_align_for_mode (machine_mode mode
)
4115 return GET_MODE_BITSIZE (mode
);
4118 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4122 cris_function_value(const_tree type
,
4123 const_tree func ATTRIBUTE_UNUSED
,
4124 bool outgoing ATTRIBUTE_UNUSED
)
4126 return gen_rtx_REG (TYPE_MODE (type
), CRIS_FIRST_ARG_REG
);
4129 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4133 cris_libcall_value (machine_mode mode
,
4134 const_rtx fun ATTRIBUTE_UNUSED
)
4136 return gen_rtx_REG (mode
, CRIS_FIRST_ARG_REG
);
4139 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4143 cris_function_value_regno_p (const unsigned int regno
)
4145 return (regno
== CRIS_FIRST_ARG_REG
);
4149 cris_arg_partial_bytes (cumulative_args_t ca
, machine_mode mode
,
4150 tree type
, bool named ATTRIBUTE_UNUSED
)
4152 if (get_cumulative_args (ca
)->regs
== CRIS_MAX_ARGS_IN_REGS
- 1
4153 && !targetm
.calls
.must_pass_in_stack (mode
, type
)
4154 && CRIS_FUNCTION_ARG_SIZE (mode
, type
) > 4
4155 && CRIS_FUNCTION_ARG_SIZE (mode
, type
) <= 8)
4156 return UNITS_PER_WORD
;
4162 cris_function_arg_1 (cumulative_args_t ca_v
,
4163 machine_mode mode ATTRIBUTE_UNUSED
,
4164 const_tree type ATTRIBUTE_UNUSED
,
4165 bool named
, bool incoming
)
4167 const CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4169 if ((!incoming
|| named
) && ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
4170 return gen_rtx_REG (mode
, CRIS_FIRST_ARG_REG
+ ca
->regs
);
4175 /* Worker function for TARGET_FUNCTION_ARG.
4176 The void_type_node is sent as a "closing" call. */
4179 cris_function_arg (cumulative_args_t ca
, machine_mode mode
,
4180 const_tree type
, bool named
)
4182 return cris_function_arg_1 (ca
, mode
, type
, named
, false);
4185 /* Worker function for TARGET_FUNCTION_INCOMING_ARG.
4187 The differences between this and the previous, is that this one checks
4188 that an argument is named, since incoming stdarg/varargs arguments are
4189 pushed onto the stack, and we don't have to check against the "closing"
4190 void_type_node TYPE parameter. */
4193 cris_function_incoming_arg (cumulative_args_t ca
, machine_mode mode
,
4194 const_tree type
, bool named
)
4196 return cris_function_arg_1 (ca
, mode
, type
, named
, true);
4199 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE. */
4202 cris_function_arg_advance (cumulative_args_t ca_v
, machine_mode mode
,
4203 const_tree type
, bool named ATTRIBUTE_UNUSED
)
4205 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4207 ca
->regs
+= (3 + CRIS_FUNCTION_ARG_SIZE (mode
, type
)) / 4;
4210 /* Worker function for TARGET_MD_ASM_CLOBBERS. */
4213 cris_md_asm_clobbers (tree outputs
, tree inputs
, tree in_clobbers
)
4215 HARD_REG_SET mof_set
;
4219 CLEAR_HARD_REG_SET (mof_set
);
4220 SET_HARD_REG_BIT (mof_set
, CRIS_MOF_REGNUM
);
4222 /* For the time being, all asms clobber condition codes. Revisit when
4223 there's a reasonable use for inputs/outputs that mention condition
4226 = tree_cons (NULL_TREE
,
4227 build_string (strlen (reg_names
[CRIS_CC0_REGNUM
]),
4228 reg_names
[CRIS_CC0_REGNUM
]),
4231 for (t
= outputs
; t
!= NULL
; t
= TREE_CHAIN (t
))
4233 tree val
= TREE_VALUE (t
);
4235 /* The constraint letter for the singleton register class of MOF
4236 is 'h'. If it's mentioned in the constraints, the asm is
4237 MOF-aware and adding it to the clobbers would cause it to have
4238 impossible constraints. */
4239 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t
))),
4241 || tree_overlaps_hard_reg_set (val
, &mof_set
) != NULL_TREE
)
4245 for (t
= inputs
; t
!= NULL
; t
= TREE_CHAIN (t
))
4247 tree val
= TREE_VALUE (t
);
4249 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t
))),
4251 || tree_overlaps_hard_reg_set (val
, &mof_set
) != NULL_TREE
)
4255 return tree_cons (NULL_TREE
,
4256 build_string (strlen (reg_names
[CRIS_MOF_REGNUM
]),
4257 reg_names
[CRIS_MOF_REGNUM
]),
4261 /* Implement TARGET_FRAME_POINTER_REQUIRED.
4263 Really only needed if the stack frame has variable length (alloca
4264 or variable sized local arguments (GNU C extension). See PR39499 and
4265 PR38609 for the reason this isn't just 0. */
4268 cris_frame_pointer_required (void)
4270 return !crtl
->sp_is_unchanging
;
4273 /* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE.
4275 This looks too complicated, and it is. I assigned r7 to be the
4276 static chain register, but it is call-saved, so we have to save it,
4277 and come back to restore it after the call, so we have to save srp...
4278 Anyway, trampolines are rare enough that we can cope with this
4279 somewhat lack of elegance.
4280 (Do not be tempted to "straighten up" whitespace in the asms; the
4281 assembler #NO_APP state mandates strict spacing). */
4282 /* ??? See the i386 regparm=3 implementation that pushes the static
4283 chain value to the stack in the trampoline, and uses a call-saved
4284 register when called directly. */
4287 cris_asm_trampoline_template (FILE *f
)
4291 /* This normally-unused nop insn acts as an instruction to
4292 the simulator to flush its instruction cache. None of
4293 the other instructions in the trampoline template suits
4294 as a trigger for V32. The pc-relative addressing mode
4295 works nicely as a trigger for V10.
4296 FIXME: Have specific V32 template (possibly avoiding the
4297 use of a special instruction). */
4298 fprintf (f
, "\tclearf x\n");
4299 /* We have to use a register as an intermediate, choosing
4300 semi-randomly R1 (which has to not be the STATIC_CHAIN_REGNUM),
4301 so we can use it for address indirection and jsr target. */
4302 fprintf (f
, "\tmove $r1,$mof\n");
4304 fprintf (f
, "\tmove.d 0,$r1\n");
4305 fprintf (f
, "\tmove.d $%s,[$r1]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4306 fprintf (f
, "\taddq 6,$r1\n");
4307 fprintf (f
, "\tmove $mof,[$r1]\n");
4308 fprintf (f
, "\taddq 6,$r1\n");
4309 fprintf (f
, "\tmove $srp,[$r1]\n");
4311 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4313 fprintf (f
, "\tmove.d 0,$r1\n");
4314 fprintf (f
, "\tjsr $r1\n");
4315 fprintf (f
, "\tsetf\n");
4317 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4319 fprintf (f
, "\tmove.d 0,$r1\n");
4321 fprintf (f
, "\tmove.d 0,$r9\n");
4322 fprintf (f
, "\tjump $r9\n");
4323 fprintf (f
, "\tsetf\n");
4327 fprintf (f
, "\tmove.d $%s,[$pc+20]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4328 fprintf (f
, "\tmove $srp,[$pc+22]\n");
4329 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4330 fprintf (f
, "\tjsr 0\n");
4331 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4332 fprintf (f
, "\tjump 0\n");
4336 /* Implement TARGET_TRAMPOLINE_INIT. */
4339 cris_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
4341 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
4342 rtx tramp
= XEXP (m_tramp
, 0);
4345 emit_block_move (m_tramp
, assemble_trampoline_template (),
4346 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
4350 mem
= adjust_address (m_tramp
, SImode
, 6);
4351 emit_move_insn (mem
, plus_constant (Pmode
, tramp
, 38));
4352 mem
= adjust_address (m_tramp
, SImode
, 22);
4353 emit_move_insn (mem
, chain_value
);
4354 mem
= adjust_address (m_tramp
, SImode
, 28);
4355 emit_move_insn (mem
, fnaddr
);
4359 mem
= adjust_address (m_tramp
, SImode
, 10);
4360 emit_move_insn (mem
, chain_value
);
4361 mem
= adjust_address (m_tramp
, SImode
, 16);
4362 emit_move_insn (mem
, fnaddr
);
4365 /* Note that there is no need to do anything with the cache for
4366 sake of a trampoline. */
4371 /* Various small functions to replace macros. Only called from a
4372 debugger. They might collide with gcc functions or system functions,
4373 so only emit them when '#if 1' above. */
4375 enum rtx_code
Get_code (rtx
);
4380 return GET_CODE (x
);
4383 const char *Get_mode (rtx
);
4388 return GET_MODE_NAME (GET_MODE (x
));
4391 rtx
Xexp (rtx
, int);
4399 rtx
Xvecexp (rtx
, int, int);
4402 Xvecexp (rtx x
, int n
, int m
)
4404 return XVECEXP (x
, n
, m
);
4407 int Get_rtx_len (rtx
);
4412 return GET_RTX_LENGTH (GET_CODE (x
));
4415 /* Use upper-case to distinguish from local variables that are sometimes
4416 called next_insn and prev_insn. */
4418 rtx
Next_insn (rtx
);
4421 Next_insn (rtx insn
)
4423 return NEXT_INSN (insn
);
4426 rtx
Prev_insn (rtx
);
4429 Prev_insn (rtx insn
)
4431 return PREV_INSN (insn
);
4435 #include "gt-cris.h"
4439 * eval: (c-set-style "gnu")
4440 * indent-tabs-mode: t