1 @c Copyright (C) 2006 Free Software Foundation, Inc.
2 @c This is part of the GCC manual.
3 @c For copying conditions, see the file gcc.texi.
5 @c This file is generated automatically using gcc/config/arm/neon-docgen.ml
6 @c Please do not edit manually.
7 @subsubsection Addition
10 @item uint32x2_t vadd_u32 (uint32x2_t, uint32x2_t)
11 @*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{d0}, @var{d0}, @var{d0}}
16 @item uint16x4_t vadd_u16 (uint16x4_t, uint16x4_t)
17 @*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{d0}, @var{d0}, @var{d0}}
22 @item uint8x8_t vadd_u8 (uint8x8_t, uint8x8_t)
23 @*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{d0}, @var{d0}, @var{d0}}
28 @item int32x2_t vadd_s32 (int32x2_t, int32x2_t)
29 @*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{d0}, @var{d0}, @var{d0}}
34 @item int16x4_t vadd_s16 (int16x4_t, int16x4_t)
35 @*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{d0}, @var{d0}, @var{d0}}
40 @item int8x8_t vadd_s8 (int8x8_t, int8x8_t)
41 @*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{d0}, @var{d0}, @var{d0}}
46 @item float32x2_t vadd_f32 (float32x2_t, float32x2_t)
47 @*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{d0}, @var{d0}, @var{d0}}
52 @item uint64x1_t vadd_u64 (uint64x1_t, uint64x1_t)
57 @item int64x1_t vadd_s64 (int64x1_t, int64x1_t)
62 @item uint32x4_t vaddq_u32 (uint32x4_t, uint32x4_t)
63 @*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{q0}, @var{q0}, @var{q0}}
68 @item uint16x8_t vaddq_u16 (uint16x8_t, uint16x8_t)
69 @*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{q0}, @var{q0}, @var{q0}}
74 @item uint8x16_t vaddq_u8 (uint8x16_t, uint8x16_t)
75 @*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{q0}, @var{q0}, @var{q0}}
80 @item int32x4_t vaddq_s32 (int32x4_t, int32x4_t)
81 @*@emph{Form of expected instruction(s):} @code{vadd.i32 @var{q0}, @var{q0}, @var{q0}}
86 @item int16x8_t vaddq_s16 (int16x8_t, int16x8_t)
87 @*@emph{Form of expected instruction(s):} @code{vadd.i16 @var{q0}, @var{q0}, @var{q0}}
92 @item int8x16_t vaddq_s8 (int8x16_t, int8x16_t)
93 @*@emph{Form of expected instruction(s):} @code{vadd.i8 @var{q0}, @var{q0}, @var{q0}}
98 @item uint64x2_t vaddq_u64 (uint64x2_t, uint64x2_t)
99 @*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{q0}, @var{q0}, @var{q0}}
104 @item int64x2_t vaddq_s64 (int64x2_t, int64x2_t)
105 @*@emph{Form of expected instruction(s):} @code{vadd.i64 @var{q0}, @var{q0}, @var{q0}}
110 @item float32x4_t vaddq_f32 (float32x4_t, float32x4_t)
111 @*@emph{Form of expected instruction(s):} @code{vadd.f32 @var{q0}, @var{q0}, @var{q0}}
116 @item uint64x2_t vaddl_u32 (uint32x2_t, uint32x2_t)
117 @*@emph{Form of expected instruction(s):} @code{vaddl.u32 @var{q0}, @var{d0}, @var{d0}}
122 @item uint32x4_t vaddl_u16 (uint16x4_t, uint16x4_t)
123 @*@emph{Form of expected instruction(s):} @code{vaddl.u16 @var{q0}, @var{d0}, @var{d0}}
128 @item uint16x8_t vaddl_u8 (uint8x8_t, uint8x8_t)
129 @*@emph{Form of expected instruction(s):} @code{vaddl.u8 @var{q0}, @var{d0}, @var{d0}}
134 @item int64x2_t vaddl_s32 (int32x2_t, int32x2_t)
135 @*@emph{Form of expected instruction(s):} @code{vaddl.s32 @var{q0}, @var{d0}, @var{d0}}
140 @item int32x4_t vaddl_s16 (int16x4_t, int16x4_t)
141 @*@emph{Form of expected instruction(s):} @code{vaddl.s16 @var{q0}, @var{d0}, @var{d0}}
146 @item int16x8_t vaddl_s8 (int8x8_t, int8x8_t)
147 @*@emph{Form of expected instruction(s):} @code{vaddl.s8 @var{q0}, @var{d0}, @var{d0}}
152 @item uint64x2_t vaddw_u32 (uint64x2_t, uint32x2_t)
153 @*@emph{Form of expected instruction(s):} @code{vaddw.u32 @var{q0}, @var{q0}, @var{d0}}
158 @item uint32x4_t vaddw_u16 (uint32x4_t, uint16x4_t)
159 @*@emph{Form of expected instruction(s):} @code{vaddw.u16 @var{q0}, @var{q0}, @var{d0}}
164 @item uint16x8_t vaddw_u8 (uint16x8_t, uint8x8_t)
165 @*@emph{Form of expected instruction(s):} @code{vaddw.u8 @var{q0}, @var{q0}, @var{d0}}
170 @item int64x2_t vaddw_s32 (int64x2_t, int32x2_t)
171 @*@emph{Form of expected instruction(s):} @code{vaddw.s32 @var{q0}, @var{q0}, @var{d0}}
176 @item int32x4_t vaddw_s16 (int32x4_t, int16x4_t)
177 @*@emph{Form of expected instruction(s):} @code{vaddw.s16 @var{q0}, @var{q0}, @var{d0}}
182 @item int16x8_t vaddw_s8 (int16x8_t, int8x8_t)
183 @*@emph{Form of expected instruction(s):} @code{vaddw.s8 @var{q0}, @var{q0}, @var{d0}}
188 @item uint32x2_t vhadd_u32 (uint32x2_t, uint32x2_t)
189 @*@emph{Form of expected instruction(s):} @code{vhadd.u32 @var{d0}, @var{d0}, @var{d0}}
194 @item uint16x4_t vhadd_u16 (uint16x4_t, uint16x4_t)
195 @*@emph{Form of expected instruction(s):} @code{vhadd.u16 @var{d0}, @var{d0}, @var{d0}}
200 @item uint8x8_t vhadd_u8 (uint8x8_t, uint8x8_t)
201 @*@emph{Form of expected instruction(s):} @code{vhadd.u8 @var{d0}, @var{d0}, @var{d0}}
206 @item int32x2_t vhadd_s32 (int32x2_t, int32x2_t)
207 @*@emph{Form of expected instruction(s):} @code{vhadd.s32 @var{d0}, @var{d0}, @var{d0}}
212 @item int16x4_t vhadd_s16 (int16x4_t, int16x4_t)
213 @*@emph{Form of expected instruction(s):} @code{vhadd.s16 @var{d0}, @var{d0}, @var{d0}}
218 @item int8x8_t vhadd_s8 (int8x8_t, int8x8_t)
219 @*@emph{Form of expected instruction(s):} @code{vhadd.s8 @var{d0}, @var{d0}, @var{d0}}
224 @item uint32x4_t vhaddq_u32 (uint32x4_t, uint32x4_t)
225 @*@emph{Form of expected instruction(s):} @code{vhadd.u32 @var{q0}, @var{q0}, @var{q0}}
230 @item uint16x8_t vhaddq_u16 (uint16x8_t, uint16x8_t)
231 @*@emph{Form of expected instruction(s):} @code{vhadd.u16 @var{q0}, @var{q0}, @var{q0}}
236 @item uint8x16_t vhaddq_u8 (uint8x16_t, uint8x16_t)
237 @*@emph{Form of expected instruction(s):} @code{vhadd.u8 @var{q0}, @var{q0}, @var{q0}}
242 @item int32x4_t vhaddq_s32 (int32x4_t, int32x4_t)
243 @*@emph{Form of expected instruction(s):} @code{vhadd.s32 @var{q0}, @var{q0}, @var{q0}}
248 @item int16x8_t vhaddq_s16 (int16x8_t, int16x8_t)
249 @*@emph{Form of expected instruction(s):} @code{vhadd.s16 @var{q0}, @var{q0}, @var{q0}}
254 @item int8x16_t vhaddq_s8 (int8x16_t, int8x16_t)
255 @*@emph{Form of expected instruction(s):} @code{vhadd.s8 @var{q0}, @var{q0}, @var{q0}}
260 @item uint32x2_t vrhadd_u32 (uint32x2_t, uint32x2_t)
261 @*@emph{Form of expected instruction(s):} @code{vrhadd.u32 @var{d0}, @var{d0}, @var{d0}}
266 @item uint16x4_t vrhadd_u16 (uint16x4_t, uint16x4_t)
267 @*@emph{Form of expected instruction(s):} @code{vrhadd.u16 @var{d0}, @var{d0}, @var{d0}}
272 @item uint8x8_t vrhadd_u8 (uint8x8_t, uint8x8_t)
273 @*@emph{Form of expected instruction(s):} @code{vrhadd.u8 @var{d0}, @var{d0}, @var{d0}}
278 @item int32x2_t vrhadd_s32 (int32x2_t, int32x2_t)
279 @*@emph{Form of expected instruction(s):} @code{vrhadd.s32 @var{d0}, @var{d0}, @var{d0}}
284 @item int16x4_t vrhadd_s16 (int16x4_t, int16x4_t)
285 @*@emph{Form of expected instruction(s):} @code{vrhadd.s16 @var{d0}, @var{d0}, @var{d0}}
290 @item int8x8_t vrhadd_s8 (int8x8_t, int8x8_t)
291 @*@emph{Form of expected instruction(s):} @code{vrhadd.s8 @var{d0}, @var{d0}, @var{d0}}
296 @item uint32x4_t vrhaddq_u32 (uint32x4_t, uint32x4_t)
297 @*@emph{Form of expected instruction(s):} @code{vrhadd.u32 @var{q0}, @var{q0}, @var{q0}}
302 @item uint16x8_t vrhaddq_u16 (uint16x8_t, uint16x8_t)
303 @*@emph{Form of expected instruction(s):} @code{vrhadd.u16 @var{q0}, @var{q0}, @var{q0}}
308 @item uint8x16_t vrhaddq_u8 (uint8x16_t, uint8x16_t)
309 @*@emph{Form of expected instruction(s):} @code{vrhadd.u8 @var{q0}, @var{q0}, @var{q0}}
314 @item int32x4_t vrhaddq_s32 (int32x4_t, int32x4_t)
315 @*@emph{Form of expected instruction(s):} @code{vrhadd.s32 @var{q0}, @var{q0}, @var{q0}}
320 @item int16x8_t vrhaddq_s16 (int16x8_t, int16x8_t)
321 @*@emph{Form of expected instruction(s):} @code{vrhadd.s16 @var{q0}, @var{q0}, @var{q0}}
326 @item int8x16_t vrhaddq_s8 (int8x16_t, int8x16_t)
327 @*@emph{Form of expected instruction(s):} @code{vrhadd.s8 @var{q0}, @var{q0}, @var{q0}}
332 @item uint32x2_t vqadd_u32 (uint32x2_t, uint32x2_t)
333 @*@emph{Form of expected instruction(s):} @code{vqadd.u32 @var{d0}, @var{d0}, @var{d0}}
338 @item uint16x4_t vqadd_u16 (uint16x4_t, uint16x4_t)
339 @*@emph{Form of expected instruction(s):} @code{vqadd.u16 @var{d0}, @var{d0}, @var{d0}}
344 @item uint8x8_t vqadd_u8 (uint8x8_t, uint8x8_t)
345 @*@emph{Form of expected instruction(s):} @code{vqadd.u8 @var{d0}, @var{d0}, @var{d0}}
350 @item int32x2_t vqadd_s32 (int32x2_t, int32x2_t)
351 @*@emph{Form of expected instruction(s):} @code{vqadd.s32 @var{d0}, @var{d0}, @var{d0}}
356 @item int16x4_t vqadd_s16 (int16x4_t, int16x4_t)
357 @*@emph{Form of expected instruction(s):} @code{vqadd.s16 @var{d0}, @var{d0}, @var{d0}}
362 @item int8x8_t vqadd_s8 (int8x8_t, int8x8_t)
363 @*@emph{Form of expected instruction(s):} @code{vqadd.s8 @var{d0}, @var{d0}, @var{d0}}
368 @item uint64x1_t vqadd_u64 (uint64x1_t, uint64x1_t)
369 @*@emph{Form of expected instruction(s):} @code{vqadd.u64 @var{d0}, @var{d0}, @var{d0}}
374 @item int64x1_t vqadd_s64 (int64x1_t, int64x1_t)
375 @*@emph{Form of expected instruction(s):} @code{vqadd.s64 @var{d0}, @var{d0}, @var{d0}}
380 @item uint32x4_t vqaddq_u32 (uint32x4_t, uint32x4_t)
381 @*@emph{Form of expected instruction(s):} @code{vqadd.u32 @var{q0}, @var{q0}, @var{q0}}
386 @item uint16x8_t vqaddq_u16 (uint16x8_t, uint16x8_t)
387 @*@emph{Form of expected instruction(s):} @code{vqadd.u16 @var{q0}, @var{q0}, @var{q0}}
392 @item uint8x16_t vqaddq_u8 (uint8x16_t, uint8x16_t)
393 @*@emph{Form of expected instruction(s):} @code{vqadd.u8 @var{q0}, @var{q0}, @var{q0}}
398 @item int32x4_t vqaddq_s32 (int32x4_t, int32x4_t)
399 @*@emph{Form of expected instruction(s):} @code{vqadd.s32 @var{q0}, @var{q0}, @var{q0}}
404 @item int16x8_t vqaddq_s16 (int16x8_t, int16x8_t)
405 @*@emph{Form of expected instruction(s):} @code{vqadd.s16 @var{q0}, @var{q0}, @var{q0}}
410 @item int8x16_t vqaddq_s8 (int8x16_t, int8x16_t)
411 @*@emph{Form of expected instruction(s):} @code{vqadd.s8 @var{q0}, @var{q0}, @var{q0}}
416 @item uint64x2_t vqaddq_u64 (uint64x2_t, uint64x2_t)
417 @*@emph{Form of expected instruction(s):} @code{vqadd.u64 @var{q0}, @var{q0}, @var{q0}}
422 @item int64x2_t vqaddq_s64 (int64x2_t, int64x2_t)
423 @*@emph{Form of expected instruction(s):} @code{vqadd.s64 @var{q0}, @var{q0}, @var{q0}}
428 @item uint32x2_t vaddhn_u64 (uint64x2_t, uint64x2_t)
429 @*@emph{Form of expected instruction(s):} @code{vaddhn.i64 @var{d0}, @var{q0}, @var{q0}}
434 @item uint16x4_t vaddhn_u32 (uint32x4_t, uint32x4_t)
435 @*@emph{Form of expected instruction(s):} @code{vaddhn.i32 @var{d0}, @var{q0}, @var{q0}}
440 @item uint8x8_t vaddhn_u16 (uint16x8_t, uint16x8_t)
441 @*@emph{Form of expected instruction(s):} @code{vaddhn.i16 @var{d0}, @var{q0}, @var{q0}}
446 @item int32x2_t vaddhn_s64 (int64x2_t, int64x2_t)
447 @*@emph{Form of expected instruction(s):} @code{vaddhn.i64 @var{d0}, @var{q0}, @var{q0}}
452 @item int16x4_t vaddhn_s32 (int32x4_t, int32x4_t)
453 @*@emph{Form of expected instruction(s):} @code{vaddhn.i32 @var{d0}, @var{q0}, @var{q0}}
458 @item int8x8_t vaddhn_s16 (int16x8_t, int16x8_t)
459 @*@emph{Form of expected instruction(s):} @code{vaddhn.i16 @var{d0}, @var{q0}, @var{q0}}
464 @item uint32x2_t vraddhn_u64 (uint64x2_t, uint64x2_t)
465 @*@emph{Form of expected instruction(s):} @code{vraddhn.i64 @var{d0}, @var{q0}, @var{q0}}
470 @item uint16x4_t vraddhn_u32 (uint32x4_t, uint32x4_t)
471 @*@emph{Form of expected instruction(s):} @code{vraddhn.i32 @var{d0}, @var{q0}, @var{q0}}
476 @item uint8x8_t vraddhn_u16 (uint16x8_t, uint16x8_t)
477 @*@emph{Form of expected instruction(s):} @code{vraddhn.i16 @var{d0}, @var{q0}, @var{q0}}
482 @item int32x2_t vraddhn_s64 (int64x2_t, int64x2_t)
483 @*@emph{Form of expected instruction(s):} @code{vraddhn.i64 @var{d0}, @var{q0}, @var{q0}}
488 @item int16x4_t vraddhn_s32 (int32x4_t, int32x4_t)
489 @*@emph{Form of expected instruction(s):} @code{vraddhn.i32 @var{d0}, @var{q0}, @var{q0}}
494 @item int8x8_t vraddhn_s16 (int16x8_t, int16x8_t)
495 @*@emph{Form of expected instruction(s):} @code{vraddhn.i16 @var{d0}, @var{q0}, @var{q0}}
501 @subsubsection Multiplication
504 @item uint32x2_t vmul_u32 (uint32x2_t, uint32x2_t)
505 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}}
510 @item uint16x4_t vmul_u16 (uint16x4_t, uint16x4_t)
511 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}}
516 @item uint8x8_t vmul_u8 (uint8x8_t, uint8x8_t)
517 @*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{d0}, @var{d0}, @var{d0}}
522 @item int32x2_t vmul_s32 (int32x2_t, int32x2_t)
523 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}}
528 @item int16x4_t vmul_s16 (int16x4_t, int16x4_t)
529 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}}
534 @item int8x8_t vmul_s8 (int8x8_t, int8x8_t)
535 @*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{d0}, @var{d0}, @var{d0}}
540 @item float32x2_t vmul_f32 (float32x2_t, float32x2_t)
541 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}}
546 @item poly8x8_t vmul_p8 (poly8x8_t, poly8x8_t)
547 @*@emph{Form of expected instruction(s):} @code{vmul.p8 @var{d0}, @var{d0}, @var{d0}}
552 @item uint32x4_t vmulq_u32 (uint32x4_t, uint32x4_t)
553 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{q0}}
558 @item uint16x8_t vmulq_u16 (uint16x8_t, uint16x8_t)
559 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{q0}}
564 @item uint8x16_t vmulq_u8 (uint8x16_t, uint8x16_t)
565 @*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{q0}, @var{q0}, @var{q0}}
570 @item int32x4_t vmulq_s32 (int32x4_t, int32x4_t)
571 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{q0}}
576 @item int16x8_t vmulq_s16 (int16x8_t, int16x8_t)
577 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{q0}}
582 @item int8x16_t vmulq_s8 (int8x16_t, int8x16_t)
583 @*@emph{Form of expected instruction(s):} @code{vmul.i8 @var{q0}, @var{q0}, @var{q0}}
588 @item float32x4_t vmulq_f32 (float32x4_t, float32x4_t)
589 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{q0}}
594 @item poly8x16_t vmulq_p8 (poly8x16_t, poly8x16_t)
595 @*@emph{Form of expected instruction(s):} @code{vmul.p8 @var{q0}, @var{q0}, @var{q0}}
600 @item int32x2_t vqdmulh_s32 (int32x2_t, int32x2_t)
601 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}}
606 @item int16x4_t vqdmulh_s16 (int16x4_t, int16x4_t)
607 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}}
612 @item int32x4_t vqdmulhq_s32 (int32x4_t, int32x4_t)
613 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{q0}}
618 @item int16x8_t vqdmulhq_s16 (int16x8_t, int16x8_t)
619 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{q0}}
624 @item int32x2_t vqrdmulh_s32 (int32x2_t, int32x2_t)
625 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}}
630 @item int16x4_t vqrdmulh_s16 (int16x4_t, int16x4_t)
631 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}}
636 @item int32x4_t vqrdmulhq_s32 (int32x4_t, int32x4_t)
637 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{q0}}
642 @item int16x8_t vqrdmulhq_s16 (int16x8_t, int16x8_t)
643 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{q0}}
648 @item uint64x2_t vmull_u32 (uint32x2_t, uint32x2_t)
649 @*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}}
654 @item uint32x4_t vmull_u16 (uint16x4_t, uint16x4_t)
655 @*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}}
660 @item uint16x8_t vmull_u8 (uint8x8_t, uint8x8_t)
661 @*@emph{Form of expected instruction(s):} @code{vmull.u8 @var{q0}, @var{d0}, @var{d0}}
666 @item int64x2_t vmull_s32 (int32x2_t, int32x2_t)
667 @*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}}
672 @item int32x4_t vmull_s16 (int16x4_t, int16x4_t)
673 @*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}}
678 @item int16x8_t vmull_s8 (int8x8_t, int8x8_t)
679 @*@emph{Form of expected instruction(s):} @code{vmull.s8 @var{q0}, @var{d0}, @var{d0}}
684 @item poly16x8_t vmull_p8 (poly8x8_t, poly8x8_t)
685 @*@emph{Form of expected instruction(s):} @code{vmull.p8 @var{q0}, @var{d0}, @var{d0}}
690 @item int64x2_t vqdmull_s32 (int32x2_t, int32x2_t)
691 @*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}}
696 @item int32x4_t vqdmull_s16 (int16x4_t, int16x4_t)
697 @*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}}
703 @subsubsection Multiply-accumulate
706 @item uint32x2_t vmla_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
707 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}}
712 @item uint16x4_t vmla_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
713 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}}
718 @item uint8x8_t vmla_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
719 @*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{d0}, @var{d0}, @var{d0}}
724 @item int32x2_t vmla_s32 (int32x2_t, int32x2_t, int32x2_t)
725 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}}
730 @item int16x4_t vmla_s16 (int16x4_t, int16x4_t, int16x4_t)
731 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}}
736 @item int8x8_t vmla_s8 (int8x8_t, int8x8_t, int8x8_t)
737 @*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{d0}, @var{d0}, @var{d0}}
742 @item float32x2_t vmla_f32 (float32x2_t, float32x2_t, float32x2_t)
743 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}}
748 @item uint32x4_t vmlaq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
749 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{q0}}
754 @item uint16x8_t vmlaq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
755 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{q0}}
760 @item uint8x16_t vmlaq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
761 @*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{q0}, @var{q0}, @var{q0}}
766 @item int32x4_t vmlaq_s32 (int32x4_t, int32x4_t, int32x4_t)
767 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{q0}}
772 @item int16x8_t vmlaq_s16 (int16x8_t, int16x8_t, int16x8_t)
773 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{q0}}
778 @item int8x16_t vmlaq_s8 (int8x16_t, int8x16_t, int8x16_t)
779 @*@emph{Form of expected instruction(s):} @code{vmla.i8 @var{q0}, @var{q0}, @var{q0}}
784 @item float32x4_t vmlaq_f32 (float32x4_t, float32x4_t, float32x4_t)
785 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{q0}}
790 @item uint64x2_t vmlal_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
791 @*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}}
796 @item uint32x4_t vmlal_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
797 @*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}}
802 @item uint16x8_t vmlal_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
803 @*@emph{Form of expected instruction(s):} @code{vmlal.u8 @var{q0}, @var{d0}, @var{d0}}
808 @item int64x2_t vmlal_s32 (int64x2_t, int32x2_t, int32x2_t)
809 @*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}}
814 @item int32x4_t vmlal_s16 (int32x4_t, int16x4_t, int16x4_t)
815 @*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}}
820 @item int16x8_t vmlal_s8 (int16x8_t, int8x8_t, int8x8_t)
821 @*@emph{Form of expected instruction(s):} @code{vmlal.s8 @var{q0}, @var{d0}, @var{d0}}
826 @item int64x2_t vqdmlal_s32 (int64x2_t, int32x2_t, int32x2_t)
827 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}}
832 @item int32x4_t vqdmlal_s16 (int32x4_t, int16x4_t, int16x4_t)
833 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}}
839 @subsubsection Multiply-subtract
842 @item uint32x2_t vmls_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
843 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}}
848 @item uint16x4_t vmls_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
849 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}}
854 @item uint8x8_t vmls_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
855 @*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{d0}, @var{d0}, @var{d0}}
860 @item int32x2_t vmls_s32 (int32x2_t, int32x2_t, int32x2_t)
861 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}}
866 @item int16x4_t vmls_s16 (int16x4_t, int16x4_t, int16x4_t)
867 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}}
872 @item int8x8_t vmls_s8 (int8x8_t, int8x8_t, int8x8_t)
873 @*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{d0}, @var{d0}, @var{d0}}
878 @item float32x2_t vmls_f32 (float32x2_t, float32x2_t, float32x2_t)
879 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}}
884 @item uint32x4_t vmlsq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
885 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{q0}}
890 @item uint16x8_t vmlsq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
891 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{q0}}
896 @item uint8x16_t vmlsq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
897 @*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{q0}, @var{q0}, @var{q0}}
902 @item int32x4_t vmlsq_s32 (int32x4_t, int32x4_t, int32x4_t)
903 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{q0}}
908 @item int16x8_t vmlsq_s16 (int16x8_t, int16x8_t, int16x8_t)
909 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{q0}}
914 @item int8x16_t vmlsq_s8 (int8x16_t, int8x16_t, int8x16_t)
915 @*@emph{Form of expected instruction(s):} @code{vmls.i8 @var{q0}, @var{q0}, @var{q0}}
920 @item float32x4_t vmlsq_f32 (float32x4_t, float32x4_t, float32x4_t)
921 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{q0}}
926 @item uint64x2_t vmlsl_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
927 @*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}}
932 @item uint32x4_t vmlsl_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
933 @*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}}
938 @item uint16x8_t vmlsl_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
939 @*@emph{Form of expected instruction(s):} @code{vmlsl.u8 @var{q0}, @var{d0}, @var{d0}}
944 @item int64x2_t vmlsl_s32 (int64x2_t, int32x2_t, int32x2_t)
945 @*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}}
950 @item int32x4_t vmlsl_s16 (int32x4_t, int16x4_t, int16x4_t)
951 @*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}}
956 @item int16x8_t vmlsl_s8 (int16x8_t, int8x8_t, int8x8_t)
957 @*@emph{Form of expected instruction(s):} @code{vmlsl.s8 @var{q0}, @var{d0}, @var{d0}}
962 @item int64x2_t vqdmlsl_s32 (int64x2_t, int32x2_t, int32x2_t)
963 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}}
968 @item int32x4_t vqdmlsl_s16 (int32x4_t, int16x4_t, int16x4_t)
969 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}}
975 @subsubsection Subtraction
978 @item uint32x2_t vsub_u32 (uint32x2_t, uint32x2_t)
979 @*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{d0}, @var{d0}, @var{d0}}
984 @item uint16x4_t vsub_u16 (uint16x4_t, uint16x4_t)
985 @*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{d0}, @var{d0}, @var{d0}}
990 @item uint8x8_t vsub_u8 (uint8x8_t, uint8x8_t)
991 @*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{d0}, @var{d0}, @var{d0}}
996 @item int32x2_t vsub_s32 (int32x2_t, int32x2_t)
997 @*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{d0}, @var{d0}, @var{d0}}
1002 @item int16x4_t vsub_s16 (int16x4_t, int16x4_t)
1003 @*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{d0}, @var{d0}, @var{d0}}
1008 @item int8x8_t vsub_s8 (int8x8_t, int8x8_t)
1009 @*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{d0}, @var{d0}, @var{d0}}
1014 @item float32x2_t vsub_f32 (float32x2_t, float32x2_t)
1015 @*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{d0}, @var{d0}, @var{d0}}
1020 @item uint64x1_t vsub_u64 (uint64x1_t, uint64x1_t)
1025 @item int64x1_t vsub_s64 (int64x1_t, int64x1_t)
1030 @item uint32x4_t vsubq_u32 (uint32x4_t, uint32x4_t)
1031 @*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{q0}, @var{q0}, @var{q0}}
1036 @item uint16x8_t vsubq_u16 (uint16x8_t, uint16x8_t)
1037 @*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{q0}, @var{q0}, @var{q0}}
1042 @item uint8x16_t vsubq_u8 (uint8x16_t, uint8x16_t)
1043 @*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{q0}, @var{q0}, @var{q0}}
1048 @item int32x4_t vsubq_s32 (int32x4_t, int32x4_t)
1049 @*@emph{Form of expected instruction(s):} @code{vsub.i32 @var{q0}, @var{q0}, @var{q0}}
1054 @item int16x8_t vsubq_s16 (int16x8_t, int16x8_t)
1055 @*@emph{Form of expected instruction(s):} @code{vsub.i16 @var{q0}, @var{q0}, @var{q0}}
1060 @item int8x16_t vsubq_s8 (int8x16_t, int8x16_t)
1061 @*@emph{Form of expected instruction(s):} @code{vsub.i8 @var{q0}, @var{q0}, @var{q0}}
1066 @item uint64x2_t vsubq_u64 (uint64x2_t, uint64x2_t)
1067 @*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{q0}, @var{q0}, @var{q0}}
1072 @item int64x2_t vsubq_s64 (int64x2_t, int64x2_t)
1073 @*@emph{Form of expected instruction(s):} @code{vsub.i64 @var{q0}, @var{q0}, @var{q0}}
1078 @item float32x4_t vsubq_f32 (float32x4_t, float32x4_t)
1079 @*@emph{Form of expected instruction(s):} @code{vsub.f32 @var{q0}, @var{q0}, @var{q0}}
1084 @item uint64x2_t vsubl_u32 (uint32x2_t, uint32x2_t)
1085 @*@emph{Form of expected instruction(s):} @code{vsubl.u32 @var{q0}, @var{d0}, @var{d0}}
1090 @item uint32x4_t vsubl_u16 (uint16x4_t, uint16x4_t)
1091 @*@emph{Form of expected instruction(s):} @code{vsubl.u16 @var{q0}, @var{d0}, @var{d0}}
1096 @item uint16x8_t vsubl_u8 (uint8x8_t, uint8x8_t)
1097 @*@emph{Form of expected instruction(s):} @code{vsubl.u8 @var{q0}, @var{d0}, @var{d0}}
1102 @item int64x2_t vsubl_s32 (int32x2_t, int32x2_t)
1103 @*@emph{Form of expected instruction(s):} @code{vsubl.s32 @var{q0}, @var{d0}, @var{d0}}
1108 @item int32x4_t vsubl_s16 (int16x4_t, int16x4_t)
1109 @*@emph{Form of expected instruction(s):} @code{vsubl.s16 @var{q0}, @var{d0}, @var{d0}}
1114 @item int16x8_t vsubl_s8 (int8x8_t, int8x8_t)
1115 @*@emph{Form of expected instruction(s):} @code{vsubl.s8 @var{q0}, @var{d0}, @var{d0}}
1120 @item uint64x2_t vsubw_u32 (uint64x2_t, uint32x2_t)
1121 @*@emph{Form of expected instruction(s):} @code{vsubw.u32 @var{q0}, @var{q0}, @var{d0}}
1126 @item uint32x4_t vsubw_u16 (uint32x4_t, uint16x4_t)
1127 @*@emph{Form of expected instruction(s):} @code{vsubw.u16 @var{q0}, @var{q0}, @var{d0}}
1132 @item uint16x8_t vsubw_u8 (uint16x8_t, uint8x8_t)
1133 @*@emph{Form of expected instruction(s):} @code{vsubw.u8 @var{q0}, @var{q0}, @var{d0}}
1138 @item int64x2_t vsubw_s32 (int64x2_t, int32x2_t)
1139 @*@emph{Form of expected instruction(s):} @code{vsubw.s32 @var{q0}, @var{q0}, @var{d0}}
1144 @item int32x4_t vsubw_s16 (int32x4_t, int16x4_t)
1145 @*@emph{Form of expected instruction(s):} @code{vsubw.s16 @var{q0}, @var{q0}, @var{d0}}
1150 @item int16x8_t vsubw_s8 (int16x8_t, int8x8_t)
1151 @*@emph{Form of expected instruction(s):} @code{vsubw.s8 @var{q0}, @var{q0}, @var{d0}}
1156 @item uint32x2_t vhsub_u32 (uint32x2_t, uint32x2_t)
1157 @*@emph{Form of expected instruction(s):} @code{vhsub.u32 @var{d0}, @var{d0}, @var{d0}}
1162 @item uint16x4_t vhsub_u16 (uint16x4_t, uint16x4_t)
1163 @*@emph{Form of expected instruction(s):} @code{vhsub.u16 @var{d0}, @var{d0}, @var{d0}}
1168 @item uint8x8_t vhsub_u8 (uint8x8_t, uint8x8_t)
1169 @*@emph{Form of expected instruction(s):} @code{vhsub.u8 @var{d0}, @var{d0}, @var{d0}}
1174 @item int32x2_t vhsub_s32 (int32x2_t, int32x2_t)
1175 @*@emph{Form of expected instruction(s):} @code{vhsub.s32 @var{d0}, @var{d0}, @var{d0}}
1180 @item int16x4_t vhsub_s16 (int16x4_t, int16x4_t)
1181 @*@emph{Form of expected instruction(s):} @code{vhsub.s16 @var{d0}, @var{d0}, @var{d0}}
1186 @item int8x8_t vhsub_s8 (int8x8_t, int8x8_t)
1187 @*@emph{Form of expected instruction(s):} @code{vhsub.s8 @var{d0}, @var{d0}, @var{d0}}
1192 @item uint32x4_t vhsubq_u32 (uint32x4_t, uint32x4_t)
1193 @*@emph{Form of expected instruction(s):} @code{vhsub.u32 @var{q0}, @var{q0}, @var{q0}}
1198 @item uint16x8_t vhsubq_u16 (uint16x8_t, uint16x8_t)
1199 @*@emph{Form of expected instruction(s):} @code{vhsub.u16 @var{q0}, @var{q0}, @var{q0}}
1204 @item uint8x16_t vhsubq_u8 (uint8x16_t, uint8x16_t)
1205 @*@emph{Form of expected instruction(s):} @code{vhsub.u8 @var{q0}, @var{q0}, @var{q0}}
1210 @item int32x4_t vhsubq_s32 (int32x4_t, int32x4_t)
1211 @*@emph{Form of expected instruction(s):} @code{vhsub.s32 @var{q0}, @var{q0}, @var{q0}}
1216 @item int16x8_t vhsubq_s16 (int16x8_t, int16x8_t)
1217 @*@emph{Form of expected instruction(s):} @code{vhsub.s16 @var{q0}, @var{q0}, @var{q0}}
1222 @item int8x16_t vhsubq_s8 (int8x16_t, int8x16_t)
1223 @*@emph{Form of expected instruction(s):} @code{vhsub.s8 @var{q0}, @var{q0}, @var{q0}}
1228 @item uint32x2_t vqsub_u32 (uint32x2_t, uint32x2_t)
1229 @*@emph{Form of expected instruction(s):} @code{vqsub.u32 @var{d0}, @var{d0}, @var{d0}}
1234 @item uint16x4_t vqsub_u16 (uint16x4_t, uint16x4_t)
1235 @*@emph{Form of expected instruction(s):} @code{vqsub.u16 @var{d0}, @var{d0}, @var{d0}}
1240 @item uint8x8_t vqsub_u8 (uint8x8_t, uint8x8_t)
1241 @*@emph{Form of expected instruction(s):} @code{vqsub.u8 @var{d0}, @var{d0}, @var{d0}}
1246 @item int32x2_t vqsub_s32 (int32x2_t, int32x2_t)
1247 @*@emph{Form of expected instruction(s):} @code{vqsub.s32 @var{d0}, @var{d0}, @var{d0}}
1252 @item int16x4_t vqsub_s16 (int16x4_t, int16x4_t)
1253 @*@emph{Form of expected instruction(s):} @code{vqsub.s16 @var{d0}, @var{d0}, @var{d0}}
1258 @item int8x8_t vqsub_s8 (int8x8_t, int8x8_t)
1259 @*@emph{Form of expected instruction(s):} @code{vqsub.s8 @var{d0}, @var{d0}, @var{d0}}
1264 @item uint64x1_t vqsub_u64 (uint64x1_t, uint64x1_t)
1265 @*@emph{Form of expected instruction(s):} @code{vqsub.u64 @var{d0}, @var{d0}, @var{d0}}
1270 @item int64x1_t vqsub_s64 (int64x1_t, int64x1_t)
1271 @*@emph{Form of expected instruction(s):} @code{vqsub.s64 @var{d0}, @var{d0}, @var{d0}}
1276 @item uint32x4_t vqsubq_u32 (uint32x4_t, uint32x4_t)
1277 @*@emph{Form of expected instruction(s):} @code{vqsub.u32 @var{q0}, @var{q0}, @var{q0}}
1282 @item uint16x8_t vqsubq_u16 (uint16x8_t, uint16x8_t)
1283 @*@emph{Form of expected instruction(s):} @code{vqsub.u16 @var{q0}, @var{q0}, @var{q0}}
1288 @item uint8x16_t vqsubq_u8 (uint8x16_t, uint8x16_t)
1289 @*@emph{Form of expected instruction(s):} @code{vqsub.u8 @var{q0}, @var{q0}, @var{q0}}
1294 @item int32x4_t vqsubq_s32 (int32x4_t, int32x4_t)
1295 @*@emph{Form of expected instruction(s):} @code{vqsub.s32 @var{q0}, @var{q0}, @var{q0}}
1300 @item int16x8_t vqsubq_s16 (int16x8_t, int16x8_t)
1301 @*@emph{Form of expected instruction(s):} @code{vqsub.s16 @var{q0}, @var{q0}, @var{q0}}
1306 @item int8x16_t vqsubq_s8 (int8x16_t, int8x16_t)
1307 @*@emph{Form of expected instruction(s):} @code{vqsub.s8 @var{q0}, @var{q0}, @var{q0}}
1312 @item uint64x2_t vqsubq_u64 (uint64x2_t, uint64x2_t)
1313 @*@emph{Form of expected instruction(s):} @code{vqsub.u64 @var{q0}, @var{q0}, @var{q0}}
1318 @item int64x2_t vqsubq_s64 (int64x2_t, int64x2_t)
1319 @*@emph{Form of expected instruction(s):} @code{vqsub.s64 @var{q0}, @var{q0}, @var{q0}}
1324 @item uint32x2_t vsubhn_u64 (uint64x2_t, uint64x2_t)
1325 @*@emph{Form of expected instruction(s):} @code{vsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1330 @item uint16x4_t vsubhn_u32 (uint32x4_t, uint32x4_t)
1331 @*@emph{Form of expected instruction(s):} @code{vsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1336 @item uint8x8_t vsubhn_u16 (uint16x8_t, uint16x8_t)
1337 @*@emph{Form of expected instruction(s):} @code{vsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1342 @item int32x2_t vsubhn_s64 (int64x2_t, int64x2_t)
1343 @*@emph{Form of expected instruction(s):} @code{vsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1348 @item int16x4_t vsubhn_s32 (int32x4_t, int32x4_t)
1349 @*@emph{Form of expected instruction(s):} @code{vsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1354 @item int8x8_t vsubhn_s16 (int16x8_t, int16x8_t)
1355 @*@emph{Form of expected instruction(s):} @code{vsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1360 @item uint32x2_t vrsubhn_u64 (uint64x2_t, uint64x2_t)
1361 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1366 @item uint16x4_t vrsubhn_u32 (uint32x4_t, uint32x4_t)
1367 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1372 @item uint8x8_t vrsubhn_u16 (uint16x8_t, uint16x8_t)
1373 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1378 @item int32x2_t vrsubhn_s64 (int64x2_t, int64x2_t)
1379 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i64 @var{d0}, @var{q0}, @var{q0}}
1384 @item int16x4_t vrsubhn_s32 (int32x4_t, int32x4_t)
1385 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i32 @var{d0}, @var{q0}, @var{q0}}
1390 @item int8x8_t vrsubhn_s16 (int16x8_t, int16x8_t)
1391 @*@emph{Form of expected instruction(s):} @code{vrsubhn.i16 @var{d0}, @var{q0}, @var{q0}}
1397 @subsubsection Comparison (equal-to)
1400 @item uint32x2_t vceq_u32 (uint32x2_t, uint32x2_t)
1401 @*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{d0}, @var{d0}, @var{d0}}
1406 @item uint16x4_t vceq_u16 (uint16x4_t, uint16x4_t)
1407 @*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{d0}, @var{d0}, @var{d0}}
1412 @item uint8x8_t vceq_u8 (uint8x8_t, uint8x8_t)
1413 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
1418 @item uint32x2_t vceq_s32 (int32x2_t, int32x2_t)
1419 @*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{d0}, @var{d0}, @var{d0}}
1424 @item uint16x4_t vceq_s16 (int16x4_t, int16x4_t)
1425 @*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{d0}, @var{d0}, @var{d0}}
1430 @item uint8x8_t vceq_s8 (int8x8_t, int8x8_t)
1431 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
1436 @item uint32x2_t vceq_f32 (float32x2_t, float32x2_t)
1437 @*@emph{Form of expected instruction(s):} @code{vceq.f32 @var{d0}, @var{d0}, @var{d0}}
1442 @item uint8x8_t vceq_p8 (poly8x8_t, poly8x8_t)
1443 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{d0}, @var{d0}, @var{d0}}
1448 @item uint32x4_t vceqq_u32 (uint32x4_t, uint32x4_t)
1449 @*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{q0}, @var{q0}, @var{q0}}
1454 @item uint16x8_t vceqq_u16 (uint16x8_t, uint16x8_t)
1455 @*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{q0}, @var{q0}, @var{q0}}
1460 @item uint8x16_t vceqq_u8 (uint8x16_t, uint8x16_t)
1461 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
1466 @item uint32x4_t vceqq_s32 (int32x4_t, int32x4_t)
1467 @*@emph{Form of expected instruction(s):} @code{vceq.i32 @var{q0}, @var{q0}, @var{q0}}
1472 @item uint16x8_t vceqq_s16 (int16x8_t, int16x8_t)
1473 @*@emph{Form of expected instruction(s):} @code{vceq.i16 @var{q0}, @var{q0}, @var{q0}}
1478 @item uint8x16_t vceqq_s8 (int8x16_t, int8x16_t)
1479 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
1484 @item uint32x4_t vceqq_f32 (float32x4_t, float32x4_t)
1485 @*@emph{Form of expected instruction(s):} @code{vceq.f32 @var{q0}, @var{q0}, @var{q0}}
1490 @item uint8x16_t vceqq_p8 (poly8x16_t, poly8x16_t)
1491 @*@emph{Form of expected instruction(s):} @code{vceq.i8 @var{q0}, @var{q0}, @var{q0}}
1497 @subsubsection Comparison (greater-than-or-equal-to)
1500 @item uint32x2_t vcge_u32 (uint32x2_t, uint32x2_t)
1501 @*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}}
1506 @item uint16x4_t vcge_u16 (uint16x4_t, uint16x4_t)
1507 @*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}}
1512 @item uint8x8_t vcge_u8 (uint8x8_t, uint8x8_t)
1513 @*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}}
1518 @item uint32x2_t vcge_s32 (int32x2_t, int32x2_t)
1519 @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}}
1524 @item uint16x4_t vcge_s16 (int16x4_t, int16x4_t)
1525 @*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{d0}, @var{d0}, @var{d0}}
1530 @item uint8x8_t vcge_s8 (int8x8_t, int8x8_t)
1531 @*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{d0}, @var{d0}, @var{d0}}
1536 @item uint32x2_t vcge_f32 (float32x2_t, float32x2_t)
1537 @*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{d0}, @var{d0}, @var{d0}}
1542 @item uint32x4_t vcgeq_u32 (uint32x4_t, uint32x4_t)
1543 @*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}}
1548 @item uint16x8_t vcgeq_u16 (uint16x8_t, uint16x8_t)
1549 @*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}}
1554 @item uint8x16_t vcgeq_u8 (uint8x16_t, uint8x16_t)
1555 @*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}}
1560 @item uint32x4_t vcgeq_s32 (int32x4_t, int32x4_t)
1561 @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{q0}, @var{q0}, @var{q0}}
1566 @item uint16x8_t vcgeq_s16 (int16x8_t, int16x8_t)
1567 @*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{q0}, @var{q0}, @var{q0}}
1572 @item uint8x16_t vcgeq_s8 (int8x16_t, int8x16_t)
1573 @*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{q0}, @var{q0}, @var{q0}}
1578 @item uint32x4_t vcgeq_f32 (float32x4_t, float32x4_t)
1579 @*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{q0}, @var{q0}, @var{q0}}
1585 @subsubsection Comparison (less-than-or-equal-to)
1588 @item uint32x2_t vcle_u32 (uint32x2_t, uint32x2_t)
1589 @*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{d0}, @var{d0}, @var{d0}}
1594 @item uint16x4_t vcle_u16 (uint16x4_t, uint16x4_t)
1595 @*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{d0}, @var{d0}, @var{d0}}
1600 @item uint8x8_t vcle_u8 (uint8x8_t, uint8x8_t)
1601 @*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{d0}, @var{d0}, @var{d0}}
1606 @item uint32x2_t vcle_s32 (int32x2_t, int32x2_t)
1607 @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{d0}, @var{d0}, @var{d0}}
1612 @item uint16x4_t vcle_s16 (int16x4_t, int16x4_t)
1613 @*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{d0}, @var{d0}, @var{d0}}
1618 @item uint8x8_t vcle_s8 (int8x8_t, int8x8_t)
1619 @*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{d0}, @var{d0}, @var{d0}}
1624 @item uint32x2_t vcle_f32 (float32x2_t, float32x2_t)
1625 @*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{d0}, @var{d0}, @var{d0}}
1630 @item uint32x4_t vcleq_u32 (uint32x4_t, uint32x4_t)
1631 @*@emph{Form of expected instruction(s):} @code{vcge.u32 @var{q0}, @var{q0}, @var{q0}}
1636 @item uint16x8_t vcleq_u16 (uint16x8_t, uint16x8_t)
1637 @*@emph{Form of expected instruction(s):} @code{vcge.u16 @var{q0}, @var{q0}, @var{q0}}
1642 @item uint8x16_t vcleq_u8 (uint8x16_t, uint8x16_t)
1643 @*@emph{Form of expected instruction(s):} @code{vcge.u8 @var{q0}, @var{q0}, @var{q0}}
1648 @item uint32x4_t vcleq_s32 (int32x4_t, int32x4_t)
1649 @*@emph{Form of expected instruction(s):} @code{vcge.s32 @var{q0}, @var{q0}, @var{q0}}
1654 @item uint16x8_t vcleq_s16 (int16x8_t, int16x8_t)
1655 @*@emph{Form of expected instruction(s):} @code{vcge.s16 @var{q0}, @var{q0}, @var{q0}}
1660 @item uint8x16_t vcleq_s8 (int8x16_t, int8x16_t)
1661 @*@emph{Form of expected instruction(s):} @code{vcge.s8 @var{q0}, @var{q0}, @var{q0}}
1666 @item uint32x4_t vcleq_f32 (float32x4_t, float32x4_t)
1667 @*@emph{Form of expected instruction(s):} @code{vcge.f32 @var{q0}, @var{q0}, @var{q0}}
1673 @subsubsection Comparison (greater-than)
1676 @item uint32x2_t vcgt_u32 (uint32x2_t, uint32x2_t)
1677 @*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}}
1682 @item uint16x4_t vcgt_u16 (uint16x4_t, uint16x4_t)
1683 @*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}}
1688 @item uint8x8_t vcgt_u8 (uint8x8_t, uint8x8_t)
1689 @*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}}
1694 @item uint32x2_t vcgt_s32 (int32x2_t, int32x2_t)
1695 @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}}
1700 @item uint16x4_t vcgt_s16 (int16x4_t, int16x4_t)
1701 @*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{d0}, @var{d0}, @var{d0}}
1706 @item uint8x8_t vcgt_s8 (int8x8_t, int8x8_t)
1707 @*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{d0}, @var{d0}, @var{d0}}
1712 @item uint32x2_t vcgt_f32 (float32x2_t, float32x2_t)
1713 @*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{d0}, @var{d0}, @var{d0}}
1718 @item uint32x4_t vcgtq_u32 (uint32x4_t, uint32x4_t)
1719 @*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}}
1724 @item uint16x8_t vcgtq_u16 (uint16x8_t, uint16x8_t)
1725 @*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}}
1730 @item uint8x16_t vcgtq_u8 (uint8x16_t, uint8x16_t)
1731 @*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}}
1736 @item uint32x4_t vcgtq_s32 (int32x4_t, int32x4_t)
1737 @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{q0}, @var{q0}, @var{q0}}
1742 @item uint16x8_t vcgtq_s16 (int16x8_t, int16x8_t)
1743 @*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{q0}, @var{q0}, @var{q0}}
1748 @item uint8x16_t vcgtq_s8 (int8x16_t, int8x16_t)
1749 @*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{q0}, @var{q0}, @var{q0}}
1754 @item uint32x4_t vcgtq_f32 (float32x4_t, float32x4_t)
1755 @*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{q0}, @var{q0}, @var{q0}}
1761 @subsubsection Comparison (less-than)
1764 @item uint32x2_t vclt_u32 (uint32x2_t, uint32x2_t)
1765 @*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{d0}, @var{d0}, @var{d0}}
1770 @item uint16x4_t vclt_u16 (uint16x4_t, uint16x4_t)
1771 @*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{d0}, @var{d0}, @var{d0}}
1776 @item uint8x8_t vclt_u8 (uint8x8_t, uint8x8_t)
1777 @*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{d0}, @var{d0}, @var{d0}}
1782 @item uint32x2_t vclt_s32 (int32x2_t, int32x2_t)
1783 @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{d0}, @var{d0}, @var{d0}}
1788 @item uint16x4_t vclt_s16 (int16x4_t, int16x4_t)
1789 @*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{d0}, @var{d0}, @var{d0}}
1794 @item uint8x8_t vclt_s8 (int8x8_t, int8x8_t)
1795 @*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{d0}, @var{d0}, @var{d0}}
1800 @item uint32x2_t vclt_f32 (float32x2_t, float32x2_t)
1801 @*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{d0}, @var{d0}, @var{d0}}
1806 @item uint32x4_t vcltq_u32 (uint32x4_t, uint32x4_t)
1807 @*@emph{Form of expected instruction(s):} @code{vcgt.u32 @var{q0}, @var{q0}, @var{q0}}
1812 @item uint16x8_t vcltq_u16 (uint16x8_t, uint16x8_t)
1813 @*@emph{Form of expected instruction(s):} @code{vcgt.u16 @var{q0}, @var{q0}, @var{q0}}
1818 @item uint8x16_t vcltq_u8 (uint8x16_t, uint8x16_t)
1819 @*@emph{Form of expected instruction(s):} @code{vcgt.u8 @var{q0}, @var{q0}, @var{q0}}
1824 @item uint32x4_t vcltq_s32 (int32x4_t, int32x4_t)
1825 @*@emph{Form of expected instruction(s):} @code{vcgt.s32 @var{q0}, @var{q0}, @var{q0}}
1830 @item uint16x8_t vcltq_s16 (int16x8_t, int16x8_t)
1831 @*@emph{Form of expected instruction(s):} @code{vcgt.s16 @var{q0}, @var{q0}, @var{q0}}
1836 @item uint8x16_t vcltq_s8 (int8x16_t, int8x16_t)
1837 @*@emph{Form of expected instruction(s):} @code{vcgt.s8 @var{q0}, @var{q0}, @var{q0}}
1842 @item uint32x4_t vcltq_f32 (float32x4_t, float32x4_t)
1843 @*@emph{Form of expected instruction(s):} @code{vcgt.f32 @var{q0}, @var{q0}, @var{q0}}
1849 @subsubsection Comparison (absolute greater-than-or-equal-to)
1852 @item uint32x2_t vcage_f32 (float32x2_t, float32x2_t)
1853 @*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{d0}, @var{d0}, @var{d0}}
1858 @item uint32x4_t vcageq_f32 (float32x4_t, float32x4_t)
1859 @*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{q0}, @var{q0}, @var{q0}}
1865 @subsubsection Comparison (absolute less-than-or-equal-to)
1868 @item uint32x2_t vcale_f32 (float32x2_t, float32x2_t)
1869 @*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{d0}, @var{d0}, @var{d0}}
1874 @item uint32x4_t vcaleq_f32 (float32x4_t, float32x4_t)
1875 @*@emph{Form of expected instruction(s):} @code{vacge.f32 @var{q0}, @var{q0}, @var{q0}}
1881 @subsubsection Comparison (absolute greater-than)
1884 @item uint32x2_t vcagt_f32 (float32x2_t, float32x2_t)
1885 @*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{d0}, @var{d0}, @var{d0}}
1890 @item uint32x4_t vcagtq_f32 (float32x4_t, float32x4_t)
1891 @*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{q0}, @var{q0}, @var{q0}}
1897 @subsubsection Comparison (absolute less-than)
1900 @item uint32x2_t vcalt_f32 (float32x2_t, float32x2_t)
1901 @*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{d0}, @var{d0}, @var{d0}}
1906 @item uint32x4_t vcaltq_f32 (float32x4_t, float32x4_t)
1907 @*@emph{Form of expected instruction(s):} @code{vacgt.f32 @var{q0}, @var{q0}, @var{q0}}
1913 @subsubsection Test bits
1916 @item uint32x2_t vtst_u32 (uint32x2_t, uint32x2_t)
1917 @*@emph{Form of expected instruction(s):} @code{vtst.32 @var{d0}, @var{d0}, @var{d0}}
1922 @item uint16x4_t vtst_u16 (uint16x4_t, uint16x4_t)
1923 @*@emph{Form of expected instruction(s):} @code{vtst.16 @var{d0}, @var{d0}, @var{d0}}
1928 @item uint8x8_t vtst_u8 (uint8x8_t, uint8x8_t)
1929 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
1934 @item uint32x2_t vtst_s32 (int32x2_t, int32x2_t)
1935 @*@emph{Form of expected instruction(s):} @code{vtst.32 @var{d0}, @var{d0}, @var{d0}}
1940 @item uint16x4_t vtst_s16 (int16x4_t, int16x4_t)
1941 @*@emph{Form of expected instruction(s):} @code{vtst.16 @var{d0}, @var{d0}, @var{d0}}
1946 @item uint8x8_t vtst_s8 (int8x8_t, int8x8_t)
1947 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
1952 @item uint8x8_t vtst_p8 (poly8x8_t, poly8x8_t)
1953 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{d0}, @var{d0}, @var{d0}}
1958 @item uint32x4_t vtstq_u32 (uint32x4_t, uint32x4_t)
1959 @*@emph{Form of expected instruction(s):} @code{vtst.32 @var{q0}, @var{q0}, @var{q0}}
1964 @item uint16x8_t vtstq_u16 (uint16x8_t, uint16x8_t)
1965 @*@emph{Form of expected instruction(s):} @code{vtst.16 @var{q0}, @var{q0}, @var{q0}}
1970 @item uint8x16_t vtstq_u8 (uint8x16_t, uint8x16_t)
1971 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
1976 @item uint32x4_t vtstq_s32 (int32x4_t, int32x4_t)
1977 @*@emph{Form of expected instruction(s):} @code{vtst.32 @var{q0}, @var{q0}, @var{q0}}
1982 @item uint16x8_t vtstq_s16 (int16x8_t, int16x8_t)
1983 @*@emph{Form of expected instruction(s):} @code{vtst.16 @var{q0}, @var{q0}, @var{q0}}
1988 @item uint8x16_t vtstq_s8 (int8x16_t, int8x16_t)
1989 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
1994 @item uint8x16_t vtstq_p8 (poly8x16_t, poly8x16_t)
1995 @*@emph{Form of expected instruction(s):} @code{vtst.8 @var{q0}, @var{q0}, @var{q0}}
2001 @subsubsection Absolute difference
2004 @item uint32x2_t vabd_u32 (uint32x2_t, uint32x2_t)
2005 @*@emph{Form of expected instruction(s):} @code{vabd.u32 @var{d0}, @var{d0}, @var{d0}}
2010 @item uint16x4_t vabd_u16 (uint16x4_t, uint16x4_t)
2011 @*@emph{Form of expected instruction(s):} @code{vabd.u16 @var{d0}, @var{d0}, @var{d0}}
2016 @item uint8x8_t vabd_u8 (uint8x8_t, uint8x8_t)
2017 @*@emph{Form of expected instruction(s):} @code{vabd.u8 @var{d0}, @var{d0}, @var{d0}}
2022 @item int32x2_t vabd_s32 (int32x2_t, int32x2_t)
2023 @*@emph{Form of expected instruction(s):} @code{vabd.s32 @var{d0}, @var{d0}, @var{d0}}
2028 @item int16x4_t vabd_s16 (int16x4_t, int16x4_t)
2029 @*@emph{Form of expected instruction(s):} @code{vabd.s16 @var{d0}, @var{d0}, @var{d0}}
2034 @item int8x8_t vabd_s8 (int8x8_t, int8x8_t)
2035 @*@emph{Form of expected instruction(s):} @code{vabd.s8 @var{d0}, @var{d0}, @var{d0}}
2040 @item float32x2_t vabd_f32 (float32x2_t, float32x2_t)
2041 @*@emph{Form of expected instruction(s):} @code{vabd.f32 @var{d0}, @var{d0}, @var{d0}}
2046 @item uint32x4_t vabdq_u32 (uint32x4_t, uint32x4_t)
2047 @*@emph{Form of expected instruction(s):} @code{vabd.u32 @var{q0}, @var{q0}, @var{q0}}
2052 @item uint16x8_t vabdq_u16 (uint16x8_t, uint16x8_t)
2053 @*@emph{Form of expected instruction(s):} @code{vabd.u16 @var{q0}, @var{q0}, @var{q0}}
2058 @item uint8x16_t vabdq_u8 (uint8x16_t, uint8x16_t)
2059 @*@emph{Form of expected instruction(s):} @code{vabd.u8 @var{q0}, @var{q0}, @var{q0}}
2064 @item int32x4_t vabdq_s32 (int32x4_t, int32x4_t)
2065 @*@emph{Form of expected instruction(s):} @code{vabd.s32 @var{q0}, @var{q0}, @var{q0}}
2070 @item int16x8_t vabdq_s16 (int16x8_t, int16x8_t)
2071 @*@emph{Form of expected instruction(s):} @code{vabd.s16 @var{q0}, @var{q0}, @var{q0}}
2076 @item int8x16_t vabdq_s8 (int8x16_t, int8x16_t)
2077 @*@emph{Form of expected instruction(s):} @code{vabd.s8 @var{q0}, @var{q0}, @var{q0}}
2082 @item float32x4_t vabdq_f32 (float32x4_t, float32x4_t)
2083 @*@emph{Form of expected instruction(s):} @code{vabd.f32 @var{q0}, @var{q0}, @var{q0}}
2088 @item uint64x2_t vabdl_u32 (uint32x2_t, uint32x2_t)
2089 @*@emph{Form of expected instruction(s):} @code{vabdl.u32 @var{q0}, @var{d0}, @var{d0}}
2094 @item uint32x4_t vabdl_u16 (uint16x4_t, uint16x4_t)
2095 @*@emph{Form of expected instruction(s):} @code{vabdl.u16 @var{q0}, @var{d0}, @var{d0}}
2100 @item uint16x8_t vabdl_u8 (uint8x8_t, uint8x8_t)
2101 @*@emph{Form of expected instruction(s):} @code{vabdl.u8 @var{q0}, @var{d0}, @var{d0}}
2106 @item int64x2_t vabdl_s32 (int32x2_t, int32x2_t)
2107 @*@emph{Form of expected instruction(s):} @code{vabdl.s32 @var{q0}, @var{d0}, @var{d0}}
2112 @item int32x4_t vabdl_s16 (int16x4_t, int16x4_t)
2113 @*@emph{Form of expected instruction(s):} @code{vabdl.s16 @var{q0}, @var{d0}, @var{d0}}
2118 @item int16x8_t vabdl_s8 (int8x8_t, int8x8_t)
2119 @*@emph{Form of expected instruction(s):} @code{vabdl.s8 @var{q0}, @var{d0}, @var{d0}}
2125 @subsubsection Absolute difference and accumulate
2128 @item uint32x2_t vaba_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
2129 @*@emph{Form of expected instruction(s):} @code{vaba.u32 @var{d0}, @var{d0}, @var{d0}}
2134 @item uint16x4_t vaba_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
2135 @*@emph{Form of expected instruction(s):} @code{vaba.u16 @var{d0}, @var{d0}, @var{d0}}
2140 @item uint8x8_t vaba_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
2141 @*@emph{Form of expected instruction(s):} @code{vaba.u8 @var{d0}, @var{d0}, @var{d0}}
2146 @item int32x2_t vaba_s32 (int32x2_t, int32x2_t, int32x2_t)
2147 @*@emph{Form of expected instruction(s):} @code{vaba.s32 @var{d0}, @var{d0}, @var{d0}}
2152 @item int16x4_t vaba_s16 (int16x4_t, int16x4_t, int16x4_t)
2153 @*@emph{Form of expected instruction(s):} @code{vaba.s16 @var{d0}, @var{d0}, @var{d0}}
2158 @item int8x8_t vaba_s8 (int8x8_t, int8x8_t, int8x8_t)
2159 @*@emph{Form of expected instruction(s):} @code{vaba.s8 @var{d0}, @var{d0}, @var{d0}}
2164 @item uint32x4_t vabaq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
2165 @*@emph{Form of expected instruction(s):} @code{vaba.u32 @var{q0}, @var{q0}, @var{q0}}
2170 @item uint16x8_t vabaq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
2171 @*@emph{Form of expected instruction(s):} @code{vaba.u16 @var{q0}, @var{q0}, @var{q0}}
2176 @item uint8x16_t vabaq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
2177 @*@emph{Form of expected instruction(s):} @code{vaba.u8 @var{q0}, @var{q0}, @var{q0}}
2182 @item int32x4_t vabaq_s32 (int32x4_t, int32x4_t, int32x4_t)
2183 @*@emph{Form of expected instruction(s):} @code{vaba.s32 @var{q0}, @var{q0}, @var{q0}}
2188 @item int16x8_t vabaq_s16 (int16x8_t, int16x8_t, int16x8_t)
2189 @*@emph{Form of expected instruction(s):} @code{vaba.s16 @var{q0}, @var{q0}, @var{q0}}
2194 @item int8x16_t vabaq_s8 (int8x16_t, int8x16_t, int8x16_t)
2195 @*@emph{Form of expected instruction(s):} @code{vaba.s8 @var{q0}, @var{q0}, @var{q0}}
2200 @item uint64x2_t vabal_u32 (uint64x2_t, uint32x2_t, uint32x2_t)
2201 @*@emph{Form of expected instruction(s):} @code{vabal.u32 @var{q0}, @var{d0}, @var{d0}}
2206 @item uint32x4_t vabal_u16 (uint32x4_t, uint16x4_t, uint16x4_t)
2207 @*@emph{Form of expected instruction(s):} @code{vabal.u16 @var{q0}, @var{d0}, @var{d0}}
2212 @item uint16x8_t vabal_u8 (uint16x8_t, uint8x8_t, uint8x8_t)
2213 @*@emph{Form of expected instruction(s):} @code{vabal.u8 @var{q0}, @var{d0}, @var{d0}}
2218 @item int64x2_t vabal_s32 (int64x2_t, int32x2_t, int32x2_t)
2219 @*@emph{Form of expected instruction(s):} @code{vabal.s32 @var{q0}, @var{d0}, @var{d0}}
2224 @item int32x4_t vabal_s16 (int32x4_t, int16x4_t, int16x4_t)
2225 @*@emph{Form of expected instruction(s):} @code{vabal.s16 @var{q0}, @var{d0}, @var{d0}}
2230 @item int16x8_t vabal_s8 (int16x8_t, int8x8_t, int8x8_t)
2231 @*@emph{Form of expected instruction(s):} @code{vabal.s8 @var{q0}, @var{d0}, @var{d0}}
2237 @subsubsection Maximum
2240 @item uint32x2_t vmax_u32 (uint32x2_t, uint32x2_t)
2241 @*@emph{Form of expected instruction(s):} @code{vmax.u32 @var{d0}, @var{d0}, @var{d0}}
2246 @item uint16x4_t vmax_u16 (uint16x4_t, uint16x4_t)
2247 @*@emph{Form of expected instruction(s):} @code{vmax.u16 @var{d0}, @var{d0}, @var{d0}}
2252 @item uint8x8_t vmax_u8 (uint8x8_t, uint8x8_t)
2253 @*@emph{Form of expected instruction(s):} @code{vmax.u8 @var{d0}, @var{d0}, @var{d0}}
2258 @item int32x2_t vmax_s32 (int32x2_t, int32x2_t)
2259 @*@emph{Form of expected instruction(s):} @code{vmax.s32 @var{d0}, @var{d0}, @var{d0}}
2264 @item int16x4_t vmax_s16 (int16x4_t, int16x4_t)
2265 @*@emph{Form of expected instruction(s):} @code{vmax.s16 @var{d0}, @var{d0}, @var{d0}}
2270 @item int8x8_t vmax_s8 (int8x8_t, int8x8_t)
2271 @*@emph{Form of expected instruction(s):} @code{vmax.s8 @var{d0}, @var{d0}, @var{d0}}
2276 @item float32x2_t vmax_f32 (float32x2_t, float32x2_t)
2277 @*@emph{Form of expected instruction(s):} @code{vmax.f32 @var{d0}, @var{d0}, @var{d0}}
2282 @item uint32x4_t vmaxq_u32 (uint32x4_t, uint32x4_t)
2283 @*@emph{Form of expected instruction(s):} @code{vmax.u32 @var{q0}, @var{q0}, @var{q0}}
2288 @item uint16x8_t vmaxq_u16 (uint16x8_t, uint16x8_t)
2289 @*@emph{Form of expected instruction(s):} @code{vmax.u16 @var{q0}, @var{q0}, @var{q0}}
2294 @item uint8x16_t vmaxq_u8 (uint8x16_t, uint8x16_t)
2295 @*@emph{Form of expected instruction(s):} @code{vmax.u8 @var{q0}, @var{q0}, @var{q0}}
2300 @item int32x4_t vmaxq_s32 (int32x4_t, int32x4_t)
2301 @*@emph{Form of expected instruction(s):} @code{vmax.s32 @var{q0}, @var{q0}, @var{q0}}
2306 @item int16x8_t vmaxq_s16 (int16x8_t, int16x8_t)
2307 @*@emph{Form of expected instruction(s):} @code{vmax.s16 @var{q0}, @var{q0}, @var{q0}}
2312 @item int8x16_t vmaxq_s8 (int8x16_t, int8x16_t)
2313 @*@emph{Form of expected instruction(s):} @code{vmax.s8 @var{q0}, @var{q0}, @var{q0}}
2318 @item float32x4_t vmaxq_f32 (float32x4_t, float32x4_t)
2319 @*@emph{Form of expected instruction(s):} @code{vmax.f32 @var{q0}, @var{q0}, @var{q0}}
2325 @subsubsection Minimum
2328 @item uint32x2_t vmin_u32 (uint32x2_t, uint32x2_t)
2329 @*@emph{Form of expected instruction(s):} @code{vmin.u32 @var{d0}, @var{d0}, @var{d0}}
2334 @item uint16x4_t vmin_u16 (uint16x4_t, uint16x4_t)
2335 @*@emph{Form of expected instruction(s):} @code{vmin.u16 @var{d0}, @var{d0}, @var{d0}}
2340 @item uint8x8_t vmin_u8 (uint8x8_t, uint8x8_t)
2341 @*@emph{Form of expected instruction(s):} @code{vmin.u8 @var{d0}, @var{d0}, @var{d0}}
2346 @item int32x2_t vmin_s32 (int32x2_t, int32x2_t)
2347 @*@emph{Form of expected instruction(s):} @code{vmin.s32 @var{d0}, @var{d0}, @var{d0}}
2352 @item int16x4_t vmin_s16 (int16x4_t, int16x4_t)
2353 @*@emph{Form of expected instruction(s):} @code{vmin.s16 @var{d0}, @var{d0}, @var{d0}}
2358 @item int8x8_t vmin_s8 (int8x8_t, int8x8_t)
2359 @*@emph{Form of expected instruction(s):} @code{vmin.s8 @var{d0}, @var{d0}, @var{d0}}
2364 @item float32x2_t vmin_f32 (float32x2_t, float32x2_t)
2365 @*@emph{Form of expected instruction(s):} @code{vmin.f32 @var{d0}, @var{d0}, @var{d0}}
2370 @item uint32x4_t vminq_u32 (uint32x4_t, uint32x4_t)
2371 @*@emph{Form of expected instruction(s):} @code{vmin.u32 @var{q0}, @var{q0}, @var{q0}}
2376 @item uint16x8_t vminq_u16 (uint16x8_t, uint16x8_t)
2377 @*@emph{Form of expected instruction(s):} @code{vmin.u16 @var{q0}, @var{q0}, @var{q0}}
2382 @item uint8x16_t vminq_u8 (uint8x16_t, uint8x16_t)
2383 @*@emph{Form of expected instruction(s):} @code{vmin.u8 @var{q0}, @var{q0}, @var{q0}}
2388 @item int32x4_t vminq_s32 (int32x4_t, int32x4_t)
2389 @*@emph{Form of expected instruction(s):} @code{vmin.s32 @var{q0}, @var{q0}, @var{q0}}
2394 @item int16x8_t vminq_s16 (int16x8_t, int16x8_t)
2395 @*@emph{Form of expected instruction(s):} @code{vmin.s16 @var{q0}, @var{q0}, @var{q0}}
2400 @item int8x16_t vminq_s8 (int8x16_t, int8x16_t)
2401 @*@emph{Form of expected instruction(s):} @code{vmin.s8 @var{q0}, @var{q0}, @var{q0}}
2406 @item float32x4_t vminq_f32 (float32x4_t, float32x4_t)
2407 @*@emph{Form of expected instruction(s):} @code{vmin.f32 @var{q0}, @var{q0}, @var{q0}}
2413 @subsubsection Pairwise add
2416 @item uint32x2_t vpadd_u32 (uint32x2_t, uint32x2_t)
2417 @*@emph{Form of expected instruction(s):} @code{vpadd.i32 @var{d0}, @var{d0}, @var{d0}}
2422 @item uint16x4_t vpadd_u16 (uint16x4_t, uint16x4_t)
2423 @*@emph{Form of expected instruction(s):} @code{vpadd.i16 @var{d0}, @var{d0}, @var{d0}}
2428 @item uint8x8_t vpadd_u8 (uint8x8_t, uint8x8_t)
2429 @*@emph{Form of expected instruction(s):} @code{vpadd.i8 @var{d0}, @var{d0}, @var{d0}}
2434 @item int32x2_t vpadd_s32 (int32x2_t, int32x2_t)
2435 @*@emph{Form of expected instruction(s):} @code{vpadd.i32 @var{d0}, @var{d0}, @var{d0}}
2440 @item int16x4_t vpadd_s16 (int16x4_t, int16x4_t)
2441 @*@emph{Form of expected instruction(s):} @code{vpadd.i16 @var{d0}, @var{d0}, @var{d0}}
2446 @item int8x8_t vpadd_s8 (int8x8_t, int8x8_t)
2447 @*@emph{Form of expected instruction(s):} @code{vpadd.i8 @var{d0}, @var{d0}, @var{d0}}
2452 @item float32x2_t vpadd_f32 (float32x2_t, float32x2_t)
2453 @*@emph{Form of expected instruction(s):} @code{vpadd.f32 @var{d0}, @var{d0}, @var{d0}}
2458 @item uint64x1_t vpaddl_u32 (uint32x2_t)
2459 @*@emph{Form of expected instruction(s):} @code{vpaddl.u32 @var{d0}, @var{d0}}
2464 @item uint32x2_t vpaddl_u16 (uint16x4_t)
2465 @*@emph{Form of expected instruction(s):} @code{vpaddl.u16 @var{d0}, @var{d0}}
2470 @item uint16x4_t vpaddl_u8 (uint8x8_t)
2471 @*@emph{Form of expected instruction(s):} @code{vpaddl.u8 @var{d0}, @var{d0}}
2476 @item int64x1_t vpaddl_s32 (int32x2_t)
2477 @*@emph{Form of expected instruction(s):} @code{vpaddl.s32 @var{d0}, @var{d0}}
2482 @item int32x2_t vpaddl_s16 (int16x4_t)
2483 @*@emph{Form of expected instruction(s):} @code{vpaddl.s16 @var{d0}, @var{d0}}
2488 @item int16x4_t vpaddl_s8 (int8x8_t)
2489 @*@emph{Form of expected instruction(s):} @code{vpaddl.s8 @var{d0}, @var{d0}}
2494 @item uint64x2_t vpaddlq_u32 (uint32x4_t)
2495 @*@emph{Form of expected instruction(s):} @code{vpaddl.u32 @var{q0}, @var{q0}}
2500 @item uint32x4_t vpaddlq_u16 (uint16x8_t)
2501 @*@emph{Form of expected instruction(s):} @code{vpaddl.u16 @var{q0}, @var{q0}}
2506 @item uint16x8_t vpaddlq_u8 (uint8x16_t)
2507 @*@emph{Form of expected instruction(s):} @code{vpaddl.u8 @var{q0}, @var{q0}}
2512 @item int64x2_t vpaddlq_s32 (int32x4_t)
2513 @*@emph{Form of expected instruction(s):} @code{vpaddl.s32 @var{q0}, @var{q0}}
2518 @item int32x4_t vpaddlq_s16 (int16x8_t)
2519 @*@emph{Form of expected instruction(s):} @code{vpaddl.s16 @var{q0}, @var{q0}}
2524 @item int16x8_t vpaddlq_s8 (int8x16_t)
2525 @*@emph{Form of expected instruction(s):} @code{vpaddl.s8 @var{q0}, @var{q0}}
2531 @subsubsection Pairwise add, single_opcode widen and accumulate
2534 @item uint64x1_t vpadal_u32 (uint64x1_t, uint32x2_t)
2535 @*@emph{Form of expected instruction(s):} @code{vpadal.u32 @var{d0}, @var{d0}}
2540 @item uint32x2_t vpadal_u16 (uint32x2_t, uint16x4_t)
2541 @*@emph{Form of expected instruction(s):} @code{vpadal.u16 @var{d0}, @var{d0}}
2546 @item uint16x4_t vpadal_u8 (uint16x4_t, uint8x8_t)
2547 @*@emph{Form of expected instruction(s):} @code{vpadal.u8 @var{d0}, @var{d0}}
2552 @item int64x1_t vpadal_s32 (int64x1_t, int32x2_t)
2553 @*@emph{Form of expected instruction(s):} @code{vpadal.s32 @var{d0}, @var{d0}}
2558 @item int32x2_t vpadal_s16 (int32x2_t, int16x4_t)
2559 @*@emph{Form of expected instruction(s):} @code{vpadal.s16 @var{d0}, @var{d0}}
2564 @item int16x4_t vpadal_s8 (int16x4_t, int8x8_t)
2565 @*@emph{Form of expected instruction(s):} @code{vpadal.s8 @var{d0}, @var{d0}}
2570 @item uint64x2_t vpadalq_u32 (uint64x2_t, uint32x4_t)
2571 @*@emph{Form of expected instruction(s):} @code{vpadal.u32 @var{q0}, @var{q0}}
2576 @item uint32x4_t vpadalq_u16 (uint32x4_t, uint16x8_t)
2577 @*@emph{Form of expected instruction(s):} @code{vpadal.u16 @var{q0}, @var{q0}}
2582 @item uint16x8_t vpadalq_u8 (uint16x8_t, uint8x16_t)
2583 @*@emph{Form of expected instruction(s):} @code{vpadal.u8 @var{q0}, @var{q0}}
2588 @item int64x2_t vpadalq_s32 (int64x2_t, int32x4_t)
2589 @*@emph{Form of expected instruction(s):} @code{vpadal.s32 @var{q0}, @var{q0}}
2594 @item int32x4_t vpadalq_s16 (int32x4_t, int16x8_t)
2595 @*@emph{Form of expected instruction(s):} @code{vpadal.s16 @var{q0}, @var{q0}}
2600 @item int16x8_t vpadalq_s8 (int16x8_t, int8x16_t)
2601 @*@emph{Form of expected instruction(s):} @code{vpadal.s8 @var{q0}, @var{q0}}
2607 @subsubsection Folding maximum
2610 @item uint32x2_t vpmax_u32 (uint32x2_t, uint32x2_t)
2611 @*@emph{Form of expected instruction(s):} @code{vpmax.u32 @var{d0}, @var{d0}, @var{d0}}
2616 @item uint16x4_t vpmax_u16 (uint16x4_t, uint16x4_t)
2617 @*@emph{Form of expected instruction(s):} @code{vpmax.u16 @var{d0}, @var{d0}, @var{d0}}
2622 @item uint8x8_t vpmax_u8 (uint8x8_t, uint8x8_t)
2623 @*@emph{Form of expected instruction(s):} @code{vpmax.u8 @var{d0}, @var{d0}, @var{d0}}
2628 @item int32x2_t vpmax_s32 (int32x2_t, int32x2_t)
2629 @*@emph{Form of expected instruction(s):} @code{vpmax.s32 @var{d0}, @var{d0}, @var{d0}}
2634 @item int16x4_t vpmax_s16 (int16x4_t, int16x4_t)
2635 @*@emph{Form of expected instruction(s):} @code{vpmax.s16 @var{d0}, @var{d0}, @var{d0}}
2640 @item int8x8_t vpmax_s8 (int8x8_t, int8x8_t)
2641 @*@emph{Form of expected instruction(s):} @code{vpmax.s8 @var{d0}, @var{d0}, @var{d0}}
2646 @item float32x2_t vpmax_f32 (float32x2_t, float32x2_t)
2647 @*@emph{Form of expected instruction(s):} @code{vpmax.f32 @var{d0}, @var{d0}, @var{d0}}
2653 @subsubsection Folding minimum
2656 @item uint32x2_t vpmin_u32 (uint32x2_t, uint32x2_t)
2657 @*@emph{Form of expected instruction(s):} @code{vpmin.u32 @var{d0}, @var{d0}, @var{d0}}
2662 @item uint16x4_t vpmin_u16 (uint16x4_t, uint16x4_t)
2663 @*@emph{Form of expected instruction(s):} @code{vpmin.u16 @var{d0}, @var{d0}, @var{d0}}
2668 @item uint8x8_t vpmin_u8 (uint8x8_t, uint8x8_t)
2669 @*@emph{Form of expected instruction(s):} @code{vpmin.u8 @var{d0}, @var{d0}, @var{d0}}
2674 @item int32x2_t vpmin_s32 (int32x2_t, int32x2_t)
2675 @*@emph{Form of expected instruction(s):} @code{vpmin.s32 @var{d0}, @var{d0}, @var{d0}}
2680 @item int16x4_t vpmin_s16 (int16x4_t, int16x4_t)
2681 @*@emph{Form of expected instruction(s):} @code{vpmin.s16 @var{d0}, @var{d0}, @var{d0}}
2686 @item int8x8_t vpmin_s8 (int8x8_t, int8x8_t)
2687 @*@emph{Form of expected instruction(s):} @code{vpmin.s8 @var{d0}, @var{d0}, @var{d0}}
2692 @item float32x2_t vpmin_f32 (float32x2_t, float32x2_t)
2693 @*@emph{Form of expected instruction(s):} @code{vpmin.f32 @var{d0}, @var{d0}, @var{d0}}
2699 @subsubsection Reciprocal step
2702 @item float32x2_t vrecps_f32 (float32x2_t, float32x2_t)
2703 @*@emph{Form of expected instruction(s):} @code{vrecps.f32 @var{d0}, @var{d0}, @var{d0}}
2708 @item float32x4_t vrecpsq_f32 (float32x4_t, float32x4_t)
2709 @*@emph{Form of expected instruction(s):} @code{vrecps.f32 @var{q0}, @var{q0}, @var{q0}}
2714 @item float32x2_t vrsqrts_f32 (float32x2_t, float32x2_t)
2715 @*@emph{Form of expected instruction(s):} @code{vrsqrts.f32 @var{d0}, @var{d0}, @var{d0}}
2720 @item float32x4_t vrsqrtsq_f32 (float32x4_t, float32x4_t)
2721 @*@emph{Form of expected instruction(s):} @code{vrsqrts.f32 @var{q0}, @var{q0}, @var{q0}}
2727 @subsubsection Vector shift left
2730 @item uint32x2_t vshl_u32 (uint32x2_t, int32x2_t)
2731 @*@emph{Form of expected instruction(s):} @code{vshl.u32 @var{d0}, @var{d0}, @var{d0}}
2736 @item uint16x4_t vshl_u16 (uint16x4_t, int16x4_t)
2737 @*@emph{Form of expected instruction(s):} @code{vshl.u16 @var{d0}, @var{d0}, @var{d0}}
2742 @item uint8x8_t vshl_u8 (uint8x8_t, int8x8_t)
2743 @*@emph{Form of expected instruction(s):} @code{vshl.u8 @var{d0}, @var{d0}, @var{d0}}
2748 @item int32x2_t vshl_s32 (int32x2_t, int32x2_t)
2749 @*@emph{Form of expected instruction(s):} @code{vshl.s32 @var{d0}, @var{d0}, @var{d0}}
2754 @item int16x4_t vshl_s16 (int16x4_t, int16x4_t)
2755 @*@emph{Form of expected instruction(s):} @code{vshl.s16 @var{d0}, @var{d0}, @var{d0}}
2760 @item int8x8_t vshl_s8 (int8x8_t, int8x8_t)
2761 @*@emph{Form of expected instruction(s):} @code{vshl.s8 @var{d0}, @var{d0}, @var{d0}}
2766 @item uint64x1_t vshl_u64 (uint64x1_t, int64x1_t)
2767 @*@emph{Form of expected instruction(s):} @code{vshl.u64 @var{d0}, @var{d0}, @var{d0}}
2772 @item int64x1_t vshl_s64 (int64x1_t, int64x1_t)
2773 @*@emph{Form of expected instruction(s):} @code{vshl.s64 @var{d0}, @var{d0}, @var{d0}}
2778 @item uint32x4_t vshlq_u32 (uint32x4_t, int32x4_t)
2779 @*@emph{Form of expected instruction(s):} @code{vshl.u32 @var{q0}, @var{q0}, @var{q0}}
2784 @item uint16x8_t vshlq_u16 (uint16x8_t, int16x8_t)
2785 @*@emph{Form of expected instruction(s):} @code{vshl.u16 @var{q0}, @var{q0}, @var{q0}}
2790 @item uint8x16_t vshlq_u8 (uint8x16_t, int8x16_t)
2791 @*@emph{Form of expected instruction(s):} @code{vshl.u8 @var{q0}, @var{q0}, @var{q0}}
2796 @item int32x4_t vshlq_s32 (int32x4_t, int32x4_t)
2797 @*@emph{Form of expected instruction(s):} @code{vshl.s32 @var{q0}, @var{q0}, @var{q0}}
2802 @item int16x8_t vshlq_s16 (int16x8_t, int16x8_t)
2803 @*@emph{Form of expected instruction(s):} @code{vshl.s16 @var{q0}, @var{q0}, @var{q0}}
2808 @item int8x16_t vshlq_s8 (int8x16_t, int8x16_t)
2809 @*@emph{Form of expected instruction(s):} @code{vshl.s8 @var{q0}, @var{q0}, @var{q0}}
2814 @item uint64x2_t vshlq_u64 (uint64x2_t, int64x2_t)
2815 @*@emph{Form of expected instruction(s):} @code{vshl.u64 @var{q0}, @var{q0}, @var{q0}}
2820 @item int64x2_t vshlq_s64 (int64x2_t, int64x2_t)
2821 @*@emph{Form of expected instruction(s):} @code{vshl.s64 @var{q0}, @var{q0}, @var{q0}}
2826 @item uint32x2_t vrshl_u32 (uint32x2_t, int32x2_t)
2827 @*@emph{Form of expected instruction(s):} @code{vrshl.u32 @var{d0}, @var{d0}, @var{d0}}
2832 @item uint16x4_t vrshl_u16 (uint16x4_t, int16x4_t)
2833 @*@emph{Form of expected instruction(s):} @code{vrshl.u16 @var{d0}, @var{d0}, @var{d0}}
2838 @item uint8x8_t vrshl_u8 (uint8x8_t, int8x8_t)
2839 @*@emph{Form of expected instruction(s):} @code{vrshl.u8 @var{d0}, @var{d0}, @var{d0}}
2844 @item int32x2_t vrshl_s32 (int32x2_t, int32x2_t)
2845 @*@emph{Form of expected instruction(s):} @code{vrshl.s32 @var{d0}, @var{d0}, @var{d0}}
2850 @item int16x4_t vrshl_s16 (int16x4_t, int16x4_t)
2851 @*@emph{Form of expected instruction(s):} @code{vrshl.s16 @var{d0}, @var{d0}, @var{d0}}
2856 @item int8x8_t vrshl_s8 (int8x8_t, int8x8_t)
2857 @*@emph{Form of expected instruction(s):} @code{vrshl.s8 @var{d0}, @var{d0}, @var{d0}}
2862 @item uint64x1_t vrshl_u64 (uint64x1_t, int64x1_t)
2863 @*@emph{Form of expected instruction(s):} @code{vrshl.u64 @var{d0}, @var{d0}, @var{d0}}
2868 @item int64x1_t vrshl_s64 (int64x1_t, int64x1_t)
2869 @*@emph{Form of expected instruction(s):} @code{vrshl.s64 @var{d0}, @var{d0}, @var{d0}}
2874 @item uint32x4_t vrshlq_u32 (uint32x4_t, int32x4_t)
2875 @*@emph{Form of expected instruction(s):} @code{vrshl.u32 @var{q0}, @var{q0}, @var{q0}}
2880 @item uint16x8_t vrshlq_u16 (uint16x8_t, int16x8_t)
2881 @*@emph{Form of expected instruction(s):} @code{vrshl.u16 @var{q0}, @var{q0}, @var{q0}}
2886 @item uint8x16_t vrshlq_u8 (uint8x16_t, int8x16_t)
2887 @*@emph{Form of expected instruction(s):} @code{vrshl.u8 @var{q0}, @var{q0}, @var{q0}}
2892 @item int32x4_t vrshlq_s32 (int32x4_t, int32x4_t)
2893 @*@emph{Form of expected instruction(s):} @code{vrshl.s32 @var{q0}, @var{q0}, @var{q0}}
2898 @item int16x8_t vrshlq_s16 (int16x8_t, int16x8_t)
2899 @*@emph{Form of expected instruction(s):} @code{vrshl.s16 @var{q0}, @var{q0}, @var{q0}}
2904 @item int8x16_t vrshlq_s8 (int8x16_t, int8x16_t)
2905 @*@emph{Form of expected instruction(s):} @code{vrshl.s8 @var{q0}, @var{q0}, @var{q0}}
2910 @item uint64x2_t vrshlq_u64 (uint64x2_t, int64x2_t)
2911 @*@emph{Form of expected instruction(s):} @code{vrshl.u64 @var{q0}, @var{q0}, @var{q0}}
2916 @item int64x2_t vrshlq_s64 (int64x2_t, int64x2_t)
2917 @*@emph{Form of expected instruction(s):} @code{vrshl.s64 @var{q0}, @var{q0}, @var{q0}}
2922 @item uint32x2_t vqshl_u32 (uint32x2_t, int32x2_t)
2923 @*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{d0}, @var{d0}, @var{d0}}
2928 @item uint16x4_t vqshl_u16 (uint16x4_t, int16x4_t)
2929 @*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{d0}, @var{d0}, @var{d0}}
2934 @item uint8x8_t vqshl_u8 (uint8x8_t, int8x8_t)
2935 @*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{d0}, @var{d0}, @var{d0}}
2940 @item int32x2_t vqshl_s32 (int32x2_t, int32x2_t)
2941 @*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{d0}, @var{d0}, @var{d0}}
2946 @item int16x4_t vqshl_s16 (int16x4_t, int16x4_t)
2947 @*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{d0}, @var{d0}, @var{d0}}
2952 @item int8x8_t vqshl_s8 (int8x8_t, int8x8_t)
2953 @*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{d0}, @var{d0}, @var{d0}}
2958 @item uint64x1_t vqshl_u64 (uint64x1_t, int64x1_t)
2959 @*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{d0}, @var{d0}, @var{d0}}
2964 @item int64x1_t vqshl_s64 (int64x1_t, int64x1_t)
2965 @*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{d0}, @var{d0}, @var{d0}}
2970 @item uint32x4_t vqshlq_u32 (uint32x4_t, int32x4_t)
2971 @*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{q0}, @var{q0}, @var{q0}}
2976 @item uint16x8_t vqshlq_u16 (uint16x8_t, int16x8_t)
2977 @*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{q0}, @var{q0}, @var{q0}}
2982 @item uint8x16_t vqshlq_u8 (uint8x16_t, int8x16_t)
2983 @*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{q0}, @var{q0}, @var{q0}}
2988 @item int32x4_t vqshlq_s32 (int32x4_t, int32x4_t)
2989 @*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{q0}, @var{q0}, @var{q0}}
2994 @item int16x8_t vqshlq_s16 (int16x8_t, int16x8_t)
2995 @*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{q0}, @var{q0}, @var{q0}}
3000 @item int8x16_t vqshlq_s8 (int8x16_t, int8x16_t)
3001 @*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{q0}, @var{q0}, @var{q0}}
3006 @item uint64x2_t vqshlq_u64 (uint64x2_t, int64x2_t)
3007 @*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{q0}, @var{q0}, @var{q0}}
3012 @item int64x2_t vqshlq_s64 (int64x2_t, int64x2_t)
3013 @*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{q0}, @var{q0}, @var{q0}}
3018 @item uint32x2_t vqrshl_u32 (uint32x2_t, int32x2_t)
3019 @*@emph{Form of expected instruction(s):} @code{vqrshl.u32 @var{d0}, @var{d0}, @var{d0}}
3024 @item uint16x4_t vqrshl_u16 (uint16x4_t, int16x4_t)
3025 @*@emph{Form of expected instruction(s):} @code{vqrshl.u16 @var{d0}, @var{d0}, @var{d0}}
3030 @item uint8x8_t vqrshl_u8 (uint8x8_t, int8x8_t)
3031 @*@emph{Form of expected instruction(s):} @code{vqrshl.u8 @var{d0}, @var{d0}, @var{d0}}
3036 @item int32x2_t vqrshl_s32 (int32x2_t, int32x2_t)
3037 @*@emph{Form of expected instruction(s):} @code{vqrshl.s32 @var{d0}, @var{d0}, @var{d0}}
3042 @item int16x4_t vqrshl_s16 (int16x4_t, int16x4_t)
3043 @*@emph{Form of expected instruction(s):} @code{vqrshl.s16 @var{d0}, @var{d0}, @var{d0}}
3048 @item int8x8_t vqrshl_s8 (int8x8_t, int8x8_t)
3049 @*@emph{Form of expected instruction(s):} @code{vqrshl.s8 @var{d0}, @var{d0}, @var{d0}}
3054 @item uint64x1_t vqrshl_u64 (uint64x1_t, int64x1_t)
3055 @*@emph{Form of expected instruction(s):} @code{vqrshl.u64 @var{d0}, @var{d0}, @var{d0}}
3060 @item int64x1_t vqrshl_s64 (int64x1_t, int64x1_t)
3061 @*@emph{Form of expected instruction(s):} @code{vqrshl.s64 @var{d0}, @var{d0}, @var{d0}}
3066 @item uint32x4_t vqrshlq_u32 (uint32x4_t, int32x4_t)
3067 @*@emph{Form of expected instruction(s):} @code{vqrshl.u32 @var{q0}, @var{q0}, @var{q0}}
3072 @item uint16x8_t vqrshlq_u16 (uint16x8_t, int16x8_t)
3073 @*@emph{Form of expected instruction(s):} @code{vqrshl.u16 @var{q0}, @var{q0}, @var{q0}}
3078 @item uint8x16_t vqrshlq_u8 (uint8x16_t, int8x16_t)
3079 @*@emph{Form of expected instruction(s):} @code{vqrshl.u8 @var{q0}, @var{q0}, @var{q0}}
3084 @item int32x4_t vqrshlq_s32 (int32x4_t, int32x4_t)
3085 @*@emph{Form of expected instruction(s):} @code{vqrshl.s32 @var{q0}, @var{q0}, @var{q0}}
3090 @item int16x8_t vqrshlq_s16 (int16x8_t, int16x8_t)
3091 @*@emph{Form of expected instruction(s):} @code{vqrshl.s16 @var{q0}, @var{q0}, @var{q0}}
3096 @item int8x16_t vqrshlq_s8 (int8x16_t, int8x16_t)
3097 @*@emph{Form of expected instruction(s):} @code{vqrshl.s8 @var{q0}, @var{q0}, @var{q0}}
3102 @item uint64x2_t vqrshlq_u64 (uint64x2_t, int64x2_t)
3103 @*@emph{Form of expected instruction(s):} @code{vqrshl.u64 @var{q0}, @var{q0}, @var{q0}}
3108 @item int64x2_t vqrshlq_s64 (int64x2_t, int64x2_t)
3109 @*@emph{Form of expected instruction(s):} @code{vqrshl.s64 @var{q0}, @var{q0}, @var{q0}}
3115 @subsubsection Vector shift left by constant
3118 @item uint32x2_t vshl_n_u32 (uint32x2_t, const int)
3119 @*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{d0}, @var{d0}, #@var{0}}
3124 @item uint16x4_t vshl_n_u16 (uint16x4_t, const int)
3125 @*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{d0}, @var{d0}, #@var{0}}
3130 @item uint8x8_t vshl_n_u8 (uint8x8_t, const int)
3131 @*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{d0}, @var{d0}, #@var{0}}
3136 @item int32x2_t vshl_n_s32 (int32x2_t, const int)
3137 @*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{d0}, @var{d0}, #@var{0}}
3142 @item int16x4_t vshl_n_s16 (int16x4_t, const int)
3143 @*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{d0}, @var{d0}, #@var{0}}
3148 @item int8x8_t vshl_n_s8 (int8x8_t, const int)
3149 @*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{d0}, @var{d0}, #@var{0}}
3154 @item uint64x1_t vshl_n_u64 (uint64x1_t, const int)
3155 @*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{d0}, @var{d0}, #@var{0}}
3160 @item int64x1_t vshl_n_s64 (int64x1_t, const int)
3161 @*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{d0}, @var{d0}, #@var{0}}
3166 @item uint32x4_t vshlq_n_u32 (uint32x4_t, const int)
3167 @*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{q0}, @var{q0}, #@var{0}}
3172 @item uint16x8_t vshlq_n_u16 (uint16x8_t, const int)
3173 @*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{q0}, @var{q0}, #@var{0}}
3178 @item uint8x16_t vshlq_n_u8 (uint8x16_t, const int)
3179 @*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{q0}, @var{q0}, #@var{0}}
3184 @item int32x4_t vshlq_n_s32 (int32x4_t, const int)
3185 @*@emph{Form of expected instruction(s):} @code{vshl.i32 @var{q0}, @var{q0}, #@var{0}}
3190 @item int16x8_t vshlq_n_s16 (int16x8_t, const int)
3191 @*@emph{Form of expected instruction(s):} @code{vshl.i16 @var{q0}, @var{q0}, #@var{0}}
3196 @item int8x16_t vshlq_n_s8 (int8x16_t, const int)
3197 @*@emph{Form of expected instruction(s):} @code{vshl.i8 @var{q0}, @var{q0}, #@var{0}}
3202 @item uint64x2_t vshlq_n_u64 (uint64x2_t, const int)
3203 @*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{q0}, @var{q0}, #@var{0}}
3208 @item int64x2_t vshlq_n_s64 (int64x2_t, const int)
3209 @*@emph{Form of expected instruction(s):} @code{vshl.i64 @var{q0}, @var{q0}, #@var{0}}
3214 @item uint32x2_t vqshl_n_u32 (uint32x2_t, const int)
3215 @*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{d0}, @var{d0}, #@var{0}}
3220 @item uint16x4_t vqshl_n_u16 (uint16x4_t, const int)
3221 @*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{d0}, @var{d0}, #@var{0}}
3226 @item uint8x8_t vqshl_n_u8 (uint8x8_t, const int)
3227 @*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{d0}, @var{d0}, #@var{0}}
3232 @item int32x2_t vqshl_n_s32 (int32x2_t, const int)
3233 @*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{d0}, @var{d0}, #@var{0}}
3238 @item int16x4_t vqshl_n_s16 (int16x4_t, const int)
3239 @*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{d0}, @var{d0}, #@var{0}}
3244 @item int8x8_t vqshl_n_s8 (int8x8_t, const int)
3245 @*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{d0}, @var{d0}, #@var{0}}
3250 @item uint64x1_t vqshl_n_u64 (uint64x1_t, const int)
3251 @*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{d0}, @var{d0}, #@var{0}}
3256 @item int64x1_t vqshl_n_s64 (int64x1_t, const int)
3257 @*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{d0}, @var{d0}, #@var{0}}
3262 @item uint32x4_t vqshlq_n_u32 (uint32x4_t, const int)
3263 @*@emph{Form of expected instruction(s):} @code{vqshl.u32 @var{q0}, @var{q0}, #@var{0}}
3268 @item uint16x8_t vqshlq_n_u16 (uint16x8_t, const int)
3269 @*@emph{Form of expected instruction(s):} @code{vqshl.u16 @var{q0}, @var{q0}, #@var{0}}
3274 @item uint8x16_t vqshlq_n_u8 (uint8x16_t, const int)
3275 @*@emph{Form of expected instruction(s):} @code{vqshl.u8 @var{q0}, @var{q0}, #@var{0}}
3280 @item int32x4_t vqshlq_n_s32 (int32x4_t, const int)
3281 @*@emph{Form of expected instruction(s):} @code{vqshl.s32 @var{q0}, @var{q0}, #@var{0}}
3286 @item int16x8_t vqshlq_n_s16 (int16x8_t, const int)
3287 @*@emph{Form of expected instruction(s):} @code{vqshl.s16 @var{q0}, @var{q0}, #@var{0}}
3292 @item int8x16_t vqshlq_n_s8 (int8x16_t, const int)
3293 @*@emph{Form of expected instruction(s):} @code{vqshl.s8 @var{q0}, @var{q0}, #@var{0}}
3298 @item uint64x2_t vqshlq_n_u64 (uint64x2_t, const int)
3299 @*@emph{Form of expected instruction(s):} @code{vqshl.u64 @var{q0}, @var{q0}, #@var{0}}
3304 @item int64x2_t vqshlq_n_s64 (int64x2_t, const int)
3305 @*@emph{Form of expected instruction(s):} @code{vqshl.s64 @var{q0}, @var{q0}, #@var{0}}
3310 @item uint64x1_t vqshlu_n_s64 (int64x1_t, const int)
3311 @*@emph{Form of expected instruction(s):} @code{vqshlu.s64 @var{d0}, @var{d0}, #@var{0}}
3316 @item uint32x2_t vqshlu_n_s32 (int32x2_t, const int)
3317 @*@emph{Form of expected instruction(s):} @code{vqshlu.s32 @var{d0}, @var{d0}, #@var{0}}
3322 @item uint16x4_t vqshlu_n_s16 (int16x4_t, const int)
3323 @*@emph{Form of expected instruction(s):} @code{vqshlu.s16 @var{d0}, @var{d0}, #@var{0}}
3328 @item uint8x8_t vqshlu_n_s8 (int8x8_t, const int)
3329 @*@emph{Form of expected instruction(s):} @code{vqshlu.s8 @var{d0}, @var{d0}, #@var{0}}
3334 @item uint64x2_t vqshluq_n_s64 (int64x2_t, const int)
3335 @*@emph{Form of expected instruction(s):} @code{vqshlu.s64 @var{q0}, @var{q0}, #@var{0}}
3340 @item uint32x4_t vqshluq_n_s32 (int32x4_t, const int)
3341 @*@emph{Form of expected instruction(s):} @code{vqshlu.s32 @var{q0}, @var{q0}, #@var{0}}
3346 @item uint16x8_t vqshluq_n_s16 (int16x8_t, const int)
3347 @*@emph{Form of expected instruction(s):} @code{vqshlu.s16 @var{q0}, @var{q0}, #@var{0}}
3352 @item uint8x16_t vqshluq_n_s8 (int8x16_t, const int)
3353 @*@emph{Form of expected instruction(s):} @code{vqshlu.s8 @var{q0}, @var{q0}, #@var{0}}
3358 @item uint64x2_t vshll_n_u32 (uint32x2_t, const int)
3359 @*@emph{Form of expected instruction(s):} @code{vshll.u32 @var{q0}, @var{d0}, #@var{0}}
3364 @item uint32x4_t vshll_n_u16 (uint16x4_t, const int)
3365 @*@emph{Form of expected instruction(s):} @code{vshll.u16 @var{q0}, @var{d0}, #@var{0}}
3370 @item uint16x8_t vshll_n_u8 (uint8x8_t, const int)
3371 @*@emph{Form of expected instruction(s):} @code{vshll.u8 @var{q0}, @var{d0}, #@var{0}}
3376 @item int64x2_t vshll_n_s32 (int32x2_t, const int)
3377 @*@emph{Form of expected instruction(s):} @code{vshll.s32 @var{q0}, @var{d0}, #@var{0}}
3382 @item int32x4_t vshll_n_s16 (int16x4_t, const int)
3383 @*@emph{Form of expected instruction(s):} @code{vshll.s16 @var{q0}, @var{d0}, #@var{0}}
3388 @item int16x8_t vshll_n_s8 (int8x8_t, const int)
3389 @*@emph{Form of expected instruction(s):} @code{vshll.s8 @var{q0}, @var{d0}, #@var{0}}
3395 @subsubsection Vector shift right by constant
3398 @item uint32x2_t vshr_n_u32 (uint32x2_t, const int)
3399 @*@emph{Form of expected instruction(s):} @code{vshr.u32 @var{d0}, @var{d0}, #@var{0}}
3404 @item uint16x4_t vshr_n_u16 (uint16x4_t, const int)
3405 @*@emph{Form of expected instruction(s):} @code{vshr.u16 @var{d0}, @var{d0}, #@var{0}}
3410 @item uint8x8_t vshr_n_u8 (uint8x8_t, const int)
3411 @*@emph{Form of expected instruction(s):} @code{vshr.u8 @var{d0}, @var{d0}, #@var{0}}
3416 @item int32x2_t vshr_n_s32 (int32x2_t, const int)
3417 @*@emph{Form of expected instruction(s):} @code{vshr.s32 @var{d0}, @var{d0}, #@var{0}}
3422 @item int16x4_t vshr_n_s16 (int16x4_t, const int)
3423 @*@emph{Form of expected instruction(s):} @code{vshr.s16 @var{d0}, @var{d0}, #@var{0}}
3428 @item int8x8_t vshr_n_s8 (int8x8_t, const int)
3429 @*@emph{Form of expected instruction(s):} @code{vshr.s8 @var{d0}, @var{d0}, #@var{0}}
3434 @item uint64x1_t vshr_n_u64 (uint64x1_t, const int)
3435 @*@emph{Form of expected instruction(s):} @code{vshr.u64 @var{d0}, @var{d0}, #@var{0}}
3440 @item int64x1_t vshr_n_s64 (int64x1_t, const int)
3441 @*@emph{Form of expected instruction(s):} @code{vshr.s64 @var{d0}, @var{d0}, #@var{0}}
3446 @item uint32x4_t vshrq_n_u32 (uint32x4_t, const int)
3447 @*@emph{Form of expected instruction(s):} @code{vshr.u32 @var{q0}, @var{q0}, #@var{0}}
3452 @item uint16x8_t vshrq_n_u16 (uint16x8_t, const int)
3453 @*@emph{Form of expected instruction(s):} @code{vshr.u16 @var{q0}, @var{q0}, #@var{0}}
3458 @item uint8x16_t vshrq_n_u8 (uint8x16_t, const int)
3459 @*@emph{Form of expected instruction(s):} @code{vshr.u8 @var{q0}, @var{q0}, #@var{0}}
3464 @item int32x4_t vshrq_n_s32 (int32x4_t, const int)
3465 @*@emph{Form of expected instruction(s):} @code{vshr.s32 @var{q0}, @var{q0}, #@var{0}}
3470 @item int16x8_t vshrq_n_s16 (int16x8_t, const int)
3471 @*@emph{Form of expected instruction(s):} @code{vshr.s16 @var{q0}, @var{q0}, #@var{0}}
3476 @item int8x16_t vshrq_n_s8 (int8x16_t, const int)
3477 @*@emph{Form of expected instruction(s):} @code{vshr.s8 @var{q0}, @var{q0}, #@var{0}}
3482 @item uint64x2_t vshrq_n_u64 (uint64x2_t, const int)
3483 @*@emph{Form of expected instruction(s):} @code{vshr.u64 @var{q0}, @var{q0}, #@var{0}}
3488 @item int64x2_t vshrq_n_s64 (int64x2_t, const int)
3489 @*@emph{Form of expected instruction(s):} @code{vshr.s64 @var{q0}, @var{q0}, #@var{0}}
3494 @item uint32x2_t vrshr_n_u32 (uint32x2_t, const int)
3495 @*@emph{Form of expected instruction(s):} @code{vrshr.u32 @var{d0}, @var{d0}, #@var{0}}
3500 @item uint16x4_t vrshr_n_u16 (uint16x4_t, const int)
3501 @*@emph{Form of expected instruction(s):} @code{vrshr.u16 @var{d0}, @var{d0}, #@var{0}}
3506 @item uint8x8_t vrshr_n_u8 (uint8x8_t, const int)
3507 @*@emph{Form of expected instruction(s):} @code{vrshr.u8 @var{d0}, @var{d0}, #@var{0}}
3512 @item int32x2_t vrshr_n_s32 (int32x2_t, const int)
3513 @*@emph{Form of expected instruction(s):} @code{vrshr.s32 @var{d0}, @var{d0}, #@var{0}}
3518 @item int16x4_t vrshr_n_s16 (int16x4_t, const int)
3519 @*@emph{Form of expected instruction(s):} @code{vrshr.s16 @var{d0}, @var{d0}, #@var{0}}
3524 @item int8x8_t vrshr_n_s8 (int8x8_t, const int)
3525 @*@emph{Form of expected instruction(s):} @code{vrshr.s8 @var{d0}, @var{d0}, #@var{0}}
3530 @item uint64x1_t vrshr_n_u64 (uint64x1_t, const int)
3531 @*@emph{Form of expected instruction(s):} @code{vrshr.u64 @var{d0}, @var{d0}, #@var{0}}
3536 @item int64x1_t vrshr_n_s64 (int64x1_t, const int)
3537 @*@emph{Form of expected instruction(s):} @code{vrshr.s64 @var{d0}, @var{d0}, #@var{0}}
3542 @item uint32x4_t vrshrq_n_u32 (uint32x4_t, const int)
3543 @*@emph{Form of expected instruction(s):} @code{vrshr.u32 @var{q0}, @var{q0}, #@var{0}}
3548 @item uint16x8_t vrshrq_n_u16 (uint16x8_t, const int)
3549 @*@emph{Form of expected instruction(s):} @code{vrshr.u16 @var{q0}, @var{q0}, #@var{0}}
3554 @item uint8x16_t vrshrq_n_u8 (uint8x16_t, const int)
3555 @*@emph{Form of expected instruction(s):} @code{vrshr.u8 @var{q0}, @var{q0}, #@var{0}}
3560 @item int32x4_t vrshrq_n_s32 (int32x4_t, const int)
3561 @*@emph{Form of expected instruction(s):} @code{vrshr.s32 @var{q0}, @var{q0}, #@var{0}}
3566 @item int16x8_t vrshrq_n_s16 (int16x8_t, const int)
3567 @*@emph{Form of expected instruction(s):} @code{vrshr.s16 @var{q0}, @var{q0}, #@var{0}}
3572 @item int8x16_t vrshrq_n_s8 (int8x16_t, const int)
3573 @*@emph{Form of expected instruction(s):} @code{vrshr.s8 @var{q0}, @var{q0}, #@var{0}}
3578 @item uint64x2_t vrshrq_n_u64 (uint64x2_t, const int)
3579 @*@emph{Form of expected instruction(s):} @code{vrshr.u64 @var{q0}, @var{q0}, #@var{0}}
3584 @item int64x2_t vrshrq_n_s64 (int64x2_t, const int)
3585 @*@emph{Form of expected instruction(s):} @code{vrshr.s64 @var{q0}, @var{q0}, #@var{0}}
3590 @item uint32x2_t vshrn_n_u64 (uint64x2_t, const int)
3591 @*@emph{Form of expected instruction(s):} @code{vshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3596 @item uint16x4_t vshrn_n_u32 (uint32x4_t, const int)
3597 @*@emph{Form of expected instruction(s):} @code{vshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3602 @item uint8x8_t vshrn_n_u16 (uint16x8_t, const int)
3603 @*@emph{Form of expected instruction(s):} @code{vshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3608 @item int32x2_t vshrn_n_s64 (int64x2_t, const int)
3609 @*@emph{Form of expected instruction(s):} @code{vshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3614 @item int16x4_t vshrn_n_s32 (int32x4_t, const int)
3615 @*@emph{Form of expected instruction(s):} @code{vshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3620 @item int8x8_t vshrn_n_s16 (int16x8_t, const int)
3621 @*@emph{Form of expected instruction(s):} @code{vshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3626 @item uint32x2_t vrshrn_n_u64 (uint64x2_t, const int)
3627 @*@emph{Form of expected instruction(s):} @code{vrshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3632 @item uint16x4_t vrshrn_n_u32 (uint32x4_t, const int)
3633 @*@emph{Form of expected instruction(s):} @code{vrshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3638 @item uint8x8_t vrshrn_n_u16 (uint16x8_t, const int)
3639 @*@emph{Form of expected instruction(s):} @code{vrshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3644 @item int32x2_t vrshrn_n_s64 (int64x2_t, const int)
3645 @*@emph{Form of expected instruction(s):} @code{vrshrn.i64 @var{d0}, @var{q0}, #@var{0}}
3650 @item int16x4_t vrshrn_n_s32 (int32x4_t, const int)
3651 @*@emph{Form of expected instruction(s):} @code{vrshrn.i32 @var{d0}, @var{q0}, #@var{0}}
3656 @item int8x8_t vrshrn_n_s16 (int16x8_t, const int)
3657 @*@emph{Form of expected instruction(s):} @code{vrshrn.i16 @var{d0}, @var{q0}, #@var{0}}
3662 @item uint32x2_t vqshrn_n_u64 (uint64x2_t, const int)
3663 @*@emph{Form of expected instruction(s):} @code{vqshrn.u64 @var{d0}, @var{q0}, #@var{0}}
3668 @item uint16x4_t vqshrn_n_u32 (uint32x4_t, const int)
3669 @*@emph{Form of expected instruction(s):} @code{vqshrn.u32 @var{d0}, @var{q0}, #@var{0}}
3674 @item uint8x8_t vqshrn_n_u16 (uint16x8_t, const int)
3675 @*@emph{Form of expected instruction(s):} @code{vqshrn.u16 @var{d0}, @var{q0}, #@var{0}}
3680 @item int32x2_t vqshrn_n_s64 (int64x2_t, const int)
3681 @*@emph{Form of expected instruction(s):} @code{vqshrn.s64 @var{d0}, @var{q0}, #@var{0}}
3686 @item int16x4_t vqshrn_n_s32 (int32x4_t, const int)
3687 @*@emph{Form of expected instruction(s):} @code{vqshrn.s32 @var{d0}, @var{q0}, #@var{0}}
3692 @item int8x8_t vqshrn_n_s16 (int16x8_t, const int)
3693 @*@emph{Form of expected instruction(s):} @code{vqshrn.s16 @var{d0}, @var{q0}, #@var{0}}
3698 @item uint32x2_t vqrshrn_n_u64 (uint64x2_t, const int)
3699 @*@emph{Form of expected instruction(s):} @code{vqrshrn.u64 @var{d0}, @var{q0}, #@var{0}}
3704 @item uint16x4_t vqrshrn_n_u32 (uint32x4_t, const int)
3705 @*@emph{Form of expected instruction(s):} @code{vqrshrn.u32 @var{d0}, @var{q0}, #@var{0}}
3710 @item uint8x8_t vqrshrn_n_u16 (uint16x8_t, const int)
3711 @*@emph{Form of expected instruction(s):} @code{vqrshrn.u16 @var{d0}, @var{q0}, #@var{0}}
3716 @item int32x2_t vqrshrn_n_s64 (int64x2_t, const int)
3717 @*@emph{Form of expected instruction(s):} @code{vqrshrn.s64 @var{d0}, @var{q0}, #@var{0}}
3722 @item int16x4_t vqrshrn_n_s32 (int32x4_t, const int)
3723 @*@emph{Form of expected instruction(s):} @code{vqrshrn.s32 @var{d0}, @var{q0}, #@var{0}}
3728 @item int8x8_t vqrshrn_n_s16 (int16x8_t, const int)
3729 @*@emph{Form of expected instruction(s):} @code{vqrshrn.s16 @var{d0}, @var{q0}, #@var{0}}
3734 @item uint32x2_t vqshrun_n_s64 (int64x2_t, const int)
3735 @*@emph{Form of expected instruction(s):} @code{vqshrun.s64 @var{d0}, @var{q0}, #@var{0}}
3740 @item uint16x4_t vqshrun_n_s32 (int32x4_t, const int)
3741 @*@emph{Form of expected instruction(s):} @code{vqshrun.s32 @var{d0}, @var{q0}, #@var{0}}
3746 @item uint8x8_t vqshrun_n_s16 (int16x8_t, const int)
3747 @*@emph{Form of expected instruction(s):} @code{vqshrun.s16 @var{d0}, @var{q0}, #@var{0}}
3752 @item uint32x2_t vqrshrun_n_s64 (int64x2_t, const int)
3753 @*@emph{Form of expected instruction(s):} @code{vqrshrun.s64 @var{d0}, @var{q0}, #@var{0}}
3758 @item uint16x4_t vqrshrun_n_s32 (int32x4_t, const int)
3759 @*@emph{Form of expected instruction(s):} @code{vqrshrun.s32 @var{d0}, @var{q0}, #@var{0}}
3764 @item uint8x8_t vqrshrun_n_s16 (int16x8_t, const int)
3765 @*@emph{Form of expected instruction(s):} @code{vqrshrun.s16 @var{d0}, @var{q0}, #@var{0}}
3771 @subsubsection Vector shift right by constant and accumulate
3774 @item uint32x2_t vsra_n_u32 (uint32x2_t, uint32x2_t, const int)
3775 @*@emph{Form of expected instruction(s):} @code{vsra.u32 @var{d0}, @var{d0}, #@var{0}}
3780 @item uint16x4_t vsra_n_u16 (uint16x4_t, uint16x4_t, const int)
3781 @*@emph{Form of expected instruction(s):} @code{vsra.u16 @var{d0}, @var{d0}, #@var{0}}
3786 @item uint8x8_t vsra_n_u8 (uint8x8_t, uint8x8_t, const int)
3787 @*@emph{Form of expected instruction(s):} @code{vsra.u8 @var{d0}, @var{d0}, #@var{0}}
3792 @item int32x2_t vsra_n_s32 (int32x2_t, int32x2_t, const int)
3793 @*@emph{Form of expected instruction(s):} @code{vsra.s32 @var{d0}, @var{d0}, #@var{0}}
3798 @item int16x4_t vsra_n_s16 (int16x4_t, int16x4_t, const int)
3799 @*@emph{Form of expected instruction(s):} @code{vsra.s16 @var{d0}, @var{d0}, #@var{0}}
3804 @item int8x8_t vsra_n_s8 (int8x8_t, int8x8_t, const int)
3805 @*@emph{Form of expected instruction(s):} @code{vsra.s8 @var{d0}, @var{d0}, #@var{0}}
3810 @item uint64x1_t vsra_n_u64 (uint64x1_t, uint64x1_t, const int)
3811 @*@emph{Form of expected instruction(s):} @code{vsra.u64 @var{d0}, @var{d0}, #@var{0}}
3816 @item int64x1_t vsra_n_s64 (int64x1_t, int64x1_t, const int)
3817 @*@emph{Form of expected instruction(s):} @code{vsra.s64 @var{d0}, @var{d0}, #@var{0}}
3822 @item uint32x4_t vsraq_n_u32 (uint32x4_t, uint32x4_t, const int)
3823 @*@emph{Form of expected instruction(s):} @code{vsra.u32 @var{q0}, @var{q0}, #@var{0}}
3828 @item uint16x8_t vsraq_n_u16 (uint16x8_t, uint16x8_t, const int)
3829 @*@emph{Form of expected instruction(s):} @code{vsra.u16 @var{q0}, @var{q0}, #@var{0}}
3834 @item uint8x16_t vsraq_n_u8 (uint8x16_t, uint8x16_t, const int)
3835 @*@emph{Form of expected instruction(s):} @code{vsra.u8 @var{q0}, @var{q0}, #@var{0}}
3840 @item int32x4_t vsraq_n_s32 (int32x4_t, int32x4_t, const int)
3841 @*@emph{Form of expected instruction(s):} @code{vsra.s32 @var{q0}, @var{q0}, #@var{0}}
3846 @item int16x8_t vsraq_n_s16 (int16x8_t, int16x8_t, const int)
3847 @*@emph{Form of expected instruction(s):} @code{vsra.s16 @var{q0}, @var{q0}, #@var{0}}
3852 @item int8x16_t vsraq_n_s8 (int8x16_t, int8x16_t, const int)
3853 @*@emph{Form of expected instruction(s):} @code{vsra.s8 @var{q0}, @var{q0}, #@var{0}}
3858 @item uint64x2_t vsraq_n_u64 (uint64x2_t, uint64x2_t, const int)
3859 @*@emph{Form of expected instruction(s):} @code{vsra.u64 @var{q0}, @var{q0}, #@var{0}}
3864 @item int64x2_t vsraq_n_s64 (int64x2_t, int64x2_t, const int)
3865 @*@emph{Form of expected instruction(s):} @code{vsra.s64 @var{q0}, @var{q0}, #@var{0}}
3870 @item uint32x2_t vrsra_n_u32 (uint32x2_t, uint32x2_t, const int)
3871 @*@emph{Form of expected instruction(s):} @code{vrsra.u32 @var{d0}, @var{d0}, #@var{0}}
3876 @item uint16x4_t vrsra_n_u16 (uint16x4_t, uint16x4_t, const int)
3877 @*@emph{Form of expected instruction(s):} @code{vrsra.u16 @var{d0}, @var{d0}, #@var{0}}
3882 @item uint8x8_t vrsra_n_u8 (uint8x8_t, uint8x8_t, const int)
3883 @*@emph{Form of expected instruction(s):} @code{vrsra.u8 @var{d0}, @var{d0}, #@var{0}}
3888 @item int32x2_t vrsra_n_s32 (int32x2_t, int32x2_t, const int)
3889 @*@emph{Form of expected instruction(s):} @code{vrsra.s32 @var{d0}, @var{d0}, #@var{0}}
3894 @item int16x4_t vrsra_n_s16 (int16x4_t, int16x4_t, const int)
3895 @*@emph{Form of expected instruction(s):} @code{vrsra.s16 @var{d0}, @var{d0}, #@var{0}}
3900 @item int8x8_t vrsra_n_s8 (int8x8_t, int8x8_t, const int)
3901 @*@emph{Form of expected instruction(s):} @code{vrsra.s8 @var{d0}, @var{d0}, #@var{0}}
3906 @item uint64x1_t vrsra_n_u64 (uint64x1_t, uint64x1_t, const int)
3907 @*@emph{Form of expected instruction(s):} @code{vrsra.u64 @var{d0}, @var{d0}, #@var{0}}
3912 @item int64x1_t vrsra_n_s64 (int64x1_t, int64x1_t, const int)
3913 @*@emph{Form of expected instruction(s):} @code{vrsra.s64 @var{d0}, @var{d0}, #@var{0}}
3918 @item uint32x4_t vrsraq_n_u32 (uint32x4_t, uint32x4_t, const int)
3919 @*@emph{Form of expected instruction(s):} @code{vrsra.u32 @var{q0}, @var{q0}, #@var{0}}
3924 @item uint16x8_t vrsraq_n_u16 (uint16x8_t, uint16x8_t, const int)
3925 @*@emph{Form of expected instruction(s):} @code{vrsra.u16 @var{q0}, @var{q0}, #@var{0}}
3930 @item uint8x16_t vrsraq_n_u8 (uint8x16_t, uint8x16_t, const int)
3931 @*@emph{Form of expected instruction(s):} @code{vrsra.u8 @var{q0}, @var{q0}, #@var{0}}
3936 @item int32x4_t vrsraq_n_s32 (int32x4_t, int32x4_t, const int)
3937 @*@emph{Form of expected instruction(s):} @code{vrsra.s32 @var{q0}, @var{q0}, #@var{0}}
3942 @item int16x8_t vrsraq_n_s16 (int16x8_t, int16x8_t, const int)
3943 @*@emph{Form of expected instruction(s):} @code{vrsra.s16 @var{q0}, @var{q0}, #@var{0}}
3948 @item int8x16_t vrsraq_n_s8 (int8x16_t, int8x16_t, const int)
3949 @*@emph{Form of expected instruction(s):} @code{vrsra.s8 @var{q0}, @var{q0}, #@var{0}}
3954 @item uint64x2_t vrsraq_n_u64 (uint64x2_t, uint64x2_t, const int)
3955 @*@emph{Form of expected instruction(s):} @code{vrsra.u64 @var{q0}, @var{q0}, #@var{0}}
3960 @item int64x2_t vrsraq_n_s64 (int64x2_t, int64x2_t, const int)
3961 @*@emph{Form of expected instruction(s):} @code{vrsra.s64 @var{q0}, @var{q0}, #@var{0}}
3967 @subsubsection Vector shift right and insert
3970 @item uint32x2_t vsri_n_u32 (uint32x2_t, uint32x2_t, const int)
3971 @*@emph{Form of expected instruction(s):} @code{vsri.32 @var{d0}, @var{d0}, #@var{0}}
3976 @item uint16x4_t vsri_n_u16 (uint16x4_t, uint16x4_t, const int)
3977 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
3982 @item uint8x8_t vsri_n_u8 (uint8x8_t, uint8x8_t, const int)
3983 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
3988 @item int32x2_t vsri_n_s32 (int32x2_t, int32x2_t, const int)
3989 @*@emph{Form of expected instruction(s):} @code{vsri.32 @var{d0}, @var{d0}, #@var{0}}
3994 @item int16x4_t vsri_n_s16 (int16x4_t, int16x4_t, const int)
3995 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
4000 @item int8x8_t vsri_n_s8 (int8x8_t, int8x8_t, const int)
4001 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
4006 @item uint64x1_t vsri_n_u64 (uint64x1_t, uint64x1_t, const int)
4007 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{d0}, @var{d0}, #@var{0}}
4012 @item int64x1_t vsri_n_s64 (int64x1_t, int64x1_t, const int)
4013 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{d0}, @var{d0}, #@var{0}}
4018 @item poly16x4_t vsri_n_p16 (poly16x4_t, poly16x4_t, const int)
4019 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{d0}, @var{d0}, #@var{0}}
4024 @item poly8x8_t vsri_n_p8 (poly8x8_t, poly8x8_t, const int)
4025 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{d0}, @var{d0}, #@var{0}}
4030 @item uint32x4_t vsriq_n_u32 (uint32x4_t, uint32x4_t, const int)
4031 @*@emph{Form of expected instruction(s):} @code{vsri.32 @var{q0}, @var{q0}, #@var{0}}
4036 @item uint16x8_t vsriq_n_u16 (uint16x8_t, uint16x8_t, const int)
4037 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
4042 @item uint8x16_t vsriq_n_u8 (uint8x16_t, uint8x16_t, const int)
4043 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
4048 @item int32x4_t vsriq_n_s32 (int32x4_t, int32x4_t, const int)
4049 @*@emph{Form of expected instruction(s):} @code{vsri.32 @var{q0}, @var{q0}, #@var{0}}
4054 @item int16x8_t vsriq_n_s16 (int16x8_t, int16x8_t, const int)
4055 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
4060 @item int8x16_t vsriq_n_s8 (int8x16_t, int8x16_t, const int)
4061 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
4066 @item uint64x2_t vsriq_n_u64 (uint64x2_t, uint64x2_t, const int)
4067 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{q0}, @var{q0}, #@var{0}}
4072 @item int64x2_t vsriq_n_s64 (int64x2_t, int64x2_t, const int)
4073 @*@emph{Form of expected instruction(s):} @code{vsri.64 @var{q0}, @var{q0}, #@var{0}}
4078 @item poly16x8_t vsriq_n_p16 (poly16x8_t, poly16x8_t, const int)
4079 @*@emph{Form of expected instruction(s):} @code{vsri.16 @var{q0}, @var{q0}, #@var{0}}
4084 @item poly8x16_t vsriq_n_p8 (poly8x16_t, poly8x16_t, const int)
4085 @*@emph{Form of expected instruction(s):} @code{vsri.8 @var{q0}, @var{q0}, #@var{0}}
4091 @subsubsection Vector shift left and insert
4094 @item uint32x2_t vsli_n_u32 (uint32x2_t, uint32x2_t, const int)
4095 @*@emph{Form of expected instruction(s):} @code{vsli.32 @var{d0}, @var{d0}, #@var{0}}
4100 @item uint16x4_t vsli_n_u16 (uint16x4_t, uint16x4_t, const int)
4101 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
4106 @item uint8x8_t vsli_n_u8 (uint8x8_t, uint8x8_t, const int)
4107 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
4112 @item int32x2_t vsli_n_s32 (int32x2_t, int32x2_t, const int)
4113 @*@emph{Form of expected instruction(s):} @code{vsli.32 @var{d0}, @var{d0}, #@var{0}}
4118 @item int16x4_t vsli_n_s16 (int16x4_t, int16x4_t, const int)
4119 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
4124 @item int8x8_t vsli_n_s8 (int8x8_t, int8x8_t, const int)
4125 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
4130 @item uint64x1_t vsli_n_u64 (uint64x1_t, uint64x1_t, const int)
4131 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{d0}, @var{d0}, #@var{0}}
4136 @item int64x1_t vsli_n_s64 (int64x1_t, int64x1_t, const int)
4137 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{d0}, @var{d0}, #@var{0}}
4142 @item poly16x4_t vsli_n_p16 (poly16x4_t, poly16x4_t, const int)
4143 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{d0}, @var{d0}, #@var{0}}
4148 @item poly8x8_t vsli_n_p8 (poly8x8_t, poly8x8_t, const int)
4149 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{d0}, @var{d0}, #@var{0}}
4154 @item uint32x4_t vsliq_n_u32 (uint32x4_t, uint32x4_t, const int)
4155 @*@emph{Form of expected instruction(s):} @code{vsli.32 @var{q0}, @var{q0}, #@var{0}}
4160 @item uint16x8_t vsliq_n_u16 (uint16x8_t, uint16x8_t, const int)
4161 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
4166 @item uint8x16_t vsliq_n_u8 (uint8x16_t, uint8x16_t, const int)
4167 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
4172 @item int32x4_t vsliq_n_s32 (int32x4_t, int32x4_t, const int)
4173 @*@emph{Form of expected instruction(s):} @code{vsli.32 @var{q0}, @var{q0}, #@var{0}}
4178 @item int16x8_t vsliq_n_s16 (int16x8_t, int16x8_t, const int)
4179 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
4184 @item int8x16_t vsliq_n_s8 (int8x16_t, int8x16_t, const int)
4185 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
4190 @item uint64x2_t vsliq_n_u64 (uint64x2_t, uint64x2_t, const int)
4191 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{q0}, @var{q0}, #@var{0}}
4196 @item int64x2_t vsliq_n_s64 (int64x2_t, int64x2_t, const int)
4197 @*@emph{Form of expected instruction(s):} @code{vsli.64 @var{q0}, @var{q0}, #@var{0}}
4202 @item poly16x8_t vsliq_n_p16 (poly16x8_t, poly16x8_t, const int)
4203 @*@emph{Form of expected instruction(s):} @code{vsli.16 @var{q0}, @var{q0}, #@var{0}}
4208 @item poly8x16_t vsliq_n_p8 (poly8x16_t, poly8x16_t, const int)
4209 @*@emph{Form of expected instruction(s):} @code{vsli.8 @var{q0}, @var{q0}, #@var{0}}
4215 @subsubsection Absolute value
4218 @item float32x2_t vabs_f32 (float32x2_t)
4219 @*@emph{Form of expected instruction(s):} @code{vabs.f32 @var{d0}, @var{d0}}
4224 @item int32x2_t vabs_s32 (int32x2_t)
4225 @*@emph{Form of expected instruction(s):} @code{vabs.s32 @var{d0}, @var{d0}}
4230 @item int16x4_t vabs_s16 (int16x4_t)
4231 @*@emph{Form of expected instruction(s):} @code{vabs.s16 @var{d0}, @var{d0}}
4236 @item int8x8_t vabs_s8 (int8x8_t)
4237 @*@emph{Form of expected instruction(s):} @code{vabs.s8 @var{d0}, @var{d0}}
4242 @item float32x4_t vabsq_f32 (float32x4_t)
4243 @*@emph{Form of expected instruction(s):} @code{vabs.f32 @var{q0}, @var{q0}}
4248 @item int32x4_t vabsq_s32 (int32x4_t)
4249 @*@emph{Form of expected instruction(s):} @code{vabs.s32 @var{q0}, @var{q0}}
4254 @item int16x8_t vabsq_s16 (int16x8_t)
4255 @*@emph{Form of expected instruction(s):} @code{vabs.s16 @var{q0}, @var{q0}}
4260 @item int8x16_t vabsq_s8 (int8x16_t)
4261 @*@emph{Form of expected instruction(s):} @code{vabs.s8 @var{q0}, @var{q0}}
4266 @item int32x2_t vqabs_s32 (int32x2_t)
4267 @*@emph{Form of expected instruction(s):} @code{vqabs.s32 @var{d0}, @var{d0}}
4272 @item int16x4_t vqabs_s16 (int16x4_t)
4273 @*@emph{Form of expected instruction(s):} @code{vqabs.s16 @var{d0}, @var{d0}}
4278 @item int8x8_t vqabs_s8 (int8x8_t)
4279 @*@emph{Form of expected instruction(s):} @code{vqabs.s8 @var{d0}, @var{d0}}
4284 @item int32x4_t vqabsq_s32 (int32x4_t)
4285 @*@emph{Form of expected instruction(s):} @code{vqabs.s32 @var{q0}, @var{q0}}
4290 @item int16x8_t vqabsq_s16 (int16x8_t)
4291 @*@emph{Form of expected instruction(s):} @code{vqabs.s16 @var{q0}, @var{q0}}
4296 @item int8x16_t vqabsq_s8 (int8x16_t)
4297 @*@emph{Form of expected instruction(s):} @code{vqabs.s8 @var{q0}, @var{q0}}
4303 @subsubsection Negation
4306 @item float32x2_t vneg_f32 (float32x2_t)
4307 @*@emph{Form of expected instruction(s):} @code{vneg.f32 @var{d0}, @var{d0}}
4312 @item int32x2_t vneg_s32 (int32x2_t)
4313 @*@emph{Form of expected instruction(s):} @code{vneg.s32 @var{d0}, @var{d0}}
4318 @item int16x4_t vneg_s16 (int16x4_t)
4319 @*@emph{Form of expected instruction(s):} @code{vneg.s16 @var{d0}, @var{d0}}
4324 @item int8x8_t vneg_s8 (int8x8_t)
4325 @*@emph{Form of expected instruction(s):} @code{vneg.s8 @var{d0}, @var{d0}}
4330 @item float32x4_t vnegq_f32 (float32x4_t)
4331 @*@emph{Form of expected instruction(s):} @code{vneg.f32 @var{q0}, @var{q0}}
4336 @item int32x4_t vnegq_s32 (int32x4_t)
4337 @*@emph{Form of expected instruction(s):} @code{vneg.s32 @var{q0}, @var{q0}}
4342 @item int16x8_t vnegq_s16 (int16x8_t)
4343 @*@emph{Form of expected instruction(s):} @code{vneg.s16 @var{q0}, @var{q0}}
4348 @item int8x16_t vnegq_s8 (int8x16_t)
4349 @*@emph{Form of expected instruction(s):} @code{vneg.s8 @var{q0}, @var{q0}}
4354 @item int32x2_t vqneg_s32 (int32x2_t)
4355 @*@emph{Form of expected instruction(s):} @code{vqneg.s32 @var{d0}, @var{d0}}
4360 @item int16x4_t vqneg_s16 (int16x4_t)
4361 @*@emph{Form of expected instruction(s):} @code{vqneg.s16 @var{d0}, @var{d0}}
4366 @item int8x8_t vqneg_s8 (int8x8_t)
4367 @*@emph{Form of expected instruction(s):} @code{vqneg.s8 @var{d0}, @var{d0}}
4372 @item int32x4_t vqnegq_s32 (int32x4_t)
4373 @*@emph{Form of expected instruction(s):} @code{vqneg.s32 @var{q0}, @var{q0}}
4378 @item int16x8_t vqnegq_s16 (int16x8_t)
4379 @*@emph{Form of expected instruction(s):} @code{vqneg.s16 @var{q0}, @var{q0}}
4384 @item int8x16_t vqnegq_s8 (int8x16_t)
4385 @*@emph{Form of expected instruction(s):} @code{vqneg.s8 @var{q0}, @var{q0}}
4391 @subsubsection Bitwise not
4394 @item uint32x2_t vmvn_u32 (uint32x2_t)
4395 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4400 @item uint16x4_t vmvn_u16 (uint16x4_t)
4401 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4406 @item uint8x8_t vmvn_u8 (uint8x8_t)
4407 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4412 @item int32x2_t vmvn_s32 (int32x2_t)
4413 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4418 @item int16x4_t vmvn_s16 (int16x4_t)
4419 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4424 @item int8x8_t vmvn_s8 (int8x8_t)
4425 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4430 @item poly8x8_t vmvn_p8 (poly8x8_t)
4431 @*@emph{Form of expected instruction(s):} @code{vmvn @var{d0}, @var{d0}}
4436 @item uint32x4_t vmvnq_u32 (uint32x4_t)
4437 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4442 @item uint16x8_t vmvnq_u16 (uint16x8_t)
4443 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4448 @item uint8x16_t vmvnq_u8 (uint8x16_t)
4449 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4454 @item int32x4_t vmvnq_s32 (int32x4_t)
4455 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4460 @item int16x8_t vmvnq_s16 (int16x8_t)
4461 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4466 @item int8x16_t vmvnq_s8 (int8x16_t)
4467 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4472 @item poly8x16_t vmvnq_p8 (poly8x16_t)
4473 @*@emph{Form of expected instruction(s):} @code{vmvn @var{q0}, @var{q0}}
4479 @subsubsection Count leading sign bits
4482 @item int32x2_t vcls_s32 (int32x2_t)
4483 @*@emph{Form of expected instruction(s):} @code{vcls.s32 @var{d0}, @var{d0}}
4488 @item int16x4_t vcls_s16 (int16x4_t)
4489 @*@emph{Form of expected instruction(s):} @code{vcls.s16 @var{d0}, @var{d0}}
4494 @item int8x8_t vcls_s8 (int8x8_t)
4495 @*@emph{Form of expected instruction(s):} @code{vcls.s8 @var{d0}, @var{d0}}
4500 @item int32x4_t vclsq_s32 (int32x4_t)
4501 @*@emph{Form of expected instruction(s):} @code{vcls.s32 @var{q0}, @var{q0}}
4506 @item int16x8_t vclsq_s16 (int16x8_t)
4507 @*@emph{Form of expected instruction(s):} @code{vcls.s16 @var{q0}, @var{q0}}
4512 @item int8x16_t vclsq_s8 (int8x16_t)
4513 @*@emph{Form of expected instruction(s):} @code{vcls.s8 @var{q0}, @var{q0}}
4519 @subsubsection Count leading zeros
4522 @item uint32x2_t vclz_u32 (uint32x2_t)
4523 @*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{d0}, @var{d0}}
4528 @item uint16x4_t vclz_u16 (uint16x4_t)
4529 @*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{d0}, @var{d0}}
4534 @item uint8x8_t vclz_u8 (uint8x8_t)
4535 @*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{d0}, @var{d0}}
4540 @item int32x2_t vclz_s32 (int32x2_t)
4541 @*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{d0}, @var{d0}}
4546 @item int16x4_t vclz_s16 (int16x4_t)
4547 @*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{d0}, @var{d0}}
4552 @item int8x8_t vclz_s8 (int8x8_t)
4553 @*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{d0}, @var{d0}}
4558 @item uint32x4_t vclzq_u32 (uint32x4_t)
4559 @*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{q0}, @var{q0}}
4564 @item uint16x8_t vclzq_u16 (uint16x8_t)
4565 @*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{q0}, @var{q0}}
4570 @item uint8x16_t vclzq_u8 (uint8x16_t)
4571 @*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{q0}, @var{q0}}
4576 @item int32x4_t vclzq_s32 (int32x4_t)
4577 @*@emph{Form of expected instruction(s):} @code{vclz.i32 @var{q0}, @var{q0}}
4582 @item int16x8_t vclzq_s16 (int16x8_t)
4583 @*@emph{Form of expected instruction(s):} @code{vclz.i16 @var{q0}, @var{q0}}
4588 @item int8x16_t vclzq_s8 (int8x16_t)
4589 @*@emph{Form of expected instruction(s):} @code{vclz.i8 @var{q0}, @var{q0}}
4595 @subsubsection Count number of set bits
4598 @item uint8x8_t vcnt_u8 (uint8x8_t)
4599 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
4604 @item int8x8_t vcnt_s8 (int8x8_t)
4605 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
4610 @item poly8x8_t vcnt_p8 (poly8x8_t)
4611 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{d0}, @var{d0}}
4616 @item uint8x16_t vcntq_u8 (uint8x16_t)
4617 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
4622 @item int8x16_t vcntq_s8 (int8x16_t)
4623 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
4628 @item poly8x16_t vcntq_p8 (poly8x16_t)
4629 @*@emph{Form of expected instruction(s):} @code{vcnt.8 @var{q0}, @var{q0}}
4635 @subsubsection Reciprocal estimate
4638 @item float32x2_t vrecpe_f32 (float32x2_t)
4639 @*@emph{Form of expected instruction(s):} @code{vrecpe.f32 @var{d0}, @var{d0}}
4644 @item uint32x2_t vrecpe_u32 (uint32x2_t)
4645 @*@emph{Form of expected instruction(s):} @code{vrecpe.u32 @var{d0}, @var{d0}}
4650 @item float32x4_t vrecpeq_f32 (float32x4_t)
4651 @*@emph{Form of expected instruction(s):} @code{vrecpe.f32 @var{q0}, @var{q0}}
4656 @item uint32x4_t vrecpeq_u32 (uint32x4_t)
4657 @*@emph{Form of expected instruction(s):} @code{vrecpe.u32 @var{q0}, @var{q0}}
4663 @subsubsection Reciprocal square-root estimate
4666 @item float32x2_t vrsqrte_f32 (float32x2_t)
4667 @*@emph{Form of expected instruction(s):} @code{vrsqrte.f32 @var{d0}, @var{d0}}
4672 @item uint32x2_t vrsqrte_u32 (uint32x2_t)
4673 @*@emph{Form of expected instruction(s):} @code{vrsqrte.u32 @var{d0}, @var{d0}}
4678 @item float32x4_t vrsqrteq_f32 (float32x4_t)
4679 @*@emph{Form of expected instruction(s):} @code{vrsqrte.f32 @var{q0}, @var{q0}}
4684 @item uint32x4_t vrsqrteq_u32 (uint32x4_t)
4685 @*@emph{Form of expected instruction(s):} @code{vrsqrte.u32 @var{q0}, @var{q0}}
4691 @subsubsection Get lanes from a vector
4694 @item uint32_t vget_lane_u32 (uint32x2_t, const int)
4695 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4700 @item uint16_t vget_lane_u16 (uint16x4_t, const int)
4701 @*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4706 @item uint8_t vget_lane_u8 (uint8x8_t, const int)
4707 @*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4712 @item int32_t vget_lane_s32 (int32x2_t, const int)
4713 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4718 @item int16_t vget_lane_s16 (int16x4_t, const int)
4719 @*@emph{Form of expected instruction(s):} @code{vmov.s16 @var{r0}, @var{d0}[@var{0}]}
4724 @item int8_t vget_lane_s8 (int8x8_t, const int)
4725 @*@emph{Form of expected instruction(s):} @code{vmov.s8 @var{r0}, @var{d0}[@var{0}]}
4730 @item float32_t vget_lane_f32 (float32x2_t, const int)
4731 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4736 @item poly16_t vget_lane_p16 (poly16x4_t, const int)
4737 @*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4742 @item poly8_t vget_lane_p8 (poly8x8_t, const int)
4743 @*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4748 @item uint64_t vget_lane_u64 (uint64x1_t, const int)
4753 @item int64_t vget_lane_s64 (int64x1_t, const int)
4758 @item uint32_t vgetq_lane_u32 (uint32x4_t, const int)
4759 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4764 @item uint16_t vgetq_lane_u16 (uint16x8_t, const int)
4765 @*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4770 @item uint8_t vgetq_lane_u8 (uint8x16_t, const int)
4771 @*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4776 @item int32_t vgetq_lane_s32 (int32x4_t, const int)
4777 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4782 @item int16_t vgetq_lane_s16 (int16x8_t, const int)
4783 @*@emph{Form of expected instruction(s):} @code{vmov.s16 @var{r0}, @var{d0}[@var{0}]}
4788 @item int8_t vgetq_lane_s8 (int8x16_t, const int)
4789 @*@emph{Form of expected instruction(s):} @code{vmov.s8 @var{r0}, @var{d0}[@var{0}]}
4794 @item float32_t vgetq_lane_f32 (float32x4_t, const int)
4795 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{r0}, @var{d0}[@var{0}]}
4800 @item poly16_t vgetq_lane_p16 (poly16x8_t, const int)
4801 @*@emph{Form of expected instruction(s):} @code{vmov.u16 @var{r0}, @var{d0}[@var{0}]}
4806 @item poly8_t vgetq_lane_p8 (poly8x16_t, const int)
4807 @*@emph{Form of expected instruction(s):} @code{vmov.u8 @var{r0}, @var{d0}[@var{0}]}
4812 @item uint64_t vgetq_lane_u64 (uint64x2_t, const int)
4813 @*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
4818 @item int64_t vgetq_lane_s64 (int64x2_t, const int)
4819 @*@emph{Form of expected instruction(s):} @code{vmov @var{r0}, @var{r0}, @var{d0}}
4825 @subsubsection Set lanes in a vector
4828 @item uint32x2_t vset_lane_u32 (uint32_t, uint32x2_t, const int)
4829 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4834 @item uint16x4_t vset_lane_u16 (uint16_t, uint16x4_t, const int)
4835 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4840 @item uint8x8_t vset_lane_u8 (uint8_t, uint8x8_t, const int)
4841 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4846 @item int32x2_t vset_lane_s32 (int32_t, int32x2_t, const int)
4847 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4852 @item int16x4_t vset_lane_s16 (int16_t, int16x4_t, const int)
4853 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4858 @item int8x8_t vset_lane_s8 (int8_t, int8x8_t, const int)
4859 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4864 @item float32x2_t vset_lane_f32 (float32_t, float32x2_t, const int)
4865 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4870 @item poly16x4_t vset_lane_p16 (poly16_t, poly16x4_t, const int)
4871 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4876 @item poly8x8_t vset_lane_p8 (poly8_t, poly8x8_t, const int)
4877 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4882 @item uint64x1_t vset_lane_u64 (uint64_t, uint64x1_t, const int)
4887 @item int64x1_t vset_lane_s64 (int64_t, int64x1_t, const int)
4892 @item uint32x4_t vsetq_lane_u32 (uint32_t, uint32x4_t, const int)
4893 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4898 @item uint16x8_t vsetq_lane_u16 (uint16_t, uint16x8_t, const int)
4899 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4904 @item uint8x16_t vsetq_lane_u8 (uint8_t, uint8x16_t, const int)
4905 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4910 @item int32x4_t vsetq_lane_s32 (int32_t, int32x4_t, const int)
4911 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4916 @item int16x8_t vsetq_lane_s16 (int16_t, int16x8_t, const int)
4917 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4922 @item int8x16_t vsetq_lane_s8 (int8_t, int8x16_t, const int)
4923 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4928 @item float32x4_t vsetq_lane_f32 (float32_t, float32x4_t, const int)
4929 @*@emph{Form of expected instruction(s):} @code{vmov.32 @var{d0}[@var{0}], @var{r0}}
4934 @item poly16x8_t vsetq_lane_p16 (poly16_t, poly16x8_t, const int)
4935 @*@emph{Form of expected instruction(s):} @code{vmov.16 @var{d0}[@var{0}], @var{r0}}
4940 @item poly8x16_t vsetq_lane_p8 (poly8_t, poly8x16_t, const int)
4941 @*@emph{Form of expected instruction(s):} @code{vmov.8 @var{d0}[@var{0}], @var{r0}}
4946 @item uint64x2_t vsetq_lane_u64 (uint64_t, uint64x2_t, const int)
4947 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
4952 @item int64x2_t vsetq_lane_s64 (int64_t, int64x2_t, const int)
4953 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{r0}, @var{r0}}
4959 @subsubsection Create vector from literal bit pattern
4962 @item uint32x2_t vcreate_u32 (uint64_t)
4967 @item uint16x4_t vcreate_u16 (uint64_t)
4972 @item uint8x8_t vcreate_u8 (uint64_t)
4977 @item int32x2_t vcreate_s32 (uint64_t)
4982 @item int16x4_t vcreate_s16 (uint64_t)
4987 @item int8x8_t vcreate_s8 (uint64_t)
4992 @item uint64x1_t vcreate_u64 (uint64_t)
4997 @item int64x1_t vcreate_s64 (uint64_t)
5002 @item float32x2_t vcreate_f32 (uint64_t)
5007 @item poly16x4_t vcreate_p16 (uint64_t)
5012 @item poly8x8_t vcreate_p8 (uint64_t)
5018 @subsubsection Set all lanes to the same value
5021 @item uint32x2_t vdup_n_u32 (uint32_t)
5022 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5027 @item uint16x4_t vdup_n_u16 (uint16_t)
5028 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5033 @item uint8x8_t vdup_n_u8 (uint8_t)
5034 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5039 @item int32x2_t vdup_n_s32 (int32_t)
5040 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5045 @item int16x4_t vdup_n_s16 (int16_t)
5046 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5051 @item int8x8_t vdup_n_s8 (int8_t)
5052 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5057 @item float32x2_t vdup_n_f32 (float32_t)
5058 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5063 @item poly16x4_t vdup_n_p16 (poly16_t)
5064 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5069 @item poly8x8_t vdup_n_p8 (poly8_t)
5070 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5075 @item uint64x1_t vdup_n_u64 (uint64_t)
5080 @item int64x1_t vdup_n_s64 (int64_t)
5085 @item uint32x4_t vdupq_n_u32 (uint32_t)
5086 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5091 @item uint16x8_t vdupq_n_u16 (uint16_t)
5092 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5097 @item uint8x16_t vdupq_n_u8 (uint8_t)
5098 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5103 @item int32x4_t vdupq_n_s32 (int32_t)
5104 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5109 @item int16x8_t vdupq_n_s16 (int16_t)
5110 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5115 @item int8x16_t vdupq_n_s8 (int8_t)
5116 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5121 @item float32x4_t vdupq_n_f32 (float32_t)
5122 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5127 @item poly16x8_t vdupq_n_p16 (poly16_t)
5128 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5133 @item poly8x16_t vdupq_n_p8 (poly8_t)
5134 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5139 @item uint64x2_t vdupq_n_u64 (uint64_t)
5144 @item int64x2_t vdupq_n_s64 (int64_t)
5149 @item uint32x2_t vmov_n_u32 (uint32_t)
5150 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5155 @item uint16x4_t vmov_n_u16 (uint16_t)
5156 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5161 @item uint8x8_t vmov_n_u8 (uint8_t)
5162 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5167 @item int32x2_t vmov_n_s32 (int32_t)
5168 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5173 @item int16x4_t vmov_n_s16 (int16_t)
5174 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5179 @item int8x8_t vmov_n_s8 (int8_t)
5180 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5185 @item float32x2_t vmov_n_f32 (float32_t)
5186 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{r0}}
5191 @item poly16x4_t vmov_n_p16 (poly16_t)
5192 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{r0}}
5197 @item poly8x8_t vmov_n_p8 (poly8_t)
5198 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{r0}}
5203 @item uint64x1_t vmov_n_u64 (uint64_t)
5208 @item int64x1_t vmov_n_s64 (int64_t)
5213 @item uint32x4_t vmovq_n_u32 (uint32_t)
5214 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5219 @item uint16x8_t vmovq_n_u16 (uint16_t)
5220 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5225 @item uint8x16_t vmovq_n_u8 (uint8_t)
5226 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5231 @item int32x4_t vmovq_n_s32 (int32_t)
5232 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5237 @item int16x8_t vmovq_n_s16 (int16_t)
5238 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5243 @item int8x16_t vmovq_n_s8 (int8_t)
5244 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5249 @item float32x4_t vmovq_n_f32 (float32_t)
5250 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{r0}}
5255 @item poly16x8_t vmovq_n_p16 (poly16_t)
5256 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{r0}}
5261 @item poly8x16_t vmovq_n_p8 (poly8_t)
5262 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{r0}}
5267 @item uint64x2_t vmovq_n_u64 (uint64_t)
5272 @item int64x2_t vmovq_n_s64 (int64_t)
5277 @item uint32x2_t vdup_lane_u32 (uint32x2_t, const int)
5278 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
5283 @item uint16x4_t vdup_lane_u16 (uint16x4_t, const int)
5284 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
5289 @item uint8x8_t vdup_lane_u8 (uint8x8_t, const int)
5290 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
5295 @item int32x2_t vdup_lane_s32 (int32x2_t, const int)
5296 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
5301 @item int16x4_t vdup_lane_s16 (int16x4_t, const int)
5302 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
5307 @item int8x8_t vdup_lane_s8 (int8x8_t, const int)
5308 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
5313 @item float32x2_t vdup_lane_f32 (float32x2_t, const int)
5314 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{d0}, @var{d0}[@var{0}]}
5319 @item poly16x4_t vdup_lane_p16 (poly16x4_t, const int)
5320 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{d0}, @var{d0}[@var{0}]}
5325 @item poly8x8_t vdup_lane_p8 (poly8x8_t, const int)
5326 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{d0}, @var{d0}[@var{0}]}
5331 @item uint64x1_t vdup_lane_u64 (uint64x1_t, const int)
5336 @item int64x1_t vdup_lane_s64 (int64x1_t, const int)
5341 @item uint32x4_t vdupq_lane_u32 (uint32x2_t, const int)
5342 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
5347 @item uint16x8_t vdupq_lane_u16 (uint16x4_t, const int)
5348 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
5353 @item uint8x16_t vdupq_lane_u8 (uint8x8_t, const int)
5354 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
5359 @item int32x4_t vdupq_lane_s32 (int32x2_t, const int)
5360 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
5365 @item int16x8_t vdupq_lane_s16 (int16x4_t, const int)
5366 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
5371 @item int8x16_t vdupq_lane_s8 (int8x8_t, const int)
5372 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
5377 @item float32x4_t vdupq_lane_f32 (float32x2_t, const int)
5378 @*@emph{Form of expected instruction(s):} @code{vdup.32 @var{q0}, @var{d0}[@var{0}]}
5383 @item poly16x8_t vdupq_lane_p16 (poly16x4_t, const int)
5384 @*@emph{Form of expected instruction(s):} @code{vdup.16 @var{q0}, @var{d0}[@var{0}]}
5389 @item poly8x16_t vdupq_lane_p8 (poly8x8_t, const int)
5390 @*@emph{Form of expected instruction(s):} @code{vdup.8 @var{q0}, @var{d0}[@var{0}]}
5395 @item uint64x2_t vdupq_lane_u64 (uint64x1_t, const int)
5400 @item int64x2_t vdupq_lane_s64 (int64x1_t, const int)
5406 @subsubsection Combining vectors
5409 @item uint32x4_t vcombine_u32 (uint32x2_t, uint32x2_t)
5414 @item uint16x8_t vcombine_u16 (uint16x4_t, uint16x4_t)
5419 @item uint8x16_t vcombine_u8 (uint8x8_t, uint8x8_t)
5424 @item int32x4_t vcombine_s32 (int32x2_t, int32x2_t)
5429 @item int16x8_t vcombine_s16 (int16x4_t, int16x4_t)
5434 @item int8x16_t vcombine_s8 (int8x8_t, int8x8_t)
5439 @item uint64x2_t vcombine_u64 (uint64x1_t, uint64x1_t)
5444 @item int64x2_t vcombine_s64 (int64x1_t, int64x1_t)
5449 @item float32x4_t vcombine_f32 (float32x2_t, float32x2_t)
5454 @item poly16x8_t vcombine_p16 (poly16x4_t, poly16x4_t)
5459 @item poly8x16_t vcombine_p8 (poly8x8_t, poly8x8_t)
5465 @subsubsection Splitting vectors
5468 @item uint32x2_t vget_high_u32 (uint32x4_t)
5473 @item uint16x4_t vget_high_u16 (uint16x8_t)
5478 @item uint8x8_t vget_high_u8 (uint8x16_t)
5483 @item int32x2_t vget_high_s32 (int32x4_t)
5488 @item int16x4_t vget_high_s16 (int16x8_t)
5493 @item int8x8_t vget_high_s8 (int8x16_t)
5498 @item uint64x1_t vget_high_u64 (uint64x2_t)
5503 @item int64x1_t vget_high_s64 (int64x2_t)
5508 @item float32x2_t vget_high_f32 (float32x4_t)
5513 @item poly16x4_t vget_high_p16 (poly16x8_t)
5518 @item poly8x8_t vget_high_p8 (poly8x16_t)
5523 @item uint32x2_t vget_low_u32 (uint32x4_t)
5524 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5529 @item uint16x4_t vget_low_u16 (uint16x8_t)
5530 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5535 @item uint8x8_t vget_low_u8 (uint8x16_t)
5536 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5541 @item int32x2_t vget_low_s32 (int32x4_t)
5542 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5547 @item int16x4_t vget_low_s16 (int16x8_t)
5548 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5553 @item int8x8_t vget_low_s8 (int8x16_t)
5554 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5559 @item float32x2_t vget_low_f32 (float32x4_t)
5560 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5565 @item poly16x4_t vget_low_p16 (poly16x8_t)
5566 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5571 @item poly8x8_t vget_low_p8 (poly8x16_t)
5572 @*@emph{Form of expected instruction(s):} @code{vmov @var{d0}, @var{d0}}
5577 @item uint64x1_t vget_low_u64 (uint64x2_t)
5582 @item int64x1_t vget_low_s64 (int64x2_t)
5588 @subsubsection Conversions
5591 @item float32x2_t vcvt_f32_u32 (uint32x2_t)
5592 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{d0}, @var{d0}}
5597 @item float32x2_t vcvt_f32_s32 (int32x2_t)
5598 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{d0}, @var{d0}}
5603 @item uint32x2_t vcvt_u32_f32 (float32x2_t)
5604 @*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{d0}, @var{d0}}
5609 @item int32x2_t vcvt_s32_f32 (float32x2_t)
5610 @*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{d0}, @var{d0}}
5615 @item float32x4_t vcvtq_f32_u32 (uint32x4_t)
5616 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{q0}, @var{q0}}
5621 @item float32x4_t vcvtq_f32_s32 (int32x4_t)
5622 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{q0}, @var{q0}}
5627 @item uint32x4_t vcvtq_u32_f32 (float32x4_t)
5628 @*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{q0}, @var{q0}}
5633 @item int32x4_t vcvtq_s32_f32 (float32x4_t)
5634 @*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{q0}, @var{q0}}
5639 @item float32x2_t vcvt_n_f32_u32 (uint32x2_t, const int)
5640 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{d0}, @var{d0}, #@var{0}}
5645 @item float32x2_t vcvt_n_f32_s32 (int32x2_t, const int)
5646 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{d0}, @var{d0}, #@var{0}}
5651 @item uint32x2_t vcvt_n_u32_f32 (float32x2_t, const int)
5652 @*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{d0}, @var{d0}, #@var{0}}
5657 @item int32x2_t vcvt_n_s32_f32 (float32x2_t, const int)
5658 @*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{d0}, @var{d0}, #@var{0}}
5663 @item float32x4_t vcvtq_n_f32_u32 (uint32x4_t, const int)
5664 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.u32 @var{q0}, @var{q0}, #@var{0}}
5669 @item float32x4_t vcvtq_n_f32_s32 (int32x4_t, const int)
5670 @*@emph{Form of expected instruction(s):} @code{vcvt.f32.s32 @var{q0}, @var{q0}, #@var{0}}
5675 @item uint32x4_t vcvtq_n_u32_f32 (float32x4_t, const int)
5676 @*@emph{Form of expected instruction(s):} @code{vcvt.u32.f32 @var{q0}, @var{q0}, #@var{0}}
5681 @item int32x4_t vcvtq_n_s32_f32 (float32x4_t, const int)
5682 @*@emph{Form of expected instruction(s):} @code{vcvt.s32.f32 @var{q0}, @var{q0}, #@var{0}}
5688 @subsubsection Move, single_opcode narrowing
5691 @item uint32x2_t vmovn_u64 (uint64x2_t)
5692 @*@emph{Form of expected instruction(s):} @code{vmovn.i64 @var{d0}, @var{q0}}
5697 @item uint16x4_t vmovn_u32 (uint32x4_t)
5698 @*@emph{Form of expected instruction(s):} @code{vmovn.i32 @var{d0}, @var{q0}}
5703 @item uint8x8_t vmovn_u16 (uint16x8_t)
5704 @*@emph{Form of expected instruction(s):} @code{vmovn.i16 @var{d0}, @var{q0}}
5709 @item int32x2_t vmovn_s64 (int64x2_t)
5710 @*@emph{Form of expected instruction(s):} @code{vmovn.i64 @var{d0}, @var{q0}}
5715 @item int16x4_t vmovn_s32 (int32x4_t)
5716 @*@emph{Form of expected instruction(s):} @code{vmovn.i32 @var{d0}, @var{q0}}
5721 @item int8x8_t vmovn_s16 (int16x8_t)
5722 @*@emph{Form of expected instruction(s):} @code{vmovn.i16 @var{d0}, @var{q0}}
5727 @item uint32x2_t vqmovn_u64 (uint64x2_t)
5728 @*@emph{Form of expected instruction(s):} @code{vqmovn.u64 @var{d0}, @var{q0}}
5733 @item uint16x4_t vqmovn_u32 (uint32x4_t)
5734 @*@emph{Form of expected instruction(s):} @code{vqmovn.u32 @var{d0}, @var{q0}}
5739 @item uint8x8_t vqmovn_u16 (uint16x8_t)
5740 @*@emph{Form of expected instruction(s):} @code{vqmovn.u16 @var{d0}, @var{q0}}
5745 @item int32x2_t vqmovn_s64 (int64x2_t)
5746 @*@emph{Form of expected instruction(s):} @code{vqmovn.s64 @var{d0}, @var{q0}}
5751 @item int16x4_t vqmovn_s32 (int32x4_t)
5752 @*@emph{Form of expected instruction(s):} @code{vqmovn.s32 @var{d0}, @var{q0}}
5757 @item int8x8_t vqmovn_s16 (int16x8_t)
5758 @*@emph{Form of expected instruction(s):} @code{vqmovn.s16 @var{d0}, @var{q0}}
5763 @item uint32x2_t vqmovun_s64 (int64x2_t)
5764 @*@emph{Form of expected instruction(s):} @code{vqmovun.s64 @var{d0}, @var{q0}}
5769 @item uint16x4_t vqmovun_s32 (int32x4_t)
5770 @*@emph{Form of expected instruction(s):} @code{vqmovun.s32 @var{d0}, @var{q0}}
5775 @item uint8x8_t vqmovun_s16 (int16x8_t)
5776 @*@emph{Form of expected instruction(s):} @code{vqmovun.s16 @var{d0}, @var{q0}}
5782 @subsubsection Move, single_opcode long
5785 @item uint64x2_t vmovl_u32 (uint32x2_t)
5786 @*@emph{Form of expected instruction(s):} @code{vmovl.u32 @var{q0}, @var{d0}}
5791 @item uint32x4_t vmovl_u16 (uint16x4_t)
5792 @*@emph{Form of expected instruction(s):} @code{vmovl.u16 @var{q0}, @var{d0}}
5797 @item uint16x8_t vmovl_u8 (uint8x8_t)
5798 @*@emph{Form of expected instruction(s):} @code{vmovl.u8 @var{q0}, @var{d0}}
5803 @item int64x2_t vmovl_s32 (int32x2_t)
5804 @*@emph{Form of expected instruction(s):} @code{vmovl.s32 @var{q0}, @var{d0}}
5809 @item int32x4_t vmovl_s16 (int16x4_t)
5810 @*@emph{Form of expected instruction(s):} @code{vmovl.s16 @var{q0}, @var{d0}}
5815 @item int16x8_t vmovl_s8 (int8x8_t)
5816 @*@emph{Form of expected instruction(s):} @code{vmovl.s8 @var{q0}, @var{d0}}
5822 @subsubsection Table lookup
5825 @item poly8x8_t vtbl1_p8 (poly8x8_t, uint8x8_t)
5826 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5831 @item int8x8_t vtbl1_s8 (int8x8_t, int8x8_t)
5832 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5837 @item uint8x8_t vtbl1_u8 (uint8x8_t, uint8x8_t)
5838 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5843 @item poly8x8_t vtbl2_p8 (poly8x8x2_t, uint8x8_t)
5844 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5849 @item int8x8_t vtbl2_s8 (int8x8x2_t, int8x8_t)
5850 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5855 @item uint8x8_t vtbl2_u8 (uint8x8x2_t, uint8x8_t)
5856 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5861 @item poly8x8_t vtbl3_p8 (poly8x8x3_t, uint8x8_t)
5862 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5867 @item int8x8_t vtbl3_s8 (int8x8x3_t, int8x8_t)
5868 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5873 @item uint8x8_t vtbl3_u8 (uint8x8x3_t, uint8x8_t)
5874 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5879 @item poly8x8_t vtbl4_p8 (poly8x8x4_t, uint8x8_t)
5880 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5885 @item int8x8_t vtbl4_s8 (int8x8x4_t, int8x8_t)
5886 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5891 @item uint8x8_t vtbl4_u8 (uint8x8x4_t, uint8x8_t)
5892 @*@emph{Form of expected instruction(s):} @code{vtbl.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5898 @subsubsection Extended table lookup
5901 @item poly8x8_t vtbx1_p8 (poly8x8_t, poly8x8_t, uint8x8_t)
5902 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5907 @item int8x8_t vtbx1_s8 (int8x8_t, int8x8_t, int8x8_t)
5908 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5913 @item uint8x8_t vtbx1_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
5914 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}@}, @var{d0}}
5919 @item poly8x8_t vtbx2_p8 (poly8x8_t, poly8x8x2_t, uint8x8_t)
5920 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5925 @item int8x8_t vtbx2_s8 (int8x8_t, int8x8x2_t, int8x8_t)
5926 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5931 @item uint8x8_t vtbx2_u8 (uint8x8_t, uint8x8x2_t, uint8x8_t)
5932 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}@}, @var{d0}}
5937 @item poly8x8_t vtbx3_p8 (poly8x8_t, poly8x8x3_t, uint8x8_t)
5938 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5943 @item int8x8_t vtbx3_s8 (int8x8_t, int8x8x3_t, int8x8_t)
5944 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5949 @item uint8x8_t vtbx3_u8 (uint8x8_t, uint8x8x3_t, uint8x8_t)
5950 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}@}, @var{d0}}
5955 @item poly8x8_t vtbx4_p8 (poly8x8_t, poly8x8x4_t, uint8x8_t)
5956 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5961 @item int8x8_t vtbx4_s8 (int8x8_t, int8x8x4_t, int8x8_t)
5962 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5967 @item uint8x8_t vtbx4_u8 (uint8x8_t, uint8x8x4_t, uint8x8_t)
5968 @*@emph{Form of expected instruction(s):} @code{vtbx.8 @var{d0}, @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, @var{d0}}
5974 @subsubsection Multiply, lane
5977 @item float32x2_t vmul_lane_f32 (float32x2_t, float32x2_t, const int)
5978 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
5983 @item uint32x2_t vmul_lane_u32 (uint32x2_t, uint32x2_t, const int)
5984 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
5989 @item uint16x4_t vmul_lane_u16 (uint16x4_t, uint16x4_t, const int)
5990 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
5995 @item int32x2_t vmul_lane_s32 (int32x2_t, int32x2_t, const int)
5996 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6001 @item int16x4_t vmul_lane_s16 (int16x4_t, int16x4_t, const int)
6002 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6007 @item float32x4_t vmulq_lane_f32 (float32x4_t, float32x2_t, const int)
6008 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6013 @item uint32x4_t vmulq_lane_u32 (uint32x4_t, uint32x2_t, const int)
6014 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6019 @item uint16x8_t vmulq_lane_u16 (uint16x8_t, uint16x4_t, const int)
6020 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6025 @item int32x4_t vmulq_lane_s32 (int32x4_t, int32x2_t, const int)
6026 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6031 @item int16x8_t vmulq_lane_s16 (int16x8_t, int16x4_t, const int)
6032 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6038 @subsubsection Long multiply, lane
6041 @item uint64x2_t vmull_lane_u32 (uint32x2_t, uint32x2_t, const int)
6042 @*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6047 @item uint32x4_t vmull_lane_u16 (uint16x4_t, uint16x4_t, const int)
6048 @*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6053 @item int64x2_t vmull_lane_s32 (int32x2_t, int32x2_t, const int)
6054 @*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6059 @item int32x4_t vmull_lane_s16 (int16x4_t, int16x4_t, const int)
6060 @*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6066 @subsubsection Saturating doubling long multiply, lane
6069 @item int64x2_t vqdmull_lane_s32 (int32x2_t, int32x2_t, const int)
6070 @*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6075 @item int32x4_t vqdmull_lane_s16 (int16x4_t, int16x4_t, const int)
6076 @*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6082 @subsubsection Saturating doubling multiply high, lane
6085 @item int32x4_t vqdmulhq_lane_s32 (int32x4_t, int32x2_t, const int)
6086 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6091 @item int16x8_t vqdmulhq_lane_s16 (int16x8_t, int16x4_t, const int)
6092 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6097 @item int32x2_t vqdmulh_lane_s32 (int32x2_t, int32x2_t, const int)
6098 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6103 @item int16x4_t vqdmulh_lane_s16 (int16x4_t, int16x4_t, const int)
6104 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6109 @item int32x4_t vqrdmulhq_lane_s32 (int32x4_t, int32x2_t, const int)
6110 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6115 @item int16x8_t vqrdmulhq_lane_s16 (int16x8_t, int16x4_t, const int)
6116 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6121 @item int32x2_t vqrdmulh_lane_s32 (int32x2_t, int32x2_t, const int)
6122 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6127 @item int16x4_t vqrdmulh_lane_s16 (int16x4_t, int16x4_t, const int)
6128 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6134 @subsubsection Multiply-accumulate, lane
6137 @item float32x2_t vmla_lane_f32 (float32x2_t, float32x2_t, float32x2_t, const int)
6138 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6143 @item uint32x2_t vmla_lane_u32 (uint32x2_t, uint32x2_t, uint32x2_t, const int)
6144 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6149 @item uint16x4_t vmla_lane_u16 (uint16x4_t, uint16x4_t, uint16x4_t, const int)
6150 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6155 @item int32x2_t vmla_lane_s32 (int32x2_t, int32x2_t, int32x2_t, const int)
6156 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6161 @item int16x4_t vmla_lane_s16 (int16x4_t, int16x4_t, int16x4_t, const int)
6162 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6167 @item float32x4_t vmlaq_lane_f32 (float32x4_t, float32x4_t, float32x2_t, const int)
6168 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6173 @item uint32x4_t vmlaq_lane_u32 (uint32x4_t, uint32x4_t, uint32x2_t, const int)
6174 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6179 @item uint16x8_t vmlaq_lane_u16 (uint16x8_t, uint16x8_t, uint16x4_t, const int)
6180 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6185 @item int32x4_t vmlaq_lane_s32 (int32x4_t, int32x4_t, int32x2_t, const int)
6186 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6191 @item int16x8_t vmlaq_lane_s16 (int16x8_t, int16x8_t, int16x4_t, const int)
6192 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6197 @item uint64x2_t vmlal_lane_u32 (uint64x2_t, uint32x2_t, uint32x2_t, const int)
6198 @*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6203 @item uint32x4_t vmlal_lane_u16 (uint32x4_t, uint16x4_t, uint16x4_t, const int)
6204 @*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6209 @item int64x2_t vmlal_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6210 @*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6215 @item int32x4_t vmlal_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6216 @*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6221 @item int64x2_t vqdmlal_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6222 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6227 @item int32x4_t vqdmlal_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6228 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6234 @subsubsection Multiply-subtract, lane
6237 @item float32x2_t vmls_lane_f32 (float32x2_t, float32x2_t, float32x2_t, const int)
6238 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6243 @item uint32x2_t vmls_lane_u32 (uint32x2_t, uint32x2_t, uint32x2_t, const int)
6244 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6249 @item uint16x4_t vmls_lane_u16 (uint16x4_t, uint16x4_t, uint16x4_t, const int)
6250 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6255 @item int32x2_t vmls_lane_s32 (int32x2_t, int32x2_t, int32x2_t, const int)
6256 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6261 @item int16x4_t vmls_lane_s16 (int16x4_t, int16x4_t, int16x4_t, const int)
6262 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6267 @item float32x4_t vmlsq_lane_f32 (float32x4_t, float32x4_t, float32x2_t, const int)
6268 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6273 @item uint32x4_t vmlsq_lane_u32 (uint32x4_t, uint32x4_t, uint32x2_t, const int)
6274 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6279 @item uint16x8_t vmlsq_lane_u16 (uint16x8_t, uint16x8_t, uint16x4_t, const int)
6280 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6285 @item int32x4_t vmlsq_lane_s32 (int32x4_t, int32x4_t, int32x2_t, const int)
6286 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6291 @item int16x8_t vmlsq_lane_s16 (int16x8_t, int16x8_t, int16x4_t, const int)
6292 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6297 @item uint64x2_t vmlsl_lane_u32 (uint64x2_t, uint32x2_t, uint32x2_t, const int)
6298 @*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6303 @item uint32x4_t vmlsl_lane_u16 (uint32x4_t, uint16x4_t, uint16x4_t, const int)
6304 @*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6309 @item int64x2_t vmlsl_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6310 @*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6315 @item int32x4_t vmlsl_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6316 @*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6321 @item int64x2_t vqdmlsl_lane_s32 (int64x2_t, int32x2_t, int32x2_t, const int)
6322 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6327 @item int32x4_t vqdmlsl_lane_s16 (int32x4_t, int16x4_t, int16x4_t, const int)
6328 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6334 @subsubsection Vector multiply by scalar
6337 @item float32x2_t vmul_n_f32 (float32x2_t, float32_t)
6338 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6343 @item uint32x2_t vmul_n_u32 (uint32x2_t, uint32_t)
6344 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6349 @item uint16x4_t vmul_n_u16 (uint16x4_t, uint16_t)
6350 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6355 @item int32x2_t vmul_n_s32 (int32x2_t, int32_t)
6356 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6361 @item int16x4_t vmul_n_s16 (int16x4_t, int16_t)
6362 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6367 @item float32x4_t vmulq_n_f32 (float32x4_t, float32_t)
6368 @*@emph{Form of expected instruction(s):} @code{vmul.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6373 @item uint32x4_t vmulq_n_u32 (uint32x4_t, uint32_t)
6374 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6379 @item uint16x8_t vmulq_n_u16 (uint16x8_t, uint16_t)
6380 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6385 @item int32x4_t vmulq_n_s32 (int32x4_t, int32_t)
6386 @*@emph{Form of expected instruction(s):} @code{vmul.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6391 @item int16x8_t vmulq_n_s16 (int16x8_t, int16_t)
6392 @*@emph{Form of expected instruction(s):} @code{vmul.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6398 @subsubsection Vector long multiply by scalar
6401 @item uint64x2_t vmull_n_u32 (uint32x2_t, uint32_t)
6402 @*@emph{Form of expected instruction(s):} @code{vmull.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6407 @item uint32x4_t vmull_n_u16 (uint16x4_t, uint16_t)
6408 @*@emph{Form of expected instruction(s):} @code{vmull.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6413 @item int64x2_t vmull_n_s32 (int32x2_t, int32_t)
6414 @*@emph{Form of expected instruction(s):} @code{vmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6419 @item int32x4_t vmull_n_s16 (int16x4_t, int16_t)
6420 @*@emph{Form of expected instruction(s):} @code{vmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6426 @subsubsection Vector saturating doubling long multiply by scalar
6429 @item int64x2_t vqdmull_n_s32 (int32x2_t, int32_t)
6430 @*@emph{Form of expected instruction(s):} @code{vqdmull.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6435 @item int32x4_t vqdmull_n_s16 (int16x4_t, int16_t)
6436 @*@emph{Form of expected instruction(s):} @code{vqdmull.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6442 @subsubsection Vector saturating doubling multiply high by scalar
6445 @item int32x4_t vqdmulhq_n_s32 (int32x4_t, int32_t)
6446 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6451 @item int16x8_t vqdmulhq_n_s16 (int16x8_t, int16_t)
6452 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6457 @item int32x2_t vqdmulh_n_s32 (int32x2_t, int32_t)
6458 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6463 @item int16x4_t vqdmulh_n_s16 (int16x4_t, int16_t)
6464 @*@emph{Form of expected instruction(s):} @code{vqdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6469 @item int32x4_t vqrdmulhq_n_s32 (int32x4_t, int32_t)
6470 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6475 @item int16x8_t vqrdmulhq_n_s16 (int16x8_t, int16_t)
6476 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6481 @item int32x2_t vqrdmulh_n_s32 (int32x2_t, int32_t)
6482 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6487 @item int16x4_t vqrdmulh_n_s16 (int16x4_t, int16_t)
6488 @*@emph{Form of expected instruction(s):} @code{vqrdmulh.s16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6494 @subsubsection Vector multiply-accumulate by scalar
6497 @item float32x2_t vmla_n_f32 (float32x2_t, float32x2_t, float32_t)
6498 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6503 @item uint32x2_t vmla_n_u32 (uint32x2_t, uint32x2_t, uint32_t)
6504 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6509 @item uint16x4_t vmla_n_u16 (uint16x4_t, uint16x4_t, uint16_t)
6510 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6515 @item int32x2_t vmla_n_s32 (int32x2_t, int32x2_t, int32_t)
6516 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6521 @item int16x4_t vmla_n_s16 (int16x4_t, int16x4_t, int16_t)
6522 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6527 @item float32x4_t vmlaq_n_f32 (float32x4_t, float32x4_t, float32_t)
6528 @*@emph{Form of expected instruction(s):} @code{vmla.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6533 @item uint32x4_t vmlaq_n_u32 (uint32x4_t, uint32x4_t, uint32_t)
6534 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6539 @item uint16x8_t vmlaq_n_u16 (uint16x8_t, uint16x8_t, uint16_t)
6540 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6545 @item int32x4_t vmlaq_n_s32 (int32x4_t, int32x4_t, int32_t)
6546 @*@emph{Form of expected instruction(s):} @code{vmla.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6551 @item int16x8_t vmlaq_n_s16 (int16x8_t, int16x8_t, int16_t)
6552 @*@emph{Form of expected instruction(s):} @code{vmla.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6557 @item uint64x2_t vmlal_n_u32 (uint64x2_t, uint32x2_t, uint32_t)
6558 @*@emph{Form of expected instruction(s):} @code{vmlal.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6563 @item uint32x4_t vmlal_n_u16 (uint32x4_t, uint16x4_t, uint16_t)
6564 @*@emph{Form of expected instruction(s):} @code{vmlal.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6569 @item int64x2_t vmlal_n_s32 (int64x2_t, int32x2_t, int32_t)
6570 @*@emph{Form of expected instruction(s):} @code{vmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6575 @item int32x4_t vmlal_n_s16 (int32x4_t, int16x4_t, int16_t)
6576 @*@emph{Form of expected instruction(s):} @code{vmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6581 @item int64x2_t vqdmlal_n_s32 (int64x2_t, int32x2_t, int32_t)
6582 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6587 @item int32x4_t vqdmlal_n_s16 (int32x4_t, int16x4_t, int16_t)
6588 @*@emph{Form of expected instruction(s):} @code{vqdmlal.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6594 @subsubsection Vector multiply-subtract by scalar
6597 @item float32x2_t vmls_n_f32 (float32x2_t, float32x2_t, float32_t)
6598 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6603 @item uint32x2_t vmls_n_u32 (uint32x2_t, uint32x2_t, uint32_t)
6604 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6609 @item uint16x4_t vmls_n_u16 (uint16x4_t, uint16x4_t, uint16_t)
6610 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6615 @item int32x2_t vmls_n_s32 (int32x2_t, int32x2_t, int32_t)
6616 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6621 @item int16x4_t vmls_n_s16 (int16x4_t, int16x4_t, int16_t)
6622 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{d0}, @var{d0}, @var{d0}[@var{0}]}
6627 @item float32x4_t vmlsq_n_f32 (float32x4_t, float32x4_t, float32_t)
6628 @*@emph{Form of expected instruction(s):} @code{vmls.f32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6633 @item uint32x4_t vmlsq_n_u32 (uint32x4_t, uint32x4_t, uint32_t)
6634 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6639 @item uint16x8_t vmlsq_n_u16 (uint16x8_t, uint16x8_t, uint16_t)
6640 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6645 @item int32x4_t vmlsq_n_s32 (int32x4_t, int32x4_t, int32_t)
6646 @*@emph{Form of expected instruction(s):} @code{vmls.i32 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6651 @item int16x8_t vmlsq_n_s16 (int16x8_t, int16x8_t, int16_t)
6652 @*@emph{Form of expected instruction(s):} @code{vmls.i16 @var{q0}, @var{q0}, @var{d0}[@var{0}]}
6657 @item uint64x2_t vmlsl_n_u32 (uint64x2_t, uint32x2_t, uint32_t)
6658 @*@emph{Form of expected instruction(s):} @code{vmlsl.u32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6663 @item uint32x4_t vmlsl_n_u16 (uint32x4_t, uint16x4_t, uint16_t)
6664 @*@emph{Form of expected instruction(s):} @code{vmlsl.u16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6669 @item int64x2_t vmlsl_n_s32 (int64x2_t, int32x2_t, int32_t)
6670 @*@emph{Form of expected instruction(s):} @code{vmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6675 @item int32x4_t vmlsl_n_s16 (int32x4_t, int16x4_t, int16_t)
6676 @*@emph{Form of expected instruction(s):} @code{vmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6681 @item int64x2_t vqdmlsl_n_s32 (int64x2_t, int32x2_t, int32_t)
6682 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s32 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6687 @item int32x4_t vqdmlsl_n_s16 (int32x4_t, int16x4_t, int16_t)
6688 @*@emph{Form of expected instruction(s):} @code{vqdmlsl.s16 @var{q0}, @var{d0}, @var{d0}[@var{0}]}
6694 @subsubsection Vector extract
6697 @item uint32x2_t vext_u32 (uint32x2_t, uint32x2_t, const int)
6698 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6703 @item uint16x4_t vext_u16 (uint16x4_t, uint16x4_t, const int)
6704 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6709 @item uint8x8_t vext_u8 (uint8x8_t, uint8x8_t, const int)
6710 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6715 @item int32x2_t vext_s32 (int32x2_t, int32x2_t, const int)
6716 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6721 @item int16x4_t vext_s16 (int16x4_t, int16x4_t, const int)
6722 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6727 @item int8x8_t vext_s8 (int8x8_t, int8x8_t, const int)
6728 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6733 @item uint64x1_t vext_u64 (uint64x1_t, uint64x1_t, const int)
6734 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6739 @item int64x1_t vext_s64 (int64x1_t, int64x1_t, const int)
6740 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6745 @item float32x2_t vext_f32 (float32x2_t, float32x2_t, const int)
6746 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6751 @item poly16x4_t vext_p16 (poly16x4_t, poly16x4_t, const int)
6752 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6757 @item poly8x8_t vext_p8 (poly8x8_t, poly8x8_t, const int)
6758 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{d0}, @var{d0}, @var{d0}, #@var{0}}
6763 @item uint32x4_t vextq_u32 (uint32x4_t, uint32x4_t, const int)
6764 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6769 @item uint16x8_t vextq_u16 (uint16x8_t, uint16x8_t, const int)
6770 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6775 @item uint8x16_t vextq_u8 (uint8x16_t, uint8x16_t, const int)
6776 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6781 @item int32x4_t vextq_s32 (int32x4_t, int32x4_t, const int)
6782 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6787 @item int16x8_t vextq_s16 (int16x8_t, int16x8_t, const int)
6788 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6793 @item int8x16_t vextq_s8 (int8x16_t, int8x16_t, const int)
6794 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6799 @item uint64x2_t vextq_u64 (uint64x2_t, uint64x2_t, const int)
6800 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6805 @item int64x2_t vextq_s64 (int64x2_t, int64x2_t, const int)
6806 @*@emph{Form of expected instruction(s):} @code{vext.64 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6811 @item float32x4_t vextq_f32 (float32x4_t, float32x4_t, const int)
6812 @*@emph{Form of expected instruction(s):} @code{vext.32 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6817 @item poly16x8_t vextq_p16 (poly16x8_t, poly16x8_t, const int)
6818 @*@emph{Form of expected instruction(s):} @code{vext.16 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6823 @item poly8x16_t vextq_p8 (poly8x16_t, poly8x16_t, const int)
6824 @*@emph{Form of expected instruction(s):} @code{vext.8 @var{q0}, @var{q0}, @var{q0}, #@var{0}}
6830 @subsubsection Reverse elements
6833 @item uint32x2_t vrev64_u32 (uint32x2_t)
6834 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
6839 @item uint16x4_t vrev64_u16 (uint16x4_t)
6840 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
6845 @item uint8x8_t vrev64_u8 (uint8x8_t)
6846 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
6851 @item int32x2_t vrev64_s32 (int32x2_t)
6852 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
6857 @item int16x4_t vrev64_s16 (int16x4_t)
6858 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
6863 @item int8x8_t vrev64_s8 (int8x8_t)
6864 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
6869 @item float32x2_t vrev64_f32 (float32x2_t)
6870 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{d0}, @var{d0}}
6875 @item poly16x4_t vrev64_p16 (poly16x4_t)
6876 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{d0}, @var{d0}}
6881 @item poly8x8_t vrev64_p8 (poly8x8_t)
6882 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{d0}, @var{d0}}
6887 @item uint32x4_t vrev64q_u32 (uint32x4_t)
6888 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
6893 @item uint16x8_t vrev64q_u16 (uint16x8_t)
6894 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
6899 @item uint8x16_t vrev64q_u8 (uint8x16_t)
6900 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
6905 @item int32x4_t vrev64q_s32 (int32x4_t)
6906 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
6911 @item int16x8_t vrev64q_s16 (int16x8_t)
6912 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
6917 @item int8x16_t vrev64q_s8 (int8x16_t)
6918 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
6923 @item float32x4_t vrev64q_f32 (float32x4_t)
6924 @*@emph{Form of expected instruction(s):} @code{vrev64.32 @var{q0}, @var{q0}}
6929 @item poly16x8_t vrev64q_p16 (poly16x8_t)
6930 @*@emph{Form of expected instruction(s):} @code{vrev64.16 @var{q0}, @var{q0}}
6935 @item poly8x16_t vrev64q_p8 (poly8x16_t)
6936 @*@emph{Form of expected instruction(s):} @code{vrev64.8 @var{q0}, @var{q0}}
6941 @item uint16x4_t vrev32_u16 (uint16x4_t)
6942 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
6947 @item int16x4_t vrev32_s16 (int16x4_t)
6948 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
6953 @item uint8x8_t vrev32_u8 (uint8x8_t)
6954 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
6959 @item int8x8_t vrev32_s8 (int8x8_t)
6960 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
6965 @item poly16x4_t vrev32_p16 (poly16x4_t)
6966 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{d0}, @var{d0}}
6971 @item poly8x8_t vrev32_p8 (poly8x8_t)
6972 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{d0}, @var{d0}}
6977 @item uint16x8_t vrev32q_u16 (uint16x8_t)
6978 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
6983 @item int16x8_t vrev32q_s16 (int16x8_t)
6984 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
6989 @item uint8x16_t vrev32q_u8 (uint8x16_t)
6990 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
6995 @item int8x16_t vrev32q_s8 (int8x16_t)
6996 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
7001 @item poly16x8_t vrev32q_p16 (poly16x8_t)
7002 @*@emph{Form of expected instruction(s):} @code{vrev32.16 @var{q0}, @var{q0}}
7007 @item poly8x16_t vrev32q_p8 (poly8x16_t)
7008 @*@emph{Form of expected instruction(s):} @code{vrev32.8 @var{q0}, @var{q0}}
7013 @item uint8x8_t vrev16_u8 (uint8x8_t)
7014 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
7019 @item int8x8_t vrev16_s8 (int8x8_t)
7020 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
7025 @item poly8x8_t vrev16_p8 (poly8x8_t)
7026 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{d0}, @var{d0}}
7031 @item uint8x16_t vrev16q_u8 (uint8x16_t)
7032 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
7037 @item int8x16_t vrev16q_s8 (int8x16_t)
7038 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
7043 @item poly8x16_t vrev16q_p8 (poly8x16_t)
7044 @*@emph{Form of expected instruction(s):} @code{vrev16.8 @var{q0}, @var{q0}}
7050 @subsubsection Bit selection
7053 @item uint32x2_t vbsl_u32 (uint32x2_t, uint32x2_t, uint32x2_t)
7054 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7059 @item uint16x4_t vbsl_u16 (uint16x4_t, uint16x4_t, uint16x4_t)
7060 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7065 @item uint8x8_t vbsl_u8 (uint8x8_t, uint8x8_t, uint8x8_t)
7066 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7071 @item int32x2_t vbsl_s32 (uint32x2_t, int32x2_t, int32x2_t)
7072 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7077 @item int16x4_t vbsl_s16 (uint16x4_t, int16x4_t, int16x4_t)
7078 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7083 @item int8x8_t vbsl_s8 (uint8x8_t, int8x8_t, int8x8_t)
7084 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7089 @item uint64x1_t vbsl_u64 (uint64x1_t, uint64x1_t, uint64x1_t)
7090 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7095 @item int64x1_t vbsl_s64 (uint64x1_t, int64x1_t, int64x1_t)
7096 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7101 @item float32x2_t vbsl_f32 (uint32x2_t, float32x2_t, float32x2_t)
7102 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7107 @item poly16x4_t vbsl_p16 (uint16x4_t, poly16x4_t, poly16x4_t)
7108 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7113 @item poly8x8_t vbsl_p8 (uint8x8_t, poly8x8_t, poly8x8_t)
7114 @*@emph{Form of expected instruction(s):} @code{vbsl @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbit @var{d0}, @var{d0}, @var{d0}} @emph{or} @code{vbif @var{d0}, @var{d0}, @var{d0}}
7119 @item uint32x4_t vbslq_u32 (uint32x4_t, uint32x4_t, uint32x4_t)
7120 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7125 @item uint16x8_t vbslq_u16 (uint16x8_t, uint16x8_t, uint16x8_t)
7126 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7131 @item uint8x16_t vbslq_u8 (uint8x16_t, uint8x16_t, uint8x16_t)
7132 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7137 @item int32x4_t vbslq_s32 (uint32x4_t, int32x4_t, int32x4_t)
7138 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7143 @item int16x8_t vbslq_s16 (uint16x8_t, int16x8_t, int16x8_t)
7144 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7149 @item int8x16_t vbslq_s8 (uint8x16_t, int8x16_t, int8x16_t)
7150 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7155 @item uint64x2_t vbslq_u64 (uint64x2_t, uint64x2_t, uint64x2_t)
7156 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7161 @item int64x2_t vbslq_s64 (uint64x2_t, int64x2_t, int64x2_t)
7162 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7167 @item float32x4_t vbslq_f32 (uint32x4_t, float32x4_t, float32x4_t)
7168 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7173 @item poly16x8_t vbslq_p16 (uint16x8_t, poly16x8_t, poly16x8_t)
7174 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7179 @item poly8x16_t vbslq_p8 (uint8x16_t, poly8x16_t, poly8x16_t)
7180 @*@emph{Form of expected instruction(s):} @code{vbsl @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbit @var{q0}, @var{q0}, @var{q0}} @emph{or} @code{vbif @var{q0}, @var{q0}, @var{q0}}
7186 @subsubsection Transpose elements
7189 @item uint32x2x2_t vtrn_u32 (uint32x2_t, uint32x2_t)
7190 @*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}}
7195 @item uint16x4x2_t vtrn_u16 (uint16x4_t, uint16x4_t)
7196 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
7201 @item uint8x8x2_t vtrn_u8 (uint8x8_t, uint8x8_t)
7202 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
7207 @item int32x2x2_t vtrn_s32 (int32x2_t, int32x2_t)
7208 @*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}}
7213 @item int16x4x2_t vtrn_s16 (int16x4_t, int16x4_t)
7214 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
7219 @item int8x8x2_t vtrn_s8 (int8x8_t, int8x8_t)
7220 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
7225 @item float32x2x2_t vtrn_f32 (float32x2_t, float32x2_t)
7226 @*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{d0}, @var{d1}}
7231 @item poly16x4x2_t vtrn_p16 (poly16x4_t, poly16x4_t)
7232 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{d0}, @var{d1}}
7237 @item poly8x8x2_t vtrn_p8 (poly8x8_t, poly8x8_t)
7238 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{d0}, @var{d1}}
7243 @item uint32x4x2_t vtrnq_u32 (uint32x4_t, uint32x4_t)
7244 @*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
7249 @item uint16x8x2_t vtrnq_u16 (uint16x8_t, uint16x8_t)
7250 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
7255 @item uint8x16x2_t vtrnq_u8 (uint8x16_t, uint8x16_t)
7256 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
7261 @item int32x4x2_t vtrnq_s32 (int32x4_t, int32x4_t)
7262 @*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
7267 @item int16x8x2_t vtrnq_s16 (int16x8_t, int16x8_t)
7268 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
7273 @item int8x16x2_t vtrnq_s8 (int8x16_t, int8x16_t)
7274 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
7279 @item float32x4x2_t vtrnq_f32 (float32x4_t, float32x4_t)
7280 @*@emph{Form of expected instruction(s):} @code{vtrn.32 @var{q0}, @var{q1}}
7285 @item poly16x8x2_t vtrnq_p16 (poly16x8_t, poly16x8_t)
7286 @*@emph{Form of expected instruction(s):} @code{vtrn.16 @var{q0}, @var{q1}}
7291 @item poly8x16x2_t vtrnq_p8 (poly8x16_t, poly8x16_t)
7292 @*@emph{Form of expected instruction(s):} @code{vtrn.8 @var{q0}, @var{q1}}
7298 @subsubsection Zip elements
7301 @item uint32x2x2_t vzip_u32 (uint32x2_t, uint32x2_t)
7302 @*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}}
7307 @item uint16x4x2_t vzip_u16 (uint16x4_t, uint16x4_t)
7308 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
7313 @item uint8x8x2_t vzip_u8 (uint8x8_t, uint8x8_t)
7314 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
7319 @item int32x2x2_t vzip_s32 (int32x2_t, int32x2_t)
7320 @*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}}
7325 @item int16x4x2_t vzip_s16 (int16x4_t, int16x4_t)
7326 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
7331 @item int8x8x2_t vzip_s8 (int8x8_t, int8x8_t)
7332 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
7337 @item float32x2x2_t vzip_f32 (float32x2_t, float32x2_t)
7338 @*@emph{Form of expected instruction(s):} @code{vzip.32 @var{d0}, @var{d1}}
7343 @item poly16x4x2_t vzip_p16 (poly16x4_t, poly16x4_t)
7344 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{d0}, @var{d1}}
7349 @item poly8x8x2_t vzip_p8 (poly8x8_t, poly8x8_t)
7350 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{d0}, @var{d1}}
7355 @item uint32x4x2_t vzipq_u32 (uint32x4_t, uint32x4_t)
7356 @*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
7361 @item uint16x8x2_t vzipq_u16 (uint16x8_t, uint16x8_t)
7362 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
7367 @item uint8x16x2_t vzipq_u8 (uint8x16_t, uint8x16_t)
7368 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
7373 @item int32x4x2_t vzipq_s32 (int32x4_t, int32x4_t)
7374 @*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
7379 @item int16x8x2_t vzipq_s16 (int16x8_t, int16x8_t)
7380 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
7385 @item int8x16x2_t vzipq_s8 (int8x16_t, int8x16_t)
7386 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
7391 @item float32x4x2_t vzipq_f32 (float32x4_t, float32x4_t)
7392 @*@emph{Form of expected instruction(s):} @code{vzip.32 @var{q0}, @var{q1}}
7397 @item poly16x8x2_t vzipq_p16 (poly16x8_t, poly16x8_t)
7398 @*@emph{Form of expected instruction(s):} @code{vzip.16 @var{q0}, @var{q1}}
7403 @item poly8x16x2_t vzipq_p8 (poly8x16_t, poly8x16_t)
7404 @*@emph{Form of expected instruction(s):} @code{vzip.8 @var{q0}, @var{q1}}
7410 @subsubsection Unzip elements
7413 @item uint32x2x2_t vuzp_u32 (uint32x2_t, uint32x2_t)
7414 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7419 @item uint16x4x2_t vuzp_u16 (uint16x4_t, uint16x4_t)
7420 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
7425 @item uint8x8x2_t vuzp_u8 (uint8x8_t, uint8x8_t)
7426 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
7431 @item int32x2x2_t vuzp_s32 (int32x2_t, int32x2_t)
7432 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7437 @item int16x4x2_t vuzp_s16 (int16x4_t, int16x4_t)
7438 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
7443 @item int8x8x2_t vuzp_s8 (int8x8_t, int8x8_t)
7444 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
7449 @item float32x2x2_t vuzp_f32 (float32x2_t, float32x2_t)
7450 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{d0}, @var{d1}}
7455 @item poly16x4x2_t vuzp_p16 (poly16x4_t, poly16x4_t)
7456 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{d0}, @var{d1}}
7461 @item poly8x8x2_t vuzp_p8 (poly8x8_t, poly8x8_t)
7462 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{d0}, @var{d1}}
7467 @item uint32x4x2_t vuzpq_u32 (uint32x4_t, uint32x4_t)
7468 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
7473 @item uint16x8x2_t vuzpq_u16 (uint16x8_t, uint16x8_t)
7474 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
7479 @item uint8x16x2_t vuzpq_u8 (uint8x16_t, uint8x16_t)
7480 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
7485 @item int32x4x2_t vuzpq_s32 (int32x4_t, int32x4_t)
7486 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
7491 @item int16x8x2_t vuzpq_s16 (int16x8_t, int16x8_t)
7492 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
7497 @item int8x16x2_t vuzpq_s8 (int8x16_t, int8x16_t)
7498 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
7503 @item float32x4x2_t vuzpq_f32 (float32x4_t, float32x4_t)
7504 @*@emph{Form of expected instruction(s):} @code{vuzp.32 @var{q0}, @var{q1}}
7509 @item poly16x8x2_t vuzpq_p16 (poly16x8_t, poly16x8_t)
7510 @*@emph{Form of expected instruction(s):} @code{vuzp.16 @var{q0}, @var{q1}}
7515 @item poly8x16x2_t vuzpq_p8 (poly8x16_t, poly8x16_t)
7516 @*@emph{Form of expected instruction(s):} @code{vuzp.8 @var{q0}, @var{q1}}
7522 @subsubsection Element/structure loads, VLD1 variants
7525 @item uint32x2_t vld1_u32 (const uint32_t *)
7526 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
7531 @item uint16x4_t vld1_u16 (const uint16_t *)
7532 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
7537 @item uint8x8_t vld1_u8 (const uint8_t *)
7538 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
7543 @item int32x2_t vld1_s32 (const int32_t *)
7544 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
7549 @item int16x4_t vld1_s16 (const int16_t *)
7550 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
7555 @item int8x8_t vld1_s8 (const int8_t *)
7556 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
7561 @item uint64x1_t vld1_u64 (const uint64_t *)
7562 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7567 @item int64x1_t vld1_s64 (const int64_t *)
7568 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7573 @item float32x2_t vld1_f32 (const float32_t *)
7574 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}@}, [@var{r0}]}
7579 @item poly16x4_t vld1_p16 (const poly16_t *)
7580 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}@}, [@var{r0}]}
7585 @item poly8x8_t vld1_p8 (const poly8_t *)
7586 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}@}, [@var{r0}]}
7591 @item uint32x4_t vld1q_u32 (const uint32_t *)
7592 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7597 @item uint16x8_t vld1q_u16 (const uint16_t *)
7598 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7603 @item uint8x16_t vld1q_u8 (const uint8_t *)
7604 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7609 @item int32x4_t vld1q_s32 (const int32_t *)
7610 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7615 @item int16x8_t vld1q_s16 (const int16_t *)
7616 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7621 @item int8x16_t vld1q_s8 (const int8_t *)
7622 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7627 @item uint64x2_t vld1q_u64 (const uint64_t *)
7628 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7633 @item int64x2_t vld1q_s64 (const int64_t *)
7634 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7639 @item float32x4_t vld1q_f32 (const float32_t *)
7640 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7645 @item poly16x8_t vld1q_p16 (const poly16_t *)
7646 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7651 @item poly8x16_t vld1q_p8 (const poly8_t *)
7652 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7657 @item uint32x2_t vld1_lane_u32 (const uint32_t *, uint32x2_t, const int)
7658 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7663 @item uint16x4_t vld1_lane_u16 (const uint16_t *, uint16x4_t, const int)
7664 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7669 @item uint8x8_t vld1_lane_u8 (const uint8_t *, uint8x8_t, const int)
7670 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7675 @item int32x2_t vld1_lane_s32 (const int32_t *, int32x2_t, const int)
7676 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7681 @item int16x4_t vld1_lane_s16 (const int16_t *, int16x4_t, const int)
7682 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7687 @item int8x8_t vld1_lane_s8 (const int8_t *, int8x8_t, const int)
7688 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7693 @item float32x2_t vld1_lane_f32 (const float32_t *, float32x2_t, const int)
7694 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7699 @item poly16x4_t vld1_lane_p16 (const poly16_t *, poly16x4_t, const int)
7700 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7705 @item poly8x8_t vld1_lane_p8 (const poly8_t *, poly8x8_t, const int)
7706 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7711 @item uint64x1_t vld1_lane_u64 (const uint64_t *, uint64x1_t, const int)
7712 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7717 @item int64x1_t vld1_lane_s64 (const int64_t *, int64x1_t, const int)
7718 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7723 @item uint32x4_t vld1q_lane_u32 (const uint32_t *, uint32x4_t, const int)
7724 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7729 @item uint16x8_t vld1q_lane_u16 (const uint16_t *, uint16x8_t, const int)
7730 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7735 @item uint8x16_t vld1q_lane_u8 (const uint8_t *, uint8x16_t, const int)
7736 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7741 @item int32x4_t vld1q_lane_s32 (const int32_t *, int32x4_t, const int)
7742 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7747 @item int16x8_t vld1q_lane_s16 (const int16_t *, int16x8_t, const int)
7748 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7753 @item int8x16_t vld1q_lane_s8 (const int8_t *, int8x16_t, const int)
7754 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7759 @item float32x4_t vld1q_lane_f32 (const float32_t *, float32x4_t, const int)
7760 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7765 @item poly16x8_t vld1q_lane_p16 (const poly16_t *, poly16x8_t, const int)
7766 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7771 @item poly8x16_t vld1q_lane_p8 (const poly8_t *, poly8x16_t, const int)
7772 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
7777 @item uint64x2_t vld1q_lane_u64 (const uint64_t *, uint64x2_t, const int)
7778 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7783 @item int64x2_t vld1q_lane_s64 (const int64_t *, int64x2_t, const int)
7784 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7789 @item uint32x2_t vld1_dup_u32 (const uint32_t *)
7790 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
7795 @item uint16x4_t vld1_dup_u16 (const uint16_t *)
7796 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
7801 @item uint8x8_t vld1_dup_u8 (const uint8_t *)
7802 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
7807 @item int32x2_t vld1_dup_s32 (const int32_t *)
7808 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
7813 @item int16x4_t vld1_dup_s16 (const int16_t *)
7814 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
7819 @item int8x8_t vld1_dup_s8 (const int8_t *)
7820 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
7825 @item float32x2_t vld1_dup_f32 (const float32_t *)
7826 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[]@}, [@var{r0}]}
7831 @item poly16x4_t vld1_dup_p16 (const poly16_t *)
7832 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[]@}, [@var{r0}]}
7837 @item poly8x8_t vld1_dup_p8 (const poly8_t *)
7838 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[]@}, [@var{r0}]}
7843 @item uint64x1_t vld1_dup_u64 (const uint64_t *)
7844 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7849 @item int64x1_t vld1_dup_s64 (const int64_t *)
7850 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}@}, [@var{r0}]}
7855 @item uint32x4_t vld1q_dup_u32 (const uint32_t *)
7856 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7861 @item uint16x8_t vld1q_dup_u16 (const uint16_t *)
7862 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7867 @item uint8x16_t vld1q_dup_u8 (const uint8_t *)
7868 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7873 @item int32x4_t vld1q_dup_s32 (const int32_t *)
7874 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7879 @item int16x8_t vld1q_dup_s16 (const int16_t *)
7880 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7885 @item int8x16_t vld1q_dup_s8 (const int8_t *)
7886 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7891 @item float32x4_t vld1q_dup_f32 (const float32_t *)
7892 @*@emph{Form of expected instruction(s):} @code{vld1.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7897 @item poly16x8_t vld1q_dup_p16 (const poly16_t *)
7898 @*@emph{Form of expected instruction(s):} @code{vld1.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7903 @item poly8x16_t vld1q_dup_p8 (const poly8_t *)
7904 @*@emph{Form of expected instruction(s):} @code{vld1.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
7909 @item uint64x2_t vld1q_dup_u64 (const uint64_t *)
7910 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7915 @item int64x2_t vld1q_dup_s64 (const int64_t *)
7916 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7922 @subsubsection Element/structure stores, VST1 variants
7925 @item void vst1_u32 (uint32_t *, uint32x2_t)
7926 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
7931 @item void vst1_u16 (uint16_t *, uint16x4_t)
7932 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
7937 @item void vst1_u8 (uint8_t *, uint8x8_t)
7938 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
7943 @item void vst1_s32 (int32_t *, int32x2_t)
7944 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
7949 @item void vst1_s16 (int16_t *, int16x4_t)
7950 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
7955 @item void vst1_s8 (int8_t *, int8x8_t)
7956 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
7961 @item void vst1_u64 (uint64_t *, uint64x1_t)
7962 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
7967 @item void vst1_s64 (int64_t *, int64x1_t)
7968 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
7973 @item void vst1_f32 (float32_t *, float32x2_t)
7974 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}@}, [@var{r0}]}
7979 @item void vst1_p16 (poly16_t *, poly16x4_t)
7980 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}@}, [@var{r0}]}
7985 @item void vst1_p8 (poly8_t *, poly8x8_t)
7986 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}@}, [@var{r0}]}
7991 @item void vst1q_u32 (uint32_t *, uint32x4_t)
7992 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
7997 @item void vst1q_u16 (uint16_t *, uint16x8_t)
7998 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8003 @item void vst1q_u8 (uint8_t *, uint8x16_t)
8004 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8009 @item void vst1q_s32 (int32_t *, int32x4_t)
8010 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8015 @item void vst1q_s16 (int16_t *, int16x8_t)
8016 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8021 @item void vst1q_s8 (int8_t *, int8x16_t)
8022 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8027 @item void vst1q_u64 (uint64_t *, uint64x2_t)
8028 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8033 @item void vst1q_s64 (int64_t *, int64x2_t)
8034 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8039 @item void vst1q_f32 (float32_t *, float32x4_t)
8040 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8045 @item void vst1q_p16 (poly16_t *, poly16x8_t)
8046 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8051 @item void vst1q_p8 (poly8_t *, poly8x16_t)
8052 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8057 @item void vst1_lane_u32 (uint32_t *, uint32x2_t, const int)
8058 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8063 @item void vst1_lane_u16 (uint16_t *, uint16x4_t, const int)
8064 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8069 @item void vst1_lane_u8 (uint8_t *, uint8x8_t, const int)
8070 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8075 @item void vst1_lane_s32 (int32_t *, int32x2_t, const int)
8076 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8081 @item void vst1_lane_s16 (int16_t *, int16x4_t, const int)
8082 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8087 @item void vst1_lane_s8 (int8_t *, int8x8_t, const int)
8088 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8093 @item void vst1_lane_f32 (float32_t *, float32x2_t, const int)
8094 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8099 @item void vst1_lane_p16 (poly16_t *, poly16x4_t, const int)
8100 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8105 @item void vst1_lane_p8 (poly8_t *, poly8x8_t, const int)
8106 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8111 @item void vst1_lane_s64 (int64_t *, int64x1_t, const int)
8112 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8117 @item void vst1_lane_u64 (uint64_t *, uint64x1_t, const int)
8118 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8123 @item void vst1q_lane_u32 (uint32_t *, uint32x4_t, const int)
8124 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8129 @item void vst1q_lane_u16 (uint16_t *, uint16x8_t, const int)
8130 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8135 @item void vst1q_lane_u8 (uint8_t *, uint8x16_t, const int)
8136 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8141 @item void vst1q_lane_s32 (int32_t *, int32x4_t, const int)
8142 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8147 @item void vst1q_lane_s16 (int16_t *, int16x8_t, const int)
8148 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8153 @item void vst1q_lane_s8 (int8_t *, int8x16_t, const int)
8154 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8159 @item void vst1q_lane_f32 (float32_t *, float32x4_t, const int)
8160 @*@emph{Form of expected instruction(s):} @code{vst1.32 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8165 @item void vst1q_lane_p16 (poly16_t *, poly16x8_t, const int)
8166 @*@emph{Form of expected instruction(s):} @code{vst1.16 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8171 @item void vst1q_lane_p8 (poly8_t *, poly8x16_t, const int)
8172 @*@emph{Form of expected instruction(s):} @code{vst1.8 @{@var{d0}[@var{0}]@}, [@var{r0}]}
8177 @item void vst1q_lane_s64 (int64_t *, int64x2_t, const int)
8178 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8183 @item void vst1q_lane_u64 (uint64_t *, uint64x2_t, const int)
8184 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}@}, [@var{r0}]}
8190 @subsubsection Element/structure loads, VLD2 variants
8193 @item uint32x2x2_t vld2_u32 (const uint32_t *)
8194 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8199 @item uint16x4x2_t vld2_u16 (const uint16_t *)
8200 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8205 @item uint8x8x2_t vld2_u8 (const uint8_t *)
8206 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8211 @item int32x2x2_t vld2_s32 (const int32_t *)
8212 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8217 @item int16x4x2_t vld2_s16 (const int16_t *)
8218 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8223 @item int8x8x2_t vld2_s8 (const int8_t *)
8224 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8229 @item float32x2x2_t vld2_f32 (const float32_t *)
8230 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8235 @item poly16x4x2_t vld2_p16 (const poly16_t *)
8236 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8241 @item poly8x8x2_t vld2_p8 (const poly8_t *)
8242 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8247 @item uint64x1x2_t vld2_u64 (const uint64_t *)
8248 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8253 @item int64x1x2_t vld2_s64 (const int64_t *)
8254 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8259 @item uint32x4x2_t vld2q_u32 (const uint32_t *)
8260 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8265 @item uint16x8x2_t vld2q_u16 (const uint16_t *)
8266 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8271 @item uint8x16x2_t vld2q_u8 (const uint8_t *)
8272 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8277 @item int32x4x2_t vld2q_s32 (const int32_t *)
8278 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8283 @item int16x8x2_t vld2q_s16 (const int16_t *)
8284 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8289 @item int8x16x2_t vld2q_s8 (const int8_t *)
8290 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8295 @item float32x4x2_t vld2q_f32 (const float32_t *)
8296 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8301 @item poly16x8x2_t vld2q_p16 (const poly16_t *)
8302 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8307 @item poly8x16x2_t vld2q_p8 (const poly8_t *)
8308 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8313 @item uint32x2x2_t vld2_lane_u32 (const uint32_t *, uint32x2x2_t, const int)
8314 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8319 @item uint16x4x2_t vld2_lane_u16 (const uint16_t *, uint16x4x2_t, const int)
8320 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8325 @item uint8x8x2_t vld2_lane_u8 (const uint8_t *, uint8x8x2_t, const int)
8326 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8331 @item int32x2x2_t vld2_lane_s32 (const int32_t *, int32x2x2_t, const int)
8332 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8337 @item int16x4x2_t vld2_lane_s16 (const int16_t *, int16x4x2_t, const int)
8338 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8343 @item int8x8x2_t vld2_lane_s8 (const int8_t *, int8x8x2_t, const int)
8344 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8349 @item float32x2x2_t vld2_lane_f32 (const float32_t *, float32x2x2_t, const int)
8350 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8355 @item poly16x4x2_t vld2_lane_p16 (const poly16_t *, poly16x4x2_t, const int)
8356 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8361 @item poly8x8x2_t vld2_lane_p8 (const poly8_t *, poly8x8x2_t, const int)
8362 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8367 @item int32x4x2_t vld2q_lane_s32 (const int32_t *, int32x4x2_t, const int)
8368 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8373 @item int16x8x2_t vld2q_lane_s16 (const int16_t *, int16x8x2_t, const int)
8374 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8379 @item uint32x4x2_t vld2q_lane_u32 (const uint32_t *, uint32x4x2_t, const int)
8380 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8385 @item uint16x8x2_t vld2q_lane_u16 (const uint16_t *, uint16x8x2_t, const int)
8386 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8391 @item float32x4x2_t vld2q_lane_f32 (const float32_t *, float32x4x2_t, const int)
8392 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8397 @item poly16x8x2_t vld2q_lane_p16 (const poly16_t *, poly16x8x2_t, const int)
8398 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8403 @item uint32x2x2_t vld2_dup_u32 (const uint32_t *)
8404 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8409 @item uint16x4x2_t vld2_dup_u16 (const uint16_t *)
8410 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8415 @item uint8x8x2_t vld2_dup_u8 (const uint8_t *)
8416 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8421 @item int32x2x2_t vld2_dup_s32 (const int32_t *)
8422 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8427 @item int16x4x2_t vld2_dup_s16 (const int16_t *)
8428 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8433 @item int8x8x2_t vld2_dup_s8 (const int8_t *)
8434 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8439 @item float32x2x2_t vld2_dup_f32 (const float32_t *)
8440 @*@emph{Form of expected instruction(s):} @code{vld2.32 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8445 @item poly16x4x2_t vld2_dup_p16 (const poly16_t *)
8446 @*@emph{Form of expected instruction(s):} @code{vld2.16 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8451 @item poly8x8x2_t vld2_dup_p8 (const poly8_t *)
8452 @*@emph{Form of expected instruction(s):} @code{vld2.8 @{@var{d0}[], @var{d1}[]@}, [@var{r0}]}
8457 @item uint64x1x2_t vld2_dup_u64 (const uint64_t *)
8458 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8463 @item int64x1x2_t vld2_dup_s64 (const int64_t *)
8464 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8470 @subsubsection Element/structure stores, VST2 variants
8473 @item void vst2_u32 (uint32_t *, uint32x2x2_t)
8474 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8479 @item void vst2_u16 (uint16_t *, uint16x4x2_t)
8480 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8485 @item void vst2_u8 (uint8_t *, uint8x8x2_t)
8486 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8491 @item void vst2_s32 (int32_t *, int32x2x2_t)
8492 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8497 @item void vst2_s16 (int16_t *, int16x4x2_t)
8498 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8503 @item void vst2_s8 (int8_t *, int8x8x2_t)
8504 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8509 @item void vst2_f32 (float32_t *, float32x2x2_t)
8510 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8515 @item void vst2_p16 (poly16_t *, poly16x4x2_t)
8516 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8521 @item void vst2_p8 (poly8_t *, poly8x8x2_t)
8522 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8527 @item void vst2_u64 (uint64_t *, uint64x1x2_t)
8528 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8533 @item void vst2_s64 (int64_t *, int64x1x2_t)
8534 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8539 @item void vst2q_u32 (uint32_t *, uint32x4x2_t)
8540 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8545 @item void vst2q_u16 (uint16_t *, uint16x8x2_t)
8546 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8551 @item void vst2q_u8 (uint8_t *, uint8x16x2_t)
8552 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8557 @item void vst2q_s32 (int32_t *, int32x4x2_t)
8558 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8563 @item void vst2q_s16 (int16_t *, int16x8x2_t)
8564 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8569 @item void vst2q_s8 (int8_t *, int8x16x2_t)
8570 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8575 @item void vst2q_f32 (float32_t *, float32x4x2_t)
8576 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8581 @item void vst2q_p16 (poly16_t *, poly16x8x2_t)
8582 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8587 @item void vst2q_p8 (poly8_t *, poly8x16x2_t)
8588 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}, @var{d1}@}, [@var{r0}]}
8593 @item void vst2_lane_u32 (uint32_t *, uint32x2x2_t, const int)
8594 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8599 @item void vst2_lane_u16 (uint16_t *, uint16x4x2_t, const int)
8600 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8605 @item void vst2_lane_u8 (uint8_t *, uint8x8x2_t, const int)
8606 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8611 @item void vst2_lane_s32 (int32_t *, int32x2x2_t, const int)
8612 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8617 @item void vst2_lane_s16 (int16_t *, int16x4x2_t, const int)
8618 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8623 @item void vst2_lane_s8 (int8_t *, int8x8x2_t, const int)
8624 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8629 @item void vst2_lane_f32 (float32_t *, float32x2x2_t, const int)
8630 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8635 @item void vst2_lane_p16 (poly16_t *, poly16x4x2_t, const int)
8636 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8641 @item void vst2_lane_p8 (poly8_t *, poly8x8x2_t, const int)
8642 @*@emph{Form of expected instruction(s):} @code{vst2.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8647 @item void vst2q_lane_s32 (int32_t *, int32x4x2_t, const int)
8648 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8653 @item void vst2q_lane_s16 (int16_t *, int16x8x2_t, const int)
8654 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8659 @item void vst2q_lane_u32 (uint32_t *, uint32x4x2_t, const int)
8660 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8665 @item void vst2q_lane_u16 (uint16_t *, uint16x8x2_t, const int)
8666 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8671 @item void vst2q_lane_f32 (float32_t *, float32x4x2_t, const int)
8672 @*@emph{Form of expected instruction(s):} @code{vst2.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8677 @item void vst2q_lane_p16 (poly16_t *, poly16x8x2_t, const int)
8678 @*@emph{Form of expected instruction(s):} @code{vst2.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}]@}, [@var{r0}]}
8684 @subsubsection Element/structure loads, VLD3 variants
8687 @item uint32x2x3_t vld3_u32 (const uint32_t *)
8688 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8693 @item uint16x4x3_t vld3_u16 (const uint16_t *)
8694 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8699 @item uint8x8x3_t vld3_u8 (const uint8_t *)
8700 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8705 @item int32x2x3_t vld3_s32 (const int32_t *)
8706 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8711 @item int16x4x3_t vld3_s16 (const int16_t *)
8712 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8717 @item int8x8x3_t vld3_s8 (const int8_t *)
8718 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8723 @item float32x2x3_t vld3_f32 (const float32_t *)
8724 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8729 @item poly16x4x3_t vld3_p16 (const poly16_t *)
8730 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8735 @item poly8x8x3_t vld3_p8 (const poly8_t *)
8736 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8741 @item uint64x1x3_t vld3_u64 (const uint64_t *)
8742 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8747 @item int64x1x3_t vld3_s64 (const int64_t *)
8748 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8753 @item uint32x4x3_t vld3q_u32 (const uint32_t *)
8754 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8759 @item uint16x8x3_t vld3q_u16 (const uint16_t *)
8760 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8765 @item uint8x16x3_t vld3q_u8 (const uint8_t *)
8766 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8771 @item int32x4x3_t vld3q_s32 (const int32_t *)
8772 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8777 @item int16x8x3_t vld3q_s16 (const int16_t *)
8778 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8783 @item int8x16x3_t vld3q_s8 (const int8_t *)
8784 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8789 @item float32x4x3_t vld3q_f32 (const float32_t *)
8790 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8795 @item poly16x8x3_t vld3q_p16 (const poly16_t *)
8796 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8801 @item poly8x16x3_t vld3q_p8 (const poly8_t *)
8802 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8807 @item uint32x2x3_t vld3_lane_u32 (const uint32_t *, uint32x2x3_t, const int)
8808 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8813 @item uint16x4x3_t vld3_lane_u16 (const uint16_t *, uint16x4x3_t, const int)
8814 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8819 @item uint8x8x3_t vld3_lane_u8 (const uint8_t *, uint8x8x3_t, const int)
8820 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8825 @item int32x2x3_t vld3_lane_s32 (const int32_t *, int32x2x3_t, const int)
8826 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8831 @item int16x4x3_t vld3_lane_s16 (const int16_t *, int16x4x3_t, const int)
8832 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8837 @item int8x8x3_t vld3_lane_s8 (const int8_t *, int8x8x3_t, const int)
8838 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8843 @item float32x2x3_t vld3_lane_f32 (const float32_t *, float32x2x3_t, const int)
8844 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8849 @item poly16x4x3_t vld3_lane_p16 (const poly16_t *, poly16x4x3_t, const int)
8850 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8855 @item poly8x8x3_t vld3_lane_p8 (const poly8_t *, poly8x8x3_t, const int)
8856 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8861 @item int32x4x3_t vld3q_lane_s32 (const int32_t *, int32x4x3_t, const int)
8862 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8867 @item int16x8x3_t vld3q_lane_s16 (const int16_t *, int16x8x3_t, const int)
8868 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8873 @item uint32x4x3_t vld3q_lane_u32 (const uint32_t *, uint32x4x3_t, const int)
8874 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8879 @item uint16x8x3_t vld3q_lane_u16 (const uint16_t *, uint16x8x3_t, const int)
8880 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8885 @item float32x4x3_t vld3q_lane_f32 (const float32_t *, float32x4x3_t, const int)
8886 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8891 @item poly16x8x3_t vld3q_lane_p16 (const poly16_t *, poly16x8x3_t, const int)
8892 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
8897 @item uint32x2x3_t vld3_dup_u32 (const uint32_t *)
8898 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8903 @item uint16x4x3_t vld3_dup_u16 (const uint16_t *)
8904 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8909 @item uint8x8x3_t vld3_dup_u8 (const uint8_t *)
8910 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8915 @item int32x2x3_t vld3_dup_s32 (const int32_t *)
8916 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8921 @item int16x4x3_t vld3_dup_s16 (const int16_t *)
8922 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8927 @item int8x8x3_t vld3_dup_s8 (const int8_t *)
8928 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8933 @item float32x2x3_t vld3_dup_f32 (const float32_t *)
8934 @*@emph{Form of expected instruction(s):} @code{vld3.32 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8939 @item poly16x4x3_t vld3_dup_p16 (const poly16_t *)
8940 @*@emph{Form of expected instruction(s):} @code{vld3.16 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8945 @item poly8x8x3_t vld3_dup_p8 (const poly8_t *)
8946 @*@emph{Form of expected instruction(s):} @code{vld3.8 @{@var{d0}[], @var{d1}[], @var{d2}[]@}, [@var{r0}]}
8951 @item uint64x1x3_t vld3_dup_u64 (const uint64_t *)
8952 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8957 @item int64x1x3_t vld3_dup_s64 (const int64_t *)
8958 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
8964 @subsubsection Element/structure stores, VST3 variants
8967 @item void vst3_u32 (uint32_t *, uint32x2x3_t)
8968 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
8973 @item void vst3_u16 (uint16_t *, uint16x4x3_t)
8974 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
8979 @item void vst3_u8 (uint8_t *, uint8x8x3_t)
8980 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
8985 @item void vst3_s32 (int32_t *, int32x2x3_t)
8986 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
8991 @item void vst3_s16 (int16_t *, int16x4x3_t)
8992 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
8997 @item void vst3_s8 (int8_t *, int8x8x3_t)
8998 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9003 @item void vst3_f32 (float32_t *, float32x2x3_t)
9004 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9009 @item void vst3_p16 (poly16_t *, poly16x4x3_t)
9010 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9015 @item void vst3_p8 (poly8_t *, poly8x8x3_t)
9016 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9021 @item void vst3_u64 (uint64_t *, uint64x1x3_t)
9022 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9027 @item void vst3_s64 (int64_t *, int64x1x3_t)
9028 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9033 @item void vst3q_u32 (uint32_t *, uint32x4x3_t)
9034 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9039 @item void vst3q_u16 (uint16_t *, uint16x8x3_t)
9040 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9045 @item void vst3q_u8 (uint8_t *, uint8x16x3_t)
9046 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9051 @item void vst3q_s32 (int32_t *, int32x4x3_t)
9052 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9057 @item void vst3q_s16 (int16_t *, int16x8x3_t)
9058 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9063 @item void vst3q_s8 (int8_t *, int8x16x3_t)
9064 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9069 @item void vst3q_f32 (float32_t *, float32x4x3_t)
9070 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9075 @item void vst3q_p16 (poly16_t *, poly16x8x3_t)
9076 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9081 @item void vst3q_p8 (poly8_t *, poly8x16x3_t)
9082 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}, @var{d1}, @var{d2}@}, [@var{r0}]}
9087 @item void vst3_lane_u32 (uint32_t *, uint32x2x3_t, const int)
9088 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9093 @item void vst3_lane_u16 (uint16_t *, uint16x4x3_t, const int)
9094 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9099 @item void vst3_lane_u8 (uint8_t *, uint8x8x3_t, const int)
9100 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9105 @item void vst3_lane_s32 (int32_t *, int32x2x3_t, const int)
9106 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9111 @item void vst3_lane_s16 (int16_t *, int16x4x3_t, const int)
9112 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9117 @item void vst3_lane_s8 (int8_t *, int8x8x3_t, const int)
9118 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9123 @item void vst3_lane_f32 (float32_t *, float32x2x3_t, const int)
9124 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9129 @item void vst3_lane_p16 (poly16_t *, poly16x4x3_t, const int)
9130 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9135 @item void vst3_lane_p8 (poly8_t *, poly8x8x3_t, const int)
9136 @*@emph{Form of expected instruction(s):} @code{vst3.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9141 @item void vst3q_lane_s32 (int32_t *, int32x4x3_t, const int)
9142 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9147 @item void vst3q_lane_s16 (int16_t *, int16x8x3_t, const int)
9148 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9153 @item void vst3q_lane_u32 (uint32_t *, uint32x4x3_t, const int)
9154 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9159 @item void vst3q_lane_u16 (uint16_t *, uint16x8x3_t, const int)
9160 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9165 @item void vst3q_lane_f32 (float32_t *, float32x4x3_t, const int)
9166 @*@emph{Form of expected instruction(s):} @code{vst3.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9171 @item void vst3q_lane_p16 (poly16_t *, poly16x8x3_t, const int)
9172 @*@emph{Form of expected instruction(s):} @code{vst3.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}]@}, [@var{r0}]}
9178 @subsubsection Element/structure loads, VLD4 variants
9181 @item uint32x2x4_t vld4_u32 (const uint32_t *)
9182 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9187 @item uint16x4x4_t vld4_u16 (const uint16_t *)
9188 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9193 @item uint8x8x4_t vld4_u8 (const uint8_t *)
9194 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9199 @item int32x2x4_t vld4_s32 (const int32_t *)
9200 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9205 @item int16x4x4_t vld4_s16 (const int16_t *)
9206 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9211 @item int8x8x4_t vld4_s8 (const int8_t *)
9212 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9217 @item float32x2x4_t vld4_f32 (const float32_t *)
9218 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9223 @item poly16x4x4_t vld4_p16 (const poly16_t *)
9224 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9229 @item poly8x8x4_t vld4_p8 (const poly8_t *)
9230 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9235 @item uint64x1x4_t vld4_u64 (const uint64_t *)
9236 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9241 @item int64x1x4_t vld4_s64 (const int64_t *)
9242 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9247 @item uint32x4x4_t vld4q_u32 (const uint32_t *)
9248 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9253 @item uint16x8x4_t vld4q_u16 (const uint16_t *)
9254 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9259 @item uint8x16x4_t vld4q_u8 (const uint8_t *)
9260 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9265 @item int32x4x4_t vld4q_s32 (const int32_t *)
9266 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9271 @item int16x8x4_t vld4q_s16 (const int16_t *)
9272 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9277 @item int8x16x4_t vld4q_s8 (const int8_t *)
9278 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9283 @item float32x4x4_t vld4q_f32 (const float32_t *)
9284 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9289 @item poly16x8x4_t vld4q_p16 (const poly16_t *)
9290 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9295 @item poly8x16x4_t vld4q_p8 (const poly8_t *)
9296 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9301 @item uint32x2x4_t vld4_lane_u32 (const uint32_t *, uint32x2x4_t, const int)
9302 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9307 @item uint16x4x4_t vld4_lane_u16 (const uint16_t *, uint16x4x4_t, const int)
9308 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9313 @item uint8x8x4_t vld4_lane_u8 (const uint8_t *, uint8x8x4_t, const int)
9314 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9319 @item int32x2x4_t vld4_lane_s32 (const int32_t *, int32x2x4_t, const int)
9320 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9325 @item int16x4x4_t vld4_lane_s16 (const int16_t *, int16x4x4_t, const int)
9326 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9331 @item int8x8x4_t vld4_lane_s8 (const int8_t *, int8x8x4_t, const int)
9332 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9337 @item float32x2x4_t vld4_lane_f32 (const float32_t *, float32x2x4_t, const int)
9338 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9343 @item poly16x4x4_t vld4_lane_p16 (const poly16_t *, poly16x4x4_t, const int)
9344 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9349 @item poly8x8x4_t vld4_lane_p8 (const poly8_t *, poly8x8x4_t, const int)
9350 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9355 @item int32x4x4_t vld4q_lane_s32 (const int32_t *, int32x4x4_t, const int)
9356 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9361 @item int16x8x4_t vld4q_lane_s16 (const int16_t *, int16x8x4_t, const int)
9362 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9367 @item uint32x4x4_t vld4q_lane_u32 (const uint32_t *, uint32x4x4_t, const int)
9368 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9373 @item uint16x8x4_t vld4q_lane_u16 (const uint16_t *, uint16x8x4_t, const int)
9374 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9379 @item float32x4x4_t vld4q_lane_f32 (const float32_t *, float32x4x4_t, const int)
9380 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9385 @item poly16x8x4_t vld4q_lane_p16 (const poly16_t *, poly16x8x4_t, const int)
9386 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9391 @item uint32x2x4_t vld4_dup_u32 (const uint32_t *)
9392 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9397 @item uint16x4x4_t vld4_dup_u16 (const uint16_t *)
9398 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9403 @item uint8x8x4_t vld4_dup_u8 (const uint8_t *)
9404 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9409 @item int32x2x4_t vld4_dup_s32 (const int32_t *)
9410 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9415 @item int16x4x4_t vld4_dup_s16 (const int16_t *)
9416 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9421 @item int8x8x4_t vld4_dup_s8 (const int8_t *)
9422 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9427 @item float32x2x4_t vld4_dup_f32 (const float32_t *)
9428 @*@emph{Form of expected instruction(s):} @code{vld4.32 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9433 @item poly16x4x4_t vld4_dup_p16 (const poly16_t *)
9434 @*@emph{Form of expected instruction(s):} @code{vld4.16 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9439 @item poly8x8x4_t vld4_dup_p8 (const poly8_t *)
9440 @*@emph{Form of expected instruction(s):} @code{vld4.8 @{@var{d0}[], @var{d1}[], @var{d2}[], @var{d3}[]@}, [@var{r0}]}
9445 @item uint64x1x4_t vld4_dup_u64 (const uint64_t *)
9446 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9451 @item int64x1x4_t vld4_dup_s64 (const int64_t *)
9452 @*@emph{Form of expected instruction(s):} @code{vld1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9458 @subsubsection Element/structure stores, VST4 variants
9461 @item void vst4_u32 (uint32_t *, uint32x2x4_t)
9462 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9467 @item void vst4_u16 (uint16_t *, uint16x4x4_t)
9468 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9473 @item void vst4_u8 (uint8_t *, uint8x8x4_t)
9474 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9479 @item void vst4_s32 (int32_t *, int32x2x4_t)
9480 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9485 @item void vst4_s16 (int16_t *, int16x4x4_t)
9486 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9491 @item void vst4_s8 (int8_t *, int8x8x4_t)
9492 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9497 @item void vst4_f32 (float32_t *, float32x2x4_t)
9498 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9503 @item void vst4_p16 (poly16_t *, poly16x4x4_t)
9504 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9509 @item void vst4_p8 (poly8_t *, poly8x8x4_t)
9510 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9515 @item void vst4_u64 (uint64_t *, uint64x1x4_t)
9516 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9521 @item void vst4_s64 (int64_t *, int64x1x4_t)
9522 @*@emph{Form of expected instruction(s):} @code{vst1.64 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9527 @item void vst4q_u32 (uint32_t *, uint32x4x4_t)
9528 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9533 @item void vst4q_u16 (uint16_t *, uint16x8x4_t)
9534 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9539 @item void vst4q_u8 (uint8_t *, uint8x16x4_t)
9540 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9545 @item void vst4q_s32 (int32_t *, int32x4x4_t)
9546 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9551 @item void vst4q_s16 (int16_t *, int16x8x4_t)
9552 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9557 @item void vst4q_s8 (int8_t *, int8x16x4_t)
9558 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9563 @item void vst4q_f32 (float32_t *, float32x4x4_t)
9564 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9569 @item void vst4q_p16 (poly16_t *, poly16x8x4_t)
9570 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9575 @item void vst4q_p8 (poly8_t *, poly8x16x4_t)
9576 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}, @var{d1}, @var{d2}, @var{d3}@}, [@var{r0}]}
9581 @item void vst4_lane_u32 (uint32_t *, uint32x2x4_t, const int)
9582 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9587 @item void vst4_lane_u16 (uint16_t *, uint16x4x4_t, const int)
9588 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9593 @item void vst4_lane_u8 (uint8_t *, uint8x8x4_t, const int)
9594 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9599 @item void vst4_lane_s32 (int32_t *, int32x2x4_t, const int)
9600 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9605 @item void vst4_lane_s16 (int16_t *, int16x4x4_t, const int)
9606 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9611 @item void vst4_lane_s8 (int8_t *, int8x8x4_t, const int)
9612 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9617 @item void vst4_lane_f32 (float32_t *, float32x2x4_t, const int)
9618 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9623 @item void vst4_lane_p16 (poly16_t *, poly16x4x4_t, const int)
9624 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9629 @item void vst4_lane_p8 (poly8_t *, poly8x8x4_t, const int)
9630 @*@emph{Form of expected instruction(s):} @code{vst4.8 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9635 @item void vst4q_lane_s32 (int32_t *, int32x4x4_t, const int)
9636 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9641 @item void vst4q_lane_s16 (int16_t *, int16x8x4_t, const int)
9642 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9647 @item void vst4q_lane_u32 (uint32_t *, uint32x4x4_t, const int)
9648 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9653 @item void vst4q_lane_u16 (uint16_t *, uint16x8x4_t, const int)
9654 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9659 @item void vst4q_lane_f32 (float32_t *, float32x4x4_t, const int)
9660 @*@emph{Form of expected instruction(s):} @code{vst4.32 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9665 @item void vst4q_lane_p16 (poly16_t *, poly16x8x4_t, const int)
9666 @*@emph{Form of expected instruction(s):} @code{vst4.16 @{@var{d0}[@var{0}], @var{d1}[@var{0}], @var{d2}[@var{0}], @var{d3}[@var{0}]@}, [@var{r0}]}
9672 @subsubsection Logical operations (AND)
9675 @item uint32x2_t vand_u32 (uint32x2_t, uint32x2_t)
9676 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9681 @item uint16x4_t vand_u16 (uint16x4_t, uint16x4_t)
9682 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9687 @item uint8x8_t vand_u8 (uint8x8_t, uint8x8_t)
9688 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9693 @item int32x2_t vand_s32 (int32x2_t, int32x2_t)
9694 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9699 @item int16x4_t vand_s16 (int16x4_t, int16x4_t)
9700 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9705 @item int8x8_t vand_s8 (int8x8_t, int8x8_t)
9706 @*@emph{Form of expected instruction(s):} @code{vand @var{d0}, @var{d0}, @var{d0}}
9711 @item uint64x1_t vand_u64 (uint64x1_t, uint64x1_t)
9716 @item int64x1_t vand_s64 (int64x1_t, int64x1_t)
9721 @item uint32x4_t vandq_u32 (uint32x4_t, uint32x4_t)
9722 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9727 @item uint16x8_t vandq_u16 (uint16x8_t, uint16x8_t)
9728 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9733 @item uint8x16_t vandq_u8 (uint8x16_t, uint8x16_t)
9734 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9739 @item int32x4_t vandq_s32 (int32x4_t, int32x4_t)
9740 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9745 @item int16x8_t vandq_s16 (int16x8_t, int16x8_t)
9746 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9751 @item int8x16_t vandq_s8 (int8x16_t, int8x16_t)
9752 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9757 @item uint64x2_t vandq_u64 (uint64x2_t, uint64x2_t)
9758 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9763 @item int64x2_t vandq_s64 (int64x2_t, int64x2_t)
9764 @*@emph{Form of expected instruction(s):} @code{vand @var{q0}, @var{q0}, @var{q0}}
9770 @subsubsection Logical operations (OR)
9773 @item uint32x2_t vorr_u32 (uint32x2_t, uint32x2_t)
9774 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9779 @item uint16x4_t vorr_u16 (uint16x4_t, uint16x4_t)
9780 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9785 @item uint8x8_t vorr_u8 (uint8x8_t, uint8x8_t)
9786 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9791 @item int32x2_t vorr_s32 (int32x2_t, int32x2_t)
9792 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9797 @item int16x4_t vorr_s16 (int16x4_t, int16x4_t)
9798 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9803 @item int8x8_t vorr_s8 (int8x8_t, int8x8_t)
9804 @*@emph{Form of expected instruction(s):} @code{vorr @var{d0}, @var{d0}, @var{d0}}
9809 @item uint64x1_t vorr_u64 (uint64x1_t, uint64x1_t)
9814 @item int64x1_t vorr_s64 (int64x1_t, int64x1_t)
9819 @item uint32x4_t vorrq_u32 (uint32x4_t, uint32x4_t)
9820 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9825 @item uint16x8_t vorrq_u16 (uint16x8_t, uint16x8_t)
9826 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9831 @item uint8x16_t vorrq_u8 (uint8x16_t, uint8x16_t)
9832 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9837 @item int32x4_t vorrq_s32 (int32x4_t, int32x4_t)
9838 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9843 @item int16x8_t vorrq_s16 (int16x8_t, int16x8_t)
9844 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9849 @item int8x16_t vorrq_s8 (int8x16_t, int8x16_t)
9850 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9855 @item uint64x2_t vorrq_u64 (uint64x2_t, uint64x2_t)
9856 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9861 @item int64x2_t vorrq_s64 (int64x2_t, int64x2_t)
9862 @*@emph{Form of expected instruction(s):} @code{vorr @var{q0}, @var{q0}, @var{q0}}
9868 @subsubsection Logical operations (exclusive OR)
9871 @item uint32x2_t veor_u32 (uint32x2_t, uint32x2_t)
9872 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9877 @item uint16x4_t veor_u16 (uint16x4_t, uint16x4_t)
9878 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9883 @item uint8x8_t veor_u8 (uint8x8_t, uint8x8_t)
9884 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9889 @item int32x2_t veor_s32 (int32x2_t, int32x2_t)
9890 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9895 @item int16x4_t veor_s16 (int16x4_t, int16x4_t)
9896 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9901 @item int8x8_t veor_s8 (int8x8_t, int8x8_t)
9902 @*@emph{Form of expected instruction(s):} @code{veor @var{d0}, @var{d0}, @var{d0}}
9907 @item uint64x1_t veor_u64 (uint64x1_t, uint64x1_t)
9912 @item int64x1_t veor_s64 (int64x1_t, int64x1_t)
9917 @item uint32x4_t veorq_u32 (uint32x4_t, uint32x4_t)
9918 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9923 @item uint16x8_t veorq_u16 (uint16x8_t, uint16x8_t)
9924 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9929 @item uint8x16_t veorq_u8 (uint8x16_t, uint8x16_t)
9930 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9935 @item int32x4_t veorq_s32 (int32x4_t, int32x4_t)
9936 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9941 @item int16x8_t veorq_s16 (int16x8_t, int16x8_t)
9942 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9947 @item int8x16_t veorq_s8 (int8x16_t, int8x16_t)
9948 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9953 @item uint64x2_t veorq_u64 (uint64x2_t, uint64x2_t)
9954 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9959 @item int64x2_t veorq_s64 (int64x2_t, int64x2_t)
9960 @*@emph{Form of expected instruction(s):} @code{veor @var{q0}, @var{q0}, @var{q0}}
9966 @subsubsection Logical operations (AND-NOT)
9969 @item uint32x2_t vbic_u32 (uint32x2_t, uint32x2_t)
9970 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
9975 @item uint16x4_t vbic_u16 (uint16x4_t, uint16x4_t)
9976 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
9981 @item uint8x8_t vbic_u8 (uint8x8_t, uint8x8_t)
9982 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
9987 @item int32x2_t vbic_s32 (int32x2_t, int32x2_t)
9988 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
9993 @item int16x4_t vbic_s16 (int16x4_t, int16x4_t)
9994 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
9999 @item int8x8_t vbic_s8 (int8x8_t, int8x8_t)
10000 @*@emph{Form of expected instruction(s):} @code{vbic @var{d0}, @var{d0}, @var{d0}}
10005 @item uint64x1_t vbic_u64 (uint64x1_t, uint64x1_t)
10010 @item int64x1_t vbic_s64 (int64x1_t, int64x1_t)
10015 @item uint32x4_t vbicq_u32 (uint32x4_t, uint32x4_t)
10016 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10021 @item uint16x8_t vbicq_u16 (uint16x8_t, uint16x8_t)
10022 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10027 @item uint8x16_t vbicq_u8 (uint8x16_t, uint8x16_t)
10028 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10033 @item int32x4_t vbicq_s32 (int32x4_t, int32x4_t)
10034 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10039 @item int16x8_t vbicq_s16 (int16x8_t, int16x8_t)
10040 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10045 @item int8x16_t vbicq_s8 (int8x16_t, int8x16_t)
10046 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10051 @item uint64x2_t vbicq_u64 (uint64x2_t, uint64x2_t)
10052 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10057 @item int64x2_t vbicq_s64 (int64x2_t, int64x2_t)
10058 @*@emph{Form of expected instruction(s):} @code{vbic @var{q0}, @var{q0}, @var{q0}}
10064 @subsubsection Logical operations (OR-NOT)
10067 @item uint32x2_t vorn_u32 (uint32x2_t, uint32x2_t)
10068 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10073 @item uint16x4_t vorn_u16 (uint16x4_t, uint16x4_t)
10074 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10079 @item uint8x8_t vorn_u8 (uint8x8_t, uint8x8_t)
10080 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10085 @item int32x2_t vorn_s32 (int32x2_t, int32x2_t)
10086 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10091 @item int16x4_t vorn_s16 (int16x4_t, int16x4_t)
10092 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10097 @item int8x8_t vorn_s8 (int8x8_t, int8x8_t)
10098 @*@emph{Form of expected instruction(s):} @code{vorn @var{d0}, @var{d0}, @var{d0}}
10103 @item uint64x1_t vorn_u64 (uint64x1_t, uint64x1_t)
10108 @item int64x1_t vorn_s64 (int64x1_t, int64x1_t)
10113 @item uint32x4_t vornq_u32 (uint32x4_t, uint32x4_t)
10114 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10119 @item uint16x8_t vornq_u16 (uint16x8_t, uint16x8_t)
10120 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10125 @item uint8x16_t vornq_u8 (uint8x16_t, uint8x16_t)
10126 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10131 @item int32x4_t vornq_s32 (int32x4_t, int32x4_t)
10132 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10137 @item int16x8_t vornq_s16 (int16x8_t, int16x8_t)
10138 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10143 @item int8x16_t vornq_s8 (int8x16_t, int8x16_t)
10144 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10149 @item uint64x2_t vornq_u64 (uint64x2_t, uint64x2_t)
10150 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10155 @item int64x2_t vornq_s64 (int64x2_t, int64x2_t)
10156 @*@emph{Form of expected instruction(s):} @code{vorn @var{q0}, @var{q0}, @var{q0}}
10162 @subsubsection Reinterpret casts
10165 @item poly8x8_t vreinterpret_p8_u32 (uint32x2_t)
10170 @item poly8x8_t vreinterpret_p8_u16 (uint16x4_t)
10175 @item poly8x8_t vreinterpret_p8_u8 (uint8x8_t)
10180 @item poly8x8_t vreinterpret_p8_s32 (int32x2_t)
10185 @item poly8x8_t vreinterpret_p8_s16 (int16x4_t)
10190 @item poly8x8_t vreinterpret_p8_s8 (int8x8_t)
10195 @item poly8x8_t vreinterpret_p8_u64 (uint64x1_t)
10200 @item poly8x8_t vreinterpret_p8_s64 (int64x1_t)
10205 @item poly8x8_t vreinterpret_p8_f32 (float32x2_t)
10210 @item poly8x8_t vreinterpret_p8_p16 (poly16x4_t)
10215 @item poly8x16_t vreinterpretq_p8_u32 (uint32x4_t)
10220 @item poly8x16_t vreinterpretq_p8_u16 (uint16x8_t)
10225 @item poly8x16_t vreinterpretq_p8_u8 (uint8x16_t)
10230 @item poly8x16_t vreinterpretq_p8_s32 (int32x4_t)
10235 @item poly8x16_t vreinterpretq_p8_s16 (int16x8_t)
10240 @item poly8x16_t vreinterpretq_p8_s8 (int8x16_t)
10245 @item poly8x16_t vreinterpretq_p8_u64 (uint64x2_t)
10250 @item poly8x16_t vreinterpretq_p8_s64 (int64x2_t)
10255 @item poly8x16_t vreinterpretq_p8_f32 (float32x4_t)
10260 @item poly8x16_t vreinterpretq_p8_p16 (poly16x8_t)
10265 @item poly16x4_t vreinterpret_p16_u32 (uint32x2_t)
10270 @item poly16x4_t vreinterpret_p16_u16 (uint16x4_t)
10275 @item poly16x4_t vreinterpret_p16_u8 (uint8x8_t)
10280 @item poly16x4_t vreinterpret_p16_s32 (int32x2_t)
10285 @item poly16x4_t vreinterpret_p16_s16 (int16x4_t)
10290 @item poly16x4_t vreinterpret_p16_s8 (int8x8_t)
10295 @item poly16x4_t vreinterpret_p16_u64 (uint64x1_t)
10300 @item poly16x4_t vreinterpret_p16_s64 (int64x1_t)
10305 @item poly16x4_t vreinterpret_p16_f32 (float32x2_t)
10310 @item poly16x4_t vreinterpret_p16_p8 (poly8x8_t)
10315 @item poly16x8_t vreinterpretq_p16_u32 (uint32x4_t)
10320 @item poly16x8_t vreinterpretq_p16_u16 (uint16x8_t)
10325 @item poly16x8_t vreinterpretq_p16_u8 (uint8x16_t)
10330 @item poly16x8_t vreinterpretq_p16_s32 (int32x4_t)
10335 @item poly16x8_t vreinterpretq_p16_s16 (int16x8_t)
10340 @item poly16x8_t vreinterpretq_p16_s8 (int8x16_t)
10345 @item poly16x8_t vreinterpretq_p16_u64 (uint64x2_t)
10350 @item poly16x8_t vreinterpretq_p16_s64 (int64x2_t)
10355 @item poly16x8_t vreinterpretq_p16_f32 (float32x4_t)
10360 @item poly16x8_t vreinterpretq_p16_p8 (poly8x16_t)
10365 @item float32x2_t vreinterpret_f32_u32 (uint32x2_t)
10370 @item float32x2_t vreinterpret_f32_u16 (uint16x4_t)
10375 @item float32x2_t vreinterpret_f32_u8 (uint8x8_t)
10380 @item float32x2_t vreinterpret_f32_s32 (int32x2_t)
10385 @item float32x2_t vreinterpret_f32_s16 (int16x4_t)
10390 @item float32x2_t vreinterpret_f32_s8 (int8x8_t)
10395 @item float32x2_t vreinterpret_f32_u64 (uint64x1_t)
10400 @item float32x2_t vreinterpret_f32_s64 (int64x1_t)
10405 @item float32x2_t vreinterpret_f32_p16 (poly16x4_t)
10410 @item float32x2_t vreinterpret_f32_p8 (poly8x8_t)
10415 @item float32x4_t vreinterpretq_f32_u32 (uint32x4_t)
10420 @item float32x4_t vreinterpretq_f32_u16 (uint16x8_t)
10425 @item float32x4_t vreinterpretq_f32_u8 (uint8x16_t)
10430 @item float32x4_t vreinterpretq_f32_s32 (int32x4_t)
10435 @item float32x4_t vreinterpretq_f32_s16 (int16x8_t)
10440 @item float32x4_t vreinterpretq_f32_s8 (int8x16_t)
10445 @item float32x4_t vreinterpretq_f32_u64 (uint64x2_t)
10450 @item float32x4_t vreinterpretq_f32_s64 (int64x2_t)
10455 @item float32x4_t vreinterpretq_f32_p16 (poly16x8_t)
10460 @item float32x4_t vreinterpretq_f32_p8 (poly8x16_t)
10465 @item int64x1_t vreinterpret_s64_u32 (uint32x2_t)
10470 @item int64x1_t vreinterpret_s64_u16 (uint16x4_t)
10475 @item int64x1_t vreinterpret_s64_u8 (uint8x8_t)
10480 @item int64x1_t vreinterpret_s64_s32 (int32x2_t)
10485 @item int64x1_t vreinterpret_s64_s16 (int16x4_t)
10490 @item int64x1_t vreinterpret_s64_s8 (int8x8_t)
10495 @item int64x1_t vreinterpret_s64_u64 (uint64x1_t)
10500 @item int64x1_t vreinterpret_s64_f32 (float32x2_t)
10505 @item int64x1_t vreinterpret_s64_p16 (poly16x4_t)
10510 @item int64x1_t vreinterpret_s64_p8 (poly8x8_t)
10515 @item int64x2_t vreinterpretq_s64_u32 (uint32x4_t)
10520 @item int64x2_t vreinterpretq_s64_u16 (uint16x8_t)
10525 @item int64x2_t vreinterpretq_s64_u8 (uint8x16_t)
10530 @item int64x2_t vreinterpretq_s64_s32 (int32x4_t)
10535 @item int64x2_t vreinterpretq_s64_s16 (int16x8_t)
10540 @item int64x2_t vreinterpretq_s64_s8 (int8x16_t)
10545 @item int64x2_t vreinterpretq_s64_u64 (uint64x2_t)
10550 @item int64x2_t vreinterpretq_s64_f32 (float32x4_t)
10555 @item int64x2_t vreinterpretq_s64_p16 (poly16x8_t)
10560 @item int64x2_t vreinterpretq_s64_p8 (poly8x16_t)
10565 @item uint64x1_t vreinterpret_u64_u32 (uint32x2_t)
10570 @item uint64x1_t vreinterpret_u64_u16 (uint16x4_t)
10575 @item uint64x1_t vreinterpret_u64_u8 (uint8x8_t)
10580 @item uint64x1_t vreinterpret_u64_s32 (int32x2_t)
10585 @item uint64x1_t vreinterpret_u64_s16 (int16x4_t)
10590 @item uint64x1_t vreinterpret_u64_s8 (int8x8_t)
10595 @item uint64x1_t vreinterpret_u64_s64 (int64x1_t)
10600 @item uint64x1_t vreinterpret_u64_f32 (float32x2_t)
10605 @item uint64x1_t vreinterpret_u64_p16 (poly16x4_t)
10610 @item uint64x1_t vreinterpret_u64_p8 (poly8x8_t)
10615 @item uint64x2_t vreinterpretq_u64_u32 (uint32x4_t)
10620 @item uint64x2_t vreinterpretq_u64_u16 (uint16x8_t)
10625 @item uint64x2_t vreinterpretq_u64_u8 (uint8x16_t)
10630 @item uint64x2_t vreinterpretq_u64_s32 (int32x4_t)
10635 @item uint64x2_t vreinterpretq_u64_s16 (int16x8_t)
10640 @item uint64x2_t vreinterpretq_u64_s8 (int8x16_t)
10645 @item uint64x2_t vreinterpretq_u64_s64 (int64x2_t)
10650 @item uint64x2_t vreinterpretq_u64_f32 (float32x4_t)
10655 @item uint64x2_t vreinterpretq_u64_p16 (poly16x8_t)
10660 @item uint64x2_t vreinterpretq_u64_p8 (poly8x16_t)
10665 @item int8x8_t vreinterpret_s8_u32 (uint32x2_t)
10670 @item int8x8_t vreinterpret_s8_u16 (uint16x4_t)
10675 @item int8x8_t vreinterpret_s8_u8 (uint8x8_t)
10680 @item int8x8_t vreinterpret_s8_s32 (int32x2_t)
10685 @item int8x8_t vreinterpret_s8_s16 (int16x4_t)
10690 @item int8x8_t vreinterpret_s8_u64 (uint64x1_t)
10695 @item int8x8_t vreinterpret_s8_s64 (int64x1_t)
10700 @item int8x8_t vreinterpret_s8_f32 (float32x2_t)
10705 @item int8x8_t vreinterpret_s8_p16 (poly16x4_t)
10710 @item int8x8_t vreinterpret_s8_p8 (poly8x8_t)
10715 @item int8x16_t vreinterpretq_s8_u32 (uint32x4_t)
10720 @item int8x16_t vreinterpretq_s8_u16 (uint16x8_t)
10725 @item int8x16_t vreinterpretq_s8_u8 (uint8x16_t)
10730 @item int8x16_t vreinterpretq_s8_s32 (int32x4_t)
10735 @item int8x16_t vreinterpretq_s8_s16 (int16x8_t)
10740 @item int8x16_t vreinterpretq_s8_u64 (uint64x2_t)
10745 @item int8x16_t vreinterpretq_s8_s64 (int64x2_t)
10750 @item int8x16_t vreinterpretq_s8_f32 (float32x4_t)
10755 @item int8x16_t vreinterpretq_s8_p16 (poly16x8_t)
10760 @item int8x16_t vreinterpretq_s8_p8 (poly8x16_t)
10765 @item int16x4_t vreinterpret_s16_u32 (uint32x2_t)
10770 @item int16x4_t vreinterpret_s16_u16 (uint16x4_t)
10775 @item int16x4_t vreinterpret_s16_u8 (uint8x8_t)
10780 @item int16x4_t vreinterpret_s16_s32 (int32x2_t)
10785 @item int16x4_t vreinterpret_s16_s8 (int8x8_t)
10790 @item int16x4_t vreinterpret_s16_u64 (uint64x1_t)
10795 @item int16x4_t vreinterpret_s16_s64 (int64x1_t)
10800 @item int16x4_t vreinterpret_s16_f32 (float32x2_t)
10805 @item int16x4_t vreinterpret_s16_p16 (poly16x4_t)
10810 @item int16x4_t vreinterpret_s16_p8 (poly8x8_t)
10815 @item int16x8_t vreinterpretq_s16_u32 (uint32x4_t)
10820 @item int16x8_t vreinterpretq_s16_u16 (uint16x8_t)
10825 @item int16x8_t vreinterpretq_s16_u8 (uint8x16_t)
10830 @item int16x8_t vreinterpretq_s16_s32 (int32x4_t)
10835 @item int16x8_t vreinterpretq_s16_s8 (int8x16_t)
10840 @item int16x8_t vreinterpretq_s16_u64 (uint64x2_t)
10845 @item int16x8_t vreinterpretq_s16_s64 (int64x2_t)
10850 @item int16x8_t vreinterpretq_s16_f32 (float32x4_t)
10855 @item int16x8_t vreinterpretq_s16_p16 (poly16x8_t)
10860 @item int16x8_t vreinterpretq_s16_p8 (poly8x16_t)
10865 @item int32x2_t vreinterpret_s32_u32 (uint32x2_t)
10870 @item int32x2_t vreinterpret_s32_u16 (uint16x4_t)
10875 @item int32x2_t vreinterpret_s32_u8 (uint8x8_t)
10880 @item int32x2_t vreinterpret_s32_s16 (int16x4_t)
10885 @item int32x2_t vreinterpret_s32_s8 (int8x8_t)
10890 @item int32x2_t vreinterpret_s32_u64 (uint64x1_t)
10895 @item int32x2_t vreinterpret_s32_s64 (int64x1_t)
10900 @item int32x2_t vreinterpret_s32_f32 (float32x2_t)
10905 @item int32x2_t vreinterpret_s32_p16 (poly16x4_t)
10910 @item int32x2_t vreinterpret_s32_p8 (poly8x8_t)
10915 @item int32x4_t vreinterpretq_s32_u32 (uint32x4_t)
10920 @item int32x4_t vreinterpretq_s32_u16 (uint16x8_t)
10925 @item int32x4_t vreinterpretq_s32_u8 (uint8x16_t)
10930 @item int32x4_t vreinterpretq_s32_s16 (int16x8_t)
10935 @item int32x4_t vreinterpretq_s32_s8 (int8x16_t)
10940 @item int32x4_t vreinterpretq_s32_u64 (uint64x2_t)
10945 @item int32x4_t vreinterpretq_s32_s64 (int64x2_t)
10950 @item int32x4_t vreinterpretq_s32_f32 (float32x4_t)
10955 @item int32x4_t vreinterpretq_s32_p16 (poly16x8_t)
10960 @item int32x4_t vreinterpretq_s32_p8 (poly8x16_t)
10965 @item uint8x8_t vreinterpret_u8_u32 (uint32x2_t)
10970 @item uint8x8_t vreinterpret_u8_u16 (uint16x4_t)
10975 @item uint8x8_t vreinterpret_u8_s32 (int32x2_t)
10980 @item uint8x8_t vreinterpret_u8_s16 (int16x4_t)
10985 @item uint8x8_t vreinterpret_u8_s8 (int8x8_t)
10990 @item uint8x8_t vreinterpret_u8_u64 (uint64x1_t)
10995 @item uint8x8_t vreinterpret_u8_s64 (int64x1_t)
11000 @item uint8x8_t vreinterpret_u8_f32 (float32x2_t)
11005 @item uint8x8_t vreinterpret_u8_p16 (poly16x4_t)
11010 @item uint8x8_t vreinterpret_u8_p8 (poly8x8_t)
11015 @item uint8x16_t vreinterpretq_u8_u32 (uint32x4_t)
11020 @item uint8x16_t vreinterpretq_u8_u16 (uint16x8_t)
11025 @item uint8x16_t vreinterpretq_u8_s32 (int32x4_t)
11030 @item uint8x16_t vreinterpretq_u8_s16 (int16x8_t)
11035 @item uint8x16_t vreinterpretq_u8_s8 (int8x16_t)
11040 @item uint8x16_t vreinterpretq_u8_u64 (uint64x2_t)
11045 @item uint8x16_t vreinterpretq_u8_s64 (int64x2_t)
11050 @item uint8x16_t vreinterpretq_u8_f32 (float32x4_t)
11055 @item uint8x16_t vreinterpretq_u8_p16 (poly16x8_t)
11060 @item uint8x16_t vreinterpretq_u8_p8 (poly8x16_t)
11065 @item uint16x4_t vreinterpret_u16_u32 (uint32x2_t)
11070 @item uint16x4_t vreinterpret_u16_u8 (uint8x8_t)
11075 @item uint16x4_t vreinterpret_u16_s32 (int32x2_t)
11080 @item uint16x4_t vreinterpret_u16_s16 (int16x4_t)
11085 @item uint16x4_t vreinterpret_u16_s8 (int8x8_t)
11090 @item uint16x4_t vreinterpret_u16_u64 (uint64x1_t)
11095 @item uint16x4_t vreinterpret_u16_s64 (int64x1_t)
11100 @item uint16x4_t vreinterpret_u16_f32 (float32x2_t)
11105 @item uint16x4_t vreinterpret_u16_p16 (poly16x4_t)
11110 @item uint16x4_t vreinterpret_u16_p8 (poly8x8_t)
11115 @item uint16x8_t vreinterpretq_u16_u32 (uint32x4_t)
11120 @item uint16x8_t vreinterpretq_u16_u8 (uint8x16_t)
11125 @item uint16x8_t vreinterpretq_u16_s32 (int32x4_t)
11130 @item uint16x8_t vreinterpretq_u16_s16 (int16x8_t)
11135 @item uint16x8_t vreinterpretq_u16_s8 (int8x16_t)
11140 @item uint16x8_t vreinterpretq_u16_u64 (uint64x2_t)
11145 @item uint16x8_t vreinterpretq_u16_s64 (int64x2_t)
11150 @item uint16x8_t vreinterpretq_u16_f32 (float32x4_t)
11155 @item uint16x8_t vreinterpretq_u16_p16 (poly16x8_t)
11160 @item uint16x8_t vreinterpretq_u16_p8 (poly8x16_t)
11165 @item uint32x2_t vreinterpret_u32_u16 (uint16x4_t)
11170 @item uint32x2_t vreinterpret_u32_u8 (uint8x8_t)
11175 @item uint32x2_t vreinterpret_u32_s32 (int32x2_t)
11180 @item uint32x2_t vreinterpret_u32_s16 (int16x4_t)
11185 @item uint32x2_t vreinterpret_u32_s8 (int8x8_t)
11190 @item uint32x2_t vreinterpret_u32_u64 (uint64x1_t)
11195 @item uint32x2_t vreinterpret_u32_s64 (int64x1_t)
11200 @item uint32x2_t vreinterpret_u32_f32 (float32x2_t)
11205 @item uint32x2_t vreinterpret_u32_p16 (poly16x4_t)
11210 @item uint32x2_t vreinterpret_u32_p8 (poly8x8_t)
11215 @item uint32x4_t vreinterpretq_u32_u16 (uint16x8_t)
11220 @item uint32x4_t vreinterpretq_u32_u8 (uint8x16_t)
11225 @item uint32x4_t vreinterpretq_u32_s32 (int32x4_t)
11230 @item uint32x4_t vreinterpretq_u32_s16 (int16x8_t)
11235 @item uint32x4_t vreinterpretq_u32_s8 (int8x16_t)
11240 @item uint32x4_t vreinterpretq_u32_u64 (uint64x2_t)
11245 @item uint32x4_t vreinterpretq_u32_s64 (int64x2_t)
11250 @item uint32x4_t vreinterpretq_u32_f32 (float32x4_t)
11255 @item uint32x4_t vreinterpretq_u32_p16 (poly16x8_t)
11260 @item uint32x4_t vreinterpretq_u32_p8 (poly8x16_t)