| blob | c748c92d2eda7f8a35de905a6d02fec43fe41986 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
108 /* Number of attempts to combine instructions in this function. */
112 /* Number of attempts that got as far as substitution in this function. */
116 /* Number of instructions combined with added SETs in this function. */
120 /* Number of instructions combined in this function. */
124 /* Totals over entire compilation. */
128 /* combine_instructions may try to replace the right hand side of the
129 second instruction with the value of an associated REG_EQUAL note
130 before throwing it at try_combine. That is problematic when there
131 is a REG_DEAD note for a register used in the old right hand side
132 and can cause distribute_notes to do wrong things. This is the
133 second instruction if it has been so modified, null otherwise. */
137 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
141 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
144 \f
146 /* Record last point of death of (hard or pseudo) register n. */
149 /* Record last point of modification of (hard or pseudo) register n. */
152 /* The next group of fields allows the recording of the last value assigned
153 to (hard or pseudo) register n. We use this information to see if an
154 operation being processed is redundant given a prior operation performed
155 on the register. For example, an `and' with a constant is redundant if
156 all the zero bits are already known to be turned off.
158 We use an approach similar to that used by cse, but change it in the
159 following ways:
161 (1) We do not want to reinitialize at each label.
162 (2) It is useful, but not critical, to know the actual value assigned
163 to a register. Often just its form is helpful.
165 Therefore, we maintain the following fields:
167 last_set_value the last value assigned
168 last_set_label records the value of label_tick when the
169 register was assigned
170 last_set_table_tick records the value of label_tick when a
171 value using the register is assigned
172 last_set_invalid set to nonzero when it is not valid
173 to use the value of this register in some
174 register's value
176 To understand the usage of these tables, it is important to understand
177 the distinction between the value in last_set_value being valid and
178 the register being validly contained in some other expression in the
179 table.
181 (The next two parameters are out of date).
183 reg_stat[i].last_set_value is valid if it is nonzero, and either
184 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
186 Register I may validly appear in any expression returned for the value
187 of another register if reg_n_sets[i] is 1. It may also appear in the
188 value for register J if reg_stat[j].last_set_invalid is zero, or
189 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
191 If an expression is found in the table containing a register which may
192 not validly appear in an expression, the register is replaced by
193 something that won't match, (clobber (const_int 0)). */
195 /* Record last value assigned to (hard or pseudo) register n. */
197 rtx last_set_value;
199 /* Record the value of label_tick when an expression involving register n
200 is placed in last_set_value. */
204 /* Record the value of label_tick when the value for register n is placed in
205 last_set_value. */
209 /* These fields are maintained in parallel with last_set_value and are
210 used to store the mode in which the register was last set, the bits
211 that were known to be zero when it was last set, and the number of
212 sign bits copies it was known to have when it was last set. */
218 /* Set nonzero if references to register n in expressions should not be
219 used. last_set_invalid is set nonzero when this register is being
220 assigned to and last_set_table_tick == label_tick. */
224 /* Some registers that are set more than once and used in more than one
225 basic block are nevertheless always set in similar ways. For example,
226 a QImode register may be loaded from memory in two places on a machine
227 where byte loads zero extend.
229 We record in the following fields if a register has some leading bits
230 that are always equal to the sign bit, and what we know about the
231 nonzero bits of a register, specifically which bits are known to be
232 zero.
234 If an entry is zero, it means that we don't know anything special. */
240 /* Record the value of the label_tick when the last truncation
241 happened. The field truncated_to_mode is only valid if
242 truncation_label == label_tick. */
246 /* Record the last truncation seen for this register. If truncation
247 is not a nop to this mode we might be able to save an explicit
248 truncation if we know that value already contains a truncated
249 value. */
252 };
257 /* One plus the highest pseudo for which we track REG_N_SETS.
258 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
259 but during combine_split_insns new pseudos can be created. As we don't have
260 updated DF information in that case, it is hard to initialize the array
261 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
262 so instead of growing the arrays, just assume all newly created pseudos
263 during combine might be set multiple times. */
267 /* Record the luid of the last insn that invalidated memory
268 (anything that writes memory, and subroutine calls, but not pushes). */
272 /* Record the luid of the last CALL_INSN
273 so we can tell whether a potential combination crosses any calls. */
277 /* When `subst' is called, this is the insn that is being modified
278 (by combining in a previous insn). The PATTERN of this insn
279 is still the old pattern partially modified and it should not be
280 looked at, but this may be used to examine the successors of the insn
281 to judge whether a simplification is valid. */
285 /* This is the lowest LUID that `subst' is currently dealing with.
286 get_last_value will not return a value if the register was set at or
287 after this LUID. If not for this mechanism, we could get confused if
288 I2 or I1 in try_combine were an insn that used the old value of a register
289 to obtain a new value. In that case, we might erroneously get the
290 new value of the register when we wanted the old one. */
294 /* This contains any hard registers that are used in newpat; reg_dead_at_p
295 must consider all these registers to be always live. */
299 /* This is an insn to which a LOG_LINKS entry has been added. If this
300 insn is the earlier than I2 or I3, combine should rescan starting at
301 that location. */
305 /* Basic block in which we are performing combines. */
309 \f
310 /* Length of the currently allocated uid_insn_cost array. */
314 /* The following array records the insn_rtx_cost for every insn
315 in the instruction stream. */
319 /* The following array records the LOG_LINKS for every insn in the
320 instruction stream as struct insn_link pointers. */
326 };
332 {
336 }
338 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
339 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
341 #define FOR_EACH_LOG_LINK(L, INSN) \
342 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
344 /* Links for LOG_LINKS are allocated from this obstack. */
348 /* Allocate a link. */
352 {
360 }
362 /* Incremented for each basic block. */
366 /* Reset to label_tick for each extended basic block in scanning order. */
370 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
371 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
375 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
376 be safely used. It is zero while computing them and after combine has
377 completed. This former test prevents propagating values based on
378 previously set values, which can be incorrect if a variable is modified
379 in a loop. */
383 \f
384 /* Record one modification to rtl structure
385 to be undone by storing old_contents into *where. */
389 struct undo
390 {
395 };
397 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
398 num_undo says how many are currently recorded.
400 other_insn is nonzero if we have modified some other insn in the process
401 of working on subst_insn. It must be verified too. */
403 struct undobuf
404 {
408 };
412 /* Number of times the pseudo being substituted for
413 was found and replaced. */
418 scalar_int_mode,
421 scalar_int_mode,
494 \f
496 /* It is not safe to use ordinary gen_lowpart in combine.
497 See comments in gen_lowpart_for_combine. */
498 #undef RTL_HOOKS_GEN_LOWPART
499 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
501 /* Our implementation of gen_lowpart never emits a new pseudo. */
502 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
503 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
505 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
506 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
508 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
509 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
511 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
512 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
516 \f
517 /* Convenience wrapper for the canonicalize_comparison target hook.
518 Target hooks cannot use enum rtx_code. */
522 {
526 }
528 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
529 PATTERN can not be split. Otherwise, it returns an insn sequence.
530 This is a wrapper around split_insns which ensures that the
531 reg_stat vector is made larger if the splitter creates a new
532 register. */
536 {
545 }
547 /* This is used by find_single_use to locate an rtx in LOC that
548 contains exactly one use of DEST, which is typically either a REG
549 or CC0. It returns a pointer to the innermost rtx expression
550 containing DEST. Appearances of DEST that are being used to
551 totally replace it are not counted. */
555 {
564 {
568 CASE_CONST_ANY:
573 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
574 of a REG that occupies all of the REG, the insn uses DEST if
575 it is mentioned in the destination or the source. Otherwise, we
576 need just check the source. */
596 }
598 /* If it wasn't one of the common cases above, check each expression and
599 vector of this code. Look for a unique usage of DEST. */
603 {
605 {
610 else
616 /* Duplicate usage. */
618 }
620 {
624 {
630 else
637 }
638 }
639 }
642 }
645 /* See if DEST, produced in INSN, is used only a single time in the
646 sequel. If so, return a pointer to the innermost rtx expression in which
647 it is used.
649 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
651 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
652 care about REG_DEAD notes or LOG_LINKS.
654 Otherwise, we find the single use by finding an insn that has a
655 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
656 only referenced once in that insn, we know that it must be the first
657 and last insn referencing DEST. */
661 {
662 basic_block bb;
668 {
678 }
688 {
694 {
699 }
700 }
703 }
704 \f
705 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
706 insn. The substitution can be undone by undo_all. If INTO is already
707 set to NEWVAL, do not record this change. Because computing NEWVAL might
708 also call SUBST, we have to compute it before we put anything into
709 the undo table. */
711 static void
713 {
720 /* We'd like to catch as many invalid transformations here as
721 possible. Unfortunately, there are way too many mode changes
722 that are perfectly valid, so we'd waste too much effort for
723 little gain doing the checks here. Focus on catching invalid
724 transformations involving integer constants. */
727 {
728 /* Sanity check that we're replacing oldval with a CONST_INT
729 that is a valid sign-extension for the original mode. */
733 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
734 CONST_INT is not valid, because after the replacement, the
735 original mode would be gone. Unfortunately, we can't tell
736 when do_SUBST is called to replace the operand thereof, so we
737 perform this test on oldval instead, checking whether an
738 invalid replacement took place before we got here. */
743 }
747 else
756 }
758 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
760 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
761 for the value of a HOST_WIDE_INT value (including CONST_INT) is
762 not safe. */
764 static void
766 {
775 else
784 }
786 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
788 /* Similar to SUBST, but just substitute the mode. This is used when
789 changing the mode of a pseudo-register, so that any other
790 references to the entry in the regno_reg_rtx array will change as
791 well. */
793 static void
795 {
804 else
813 }
815 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
817 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
819 static void
821 {
830 else
839 }
841 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
842 \f
843 /* Subroutine of try_combine. Determine whether the replacement patterns
844 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
845 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
846 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
847 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
848 of all the instructions can be estimated and the replacements are more
849 expensive than the original sequence. */
851 static bool
854 {
859 /* Lookup the original insn_rtx_costs. */
864 {
867 {
871 }
872 else
873 {
877 }
878 }
879 else
880 {
883 }
885 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
886 correct that. */
891 /* Calculate the replacement insn_rtx_costs. */
894 {
898 }
899 else
900 {
903 }
906 {
912 {
915 }
916 else
918 }
920 /* Disallow this combination if both new_cost and old_cost are greater than
921 zero, and new_cost is greater than old cost. */
925 {
944 else
946 }
951 /* Update the uid_insn_cost array with the replacement costs. */
955 {
959 }
962 }
965 /* Delete any insns that copy a register to itself. */
967 static void
969 {
971 basic_block bb;
974 {
976 {
979 {
984 }
985 }
986 }
987 }
989 \f
990 /* Return false if we do not want to (or cannot) combine DEF. */
991 static bool
993 {
994 /* Do not consider if it is pre/post modification in MEM. */
1000 /* Do not combine frame pointer adjustments. */
1003 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1011 }
1013 /* Return false if we do not want to (or cannot) combine USE. */
1014 static bool
1016 {
1017 /* Do not consider the usage of the stack pointer by function call. */
1022 }
1024 /* Fill in log links field for all insns. */
1026 static void
1028 {
1029 basic_block bb;
1036 /* Pass through each block from the end, recording the uses of each
1037 register and establishing log links when def is encountered.
1038 Note that we do not clear next_use array in order to save time,
1039 so we have to test whether the use is in the same basic block as def.
1041 There are a few cases below when we do not consider the definition or
1042 usage -- these are taken from original flow.c did. Don't ask me why it is
1043 done this way; I don't know and if it works, I don't want to know. */
1046 {
1048 {
1052 /* Log links are created only once. */
1056 {
1072 /* flow.c claimed:
1074 We don't build a LOG_LINK for hard registers contained
1075 in ASM_OPERANDs. If these registers get replaced,
1076 we might wind up changing the semantics of the insn,
1077 even if reload can make what appear to be valid
1078 assignments later. */
1083 /* Don't add duplicate links between instructions. */
1092 }
1097 }
1098 }
1101 }
1103 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1104 true if we found a LOG_LINK that proves that A feeds B. This only works
1105 if there are no instructions between A and B which could have a link
1106 depending on A, since in that case we would not record a link for B.
1107 We also check the implicit dependency created by a cc0 setter/user
1108 pair. */
1110 static bool
1112 {
1120 }
1121 \f
1122 /* Main entry point for combiner. F is the first insn of the function.
1123 NREGS is the first unused pseudo-reg number.
1125 Return nonzero if the combiner has turned an indirect jump
1126 instruction into a direct jump. */
1127 static int
1129 {
1134 basic_block last_bb;
1154 /* Allocate array for insn info. */
1162 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1163 problems when, for example, we have j <<= 1 in a loop. */
1168 /* Scan all SETs and see if we can deduce anything about what
1169 bits are known to be zero for some registers and how many copies
1170 of the sign bit are known to exist for those registers.
1172 Also set any known values so that we can use it while searching
1173 for what bits are known to be set. */
1176 /* Allow the entry block and the first block to fall into the same EBB.
1177 Conceptually the incoming promotions are assigned to the entry block. */
1182 {
1187 label_tick++;
1195 {
1196 rtx links;
1202 insn);
1209 insn);
1211 /* Record the current insn_rtx_cost of this instruction. */
1214 optimize_this_for_speed_p);
1216 {
1219 }
1220 }
1221 }
1225 /* Now scan all the insns in forward order. */
1233 {
1239 label_tick++;
1249 {
1263 /* See if we know about function return values before this
1264 insn based upon SUBREG flags. */
1267 /* See if we can find hardregs and subreg of pseudos in
1268 narrower modes. This could help turning TRUNCATEs
1269 into SUBREGs. */
1272 /* Try this insn with each insn it links back to. */
1278 {
1281 }
1283 /* Try each sequence of three linked insns ending with this one. */
1287 {
1290 /* If the linked insn has been replaced by a note, then there
1291 is no point in pursuing this chain any further. */
1299 {
1302 }
1303 }
1305 /* Try to combine a jump insn that uses CC0
1306 with a preceding insn that sets CC0, and maybe with its
1307 logical predecessor as well.
1308 This is how we make decrement-and-branch insns.
1309 We need this special code because data flow connections
1310 via CC0 do not get entered in LOG_LINKS. */
1317 {
1328 }
1330 /* Do the same for an insn that explicitly references CC0. */
1337 {
1348 }
1350 /* Finally, see if any of the insns that this insn links to
1351 explicitly references CC0. If so, try this insn, that insn,
1352 and its predecessor if it sets CC0. */
1354 {
1366 }
1368 /* Try combining an insn with two different insns whose results it
1369 uses. */
1379 {
1382 }
1384 /* Try four-instruction combinations. */
1387 {
1391 /* If the linked insn has been replaced by a note, then there
1392 is no point in pursuing this chain any further. */
1397 {
1401 /* I0 -> I1 -> I2 -> I3. */
1407 {
1410 }
1411 /* I0, I1 -> I2, I2 -> I3. */
1418 {
1421 }
1422 }
1425 {
1429 /* I0 -> I2; I1, I2 -> I3. */
1435 {
1438 }
1439 /* I0 -> I1; I1, I2 -> I3. */
1445 {
1448 }
1449 }
1450 }
1452 /* Try this insn with each REG_EQUAL note it links back to. */
1454 {
1460 /* Avoid using a register that may already been marked
1461 dead by an earlier instruction. */
1469 {
1470 /* Temporarily replace the set's source with the
1471 contents of the REG_EQUAL note. The insn will
1472 be deleted or recognized by try_combine. */
1483 last_combined_insn);
1486 {
1489 }
1492 }
1493 }
1498 retry:
1499 ;
1500 }
1501 }
1508 /* Clean up. */
1514 {
1517 {
1520 }
1522 }
1532 /* Make recognizer allow volatile MEMs again. */
1536 }
1538 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1540 static void
1542 {
1548 }
1549 \f
1550 /* Set up any promoted values for incoming argument registers. */
1552 static void
1554 {
1555 tree arg;
1560 {
1565 /* Only continue if the incoming argument is in a register. */
1569 /* Determine, if possible, whether all call sites of the current
1570 function lie within the current compilation unit. (This does
1571 take into account the exporting of a function via taking its
1572 address, and so forth.) */
1575 /* The mode and signedness of the argument before any promotions happen
1576 (equal to the mode of the pseudo holding it at that stage). */
1580 /* The mode and signedness of the argument after any source language and
1581 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1585 /* The mode and signedness of the argument as it is actually passed,
1586 see assign_parm_setup_reg in function.c. */
1590 /* The mode of the register in which the argument is being passed. */
1593 /* Eliminate sign extensions in the callee when:
1594 (a) A mode promotion has occurred; */
1597 /* (b) The mode of the register is the same as the mode of
1598 the argument as it is passed; */
1601 /* (c) There's no language level extension; */
1603 ;
1604 /* (c.1) All callers are from the current compilation unit. If that's
1605 the case we don't have to rely on an ABI, we only have to know
1606 what we're generating right now, and we know that we will do the
1607 mode1 to mode2 promotion with the given sign. */
1610 /* (c.2) The combination of the two promotions is useful. This is
1611 true when the signs match, or if the first promotion is unsigned.
1612 In the later case, (sign_extend (zero_extend x)) is the same as
1613 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1619 /* Record that the value was promoted from mode1 to mode3,
1620 so that any sign extension at the head of the current
1621 function may be eliminated. */
1625 }
1626 }
1628 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1629 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1630 because some machines (maybe most) will actually do the sign-extension and
1631 this is the conservative approach.
1633 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1634 kludge. */
1636 static rtx
1638 {
1639 scalar_int_mode int_mode;
1648 }
1650 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1651 and SET. */
1653 static void
1655 rtx x)
1656 {
1666 {
1670 }
1672 /* Don't call nonzero_bits if it cannot change anything. */
1674 {
1679 }
1681 /* Don't call num_sign_bit_copies if it cannot change anything. */
1683 {
1686 {
1690 }
1693 }
1694 }
1696 /* Called via note_stores. If X is a pseudo that is narrower than
1697 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1699 If we are setting only a portion of X and we can't figure out what
1700 portion, assume all bits will be used since we don't know what will
1701 be happening.
1703 Similarly, set how many bits of X are known to be copies of the sign bit
1704 at all locations in the function. This is the smallest number implied
1705 by any set of X. */
1707 static void
1709 {
1711 scalar_int_mode mode;
1715 /* If this register is undefined at the start of the file, we can't
1716 say what its contents were. */
1717 && ! REGNO_REG_SET_P
1721 {
1725 {
1729 }
1731 /* If this register is being initialized using itself, and the
1732 register is uninitialized in this basic block, and there are
1733 no LOG_LINKS which set the register, then part of the
1734 register is uninitialized. In that case we can't assume
1735 anything about the number of nonzero bits.
1737 ??? We could do better if we checked this in
1738 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1739 could avoid making assumptions about the insn which initially
1740 sets the register, while still using the information in other
1741 insns. We would have to be careful to check every insn
1742 involved in the combination. */
1748 {
1755 {
1759 }
1760 }
1762 /* If this is a complex assignment, see if we can convert it into a
1763 simple assignment. */
1766 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1767 set what we know about X. */
1773 else
1774 {
1777 }
1778 }
1779 }
1780 \f
1781 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1782 optionally insns that were previously combined into I3 or that will be
1783 combined into the merger of INSN and I3. The order is PRED, PRED2,
1784 INSN, SUCC, SUCC2, I3.
1786 Return 0 if the combination is not allowed for any reason.
1788 If the combination is allowed, *PDEST will be set to the single
1789 destination of INSN and *PSRC to the single source, and this function
1790 will return 1. */
1792 static int
1796 {
1801 rtx link;
1806 {
1808 {
1813 }
1818 }
1822 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1823 or a PARALLEL consisting of such a SET and CLOBBERs.
1825 If INSN has CLOBBER parallel parts, ignore them for our processing.
1826 By definition, these happen during the execution of the insn. When it
1827 is merged with another insn, all bets are off. If they are, in fact,
1828 needed and aren't also supplied in I3, they may be added by
1829 recog_for_combine. Otherwise, it won't match.
1831 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1832 note.
1834 Get the source and destination of INSN. If more than one, can't
1835 combine. */
1841 {
1843 {
1847 {
1848 /* This is important to combine floating point insns
1849 for the SH4 port. */
1851 /* Combining an isolated USE doesn't make sense.
1852 We depend here on combinable_i3pat to reject them. */
1853 /* The code below this loop only verifies that the inputs of
1854 the SET in INSN do not change. We call reg_set_between_p
1855 to verify that the REG in the USE does not change between
1856 I3 and INSN.
1857 If the USE in INSN was for a pseudo register, the matching
1858 insn pattern will likely match any register; combining this
1859 with any other USE would only be safe if we knew that the
1860 used registers have identical values, or if there was
1861 something to tell them apart, e.g. different modes. For
1862 now, we forgo such complicated tests and simply disallow
1863 combining of USES of pseudo registers with any other USE. */
1866 {
1871 do
1872 {
1882 }
1884 }
1887 /* We can ignore CLOBBERs. */
1892 /* Ignore SETs whose result isn't used but not those that
1893 have side-effects. */
1899 /* If we have already found a SET, this is a second one and
1900 so we cannot combine with this insn. */
1908 /* Anything else means we can't combine. */
1910 }
1911 }
1914 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1915 so don't do anything with it. */
1918 }
1919 else
1925 /* The simplification in expand_field_assignment may call back to
1926 get_last_value, so set safe guard here. */
1932 /* Do not eliminate user-specified register if it is in an
1933 asm input because we may break the register asm usage defined
1934 in GCC manual if allow to do so.
1935 Be aware that this may cover more cases than we expect but this
1936 should be harmless. */
1941 /* Don't eliminate a store in the stack pointer. */
1943 /* Don't combine with an insn that sets a register to itself if it has
1944 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1946 /* Can't merge an ASM_OPERANDS. */
1948 /* Can't merge a function call. */
1950 /* Don't eliminate a function call argument. */
1956 /* Don't substitute into an incremented register. */
1960 /* Don't substitute into a non-local goto, this confuses CFG. */
1962 /* Make sure that DEST is not used after INSN but before SUCC, or
1963 after SUCC and before SUCC2, or after SUCC2 but before I3. */
1964 || (!all_adjacent
1965 && ((succ2
1969 || (succ
1970 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
1971 that case SUCC is not in the insn stream, so use SUCC2
1972 instead for this test. */
1974 succ2
1977 /* Make sure that the value that is to be substituted for the register
1978 does not use any registers whose values alter in between. However,
1979 If the insns are adjacent, a use can't cross a set even though we
1980 think it might (this can happen for a sequence of insns each setting
1981 the same destination; last_set of that register might point to
1982 a NOTE). If INSN has a REG_EQUIV note, the register is always
1983 equivalent to the memory so the substitution is valid even if there
1984 are intervening stores. Also, don't move a volatile asm or
1985 UNSPEC_VOLATILE across any other insns. */
1986 || (! all_adjacent
1992 /* Don't combine across a CALL_INSN, because that would possibly
1993 change whether the life span of some REGs crosses calls or not,
1994 and it is a pain to update that information.
1995 Exception: if source is a constant, moving it later can't hurt.
1996 Accept that as a special case. */
2000 /* DEST must either be a REG or CC0. */
2002 {
2003 /* If register alignment is being enforced for multi-word items in all
2004 cases except for parameters, it is possible to have a register copy
2005 insn referencing a hard register that is not allowed to contain the
2006 mode being copied and which would not be valid as an operand of most
2007 insns. Eliminate this problem by not combining with such an insn.
2009 Also, on some machines we don't want to extend the life of a hard
2010 register. */
2015 /* Don't extend the life of a hard register unless it is
2016 user variable (if we have few registers) or it can't
2017 fit into the desired register (meaning something special
2018 is going on).
2019 Also avoid substituting a return register into I3, because
2020 reload can't handle a conflict with constraints of other
2021 inputs. */
2025 }
2033 {
2036 /* If the clobber represents an earlyclobber operand, we must not
2037 substitute an expression containing the clobbered register.
2038 As we do not analyze the constraint strings here, we have to
2039 make the conservative assumption. However, if the register is
2040 a fixed hard reg, the clobber cannot represent any operand;
2041 we leave it up to the machine description to either accept or
2042 reject use-and-clobber patterns. */
2048 }
2050 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2051 or not), reject, unless nothing volatile comes between it and I3 */
2054 {
2055 /* Make sure neither succ nor succ2 contains a volatile reference. */
2060 /* We'll check insns between INSN and I3 below. */
2061 }
2063 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2064 to be an explicit register variable, and was chosen for a reason. */
2070 /* If INSN contains volatile references (specifically volatile MEMs),
2071 we cannot combine across any other volatile references.
2072 Even if INSN doesn't contain volatile references, any intervening
2073 volatile insn might affect machine state. */
2076 ? volatile_refs_p
2083 /* If INSN contains an autoincrement or autodecrement, make sure that
2084 register is not used between there and I3, and not already used in
2085 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2086 Also insist that I3 not be a jump; if it were one
2087 and the incremented register were spilled, we would lose. */
2105 /* Don't combine an insn that follows a CC0-setting insn.
2106 An insn that uses CC0 must not be separated from the one that sets it.
2107 We do, however, allow I2 to follow a CC0-setting insn if that insn
2108 is passed as I1; in that case it will be deleted also.
2109 We also allow combining in this case if all the insns are adjacent
2110 because that would leave the two CC0 insns adjacent as well.
2111 It would be more logical to test whether CC0 occurs inside I1 or I2,
2112 but that would be much slower, and this ought to be equivalent. */
2115 {
2120 }
2122 /* If we get here, we have passed all the tests and the combination is
2123 to be allowed. */
2129 }
2130 \f
2131 /* LOC is the location within I3 that contains its pattern or the component
2132 of a PARALLEL of the pattern. We validate that it is valid for combining.
2134 One problem is if I3 modifies its output, as opposed to replacing it
2135 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2136 doing so would produce an insn that is not equivalent to the original insns.
2138 Consider:
2140 (set (reg:DI 101) (reg:DI 100))
2141 (set (subreg:SI (reg:DI 101) 0) <foo>)
2143 This is NOT equivalent to:
2145 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2146 (set (reg:DI 101) (reg:DI 100))])
2148 Not only does this modify 100 (in which case it might still be valid
2149 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2151 We can also run into a problem if I2 sets a register that I1
2152 uses and I1 gets directly substituted into I3 (not via I2). In that
2153 case, we would be getting the wrong value of I2DEST into I3, so we
2154 must reject the combination. This case occurs when I2 and I1 both
2155 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2156 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2157 of a SET must prevent combination from occurring. The same situation
2158 can occur for I0, in which case I0_NOT_IN_SRC is set.
2160 Before doing the above check, we first try to expand a field assignment
2161 into a set of logical operations.
2163 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2164 we place a register that is both set and used within I3. If more than one
2165 such register is detected, we fail.
2167 Return 1 if the combination is valid, zero otherwise. */
2169 static int
2172 {
2176 {
2181 rtx subdest;
2188 /* Check for the case where I3 modifies its output, as discussed
2189 above. We don't want to prevent pseudos from being combined
2190 into the address of a MEM, so only prevent the combination if
2191 i1 or i2 set the same MEM. */
2201 /* This is the same test done in can_combine_p except we can't test
2202 all_adjacent; we don't have to, since this instruction will stay
2203 in place, thus we are not considering increasing the lifetime of
2204 INNER_DEST.
2206 Also, if this insn sets a function argument, combining it with
2207 something that might need a spill could clobber a previous
2208 function argument; the all_adjacent test in can_combine_p also
2209 checks this; here, we do a more specific test for this case. */
2219 /* If DEST is used in I3, it is being killed in this insn, so
2220 record that for later. We have to consider paradoxical
2221 subregs here, since they kill the whole register, but we
2222 ignore partial subregs, STRICT_LOW_PART, etc.
2223 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2224 STACK_POINTER_REGNUM, since these are always considered to be
2225 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2233 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2239 {
2244 }
2245 }
2248 {
2255 }
2258 }
2259 \f
2260 /* Return 1 if X is an arithmetic expression that contains a multiplication
2261 and division. We don't count multiplications by powers of two here. */
2263 static int
2265 {
2267 {
2283 }
2284 }
2285 \f
2286 /* Determine whether INSN can be used in a combination. Return nonzero if
2287 not. This is used in try_combine to detect early some cases where we
2288 can't perform combinations. */
2290 static int
2292 {
2293 rtx set;
2296 /* If this isn't really an insn, we can't do anything.
2297 This can occur when flow deletes an insn that it has merged into an
2298 auto-increment address. */
2302 /* Never combine loads and stores involving hard regs that are likely
2303 to be spilled. The register allocator can usually handle such
2304 reg-reg moves by tying. If we allow the combiner to make
2305 substitutions of likely-spilled regs, reload might die.
2306 As an exception, we allow combinations involving fixed regs; these are
2307 not available to the register allocator so there's no risk involved. */
2328 }
2330 struct likely_spilled_retval_info
2331 {
2334 };
2336 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2337 hard registers that are known to be written to / clobbered in full. */
2338 static void
2340 {
2357 else
2360 }
2362 /* Return nonzero iff part of the return value is live during INSN, and
2363 it is likely spilled. This can happen when more than one insn is needed
2364 to copy the return value, e.g. when we consider to combine into the
2365 second copy insn for a complex value. */
2367 static int
2369 {
2371 rtx reg;
2374 /* We assume here that no machine mode needs more than
2375 32 hard registers when the value overlaps with a register
2376 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2391 /* Disregard parts of the return value that are set later. */
2400 /* Check if any of the (probably) live return value registers is
2401 likely spilled. */
2402 nregs --;
2403 do
2404 {
2410 }
2412 /* Adjust INSN after we made a change to its destination.
2414 Changing the destination can invalidate notes that say something about
2415 the results of the insn and a LOG_LINK pointing to the insn. */
2417 static void
2419 {
2420 /* For notes, be conservative and simply remove them. */
2423 /* The new insn will have a destination that was previously the destination
2424 of an insn just above it. Call distribute_links to make a LOG_LINK from
2425 the next use of that destination. */
2441 }
2443 /* Return TRUE if combine can reuse reg X in mode MODE.
2444 ADDED_SETS is nonzero if the original set is still required. */
2445 static bool
2447 {
2454 /* Allow hard registers if the new mode is legal, and occupies no more
2455 registers than the old mode. */
2460 /* Or a pseudo that is only used once. */
2463 && !added_sets
2465 }
2468 /* Check whether X, the destination of a set, refers to part of
2469 the register specified by REG. */
2471 static bool
2473 {
2474 /* Check that reg is an integer mode register. */
2485 }
2487 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2488 Note that the INSN should be deleted *after* removing dead edges, so
2489 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2490 but not for a (set (pc) (label_ref FOO)). */
2492 static void
2494 {
2502 {
2507 /* Remove barriers from the footer if there are any. */
2510 {
2513 else
2517 }
2520 }
2521 }
2523 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2524 by an arbitrary number of CLOBBERs. */
2525 static bool
2527 {
2546 }
2548 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2549 CLOBBERs), can be split into individual SETs in that order, without
2550 changing semantics. */
2551 static bool
2553 {
2561 {
2570 }
2573 }
2575 /* Try to combine the insns I0, I1 and I2 into I3.
2576 Here I0, I1 and I2 appear earlier than I3.
2577 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2578 I3.
2580 If we are combining more than two insns and the resulting insn is not
2581 recognized, try splitting it into two insns. If that happens, I2 and I3
2582 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2583 Otherwise, I0, I1 and I2 are pseudo-deleted.
2585 Return 0 if the combination does not work. Then nothing is changed.
2586 If we did the combination, return the insn at which combine should
2587 resume scanning.
2589 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2590 new direct jump instruction.
2592 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2593 been I3 passed to an earlier try_combine within the same basic
2594 block. */
2599 {
2600 /* New patterns for I3 and I2, respectively. */
2604 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2605 dead. */
2607 /* Total number of SETs to put into I3. */
2609 /* Nonzero if I2's or I1's body now appears in I3. */
2611 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2613 /* Contains I3 if the destination of I3 is used in its source, which means
2614 that the old life of I3 is being killed. If that usage is placed into
2615 I2 and not in I3, a REG_DEAD note must be made. */
2617 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2619 /* Copy of SET_SRC of I1 and I0, if needed. */
2621 /* Set if I2DEST was reused as a scratch register. */
2623 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2625 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2630 /* Notes that must be added to REG_NOTES in I3 and I2. */
2632 /* Notes that we substituted I3 into I2 instead of the normal case. */
2634 /* Notes that I1, I2 or I3 is a MULT operation. */
2641 rtx temp_expr;
2644 rtx new_other_notes;
2648 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2649 never be). */
2653 /* Only try four-insn combinations when there's high likelihood of
2654 success. Look for simple insns, such as loads of constants or
2655 binary operations involving a constant. */
2657 {
2667 {
2670 rtx src;
2675 {
2678 }
2680 ngood++;
2683 nshift++;
2684 }
2686 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2687 are likely manipulating its value. Ideally we'll be able to combine
2688 all four insns into a bitfield insertion of some kind.
2690 Note the source in I0 might be inside a sign/zero extension and the
2691 memory modes in I0 and I3 might be different. So extract the address
2692 from the destination of I3 and search for it in the source of I0.
2694 In the event that there's a match but the source/dest do not actually
2695 refer to the same memory, the worst that happens is we try some
2696 combinations that we wouldn't have otherwise. */
2698 /* Ensure the source of SET0 is a MEM, possibly buried inside
2699 an extension. */
2705 /* Ensure the destination of SET3 is a MEM. */
2707 /* Would it be better to extract the base address for the MEM
2708 in SET3 and look for that? I don't have cases where it matters
2709 but I could envision such cases. */
2715 }
2717 /* Exit early if one of the insns involved can't be used for
2718 combinations. */
2729 combine_attempts++;
2732 /* Reset the hard register usage information. */
2736 {
2743 else
2746 }
2748 /* If multiple insns feed into one of I2 or I3, they can be in any
2749 order. To simplify the code below, reorder them in sequence. */
2759 /* First check for one important special case that the code below will
2760 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2761 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2762 we may be able to replace that destination with the destination of I3.
2763 This occurs in the common code where we compute both a quotient and
2764 remainder into a structure, in which case we want to do the computation
2765 directly into the structure to avoid register-register copies.
2767 Note that this case handles both multiple sets in I2 and also cases
2768 where I2 has a number of CLOBBERs inside the PARALLEL.
2770 We make very conservative checks below and only try to handle the
2771 most common cases of this. For example, we only handle the case
2772 where I2 and I3 are adjacent to avoid making difficult register
2773 usage tests. */
2781 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2782 below would need to check what is inside (and reg_overlap_mentioned_p
2783 doesn't support those codes anyway). Don't allow those destinations;
2784 the resulting insn isn't likely to be recognized anyway. */
2790 {
2793 /* Make sure that the destination of I3,
2794 which we are going to substitute into one output of I2,
2795 is not used within another output of I2. We must avoid making this:
2796 (parallel [(set (mem (reg 69)) ...)
2797 (set (reg 69) ...)])
2798 which is not well-defined as to order of actions.
2799 (Besides, reload can't handle output reloads for this.)
2801 The problem can also happen if the dest of I3 is a memory ref,
2802 if another dest in I2 is an indirect memory ref.
2804 Neither can this PARALLEL be an asm. We do not allow combining
2805 that usually (see can_combine_p), so do not here either. */
2808 {
2817 }
2823 {
2824 combine_merges++;
2834 /* Replace the dest in I2 with our dest and make the resulting
2835 insn the new pattern for I3. Then skip to where we validate
2836 the pattern. Everything was set up above. */
2841 }
2842 }
2844 /* If I2 is setting a pseudo to a constant and I3 is setting some
2845 sub-part of it to another constant, merge them by making a new
2846 constant. */
2854 {
2861 {
2866 {
2872 }
2873 }
2874 else
2875 {
2879 {
2882 }
2883 }
2886 {
2887 /* If this is the low part, we're done. */
2889 ;
2890 /* Handle the case where inner is twice the size of outer. */
2894 /* Otherwise give up for now. */
2895 else
2897 }
2900 {
2908 combine_merges++;
2915 /* Replace the source in I2 with the new constant and make the
2916 resulting insn the new pattern for I3. Then skip to where we
2917 validate the pattern. Everything was set up above. */
2923 /* The dest of I3 has been replaced with the dest of I2. */
2926 }
2927 }
2929 /* If we have no I1 and I2 looks like:
2930 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2931 (set Y OP)])
2932 make up a dummy I1 that is
2933 (set Y OP)
2934 and change I2 to be
2935 (set (reg:CC X) (compare:CC Y (const_int 0)))
2937 (We can ignore any trailing CLOBBERs.)
2939 This undoes a previous combination and allows us to match a branch-and-
2940 decrement insn. */
2952 {
2953 /* We make I1 with the same INSN_UID as I2. This gives it
2954 the same DF_INSN_LUID for value tracking. Our fake I1 will
2955 never appear in the insn stream so giving it the same INSN_UID
2956 as I2 will not cause a problem. */
2969 }
2971 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2972 make those two SETs separate I1 and I2 insns, and make an I0 that is
2973 the original I1. */
2979 {
2980 /* If there is no I1, there is no I0 either. */
2983 /* We make I1 with the same INSN_UID as I2. This gives it
2984 the same DF_INSN_LUID for value tracking. Our fake I1 will
2985 never appear in the insn stream so giving it the same INSN_UID
2986 as I2 will not cause a problem. */
2994 }
2996 /* Verify that I2 and I1 are valid for combining. */
3002 {
3005 }
3007 /* Record whether I2DEST is used in I2SRC and similarly for the other
3008 cases. Knowing this will help in register status updating below. */
3019 /* For the earlier insns, determine which of the subsequent ones they
3020 feed. */
3027 /* Ensure that I3's pattern can be the destination of combines. */
3033 {
3036 }
3038 /* See if any of the insns is a MULT operation. Unless one is, we will
3039 reject a combination that is, since it must be slower. Be conservative
3040 here. */
3048 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3049 We used to do this EXCEPT in one case: I3 has a post-inc in an
3050 output operand. However, that exception can give rise to insns like
3051 mov r3,(r3)+
3052 which is a famous insn on the PDP-11 where the value of r3 used as the
3053 source was model-dependent. Avoid this sort of thing. */
3055 #if 0
3061 /* It's not the exception. */
3062 #endif
3064 {
3065 rtx link;
3071 {
3074 }
3075 }
3077 /* See if the SETs in I1 or I2 need to be kept around in the merged
3078 instruction: whenever the value set there is still needed past I3.
3079 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3081 For the SET in I1, we have two cases: if I1 and I2 independently feed
3082 into I3, the set in I1 needs to be kept around unless I1DEST dies
3083 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3084 in I1 needs to be kept around unless I1DEST dies or is set in either
3085 I2 or I3. The same considerations apply to I0. */
3092 else
3100 else
3103 /* We are about to copy insns for the case where they need to be kept
3104 around. Check that they can be copied in the merged instruction. */
3110 {
3113 }
3115 /* If the set in I2 needs to be kept around, we must make a copy of
3116 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3117 PATTERN (I2), we are only substituting for the original I1DEST, not into
3118 an already-substituted copy. This also prevents making self-referential
3119 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3120 I2DEST. */
3123 {
3126 else
3128 }
3131 {
3134 else
3136 }
3139 {
3142 else
3144 }
3146 combine_merges++;
3148 /* Substitute in the latest insn for the regs set by the earlier ones. */
3154 /* Many machines that don't use CC0 have insns that can both perform an
3155 arithmetic operation and set the condition code. These operations will
3156 be represented as a PARALLEL with the first element of the vector
3157 being a COMPARE of an arithmetic operation with the constant zero.
3158 The second element of the vector will set some pseudo to the result
3159 of the same arithmetic operation. If we simplify the COMPARE, we won't
3160 match such a pattern and so will generate an extra insn. Here we test
3161 for this case, where both the comparison and the operation result are
3162 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3163 I2SRC. Later we will make the PARALLEL that contains I2. */
3169 {
3170 rtx newpat_dest;
3176 scalar_int_mode mode;
3185 {
3191 }
3193 /* Do the rest only if op1 is const0_rtx, which may be the
3194 result of simplification. */
3196 {
3197 /* If a single use of the CC is found, prepare to modify it
3198 when SELECT_CC_MODE returns a new CC-class mode, or when
3199 the above simplify_compare_const() returned a new comparison
3200 operator. undobuf.other_insn is assigned the CC use insn
3201 when modifying it. */
3203 {
3204 #ifdef SELECT_CC_MODE
3205 machine_mode new_mode
3210 {
3215 else
3216 {
3219 }
3220 }
3221 #endif
3222 /* Cases for modifying the CC-using comparison. */
3224 /* ??? Do we need to verify the zero rtx? */
3226 {
3227 /* Replace cc_use_loc with entire new RTX. */
3232 }
3234 {
3235 /* Just replace the CC reg with a new mode. */
3238 }
3239 }
3241 /* Now we modify the current newpat:
3242 First, SET_DEST(newpat) is updated if the CC mode has been
3243 altered. For targets without SELECT_CC_MODE, this should be
3244 optimized away. */
3247 /* This is always done to propagate i2src into newpat. */
3250 /* Create new version of i2pat if needed; the below PARALLEL
3251 creation needs this to work correctly. */
3255 }
3256 }
3259 {
3260 /* It is possible that the source of I2 or I1 may be performing
3261 an unneeded operation, such as a ZERO_EXTEND of something
3262 that is known to have the high part zero. Handle that case
3263 by letting subst look at the inner insns.
3265 Another way to do this would be to have a function that tries
3266 to simplify a single insn instead of merging two or more
3267 insns. We don't do this because of the potential of infinite
3268 loops and because of the potential extra memory required.
3269 However, doing it the way we are is a bit of a kludge and
3270 doesn't catch all cases.
3272 But only do this if -fexpensive-optimizations since it slows
3273 things down and doesn't usually win.
3275 This is not done in the COMPARE case above because the
3276 unmodified I2PAT is used in the PARALLEL and so a pattern
3277 with a modified I2SRC would not match. */
3280 {
3281 /* Pass pc_rtx so no substitutions are done, just
3282 simplifications. */
3284 {
3287 }
3291 }
3296 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3297 copy of I2SRC each time we substitute it, in order to avoid creating
3298 self-referential RTL when we will be substituting I1SRC for I1DEST
3299 later. Likewise if I0 feeds into I2, either directly or indirectly
3300 through I1, and I0DEST is in I0SRC. */
3307 /* Record whether I2's body now appears within I3's body. */
3309 }
3311 /* If we already got a failure, don't try to do more. Otherwise, try to
3312 substitute I1 if we have it. */
3315 {
3316 /* Check that an autoincrement side-effect on I1 has not been lost.
3317 This happens if I1DEST is mentioned in I2 and dies there, and
3318 has disappeared from the new pattern. */
3320 && i1_feeds_i2_n
3323 /* Before we can do this substitution, we must redo the test done
3324 above (see detailed comments there) that ensures I1DEST isn't
3325 mentioned in any SETs in NEWPAT that are field assignments. */
3328 {
3331 }
3336 /* If the following substitution will modify I1SRC, make a copy of it
3337 for the case where it is substituted for I1DEST in I2PAT later. */
3341 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3342 copy of I1SRC each time we substitute it, in order to avoid creating
3343 self-referential RTL when we will be substituting I0SRC for I0DEST
3344 later. */
3349 /* Record whether I1's body now appears within I3's body. */
3351 }
3353 /* Likewise for I0 if we have it. */
3356 {
3363 {
3366 }
3368 /* If the following substitution will modify I0SRC, make a copy of it
3369 for the case where it is substituted for I0DEST in I1PAT later. */
3372 /* And a copy for I0DEST in I2PAT substitution. */
3381 }
3383 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3384 to count all the ways that I2SRC and I1SRC can be used. */
3395 /* Fail if we tried to make a new register. */
3397 /* Fail if we couldn't do something and have a CLOBBER. */
3399 /* Fail if this new pattern is a MULT and we didn't have one before
3400 at the outer level. */
3403 {
3406 }
3408 /* If the actions of the earlier insns must be kept
3409 in addition to substituting them into the latest one,
3410 we must make a new PARALLEL for the latest insn
3411 to hold additional the SETs. */
3414 {
3416 combine_extras++;
3419 {
3425 }
3426 else
3427 {
3432 }
3438 {
3444 }
3446 {
3455 }
3456 }
3458 validate_replacement:
3460 /* Note which hard regs this insn has as inputs. */
3463 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3464 consider splitting this pattern, we might need these clobbers. */
3467 {
3473 }
3475 /* We have recognized nothing yet. */
3478 /* See if this is a PARALLEL of two SETs where one SET's destination is
3479 a register that is unused and this isn't marked as an instruction that
3480 might trap in an EH region. In that case, we just need the other SET.
3481 We prefer this over the PARALLEL.
3483 This can occur when simplifying a divmod insn. We *must* test for this
3484 case here because the code below that splits two independent SETs doesn't
3485 handle this case correctly when it updates the register status.
3487 It's pointless doing this if we originally had two sets, one from
3488 i3, and one from i2. Combining then splitting the parallel results
3489 in the original i2 again plus an invalid insn (which we delete).
3490 The net effect is only to move instructions around, which makes
3491 debug info less accurate.
3493 If the remaining SET came from I2 its destination should not be used
3494 between I2 and I3. See PR82024. */
3499 {
3510 {
3513 }
3522 {
3527 {
3533 }
3534 }
3538 }
3540 /* Is the result of combination a valid instruction? */
3544 /* If we were combining three insns and the result is a simple SET
3545 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3546 insns. There are two ways to do this. It can be split using a
3547 machine-specific method (like when you have an addition of a large
3548 constant) or by combine in the function find_split_point. */
3552 {
3556 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3557 use I2DEST as a scratch register will help. In the latter case,
3558 convert I2DEST to the mode of the source of NEWPAT if we can. */
3562 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3563 inputs of NEWPAT. */
3565 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3566 possible to try that as a scratch reg. This would require adding
3567 more code to make it work though. */
3570 {
3573 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3574 (temporarily, until we are committed to this instruction
3575 combination) does not work: for example, any call to nonzero_bits
3576 on the register (from a splitter in the MD file, for example)
3577 will get the old information, which is invalid.
3579 Since nowadays we can create registers during combine just fine,
3580 we should just create a new one here, not reuse i2dest. */
3582 /* First try to split using the original register as a
3583 scratch register. */
3587 i2dest)));
3590 /* If that didn't work, try changing the mode of I2DEST if
3591 we can. */
3596 {
3598 rtx ni2dest;
3602 else
3603 {
3606 }
3608 parallel = (gen_rtx_PARALLEL
3612 ni2dest))));
3617 {
3625 }
3626 }
3629 }
3631 /* If recog_for_combine has discarded clobbers, try to use them
3632 again for the split. */
3634 {
3637 }
3640 {
3645 }
3649 {
3659 /* If I2 or I3 has multiple SETs, we won't know how to track
3660 register status, so don't use these insns. If I2's destination
3661 is used between I2 and I3, we also can't use these insns. */
3671 /* It is possible that both insns now set the destination of I3.
3672 If so, we must show an extra use of it. */
3675 {
3694 }
3695 }
3697 /* If we can split it and use I2DEST, go ahead and see if that
3698 helps things be recognized. Verify that none of the registers
3699 are set between I2 and I3. */
3703 /* We need I2DEST in the proper mode. If it is a hard register
3704 or the only use of a pseudo, we can change its mode.
3705 Make sure we don't change a hard register to have a mode that
3706 isn't valid for it, or change the number of registers. */
3713 /* We can't overwrite I2DEST if its value is still used by
3714 NEWPAT. */
3716 {
3725 /* *SPLIT may be part of I2SRC, so make sure we have the
3726 original expression around for later debug processing.
3727 We should not need I2SRC any more in other cases. */
3730 else
3733 /* Get NEWDEST as a register in the proper mode. We have already
3734 validated that we can do this. */
3736 {
3739 else
3740 {
3743 }
3744 }
3746 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3747 an ASHIFT. This can occur if it was inside a PLUS and hence
3748 appeared to be a memory address. This is a kludge. */
3753 {
3756 /* Update split_code because we may not have a multiply
3757 anymore. */
3759 }
3761 /* Similarly for (plus (mult FOO (const_int pow2))). */
3767 {
3771 /* Update split_code because we may not have a multiply
3772 anymore. */
3774 }
3776 #ifdef INSN_SCHEDULING
3777 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3778 be written as a ZERO_EXTEND. */
3780 {
3781 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3782 what it really is. */
3787 else
3790 }
3791 #endif
3793 /* Attempt to split binary operators using arithmetic identities. */
3797 {
3804 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3806 {
3811 }
3812 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3819 {
3825 /* Split both "((X op Y) op X) op Y" and
3826 "((X op Y) op Y) op X" as "T op T" where T is
3827 "X op Y". */
3830 {
3835 }
3836 /* Split "((X op X) op Y) op Y)" as "T op T" where
3837 T is "X op Y". */
3839 {
3845 }
3846 }
3847 }
3850 {
3853 }
3857 /* recog_for_combine might have added CLOBBERs to newi2pat.
3858 Make sure NEWPAT does not depend on the clobbered regs. */
3862 {
3865 {
3868 }
3869 }
3871 /* If the split point was a MULT and we didn't have one before,
3872 don't use one now. */
3875 }
3876 }
3878 /* Check for a case where we loaded from memory in a narrow mode and
3879 then sign extended it, but we need both registers. In that case,
3880 we have a PARALLEL with both loads from the same memory location.
3881 We can split this into a load from memory followed by a register-register
3882 copy. This saves at least one insn, more if register allocation can
3883 eliminate the copy.
3885 We cannot do this if the destination of the first assignment is a
3886 condition code register or cc0. We eliminate this case by making sure
3887 the SET_DEST and SET_SRC have the same mode.
3889 We cannot do this if the destination of the second assignment is
3890 a register that we have already assumed is zero-extended. Similarly
3891 for a SUBREG of such a register. */
3926 {
3927 rtx ni2dest;
3941 }
3943 /* Similarly, check for a case where we have a PARALLEL of two independent
3944 SETs but we started with three insns. In this case, we can do the sets
3945 as two separate insns. This case occurs when some SET allows two
3946 other insns to combine, but the destination of that SET is still live.
3948 Also do this if we started with two insns and (at least) one of the
3949 resulting sets is a noop; this noop will be deleted later. */
3968 {
3972 /* Normally, it doesn't matter which of the two is done first,
3973 but the one that references cc0 can't be the second, and
3974 one which uses any regs/memory set in between i2 and i3 can't
3975 be first. The PARALLEL might also have been pre-existing in i3,
3976 so we need to make sure that we won't wrongly hoist a SET to i2
3977 that would conflict with a death note present in there. */
3985 /* If I3 is a jump, ensure that set0 is a jump so that
3986 we do not create invalid RTL. */
3988 )
3989 {
3992 }
4000 /* If I3 is a jump, ensure that set1 is a jump so that
4001 we do not create invalid RTL. */
4003 )
4004 {
4007 }
4008 else
4009 {
4012 }
4017 {
4018 /* recog_for_combine might have added CLOBBERs to newi2pat.
4019 Make sure NEWPAT does not depend on the clobbered regs. */
4021 {
4024 {
4027 {
4030 }
4031 }
4032 }
4035 }
4036 }
4038 /* If it still isn't recognized, fail and change things back the way they
4039 were. */
4041 /* Is the result a reasonable ASM_OPERANDS? */
4043 {
4046 }
4048 /* If we had to change another insn, make sure it is valid also. */
4050 {
4058 {
4061 }
4062 }
4064 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4065 they are adjacent to each other or not. */
4067 {
4071 {
4074 }
4075 }
4077 /* Only allow this combination if insn_rtx_costs reports that the
4078 replacement instructions are cheaper than the originals. */
4080 {
4083 }
4086 {
4091 {
4096 /* Temporarily revert mode back. */
4100 {
4101 /* If we used i2dest as a scratch register with a
4102 different mode, substitute it for the original
4103 i2src while its original mode is temporarily
4104 restored, and then clear i2scratch so that we don't
4105 do it again later. */
4107 this_basic_block);
4109 /* Put back the new mode. */
4111 }
4112 else
4113 {
4118 {
4121 }
4122 else
4123 {
4130 }
4132 /* We're dealing with a reg that changed mode but not
4133 meaning, so we want to turn it into a subreg for
4134 the new mode. However, because of REG sharing and
4135 because its mode had already changed, we have to do
4136 it in two steps. First, replace any debug uses of
4137 reg, with its original mode temporarily restored,
4138 with this copy we have created; then, replace the
4139 copy with the SUBREG of the original shared reg,
4140 once again changed to the new mode. */
4142 this_basic_block);
4146 this_basic_block);
4147 }
4148 }
4149 }
4151 /* If we will be able to accept this, we have made a
4152 change to the destination of I3. This requires us to
4153 do a few adjustments. */
4156 {
4159 }
4161 /* We now know that we can do this combination. Merge the insns and
4162 update the status of registers and LOG_LINKS. */
4165 {
4170 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4171 ensure that they are still valid. Then add any non-duplicate
4172 notes added by recog_for_combine. */
4174 {
4183 /* Simply drop equal note since it may be no longer valid
4184 for other_insn. It may be possible to record that CC
4185 register is changed and only discard those notes, but
4186 in practice it's unnecessary complication and doesn't
4187 give any meaningful improvement.
4189 See PR78559. */
4193 }
4197 NULL_RTX);
4198 }
4201 {
4204 rtx ni2dest;
4206 /* I3 now uses what used to be its destination and which is now
4207 I2's destination. This requires us to do a few adjustments. */
4211 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4212 so we still will.
4214 However, some later insn might be using I2's dest and have
4215 a LOG_LINK pointing at I3. We must remove this link.
4216 The simplest way to remove the link is to point it at I1,
4217 which we know will be a NOTE. */
4219 /* newi2pat is usually a SET here; however, recog_for_combine might
4220 have added some clobbers. */
4223 else
4230 {
4233 {
4239 }
4240 }
4241 }
4243 {
4248 /* Compute which registers we expect to eliminate. newi2pat may be setting
4249 either i3dest or i2dest, so we must check it. */
4252 || !i2dest_killed
4254 /* For i1, we need to compute both local elimination and global
4255 elimination information with respect to newi2pat because i1dest
4256 may be the same as i3dest, in which case newi2pat may be setting
4257 i1dest. Global information is used when distributing REG_DEAD
4258 note for i2 and i3, in which case it does matter if newi2pat sets
4259 i1dest or not.
4261 Local information is used when distributing REG_DEAD note for i1,
4262 in which case it doesn't matter if newi2pat sets i1dest or not.
4263 See PR62151, if we have four insns combination:
4264 i0: r0 <- i0src
4265 i1: r1 <- i1src (using r0)
4266 REG_DEAD (r0)
4267 i2: r0 <- i2src (using r1)
4268 i3: r3 <- i3src (using r0)
4269 ix: using r0
4270 From i1's point of view, r0 is eliminated, no matter if it is set
4271 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4272 should be discarded.
4274 Note local information only affects cases in forms like "I1->I2->I3",
4275 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4276 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4277 i0dest anyway. */
4279 || !i1dest_killed
4284 /* Same case as i1. */
4291 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4292 clear them. */
4300 /* Ensure that we do not have something that should not be shared but
4301 occurs multiple times in the new insns. Check this by first
4302 resetting all the `used' flags and then copying anything is shared. */
4326 {
4329 {
4331 {
4332 /* I2SRC must still be meaningful at this point. Some
4333 splitting operations can invalidate I2SRC, but those
4334 operations do not apply to calls. */
4338 }
4345 }
4346 }
4351 /* We had one special case above where I2 had more than one set and
4352 we replaced a destination of one of those sets with the destination
4353 of I3. In that case, we have to update LOG_LINKS of insns later
4354 in this basic block. Note that this (expensive) case is rare.
4356 Also, in this case, we must pretend that all REG_NOTEs for I2
4357 actually came from I3, so that REG_UNUSED notes from I2 will be
4358 properly handled. */
4361 {
4370 temp_insn
4380 {
4385 }
4386 else
4389 }
4397 {
4400 this_basic_block);
4403 }
4404 else
4405 {
4408 this_basic_block);
4410 }
4413 {
4418 this_basic_block);
4420 }
4423 {
4428 this_basic_block);
4430 }
4432 /* Get death notes for everything that is now used in either I3 or
4433 I2 and used to die in a previous insn. If we built two new
4434 patterns, move from I1 to I2 then I2 to I3 so that we get the
4435 proper movement on registers that I2 modifies. */
4441 else
4447 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4464 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4465 know these are REG_UNUSED and want them to go to the desired insn,
4466 so we always pass it as i3. */
4470 NULL_RTX);
4474 NULL_RTX);
4476 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4477 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4478 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4479 in that case, it might delete I2. Similarly for I2 and I1.
4480 Show an additional death due to the REG_DEAD note we make here. If
4481 we discard it in distribute_notes, we will decrement it again. */
4484 {
4489 else
4492 }
4495 {
4500 else
4503 }
4506 {
4511 else
4514 }
4517 {
4522 else
4525 }
4533 {
4538 /* The insn that used to set this register doesn't exist, and
4539 this life of the register may not exist either. See if one of
4540 I3's links points to an insn that sets I2DEST. If it does,
4541 that is now the last known value for I2DEST. If we don't update
4542 this and I2 set the register to a value that depended on its old
4543 contents, we will get confused. If this insn is used, thing
4544 will be set correctly in combine_instructions. */
4552 /* If the reg formerly set in I2 died only once and that was in I3,
4553 zero its use count so it won't make `reload' do any work. */
4556 && ! i2dest_in_i2src
4559 }
4562 {
4575 && ! i1dest_in_i1src
4578 }
4581 {
4594 && ! i0dest_in_i0src
4597 }
4599 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4600 been made to this insn. The order is important, because newi2pat
4601 can affect nonzero_bits of newpat. */
4605 }
4608 {
4610 {
4613 }
4615 }
4618 {
4620 {
4623 }
4625 }
4628 {
4630 {
4633 }
4635 }
4638 {
4640 {
4643 }
4645 }
4648 {
4650 {
4653 }
4655 }
4657 /* Set new_direct_jump_p if a new return or simple jump instruction
4658 has been created. Adjust the CFG accordingly. */
4660 {
4664 }
4669 {
4672 }
4676 {
4682 }
4687 {
4693 }
4695 /* A noop might also need cleaning up of CFG, if it comes from the
4696 simplification of a jump. */
4701 {
4704 }
4711 {
4714 }
4716 combine_successes++;
4723 else
4725 }
4726 \f
4727 /* Get a marker for undoing to the current state. */
4731 {
4733 }
4735 /* Undo the modifications up to the marker. */
4737 static void
4739 {
4743 {
4748 {
4763 }
4767 }
4770 }
4772 /* Undo all the modifications recorded in undobuf. */
4774 static void
4776 {
4778 }
4780 /* We've committed to accepting the changes we made. Move all
4781 of the undos to the free list. */
4783 static void
4785 {
4789 {
4793 }
4795 }
4796 \f
4797 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4798 where we have an arithmetic expression and return that point. LOC will
4799 be inside INSN.
4801 try_combine will call this function to see if an insn can be split into
4802 two insns. */
4806 {
4816 /* First special-case some codes. */
4818 {
4820 #ifdef INSN_SCHEDULING
4821 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4822 point. */
4825 #endif
4829 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4830 using LO_SUM and HIGH. */
4833 {
4841 }
4843 /* If we have a PLUS whose second operand is a constant and the
4844 address is not valid, perhaps will can split it up using
4845 the machine-specific way to split large constants. We use
4846 the first pseudo-reg (one of the virtual regs) as a placeholder;
4847 it will not remain in the result. */
4852 {
4855 subst_insn);
4857 /* This should have produced two insns, each of which sets our
4858 placeholder. If the source of the second is a valid address,
4859 we can make put both sources together and make a split point
4860 in the middle. */
4873 && memory_address_addr_space_p
4876 {
4880 /* Replace the placeholder in SRC2 with SRC1. If we can
4881 find where in SRC2 it was placed, that can become our
4882 split point and we can replace this address with SRC2.
4883 Just try two obvious places. */
4894 {
4897 }
4898 }
4900 /* If that didn't work, perhaps the first operand is complex and
4901 needs to be computed separately, so make a split point there.
4902 This will occur on machines that just support REG + CONST
4903 and have a constant moved through some previous computation. */
4909 }
4911 /* If we have a PLUS whose first operand is complex, try computing it
4912 separately by making a split there. */
4923 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4924 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4925 we need to put the operand into a register. So split at that
4926 point. */
4936 /* See if we can split SET_SRC as it stands. */
4941 /* See if we can split SET_DEST as it stands. */
4946 /* See if this is a bitfield assignment with everything constant. If
4947 so, this is an IOR of an AND, so split it into that. */
4959 {
4964 unsigned HOST_WIDE_INT mask
4966 rtx or_mask;
4975 else
4976 {
4982 or_mask));
4983 }
4990 }
4992 /* Otherwise, see if this is an operation that we can split into two.
4993 If so, try to split that. */
4997 {
4999 /* If we are AND'ing with a large constant that is only a single
5000 bit and the result is only being used in a context where we
5001 need to know if it is zero or nonzero, replace it with a bit
5002 extraction. This will avoid the large constant, which might
5003 have taken more than one insn to make. If the constant were
5004 not a valid argument to the AND but took only one insn to make,
5005 this is no worse, but if it took more than one insn, it will
5006 be better. */
5016 {
5021 {
5024 }
5025 }
5029 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5030 is known to be on, this can be converted into a NEG of a shift. */
5036 {
5048 }
5054 /* We can't optimize if either mode is a partial integer
5055 mode as we don't know how many bits are significant
5056 in those modes. */
5072 {
5080 }
5085 }
5090 {
5091 /* For unsigned, we have a choice of a shift followed by an
5092 AND or two shifts. Use two shifts for field sizes where the
5093 constant might be too large. We assume here that we can
5094 always at least get 8-bit constants in an AND insn, which is
5095 true for every current RISC. */
5098 {
5099 unsigned HOST_WIDE_INT mask
5103 gen_rtx_LSHIFTRT
5111 }
5112 else
5113 {
5115 gen_rtx_fmt_ee
5126 }
5127 }
5129 /* See if this is a simple operation with a constant as the second
5130 operand. It might be that this constant is out of range and hence
5131 could be used as a split point. */
5139 /* Finally, see if this is a simple operation with its first operand
5140 not in a register. The operation might require this operand in a
5141 register, so return it as a split point. We can always do this
5142 because if the first operand were another operation, we would have
5143 already found it as a split point. */
5152 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5153 it is better to write this as (not (ior A B)) so we can split it.
5154 Similarly for IOR. */
5156 {
5164 }
5166 /* Many RISC machines have a large set of logical insns. If the
5167 second operand is a NOT, put it first so we will try to split the
5168 other operand first. */
5170 {
5174 }
5179 /* Canonicalization can produce (minus A (mult B C)), where C is a
5180 constant. It may be better to try splitting (plus (mult B -C) A)
5181 instead if this isn't a multiply by a power of two. */
5185 {
5193 mode)),
5196 }
5198 /* Split at a multiply-accumulate instruction. However if this is
5199 the SET_SRC, we likely do not have such an instruction and it's
5200 worthless to try this split. */
5209 }
5211 /* Otherwise, select our actions depending on our rtx class. */
5213 {
5219 /* fall through */
5227 /* fall through */
5229 /* Some machines have (and (shift ...) ...) insns. If X is not
5230 an AND, but XEXP (X, 0) is, use it as our split point. */
5240 /* Otherwise, we don't have a split point. */
5242 }
5243 }
5244 \f
5245 /* Throughout X, replace FROM with TO, and return the result.
5246 The result is TO if X is FROM;
5247 otherwise the result is X, but its contents may have been modified.
5248 If they were modified, a record was made in undobuf so that
5249 undo_all will (among other things) return X to its original state.
5251 If the number of changes necessary is too much to record to undo,
5252 the excess changes are not made, so the result is invalid.
5253 The changes already made can still be undone.
5254 undobuf.num_undo is incremented for such changes, so by testing that
5255 the caller can tell whether the result is valid.
5257 `n_occurrences' is incremented each time FROM is replaced.
5259 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5261 IN_COND is nonzero if we are at the top level of a condition.
5263 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5264 by copying if `n_occurrences' is nonzero. */
5266 static rtx
5268 {
5273 rtx new_rtx;
5275 /* Two expressions are equal if they are identical copies of a shared
5276 RTX or if they are both registers with the same register number
5277 and mode. */
5279 #define COMBINE_RTX_EQUAL_P(X,Y) \
5280 ((X) == (Y) \
5281 || (REG_P (X) && REG_P (Y) \
5282 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5284 /* Do not substitute into clobbers of regs -- this will never result in
5285 valid RTL. */
5290 {
5291 n_occurrences++;
5293 }
5295 /* If X and FROM are the same register but different modes, they
5296 will not have been seen as equal above. However, the log links code
5297 will make a LOG_LINKS entry for that case. If we do nothing, we
5298 will try to rerecognize our original insn and, when it succeeds,
5299 we will delete the feeding insn, which is incorrect.
5301 So force this insn not to match in this (rare) case. */
5306 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5307 of which may contain things that can be combined. */
5311 /* It is possible to have a subexpression appear twice in the insn.
5312 Suppose that FROM is a register that appears within TO.
5313 Then, after that subexpression has been scanned once by `subst',
5314 the second time it is scanned, TO may be found. If we were
5315 to scan TO here, we would find FROM within it and create a
5316 self-referent rtl structure which is completely wrong. */
5320 /* Parallel asm_operands need special attention because all of the
5321 inputs are shared across the arms. Furthermore, unsharing the
5322 rtl results in recognition failures. Failure to handle this case
5323 specially can result in circular rtl.
5325 Solve this by doing a normal pass across the first entry of the
5326 parallel, and only processing the SET_DESTs of the subsequent
5327 entries. Ug. */
5332 {
5335 /* If this substitution failed, this whole thing fails. */
5343 {
5349 {
5352 /* If this substitution failed, this whole thing fails. */
5358 }
5359 }
5360 }
5361 else
5362 {
5366 /* We don't need to process a SET_DEST that is a register, CC0,
5367 or PC, so set up to skip this common case. All other cases
5368 where we want to suppress replacing something inside a
5369 SET_SRC are handled via the IN_DEST operand. */
5376 /* Trying to simplify the operands of a widening MULT is not likely
5377 to create RTL matching a machine insn. */
5389 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5390 constant. */
5395 {
5397 {
5400 {
5402 {
5405 n_occurrences++;
5406 }
5407 else
5408 {
5410 unique_copy);
5412 /* If this substitution failed, this whole thing
5413 fails. */
5417 }
5420 }
5421 }
5423 {
5424 /* If this is a register being set, ignore it. */
5431 ;
5434 {
5435 /* In general, don't install a subreg involving two
5436 modes not tieable. It can worsen register
5437 allocation, and can even make invalid reload
5438 insns, since the reg inside may need to be copied
5439 from in the outside mode, and that may be invalid
5440 if it is an fp reg copied in integer mode.
5442 We allow two exceptions to this: It is valid if
5443 it is inside another SUBREG and the mode of that
5444 SUBREG and the mode of the inside of TO is
5445 tieable and it is valid if X is a SET that copies
5446 FROM to CC0. */
5454 && (!HAVE_cc0
5469 n_occurrences++;
5470 }
5471 else
5472 /* If we are in a SET_DEST, suppress most cases unless we
5473 have gone inside a MEM, in which case we want to
5474 simplify the address. We assume here that things that
5475 are actually part of the destination have their inner
5476 parts in the first expression. This is true for SUBREG,
5477 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5478 things aside from REG and MEM that should appear in a
5479 SET_DEST. */
5481 (((in_dest
5487 unique_copy);
5489 /* If we found that we will have to reject this combination,
5490 indicate that by returning the CLOBBER ourselves, rather than
5491 an expression containing it. This will speed things up as
5492 well as prevent accidents where two CLOBBERs are considered
5493 to be equal, thus producing an incorrect simplification. */
5499 {
5507 }
5510 {
5514 }
5515 else
5517 }
5518 }
5519 }
5521 /* Check if we are loading something from the constant pool via float
5522 extension; in this case we would undo compress_float_constant
5523 optimization and degenerate constant load to an immediate value. */
5527 {
5531 }
5533 /* Try to simplify X. If the simplification changed the code, it is likely
5534 that further simplification will help, so loop, but limit the number
5535 of repetitions that will be performed. */
5538 {
5539 /* If X is sufficiently simple, don't bother trying to do anything
5540 with it. */
5549 /* We no longer know the original mode of operand 0 since we
5550 have changed the form of X) */
5552 }
5555 }
5556 \f
5557 /* If X is a commutative operation whose operands are not in the canonical
5558 order, use substitutions to swap them. */
5560 static void
5562 {
5565 {
5569 }
5570 }
5572 /* Simplify X, a piece of RTL. We just operate on the expression at the
5573 outer level; call `subst' to simplify recursively. Return the new
5574 expression.
5576 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5577 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5578 of a condition. */
5580 static rtx
5583 {
5586 scalar_int_mode int_mode;
5587 rtx temp;
5590 /* If this is a commutative operation, put a constant last and a complex
5591 expression first. We don't need to do this for comparisons here. */
5594 /* Try to fold this expression in case we have constants that weren't
5595 present before. */
5598 {
5606 {
5609 {
5613 }
5616 }
5629 }
5632 {
5637 }
5639 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5640 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5641 things. Check for cases where both arms are testing the same
5642 condition.
5644 Don't do anything if all operands are very simple. */
5657 {
5662 /* If everything is a comparison, what we have is highly unlikely
5663 to be simpler, so don't use it. */
5666 {
5673 /* Simplify the alternative arms; this may collapse the true and
5674 false arms to store-flag values. Be careful to use copy_rtx
5675 here since true_rtx or false_rtx might share RTL with x as a
5676 result of the if_then_else_cond call above. */
5680 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5681 is unlikely to be simpler. */
5684 {
5687 /* Restarting if we generate a store-flag expression will cause
5688 us to loop. Just drop through in this case. */
5690 /* If the result values are STORE_FLAG_VALUE and zero, we can
5691 just make the comparison operation. */
5702 /* Likewise, we can make the negate of a comparison operation
5703 if the result values are - STORE_FLAG_VALUE and zero. */
5711 mode);
5722 mode);
5723 else
5726 mode,
5727 VOIDmode,
5728 cond,
5729 cop1),
5734 }
5735 }
5736 }
5738 /* First see if we can apply the inverse distributive law. */
5741 {
5745 }
5747 /* If CODE is an associative operation not otherwise handled, see if we
5748 can associate some operands. This can win if they are constants or
5749 if they are logically related (i.e. (a & b) & a). */
5755 {
5757 {
5761 rtx inner;
5763 /* Make sure we pass the constant operand if any as the second
5764 one if this is a commutative operation. */
5772 /* For commutative operations, try the other pair if that one
5773 didn't simplify. */
5775 {
5780 }
5784 }
5785 }
5787 /* A little bit of algebraic simplification here. */
5789 {
5791 /* Ensure that our address has any ASHIFTs converted to MULT in case
5792 address-recognizing predicates are called later. */
5801 /* See if this can be moved to simplify_subreg. */
5804 /* Don't call gen_lowpart if the inner mode
5805 is VOIDmode and we cannot simplify it, as SUBREG without
5806 inner mode is invalid. */
5813 {
5814 rtx temp;
5820 /* If op is known to have all lower bits zero, the result is zero. */
5833 }
5835 /* Don't change the mode of the MEM if that would change the meaning
5836 of the address. */
5843 /* Note that we cannot do any narrowing for non-constants since
5844 we might have been counting on using the fact that some bits were
5845 zero. We now do this in the SET. */
5852 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5853 replaced by (lshiftrt X C). This will convert
5854 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5862 /* If X has only a single bit that might be nonzero, say, bit I, convert
5863 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5864 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5865 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5866 or a SUBREG of one since we'd be making the expression more
5867 complex if it was just a register. */
5874 {
5875 rtx temp1 = simplify_shift_const
5881 /* If all we did was surround TEMP with the two shifts, we
5882 haven't improved anything, so don't use it. Otherwise,
5883 we are better off with TEMP1. */
5888 }
5892 /* We can't handle truncation to a partial integer mode here
5893 because we don't know the real bitsize of the partial
5894 integer mode. */
5903 /* We can truncate a constant value and return it. */
5907 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5908 whose value is a comparison can be replaced with a subreg if
5909 STORE_FLAG_VALUE permits. */
5918 /* (const (const X)) can become (const X). Do it this way rather than
5919 returning the inner CONST since CONST can be shared with a
5920 REG_EQUAL note. */
5926 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5927 can add in an offset. find_split_point will split this address up
5928 again if it doesn't match. */
5935 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5936 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5937 bit-field and can be replaced by either a sign_extend or a
5938 sign_extract. The `and' may be a zero_extend and the two
5939 <c>, -<c> constants may be reversed. */
5955 return simplify_shift_const
5962 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5963 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5964 the bitsize of the mode - 1. This allows simplification of
5965 "a = (b & 8) == 0;" */
5972 return simplify_shift_const
5976 const1_rtx),
5980 /* If we are adding two things that have no bits in common, convert
5981 the addition into an IOR. This will often be further simplified,
5982 for example in cases like ((a & 1) + (a & 2)), which can
5983 become a & 3. */
5988 {
5989 /* Try to simplify the expression further. */
5993 /* If we could, great. If not, do not go ahead with the IOR
5994 replacement, since PLUS appears in many special purpose
5995 address arithmetic instructions. */
6003 }
6005 /* Canonicalize x + x into x << 1. */
6014 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6015 (and <foo> (const_int pow2-1)) */
6026 /* If we have (mult (plus A B) C), apply the distributive law and then
6027 the inverse distributive law to see if things simplify. This
6028 occurs mostly in addresses, often when unrolling loops. */
6031 {
6035 }
6037 /* Try simplify a*(b/c) as (a*b)/c. */
6040 {
6046 }
6050 /* If this is a divide by a power of two, treat it as a shift if
6051 its first operand is a shift. */
6071 /* If the first operand is a condition code, we can't do anything
6072 with it. */
6076 {
6084 /* Simplify our comparison, if possible. */
6087 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6088 if only the low-order bit is possibly nonzero in X (such as when
6089 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6090 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6091 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6092 (plus X 1).
6094 Remove any ZERO_EXTRACT we made when thinking this was a
6095 comparison. It may now be simpler to use, e.g., an AND. If a
6096 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6097 the call to make_compound_operation in the SET case.
6099 Don't apply these optimizations if the caller would
6100 prefer a comparison rather than a value.
6101 E.g., for the condition in an IF_THEN_ELSE most targets need
6102 an explicit comparison. */
6105 ;
6123 {
6127 int_mode);
6128 }
6136 {
6140 const1_rtx);
6141 }
6150 {
6153 }
6155 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6156 those above. */
6158 ;
6175 {
6179 int_mode);
6180 }
6189 {
6193 int_mode);
6194 }
6196 /* If X is 0/1, (eq X 0) is X-1. */
6203 {
6206 }
6208 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6209 one bit that might be nonzero, we can convert (ne x 0) to
6210 (ashift x c) where C puts the bit in the sign bit. Remove any
6211 AND with STORE_FLAG_VALUE when we are done, since we are only
6212 going to test the sign bit. */
6220 {
6226 else
6228 }
6230 /* If the code changed, return a whole new comparison.
6231 We also need to avoid using SUBST in cases where
6232 simplify_comparison has widened a comparison with a CONST_INT,
6233 since in that case the wider CONST_INT may fail the sanity
6234 checks in do_SUBST. */
6241 /* Otherwise, keep this operation, but maybe change its operands.
6242 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6245 }
6255 /* If we are processing SET_DEST, we are done. */
6273 /* If this is a shift by a constant amount, simplify it. */
6281 (HOST_WIDE_INT_1U
6289 }
6292 }
6293 \f
6294 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6296 static rtx
6298 {
6305 rtx temp;
6308 rtx reversed;
6311 /* Simplify storing of the truth value. */
6316 /* Also when the truth value has to be reversed. */
6322 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6323 in it is being compared against certain values. Get the true and false
6324 comparisons and see if that says anything about the value of each arm. */
6330 {
6331 HOST_WIDE_INT nzb;
6337 /* If FALSE_CODE is EQ, swap the codes and arms. */
6340 {
6343 }
6345 scalar_int_mode from_mode;
6347 {
6348 /* If we are comparing against zero and the expression being
6349 tested has only a single bit that might be nonzero, that is
6350 its value when it is not equal to zero. Similarly if it is
6351 known to be -1 or 0. */
6355 {
6358 }
6363 {
6366 }
6367 }
6369 /* Now simplify an arm if we know the value of the register in the
6370 branch and it is used in the arm. Be careful due to the potential
6371 of locally-shared RTL. */
6388 }
6390 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6391 reversed, do so to avoid needing two sets of patterns for
6392 subtract-and-branch insns. Similarly if we have a constant in the true
6393 arm, the false arm is the same as the first operand of the comparison, or
6394 the false arm is more complicated than the true arm. */
6407 {
6416 /* It is possible that the conditional has been simplified out. */
6419 }
6421 /* If the two arms are identical, we don't need the comparison. */
6426 /* Convert a == b ? b : a to "a". */
6438 /* Look for cases where we have (abs x) or (neg (abs X)). */
6441 && comparison_p
6448 {
6454 return
6457 mode);
6460 }
6462 /* Look for MIN or MAX. */
6465 && comparison_p
6470 {
6485 }
6487 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6488 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6489 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6490 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6491 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6492 neither 1 or -1, but it isn't worth checking for. */
6495 && comparison_p
6498 {
6514 /* If an identity-zero op is commutative, check whether there
6515 would be a match if we swapped the operands. */
6536 {
6540 }
6553 {
6557 }
6574 {
6578 }
6591 {
6595 }
6598 {
6604 const_true_rtx));
6612 }
6613 }
6615 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6616 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6617 negation of a single bit, we can convert this operation to a shift. We
6618 can actually do this more generally, but it doesn't seem worth it. */
6630 return
6634 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6635 non-zero bit in A is C1. */
6643 {
6649 }
6652 }
6653 \f
6654 /* Simplify X, a SET expression. Return the new expression. */
6656 static rtx
6658 {
6661 machine_mode mode
6665 scalar_int_mode int_mode;
6667 /* (set (pc) (return)) gets written as (return). */
6671 /* Now that we know for sure which bits of SRC we are using, see if we can
6672 simplify the expression for the object knowing that we only need the
6673 low-order bits. */
6676 {
6679 }
6681 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6682 the comparison result and try to simplify it unless we already have used
6683 undobuf.other_insn. */
6691 {
6700 {
6703 {
6706 }
6707 }
6708 else
6716 {
6720 }
6721 else
6722 {
6727 /* Attempt to simplify CC user. */
6729 {
6733 }
6735 /* Convert X into a no-op move. */
6739 }
6741 /* Simplify our comparison, if possible. */
6744 #ifdef SELECT_CC_MODE
6745 /* If this machine has CC modes other than CCmode, check to see if we
6746 need to use a different CC mode here. */
6755 else
6758 /* If the mode changed, we have to change SET_DEST, the mode in the
6759 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6760 a hard register, just build new versions with the proper mode. If it
6761 is a pseudo, we lose unless it is only time we set the pseudo, in
6762 which case we can safely change its mode. */
6764 {
6766 {
6768 rtx new_dest;
6772 else
6773 {
6776 }
6783 }
6784 }
6787 /* If the code changed, we have to build a new comparison in
6788 undobuf.other_insn. */
6790 {
6799 /* If the only change we made was to change an EQ into an NE or
6800 vice versa, OP0 has only one bit that might be nonzero, and OP1
6801 is zero, check if changing the user of the condition code will
6802 produce a valid insn. If it won't, we can keep the original code
6803 in that insn by surrounding our operation with an XOR. */
6810 {
6815 {
6822 }
6823 }
6824 }
6829 /* Don't generate a compare of a CC with 0, just use that CC. */
6831 {
6834 }
6835 /* Otherwise, if we didn't previously have the same COMPARE we
6836 want, create it from scratch. */
6839 {
6842 }
6843 }
6844 else
6845 {
6846 /* Get SET_SRC in a form where we have placed back any
6847 compound expressions. Then do the checks below. */
6850 }
6852 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6853 and X being a REG or (subreg (reg)), we may be able to convert this to
6854 (set (subreg:m2 x) (op)).
6856 We can always do this if M1 is narrower than M2 because that means that
6857 we only care about the low bits of the result.
6859 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6860 perform a narrower operation than requested since the high-order bits will
6861 be undefined. On machine where it is defined, this transformation is safe
6862 as long as M1 and M2 have the same number of words. */
6871 #ifdef CANNOT_CHANGE_MODE_CLASS
6876 #endif
6880 {
6883 dest));
6887 }
6889 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6890 in SRC. */
6894 {
6898 /* Here we make sure that we don't have a sign bit on. */
6901 {
6904 }
6905 }
6907 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6908 would require a paradoxical subreg. Replace the subreg with a
6909 zero_extend to avoid the reload that would otherwise be required. */
6915 {
6920 }
6922 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6923 are comparing an item known to be 0 or -1 against 0, use a logical
6924 operation instead. Check for one of the arms being an IOR of the other
6925 arm with some value. We compute three terms to be IOR'ed together. In
6926 practice, at most two will be nonzero. Then we do the IOR's. */
6934 && (!HAVE_conditional_move
6939 {
6964 int_mode),
6965 false_rtx);
6971 term3));
6974 }
6976 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6977 whole thing fail. */
6982 else
6983 /* Convert this into a field assignment operation, if possible. */
6985 }
6986 \f
6987 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6988 result. */
6990 static rtx
6992 {
6995 scalar_int_mode mode;
6998 {
7000 /* We can call simplify_and_const_int only if we don't lose
7001 any (sign) bits when converting INTVAL (op1) to
7002 "unsigned HOST_WIDE_INT". */
7007 {
7014 }
7016 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7017 apply the distributive law and then the inverse distributive
7018 law to see if things simplify. */
7020 {
7024 }
7026 {
7030 }
7034 /* If we have (ior (and A B) C), apply the distributive law and then
7035 the inverse distributive law to see if things simplify. */
7038 {
7042 }
7045 {
7049 }
7054 }
7057 }
7058 \f
7059 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7060 operations" because they can be replaced with two more basic operations.
7061 ZERO_EXTEND is also considered "compound" because it can be replaced with
7062 an AND operation, which is simpler, though only one operation.
7064 The function expand_compound_operation is called with an rtx expression
7065 and will convert it to the appropriate shifts and AND operations,
7066 simplifying at each stage.
7068 The function make_compound_operation is called to convert an expression
7069 consisting of shifts and ANDs into the equivalent compound expression.
7070 It is the inverse of this function, loosely speaking. */
7072 static rtx
7074 {
7078 rtx tem;
7079 scalar_int_mode inner_mode;
7082 {
7085 /* FALLTHRU */
7087 /* We can't necessarily use a const_int for a multiword mode;
7088 it depends on implicitly extending the value.
7089 Since we don't know the right way to extend it,
7090 we can't tell whether the implicit way is right.
7092 Even for a mode that is no wider than a const_int,
7093 we can't win, because we need to sign extend one of its bits through
7094 the rest of it, and we don't know which bit. */
7098 /* Reject modes that aren't scalar integers because turning vector
7099 or complex modes into shifts causes problems. */
7103 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7104 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7105 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7106 reloaded. If not for that, MEM's would very rarely be safe.
7108 Reject modes bigger than a word, because we might not be able
7109 to reference a two-register group starting with an arbitrary register
7110 (and currently gen_lowpart might crash for a SUBREG). */
7116 /* If the inner object has VOIDmode (the only way this can happen
7117 is if it is an ASM_OPERANDS), we can't do anything since we don't
7118 know how much masking to do. */
7127 /* fall through */
7130 /* If the operand is a CLOBBER, just return it. */
7138 /* Reject modes that aren't scalar integers because turning vector
7139 or complex modes into shifts causes problems. */
7146 /* This should stay within the object being extracted, fail otherwise. */
7157 }
7159 /* We've rejected non-scalar operations by now. */
7162 /* Convert sign extension to zero extension, if we know that the high
7163 bit is not set, as this is easier to optimize. It will be converted
7164 back to cheaper alternative in make_extraction. */
7170 {
7174 /* Make sure this is a profitable operation. */
7181 else
7183 }
7185 /* We can optimize some special cases of ZERO_EXTEND. */
7187 {
7188 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7189 know that the last value didn't have any inappropriate bits
7190 set. */
7198 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7207 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7208 is a comparison and STORE_FLAG_VALUE permits. This is like
7209 the first case, but it works even when MODE is larger
7210 than HOST_WIDE_INT. */
7218 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7227 }
7229 /* If we reach here, we want to return a pair of shifts. The inner
7230 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7231 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7232 logical depending on the value of UNSIGNEDP.
7234 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7235 converted into an AND of a shift.
7237 We must check for the case where the left shift would have a negative
7238 count. This can happen in a case like (x >> 31) & 255 on machines
7239 that can't shift by a constant. On those machines, we would first
7240 combine the shift with the AND to produce a variable-position
7241 extraction. Then the constant of 31 would be substituted in
7242 to produce such a position. */
7246 {
7254 }
7259 pos),
7261 else
7262 /* Any other cases we can't handle. */
7265 /* If we couldn't do this for some reason, return the original
7266 expression. */
7271 }
7272 \f
7273 /* X is a SET which contains an assignment of one object into
7274 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7275 or certain SUBREGS). If possible, convert it into a series of
7276 logical operations.
7278 We half-heartedly support variable positions, but do not at all
7279 support variable lengths. */
7281 static const_rtx
7283 {
7284 rtx inner;
7288 scalar_int_mode compute_mode;
7290 /* Loop until we find something we can't simplify. */
7292 {
7295 {
7299 }
7302 {
7307 /* A constant position should stay within the width of INNER. */
7313 {
7321 /* If position is ADJUST - X, new position is X. */
7323 else
7324 {
7329 pos);
7330 }
7331 }
7332 }
7334 /* A SUBREG between two modes that occupy the same numbers of words
7335 can be done by moving the SUBREG to the source. */
7337 /* We need SUBREGs to compute nonzero_bits properly. */
7338 && nonzero_sign_valid
7343 {
7345 gen_lowpart
7349 }
7350 else
7356 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7358 {
7359 /* Don't do anything for vector or complex integral types. */
7363 /* Try to find an integral mode to pun with. */
7369 }
7371 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7375 /* Don't try to compute in too wide unsupported modes. */
7379 /* Now compute the equivalent expression. Make a copy of INNER
7380 for the SET_DEST in case it is a MEM into which we will substitute;
7381 we don't want shared RTL in that case. */
7383 compute_mode);
7387 compute_mode,
7389 compute_mode),
7390 inner);
7395 mask),
7396 pos);
7401 }
7404 }
7405 \f
7406 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7407 it is an RTX that represents the (variable) starting position; otherwise,
7408 POS is the (constant) starting bit position. Both are counted from the LSB.
7410 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7412 IN_DEST is nonzero if this is a reference in the destination of a SET.
7413 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7414 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7415 be used.
7417 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7418 ZERO_EXTRACT should be built even for bits starting at bit 0.
7420 MODE is the desired mode of the result (if IN_DEST == 0).
7422 The result is an RTX for the extraction or NULL_RTX if the target
7423 can't handle it. */
7425 static rtx
7429 {
7430 /* This mode describes the size of the storage area
7431 to fetch the overall value from. Within that, we
7432 ignore the POS lowest bits, etc. */
7434 machine_mode inner_mode;
7435 scalar_int_mode wanted_inner_mode;
7441 HOST_WIDE_INT orig_pos;
7447 {
7448 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7449 consider just the QI as the memory to extract from.
7450 The subreg adds or removes high bits; its mode is
7451 irrelevant to the meaning of this extraction,
7452 since POS and LEN count from the lsb. */
7456 }
7461 {
7462 /* We're extracting the least significant bits of an rtx
7463 (ashift X (const_int C)), where LEN > C. Extract the
7464 least significant (LEN - C) bits of X, giving an rtx
7465 whose mode is MODE, then shift it left C times. */
7471 }
7477 /* See if this can be done without an extraction. We never can if the
7478 width of the field is not the same as that of some integer mode. For
7479 registers, we can only avoid the extraction if the position is at the
7480 low-order bit and this is either not in the destination or we have the
7481 appropriate STRICT_LOW_PART operation available.
7483 For MEM, we can avoid an extract if the field starts on an appropriate
7484 boundary and we can change the mode of the memory reference. */
7486 scalar_int_mode tmode;
7495 && (! in_dest
7499 && (pos
7502 /* We can't do this if we are widening INNER_MODE (it
7503 may not be aligned, for one thing). */
7509 {
7510 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7511 field. If the original and current mode are the same, we need not
7512 adjust the offset. Otherwise, we do if bytes big endian.
7514 If INNER is not a MEM, get a piece consisting of just the field
7515 of interest (in this case POS % BITS_PER_WORD must be 0). */
7518 {
7519 HOST_WIDE_INT offset;
7521 /* POS counts from lsb, but make OFFSET count in memory order. */
7524 else
7528 }
7530 {
7532 {
7533 /* We can't call gen_lowpart in a DEST since we
7534 always want a SUBREG (see below) and it would sometimes
7535 return a new hard register. */
7537 {
7538 unsigned int offset
7541 /* Avoid creating invalid subregs, for example when
7542 simplifying (x>>32)&255. */
7547 }
7548 else
7550 }
7551 else
7553 }
7554 else
7556 len >= HOST_BITS_PER_WIDE_INT
7557 ? HOST_WIDE_INT_M1U
7560 /* If this extraction is going into the destination of a SET,
7561 make a STRICT_LOW_PART unless we made a MEM. */
7576 /* If we know that no extraneous bits are set, and that the high
7577 bit is not set, convert the extraction to the cheaper of
7578 sign and zero extension, that are equivalent in these cases. */
7584 {
7588 /* Prefer ZERO_EXTENSION, since it gives more information to
7589 backends. */
7594 }
7596 /* Otherwise, sign- or zero-extend unless we already are in the
7597 proper mode. */
7601 }
7603 /* Unless this is a COMPARE or we have a funny memory reference,
7604 don't do anything with zero-extending field extracts starting at
7605 the low-order bit since they are simple AND operations. */
7610 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7611 if the position is not a constant and the length is not 1. In all
7612 other cases, we would only be going outside our object in cases when
7613 an original shift would have been undefined. */
7622 /* If INNER is not from memory, we want it to have the mode of a register
7623 extraction pattern's structure operand, or word_mode if there is no
7624 such pattern. The same applies to extraction_mode and pos_mode
7625 and their respective operands.
7627 For memory, assume that the desired extraction_mode and pos_mode
7628 are the same as for a register operation, since at present we don't
7629 have named patterns for aligned memory structures. */
7633 {
7637 }
7639 /* Never narrow an object, since that might not be safe. */
7647 else
7648 {
7649 /* Be careful not to go beyond the extracted object and maintain the
7650 natural alignment of the memory. */
7655 }
7660 {
7661 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7662 BITS_BIG_ENDIAN style. If position is constant, compute new
7663 position. Otherwise, build subtraction.
7664 Note that POS is relative to the mode of the original argument.
7665 If it's a MEM we need to recompute POS relative to that.
7666 However, if we're extracting from (or inserting into) a register,
7667 we want to recompute POS relative to wanted_inner_mode. */
7674 else
7675 pos_rtx
7678 pos_rtx);
7679 /* POS may be less than 0 now, but we check for that below.
7680 Note that it can only be less than 0 if !MEM_P (inner). */
7681 }
7683 /* If INNER has a wider mode, and this is a constant extraction, try to
7684 make it smaller and adjust the byte to point to the byte containing
7685 the value. */
7688 && ! pos_rtx
7693 {
7696 /* The computations below will be correct if the machine is big
7697 endian in both bits and bytes or little endian in bits and bytes.
7698 If it is mixed, we must adjust. */
7700 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7701 adjust OFFSET to compensate. */
7706 /* We can now move to the desired byte. */
7717 }
7719 /* If INNER is not memory, get it into the proper mode. If we are changing
7720 its mode, POS must be a constant and smaller than the size of the new
7721 mode. */
7723 {
7724 /* On the LHS, don't create paradoxical subregs implicitely truncating
7725 the register unless TRULY_NOOP_TRUNCATION. */
7728 wanted_inner_mode))
7740 pos_rtx
7742 ? HOST_WIDE_INT_M1U
7746 }
7748 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7749 have to zero extend. Otherwise, we can just use a SUBREG.
7751 We dealt with constant rtxes earlier, so pos_rtx cannot
7752 have VOIDmode at this point. */
7756 {
7760 /* If we know that no extraneous bits are set, and that the high
7761 bit is not set, convert extraction to cheaper one - either
7762 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7763 cases. */
7771 {
7775 /* Prefer ZERO_EXTENSION, since it gives more information to
7776 backends. */
7780 }
7782 }
7784 /* Make POS_RTX unless we already have it and it is correct. If we don't
7785 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7786 be a CONST_INT. */
7793 /* Make the required operation. See if we can use existing rtx. */
7800 }
7801 \f
7802 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
7803 can be commuted with any other operations in X. Return X without
7804 that shift if so. */
7806 static rtx
7808 {
7810 rtx tem;
7813 {
7815 /* This is the shift itself. If it is wide enough, we will return
7816 either the value being shifted if the shift count is equal to
7817 COUNT or a shift for the difference. */
7831 /* If we can safely shift this constant and we find the inner shift,
7832 make a new operation. */
7837 {
7841 }
7846 }
7849 }
7850 \f
7851 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7852 level of the expression and MODE is its mode. IN_CODE is as for
7853 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7854 that should be used when recursing on operands of *X_PTR.
7856 There are two possible actions:
7858 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7859 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7861 - Return a new rtx, which the caller returns directly. */
7863 static rtx
7867 {
7875 rtx tem;
7876 scalar_int_mode inner_mode;
7880 {
7883 }
7885 /* Process depending on the code of this operation. If NEW is set
7886 nonzero, it will be returned. */
7889 {
7891 /* Convert shifts by constants into multiplications if inside
7892 an address. */
7896 {
7902 {
7905 }
7908 }
7917 {
7921 }
7924 {
7928 mode));
7930 }
7931 else
7932 {
7935 }
7945 {
7949 }
7952 {
7956 mode));
7958 }
7959 else
7960 {
7964 }
7967 /* If the second operand is not a constant, we can't do anything
7968 with it. */
7972 /* If the constant is a power of two minus one and the first operand
7973 is a logical right shift, make an extraction. */
7976 {
7980 }
7982 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7989 {
7996 /* If we narrowed the mode when dropping the subreg, then we lose. */
8000 /* If that didn't give anything, see if the AND simplifies on
8001 its own. */
8003 {
8007 }
8008 }
8009 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8015 {
8016 /* Apply the distributive law, and then try to make extractions. */
8023 }
8025 /* If we are have (and (rotate X C) M) and C is larger than the number
8026 of bits in M, this is an extraction. */
8032 {
8038 }
8040 /* On machines without logical shifts, if the operand of the AND is
8041 a logical shift and our mask turns off all the propagated sign
8042 bits, we can replace the logical shift with an arithmetic shift. */
8050 {
8057 make_compound_operation
8060 }
8062 /* If the constant is one less than a power of two, this might be
8063 representable by an extraction even if no shift is present.
8064 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8065 we are in a COMPARE. */
8069 next_code),
8072 /* If we are in a comparison and this is an AND with a power of two,
8073 convert this into the appropriate bit extract. */
8079 next_code),
8082 /* If the one operand is a paradoxical subreg of a register or memory and
8083 the constant (limited to the smaller mode) has only zero bits where
8084 the sub expression has known zero bits, this can be expressed as
8085 a zero_extend. */
8087 {
8088 rtx sub;
8094 {
8098 /* original AND constant with all the known zero bits set */
8101 {
8106 }
8107 }
8108 }
8113 /* If the sign bit is known to be zero, replace this with an
8114 arithmetic shift. */
8119 {
8122 next_code),
8125 }
8127 /* fall through */
8133 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8134 this is a SIGN_EXTRACT. */
8141 {
8148 }
8150 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8151 If so, try to merge the shifts into a SIGN_EXTEND. We could
8152 also do this for some cases of SIGN_EXTRACT, but it doesn't
8153 seem worth the effort; the case checked for occurs on Alpha. */
8170 /* Call ourselves recursively on the inner expression. If we are
8171 narrowing the object and it has a different RTL code from
8172 what it originally did, do this SUBREG as a force_to_mode. */
8173 {
8177 /* If the SUBREG is masking of a logical right shift,
8178 make an extraction. */
8185 {
8194 }
8196 /* If in_code is COMPARE, it isn't always safe to pass it through
8197 to the recursive make_compound_operation call. */
8201 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8202 is (const_int 0), rather than
8203 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8204 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8205 for non-equality comparisons against 0 is not equivalent
8206 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8216 simplified
8224 {
8225 rtx newer
8228 /* If we have something other than a SUBREG, we might have
8229 done an expansion, so rerun ourselves. */
8233 /* force_to_mode can expand compounds. If it just re-expanded
8234 the compound, use gen_lowpart to convert to the desired
8235 mode. */
8237 /* Likewise if it re-expanded the compound only partially.
8238 This happens for SUBREG of ZERO_EXTRACT if they extract
8239 the same number of bits. */
8248 }
8252 }
8257 }
8263 }
8265 /* Look at the expression rooted at X. Look for expressions
8266 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8267 Form these expressions.
8269 Return the new rtx, usually just X.
8271 Also, for machines like the VAX that don't have logical shift insns,
8272 try to convert logical to arithmetic shift operations in cases where
8273 they are equivalent. This undoes the canonicalizations to logical
8274 shifts done elsewhere.
8276 We try, as much as possible, to re-use rtl expressions to save memory.
8278 IN_CODE says what kind of expression we are processing. Normally, it is
8279 SET. In a memory address it is MEM. When processing the arguments of
8280 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8281 precisely it is an equality comparison against zero. */
8283 rtx
8285 {
8292 /* Select the code to be used in recursive calls. Once we are inside an
8293 address, we stay there. If we have a comparison, set to COMPARE,
8294 but once inside, go back to our default of SET. */
8301 scalar_int_mode mode;
8303 {
8309 }
8311 /* Now recursively process each operand of this operation. We need to
8312 handle ZERO_EXTEND specially so that we don't lose track of the
8313 inner mode. */
8315 {
8323 }
8328 {
8331 }
8334 {
8337 }
8341 }
8342 \f
8343 /* Given M see if it is a value that would select a field of bits
8344 within an item, but not the entire word. Return -1 if not.
8345 Otherwise, return the starting position of the field, where 0 is the
8346 low-order bit.
8348 *PLEN is set to the length of the field. */
8350 static int
8352 {
8353 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8358 /* Now shift off the low-order zero bits and see if we have a
8359 power of two minus 1. */
8367 }
8368 \f
8369 /* If X refers to a register that equals REG in value, replace these
8370 references with REG. */
8371 static rtx
8373 {
8381 {
8414 /* FALLTHRU */
8418 {
8422 else
8424 }
8426 /* fall through */
8433 {
8436 {
8438 {
8441 }
8443 }
8444 }
8446 {
8449 {
8452 {
8454 {
8457 }
8459 }
8460 }
8461 }
8464 }
8467 }
8469 /* Return X converted to MODE. If the value is already truncated to
8470 MODE we can just return a subreg even though in the general case we
8471 would need an explicit truncation. */
8473 static rtx
8475 {
8480 {
8481 /* Bit-cast X into an integer mode. */
8486 }
8489 }
8491 /* See if X can be simplified knowing that we will only refer to it in
8492 MODE and will only refer to those bits that are nonzero in MASK.
8493 If other bits are being computed or if masking operations are done
8494 that select a superset of the bits in MASK, they can sometimes be
8495 ignored.
8497 Return a possibly simplified expression, but always convert X to
8498 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8500 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8501 are all off in X. This is used when X will be complemented, by either
8502 NOT, NEG, or XOR. */
8504 static rtx
8507 {
8510 machine_mode op_mode;
8513 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8514 code below will do the wrong thing since the mode of such an
8515 expression is VOIDmode.
8517 Also do nothing if X is a CLOBBER; this can happen if X was
8518 the return value from a call to gen_lowpart. */
8522 /* We want to perform the operation in its present mode unless we know
8523 that the operation is valid in MODE, in which case we do the operation
8524 in MODE. */
8529 /* It is not valid to do a right-shift in a narrower mode
8530 than the one it came in with. */
8535 /* Truncate MASK to fit OP_MODE. */
8539 /* Determine what bits of X are guaranteed to be (non)zero. */
8542 /* If none of the bits in X are needed, return a zero. */
8546 /* If X is a CONST_INT, return a new one. Do this here since the
8547 test below will fail. */
8549 {
8552 else
8553 {
8556 }
8557 }
8559 /* If X is narrower than MODE and we want all the bits in X's mode, just
8560 get X in the proper mode. */
8565 /* We can ignore the effect of a SUBREG if it narrows the mode or
8566 if the constant masks to zero all the bits the mode doesn't have. */
8578 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8579 integer too. */
8585 }
8587 /* Subroutine of force_to_mode that handles cases in which both X and
8588 the result are scalar integers. MODE is the mode of the result,
8589 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8590 is preferred for simplified versions of X. The other arguments
8591 are as for force_to_mode. */
8593 static rtx
8597 {
8603 /* When we have an arithmetic operation, or a shift whose count we
8604 do not know, we need to assume that all bits up to the highest-order
8605 bit in MASK will be needed. This is how we form such a mask. */
8608 else
8613 {
8615 /* If X is a (clobber (const_int)), return it since we know we are
8616 generating something that won't match. */
8629 /* Similarly for a truncate. */
8633 /* If this is an AND with a constant, convert it into an AND
8634 whose constant is the AND of that constant with MASK. If it
8635 remains an AND of MASK, delete it since it is redundant. */
8638 {
8643 /* If X is still an AND, see if it is an AND with a mask that
8644 is just some low-order bits. If so, and it is MASK, we don't
8645 need it. */
8651 /* If it remains an AND, try making another AND with the bits
8652 in the mode mask that aren't in MASK turned on. If the
8653 constant in the AND is wide enough, this might make a
8654 cheaper constant. */
8659 {
8660 unsigned HOST_WIDE_INT cval
8662 rtx y;
8669 }
8672 }
8677 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8678 low-order bits (as in an alignment operation) and FOO is already
8679 aligned to that boundary, mask C1 to that boundary as well.
8680 This may eliminate that PLUS and, later, the AND. */
8682 {
8686 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8687 number, sign extend it. */
8700 }
8702 /* fall through */
8705 /* Substituting into the operands of a widening MULT is not likely to
8706 create RTL matching a machine insn. */
8716 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8717 most significant bit in MASK since carries from those bits will
8718 affect the bits we are interested in. */
8723 /* If X is (minus C Y) where C's least set bit is larger than any bit
8724 in the mask, then we may replace with (neg Y). */
8727 {
8730 }
8732 /* Similarly, if C contains every bit in the fuller_mask, then we may
8733 replace with (not Y). */
8736 {
8739 }
8746 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8747 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8748 operation which may be a bitfield extraction. Ensure that the
8749 constant we form is not wider than the mode of X. */
8761 {
8764 xmode);
8770 }
8772 binop:
8773 /* For most binary operations, just propagate into the operation and
8774 change the mode if we have an operation of that mode. */
8779 /* If we ended up truncating both operands, truncate the result of the
8780 operation instead. */
8783 {
8786 }
8792 {
8795 }
8799 /* For left shifts, do the same, but just for the first operand.
8800 However, we cannot do anything with shifts where we cannot
8801 guarantee that the counts are smaller than the size of the mode
8802 because such a count will have a different meaning in a
8803 wider mode. */
8813 /* If the shift count is a constant and we can do arithmetic in
8814 the mode of the shift, refine which bits we need. Otherwise, use the
8815 conservative form of the mask. */
8821 else
8829 {
8832 }
8836 /* Here we can only do something if the shift count is a constant,
8837 this shift constant is valid for the host, and we can do arithmetic
8838 in OP_MODE. */
8844 {
8848 /* Select the mask of the bits we need for the shift operand. */
8851 /* We can only change the mode of the shift if we can do arithmetic
8852 in the mode of the shift and INNER_MASK is no wider than the
8853 width of X's mode. */
8860 {
8863 }
8864 }
8866 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8867 shift and AND produces only copies of the sign bit (C2 is one less
8868 than a power of two), we can do this with just a shift. */
8872 /* The shift puts one of the sign bit copies in the least significant
8873 bit. */
8878 /* Number of bits left after the shift must be more than the mask
8879 needs. */
8882 /* Must be more sign bit copies than the mask needs. */
8892 /* If we are just looking for the sign bit, we don't need this shift at
8893 all, even if it has a variable count. */
8897 /* If this is a shift by a constant, get a mask that contains those bits
8898 that are not copies of the sign bit. We then have two cases: If
8899 MASK only includes those bits, this can be a logical shift, which may
8900 allow simplifications. If MASK is a single-bit field not within
8901 those bits, we are requesting a copy of the sign bit and hence can
8902 shift the sign bit to the appropriate location. */
8906 {
8910 /* If the considered data is wider than HOST_WIDE_INT, we can't
8911 represent a mask for all its bits in a single scalar.
8912 But we only care about the lower bits, so calculate these. */
8915 {
8918 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8919 is the number of bits a full-width mask would have set.
8920 We need only shift if these are fewer than nonzero can
8921 hold. If not, we must keep all bits set in nonzero. */
8926 + HOST_BITS_PER_WIDE_INT
8928 }
8929 else
8930 {
8933 }
8936 {
8941 }
8944 {
8945 x = simplify_shift_const
8951 }
8952 }
8954 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8955 even if the shift count isn't a constant. */
8959 shiftrt:
8961 /* If this is a zero- or sign-extension operation that just affects bits
8962 we don't care about, remove it. Be sure the call above returned
8963 something that is still a shift. */
8973 next_select);
8979 /* If the shift count is constant and we can do computations
8980 in the mode of X, compute where the bits we care about are.
8981 Otherwise, we can't do anything. Don't change the mode of
8982 the shift or propagate MODE into the shift, though. */
8985 {
8994 }
8998 /* If we just want the low-order bit, the NEG isn't needed since it
8999 won't change the low-order bit. */
9003 /* We need any bits less significant than the most significant bit in
9004 MASK since carries from those bits will affect the bits we are
9005 interested in. */
9010 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9011 same as the XOR case above. Ensure that the constant we form is not
9012 wider than the mode of X. */
9020 {
9027 }
9029 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9030 use the full mask inside the NOT. */
9033 unop:
9036 next_select));
9038 {
9041 }
9045 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9046 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9047 which is equal to STORE_FLAG_VALUE. */
9059 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9060 written in a narrower mode. We play it safe and do not do so. */
9076 }
9078 /* Ensure we return a value of the proper mode. */
9080 }
9081 \f
9082 /* Return nonzero if X is an expression that has one of two values depending on
9083 whether some other value is zero or nonzero. In that case, we return the
9084 value that is being tested, *PTRUE is set to the value if the rtx being
9085 returned has a nonzero value, and *PFALSE is set to the other alternative.
9087 If we return zero, we set *PTRUE and *PFALSE to X. */
9089 static rtx
9091 {
9096 scalar_int_mode int_mode;
9098 /* If we are comparing a value against zero, we are done. */
9101 {
9105 }
9107 /* If this is a unary operation whose operand has one of two values, apply
9108 our opcode to compute those values. */
9111 {
9116 }
9118 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9119 make can't possibly match and would suppress other optimizations. */
9121 ;
9123 /* If this is a binary operation, see if either side has only one of two
9124 values. If either one does or if both do and they are conditional on
9125 the same value, compute the new true and false values. */
9127 {
9135 {
9136 /* Try to enable a simplification by undoing work done by
9137 if_then_else_cond if it converted a REG into something more
9138 complex. */
9140 {
9143 }
9144 else
9145 {
9148 }
9149 }
9153 {
9154 /* If if_then_else_cond returned zero, then true/false are the
9155 same rtl. We must copy one of them to prevent invalid rtl
9156 sharing. */
9163 {
9168 }
9169 else
9170 {
9173 }
9176 }
9178 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9179 operands is zero when the other is nonzero, and vice-versa,
9180 and STORE_FLAG_VALUE is 1 or -1. */
9186 {
9203 {
9210 const_true_rtx);
9212 }
9213 }
9215 /* Similarly for MULT, AND and UMIN, except that for these the result
9216 is always zero. */
9220 {
9234 {
9237 }
9238 }
9239 }
9242 {
9243 /* If we have IF_THEN_ELSE already, extract the condition and
9244 canonicalize it if it is NE or EQ. */
9250 {
9253 }
9254 else
9256 }
9258 /* If X is a SUBREG, we can narrow both the true and false values
9259 if the inner expression, if there is a condition. */
9263 {
9269 {
9273 }
9274 }
9276 /* If X is a constant, this isn't special and will cause confusions
9277 if we treat it as such. Likewise if it is equivalent to a constant. */
9280 ;
9282 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9283 will be least confusing to the rest of the compiler. */
9285 {
9288 }
9290 /* If X is known to be either 0 or -1, those are the true and
9291 false values when testing X. */
9296 {
9299 }
9301 /* Likewise for 0 or a single bit. */
9304 {
9307 }
9309 /* Otherwise fail; show no condition with true and false values the same. */
9312 }
9313 \f
9314 /* Return the value of expression X given the fact that condition COND
9315 is known to be true when applied to REG as its first operand and VAL
9316 as its second. X is known to not be shared and so can be modified in
9317 place.
9319 We only handle the simplest cases, and specifically those cases that
9320 arise with IF_THEN_ELSE expressions. */
9322 static rtx
9324 {
9332 /* If either operand of the condition is a floating point value,
9333 then we have to avoid collapsing an EQ comparison. */
9343 /* If X is (abs REG) and we know something about REG's relationship
9344 with zero, we may be able to simplify this. */
9348 {
9357 }
9359 /* The only other cases we handle are MIN, MAX, and comparisons if the
9360 operands are the same as REG and VAL. */
9363 {
9365 {
9368 }
9371 {
9373 {
9381 else
9383 }
9386 {
9389 /* Do not reverse the condition when it is NE or EQ.
9390 This is because we cannot conclude anything about
9391 the value of 'SMAX (x, y)' when x is not equal to y,
9392 but we can when x equals y. */
9398 {
9409 }
9410 }
9411 }
9412 }
9414 {
9419 {
9420 /* We must simplify subreg here, before we lose track of the
9421 original inner_mode. */
9426 else
9428 }
9431 }
9432 /* We don't have to handle SIGN_EXTEND here, because even in the
9433 case of replacing something with a modeless CONST_INT, a
9434 CONST_INT is already (supposed to be) a valid sign extension for
9435 its narrower mode, which implies it's already properly
9436 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9437 story is different. */
9439 {
9444 {
9445 /* We must simplify the zero_extend here, before we lose
9446 track of the original inner_mode. */
9451 else
9453 }
9456 }
9460 {
9467 }
9470 }
9471 \f
9472 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9473 assignment as a field assignment. */
9475 static int
9477 {
9479 {
9484 /* For big endian, adjust the memory offset. */
9489 else
9491 }
9499 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9500 Note that all SUBREGs of MEM are paradoxical; otherwise they
9501 would have been rewritten. */
9514 /* We used to see if get_last_value of X and Y were the same but that's
9515 not correct. In one direction, we'll cause the assignment to have
9516 the wrong destination and in the case, we'll import a register into this
9517 insn that might have already have been dead. So fail if none of the
9518 above cases are true. */
9520 }
9521 \f
9522 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9523 Return that assignment if so.
9525 We only handle the most common cases. */
9527 static rtx
9529 {
9532 rtx assign;
9534 HOST_WIDE_INT c1;
9535 HOST_WIDE_INT pos;
9537 rtx other;
9539 /* All the rules in this function are specific to scalar integers. */
9540 scalar_int_mode mode;
9544 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9545 a clear of a one-bit field. We will have changed it to
9546 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9547 for a SUBREG. */
9553 {
9559 }
9568 {
9575 }
9577 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9578 one-bit field. */
9582 {
9588 }
9590 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9591 SRC is an AND with all bits of that field set, then we can discard
9592 the AND. */
9597 {
9604 else
9607 /* Complete overlap. We can remove the source AND. */
9611 /* Partial overlap. We can reduce the source AND. */
9613 {
9617 }
9618 }
9620 /* The other case we handle is assignments into a constant-position
9621 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9622 a mask that has all one bits except for a group of zero bits and
9623 OTHER is known to have zeros where C1 has ones, this is such an
9624 assignment. Compute the position and length from C1. Shift OTHER
9625 to the appropriate position, force it to the required mode, and
9626 make the extraction. Check for the AND in both operands. */
9628 /* One or more SUBREGs might obscure the constant-position field
9629 assignment. The first one we are likely to encounter is an outer
9630 narrowing SUBREG, which we can just strip for the purposes of
9631 identifying the constant-field assignment. */
9648 /* The second SUBREG that might get in the way is a paradoxical
9649 SUBREG around the first operand of the AND. We want to
9650 pretend the operand is as wide as the destination here. We
9651 do this by adjusting the MEM to wider mode for the sole
9652 purpose of the call to rtx_equal_for_field_assignment_p. Also
9653 note this trick only works for MEMs. */
9665 /* The second SUBREG that might get in the way is a paradoxical
9666 SUBREG around the first operand of the AND. We want to
9667 pretend the operand is as wide as the destination here. We
9668 do this by adjusting the MEM to wider mode for the sole
9669 purpose of the call to rtx_equal_for_field_assignment_p. Also
9670 note this trick only works for MEMs. */
9678 else
9692 /* The mode to use for the source is the mode of the assignment, or of
9693 what is inside a possible STRICT_LOW_PART. */
9697 /* Shift OTHER right POS places and make it the source, restricting it
9698 to the proper length and mode. */
9702 dest);
9704 len >= HOST_BITS_PER_WIDE_INT
9705 ? HOST_WIDE_INT_M1U
9709 /* If SRC is masked by an AND that does not make a difference in
9710 the value being stored, strip it. */
9721 }
9722 \f
9723 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9724 if so. */
9726 static rtx
9728 {
9732 rtx tem;
9734 /* Distributivity is not true for floating point as it can change the
9735 value. So we don't do it unless -funsafe-math-optimizations. */
9740 /* The outer operation can only be one of the following: */
9748 /* If either operand is a primitive we can't do anything, so get out
9749 fast. */
9759 /* See if the inner and outer operations distribute. */
9761 {
9766 /* These all distribute except over PLUS. */
9777 /* This is also a multiply, so it distributes over everything. */
9780 /* This used to handle SUBREG, but this turned out to be counter-
9781 productive, since (subreg (op ...)) usually is not handled by
9782 insn patterns, and this "optimization" therefore transformed
9783 recognizable patterns into unrecognizable ones. Therefore the
9784 SUBREG case was removed from here.
9786 It is possible that distributing SUBREG over arithmetic operations
9787 leads to an intermediate result than can then be optimized further,
9788 e.g. by moving the outer SUBREG to the other side of a SET as done
9789 in simplify_set. This seems to have been the original intent of
9790 handling SUBREGs here.
9792 However, with current GCC this does not appear to actually happen,
9793 at least on major platforms. If some case is found where removing
9794 the SUBREG case here prevents follow-on optimizations, distributing
9795 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9799 }
9801 /* Set LHS and RHS to the inner operands (A and B in the example
9802 above) and set OTHER to the common operand (C in the example).
9803 There is only one way to do this unless the inner operation is
9804 commutative. */
9816 else
9819 /* Form the new inner operation, seeing if it simplifies first. */
9822 /* There is one exception to the general way of distributing:
9823 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9825 {
9828 }
9830 /* We may be able to continuing distributing the result, so call
9831 ourselves recursively on the inner operation before forming the
9832 outer operation, which we return. */
9835 }
9837 /* See if X is of the form (* (+ A B) C), and if so convert to
9838 (+ (* A C) (* B C)) and try to simplify.
9840 Most of the time, this results in no change. However, if some of
9841 the operands are the same or inverses of each other, simplifications
9842 will result.
9844 For example, (and (ior A B) (not B)) can occur as the result of
9845 expanding a bit field assignment. When we apply the distributive
9846 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9847 which then simplifies to (and (A (not B))).
9849 Note that no checks happen on the validity of applying the inverse
9850 distributive law. This is pointless since we can do it in the
9851 few places where this routine is called.
9853 N is the index of the term that is decomposed (the arithmetic operation,
9854 i.e. (+ A B) in the first example above). !N is the index of the term that
9855 is distributed, i.e. of C in the first example above. */
9856 static rtx
9858 {
9859 machine_mode mode;
9863 /* Distributivity is not true for floating point as it can change the
9864 value. So we don't do it unless -funsafe-math-optimizations. */
9881 /* Special case (and (xor B C) (not A)), which is equivalent to
9882 (xor (ior A B) (ior A C)) */
9884 {
9887 }
9890 {
9891 /* Distribute the second term. */
9894 }
9895 else
9896 {
9897 /* Distribute the first term. */
9900 }
9910 }
9911 \f
9912 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9913 in MODE. Return an equivalent form, if different from (and VAROP
9914 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9916 static rtx
9919 {
9922 rtx orig_varop;
9930 /* Simplify VAROP knowing that we will be only looking at some of the
9931 bits in it.
9933 Note by passing in CONSTOP, we guarantee that the bits not set in
9934 CONSTOP are not significant and will never be examined. We must
9935 ensure that is the case by explicitly masking out those bits
9936 before returning. */
9939 /* If VAROP is a CLOBBER, we will fail so return it. */
9943 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9944 to VAROP and return the new constant. */
9948 /* See what bits may be nonzero in VAROP. Unlike the general case of
9949 a call to nonzero_bits, here we don't care about bits outside
9950 MODE. */
9954 /* Turn off all bits in the constant that are known to already be zero.
9955 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9956 which is tested below. */
9960 /* If we don't have any bits left, return zero. */
9964 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9965 a power of two, we can replace this with an ASHIFT. */
9970 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9971 or XOR, then try to apply the distributive law. This may eliminate
9972 operations if either branch can be simplified because of the AND.
9973 It may also make some cases more complex, but those cases probably
9974 won't match a pattern either with or without this. */
9977 {
9979 return
9980 gen_lowpart
9982 apply_distributive_law
9986 constop),
9989 constop))));
9990 }
9992 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9993 the AND and see if one of the operands simplifies to zero. If so, we
9994 may eliminate it. */
9998 {
10007 }
10009 /* Make a SUBREG if necessary. If we can't make it, fail. */
10014 /* If we are only masking insignificant bits, return VAROP. */
10021 /* Otherwise, return an AND. */
10023 }
10026 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10027 in MODE.
10029 Return an equivalent form, if different from X. Otherwise, return X. If
10030 X is zero, we are to always construct the equivalent form. */
10032 static rtx
10035 {
10046 }
10047 \f
10048 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10049 We don't care about bits outside of those defined in MODE.
10051 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10052 a shift, AND, or zero_extract, we can do better. */
10054 static rtx
10056 scalar_int_mode mode,
10058 {
10059 rtx tem;
10062 /* If X is a register whose nonzero bits value is current, use it.
10063 Otherwise, if X is a register whose value we can find, use that
10064 value. Otherwise, use the previously-computed global nonzero bits
10065 for this register. */
10079 && !REGNO_REG_SET_P
10082 {
10083 /* Note that, even if the precision of last_set_mode is lower than that
10084 of mode, record_value_for_reg invoked nonzero_bits on the register
10085 with nonzero_bits_mode (because last_set_mode is necessarily integral
10086 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10087 are all valid, hence in mode too since nonzero_bits_mode is defined
10088 to the largest HWI_COMPUTABLE_MODE_P mode. */
10091 }
10095 {
10100 }
10103 {
10107 /* We don't know anything about the upper bits. */
10111 }
10114 }
10116 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10117 end of X that are known to be equal to the sign bit. X will be used
10118 in mode MODE; the returned value will always be between 1 and the
10119 number of bits in MODE. */
10121 static rtx
10123 scalar_int_mode mode,
10125 {
10126 rtx tem;
10139 && !REGNO_REG_SET_P
10142 {
10145 }
10156 }
10157 \f
10158 /* Return the number of "extended" bits there are in X, when interpreted
10159 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10160 unsigned quantities, this is the number of high-order zero bits.
10161 For signed quantities, this is the number of copies of the sign bit
10162 minus 1. In both case, this function returns the number of "spare"
10163 bits. For example, if two quantities for which this function returns
10164 at least 1 are added, the addition is known not to overflow.
10166 This function will always return 0 unless called during combine, which
10167 implies that it must be called from a define_split. */
10169 unsigned int
10171 {
10175 scalar_int_mode int_mode;
10183 }
10185 /* This function is called from `simplify_shift_const' to merge two
10186 outer operations. Specifically, we have already found that we need
10187 to perform operation *POP0 with constant *PCONST0 at the outermost
10188 position. We would now like to also perform OP1 with constant CONST1
10189 (with *POP0 being done last).
10191 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10192 the resulting operation. *PCOMP_P is set to 1 if we would need to
10193 complement the innermost operand, otherwise it is unchanged.
10195 MODE is the mode in which the operation will be done. No bits outside
10196 the width of this mode matter. It is assumed that the width of this mode
10197 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10199 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10200 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10201 result is simply *PCONST0.
10203 If the resulting operation cannot be expressed as one operation, we
10204 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10206 static int
10207 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10208 {
10215 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10219 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10220 if OP0 is SET. */
10229 {
10231 {
10249 }
10250 }
10252 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10256 /* If the two constants aren't the same, we can't do anything. The
10257 remaining six cases can all be done. */
10261 else
10263 {
10266 /* (a & b) | b == b */
10269 /* (a ^ b) | b == a | b */
10270 {;}
10275 /* (a & b) ^ b == (~a) & b */
10278 /* (a | b) ^ b == a & ~b */
10284 /* (a | b) & b == b */
10287 /* (a ^ b) & b) == (~a) & b */
10292 }
10294 /* Check for NO-OP cases. */
10307 /* ??? Slightly redundant with the above mask, but not entirely.
10308 Moving this above means we'd have to sign-extend the mode mask
10309 for the final test. */
10314 }
10315 \f
10316 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10317 the shift in. The original shift operation CODE is performed on OP in
10318 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10319 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10320 result of the shift is subject to operation OUTER_CODE with operand
10321 OUTER_CONST. */
10323 static scalar_int_mode
10327 {
10330 /* In general we can't perform in wider mode for right shift and rotate. */
10332 {
10334 /* We can still widen if the bits brought in from the left are identical
10335 to the sign bit of ORIG_MODE. */
10343 /* Similarly here but with zero bits. */
10348 /* We can also widen if the bits brought in will be masked off. This
10349 operation is performed in ORIG_MODE. */
10351 {
10357 }
10358 /* fall through */
10368 }
10369 }
10371 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10372 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10373 if we cannot simplify it. Otherwise, return a simplified value.
10375 The shift is normally computed in the widest mode we find in VAROP, as
10376 long as it isn't a different number of words than RESULT_MODE. Exceptions
10377 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10379 static rtx
10382 {
10387 machine_mode shift_mode;
10389 unsigned int mode_words
10391 /* We form (outer_op (code varop count) (outer_const)). */
10397 /* Make sure and truncate the "natural" shift on the way in. We don't
10398 want to do this inside the loop as it makes it more difficult to
10399 combine shifts. */
10403 /* If we were given an invalid count, don't do anything except exactly
10404 what was requested. */
10411 /* Unless one of the branches of the `if' in this loop does a `continue',
10412 we will `break' the loop after the `if'. */
10415 {
10416 /* If we have an operand of (clobber (const_int 0)), fail. */
10420 /* Convert ROTATERT to ROTATE. */
10422 {
10426 }
10430 {
10431 /* We only change the modes of scalar shifts. */
10437 }
10439 scalar_int_mode shift_unit_mode
10442 /* Handle cases where the count is greater than the size of the mode
10443 minus 1. For ASHIFT, use the size minus one as the count (this can
10444 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10445 take the count modulo the size. For other shifts, the result is
10446 zero.
10448 Since these shifts are being produced by the compiler by combining
10449 multiple operations, each of which are defined, we know what the
10450 result is supposed to be. */
10453 {
10458 else
10459 {
10460 /* We can't simply return zero because there may be an
10461 outer op. */
10465 }
10466 }
10468 /* If we discovered we had to complement VAROP, leave. Making a NOT
10469 here would cause an infinite loop. */
10474 {
10475 /* An arithmetic right shift of a quantity known to be -1 or 0
10476 is a no-op. */
10480 {
10483 }
10485 /* If we are doing an arithmetic right shift and discarding all but
10486 the sign bit copies, this is equivalent to doing a shift by the
10487 bitsize minus one. Convert it into that shift because it will
10488 often allow other simplifications. */
10495 /* We simplify the tests below and elsewhere by converting
10496 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10497 `make_compound_operation' will convert it to an ASHIFTRT for
10498 those machines (such as VAX) that don't have an LSHIFTRT. */
10503 shift_unit_mode)))
10515 }
10518 {
10525 {
10528 }
10532 /* The following rules apply only to scalars. */
10537 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10538 minus the width of a smaller mode, we can do this with a
10539 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10546 {
10555 }
10559 /* The following rules apply only to scalars. */
10565 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10566 the same number of words as what we've seen so far. Then store
10567 the widest mode in MODE. */
10573 == mode_words
10575 {
10580 }
10584 /* Some machines use MULT instead of ASHIFT because MULT
10585 is cheaper. But it is still better on those machines to
10586 merge two shifts into one. */
10589 {
10590 varop
10596 }
10600 /* Similar, for when divides are cheaper. */
10603 {
10604 varop
10610 }
10614 /* If we are extracting just the sign bit of an arithmetic
10615 right shift, that shift is not needed. However, the sign
10616 bit of a wider mode may be different from what would be
10617 interpreted as the sign bit in a narrower mode, so, if
10618 the result is narrower, don't discard the shift. */
10623 {
10626 }
10628 /* fall through */
10633 /* The following rules apply only to scalars. */
10640 /* Here we have two nested shifts. The result is usually the
10641 AND of a new shift with a mask. We compute the result below. */
10647 {
10651 rtx mask_rtx;
10653 /* We have one common special case. We can't do any merging if
10654 the inner code is an ASHIFTRT of a smaller mode. However, if
10655 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10656 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10657 we can convert it to
10658 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10659 This simplifies certain SIGN_EXTEND operations. */
10663 {
10664 /* C3 has the low-order C1 bits zero. */
10676 }
10678 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10679 than C1 high-order bits equal to the sign bit, we can convert
10680 this to either an ASHIFT or an ASHIFTRT depending on the
10681 two counts.
10683 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10689 {
10693 {
10696 }
10699 }
10701 /* There are some cases we can't do. If CODE is ASHIFTRT,
10702 we can only do this if FIRST_CODE is also ASHIFTRT.
10704 We can't do the case when CODE is ROTATE and FIRST_CODE is
10705 ASHIFTRT.
10707 If the mode of this shift is not the mode of the outer shift,
10708 we can't do this if either shift is a right shift or ROTATE.
10710 Finally, we can't do any of these if the mode is too wide
10711 unless the codes are the same.
10713 Handle the case where the shift codes are the same
10714 first. */
10717 {
10726 }
10737 /* To compute the mask to apply after the shift, shift the
10738 nonzero bits of the inner shift the same way the
10739 outer shift will. */
10742 int_result_mode);
10744 mask_rtx
10748 /* Give up if we can't compute an outer operation to use. */
10756 /* If the shifts are in the same direction, we add the
10757 counts. Otherwise, we subtract them. */
10761 else
10764 /* If COUNT is positive, the new shift is usually CODE,
10765 except for the two exceptions below, in which case it is
10766 FIRST_CODE. If the count is negative, FIRST_CODE should
10767 always be used */
10777 }
10779 /* If we have (A << B << C) for any shift, we can convert this to
10780 (A << C << B). This wins if A is a constant. Only try this if
10781 B is not a constant. */
10786 {
10787 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10788 sure the result will be masked. See PR70222. */
10796 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10797 up outer sign extension (often left and right shift) is
10798 hardly more efficient than the original. See PR70429. */
10808 }
10812 /* The following rules apply only to scalars. */
10816 /* Make this fit the case below. */
10823 /* The following rules apply only to scalars. */
10829 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10830 with C the size of VAROP - 1 and the shift is logical if
10831 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10832 we have an (le X 0) operation. If we have an arithmetic shift
10833 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10834 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10842 {
10845 const0_rtx);
10851 }
10853 /* If we have (shift (logical)), move the logical to the outside
10854 to allow it to possibly combine with another logical and the
10855 shift to combine with another shift. This also canonicalizes to
10856 what a ZERO_EXTRACT looks like. Also, some machines have
10857 (and (shift)) insns. */
10860 /* We can't do this if we have (ashiftrt (xor)) and the
10861 constant has its sign bit set in shift_unit_mode with
10862 shift_unit_mode wider than result_mode. */
10866 shift_unit_mode))
10875 {
10878 }
10880 /* If we can't do that, try to simplify the shift in each arm of the
10881 logical expression, make a new logical expression, and apply
10882 the inverse distributive law. This also can't be done for
10883 (ashiftrt (xor)) where we've widened the shift and the constant
10884 changes the sign bit. */
10889 shift_unit_mode)))
10890 {
10902 }
10906 /* The following rules apply only to scalars. */
10911 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10912 says that the sign bit can be tested, FOO has mode MODE, C is
10913 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10914 that may be nonzero. */
10924 {
10928 }
10932 /* The following rules apply only to scalars. */
10937 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10938 than the number of bits in the mode is equivalent to A. */
10942 {
10946 }
10948 /* NEG commutes with ASHIFT since it is multiplication. Move the
10949 NEG outside to allow shifts to combine. */
10953 {
10956 }
10960 /* The following rules apply only to scalars. */
10965 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10966 is one less than the number of bits in the mode is
10967 equivalent to (xor A 1). */
10974 {
10978 }
10980 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10981 that might be nonzero in BAR are those being shifted out and those
10982 bits are known zero in FOO, we can replace the PLUS with FOO.
10983 Similarly in the other operand order. This code occurs when
10984 we are computing the size of a variable-size array. */
10991 {
10994 }
11002 {
11005 }
11007 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11018 {
11021 }
11023 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11024 signbit', and attempt to change the PLUS to an XOR and move it to
11025 the outer operation as is done above in the AND/IOR/XOR case
11026 leg for shift(logical). See details in logical handling above
11027 for reasoning in doing so. */
11039 {
11042 }
11047 /* The following rules apply only to scalars. */
11052 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11053 with C the size of VAROP - 1 and the shift is logical if
11054 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11055 we have a (gt X 0) operation. If the shift is arithmetic with
11056 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11057 we have a (neg (gt X 0)) operation. */
11066 {
11069 const0_rtx);
11075 }
11079 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11080 if the truncate does not affect the value. */
11087 {
11090 varop_inner
11093 GEN_INT
11098 }
11103 }
11106 }
11110 {
11111 /* We only change the modes of scalar shifts. */
11116 }
11118 /* We have now finished analyzing the shift. The result should be
11119 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11120 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11121 to the result of the shift. OUTER_CONST is the relevant constant,
11122 but we must turn off all bits turned off in the shift. */
11130 /* Make a SUBREG if necessary. If we can't make it, fail. */
11135 /* If we have an outer operation and we just made a shift, it is
11136 possible that we could have simplified the shift were it not
11137 for the outer operation. So try to do the simplification
11138 recursively. */
11142 else
11148 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11149 turn off all the bits that the shift would have turned off. */
11151 /* We only change the modes of scalar shifts. */
11155 /* Do the remainder of the processing in RESULT_MODE. */
11158 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11159 operation. */
11164 {
11174 {
11175 /* This means that we have determined that the result is
11176 equivalent to a constant. This should be rare. */
11179 }
11182 else
11185 }
11188 }
11190 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11191 The result of the shift is RESULT_MODE. If we cannot simplify it,
11192 return X or, if it is NULL, synthesize the expression with
11193 simplify_gen_binary. Otherwise, return a simplified value.
11195 The shift is normally computed in the widest mode we find in VAROP, as
11196 long as it isn't a different number of words than RESULT_MODE. Exceptions
11197 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11199 static rtx
11202 {
11212 }
11214 \f
11215 /* A subroutine of recog_for_combine. See there for arguments and
11216 return value. */
11218 static int
11220 {
11222 rtx pat_without_clobbers;
11230 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11231 we use to indicate that something didn't match. If we find such a
11232 thing, force rejection. */
11246 {
11249 else
11252 }
11254 /* If it isn't, there is the possibility that we previously had an insn
11255 that clobbered some register as a side effect, but the combined
11256 insn doesn't need to do that. So try once more without the clobbers
11257 unless this represents an ASM insn. */
11261 {
11266 {
11269 pos++;
11270 }
11280 {
11283 else
11286 }
11287 }
11294 /* Recognize all noop sets, these will be killed by followup pass. */
11298 /* If we had any clobbers to add, make a new pattern than contains
11299 them. Then check to make sure that all of them are dead. */
11301 {
11311 else
11318 {
11323 {
11327 }
11328 }
11330 }
11334 {
11342 /* Allow targets to reject combined insn. */
11344 {
11347 dump_file);
11349 /* Callers expect recog_for_combine to strip
11350 clobbers from the pattern on failure. */
11355 }
11360 }
11366 }
11368 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11369 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11370 Return whether anything was so changed. */
11372 static bool
11374 {
11380 {
11392 {
11401 else
11405 }
11411 {
11417 }
11422 {
11426 }
11427 else
11433 {
11436 }
11440 }
11447 scalar_int_mode mode;
11453 {
11467 else
11475 }
11478 }
11480 /* Like recog, but we receive the address of a pointer to a new pattern.
11481 We try to match the rtx that the pointer points to.
11482 If that fails, we may try to modify or replace the pattern,
11483 storing the replacement into the same pointer object.
11485 Modifications include deletion or addition of CLOBBERs. If the
11486 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11487 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11488 (and undo if that fails).
11490 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11491 the CLOBBERs are placed.
11493 The value is the final insn code from the pattern ultimately matched,
11494 or -1. */
11496 static int
11498 {
11510 {
11513 {
11517 }
11518 }
11521 {
11526 }
11529 }
11530 \f
11531 /* Like gen_lowpart_general but for use by combine. In combine it
11532 is not possible to create any new pseudoregs. However, it is
11533 safe to create invalid memory addresses, because combine will
11534 try to recognize them and all they will do is make the combine
11535 attempt fail.
11537 If for some reason this cannot do its job, an rtx
11538 (clobber (const_int 0)) is returned.
11539 An insn containing that will not be recognized. */
11541 static rtx
11543 {
11547 rtx result;
11552 /* We can only support MODE being wider than a word if X is a
11553 constant integer or has a mode the same size. */
11558 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11559 won't know what to do. So we will strip off the SUBREG here and
11560 process normally. */
11562 {
11565 /* For use in case we fall down into the address adjustments
11566 further below, we need to adjust the known mode and size of
11567 x; imode and isize, since we just adjusted x. */
11574 }
11582 {
11585 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11586 address. */
11591 /* If we want to refer to something bigger than the original memref,
11592 generate a paradoxical subreg instead. That will force a reload
11593 of the original memref X. */
11600 /* Adjust the address so that the address-after-the-data is
11601 unchanged. */
11606 }
11608 /* If X is a comparison operator, rewrite it in a new mode. This
11609 probably won't match, but may allow further simplifications. */
11613 /* If we couldn't simplify X any other way, just enclose it in a
11614 SUBREG. Normally, this SUBREG won't match, but some patterns may
11615 include an explicit SUBREG or we may simplify it further in combine. */
11616 else
11617 {
11618 rtx res;
11621 {
11626 }
11630 }
11632 fail:
11634 }
11635 \f
11636 /* Try to simplify a comparison between OP0 and a constant OP1,
11637 where CODE is the comparison code that will be tested, into a
11638 (CODE OP0 const0_rtx) form.
11640 The result is a possibly different comparison code to use.
11641 *POP1 may be updated. */
11643 static enum rtx_code
11646 {
11647 scalar_int_mode int_mode;
11650 /* Get the constant we are comparing against and turn off all bits
11651 not on in our mode. */
11655 /* If we are comparing against a constant power of two and the value
11656 being compared can only have that single bit nonzero (e.g., it was
11657 `and'ed with that bit), we can replace this with a comparison
11658 with zero. */
11667 {
11670 }
11672 /* Similarly, if we are comparing a value known to be either -1 or
11673 0 with -1, change it to the opposite comparison against zero. */
11679 {
11682 }
11684 /* Do some canonicalizations based on the comparison code. We prefer
11685 comparisons against zero and then prefer equality comparisons.
11686 If we can reduce the size of a constant, we will do that too. */
11688 {
11690 /* < C is equivalent to <= (C - 1) */
11692 {
11695 /* ... fall through to LE case below. */
11697 }
11698 else
11702 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11704 {
11707 }
11709 /* If we are doing a <= 0 comparison on a value known to have
11710 a zero sign bit, we can replace this with == 0. */
11721 /* >= C is equivalent to > (C - 1). */
11723 {
11726 /* ... fall through to GT below. */
11728 }
11729 else
11733 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11735 {
11738 }
11740 /* If we are doing a > 0 comparison on a value known to have
11741 a zero sign bit, we can replace this with != 0. */
11752 /* < C is equivalent to <= (C - 1). */
11754 {
11757 /* ... fall through ... */
11758 }
11759 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11764 {
11768 }
11769 else
11773 /* unsigned <= 0 is equivalent to == 0 */
11776 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11780 == ((HOST_WIDE_INT_1U
11782 {
11785 }
11789 /* >= C is equivalent to > (C - 1). */
11791 {
11794 /* ... fall through ... */
11795 }
11797 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11802 {
11806 }
11807 else
11811 /* unsigned > 0 is equivalent to != 0 */
11814 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11818 == (HOST_WIDE_INT_1U
11820 {
11823 }
11828 }
11832 }
11833 \f
11834 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11835 comparison code that will be tested.
11837 The result is a possibly different comparison code to use. *POP0 and
11838 *POP1 may be updated.
11840 It is possible that we might detect that a comparison is either always
11841 true or always false. However, we do not perform general constant
11842 folding in combine, so this knowledge isn't useful. Such tautologies
11843 should have been detected earlier. Hence we ignore all such cases. */
11845 static enum rtx_code
11847 {
11853 opt_scalar_int_mode tmode_iter;
11855 /* Try a few ways of applying the same transformation to both operands. */
11857 {
11858 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11859 so check specially. */
11878 {
11881 }
11883 /* If both operands are the same constant shift, see if we can ignore the
11884 shift. We can if the shift is a rotate or if the bits shifted out of
11885 this shift are known to be zero for both inputs and if the type of
11886 comparison is compatible with the shift. */
11899 {
11912 else
11914 }
11916 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11917 SUBREGs are of the same mode, and, in both cases, the AND would
11918 be redundant if the comparison was done in the narrower mode,
11919 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11920 and the operand's possibly nonzero bits are 0xffffff01; in that case
11921 if we only care about QImode, we don't need the AND). This case
11922 occurs if the output mode of an scc insn is not SImode and
11923 STORE_FLAG_VALUE == 1 (e.g., the 386).
11925 Similarly, check for a case where the AND's are ZERO_EXTEND
11926 operations from some narrower mode even though a SUBREG is not
11927 present. */
11932 {
11949 {
11953 /* The resulting comparison is always unsigned since we masked
11954 off the original sign bit. */
11958 }
11964 {
11970 }
11974 }
11976 /* If both operands are NOT, we can strip off the outer operation
11977 and adjust the comparison code for swapped operands; similarly for
11978 NEG, except that this must be an equality comparison. */
11984 else
11986 }
11988 /* If the first operand is a constant, swap the operands and adjust the
11989 comparison code appropriately, but don't do this if the second operand
11990 is already a constant integer. */
11992 {
11995 }
11997 /* We now enter a loop during which we will try to simplify the comparison.
11998 For the most part, we only are concerned with comparisons with zero,
11999 but some things may really be comparisons with zero but not start
12000 out looking that way. */
12003 {
12005 scalar_int_mode int_mode;
12009 HOST_WIDE_INT const_op;
12011 /* We only want to handle integral modes. This catches VOIDmode,
12012 CCmode, and the floating-point modes. An exception is that we
12013 can handle VOIDmode if OP0 is a COMPARE or a comparison
12014 operation. */
12021 /* Try to simplify the compare to constant, possibly changing the
12022 comparison op, and/or changing op1 to zero. */
12026 /* Compute some predicates to simplify code below. */
12033 /* If this is a sign bit comparison and we can do arithmetic in
12034 MODE, say that we will only be needing the sign bit of OP0. */
12039 HOST_WIDE_INT_1U
12044 {
12045 /* We can't do anything if OP0 is a condition code value, rather
12046 than an actual data value. */
12052 /* Get the two operands being compared. */
12055 else
12058 /* Check for the cases where we simply want the result of the
12059 earlier test or the opposite of that result. */
12063 {
12067 else
12071 {
12076 }
12077 }
12079 }
12085 /* Now try cases based on the opcode of OP0. If none of the cases
12086 does a "continue", we exit this loop immediately after the
12087 switch. */
12092 {
12094 /* If we are extracting a single bit from a variable position in
12095 a constant that has only a single bit set and are comparing it
12096 with zero, we can convert this into an equality comparison
12097 between the position and the location of the single bit. */
12098 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12099 have already reduced the shift count modulo the word size. */
12105 {
12113 /* Result is nonzero iff shift count is equal to I. */
12116 }
12118 /* fall through */
12123 {
12126 }
12130 /* If testing for equality, we can take the NOT of the constant. */
12133 {
12137 }
12139 /* If just looking at the sign bit, reverse the sense of the
12140 comparison. */
12142 {
12146 }
12150 /* If testing for equality, we can take the NEG of the constant. */
12153 {
12157 }
12159 /* The remaining cases only apply to comparisons with zero. */
12163 /* When X is ABS or is known positive,
12164 (neg X) is < 0 if and only if X != 0. */
12172 {
12176 }
12178 /* If we have NEG of something whose two high-order bits are the
12179 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12181 {
12185 }
12189 /* If we are testing equality and our count is a constant, we
12190 can perform the inverse operation on our RHS. */
12194 {
12198 }
12200 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12201 a particular bit. Convert it to an AND of a constant of that
12202 bit. This will be converted into a ZERO_EXTRACT. */
12206 {
12208 (HOST_WIDE_INT_1U
12213 }
12215 /* Fall through. */
12218 /* ABS is ignorable inside an equality comparison with zero. */
12220 {
12223 }
12227 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12228 (compare FOO CONST) if CONST fits in FOO's mode and we
12229 are either testing inequality or have an unsigned
12230 comparison with ZERO_EXTEND or a signed comparison with
12231 SIGN_EXTEND. But don't do it if we don't have a compare
12232 insn of the given mode, since we'd have to revert it
12233 later on, and then we wouldn't know whether to sign- or
12234 zero-extend. */
12236 && ! unsigned_comparison_p
12240 {
12243 }
12247 /* Check for the case where we are comparing A - C1 with C2, that is
12249 (subreg:MODE (plus (A) (-C1))) op (C2)
12251 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12252 comparison in the wider mode. One of the following two conditions
12253 must be true in order for this to be valid:
12255 1. The mode extension results in the same bit pattern being added
12256 on both sides and the comparison is equality or unsigned. As
12257 C2 has been truncated to fit in MODE, the pattern can only be
12258 all 0s or all 1s.
12260 2. The mode extension results in the sign bit being copied on
12261 each side.
12263 The difficulty here is that we have predicates for A but not for
12264 (A - C1) so we need to check that C1 is within proper bounds so
12265 as to perturbate A as little as possible. */
12274 {
12282 /* (A - C1) zero-extends if it is positive and sign-extends
12283 if it is negative, C2 both zero- and sign-extends. */
12287 /* (A - C1) sign-extends if it is positive and 1-extends
12288 if it is negative, C2 both sign- and 1-extends. */
12295 /* (A - C1) always sign-extends, like C2. */
12299 {
12302 }
12303 }
12305 /* If the inner mode is narrower and we are extracting the low part,
12306 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12308 ;
12317 {
12318 /* Remove outer subregs that don't do anything. */
12323 {
12327 }
12329 }
12330 else
12333 /* FALLTHROUGH */
12342 {
12345 }
12349 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12350 this for equality comparisons due to pathological cases involving
12351 overflows. */
12355 {
12359 }
12361 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12364 {
12368 }
12372 /* We used to optimize signed comparisons against zero, but that
12373 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12374 arrive here as equality comparisons, or (GEU, LTU) are
12375 optimized away. No need to special-case them. */
12377 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12378 (eq B (minus A C)), whichever simplifies. We can only do
12379 this for equality comparisons due to pathological cases involving
12380 overflows. */
12384 {
12388 }
12393 {
12397 }
12399 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12400 of bits in X minus 1, is one iff X > 0. */
12405 {
12409 }
12413 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12414 if C is zero or B is a constant. */
12418 {
12422 }
12427 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12428 iff X <= 0. */
12432 {
12436 }
12440 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12441 will be converted to a ZERO_EXTRACT later. */
12445 {
12450 }
12452 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12453 zero and X is a comparison and C1 and C2 describe only bits set
12454 in STORE_FLAG_VALUE, we can compare with X. */
12462 {
12469 {
12472 }
12473 }
12475 /* If we are doing an equality comparison of an AND of a bit equal
12476 to the sign bit, replace this with a LT or GE comparison of
12477 the underlying value. */
12484 {
12488 }
12490 /* If this AND operation is really a ZERO_EXTEND from a narrower
12491 mode, the constant fits within that mode, and this is either an
12492 equality or unsigned comparison, try to do this comparison in
12493 the narrower mode.
12495 Note that in:
12497 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12498 -> (ne:DI (reg:SI 4) (const_int 0))
12500 unless TRULY_NOOP_TRUNCATION allows it or the register is
12501 known to hold a value of the required mode the
12502 transformation is invalid. */
12510 {
12513 }
12515 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12516 fits in both M1 and M2 and the SUBREG is either paradoxical
12517 or represents the low part, permute the SUBREG and the AND
12518 and try again. */
12521 {
12523 /* Require an integral mode, to avoid creating something like
12524 (AND:SF ...). */
12527 /* It is unsafe to commute the AND into the SUBREG if the
12528 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12529 not defined. As originally written the upper bits
12530 have a defined value due to the AND operation.
12531 However, if we commute the AND inside the SUBREG then
12532 they no longer have defined values and the meaning of
12533 the code has been changed.
12534 Also C1 should not change value in the smaller mode,
12535 see PR67028 (a positive C1 can become negative in the
12536 smaller mode, so that the AND does no longer mask the
12537 upper bits). */
12538 && ((WORD_REGISTER_OPERATIONS
12550 {
12556 }
12557 }
12559 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12563 {
12568 }
12570 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12571 (eq (and (lshiftrt X) 1) 0).
12572 Also handle the case where (not X) is expressed using xor. */
12576 {
12586 == HOST_WIDE_INT_1U
12588 {
12589 op0
12594 }
12595 }
12599 /* If we have (compare (ashift FOO N) (const_int C)) and
12600 the high order N bits of FOO (N+1 if an inequality comparison)
12601 are known to be zero, we can do this by comparing FOO with C
12602 shifted right N bits so long as the low-order N bits of C are
12603 zero. */
12615 {
12616 /* We must perform a logical shift, not an arithmetic one,
12617 as we want the top N bits of C to be zero. */
12624 }
12626 /* If we are doing a sign bit comparison, it means we are testing
12627 a particular bit. Convert it to the appropriate AND. */
12630 {
12632 (HOST_WIDE_INT_1U
12637 }
12639 /* If this an equality comparison with zero and we are shifting
12640 the low bit to the sign bit, we can convert this to an AND of the
12641 low-order bit. */
12645 {
12648 }
12652 /* If this is an equality comparison with zero, we can do this
12653 as a logical shift, which might be much simpler. */
12656 {
12661 }
12663 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12664 do the comparison in a narrower mode. */
12674 {
12677 }
12679 /* Likewise if OP0 is a PLUS of a sign extension with a
12680 constant, which is usually represented with the PLUS
12681 between the shifts. */
12693 {
12701 new_const);
12703 }
12705 /* FALLTHROUGH */
12707 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12708 the low order N bits of FOO are known to be zero, we can do this
12709 by comparing FOO with C shifted left N bits so long as no
12710 overflow occurs. Even if the low order N bits of FOO aren't known
12711 to be zero, if the comparison is >= or < we can use the same
12712 optimization and for > or <= by setting all the low
12713 order N bits in the comparison constant. */
12724 {
12725 unsigned HOST_WIDE_INT low_bits
12727 & ((HOST_WIDE_INT_1U
12730 {
12731 /* If the shift was logical, then we must make the condition
12732 unsigned. */
12741 const_op
12746 }
12747 }
12749 /* If we are using this shift to extract just the sign bit, we
12750 can replace this with an LT or GE comparison. */
12755 {
12759 }
12764 }
12767 }
12769 /* Now make any compound operations involved in this comparison. Then,
12770 check for an outmost SUBREG on OP0 that is not doing anything or is
12771 paradoxical. The latter transformation must only be performed when
12772 it is known that the "extra" bits will be the same in op0 and op1 or
12773 that they don't matter. There are three cases to consider:
12775 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12776 care bits and we can assume they have any convenient value. So
12777 making the transformation is safe.
12779 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12780 In this case the upper bits of op0 are undefined. We should not make
12781 the simplification in that case as we do not know the contents of
12782 those bits.
12784 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12785 In that case we know those bits are zeros or ones. We must also be
12786 sure that they are the same as the upper bits of op1.
12788 We can never remove a SUBREG for a non-equality comparison because
12789 the sign bit is in a different place in the underlying object. */
12802 {
12804 {
12805 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12806 implemented. */
12808 {
12811 }
12812 }
12816 {
12821 }
12822 }
12824 /* We now do the opposite procedure: Some machines don't have compare
12825 insns in all modes. If OP0's mode is an integer mode smaller than a
12826 word and we can't do a compare in that mode, see if there is a larger
12827 mode for which we can do the compare. There are a number of cases in
12828 which we can use the wider mode. */
12834 {
12839 {
12842 /* If this is a test for negative, we can make an explicit
12843 test of the sign bit. Test this first so we can use
12844 a paradoxical subreg to extend OP0. */
12848 {
12849 unsigned HOST_WIDE_INT sign
12856 }
12858 /* If the only nonzero bits in OP0 and OP1 are those in the
12859 narrower mode and this is an equality or unsigned comparison,
12860 we can use the wider mode. Similarly for sign-extended
12861 values, in which case it is true for all comparisons. */
12878 {
12879 /* If OP0 is an AND and we don't have an AND in MODE either,
12880 make a new AND in the proper mode. */
12888 else
12889 {
12891 {
12896 }
12897 else
12898 {
12903 }
12905 }
12906 }
12907 }
12908 }
12910 /* We may have changed the comparison operands. Re-canonicalize. */
12912 {
12915 }
12917 /* If this machine only supports a subset of valid comparisons, see if we
12918 can convert an unsupported one into a supported one. */
12925 }
12926 \f
12927 /* Utility function for record_value_for_reg. Count number of
12928 rtxs in X. */
12929 static int
12931 {
12938 {
12958 }
12969 }
12970 \f
12971 /* Utility function for following routine. Called when X is part of a value
12972 being stored into last_set_value. Sets last_set_table_tick
12973 for each register mentioned. Similar to mention_regs in cse.c */
12975 static void
12977 {
12983 {
12989 {
12992 }
12995 }
12999 {
13000 /* Check for identical subexpressions. If x contains
13001 identical subexpression we only have to traverse one of
13002 them. */
13004 {
13005 /* Note that at this point x1 has already been
13006 processed. */
13010 /* If x0 and x1 are identical then there is no need to
13011 process x0. */
13015 /* If x0 is identical to a subexpression of x1 then while
13016 processing x1, x0 has already been processed. Thus we
13017 are done with x. */
13022 /* If x1 is identical to a subexpression of x0 then we
13023 still have to process the rest of x0. */
13026 {
13029 }
13030 }
13033 }
13037 }
13039 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13040 are saying that the register is clobbered and we no longer know its
13041 value. If INSN is zero, don't update reg_stat[].last_set; this is
13042 only permitted with VALUE also zero and is used to invalidate the
13043 register. */
13045 static void
13047 {
13053 /* If VALUE contains REG and we have a previous value for REG, substitute
13054 the previous value. */
13056 {
13057 rtx tem;
13059 /* Set things up so get_last_value is allowed to see anything set up to
13060 our insn. */
13064 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13065 it isn't going to be useful and will take a lot of time to process,
13066 so just use the CLOBBER. */
13069 {
13075 {
13076 /* If there are two or more occurrences of REG in VALUE,
13077 prevent the value from growing too much. */
13080 }
13083 }
13084 }
13086 /* For each register modified, show we don't know its value, that
13087 we don't know about its bitwise content, that its value has been
13088 updated, and that we don't know the location of the death of the
13089 register. */
13091 {
13103 }
13105 /* Mark registers that are being referenced in this value. */
13109 /* Now update the status of each register being set.
13110 If someone is using this register in this block, set this register
13111 to invalid since we will get confused between the two lives in this
13112 basic block. This makes using this register always invalid. In cse, we
13113 scan the table to invalidate all entries using this register, but this
13114 is too much work for us. */
13117 {
13123 else
13125 }
13127 /* The value being assigned might refer to X (like in "x++;"). In that
13128 case, we must replace it with (clobber (const_int 0)) to prevent
13129 infinite loops. */
13132 {
13136 }
13138 /* For the main register being modified, update the value, the mode, the
13139 nonzero bits, and the number of sign bit copies. */
13144 {
13152 rsp->last_set_sign_bit_copies
13154 }
13155 }
13157 /* Called via note_stores from record_dead_and_set_regs to handle one
13158 SET or CLOBBER in an insn. DATA is the instruction in which the
13159 set is occurring. */
13161 static void
13163 {
13170 {
13174 }
13177 {
13178 /* If we are setting the whole register, we know its value. Otherwise
13179 show that we don't know the value. We can handle SUBREG in
13180 some cases. */
13191 else
13193 }
13195 /* Ignore pushes, they clobber nothing. */
13198 }
13200 /* Update the records of when each REG was most recently set or killed
13201 for the things done by INSN. This is the last thing done in processing
13202 INSN in the combiner loop.
13204 We update reg_stat[], in particular fields last_set, last_set_value,
13205 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13206 last_death, and also the similar information mem_last_set (which insn
13207 most recently modified memory) and last_call_luid (which insn was the
13208 most recent subroutine call). */
13210 static void
13212 {
13213 rtx link;
13217 {
13220 {
13225 {
13230 }
13231 }
13234 }
13237 {
13238 hard_reg_set_iterator hrsi;
13240 {
13252 }
13256 /* We can't combine into a call pattern. Remember, though, that
13257 the return value register is set at this LUID. We could
13258 still replace a register with the return value from the
13259 wrong subroutine call! */
13261 }
13262 else
13264 }
13266 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13267 register present in the SUBREG, so for each such SUBREG go back and
13268 adjust nonzero and sign bit information of the registers that are
13269 known to have some zero/sign bits set.
13271 This is needed because when combine blows the SUBREGs away, the
13272 information on zero/sign bits is lost and further combines can be
13273 missed because of that. */
13275 static void
13277 {
13279 rtx set;
13287 {
13296 {
13299 }
13303 {
13306 }
13309 {
13312 }
13313 else
13315 }
13316 }
13318 /* Check if X, a register, is known to contain a value already
13319 truncated to MODE. In this case we can use a subreg to refer to
13320 the truncated value even though in the generic case we would need
13321 an explicit truncation. */
13323 static bool
13325 {
13337 }
13339 /* If X is a hard reg or a subreg record the mode that the register is
13340 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
13341 to turn a truncate into a subreg using this information. Return true
13342 if traversing X is complete. */
13344 static bool
13346 {
13347 machine_mode truncated_mode;
13351 {
13363 }
13364 /* ??? For hard-regs we now record everything. We might be able to
13365 optimize this using last_set_mode. */
13368 else
13375 {
13378 }
13381 }
13383 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13384 the modes they are used in. This can help truning TRUNCATEs into
13385 SUBREGs. */
13387 static void
13389 {
13394 }
13396 /* Scan X for promoted SUBREGs. For each one found,
13397 note what it implies to the registers used in it. */
13399 static void
13401 {
13406 else
13407 {
13413 {
13423 }
13424 }
13425 }
13426 \f
13427 /* Verify that all the registers and memory references mentioned in *LOC are
13428 still valid. *LOC was part of a value set in INSN when label_tick was
13429 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13430 the invalid references with (clobber (const_int 0)) and return 1. This
13431 replacement is useful because we often can get useful information about
13432 the form of a value (e.g., if it was produced by a shift that always
13433 produces -1 or 0) even though we don't know exactly what registers it
13434 was produced from. */
13436 static int
13438 {
13445 {
13451 {
13454 /* If this is a pseudo-register that was only set once and not
13455 live at the beginning of the function, it is always valid. */
13459 && (!REGNO_REG_SET_P
13461 regno)))
13463 {
13467 }
13468 }
13471 }
13472 /* If this is a memory reference, make sure that there were no stores after
13473 it that might have clobbered the value. We don't have alias info, so we
13474 assume any store invalidates it. Moreover, we only have local UIDs, so
13475 we also assume that there were stores in the intervening basic blocks. */
13478 {
13482 }
13485 {
13487 {
13488 /* Check for identical subexpressions. If x contains
13489 identical subexpression we only have to traverse one of
13490 them. */
13492 {
13493 /* Note that at this point x0 has already been checked
13494 and found valid. */
13498 /* If x0 and x1 are identical then x is also valid. */
13502 /* If x1 is identical to a subexpression of x0 then
13503 while checking x0, x1 has already been checked. Thus
13504 it is valid and so as x. */
13509 /* If x0 is identical to a subexpression of x1 then x is
13510 valid iff the rest of x1 is valid. */
13513 return
13517 }
13522 }
13528 }
13530 /* If we haven't found a reason for it to be invalid, it is valid. */
13532 }
13534 /* Get the last value assigned to X, if known. Some registers
13535 in the value may be replaced with (clobber (const_int 0)) if their value
13536 is known longer known reliably. */
13538 static rtx
13540 {
13542 rtx value;
13545 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13546 then convert it to the desired mode. If this is a paradoxical SUBREG,
13547 we cannot predict what values the "extra" bits might have. */
13561 /* If we don't have a value, or if it isn't for this basic block and
13562 it's either a hard register, set more than once, or it's a live
13563 at the beginning of the function, return 0.
13565 Because if it's not live at the beginning of the function then the reg
13566 is always set before being used (is never used without being set).
13567 And, if it's set only once, and it's always set before use, then all
13568 uses must have the same last value, even if it's not from this basic
13569 block. */
13576 || REGNO_REG_SET_P
13580 /* If the value was set in a later insn than the ones we are processing,
13581 we can't use it even if the register was only set once. */
13586 /* If fewer bits were set than what we are asked for now, we cannot use
13587 the value. */
13592 /* If the value has all its registers valid, return it. */
13596 /* Otherwise, make a copy and replace any invalid register with
13597 (clobber (const_int 0)). If that fails for some reason, return 0. */
13604 }
13605 \f
13606 /* Return nonzero if expression X refers to a REG or to memory
13607 that is set in an instruction more recent than FROM_LUID. */
13609 static int
13611 {
13617 {
13621 #ifdef PUSH_ROUNDING
13622 /* Don't allow uses of the stack pointer to be moved,
13623 because we don't know whether the move crosses a push insn. */
13626 #endif
13628 {
13634 }
13636 }
13644 {
13646 {
13651 }
13655 }
13657 }
13658 \f
13659 /* Define three variables used for communication between the following
13660 routines. */
13665 /* Function called via note_stores from reg_dead_at_p.
13667 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13668 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13670 static void
13672 {
13682 }
13684 /* Return nonzero if REG is known to be dead at INSN.
13686 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13687 referencing REG, it is dead. If we hit a SET referencing REG, it is
13688 live. Otherwise, see if it is live or dead at the start of the basic
13689 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13690 must be assumed to be always live. */
13692 static int
13694 {
13695 basic_block block;
13698 /* Set variables for reg_dead_at_p_1. */
13704 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13705 we allow the machine description to decide whether use-and-clobber
13706 patterns are OK. */
13708 {
13712 }
13714 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13715 beginning of basic block. */
13718 {
13720 {
13730 }
13736 }
13738 /* Look at live-in sets for the basic block that we were in. */
13744 }
13745 \f
13746 /* Note hard registers in X that are used. */
13748 static void
13750 {
13756 {
13760 CASE_CONST_ANY:
13765 /* CC0 must die in the insn after it is set, so we don't need to take
13766 special note of it here. */
13771 /* If we are clobbering a MEM, mark any hard registers inside the
13772 address as used. */
13779 /* A hard reg in a wide mode may really be multiple registers.
13780 If so, mark all of them just like the first. */
13782 {
13783 /* None of this applies to the stack, frame or arg pointers. */
13785 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13793 }
13797 {
13798 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13799 the address. */
13811 }
13816 }
13818 /* Recursively scan the operands of this expression. */
13820 {
13824 {
13828 {
13833 }
13834 }
13835 }
13836 }
13837 \f
13838 /* Remove register number REGNO from the dead registers list of INSN.
13840 Return the note used to record the death, if there was one. */
13842 rtx
13844 {
13851 }
13853 /* For each register (hardware or pseudo) used within expression X, if its
13854 death is in an instruction with luid between FROM_LUID (inclusive) and
13855 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13856 list headed by PNOTES.
13858 That said, don't move registers killed by maybe_kill_insn.
13860 This is done when X is being merged by combination into TO_INSN. These
13861 notes will then be distributed as needed. */
13863 static void
13866 {
13872 {
13876 /* Don't move the register if it gets killed in between from and to. */
13885 {
13888 /* It is possible for the call above to return 0. This can occur
13889 when last_death points to I2 or I1 that we combined with.
13890 In that case make a new note.
13892 We must also check for the case where X is a hard register
13893 and NOTE is a death note for a range of hard registers
13894 including X. In that case, we must put REG_DEAD notes for
13895 the remaining registers in place of NOTE. */
13899 {
13908 }
13910 /* If we didn't find any note, or if we found a REG_DEAD note that
13911 covers only part of the given reg, and we have a multi-reg hard
13912 register, then to be safe we must check for REG_DEAD notes
13913 for each register other than the first. They could have
13914 their own REG_DEAD notes lying around. */
13921 {
13928 else
13934 }
13937 {
13940 }
13941 else
13943 }
13946 }
13949 {
13954 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13955 that accesses one word of a multi-word item, some
13956 piece of everything register in the expression is used by
13957 this insn, so remove any old death. */
13958 /* ??? So why do we test for equality of the sizes? */
13967 {
13970 }
13972 /* If this is some other SUBREG, we know it replaces the entire
13973 value, so use that as the destination. */
13977 /* If this is a MEM, adjust deaths of anything used in the address.
13978 For a REG (the only other possibility), the entire value is
13979 being replaced so the old value is not used in this insn. */
13985 }
13994 {
13996 {
14001 }
14004 }
14005 }
14006 \f
14007 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14008 pattern of an insn. X must be a REG. */
14010 static int
14012 {
14016 {
14018 rtx target;
14025 else
14042 }
14050 }
14051 \f
14052 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14053 as appropriate. I3 and I2 are the insns resulting from the combination
14054 insns including FROM (I2 may be zero).
14056 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14057 not need REG_DEAD notes because they are being substituted for. This
14058 saves searching in the most common cases.
14060 Each note in the list is either ignored or placed on some insns, depending
14061 on the type of note. */
14063 static void
14066 {
14068 rtx tem_note;
14072 {
14077 {
14080 /* Doesn't matter much where we put this, as long as it's somewhere.
14081 It is preferable to keep these notes on branches, which is most
14082 likely to be i3. */
14089 else
14090 {
14093 }
14097 /* These notes must remain with the call or trapping instruction. */
14102 else
14103 {
14109 /* ??? Otherwise assume we've combined things such that we
14110 can now prove that the instructions can't trap. Drop the
14111 note in this case. */
14112 }
14116 /* ??? How to distribute between i3-i1. Assume i3 contains the
14117 entire adjustment. Assert i3 contains at least some adjust. */
14119 {
14121 /* fixup_args_size_notes looks at REG_NORETURN note,
14122 so ensure the note is placed there first. */
14124 {
14128 {
14134 }
14135 }
14137 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14138 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14141 && !ACCUMULATE_OUTGOING_ARGS
14143 }
14150 /* These notes must remain with the call. It should not be
14151 possible for both I2 and I3 to be a call. */
14154 else
14155 {
14158 }
14162 /* Any clobbers for i3 may still exist, and so we must process
14163 REG_UNUSED notes from that insn.
14165 Any clobbers from i2 or i1 can only exist if they were added by
14166 recog_for_combine. In that case, recog_for_combine created the
14167 necessary REG_UNUSED notes. Trying to keep any original
14168 REG_UNUSED notes from these insns can cause incorrect output
14169 if it is for the same register as the original i3 dest.
14170 In that case, we will notice that the register is set in i3,
14171 and then add a REG_UNUSED note for the destination of i3, which
14172 is wrong. However, it is possible to have REG_UNUSED notes from
14173 i2 or i1 for register which were both used and clobbered, so
14174 we keep notes from i2 or i1 if they will turn into REG_DEAD
14175 notes. */
14177 /* If this register is set or clobbered in I3, put the note there
14178 unless there is one already. */
14180 {
14188 }
14189 /* Otherwise, if this register is used by I3, then this register
14190 now dies here, so we must put a REG_DEAD note here unless there
14191 is one already. */
14197 {
14200 }
14206 /* These notes say something about results of an insn. We can
14207 only support them if they used to be on I3 in which case they
14208 remain on I3. Otherwise they are ignored.
14210 If the note refers to an expression that is not a constant, we
14211 must also ignore the note since we cannot tell whether the
14212 equivalence is still true. It might be possible to do
14213 slightly better than this (we only have a problem if I2DEST
14214 or I1DEST is present in the expression), but it doesn't
14215 seem worth the trouble. */
14223 /* These notes say something about how a register is used. They must
14224 be present on any use of the register in I2 or I3. */
14229 {
14232 else
14234 }
14239 /* This can show up in several ways -- either directly in the
14240 pattern, or hidden off in the constant pool with (or without?)
14241 a REG_EQUAL note. */
14242 /* ??? Ignore the without-reg_equal-note problem for now. */
14254 {
14257 else
14259 }
14261 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14262 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14263 there. */
14268 {
14275 }
14281 {
14289 }
14293 /* This note says something about the value of a register prior
14294 to the execution of an insn. It is too much trouble to see
14295 if the note is still correct in all situations. It is better
14296 to simply delete it. */
14300 /* If we replaced the right hand side of FROM_INSN with a
14301 REG_EQUAL note, the original use of the dying register
14302 will not have been combined into I3 and I2. In such cases,
14303 FROM_INSN is guaranteed to be the first of the combined
14304 instructions, so we simply need to search back before
14305 FROM_INSN for the previous use or set of this register,
14306 then alter the notes there appropriately.
14308 If the register is used as an input in I3, it dies there.
14309 Similarly for I2, if it is nonzero and adjacent to I3.
14311 If the register is not used as an input in either I3 or I2
14312 and it is not one of the registers we were supposed to eliminate,
14313 there are two possibilities. We might have a non-adjacent I2
14314 or we might have somehow eliminated an additional register
14315 from a computation. For example, we might have had A & B where
14316 we discover that B will always be zero. In this case we will
14317 eliminate the reference to A.
14319 In both cases, we must search to see if we can find a previous
14320 use of A and put the death note there. */
14326 else
14327 {
14338 && !(i2mod
14340 i2mod_old_rhs)))
14345 /* If the new I2 sets the same register that is marked dead
14346 in the note, we do not know where to put the note.
14347 Give up. */
14350 }
14353 {
14357 {
14359 {
14363 }
14365 /* If the register is being set at TEM_INSN, see if that is all
14366 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14367 into a REG_UNUSED note instead. Don't delete sets to
14368 global register vars. */
14372 {
14383 ;
14385 /* Verify that it was the set, and not a clobber that
14386 modified the register.
14388 CC0 targets must be careful to maintain setter/user
14389 pairs. If we cannot delete the setter due to side
14390 effects, mark the user with an UNUSED note instead
14391 of deleting it. */
14395 && (!HAVE_cc0
14399 {
14400 /* Move the notes and links of TEM_INSN elsewhere.
14401 This might delete other dead insns recursively.
14402 First set the pattern to something that won't use
14403 any register. */
14422 /* Delete the setter too. */
14424 {
14437 }
14438 }
14439 else
14440 {
14443 /* If there isn't already a REG_UNUSED note, put one
14444 here. Do not place a REG_DEAD note, even if
14445 the register is also used here; that would not
14446 match the algorithm used in lifetime analysis
14447 and can cause the consistency check in the
14448 scheduler to fail. */
14453 }
14454 }
14458 {
14461 /* If we are doing a 3->2 combination, and we have a
14462 register which formerly died in i3 and was not used
14463 by i2, which now no longer dies in i3 and is used in
14464 i2 but does not die in i2, and place is between i2
14465 and i3, then we may need to move a link from place to
14466 i2. */
14468 && from_insn
14471 {
14475 }
14477 }
14481 }
14483 }
14485 /* If the register is set or already dead at PLACE, we needn't do
14486 anything with this note if it is still a REG_DEAD note.
14487 We check here if it is set at all, not if is it totally replaced,
14488 which is what `dead_or_set_p' checks, so also check for it being
14489 set partially. */
14492 {
14498 {
14499 /* Unless the register previously died in PLACE, clear
14500 last_death. [I no longer understand why this is
14501 being done.] */
14505 }
14506 else
14509 /* If this is a death note for a hard reg that is occupying
14510 multiple registers, ensure that we are still using all
14511 parts of the object. If we find a piece of the object
14512 that is unused, we must arrange for an appropriate REG_DEAD
14513 note to be added for it. However, we can't just emit a USE
14514 and tag the note to it, since the register might actually
14515 be dead; so we recourse, and the recursive call then finds
14516 the previous insn that used this register. */
14519 {
14528 {
14531 }
14534 {
14535 /* Put only REG_DEAD notes for pieces that are
14536 not already dead or set. */
14540 {
14547 {
14549 NULL_RTX);
14553 NULL_RTX);
14554 }
14559 {
14561 {
14565 }
14569 {
14572 }
14573 }
14574 }
14577 }
14578 }
14579 }
14583 /* Any other notes should not be present at this point in the
14584 compilation. */
14586 }
14589 {
14592 }
14596 }
14597 }
14598 \f
14599 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14600 I3, I2, and I1 to new locations. This is also called to add a link
14601 pointing at I3 when I3's destination is changed. */
14603 static void
14605 {
14609 {
14616 /* If the insn that this link points to is a NOTE, ignore it. */
14625 {
14628 {
14644 }
14647 }
14648 else
14658 /* A LOG_LINK is defined as being placed on the first insn that uses
14659 a register and points to the insn that sets the register. Start
14660 searching at the next insn after the target of the link and stop
14661 when we reach a set of the register or the end of the basic block.
14663 Note that this correctly handles the link that used to point from
14664 I3 to I2. Also note that not much searching is typically done here
14665 since most links don't point very far away. */
14674 {
14678 }
14681 {
14684 }
14688 /* If we found a place to put the link, place it there unless there
14689 is already a link to the same insn as LINK at that point. */
14692 {
14700 {
14704 /* Set added_links_insn to the earliest insn we added a
14705 link to. */
14709 }
14710 }
14711 }
14712 }
14713 \f
14714 /* Check for any register or memory mentioned in EQUIV that is not
14715 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14716 of EXPR where some registers may have been replaced by constants. */
14718 static bool
14720 {
14723 {
14728 }
14730 }
14731 \f
14732 DEBUG_FUNCTION void
14734 {
14735 fprintf
14737 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14739 }
14741 void
14743 {
14744 fprintf
14746 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14748 }
14749 \f
14750 /* Try combining insns through substitution. */
14751 static unsigned int
14753 {
14763 rebuild_jump_labels_after_combine
14766 /* Combining insns may have turned an indirect jump into a
14767 direct jump. Rebuild the JUMP_LABEL fields of jumping
14768 instructions. */
14770 {
14777 }
14781 }
14786 {
14796 };
14799 {
14803 {}
14805 /* opt_pass methods: */
14808 {
14810 }
14816 rtl_opt_pass *
14818 {
14820 }