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1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
101 /* This file should be included last. */
108 #ifndef CHECK_STACK_LIMIT
109 #define CHECK_STACK_LIMIT (-1)
110 #endif
112 /* Return index of given mode in mult and division cost tables. */
113 #define MODE_INDEX(mode) \
114 ((mode) == QImode ? 0 \
115 : (mode) == HImode ? 1 \
116 : (mode) == SImode ? 2 \
117 : (mode) == DImode ? 3 \
118 : 4)
120 /* Processor costs (relative to an add) */
121 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
122 #define COSTS_N_BYTES(N) ((N) * 2)
124 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
133 const
156 in QImode, HImode and SImode.
157 Relative to reg-reg move (2). */
161 in SFmode, DFmode and XFmode */
163 in SFmode, DFmode and XFmode */
166 in SImode and DImode */
168 in SImode and DImode */
171 in SImode, DImode and TImode */
173 in SImode, DImode and TImode */
186 ix86_size_memcpy,
187 ix86_size_memset,
199 };
201 /* Processor costs (relative to an add) */
204 DUMMY_STRINGOP_ALGS};
207 DUMMY_STRINGOP_ALGS};
209 static const
232 in QImode, HImode and SImode.
233 Relative to reg-reg move (2). */
237 in SFmode, DFmode and XFmode */
239 in SFmode, DFmode and XFmode */
242 in SImode and DImode */
244 in SImode and DImode */
247 in SImode, DImode and TImode */
249 in SImode, DImode and TImode */
262 i386_memcpy,
263 i386_memset,
275 };
279 DUMMY_STRINGOP_ALGS};
282 DUMMY_STRINGOP_ALGS};
284 static const
307 in QImode, HImode and SImode.
308 Relative to reg-reg move (2). */
312 in SFmode, DFmode and XFmode */
314 in SFmode, DFmode and XFmode */
317 in SImode and DImode */
319 in SImode and DImode */
322 in SImode, DImode and TImode */
324 in SImode, DImode and TImode */
327 shared for code and data, so 4kB is
328 not really precise. */
339 i486_memcpy,
340 i486_memset,
352 };
356 DUMMY_STRINGOP_ALGS};
359 DUMMY_STRINGOP_ALGS};
361 static const
384 in QImode, HImode and SImode.
385 Relative to reg-reg move (2). */
389 in SFmode, DFmode and XFmode */
391 in SFmode, DFmode and XFmode */
394 in SImode and DImode */
396 in SImode and DImode */
399 in SImode, DImode and TImode */
401 in SImode, DImode and TImode */
414 pentium_memcpy,
415 pentium_memset,
427 };
429 static const
452 in QImode, HImode and SImode.
453 Relative to reg-reg move (2). */
457 in SFmode, DFmode and XFmode */
459 in SFmode, DFmode and XFmode */
462 in SImode and DImode */
464 in SImode and DImode */
467 in SImode, DImode and TImode */
469 in SImode, DImode and TImode */
482 pentium_memcpy,
483 pentium_memset,
495 };
497 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
498 (we ensure the alignment). For small blocks inline loop is still a
499 noticeable win, for bigger blocks either rep movsl or rep movsb is
500 way to go. Rep movsb has apparently more expensive startup time in CPU,
501 but after 4K the difference is down in the noise. */
506 DUMMY_STRINGOP_ALGS};
511 DUMMY_STRINGOP_ALGS};
512 static const
535 in QImode, HImode and SImode.
536 Relative to reg-reg move (2). */
540 in SFmode, DFmode and XFmode */
542 in SFmode, DFmode and XFmode */
545 in SImode and DImode */
547 in SImode and DImode */
550 in SImode, DImode and TImode */
552 in SImode, DImode and TImode */
565 pentiumpro_memcpy,
566 pentiumpro_memset,
578 };
582 DUMMY_STRINGOP_ALGS};
585 DUMMY_STRINGOP_ALGS};
586 static const
609 in QImode, HImode and SImode.
610 Relative to reg-reg move (2). */
614 in SFmode, DFmode and XFmode */
616 in SFmode, DFmode and XFmode */
620 in SImode and DImode */
622 in SImode and DImode */
625 in SImode, DImode and TImode */
627 in SImode, DImode and TImode */
640 geode_memcpy,
641 geode_memset,
653 };
657 DUMMY_STRINGOP_ALGS};
660 DUMMY_STRINGOP_ALGS};
661 static const
684 in QImode, HImode and SImode.
685 Relative to reg-reg move (2). */
689 in SFmode, DFmode and XFmode */
691 in SFmode, DFmode and XFmode */
694 in SImode and DImode */
696 in SImode and DImode */
699 in SImode, DImode and TImode */
701 in SImode, DImode and TImode */
705 have integrated l2 cache, but
706 optimizing for k6 is not important
707 enough to worry about that. */
717 k6_memcpy,
718 k6_memset,
730 };
732 /* For some reason, Athlon deals better with REP prefix (relative to loops)
733 compared to K8. Alignment becomes important after 8 bytes for memcpy and
734 128 bytes for memset. */
737 DUMMY_STRINGOP_ALGS};
740 DUMMY_STRINGOP_ALGS};
741 static const
764 in QImode, HImode and SImode.
765 Relative to reg-reg move (2). */
769 in SFmode, DFmode and XFmode */
771 in SFmode, DFmode and XFmode */
774 in SImode and DImode */
776 in SImode and DImode */
779 in SImode, DImode and TImode */
781 in SImode, DImode and TImode */
794 athlon_memcpy,
795 athlon_memset,
807 };
809 /* K8 has optimized REP instruction for medium sized blocks, but for very
810 small blocks it is better to use loop. For large blocks, libcall can
811 do nontemporary accesses and beat inline considerably. */
822 static const
845 in QImode, HImode and SImode.
846 Relative to reg-reg move (2). */
850 in SFmode, DFmode and XFmode */
852 in SFmode, DFmode and XFmode */
855 in SImode and DImode */
857 in SImode and DImode */
860 in SImode, DImode and TImode */
862 in SImode, DImode and TImode */
867 /* New AMD processors never drop prefetches; if they cannot be performed
868 immediately, they are queued. We set number of simultaneous prefetches
869 to a large constant to reflect this (it probably is not a good idea not
870 to limit number of prefetches at all, as their execution also takes some
871 time). */
881 k8_memcpy,
882 k8_memset,
894 };
896 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
897 very small blocks it is better to use loop. For large blocks, libcall can
898 do nontemporary accesses and beat inline considerably. */
931 in QImode, HImode and SImode.
932 Relative to reg-reg move (2). */
936 in SFmode, DFmode and XFmode */
938 in SFmode, DFmode and XFmode */
941 in SImode and DImode */
943 in SImode and DImode */
946 in SImode, DImode and TImode */
948 in SImode, DImode and TImode */
950 /* On K8:
951 MOVD reg64, xmmreg Double FSTORE 4
952 MOVD reg32, xmmreg Double FSTORE 4
953 On AMDFAM10:
954 MOVD reg64, xmmreg Double FADD 3
955 1/1 1/1
956 MOVD reg32, xmmreg Double FADD 3
957 1/1 1/1 */
961 /* New AMD processors never drop prefetches; if they cannot be performed
962 immediately, they are queued. We set number of simultaneous prefetches
963 to a large constant to reflect this (it probably is not a good idea not
964 to limit number of prefetches at all, as their execution also takes some
965 time). */
975 amdfam10_memcpy,
976 amdfam10_memset,
988 };
990 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
991 very small blocks it is better to use loop. For large blocks, libcall
992 can do nontemporary accesses and beat inline considerably. */
1026 in QImode, HImode and SImode.
1027 Relative to reg-reg move (2). */
1031 in SFmode, DFmode and XFmode */
1033 in SFmode, DFmode and XFmode */
1036 in SImode and DImode */
1038 in SImode and DImode */
1041 in SImode, DImode and TImode */
1043 in SImode, DImode and TImode */
1045 /* On K8:
1046 MOVD reg64, xmmreg Double FSTORE 4
1047 MOVD reg32, xmmreg Double FSTORE 4
1048 On AMDFAM10:
1049 MOVD reg64, xmmreg Double FADD 3
1050 1/1 1/1
1051 MOVD reg32, xmmreg Double FADD 3
1052 1/1 1/1 */
1056 /* New AMD processors never drop prefetches; if they cannot be performed
1057 immediately, they are queued. We set number of simultaneous prefetches
1058 to a large constant to reflect this (it probably is not a good idea not
1059 to limit number of prefetches at all, as their execution also takes some
1060 time). */
1070 bdver1_memcpy,
1071 bdver1_memset,
1083 };
1085 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1086 very small blocks it is better to use loop. For large blocks, libcall
1087 can do nontemporary accesses and beat inline considerably. */
1122 in QImode, HImode and SImode.
1123 Relative to reg-reg move (2). */
1127 in SFmode, DFmode and XFmode */
1129 in SFmode, DFmode and XFmode */
1132 in SImode and DImode */
1134 in SImode and DImode */
1137 in SImode, DImode and TImode */
1139 in SImode, DImode and TImode */
1141 /* On K8:
1142 MOVD reg64, xmmreg Double FSTORE 4
1143 MOVD reg32, xmmreg Double FSTORE 4
1144 On AMDFAM10:
1145 MOVD reg64, xmmreg Double FADD 3
1146 1/1 1/1
1147 MOVD reg32, xmmreg Double FADD 3
1148 1/1 1/1 */
1152 /* New AMD processors never drop prefetches; if they cannot be performed
1153 immediately, they are queued. We set number of simultaneous prefetches
1154 to a large constant to reflect this (it probably is not a good idea not
1155 to limit number of prefetches at all, as their execution also takes some
1156 time). */
1166 bdver2_memcpy,
1167 bdver2_memset,
1179 };
1182 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1183 very small blocks it is better to use loop. For large blocks, libcall
1184 can do nontemporary accesses and beat inline considerably. */
1217 in QImode, HImode and SImode.
1218 Relative to reg-reg move (2). */
1222 in SFmode, DFmode and XFmode */
1224 in SFmode, DFmode and XFmode */
1227 in SImode and DImode */
1229 in SImode and DImode */
1232 in SImode, DImode and TImode */
1234 in SImode, DImode and TImode */
1239 /* New AMD processors never drop prefetches; if they cannot be performed
1240 immediately, they are queued. We set number of simultaneous prefetches
1241 to a large constant to reflect this (it probably is not a good idea not
1242 to limit number of prefetches at all, as their execution also takes some
1243 time). */
1253 bdver3_memcpy,
1254 bdver3_memset,
1266 };
1268 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1269 very small blocks it is better to use loop. For large blocks, libcall
1270 can do nontemporary accesses and beat inline considerably. */
1303 in QImode, HImode and SImode.
1304 Relative to reg-reg move (2). */
1308 in SFmode, DFmode and XFmode */
1310 in SFmode, DFmode and XFmode */
1313 in SImode and DImode */
1315 in SImode and DImode */
1318 in SImode, DImode and TImode */
1320 in SImode, DImode and TImode */
1325 /* New AMD processors never drop prefetches; if they cannot be performed
1326 immediately, they are queued. We set number of simultaneous prefetches
1327 to a large constant to reflect this (it probably is not a good idea not
1328 to limit number of prefetches at all, as their execution also takes some
1329 time). */
1339 bdver4_memcpy,
1340 bdver4_memset,
1352 };
1354 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1355 very small blocks it is better to use loop. For large blocks, libcall can
1356 do nontemporary accesses and beat inline considerably. */
1389 in QImode, HImode and SImode.
1390 Relative to reg-reg move (2). */
1394 in SFmode, DFmode and XFmode */
1396 in SFmode, DFmode and XFmode */
1399 in SImode and DImode */
1401 in SImode and DImode */
1404 in SImode, DImode and TImode */
1406 in SImode, DImode and TImode */
1408 /* On K8:
1409 MOVD reg64, xmmreg Double FSTORE 4
1410 MOVD reg32, xmmreg Double FSTORE 4
1411 On AMDFAM10:
1412 MOVD reg64, xmmreg Double FADD 3
1413 1/1 1/1
1414 MOVD reg32, xmmreg Double FADD 3
1415 1/1 1/1 */
1428 btver1_memcpy,
1429 btver1_memset,
1441 };
1475 in QImode, HImode and SImode.
1476 Relative to reg-reg move (2). */
1480 in SFmode, DFmode and XFmode */
1482 in SFmode, DFmode and XFmode */
1485 in SImode and DImode */
1487 in SImode and DImode */
1490 in SImode, DImode and TImode */
1492 in SImode, DImode and TImode */
1494 /* On K8:
1495 MOVD reg64, xmmreg Double FSTORE 4
1496 MOVD reg32, xmmreg Double FSTORE 4
1497 On AMDFAM10:
1498 MOVD reg64, xmmreg Double FADD 3
1499 1/1 1/1
1500 MOVD reg32, xmmreg Double FADD 3
1501 1/1 1/1 */
1513 btver2_memcpy,
1514 btver2_memset,
1526 };
1530 DUMMY_STRINGOP_ALGS};
1534 DUMMY_STRINGOP_ALGS};
1536 static const
1559 in QImode, HImode and SImode.
1560 Relative to reg-reg move (2). */
1564 in SFmode, DFmode and XFmode */
1566 in SFmode, DFmode and XFmode */
1569 in SImode and DImode */
1571 in SImode and DImode */
1574 in SImode, DImode and TImode */
1576 in SImode, DImode and TImode */
1589 pentium4_memcpy,
1590 pentium4_memset,
1602 };
1615 static const
1638 in QImode, HImode and SImode.
1639 Relative to reg-reg move (2). */
1643 in SFmode, DFmode and XFmode */
1645 in SFmode, DFmode and XFmode */
1648 in SImode and DImode */
1650 in SImode and DImode */
1653 in SImode, DImode and TImode */
1655 in SImode, DImode and TImode */
1668 nocona_memcpy,
1669 nocona_memset,
1681 };
1692 static const
1715 in QImode, HImode and SImode.
1716 Relative to reg-reg move (2). */
1720 in SFmode, DFmode and XFmode */
1722 in SFmode, DFmode and XFmode */
1725 in SImode and DImode */
1727 in SImode and DImode */
1730 in SImode, DImode and TImode */
1732 in SImode, DImode and TImode */
1745 atom_memcpy,
1746 atom_memset,
1758 };
1769 static const
1792 in QImode, HImode and SImode.
1793 Relative to reg-reg move (2). */
1797 in SFmode, DFmode and XFmode */
1799 in SFmode, DFmode and XFmode */
1802 in SImode and DImode */
1804 in SImode and DImode */
1807 in SImode, DImode and TImode */
1809 in SImode, DImode and TImode */
1822 slm_memcpy,
1823 slm_memset,
1835 };
1846 static const
1869 in QImode, HImode and SImode.
1870 Relative to reg-reg move (2). */
1874 in SFmode, DFmode and XFmode */
1876 in SFmode, DFmode and XFmode */
1879 in SImode and DImode */
1881 in SImode and DImode */
1884 in SImode, DImode and TImode */
1886 in SImode, DImode and TImode */
1899 intel_memcpy,
1900 intel_memset,
1912 };
1914 /* Generic should produce code tuned for Core-i7 (and newer chips)
1915 and btver1 (and newer chips). */
1927 static const
1930 /* On all chips taken into consideration lea is 2 cycles and more. With
1931 this cost however our current implementation of synth_mult results in
1932 use of unnecessary temporary registers causing regression on several
1933 SPECfp benchmarks. */
1954 in QImode, HImode and SImode.
1955 Relative to reg-reg move (2). */
1959 in SFmode, DFmode and XFmode */
1961 in SFmode, DFmode and XFmode */
1964 in SImode and DImode */
1966 in SImode and DImode */
1969 in SImode, DImode and TImode */
1971 in SImode, DImode and TImode */
1977 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1978 value is increased to perhaps more appropriate value of 5. */
1986 generic_memcpy,
1987 generic_memset,
1999 };
2001 /* core_cost should produce code tuned for Core familly of CPUs. */
2014 static const
2017 /* On all chips taken into consideration lea is 2 cycles and more. With
2018 this cost however our current implementation of synth_mult results in
2019 use of unnecessary temporary registers causing regression on several
2020 SPECfp benchmarks. */
2041 in QImode, HImode and SImode.
2042 Relative to reg-reg move (2). */
2046 in SFmode, DFmode and XFmode */
2048 in SFmode, DFmode and XFmode */
2051 in SImode and DImode */
2053 in SImode and DImode */
2056 in SImode, DImode and TImode */
2058 in SImode, DImode and TImode */
2064 /* FIXME perhaps more appropriate value is 5. */
2072 core_memcpy,
2073 core_memset,
2085 };
2088 /* Set by -mtune. */
2091 /* Set by -mtune or -Os. */
2094 /* Processor feature/optimization bitmasks. */
2095 #define m_386 (1<<PROCESSOR_I386)
2096 #define m_486 (1<<PROCESSOR_I486)
2097 #define m_PENT (1<<PROCESSOR_PENTIUM)
2098 #define m_IAMCU (1<<PROCESSOR_IAMCU)
2099 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2100 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2101 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2102 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2103 #define m_CORE2 (1<<PROCESSOR_CORE2)
2104 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2105 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2106 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2107 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2108 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2109 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2110 #define m_KNL (1<<PROCESSOR_KNL)
2111 #define m_INTEL (1<<PROCESSOR_INTEL)
2113 #define m_GEODE (1<<PROCESSOR_GEODE)
2114 #define m_K6 (1<<PROCESSOR_K6)
2115 #define m_K6_GEODE (m_K6 | m_GEODE)
2116 #define m_K8 (1<<PROCESSOR_K8)
2117 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2118 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2119 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2120 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2121 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2122 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2123 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2124 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2125 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2126 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2127 #define m_BTVER (m_BTVER1 | m_BTVER2)
2128 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2130 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2133 #undef DEF_TUNE
2134 #define DEF_TUNE(tune, name, selector) name,
2136 #undef DEF_TUNE
2137 };
2139 /* Feature tests against the various tunings. */
2142 /* Feature tests against the various tunings used to create ix86_tune_features
2143 based on the processor mask. */
2145 #undef DEF_TUNE
2146 #define DEF_TUNE(tune, name, selector) selector,
2148 #undef DEF_TUNE
2149 };
2151 /* Feature tests against the various architecture variations. */
2154 /* Feature tests against the various architecture variations, used to create
2155 ix86_arch_features based on the processor mask. */
2157 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2160 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2163 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2166 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2169 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2171 };
2173 /* In case the average insn count for single function invocation is
2174 lower than this constant, emit fast (but longer) prologue and
2175 epilogue code. */
2176 #define FAST_PROLOGUE_INSN_COUNT 20
2178 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2183 /* Array of the smallest class containing reg number REGNO, indexed by
2184 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2187 {
2188 /* ax, dx, cx, bx */
2190 /* si, di, bp, sp */
2192 /* FP registers */
2195 /* arg pointer */
2196 NON_Q_REGS,
2197 /* flags, fpsr, fpcr, frame */
2199 /* SSE registers */
2202 /* MMX registers */
2205 /* REX registers */
2208 /* SSE REX registers */
2211 /* AVX-512 SSE registers */
2216 /* Mask registers. */
2219 /* MPX bound registers */
2221 };
2223 /* The "default" register map used in 32bit mode. */
2226 {
2238 };
2240 /* The "default" register map used in 64bit mode. */
2243 {
2255 };
2257 /* Define the register numbers to be used in Dwarf debugging information.
2258 The SVR4 reference port C compiler uses the following register numbers
2259 in its Dwarf output code:
2260 0 for %eax (gcc regno = 0)
2261 1 for %ecx (gcc regno = 2)
2262 2 for %edx (gcc regno = 1)
2263 3 for %ebx (gcc regno = 3)
2264 4 for %esp (gcc regno = 7)
2265 5 for %ebp (gcc regno = 6)
2266 6 for %esi (gcc regno = 4)
2267 7 for %edi (gcc regno = 5)
2268 The following three DWARF register numbers are never generated by
2269 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2270 believes these numbers have these meanings.
2271 8 for %eip (no gcc equivalent)
2272 9 for %eflags (gcc regno = 17)
2273 10 for %trapno (no gcc equivalent)
2274 It is not at all clear how we should number the FP stack registers
2275 for the x86 architecture. If the version of SDB on x86/svr4 were
2276 a bit less brain dead with respect to floating-point then we would
2277 have a precedent to follow with respect to DWARF register numbers
2278 for x86 FP registers, but the SDB on x86/svr4 is so completely
2279 broken with respect to FP registers that it is hardly worth thinking
2280 of it as something to strive for compatibility with.
2281 The version of x86/svr4 SDB I have at the moment does (partially)
2282 seem to believe that DWARF register number 11 is associated with
2283 the x86 register %st(0), but that's about all. Higher DWARF
2284 register numbers don't seem to be associated with anything in
2285 particular, and even for DWARF regno 11, SDB only seems to under-
2286 stand that it should say that a variable lives in %st(0) (when
2287 asked via an `=' command) if we said it was in DWARF regno 11,
2288 but SDB still prints garbage when asked for the value of the
2289 variable in question (via a `/' command).
2290 (Also note that the labels SDB prints for various FP stack regs
2291 when doing an `x' command are all wrong.)
2292 Note that these problems generally don't affect the native SVR4
2293 C compiler because it doesn't allow the use of -O with -g and
2294 because when it is *not* optimizing, it allocates a memory
2295 location for each floating-point variable, and the memory
2296 location is what gets described in the DWARF AT_location
2297 attribute for the variable in question.
2298 Regardless of the severe mental illness of the x86/svr4 SDB, we
2299 do something sensible here and we use the following DWARF
2300 register numbers. Note that these are all stack-top-relative
2301 numbers.
2302 11 for %st(0) (gcc regno = 8)
2303 12 for %st(1) (gcc regno = 9)
2304 13 for %st(2) (gcc regno = 10)
2305 14 for %st(3) (gcc regno = 11)
2306 15 for %st(4) (gcc regno = 12)
2307 16 for %st(5) (gcc regno = 13)
2308 17 for %st(6) (gcc regno = 14)
2309 18 for %st(7) (gcc regno = 15)
2310 */
2312 {
2324 };
2326 /* Define parameter passing and return registers. */
2329 {
2331 };
2334 {
2336 };
2339 {
2341 };
2343 /* Additional registers that are clobbered by SYSV calls. */
2346 {
2351 };
2353 /* Define the structure for the machine field in struct function. */
2358 rtx rtl;
2360 };
2362 /* Structure describing stack frame layout.
2363 Stack grows downward:
2365 [arguments]
2366 <- ARG_POINTER
2367 saved pc
2369 saved static chain if ix86_static_chain_on_stack
2371 saved frame pointer if frame_pointer_needed
2372 <- HARD_FRAME_POINTER
2373 [saved regs]
2374 <- regs_save_offset
2375 [padding0]
2377 [saved SSE regs]
2378 <- sse_regs_save_offset
2379 [padding1] |
2380 | <- FRAME_POINTER
2381 [va_arg registers] |
2382 |
2383 [frame] |
2384 |
2385 [padding2] | = to_allocate
2386 <- STACK_POINTER
2387 */
2388 struct ix86_frame
2389 {
2396 /* The offsets relative to ARG_POINTER. */
2397 HOST_WIDE_INT frame_pointer_offset;
2398 HOST_WIDE_INT hard_frame_pointer_offset;
2399 HOST_WIDE_INT stack_pointer_offset;
2400 HOST_WIDE_INT hfp_save_offset;
2401 HOST_WIDE_INT reg_save_offset;
2402 HOST_WIDE_INT sse_reg_save_offset;
2404 /* When save_regs_using_mov is set, emit prologue using
2405 move instead of push instructions. */
2407 };
2409 /* Which cpu are we scheduling for. */
2412 /* Which cpu are we optimizing for. */
2415 /* Which instruction set architecture to use. */
2418 /* True if processor has SSE prefetch instruction. */
2421 /* -mstackrealign option */
2439 /* Preferred alignment for stack boundary in bits. */
2442 /* Alignment for incoming stack boundary in bits specified at
2443 command line. */
2446 /* Default alignment for incoming stack boundary in bits. */
2449 /* Alignment for incoming stack boundary in bits. */
2452 /* Calling abi specific va_list type nodes. */
2456 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2460 /* Fence to use after loop using movnt. */
2461 tree x86_mfence;
2463 /* Register class used for passing given 64bit part of the argument.
2464 These represent classes as documented by the PS ABI, with the exception
2465 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2466 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2468 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2469 whenever possible (upper half does contain padding). */
2470 enum x86_64_reg_class
2471 {
2472 X86_64_NO_CLASS,
2473 X86_64_INTEGER_CLASS,
2474 X86_64_INTEGERSI_CLASS,
2475 X86_64_SSE_CLASS,
2476 X86_64_SSESF_CLASS,
2477 X86_64_SSEDF_CLASS,
2478 X86_64_SSEUP_CLASS,
2479 X86_64_X87_CLASS,
2480 X86_64_X87UP_CLASS,
2481 X86_64_COMPLEX_X87_CLASS,
2482 X86_64_MEMORY_CLASS
2483 };
2485 #define MAX_CLASSES 8
2487 /* Table of constants used by fldpi, fldln2, etc.... */
2491 \f
2496 const_tree);
2508 enum ix86_function_specific_strings
2509 {
2510 IX86_FUNCTION_SPECIFIC_ARCH,
2511 IX86_FUNCTION_SPECIFIC_TUNE,
2512 IX86_FUNCTION_SPECIFIC_MAX
2513 };
2535 \f
2536 #ifndef SUBTARGET32_DEFAULT_CPU
2538 #endif
2540 /* Whether -mtune= or -march= were specified */
2544 /* Vectorization library interface and handlers. */
2550 /* Processor target table, indexed by processor number */
2551 struct ptt
2552 {
2560 };
2562 /* This table must be in sync with enum processor_type in i386.h. */
2564 {
2592 };
2593 \f
2594 static unsigned int
2596 {
2599 /* vzeroupper instructions are inserted immediately after reload to
2600 account for possible spills from 256bit registers. The pass
2601 reuses mode switching infrastructure by re-running mode insertion
2602 pass, so disable entities that have already been processed. */
2608 /* Call optimize_mode_switching. */
2611 }
2616 {
2626 };
2629 {
2633 {}
2635 /* opt_pass methods: */
2637 {
2641 }
2644 {
2646 }
2652 rtl_opt_pass *
2654 {
2656 }
2658 /* Return true if a red-zone is in use. */
2662 {
2664 }
2665 \f
2666 /* Return a string that documents the current -m options. The caller is
2667 responsible for freeing the string. */
2673 {
2674 struct ix86_target_opts
2675 {
2678 };
2680 /* This table is ordered so that options like -msse4.2 that imply
2681 preceding options while match those first. */
2683 {
2737 };
2739 /* Flag options. */
2741 {
2770 };
2787 /* Add -march= option. */
2789 {
2792 }
2794 /* Add -mtune= option. */
2796 {
2799 }
2801 /* Add -m32/-m64/-mx32. */
2803 {
2806 else
2808 isa &= ~ (OPTION_MASK_ISA_64BIT
2809 | OPTION_MASK_ABI_64
2811 }
2812 else
2816 /* Pick out the options in isa options. */
2818 {
2820 {
2823 }
2824 }
2827 {
2830 isa);
2831 }
2833 /* Add flag options. */
2835 {
2837 {
2840 }
2841 }
2844 {
2847 }
2849 /* Add -fpmath= option. */
2851 {
2854 {
2869 }
2870 }
2872 /* Any options? */
2878 /* Size the string. */
2882 {
2887 }
2889 /* Build the string. */
2894 {
2901 {
2903 line_len++;
2906 {
2910 }
2911 }
2915 {
2919 }
2920 }
2926 }
2928 /* Return true, if profiling code should be emitted before
2929 prologue. Otherwise it returns false.
2930 Note: For x86 with "hotfix" it is sorried. */
2931 static bool
2933 {
2935 }
2937 /* Function that is callable from the debugger to print the current
2938 options. */
2939 void ATTRIBUTE_UNUSED
2941 {
2947 {
2950 }
2951 else
2955 }
2958 #define DEF_ENUM
2959 #define DEF_ALG(alg, name) #name,
2961 #undef DEF_ENUM
2962 #undef DEF_ALG
2963 };
2965 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2966 The string is of the following form (or comma separated list of it):
2968 strategy_alg:max_size:[align|noalign]
2970 where the full size range for the strategy is either [0, max_size] or
2971 [min_size, max_size], in which min_size is the max_size + 1 of the
2972 preceding range. The last size range must have max_size == -1.
2974 Examples:
2976 1.
2977 -mmemcpy-strategy=libcall:-1:noalign
2979 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2982 2.
2983 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2985 This is to tell the compiler to use the following strategy for memset
2986 1) when the expected size is between [1, 16], use rep_8byte strategy;
2987 2) when the size is between [17, 2048], use vector_loop;
2988 3) when the size is > 2048, use libcall. */
2990 struct stringop_size_range
2991 {
2993 stringop_alg alg;
2995 };
2997 static void
2999 {
3007 else
3012 do
3013 {
3023 {
3027 }
3030 {
3034 }
3041 {
3043 alg_name,
3046 }
3050 {
3051 /* rep; movq isn't available in 32-bit code. */
3054 alg_name,
3057 }
3065 else
3066 {
3070 }
3071 n++;
3073 }
3077 {
3082 }
3085 {
3089 }
3091 /* Now override the default algs array. */
3093 {
3099 }
3100 }
3102 \f
3103 /* parse -mtune-ctrl= option. When DUMP is true,
3104 print the features that are explicitly set. */
3106 static void
3108 {
3116 do
3117 {
3124 {
3125 curr_feature_string++;
3127 }
3129 {
3131 {
3137 }
3138 }
3143 }
3146 }
3148 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3149 processor type. */
3151 static void
3153 {
3158 {
3161 else
3163 }
3166 {
3171 }
3174 }
3177 /* Default align_* from the processor table. */
3179 static void
3181 {
3183 {
3186 }
3188 {
3191 }
3193 {
3195 }
3196 }
3198 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE hook. */
3200 static void
3202 {
3204 }
3206 /* Override various settings based on options. If MAIN_ARGS_P, the
3207 options are from the command line, otherwise they are from
3208 attributes. */
3210 static void
3214 {
3222 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3223 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3224 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3225 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3226 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3227 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3228 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3229 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3230 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3231 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3232 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3233 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3234 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3235 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3236 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3237 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3238 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3239 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3240 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3241 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3242 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3243 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3244 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3245 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3246 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3247 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3248 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3249 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3250 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3251 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3252 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3253 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3254 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3255 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3256 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3257 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3258 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3259 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3260 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3261 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3262 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3263 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3264 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3265 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3266 #define PTA_MPX (HOST_WIDE_INT_1 << 44)
3267 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3268 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3269 #define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
3270 #define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
3271 #define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
3272 #define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
3273 #define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
3274 #define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
3275 #define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 53)
3276 #define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 54)
3277 #define PTA_CLWB (HOST_WIDE_INT_1 << 55)
3278 #define PTA_PCOMMIT (HOST_WIDE_INT_1 << 56)
3279 #define PTA_MWAITX (HOST_WIDE_INT_1 << 57)
3281 #define PTA_CORE2 \
3282 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3283 | PTA_CX16 | PTA_FXSR)
3284 #define PTA_NEHALEM \
3285 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3286 #define PTA_WESTMERE \
3287 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3288 #define PTA_SANDYBRIDGE \
3289 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3290 #define PTA_IVYBRIDGE \
3291 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3292 #define PTA_HASWELL \
3293 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3294 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3295 #define PTA_BROADWELL \
3296 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3297 #define PTA_KNL \
3298 (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
3299 #define PTA_BONNELL \
3300 (PTA_CORE2 | PTA_MOVBE)
3301 #define PTA_SILVERMONT \
3302 (PTA_WESTMERE | PTA_MOVBE)
3304 /* if this reaches 64, need to widen struct pta flags below */
3306 static struct pta
3307 {
3312 }
3314 {
3349 PTA_SANDYBRIDGE},
3351 PTA_SANDYBRIDGE},
3353 PTA_IVYBRIDGE},
3355 PTA_IVYBRIDGE},
3447 PTA_64BIT
3449 };
3451 /* -mrecip options. */
3452 static struct
3453 {
3456 }
3458 {
3465 };
3469 /* Set up prefix/suffix so the error messages refer to either the command
3470 line argument, or the attribute(target). */
3472 {
3476 }
3477 else
3478 {
3482 }
3484 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3485 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3488 #ifdef TARGET_BI_ARCH
3489 else
3490 {
3491 #if TARGET_BI_ARCH == 1
3492 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3493 is on and OPTION_MASK_ABI_X32 is off. We turn off
3494 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3495 -mx32. */
3498 #else
3499 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3500 on and OPTION_MASK_ABI_64 is off. We turn off
3501 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3502 -m64 or OPTION_MASK_CODE16 is turned on by -m16. */
3506 #endif
3511 }
3512 #endif
3515 {
3516 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3517 OPTION_MASK_ABI_64 for TARGET_X32. */
3520 }
3523 | OPTION_MASK_ABI_X32
3526 {
3527 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3528 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3531 }
3533 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3534 SUBTARGET_OVERRIDE_OPTIONS;
3535 #endif
3537 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3538 SUBSUBTARGET_OVERRIDE_OPTIONS;
3539 #endif
3541 /* -fPIC is the default for x86_64. */
3545 /* Need to check -mtune=generic first. */
3547 {
3548 /* As special support for cross compilers we read -mtune=native
3549 as -mtune=generic. With native compilers we won't see the
3550 -mtune=native, as it was changed by the driver. */
3552 {
3554 }
3559 }
3560 else
3561 {
3565 {
3566 opts->x_ix86_tune_string
3569 }
3571 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3572 or defaulted. We need to use a sensible tune option. */
3574 {
3576 }
3577 }
3581 {
3582 /* rep; movq isn't available in 32-bit code. */
3585 }
3588 opts->x_ix86_arch_string
3591 else
3595 {
3603 }
3604 else
3611 /* For targets using ms ABI enable ms-extensions, if not
3612 explicit turned off. For non-ms ABI we turn off this
3613 option. */
3618 {
3620 {
3664 {
3667 }
3675 }
3676 }
3677 else
3678 {
3679 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3680 use of rip-relative addressing. This eliminates fixups that
3681 would otherwise be needed if this object is to be placed in a
3682 DLL, and is essentially just as efficient as direct addressing. */
3688 else
3690 }
3692 {
3695 }
3703 {
3706 /* Default cpu tuning to the architecture. */
3887 }
3896 {
3897 /* Verify that x87/MMX/SSE/AVX is off for -miamcu. */
3901 | OPTION_MASK_ISA_SSE
3907 }
3925 {
3929 {
3931 {
3933 {
3941 }
3942 else
3945 }
3946 }
3947 /* Intel CPUs have always interpreted SSE prefetch instructions as
3948 NOPs; so, we can enable SSE prefetch instructions even when
3949 -mtune (rather than -march) points us to a processor that has them.
3950 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3951 higher processors. */
3956 }
3964 #ifndef USE_IX86_FRAME_POINTER
3965 #define USE_IX86_FRAME_POINTER 0
3966 #endif
3968 #ifndef USE_X86_64_FRAME_POINTER
3969 #define USE_X86_64_FRAME_POINTER 0
3970 #endif
3972 /* Set the default values for switches whose default depends on TARGET_64BIT
3973 in case they weren't overwritten by command line options. */
3975 {
3983 opts->x_flag_unwind_tables
3987 }
3988 else
3989 {
3991 opts->x_flag_omit_frame_pointer
3996 {
3997 /* Intel MCU psABI specifies that -freg-struct-return should
3998 be on. Instead of setting DEFAULT_PCC_STRUCT_RETURN to 1,
3999 we check -miamcu so that -freg-struct-return is always
4000 turned on if -miamcu is used. */
4003 else
4005 }
4006 }
4009 /* TODO: ix86_cost should be chosen at instruction or function granuality
4010 so for cold code we use size_cost even in !optimize_size compilation. */
4013 else
4016 /* Arrange to set up i386_stack_locals for all functions. */
4019 /* Validate -mregparm= value. */
4021 {
4027 {
4031 }
4032 }
4037 /* Default align_* from the processor table. */
4040 /* Provide default for -mbranch-cost= value. */
4045 {
4046 opts->x_target_flags
4049 /* Enable by default the SSE and MMX builtins. Do allow the user to
4050 explicitly disable any of these. In particular, disabling SSE and
4051 MMX for kernel code is extremely useful. */
4053 opts->x_ix86_isa_flags
4060 }
4061 else
4062 {
4063 opts->x_target_flags
4067 opts->x_ix86_isa_flags
4070 /* i386 ABI does not specify red zone. It still makes sense to use it
4071 when programmer takes care to stack from being destroyed. */
4074 }
4076 /* Keep nonleaf frame pointers. */
4082 /* If we're doing fast math, we don't care about comparison order
4083 wrt NaNs. This lets us use a shorter comparison sequence. */
4087 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
4088 since the insns won't need emulation. */
4092 /* Likewise, if the target doesn't have a 387, or we've specified
4093 software floating point, don't use 387 inline intrinsics. */
4097 /* Turn on MMX builtins for -msse. */
4099 opts->x_ix86_isa_flags
4102 /* Enable SSE prefetch. */
4107 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
4110 opts->x_ix86_isa_flags
4113 /* Enable popcnt instruction for -msse4.2 or -mabm. */
4116 opts->x_ix86_isa_flags
4119 /* Enable lzcnt instruction for -mabm. */
4121 opts->x_ix86_isa_flags
4124 /* Validate -mpreferred-stack-boundary= value or default it to
4125 PREFERRED_STACK_BOUNDARY_DEFAULT. */
4128 {
4135 {
4139 else
4142 }
4143 else
4144 ix86_preferred_stack_boundary
4146 }
4148 /* Set the default value for -mstackrealign. */
4154 /* Validate -mincoming-stack-boundary= value or default it to
4155 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
4158 {
4166 else
4167 {
4168 ix86_user_incoming_stack_boundary
4170 ix86_incoming_stack_boundary
4172 }
4173 }
4175 #ifndef NO_PROFILE_COUNTERS
4178 #endif
4182 /* Accept -msseregparm only if at least SSE support is enabled. */
4188 {
4190 {
4192 {
4195 }
4198 {
4201 }
4202 }
4203 }
4204 /* For all chips supporting SSE2, -mfpmath=sse performs better than
4205 fpmath=387. The second is however default at many targets since the
4206 extra 80bit precision of temporaries is considered to be part of ABI.
4207 Overwrite the default at least for -ffast-math.
4208 TODO: -mfpmath=both seems to produce same performing code with bit
4209 smaller binaries. It is however not clear if register allocation is
4210 ready for this setting.
4211 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
4212 codegen. We may switch to 387 with -ffast-math for size optimized
4213 functions. */
4217 else
4220 /* If the i387 is disabled, then do not return values in it. */
4224 /* Use external vectorized library in vectorizing intrinsics. */
4227 {
4238 }
4244 /* If stack probes are required, the space used for large function
4245 arguments on the stack must also be probed, so enable
4246 -maccumulate-outgoing-args so this happens in the prologue. */
4249 {
4254 }
4256 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4257 {
4263 }
4265 /* When scheduling description is not available, disable scheduler pass
4266 so it won't slow down the compilation and make x87 code slower. */
4287 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4289 && HAVE_prefetch
4295 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4296 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4301 {
4304 {
4306 ix86_gen_tls_local_dynamic_base_64
4308 }
4309 else
4310 {
4312 ix86_gen_tls_local_dynamic_base_64
4314 }
4315 }
4316 else
4320 {
4331 }
4332 else
4333 {
4344 }
4346 #ifdef USE_IX86_CLD
4347 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4350 #endif
4353 {
4358 }
4360 {
4364 }
4366 {
4367 #if defined(PROFILE_BEFORE_PROLOGUE)
4369 #else
4371 #endif
4372 }
4382 /* Enable 128-bit AVX instruction generation
4383 for the auto-vectorizer. */
4389 {
4396 {
4399 {
4401 q++;
4402 }
4403 else
4408 else
4409 {
4412 {
4415 }
4418 {
4422 }
4423 }
4428 else
4430 }
4431 }
4438 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4439 for 64-bit Bionic. Also default long double to 64-bit for Intel
4440 MCU psABI. */
4445 ? MASK_LONG_DOUBLE_128
4448 /* Only one of them can be active. */
4452 /* Save the initial options in case the user does function specific
4453 options. */
4455 target_option_default_node = target_option_current_node
4458 /* Handle stack protector */
4460 opts->x_ix86_stack_protector_guard
4463 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4465 {
4469 }
4472 {
4476 }
4477 }
4479 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4481 static void
4483 {
4485 struct register_pass_info insert_vzeroupper_info
4488 };
4493 /* This needs to be done at start up. It's convenient to do it here. */
4495 }
4497 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
4500 {
4504 }
4506 /* Update register usage after having seen the compiler flags. */
4508 static void
4510 {
4513 /* For 32-bit targets, squash the REX registers. */
4515 {
4522 }
4524 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4532 {
4533 /* Set/reset conditionally defined registers from
4534 CALL_USED_REGISTERS initializer. */
4538 /* Calculate registers of CLOBBERED_REGS register set
4539 as call used registers from GENERAL_REGS register set. */
4543 }
4545 /* If MMX is disabled, squash the registers. */
4551 /* If SSE is disabled, squash the registers. */
4557 /* If the FPU is disabled, squash the registers. */
4563 /* If AVX512F is disabled, squash the registers. */
4565 {
4571 }
4573 /* If MPX is disabled, squash the registers. */
4577 }
4579 \f
4580 /* Save the current options */
4582 static void
4585 {
4621 /* The fields are char but the variables are not; make sure the
4622 values fit in the fields. */
4627 }
4629 /* Restore the current options */
4631 static void
4634 {
4640 /* We don't change -fPIC. */
4678 /* TODO: ix86_cost should be chosen at instruction or function granuality
4679 so for cold code we use size_cost even in !optimize_size compilation. */
4682 else
4685 /* Recreate the arch feature tests if the arch changed */
4687 {
4692 }
4694 /* Recreate the tune optimization tests */
4697 }
4699 /* Adjust target options after streaming them in. This is mainly about
4700 reconciling them with global options. */
4702 static void
4704 {
4705 /* flag_pic is a global option, but ix86_cmodel is target saved option
4706 partly computed from flag_pic. If flag_pic is on, adjust x_ix86_cmodel
4707 for PIC, or error out. */
4710 {
4729 }
4730 else
4732 {
4747 }
4748 }
4750 /* Print the current options */
4752 static void
4755 {
4773 {
4776 }
4777 }
4779 \f
4780 /* Inner function to process the attribute((target(...))), take an argument and
4781 set the current options from the argument. If we have a list, recursively go
4782 over the list. */
4784 static bool
4789 {
4793 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4794 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4795 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4796 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4797 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4799 enum ix86_opt_type
4800 {
4801 ix86_opt_unknown,
4802 ix86_opt_yes,
4803 ix86_opt_no,
4804 ix86_opt_str,
4805 ix86_opt_enum,
4806 ix86_opt_isa
4807 };
4809 static const struct
4810 {
4817 /* isa options */
4871 /* enum options */
4874 /* string options */
4878 /* flag options */
4880 OPT_mcld,
4881 MASK_CLD),
4884 OPT_mfancy_math_387,
4885 MASK_NO_FANCY_MATH_387),
4888 OPT_mieee_fp,
4889 MASK_IEEE_FP),
4892 OPT_minline_all_stringops,
4893 MASK_INLINE_ALL_STRINGOPS),
4896 OPT_minline_stringops_dynamically,
4897 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4900 OPT_mno_align_stringops,
4901 MASK_NO_ALIGN_STRINGOPS),
4904 OPT_mrecip,
4905 MASK_RECIP),
4907 };
4909 /* If this is a list, recurse to get the options. */
4911 {
4918 enum_opts_set))
4922 }
4925 {
4928 }
4930 /* Handle multiple arguments separated by commas. */
4934 {
4948 {
4952 }
4953 else
4954 {
4957 }
4959 /* Recognize no-xxx. */
4961 {
4965 }
4966 else
4969 /* Find the option. */
4973 {
4981 {
4986 }
4987 }
4989 /* Process the option. */
4991 {
4994 }
4997 {
5003 }
5006 {
5012 else
5014 }
5017 {
5019 {
5022 }
5023 else
5025 }
5028 {
5036 global_dc);
5037 else
5038 {
5041 }
5042 }
5044 else
5046 }
5049 }
5051 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
5053 tree
5057 {
5072 /* Process each of the options on the chain. */
5077 /* If the changed options are different from the default, rerun
5078 ix86_option_override_internal, and then save the options away.
5079 The string options are are attribute options, and will be undone
5080 when we copy the save structure. */
5086 {
5087 /* If we are using the default tune= or arch=, undo the string assigned,
5088 and use the default. */
5099 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
5104 {
5107 }
5109 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
5112 /* Add any builtin functions with the new isa if any. */
5115 /* Save the current options unless we are validating options for
5116 #pragma. */
5123 /* Free up memory allocated to hold the strings */
5126 }
5129 }
5131 /* Hook to validate attribute((target("string"))). */
5133 static bool
5136 tree args,
5138 {
5143 /* attribute((target("default"))) does nothing, beyond
5144 affecting multi-versioning. */
5153 /* Get the optimization options of the current function. */
5159 /* Init func_options. */
5167 /* Initialize func_options to the default before its target options can
5168 be set. */
5181 {
5186 }
5189 }
5191 \f
5192 /* Hook to determine if one function can safely inline another. */
5194 static bool
5196 {
5201 /* If callee has no option attributes, then it is ok to inline. */
5205 /* If caller has no option attributes, but callee does then it is not ok to
5206 inline. */
5210 else
5211 {
5215 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
5216 can inline a SSE2 function but a SSE2 function can't inline a SSE4
5217 function. */
5222 /* See if we have the same non-isa options. */
5226 /* See if arch, tune, etc. are the same. */
5239 else
5241 }
5244 }
5246 \f
5247 /* Remember the last target of ix86_set_current_function. */
5250 /* Set targets globals to the default (or current #pragma GCC target
5251 if active). Invalidate ix86_previous_fndecl cache. */
5253 void
5255 {
5262 else
5265 }
5267 /* Establish appropriate back-end context for processing the function
5268 FNDECL. The argument might be NULL to indicate processing at top
5269 level, outside of any function scope. */
5270 static void
5272 {
5273 /* Only change the context if the function changes. This hook is called
5274 several times in the course of compiling a function, and we don't want to
5275 slow things down too much or call target_reinit when it isn't safe. */
5279 tree old_tree;
5284 else
5288 {
5292 }
5299 {
5305 else
5307 }
5309 }
5311 \f
5312 /* Return true if this goes in large data/bss. */
5314 static bool
5316 {
5320 /* Functions are never large data. */
5324 /* Automatic variables are never large data. */
5329 {
5335 }
5336 else
5337 {
5340 /* If this is an incomplete type with size 0, then we can't put it
5341 in data because it might be too big when completed. Also,
5342 int_size_in_bytes returns -1 if size can vary or is larger than
5343 an integer in which case also it is safer to assume that it goes in
5344 large data. */
5347 }
5350 }
5352 /* Switch to the appropriate section for output of DECL.
5353 DECL is either a `VAR_DECL' node or a constant of some sort.
5354 RELOC indicates whether forming the initial value of DECL requires
5355 link-time relocations. */
5360 {
5362 {
5366 {
5400 /* We don't split these for medium model. Place them into
5401 default sections and hope for best. */
5403 }
5405 {
5406 /* We might get called with string constants, but get_named_section
5407 doesn't like them as they are not DECLs. Also, we need to set
5408 flags in that case. */
5412 }
5413 }
5415 }
5417 /* Select a set of attributes for section NAME based on the properties
5418 of DECL and whether or not RELOC indicates that DECL's initializer
5419 might contain runtime relocations. */
5421 static unsigned int ATTRIBUTE_UNUSED
5423 {
5437 }
5439 /* Build up a unique section name, expressed as a
5440 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5441 RELOC indicates whether the initial value of EXP requires
5442 link-time relocations. */
5444 static void ATTRIBUTE_UNUSED
5446 {
5448 {
5450 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5454 {
5478 /* We don't split these for medium model. Place them into
5479 default sections and hope for best. */
5481 }
5483 {
5490 /* If we're using one_only, then there needs to be a .gnu.linkonce
5491 prefix to the section name. */
5498 }
5499 }
5501 }
5503 #ifdef COMMON_ASM_OP
5504 /* This says how to output assembler code to declare an
5505 uninitialized external linkage data object.
5507 For medium model x86-64 we need to use .largecomm opcode for
5508 large objects. */
5509 void
5513 {
5517 else
5522 }
5523 #endif
5525 /* Utility function for targets to use in implementing
5526 ASM_OUTPUT_ALIGNED_BSS. */
5528 void
5531 {
5535 else
5538 #ifdef ASM_DECLARE_OBJECT_NAME
5541 #else
5542 /* Standard thing is just output label for the object. */
5546 }
5547 \f
5548 /* Decide whether we must probe the stack before any space allocation
5549 on this target. It's essentially TARGET_STACK_PROBE except when
5550 -fstack-check causes the stack to be already probed differently. */
5552 bool
5554 {
5555 /* Do not probe the stack twice if static stack checking is enabled. */
5560 }
5561 \f
5562 /* Decide whether we can make a sibling call to a function. DECL is the
5563 declaration of the function being targeted by the call and EXP is the
5564 CALL_EXPR representing the call. */
5566 static bool
5568 {
5572 /* If we are generating position-independent code, we cannot sibcall
5573 optimize direct calls to global functions, as the PLT requires
5574 %ebx be live. (Darwin does not have a PLT.) */
5576 && !TARGET_64BIT
5577 && flag_pic
5578 && flag_plt
5582 /* If we need to align the outgoing stack, then sibcalling would
5583 unalign the stack, which may break the called function. */
5589 {
5592 }
5593 else
5594 {
5595 /* We're looking at the CALL_EXPR, we need the type of the function. */
5600 }
5602 /* Check that the return value locations are the same. Like
5603 if we are returning floats on the 80387 register stack, we cannot
5604 make a sibcall from a function that doesn't return a float to a
5605 function that does or, conversely, from a function that does return
5606 a float to a function that doesn't; the necessary stack adjustment
5607 would not be executed. This is also the place we notice
5608 differences in the return value ABI. Note that it is ok for one
5609 of the functions to have void return type as long as the return
5610 value of the other is passed in a register. */
5615 {
5618 }
5620 ;
5625 {
5626 /* The SYSV ABI has more call-clobbered registers;
5627 disallow sibcalls from MS to SYSV. */
5631 }
5632 else
5633 {
5634 /* If this call is indirect, we'll need to be able to use a
5635 call-clobbered register for the address of the target function.
5636 Make sure that all such registers are not used for passing
5637 parameters. Note that DLLIMPORT functions are indirect. */
5640 {
5642 {
5643 /* ??? Need to count the actual number of registers to be used,
5644 not the possible number of registers. Fix later. */
5646 }
5647 }
5648 }
5650 /* Otherwise okay. That also includes certain types of indirect calls. */
5652 }
5654 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5655 and "sseregparm" calling convention attributes;
5656 arguments as in struct attribute_spec.handler. */
5658 static tree
5660 tree args,
5663 {
5668 {
5670 name);
5673 }
5675 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5677 {
5678 tree cst;
5681 {
5683 }
5686 {
5688 }
5692 {
5695 name);
5697 }
5699 {
5703 }
5706 }
5709 {
5710 /* Do not warn when emulating the MS ABI. */
5715 name);
5718 }
5720 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5722 {
5724 {
5726 }
5728 {
5730 }
5732 {
5734 }
5736 {
5738 }
5739 }
5741 /* Can combine stdcall with fastcall (redundant), regparm and
5742 sseregparm. */
5744 {
5746 {
5748 }
5750 {
5752 }
5754 {
5756 }
5757 }
5759 /* Can combine cdecl with regparm and sseregparm. */
5761 {
5763 {
5765 }
5767 {
5769 }
5771 {
5773 }
5774 }
5776 {
5779 name);
5781 {
5783 }
5785 {
5787 }
5789 {
5791 }
5792 }
5794 /* Can combine sseregparm with all attributes. */
5797 }
5799 /* The transactional memory builtins are implicitly regparm or fastcall
5800 depending on the ABI. Override the generic do-nothing attribute that
5801 these builtins were declared with, and replace it with one of the two
5802 attributes that we expect elsewhere. */
5804 static tree
5807 {
5808 tree alt;
5810 /* In no case do we want to add the placeholder attribute. */
5813 /* The 64-bit ABI is unchanged for transactional memory. */
5817 /* ??? Is there a better way to validate 32-bit windows? We have
5818 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5821 else
5822 {
5825 }
5829 }
5831 /* This function determines from TYPE the calling-convention. */
5833 unsigned int
5835 {
5838 tree attrs;
5845 {
5855 /* Regparam isn't allowed for thiscall and fastcall. */
5857 {
5862 }
5866 }
5873 || is_stdarg
5879 }
5881 /* Return 0 if the attributes for two types are incompatible, 1 if they
5882 are compatible, and 2 if they are nearly compatible (which causes a
5883 warning to be generated). */
5885 static int
5887 {
5903 }
5904 \f
5905 /* Return the regparm value for a function with the indicated TYPE and DECL.
5906 DECL may be NULL when calling function indirectly
5907 or considering a libcall. */
5909 static int
5911 {
5912 tree attr;
5923 {
5926 {
5929 }
5930 }
5936 /* Use register calling convention for local functions when possible. */
5939 {
5944 /* Caller and callee must agree on the calling convention, so
5945 checking here just optimize means that with
5946 __attribute__((optimize (...))) caller could use regparm convention
5947 and callee not, or vice versa. Instead look at whether the callee
5948 is optimized or not. */
5951 {
5954 {
5957 /* Make sure no regparm register is taken by a
5958 fixed register variable. */
5960 local_regparm++)
5964 /* We don't want to use regparm(3) for nested functions as
5965 these use a static chain pointer in the third argument. */
5969 /* Save a register for the split stack. */
5973 /* Each fixed register usage increases register pressure,
5974 so less registers should be used for argument passing.
5975 This functionality can be overriden by an explicit
5976 regparm value. */
5979 globals++;
5981 local_regparm
5986 }
5987 }
5988 }
5991 }
5993 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5994 DFmode (2) arguments in SSE registers for a function with the
5995 indicated TYPE and DECL. DECL may be NULL when calling function
5996 indirectly or considering a libcall. Return -1 if any FP parameter
5997 should be rejected by error. This is used in siutation we imply SSE
5998 calling convetion but the function is called from another function with
5999 SSE disabled. Otherwise return 0. */
6001 static int
6003 {
6006 /* Use SSE registers to pass SFmode and DFmode arguments if requested
6007 by the sseregparm attribute. */
6010 {
6012 {
6014 {
6018 else
6021 }
6023 }
6026 }
6035 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
6036 (and DFmode for SSE2) arguments in SSE registers. */
6038 /* TARGET_SSE_MATH */
6042 {
6045 {
6046 /* Refuse to produce wrong code when local function with SSE enabled
6047 is called from SSE disabled function.
6048 FIXME: We need a way to detect these cases cross-ltrans partition
6049 and avoid using SSE calling conventions on local functions called
6050 from function with SSE disabled. For now at least delay the
6051 warning until we know we are going to produce wrong code.
6052 See PR66047 */
6057 }
6058 }
6061 }
6063 /* Return true if EAX is live at the start of the function. Used by
6064 ix86_expand_prologue to determine if we need special help before
6065 calling allocate_stack_worker. */
6067 static bool
6069 {
6070 /* Cheat. Don't bother working forward from ix86_function_regparm
6071 to the function type to whether an actual argument is located in
6072 eax. Instead just look at cfg info, which is still close enough
6073 to correct at this point. This gives false positives for broken
6074 functions that might use uninitialized data that happens to be
6075 allocated in eax, but who cares? */
6077 }
6079 static bool
6081 {
6082 tree attr;
6085 {
6091 /* For 32-bit MS-ABI the default is to keep aggregate
6092 return pointer. */
6095 }
6097 }
6099 /* Value is the number of bytes of arguments automatically
6100 popped when returning from a subroutine call.
6101 FUNDECL is the declaration node of the function (as a tree),
6102 FUNTYPE is the data type of the function (as a tree),
6103 or for a library call it is an identifier node for the subroutine name.
6104 SIZE is the number of bytes of arguments passed on the stack.
6106 On the 80386, the RTD insn may be used to pop them if the number
6107 of args is fixed, but if the number is variable then the caller
6108 must pop them all. RTD can't be used for library calls now
6109 because the library is compiled with the Unix compiler.
6110 Use of RTD is a selectable option, since it is incompatible with
6111 standard Unix calling sequences. If the option is not selected,
6112 the caller must always pop the args.
6114 The attribute stdcall is equivalent to RTD on a per module basis. */
6116 static int
6118 {
6121 /* None of the 64-bit ABIs pop arguments. */
6132 /* Lose any fake structure return argument if it is passed on the stack. */
6135 {
6139 }
6142 }
6144 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
6146 static bool
6148 {
6149 /* Check operand constraints in case hard registers were propagated
6150 into insn pattern. This check prevents combine pass from
6151 generating insn patterns with invalid hard register operands.
6152 These invalid insns can eventually confuse reload to error out
6153 with a spill failure. See also PRs 46829 and 46843. */
6155 {
6164 {
6172 /* For pre-AVX disallow unaligned loads/stores where the
6173 instructions don't support it. */
6177 {
6181 }
6183 /* A unary operator may be accepted by the predicate, but it
6184 is irrelevant for matching constraints. */
6189 {
6197 }
6204 /* Operand has no constraints, anything is OK. */
6209 {
6214 && operands_match_p
6218 {
6221 }
6222 }
6226 }
6227 }
6230 }
6231 \f
6232 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
6234 static unsigned HOST_WIDE_INT
6236 {
6240 }
6241 \f
6242 /* Argument support functions. */
6244 /* Return true when register may be used to pass function parameters. */
6245 bool
6247 {
6256 {
6260 else
6266 }
6272 /* TODO: The function should depend on current function ABI but
6273 builtins.c would need updating then. Therefore we use the
6274 default ABI. */
6277 /* RAX is used as hidden argument to va_arg functions. */
6283 else
6291 }
6293 /* Return if we do not know how to pass TYPE solely in registers. */
6295 static bool
6297 {
6301 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
6302 The layout_type routine is crafty and tries to trick us into passing
6303 currently unsupported vector types on the stack by using TImode. */
6306 }
6308 /* It returns the size, in bytes, of the area reserved for arguments passed
6309 in registers for the function represented by fndecl dependent to the used
6310 abi format. */
6311 int
6313 {
6317 else
6322 }
6324 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
6325 call abi used. */
6326 enum calling_abi
6328 {
6330 {
6333 {
6335 {
6337 {
6340 {
6343 }
6344 }
6346 }
6347 }
6351 }
6353 }
6355 /* We add this as a workaround in order to use libc_has_function
6356 hook in i386.md. */
6357 bool
6359 {
6361 }
6363 static bool
6365 {
6367 {
6371 else
6373 }
6375 }
6377 static enum calling_abi
6379 {
6383 }
6385 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6386 call abi used. */
6387 enum calling_abi
6389 {
6393 }
6395 /* Write the extra assembler code needed to declare a function properly. */
6397 void
6399 tree decl)
6400 {
6404 {
6410 }
6412 #ifdef SUBTARGET_ASM_UNWIND_INIT
6414 #endif
6418 /* Output magic byte marker, if hot-patch attribute is set. */
6420 {
6422 {
6423 /* leaq [%rsp + 0], %rsp */
6426 }
6427 else
6428 {
6429 /* movl.s %edi, %edi
6430 push %ebp
6431 movl.s %esp, %ebp */
6434 }
6435 }
6436 }
6438 /* regclass.c */
6441 /* Implementation of call abi switching target hook. Specific to FNDECL
6442 the specific call register sets are set. See also
6443 ix86_conditional_register_usage for more details. */
6444 void
6446 {
6449 else
6451 }
6453 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6454 expensive re-initialization of init_regs each time we switch function context
6455 since this is needed only during RTL expansion. */
6456 static void
6458 {
6462 }
6464 /* Return 1 if pseudo register should be created and used to hold
6465 GOT address for PIC code. */
6466 bool
6468 {
6475 }
6477 /* Initialize large model PIC register. */
6479 static void
6481 {
6483 rtx tmp_reg;
6492 label));
6496 }
6498 /* Create and initialize PIC register if required. */
6499 static void
6501 {
6502 edge entry_edge;
6511 {
6514 else
6516 }
6517 else
6518 {
6519 /* If there is future mcount call in the function it is more profitable
6520 to emit SET_GOT into ABI defined REAL_PIC_OFFSET_TABLE_REGNUM. */
6529 }
6537 }
6539 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6540 for a call to a function whose data type is FNTYPE.
6541 For a library call, FNTYPE is 0. */
6543 void
6547 tree fndecl,
6549 {
6556 {
6559 {
6563 }
6564 else
6566 }
6567 else
6572 /* Set up the number of registers to use for passing arguments. */
6575 {
6577 ? X86_64_REGPARM_MAX
6579 }
6581 {
6584 {
6586 ? X86_64_SSE_REGPARM_MAX
6588 }
6589 }
6597 /* Because type might mismatch in between caller and callee, we need to
6598 use actual type of function for local calls.
6599 FIXME: cgraph_analyze can be told to actually record if function uses
6600 va_start so for local functions maybe_vaarg can be made aggressive
6601 helping K&R code.
6602 FIXME: once typesytem is fixed, we won't need this code anymore. */
6616 {
6617 /* If there are variable arguments, then we won't pass anything
6618 in registers in 32-bit mode. */
6620 {
6629 }
6631 /* Use ecx and edx registers if function has fastcall attribute,
6632 else look for regparm information. */
6634 {
6637 {
6640 }
6642 {
6645 }
6646 else
6648 }
6650 /* Set up the number of SSE registers used for passing SFmode
6651 and DFmode arguments. Warn for mismatching ABI. */
6653 }
6654 }
6656 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6657 But in the case of vector types, it is some vector mode.
6659 When we have only some of our vector isa extensions enabled, then there
6660 are some modes for which vector_mode_supported_p is false. For these
6661 modes, the generic vector support in gcc will choose some non-vector mode
6662 in order to implement the type. By computing the natural mode, we'll
6663 select the proper ABI location for the operand and not depend on whatever
6664 the middle-end decides to do with these vector types.
6666 The midde-end can't deal with the vector types > 16 bytes. In this
6667 case, we return the original mode and warn ABI change if CUM isn't
6668 NULL.
6670 If INT_RETURN is true, warn ABI change if the vector mode isn't
6671 available for function return value. */
6673 static machine_mode
6676 {
6680 {
6683 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6685 {
6690 else
6693 /* Get the mode which has this inner mode and number of units. */
6697 {
6699 {
6704 {
6708 }
6710 {
6714 }
6717 }
6719 {
6724 {
6728 }
6730 {
6734 }
6737 }
6740 {
6745 {
6749 }
6751 {
6755 }
6756 }
6758 {
6763 {
6767 }
6769 {
6773 }
6774 }
6776 }
6779 }
6780 }
6783 }
6785 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6786 this may not agree with the mode that the type system has chosen for the
6787 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6788 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6790 static rtx
6793 {
6794 rtx tmp;
6798 else
6799 {
6803 }
6806 }
6808 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6809 of this code is to classify each 8bytes of incoming argument by the register
6810 class and assign registers accordingly. */
6812 /* Return the union class of CLASS1 and CLASS2.
6813 See the x86-64 PS ABI for details. */
6815 static enum x86_64_reg_class
6817 {
6818 /* Rule #1: If both classes are equal, this is the resulting class. */
6822 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6823 the other class. */
6829 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6833 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6841 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6842 MEMORY is used. */
6851 /* Rule #6: Otherwise class SSE is used. */
6853 }
6855 /* Classify the argument of type TYPE and mode MODE.
6856 CLASSES will be filled by the register class used to pass each word
6857 of the operand. The number of words is returned. In case the parameter
6858 should be passed in memory, 0 is returned. As a special case for zero
6859 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6861 BIT_OFFSET is used internally for handling records and specifies offset
6862 of the offset in bits modulo 512 to avoid overflow cases.
6864 See the x86-64 PS ABI for details.
6865 */
6867 static int
6870 {
6871 HOST_WIDE_INT bytes =
6873 int words
6876 /* Variable sized entities are always passed/returned in memory. */
6885 {
6887 tree field;
6890 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6897 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6898 signalize memory class, so handle it as special case. */
6900 {
6903 }
6905 /* Classify each field of record and merge classes. */
6907 {
6909 /* And now merge the fields of structure. */
6911 {
6913 {
6919 /* Bitfields are always classified as integer. Handle them
6920 early, since later code would consider them to be
6921 misaligned integers. */
6923 {
6932 }
6933 else
6934 {
6939 /* Flexible array member is ignored. */
6946 {
6950 {
6953 "the ABI of passing struct with"
6954 " a flexible array member has"
6956 }
6958 }
6960 subclasses,
6970 }
6971 }
6972 }
6976 /* Arrays are handled as small records. */
6977 {
6984 /* The partial classes are now full classes. */
6995 }
6998 /* Unions are similar to RECORD_TYPE but offset is always 0.
6999 */
7001 {
7003 {
7011 bit_offset);
7016 }
7017 }
7022 }
7025 {
7026 /* When size > 16 bytes, if the first one isn't
7027 X86_64_SSE_CLASS or any other ones aren't
7028 X86_64_SSEUP_CLASS, everything should be passed in
7029 memory. */
7036 }
7038 /* Final merger cleanup. */
7040 {
7041 /* If one class is MEMORY, everything should be passed in
7042 memory. */
7046 /* The X86_64_SSEUP_CLASS should be always preceded by
7047 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
7051 {
7052 /* The first one should never be X86_64_SSEUP_CLASS. */
7055 }
7057 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
7058 everything should be passed in memory. */
7061 {
7064 /* The first one should never be X86_64_X87UP_CLASS. */
7067 {
7070 "the ABI of passing union with long double"
7072 }
7074 }
7075 }
7077 }
7079 /* Compute alignment needed. We align all types to natural boundaries with
7080 exception of XFmode that is aligned to 64bits. */
7082 {
7091 /* Misaligned fields are always returned in memory. */
7094 }
7096 /* for V1xx modes, just use the base mode */
7101 /* Classification of atomic types. */
7103 {
7119 {
7122 /* Analyze last 128 bits only. */
7126 {
7129 }
7131 {
7134 }
7136 {
7140 }
7142 {
7145 }
7146 else
7148 }
7155 /* OImode shouldn't be used directly. */
7162 else
7180 else
7181 {
7185 {
7188 "the ABI of passing structure with complex float"
7190 }
7193 }
7202 /* This modes is larger than 16 bytes. */
7260 else
7264 }
7265 }
7267 /* Examine the argument and return set number of register required in each
7268 class. Return true iff parameter should be passed in memory. */
7270 static bool
7273 {
7284 {
7305 }
7308 }
7310 /* Construct container for the argument used by GCC interface. See
7311 FUNCTION_ARG for the detailed description. */
7313 static rtx
7317 {
7318 /* The following variables hold the static issued_error state. */
7323 machine_mode tmpmode;
7332 rtx ret;
7343 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
7344 some less clueful developer tries to use floating-point anyway. */
7346 {
7348 {
7350 {
7353 }
7354 }
7356 {
7359 }
7361 }
7363 /* Likewise, error if the ABI requires us to return values in the
7364 x87 registers and the user specified -mno-80387. */
7370 {
7372 {
7375 }
7377 }
7379 /* First construct simple cases. Avoid SCmode, since we want to use
7380 single register to pass this type. */
7383 {
7398 /* Zero sized array, struct or class. */
7402 }
7441 /* Otherwise figure out the entries of the PARALLEL. */
7443 {
7447 {
7452 /* Merge TImodes on aligned occasions here too. */
7454 tmpmode
7458 else
7460 /* We've requested 24 bytes we
7461 don't have mode for. Use DImode. */
7468 intreg++;
7476 sse_regno++;
7484 sse_regno++;
7489 {
7495 {
7497 i++;
7498 }
7499 else
7524 }
7530 sse_regno++;
7534 }
7535 }
7537 /* Empty aligned struct, union or class. */
7545 }
7547 /* Update the data in CUM to advance over an argument of mode MODE
7548 and data type TYPE. (TYPE is null for libcalls where that information
7549 may not be available.)
7551 Return a number of integer regsiters advanced over. */
7553 static int
7556 HOST_WIDE_INT words)
7557 {
7562 {
7563 /* Intel MCU psABI passes scalars and aggregates no larger than 8
7564 bytes in registers. */
7568 }
7571 {
7578 /* FALLTHRU */
7584 pass_in_reg:
7591 {
7594 }
7598 /* OImode shouldn't be used directly. */
7611 /* FALLTHRU */
7633 {
7638 {
7641 }
7642 }
7652 {
7657 {
7660 }
7661 }
7663 }
7665 {
7671 }
7674 }
7676 static int
7679 {
7682 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7689 {
7695 }
7696 else
7697 {
7702 }
7703 }
7705 static int
7707 HOST_WIDE_INT words)
7708 {
7709 /* Otherwise, this should be passed indirect. */
7714 {
7718 }
7720 }
7722 /* Update the data in CUM to advance over an argument of mode MODE and
7723 data type TYPE. (TYPE is null for libcalls where that information
7724 may not be available.) */
7726 static void
7729 {
7736 else
7745 {
7746 /* If we pass bounds in BT then just update remained bounds count. */
7748 {
7751 }
7753 /* Update remained number of bounds to force. */
7760 }
7762 /* The first arg not going to Bounds Tables resets this counter. */
7764 /* For unnamed args we always pass bounds to avoid bounds mess when
7765 passed and received types do not match. If bounds do not follow
7766 unnamed arg, still pretend required number of bounds were passed. */
7768 {
7771 }
7774 {
7779 else
7781 }
7782 else
7785 /* For stdarg we expect bounds to be passed for each value passed
7786 in register. */
7789 /* For pointers passed in memory we expect bounds passed in Bounds
7790 Table. */
7793 }
7795 /* Define where to put the arguments to a function.
7796 Value is zero to push the argument on the stack,
7797 or a hard register in which to store the argument.
7799 MODE is the argument's machine mode.
7800 TYPE is the data type of the argument (as a tree).
7801 This is null for libcalls where that information may
7802 not be available.
7803 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7804 the preceding args and about the function being called.
7805 NAMED is nonzero if this argument is a named parameter
7806 (otherwise it is an extra parameter matching an ellipsis). */
7808 static rtx
7812 {
7814 /* Avoid the AL settings for the Unix64 ABI. */
7819 {
7820 /* Intel MCU psABI passes scalars and aggregates no larger than 8
7821 bytes in registers. */
7825 }
7828 {
7835 /* FALLTHRU */
7840 pass_in_reg:
7842 {
7845 /* Fastcall allocates the first two DWORD (SImode) or
7846 smaller arguments to ECX and EDX if it isn't an
7847 aggregate type . */
7849 {
7855 /* ECX not EAX is the first allocated register. */
7858 }
7860 }
7873 /* FALLTHRU */
7875 /* In 32bit, we pass TImode in xmm registers. */
7883 {
7887 }
7892 /* OImode and XImode shouldn't be used directly. */
7908 {
7912 }
7922 {
7926 }
7928 }
7930 {
7936 }
7939 }
7941 static rtx
7944 {
7945 /* Handle a hidden AL argument containing number of registers
7946 for varargs x86-64 functions. */
7950 ? X86_64_SSE_REGPARM_MAX
7955 {
7971 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7975 }
7981 }
7983 static rtx
7986 HOST_WIDE_INT bytes)
7987 {
7990 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7991 We use value of -2 to specify that current function call is MSABI. */
7995 /* If we've run out of registers, it goes on the stack. */
8001 /* Only floating point modes are passed in anything but integer regs. */
8003 {
8006 else
8007 {
8010 /* Unnamed floating parameters are passed in both the
8011 SSE and integer registers. */
8017 }
8018 }
8019 /* Handle aggregated types passed in register. */
8021 {
8026 }
8029 }
8031 /* Return where to put the arguments to a function.
8032 Return zero to push the argument on the stack, or a hard register in which to store the argument.
8034 MODE is the argument's machine mode. TYPE is the data type of the
8035 argument. It is null for libcalls where that information may not be
8036 available. CUM gives information about the preceding args and about
8037 the function being called. NAMED is nonzero if this argument is a
8038 named parameter (otherwise it is an extra parameter matching an
8039 ellipsis). */
8041 static rtx
8044 {
8048 rtx arg;
8050 /* All pointer bounds argumntas are handled separately here. */
8053 {
8054 /* Return NULL if bounds are forced to go in Bounds Table. */
8057 /* Return the next available bound reg if any. */
8060 /* Return the next special slot number otherwise. */
8061 else
8065 }
8069 else
8073 /* To simplify the code below, represent vector types with a vector mode
8074 even if MMX/SSE are not active. */
8079 {
8084 else
8086 }
8087 else
8091 }
8093 /* A C expression that indicates when an argument must be passed by
8094 reference. If nonzero for an argument, a copy of that argument is
8095 made in memory and a pointer to the argument is passed instead of
8096 the argument itself. The pointer is passed in whatever way is
8097 appropriate for passing a pointer to that type. */
8099 static bool
8102 {
8105 /* Bounds are never passed by reference. */
8111 {
8114 /* See Windows x64 Software Convention. */
8116 {
8120 {
8121 /* Arrays are passed by reference. */
8126 {
8127 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
8128 are passed by reference. */
8130 }
8131 }
8133 /* __m128 is passed by reference. */
8135 }
8138 }
8141 }
8143 /* Return true when TYPE should be 128bit aligned for 32bit argument
8144 passing ABI. XXX: This function is obsolete and is only used for
8145 checking psABI compatibility with previous versions of GCC. */
8147 static bool
8149 {
8161 {
8162 /* Walk the aggregates recursively. */
8164 {
8168 {
8169 tree field;
8171 /* Walk all the structure fields. */
8173 {
8177 }
8179 }
8182 /* Just for use if some languages passes arrays by value. */
8189 }
8190 }
8192 }
8194 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
8195 XXX: This function is obsolete and is only used for checking psABI
8196 compatibility with previous versions of GCC. */
8198 static unsigned int
8201 {
8202 /* In 32bit, only _Decimal128 and __float128 are aligned to their
8203 natural boundaries. */
8205 {
8206 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
8207 make an exception for SSE modes since these require 128bit
8208 alignment.
8210 The handling here differs from field_alignment. ICC aligns MMX
8211 arguments to 4 byte boundaries, while structure fields are aligned
8212 to 8 byte boundaries. */
8214 {
8217 }
8218 else
8219 {
8222 }
8223 }
8227 }
8229 /* Return true when TYPE should be 128bit aligned for 32bit argument
8230 passing ABI. */
8232 static bool
8234 {
8244 {
8245 /* Walk the aggregates recursively. */
8247 {
8251 {
8252 tree field;
8254 /* Walk all the structure fields. */
8256 field;
8258 {
8262 }
8264 }
8267 /* Just for use if some languages passes arrays by value. */
8274 }
8275 }
8276 else
8280 }
8282 /* Gives the alignment boundary, in bits, of an argument with the
8283 specified mode and type. */
8285 static unsigned int
8287 {
8290 {
8291 /* Since the main variant type is used for call, we convert it to
8292 the main variant type. */
8295 }
8296 else
8300 else
8301 {
8306 {
8307 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
8309 {
8312 }
8318 }
8321 && !warned
8323 saved_align))
8324 {
8327 "The ABI for passing parameters with %d-byte"
8330 }
8331 }
8334 }
8336 /* Return true if N is a possible register number of function value. */
8338 static bool
8340 {
8342 {
8355 /* Complex values are returned in %st(0)/%st(1) pair. */
8358 /* TODO: The function should depend on current function ABI but
8359 builtins.c would need updating then. Therefore we use the
8360 default ABI. */
8365 /* Complex values are returned in %xmm0/%xmm1 pair. */
8374 }
8377 }
8379 /* Define how to find the value returned by a function.
8380 VALTYPE is the data type of the value (as a tree).
8381 If the precise function being called is known, FUNC is its FUNCTION_DECL;
8382 otherwise, FUNC is 0. */
8384 static rtx
8387 {
8390 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
8391 we normally prevent this case when mmx is not available. However
8392 some ABIs may require the result to be returned like DImode. */
8396 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
8397 we prevent this case when sse is not available. However some ABIs
8398 may require the result to be returned like integer TImode. */
8403 /* 32-byte vector modes in %ymm0. */
8407 /* 64-byte vector modes in %zmm0. */
8411 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
8414 else
8415 /* Most things go in %eax. */
8418 /* Override FP return register with %xmm0 for local functions when
8419 SSE math is enabled or for functions with sseregparm attribute. */
8421 {
8424 {
8429 }
8433 }
8435 /* OImode shouldn't be used directly. */
8439 }
8441 static rtx
8443 const_tree valtype)
8444 {
8445 rtx ret;
8447 /* Handle libcalls, which don't provide a type node. */
8449 {
8453 {
8472 }
8475 }
8477 {
8478 /* Pointers are always returned in word_mode. */
8480 }
8486 /* For zero sized structures, construct_container returns NULL, but we
8487 need to keep rest of compiler happy by returning meaningful value. */
8492 }
8494 static rtx
8496 const_tree valtype)
8497 {
8501 {
8503 {
8522 }
8523 }
8525 }
8527 static rtx
8530 {
8545 else
8547 }
8549 static rtx
8551 {
8557 }
8559 /* Return an RTX representing a place where a function returns
8560 or recieves pointer bounds or NULL if no bounds are returned.
8562 VALTYPE is a data type of a value returned by the function.
8564 FN_DECL_OR_TYPE is a tree node representing FUNCTION_DECL
8565 or FUNCTION_TYPE of the function.
8567 If OUTGOING is false, return a place in which the caller will
8568 see the return value. Otherwise, return a place where a
8569 function returns a value. */
8571 static rtx
8573 const_tree fntype_or_decl ATTRIBUTE_UNUSED,
8575 {
8581 {
8582 bitmap slots;
8584 bitmap_iterator bi;
8592 {
8597 }
8603 }
8604 else
8608 }
8610 /* Pointer function arguments and return values are promoted to
8611 word_mode. */
8613 static machine_mode
8617 {
8619 {
8622 }
8624 for_return);
8625 }
8627 /* Return true if a structure, union or array with MODE containing FIELD
8628 should be accessed using BLKmode. */
8630 static bool
8632 {
8633 /* Union with XFmode must be in BLKmode. */
8637 }
8639 rtx
8641 {
8643 }
8645 /* Return true iff type is returned in memory. */
8647 static bool
8649 {
8650 #ifdef SUBTARGET_RETURN_IN_MEMORY
8652 #else
8654 HOST_WIDE_INT size;
8660 {
8662 {
8665 /* __m128 is returned in xmm0. */
8674 /* Otherwise, the size must be exactly in [1248]. */
8676 }
8677 else
8678 {
8683 }
8684 }
8685 else
8686 {
8689 /* Intel MCU psABI returns scalars and aggregates no larger than 8
8690 bytes in registers. */
8701 {
8702 /* User-created vectors small enough to fit in EAX. */
8706 /* Unless ABI prescibes otherwise,
8707 MMX/3dNow values are returned in MM0 if available. */
8712 /* SSE values are returned in XMM0 if available. */
8716 /* AVX values are returned in YMM0 if available. */
8720 /* AVX512F values are returned in ZMM0 if available. */
8723 }
8731 /* OImode shouldn't be used directly. */
8735 }
8736 #endif
8737 }
8739 \f
8740 /* Create the va_list data type. */
8742 /* Returns the calling convention specific va_list date type.
8743 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8745 static tree
8747 {
8750 /* For i386 we use plain pointer to argument area. */
8760 unsigned_type_node);
8763 unsigned_type_node);
8766 ptr_type_node);
8769 ptr_type_node);
8788 /* The correct type is an array type of one element. */
8790 }
8792 /* Setup the builtin va_list data type and for 64-bit the additional
8793 calling convention specific va_list data types. */
8795 static tree
8797 {
8800 /* Initialize abi specific va_list builtin types. */
8802 {
8803 tree t;
8805 {
8810 }
8811 else
8812 {
8817 }
8819 {
8824 }
8825 else
8826 {
8831 }
8832 }
8835 }
8837 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8839 static void
8841 {
8843 alias_set_type set;
8846 /* GPR size of varargs save area. */
8849 else
8852 /* FPR size of varargs save area. We don't need it if we don't pass
8853 anything in SSE registers. */
8856 else
8870 {
8878 }
8881 {
8882 machine_mode smode;
8884 rtx test;
8886 /* Now emit code to save SSE registers. The AX parameter contains number
8887 of SSE parameter registers used to call this function, though all we
8888 actually check here is the zero/non-zero status. */
8893 label));
8895 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8896 we used movdqa (i.e. TImode) instead? Perhaps even better would
8897 be if we could determine the real mode of the data, via a hook
8898 into pass_stdarg. Ignore all that for now. */
8908 {
8917 }
8920 }
8921 }
8923 static void
8925 {
8929 /* Reset to zero, as there might be a sysv vaarg used
8930 before. */
8935 {
8946 }
8947 }
8949 static void
8952 {
8954 CUMULATIVE_ARGS next_cum;
8955 tree fntype;
8957 /* This argument doesn't appear to be used anymore. Which is good,
8958 because the old code here didn't suppress rtl generation. */
8966 /* For varargs, we do not want to skip the dummy va_dcl argument.
8967 For stdargs, we do want to skip the last named argument. */
8975 else
8977 }
8979 static void
8982 tree type,
8985 {
8987 CUMULATIVE_ARGS next_cum;
8988 tree fntype;
8989 rtx save_area;
8994 /* Do nothing if we use plain pointer to argument area. */
9000 /* For varargs, we do not want to skip the dummy va_dcl argument.
9001 For stdargs, we do want to skip the last named argument. */
9015 {
9019 rtx bounds;
9023 else
9024 {
9025 rtx ldx_addr =
9032 }
9038 bnd_reg++;
9039 }
9040 }
9043 /* Checks if TYPE is of kind va_list char *. */
9045 static bool
9047 {
9048 tree canonic;
9050 /* For 32-bit it is always true. */
9056 }
9058 /* Implement va_start. */
9060 static void
9062 {
9066 tree type;
9067 rtx ovf_rtx;
9071 {
9074 /* When we are splitting the stack, we can't refer to the stack
9075 arguments using internal_arg_pointer, because they may be on
9076 the old stack. The split stack prologue will arrange to
9077 leave a pointer to the old stack arguments in a scratch
9078 register, which we here copy to a pseudo-register. The split
9079 stack prologue can't set the pseudo-register directly because
9080 it (the prologue) runs before any registers have been saved. */
9084 {
9085 rtx reg;
9099 }
9100 }
9102 /* Only 64bit target needs something special. */
9104 {
9107 else
9108 {
9118 /* Store zero bounds for va_list. */
9122 next));
9124 }
9126 }
9135 /* The following should be folded into the MEM_REF offset. */
9145 /* Count number of gp and fp argument registers used. */
9151 {
9157 }
9160 {
9166 }
9168 /* Find the overflow area. */
9172 else
9178 /* Store zero bounds for overflow area pointer. */
9187 {
9188 /* Find the register save area.
9189 Prologue of the function save it right above stack frame. */
9195 /* Store zero bounds for save area pointer. */
9202 }
9203 }
9205 /* Implement va_arg. */
9207 static tree
9210 {
9217 rtx container;
9219 tree ptrtype;
9220 machine_mode nat_mode;
9223 /* Only 64bit target needs something special. */
9247 {
9260 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
9262 {
9265 }
9273 }
9275 /* Pull the value out of the saved registers. */
9280 {
9294 /* In case we are passing structure, verify that it is consecutive block
9295 on the register save area. If not we need to do moves. */
9297 {
9298 /* Verify that all registers are strictly consecutive */
9300 {
9304 {
9309 }
9310 }
9311 else
9312 {
9316 {
9321 }
9322 }
9323 }
9325 {
9328 }
9329 else
9330 {
9333 }
9335 /* First ensure that we fit completely in registers. */
9337 {
9344 }
9346 {
9354 }
9356 /* Compute index to start of area used for integer regs. */
9358 {
9359 /* int_addr = gpr + sav; */
9362 }
9364 {
9365 /* sse_addr = fpr + sav; */
9368 }
9370 {
9374 /* addr = &temp; */
9379 {
9383 tree piece_type;
9384 tree addr_type;
9385 tree daddr_type;
9394 {
9399 }
9403 else
9410 {
9413 }
9414 else
9415 {
9418 }
9425 {
9430 }
9431 else
9432 {
9433 tree copy
9438 }
9440 }
9441 }
9444 {
9448 }
9451 {
9455 }
9460 }
9462 /* ... otherwise out of the overflow area. */
9464 /* When we align parameter on stack for caller, if the parameter
9465 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
9466 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
9467 here with caller. */
9472 /* Care for on-stack alignment if needed. */
9475 else
9476 {
9481 }
9498 }
9499 \f
9500 /* Return true if OPNUM's MEM should be matched
9501 in movabs* patterns. */
9503 bool
9505 {
9517 }
9518 \f
9519 /* Initialize the table of extra 80387 mathematical constants. */
9521 static void
9523 {
9525 {
9531 };
9535 {
9537 /* Ensure each constant is rounded to XFmode precision. */
9540 }
9543 }
9545 /* Return non-zero if the constant is something that
9546 can be loaded with a special instruction. */
9548 int
9550 {
9553 REAL_VALUE_TYPE r;
9565 /* For XFmode constants, try to find a special 80387 instruction when
9566 optimizing for size or on those CPUs that benefit from them. */
9569 {
9578 }
9580 /* Load of the constant -0.0 or -1.0 will be split as
9581 fldz;fchs or fld1;fchs sequence. */
9588 }
9590 /* Return the opcode of the special instruction to be used to load
9591 the constant X. */
9595 {
9597 {
9617 }
9618 }
9620 /* Return the CONST_DOUBLE representing the 80387 constant that is
9621 loaded by the specified special instruction. The argument IDX
9622 matches the return value from standard_80387_constant_p. */
9624 rtx
9626 {
9633 {
9644 }
9647 XFmode);
9648 }
9650 /* Return 1 if X is all 0s and 2 if x is all 1s
9651 in supported SSE/AVX vector mode. */
9653 int
9655 {
9656 machine_mode mode;
9667 {
9688 }
9691 }
9693 /* Return the opcode of the special instruction to be used to load
9694 the constant X. */
9698 {
9700 {
9703 {
9730 }
9740 else
9745 }
9747 }
9749 /* Returns true if OP contains a symbol reference */
9751 bool
9753 {
9762 {
9764 {
9770 }
9774 }
9777 }
9779 /* Return true if it is appropriate to emit `ret' instructions in the
9780 body of a function. Do this only if the epilogue is simple, needing a
9781 couple of insns. Prior to reloading, we can't tell how many registers
9782 must be saved, so return false then. Return false if there is no frame
9783 marker to de-allocate. */
9785 bool
9787 {
9793 /* Don't allow more than 32k pop, since that's all we can do
9794 with one instruction. */
9801 }
9802 \f
9803 /* Value should be nonzero if functions must have frame pointers.
9804 Zero means the frame pointer need not be set up (and parms may
9805 be accessed via the stack pointer) in functions that seem suitable. */
9807 static bool
9809 {
9810 /* If we accessed previous frames, then the generated code expects
9811 to be able to access the saved ebp value in our frame. */
9815 /* Several x86 os'es need a frame pointer for other reasons,
9816 usually pertaining to setjmp. */
9820 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9824 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9825 allocation is 4GB. */
9829 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9830 turns off the frame pointer by default. Turn it back on now if
9831 we've not got a leaf function. */
9841 }
9843 /* Record that the current function accesses previous call frames. */
9845 void
9847 {
9849 }
9850 \f
9851 #ifndef USE_HIDDEN_LINKONCE
9852 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9853 # define USE_HIDDEN_LINKONCE 1
9854 # else
9855 # define USE_HIDDEN_LINKONCE 0
9856 # endif
9857 #endif
9861 /* Fills in the label name that should be used for a pc thunk for
9862 the given register. */
9864 static void
9866 {
9871 else
9873 }
9876 /* This function generates code for -fpic that loads %ebx with
9877 the return address of the caller and then returns. */
9879 static void
9881 {
9886 {
9888 tree decl;
9904 #if TARGET_MACHO
9906 {
9915 }
9916 else
9917 #endif
9919 {
9930 }
9931 else
9932 {
9935 }
9941 /* Make sure unwind info is emitted for the thunk if needed. */
9944 /* Pad stack IP move with 4 instructions (two NOPs count
9945 as one instruction). */
9947 {
9952 }
9963 }
9967 }
9969 /* Emit code for the SET_GOT patterns. */
9973 {
9979 {
9980 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9985 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9986 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9987 an unadorned address. */
9992 }
9997 {
9999 /* We don't need a pic base, we're not producing pic. */
10006 }
10007 else
10008 {
10017 #if TARGET_MACHO
10018 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
10019 This is what will be referenced by the Mach-O PIC subsystem. */
10023 /* When we are restoring the pic base at the site of a nonlocal label,
10024 and we decided to emit the pic base above, we will still output a
10025 local label used for calculating the correction offset (even though
10026 the offset will be 0 in that case). */
10030 #endif
10031 }
10037 }
10039 /* Generate an "push" pattern for input ARG. */
10041 static rtx
10043 {
10055 stack_pointer_rtx)),
10056 arg);
10057 }
10059 /* Generate an "pop" pattern for input ARG. */
10061 static rtx
10063 {
10070 stack_pointer_rtx)));
10071 }
10073 /* Return >= 0 if there is an unused call-clobbered register available
10074 for the entire function. */
10076 static unsigned int
10078 {
10085 {
10087 /* Can't use the same register for both PIC and DRAP. */
10090 else
10095 }
10098 }
10100 /* Return TRUE if we need to save REGNO. */
10102 static bool
10104 {
10107 {
10109 {
10110 /* REAL_PIC_OFFSET_TABLE_REGNUM used by call to
10111 _mcount in prologue. */
10114 }
10121 }
10124 {
10127 {
10133 }
10134 }
10145 }
10147 /* Return number of saved general prupose registers. */
10149 static int
10151 {
10157 nregs ++;
10159 }
10161 /* Return number of saved SSE registrers. */
10163 static int
10165 {
10173 nregs ++;
10175 }
10177 /* Given FROM and TO register numbers, say whether this elimination is
10178 allowed. If stack alignment is needed, we can only replace argument
10179 pointer with hard frame pointer, or replace frame pointer with stack
10180 pointer. Otherwise, frame pointer elimination is automatically
10181 handled and all other eliminations are valid. */
10183 static bool
10185 {
10191 else
10193 }
10195 /* Return the offset between two registers, one to be eliminated, and the other
10196 its replacement, at the start of a routine. */
10198 HOST_WIDE_INT
10200 {
10209 else
10210 {
10218 }
10219 }
10221 /* In a dynamically-aligned function, we can't know the offset from
10222 stack pointer to frame pointer, so we must ensure that setjmp
10223 eliminates fp against the hard fp (%ebp) rather than trying to
10224 index from %esp up to the top of the frame across a gap that is
10225 of unknown (at compile-time) size. */
10226 static rtx
10228 {
10230 }
10232 /* When using -fsplit-stack, the allocation routines set a field in
10233 the TCB to the bottom of the stack plus this much space, measured
10234 in bytes. */
10236 #define SPLIT_STACK_AVAILABLE 256
10238 /* Fill structure ix86_frame about frame of currently computed function. */
10240 static void
10242 {
10244 HOST_WIDE_INT offset;
10247 HOST_WIDE_INT to_allocate;
10252 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
10253 function prologues and leaf. */
10257 {
10260 }
10261 /* preferred_stack_boundary is never updated for call
10262 expanded from tls descriptor. Update it here. We don't update it in
10263 expand stage because according to the comments before
10264 ix86_current_function_calls_tls_descriptor, tls calls may be optimized
10265 away. */
10268 {
10272 }
10281 /* For SEH we have to limit the amount of code movement into the prologue.
10282 At present we do this via a BLOCKAGE, at which point there's very little
10283 scheduling that can be done, which means that there's very little point
10284 in doing anything except PUSHs. */
10288 /* During reload iteration the amount of registers saved can change.
10289 Recompute the value as needed. Do not recompute when amount of registers
10290 didn't change as reload does multiple calls to the function and does not
10291 expect the decision to change within single iteration. */
10294 {
10300 /* The fast prologue uses move instead of push to save registers. This
10301 is significantly longer, but also executes faster as modern hardware
10302 can execute the moves in parallel, but can't do that for push/pop.
10304 Be careful about choosing what prologue to emit: When function takes
10305 many instructions to execute we may use slow version as well as in
10306 case function is known to be outside hot spot (this is known with
10307 feedback only). Weight the size of function by number of registers
10308 to save as it is cheap to use one or two push instructions but very
10309 slow to use many of them. */
10313 || (flag_branch_probabilities
10316 else
10319 }
10321 frame->save_regs_using_mov
10323 /* If static stack checking is enabled and done with probes,
10324 the registers need to be saved before allocating the frame. */
10327 /* Skip return address. */
10330 /* Skip pushed static chain. */
10334 /* Skip saved base pointer. */
10339 /* The traditional frame pointer location is at the top of the frame. */
10342 /* Register save area */
10346 /* On SEH target, registers are pushed just before the frame pointer
10347 location. */
10351 /* Align and set SSE register save area. */
10353 {
10354 /* The only ABI that has saved SSE registers (Win64) also has a
10355 16-byte aligned default stack, and thus we don't need to be
10356 within the re-aligned local stack frame to save them. */
10360 }
10363 /* The re-aligned stack starts here. Values before this point are not
10364 directly comparable with values below this point. In order to make
10365 sure that no value happens to be the same before and after, force
10366 the alignment computation below to add a non-zero value. */
10370 /* Va-arg area */
10374 /* Align start of frame for local function. */
10383 /* Frame pointer points here. */
10388 /* Add outgoing arguments area. Can be skipped if we eliminated
10389 all the function calls as dead code.
10390 Skipping is however impossible when function calls alloca. Alloca
10391 expander assumes that last crtl->outgoing_args_size
10392 of stack frame are unused. */
10396 {
10399 }
10400 else
10403 /* Align stack boundary. Only needed if we're calling another function
10404 or using alloca. */
10409 /* We've reached end of stack frame. */
10412 /* Size prologue needs to allocate. */
10423 {
10429 }
10430 else
10434 /* The SEH frame pointer location is near the bottom of the frame.
10435 This is enforced by the fact that the difference between the
10436 stack pointer and the frame pointer is limited to 240 bytes in
10437 the unwind data structure. */
10439 {
10440 HOST_WIDE_INT diff;
10442 /* If we can leave the frame pointer where it is, do so. Also, returns
10443 the establisher frame for __builtin_frame_address (0). */
10448 {
10449 /* Ideally we'd determine what portion of the local stack frame
10450 (within the constraint of the lowest 240) is most heavily used.
10451 But without that complication, simply bias the frame pointer
10452 by 128 bytes so as to maximize the amount of the local stack
10453 frame that is addressable with 8-bit offsets. */
10455 }
10456 }
10457 }
10459 /* This is semi-inlined memory_address_length, but simplified
10460 since we know that we're always dealing with reg+offset, and
10461 to avoid having to create and discard all that rtl. */
10465 {
10469 {
10470 /* EBP and R13 cannot be encoded without an offset. */
10472 }
10476 /* ESP and R12 must be encoded with a SIB byte. */
10478 len++;
10481 }
10483 /* Return an RTX that points to CFA_OFFSET within the stack frame.
10484 The valid base registers are taken from CFUN->MACHINE->FS. */
10486 static rtx
10488 {
10494 {
10495 /* Choose the base register most likely to allow the most scheduling
10496 opportunities. Generally FP is valid throughout the function,
10497 while DRAP must be reloaded within the epilogue. But choose either
10498 over the SP due to increased encoding size. */
10501 {
10504 }
10506 {
10509 }
10511 {
10514 }
10515 }
10516 else
10517 {
10518 HOST_WIDE_INT toffset;
10521 /* Choose the base register with the smallest address encoding.
10522 With a tie, choose FP > DRAP > SP. */
10524 {
10528 }
10530 {
10534 {
10538 }
10539 }
10541 {
10545 {
10549 }
10550 }
10551 }
10555 }
10557 /* Emit code to save registers in the prologue. */
10559 static void
10561 {
10567 {
10570 }
10571 }
10573 /* Emit a single register save at CFA - CFA_OFFSET. */
10575 static void
10577 HOST_WIDE_INT cfa_offset)
10578 {
10586 /* For SSE saves, we need to indicate the 128-bit alignment. */
10597 /* When saving registers into a re-aligned local stack frame, avoid
10598 any tricky guessing by dwarf2out. */
10600 {
10604 {
10605 /* A bit of a hack. We force the DRAP register to be saved in
10606 the re-aligned stack frame, which provides us with a copy
10607 of the CFA that will last past the prologue. Install it. */
10613 }
10614 else
10615 {
10616 /* The frame pointer is a stable reference within the
10617 aligned frame. Use it. */
10623 }
10624 }
10626 /* The memory may not be relative to the current CFA register,
10627 which means that we may need to generate a new pattern for
10628 use by the unwind info. */
10630 {
10635 }
10636 }
10638 /* Emit code to save registers using MOV insns.
10639 First register is stored at CFA - CFA_OFFSET. */
10640 static void
10642 {
10647 {
10650 }
10651 }
10653 /* Emit code to save SSE registers using MOV insns.
10654 First register is stored at CFA - CFA_OFFSET. */
10655 static void
10657 {
10662 {
10665 }
10666 }
10670 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
10671 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
10672 Don't add the note if the previously saved value will be left untouched
10673 within stack red-zone till return, as unwinders can find the same value
10674 in the register and on the stack. */
10676 static void
10678 {
10684 {
10687 }
10688 else
10689 queued_cfa_restores
10691 }
10693 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
10695 static void
10697 {
10698 rtx last;
10702 ;
10707 }
10709 /* Expand prologue or epilogue stack adjustment.
10710 The pattern exist to put a dependency on all ebp-based memory accesses.
10711 STYLE should be negative if instructions should be marked as frame related,
10712 zero if %r11 register is live and cannot be freely used and positive
10713 otherwise. */
10715 static void
10718 {
10720 rtx insn;
10727 else
10728 {
10729 rtx tmp;
10730 /* r11 is used by indirect sibcall return as well, set before the
10731 epilogue and used after the epilogue. */
10734 else
10735 {
10739 }
10745 }
10752 {
10753 rtx r;
10763 }
10765 {
10768 {
10772 }
10773 }
10776 {
10781 {
10784 }
10786 {
10789 }
10790 else
10791 {
10792 /* Else there are two possibilities: SP itself, which we set
10793 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10794 taken care of this by hand along the eh_return path. */
10797 }
10801 }
10802 }
10804 /* Find an available register to be used as dynamic realign argument
10805 pointer regsiter. Such a register will be written in prologue and
10806 used in begin of body, so it must not be
10807 1. parameter passing register.
10808 2. GOT pointer.
10809 We reuse static-chain register if it is available. Otherwise, we
10810 use DI for i386 and R13 for x86-64. We chose R13 since it has
10811 shorter encoding.
10813 Return: the regno of chosen register. */
10815 static unsigned int
10817 {
10821 {
10822 /* Use R13 for nested function or function need static chain.
10823 Since function with tail call may use any caller-saved
10824 registers in epilogue, DRAP must not use caller-saved
10825 register in such case. */
10830 }
10831 else
10832 {
10833 /* Use DI for nested function or function need static chain.
10834 Since function with tail call may use any caller-saved
10835 registers in epilogue, DRAP must not use caller-saved
10836 register in such case. */
10840 /* Reuse static chain register if it isn't used for parameter
10841 passing. */
10843 {
10847 }
10849 }
10850 }
10852 /* Return minimum incoming stack alignment. */
10854 static unsigned int
10856 {
10859 /* Prefer the one specified at command line. */
10862 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10863 if -mstackrealign is used, it isn't used for sibcall check and
10864 estimated stack alignment is 128bit. */
10866 && !TARGET_64BIT
10867 && ix86_force_align_arg_pointer
10870 else
10873 /* Incoming stack alignment can be changed on individual functions
10874 via force_align_arg_pointer attribute. We use the smallest
10875 incoming stack boundary. */
10881 /* The incoming stack frame has to be aligned at least at
10882 parm_stack_boundary. */
10886 /* Stack at entrance of main is aligned by runtime. We use the
10887 smallest incoming stack boundary. */
10895 }
10897 /* Update incoming stack boundary and estimated stack alignment. */
10899 static void
10901 {
10902 ix86_incoming_stack_boundary
10905 /* x86_64 vararg needs 16byte stack alignment for register save
10906 area. */
10911 }
10913 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10914 needed or an rtx for DRAP otherwise. */
10916 static rtx
10918 {
10923 {
10924 /* Assign DRAP to vDRAP and returns vDRAP */
10926 rtx drap_vreg;
10927 rtx arg_ptr;
10940 {
10943 }
10945 }
10946 else
10948 }
10950 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10952 static rtx
10954 {
10956 }
10959 rtx reg;
10961 };
10963 /* Return a short-lived scratch register for use on function entry.
10964 In 32-bit mode, it is valid only after the registers are saved
10965 in the prologue. This register must be released by means of
10966 release_scratch_register_on_entry once it is dead. */
10968 static void
10970 {
10976 {
10977 /* We always use R11 in 64-bit mode. */
10979 }
10980 else
10981 {
10983 bool fastcall_p
10985 bool thiscall_p
10989 int drap_regno
10992 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10993 for the static chain register. */
10997 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10998 for the static chain register. */
11003 /* ecx is the static chain register. */
11005 && !static_chain_p
11010 /* esi is the static chain register. */
11016 else
11017 {
11020 }
11021 }
11025 {
11028 }
11029 }
11031 /* Release a scratch register obtained from the preceding function. */
11033 static void
11035 {
11037 {
11041 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
11047 }
11048 }
11050 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
11052 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
11054 static void
11056 {
11057 /* We skip the probe for the first interval + a small dope of 4 words and
11058 probe that many bytes past the specified size to maintain a protection
11059 area at the botton of the stack. */
11063 /* See if we have a constant small number of probes to generate. If so,
11064 that's the easy case. The run-time loop is made up of 11 insns in the
11065 generic case while the compile-time loop is made up of 3+2*(n-1) insns
11066 for n # of intervals. */
11068 {
11072 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
11073 values of N from 1 until it exceeds SIZE. If only one probe is
11074 needed, this will not generate any code. Then adjust and probe
11075 to PROBE_INTERVAL + SIZE. */
11077 {
11079 {
11082 }
11083 else
11090 }
11094 else
11102 /* Adjust back to account for the additional first interval. */
11106 }
11108 /* Otherwise, do the same as above, but in a loop. Note that we must be
11109 extra careful with variables wrapping around because we might be at
11110 the very top (or the very bottom) of the address space and we have
11111 to be able to handle this case properly; in particular, we use an
11112 equality test for the loop condition. */
11113 else
11114 {
11115 HOST_WIDE_INT rounded_size;
11121 /* Step 1: round SIZE to the previous multiple of the interval. */
11126 /* Step 2: compute initial and final value of the loop counter. */
11128 /* SP = SP_0 + PROBE_INTERVAL. */
11133 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
11137 stack_pointer_rtx)));
11140 /* Step 3: the loop
11142 while (SP != LAST_ADDR)
11143 {
11144 SP = SP + PROBE_INTERVAL
11145 probe at SP
11146 }
11148 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
11149 values of N from 1 until it is equal to ROUNDED_SIZE. */
11154 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
11155 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
11158 {
11163 }
11165 /* Adjust back to account for the additional first interval. */
11171 }
11175 /* Even if the stack pointer isn't the CFA register, we need to correctly
11176 describe the adjustments made to it, in particular differentiate the
11177 frame-related ones from the frame-unrelated ones. */
11179 {
11192 }
11194 /* Make sure nothing is scheduled before we are done. */
11196 }
11198 /* Adjust the stack pointer up to REG while probing it. */
11202 {
11212 /* Jump to END_LAB if SP == LAST_ADDR. */
11220 /* SP = SP + PROBE_INTERVAL. */
11224 /* Probe at SP. */
11235 }
11237 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
11238 inclusive. These are offsets from the current stack pointer. */
11240 static void
11242 {
11243 /* See if we have a constant small number of probes to generate. If so,
11244 that's the easy case. The run-time loop is made up of 7 insns in the
11245 generic case while the compile-time loop is made up of n insns for n #
11246 of intervals. */
11248 {
11249 HOST_WIDE_INT i;
11251 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
11252 it exceeds SIZE. If only one probe is needed, this will not
11253 generate any code. Then probe at FIRST + SIZE. */
11260 }
11262 /* Otherwise, do the same as above, but in a loop. Note that we must be
11263 extra careful with variables wrapping around because we might be at
11264 the very top (or the very bottom) of the address space and we have
11265 to be able to handle this case properly; in particular, we use an
11266 equality test for the loop condition. */
11267 else
11268 {
11275 /* Step 1: round SIZE to the previous multiple of the interval. */
11280 /* Step 2: compute initial and final value of the loop counter. */
11282 /* TEST_OFFSET = FIRST. */
11285 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
11289 /* Step 3: the loop
11291 while (TEST_ADDR != LAST_ADDR)
11292 {
11293 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11294 probe at TEST_ADDR
11295 }
11297 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11298 until it is equal to ROUNDED_SIZE. */
11303 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11304 that SIZE is equal to ROUNDED_SIZE. */
11309 stack_pointer_rtx,
11314 }
11316 /* Make sure nothing is scheduled before we are done. */
11318 }
11320 /* Probe a range of stack addresses from REG to END, inclusive. These are
11321 offsets from the current stack pointer. */
11325 {
11335 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11343 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11347 /* Probe at TEST_ADDR. */
11360 }
11362 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
11363 to be generated in correct form. */
11364 static void
11366 {
11367 /* Check if stack realign is really needed after reload, and
11368 stores result in cfun */
11369 unsigned int incoming_stack_boundary
11378 {
11379 /* After stack_realign_needed is finalized, we can't no longer
11380 change it. */
11383 }
11385 /* If the only reason for frame_pointer_needed is that we conservatively
11386 assumed stack realignment might be needed, but in the end nothing that
11387 needed the stack alignment had been spilled, clear frame_pointer_needed
11388 and say we don't need stack realignment. */
11390 && frame_pointer_needed
11392 && flag_omit_frame_pointer
11394 && !ix86_current_function_calls_tls_descriptor
11403 {
11405 basic_block bb;
11412 HARD_FRAME_POINTER_REGNUM);
11414 {
11419 set_up_by_prologue))
11420 {
11424 }
11425 }
11427 /* If drap has been set, but it actually isn't live at the start
11428 of the function, there is no reason to set it up. */
11430 {
11433 {
11436 }
11437 }
11438 else
11453 }
11457 }
11459 /* Delete SET_GOT right after entry block if it is allocated to reg. */
11461 static void
11463 {
11469 {
11472 {
11478 }
11479 }
11480 }
11482 /* Expand the prologue into a bunch of separate insns. */
11484 void
11486 {
11490 HOST_WIDE_INT allocate;
11496 /* DRAP should not coexist with stack_realign_fp */
11501 /* Initialize CFA state for before the prologue. */
11505 /* Track SP offset to the CFA. We continue tracking this after we've
11506 swapped the CFA register away from SP. In the case of re-alignment
11507 this is fudged; we're interested to offsets within the local frame. */
11514 {
11515 /* We should have already generated an error for any use of
11516 ms_hook on a nested function. */
11519 /* Check if profiling is active and we shall use profiling before
11520 prologue variant. If so sorry. */
11525 /* In ix86_asm_output_function_label we emitted:
11526 8b ff movl.s %edi,%edi
11527 55 push %ebp
11528 8b ec movl.s %esp,%ebp
11530 This matches the hookable function prologue in Win32 API
11531 functions in Microsoft Windows XP Service Pack 2 and newer.
11532 Wine uses this to enable Windows apps to hook the Win32 API
11533 functions provided by Wine.
11535 What that means is that we've already set up the frame pointer. */
11539 {
11542 /* We've decided to use the frame pointer already set up.
11543 Describe this to the unwinder by pretending that both
11544 push and mov insns happen right here.
11546 Putting the unwind info here at the end of the ms_hook
11547 is done so that we can make absolutely certain we get
11548 the required byte sequence at the start of the function,
11549 rather than relying on an assembler that can produce
11550 the exact encoding required.
11552 However it does mean (in the unpatched case) that we have
11553 a 1 insn window where the asynchronous unwind info is
11554 incorrect. However, if we placed the unwind info at
11555 its correct location we would have incorrect unwind info
11556 in the patched case. Which is probably all moot since
11557 I don't expect Wine generates dwarf2 unwind info for the
11558 system libraries that use this feature. */
11564 stack_pointer_rtx);
11572 /* Note that gen_push incremented m->fs.cfa_offset, even
11573 though we didn't emit the push insn here. */
11577 }
11578 else
11579 {
11580 /* The frame pointer is not needed so pop %ebp again.
11581 This leaves us with a pristine state. */
11583 }
11584 }
11586 /* The first insn of a function that accepts its static chain on the
11587 stack is to push the register that would be filled in by a direct
11588 call. This insn will be skipped by the trampoline. */
11590 {
11594 /* We don't want to interpret this push insn as a register save,
11595 only as a stack adjustment. The real copy of the register as
11596 a save will be done later, if needed. */
11601 }
11603 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
11604 of DRAP is needed and stack realignment is really needed after reload */
11606 {
11609 /* Only need to push parameter pointer reg if it is caller saved. */
11611 {
11612 /* Push arg pointer reg */
11615 }
11617 /* Grab the argument pointer. */
11624 /* Align the stack. */
11626 stack_pointer_rtx,
11630 /* Replicate the return address on the stack so that return
11631 address can be reached via (argp - 1) slot. This is needed
11632 to implement macro RETURN_ADDR_RTX and intrinsic function
11633 expand_builtin_return_addr etc. */
11639 /* For the purposes of frame and register save area addressing,
11640 we've started over with a new frame. */
11643 }
11649 {
11650 /* Note: AT&T enter does NOT have reversed args. Enter is probably
11651 slower on all targets. Also sdb doesn't like it. */
11655 /* Push registers now, before setting the frame pointer
11656 on SEH target. */
11658 && TARGET_SEH
11660 {
11664 }
11667 {
11675 }
11676 }
11679 {
11680 /* If saving registers via PUSH, do so now. */
11682 {
11686 }
11688 /* When using red zone we may start register saving before allocating
11689 the stack frame saving one cycle of the prologue. However, avoid
11690 doing this if we have to probe the stack; at least on x86_64 the
11691 stack probe can turn into a call that clobbers a red zone location. */
11693 && (! TARGET_STACK_PROBE
11695 {
11698 }
11699 }
11702 {
11706 /* The computation of the size of the re-aligned stack frame means
11707 that we must allocate the size of the register save area before
11708 performing the actual alignment. Otherwise we cannot guarantee
11709 that there's enough storage above the realignment point. */
11716 /* Align the stack. */
11718 stack_pointer_rtx,
11721 /* For the purposes of register save area addressing, the stack
11722 pointer is no longer valid. As for the value of sp_offset,
11723 see ix86_compute_frame_layout, which we need to match in order
11724 to pass verification of stack_pointer_offset at the end. */
11727 }
11732 {
11733 /* We start to count from ARG_POINTER. */
11736 /* If it was realigned, take into account the fake frame. */
11738 {
11745 /* This over-estimates by 1 minimal-stack-alignment-unit but
11746 mitigates that by counting in the new return address slot. */
11747 current_function_dynamic_stack_size
11749 }
11752 }
11754 /* On SEH target with very large frame size, allocate an area to save
11755 SSE registers (as the very large allocation won't be described). */
11759 {
11760 HOST_WIDE_INT sse_size =
11765 /* No need to do stack checking as the area will be immediately
11766 written. */
11773 }
11775 /* The stack has already been decremented by the instruction calling us
11776 so probe if the size is non-negative to preserve the protection area. */
11778 {
11779 /* We expect the registers to be saved when probes are used. */
11783 {
11786 {
11789 }
11790 }
11791 else
11792 {
11799 {
11801 {
11804 }
11805 else
11807 }
11808 else
11809 {
11811 {
11815 }
11816 else
11818 }
11819 }
11820 }
11823 ;
11826 {
11830 }
11831 else
11832 {
11844 {
11847 /* Note that SEH directives need to continue tracking the stack
11848 pointer even after the frame pointer has been set up. */
11850 {
11858 }
11859 }
11862 {
11867 {
11875 }
11876 }
11881 /* Use the fact that AX still contains ALLOCATE. */
11883 ? gen_pro_epilogue_adjust_stack_di_sub
11890 {
11898 }
11901 /* Use stack_pointer_rtx for relative addressing so that code
11902 works for realigned stack, too. */
11904 {
11911 }
11913 {
11918 }
11919 }
11922 /* If we havn't already set up the frame pointer, do so now. */
11924 {
11936 }
11943 /* For the mcount profiling on 32 bit PIC mode we need to emit SET_GOT
11944 in PROLOGUE. */
11946 {
11952 /* Deleting already emmitted SET_GOT if exist and allocated to
11953 REAL_PIC_OFFSET_TABLE_REGNUM. */
11955 }
11958 {
11959 /* vDRAP is setup but after reload it turns out stack realign
11960 isn't necessary, here we will emit prologue to setup DRAP
11961 without stack realign adjustment */
11964 }
11966 /* Prevent instructions from being scheduled into register save push
11967 sequence when access to the redzone area is done through frame pointer.
11968 The offset between the frame pointer and the stack pointer is calculated
11969 relative to the value of the stack pointer at the end of the function
11970 prologue, and moving instructions that access redzone area via frame
11971 pointer inside push sequence violates this assumption. */
11975 /* Emit cld instruction if stringops are used in the function. */
11979 /* SEH requires that the prologue end within 256 bytes of the start of
11980 the function. Prevent instruction schedules that would extend that.
11981 Further, prevent alloca modifications to the stack pointer from being
11982 combined with prologue modifications. */
11985 }
11987 /* Emit code to restore REG using a POP insn. */
11989 static void
11991 {
12000 {
12001 /* Previously we'd represented the CFA as an expression
12002 like *(%ebp - 8). We've just popped that value from
12003 the stack, which means we need to reset the CFA to
12004 the drap register. This will remain until we restore
12005 the stack pointer. */
12009 /* This means that the DRAP register is valid for addressing too. */
12012 }
12015 {
12022 }
12024 /* When the frame pointer is the CFA, and we pop it, we are
12025 swapping back to the stack pointer as the CFA. This happens
12026 for stack frames that don't allocate other data, so we assume
12027 the stack pointer is now pointing at the return address, i.e.
12028 the function entry state, which makes the offset be 1 word. */
12030 {
12033 {
12041 }
12042 }
12043 }
12045 /* Emit code to restore saved registers using POP insns. */
12047 static void
12049 {
12055 }
12057 /* Emit code and notes for the LEAVE instruction. */
12059 static void
12061 {
12073 {
12081 }
12084 }
12086 /* Emit code to restore saved registers using MOV insns.
12087 First register is restored from CFA - CFA_OFFSET. */
12088 static void
12091 {
12097 {
12099 rtx mem;
12107 {
12108 /* Previously we'd represented the CFA as an expression
12109 like *(%ebp - 8). We've just popped that value from
12110 the stack, which means we need to reset the CFA to
12111 the drap register. This will remain until we restore
12112 the stack pointer. */
12116 /* This means that the DRAP register is valid for addressing. */
12118 }
12119 else
12123 }
12124 }
12126 /* Emit code to restore saved registers using MOV insns.
12127 First register is restored from CFA - CFA_OFFSET. */
12128 static void
12131 {
12136 {
12138 rtx mem;
12148 }
12149 }
12151 /* Restore function stack, frame, and registers. */
12153 void
12155 {
12171 /* The FP must be valid if the frame pointer is present. */
12176 /* We must have *some* valid pointer to the stack frame. */
12179 /* The DRAP is never valid at this point. */
12182 /* See the comment about red zone and frame
12183 pointer usage in ix86_expand_prologue. */
12190 /* Determine the CFA offset of the end of the red-zone. */
12193 {
12194 /* The red-zone begins below the return address. */
12197 /* When the register save area is in the aligned portion of
12198 the stack, determine the maximum runtime displacement that
12199 matches up with the aligned frame. */
12203 }
12205 /* Special care must be taken for the normal return case of a function
12206 using eh_return: the eax and edx registers are marked as saved, but
12207 not restored along this path. Adjust the save location to match. */
12211 /* EH_RETURN requires the use of moves to function properly. */
12214 /* SEH requires the use of pops to identify the epilogue. */
12217 /* If we're only restoring one register and sp is not valid then
12218 using a move instruction to restore the register since it's
12219 less work than reloading sp and popping the register. */
12232 && TARGET_USE_LEAVE
12236 else
12240 {
12241 /* Ensure that the entire register save area is addressable via
12242 the stack pointer, if we will restore via sp. */
12247 {
12251 style,
12253 }
12254 }
12256 /* If there are any SSE registers to restore, then we have to do it
12257 via moves, since there's obviously no pop for SSE regs. */
12263 {
12264 rtx t;
12269 /* eh_return epilogues need %ecx added to the stack pointer. */
12271 {
12275 /* Stack align doesn't work with eh_return. */
12277 /* Neither does regparm nested functions. */
12281 {
12289 /* Note that we use SA as a temporary CFA, as the return
12290 address is at the proper place relative to it. We
12291 pretend this happens at the FP restore insn because
12292 prior to this insn the FP would be stored at the wrong
12293 offset relative to SA, and after this insn we have no
12294 other reasonable register to use for the CFA. We don't
12295 bother resetting the CFA to the SP for the duration of
12296 the return insn. */
12309 }
12310 else
12311 {
12319 {
12323 UNITS_PER_WORD));
12325 }
12326 }
12329 }
12330 }
12331 else
12332 {
12333 /* SEH requires that the function end with (1) a stack adjustment
12334 if necessary, (2) a sequence of pops, and (3) a return or
12335 jump instruction. Prevent insns from the function body from
12336 being scheduled into this sequence. */
12338 {
12339 /* Prevent a catch region from being adjacent to the standard
12340 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
12341 several other flags that would be interesting to test are
12342 not yet set up. */
12345 else
12347 }
12349 /* First step is to deallocate the stack frame so that we can
12350 pop the registers. Also do it on SEH target for very large
12351 frame as the emitted instructions aren't allowed by the ABI in
12352 epilogues. */
12354 || (TARGET_SEH
12357 {
12362 }
12364 {
12368 style,
12370 }
12373 }
12375 /* If we used a stack pointer and haven't already got rid of it,
12376 then do so now. */
12378 {
12379 /* If the stack pointer is valid and pointing at the frame
12380 pointer store address, then we only need a pop. */
12383 /* Leave results in shorter dependency chains on CPUs that are
12384 able to grok it fast. */
12389 else
12390 {
12392 hard_frame_pointer_rtx,
12395 }
12396 }
12399 {
12427 }
12429 /* At this point the stack pointer must be valid, and we must have
12430 restored all of the registers. We may not have deallocated the
12431 entire stack frame. We've delayed this until now because it may
12432 be possible to merge the local stack deallocation with the
12433 deallocation forced by ix86_static_chain_on_stack. */
12438 {
12442 }
12443 else
12446 /* Sibcall epilogues don't want a return instruction. */
12448 {
12451 }
12454 {
12457 /* i386 can only pop 64K bytes. If asked to pop more, pop return
12458 address, do explicit add, and jump indirectly to the caller. */
12461 {
12465 /* There is no "pascal" calling convention in any 64bit ABI. */
12481 }
12482 else
12484 }
12485 else
12488 /* Restore the state back to the state from the prologue,
12489 so that it's correct for the next epilogue. */
12491 }
12493 /* Reset from the function's potential modifications. */
12495 static void
12497 {
12501 #if TARGET_MACHO
12502 /* Mach-O doesn't support labels at the end of objects, so if
12503 it looks like we might want one, insert a NOP. */
12504 {
12510 {
12511 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
12512 notes only, instead set their CODE_LABEL_NUMBER to -1,
12513 otherwise there would be code generation differences
12514 in between -g and -g0. */
12518 }
12528 }
12529 #endif
12531 }
12533 /* Return a scratch register to use in the split stack prologue. The
12534 split stack prologue is used for -fsplit-stack. It is the first
12535 instructions in the function, even before the regular prologue.
12536 The scratch register can be any caller-saved register which is not
12537 used for parameters or for the static chain. */
12539 static unsigned int
12541 {
12544 else
12545 {
12558 {
12560 {
12564 }
12566 }
12568 {
12572 }
12574 {
12577 else
12578 {
12580 {
12584 }
12586 }
12587 }
12588 else
12589 {
12590 /* FIXME: We could make this work by pushing a register
12591 around the addition and comparison. */
12594 }
12595 }
12596 }
12598 /* A SYMBOL_REF for the function which allocates new stackspace for
12599 -fsplit-stack. */
12603 /* A SYMBOL_REF for the more stack function when using the large
12604 model. */
12608 /* Handle -fsplit-stack. These are the first instructions in the
12609 function, even before the regular prologue. */
12611 void
12613 {
12615 HOST_WIDE_INT allocate;
12621 rtx fn;
12629 /* This is the label we will branch to if we have enough stack
12630 space. We expect the basic block reordering pass to reverse this
12631 branch if optimizing, so that we branch in the unlikely case. */
12634 /* We need to compare the stack pointer minus the frame size with
12635 the stack boundary in the TCB. The stack boundary always gives
12636 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
12637 can compare directly. Otherwise we need to do an addition. */
12640 UNSPEC_STACK_CHECK);
12645 else
12646 {
12648 rtx offset;
12650 /* We need a scratch register to hold the stack pointer minus
12651 the required frame size. Since this is the very start of the
12652 function, the scratch register can be any caller-saved
12653 register which is not used for parameters. */
12660 {
12661 /* We don't use ix86_gen_add3 in this case because it will
12662 want to split to lea, but when not optimizing the insn
12663 will not be split after this point. */
12666 offset)));
12667 }
12668 else
12669 {
12672 stack_pointer_rtx));
12673 }
12675 }
12681 /* Mark the jump as very likely to be taken. */
12686 {
12689 }
12692 /* Get more stack space. We pass in the desired stack space and the
12693 size of the arguments to copy to the new stack. In 32-bit mode
12694 we push the parameters; __morestack will return on a new stack
12695 anyhow. In 64-bit mode we pass the parameters in r10 and
12696 r11. */
12701 {
12707 /* If this function uses a static chain, it will be in %r10.
12708 Preserve it across the call to __morestack. */
12710 {
12711 rtx rax;
12716 }
12720 {
12721 HOST_WIDE_INT argval;
12724 /* When using the large model we need to load the address
12725 into a register, and we've run out of registers. So we
12726 switch to a different calling convention, and we call a
12727 different function: __morestack_large. We pass the
12728 argument size in the upper 32 bits of r10 and pass the
12729 frame size in the lower 32 bits. */
12734 {
12735 split_stack_fn_large =
12738 }
12740 {
12742 rtx x;
12751 UNSPEC_GOT);
12757 }
12758 else
12765 }
12766 else
12767 {
12771 }
12774 }
12775 else
12776 {
12779 }
12785 /* In order to make call/return prediction work right, we now need
12786 to execute a return instruction. See
12787 libgcc/config/i386/morestack.S for the details on how this works.
12789 For flow purposes gcc must not see this as a return
12790 instruction--we need control flow to continue at the subsequent
12791 label. Therefore, we use an unspec. */
12795 /* If we are in 64-bit mode and this function uses a static chain,
12796 we saved %r10 in %rax before calling _morestack. */
12801 /* If this function calls va_start, we need to store a pointer to
12802 the arguments on the old stack, because they may not have been
12803 all copied to the new stack. At this point the old stack can be
12804 found at the frame pointer value used by __morestack, because
12805 __morestack has set that up before calling back to us. Here we
12806 store that pointer in a scratch register, and in
12807 ix86_expand_prologue we store the scratch register in a stack
12808 slot. */
12810 {
12812 rtx frame_reg;
12819 /* 64-bit:
12820 fp -> old fp value
12821 return address within this function
12822 return address of caller of this function
12823 stack arguments
12824 So we add three words to get to the stack arguments.
12826 32-bit:
12827 fp -> old fp value
12828 return address within this function
12829 first argument to __morestack
12830 second argument to __morestack
12831 return address of caller of this function
12832 stack arguments
12833 So we add five words to get to the stack arguments.
12834 */
12845 }
12850 /* If this function calls va_start, we now have to set the scratch
12851 register for the case where we do not call __morestack. In this
12852 case we need to set it based on the stack pointer. */
12854 {
12861 }
12862 }
12864 /* We may have to tell the dataflow pass that the split stack prologue
12865 is initializing a scratch register. */
12867 static void
12869 {
12871 {
12874 }
12875 }
12876 \f
12877 /* Extract the parts of an RTL expression that is a valid memory address
12878 for an instruction. Return 0 if the structure of the address is
12879 grossly off. Return -1 if the address contains ASHIFT, so it is not
12880 strictly valid, but still used for computing length of lea instruction. */
12882 int
12884 {
12889 rtx tmp;
12893 /* Allow zero-extended SImode addresses,
12894 they will be emitted with addr32 prefix. */
12896 {
12899 {
12903 }
12906 {
12913 }
12914 }
12916 /* Allow SImode subregs of DImode addresses,
12917 they will be emitted with addr32 prefix. */
12919 {
12922 {
12926 }
12927 }
12932 {
12935 else
12937 }
12939 {
12944 do
12945 {
12950 }
12957 {
12960 {
12985 /* FALLTHRU */
12989 && TARGET_TLS_DIRECT_SEG_REFS
12992 else
12999 /* FALLTHRU */
13006 else
13021 }
13022 }
13023 }
13025 {
13028 }
13030 {
13031 /* We're called for lea too, which implements ashift on occasion. */
13041 }
13042 else
13046 {
13048 ;
13051 ;
13052 else
13054 }
13056 /* Extract the integral value of scale. */
13058 {
13062 }
13067 /* Avoid useless 0 displacement. */
13071 /* Allow arg pointer and stack pointer as index if there is not scaling. */
13076 {
13079 }
13081 /* Special case: %ebp cannot be encoded as a base without a displacement.
13082 Similarly %r13. */
13084 && base_reg
13093 /* Special case: on K6, [%esi] makes the instruction vector decoded.
13094 Avoid this by transforming to [%esi+0].
13095 Reload calls address legitimization without cfun defined, so we need
13096 to test cfun for being non-NULL. */
13102 /* Special case: encode reg+reg instead of reg*2. */
13106 /* Special case: scaling cannot be encoded without base or displacement. */
13117 }
13118 \f
13119 /* Return cost of the memory address x.
13120 For i386, it is better to use a complex address than let gcc copy
13121 the address into a reg and make a new pseudo. But not if the address
13122 requires to two regs - that would mean more pseudos with longer
13123 lifetimes. */
13124 static int
13126 {
13138 /* Attempt to minimize number of registers in the address by increasing
13139 address cost for each used register. We don't increase address cost
13140 for "pic_offset_table_rtx". When a memopt with "pic_offset_table_rtx"
13141 is not invariant itself it most likely means that base or index is not
13142 invariant. Therefore only "pic_offset_table_rtx" could be hoisted out,
13143 which is not profitable for x86. */
13147 || !pic_offset_table_rtx
13150 cost++;
13155 || !pic_offset_table_rtx
13158 cost++;
13160 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
13161 since it's predecode logic can't detect the length of instructions
13162 and it degenerates to vector decoded. Increase cost of such
13163 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
13164 to split such addresses or even refuse such addresses at all.
13166 Following addressing modes are affected:
13167 [base+scale*index]
13168 [scale*index+disp]
13169 [base+index]
13171 The first and last case may be avoidable by explicitly coding the zero in
13172 memory address, but I don't have AMD-K6 machine handy to check this
13173 theory. */
13182 }
13183 \f
13184 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
13185 this is used for to form addresses to local data when -fPIC is in
13186 use. */
13188 static bool
13190 {
13193 }
13195 /* Determine if a given RTX is a valid constant. We already know this
13196 satisfies CONSTANT_P. */
13198 static bool
13200 {
13201 /* Pointer bounds constants are not valid. */
13206 {
13211 {
13215 }
13220 /* Only some unspecs are valid as "constants". */
13223 {
13239 }
13241 /* We must have drilled down to a symbol. */
13246 /* FALLTHRU */
13249 /* TLS symbols are never valid. */
13253 /* DLLIMPORT symbols are never valid. */
13258 #if TARGET_MACHO
13259 /* mdynamic-no-pic */
13262 #endif
13276 }
13278 /* Otherwise we handle everything else in the move patterns. */
13280 }
13282 /* Determine if it's legal to put X into the constant pool. This
13283 is not possible for the address of thread-local symbols, which
13284 is checked above. */
13286 static bool
13288 {
13289 /* We can always put integral constants and vectors in memory. */
13291 {
13300 }
13302 }
13304 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
13305 otherwise zero. */
13307 static bool
13309 {
13315 }
13318 /* Nonzero if the constant value X is a legitimate general operand
13319 when generating PIC code. It is given that flag_pic is on and
13320 that X satisfies CONSTANT_P. */
13322 bool
13324 {
13325 rtx inner;
13328 {
13335 /* Only some unspecs are valid as "constants". */
13338 {
13351 }
13352 /* FALLTHRU */
13360 }
13361 }
13363 /* Determine if a given CONST RTX is a valid memory displacement
13364 in PIC mode. */
13366 bool
13368 {
13371 /* In 64bit mode we can allow direct addresses of symbols and labels
13372 when they are not dynamic symbols. */
13374 {
13378 {
13402 /* FALLTHRU */
13405 /* TLS references should always be enclosed in UNSPEC.
13406 The dllimported symbol needs always to be resolved. */
13412 {
13420 /* Function-symbols need to be resolved only for
13421 large-model.
13422 For the small-model we don't need to resolve anything
13423 here. */
13428 /* Non-external symbols don't need to be resolved for
13429 large, and medium-model. */
13434 }
13437 || (HAVE_LD_PIE_COPYRELOC
13438 && flag_pie
13447 }
13448 }
13454 {
13455 /* We are unsafe to allow PLUS expressions. This limit allowed distance
13456 of GOT tables. We should not need these anyway. */
13468 }
13472 {
13477 }
13486 {
13490 /* We need to check for both symbols and labels because VxWorks loads
13491 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
13492 details. */
13496 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
13497 While ABI specify also 32bit relocation but we don't produce it in
13498 small PIC model at all. */
13520 }
13523 }
13525 /* Determine if op is suitable RTX for an address register.
13526 Return naked register if a register or a register subreg is
13527 found, otherwise return NULL_RTX. */
13529 static rtx
13531 {
13534 /* Only SImode or DImode registers can form the address. */
13541 {
13549 /* Don't allow SUBREGs that span more than a word. It can
13550 lead to spill failures when the register is one word out
13551 of a two word structure. */
13555 /* Allow only SUBREGs of non-eliminable hard registers. */
13558 }
13560 /* Op is not a register. */
13562 }
13564 /* Recognizes RTL expressions that are valid memory addresses for an
13565 instruction. The MODE argument is the machine mode for the MEM
13566 expression that wants to use this address.
13568 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
13569 convert common non-canonical forms to canonical form so that they will
13570 be recognized. */
13572 static bool
13574 {
13577 HOST_WIDE_INT scale;
13581 /* Decomposition failed. */
13590 /* Validate base register. */
13592 {
13600 /* Base is not valid. */
13602 }
13604 /* Validate index register. */
13606 {
13614 /* Index is not valid. */
13616 }
13618 /* Index and base should have the same mode. */
13623 /* Address override works only on the (%reg) part of %fs:(%reg). */
13629 /* Validate scale factor. */
13631 {
13633 /* Scale without index. */
13637 /* Scale is not a valid multiplier. */
13639 }
13641 /* Validate displacement. */
13643 {
13648 {
13649 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
13650 used. While ABI specify also 32bit relocations, we don't produce
13651 them at all and use IP relative instead. */
13658 /* 64bit address unspec. */
13678 /* Invalid address unspec. */
13680 }
13683 && (flag_pic
13684 || (TARGET_MACHO
13685 #if TARGET_MACHO
13686 && MACHOPIC_INDIRECT
13688 #endif
13689 )))
13690 {
13692 is_legitimate_pic:
13694 {
13695 /* foo@dtpoff(%rX) is ok. */
13702 /* Non-constant pic memory reference. */
13704 }
13707 /* Displacement is an invalid pic construct. */
13709 #if TARGET_MACHO
13712 /* displacment must be referenced via non_lazy_pointer */
13714 #endif
13716 /* This code used to verify that a symbolic pic displacement
13717 includes the pic_offset_table_rtx register.
13719 While this is good idea, unfortunately these constructs may
13720 be created by "adds using lea" optimization for incorrect
13721 code like:
13723 int a;
13724 int foo(int i)
13725 {
13726 return *(&a+i);
13727 }
13729 This code is nonsensical, but results in addressing
13730 GOT table with pic_offset_table_rtx base. We can't
13731 just refuse it easily, since it gets matched by
13732 "addsi3" pattern, that later gets split to lea in the
13733 case output register differs from input. While this
13734 can be handled by separate addsi pattern for this case
13735 that never results in lea, this seems to be easier and
13736 correct fix for crash to disable this test. */
13737 }
13744 /* Displacement is not constant. */
13748 /* Displacement is out of range. */
13750 /* In x32 mode, constant addresses are sign extended to 64bit, so
13751 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13756 }
13758 /* Everything looks valid. */
13760 }
13762 /* Determine if a given RTX is a valid constant address. */
13764 bool
13766 {
13768 }
13769 \f
13770 /* Return a unique alias set for the GOT. */
13772 static alias_set_type
13774 {
13779 }
13781 /* Return a legitimate reference for ORIG (an address) using the
13782 register REG. If REG is 0, a new pseudo is generated.
13784 There are two types of references that must be handled:
13786 1. Global data references must load the address from the GOT, via
13787 the PIC reg. An insn is emitted to do this load, and the reg is
13788 returned.
13790 2. Static data references, constant pool addresses, and code labels
13791 compute the address as an offset from the GOT, whose base is in
13792 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13793 differentiate them from global data objects. The returned
13794 address is the PIC reg + an unspec constant.
13796 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13797 reg also appears in the address. */
13799 static rtx
13801 {
13805 #if TARGET_MACHO
13807 {
13810 /* Use the generic Mach-O PIC machinery. */
13812 }
13813 #endif
13816 {
13820 }
13826 {
13827 rtx tmpreg;
13828 /* This symbol may be referenced via a displacement from the PIC
13829 base address (@GOTOFF). */
13834 {
13836 UNSPEC_GOTOFF);
13838 }
13839 else
13844 else
13849 {
13853 }
13854 else
13856 }
13858 {
13859 /* This symbol may be referenced via a displacement from the PIC
13860 base address (@GOTOFF). */
13865 {
13867 UNSPEC_GOTOFF);
13869 }
13870 else
13876 {
13879 }
13880 }
13882 /* We can't use @GOTOFF for text labels on VxWorks;
13883 see gotoff_operand. */
13885 {
13890 /* For x64 PE-COFF there is no GOT table. So we use address
13891 directly. */
13893 {
13901 }
13903 {
13911 /* Use directly gen_movsi, otherwise the address is loaded
13912 into register for CSE. We don't want to CSE this addresses,
13913 instead we CSE addresses from the GOT table, so skip this. */
13916 }
13917 else
13918 {
13919 /* This symbol must be referenced via a load from the
13920 Global Offset Table (@GOT). */
13934 }
13935 }
13936 else
13937 {
13940 {
13942 {
13945 }
13946 else
13948 }
13950 {
13953 /* We must match stuff we generate before. Assume the only
13954 unspecs that can get here are ours. Not that we could do
13955 anything with them anyway.... */
13961 }
13963 {
13966 /* Check first to see if this is a constant offset from a @GOTOFF
13967 symbol reference. */
13970 {
13972 {
13974 UNSPEC_GOTOFF);
13980 {
13983 }
13984 }
13985 else
13986 {
13989 {
13993 }
13994 }
13995 }
13996 else
13997 {
14000 new_rtx
14004 {
14007 {
14010 new_rtx
14012 }
14013 else
14015 }
14016 else
14017 {
14018 /* For %rip addressing, we have to use just disp32, not
14019 base nor index. */
14026 {
14029 }
14031 }
14032 }
14033 }
14034 }
14036 }
14037 \f
14038 /* Load the thread pointer. If TO_REG is true, force it into a register. */
14040 static rtx
14042 {
14046 {
14051 }
14057 }
14059 /* Construct the SYMBOL_REF for the tls_get_addr function. */
14063 static rtx
14065 {
14067 {
14073 }
14076 {
14078 UNSPEC_PLTOFF);
14081 }
14084 }
14086 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
14090 rtx
14092 {
14094 {
14095 ix86_tls_module_base_symbol
14100 }
14103 }
14105 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
14106 false if we expect this to be used for a memory address and true if
14107 we expect to load the address into a register. */
14109 static rtx
14111 {
14117 /* Fall back to global dynamic model if tool chain cannot support local
14118 dynamic. */
14125 {
14130 {
14133 else
14134 {
14137 }
14138 }
14141 {
14144 else
14154 }
14155 else
14156 {
14160 {
14165 emit_call_insn
14175 }
14176 else
14178 }
14185 {
14188 else
14189 {
14192 }
14193 }
14196 {
14201 else
14207 }
14208 else
14209 {
14213 {
14216 rtx eqv;
14219 emit_call_insn
14224 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
14225 share the LD_BASE result with other LD model accesses. */
14227 UNSPEC_TLS_LD_BASE);
14231 }
14232 else
14234 }
14242 {
14249 }
14254 {
14256 {
14257 /* The Sun linker took the AMD64 TLS spec literally
14258 and can only handle %rax as destination of the
14259 initial executable code sequence. */
14264 }
14266 /* Generate DImode references to avoid %fs:(%reg32)
14267 problems and linker IE->LE relaxation bug. */
14271 }
14273 {
14276 }
14278 {
14282 }
14283 else
14284 {
14287 }
14297 {
14302 }
14303 else
14304 {
14308 }
14318 {
14322 }
14323 else
14324 {
14328 }
14333 }
14336 }
14338 /* Create or return the unique __imp_DECL dllimport symbol corresponding
14339 to symbol DECL if BEIMPORT is true. Otherwise create or return the
14340 unique refptr-DECL symbol corresponding to symbol DECL. */
14343 {
14347 {
14349 }
14351 static int
14353 {
14355 }
14356 };
14360 static tree
14362 {
14368 tree to;
14369 rtx rtl;
14396 else
14409 {
14411 #ifdef SUB_TARGET_RECORD_STUB
14413 #endif
14414 }
14423 }
14425 /* Expand SYMBOL into its corresponding far-addresse symbol.
14426 WANT_REG is true if we require the result be a register. */
14428 static rtx
14430 {
14431 tree imp_decl;
14432 rtx x;
14441 }
14443 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
14444 true if we require the result be a register. */
14446 static rtx
14448 {
14449 tree imp_decl;
14450 rtx x;
14459 }
14461 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
14462 is true if we require the result be a register. */
14464 static rtx
14466 {
14471 {
14478 {
14481 }
14482 }
14498 {
14501 }
14503 }
14505 /* Try machine-dependent ways of modifying an illegitimate address
14506 to be legitimate. If we find one, return the new, valid address.
14507 This macro is used in only one place: `memory_address' in explow.c.
14509 OLDX is the address as it was before break_out_memory_refs was called.
14510 In some cases it is useful to look at this to decide what needs to be done.
14512 It is always safe for this macro to do nothing. It exists to recognize
14513 opportunities to optimize the output.
14515 For the 80386, we handle X+REG by loading X into a register R and
14516 using R+REG. R will go in a general reg and indexing will be used.
14517 However, if REG is a broken-out memory address or multiplication,
14518 nothing needs to be done because REG can certainly go in a general reg.
14520 When -fpic is used, special handling is needed for symbolic references.
14521 See comments by legitimize_pic_address in i386.c for details. */
14523 static rtx
14525 {
14536 {
14540 }
14543 {
14547 }
14552 #if TARGET_MACHO
14555 #endif
14557 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
14561 {
14566 }
14569 {
14570 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
14575 {
14581 }
14586 {
14592 }
14594 /* Put multiply first if it isn't already. */
14596 {
14599 }
14601 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
14602 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
14603 created by virtual register instantiation, register elimination, and
14604 similar optimizations. */
14606 {
14612 }
14614 /* Canonicalize
14615 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
14616 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
14621 {
14622 rtx constant;
14626 {
14629 }
14631 {
14634 }
14635 else
14639 {
14646 }
14647 }
14653 {
14656 }
14659 {
14662 }
14670 {
14673 }
14679 {
14683 {
14686 }
14690 }
14693 {
14697 {
14700 }
14704 }
14705 }
14708 }
14709 \f
14710 /* Print an integer constant expression in assembler syntax. Addition
14711 and subtraction are the only arithmetic that may appear in these
14712 expressions. FILE is the stdio stream to write to, X is the rtx, and
14713 CODE is the operand print code from the output string. */
14715 static void
14717 {
14721 {
14730 else
14731 {
14734 /* Mark the decl as referenced so that cgraph will
14735 output the function. */
14739 #if TARGET_MACHO
14743 #endif
14745 }
14753 /* FALLTHRU */
14764 /* This used to output parentheses around the expression,
14765 but that does not work on the 386 (either ATT or BSD assembler). */
14770 /* We can't handle floating point constants;
14771 TARGET_PRINT_OPERAND must handle them. */
14776 /* Some assemblers need integer constants to appear first. */
14778 {
14782 }
14783 else
14784 {
14789 }
14804 {
14808 }
14813 {
14832 /* FIXME: This might be @TPOFF in Sun ld too. */
14841 else
14851 else
14857 #if TARGET_MACHO
14862 #endif
14866 }
14871 }
14872 }
14874 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14875 We need to emit DTP-relative relocations. */
14877 static void ATTRIBUTE_UNUSED
14879 {
14884 {
14892 }
14893 }
14895 /* Return true if X is a representation of the PIC register. This copes
14896 with calls from ix86_find_base_term, where the register might have
14897 been replaced by a cselib value. */
14899 static bool
14901 {
14908 {
14916 }
14917 else
14919 }
14921 /* Helper function for ix86_delegitimize_address.
14922 Attempt to delegitimize TLS local-exec accesses. */
14924 static rtx
14926 {
14951 {
14956 }
14962 }
14964 /* In the name of slightly smaller debug output, and to cater to
14965 general assembler lossage, recognize PIC+GOTOFF and turn it back
14966 into a direct symbol reference.
14968 On Darwin, this is necessary to avoid a crash, because Darwin
14969 has a different PIC label for each routine but the DWARF debugging
14970 information is not associated with any particular routine, so it's
14971 necessary to remove references to the PIC label from RTL stored by
14972 the DWARF output code. */
14974 static rtx
14976 {
14978 /* addend is NULL or some rtx if x is something+GOTOFF where
14979 something doesn't include the PIC register. */
14981 /* reg_addend is NULL or a multiple of some register. */
14983 /* const_addend is NULL or a const_int. */
14985 /* This is the result, or NULL. */
14994 {
15001 {
15007 }
15014 {
15017 {
15022 }
15024 }
15029 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
15030 and -mcmodel=medium -fpic. */
15031 }
15038 /* %ebx + GOT/GOTOFF */
15039 ;
15041 {
15042 /* %ebx + %reg * scale + GOT/GOTOFF */
15048 else
15049 {
15052 }
15053 }
15054 else
15060 {
15063 }
15084 {
15085 /* If the rest of original X doesn't involve the PIC register, add
15086 addend and subtract pic_offset_table_rtx. This can happen e.g.
15087 for code like:
15088 leal (%ebx, %ecx, 4), %ecx
15089 ...
15090 movl foo@GOTOFF(%ecx), %edx
15091 in which case we return (%ecx - %ebx) + foo
15092 or (%ecx - _GLOBAL_OFFSET_TABLE_) + foo if pseudo_pic_reg
15093 and reload has completed. */
15097 pic_offset_table_rtx),
15098 result);
15100 {
15104 }
15105 else
15107 }
15109 {
15113 }
15115 }
15117 /* If X is a machine specific address (i.e. a symbol or label being
15118 referenced as a displacement from the GOT implemented using an
15119 UNSPEC), then return the base term. Otherwise return X. */
15121 rtx
15123 {
15124 rtx term;
15127 {
15140 }
15143 }
15144 \f
15145 static void
15148 {
15152 {
15155 }
15160 {
15163 {
15182 }
15186 {
15205 }
15212 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
15213 Those same assemblers have the same but opposite lossage on cmov. */
15216 else
15221 {
15234 }
15241 else
15246 {
15259 }
15266 else
15276 else
15287 }
15289 }
15291 /* Print the name of register X to FILE based on its machine mode and number.
15292 If CODE is 'w', pretend the mode is HImode.
15293 If CODE is 'b', pretend the mode is QImode.
15294 If CODE is 'k', pretend the mode is SImode.
15295 If CODE is 'q', pretend the mode is DImode.
15296 If CODE is 'x', pretend the mode is V4SFmode.
15297 If CODE is 't', pretend the mode is V8SFmode.
15298 If CODE is 'g', pretend the mode is V16SFmode.
15299 If CODE is 'h', pretend the reg is the 'high' byte register.
15300 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
15301 If CODE is 'd', duplicate the operand for AVX instruction.
15302 */
15304 void
15306 {
15316 {
15320 }
15323 {
15326 }
15344 else
15358 {
15366 normal:
15382 {
15387 }
15391 }
15395 /* Irritatingly, AMD extended registers use
15396 different naming convention: "r%d[bwd]" */
15398 {
15401 {
15415 /* no suffix */
15420 }
15422 }
15425 {
15428 else
15430 }
15431 }
15433 /* Meaning of CODE:
15434 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
15435 C -- print opcode suffix for set/cmov insn.
15436 c -- like C, but print reversed condition
15437 F,f -- likewise, but for floating-point.
15438 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
15439 otherwise nothing
15440 R -- print embeded rounding and sae.
15441 r -- print only sae.
15442 z -- print the opcode suffix for the size of the current operand.
15443 Z -- likewise, with special suffixes for x87 instructions.
15444 * -- print a star (in certain assembler syntax)
15445 A -- print an absolute memory reference.
15446 E -- print address with DImode register names if TARGET_64BIT.
15447 w -- print the operand as if it's a "word" (HImode) even if it isn't.
15448 s -- print a shift double count, followed by the assemblers argument
15449 delimiter.
15450 b -- print the QImode name of the register for the indicated operand.
15451 %b0 would print %al if operands[0] is reg 0.
15452 w -- likewise, print the HImode name of the register.
15453 k -- likewise, print the SImode name of the register.
15454 q -- likewise, print the DImode name of the register.
15455 x -- likewise, print the V4SFmode name of the register.
15456 t -- likewise, print the V8SFmode name of the register.
15457 g -- likewise, print the V16SFmode name of the register.
15458 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
15459 y -- print "st(0)" instead of "st" as a register.
15460 d -- print duplicated register operand for AVX instruction.
15461 D -- print condition for SSE cmp instruction.
15462 P -- if PIC, print an @PLT suffix.
15463 p -- print raw symbol name.
15464 X -- don't print any sort of PIC '@' suffix for a symbol.
15465 & -- print some in-use local-dynamic symbol name.
15466 H -- print a memory address offset by 8; used for sse high-parts
15467 Y -- print condition for XOP pcom* instruction.
15468 + -- print a branch hint as 'cs' or 'ds' prefix
15469 ; -- print a semicolon (after prefixes due to bug in older gas).
15470 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
15471 @ -- print a segment register of thread base pointer load
15472 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
15473 ! -- print MPX prefix for jxx/call/ret instructions if required.
15474 */
15476 void
15478 {
15480 {
15482 {
15485 {
15491 /* Intel syntax. For absolute addresses, registers should not
15492 be surrounded by braces. */
15494 {
15499 }
15504 }
15510 /* Wrap address in an UNSPEC to declare special handling. */
15548 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15553 {
15567 output_operand_lossage
15570 }
15573 #endif
15578 {
15579 /* Opcodes don't get size suffixes if using Intel opcodes. */
15584 {
15602 output_operand_lossage
15605 }
15606 }
15609 warning
15611 /* FALLTHRU */
15614 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
15619 {
15621 {
15623 #ifdef HAVE_AS_IX86_FILDS
15625 #endif
15633 #ifdef HAVE_AS_IX86_FILDQ
15635 #else
15637 #endif
15642 }
15643 }
15645 {
15646 /* 387 opcodes don't get size suffixes
15647 if the operands are registers. */
15652 {
15668 }
15669 }
15670 else
15671 {
15672 output_operand_lossage
15675 }
15677 output_operand_lossage
15698 {
15701 }
15706 {
15757 }
15761 /* Little bit of braindamage here. The SSE compare instructions
15762 does use completely different names for the comparisons that the
15763 fp conditional moves. */
15765 {
15768 {
15771 }
15777 {
15780 }
15786 {
15789 }
15798 {
15801 }
15807 {
15810 }
15816 {
15819 }
15830 }
15835 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15838 #endif
15843 {
15847 }
15851 file);
15856 {
15860 }
15861 /* It doesn't actually matter what mode we use here, as we're
15862 only going to use this for printing. */
15864 /* Output 'qword ptr' for intel assembler dialect. */
15873 #ifdef HAVE_AS_IX86_HLE
15875 #else
15877 #endif
15879 #ifdef HAVE_AS_IX86_HLE
15881 #else
15883 #endif
15884 /* We do not want to print value of the operand. */
15913 {
15928 }
15941 {
15946 else
15949 }
15952 {
15953 rtx x;
15962 {
15967 {
15969 bool cputaken
15972 /* Emit hints only in the case default branch prediction
15973 heuristics would fail. */
15975 {
15976 /* We use 3e (DS) prefix for taken branches and
15977 2e (CS) prefix for not taken branches. */
15980 else
15982 }
15983 }
15984 }
15986 }
15989 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15991 #endif
15998 /* The kernel uses a different segment register for performance
15999 reasons; a system call would not have to trash the userspace
16000 segment register, which would be expensive. */
16003 else
16023 }
16024 }
16030 {
16031 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
16034 {
16037 {
16046 else
16053 }
16055 /* Check for explicit size override (codes 'b', 'w', 'k',
16056 'q' and 'x') */
16070 }
16073 /* Avoid (%rip) for call operands. */
16079 else
16081 }
16084 {
16085 REAL_VALUE_TYPE r;
16093 /* Sign extend 32bit SFmode immediate to 8 bytes. */
16097 else
16099 }
16102 {
16103 REAL_VALUE_TYPE r;
16112 }
16114 /* These float cases don't actually occur as immediate operands. */
16116 {
16121 }
16123 else
16124 {
16125 /* We have patterns that allow zero sets of memory, for instance.
16126 In 64-bit mode, we should probably support all 8-byte vectors,
16127 since we can in fact encode that into an immediate. */
16129 {
16132 }
16135 {
16137 {
16140 }
16143 {
16146 else
16148 }
16149 }
16154 else
16156 }
16157 }
16159 static bool
16161 {
16164 }
16165 \f
16166 /* Print a memory operand whose address is ADDR. */
16168 static void
16170 {
16179 {
16186 }
16188 {
16192 }
16194 {
16198 {
16201 }
16204 }
16206 {
16211 }
16212 else
16223 {
16234 }
16236 /* Use one byte shorter RIP relative addressing for 64bit mode. */
16238 {
16250 }
16252 {
16253 /* Displacement only requires special attention. */
16256 {
16260 }
16263 else
16265 }
16266 else
16267 {
16268 /* Print SImode register names to force addr32 prefix. */
16270 {
16271 #ifdef ENABLE_CHECKING
16274 {
16285 }
16286 #endif
16289 }
16291 && TARGET_X32
16292 && disp
16295 {
16296 /* X32 runs in 64-bit mode, where displacement, DISP, in
16297 address DISP(%r64), is encoded as 32-bit immediate sign-
16298 extended from 32-bit to 64-bit. For -0x40000300(%r64),
16299 address is %r64 + 0xffffffffbffffd00. When %r64 <
16300 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
16301 which is invalid for x32. The correct address is %r64
16302 - 0x40000300 == 0xf7ffdd64. To properly encode
16303 -0x40000300(%r64) for x32, we zero-extend negative
16304 displacement by forcing addr32 prefix which truncates
16305 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
16306 zero-extend all negative displacements, including -1(%rsp).
16307 However, for small negative displacements, sign-extension
16308 won't cause overflow. We only zero-extend negative
16309 displacements if they < -16*1024*1024, which is also used
16310 to check legitimate address displacements for PIC. */
16312 }
16315 {
16317 {
16322 else
16324 }
16330 {
16335 }
16337 }
16338 else
16339 {
16343 {
16344 /* Pull out the offset of a symbol; print any symbol itself. */
16348 {
16352 }
16360 else
16362 }
16366 {
16369 {
16373 }
16374 }
16377 else
16381 {
16386 }
16388 }
16389 }
16390 }
16392 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
16394 static bool
16396 {
16397 rtx op;
16404 {
16407 /* FIXME: This might be @TPOFF in Sun ld. */
16418 else
16430 else
16437 #if TARGET_MACHO
16443 #endif
16446 {
16451 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
16453 #else
16455 #endif
16458 }
16463 }
16466 }
16467 \f
16468 /* Split one or more double-mode RTL references into pairs of half-mode
16469 references. The RTL can be REG, offsettable MEM, integer constant, or
16470 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
16471 split and "num" is its length. lo_half and hi_half are output arrays
16472 that parallel "operands". */
16474 void
16477 {
16478 machine_mode half_mode;
16482 {
16491 }
16496 {
16499 /* simplify_subreg refuse to split volatile memory addresses,
16500 but we still have to handle it. */
16502 {
16505 }
16506 else
16507 {
16514 }
16515 }
16516 }
16517 \f
16518 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
16519 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
16520 is the expression of the binary operation. The output may either be
16521 emitted here, or returned to the caller, like all output_* functions.
16523 There is no guarantee that the operands are the same mode, as they
16524 might be within FLOAT or FLOAT_EXTEND expressions. */
16526 #ifndef SYSV386_COMPAT
16527 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
16528 wants to fix the assemblers because that causes incompatibility
16529 with gcc. No-one wants to fix gcc because that causes
16530 incompatibility with assemblers... You can use the option of
16531 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
16532 #define SYSV386_COMPAT 1
16533 #endif
16537 {
16543 #ifdef ENABLE_CHECKING
16544 /* Even if we do not want to check the inputs, this documents input
16545 constraints. Which helps in understanding the following code. */
16555 else
16557 #endif
16560 {
16565 else
16574 else
16583 else
16592 else
16599 }
16602 {
16604 {
16608 else
16610 }
16611 else
16612 {
16616 else
16618 }
16620 }
16624 {
16630 /* know operands[0] == operands[1]. */
16633 {
16636 }
16639 {
16641 /* How is it that we are storing to a dead operand[2]?
16642 Well, presumably operands[1] is dead too. We can't
16643 store the result to st(0) as st(0) gets popped on this
16644 instruction. Instead store to operands[2] (which I
16645 think has to be st(1)). st(1) will be popped later.
16646 gcc <= 2.8.1 didn't have this check and generated
16647 assembly code that the Unixware assembler rejected. */
16649 else
16652 }
16656 else
16663 {
16666 }
16669 {
16672 }
16675 {
16676 #if SYSV386_COMPAT
16677 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
16678 derived assemblers, confusingly reverse the direction of
16679 the operation for fsub{r} and fdiv{r} when the
16680 destination register is not st(0). The Intel assembler
16681 doesn't have this brain damage. Read !SYSV386_COMPAT to
16682 figure out what the hardware really does. */
16685 else
16687 #else
16689 /* As above for fmul/fadd, we can't store to st(0). */
16691 else
16693 #endif
16695 }
16698 {
16699 #if SYSV386_COMPAT
16702 else
16704 #else
16707 else
16709 #endif
16711 }
16714 {
16717 else
16720 }
16722 {
16723 #if SYSV386_COMPAT
16725 #else
16727 #endif
16728 }
16729 else
16730 {
16731 #if SYSV386_COMPAT
16733 #else
16735 #endif
16736 }
16741 }
16745 }
16747 /* Check if a 256bit AVX register is referenced inside of EXP. */
16749 static bool
16751 {
16757 }
16759 /* Return needed mode for entity in optimize_mode_switching pass. */
16761 static int
16763 {
16765 {
16766 rtx link;
16768 /* Needed mode is set to AVX_U128_CLEAN if there are
16769 no 256bit modes used in function arguments. */
16771 link;
16773 {
16775 {
16780 }
16781 }
16784 }
16786 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16787 changes state only when a 256bit register is written to, but we need
16788 to prevent the compiler from moving optimal insertion point above
16789 eventual read from 256bit register. */
16796 }
16798 /* Return mode that i387 must be switched into
16799 prior to the execution of insn. */
16801 static int
16803 {
16806 /* The mode UNINITIALIZED is used to store control word after a
16807 function call or ASM pattern. The mode ANY specify that function
16808 has no requirements on the control word and make no changes in the
16809 bits we are interested in. */
16823 {
16846 }
16849 }
16851 /* Return mode that entity must be switched into
16852 prior to the execution of insn. */
16854 static int
16856 {
16858 {
16868 }
16870 }
16872 /* Check if a 256bit AVX register is referenced in stores. */
16874 static void
16876 {
16878 {
16881 }
16882 }
16884 /* Calculate mode of upper 128bit AVX registers after the insn. */
16886 static int
16888 {
16895 /* We know that state is clean after CALL insn if there are no
16896 256bit registers used in the function return register. */
16898 {
16903 }
16905 /* Otherwise, return current mode. Remember that if insn
16906 references AVX 256bit registers, the mode was already changed
16907 to DIRTY from MODE_NEEDED. */
16909 }
16911 /* Return the mode that an insn results in. */
16913 static int
16915 {
16917 {
16927 }
16928 }
16930 static int
16932 {
16933 tree arg;
16935 /* Entry mode is set to AVX_U128_DIRTY if there are
16936 256bit modes used in function arguments. */
16939 {
16944 }
16947 }
16949 /* Return a mode that ENTITY is assumed to be
16950 switched to at function entry. */
16952 static int
16954 {
16956 {
16966 }
16967 }
16969 static int
16971 {
16974 /* Exit mode is set to AVX_U128_DIRTY if there are
16975 256bit modes used in the function return register. */
16980 }
16982 /* Return a mode that ENTITY is assumed to be
16983 switched to at function exit. */
16985 static int
16987 {
16989 {
16999 }
17000 }
17002 static int
17004 {
17006 }
17008 /* Output code to initialize control word copies used by trunc?f?i and
17009 rounding patterns. CURRENT_MODE is set to current control word,
17010 while NEW_MODE is set to new control word. */
17012 static void
17014 {
17016 rtx new_mode;
17027 {
17029 {
17031 /* round toward zero (truncate) */
17037 /* round down toward -oo */
17044 /* round up toward +oo */
17051 /* mask precision exception for nearbyint() */
17058 }
17059 }
17060 else
17061 {
17063 {
17065 /* round toward zero (truncate) */
17071 /* round down toward -oo */
17077 /* round up toward +oo */
17083 /* mask precision exception for nearbyint() */
17090 }
17091 }
17097 }
17099 /* Emit vzeroupper. */
17101 void
17103 {
17106 /* Cancel automatic vzeroupper insertion if there are
17107 live call-saved SSE registers at the insertion point. */
17119 }
17121 /* Generate one or more insns to set ENTITY to MODE. */
17123 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
17124 is the set of hard registers live at the point where the insn(s)
17125 are to be inserted. */
17127 static void
17129 HARD_REG_SET regs_live)
17130 {
17132 {
17147 }
17148 }
17150 /* Output code for INSN to convert a float to a signed int. OPERANDS
17151 are the insn operands. The output may be [HSD]Imode and the input
17152 operand may be [SDX]Fmode. */
17156 {
17161 /* Jump through a hoop or two for DImode, since the hardware has no
17162 non-popping instruction. We used to do this a different way, but
17163 that was somewhat fragile and broke with post-reload splitters. */
17173 else
17174 {
17179 else
17183 }
17186 }
17188 /* Output code for x87 ffreep insn. The OPNO argument, which may only
17189 have the values zero or one, indicates the ffreep insn's operand
17190 from the OPERANDS array. */
17194 {
17196 #ifdef HAVE_AS_IX86_FFREEP
17198 #else
17199 {
17209 }
17210 #endif
17213 }
17216 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
17217 should be used. UNORDERED_P is true when fucom should be used. */
17221 {
17227 {
17230 }
17231 else
17232 {
17235 }
17238 {
17242 else
17244 else
17247 else
17249 }
17256 {
17258 {
17261 }
17262 else
17264 }
17267 && stack_top_dies
17270 {
17271 /* If both the top of the 387 stack dies, and the other operand
17272 is also a stack register that dies, then this must be a
17273 `fcompp' float compare */
17276 {
17277 /* There is no double popping fcomi variant. Fortunately,
17278 eflags is immune from the fstp's cc clobbering. */
17281 else
17284 }
17285 else
17286 {
17289 else
17291 }
17292 }
17293 else
17294 {
17295 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
17298 {
17306 NULL,
17307 NULL,
17314 NULL,
17315 NULL,
17316 NULL,
17317 NULL
17318 };
17333 }
17334 }
17336 void
17338 {
17341 #ifdef ASM_QUAD
17344 #else
17346 #endif
17349 }
17351 void
17353 {
17356 #ifdef ASM_QUAD
17359 #else
17361 #endif
17362 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
17368 #if TARGET_MACHO
17370 {
17374 }
17375 #endif
17376 else
17379 }
17380 \f
17381 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
17382 for the target. */
17384 void
17386 {
17387 rtx tmp;
17389 /* We play register width games, which are only valid after reload. */
17392 /* Avoid HImode and its attendant prefix byte. */
17398 {
17401 }
17404 }
17406 /* X is an unchanging MEM. If it is a constant pool reference, return
17407 the constant pool rtx, else NULL. */
17409 rtx
17411 {
17418 }
17420 void
17422 {
17430 {
17431 rtx tmp;
17435 {
17441 }
17444 }
17448 {
17451 rtx tmp;
17456 else
17460 {
17467 }
17468 }
17472 {
17474 {
17475 #if TARGET_MACHO
17476 /* dynamic-no-pic */
17478 {
17485 }
17487 {
17491 }
17494 else
17495 {
17503 }
17504 /* dynamic-no-pic */
17505 #endif
17506 }
17507 else
17508 {
17512 {
17518 }
17519 }
17520 }
17521 else
17522 {
17533 /* Force large constants in 64bit compilation into register
17534 to get them CSEed. */
17545 {
17546 /* If we are loading a floating point constant to a register,
17547 force the value to memory now, since we'll get better code
17548 out the back end. */
17552 {
17557 }
17558 }
17559 }
17562 }
17564 void
17566 {
17573 /* Force constants other than zero into memory. We do not know how
17574 the instructions used to build constants modify the upper 64 bits
17575 of the register, once we have that information we may be able
17576 to handle some of them more efficiently. */
17585 /* We need to check memory alignment for SSE mode since attribute
17586 can make operands unaligned. */
17591 {
17594 /* ix86_expand_vector_move_misalign() does not like constants ... */
17600 /* ... nor both arguments in memory. */
17608 }
17610 /* Make operand1 a register if it isn't already. */
17614 {
17617 }
17620 }
17622 /* Split 32-byte AVX unaligned load and store if needed. */
17624 static void
17626 {
17627 rtx m;
17631 machine_mode mode;
17634 {
17655 }
17658 {
17661 {
17668 }
17669 /* Normal *mov<mode>_internal pattern will handle
17670 unaligned loads just fine if misaligned_operand
17671 is true, and without the UNSPEC it can be combined
17672 with arithmetic instructions. */
17675 else
17677 }
17679 {
17682 {
17687 }
17688 else
17690 }
17691 else
17693 }
17695 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17696 straight to ix86_expand_vector_move. */
17697 /* Code generation for scalar reg-reg moves of single and double precision data:
17698 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17699 movaps reg, reg
17700 else
17701 movss reg, reg
17702 if (x86_sse_partial_reg_dependency == true)
17703 movapd reg, reg
17704 else
17705 movsd reg, reg
17707 Code generation for scalar loads of double precision data:
17708 if (x86_sse_split_regs == true)
17709 movlpd mem, reg (gas syntax)
17710 else
17711 movsd mem, reg
17713 Code generation for unaligned packed loads of single precision data
17714 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17715 if (x86_sse_unaligned_move_optimal)
17716 movups mem, reg
17718 if (x86_sse_partial_reg_dependency == true)
17719 {
17720 xorps reg, reg
17721 movlps mem, reg
17722 movhps mem+8, reg
17723 }
17724 else
17725 {
17726 movlps mem, reg
17727 movhps mem+8, reg
17728 }
17730 Code generation for unaligned packed loads of double precision data
17731 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17732 if (x86_sse_unaligned_move_optimal)
17733 movupd mem, reg
17735 if (x86_sse_split_regs == true)
17736 {
17737 movlpd mem, reg
17738 movhpd mem+8, reg
17739 }
17740 else
17741 {
17742 movsd mem, reg
17743 movhpd mem+8, reg
17744 }
17745 */
17747 void
17749 {
17758 {
17760 {
17764 {
17766 {
17769 }
17770 else
17772 }
17774 /* FALLTHRU */
17778 {
17793 }
17799 else
17807 }
17810 }
17814 {
17816 {
17820 {
17822 {
17825 }
17826 else
17828 }
17830 /* FALLTHRU */
17840 }
17843 }
17846 {
17847 /* Normal *mov<mode>_internal pattern will handle
17848 unaligned loads just fine if misaligned_operand
17849 is true, and without the UNSPEC it can be combined
17850 with arithmetic instructions. */
17856 /* ??? If we have typed data, then it would appear that using
17857 movdqu is the only way to get unaligned data loaded with
17858 integer type. */
17860 {
17862 {
17865 }
17867 /* We will eventually emit movups based on insn attributes. */
17871 }
17873 {
17874 rtx zero;
17877 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17878 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17880 {
17881 /* We will eventually emit movups based on insn attributes. */
17884 }
17886 /* When SSE registers are split into halves, we can avoid
17887 writing to the top half twice. */
17889 {
17892 }
17893 else
17894 {
17895 /* ??? Not sure about the best option for the Intel chips.
17896 The following would seem to satisfy; the register is
17897 entirely cleared, breaking the dependency chain. We
17898 then store to the upper half, with a dependency depth
17899 of one. A rumor has it that Intel recommends two movsd
17900 followed by an unpacklpd, but this is unconfirmed. And
17901 given that the dependency depth of the unpacklpd would
17902 still be one, I'm not sure why this would be better. */
17904 }
17910 }
17911 else
17912 {
17913 rtx t;
17916 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17917 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17919 {
17921 {
17924 }
17931 }
17935 else
17940 else
17949 }
17950 }
17952 {
17954 {
17957 /* We will eventually emit movups based on insn attributes. */
17959 }
17961 {
17963 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17964 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17966 /* We will eventually emit movups based on insn attributes. */
17968 else
17969 {
17974 }
17975 }
17976 else
17977 {
17982 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17983 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17985 {
17988 }
17989 else
17990 {
17995 }
17996 }
17997 }
17998 else
18000 }
18002 /* Helper function of ix86_fixup_binary_operands to canonicalize
18003 operand order. Returns true if the operands should be swapped. */
18005 static bool
18007 rtx operands[])
18008 {
18013 /* If the operation is not commutative, we can't do anything. */
18017 /* Highest priority is that src1 should match dst. */
18023 /* Next highest priority is that immediate constants come second. */
18029 /* Lowest priority is that memory references should come second. */
18036 }
18039 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
18040 destination to use for the operation. If different from the true
18041 destination in operands[0], a copy operation will be required. */
18043 rtx
18045 rtx operands[])
18046 {
18051 /* Canonicalize operand order. */
18053 {
18054 /* It is invalid to swap operands of different modes. */
18058 }
18060 /* Both source operands cannot be in memory. */
18062 {
18063 /* Optimization: Only read from memory once. */
18065 {
18068 }
18071 else
18073 }
18075 /* If the destination is memory, and we do not have matching source
18076 operands, do things in registers. */
18080 /* Source 1 cannot be a constant. */
18084 /* Source 1 cannot be a non-matching memory. */
18088 /* Improve address combine. */
18097 }
18099 /* Similarly, but assume that the destination has already been
18100 set up properly. */
18102 void
18105 {
18108 }
18110 /* Attempt to expand a binary operator. Make the expansion closer to the
18111 actual machine, then just general_operand, which will allow 3 separate
18112 memory references (one output, two input) in a single insn. */
18114 void
18116 rtx operands[])
18117 {
18124 /* Emit the instruction. */
18131 {
18132 /* This is going to be an LEA; avoid splitting it later. */
18134 }
18135 else
18136 {
18139 }
18141 /* Fix up the destination if needed. */
18144 }
18146 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
18147 the given OPERANDS. */
18149 void
18151 rtx operands[])
18152 {
18155 {
18158 }
18160 {
18163 }
18164 /* Optimize (__m128i) d | (__m128i) e and similar code
18165 when d and e are float vectors into float vector logical
18166 insn. In C/C++ without using intrinsics there is no other way
18167 to express vector logical operation on float vectors than
18168 to cast them temporarily to integer vectors. */
18170 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
18179 {
18180 rtx dst;
18182 {
18191 {
18194 }
18195 else
18196 {
18201 }
18212 }
18213 }
18222 }
18224 /* Return TRUE or FALSE depending on whether the binary operator meets the
18225 appropriate constraints. */
18227 bool
18230 {
18235 /* Both source operands cannot be in memory. */
18239 /* Canonicalize operand order for commutative operators. */
18243 /* If the destination is memory, we must have a matching source operand. */
18247 /* Source 1 cannot be a constant. */
18251 /* Source 1 cannot be a non-matching memory. */
18253 /* Support "andhi/andsi/anddi" as a zero-extending move. */
18261 }
18263 /* Attempt to expand a unary operator. Make the expansion closer to the
18264 actual machine, then just general_operand, which will allow 2 separate
18265 memory references (one output, one input) in a single insn. */
18267 void
18269 rtx operands[])
18270 {
18277 /* If the destination is memory, and we do not have matching source
18278 operands, do things in registers. */
18280 {
18283 else
18285 }
18287 /* When source operand is memory, destination must match. */
18291 /* Emit the instruction. */
18297 else
18298 {
18301 }
18303 /* Fix up the destination if needed. */
18306 }
18308 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
18309 divisor are within the range [0-255]. */
18311 void
18314 {
18323 {
18336 }
18343 /* Use 8bit unsigned divimod if dividend and divisor are within
18344 the range [0-255]. */
18353 pc_rtx);
18358 /* Generate original signed/unsigned divimod. */
18363 /* Branch to the end. */
18367 /* Generate 8bit unsigned divide. */
18369 /* Don't use operands[0] for result of 8bit divide since not all
18370 registers support QImode ZERO_EXTRACT. */
18377 {
18380 }
18381 else
18382 {
18385 }
18387 /* Extract remainder from AH. */
18391 else
18392 {
18393 /* Need a new scratch register since the old one has result
18394 of 8bit divide. */
18398 }
18401 /* Zero extend quotient from AL. */
18407 }
18409 #define LEA_MAX_STALL (3)
18410 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
18412 /* Increase given DISTANCE in half-cycles according to
18413 dependencies between PREV and NEXT instructions.
18414 Add 1 half-cycle if there is no dependency and
18415 go to next cycle if there is some dependecy. */
18417 static unsigned int
18419 {
18435 }
18437 /* Function checks if instruction INSN defines register number
18438 REGNO1 or REGNO2. */
18440 static bool
18443 {
18444 df_ref def;
18454 }
18456 /* Function checks if instruction INSN uses register number
18457 REGNO as a part of address expression. */
18459 static bool
18461 {
18462 df_ref use;
18469 }
18471 /* Search backward for non-agu definition of register number REGNO1
18472 or register number REGNO2 in basic block starting from instruction
18473 START up to head of basic block or instruction INSN.
18475 Function puts true value into *FOUND var if definition was found
18476 and false otherwise.
18478 Distance in half-cycles between START and found instruction or head
18479 of BB is added to DISTANCE and returned. */
18481 static int
18485 {
18495 {
18497 {
18500 {
18503 {
18506 }
18507 }
18510 }
18515 }
18518 }
18520 /* Search backward for non-agu definition of register number REGNO1
18521 or register number REGNO2 in INSN's basic block until
18522 1. Pass LEA_SEARCH_THRESHOLD instructions, or
18523 2. Reach neighbour BBs boundary, or
18524 3. Reach agu definition.
18525 Returns the distance between the non-agu definition point and INSN.
18526 If no definition point, returns -1. */
18528 static int
18531 {
18542 {
18543 edge e;
18544 edge_iterator ei;
18549 {
18552 }
18558 else
18559 {
18564 {
18565 int bb_dist
18571 {
18578 }
18579 }
18582 }
18583 }
18585 /* get_attr_type may modify recog data. We want to make sure
18586 that recog data is valid for instruction INSN, on which
18587 distance_non_agu_define is called. INSN is unchanged here. */
18594 }
18596 /* Return the distance in half-cycles between INSN and the next
18597 insn that uses register number REGNO in memory address added
18598 to DISTANCE. Return -1 if REGNO0 is set.
18600 Put true value into *FOUND if register usage was found and
18601 false otherwise.
18602 Put true value into *REDEFINED if register redefinition was
18603 found and false otherwise. */
18605 static int
18609 {
18618 {
18621 /* If insn and start belong to the same bb, set prev to insn,
18622 so the call to increase_distance will increase the distance
18623 between insns by 1. */
18625 }
18630 {
18632 {
18635 {
18636 /* Return DISTANCE if OP0 is used in memory
18637 address in NEXT. */
18640 }
18643 {
18644 /* Return -1 if OP0 is set in NEXT. */
18647 }
18650 }
18656 }
18659 }
18661 /* Return the distance between INSN and the next insn that uses
18662 register number REGNO0 in memory address. Return -1 if no such
18663 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18665 static int
18667 {
18679 {
18680 edge e;
18681 edge_iterator ei;
18686 {
18689 }
18695 else
18696 {
18702 {
18703 int bb_dist
18708 {
18715 }
18716 }
18719 }
18720 }
18726 }
18728 /* Define this macro to tune LEA priority vs ADD, it take effect when
18729 there is a dilemma of choicing LEA or ADD
18730 Negative value: ADD is more preferred than LEA
18731 Zero: Netrual
18732 Positive value: LEA is more preferred than ADD*/
18733 #define IX86_LEA_PRIORITY 0
18735 /* Return true if usage of lea INSN has performance advantage
18736 over a sequence of instructions. Instructions sequence has
18737 SPLIT_COST cycles higher latency than lea latency. */
18739 static bool
18742 {
18745 /* For Silvermont if using a 2-source or 3-source LEA for
18746 non-destructive destination purposes, or due to wanting
18747 ability to use SCALE, the use of LEA is justified. */
18749 {
18757 }
18763 {
18764 /* If there is no non AGU operand definition, no AGU
18765 operand usage and split cost is 0 then both lea
18766 and non lea variants have same priority. Currently
18767 we prefer lea for 64 bit code and non lea on 32 bit
18768 code. */
18771 else
18773 }
18775 /* With longer definitions distance lea is more preferable.
18776 Here we change it to take into account splitting cost and
18777 lea priority. */
18780 /* If there is no use in memory addess then we just check
18781 that split cost exceeds AGU stall. */
18785 /* If this insn has both backward non-agu dependence and forward
18786 agu dependence, the one with short distance takes effect. */
18788 }
18790 /* Return true if it is legal to clobber flags by INSN and
18791 false otherwise. */
18793 static bool
18795 {
18797 df_ref use;
18798 bitmap live;
18801 {
18803 {
18810 }
18816 }
18820 }
18822 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18823 move and add to avoid AGU stalls. */
18825 bool
18827 {
18830 /* Check if we need to optimize. */
18834 /* Check it is correct to split here. */
18842 /* We need to split only adds with non destructive
18843 destination operand. */
18846 else
18848 }
18850 /* Return true if we should emit lea instruction instead of mov
18851 instruction. */
18853 bool
18855 {
18858 /* Check if we need to optimize. */
18862 /* Use lea for reg to reg moves only. */
18870 }
18872 /* Return true if we need to split lea into a sequence of
18873 instructions to avoid AGU stalls. */
18875 bool
18877 {
18883 /* Check we need to optimize. */
18887 /* The "at least two components" test below might not catch simple
18888 move or zero extension insns if parts.base is non-NULL and parts.disp
18889 is const0_rtx as the only components in the address, e.g. if the
18890 register is %rbp or %r13. As this test is much cheaper and moves or
18891 zero extensions are the common case, do this check first. */
18897 /* Check if it is OK to split here. */
18904 /* There should be at least two components in the address. */
18909 /* We should not split into add if non legitimate pic
18910 operand is used as displacement. */
18925 /* Compute how many cycles we will add to execution time
18926 if split lea into a sequence of instructions. */
18928 {
18929 /* Have to use mov instruction if non desctructive
18930 destination form is used. */
18934 /* Have to add index to base if both exist. */
18938 /* Have to use shift and adds if scale is 2 or greater. */
18940 {
18945 else
18947 }
18949 /* Have to use add instruction with immediate if
18950 disp is non zero. */
18954 /* Subtract the price of lea. */
18956 }
18960 }
18962 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18963 matches destination. RTX includes clobber of FLAGS_REG. */
18965 static void
18968 {
18975 }
18977 /* Return true if regno1 def is nearest to the insn. */
18979 static bool
18981 {
18988 {
18990 {
18993 }
18999 }
19001 /* None of the regs is defined in the bb. */
19003 }
19005 /* Split lea instructions into a sequence of instructions
19006 which are executed on ALU to avoid AGU stalls.
19007 It is assumed that it is allowed to clobber flags register
19008 at lea position. */
19010 void
19012 {
19028 {
19031 }
19034 {
19037 }
19043 {
19044 /* Case r1 = r1 + ... */
19046 {
19047 /* If we have a case r1 = r1 + C * r2 then we
19048 should use multiplication which is very
19049 expensive. Assume cost model is wrong if we
19050 have such case here. */
19055 }
19056 else
19057 {
19058 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
19062 /* Use shift for scaling. */
19071 }
19072 }
19074 {
19077 }
19078 else
19079 {
19081 {
19084 }
19086 {
19089 }
19090 else
19091 {
19096 else
19097 {
19098 rtx tmp1;
19100 /* Find better operand for SET instruction, depending
19101 on which definition is farther from the insn. */
19104 else
19114 }
19117 }
19121 }
19122 }
19124 /* Return true if it is ok to optimize an ADD operation to LEA
19125 operation to avoid flag register consumation. For most processors,
19126 ADD is faster than LEA. For the processors like BONNELL, if the
19127 destination register of LEA holds an actual address which will be
19128 used soon, LEA is better and otherwise ADD is better. */
19130 bool
19132 {
19137 /* If a = b + c, (a!=b && a!=c), must use lea form. */
19145 }
19147 /* Return true if destination reg of SET_BODY is shift count of
19148 USE_BODY. */
19150 static bool
19152 {
19153 rtx set_dest;
19154 rtx shift_rtx;
19157 /* Retrieve destination of SET_BODY. */
19159 {
19168 use_body))
19173 }
19175 /* Retrieve shift count of USE_BODY. */
19177 {
19189 }
19197 {
19200 /* Return true if shift count is dest of SET_BODY. */
19202 {
19203 /* Add check since it can be invoked before register
19204 allocation in pre-reload schedule. */
19210 }
19211 }
19214 }
19216 /* Return true if destination reg of SET_INSN is shift count of
19217 USE_INSN. */
19219 bool
19221 {
19224 }
19226 /* Return TRUE or FALSE depending on whether the unary operator meets the
19227 appropriate constraints. */
19229 bool
19231 machine_mode,
19233 {
19234 /* If one of operands is memory, source and destination must match. */
19240 }
19242 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
19243 are ok, keeping in mind the possible movddup alternative. */
19245 bool
19247 {
19253 }
19255 /* Post-reload splitter for converting an SF or DFmode value in an
19256 SSE register into an unsigned SImode. */
19258 void
19260 {
19261 machine_mode vecmode;
19271 /* Load up the value into the low element. We must ensure that the other
19272 elements are valid floats -- zero is the easiest such value. */
19274 {
19277 else
19279 }
19280 else
19281 {
19286 else
19288 }
19308 else
19313 }
19315 /* Convert an unsigned DImode value into a DFmode, using only SSE.
19316 Expects the 64-bit DImode to be supplied in a pair of integral
19317 registers. Requires SSE2; will use SSE3 if available. For x86_32,
19318 -mfpmath=sse, !optimize_size only. */
19320 void
19322 {
19326 rtx x;
19332 {
19335 }
19336 else
19337 {
19341 }
19349 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
19352 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
19353 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
19354 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
19355 (0x1.0p84 + double(fp_value_hi_xmm)).
19356 Note these exponents differ by 32. */
19360 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
19361 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
19370 /* Add the upper and lower DFmode values together. */
19373 else
19374 {
19378 }
19381 }
19383 /* Not used, but eases macroization of patterns. */
19384 void
19386 {
19388 }
19390 /* Convert an unsigned SImode value into a DFmode. Only currently used
19391 for SSE, but applicable anywhere. */
19393 void
19395 {
19396 REAL_VALUE_TYPE TWO31r;
19411 }
19413 /* Convert a signed DImode value into a DFmode. Only used for SSE in
19414 32-bit mode; otherwise we have a direct convert instruction. */
19416 void
19418 {
19419 REAL_VALUE_TYPE TWO32r;
19437 }
19439 /* Convert an unsigned SImode value into a SFmode, using only SSE.
19440 For x86_32, -mfpmath=sse, !optimize_size only. */
19441 void
19443 {
19444 REAL_VALUE_TYPE ONE16r;
19463 }
19465 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
19466 a vector of unsigned ints VAL to vector of floats TARGET. */
19468 void
19470 {
19472 REAL_VALUE_TYPE TWO16r;
19479 else
19484 OPTAB_DIRECT);
19495 OPTAB_DIRECT);
19497 OPTAB_DIRECT);
19500 }
19502 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
19503 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
19504 This is done by doing just signed conversion if < 0x1p31, and otherwise by
19505 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
19507 rtx
19509 {
19510 REAL_VALUE_TYPE TWO31r;
19525 {
19531 }
19540 OPTAB_DIRECT);
19541 else
19542 {
19548 OPTAB_DIRECT);
19549 }
19552 }
19554 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
19555 then replicate the value for all elements of the vector
19556 register. */
19558 rtx
19560 {
19562 rtvec v;
19563 machine_mode scalar_mode;
19566 {
19599 }
19600 }
19602 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
19603 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
19604 for an SSE register. If VECT is true, then replicate the mask for
19605 all elements of the vector register. If INVERT is true, then create
19606 a mask excluding the sign bit. */
19608 rtx
19610 {
19612 wide_int w;
19616 {
19647 }
19654 /* Force this value into the low part of a fp vector constant. */
19663 }
19665 /* Generate code for floating point ABS or NEG. */
19667 void
19669 rtx operands[])
19670 {
19681 {
19687 }
19689 /* NEG and ABS performed with SSE use bitwise mask operations.
19690 Create the appropriate mask now. */
19693 else
19703 {
19705 rtvec par;
19710 else
19711 {
19714 }
19716 }
19717 else
19719 }
19721 /* Expand a copysign operation. Special case operand 0 being a constant. */
19723 void
19725 {
19739 else
19743 {
19750 {
19753 else
19754 {
19758 }
19759 }
19769 else
19773 }
19774 else
19775 {
19785 else
19789 }
19790 }
19792 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19793 be a constant, and so has already been expanded into a vector constant. */
19795 void
19797 {
19813 {
19816 }
19817 }
19819 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19820 so we have to do two masks. */
19822 void
19824 {
19839 {
19840 /* Shouldn't happen often (it's useless, obviously), but when it does
19841 we'd generate incorrect code if we continue below. */
19844 }
19847 {
19858 }
19859 else
19860 {
19862 {
19864 }
19866 {
19870 }
19874 {
19877 }
19879 {
19884 }
19886 }
19890 }
19892 /* Return TRUE or FALSE depending on whether the first SET in INSN
19893 has source and destination with matching CC modes, and that the
19894 CC mode is at least as constrained as REQ_MODE. */
19896 bool
19898 {
19899 rtx set;
19900 machine_mode set_mode;
19910 {
19920 /* FALLTHRU */
19924 /* FALLTHRU */
19928 /* FALLTHRU */
19943 }
19946 }
19948 /* Generate insn patterns to do an integer compare of OPERANDS. */
19950 static rtx
19952 {
19953 machine_mode cmpmode;
19959 /* This is very simple, but making the interface the same as in the
19960 FP case makes the rest of the code easier. */
19964 /* Return the test that should be put into the flags user, i.e.
19965 the bcc, scc, or cmov instruction. */
19967 }
19969 /* Figure out whether to use ordered or unordered fp comparisons.
19970 Return the appropriate mode to use. */
19972 machine_mode
19974 {
19975 /* ??? In order to make all comparisons reversible, we do all comparisons
19976 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19977 all forms trapping and nontrapping comparisons, we can make inequality
19978 comparisons trapping again, since it results in better code when using
19979 FCOM based compares. */
19981 }
19983 machine_mode
19985 {
19989 {
19992 }
19995 {
19996 /* Only zero flag is needed. */
20000 /* Codes needing carry flag. */
20003 /* Detect overflow checks. They need just the carry flag. */
20007 else
20012 /* Codes possibly doable only with sign flag when
20013 comparing against zero. */
20018 else
20019 /* For other cases Carry flag is not required. */
20021 /* Codes doable only with sign flag when comparing
20022 against zero, but we miss jump instruction for it
20023 so we need to use relational tests against overflow
20024 that thus needs to be zero. */
20029 else
20031 /* strcmp pattern do (use flags) and combine may ask us for proper
20032 mode. */
20037 }
20038 }
20040 /* Return the fixed registers used for condition codes. */
20042 static bool
20044 {
20048 }
20050 /* If two condition code modes are compatible, return a condition code
20051 mode which is compatible with both. Otherwise, return
20052 VOIDmode. */
20054 static machine_mode
20056 {
20073 {
20088 {
20103 }
20107 /* These are only compatible with themselves, which we already
20108 checked above. */
20110 }
20111 }
20114 /* Return a comparison we can do and that it is equivalent to
20115 swap_condition (code) apart possibly from orderedness.
20116 But, never change orderedness if TARGET_IEEE_FP, returning
20117 UNKNOWN in that case if necessary. */
20119 static enum rtx_code
20121 {
20123 {
20134 }
20135 }
20137 /* Return cost of comparison CODE using the best strategy for performance.
20138 All following functions do use number of instructions as a cost metrics.
20139 In future this should be tweaked to compute bytes for optimize_size and
20140 take into account performance of various instructions on various CPUs. */
20142 static int
20144 {
20147 /* The cost of code using bit-twiddling on %ah. */
20149 {
20172 }
20175 {
20182 }
20183 }
20185 /* Return strategy to use for floating-point. We assume that fcomi is always
20186 preferrable where available, since that is also true when looking at size
20187 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
20189 enum ix86_fpcmp_strategy
20191 {
20192 /* Do fcomi/sahf based test when profitable. */
20201 }
20203 /* Swap, force into registers, or otherwise massage the two operands
20204 to a fp comparison. The operands are updated in place; the new
20205 comparison code is returned. */
20207 static enum rtx_code
20209 {
20215 /* All of the unordered compare instructions only work on registers.
20216 The same is true of the fcomi compare instructions. The XFmode
20217 compare instructions require registers except when comparing
20218 against zero or when converting operand 1 from fixed point to
20219 floating point. */
20228 {
20231 }
20232 else
20233 {
20234 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
20235 things around if they appear profitable, otherwise force op0
20236 into a register. */
20242 {
20245 {
20248 }
20249 }
20255 {
20260 {
20263 }
20264 else
20266 }
20267 }
20269 /* Try to rearrange the comparison to make it cheaper. */
20273 {
20278 }
20283 }
20285 /* Convert comparison codes we use to represent FP comparison to integer
20286 code that will result in proper branch. Return UNKNOWN if no such code
20287 is available. */
20289 enum rtx_code
20291 {
20293 {
20316 }
20317 }
20319 /* Generate insn patterns to do a floating point compare of OPERANDS. */
20321 static rtx
20323 {
20330 /* Do fcomi/sahf based test when profitable. */
20332 {
20352 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
20359 /* In the unordered case, we have to check C2 for NaN's, which
20360 doesn't happen to work out to anything nice combination-wise.
20361 So do some bit twiddling on the value we've got in AH to come
20362 up with an appropriate set of condition codes. */
20366 {
20370 {
20373 }
20374 else
20375 {
20381 }
20386 {
20391 }
20392 else
20393 {
20396 }
20401 {
20404 }
20405 else
20406 {
20410 }
20415 {
20421 }
20422 else
20423 {
20426 }
20431 {
20436 }
20437 else
20438 {
20441 }
20446 {
20451 }
20452 else
20453 {
20456 }
20470 }
20475 }
20477 /* Return the test that should be put into the flags user, i.e.
20478 the bcc, scc, or cmov instruction. */
20481 const0_rtx);
20482 }
20484 static rtx
20486 {
20487 rtx ret;
20493 {
20496 }
20497 else
20501 }
20503 void
20505 {
20507 rtx tmp;
20510 {
20517 simple:
20521 pc_rtx);
20529 /* Expand DImode branch into multiple compare+branch. */
20530 {
20534 machine_mode submode;
20537 {
20540 }
20547 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
20548 avoid two branches. This costs one extra insn, so disable when
20549 optimizing for size. */
20554 {
20572 }
20574 /* Otherwise, if we are doing less-than or greater-or-equal-than,
20575 op1 is a constant and the low word is zero, then we can just
20576 examine the high word. Similarly for low word -1 and
20577 less-or-equal-than or greater-than. */
20581 {
20584 {
20587 }
20591 {
20594 }
20598 }
20600 /* Otherwise, we need two or three jumps. */
20609 {
20623 }
20625 /*
20626 * a < b =>
20627 * if (hi(a) < hi(b)) goto true;
20628 * if (hi(a) > hi(b)) goto false;
20629 * if (lo(a) < lo(b)) goto true;
20630 * false:
20631 */
20643 }
20648 }
20649 }
20651 /* Split branch based on floating point condition. */
20652 void
20655 {
20656 rtx condition;
20657 rtx i;
20660 {
20663 }
20666 tmp);
20674 }
20676 void
20678 {
20679 rtx ret;
20686 }
20688 /* Expand comparison setting or clearing carry flag. Return true when
20689 successful and set pop for the operation. */
20690 static bool
20692 {
20693 machine_mode mode =
20696 /* Do not handle double-mode compares that go through special path. */
20701 {
20702 rtx compare_op;
20707 /* Shortcut: following common codes never translate
20708 into carry flag compares. */
20713 /* These comparisons require zero flag; swap operands so they won't. */
20716 {
20719 }
20721 /* Try to expand the comparison and verify that we end up with
20722 carry flag based comparison. This fails to be true only when
20723 we decide to expand comparison using arithmetic that is not
20724 too common scenario. */
20733 else
20742 }
20748 {
20753 /* Convert a==0 into (unsigned)a<1. */
20762 /* Convert a>b into b<a or a>=b-1. */
20766 {
20768 /* Bail out on overflow. We still can swap operands but that
20769 would force loading of the constant into register. */
20774 }
20775 else
20776 {
20779 }
20782 /* Convert a>=0 into (unsigned)a<0x80000000. */
20800 }
20801 /* Swapping operands may cause constant to appear as first operand. */
20803 {
20807 }
20811 }
20813 bool
20815 {
20818 rtx compare_op;
20840 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20841 HImode insns, we'd be swallowed in word prefix ops. */
20847 {
20851 HOST_WIDE_INT diff;
20854 /* Sign bit compares are better done using shifts than we do by using
20855 sbb. */
20858 {
20859 /* Detect overlap between destination and compare sources. */
20863 {
20864 rtx flags;
20873 {
20875 compare_code
20877 }
20879 /* To simplify rest of code, restrict to the GEU case. */
20881 {
20885 }
20886 else
20887 {
20890 reverse_condition_maybe_unordered
20892 else
20895 }
20904 else
20907 }
20908 else
20909 {
20912 else
20913 {
20916 }
20918 }
20921 {
20922 /*
20923 * cmpl op0,op1
20924 * sbbl dest,dest
20925 * [addl dest, ct]
20926 *
20927 * Size 5 - 8.
20928 */
20933 }
20935 {
20936 /*
20937 * cmpl op0,op1
20938 * sbbl dest,dest
20939 * orl $ct, dest
20940 *
20941 * Size 8.
20942 */
20946 }
20948 {
20949 /*
20950 * cmpl op0,op1
20951 * sbbl dest,dest
20952 * notl dest
20953 * [addl dest, cf]
20954 *
20955 * Size 8 - 11.
20956 */
20962 }
20963 else
20964 {
20965 /*
20966 * cmpl op0,op1
20967 * sbbl dest,dest
20968 * [notl dest]
20969 * andl cf - ct, dest
20970 * [addl dest, ct]
20971 *
20972 * Size 8 - 11.
20973 */
20976 {
20980 }
20990 }
20996 }
20999 {
21004 {
21007 /* We may be reversing unordered compare to normal compare, that
21008 is not valid in general (we may convert non-trapping condition
21009 to trapping one), however on i386 we currently emit all
21010 comparisons unordered. */
21012 }
21013 else
21016 {
21020 }
21021 }
21026 {
21031 {
21036 }
21037 }
21039 /* Optimize dest = (op0 < 0) ? -1 : cf. */
21043 {
21044 /* If lea code below could be used, only optimize
21045 if it results in a 2 insn sequence. */
21051 {
21052 /*
21053 * notl op1 (if necessary)
21054 * sarl $31, op1
21055 * orl cf, op1
21056 */
21058 {
21062 }
21073 }
21074 }
21082 {
21083 /*
21084 * xorl dest,dest
21085 * cmpl op1,op2
21086 * setcc dest
21087 * lea cf(dest*(ct-cf)),dest
21088 *
21089 * Size 14.
21090 *
21091 * This also catches the degenerate setcc-only case.
21092 */
21094 rtx tmp;
21100 /* On x86_64 the lea instruction operates on Pmode, so we need
21101 to get arithmetics done in proper mode to match. */
21104 else
21105 {
21106 rtx out1;
21109 nops++;
21111 {
21113 nops++;
21114 }
21115 }
21117 {
21119 nops++;
21120 }
21122 {
21125 else
21127 }
21132 }
21134 /*
21135 * General case: Jumpful:
21136 * xorl dest,dest cmpl op1, op2
21137 * cmpl op1, op2 movl ct, dest
21138 * setcc dest jcc 1f
21139 * decl dest movl cf, dest
21140 * andl (cf-ct),dest 1:
21141 * addl ct,dest
21142 *
21143 * Size 20. Size 14.
21144 *
21145 * This is reasonably steep, but branch mispredict costs are
21146 * high on modern cpus, so consider failing only if optimizing
21147 * for space.
21148 */
21153 {
21155 {
21160 {
21163 /* We may be reversing unordered compare to normal compare,
21164 that is not valid in general (we may convert non-trapping
21165 condition to trapping one), however on i386 we currently
21166 emit all comparisons unordered. */
21168 }
21169 else
21170 {
21174 }
21177 {
21181 }
21182 }
21185 {
21186 /* notl op1 (if needed)
21187 sarl $31, op1
21188 andl (cf-ct), op1
21189 addl ct, op1
21191 For x < 0 (resp. x <= -1) there will be no notl,
21192 so if possible swap the constants to get rid of the
21193 complement.
21194 True/false will be -1/0 while code below (store flag
21195 followed by decrement) is 0/-1, so the constants need
21196 to be exchanged once more. */
21199 {
21202 }
21203 else
21207 }
21208 else
21209 {
21213 constm1_rtx,
21215 }
21227 }
21228 }
21231 {
21232 /* Try a few things more with specific constants and a variable. */
21234 optab op;
21240 /* If one of the two operands is an interesting constant, load a
21241 constant with the above and mask it in with a logical operation. */
21244 {
21250 else
21252 }
21254 {
21260 else
21262 }
21263 else
21270 /* Recurse to get the constant loaded. */
21274 /* Mask in the interesting variable. */
21276 OPTAB_WIDEN);
21281 }
21283 /*
21284 * For comparison with above,
21285 *
21286 * movl cf,dest
21287 * movl ct,tmp
21288 * cmpl op1,op2
21289 * cmovcc tmp,dest
21290 *
21291 * Size 15.
21292 */
21314 }
21316 /* Swap, force into registers, or otherwise massage the two operands
21317 to an sse comparison with a mask result. Thus we differ a bit from
21318 ix86_prepare_fp_compare_args which expects to produce a flags result.
21320 The DEST operand exists to help determine whether to commute commutative
21321 operators. The POP0/POP1 operands are updated in place. The new
21322 comparison code is returned, or UNKNOWN if not implementable. */
21324 static enum rtx_code
21327 {
21329 {
21332 /* AVX supports all the needed comparisons. */
21335 /* We have no LTGT as an operator. We could implement it with
21336 NE & ORDERED, but this requires an extra temporary. It's
21337 not clear that it's worth it. */
21344 /* These are supported directly. */
21351 /* AVX has 3 operand comparisons, no need to swap anything. */
21354 /* For commutative operators, try to canonicalize the destination
21355 operand to be first in the comparison - this helps reload to
21356 avoid extra moves. */
21359 /* FALLTHRU */
21365 /* These are not supported directly before AVX, and furthermore
21366 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
21367 comparison operands to transform into something that is
21368 supported. */
21375 }
21378 }
21380 /* Detect conditional moves that exactly match min/max operational
21381 semantics. Note that this is IEEE safe, as long as we don't
21382 interchange the operands.
21384 Returns FALSE if this conditional move doesn't match a MIN/MAX,
21385 and TRUE if the operation is successful and instructions are emitted. */
21387 static bool
21390 {
21391 machine_mode mode;
21393 rtx tmp;
21396 ;
21399 else
21406 else
21411 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
21412 but MODE may be a vector mode and thus not appropriate. */
21414 {
21416 rtvec v;
21421 }
21422 else
21423 {
21426 }
21430 }
21432 /* Expand an sse vector comparison. Return the register with the result. */
21434 static rtx
21437 {
21441 /* In general case result of comparison can differ from operands' type. */
21442 machine_mode cmp_mode;
21444 /* In AVX512F the result of comparison is an integer mask. */
21446 rtx x;
21449 {
21454 }
21455 else
21468 /* Compare patterns for int modes are unspec in AVX512F only. */
21470 {
21474 {
21491 }
21494 {
21497 }
21498 }
21502 {
21505 }
21506 else
21510 }
21512 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
21513 operations. This is used for both scalar and vector conditional moves. */
21515 static void
21517 {
21521 /* In AVX512F the result of comparison is an integer mask. */
21529 {
21531 }
21534 {
21538 }
21541 {
21546 }
21549 {
21553 }
21556 {
21563 op_true,
21564 op_false)));
21565 }
21566 else
21567 {
21577 {
21591 {
21598 }
21613 {
21620 }
21644 }
21647 {
21651 }
21652 else
21653 {
21659 else
21671 }
21672 }
21673 }
21675 /* Expand a floating-point conditional move. Return true if successful. */
21677 bool
21679 {
21687 {
21688 machine_mode cmode;
21690 /* Since we've no cmove for sse registers, don't force bad register
21691 allocation just to gain access to it. Deny movcc when the
21692 comparison mode doesn't match the move mode. */
21711 }
21718 /* The floating point conditional move instructions don't directly
21719 support conditions resulting from a signed integer comparison. */
21723 {
21728 }
21735 }
21737 /* Expand a floating-point vector conditional move; a vcond operation
21738 rather than a movcc operation. */
21740 bool
21742 {
21744 rtx cmp;
21749 {
21750 rtx temp;
21752 {
21769 }
21771 OPTAB_DIRECT);
21774 }
21784 }
21786 /* Expand a signed/unsigned integral vector conditional move. */
21788 bool
21790 {
21800 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21801 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21810 {
21814 {
21820 }
21823 {
21829 }
21830 }
21839 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21843 ;
21844 else
21845 {
21846 /* Canonicalize the comparison to EQ, GT, GTU. */
21848 {
21865 /* FALLTHRU */
21875 }
21877 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21879 {
21881 {
21883 /* SSE4.1 supports EQ. */
21890 /* SSE4.2 supports GT/GTU. */
21897 }
21898 }
21900 /* Unsigned parallel compare is not supported by the hardware.
21901 Play some tricks to turn this into a signed comparison
21902 against 0. */
21904 {
21908 {
21915 {
21920 {
21929 }
21930 /* Subtract (-(INT MAX) - 1) from both operands to make
21931 them signed. */
21942 }
21951 /* Perform a parallel unsigned saturating subtraction. */
21963 }
21964 }
21965 }
21967 /* Allow the comparison to be done in one mode, but the movcc to
21968 happen in another mode. */
21970 {
21973 }
21974 else
21975 {
21981 }
21986 }
21988 /* AVX512F does support 64-byte integer vector operations,
21989 thus the longest vector we are faced with is V64QImode. */
21990 #define MAX_VECT_LEN 64
21992 struct expand_vec_perm_d
21993 {
21996 machine_mode vmode;
22000 };
22002 static bool
22005 {
22006 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
22007 expander, so args are either in d, or in op0, op1 etc. */
22013 {
22044 {
22047 }
22051 {
22054 }
22058 {
22061 }
22077 {
22080 }
22084 {
22087 }
22091 {
22094 }
22098 }
22103 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
22104 expander, so args are either in d, or in op0, op1 etc. */
22106 {
22114 }
22118 }
22120 /* Expand a variable vector permutation. */
22122 void
22124 {
22135 /* Number of elements in the vector. */
22144 {
22146 {
22147 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
22148 an constant shuffle operand. With a tiny bit of effort we can
22149 use VPERMD instead. A re-interpretation stall for V4DFmode is
22150 unfortunate but there's no avoiding it.
22151 Similarly for V16HImode we don't have instructions for variable
22152 shuffling, while for V32QImode we can use after preparing suitable
22153 masks vpshufb; vpshufb; vpermq; vpor. */
22156 {
22160 }
22161 else
22162 {
22166 }
22169 /* Replicate the low bits of the V4DImode mask into V8SImode:
22170 mask = { A B C D }
22171 t1 = { A A B B C C D D }. */
22179 else
22182 /* Multiply the shuffle indicies by two. */
22184 OPTAB_DIRECT);
22186 /* Add one to the odd shuffle indicies:
22187 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
22189 {
22192 }
22196 OPTAB_DIRECT);
22198 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
22203 }
22206 {
22208 /* The VPERMD and VPERMPS instructions already properly ignore
22209 the high bits of the shuffle elements. No need for us to
22210 perform an AND ourselves. */
22212 {
22217 }
22218 else
22219 {
22225 }
22232 else
22233 {
22239 }
22243 /* By combining the two 128-bit input vectors into one 256-bit
22244 input vector, we can use VPERMD and VPERMPS for the full
22245 two-operand shuffle. */
22277 /* From mask create two adjusted masks, which contain the same
22278 bits as mask in the low 7 bits of each vector element.
22279 The first mask will have the most significant bit clear
22280 if it requests element from the same 128-bit lane
22281 and MSB set if it requests element from the other 128-bit lane.
22282 The second mask will have the opposite values of the MSB,
22283 and additionally will have its 128-bit lanes swapped.
22284 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
22285 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
22286 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
22287 stands for other 12 bytes. */
22288 /* The bit whether element is from the same lane or the other
22289 lane is bit 4, so shift it up by 3 to the MSB position. */
22293 /* Clear MSB bits from the mask just in case it had them set. */
22295 /* After this t1 will have MSB set for elements from other lane. */
22297 /* Clear bits other than MSB. */
22299 /* Or in the lower bits from mask into t3. */
22301 /* And invert MSB bits in t1, so MSB is set for elements from the same
22302 lane. */
22304 /* Swap 128-bit lanes in t3. */
22309 /* And or in the lower bits from mask into t1. */
22312 {
22313 /* Each of these shuffles will put 0s in places where
22314 element from the other 128-bit lane is needed, otherwise
22315 will shuffle in the requested value. */
22319 /* For t3 the 128-bit lanes are swapped again. */
22324 /* And oring both together leads to the result. */
22331 }
22334 /* Similarly to the above one_operand_shuffle code,
22335 just for repeated twice for each operand. merge_two:
22336 code will merge the two results together. */
22360 }
22361 }
22364 {
22365 /* The XOP VPPERM insn supports three inputs. By ignoring the
22366 one_operand_shuffle special case, we avoid creating another
22367 set of constant vectors in memory. */
22370 /* mask = mask & {2*w-1, ...} */
22372 }
22373 else
22374 {
22375 /* mask = mask & {w-1, ...} */
22377 }
22385 /* For non-QImode operations, convert the word permutation control
22386 into a byte permutation control. */
22388 {
22393 /* Convert mask to vector of chars. */
22396 /* Replicate each of the input bytes into byte positions:
22397 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
22398 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
22399 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
22406 else
22409 /* Convert it into the byte positions by doing
22410 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
22416 }
22418 /* The actual shuffle operations all operate on V16QImode. */
22423 {
22430 }
22432 {
22439 }
22440 else
22441 {
22445 /* Shuffle the two input vectors independently. */
22451 merge_two:
22452 /* Then merge them together. The key is whether any given control
22453 element contained a bit set that indicates the second word. */
22457 {
22458 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
22459 more shuffle to convert the V2DI input mask into a V4SI
22460 input mask. At which point the masking that expand_int_vcond
22461 will work as desired. */
22469 }
22491 }
22492 }
22494 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
22495 true if we should do zero extension, else sign extension. HIGH_P is
22496 true if we want the N/2 high elements, else the low elements. */
22498 void
22500 {
22502 rtx tmp;
22505 {
22511 {
22515 else
22518 extract
22524 else
22527 extract
22533 else
22536 extract
22542 else
22545 extract
22551 else
22554 extract
22560 else
22563 extract
22569 else
22575 else
22581 else
22586 }
22589 {
22592 }
22594 {
22595 /* Shift higher 8 bytes to lower 8 bytes. */
22600 }
22601 else
22605 }
22606 else
22607 {
22611 {
22615 else
22621 else
22627 else
22632 }
22636 else
22643 }
22644 }
22646 /* Expand conditional increment or decrement using adb/sbb instructions.
22647 The default case using setcc followed by the conditional move can be
22648 done by generic code. */
22649 bool
22651 {
22653 rtx flags;
22655 rtx compare_op;
22658 machine_mode mode;
22673 {
22676 }
22679 {
22683 reverse_condition_maybe_unordered
22685 else
22687 }
22691 /* Construct either adc or sbb insn. */
22693 {
22695 {
22710 }
22711 }
22712 else
22713 {
22715 {
22730 }
22731 }
22735 }
22738 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22739 but works for floating pointer parameters and nonoffsetable memories.
22740 For pushes, it returns just stack offsets; the values will be saved
22741 in the right order. Maximally three parts are generated. */
22743 static int
22745 {
22750 else
22756 /* Optimize constant pool reference to immediates. This is used by fp
22757 moves, that force all constants to memory to allow combining. */
22759 {
22763 }
22766 {
22767 /* The only non-offsetable memories we handle are pushes. */
22776 }
22779 {
22781 /* Caution: if we looked through a constant pool memory above,
22782 the operand may actually have a different mode now. That's
22783 ok, since we want to pun this all the way back to an integer. */
22787 }
22790 {
22793 else
22794 {
22798 {
22802 }
22804 {
22809 }
22811 {
22812 REAL_VALUE_TYPE r;
22817 {
22824 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22825 long double may not be 80-bit. */
22834 }
22837 }
22838 else
22840 }
22841 }
22842 else
22843 {
22847 {
22850 {
22854 }
22856 {
22860 }
22862 {
22863 REAL_VALUE_TYPE r;
22869 /* real_to_target puts 32-bit pieces in each long. */
22871 gen_int_mode
22874 DImode);
22878 else
22880 gen_int_mode
22883 DImode);
22884 }
22885 else
22887 }
22888 }
22891 }
22893 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22894 Return false when normal moves are needed; true when all required
22895 insns have been emitted. Operands 2-4 contain the input values
22896 int the correct order; operands 5-7 contain the output values. */
22898 void
22900 {
22908 /* The DFmode expanders may ask us to move double.
22909 For 64bit target this is single move. By hiding the fact
22910 here we simplify i386.md splitters. */
22912 {
22913 /* Optimize constant pool reference to immediates. This is used by
22914 fp moves, that force all constants to memory to allow combining. */
22921 {
22924 }
22925 else
22930 }
22932 /* The only non-offsettable memory we handle is push. */
22935 else
22942 /* When emitting push, take care for source operands on the stack. */
22945 {
22948 /* Compensate for the stack decrement by 4. */
22953 /* src_base refers to the stack pointer and is
22954 automatically decreased by emitted push. */
22958 }
22960 /* We need to do copy in the right order in case an address register
22961 of the source overlaps the destination. */
22963 {
22964 rtx tmp;
22967 {
22971 collisions++;
22972 }
22974 /* Collision in the middle part can be handled by reordering. */
22976 {
22979 }
22983 {
22985 {
22988 }
22989 else
22990 {
22993 }
22994 }
22996 /* If there are more collisions, we can't handle it by reordering.
22997 Do an lea to the last part and use only one colliding move. */
22999 {
23006 /* Handle the case when the last part isn't valid for lea.
23007 Happens in 64-bit mode storing the 12-byte XFmode. */
23013 {
23018 {
23019 /* It is not valid to use %gs: or %fs: in
23020 lea though, so we need to remove it from the
23021 address used for lea and add it to each individual
23022 memory loads instead. */
23026 {
23028 {
23034 {
23038 }
23039 }
23043 }
23045 }
23046 }
23052 {
23057 }
23058 }
23059 }
23062 {
23064 {
23066 {
23071 }
23073 {
23076 }
23077 }
23078 else
23079 {
23080 /* In 64bit mode we don't have 32bit push available. In case this is
23081 register, it is OK - we will just use larger counterpart. We also
23082 retype memory - these comes from attempt to avoid REX prefix on
23083 moving of second half of TFmode value. */
23085 {
23087 {
23098 }
23102 }
23103 }
23107 }
23109 /* Choose correct order to not overwrite the source before it is copied. */
23119 {
23121 {
23124 }
23125 }
23126 else
23127 {
23129 {
23132 }
23133 }
23135 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
23137 {
23146 }
23152 }
23154 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
23155 left shift by a constant, either using a single shift or
23156 a sequence of add instructions. */
23158 static void
23160 {
23166 {
23170 }
23171 else
23172 {
23175 }
23176 }
23178 void
23180 {
23189 {
23194 {
23200 }
23201 else
23202 {
23210 }
23212 }
23219 {
23220 /* Assuming we've chosen a QImode capable registers, then 1 << N
23221 can be done with two 32/64-bit shifts, no branches, no cmoves. */
23223 {
23239 }
23241 /* Otherwise, we can get the same results by manually performing
23242 a bit extract operation on bit 5/6, and then performing the two
23243 shifts. The two methods of getting 0/1 into low/high are exactly
23244 the same size. Avoiding the shift in the bit extract case helps
23245 pentium4 a bit; no one else seems to care much either way. */
23246 else
23247 {
23248 machine_mode half_mode;
23252 HOST_WIDE_INT bits;
23253 rtx x;
23256 {
23262 }
23263 else
23264 {
23270 }
23274 else
23282 }
23287 }
23290 {
23291 /* For -1 << N, we can avoid the shld instruction, because we
23292 know that we're shifting 0...31/63 ones into a -1. */
23296 else
23298 }
23299 else
23300 {
23308 }
23313 {
23319 }
23320 else
23321 {
23326 }
23327 }
23329 void
23331 {
23341 {
23346 {
23352 }
23354 {
23363 }
23364 else
23365 {
23373 }
23374 }
23375 else
23376 {
23388 {
23396 scratch));
23397 }
23398 else
23399 {
23404 }
23405 }
23406 }
23408 void
23410 {
23420 {
23425 {
23432 }
23433 else
23434 {
23442 }
23443 }
23444 else
23445 {
23457 {
23463 scratch));
23464 }
23465 else
23466 {
23471 }
23472 }
23473 }
23475 /* Predict just emitted jump instruction to be taken with probability PROB. */
23476 static void
23478 {
23482 }
23484 /* Helper function for the string operations below. Dest VARIABLE whether
23485 it is aligned to VALUE bytes. If true, jump to the label. */
23488 {
23493 else
23499 else
23502 }
23504 /* Adjust COUNTER by the VALUE. */
23505 static void
23507 {
23512 }
23514 /* Zero extend possibly SImode EXP to Pmode register. */
23515 rtx
23517 {
23519 }
23521 /* Divide COUNTREG by SCALE. */
23522 static rtx
23524 {
23525 rtx sc;
23537 }
23539 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
23540 DImode for constant loop counts. */
23542 static machine_mode
23544 {
23552 }
23554 /* Copy the address to a Pmode register. This is used for x32 to
23555 truncate DImode TLS address to a SImode register. */
23557 static rtx
23559 {
23560 rtx reg;
23562 {
23566 }
23567 else
23568 {
23573 }
23574 }
23576 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
23577 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
23578 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
23579 memory by VALUE (supposed to be in MODE).
23581 The size is rounded down to whole number of chunk size moved at once.
23582 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
23585 static void
23590 {
23597 rtx size;
23606 /* Those two should combine. */
23608 {
23612 }
23619 /* This assert could be relaxed - in this case we'll need to compute
23620 smallest power of two, containing in PIECE_SIZE_N and pass it to
23621 offset_address. */
23627 {
23631 /* When unrolling for chips that reorder memory reads and writes,
23632 we can save registers by using single temporary.
23633 Also using 4 temporaries is overkill in 32bit mode. */
23635 {
23637 {
23639 {
23640 destmem =
23642 srcmem =
23644 }
23646 }
23647 }
23648 else
23649 {
23653 {
23656 {
23657 srcmem =
23659 }
23661 }
23663 {
23665 {
23666 destmem =
23668 }
23670 }
23671 }
23672 }
23673 else
23675 {
23677 destmem =
23680 }
23690 {
23696 else
23698 }
23699 else
23707 {
23712 }
23714 }
23716 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
23717 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
23718 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
23719 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
23720 ORIG_VALUE is the original value passed to memset to fill the memory with.
23721 Other arguments have same meaning as for previous function. */
23723 static void
23726 rtx count,
23728 {
23729 rtx destexp;
23730 rtx srcexp;
23731 rtx countreg;
23732 HOST_WIDE_INT rounded_count;
23734 /* If possible, it is shorter to use rep movs.
23735 TODO: Maybe it is better to move this logic to decide_alg. */
23746 {
23750 }
23751 else
23754 {
23759 }
23764 {
23767 }
23768 else
23769 {
23773 {
23777 }
23778 else
23781 {
23786 }
23787 else
23788 {
23791 }
23794 }
23795 }
23797 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23798 DESTMEM.
23799 SRC is passed by pointer to be updated on return.
23800 Return value is updated DST. */
23801 static rtx
23803 HOST_WIDE_INT size_to_move)
23804 {
23807 machine_mode move_mode;
23810 /* Find the widest mode in which we could perform moves.
23811 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23812 it until move of such size is supported. */
23817 {
23821 }
23823 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23824 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23826 {
23831 {
23835 }
23836 }
23842 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23846 {
23847 /* We move from memory to memory, so we'll need to do it via
23848 a temporary register. */
23859 piece_size);
23861 piece_size);
23862 }
23864 /* Update DST and SRC rtx. */
23867 }
23869 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23870 static void
23873 {
23876 {
23881 /* For now MAX_SIZE should be a power of 2. This assert could be
23882 relaxed, but it'll require a bit more complicated epilogue
23883 expanding. */
23886 {
23889 }
23891 }
23893 {
23899 }
23901 /* When there are stringops, we can cheaply increase dest and src pointers.
23902 Otherwise we save code size by maintaining offset (zero is readily
23903 available from preceding rep operation) and using x86 addressing modes.
23904 */
23906 {
23908 {
23915 }
23917 {
23924 }
23926 {
23933 }
23934 }
23935 else
23936 {
23938 rtx tmp;
23941 {
23952 }
23954 {
23967 }
23969 {
23978 }
23979 }
23980 }
23982 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23983 with value PROMOTED_VAL.
23984 SRC is passed by pointer to be updated on return.
23985 Return value is updated DST. */
23986 static rtx
23988 HOST_WIDE_INT size_to_move)
23989 {
23992 machine_mode move_mode;
23995 /* Find the widest mode in which we could perform moves.
23996 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23997 it until move of such size is supported. */
24002 {
24005 }
24012 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
24016 {
24018 {
24021 piece_size);
24023 }
24031 piece_size);
24032 }
24034 /* Update DST rtx. */
24036 }
24037 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
24038 static void
24041 {
24042 count =
24048 }
24050 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
24051 static void
24054 {
24055 rtx dest;
24058 {
24063 /* For now MAX_SIZE should be a power of 2. This assert could be
24064 relaxed, but it'll require a bit more complicated epilogue
24065 expanding. */
24068 {
24070 {
24073 else
24075 }
24076 }
24078 }
24080 {
24083 }
24085 {
24088 {
24093 }
24094 else
24095 {
24104 }
24107 }
24109 {
24112 {
24115 }
24116 else
24117 {
24122 }
24125 }
24127 {
24133 }
24135 {
24141 }
24143 {
24149 }
24150 }
24152 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
24153 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
24154 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
24155 ignored.
24156 Return value is updated DESTMEM. */
24157 static rtx
24162 {
24165 {
24167 {
24170 {
24173 else
24175 }
24176 else
24182 }
24183 }
24185 }
24187 /* Test if COUNT&SIZE is nonzero and if so, expand movme
24188 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
24189 and jump to DONE_LABEL. */
24190 static void
24196 {
24199 rtx modesize;
24202 /* If we do not have vector value to copy, we must reduce size. */
24204 {
24206 {
24211 }
24212 else
24214 }
24215 else
24216 {
24217 /* Choose appropriate vector mode. */
24223 }
24228 {
24231 else
24232 {
24235 }
24237 }
24243 {
24247 }
24249 {
24252 else
24253 {
24256 }
24258 }
24264 }
24266 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
24267 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
24268 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
24269 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
24270 DONE_LABEL is a label after the whole copying sequence. The label is created
24271 on demand if *DONE_LABEL is NULL.
24272 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
24273 bounds after the initial copies.
24275 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
24276 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
24277 we will dispatch to a library call for large blocks.
24279 In pseudocode we do:
24281 if (COUNT < SIZE)
24282 {
24283 Assume that SIZE is 4. Bigger sizes are handled analogously
24284 if (COUNT & 4)
24285 {
24286 copy 4 bytes from SRCPTR to DESTPTR
24287 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
24288 goto done_label
24289 }
24290 if (!COUNT)
24291 goto done_label;
24292 copy 1 byte from SRCPTR to DESTPTR
24293 if (COUNT & 2)
24294 {
24295 copy 2 bytes from SRCPTR to DESTPTR
24296 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
24297 }
24298 }
24299 else
24300 {
24301 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
24302 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
24304 OLD_DESPTR = DESTPTR;
24305 Align DESTPTR up to DESIRED_ALIGN
24306 SRCPTR += DESTPTR - OLD_DESTPTR
24307 COUNT -= DEST_PTR - OLD_DESTPTR
24308 if (DYNAMIC_CHECK)
24309 Round COUNT down to multiple of SIZE
24310 << optional caller supplied zero size guard is here >>
24311 << optional caller suppplied dynamic check is here >>
24312 << caller supplied main copy loop is here >>
24313 }
24314 done_label:
24315 */
24316 static void
24319 machine_mode mode,
24329 {
24332 rtx modesize;
24334 rtx mode_value;
24336 /* Chose proper value to copy. */
24339 else
24343 /* See if block is big or small, handle small blocks. */
24345 {
24356 /* Handle sizes > 3. */
24363 /* Nothing to copy? Jump to DONE_LABEL if so */
24367 /* Do a byte copy. */
24371 else
24372 {
24375 }
24377 /* Handle sizes 2 and 3. */
24384 else
24385 {
24390 }
24396 }
24397 else
24401 /* Start memcpy for COUNT >= SIZE. */
24403 {
24406 }
24408 /* Copy first desired_align bytes. */
24414 {
24417 else
24418 {
24421 }
24424 }
24427 /* Copy last SIZE bytes. */
24434 else
24435 {
24441 }
24443 {
24447 else
24448 {
24451 }
24452 }
24454 /* Align destination. */
24456 {
24460 /* Align destptr up, place it to new register. */
24469 /* See how many bytes we skipped. */
24473 /* Adjust srcptr and count. */
24479 /* We copied at most size + prolog_size. */
24482 else
24485 /* Our loops always round down the bock size, but for dispatch to library
24486 we need precise value. */
24490 }
24491 else
24492 {
24494 /* Decrease count, so we won't end up copying last word twice. */
24498 else
24502 }
24503 }
24506 /* This function is like the previous one, except here we know how many bytes
24507 need to be copied. That allows us to update alignment not only of DST, which
24508 is returned, but also of SRC, which is passed as a pointer for that
24509 reason. */
24510 static rtx
24515 {
24523 {
24527 }
24532 {
24534 {
24536 {
24539 else
24541 }
24542 else
24545 }
24546 }
24553 {
24559 {
24562 {
24566 }
24571 }
24575 }
24578 }
24580 /* Return true if ALG can be used in current context.
24581 Assume we expand memset if MEMSET is true. */
24582 static bool
24584 {
24589 /* Algorithms using the rep prefix want at least edi and ecx;
24590 additionally, memset wants eax and memcpy wants esi. Don't
24591 consider such algorithms if the user has appropriated those
24592 registers for their own purposes. */
24599 }
24601 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
24602 static enum stringop_alg
24606 {
24617 /* Even if the string operation call is cold, we still might spend a lot
24618 of time processing large blocks. */
24624 else
24630 else
24633 /* See maximal size for user defined algorithm. */
24635 {
24642 }
24644 /* If expected size is not known but max size is small enough
24645 so inline version is a win, set expected size into
24646 the range. */
24651 /* If user specified the algorithm, honnor it if possible. */
24655 /* rep; movq or rep; movl is the smallest variant. */
24657 {
24662 else
24665 }
24666 /* Very tiny blocks are best handled via the loop, REP is expensive to
24667 setup. */
24671 {
24675 {
24676 /* We get here if the algorithms that were not libcall-based
24677 were rep-prefix based and we are unable to use rep prefixes
24678 based on global register usage. Break out of the loop and
24679 use the heuristic below. */
24683 {
24687 {
24690 }
24691 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
24692 last non-libcall inline algorithm. */
24694 {
24695 /* When the current size is best to be copied by a libcall,
24696 but we are still forced to inline, run the heuristic below
24697 that will pick code for medium sized blocks. */
24699 {
24702 }
24705 }
24707 {
24710 }
24711 }
24712 }
24713 }
24714 /* When asked to inline the call anyway, try to pick meaningful choice.
24715 We look for maximal size of block that is faster to copy by hand and
24716 take blocks of at most of that size guessing that average size will
24717 be roughly half of the block.
24719 If this turns out to be bad, we might simply specify the preferred
24720 choice in ix86_costs. */
24724 {
24727 /* If there aren't any usable algorithms, then recursing on
24728 smaller sizes isn't going to find anything. Just return the
24729 simple byte-at-a-time copy loop. */
24731 {
24732 /* Pick something reasonable. */
24736 }
24744 else
24747 }
24750 }
24752 /* Decide on alignment. We know that the operand is already aligned to ALIGN
24753 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
24754 static int
24758 machine_mode move_mode)
24759 {
24770 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
24771 copying whole cacheline at once. */
24784 }
24787 /* Helper function for memcpy. For QImode value 0xXY produce
24788 0xXYXYXYXY of wide specified by MODE. This is essentially
24789 a * 0x10101010, but we can do slightly better than
24790 synth_mult by unwinding the sequence by hand on CPUs with
24791 slow multiply. */
24792 static rtx
24794 {
24796 rtx tmp;
24803 {
24811 }
24820 nops--;
24825 {
24829 OPTAB_DIRECT);
24830 }
24831 else
24832 {
24838 else
24840 else
24841 {
24844 reg =
24846 }
24856 }
24857 }
24859 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24860 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24861 alignment from ALIGN to DESIRED_ALIGN. */
24862 static rtx
24865 {
24866 rtx promoted_val;
24875 else
24879 }
24881 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24882 operations when profitable. The code depends upon architecture, block size
24883 and alignment, but always has one of the following overall structures:
24885 Aligned move sequence:
24887 1) Prologue guard: Conditional that jumps up to epilogues for small
24888 blocks that can be handled by epilogue alone. This is faster
24889 but also needed for correctness, since prologue assume the block
24890 is larger than the desired alignment.
24892 Optional dynamic check for size and libcall for large
24893 blocks is emitted here too, with -minline-stringops-dynamically.
24895 2) Prologue: copy first few bytes in order to get destination
24896 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24897 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24898 copied. We emit either a jump tree on power of two sized
24899 blocks, or a byte loop.
24901 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24902 with specified algorithm.
24904 4) Epilogue: code copying tail of the block that is too small to be
24905 handled by main body (or up to size guarded by prologue guard).
24907 Misaligned move sequence
24909 1) missaligned move prologue/epilogue containing:
24910 a) Prologue handling small memory blocks and jumping to done_label
24911 (skipped if blocks are known to be large enough)
24912 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24913 needed by single possibly misaligned move
24914 (skipped if alignment is not needed)
24915 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24917 2) Zero size guard dispatching to done_label, if needed
24919 3) dispatch to library call, if needed,
24921 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24922 with specified algorithm. */
24923 bool
24929 {
24930 rtx destreg;
24933 rtx tmp;
24949 /* TODO: Once value ranges are available, fill in proper data. */
24957 /* i386 can do misaligned access on reasonably increased cost. */
24961 /* ALIGN is the minimum of destination and source alignment, but we care here
24962 just about destination alignment. */
24968 {
24971 /* When COUNT is 0, there is nothing to do. */
24974 }
24975 else
24976 {
24985 }
24987 /* Make sure we don't need to care about overflow later on. */
24991 /* Step 0: Decide on preferred algorithm, desired alignment and
24992 size of chunks to be copied by main loop. */
24994 issetmem,
25001 /* For now vector-version of memset is generated only for memory zeroing, as
25002 creating of promoted vector value is very cheap in this case. */
25015 {
25034 /* Find the widest supported mode. */
25040 /* Find the corresponding vector mode with the same size as MOVE_MODE.
25041 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
25043 {
25048 }
25060 }
25068 /* Step 1: Prologue guard. */
25070 /* Alignment code needs count to be in register. */
25072 {
25075 {
25076 align_bytes
25080 else
25082 }
25085 }
25088 /* Misaligned move sequences handle both prologue and epilogue at once.
25089 Default code generation results in a smaller code for large alignments
25090 and also avoids redundant job when sizes are known precisely. */
25091 misaligned_prologue_used
25092 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
25098 /* Do the cheap promotion to allow better CSE across the
25099 main loop and epilogue (ie one load of the big constant in the
25100 front of all code.
25101 For now the misaligned move sequences do not have fast path
25102 without broadcasting. */
25104 {
25106 {
25112 }
25113 else
25114 {
25117 }
25118 }
25119 /* Misaligned move sequences handles both prologues and epilogues at once.
25120 Default code generation results in smaller code for large alignments and
25121 also avoids redundant job when sizes are known precisely. */
25123 {
25124 /* Misaligned move prologue handled small blocks by itself. */
25125 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
25130 desired_align < align
25139 {
25140 /* It is possible that we copied enough so the main loop will not
25141 execute. */
25151 else
25153 }
25154 }
25155 /* Ensure that alignment prologue won't copy past end of block. */
25157 {
25159 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
25160 Make sure it is power of 2. */
25163 /* To improve performance of small blocks, we jump around the VAL
25164 promoting mode. This mean that if the promoted VAL is not constant,
25165 we might not use it in the epilogue and have to use byte
25166 loop variant. */
25171 {
25172 /* If main algorithm works on QImode, no epilogue is needed.
25173 For small sizes just don't align anything. */
25176 else
25178 }
25181 {
25188 else
25190 }
25191 }
25193 /* Emit code to decide on runtime whether library call or inline should be
25194 used. */
25196 {
25198 {
25200 {
25204 }
25205 }
25206 else
25207 {
25217 else
25221 }
25222 }
25224 /* Step 2: Alignment prologue. */
25225 /* Do the expensive promotion once we branched off the small blocks. */
25231 {
25233 {
25234 /* Except for the first move in prologue, we no longer know
25235 constant offset in aliasing info. It don't seems to worth
25236 the pain to maintain it for the first move, so throw away
25237 the info early. */
25244 issetmem);
25245 /* At most desired_align - align bytes are copied. */
25248 else
25250 }
25251 else
25252 {
25253 /* If we know how many bytes need to be stored before dst is
25254 sufficiently aligned, maintain aliasing info accurately. */
25256 srcreg,
25257 promoted_val,
25258 vec_promoted_val,
25259 desired_align,
25260 align_bytes,
25261 issetmem);
25268 }
25270 && !min_size
25275 {
25276 /* It is possible that we copied enough so the main loop will not
25277 execute. */
25287 else
25289 }
25290 }
25292 {
25299 }
25303 /* Step 3: Main loop. */
25306 {
25329 }
25330 /* Adjust properly the offset of src and dest memory for aliasing. */
25332 {
25338 }
25339 else
25340 {
25344 }
25346 /* Step 4: Epilogue to copy the remaining bytes. */
25347 epilogue:
25349 {
25350 /* When the main loop is done, COUNT_EXP might hold original count,
25351 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
25352 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
25353 bytes. Compensate if needed. */
25356 {
25357 tmp =
25360 OPTAB_DIRECT);
25363 }
25366 }
25369 {
25372 epilogue_size_needed);
25373 else
25374 {
25378 epilogue_size_needed);
25379 else
25381 epilogue_size_needed);
25382 }
25383 }
25387 }
25390 /* Expand the appropriate insns for doing strlen if not just doing
25391 repnz; scasb
25393 out = result, initialized with the start address
25394 align_rtx = alignment of the address.
25395 scratch = scratch register, initialized with the startaddress when
25396 not aligned, otherwise undefined
25398 This is just the body. It needs the initializations mentioned above and
25399 some address computing at the end. These things are done in i386.md. */
25401 static void
25403 {
25405 rtx tmp;
25410 rtx mem;
25413 rtx cmp;
25419 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
25421 /* Is there a known alignment and is it less than 4? */
25423 {
25426 /* Is there a known alignment and is it not 2? */
25428 {
25432 /* Leave just the 3 lower bits. */
25442 }
25443 else
25444 {
25445 /* Since the alignment is 2, we have to check 2 or 0 bytes;
25446 check if is aligned to 4 - byte. */
25453 }
25457 /* Now compare the bytes. */
25459 /* Compare the first n unaligned byte on a byte per byte basis. */
25463 /* Increment the address. */
25466 /* Not needed with an alignment of 2 */
25468 {
25472 end_0_label);
25477 }
25480 end_0_label);
25483 }
25485 /* Generate loop to check 4 bytes at a time. It is not a good idea to
25486 align this loop. It gives only huge programs, but does not help to
25487 speed up. */
25494 /* This formula yields a nonzero result iff one of the bytes is zero.
25495 This saves three branches inside loop and many cycles. */
25503 align_4_label);
25506 {
25512 /* If zero is not in the first two bytes, move two bytes forward. */
25518 reg,
25519 tmpreg)));
25520 /* Emit lea manually to avoid clobbering of flags. */
25527 reg2,
25528 out)));
25529 }
25530 else
25531 {
25533 /* Is zero in the first two bytes? */
25540 pc_rtx);
25544 /* Not in the first two. Move two bytes forward. */
25550 }
25552 /* Avoid branch in fixing the byte. */
25560 }
25562 /* Expand strlen. */
25564 bool
25566 {
25569 /* The generic case of strlen expander is long. Avoid it's
25570 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
25573 && !TARGET_INLINE_ALL_STRINGOPS
25583 {
25584 /* Well it seems that some optimizer does not combine a call like
25585 foo(strlen(bar), strlen(bar));
25586 when the move and the subtraction is done here. It does calculate
25587 the length just once when these instructions are done inside of
25588 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
25589 often used and I use one fewer register for the lifetime of
25590 output_strlen_unroll() this is better. */
25596 /* strlensi_unroll_1 returns the address of the zero at the end of
25597 the string, like memchr(), so compute the length by subtracting
25598 the start address. */
25600 }
25601 else
25602 {
25603 rtx unspec;
25605 /* Can't use this if the user has appropriated eax, ecx, or edi. */
25618 /* If .md starts supporting :P, this can be done in .md. */
25624 }
25626 }
25628 /* For given symbol (function) construct code to compute address of it's PLT
25629 entry in large x86-64 PIC model. */
25630 static rtx
25632 {
25645 }
25647 rtx
25649 rtx callarg2,
25651 {
25661 {
25662 #if TARGET_MACHO
25665 #endif
25666 }
25667 else
25668 {
25669 /* Static functions and indirect calls don't need the pic register. Also,
25670 check if PLT was explicitly avoided via no-plt or "noplt" attribute, making
25671 it an indirect call. */
25673 && (!TARGET_64BIT
25678 && flag_plt
25682 {
25686 pic_offset_table_rtx);
25687 }
25688 }
25690 /* Skip setting up RAX register for -mskip-rax-setup when there are no
25691 parameters passed in vector registers. */
25696 {
25700 }
25703 && !TARGET_PECOFF
25711 {
25714 }
25719 {
25720 /* We should add bounds as destination register in case
25721 pointer with bounds may be returned. */
25723 {
25727 {
25732 }
25733 else
25734 {
25738 }
25739 }
25742 }
25746 {
25750 }
25754 {
25755 int const cregs_size
25760 {
25765 }
25766 }
25775 }
25777 /* Return true if the function being called was marked with attribute "noplt"
25778 or using -fno-plt and we are compiling for non-PIC and x86_64. We need to
25779 handle the non-PIC case in the backend because there is no easy interface
25780 for the front-end to force non-PLT calls to use the GOT. This is currently
25781 used only with 64-bit ELF targets to call the function marked "noplt"
25782 indirectly. */
25784 static bool
25786 {
25800 }
25802 /* Output the assembly for a call instruction. */
25806 {
25812 {
25817 /* SEH epilogue detection requires the indirect branch case
25818 to include REX.W. */
25821 else
25826 }
25828 /* SEH unwinding can require an extra nop to be emitted in several
25829 circumstances. Determine if we have one of those. */
25831 {
25835 {
25836 /* If we get to another real insn, we don't need the nop. */
25840 /* If we get to the epilogue note, prevent a catch region from
25841 being adjacent to the standard epilogue sequence. If non-
25842 call-exceptions, we'll have done this during epilogue emission. */
25844 && !flag_non_call_exceptions
25846 {
25849 }
25850 }
25852 /* If we didn't find a real insn following the call, prevent the
25853 unwinder from looking into the next function. */
25856 }
25862 else
25871 }
25872 \f
25873 /* Clear stack slot assignments remembered from previous functions.
25874 This is called from INIT_EXPANDERS once before RTL is emitted for each
25875 function. */
25879 {
25887 }
25889 /* Return a MEM corresponding to a stack slot with mode MODE.
25890 Allocate a new slot if necessary.
25892 The RTL for a function can have several slots available: N is
25893 which slot to use. */
25895 rtx
25897 {
25914 }
25916 static void
25918 {
25924 }
25925 \f
25926 /* Check whether x86 address PARTS is a pc-relative address. */
25928 static bool
25930 {
25938 {
25940 {
25957 }
25958 }
25960 }
25962 /* Calculate the length of the memory address in the instruction encoding.
25963 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25964 or other prefixes. We never generate addr32 prefix for LEA insn. */
25966 int
25968 {
25985 /* If this is not LEA instruction, add the length of addr32 prefix. */
25990 len++;
26004 /* Rule of thumb:
26005 - esp as the base always wants an index,
26006 - ebp as the base always wants a displacement,
26007 - r12 as the base always wants an index,
26008 - r13 as the base always wants a displacement. */
26010 /* Register Indirect. */
26012 {
26013 /* esp (for its index) and ebp (for its displacement) need
26014 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
26015 code. */
26022 len++;
26023 }
26025 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
26026 is not disp32, but disp32(%rip), so for disp32
26027 SIB byte is needed, unless print_operand_address
26028 optimizes it into disp32(%rip) or (%rip) is implied
26029 by UNSPEC. */
26031 {
26034 len++;
26035 }
26036 else
26037 {
26038 /* Find the length of the displacement constant. */
26040 {
26043 else
26045 }
26046 /* ebp always wants a displacement. Similarly r13. */
26048 len++;
26050 /* An index requires the two-byte modrm form.... */
26052 /* ...like esp (or r12), which always wants an index. */
26056 len++;
26057 }
26060 }
26062 /* Compute default value for "length_immediate" attribute. When SHORTFORM
26063 is set, expect that insn have 8bit immediate alternative. */
26064 int
26066 {
26072 {
26077 {
26080 {
26092 }
26094 {
26097 }
26098 }
26100 {
26110 /* Immediates for DImode instructions are encoded
26111 as 32bit sign extended values. */
26117 }
26118 }
26120 }
26122 /* Compute default value for "length_address" attribute. */
26123 int
26125 {
26129 {
26140 }
26145 {
26148 {
26153 constraints++;
26156 ;
26157 /* Skip ignored operands. */
26160 }
26162 }
26164 }
26166 /* Compute default value for "length_vex" attribute. It includes
26167 2 or 3 byte VEX prefix and 1 opcode byte. */
26169 int
26172 {
26175 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
26176 byte VEX prefix. */
26180 /* We can always use 2 byte VEX prefix in 32bit. */
26188 {
26189 /* REX.W bit uses 3 byte VEX prefix. */
26193 }
26194 else
26195 {
26196 /* REX.X or REX.B bits use 3 byte VEX prefix. */
26200 }
26203 }
26204 \f
26205 /* Return the maximum number of instructions a cpu can issue. */
26207 static int
26209 {
26211 {
26244 }
26245 }
26247 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
26248 by DEP_INSN and nothing set by DEP_INSN. */
26250 static bool
26252 {
26255 /* Simplify the test for uninteresting insns. */
26263 {
26266 }
26271 {
26274 }
26275 else
26281 /* This test is true if the dependent insn reads the flags but
26282 not any other potentially set register. */
26290 }
26292 /* Return true iff USE_INSN has a memory address with operands set by
26293 SET_INSN. */
26295 bool
26297 {
26302 {
26305 }
26307 }
26309 /* Helper function for exact_store_load_dependency.
26310 Return true if addr is found in insn. */
26311 static bool
26313 {
26320 {
26326 CASE_CONST_ANY:
26335 }
26339 {
26341 {
26351 }
26352 }
26354 }
26356 /* Return true if there exists exact dependency for store & load, i.e.
26357 the same memory address is used in them. */
26358 static bool
26360 {
26374 }
26376 static int
26378 {
26384 /* Anti and output dependencies have zero cost on all CPUs. */
26390 /* If we can't recognize the insns, we can't really do anything. */
26398 {
26401 /* Address Generation Interlock adds a cycle of latency. */
26403 {
26414 }
26418 /* ??? Compares pair with jump/setcc. */
26422 /* Floating point stores require value to be ready one cycle earlier. */
26430 /* INT->FP conversion is expensive. */
26434 /* There is one cycle extra latency between an FP op and a store. */
26444 /* Show ability of reorder buffer to hide latency of load by executing
26445 in parallel with previous instruction in case
26446 previous instruction is not needed to compute the address. */
26449 {
26450 /* Claim moves to take one cycle, as core can issue one load
26451 at time and the next load can start cycle later. */
26456 cost--;
26457 }
26461 /* The esp dependency is resolved before
26462 the instruction is really finished. */
26467 /* INT->FP conversion is expensive. */
26473 /* Show ability of reorder buffer to hide latency of load by executing
26474 in parallel with previous instruction in case
26475 previous instruction is not needed to compute the address. */
26478 {
26479 /* Claim moves to take one cycle, as core can issue one load
26480 at time and the next load can start cycle later. */
26486 else
26488 }
26499 /* Stack engine allows to execute push&pop instructions in parall. */
26503 /* FALLTHRU */
26509 /* Show ability of reorder buffer to hide latency of load by executing
26510 in parallel with previous instruction in case
26511 previous instruction is not needed to compute the address. */
26514 {
26518 /* Because of the difference between the length of integer and
26519 floating unit pipeline preparation stages, the memory operands
26520 for floating point are cheaper.
26522 ??? For Athlon it the difference is most probably 2. */
26525 else
26530 else
26532 }
26539 /* Stack engine allows to execute push&pop instructions in parall. */
26546 /* Show ability of reorder buffer to hide latency of load by executing
26547 in parallel with previous instruction in case
26548 previous instruction is not needed to compute the address. */
26551 {
26554 else
26556 }
26565 /* Increase cost of integer loads. */
26568 {
26571 {
26574 else
26575 {
26576 /* Increase cost of ld/st for short int types only
26577 because of store forwarding issue. */
26581 {
26582 /* Increase cost of store/load insn if exact
26583 dependence exists and it is load insn. */
26588 }
26589 }
26590 }
26591 }
26595 }
26598 }
26600 /* How many alternative schedules to try. This should be as wide as the
26601 scheduling freedom in the DFA, but no wider. Making this value too
26602 large results extra work for the scheduler. */
26604 static int
26606 {
26608 {
26621 /* We use lookahead value 4 for BD both before and after reload
26622 schedules. Plan is to have value 8 included for O3. */
26633 /* Generally, we want haifa-sched:max_issue() to look ahead as far
26634 as many instructions can be executed on a cycle, i.e.,
26635 issue_rate. I wonder why tuning for many CPUs does not do this. */
26638 /* Don't use lookahead for pre-reload schedule to save compile time. */
26643 }
26644 }
26646 /* Return true if target platform supports macro-fusion. */
26648 static bool
26650 {
26652 }
26654 /* Check whether current microarchitecture support macro fusion
26655 for insn pair "CONDGEN + CONDJMP". Refer to
26656 "Intel Architectures Optimization Reference Manual". */
26658 static bool
26660 {
26681 {
26686 {
26690 else
26692 }
26693 }
26700 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
26701 supported. */
26708 /* No fusion for RIP-relative address. */
26715 ix86_address parts;
26721 }
26726 /* Check whether conditional jump use Sign or Overflow Flags. */
26734 /* Return true for TYPE_TEST and TYPE_ICMP. */
26739 /* The following is the case that macro-fusion for alu + jmp. */
26743 /* No fusion for alu op with memory destination operand. */
26748 /* Macro-fusion for inc/dec + unsigned conditional jump is not
26749 supported. */
26758 }
26760 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
26761 execution. It is applied if
26762 (1) IMUL instruction is on the top of list;
26763 (2) There exists the only producer of independent IMUL instruction in
26764 ready list.
26765 Return index of IMUL producer if it was found and -1 otherwise. */
26766 static int
26768 {
26771 sd_iterator_def sd_it;
26772 dep_t dep;
26779 /* Check that IMUL instruction is on the top of ready list. */
26788 /* Search for producer of independent IMUL instruction. */
26790 {
26794 /* Skip IMUL instruction. */
26804 {
26805 rtx con;
26816 {
26817 sd_iterator_def sd_it1;
26818 dep_t dep1;
26819 /* Check if there is no other dependee for IMUL. */
26822 {
26823 rtx pro;
26829 }
26832 }
26833 }
26836 }
26838 }
26840 /* Try to find the best candidate on the top of ready list if two insns
26841 have the same priority - candidate is best if its dependees were
26842 scheduled earlier. Applied for Silvermont only.
26843 Return true if top 2 insns must be interchanged. */
26844 static bool
26846 {
26849 rtx set;
26850 sd_iterator_def sd_it;
26851 dep_t dep;
26854 #define INSN_TICK(INSN) (HID (INSN)->tick)
26875 {
26878 /* Determine winner more precise. */
26880 {
26881 rtx pro;
26887 }
26889 {
26890 rtx pro;
26896 }
26899 {
26900 /* Determine winner - load must win. */
26906 }
26908 }
26910 #undef INSN_TICK
26911 }
26913 /* Perform possible reodering of ready list for Atom/Silvermont only.
26914 Return issue rate. */
26915 static int
26918 {
26925 /* Set up issue rate. */
26928 /* Do reodering for BONNELL/SILVERMONT only. */
26932 /* Nothing to do if ready list contains only 1 instruction. */
26936 /* Do reodering for post-reload scheduler only. */
26941 {
26946 /* Put IMUL producer (ready[index]) at the top of ready list. */
26952 }
26954 /* Skip selective scheduling since HID is not populated in it. */
26958 {
26962 /* Swap 2 top elements of ready list. */
26966 }
26968 }
26970 static bool
26973 /* Returns true if lhs of insn is HW function argument register and set up
26974 is_spilled to true if it is likely spilled HW register. */
26975 static bool
26977 {
26978 rtx dst;
26982 /* Call instructions are not movable, ignore it. */
26993 {
26994 /* Is it likely spilled HW register? */
26999 }
27001 }
27003 /* Add output dependencies for chain of function adjacent arguments if only
27004 there is a move to likely spilled HW register. Return first argument
27005 if at least one dependence was added or NULL otherwise. */
27008 {
27016 /* Find nearest to call argument passing instruction. */
27018 {
27027 }
27031 {
27038 {
27041 }
27043 {
27044 /* Add output depdendence between two function arguments if chain
27045 of output arguments contains likely spilled HW registers. */
27049 }
27050 else
27052 }
27056 }
27058 /* Add output or anti dependency from insn to first_arg to restrict its code
27059 motion. */
27060 static void
27062 {
27063 rtx set;
27064 rtx tmp;
27066 /* Add anti dependencies for bounds stores. */
27071 {
27074 }
27081 {
27082 /* Add output dependency to the first function argument. */
27085 }
27086 /* Add anti dependency. */
27088 }
27090 /* Avoid cross block motion of function argument through adding dependency
27091 from the first non-jump instruction in bb. */
27092 static void
27094 {
27098 {
27100 {
27103 {
27106 }
27107 }
27111 }
27112 }
27114 /* Hook for pre-reload schedule - avoid motion of function arguments
27115 passed in likely spilled HW registers. */
27116 static void
27118 {
27127 {
27130 {
27131 /* Add dependee for first argument to predecessors if only
27132 region contains more than one block. */
27136 /* Skip trivial regions and region head blocks that can have
27137 predecessors outside of region. */
27139 {
27140 edge e;
27141 edge_iterator ei;
27143 /* Regions are SCCs with the exception of selective
27144 scheduling with pipelining of outer blocks enabled.
27145 So also check that immediate predecessors of a non-head
27146 block are in the same region. */
27148 {
27149 /* Avoid creating of loop-carried dependencies through
27150 using topological ordering in the region. */
27154 }
27155 }
27159 }
27160 }
27163 }
27165 /* Hook for pre-reload schedule - set priority of moves from likely spilled
27166 HW registers to maximum, to schedule them at soon as possible. These are
27167 moves from function argument registers at the top of the function entry
27168 and moves from function return value registers after call. */
27169 static int
27171 {
27172 rtx set;
27182 {
27189 }
27192 }
27194 /* Model decoder of Core 2/i7.
27195 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
27196 track the instruction fetch block boundaries and make sure that long
27197 (9+ bytes) instructions are assigned to D0. */
27199 /* Maximum length of an insn that can be handled by
27200 a secondary decoder unit. '8' for Core 2/i7. */
27203 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
27204 '16' for Core 2/i7. */
27207 /* Maximum number of instructions decoder can handle per cycle.
27208 '6' for Core 2/i7. */
27212 ix86_first_cycle_multipass_data_t;
27214 const_ix86_first_cycle_multipass_data_t;
27216 /* A variable to store target state across calls to max_issue within
27217 one cycle. */
27221 /* Initialize DATA. */
27222 static void
27224 {
27225 ix86_first_cycle_multipass_data_t data
27232 }
27234 /* Advancing the cycle; reset ifetch block counts. */
27235 static void
27237 {
27244 }
27248 /* Filter out insns from ready_try that the core will not be able to issue
27249 on current cycle due to decoder. */
27250 static void
27251 core2i7_first_cycle_multipass_filter_ready_try
27254 {
27256 {
27267 (!first_cycle_insn_p
27269 /* ... or it would not fit into the ifetch block ... */
27271 /* ... or the decoder is full already ... */
27273 /* ... mask the insn out. */
27274 {
27279 }
27280 }
27281 }
27283 /* Prepare for a new round of multipass lookahead scheduling. */
27284 static void
27288 {
27289 ix86_first_cycle_multipass_data_t data
27291 const_ix86_first_cycle_multipass_data_t prev_data
27294 /* Restore the state from the end of the previous round. */
27298 /* Filter instructions that cannot be issued on current cycle due to
27299 decoder restrictions. */
27301 first_cycle_insn_p);
27302 }
27304 /* INSN is being issued in current solution. Account for its impact on
27305 the decoder model. */
27306 static void
27310 {
27311 ix86_first_cycle_multipass_data_t data
27313 const_ix86_first_cycle_multipass_data_t prev_data
27323 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
27325 {
27328 }
27330 {
27334 }
27337 /* Filter out insns from ready_try that the core will not be able to issue
27338 on current cycle due to decoder. */
27341 }
27343 /* Revert the effect on ready_try. */
27344 static void
27348 {
27349 const_ix86_first_cycle_multipass_data_t data
27352 sbitmap_iterator sbi;
27356 {
27358 }
27359 }
27361 /* Save the result of multipass lookahead scheduling for the next round. */
27362 static void
27364 {
27365 const_ix86_first_cycle_multipass_data_t data
27367 ix86_first_cycle_multipass_data_t next_data
27371 {
27374 }
27375 }
27377 /* Deallocate target data. */
27378 static void
27380 {
27381 ix86_first_cycle_multipass_data_t data
27385 {
27389 }
27390 }
27392 /* Prepare for scheduling pass. */
27393 static void
27395 {
27396 /* Install scheduling hooks for current CPU. Some of these hooks are used
27397 in time-critical parts of the scheduler, so we only set them up when
27398 they are actually used. */
27400 {
27405 /* Do not perform multipass scheduling for pre-reload schedule
27406 to save compile time. */
27408 {
27424 /* Set decoder parameters. */
27429 }
27430 /* ... Fall through ... */
27440 }
27441 }
27443 \f
27444 /* Compute the alignment given to a constant that is being placed in memory.
27445 EXP is the constant and ALIGN is the alignment that the object would
27446 ordinarily have.
27447 The value of this function is used instead of that alignment to align
27448 the object. */
27450 int
27452 {
27455 {
27460 }
27466 }
27468 /* Compute the alignment for a variable for Intel MCU psABI. TYPE is
27469 the data type, and ALIGN is the alignment that the object would
27470 ordinarily have. */
27472 static int
27474 {
27480 /* Intel MCU psABI specifies scalar types > 4 bytes aligned to 4
27481 bytes. */
27484 {
27493 }
27494 }
27496 /* Compute the alignment for a static variable.
27497 TYPE is the data type, and ALIGN is the alignment that
27498 the object would ordinarily have. The value of this function is used
27499 instead of that alignment to align the object. */
27501 int
27503 {
27504 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
27505 for symbols from other compilation units or symbols that don't need
27506 to bind locally. In order to preserve some ABI compatibility with
27507 those compilers, ensure we don't decrease alignment from what we
27508 used to assume. */
27512 /* A data structure, equal or greater than the size of a cache line
27513 (64 bytes in the Pentium 4 and other recent Intel processors, including
27514 processors based on Intel Core microarchitecture) should be aligned
27515 so that its base address is a multiple of a cache line size. */
27517 int max_align
27524 {
27528 }
27537 {
27544 }
27546 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27547 to 16byte boundary. */
27549 {
27556 }
27562 {
27567 }
27569 {
27576 }
27581 {
27586 }
27589 {
27594 }
27597 }
27599 /* Compute the alignment for a local variable or a stack slot. EXP is
27600 the data type or decl itself, MODE is the widest mode available and
27601 ALIGN is the alignment that the object would ordinarily have. The
27602 value of this macro is used instead of that alignment to align the
27603 object. */
27605 unsigned int
27608 {
27612 {
27615 }
27616 else
27617 {
27620 }
27622 /* Don't do dynamic stack realignment for long long objects with
27623 -mpreferred-stack-boundary=2. */
27632 /* If TYPE is NULL, we are allocating a stack slot for caller-save
27633 register in MODE. We will return the largest alignment of XF
27634 and DF. */
27636 {
27640 }
27642 /* Don't increase alignment for Intel MCU psABI. */
27646 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27647 to 16byte boundary. Exact wording is:
27649 An array uses the same alignment as its elements, except that a local or
27650 global array variable of length at least 16 bytes or
27651 a C99 variable-length array variable always has alignment of at least 16 bytes.
27653 This was added to allow use of aligned SSE instructions at arrays. This
27654 rule is meant for static storage (where compiler can not do the analysis
27655 by itself). We follow it for automatic variables only when convenient.
27656 We fully control everything in the function compiled and functions from
27657 other unit can not rely on the alignment.
27659 Exclude va_list type. It is the common case of local array where
27660 we can not benefit from the alignment.
27662 TODO: Probably one should optimize for size only when var is not escaping. */
27665 {
27675 }
27677 {
27682 }
27684 {
27690 }
27695 {
27700 }
27703 {
27709 }
27711 }
27713 /* Compute the minimum required alignment for dynamic stack realignment
27714 purposes for a local variable, parameter or a stack slot. EXP is
27715 the data type or decl itself, MODE is its mode and ALIGN is the
27716 alignment that the object would ordinarily have. */
27718 unsigned int
27721 {
27725 {
27728 }
27729 else
27730 {
27733 }
27738 /* Don't do dynamic stack realignment for long long objects with
27739 -mpreferred-stack-boundary=2. */
27746 }
27747 \f
27748 /* Find a location for the static chain incoming to a nested function.
27749 This is a register, unless all free registers are used by arguments. */
27751 static rtx
27753 {
27756 /* While this function won't be called by the middle-end when a static
27757 chain isn't needed, it's also used throughout the backend so it's
27758 easiest to keep this check centralized. */
27763 {
27764 /* We always use R10 in 64-bit mode. */
27766 }
27767 else
27768 {
27772 /* By default in 32-bit mode we use ECX to pass the static chain. */
27776 {
27779 }
27780 else
27781 {
27784 }
27788 {
27789 /* Fastcall functions use ecx/edx for arguments, which leaves
27790 us with EAX for the static chain.
27791 Thiscall functions use ecx for arguments, which also
27792 leaves us with EAX for the static chain. */
27794 }
27796 {
27797 /* Thiscall functions use ecx for arguments, which leaves
27798 us with EAX and EDX for the static chain.
27799 We are using for abi-compatibility EAX. */
27801 }
27803 {
27804 /* For regparm 3, we have no free call-clobbered registers in
27805 which to store the static chain. In order to implement this,
27806 we have the trampoline push the static chain to the stack.
27807 However, we can't push a value below the return address when
27808 we call the nested function directly, so we have to use an
27809 alternate entry point. For this we use ESI, and have the
27810 alternate entry point push ESI, so that things appear the
27811 same once we're executing the nested function. */
27813 {
27819 }
27821 }
27822 }
27825 }
27827 /* Emit RTL insns to initialize the variable parts of a trampoline.
27828 FNDECL is the decl of the target address; M_TRAMP is a MEM for
27829 the trampoline, and CHAIN_VALUE is an RTX for the static chain
27830 to be passed to the target function. */
27832 static void
27834 {
27842 {
27845 /* Load the function address to r11. Try to load address using
27846 the shorter movl instead of movabs. We may want to support
27847 movq for kernel mode, but kernel does not use trampolines at
27848 the moment. FNADDR is a 32bit address and may not be in
27849 DImode when ptr_mode == SImode. Always use movl in this
27850 case. */
27853 {
27862 }
27863 else
27864 {
27871 }
27873 /* Load static chain using movabs to r10. Use the shorter movl
27874 instead of movabs when ptr_mode == SImode. */
27876 {
27879 }
27880 else
27881 {
27884 }
27893 /* Jump to r11; the last (unused) byte is a nop, only there to
27894 pad the write out to a single 32-bit store. */
27898 }
27899 else
27900 {
27903 /* Depending on the static chain location, either load a register
27904 with a constant, or push the constant to the stack. All of the
27905 instructions are the same size. */
27908 {
27910 {
27917 }
27918 }
27919 else
27934 /* Compute offset from the end of the jmp to the target function.
27935 In the case in which the trampoline stores the static chain on
27936 the stack, we need to skip the first insn which pushes the
27937 (call-saved) register static chain; this push is 1 byte. */
27944 }
27948 #ifdef HAVE_ENABLE_EXECUTE_STACK
27949 #ifdef CHECK_EXECUTE_STACK_ENABLED
27951 #endif
27954 #endif
27955 }
27956 \f
27957 /* The following file contains several enumerations and data structures
27958 built from the definitions in i386-builtin-types.def. */
27962 /* Table for the ix86 builtin non-function types. */
27965 /* Retrieve an element from the above table, building some of
27966 the types lazily. */
27968 static tree
27970 {
27982 {
27983 machine_mode mode;
27990 }
27991 else
27992 {
27998 else
28006 }
28010 }
28012 /* Table for the ix86 builtin function types. */
28015 /* Retrieve an element from the above table, building some of
28016 the types lazily. */
28018 static tree
28020 {
28021 tree type;
28030 {
28038 {
28041 }
28044 }
28045 else
28046 {
28052 }
28056 }
28059 /* Codes for all the SSE/MMX builtins. */
28060 enum ix86_builtins
28061 {
28062 IX86_BUILTIN_ADDPS,
28063 IX86_BUILTIN_ADDSS,
28064 IX86_BUILTIN_DIVPS,
28065 IX86_BUILTIN_DIVSS,
28066 IX86_BUILTIN_MULPS,
28067 IX86_BUILTIN_MULSS,
28068 IX86_BUILTIN_SUBPS,
28069 IX86_BUILTIN_SUBSS,
28071 IX86_BUILTIN_CMPEQPS,
28072 IX86_BUILTIN_CMPLTPS,
28073 IX86_BUILTIN_CMPLEPS,
28074 IX86_BUILTIN_CMPGTPS,
28075 IX86_BUILTIN_CMPGEPS,
28076 IX86_BUILTIN_CMPNEQPS,
28077 IX86_BUILTIN_CMPNLTPS,
28078 IX86_BUILTIN_CMPNLEPS,
28079 IX86_BUILTIN_CMPNGTPS,
28080 IX86_BUILTIN_CMPNGEPS,
28081 IX86_BUILTIN_CMPORDPS,
28082 IX86_BUILTIN_CMPUNORDPS,
28083 IX86_BUILTIN_CMPEQSS,
28084 IX86_BUILTIN_CMPLTSS,
28085 IX86_BUILTIN_CMPLESS,
28086 IX86_BUILTIN_CMPNEQSS,
28087 IX86_BUILTIN_CMPNLTSS,
28088 IX86_BUILTIN_CMPNLESS,
28089 IX86_BUILTIN_CMPORDSS,
28090 IX86_BUILTIN_CMPUNORDSS,
28092 IX86_BUILTIN_COMIEQSS,
28093 IX86_BUILTIN_COMILTSS,
28094 IX86_BUILTIN_COMILESS,
28095 IX86_BUILTIN_COMIGTSS,
28096 IX86_BUILTIN_COMIGESS,
28097 IX86_BUILTIN_COMINEQSS,
28098 IX86_BUILTIN_UCOMIEQSS,
28099 IX86_BUILTIN_UCOMILTSS,
28100 IX86_BUILTIN_UCOMILESS,
28101 IX86_BUILTIN_UCOMIGTSS,
28102 IX86_BUILTIN_UCOMIGESS,
28103 IX86_BUILTIN_UCOMINEQSS,
28105 IX86_BUILTIN_CVTPI2PS,
28106 IX86_BUILTIN_CVTPS2PI,
28107 IX86_BUILTIN_CVTSI2SS,
28108 IX86_BUILTIN_CVTSI642SS,
28109 IX86_BUILTIN_CVTSS2SI,
28110 IX86_BUILTIN_CVTSS2SI64,
28111 IX86_BUILTIN_CVTTPS2PI,
28112 IX86_BUILTIN_CVTTSS2SI,
28113 IX86_BUILTIN_CVTTSS2SI64,
28115 IX86_BUILTIN_MAXPS,
28116 IX86_BUILTIN_MAXSS,
28117 IX86_BUILTIN_MINPS,
28118 IX86_BUILTIN_MINSS,
28120 IX86_BUILTIN_LOADUPS,
28121 IX86_BUILTIN_STOREUPS,
28122 IX86_BUILTIN_MOVSS,
28124 IX86_BUILTIN_MOVHLPS,
28125 IX86_BUILTIN_MOVLHPS,
28126 IX86_BUILTIN_LOADHPS,
28127 IX86_BUILTIN_LOADLPS,
28128 IX86_BUILTIN_STOREHPS,
28129 IX86_BUILTIN_STORELPS,
28131 IX86_BUILTIN_MASKMOVQ,
28132 IX86_BUILTIN_MOVMSKPS,
28133 IX86_BUILTIN_PMOVMSKB,
28135 IX86_BUILTIN_MOVNTPS,
28136 IX86_BUILTIN_MOVNTQ,
28138 IX86_BUILTIN_LOADDQU,
28139 IX86_BUILTIN_STOREDQU,
28141 IX86_BUILTIN_PACKSSWB,
28142 IX86_BUILTIN_PACKSSDW,
28143 IX86_BUILTIN_PACKUSWB,
28145 IX86_BUILTIN_PADDB,
28146 IX86_BUILTIN_PADDW,
28147 IX86_BUILTIN_PADDD,
28148 IX86_BUILTIN_PADDQ,
28149 IX86_BUILTIN_PADDSB,
28150 IX86_BUILTIN_PADDSW,
28151 IX86_BUILTIN_PADDUSB,
28152 IX86_BUILTIN_PADDUSW,
28153 IX86_BUILTIN_PSUBB,
28154 IX86_BUILTIN_PSUBW,
28155 IX86_BUILTIN_PSUBD,
28156 IX86_BUILTIN_PSUBQ,
28157 IX86_BUILTIN_PSUBSB,
28158 IX86_BUILTIN_PSUBSW,
28159 IX86_BUILTIN_PSUBUSB,
28160 IX86_BUILTIN_PSUBUSW,
28162 IX86_BUILTIN_PAND,
28163 IX86_BUILTIN_PANDN,
28164 IX86_BUILTIN_POR,
28165 IX86_BUILTIN_PXOR,
28167 IX86_BUILTIN_PAVGB,
28168 IX86_BUILTIN_PAVGW,
28170 IX86_BUILTIN_PCMPEQB,
28171 IX86_BUILTIN_PCMPEQW,
28172 IX86_BUILTIN_PCMPEQD,
28173 IX86_BUILTIN_PCMPGTB,
28174 IX86_BUILTIN_PCMPGTW,
28175 IX86_BUILTIN_PCMPGTD,
28177 IX86_BUILTIN_PMADDWD,
28179 IX86_BUILTIN_PMAXSW,
28180 IX86_BUILTIN_PMAXUB,
28181 IX86_BUILTIN_PMINSW,
28182 IX86_BUILTIN_PMINUB,
28184 IX86_BUILTIN_PMULHUW,
28185 IX86_BUILTIN_PMULHW,
28186 IX86_BUILTIN_PMULLW,
28188 IX86_BUILTIN_PSADBW,
28189 IX86_BUILTIN_PSHUFW,
28191 IX86_BUILTIN_PSLLW,
28192 IX86_BUILTIN_PSLLD,
28193 IX86_BUILTIN_PSLLQ,
28194 IX86_BUILTIN_PSRAW,
28195 IX86_BUILTIN_PSRAD,
28196 IX86_BUILTIN_PSRLW,
28197 IX86_BUILTIN_PSRLD,
28198 IX86_BUILTIN_PSRLQ,
28199 IX86_BUILTIN_PSLLWI,
28200 IX86_BUILTIN_PSLLDI,
28201 IX86_BUILTIN_PSLLQI,
28202 IX86_BUILTIN_PSRAWI,
28203 IX86_BUILTIN_PSRADI,
28204 IX86_BUILTIN_PSRLWI,
28205 IX86_BUILTIN_PSRLDI,
28206 IX86_BUILTIN_PSRLQI,
28208 IX86_BUILTIN_PUNPCKHBW,
28209 IX86_BUILTIN_PUNPCKHWD,
28210 IX86_BUILTIN_PUNPCKHDQ,
28211 IX86_BUILTIN_PUNPCKLBW,
28212 IX86_BUILTIN_PUNPCKLWD,
28213 IX86_BUILTIN_PUNPCKLDQ,
28215 IX86_BUILTIN_SHUFPS,
28217 IX86_BUILTIN_RCPPS,
28218 IX86_BUILTIN_RCPSS,
28219 IX86_BUILTIN_RSQRTPS,
28220 IX86_BUILTIN_RSQRTPS_NR,
28221 IX86_BUILTIN_RSQRTSS,
28222 IX86_BUILTIN_RSQRTF,
28223 IX86_BUILTIN_SQRTPS,
28224 IX86_BUILTIN_SQRTPS_NR,
28225 IX86_BUILTIN_SQRTSS,
28227 IX86_BUILTIN_UNPCKHPS,
28228 IX86_BUILTIN_UNPCKLPS,
28230 IX86_BUILTIN_ANDPS,
28231 IX86_BUILTIN_ANDNPS,
28232 IX86_BUILTIN_ORPS,
28233 IX86_BUILTIN_XORPS,
28235 IX86_BUILTIN_EMMS,
28236 IX86_BUILTIN_LDMXCSR,
28237 IX86_BUILTIN_STMXCSR,
28238 IX86_BUILTIN_SFENCE,
28240 IX86_BUILTIN_FXSAVE,
28241 IX86_BUILTIN_FXRSTOR,
28242 IX86_BUILTIN_FXSAVE64,
28243 IX86_BUILTIN_FXRSTOR64,
28245 IX86_BUILTIN_XSAVE,
28246 IX86_BUILTIN_XRSTOR,
28247 IX86_BUILTIN_XSAVE64,
28248 IX86_BUILTIN_XRSTOR64,
28250 IX86_BUILTIN_XSAVEOPT,
28251 IX86_BUILTIN_XSAVEOPT64,
28253 IX86_BUILTIN_XSAVEC,
28254 IX86_BUILTIN_XSAVEC64,
28256 IX86_BUILTIN_XSAVES,
28257 IX86_BUILTIN_XRSTORS,
28258 IX86_BUILTIN_XSAVES64,
28259 IX86_BUILTIN_XRSTORS64,
28261 /* 3DNow! Original */
28262 IX86_BUILTIN_FEMMS,
28263 IX86_BUILTIN_PAVGUSB,
28264 IX86_BUILTIN_PF2ID,
28265 IX86_BUILTIN_PFACC,
28266 IX86_BUILTIN_PFADD,
28267 IX86_BUILTIN_PFCMPEQ,
28268 IX86_BUILTIN_PFCMPGE,
28269 IX86_BUILTIN_PFCMPGT,
28270 IX86_BUILTIN_PFMAX,
28271 IX86_BUILTIN_PFMIN,
28272 IX86_BUILTIN_PFMUL,
28273 IX86_BUILTIN_PFRCP,
28274 IX86_BUILTIN_PFRCPIT1,
28275 IX86_BUILTIN_PFRCPIT2,
28276 IX86_BUILTIN_PFRSQIT1,
28277 IX86_BUILTIN_PFRSQRT,
28278 IX86_BUILTIN_PFSUB,
28279 IX86_BUILTIN_PFSUBR,
28280 IX86_BUILTIN_PI2FD,
28281 IX86_BUILTIN_PMULHRW,
28283 /* 3DNow! Athlon Extensions */
28284 IX86_BUILTIN_PF2IW,
28285 IX86_BUILTIN_PFNACC,
28286 IX86_BUILTIN_PFPNACC,
28287 IX86_BUILTIN_PI2FW,
28288 IX86_BUILTIN_PSWAPDSI,
28289 IX86_BUILTIN_PSWAPDSF,
28291 /* SSE2 */
28292 IX86_BUILTIN_ADDPD,
28293 IX86_BUILTIN_ADDSD,
28294 IX86_BUILTIN_DIVPD,
28295 IX86_BUILTIN_DIVSD,
28296 IX86_BUILTIN_MULPD,
28297 IX86_BUILTIN_MULSD,
28298 IX86_BUILTIN_SUBPD,
28299 IX86_BUILTIN_SUBSD,
28301 IX86_BUILTIN_CMPEQPD,
28302 IX86_BUILTIN_CMPLTPD,
28303 IX86_BUILTIN_CMPLEPD,
28304 IX86_BUILTIN_CMPGTPD,
28305 IX86_BUILTIN_CMPGEPD,
28306 IX86_BUILTIN_CMPNEQPD,
28307 IX86_BUILTIN_CMPNLTPD,
28308 IX86_BUILTIN_CMPNLEPD,
28309 IX86_BUILTIN_CMPNGTPD,
28310 IX86_BUILTIN_CMPNGEPD,
28311 IX86_BUILTIN_CMPORDPD,
28312 IX86_BUILTIN_CMPUNORDPD,
28313 IX86_BUILTIN_CMPEQSD,
28314 IX86_BUILTIN_CMPLTSD,
28315 IX86_BUILTIN_CMPLESD,
28316 IX86_BUILTIN_CMPNEQSD,
28317 IX86_BUILTIN_CMPNLTSD,
28318 IX86_BUILTIN_CMPNLESD,
28319 IX86_BUILTIN_CMPORDSD,
28320 IX86_BUILTIN_CMPUNORDSD,
28322 IX86_BUILTIN_COMIEQSD,
28323 IX86_BUILTIN_COMILTSD,
28324 IX86_BUILTIN_COMILESD,
28325 IX86_BUILTIN_COMIGTSD,
28326 IX86_BUILTIN_COMIGESD,
28327 IX86_BUILTIN_COMINEQSD,
28328 IX86_BUILTIN_UCOMIEQSD,
28329 IX86_BUILTIN_UCOMILTSD,
28330 IX86_BUILTIN_UCOMILESD,
28331 IX86_BUILTIN_UCOMIGTSD,
28332 IX86_BUILTIN_UCOMIGESD,
28333 IX86_BUILTIN_UCOMINEQSD,
28335 IX86_BUILTIN_MAXPD,
28336 IX86_BUILTIN_MAXSD,
28337 IX86_BUILTIN_MINPD,
28338 IX86_BUILTIN_MINSD,
28340 IX86_BUILTIN_ANDPD,
28341 IX86_BUILTIN_ANDNPD,
28342 IX86_BUILTIN_ORPD,
28343 IX86_BUILTIN_XORPD,
28345 IX86_BUILTIN_SQRTPD,
28346 IX86_BUILTIN_SQRTSD,
28348 IX86_BUILTIN_UNPCKHPD,
28349 IX86_BUILTIN_UNPCKLPD,
28351 IX86_BUILTIN_SHUFPD,
28353 IX86_BUILTIN_LOADUPD,
28354 IX86_BUILTIN_STOREUPD,
28355 IX86_BUILTIN_MOVSD,
28357 IX86_BUILTIN_LOADHPD,
28358 IX86_BUILTIN_LOADLPD,
28360 IX86_BUILTIN_CVTDQ2PD,
28361 IX86_BUILTIN_CVTDQ2PS,
28363 IX86_BUILTIN_CVTPD2DQ,
28364 IX86_BUILTIN_CVTPD2PI,
28365 IX86_BUILTIN_CVTPD2PS,
28366 IX86_BUILTIN_CVTTPD2DQ,
28367 IX86_BUILTIN_CVTTPD2PI,
28369 IX86_BUILTIN_CVTPI2PD,
28370 IX86_BUILTIN_CVTSI2SD,
28371 IX86_BUILTIN_CVTSI642SD,
28373 IX86_BUILTIN_CVTSD2SI,
28374 IX86_BUILTIN_CVTSD2SI64,
28375 IX86_BUILTIN_CVTSD2SS,
28376 IX86_BUILTIN_CVTSS2SD,
28377 IX86_BUILTIN_CVTTSD2SI,
28378 IX86_BUILTIN_CVTTSD2SI64,
28380 IX86_BUILTIN_CVTPS2DQ,
28381 IX86_BUILTIN_CVTPS2PD,
28382 IX86_BUILTIN_CVTTPS2DQ,
28384 IX86_BUILTIN_MOVNTI,
28385 IX86_BUILTIN_MOVNTI64,
28386 IX86_BUILTIN_MOVNTPD,
28387 IX86_BUILTIN_MOVNTDQ,
28389 IX86_BUILTIN_MOVQ128,
28391 /* SSE2 MMX */
28392 IX86_BUILTIN_MASKMOVDQU,
28393 IX86_BUILTIN_MOVMSKPD,
28394 IX86_BUILTIN_PMOVMSKB128,
28396 IX86_BUILTIN_PACKSSWB128,
28397 IX86_BUILTIN_PACKSSDW128,
28398 IX86_BUILTIN_PACKUSWB128,
28400 IX86_BUILTIN_PADDB128,
28401 IX86_BUILTIN_PADDW128,
28402 IX86_BUILTIN_PADDD128,
28403 IX86_BUILTIN_PADDQ128,
28404 IX86_BUILTIN_PADDSB128,
28405 IX86_BUILTIN_PADDSW128,
28406 IX86_BUILTIN_PADDUSB128,
28407 IX86_BUILTIN_PADDUSW128,
28408 IX86_BUILTIN_PSUBB128,
28409 IX86_BUILTIN_PSUBW128,
28410 IX86_BUILTIN_PSUBD128,
28411 IX86_BUILTIN_PSUBQ128,
28412 IX86_BUILTIN_PSUBSB128,
28413 IX86_BUILTIN_PSUBSW128,
28414 IX86_BUILTIN_PSUBUSB128,
28415 IX86_BUILTIN_PSUBUSW128,
28417 IX86_BUILTIN_PAND128,
28418 IX86_BUILTIN_PANDN128,
28419 IX86_BUILTIN_POR128,
28420 IX86_BUILTIN_PXOR128,
28422 IX86_BUILTIN_PAVGB128,
28423 IX86_BUILTIN_PAVGW128,
28425 IX86_BUILTIN_PCMPEQB128,
28426 IX86_BUILTIN_PCMPEQW128,
28427 IX86_BUILTIN_PCMPEQD128,
28428 IX86_BUILTIN_PCMPGTB128,
28429 IX86_BUILTIN_PCMPGTW128,
28430 IX86_BUILTIN_PCMPGTD128,
28432 IX86_BUILTIN_PMADDWD128,
28434 IX86_BUILTIN_PMAXSW128,
28435 IX86_BUILTIN_PMAXUB128,
28436 IX86_BUILTIN_PMINSW128,
28437 IX86_BUILTIN_PMINUB128,
28439 IX86_BUILTIN_PMULUDQ,
28440 IX86_BUILTIN_PMULUDQ128,
28441 IX86_BUILTIN_PMULHUW128,
28442 IX86_BUILTIN_PMULHW128,
28443 IX86_BUILTIN_PMULLW128,
28445 IX86_BUILTIN_PSADBW128,
28446 IX86_BUILTIN_PSHUFHW,
28447 IX86_BUILTIN_PSHUFLW,
28448 IX86_BUILTIN_PSHUFD,
28450 IX86_BUILTIN_PSLLDQI128,
28451 IX86_BUILTIN_PSLLWI128,
28452 IX86_BUILTIN_PSLLDI128,
28453 IX86_BUILTIN_PSLLQI128,
28454 IX86_BUILTIN_PSRAWI128,
28455 IX86_BUILTIN_PSRADI128,
28456 IX86_BUILTIN_PSRLDQI128,
28457 IX86_BUILTIN_PSRLWI128,
28458 IX86_BUILTIN_PSRLDI128,
28459 IX86_BUILTIN_PSRLQI128,
28461 IX86_BUILTIN_PSLLDQ128,
28462 IX86_BUILTIN_PSLLW128,
28463 IX86_BUILTIN_PSLLD128,
28464 IX86_BUILTIN_PSLLQ128,
28465 IX86_BUILTIN_PSRAW128,
28466 IX86_BUILTIN_PSRAD128,
28467 IX86_BUILTIN_PSRLW128,
28468 IX86_BUILTIN_PSRLD128,
28469 IX86_BUILTIN_PSRLQ128,
28471 IX86_BUILTIN_PUNPCKHBW128,
28472 IX86_BUILTIN_PUNPCKHWD128,
28473 IX86_BUILTIN_PUNPCKHDQ128,
28474 IX86_BUILTIN_PUNPCKHQDQ128,
28475 IX86_BUILTIN_PUNPCKLBW128,
28476 IX86_BUILTIN_PUNPCKLWD128,
28477 IX86_BUILTIN_PUNPCKLDQ128,
28478 IX86_BUILTIN_PUNPCKLQDQ128,
28480 IX86_BUILTIN_CLFLUSH,
28481 IX86_BUILTIN_MFENCE,
28482 IX86_BUILTIN_LFENCE,
28483 IX86_BUILTIN_PAUSE,
28485 IX86_BUILTIN_FNSTENV,
28486 IX86_BUILTIN_FLDENV,
28487 IX86_BUILTIN_FNSTSW,
28488 IX86_BUILTIN_FNCLEX,
28490 IX86_BUILTIN_BSRSI,
28491 IX86_BUILTIN_BSRDI,
28492 IX86_BUILTIN_RDPMC,
28493 IX86_BUILTIN_RDTSC,
28494 IX86_BUILTIN_RDTSCP,
28495 IX86_BUILTIN_ROLQI,
28496 IX86_BUILTIN_ROLHI,
28497 IX86_BUILTIN_RORQI,
28498 IX86_BUILTIN_RORHI,
28500 /* SSE3. */
28501 IX86_BUILTIN_ADDSUBPS,
28502 IX86_BUILTIN_HADDPS,
28503 IX86_BUILTIN_HSUBPS,
28504 IX86_BUILTIN_MOVSHDUP,
28505 IX86_BUILTIN_MOVSLDUP,
28506 IX86_BUILTIN_ADDSUBPD,
28507 IX86_BUILTIN_HADDPD,
28508 IX86_BUILTIN_HSUBPD,
28509 IX86_BUILTIN_LDDQU,
28511 IX86_BUILTIN_MONITOR,
28512 IX86_BUILTIN_MWAIT,
28514 /* SSSE3. */
28515 IX86_BUILTIN_PHADDW,
28516 IX86_BUILTIN_PHADDD,
28517 IX86_BUILTIN_PHADDSW,
28518 IX86_BUILTIN_PHSUBW,
28519 IX86_BUILTIN_PHSUBD,
28520 IX86_BUILTIN_PHSUBSW,
28521 IX86_BUILTIN_PMADDUBSW,
28522 IX86_BUILTIN_PMULHRSW,
28523 IX86_BUILTIN_PSHUFB,
28524 IX86_BUILTIN_PSIGNB,
28525 IX86_BUILTIN_PSIGNW,
28526 IX86_BUILTIN_PSIGND,
28527 IX86_BUILTIN_PALIGNR,
28528 IX86_BUILTIN_PABSB,
28529 IX86_BUILTIN_PABSW,
28530 IX86_BUILTIN_PABSD,
28532 IX86_BUILTIN_PHADDW128,
28533 IX86_BUILTIN_PHADDD128,
28534 IX86_BUILTIN_PHADDSW128,
28535 IX86_BUILTIN_PHSUBW128,
28536 IX86_BUILTIN_PHSUBD128,
28537 IX86_BUILTIN_PHSUBSW128,
28538 IX86_BUILTIN_PMADDUBSW128,
28539 IX86_BUILTIN_PMULHRSW128,
28540 IX86_BUILTIN_PSHUFB128,
28541 IX86_BUILTIN_PSIGNB128,
28542 IX86_BUILTIN_PSIGNW128,
28543 IX86_BUILTIN_PSIGND128,
28544 IX86_BUILTIN_PALIGNR128,
28545 IX86_BUILTIN_PABSB128,
28546 IX86_BUILTIN_PABSW128,
28547 IX86_BUILTIN_PABSD128,
28549 /* AMDFAM10 - SSE4A New Instructions. */
28550 IX86_BUILTIN_MOVNTSD,
28551 IX86_BUILTIN_MOVNTSS,
28552 IX86_BUILTIN_EXTRQI,
28553 IX86_BUILTIN_EXTRQ,
28554 IX86_BUILTIN_INSERTQI,
28555 IX86_BUILTIN_INSERTQ,
28557 /* SSE4.1. */
28558 IX86_BUILTIN_BLENDPD,
28559 IX86_BUILTIN_BLENDPS,
28560 IX86_BUILTIN_BLENDVPD,
28561 IX86_BUILTIN_BLENDVPS,
28562 IX86_BUILTIN_PBLENDVB128,
28563 IX86_BUILTIN_PBLENDW128,
28565 IX86_BUILTIN_DPPD,
28566 IX86_BUILTIN_DPPS,
28568 IX86_BUILTIN_INSERTPS128,
28570 IX86_BUILTIN_MOVNTDQA,
28571 IX86_BUILTIN_MPSADBW128,
28572 IX86_BUILTIN_PACKUSDW128,
28573 IX86_BUILTIN_PCMPEQQ,
28574 IX86_BUILTIN_PHMINPOSUW128,
28576 IX86_BUILTIN_PMAXSB128,
28577 IX86_BUILTIN_PMAXSD128,
28578 IX86_BUILTIN_PMAXUD128,
28579 IX86_BUILTIN_PMAXUW128,
28581 IX86_BUILTIN_PMINSB128,
28582 IX86_BUILTIN_PMINSD128,
28583 IX86_BUILTIN_PMINUD128,
28584 IX86_BUILTIN_PMINUW128,
28586 IX86_BUILTIN_PMOVSXBW128,
28587 IX86_BUILTIN_PMOVSXBD128,
28588 IX86_BUILTIN_PMOVSXBQ128,
28589 IX86_BUILTIN_PMOVSXWD128,
28590 IX86_BUILTIN_PMOVSXWQ128,
28591 IX86_BUILTIN_PMOVSXDQ128,
28593 IX86_BUILTIN_PMOVZXBW128,
28594 IX86_BUILTIN_PMOVZXBD128,
28595 IX86_BUILTIN_PMOVZXBQ128,
28596 IX86_BUILTIN_PMOVZXWD128,
28597 IX86_BUILTIN_PMOVZXWQ128,
28598 IX86_BUILTIN_PMOVZXDQ128,
28600 IX86_BUILTIN_PMULDQ128,
28601 IX86_BUILTIN_PMULLD128,
28603 IX86_BUILTIN_ROUNDSD,
28604 IX86_BUILTIN_ROUNDSS,
28606 IX86_BUILTIN_ROUNDPD,
28607 IX86_BUILTIN_ROUNDPS,
28609 IX86_BUILTIN_FLOORPD,
28610 IX86_BUILTIN_CEILPD,
28611 IX86_BUILTIN_TRUNCPD,
28612 IX86_BUILTIN_RINTPD,
28613 IX86_BUILTIN_ROUNDPD_AZ,
28615 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
28616 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
28617 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
28619 IX86_BUILTIN_FLOORPS,
28620 IX86_BUILTIN_CEILPS,
28621 IX86_BUILTIN_TRUNCPS,
28622 IX86_BUILTIN_RINTPS,
28623 IX86_BUILTIN_ROUNDPS_AZ,
28625 IX86_BUILTIN_FLOORPS_SFIX,
28626 IX86_BUILTIN_CEILPS_SFIX,
28627 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
28629 IX86_BUILTIN_PTESTZ,
28630 IX86_BUILTIN_PTESTC,
28631 IX86_BUILTIN_PTESTNZC,
28633 IX86_BUILTIN_VEC_INIT_V2SI,
28634 IX86_BUILTIN_VEC_INIT_V4HI,
28635 IX86_BUILTIN_VEC_INIT_V8QI,
28636 IX86_BUILTIN_VEC_EXT_V2DF,
28637 IX86_BUILTIN_VEC_EXT_V2DI,
28638 IX86_BUILTIN_VEC_EXT_V4SF,
28639 IX86_BUILTIN_VEC_EXT_V4SI,
28640 IX86_BUILTIN_VEC_EXT_V8HI,
28641 IX86_BUILTIN_VEC_EXT_V2SI,
28642 IX86_BUILTIN_VEC_EXT_V4HI,
28643 IX86_BUILTIN_VEC_EXT_V16QI,
28644 IX86_BUILTIN_VEC_SET_V2DI,
28645 IX86_BUILTIN_VEC_SET_V4SF,
28646 IX86_BUILTIN_VEC_SET_V4SI,
28647 IX86_BUILTIN_VEC_SET_V8HI,
28648 IX86_BUILTIN_VEC_SET_V4HI,
28649 IX86_BUILTIN_VEC_SET_V16QI,
28651 IX86_BUILTIN_VEC_PACK_SFIX,
28652 IX86_BUILTIN_VEC_PACK_SFIX256,
28654 /* SSE4.2. */
28655 IX86_BUILTIN_CRC32QI,
28656 IX86_BUILTIN_CRC32HI,
28657 IX86_BUILTIN_CRC32SI,
28658 IX86_BUILTIN_CRC32DI,
28660 IX86_BUILTIN_PCMPESTRI128,
28661 IX86_BUILTIN_PCMPESTRM128,
28662 IX86_BUILTIN_PCMPESTRA128,
28663 IX86_BUILTIN_PCMPESTRC128,
28664 IX86_BUILTIN_PCMPESTRO128,
28665 IX86_BUILTIN_PCMPESTRS128,
28666 IX86_BUILTIN_PCMPESTRZ128,
28667 IX86_BUILTIN_PCMPISTRI128,
28668 IX86_BUILTIN_PCMPISTRM128,
28669 IX86_BUILTIN_PCMPISTRA128,
28670 IX86_BUILTIN_PCMPISTRC128,
28671 IX86_BUILTIN_PCMPISTRO128,
28672 IX86_BUILTIN_PCMPISTRS128,
28673 IX86_BUILTIN_PCMPISTRZ128,
28675 IX86_BUILTIN_PCMPGTQ,
28677 /* AES instructions */
28678 IX86_BUILTIN_AESENC128,
28679 IX86_BUILTIN_AESENCLAST128,
28680 IX86_BUILTIN_AESDEC128,
28681 IX86_BUILTIN_AESDECLAST128,
28682 IX86_BUILTIN_AESIMC128,
28683 IX86_BUILTIN_AESKEYGENASSIST128,
28685 /* PCLMUL instruction */
28686 IX86_BUILTIN_PCLMULQDQ128,
28688 /* AVX */
28689 IX86_BUILTIN_ADDPD256,
28690 IX86_BUILTIN_ADDPS256,
28691 IX86_BUILTIN_ADDSUBPD256,
28692 IX86_BUILTIN_ADDSUBPS256,
28693 IX86_BUILTIN_ANDPD256,
28694 IX86_BUILTIN_ANDPS256,
28695 IX86_BUILTIN_ANDNPD256,
28696 IX86_BUILTIN_ANDNPS256,
28697 IX86_BUILTIN_BLENDPD256,
28698 IX86_BUILTIN_BLENDPS256,
28699 IX86_BUILTIN_BLENDVPD256,
28700 IX86_BUILTIN_BLENDVPS256,
28701 IX86_BUILTIN_DIVPD256,
28702 IX86_BUILTIN_DIVPS256,
28703 IX86_BUILTIN_DPPS256,
28704 IX86_BUILTIN_HADDPD256,
28705 IX86_BUILTIN_HADDPS256,
28706 IX86_BUILTIN_HSUBPD256,
28707 IX86_BUILTIN_HSUBPS256,
28708 IX86_BUILTIN_MAXPD256,
28709 IX86_BUILTIN_MAXPS256,
28710 IX86_BUILTIN_MINPD256,
28711 IX86_BUILTIN_MINPS256,
28712 IX86_BUILTIN_MULPD256,
28713 IX86_BUILTIN_MULPS256,
28714 IX86_BUILTIN_ORPD256,
28715 IX86_BUILTIN_ORPS256,
28716 IX86_BUILTIN_SHUFPD256,
28717 IX86_BUILTIN_SHUFPS256,
28718 IX86_BUILTIN_SUBPD256,
28719 IX86_BUILTIN_SUBPS256,
28720 IX86_BUILTIN_XORPD256,
28721 IX86_BUILTIN_XORPS256,
28722 IX86_BUILTIN_CMPSD,
28723 IX86_BUILTIN_CMPSS,
28724 IX86_BUILTIN_CMPPD,
28725 IX86_BUILTIN_CMPPS,
28726 IX86_BUILTIN_CMPPD256,
28727 IX86_BUILTIN_CMPPS256,
28728 IX86_BUILTIN_CVTDQ2PD256,
28729 IX86_BUILTIN_CVTDQ2PS256,
28730 IX86_BUILTIN_CVTPD2PS256,
28731 IX86_BUILTIN_CVTPS2DQ256,
28732 IX86_BUILTIN_CVTPS2PD256,
28733 IX86_BUILTIN_CVTTPD2DQ256,
28734 IX86_BUILTIN_CVTPD2DQ256,
28735 IX86_BUILTIN_CVTTPS2DQ256,
28736 IX86_BUILTIN_EXTRACTF128PD256,
28737 IX86_BUILTIN_EXTRACTF128PS256,
28738 IX86_BUILTIN_EXTRACTF128SI256,
28739 IX86_BUILTIN_VZEROALL,
28740 IX86_BUILTIN_VZEROUPPER,
28741 IX86_BUILTIN_VPERMILVARPD,
28742 IX86_BUILTIN_VPERMILVARPS,
28743 IX86_BUILTIN_VPERMILVARPD256,
28744 IX86_BUILTIN_VPERMILVARPS256,
28745 IX86_BUILTIN_VPERMILPD,
28746 IX86_BUILTIN_VPERMILPS,
28747 IX86_BUILTIN_VPERMILPD256,
28748 IX86_BUILTIN_VPERMILPS256,
28749 IX86_BUILTIN_VPERMIL2PD,
28750 IX86_BUILTIN_VPERMIL2PS,
28751 IX86_BUILTIN_VPERMIL2PD256,
28752 IX86_BUILTIN_VPERMIL2PS256,
28753 IX86_BUILTIN_VPERM2F128PD256,
28754 IX86_BUILTIN_VPERM2F128PS256,
28755 IX86_BUILTIN_VPERM2F128SI256,
28756 IX86_BUILTIN_VBROADCASTSS,
28757 IX86_BUILTIN_VBROADCASTSD256,
28758 IX86_BUILTIN_VBROADCASTSS256,
28759 IX86_BUILTIN_VBROADCASTPD256,
28760 IX86_BUILTIN_VBROADCASTPS256,
28761 IX86_BUILTIN_VINSERTF128PD256,
28762 IX86_BUILTIN_VINSERTF128PS256,
28763 IX86_BUILTIN_VINSERTF128SI256,
28764 IX86_BUILTIN_LOADUPD256,
28765 IX86_BUILTIN_LOADUPS256,
28766 IX86_BUILTIN_STOREUPD256,
28767 IX86_BUILTIN_STOREUPS256,
28768 IX86_BUILTIN_LDDQU256,
28769 IX86_BUILTIN_MOVNTDQ256,
28770 IX86_BUILTIN_MOVNTPD256,
28771 IX86_BUILTIN_MOVNTPS256,
28772 IX86_BUILTIN_LOADDQU256,
28773 IX86_BUILTIN_STOREDQU256,
28774 IX86_BUILTIN_MASKLOADPD,
28775 IX86_BUILTIN_MASKLOADPS,
28776 IX86_BUILTIN_MASKSTOREPD,
28777 IX86_BUILTIN_MASKSTOREPS,
28778 IX86_BUILTIN_MASKLOADPD256,
28779 IX86_BUILTIN_MASKLOADPS256,
28780 IX86_BUILTIN_MASKSTOREPD256,
28781 IX86_BUILTIN_MASKSTOREPS256,
28782 IX86_BUILTIN_MOVSHDUP256,
28783 IX86_BUILTIN_MOVSLDUP256,
28784 IX86_BUILTIN_MOVDDUP256,
28786 IX86_BUILTIN_SQRTPD256,
28787 IX86_BUILTIN_SQRTPS256,
28788 IX86_BUILTIN_SQRTPS_NR256,
28789 IX86_BUILTIN_RSQRTPS256,
28790 IX86_BUILTIN_RSQRTPS_NR256,
28792 IX86_BUILTIN_RCPPS256,
28794 IX86_BUILTIN_ROUNDPD256,
28795 IX86_BUILTIN_ROUNDPS256,
28797 IX86_BUILTIN_FLOORPD256,
28798 IX86_BUILTIN_CEILPD256,
28799 IX86_BUILTIN_TRUNCPD256,
28800 IX86_BUILTIN_RINTPD256,
28801 IX86_BUILTIN_ROUNDPD_AZ256,
28803 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
28804 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
28805 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
28807 IX86_BUILTIN_FLOORPS256,
28808 IX86_BUILTIN_CEILPS256,
28809 IX86_BUILTIN_TRUNCPS256,
28810 IX86_BUILTIN_RINTPS256,
28811 IX86_BUILTIN_ROUNDPS_AZ256,
28813 IX86_BUILTIN_FLOORPS_SFIX256,
28814 IX86_BUILTIN_CEILPS_SFIX256,
28815 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
28817 IX86_BUILTIN_UNPCKHPD256,
28818 IX86_BUILTIN_UNPCKLPD256,
28819 IX86_BUILTIN_UNPCKHPS256,
28820 IX86_BUILTIN_UNPCKLPS256,
28822 IX86_BUILTIN_SI256_SI,
28823 IX86_BUILTIN_PS256_PS,
28824 IX86_BUILTIN_PD256_PD,
28825 IX86_BUILTIN_SI_SI256,
28826 IX86_BUILTIN_PS_PS256,
28827 IX86_BUILTIN_PD_PD256,
28829 IX86_BUILTIN_VTESTZPD,
28830 IX86_BUILTIN_VTESTCPD,
28831 IX86_BUILTIN_VTESTNZCPD,
28832 IX86_BUILTIN_VTESTZPS,
28833 IX86_BUILTIN_VTESTCPS,
28834 IX86_BUILTIN_VTESTNZCPS,
28835 IX86_BUILTIN_VTESTZPD256,
28836 IX86_BUILTIN_VTESTCPD256,
28837 IX86_BUILTIN_VTESTNZCPD256,
28838 IX86_BUILTIN_VTESTZPS256,
28839 IX86_BUILTIN_VTESTCPS256,
28840 IX86_BUILTIN_VTESTNZCPS256,
28841 IX86_BUILTIN_PTESTZ256,
28842 IX86_BUILTIN_PTESTC256,
28843 IX86_BUILTIN_PTESTNZC256,
28845 IX86_BUILTIN_MOVMSKPD256,
28846 IX86_BUILTIN_MOVMSKPS256,
28848 /* AVX2 */
28849 IX86_BUILTIN_MPSADBW256,
28850 IX86_BUILTIN_PABSB256,
28851 IX86_BUILTIN_PABSW256,
28852 IX86_BUILTIN_PABSD256,
28853 IX86_BUILTIN_PACKSSDW256,
28854 IX86_BUILTIN_PACKSSWB256,
28855 IX86_BUILTIN_PACKUSDW256,
28856 IX86_BUILTIN_PACKUSWB256,
28857 IX86_BUILTIN_PADDB256,
28858 IX86_BUILTIN_PADDW256,
28859 IX86_BUILTIN_PADDD256,
28860 IX86_BUILTIN_PADDQ256,
28861 IX86_BUILTIN_PADDSB256,
28862 IX86_BUILTIN_PADDSW256,
28863 IX86_BUILTIN_PADDUSB256,
28864 IX86_BUILTIN_PADDUSW256,
28865 IX86_BUILTIN_PALIGNR256,
28866 IX86_BUILTIN_AND256I,
28867 IX86_BUILTIN_ANDNOT256I,
28868 IX86_BUILTIN_PAVGB256,
28869 IX86_BUILTIN_PAVGW256,
28870 IX86_BUILTIN_PBLENDVB256,
28871 IX86_BUILTIN_PBLENDVW256,
28872 IX86_BUILTIN_PCMPEQB256,
28873 IX86_BUILTIN_PCMPEQW256,
28874 IX86_BUILTIN_PCMPEQD256,
28875 IX86_BUILTIN_PCMPEQQ256,
28876 IX86_BUILTIN_PCMPGTB256,
28877 IX86_BUILTIN_PCMPGTW256,
28878 IX86_BUILTIN_PCMPGTD256,
28879 IX86_BUILTIN_PCMPGTQ256,
28880 IX86_BUILTIN_PHADDW256,
28881 IX86_BUILTIN_PHADDD256,
28882 IX86_BUILTIN_PHADDSW256,
28883 IX86_BUILTIN_PHSUBW256,
28884 IX86_BUILTIN_PHSUBD256,
28885 IX86_BUILTIN_PHSUBSW256,
28886 IX86_BUILTIN_PMADDUBSW256,
28887 IX86_BUILTIN_PMADDWD256,
28888 IX86_BUILTIN_PMAXSB256,
28889 IX86_BUILTIN_PMAXSW256,
28890 IX86_BUILTIN_PMAXSD256,
28891 IX86_BUILTIN_PMAXUB256,
28892 IX86_BUILTIN_PMAXUW256,
28893 IX86_BUILTIN_PMAXUD256,
28894 IX86_BUILTIN_PMINSB256,
28895 IX86_BUILTIN_PMINSW256,
28896 IX86_BUILTIN_PMINSD256,
28897 IX86_BUILTIN_PMINUB256,
28898 IX86_BUILTIN_PMINUW256,
28899 IX86_BUILTIN_PMINUD256,
28900 IX86_BUILTIN_PMOVMSKB256,
28901 IX86_BUILTIN_PMOVSXBW256,
28902 IX86_BUILTIN_PMOVSXBD256,
28903 IX86_BUILTIN_PMOVSXBQ256,
28904 IX86_BUILTIN_PMOVSXWD256,
28905 IX86_BUILTIN_PMOVSXWQ256,
28906 IX86_BUILTIN_PMOVSXDQ256,
28907 IX86_BUILTIN_PMOVZXBW256,
28908 IX86_BUILTIN_PMOVZXBD256,
28909 IX86_BUILTIN_PMOVZXBQ256,
28910 IX86_BUILTIN_PMOVZXWD256,
28911 IX86_BUILTIN_PMOVZXWQ256,
28912 IX86_BUILTIN_PMOVZXDQ256,
28913 IX86_BUILTIN_PMULDQ256,
28914 IX86_BUILTIN_PMULHRSW256,
28915 IX86_BUILTIN_PMULHUW256,
28916 IX86_BUILTIN_PMULHW256,
28917 IX86_BUILTIN_PMULLW256,
28918 IX86_BUILTIN_PMULLD256,
28919 IX86_BUILTIN_PMULUDQ256,
28920 IX86_BUILTIN_POR256,
28921 IX86_BUILTIN_PSADBW256,
28922 IX86_BUILTIN_PSHUFB256,
28923 IX86_BUILTIN_PSHUFD256,
28924 IX86_BUILTIN_PSHUFHW256,
28925 IX86_BUILTIN_PSHUFLW256,
28926 IX86_BUILTIN_PSIGNB256,
28927 IX86_BUILTIN_PSIGNW256,
28928 IX86_BUILTIN_PSIGND256,
28929 IX86_BUILTIN_PSLLDQI256,
28930 IX86_BUILTIN_PSLLWI256,
28931 IX86_BUILTIN_PSLLW256,
28932 IX86_BUILTIN_PSLLDI256,
28933 IX86_BUILTIN_PSLLD256,
28934 IX86_BUILTIN_PSLLQI256,
28935 IX86_BUILTIN_PSLLQ256,
28936 IX86_BUILTIN_PSRAWI256,
28937 IX86_BUILTIN_PSRAW256,
28938 IX86_BUILTIN_PSRADI256,
28939 IX86_BUILTIN_PSRAD256,
28940 IX86_BUILTIN_PSRLDQI256,
28941 IX86_BUILTIN_PSRLWI256,
28942 IX86_BUILTIN_PSRLW256,
28943 IX86_BUILTIN_PSRLDI256,
28944 IX86_BUILTIN_PSRLD256,
28945 IX86_BUILTIN_PSRLQI256,
28946 IX86_BUILTIN_PSRLQ256,
28947 IX86_BUILTIN_PSUBB256,
28948 IX86_BUILTIN_PSUBW256,
28949 IX86_BUILTIN_PSUBD256,
28950 IX86_BUILTIN_PSUBQ256,
28951 IX86_BUILTIN_PSUBSB256,
28952 IX86_BUILTIN_PSUBSW256,
28953 IX86_BUILTIN_PSUBUSB256,
28954 IX86_BUILTIN_PSUBUSW256,
28955 IX86_BUILTIN_PUNPCKHBW256,
28956 IX86_BUILTIN_PUNPCKHWD256,
28957 IX86_BUILTIN_PUNPCKHDQ256,
28958 IX86_BUILTIN_PUNPCKHQDQ256,
28959 IX86_BUILTIN_PUNPCKLBW256,
28960 IX86_BUILTIN_PUNPCKLWD256,
28961 IX86_BUILTIN_PUNPCKLDQ256,
28962 IX86_BUILTIN_PUNPCKLQDQ256,
28963 IX86_BUILTIN_PXOR256,
28964 IX86_BUILTIN_MOVNTDQA256,
28965 IX86_BUILTIN_VBROADCASTSS_PS,
28966 IX86_BUILTIN_VBROADCASTSS_PS256,
28967 IX86_BUILTIN_VBROADCASTSD_PD256,
28968 IX86_BUILTIN_VBROADCASTSI256,
28969 IX86_BUILTIN_PBLENDD256,
28970 IX86_BUILTIN_PBLENDD128,
28971 IX86_BUILTIN_PBROADCASTB256,
28972 IX86_BUILTIN_PBROADCASTW256,
28973 IX86_BUILTIN_PBROADCASTD256,
28974 IX86_BUILTIN_PBROADCASTQ256,
28975 IX86_BUILTIN_PBROADCASTB128,
28976 IX86_BUILTIN_PBROADCASTW128,
28977 IX86_BUILTIN_PBROADCASTD128,
28978 IX86_BUILTIN_PBROADCASTQ128,
28979 IX86_BUILTIN_VPERMVARSI256,
28980 IX86_BUILTIN_VPERMDF256,
28981 IX86_BUILTIN_VPERMVARSF256,
28982 IX86_BUILTIN_VPERMDI256,
28983 IX86_BUILTIN_VPERMTI256,
28984 IX86_BUILTIN_VEXTRACT128I256,
28985 IX86_BUILTIN_VINSERT128I256,
28986 IX86_BUILTIN_MASKLOADD,
28987 IX86_BUILTIN_MASKLOADQ,
28988 IX86_BUILTIN_MASKLOADD256,
28989 IX86_BUILTIN_MASKLOADQ256,
28990 IX86_BUILTIN_MASKSTORED,
28991 IX86_BUILTIN_MASKSTOREQ,
28992 IX86_BUILTIN_MASKSTORED256,
28993 IX86_BUILTIN_MASKSTOREQ256,
28994 IX86_BUILTIN_PSLLVV4DI,
28995 IX86_BUILTIN_PSLLVV2DI,
28996 IX86_BUILTIN_PSLLVV8SI,
28997 IX86_BUILTIN_PSLLVV4SI,
28998 IX86_BUILTIN_PSRAVV8SI,
28999 IX86_BUILTIN_PSRAVV4SI,
29000 IX86_BUILTIN_PSRLVV4DI,
29001 IX86_BUILTIN_PSRLVV2DI,
29002 IX86_BUILTIN_PSRLVV8SI,
29003 IX86_BUILTIN_PSRLVV4SI,
29005 IX86_BUILTIN_GATHERSIV2DF,
29006 IX86_BUILTIN_GATHERSIV4DF,
29007 IX86_BUILTIN_GATHERDIV2DF,
29008 IX86_BUILTIN_GATHERDIV4DF,
29009 IX86_BUILTIN_GATHERSIV4SF,
29010 IX86_BUILTIN_GATHERSIV8SF,
29011 IX86_BUILTIN_GATHERDIV4SF,
29012 IX86_BUILTIN_GATHERDIV8SF,
29013 IX86_BUILTIN_GATHERSIV2DI,
29014 IX86_BUILTIN_GATHERSIV4DI,
29015 IX86_BUILTIN_GATHERDIV2DI,
29016 IX86_BUILTIN_GATHERDIV4DI,
29017 IX86_BUILTIN_GATHERSIV4SI,
29018 IX86_BUILTIN_GATHERSIV8SI,
29019 IX86_BUILTIN_GATHERDIV4SI,
29020 IX86_BUILTIN_GATHERDIV8SI,
29022 /* AVX512F */
29023 IX86_BUILTIN_SI512_SI256,
29024 IX86_BUILTIN_PD512_PD256,
29025 IX86_BUILTIN_PS512_PS256,
29026 IX86_BUILTIN_SI512_SI,
29027 IX86_BUILTIN_PD512_PD,
29028 IX86_BUILTIN_PS512_PS,
29029 IX86_BUILTIN_ADDPD512,
29030 IX86_BUILTIN_ADDPS512,
29031 IX86_BUILTIN_ADDSD_ROUND,
29032 IX86_BUILTIN_ADDSS_ROUND,
29033 IX86_BUILTIN_ALIGND512,
29034 IX86_BUILTIN_ALIGNQ512,
29035 IX86_BUILTIN_BLENDMD512,
29036 IX86_BUILTIN_BLENDMPD512,
29037 IX86_BUILTIN_BLENDMPS512,
29038 IX86_BUILTIN_BLENDMQ512,
29039 IX86_BUILTIN_BROADCASTF32X4_512,
29040 IX86_BUILTIN_BROADCASTF64X4_512,
29041 IX86_BUILTIN_BROADCASTI32X4_512,
29042 IX86_BUILTIN_BROADCASTI64X4_512,
29043 IX86_BUILTIN_BROADCASTSD512,
29044 IX86_BUILTIN_BROADCASTSS512,
29045 IX86_BUILTIN_CMPD512,
29046 IX86_BUILTIN_CMPPD512,
29047 IX86_BUILTIN_CMPPS512,
29048 IX86_BUILTIN_CMPQ512,
29049 IX86_BUILTIN_CMPSD_MASK,
29050 IX86_BUILTIN_CMPSS_MASK,
29051 IX86_BUILTIN_COMIDF,
29052 IX86_BUILTIN_COMISF,
29053 IX86_BUILTIN_COMPRESSPD512,
29054 IX86_BUILTIN_COMPRESSPDSTORE512,
29055 IX86_BUILTIN_COMPRESSPS512,
29056 IX86_BUILTIN_COMPRESSPSSTORE512,
29057 IX86_BUILTIN_CVTDQ2PD512,
29058 IX86_BUILTIN_CVTDQ2PS512,
29059 IX86_BUILTIN_CVTPD2DQ512,
29060 IX86_BUILTIN_CVTPD2PS512,
29061 IX86_BUILTIN_CVTPD2UDQ512,
29062 IX86_BUILTIN_CVTPH2PS512,
29063 IX86_BUILTIN_CVTPS2DQ512,
29064 IX86_BUILTIN_CVTPS2PD512,
29065 IX86_BUILTIN_CVTPS2PH512,
29066 IX86_BUILTIN_CVTPS2UDQ512,
29067 IX86_BUILTIN_CVTSD2SS_ROUND,
29068 IX86_BUILTIN_CVTSI2SD64,
29069 IX86_BUILTIN_CVTSI2SS32,
29070 IX86_BUILTIN_CVTSI2SS64,
29071 IX86_BUILTIN_CVTSS2SD_ROUND,
29072 IX86_BUILTIN_CVTTPD2DQ512,
29073 IX86_BUILTIN_CVTTPD2UDQ512,
29074 IX86_BUILTIN_CVTTPS2DQ512,
29075 IX86_BUILTIN_CVTTPS2UDQ512,
29076 IX86_BUILTIN_CVTUDQ2PD512,
29077 IX86_BUILTIN_CVTUDQ2PS512,
29078 IX86_BUILTIN_CVTUSI2SD32,
29079 IX86_BUILTIN_CVTUSI2SD64,
29080 IX86_BUILTIN_CVTUSI2SS32,
29081 IX86_BUILTIN_CVTUSI2SS64,
29082 IX86_BUILTIN_DIVPD512,
29083 IX86_BUILTIN_DIVPS512,
29084 IX86_BUILTIN_DIVSD_ROUND,
29085 IX86_BUILTIN_DIVSS_ROUND,
29086 IX86_BUILTIN_EXPANDPD512,
29087 IX86_BUILTIN_EXPANDPD512Z,
29088 IX86_BUILTIN_EXPANDPDLOAD512,
29089 IX86_BUILTIN_EXPANDPDLOAD512Z,
29090 IX86_BUILTIN_EXPANDPS512,
29091 IX86_BUILTIN_EXPANDPS512Z,
29092 IX86_BUILTIN_EXPANDPSLOAD512,
29093 IX86_BUILTIN_EXPANDPSLOAD512Z,
29094 IX86_BUILTIN_EXTRACTF32X4,
29095 IX86_BUILTIN_EXTRACTF64X4,
29096 IX86_BUILTIN_EXTRACTI32X4,
29097 IX86_BUILTIN_EXTRACTI64X4,
29098 IX86_BUILTIN_FIXUPIMMPD512_MASK,
29099 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
29100 IX86_BUILTIN_FIXUPIMMPS512_MASK,
29101 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
29102 IX86_BUILTIN_FIXUPIMMSD128_MASK,
29103 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
29104 IX86_BUILTIN_FIXUPIMMSS128_MASK,
29105 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
29106 IX86_BUILTIN_GETEXPPD512,
29107 IX86_BUILTIN_GETEXPPS512,
29108 IX86_BUILTIN_GETEXPSD128,
29109 IX86_BUILTIN_GETEXPSS128,
29110 IX86_BUILTIN_GETMANTPD512,
29111 IX86_BUILTIN_GETMANTPS512,
29112 IX86_BUILTIN_GETMANTSD128,
29113 IX86_BUILTIN_GETMANTSS128,
29114 IX86_BUILTIN_INSERTF32X4,
29115 IX86_BUILTIN_INSERTF64X4,
29116 IX86_BUILTIN_INSERTI32X4,
29117 IX86_BUILTIN_INSERTI64X4,
29118 IX86_BUILTIN_LOADAPD512,
29119 IX86_BUILTIN_LOADAPS512,
29120 IX86_BUILTIN_LOADDQUDI512,
29121 IX86_BUILTIN_LOADDQUSI512,
29122 IX86_BUILTIN_LOADUPD512,
29123 IX86_BUILTIN_LOADUPS512,
29124 IX86_BUILTIN_MAXPD512,
29125 IX86_BUILTIN_MAXPS512,
29126 IX86_BUILTIN_MAXSD_ROUND,
29127 IX86_BUILTIN_MAXSS_ROUND,
29128 IX86_BUILTIN_MINPD512,
29129 IX86_BUILTIN_MINPS512,
29130 IX86_BUILTIN_MINSD_ROUND,
29131 IX86_BUILTIN_MINSS_ROUND,
29132 IX86_BUILTIN_MOVAPD512,
29133 IX86_BUILTIN_MOVAPS512,
29134 IX86_BUILTIN_MOVDDUP512,
29135 IX86_BUILTIN_MOVDQA32LOAD512,
29136 IX86_BUILTIN_MOVDQA32STORE512,
29137 IX86_BUILTIN_MOVDQA32_512,
29138 IX86_BUILTIN_MOVDQA64LOAD512,
29139 IX86_BUILTIN_MOVDQA64STORE512,
29140 IX86_BUILTIN_MOVDQA64_512,
29141 IX86_BUILTIN_MOVNTDQ512,
29142 IX86_BUILTIN_MOVNTDQA512,
29143 IX86_BUILTIN_MOVNTPD512,
29144 IX86_BUILTIN_MOVNTPS512,
29145 IX86_BUILTIN_MOVSHDUP512,
29146 IX86_BUILTIN_MOVSLDUP512,
29147 IX86_BUILTIN_MULPD512,
29148 IX86_BUILTIN_MULPS512,
29149 IX86_BUILTIN_MULSD_ROUND,
29150 IX86_BUILTIN_MULSS_ROUND,
29151 IX86_BUILTIN_PABSD512,
29152 IX86_BUILTIN_PABSQ512,
29153 IX86_BUILTIN_PADDD512,
29154 IX86_BUILTIN_PADDQ512,
29155 IX86_BUILTIN_PANDD512,
29156 IX86_BUILTIN_PANDND512,
29157 IX86_BUILTIN_PANDNQ512,
29158 IX86_BUILTIN_PANDQ512,
29159 IX86_BUILTIN_PBROADCASTD512,
29160 IX86_BUILTIN_PBROADCASTD512_GPR,
29161 IX86_BUILTIN_PBROADCASTMB512,
29162 IX86_BUILTIN_PBROADCASTMW512,
29163 IX86_BUILTIN_PBROADCASTQ512,
29164 IX86_BUILTIN_PBROADCASTQ512_GPR,
29165 IX86_BUILTIN_PCMPEQD512_MASK,
29166 IX86_BUILTIN_PCMPEQQ512_MASK,
29167 IX86_BUILTIN_PCMPGTD512_MASK,
29168 IX86_BUILTIN_PCMPGTQ512_MASK,
29169 IX86_BUILTIN_PCOMPRESSD512,
29170 IX86_BUILTIN_PCOMPRESSDSTORE512,
29171 IX86_BUILTIN_PCOMPRESSQ512,
29172 IX86_BUILTIN_PCOMPRESSQSTORE512,
29173 IX86_BUILTIN_PEXPANDD512,
29174 IX86_BUILTIN_PEXPANDD512Z,
29175 IX86_BUILTIN_PEXPANDDLOAD512,
29176 IX86_BUILTIN_PEXPANDDLOAD512Z,
29177 IX86_BUILTIN_PEXPANDQ512,
29178 IX86_BUILTIN_PEXPANDQ512Z,
29179 IX86_BUILTIN_PEXPANDQLOAD512,
29180 IX86_BUILTIN_PEXPANDQLOAD512Z,
29181 IX86_BUILTIN_PMAXSD512,
29182 IX86_BUILTIN_PMAXSQ512,
29183 IX86_BUILTIN_PMAXUD512,
29184 IX86_BUILTIN_PMAXUQ512,
29185 IX86_BUILTIN_PMINSD512,
29186 IX86_BUILTIN_PMINSQ512,
29187 IX86_BUILTIN_PMINUD512,
29188 IX86_BUILTIN_PMINUQ512,
29189 IX86_BUILTIN_PMOVDB512,
29190 IX86_BUILTIN_PMOVDB512_MEM,
29191 IX86_BUILTIN_PMOVDW512,
29192 IX86_BUILTIN_PMOVDW512_MEM,
29193 IX86_BUILTIN_PMOVQB512,
29194 IX86_BUILTIN_PMOVQB512_MEM,
29195 IX86_BUILTIN_PMOVQD512,
29196 IX86_BUILTIN_PMOVQD512_MEM,
29197 IX86_BUILTIN_PMOVQW512,
29198 IX86_BUILTIN_PMOVQW512_MEM,
29199 IX86_BUILTIN_PMOVSDB512,
29200 IX86_BUILTIN_PMOVSDB512_MEM,
29201 IX86_BUILTIN_PMOVSDW512,
29202 IX86_BUILTIN_PMOVSDW512_MEM,
29203 IX86_BUILTIN_PMOVSQB512,
29204 IX86_BUILTIN_PMOVSQB512_MEM,
29205 IX86_BUILTIN_PMOVSQD512,
29206 IX86_BUILTIN_PMOVSQD512_MEM,
29207 IX86_BUILTIN_PMOVSQW512,
29208 IX86_BUILTIN_PMOVSQW512_MEM,
29209 IX86_BUILTIN_PMOVSXBD512,
29210 IX86_BUILTIN_PMOVSXBQ512,
29211 IX86_BUILTIN_PMOVSXDQ512,
29212 IX86_BUILTIN_PMOVSXWD512,
29213 IX86_BUILTIN_PMOVSXWQ512,
29214 IX86_BUILTIN_PMOVUSDB512,
29215 IX86_BUILTIN_PMOVUSDB512_MEM,
29216 IX86_BUILTIN_PMOVUSDW512,
29217 IX86_BUILTIN_PMOVUSDW512_MEM,
29218 IX86_BUILTIN_PMOVUSQB512,
29219 IX86_BUILTIN_PMOVUSQB512_MEM,
29220 IX86_BUILTIN_PMOVUSQD512,
29221 IX86_BUILTIN_PMOVUSQD512_MEM,
29222 IX86_BUILTIN_PMOVUSQW512,
29223 IX86_BUILTIN_PMOVUSQW512_MEM,
29224 IX86_BUILTIN_PMOVZXBD512,
29225 IX86_BUILTIN_PMOVZXBQ512,
29226 IX86_BUILTIN_PMOVZXDQ512,
29227 IX86_BUILTIN_PMOVZXWD512,
29228 IX86_BUILTIN_PMOVZXWQ512,
29229 IX86_BUILTIN_PMULDQ512,
29230 IX86_BUILTIN_PMULLD512,
29231 IX86_BUILTIN_PMULUDQ512,
29232 IX86_BUILTIN_PORD512,
29233 IX86_BUILTIN_PORQ512,
29234 IX86_BUILTIN_PROLD512,
29235 IX86_BUILTIN_PROLQ512,
29236 IX86_BUILTIN_PROLVD512,
29237 IX86_BUILTIN_PROLVQ512,
29238 IX86_BUILTIN_PRORD512,
29239 IX86_BUILTIN_PRORQ512,
29240 IX86_BUILTIN_PRORVD512,
29241 IX86_BUILTIN_PRORVQ512,
29242 IX86_BUILTIN_PSHUFD512,
29243 IX86_BUILTIN_PSLLD512,
29244 IX86_BUILTIN_PSLLDI512,
29245 IX86_BUILTIN_PSLLQ512,
29246 IX86_BUILTIN_PSLLQI512,
29247 IX86_BUILTIN_PSLLVV16SI,
29248 IX86_BUILTIN_PSLLVV8DI,
29249 IX86_BUILTIN_PSRAD512,
29250 IX86_BUILTIN_PSRADI512,
29251 IX86_BUILTIN_PSRAQ512,
29252 IX86_BUILTIN_PSRAQI512,
29253 IX86_BUILTIN_PSRAVV16SI,
29254 IX86_BUILTIN_PSRAVV8DI,
29255 IX86_BUILTIN_PSRLD512,
29256 IX86_BUILTIN_PSRLDI512,
29257 IX86_BUILTIN_PSRLQ512,
29258 IX86_BUILTIN_PSRLQI512,
29259 IX86_BUILTIN_PSRLVV16SI,
29260 IX86_BUILTIN_PSRLVV8DI,
29261 IX86_BUILTIN_PSUBD512,
29262 IX86_BUILTIN_PSUBQ512,
29263 IX86_BUILTIN_PTESTMD512,
29264 IX86_BUILTIN_PTESTMQ512,
29265 IX86_BUILTIN_PTESTNMD512,
29266 IX86_BUILTIN_PTESTNMQ512,
29267 IX86_BUILTIN_PUNPCKHDQ512,
29268 IX86_BUILTIN_PUNPCKHQDQ512,
29269 IX86_BUILTIN_PUNPCKLDQ512,
29270 IX86_BUILTIN_PUNPCKLQDQ512,
29271 IX86_BUILTIN_PXORD512,
29272 IX86_BUILTIN_PXORQ512,
29273 IX86_BUILTIN_RCP14PD512,
29274 IX86_BUILTIN_RCP14PS512,
29275 IX86_BUILTIN_RCP14SD,
29276 IX86_BUILTIN_RCP14SS,
29277 IX86_BUILTIN_RNDSCALEPD,
29278 IX86_BUILTIN_RNDSCALEPS,
29279 IX86_BUILTIN_RNDSCALESD,
29280 IX86_BUILTIN_RNDSCALESS,
29281 IX86_BUILTIN_RSQRT14PD512,
29282 IX86_BUILTIN_RSQRT14PS512,
29283 IX86_BUILTIN_RSQRT14SD,
29284 IX86_BUILTIN_RSQRT14SS,
29285 IX86_BUILTIN_SCALEFPD512,
29286 IX86_BUILTIN_SCALEFPS512,
29287 IX86_BUILTIN_SCALEFSD,
29288 IX86_BUILTIN_SCALEFSS,
29289 IX86_BUILTIN_SHUFPD512,
29290 IX86_BUILTIN_SHUFPS512,
29291 IX86_BUILTIN_SHUF_F32x4,
29292 IX86_BUILTIN_SHUF_F64x2,
29293 IX86_BUILTIN_SHUF_I32x4,
29294 IX86_BUILTIN_SHUF_I64x2,
29295 IX86_BUILTIN_SQRTPD512,
29296 IX86_BUILTIN_SQRTPD512_MASK,
29297 IX86_BUILTIN_SQRTPS512_MASK,
29298 IX86_BUILTIN_SQRTPS_NR512,
29299 IX86_BUILTIN_SQRTSD_ROUND,
29300 IX86_BUILTIN_SQRTSS_ROUND,
29301 IX86_BUILTIN_STOREAPD512,
29302 IX86_BUILTIN_STOREAPS512,
29303 IX86_BUILTIN_STOREDQUDI512,
29304 IX86_BUILTIN_STOREDQUSI512,
29305 IX86_BUILTIN_STOREUPD512,
29306 IX86_BUILTIN_STOREUPS512,
29307 IX86_BUILTIN_SUBPD512,
29308 IX86_BUILTIN_SUBPS512,
29309 IX86_BUILTIN_SUBSD_ROUND,
29310 IX86_BUILTIN_SUBSS_ROUND,
29311 IX86_BUILTIN_UCMPD512,
29312 IX86_BUILTIN_UCMPQ512,
29313 IX86_BUILTIN_UNPCKHPD512,
29314 IX86_BUILTIN_UNPCKHPS512,
29315 IX86_BUILTIN_UNPCKLPD512,
29316 IX86_BUILTIN_UNPCKLPS512,
29317 IX86_BUILTIN_VCVTSD2SI32,
29318 IX86_BUILTIN_VCVTSD2SI64,
29319 IX86_BUILTIN_VCVTSD2USI32,
29320 IX86_BUILTIN_VCVTSD2USI64,
29321 IX86_BUILTIN_VCVTSS2SI32,
29322 IX86_BUILTIN_VCVTSS2SI64,
29323 IX86_BUILTIN_VCVTSS2USI32,
29324 IX86_BUILTIN_VCVTSS2USI64,
29325 IX86_BUILTIN_VCVTTSD2SI32,
29326 IX86_BUILTIN_VCVTTSD2SI64,
29327 IX86_BUILTIN_VCVTTSD2USI32,
29328 IX86_BUILTIN_VCVTTSD2USI64,
29329 IX86_BUILTIN_VCVTTSS2SI32,
29330 IX86_BUILTIN_VCVTTSS2SI64,
29331 IX86_BUILTIN_VCVTTSS2USI32,
29332 IX86_BUILTIN_VCVTTSS2USI64,
29333 IX86_BUILTIN_VFMADDPD512_MASK,
29334 IX86_BUILTIN_VFMADDPD512_MASK3,
29335 IX86_BUILTIN_VFMADDPD512_MASKZ,
29336 IX86_BUILTIN_VFMADDPS512_MASK,
29337 IX86_BUILTIN_VFMADDPS512_MASK3,
29338 IX86_BUILTIN_VFMADDPS512_MASKZ,
29339 IX86_BUILTIN_VFMADDSD3_ROUND,
29340 IX86_BUILTIN_VFMADDSS3_ROUND,
29341 IX86_BUILTIN_VFMADDSUBPD512_MASK,
29342 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
29343 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
29344 IX86_BUILTIN_VFMADDSUBPS512_MASK,
29345 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
29346 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
29347 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
29348 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
29349 IX86_BUILTIN_VFMSUBPD512_MASK3,
29350 IX86_BUILTIN_VFMSUBPS512_MASK3,
29351 IX86_BUILTIN_VFMSUBSD3_MASK3,
29352 IX86_BUILTIN_VFMSUBSS3_MASK3,
29353 IX86_BUILTIN_VFNMADDPD512_MASK,
29354 IX86_BUILTIN_VFNMADDPS512_MASK,
29355 IX86_BUILTIN_VFNMSUBPD512_MASK,
29356 IX86_BUILTIN_VFNMSUBPD512_MASK3,
29357 IX86_BUILTIN_VFNMSUBPS512_MASK,
29358 IX86_BUILTIN_VFNMSUBPS512_MASK3,
29359 IX86_BUILTIN_VPCLZCNTD512,
29360 IX86_BUILTIN_VPCLZCNTQ512,
29361 IX86_BUILTIN_VPCONFLICTD512,
29362 IX86_BUILTIN_VPCONFLICTQ512,
29363 IX86_BUILTIN_VPERMDF512,
29364 IX86_BUILTIN_VPERMDI512,
29365 IX86_BUILTIN_VPERMI2VARD512,
29366 IX86_BUILTIN_VPERMI2VARPD512,
29367 IX86_BUILTIN_VPERMI2VARPS512,
29368 IX86_BUILTIN_VPERMI2VARQ512,
29369 IX86_BUILTIN_VPERMILPD512,
29370 IX86_BUILTIN_VPERMILPS512,
29371 IX86_BUILTIN_VPERMILVARPD512,
29372 IX86_BUILTIN_VPERMILVARPS512,
29373 IX86_BUILTIN_VPERMT2VARD512,
29374 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
29375 IX86_BUILTIN_VPERMT2VARPD512,
29376 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
29377 IX86_BUILTIN_VPERMT2VARPS512,
29378 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
29379 IX86_BUILTIN_VPERMT2VARQ512,
29380 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
29381 IX86_BUILTIN_VPERMVARDF512,
29382 IX86_BUILTIN_VPERMVARDI512,
29383 IX86_BUILTIN_VPERMVARSF512,
29384 IX86_BUILTIN_VPERMVARSI512,
29385 IX86_BUILTIN_VTERNLOGD512_MASK,
29386 IX86_BUILTIN_VTERNLOGD512_MASKZ,
29387 IX86_BUILTIN_VTERNLOGQ512_MASK,
29388 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
29390 /* Mask arithmetic operations */
29391 IX86_BUILTIN_KAND16,
29392 IX86_BUILTIN_KANDN16,
29393 IX86_BUILTIN_KNOT16,
29394 IX86_BUILTIN_KOR16,
29395 IX86_BUILTIN_KORTESTC16,
29396 IX86_BUILTIN_KORTESTZ16,
29397 IX86_BUILTIN_KUNPCKBW,
29398 IX86_BUILTIN_KXNOR16,
29399 IX86_BUILTIN_KXOR16,
29400 IX86_BUILTIN_KMOV16,
29402 /* AVX512VL. */
29403 IX86_BUILTIN_PMOVUSQD256_MEM,
29404 IX86_BUILTIN_PMOVUSQD128_MEM,
29405 IX86_BUILTIN_PMOVSQD256_MEM,
29406 IX86_BUILTIN_PMOVSQD128_MEM,
29407 IX86_BUILTIN_PMOVQD256_MEM,
29408 IX86_BUILTIN_PMOVQD128_MEM,
29409 IX86_BUILTIN_PMOVUSQW256_MEM,
29410 IX86_BUILTIN_PMOVUSQW128_MEM,
29411 IX86_BUILTIN_PMOVSQW256_MEM,
29412 IX86_BUILTIN_PMOVSQW128_MEM,
29413 IX86_BUILTIN_PMOVQW256_MEM,
29414 IX86_BUILTIN_PMOVQW128_MEM,
29415 IX86_BUILTIN_PMOVUSQB256_MEM,
29416 IX86_BUILTIN_PMOVUSQB128_MEM,
29417 IX86_BUILTIN_PMOVSQB256_MEM,
29418 IX86_BUILTIN_PMOVSQB128_MEM,
29419 IX86_BUILTIN_PMOVQB256_MEM,
29420 IX86_BUILTIN_PMOVQB128_MEM,
29421 IX86_BUILTIN_PMOVUSDW256_MEM,
29422 IX86_BUILTIN_PMOVUSDW128_MEM,
29423 IX86_BUILTIN_PMOVSDW256_MEM,
29424 IX86_BUILTIN_PMOVSDW128_MEM,
29425 IX86_BUILTIN_PMOVDW256_MEM,
29426 IX86_BUILTIN_PMOVDW128_MEM,
29427 IX86_BUILTIN_PMOVUSDB256_MEM,
29428 IX86_BUILTIN_PMOVUSDB128_MEM,
29429 IX86_BUILTIN_PMOVSDB256_MEM,
29430 IX86_BUILTIN_PMOVSDB128_MEM,
29431 IX86_BUILTIN_PMOVDB256_MEM,
29432 IX86_BUILTIN_PMOVDB128_MEM,
29433 IX86_BUILTIN_MOVDQA64LOAD256_MASK,
29434 IX86_BUILTIN_MOVDQA64LOAD128_MASK,
29435 IX86_BUILTIN_MOVDQA32LOAD256_MASK,
29436 IX86_BUILTIN_MOVDQA32LOAD128_MASK,
29437 IX86_BUILTIN_MOVDQA64STORE256_MASK,
29438 IX86_BUILTIN_MOVDQA64STORE128_MASK,
29439 IX86_BUILTIN_MOVDQA32STORE256_MASK,
29440 IX86_BUILTIN_MOVDQA32STORE128_MASK,
29441 IX86_BUILTIN_LOADAPD256_MASK,
29442 IX86_BUILTIN_LOADAPD128_MASK,
29443 IX86_BUILTIN_LOADAPS256_MASK,
29444 IX86_BUILTIN_LOADAPS128_MASK,
29445 IX86_BUILTIN_STOREAPD256_MASK,
29446 IX86_BUILTIN_STOREAPD128_MASK,
29447 IX86_BUILTIN_STOREAPS256_MASK,
29448 IX86_BUILTIN_STOREAPS128_MASK,
29449 IX86_BUILTIN_LOADUPD256_MASK,
29450 IX86_BUILTIN_LOADUPD128_MASK,
29451 IX86_BUILTIN_LOADUPS256_MASK,
29452 IX86_BUILTIN_LOADUPS128_MASK,
29453 IX86_BUILTIN_STOREUPD256_MASK,
29454 IX86_BUILTIN_STOREUPD128_MASK,
29455 IX86_BUILTIN_STOREUPS256_MASK,
29456 IX86_BUILTIN_STOREUPS128_MASK,
29457 IX86_BUILTIN_LOADDQUDI256_MASK,
29458 IX86_BUILTIN_LOADDQUDI128_MASK,
29459 IX86_BUILTIN_LOADDQUSI256_MASK,
29460 IX86_BUILTIN_LOADDQUSI128_MASK,
29461 IX86_BUILTIN_LOADDQUHI256_MASK,
29462 IX86_BUILTIN_LOADDQUHI128_MASK,
29463 IX86_BUILTIN_LOADDQUQI256_MASK,
29464 IX86_BUILTIN_LOADDQUQI128_MASK,
29465 IX86_BUILTIN_STOREDQUDI256_MASK,
29466 IX86_BUILTIN_STOREDQUDI128_MASK,
29467 IX86_BUILTIN_STOREDQUSI256_MASK,
29468 IX86_BUILTIN_STOREDQUSI128_MASK,
29469 IX86_BUILTIN_STOREDQUHI256_MASK,
29470 IX86_BUILTIN_STOREDQUHI128_MASK,
29471 IX86_BUILTIN_STOREDQUQI256_MASK,
29472 IX86_BUILTIN_STOREDQUQI128_MASK,
29473 IX86_BUILTIN_COMPRESSPDSTORE256,
29474 IX86_BUILTIN_COMPRESSPDSTORE128,
29475 IX86_BUILTIN_COMPRESSPSSTORE256,
29476 IX86_BUILTIN_COMPRESSPSSTORE128,
29477 IX86_BUILTIN_PCOMPRESSQSTORE256,
29478 IX86_BUILTIN_PCOMPRESSQSTORE128,
29479 IX86_BUILTIN_PCOMPRESSDSTORE256,
29480 IX86_BUILTIN_PCOMPRESSDSTORE128,
29481 IX86_BUILTIN_EXPANDPDLOAD256,
29482 IX86_BUILTIN_EXPANDPDLOAD128,
29483 IX86_BUILTIN_EXPANDPSLOAD256,
29484 IX86_BUILTIN_EXPANDPSLOAD128,
29485 IX86_BUILTIN_PEXPANDQLOAD256,
29486 IX86_BUILTIN_PEXPANDQLOAD128,
29487 IX86_BUILTIN_PEXPANDDLOAD256,
29488 IX86_BUILTIN_PEXPANDDLOAD128,
29489 IX86_BUILTIN_EXPANDPDLOAD256Z,
29490 IX86_BUILTIN_EXPANDPDLOAD128Z,
29491 IX86_BUILTIN_EXPANDPSLOAD256Z,
29492 IX86_BUILTIN_EXPANDPSLOAD128Z,
29493 IX86_BUILTIN_PEXPANDQLOAD256Z,
29494 IX86_BUILTIN_PEXPANDQLOAD128Z,
29495 IX86_BUILTIN_PEXPANDDLOAD256Z,
29496 IX86_BUILTIN_PEXPANDDLOAD128Z,
29497 IX86_BUILTIN_PALIGNR256_MASK,
29498 IX86_BUILTIN_PALIGNR128_MASK,
29499 IX86_BUILTIN_MOVDQA64_256_MASK,
29500 IX86_BUILTIN_MOVDQA64_128_MASK,
29501 IX86_BUILTIN_MOVDQA32_256_MASK,
29502 IX86_BUILTIN_MOVDQA32_128_MASK,
29503 IX86_BUILTIN_MOVAPD256_MASK,
29504 IX86_BUILTIN_MOVAPD128_MASK,
29505 IX86_BUILTIN_MOVAPS256_MASK,
29506 IX86_BUILTIN_MOVAPS128_MASK,
29507 IX86_BUILTIN_MOVDQUHI256_MASK,
29508 IX86_BUILTIN_MOVDQUHI128_MASK,
29509 IX86_BUILTIN_MOVDQUQI256_MASK,
29510 IX86_BUILTIN_MOVDQUQI128_MASK,
29511 IX86_BUILTIN_MINPS128_MASK,
29512 IX86_BUILTIN_MAXPS128_MASK,
29513 IX86_BUILTIN_MINPD128_MASK,
29514 IX86_BUILTIN_MAXPD128_MASK,
29515 IX86_BUILTIN_MAXPD256_MASK,
29516 IX86_BUILTIN_MAXPS256_MASK,
29517 IX86_BUILTIN_MINPD256_MASK,
29518 IX86_BUILTIN_MINPS256_MASK,
29519 IX86_BUILTIN_MULPS128_MASK,
29520 IX86_BUILTIN_DIVPS128_MASK,
29521 IX86_BUILTIN_MULPD128_MASK,
29522 IX86_BUILTIN_DIVPD128_MASK,
29523 IX86_BUILTIN_DIVPD256_MASK,
29524 IX86_BUILTIN_DIVPS256_MASK,
29525 IX86_BUILTIN_MULPD256_MASK,
29526 IX86_BUILTIN_MULPS256_MASK,
29527 IX86_BUILTIN_ADDPD128_MASK,
29528 IX86_BUILTIN_ADDPD256_MASK,
29529 IX86_BUILTIN_ADDPS128_MASK,
29530 IX86_BUILTIN_ADDPS256_MASK,
29531 IX86_BUILTIN_SUBPD128_MASK,
29532 IX86_BUILTIN_SUBPD256_MASK,
29533 IX86_BUILTIN_SUBPS128_MASK,
29534 IX86_BUILTIN_SUBPS256_MASK,
29535 IX86_BUILTIN_XORPD256_MASK,
29536 IX86_BUILTIN_XORPD128_MASK,
29537 IX86_BUILTIN_XORPS256_MASK,
29538 IX86_BUILTIN_XORPS128_MASK,
29539 IX86_BUILTIN_ORPD256_MASK,
29540 IX86_BUILTIN_ORPD128_MASK,
29541 IX86_BUILTIN_ORPS256_MASK,
29542 IX86_BUILTIN_ORPS128_MASK,
29543 IX86_BUILTIN_BROADCASTF32x2_256,
29544 IX86_BUILTIN_BROADCASTI32x2_256,
29545 IX86_BUILTIN_BROADCASTI32x2_128,
29546 IX86_BUILTIN_BROADCASTF64X2_256,
29547 IX86_BUILTIN_BROADCASTI64X2_256,
29548 IX86_BUILTIN_BROADCASTF32X4_256,
29549 IX86_BUILTIN_BROADCASTI32X4_256,
29550 IX86_BUILTIN_EXTRACTF32X4_256,
29551 IX86_BUILTIN_EXTRACTI32X4_256,
29552 IX86_BUILTIN_DBPSADBW256,
29553 IX86_BUILTIN_DBPSADBW128,
29554 IX86_BUILTIN_CVTTPD2QQ256,
29555 IX86_BUILTIN_CVTTPD2QQ128,
29556 IX86_BUILTIN_CVTTPD2UQQ256,
29557 IX86_BUILTIN_CVTTPD2UQQ128,
29558 IX86_BUILTIN_CVTPD2QQ256,
29559 IX86_BUILTIN_CVTPD2QQ128,
29560 IX86_BUILTIN_CVTPD2UQQ256,
29561 IX86_BUILTIN_CVTPD2UQQ128,
29562 IX86_BUILTIN_CVTPD2UDQ256_MASK,
29563 IX86_BUILTIN_CVTPD2UDQ128_MASK,
29564 IX86_BUILTIN_CVTTPS2QQ256,
29565 IX86_BUILTIN_CVTTPS2QQ128,
29566 IX86_BUILTIN_CVTTPS2UQQ256,
29567 IX86_BUILTIN_CVTTPS2UQQ128,
29568 IX86_BUILTIN_CVTTPS2DQ256_MASK,
29569 IX86_BUILTIN_CVTTPS2DQ128_MASK,
29570 IX86_BUILTIN_CVTTPS2UDQ256,
29571 IX86_BUILTIN_CVTTPS2UDQ128,
29572 IX86_BUILTIN_CVTTPD2DQ256_MASK,
29573 IX86_BUILTIN_CVTTPD2DQ128_MASK,
29574 IX86_BUILTIN_CVTTPD2UDQ256_MASK,
29575 IX86_BUILTIN_CVTTPD2UDQ128_MASK,
29576 IX86_BUILTIN_CVTPD2DQ256_MASK,
29577 IX86_BUILTIN_CVTPD2DQ128_MASK,
29578 IX86_BUILTIN_CVTDQ2PD256_MASK,
29579 IX86_BUILTIN_CVTDQ2PD128_MASK,
29580 IX86_BUILTIN_CVTUDQ2PD256_MASK,
29581 IX86_BUILTIN_CVTUDQ2PD128_MASK,
29582 IX86_BUILTIN_CVTDQ2PS256_MASK,
29583 IX86_BUILTIN_CVTDQ2PS128_MASK,
29584 IX86_BUILTIN_CVTUDQ2PS256_MASK,
29585 IX86_BUILTIN_CVTUDQ2PS128_MASK,
29586 IX86_BUILTIN_CVTPS2PD256_MASK,
29587 IX86_BUILTIN_CVTPS2PD128_MASK,
29588 IX86_BUILTIN_PBROADCASTB256_MASK,
29589 IX86_BUILTIN_PBROADCASTB256_GPR_MASK,
29590 IX86_BUILTIN_PBROADCASTB128_MASK,
29591 IX86_BUILTIN_PBROADCASTB128_GPR_MASK,
29592 IX86_BUILTIN_PBROADCASTW256_MASK,
29593 IX86_BUILTIN_PBROADCASTW256_GPR_MASK,
29594 IX86_BUILTIN_PBROADCASTW128_MASK,
29595 IX86_BUILTIN_PBROADCASTW128_GPR_MASK,
29596 IX86_BUILTIN_PBROADCASTD256_MASK,
29597 IX86_BUILTIN_PBROADCASTD256_GPR_MASK,
29598 IX86_BUILTIN_PBROADCASTD128_MASK,
29599 IX86_BUILTIN_PBROADCASTD128_GPR_MASK,
29600 IX86_BUILTIN_PBROADCASTQ256_MASK,
29601 IX86_BUILTIN_PBROADCASTQ256_GPR_MASK,
29602 IX86_BUILTIN_PBROADCASTQ128_MASK,
29603 IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
29604 IX86_BUILTIN_BROADCASTSS256,
29605 IX86_BUILTIN_BROADCASTSS128,
29606 IX86_BUILTIN_BROADCASTSD256,
29607 IX86_BUILTIN_EXTRACTF64X2_256,
29608 IX86_BUILTIN_EXTRACTI64X2_256,
29609 IX86_BUILTIN_INSERTF32X4_256,
29610 IX86_BUILTIN_INSERTI32X4_256,
29611 IX86_BUILTIN_PMOVSXBW256_MASK,
29612 IX86_BUILTIN_PMOVSXBW128_MASK,
29613 IX86_BUILTIN_PMOVSXBD256_MASK,
29614 IX86_BUILTIN_PMOVSXBD128_MASK,
29615 IX86_BUILTIN_PMOVSXBQ256_MASK,
29616 IX86_BUILTIN_PMOVSXBQ128_MASK,
29617 IX86_BUILTIN_PMOVSXWD256_MASK,
29618 IX86_BUILTIN_PMOVSXWD128_MASK,
29619 IX86_BUILTIN_PMOVSXWQ256_MASK,
29620 IX86_BUILTIN_PMOVSXWQ128_MASK,
29621 IX86_BUILTIN_PMOVSXDQ256_MASK,
29622 IX86_BUILTIN_PMOVSXDQ128_MASK,
29623 IX86_BUILTIN_PMOVZXBW256_MASK,
29624 IX86_BUILTIN_PMOVZXBW128_MASK,
29625 IX86_BUILTIN_PMOVZXBD256_MASK,
29626 IX86_BUILTIN_PMOVZXBD128_MASK,
29627 IX86_BUILTIN_PMOVZXBQ256_MASK,
29628 IX86_BUILTIN_PMOVZXBQ128_MASK,
29629 IX86_BUILTIN_PMOVZXWD256_MASK,
29630 IX86_BUILTIN_PMOVZXWD128_MASK,
29631 IX86_BUILTIN_PMOVZXWQ256_MASK,
29632 IX86_BUILTIN_PMOVZXWQ128_MASK,
29633 IX86_BUILTIN_PMOVZXDQ256_MASK,
29634 IX86_BUILTIN_PMOVZXDQ128_MASK,
29635 IX86_BUILTIN_REDUCEPD256_MASK,
29636 IX86_BUILTIN_REDUCEPD128_MASK,
29637 IX86_BUILTIN_REDUCEPS256_MASK,
29638 IX86_BUILTIN_REDUCEPS128_MASK,
29639 IX86_BUILTIN_REDUCESD_MASK,
29640 IX86_BUILTIN_REDUCESS_MASK,
29641 IX86_BUILTIN_VPERMVARHI256_MASK,
29642 IX86_BUILTIN_VPERMVARHI128_MASK,
29643 IX86_BUILTIN_VPERMT2VARHI256,
29644 IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
29645 IX86_BUILTIN_VPERMT2VARHI128,
29646 IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
29647 IX86_BUILTIN_VPERMI2VARHI256,
29648 IX86_BUILTIN_VPERMI2VARHI128,
29649 IX86_BUILTIN_RCP14PD256,
29650 IX86_BUILTIN_RCP14PD128,
29651 IX86_BUILTIN_RCP14PS256,
29652 IX86_BUILTIN_RCP14PS128,
29653 IX86_BUILTIN_RSQRT14PD256_MASK,
29654 IX86_BUILTIN_RSQRT14PD128_MASK,
29655 IX86_BUILTIN_RSQRT14PS256_MASK,
29656 IX86_BUILTIN_RSQRT14PS128_MASK,
29657 IX86_BUILTIN_SQRTPD256_MASK,
29658 IX86_BUILTIN_SQRTPD128_MASK,
29659 IX86_BUILTIN_SQRTPS256_MASK,
29660 IX86_BUILTIN_SQRTPS128_MASK,
29661 IX86_BUILTIN_PADDB128_MASK,
29662 IX86_BUILTIN_PADDW128_MASK,
29663 IX86_BUILTIN_PADDD128_MASK,
29664 IX86_BUILTIN_PADDQ128_MASK,
29665 IX86_BUILTIN_PSUBB128_MASK,
29666 IX86_BUILTIN_PSUBW128_MASK,
29667 IX86_BUILTIN_PSUBD128_MASK,
29668 IX86_BUILTIN_PSUBQ128_MASK,
29669 IX86_BUILTIN_PADDSB128_MASK,
29670 IX86_BUILTIN_PADDSW128_MASK,
29671 IX86_BUILTIN_PSUBSB128_MASK,
29672 IX86_BUILTIN_PSUBSW128_MASK,
29673 IX86_BUILTIN_PADDUSB128_MASK,
29674 IX86_BUILTIN_PADDUSW128_MASK,
29675 IX86_BUILTIN_PSUBUSB128_MASK,
29676 IX86_BUILTIN_PSUBUSW128_MASK,
29677 IX86_BUILTIN_PADDB256_MASK,
29678 IX86_BUILTIN_PADDW256_MASK,
29679 IX86_BUILTIN_PADDD256_MASK,
29680 IX86_BUILTIN_PADDQ256_MASK,
29681 IX86_BUILTIN_PADDSB256_MASK,
29682 IX86_BUILTIN_PADDSW256_MASK,
29683 IX86_BUILTIN_PADDUSB256_MASK,
29684 IX86_BUILTIN_PADDUSW256_MASK,
29685 IX86_BUILTIN_PSUBB256_MASK,
29686 IX86_BUILTIN_PSUBW256_MASK,
29687 IX86_BUILTIN_PSUBD256_MASK,
29688 IX86_BUILTIN_PSUBQ256_MASK,
29689 IX86_BUILTIN_PSUBSB256_MASK,
29690 IX86_BUILTIN_PSUBSW256_MASK,
29691 IX86_BUILTIN_PSUBUSB256_MASK,
29692 IX86_BUILTIN_PSUBUSW256_MASK,
29693 IX86_BUILTIN_SHUF_F64x2_256,
29694 IX86_BUILTIN_SHUF_I64x2_256,
29695 IX86_BUILTIN_SHUF_I32x4_256,
29696 IX86_BUILTIN_SHUF_F32x4_256,
29697 IX86_BUILTIN_PMOVWB128,
29698 IX86_BUILTIN_PMOVWB256,
29699 IX86_BUILTIN_PMOVSWB128,
29700 IX86_BUILTIN_PMOVSWB256,
29701 IX86_BUILTIN_PMOVUSWB128,
29702 IX86_BUILTIN_PMOVUSWB256,
29703 IX86_BUILTIN_PMOVDB128,
29704 IX86_BUILTIN_PMOVDB256,
29705 IX86_BUILTIN_PMOVSDB128,
29706 IX86_BUILTIN_PMOVSDB256,
29707 IX86_BUILTIN_PMOVUSDB128,
29708 IX86_BUILTIN_PMOVUSDB256,
29709 IX86_BUILTIN_PMOVDW128,
29710 IX86_BUILTIN_PMOVDW256,
29711 IX86_BUILTIN_PMOVSDW128,
29712 IX86_BUILTIN_PMOVSDW256,
29713 IX86_BUILTIN_PMOVUSDW128,
29714 IX86_BUILTIN_PMOVUSDW256,
29715 IX86_BUILTIN_PMOVQB128,
29716 IX86_BUILTIN_PMOVQB256,
29717 IX86_BUILTIN_PMOVSQB128,
29718 IX86_BUILTIN_PMOVSQB256,
29719 IX86_BUILTIN_PMOVUSQB128,
29720 IX86_BUILTIN_PMOVUSQB256,
29721 IX86_BUILTIN_PMOVQW128,
29722 IX86_BUILTIN_PMOVQW256,
29723 IX86_BUILTIN_PMOVSQW128,
29724 IX86_BUILTIN_PMOVSQW256,
29725 IX86_BUILTIN_PMOVUSQW128,
29726 IX86_BUILTIN_PMOVUSQW256,
29727 IX86_BUILTIN_PMOVQD128,
29728 IX86_BUILTIN_PMOVQD256,
29729 IX86_BUILTIN_PMOVSQD128,
29730 IX86_BUILTIN_PMOVSQD256,
29731 IX86_BUILTIN_PMOVUSQD128,
29732 IX86_BUILTIN_PMOVUSQD256,
29733 IX86_BUILTIN_RANGEPD256,
29734 IX86_BUILTIN_RANGEPD128,
29735 IX86_BUILTIN_RANGEPS256,
29736 IX86_BUILTIN_RANGEPS128,
29737 IX86_BUILTIN_GETEXPPS256,
29738 IX86_BUILTIN_GETEXPPD256,
29739 IX86_BUILTIN_GETEXPPS128,
29740 IX86_BUILTIN_GETEXPPD128,
29741 IX86_BUILTIN_FIXUPIMMPD256_MASK,
29742 IX86_BUILTIN_FIXUPIMMPD256_MASKZ,
29743 IX86_BUILTIN_FIXUPIMMPS256_MASK,
29744 IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
29745 IX86_BUILTIN_FIXUPIMMPD128_MASK,
29746 IX86_BUILTIN_FIXUPIMMPD128_MASKZ,
29747 IX86_BUILTIN_FIXUPIMMPS128_MASK,
29748 IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
29749 IX86_BUILTIN_PABSQ256,
29750 IX86_BUILTIN_PABSQ128,
29751 IX86_BUILTIN_PABSD256_MASK,
29752 IX86_BUILTIN_PABSD128_MASK,
29753 IX86_BUILTIN_PMULHRSW256_MASK,
29754 IX86_BUILTIN_PMULHRSW128_MASK,
29755 IX86_BUILTIN_PMULHUW128_MASK,
29756 IX86_BUILTIN_PMULHUW256_MASK,
29757 IX86_BUILTIN_PMULHW256_MASK,
29758 IX86_BUILTIN_PMULHW128_MASK,
29759 IX86_BUILTIN_PMULLW256_MASK,
29760 IX86_BUILTIN_PMULLW128_MASK,
29761 IX86_BUILTIN_PMULLQ256,
29762 IX86_BUILTIN_PMULLQ128,
29763 IX86_BUILTIN_ANDPD256_MASK,
29764 IX86_BUILTIN_ANDPD128_MASK,
29765 IX86_BUILTIN_ANDPS256_MASK,
29766 IX86_BUILTIN_ANDPS128_MASK,
29767 IX86_BUILTIN_ANDNPD256_MASK,
29768 IX86_BUILTIN_ANDNPD128_MASK,
29769 IX86_BUILTIN_ANDNPS256_MASK,
29770 IX86_BUILTIN_ANDNPS128_MASK,
29771 IX86_BUILTIN_PSLLWI128_MASK,
29772 IX86_BUILTIN_PSLLDI128_MASK,
29773 IX86_BUILTIN_PSLLQI128_MASK,
29774 IX86_BUILTIN_PSLLW128_MASK,
29775 IX86_BUILTIN_PSLLD128_MASK,
29776 IX86_BUILTIN_PSLLQ128_MASK,
29777 IX86_BUILTIN_PSLLWI256_MASK ,
29778 IX86_BUILTIN_PSLLW256_MASK,
29779 IX86_BUILTIN_PSLLDI256_MASK,
29780 IX86_BUILTIN_PSLLD256_MASK,
29781 IX86_BUILTIN_PSLLQI256_MASK,
29782 IX86_BUILTIN_PSLLQ256_MASK,
29783 IX86_BUILTIN_PSRADI128_MASK,
29784 IX86_BUILTIN_PSRAD128_MASK,
29785 IX86_BUILTIN_PSRADI256_MASK,
29786 IX86_BUILTIN_PSRAD256_MASK,
29787 IX86_BUILTIN_PSRAQI128_MASK,
29788 IX86_BUILTIN_PSRAQ128_MASK,
29789 IX86_BUILTIN_PSRAQI256_MASK,
29790 IX86_BUILTIN_PSRAQ256_MASK,
29791 IX86_BUILTIN_PANDD256,
29792 IX86_BUILTIN_PANDD128,
29793 IX86_BUILTIN_PSRLDI128_MASK,
29794 IX86_BUILTIN_PSRLD128_MASK,
29795 IX86_BUILTIN_PSRLDI256_MASK,
29796 IX86_BUILTIN_PSRLD256_MASK,
29797 IX86_BUILTIN_PSRLQI128_MASK,
29798 IX86_BUILTIN_PSRLQ128_MASK,
29799 IX86_BUILTIN_PSRLQI256_MASK,
29800 IX86_BUILTIN_PSRLQ256_MASK,
29801 IX86_BUILTIN_PANDQ256,
29802 IX86_BUILTIN_PANDQ128,
29803 IX86_BUILTIN_PANDND256,
29804 IX86_BUILTIN_PANDND128,
29805 IX86_BUILTIN_PANDNQ256,
29806 IX86_BUILTIN_PANDNQ128,
29807 IX86_BUILTIN_PORD256,
29808 IX86_BUILTIN_PORD128,
29809 IX86_BUILTIN_PORQ256,
29810 IX86_BUILTIN_PORQ128,
29811 IX86_BUILTIN_PXORD256,
29812 IX86_BUILTIN_PXORD128,
29813 IX86_BUILTIN_PXORQ256,
29814 IX86_BUILTIN_PXORQ128,
29815 IX86_BUILTIN_PACKSSWB256_MASK,
29816 IX86_BUILTIN_PACKSSWB128_MASK,
29817 IX86_BUILTIN_PACKUSWB256_MASK,
29818 IX86_BUILTIN_PACKUSWB128_MASK,
29819 IX86_BUILTIN_RNDSCALEPS256,
29820 IX86_BUILTIN_RNDSCALEPD256,
29821 IX86_BUILTIN_RNDSCALEPS128,
29822 IX86_BUILTIN_RNDSCALEPD128,
29823 IX86_BUILTIN_VTERNLOGQ256_MASK,
29824 IX86_BUILTIN_VTERNLOGQ256_MASKZ,
29825 IX86_BUILTIN_VTERNLOGD256_MASK,
29826 IX86_BUILTIN_VTERNLOGD256_MASKZ,
29827 IX86_BUILTIN_VTERNLOGQ128_MASK,
29828 IX86_BUILTIN_VTERNLOGQ128_MASKZ,
29829 IX86_BUILTIN_VTERNLOGD128_MASK,
29830 IX86_BUILTIN_VTERNLOGD128_MASKZ,
29831 IX86_BUILTIN_SCALEFPD256,
29832 IX86_BUILTIN_SCALEFPS256,
29833 IX86_BUILTIN_SCALEFPD128,
29834 IX86_BUILTIN_SCALEFPS128,
29835 IX86_BUILTIN_VFMADDPD256_MASK,
29836 IX86_BUILTIN_VFMADDPD256_MASK3,
29837 IX86_BUILTIN_VFMADDPD256_MASKZ,
29838 IX86_BUILTIN_VFMADDPD128_MASK,
29839 IX86_BUILTIN_VFMADDPD128_MASK3,
29840 IX86_BUILTIN_VFMADDPD128_MASKZ,
29841 IX86_BUILTIN_VFMADDPS256_MASK,
29842 IX86_BUILTIN_VFMADDPS256_MASK3,
29843 IX86_BUILTIN_VFMADDPS256_MASKZ,
29844 IX86_BUILTIN_VFMADDPS128_MASK,
29845 IX86_BUILTIN_VFMADDPS128_MASK3,
29846 IX86_BUILTIN_VFMADDPS128_MASKZ,
29847 IX86_BUILTIN_VFMSUBPD256_MASK3,
29848 IX86_BUILTIN_VFMSUBPD128_MASK3,
29849 IX86_BUILTIN_VFMSUBPS256_MASK3,
29850 IX86_BUILTIN_VFMSUBPS128_MASK3,
29851 IX86_BUILTIN_VFNMADDPD256_MASK,
29852 IX86_BUILTIN_VFNMADDPD128_MASK,
29853 IX86_BUILTIN_VFNMADDPS256_MASK,
29854 IX86_BUILTIN_VFNMADDPS128_MASK,
29855 IX86_BUILTIN_VFNMSUBPD256_MASK,
29856 IX86_BUILTIN_VFNMSUBPD256_MASK3,
29857 IX86_BUILTIN_VFNMSUBPD128_MASK,
29858 IX86_BUILTIN_VFNMSUBPD128_MASK3,
29859 IX86_BUILTIN_VFNMSUBPS256_MASK,
29860 IX86_BUILTIN_VFNMSUBPS256_MASK3,
29861 IX86_BUILTIN_VFNMSUBPS128_MASK,
29862 IX86_BUILTIN_VFNMSUBPS128_MASK3,
29863 IX86_BUILTIN_VFMADDSUBPD256_MASK,
29864 IX86_BUILTIN_VFMADDSUBPD256_MASK3,
29865 IX86_BUILTIN_VFMADDSUBPD256_MASKZ,
29866 IX86_BUILTIN_VFMADDSUBPD128_MASK,
29867 IX86_BUILTIN_VFMADDSUBPD128_MASK3,
29868 IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
29869 IX86_BUILTIN_VFMADDSUBPS256_MASK,
29870 IX86_BUILTIN_VFMADDSUBPS256_MASK3,
29871 IX86_BUILTIN_VFMADDSUBPS256_MASKZ,
29872 IX86_BUILTIN_VFMADDSUBPS128_MASK,
29873 IX86_BUILTIN_VFMADDSUBPS128_MASK3,
29874 IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
29875 IX86_BUILTIN_VFMSUBADDPD256_MASK3,
29876 IX86_BUILTIN_VFMSUBADDPD128_MASK3,
29877 IX86_BUILTIN_VFMSUBADDPS256_MASK3,
29878 IX86_BUILTIN_VFMSUBADDPS128_MASK3,
29879 IX86_BUILTIN_INSERTF64X2_256,
29880 IX86_BUILTIN_INSERTI64X2_256,
29881 IX86_BUILTIN_PSRAVV16HI,
29882 IX86_BUILTIN_PSRAVV8HI,
29883 IX86_BUILTIN_PMADDUBSW256_MASK,
29884 IX86_BUILTIN_PMADDUBSW128_MASK,
29885 IX86_BUILTIN_PMADDWD256_MASK,
29886 IX86_BUILTIN_PMADDWD128_MASK,
29887 IX86_BUILTIN_PSRLVV16HI,
29888 IX86_BUILTIN_PSRLVV8HI,
29889 IX86_BUILTIN_CVTPS2DQ256_MASK,
29890 IX86_BUILTIN_CVTPS2DQ128_MASK,
29891 IX86_BUILTIN_CVTPS2UDQ256,
29892 IX86_BUILTIN_CVTPS2UDQ128,
29893 IX86_BUILTIN_CVTPS2QQ256,
29894 IX86_BUILTIN_CVTPS2QQ128,
29895 IX86_BUILTIN_CVTPS2UQQ256,
29896 IX86_BUILTIN_CVTPS2UQQ128,
29897 IX86_BUILTIN_GETMANTPS256,
29898 IX86_BUILTIN_GETMANTPS128,
29899 IX86_BUILTIN_GETMANTPD256,
29900 IX86_BUILTIN_GETMANTPD128,
29901 IX86_BUILTIN_MOVDDUP256_MASK,
29902 IX86_BUILTIN_MOVDDUP128_MASK,
29903 IX86_BUILTIN_MOVSHDUP256_MASK,
29904 IX86_BUILTIN_MOVSHDUP128_MASK,
29905 IX86_BUILTIN_MOVSLDUP256_MASK,
29906 IX86_BUILTIN_MOVSLDUP128_MASK,
29907 IX86_BUILTIN_CVTQQ2PS256,
29908 IX86_BUILTIN_CVTQQ2PS128,
29909 IX86_BUILTIN_CVTUQQ2PS256,
29910 IX86_BUILTIN_CVTUQQ2PS128,
29911 IX86_BUILTIN_CVTQQ2PD256,
29912 IX86_BUILTIN_CVTQQ2PD128,
29913 IX86_BUILTIN_CVTUQQ2PD256,
29914 IX86_BUILTIN_CVTUQQ2PD128,
29915 IX86_BUILTIN_VPERMT2VARQ256,
29916 IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
29917 IX86_BUILTIN_VPERMT2VARD256,
29918 IX86_BUILTIN_VPERMT2VARD256_MASKZ,
29919 IX86_BUILTIN_VPERMI2VARQ256,
29920 IX86_BUILTIN_VPERMI2VARD256,
29921 IX86_BUILTIN_VPERMT2VARPD256,
29922 IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
29923 IX86_BUILTIN_VPERMT2VARPS256,
29924 IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
29925 IX86_BUILTIN_VPERMI2VARPD256,
29926 IX86_BUILTIN_VPERMI2VARPS256,
29927 IX86_BUILTIN_VPERMT2VARQ128,
29928 IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
29929 IX86_BUILTIN_VPERMT2VARD128,
29930 IX86_BUILTIN_VPERMT2VARD128_MASKZ,
29931 IX86_BUILTIN_VPERMI2VARQ128,
29932 IX86_BUILTIN_VPERMI2VARD128,
29933 IX86_BUILTIN_VPERMT2VARPD128,
29934 IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
29935 IX86_BUILTIN_VPERMT2VARPS128,
29936 IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
29937 IX86_BUILTIN_VPERMI2VARPD128,
29938 IX86_BUILTIN_VPERMI2VARPS128,
29939 IX86_BUILTIN_PSHUFB256_MASK,
29940 IX86_BUILTIN_PSHUFB128_MASK,
29941 IX86_BUILTIN_PSHUFHW256_MASK,
29942 IX86_BUILTIN_PSHUFHW128_MASK,
29943 IX86_BUILTIN_PSHUFLW256_MASK,
29944 IX86_BUILTIN_PSHUFLW128_MASK,
29945 IX86_BUILTIN_PSHUFD256_MASK,
29946 IX86_BUILTIN_PSHUFD128_MASK,
29947 IX86_BUILTIN_SHUFPD256_MASK,
29948 IX86_BUILTIN_SHUFPD128_MASK,
29949 IX86_BUILTIN_SHUFPS256_MASK,
29950 IX86_BUILTIN_SHUFPS128_MASK,
29951 IX86_BUILTIN_PROLVQ256,
29952 IX86_BUILTIN_PROLVQ128,
29953 IX86_BUILTIN_PROLQ256,
29954 IX86_BUILTIN_PROLQ128,
29955 IX86_BUILTIN_PRORVQ256,
29956 IX86_BUILTIN_PRORVQ128,
29957 IX86_BUILTIN_PRORQ256,
29958 IX86_BUILTIN_PRORQ128,
29959 IX86_BUILTIN_PSRAVQ128,
29960 IX86_BUILTIN_PSRAVQ256,
29961 IX86_BUILTIN_PSLLVV4DI_MASK,
29962 IX86_BUILTIN_PSLLVV2DI_MASK,
29963 IX86_BUILTIN_PSLLVV8SI_MASK,
29964 IX86_BUILTIN_PSLLVV4SI_MASK,
29965 IX86_BUILTIN_PSRAVV8SI_MASK,
29966 IX86_BUILTIN_PSRAVV4SI_MASK,
29967 IX86_BUILTIN_PSRLVV4DI_MASK,
29968 IX86_BUILTIN_PSRLVV2DI_MASK,
29969 IX86_BUILTIN_PSRLVV8SI_MASK,
29970 IX86_BUILTIN_PSRLVV4SI_MASK,
29971 IX86_BUILTIN_PSRAWI256_MASK,
29972 IX86_BUILTIN_PSRAW256_MASK,
29973 IX86_BUILTIN_PSRAWI128_MASK,
29974 IX86_BUILTIN_PSRAW128_MASK,
29975 IX86_BUILTIN_PSRLWI256_MASK,
29976 IX86_BUILTIN_PSRLW256_MASK,
29977 IX86_BUILTIN_PSRLWI128_MASK,
29978 IX86_BUILTIN_PSRLW128_MASK,
29979 IX86_BUILTIN_PRORVD256,
29980 IX86_BUILTIN_PROLVD256,
29981 IX86_BUILTIN_PRORD256,
29982 IX86_BUILTIN_PROLD256,
29983 IX86_BUILTIN_PRORVD128,
29984 IX86_BUILTIN_PROLVD128,
29985 IX86_BUILTIN_PRORD128,
29986 IX86_BUILTIN_PROLD128,
29987 IX86_BUILTIN_FPCLASSPD256,
29988 IX86_BUILTIN_FPCLASSPD128,
29989 IX86_BUILTIN_FPCLASSSD,
29990 IX86_BUILTIN_FPCLASSPS256,
29991 IX86_BUILTIN_FPCLASSPS128,
29992 IX86_BUILTIN_FPCLASSSS,
29993 IX86_BUILTIN_CVTB2MASK128,
29994 IX86_BUILTIN_CVTB2MASK256,
29995 IX86_BUILTIN_CVTW2MASK128,
29996 IX86_BUILTIN_CVTW2MASK256,
29997 IX86_BUILTIN_CVTD2MASK128,
29998 IX86_BUILTIN_CVTD2MASK256,
29999 IX86_BUILTIN_CVTQ2MASK128,
30000 IX86_BUILTIN_CVTQ2MASK256,
30001 IX86_BUILTIN_CVTMASK2B128,
30002 IX86_BUILTIN_CVTMASK2B256,
30003 IX86_BUILTIN_CVTMASK2W128,
30004 IX86_BUILTIN_CVTMASK2W256,
30005 IX86_BUILTIN_CVTMASK2D128,
30006 IX86_BUILTIN_CVTMASK2D256,
30007 IX86_BUILTIN_CVTMASK2Q128,
30008 IX86_BUILTIN_CVTMASK2Q256,
30009 IX86_BUILTIN_PCMPEQB128_MASK,
30010 IX86_BUILTIN_PCMPEQB256_MASK,
30011 IX86_BUILTIN_PCMPEQW128_MASK,
30012 IX86_BUILTIN_PCMPEQW256_MASK,
30013 IX86_BUILTIN_PCMPEQD128_MASK,
30014 IX86_BUILTIN_PCMPEQD256_MASK,
30015 IX86_BUILTIN_PCMPEQQ128_MASK,
30016 IX86_BUILTIN_PCMPEQQ256_MASK,
30017 IX86_BUILTIN_PCMPGTB128_MASK,
30018 IX86_BUILTIN_PCMPGTB256_MASK,
30019 IX86_BUILTIN_PCMPGTW128_MASK,
30020 IX86_BUILTIN_PCMPGTW256_MASK,
30021 IX86_BUILTIN_PCMPGTD128_MASK,
30022 IX86_BUILTIN_PCMPGTD256_MASK,
30023 IX86_BUILTIN_PCMPGTQ128_MASK,
30024 IX86_BUILTIN_PCMPGTQ256_MASK,
30025 IX86_BUILTIN_PTESTMB128,
30026 IX86_BUILTIN_PTESTMB256,
30027 IX86_BUILTIN_PTESTMW128,
30028 IX86_BUILTIN_PTESTMW256,
30029 IX86_BUILTIN_PTESTMD128,
30030 IX86_BUILTIN_PTESTMD256,
30031 IX86_BUILTIN_PTESTMQ128,
30032 IX86_BUILTIN_PTESTMQ256,
30033 IX86_BUILTIN_PTESTNMB128,
30034 IX86_BUILTIN_PTESTNMB256,
30035 IX86_BUILTIN_PTESTNMW128,
30036 IX86_BUILTIN_PTESTNMW256,
30037 IX86_BUILTIN_PTESTNMD128,
30038 IX86_BUILTIN_PTESTNMD256,
30039 IX86_BUILTIN_PTESTNMQ128,
30040 IX86_BUILTIN_PTESTNMQ256,
30041 IX86_BUILTIN_PBROADCASTMB128,
30042 IX86_BUILTIN_PBROADCASTMB256,
30043 IX86_BUILTIN_PBROADCASTMW128,
30044 IX86_BUILTIN_PBROADCASTMW256,
30045 IX86_BUILTIN_COMPRESSPD256,
30046 IX86_BUILTIN_COMPRESSPD128,
30047 IX86_BUILTIN_COMPRESSPS256,
30048 IX86_BUILTIN_COMPRESSPS128,
30049 IX86_BUILTIN_PCOMPRESSQ256,
30050 IX86_BUILTIN_PCOMPRESSQ128,
30051 IX86_BUILTIN_PCOMPRESSD256,
30052 IX86_BUILTIN_PCOMPRESSD128,
30053 IX86_BUILTIN_EXPANDPD256,
30054 IX86_BUILTIN_EXPANDPD128,
30055 IX86_BUILTIN_EXPANDPS256,
30056 IX86_BUILTIN_EXPANDPS128,
30057 IX86_BUILTIN_PEXPANDQ256,
30058 IX86_BUILTIN_PEXPANDQ128,
30059 IX86_BUILTIN_PEXPANDD256,
30060 IX86_BUILTIN_PEXPANDD128,
30061 IX86_BUILTIN_EXPANDPD256Z,
30062 IX86_BUILTIN_EXPANDPD128Z,
30063 IX86_BUILTIN_EXPANDPS256Z,
30064 IX86_BUILTIN_EXPANDPS128Z,
30065 IX86_BUILTIN_PEXPANDQ256Z,
30066 IX86_BUILTIN_PEXPANDQ128Z,
30067 IX86_BUILTIN_PEXPANDD256Z,
30068 IX86_BUILTIN_PEXPANDD128Z,
30069 IX86_BUILTIN_PMAXSD256_MASK,
30070 IX86_BUILTIN_PMINSD256_MASK,
30071 IX86_BUILTIN_PMAXUD256_MASK,
30072 IX86_BUILTIN_PMINUD256_MASK,
30073 IX86_BUILTIN_PMAXSD128_MASK,
30074 IX86_BUILTIN_PMINSD128_MASK,
30075 IX86_BUILTIN_PMAXUD128_MASK,
30076 IX86_BUILTIN_PMINUD128_MASK,
30077 IX86_BUILTIN_PMAXSQ256_MASK,
30078 IX86_BUILTIN_PMINSQ256_MASK,
30079 IX86_BUILTIN_PMAXUQ256_MASK,
30080 IX86_BUILTIN_PMINUQ256_MASK,
30081 IX86_BUILTIN_PMAXSQ128_MASK,
30082 IX86_BUILTIN_PMINSQ128_MASK,
30083 IX86_BUILTIN_PMAXUQ128_MASK,
30084 IX86_BUILTIN_PMINUQ128_MASK,
30085 IX86_BUILTIN_PMINSB256_MASK,
30086 IX86_BUILTIN_PMINUB256_MASK,
30087 IX86_BUILTIN_PMAXSB256_MASK,
30088 IX86_BUILTIN_PMAXUB256_MASK,
30089 IX86_BUILTIN_PMINSB128_MASK,
30090 IX86_BUILTIN_PMINUB128_MASK,
30091 IX86_BUILTIN_PMAXSB128_MASK,
30092 IX86_BUILTIN_PMAXUB128_MASK,
30093 IX86_BUILTIN_PMINSW256_MASK,
30094 IX86_BUILTIN_PMINUW256_MASK,
30095 IX86_BUILTIN_PMAXSW256_MASK,
30096 IX86_BUILTIN_PMAXUW256_MASK,
30097 IX86_BUILTIN_PMINSW128_MASK,
30098 IX86_BUILTIN_PMINUW128_MASK,
30099 IX86_BUILTIN_PMAXSW128_MASK,
30100 IX86_BUILTIN_PMAXUW128_MASK,
30101 IX86_BUILTIN_VPCONFLICTQ256,
30102 IX86_BUILTIN_VPCONFLICTD256,
30103 IX86_BUILTIN_VPCLZCNTQ256,
30104 IX86_BUILTIN_VPCLZCNTD256,
30105 IX86_BUILTIN_UNPCKHPD256_MASK,
30106 IX86_BUILTIN_UNPCKHPD128_MASK,
30107 IX86_BUILTIN_UNPCKHPS256_MASK,
30108 IX86_BUILTIN_UNPCKHPS128_MASK,
30109 IX86_BUILTIN_UNPCKLPD256_MASK,
30110 IX86_BUILTIN_UNPCKLPD128_MASK,
30111 IX86_BUILTIN_UNPCKLPS256_MASK,
30112 IX86_BUILTIN_VPCONFLICTQ128,
30113 IX86_BUILTIN_VPCONFLICTD128,
30114 IX86_BUILTIN_VPCLZCNTQ128,
30115 IX86_BUILTIN_VPCLZCNTD128,
30116 IX86_BUILTIN_UNPCKLPS128_MASK,
30117 IX86_BUILTIN_ALIGND256,
30118 IX86_BUILTIN_ALIGNQ256,
30119 IX86_BUILTIN_ALIGND128,
30120 IX86_BUILTIN_ALIGNQ128,
30121 IX86_BUILTIN_CVTPS2PH256_MASK,
30122 IX86_BUILTIN_CVTPS2PH_MASK,
30123 IX86_BUILTIN_CVTPH2PS_MASK,
30124 IX86_BUILTIN_CVTPH2PS256_MASK,
30125 IX86_BUILTIN_PUNPCKHDQ128_MASK,
30126 IX86_BUILTIN_PUNPCKHDQ256_MASK,
30127 IX86_BUILTIN_PUNPCKHQDQ128_MASK,
30128 IX86_BUILTIN_PUNPCKHQDQ256_MASK,
30129 IX86_BUILTIN_PUNPCKLDQ128_MASK,
30130 IX86_BUILTIN_PUNPCKLDQ256_MASK,
30131 IX86_BUILTIN_PUNPCKLQDQ128_MASK,
30132 IX86_BUILTIN_PUNPCKLQDQ256_MASK,
30133 IX86_BUILTIN_PUNPCKHBW128_MASK,
30134 IX86_BUILTIN_PUNPCKHBW256_MASK,
30135 IX86_BUILTIN_PUNPCKHWD128_MASK,
30136 IX86_BUILTIN_PUNPCKHWD256_MASK,
30137 IX86_BUILTIN_PUNPCKLBW128_MASK,
30138 IX86_BUILTIN_PUNPCKLBW256_MASK,
30139 IX86_BUILTIN_PUNPCKLWD128_MASK,
30140 IX86_BUILTIN_PUNPCKLWD256_MASK,
30141 IX86_BUILTIN_PSLLVV16HI,
30142 IX86_BUILTIN_PSLLVV8HI,
30143 IX86_BUILTIN_PACKSSDW256_MASK,
30144 IX86_BUILTIN_PACKSSDW128_MASK,
30145 IX86_BUILTIN_PACKUSDW256_MASK,
30146 IX86_BUILTIN_PACKUSDW128_MASK,
30147 IX86_BUILTIN_PAVGB256_MASK,
30148 IX86_BUILTIN_PAVGW256_MASK,
30149 IX86_BUILTIN_PAVGB128_MASK,
30150 IX86_BUILTIN_PAVGW128_MASK,
30151 IX86_BUILTIN_VPERMVARSF256_MASK,
30152 IX86_BUILTIN_VPERMVARDF256_MASK,
30153 IX86_BUILTIN_VPERMDF256_MASK,
30154 IX86_BUILTIN_PABSB256_MASK,
30155 IX86_BUILTIN_PABSB128_MASK,
30156 IX86_BUILTIN_PABSW256_MASK,
30157 IX86_BUILTIN_PABSW128_MASK,
30158 IX86_BUILTIN_VPERMILVARPD_MASK,
30159 IX86_BUILTIN_VPERMILVARPS_MASK,
30160 IX86_BUILTIN_VPERMILVARPD256_MASK,
30161 IX86_BUILTIN_VPERMILVARPS256_MASK,
30162 IX86_BUILTIN_VPERMILPD_MASK,
30163 IX86_BUILTIN_VPERMILPS_MASK,
30164 IX86_BUILTIN_VPERMILPD256_MASK,
30165 IX86_BUILTIN_VPERMILPS256_MASK,
30166 IX86_BUILTIN_BLENDMQ256,
30167 IX86_BUILTIN_BLENDMD256,
30168 IX86_BUILTIN_BLENDMPD256,
30169 IX86_BUILTIN_BLENDMPS256,
30170 IX86_BUILTIN_BLENDMQ128,
30171 IX86_BUILTIN_BLENDMD128,
30172 IX86_BUILTIN_BLENDMPD128,
30173 IX86_BUILTIN_BLENDMPS128,
30174 IX86_BUILTIN_BLENDMW256,
30175 IX86_BUILTIN_BLENDMB256,
30176 IX86_BUILTIN_BLENDMW128,
30177 IX86_BUILTIN_BLENDMB128,
30178 IX86_BUILTIN_PMULLD256_MASK,
30179 IX86_BUILTIN_PMULLD128_MASK,
30180 IX86_BUILTIN_PMULUDQ256_MASK,
30181 IX86_BUILTIN_PMULDQ256_MASK,
30182 IX86_BUILTIN_PMULDQ128_MASK,
30183 IX86_BUILTIN_PMULUDQ128_MASK,
30184 IX86_BUILTIN_CVTPD2PS256_MASK,
30185 IX86_BUILTIN_CVTPD2PS_MASK,
30186 IX86_BUILTIN_VPERMVARSI256_MASK,
30187 IX86_BUILTIN_VPERMVARDI256_MASK,
30188 IX86_BUILTIN_VPERMDI256_MASK,
30189 IX86_BUILTIN_CMPQ256,
30190 IX86_BUILTIN_CMPD256,
30191 IX86_BUILTIN_UCMPQ256,
30192 IX86_BUILTIN_UCMPD256,
30193 IX86_BUILTIN_CMPB256,
30194 IX86_BUILTIN_CMPW256,
30195 IX86_BUILTIN_UCMPB256,
30196 IX86_BUILTIN_UCMPW256,
30197 IX86_BUILTIN_CMPPD256_MASK,
30198 IX86_BUILTIN_CMPPS256_MASK,
30199 IX86_BUILTIN_CMPQ128,
30200 IX86_BUILTIN_CMPD128,
30201 IX86_BUILTIN_UCMPQ128,
30202 IX86_BUILTIN_UCMPD128,
30203 IX86_BUILTIN_CMPB128,
30204 IX86_BUILTIN_CMPW128,
30205 IX86_BUILTIN_UCMPB128,
30206 IX86_BUILTIN_UCMPW128,
30207 IX86_BUILTIN_CMPPD128_MASK,
30208 IX86_BUILTIN_CMPPS128_MASK,
30210 IX86_BUILTIN_GATHER3SIV8SF,
30211 IX86_BUILTIN_GATHER3SIV4SF,
30212 IX86_BUILTIN_GATHER3SIV4DF,
30213 IX86_BUILTIN_GATHER3SIV2DF,
30214 IX86_BUILTIN_GATHER3DIV8SF,
30215 IX86_BUILTIN_GATHER3DIV4SF,
30216 IX86_BUILTIN_GATHER3DIV4DF,
30217 IX86_BUILTIN_GATHER3DIV2DF,
30218 IX86_BUILTIN_GATHER3SIV8SI,
30219 IX86_BUILTIN_GATHER3SIV4SI,
30220 IX86_BUILTIN_GATHER3SIV4DI,
30221 IX86_BUILTIN_GATHER3SIV2DI,
30222 IX86_BUILTIN_GATHER3DIV8SI,
30223 IX86_BUILTIN_GATHER3DIV4SI,
30224 IX86_BUILTIN_GATHER3DIV4DI,
30225 IX86_BUILTIN_GATHER3DIV2DI,
30226 IX86_BUILTIN_SCATTERSIV8SF,
30227 IX86_BUILTIN_SCATTERSIV4SF,
30228 IX86_BUILTIN_SCATTERSIV4DF,
30229 IX86_BUILTIN_SCATTERSIV2DF,
30230 IX86_BUILTIN_SCATTERDIV8SF,
30231 IX86_BUILTIN_SCATTERDIV4SF,
30232 IX86_BUILTIN_SCATTERDIV4DF,
30233 IX86_BUILTIN_SCATTERDIV2DF,
30234 IX86_BUILTIN_SCATTERSIV8SI,
30235 IX86_BUILTIN_SCATTERSIV4SI,
30236 IX86_BUILTIN_SCATTERSIV4DI,
30237 IX86_BUILTIN_SCATTERSIV2DI,
30238 IX86_BUILTIN_SCATTERDIV8SI,
30239 IX86_BUILTIN_SCATTERDIV4SI,
30240 IX86_BUILTIN_SCATTERDIV4DI,
30241 IX86_BUILTIN_SCATTERDIV2DI,
30243 /* AVX512DQ. */
30244 IX86_BUILTIN_RANGESD128,
30245 IX86_BUILTIN_RANGESS128,
30246 IX86_BUILTIN_KUNPCKWD,
30247 IX86_BUILTIN_KUNPCKDQ,
30248 IX86_BUILTIN_BROADCASTF32x2_512,
30249 IX86_BUILTIN_BROADCASTI32x2_512,
30250 IX86_BUILTIN_BROADCASTF64X2_512,
30251 IX86_BUILTIN_BROADCASTI64X2_512,
30252 IX86_BUILTIN_BROADCASTF32X8_512,
30253 IX86_BUILTIN_BROADCASTI32X8_512,
30254 IX86_BUILTIN_EXTRACTF64X2_512,
30255 IX86_BUILTIN_EXTRACTF32X8,
30256 IX86_BUILTIN_EXTRACTI64X2_512,
30257 IX86_BUILTIN_EXTRACTI32X8,
30258 IX86_BUILTIN_REDUCEPD512_MASK,
30259 IX86_BUILTIN_REDUCEPS512_MASK,
30260 IX86_BUILTIN_PMULLQ512,
30261 IX86_BUILTIN_XORPD512,
30262 IX86_BUILTIN_XORPS512,
30263 IX86_BUILTIN_ORPD512,
30264 IX86_BUILTIN_ORPS512,
30265 IX86_BUILTIN_ANDPD512,
30266 IX86_BUILTIN_ANDPS512,
30267 IX86_BUILTIN_ANDNPD512,
30268 IX86_BUILTIN_ANDNPS512,
30269 IX86_BUILTIN_INSERTF32X8,
30270 IX86_BUILTIN_INSERTI32X8,
30271 IX86_BUILTIN_INSERTF64X2_512,
30272 IX86_BUILTIN_INSERTI64X2_512,
30273 IX86_BUILTIN_FPCLASSPD512,
30274 IX86_BUILTIN_FPCLASSPS512,
30275 IX86_BUILTIN_CVTD2MASK512,
30276 IX86_BUILTIN_CVTQ2MASK512,
30277 IX86_BUILTIN_CVTMASK2D512,
30278 IX86_BUILTIN_CVTMASK2Q512,
30279 IX86_BUILTIN_CVTPD2QQ512,
30280 IX86_BUILTIN_CVTPS2QQ512,
30281 IX86_BUILTIN_CVTPD2UQQ512,
30282 IX86_BUILTIN_CVTPS2UQQ512,
30283 IX86_BUILTIN_CVTQQ2PS512,
30284 IX86_BUILTIN_CVTUQQ2PS512,
30285 IX86_BUILTIN_CVTQQ2PD512,
30286 IX86_BUILTIN_CVTUQQ2PD512,
30287 IX86_BUILTIN_CVTTPS2QQ512,
30288 IX86_BUILTIN_CVTTPS2UQQ512,
30289 IX86_BUILTIN_CVTTPD2QQ512,
30290 IX86_BUILTIN_CVTTPD2UQQ512,
30291 IX86_BUILTIN_RANGEPS512,
30292 IX86_BUILTIN_RANGEPD512,
30294 /* AVX512BW. */
30295 IX86_BUILTIN_PACKUSDW512,
30296 IX86_BUILTIN_PACKSSDW512,
30297 IX86_BUILTIN_LOADDQUHI512_MASK,
30298 IX86_BUILTIN_LOADDQUQI512_MASK,
30299 IX86_BUILTIN_PSLLDQ512,
30300 IX86_BUILTIN_PSRLDQ512,
30301 IX86_BUILTIN_STOREDQUHI512_MASK,
30302 IX86_BUILTIN_STOREDQUQI512_MASK,
30303 IX86_BUILTIN_PALIGNR512,
30304 IX86_BUILTIN_PALIGNR512_MASK,
30305 IX86_BUILTIN_MOVDQUHI512_MASK,
30306 IX86_BUILTIN_MOVDQUQI512_MASK,
30307 IX86_BUILTIN_PSADBW512,
30308 IX86_BUILTIN_DBPSADBW512,
30309 IX86_BUILTIN_PBROADCASTB512,
30310 IX86_BUILTIN_PBROADCASTB512_GPR,
30311 IX86_BUILTIN_PBROADCASTW512,
30312 IX86_BUILTIN_PBROADCASTW512_GPR,
30313 IX86_BUILTIN_PMOVSXBW512_MASK,
30314 IX86_BUILTIN_PMOVZXBW512_MASK,
30315 IX86_BUILTIN_VPERMVARHI512_MASK,
30316 IX86_BUILTIN_VPERMT2VARHI512,
30317 IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
30318 IX86_BUILTIN_VPERMI2VARHI512,
30319 IX86_BUILTIN_PAVGB512,
30320 IX86_BUILTIN_PAVGW512,
30321 IX86_BUILTIN_PADDB512,
30322 IX86_BUILTIN_PSUBB512,
30323 IX86_BUILTIN_PSUBSB512,
30324 IX86_BUILTIN_PADDSB512,
30325 IX86_BUILTIN_PSUBUSB512,
30326 IX86_BUILTIN_PADDUSB512,
30327 IX86_BUILTIN_PSUBW512,
30328 IX86_BUILTIN_PADDW512,
30329 IX86_BUILTIN_PSUBSW512,
30330 IX86_BUILTIN_PADDSW512,
30331 IX86_BUILTIN_PSUBUSW512,
30332 IX86_BUILTIN_PADDUSW512,
30333 IX86_BUILTIN_PMAXUW512,
30334 IX86_BUILTIN_PMAXSW512,
30335 IX86_BUILTIN_PMINUW512,
30336 IX86_BUILTIN_PMINSW512,
30337 IX86_BUILTIN_PMAXUB512,
30338 IX86_BUILTIN_PMAXSB512,
30339 IX86_BUILTIN_PMINUB512,
30340 IX86_BUILTIN_PMINSB512,
30341 IX86_BUILTIN_PMOVWB512,
30342 IX86_BUILTIN_PMOVSWB512,
30343 IX86_BUILTIN_PMOVUSWB512,
30344 IX86_BUILTIN_PMULHRSW512_MASK,
30345 IX86_BUILTIN_PMULHUW512_MASK,
30346 IX86_BUILTIN_PMULHW512_MASK,
30347 IX86_BUILTIN_PMULLW512_MASK,
30348 IX86_BUILTIN_PSLLWI512_MASK,
30349 IX86_BUILTIN_PSLLW512_MASK,
30350 IX86_BUILTIN_PACKSSWB512,
30351 IX86_BUILTIN_PACKUSWB512,
30352 IX86_BUILTIN_PSRAVV32HI,
30353 IX86_BUILTIN_PMADDUBSW512_MASK,
30354 IX86_BUILTIN_PMADDWD512_MASK,
30355 IX86_BUILTIN_PSRLVV32HI,
30356 IX86_BUILTIN_PUNPCKHBW512,
30357 IX86_BUILTIN_PUNPCKHWD512,
30358 IX86_BUILTIN_PUNPCKLBW512,
30359 IX86_BUILTIN_PUNPCKLWD512,
30360 IX86_BUILTIN_PSHUFB512,
30361 IX86_BUILTIN_PSHUFHW512,
30362 IX86_BUILTIN_PSHUFLW512,
30363 IX86_BUILTIN_PSRAWI512,
30364 IX86_BUILTIN_PSRAW512,
30365 IX86_BUILTIN_PSRLWI512,
30366 IX86_BUILTIN_PSRLW512,
30367 IX86_BUILTIN_CVTB2MASK512,
30368 IX86_BUILTIN_CVTW2MASK512,
30369 IX86_BUILTIN_CVTMASK2B512,
30370 IX86_BUILTIN_CVTMASK2W512,
30371 IX86_BUILTIN_PCMPEQB512_MASK,
30372 IX86_BUILTIN_PCMPEQW512_MASK,
30373 IX86_BUILTIN_PCMPGTB512_MASK,
30374 IX86_BUILTIN_PCMPGTW512_MASK,
30375 IX86_BUILTIN_PTESTMB512,
30376 IX86_BUILTIN_PTESTMW512,
30377 IX86_BUILTIN_PTESTNMB512,
30378 IX86_BUILTIN_PTESTNMW512,
30379 IX86_BUILTIN_PSLLVV32HI,
30380 IX86_BUILTIN_PABSB512,
30381 IX86_BUILTIN_PABSW512,
30382 IX86_BUILTIN_BLENDMW512,
30383 IX86_BUILTIN_BLENDMB512,
30384 IX86_BUILTIN_CMPB512,
30385 IX86_BUILTIN_CMPW512,
30386 IX86_BUILTIN_UCMPB512,
30387 IX86_BUILTIN_UCMPW512,
30389 /* Alternate 4 and 8 element gather/scatter for the vectorizer
30390 where all operands are 32-byte or 64-byte wide respectively. */
30391 IX86_BUILTIN_GATHERALTSIV4DF,
30392 IX86_BUILTIN_GATHERALTDIV8SF,
30393 IX86_BUILTIN_GATHERALTSIV4DI,
30394 IX86_BUILTIN_GATHERALTDIV8SI,
30395 IX86_BUILTIN_GATHER3ALTDIV16SF,
30396 IX86_BUILTIN_GATHER3ALTDIV16SI,
30397 IX86_BUILTIN_GATHER3ALTSIV4DF,
30398 IX86_BUILTIN_GATHER3ALTDIV8SF,
30399 IX86_BUILTIN_GATHER3ALTSIV4DI,
30400 IX86_BUILTIN_GATHER3ALTDIV8SI,
30401 IX86_BUILTIN_GATHER3ALTSIV8DF,
30402 IX86_BUILTIN_GATHER3ALTSIV8DI,
30403 IX86_BUILTIN_GATHER3DIV16SF,
30404 IX86_BUILTIN_GATHER3DIV16SI,
30405 IX86_BUILTIN_GATHER3DIV8DF,
30406 IX86_BUILTIN_GATHER3DIV8DI,
30407 IX86_BUILTIN_GATHER3SIV16SF,
30408 IX86_BUILTIN_GATHER3SIV16SI,
30409 IX86_BUILTIN_GATHER3SIV8DF,
30410 IX86_BUILTIN_GATHER3SIV8DI,
30411 IX86_BUILTIN_SCATTERDIV16SF,
30412 IX86_BUILTIN_SCATTERDIV16SI,
30413 IX86_BUILTIN_SCATTERDIV8DF,
30414 IX86_BUILTIN_SCATTERDIV8DI,
30415 IX86_BUILTIN_SCATTERSIV16SF,
30416 IX86_BUILTIN_SCATTERSIV16SI,
30417 IX86_BUILTIN_SCATTERSIV8DF,
30418 IX86_BUILTIN_SCATTERSIV8DI,
30420 /* AVX512PF */
30421 IX86_BUILTIN_GATHERPFQPD,
30422 IX86_BUILTIN_GATHERPFDPS,
30423 IX86_BUILTIN_GATHERPFDPD,
30424 IX86_BUILTIN_GATHERPFQPS,
30425 IX86_BUILTIN_SCATTERPFDPD,
30426 IX86_BUILTIN_SCATTERPFDPS,
30427 IX86_BUILTIN_SCATTERPFQPD,
30428 IX86_BUILTIN_SCATTERPFQPS,
30430 /* AVX-512ER */
30431 IX86_BUILTIN_EXP2PD_MASK,
30432 IX86_BUILTIN_EXP2PS_MASK,
30433 IX86_BUILTIN_EXP2PS,
30434 IX86_BUILTIN_RCP28PD,
30435 IX86_BUILTIN_RCP28PS,
30436 IX86_BUILTIN_RCP28SD,
30437 IX86_BUILTIN_RCP28SS,
30438 IX86_BUILTIN_RSQRT28PD,
30439 IX86_BUILTIN_RSQRT28PS,
30440 IX86_BUILTIN_RSQRT28SD,
30441 IX86_BUILTIN_RSQRT28SS,
30443 /* AVX-512IFMA */
30444 IX86_BUILTIN_VPMADD52LUQ512,
30445 IX86_BUILTIN_VPMADD52HUQ512,
30446 IX86_BUILTIN_VPMADD52LUQ256,
30447 IX86_BUILTIN_VPMADD52HUQ256,
30448 IX86_BUILTIN_VPMADD52LUQ128,
30449 IX86_BUILTIN_VPMADD52HUQ128,
30450 IX86_BUILTIN_VPMADD52LUQ512_MASKZ,
30451 IX86_BUILTIN_VPMADD52HUQ512_MASKZ,
30452 IX86_BUILTIN_VPMADD52LUQ256_MASKZ,
30453 IX86_BUILTIN_VPMADD52HUQ256_MASKZ,
30454 IX86_BUILTIN_VPMADD52LUQ128_MASKZ,
30455 IX86_BUILTIN_VPMADD52HUQ128_MASKZ,
30457 /* AVX-512VBMI */
30458 IX86_BUILTIN_VPMULTISHIFTQB512,
30459 IX86_BUILTIN_VPMULTISHIFTQB256,
30460 IX86_BUILTIN_VPMULTISHIFTQB128,
30461 IX86_BUILTIN_VPERMVARQI512_MASK,
30462 IX86_BUILTIN_VPERMT2VARQI512,
30463 IX86_BUILTIN_VPERMT2VARQI512_MASKZ,
30464 IX86_BUILTIN_VPERMI2VARQI512,
30465 IX86_BUILTIN_VPERMVARQI256_MASK,
30466 IX86_BUILTIN_VPERMVARQI128_MASK,
30467 IX86_BUILTIN_VPERMT2VARQI256,
30468 IX86_BUILTIN_VPERMT2VARQI256_MASKZ,
30469 IX86_BUILTIN_VPERMT2VARQI128,
30470 IX86_BUILTIN_VPERMT2VARQI128_MASKZ,
30471 IX86_BUILTIN_VPERMI2VARQI256,
30472 IX86_BUILTIN_VPERMI2VARQI128,
30474 /* SHA builtins. */
30475 IX86_BUILTIN_SHA1MSG1,
30476 IX86_BUILTIN_SHA1MSG2,
30477 IX86_BUILTIN_SHA1NEXTE,
30478 IX86_BUILTIN_SHA1RNDS4,
30479 IX86_BUILTIN_SHA256MSG1,
30480 IX86_BUILTIN_SHA256MSG2,
30481 IX86_BUILTIN_SHA256RNDS2,
30483 /* CLWB instructions. */
30484 IX86_BUILTIN_CLWB,
30486 /* PCOMMIT instructions. */
30487 IX86_BUILTIN_PCOMMIT,
30489 /* CLFLUSHOPT instructions. */
30490 IX86_BUILTIN_CLFLUSHOPT,
30492 /* TFmode support builtins. */
30493 IX86_BUILTIN_INFQ,
30494 IX86_BUILTIN_HUGE_VALQ,
30495 IX86_BUILTIN_FABSQ,
30496 IX86_BUILTIN_COPYSIGNQ,
30498 /* Vectorizer support builtins. */
30499 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
30500 IX86_BUILTIN_CPYSGNPS,
30501 IX86_BUILTIN_CPYSGNPD,
30502 IX86_BUILTIN_CPYSGNPS256,
30503 IX86_BUILTIN_CPYSGNPS512,
30504 IX86_BUILTIN_CPYSGNPD256,
30505 IX86_BUILTIN_CPYSGNPD512,
30506 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
30507 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
30510 /* FMA4 instructions. */
30511 IX86_BUILTIN_VFMADDSS,
30512 IX86_BUILTIN_VFMADDSD,
30513 IX86_BUILTIN_VFMADDPS,
30514 IX86_BUILTIN_VFMADDPD,
30515 IX86_BUILTIN_VFMADDPS256,
30516 IX86_BUILTIN_VFMADDPD256,
30517 IX86_BUILTIN_VFMADDSUBPS,
30518 IX86_BUILTIN_VFMADDSUBPD,
30519 IX86_BUILTIN_VFMADDSUBPS256,
30520 IX86_BUILTIN_VFMADDSUBPD256,
30522 /* FMA3 instructions. */
30523 IX86_BUILTIN_VFMADDSS3,
30524 IX86_BUILTIN_VFMADDSD3,
30526 /* XOP instructions. */
30527 IX86_BUILTIN_VPCMOV,
30528 IX86_BUILTIN_VPCMOV_V2DI,
30529 IX86_BUILTIN_VPCMOV_V4SI,
30530 IX86_BUILTIN_VPCMOV_V8HI,
30531 IX86_BUILTIN_VPCMOV_V16QI,
30532 IX86_BUILTIN_VPCMOV_V4SF,
30533 IX86_BUILTIN_VPCMOV_V2DF,
30534 IX86_BUILTIN_VPCMOV256,
30535 IX86_BUILTIN_VPCMOV_V4DI256,
30536 IX86_BUILTIN_VPCMOV_V8SI256,
30537 IX86_BUILTIN_VPCMOV_V16HI256,
30538 IX86_BUILTIN_VPCMOV_V32QI256,
30539 IX86_BUILTIN_VPCMOV_V8SF256,
30540 IX86_BUILTIN_VPCMOV_V4DF256,
30542 IX86_BUILTIN_VPPERM,
30544 IX86_BUILTIN_VPMACSSWW,
30545 IX86_BUILTIN_VPMACSWW,
30546 IX86_BUILTIN_VPMACSSWD,
30547 IX86_BUILTIN_VPMACSWD,
30548 IX86_BUILTIN_VPMACSSDD,
30549 IX86_BUILTIN_VPMACSDD,
30550 IX86_BUILTIN_VPMACSSDQL,
30551 IX86_BUILTIN_VPMACSSDQH,
30552 IX86_BUILTIN_VPMACSDQL,
30553 IX86_BUILTIN_VPMACSDQH,
30554 IX86_BUILTIN_VPMADCSSWD,
30555 IX86_BUILTIN_VPMADCSWD,
30557 IX86_BUILTIN_VPHADDBW,
30558 IX86_BUILTIN_VPHADDBD,
30559 IX86_BUILTIN_VPHADDBQ,
30560 IX86_BUILTIN_VPHADDWD,
30561 IX86_BUILTIN_VPHADDWQ,
30562 IX86_BUILTIN_VPHADDDQ,
30563 IX86_BUILTIN_VPHADDUBW,
30564 IX86_BUILTIN_VPHADDUBD,
30565 IX86_BUILTIN_VPHADDUBQ,
30566 IX86_BUILTIN_VPHADDUWD,
30567 IX86_BUILTIN_VPHADDUWQ,
30568 IX86_BUILTIN_VPHADDUDQ,
30569 IX86_BUILTIN_VPHSUBBW,
30570 IX86_BUILTIN_VPHSUBWD,
30571 IX86_BUILTIN_VPHSUBDQ,
30573 IX86_BUILTIN_VPROTB,
30574 IX86_BUILTIN_VPROTW,
30575 IX86_BUILTIN_VPROTD,
30576 IX86_BUILTIN_VPROTQ,
30577 IX86_BUILTIN_VPROTB_IMM,
30578 IX86_BUILTIN_VPROTW_IMM,
30579 IX86_BUILTIN_VPROTD_IMM,
30580 IX86_BUILTIN_VPROTQ_IMM,
30582 IX86_BUILTIN_VPSHLB,
30583 IX86_BUILTIN_VPSHLW,
30584 IX86_BUILTIN_VPSHLD,
30585 IX86_BUILTIN_VPSHLQ,
30586 IX86_BUILTIN_VPSHAB,
30587 IX86_BUILTIN_VPSHAW,
30588 IX86_BUILTIN_VPSHAD,
30589 IX86_BUILTIN_VPSHAQ,
30591 IX86_BUILTIN_VFRCZSS,
30592 IX86_BUILTIN_VFRCZSD,
30593 IX86_BUILTIN_VFRCZPS,
30594 IX86_BUILTIN_VFRCZPD,
30595 IX86_BUILTIN_VFRCZPS256,
30596 IX86_BUILTIN_VFRCZPD256,
30598 IX86_BUILTIN_VPCOMEQUB,
30599 IX86_BUILTIN_VPCOMNEUB,
30600 IX86_BUILTIN_VPCOMLTUB,
30601 IX86_BUILTIN_VPCOMLEUB,
30602 IX86_BUILTIN_VPCOMGTUB,
30603 IX86_BUILTIN_VPCOMGEUB,
30604 IX86_BUILTIN_VPCOMFALSEUB,
30605 IX86_BUILTIN_VPCOMTRUEUB,
30607 IX86_BUILTIN_VPCOMEQUW,
30608 IX86_BUILTIN_VPCOMNEUW,
30609 IX86_BUILTIN_VPCOMLTUW,
30610 IX86_BUILTIN_VPCOMLEUW,
30611 IX86_BUILTIN_VPCOMGTUW,
30612 IX86_BUILTIN_VPCOMGEUW,
30613 IX86_BUILTIN_VPCOMFALSEUW,
30614 IX86_BUILTIN_VPCOMTRUEUW,
30616 IX86_BUILTIN_VPCOMEQUD,
30617 IX86_BUILTIN_VPCOMNEUD,
30618 IX86_BUILTIN_VPCOMLTUD,
30619 IX86_BUILTIN_VPCOMLEUD,
30620 IX86_BUILTIN_VPCOMGTUD,
30621 IX86_BUILTIN_VPCOMGEUD,
30622 IX86_BUILTIN_VPCOMFALSEUD,
30623 IX86_BUILTIN_VPCOMTRUEUD,
30625 IX86_BUILTIN_VPCOMEQUQ,
30626 IX86_BUILTIN_VPCOMNEUQ,
30627 IX86_BUILTIN_VPCOMLTUQ,
30628 IX86_BUILTIN_VPCOMLEUQ,
30629 IX86_BUILTIN_VPCOMGTUQ,
30630 IX86_BUILTIN_VPCOMGEUQ,
30631 IX86_BUILTIN_VPCOMFALSEUQ,
30632 IX86_BUILTIN_VPCOMTRUEUQ,
30634 IX86_BUILTIN_VPCOMEQB,
30635 IX86_BUILTIN_VPCOMNEB,
30636 IX86_BUILTIN_VPCOMLTB,
30637 IX86_BUILTIN_VPCOMLEB,
30638 IX86_BUILTIN_VPCOMGTB,
30639 IX86_BUILTIN_VPCOMGEB,
30640 IX86_BUILTIN_VPCOMFALSEB,
30641 IX86_BUILTIN_VPCOMTRUEB,
30643 IX86_BUILTIN_VPCOMEQW,
30644 IX86_BUILTIN_VPCOMNEW,
30645 IX86_BUILTIN_VPCOMLTW,
30646 IX86_BUILTIN_VPCOMLEW,
30647 IX86_BUILTIN_VPCOMGTW,
30648 IX86_BUILTIN_VPCOMGEW,
30649 IX86_BUILTIN_VPCOMFALSEW,
30650 IX86_BUILTIN_VPCOMTRUEW,
30652 IX86_BUILTIN_VPCOMEQD,
30653 IX86_BUILTIN_VPCOMNED,
30654 IX86_BUILTIN_VPCOMLTD,
30655 IX86_BUILTIN_VPCOMLED,
30656 IX86_BUILTIN_VPCOMGTD,
30657 IX86_BUILTIN_VPCOMGED,
30658 IX86_BUILTIN_VPCOMFALSED,
30659 IX86_BUILTIN_VPCOMTRUED,
30661 IX86_BUILTIN_VPCOMEQQ,
30662 IX86_BUILTIN_VPCOMNEQ,
30663 IX86_BUILTIN_VPCOMLTQ,
30664 IX86_BUILTIN_VPCOMLEQ,
30665 IX86_BUILTIN_VPCOMGTQ,
30666 IX86_BUILTIN_VPCOMGEQ,
30667 IX86_BUILTIN_VPCOMFALSEQ,
30668 IX86_BUILTIN_VPCOMTRUEQ,
30670 /* LWP instructions. */
30671 IX86_BUILTIN_LLWPCB,
30672 IX86_BUILTIN_SLWPCB,
30673 IX86_BUILTIN_LWPVAL32,
30674 IX86_BUILTIN_LWPVAL64,
30675 IX86_BUILTIN_LWPINS32,
30676 IX86_BUILTIN_LWPINS64,
30678 IX86_BUILTIN_CLZS,
30680 /* RTM */
30681 IX86_BUILTIN_XBEGIN,
30682 IX86_BUILTIN_XEND,
30683 IX86_BUILTIN_XABORT,
30684 IX86_BUILTIN_XTEST,
30686 /* MPX */
30687 IX86_BUILTIN_BNDMK,
30688 IX86_BUILTIN_BNDSTX,
30689 IX86_BUILTIN_BNDLDX,
30690 IX86_BUILTIN_BNDCL,
30691 IX86_BUILTIN_BNDCU,
30692 IX86_BUILTIN_BNDRET,
30693 IX86_BUILTIN_BNDNARROW,
30694 IX86_BUILTIN_BNDINT,
30695 IX86_BUILTIN_SIZEOF,
30696 IX86_BUILTIN_BNDLOWER,
30697 IX86_BUILTIN_BNDUPPER,
30699 /* BMI instructions. */
30700 IX86_BUILTIN_BEXTR32,
30701 IX86_BUILTIN_BEXTR64,
30702 IX86_BUILTIN_CTZS,
30704 /* TBM instructions. */
30705 IX86_BUILTIN_BEXTRI32,
30706 IX86_BUILTIN_BEXTRI64,
30708 /* BMI2 instructions. */
30709 IX86_BUILTIN_BZHI32,
30710 IX86_BUILTIN_BZHI64,
30711 IX86_BUILTIN_PDEP32,
30712 IX86_BUILTIN_PDEP64,
30713 IX86_BUILTIN_PEXT32,
30714 IX86_BUILTIN_PEXT64,
30716 /* ADX instructions. */
30717 IX86_BUILTIN_ADDCARRYX32,
30718 IX86_BUILTIN_ADDCARRYX64,
30720 /* SBB instructions. */
30721 IX86_BUILTIN_SBB32,
30722 IX86_BUILTIN_SBB64,
30724 /* FSGSBASE instructions. */
30725 IX86_BUILTIN_RDFSBASE32,
30726 IX86_BUILTIN_RDFSBASE64,
30727 IX86_BUILTIN_RDGSBASE32,
30728 IX86_BUILTIN_RDGSBASE64,
30729 IX86_BUILTIN_WRFSBASE32,
30730 IX86_BUILTIN_WRFSBASE64,
30731 IX86_BUILTIN_WRGSBASE32,
30732 IX86_BUILTIN_WRGSBASE64,
30734 /* RDRND instructions. */
30735 IX86_BUILTIN_RDRAND16_STEP,
30736 IX86_BUILTIN_RDRAND32_STEP,
30737 IX86_BUILTIN_RDRAND64_STEP,
30739 /* RDSEED instructions. */
30740 IX86_BUILTIN_RDSEED16_STEP,
30741 IX86_BUILTIN_RDSEED32_STEP,
30742 IX86_BUILTIN_RDSEED64_STEP,
30744 /* F16C instructions. */
30745 IX86_BUILTIN_CVTPH2PS,
30746 IX86_BUILTIN_CVTPH2PS256,
30747 IX86_BUILTIN_CVTPS2PH,
30748 IX86_BUILTIN_CVTPS2PH256,
30750 /* MONITORX and MWAITX instrucions. */
30751 IX86_BUILTIN_MONITORX,
30752 IX86_BUILTIN_MWAITX,
30754 /* CFString built-in for darwin */
30755 IX86_BUILTIN_CFSTRING,
30757 /* Builtins to get CPU type and supported features. */
30758 IX86_BUILTIN_CPU_INIT,
30759 IX86_BUILTIN_CPU_IS,
30760 IX86_BUILTIN_CPU_SUPPORTS,
30762 /* Read/write FLAGS register built-ins. */
30763 IX86_BUILTIN_READ_FLAGS,
30764 IX86_BUILTIN_WRITE_FLAGS,
30766 IX86_BUILTIN_MAX
30767 };
30769 /* Table for the ix86 builtin decls. */
30772 /* Table of all of the builtin functions that are possible with different ISA's
30773 but are waiting to be built until a function is declared to use that
30774 ISA. */
30783 };
30787 /* Bits that can still enable any inclusion of a builtin. */
30790 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
30791 of which isa_flags to use in the ix86_builtins_isa array. Stores the
30792 function decl in the ix86_builtins array. Returns the function decl or
30793 NULL_TREE, if the builtin was not added.
30795 If the front end has a special hook for builtin functions, delay adding
30796 builtin functions that aren't in the current ISA until the ISA is changed
30797 with function specific optimization. Doing so, can save about 300K for the
30798 default compiler. When the builtin is expanded, check at that time whether
30799 it is valid.
30801 If the front end doesn't have a special hook, record all builtins, even if
30802 it isn't an instruction set in the current ISA in case the user uses
30803 function specific options for a different ISA, so that we don't get scope
30804 errors if a builtin is added in the middle of a function scope. */
30810 {
30814 {
30823 {
30829 }
30830 else
30831 {
30832 /* Just a MASK where set_and_not_built_p == true can potentially
30833 include a builtin. */
30842 }
30843 }
30846 }
30848 /* Like def_builtin, but also marks the function decl "const". */
30853 {
30857 else
30861 }
30863 /* Add any new builtin functions for a given ISA that may not have been
30864 declared. This saves a bit of space compared to adding all of the
30865 declarations to the tree, even if we didn't use them. */
30867 static void
30869 {
30873 /* Bits in ISA value can be removed from potential isa values. */
30881 {
30884 {
30887 /* Don't define the builtin again. */
30893 NULL_TREE);
30900 NULL_TREE);
30903 }
30904 }
30907 }
30909 /* Bits for builtin_description.flag. */
30911 /* Set when we don't support the comparison natively, and should
30912 swap_comparison in order to support it. */
30913 #define BUILTIN_DESC_SWAP_OPERANDS 1
30915 struct builtin_description
30916 {
30923 };
30926 {
30927 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
30928 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
30929 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
30930 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
30931 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
30932 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
30933 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
30934 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
30935 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
30936 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
30937 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
30938 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
30939 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
30940 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
30941 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
30942 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
30943 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
30944 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
30945 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
30946 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
30947 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
30948 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
30949 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
30950 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
30951 };
30954 {
30955 /* SSE4.2 */
30956 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
30957 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
30958 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
30959 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
30960 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
30961 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
30962 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
30963 };
30966 {
30967 /* SSE4.2 */
30968 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
30969 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
30970 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
30971 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
30972 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
30973 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
30974 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
30975 };
30977 /* Special builtins with variable number of arguments. */
30979 {
30980 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
30981 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
30982 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
30984 /* 80387 (for use internally for atomic compound assignment). */
30985 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
30986 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
30987 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) USHORT_FTYPE_VOID },
30988 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
30990 /* MMX */
30991 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30993 /* 3DNow! */
30994 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30996 /* FXSR, XSAVE, XSAVEOPT, XSAVEC and XSAVES. */
30997 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
30998 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
30999 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
31000 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
31001 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
31002 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xsaves", IX86_BUILTIN_XSAVES, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
31003 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xrstors", IX86_BUILTIN_XRSTORS, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
31004 { OPTION_MASK_ISA_XSAVEC, CODE_FOR_nothing, "__builtin_ia32_xsavec", IX86_BUILTIN_XSAVEC, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
31006 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
31007 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
31008 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
31009 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
31010 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
31011 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaves64", IX86_BUILTIN_XSAVES64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
31012 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
31013 { OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
31015 /* SSE */
31016 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
31017 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
31018 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
31020 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
31021 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
31022 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
31023 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
31025 /* SSE or 3DNow!A */
31026 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
31027 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
31029 /* SSE2 */
31030 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
31031 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
31032 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
31033 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
31034 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
31035 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
31036 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
31037 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
31038 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
31039 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
31041 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
31042 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
31044 /* SSE3 */
31045 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
31047 /* SSE4.1 */
31048 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
31050 /* SSE4A */
31051 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
31052 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
31054 /* AVX */
31055 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
31056 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
31058 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
31059 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
31060 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
31061 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
31062 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
31064 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
31065 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
31066 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
31067 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
31068 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
31069 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
31070 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
31072 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
31073 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
31074 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
31076 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
31077 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
31078 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
31079 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
31080 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
31081 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
31082 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
31083 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
31085 /* AVX2 */
31086 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
31087 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
31088 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
31089 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
31090 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
31091 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
31092 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
31093 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
31094 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
31096 /* AVX512F */
31097 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
31098 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
31099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
31100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
31101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
31102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
31103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
31104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
31105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
31106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
31107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
31108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
31109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
31110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
31111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
31112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
31113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
31114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
31115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
31116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
31117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
31118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
31119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
31120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
31121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
31122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
31123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
31124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
31125 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
31126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
31127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
31128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
31129 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
31130 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
31131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
31132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
31133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
31134 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
31135 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
31136 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
31137 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
31138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
31139 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
31140 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
31141 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
31142 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
31143 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
31145 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
31146 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
31147 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
31148 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
31149 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
31150 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
31152 /* FSGSBASE */
31153 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
31154 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
31155 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
31156 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
31157 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
31158 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
31159 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
31160 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
31162 /* RTM */
31163 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
31164 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
31165 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
31167 /* AVX512BW */
31168 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_loaddquhi512_mask", IX86_BUILTIN_LOADDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_SI },
31169 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_loaddquqi512_mask", IX86_BUILTIN_LOADDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_DI },
31170 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv32hi_mask, "__builtin_ia32_storedquhi512_mask", IX86_BUILTIN_STOREDQUHI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV32HI_V32HI_SI },
31171 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_DI },
31173 /* AVX512VL */
31174 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_HI },
31175 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_loaddquhi128_mask", IX86_BUILTIN_LOADDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_QI },
31176 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_loaddquqi256_mask", IX86_BUILTIN_LOADDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_SI },
31177 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_loaddquqi128_mask", IX86_BUILTIN_LOADDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_HI },
31178 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64load256_mask", IX86_BUILTIN_MOVDQA64LOAD256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31179 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64load128_mask", IX86_BUILTIN_MOVDQA64LOAD128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31180 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32load256_mask", IX86_BUILTIN_MOVDQA32LOAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31181 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32load128_mask", IX86_BUILTIN_MOVDQA32LOAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31182 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4di_mask, "__builtin_ia32_movdqa64store256_mask", IX86_BUILTIN_MOVDQA64STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
31183 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2di_mask, "__builtin_ia32_movdqa64store128_mask", IX86_BUILTIN_MOVDQA64STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
31184 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8si_mask, "__builtin_ia32_movdqa32store256_mask", IX86_BUILTIN_MOVDQA32STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
31185 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4si_mask, "__builtin_ia32_movdqa32store128_mask", IX86_BUILTIN_MOVDQA32STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
31186 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_loadapd256_mask", IX86_BUILTIN_LOADAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31187 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_loadapd128_mask", IX86_BUILTIN_LOADAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31188 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_loadaps256_mask", IX86_BUILTIN_LOADAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31189 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_loadaps128_mask", IX86_BUILTIN_LOADAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31190 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4df_mask, "__builtin_ia32_storeapd256_mask", IX86_BUILTIN_STOREAPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
31191 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2df_mask, "__builtin_ia32_storeapd128_mask", IX86_BUILTIN_STOREAPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
31192 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8sf_mask, "__builtin_ia32_storeaps256_mask", IX86_BUILTIN_STOREAPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
31193 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4sf_mask, "__builtin_ia32_storeaps128_mask", IX86_BUILTIN_STOREAPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
31194 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadupd256_mask, "__builtin_ia32_loadupd256_mask", IX86_BUILTIN_LOADUPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31195 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loadupd_mask, "__builtin_ia32_loadupd128_mask", IX86_BUILTIN_LOADUPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31196 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadups256_mask, "__builtin_ia32_loadups256_mask", IX86_BUILTIN_LOADUPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31197 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_loadups_mask, "__builtin_ia32_loadups128_mask", IX86_BUILTIN_LOADUPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31198 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd256_mask, "__builtin_ia32_storeupd256_mask", IX86_BUILTIN_STOREUPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
31199 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd_mask, "__builtin_ia32_storeupd128_mask", IX86_BUILTIN_STOREUPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
31200 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups256_mask, "__builtin_ia32_storeups256_mask", IX86_BUILTIN_STOREUPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
31201 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups_mask, "__builtin_ia32_storeups128_mask", IX86_BUILTIN_STOREUPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
31202 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv4di_mask, "__builtin_ia32_loaddqudi256_mask", IX86_BUILTIN_LOADDQUDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31203 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv2di_mask, "__builtin_ia32_loaddqudi128_mask", IX86_BUILTIN_LOADDQUDI128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31204 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv8si_mask, "__builtin_ia32_loaddqusi256_mask", IX86_BUILTIN_LOADDQUSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31205 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv4si_mask, "__builtin_ia32_loaddqusi128_mask", IX86_BUILTIN_LOADDQUSI128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31206 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4di_mask, "__builtin_ia32_storedqudi256_mask", IX86_BUILTIN_STOREDQUDI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
31207 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv2di_mask, "__builtin_ia32_storedqudi128_mask", IX86_BUILTIN_STOREDQUDI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
31208 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8si_mask, "__builtin_ia32_storedqusi256_mask", IX86_BUILTIN_STOREDQUSI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
31209 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4si_mask, "__builtin_ia32_storedqusi128_mask", IX86_BUILTIN_STOREDQUSI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
31210 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16hi_mask, "__builtin_ia32_storedquhi256_mask", IX86_BUILTIN_STOREDQUHI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16HI_HI },
31211 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8hi_mask, "__builtin_ia32_storedquhi128_mask", IX86_BUILTIN_STOREDQUHI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8HI_QI },
31212 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv32qi_mask, "__builtin_ia32_storedquqi256_mask", IX86_BUILTIN_STOREDQUQI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV32QI_V32QI_SI },
31213 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16qi_mask, "__builtin_ia32_storedquqi128_mask", IX86_BUILTIN_STOREDQUQI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16QI_HI },
31214 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4df_mask, "__builtin_ia32_compressstoredf256_mask", IX86_BUILTIN_COMPRESSPDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
31215 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2df_mask, "__builtin_ia32_compressstoredf128_mask", IX86_BUILTIN_COMPRESSPDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
31216 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8sf_mask, "__builtin_ia32_compressstoresf256_mask", IX86_BUILTIN_COMPRESSPSSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
31217 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4sf_mask, "__builtin_ia32_compressstoresf128_mask", IX86_BUILTIN_COMPRESSPSSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
31218 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4di_mask, "__builtin_ia32_compressstoredi256_mask", IX86_BUILTIN_PCOMPRESSQSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
31219 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2di_mask, "__builtin_ia32_compressstoredi128_mask", IX86_BUILTIN_PCOMPRESSQSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
31220 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8si_mask, "__builtin_ia32_compressstoresi256_mask", IX86_BUILTIN_PCOMPRESSDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
31221 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4si_mask, "__builtin_ia32_compressstoresi128_mask", IX86_BUILTIN_PCOMPRESSDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
31222 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expandloaddf256_mask", IX86_BUILTIN_EXPANDPDLOAD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31223 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expandloaddf128_mask", IX86_BUILTIN_EXPANDPDLOAD128, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31224 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandloadsf256_mask", IX86_BUILTIN_EXPANDPSLOAD256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31225 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandloadsf128_mask", IX86_BUILTIN_EXPANDPSLOAD128, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31226 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expandloaddi256_mask", IX86_BUILTIN_PEXPANDQLOAD256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31227 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expandloaddi128_mask", IX86_BUILTIN_PEXPANDQLOAD128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31228 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandloadsi256_mask", IX86_BUILTIN_PEXPANDDLOAD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31229 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandloadsi128_mask", IX86_BUILTIN_PEXPANDDLOAD128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31230 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expandloaddf256_maskz", IX86_BUILTIN_EXPANDPDLOAD256Z, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31231 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expandloaddf128_maskz", IX86_BUILTIN_EXPANDPDLOAD128Z, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31232 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandloadsf256_maskz", IX86_BUILTIN_EXPANDPSLOAD256Z, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31233 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandloadsf128_maskz", IX86_BUILTIN_EXPANDPSLOAD128Z, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31234 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expandloaddi256_maskz", IX86_BUILTIN_PEXPANDQLOAD256Z, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31235 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expandloaddi128_maskz", IX86_BUILTIN_PEXPANDQLOAD128Z, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31236 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandloadsi256_maskz", IX86_BUILTIN_PEXPANDDLOAD256Z, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31237 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandloadsi128_maskz", IX86_BUILTIN_PEXPANDDLOAD128Z, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31238 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask_store, "__builtin_ia32_pmovqd256mem_mask", IX86_BUILTIN_PMOVQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
31239 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask_store, "__builtin_ia32_pmovqd128mem_mask", IX86_BUILTIN_PMOVQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
31240 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask_store, "__builtin_ia32_pmovsqd256mem_mask", IX86_BUILTIN_PMOVSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
31241 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask_store, "__builtin_ia32_pmovsqd128mem_mask", IX86_BUILTIN_PMOVSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
31242 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask_store, "__builtin_ia32_pmovusqd256mem_mask", IX86_BUILTIN_PMOVUSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
31243 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask_store, "__builtin_ia32_pmovusqd128mem_mask", IX86_BUILTIN_PMOVUSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
31244 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovqw256mem_mask", IX86_BUILTIN_PMOVQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
31245 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovqw128mem_mask", IX86_BUILTIN_PMOVQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
31246 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovsqw256mem_mask", IX86_BUILTIN_PMOVSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
31247 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovsqw128mem_mask", IX86_BUILTIN_PMOVSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
31248 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovusqw256mem_mask", IX86_BUILTIN_PMOVUSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
31249 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovusqw128mem_mask", IX86_BUILTIN_PMOVUSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
31250 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovqb256mem_mask", IX86_BUILTIN_PMOVQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
31251 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovqb128mem_mask", IX86_BUILTIN_PMOVQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
31252 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovsqb256mem_mask", IX86_BUILTIN_PMOVSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
31253 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovsqb128mem_mask", IX86_BUILTIN_PMOVSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
31254 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovusqb256mem_mask", IX86_BUILTIN_PMOVUSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
31255 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovusqb128mem_mask", IX86_BUILTIN_PMOVUSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
31256 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovdb256mem_mask", IX86_BUILTIN_PMOVDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
31257 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovdb128mem_mask", IX86_BUILTIN_PMOVDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
31258 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovsdb256mem_mask", IX86_BUILTIN_PMOVSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
31259 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovsdb128mem_mask", IX86_BUILTIN_PMOVSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
31260 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovusdb256mem_mask", IX86_BUILTIN_PMOVUSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
31261 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovusdb128mem_mask", IX86_BUILTIN_PMOVUSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
31262 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovdw256mem_mask", IX86_BUILTIN_PMOVDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
31263 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovdw128mem_mask", IX86_BUILTIN_PMOVDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
31264 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovsdw256mem_mask", IX86_BUILTIN_PMOVSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
31265 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
31266 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
31267 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
31269 /* PCOMMIT. */
31270 { OPTION_MASK_ISA_PCOMMIT, CODE_FOR_pcommit, "__builtin_ia32_pcommit", IX86_BUILTIN_PCOMMIT, UNKNOWN, (int) VOID_FTYPE_VOID },
31271 };
31273 /* Builtins with variable number of arguments. */
31275 {
31276 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
31277 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
31278 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
31279 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
31280 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
31281 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
31282 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
31284 /* MMX */
31285 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31286 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31287 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31288 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31289 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31290 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31292 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31293 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31294 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31295 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31296 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31297 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31298 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31299 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31301 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31302 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31304 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31305 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31306 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31307 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31309 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31310 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31311 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31312 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31313 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31314 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31316 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31317 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31318 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31319 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31320 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
31321 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
31323 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31324 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
31325 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31327 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
31329 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31330 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31331 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31332 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31333 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31334 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31336 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31337 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31338 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31339 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31340 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31341 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31343 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31344 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31345 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31346 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31348 /* 3DNow! */
31349 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31350 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31351 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31352 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31354 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31355 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31356 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31357 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31358 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31359 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31360 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31361 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31362 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31363 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31364 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31365 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31366 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31367 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31368 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31370 /* 3DNow!A */
31371 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31372 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31373 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31374 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31375 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31376 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31378 /* SSE */
31379 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
31380 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31381 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31382 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31383 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31384 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31385 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31386 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31387 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31388 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31389 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31390 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31392 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31394 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31395 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31396 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31397 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31398 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31399 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31400 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31401 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31403 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31404 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31405 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31406 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31407 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31408 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31409 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31410 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31411 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31412 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31413 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
31414 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31415 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31416 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31417 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31418 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31419 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31420 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31421 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31422 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31424 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31425 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31426 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31427 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31429 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31430 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31431 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31432 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31434 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31436 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31437 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31438 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31439 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31440 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31442 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
31443 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
31444 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
31446 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
31448 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31449 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31450 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31452 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
31453 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
31455 /* SSE MMX or 3Dnow!A */
31456 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31457 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31458 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31460 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31461 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31462 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31463 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31465 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
31466 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
31468 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
31470 /* SSE2 */
31471 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31473 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
31474 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
31475 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31476 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
31477 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
31479 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31480 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31481 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
31482 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31483 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31485 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
31487 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31488 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31489 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31490 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31492 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31493 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
31494 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31496 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31497 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31498 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31499 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31500 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31501 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31502 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31503 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31505 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31506 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31507 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31508 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31509 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
31510 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31511 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31512 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31513 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31514 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31515 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31516 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31517 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31518 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31519 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31520 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31521 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31522 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31523 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31524 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31526 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31527 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31528 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31529 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31531 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31532 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31533 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31534 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31536 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31538 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31539 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31540 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31542 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31544 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31545 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31546 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31547 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31548 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31549 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31550 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31551 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31553 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31554 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31555 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31556 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31557 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31558 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31559 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31560 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31562 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31563 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
31565 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31566 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31567 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31568 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31570 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31571 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31573 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31574 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31575 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31576 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31577 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31578 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31580 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31581 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31582 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31583 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31585 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31586 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31587 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31588 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31589 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31590 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31591 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31592 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31594 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31595 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31596 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31598 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31599 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
31601 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
31602 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31604 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
31606 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
31607 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
31608 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
31609 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
31611 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31612 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31613 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31614 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31615 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31616 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31617 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31619 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31620 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31621 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31622 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31623 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31624 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31625 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31627 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31628 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31629 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31630 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31632 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
31633 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31634 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31636 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
31638 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31640 /* SSE2 MMX */
31641 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31642 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31644 /* SSE3 */
31645 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
31646 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31648 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31649 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31650 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31651 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31652 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31653 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31655 /* SSSE3 */
31656 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31657 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
31658 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31659 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
31660 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31661 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31663 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31664 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31665 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31666 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31667 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31668 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31669 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31670 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31671 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31672 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31673 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31674 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31675 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
31676 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
31677 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31678 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31679 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31680 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31681 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31682 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31683 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31684 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31685 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31686 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31688 /* SSSE3. */
31689 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
31690 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
31692 /* SSE4.1 */
31693 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31694 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31695 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
31696 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
31697 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31698 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31699 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31700 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
31701 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
31702 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
31704 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31705 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31706 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31707 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31708 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31709 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31710 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31711 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31712 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31713 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31714 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31715 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31716 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31718 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31719 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31720 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31721 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31722 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31723 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31724 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31725 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31726 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31727 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31728 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31729 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31731 /* SSE4.1 */
31732 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31733 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31734 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31735 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31737 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
31738 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
31739 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
31740 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
31742 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31743 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31745 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31746 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31748 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
31749 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
31750 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
31751 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
31753 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
31754 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
31756 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31757 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31759 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31760 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31761 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31763 /* SSE4.2 */
31764 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31765 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
31766 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
31767 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31768 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31770 /* SSE4A */
31771 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
31772 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
31773 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
31774 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31776 /* AES */
31777 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
31778 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31780 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31781 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31782 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31783 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31785 /* PCLMUL */
31786 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
31788 /* AVX */
31789 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31790 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31791 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31792 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31793 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31794 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31795 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31796 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31797 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31798 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31799 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31800 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31801 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31802 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31803 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31804 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31805 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31806 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31807 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31808 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31809 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31810 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31811 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31812 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31813 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31814 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31816 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
31817 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
31818 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
31819 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31821 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31822 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31823 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
31824 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
31825 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31826 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31827 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31828 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31829 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31830 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31831 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31832 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31833 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31834 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
31835 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
31836 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
31837 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
31838 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
31839 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
31840 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31841 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
31842 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31843 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31844 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31845 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31846 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31847 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31848 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31849 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31850 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31851 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31852 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
31853 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
31854 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
31856 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31857 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31858 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31860 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31861 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31862 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31863 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31864 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31866 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31868 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31869 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31871 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
31872 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
31873 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
31874 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
31876 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31877 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31879 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31880 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31882 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
31883 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
31884 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
31885 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
31887 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
31888 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
31890 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31891 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31893 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31894 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31895 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31896 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31898 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31899 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31900 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31901 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
31902 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
31903 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
31905 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31906 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31907 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31908 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31909 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31910 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31911 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31912 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31913 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31914 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31915 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31916 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31917 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31918 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31919 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31921 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
31922 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
31924 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31925 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31927 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31929 /* AVX2 */
31930 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
31931 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
31932 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
31933 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
31934 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31935 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31936 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31937 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31938 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31939 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31940 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31941 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31942 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31943 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31944 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31945 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31946 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
31947 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31948 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31949 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31950 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31951 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
31952 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
31953 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31954 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31955 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31956 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31957 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31958 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31959 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31960 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31961 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31962 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31963 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31964 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31965 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31966 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31967 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31968 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
31969 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31970 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31971 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31972 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31973 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31974 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31975 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31976 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31977 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31978 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31979 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31980 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31981 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
31982 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31983 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31984 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31985 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31986 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31987 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31988 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31989 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31990 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31991 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31992 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31993 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31994 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31995 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31996 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31997 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31998 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31999 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32000 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
32001 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32002 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
32003 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32004 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
32005 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
32006 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
32007 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32008 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
32009 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32010 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
32011 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
32012 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
32013 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
32014 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
32015 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
32016 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
32017 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
32018 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
32019 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
32020 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
32021 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
32022 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
32023 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
32024 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
32025 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
32026 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
32027 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
32028 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32029 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
32030 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32031 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32032 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32033 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
32034 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32035 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
32036 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32037 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
32038 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32039 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32040 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32041 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
32042 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32043 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32044 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32045 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
32046 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
32047 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
32048 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
32049 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
32050 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
32051 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
32052 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
32053 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
32054 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
32055 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
32056 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
32057 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
32058 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
32059 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32060 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
32061 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
32062 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
32063 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
32064 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vextractf128v4di, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
32065 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vinsertf128v4di, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
32066 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32067 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
32068 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32069 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32070 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32071 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32072 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32073 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
32074 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32075 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32077 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
32079 /* BMI */
32080 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32081 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32082 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
32084 /* TBM */
32085 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32086 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32088 /* F16C */
32089 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
32090 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
32091 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
32092 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
32094 /* BMI2 */
32095 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32096 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32097 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32098 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32099 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32100 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32102 /* AVX512F */
32103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_256si, "__builtin_ia32_si512_256si", IX86_BUILTIN_SI512_SI256, UNKNOWN, (int) V16SI_FTYPE_V8SI },
32104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_256ps, "__builtin_ia32_ps512_256ps", IX86_BUILTIN_PS512_PS256, UNKNOWN, (int) V16SF_FTYPE_V8SF },
32105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_256pd, "__builtin_ia32_pd512_256pd", IX86_BUILTIN_PD512_PD256, UNKNOWN, (int) V8DF_FTYPE_V4DF },
32106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_si, "__builtin_ia32_si512_si", IX86_BUILTIN_SI512_SI, UNKNOWN, (int) V16SI_FTYPE_V4SI },
32107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_ps, "__builtin_ia32_ps512_ps", IX86_BUILTIN_PS512_PS, UNKNOWN, (int) V16SF_FTYPE_V4SF },
32108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_pd, "__builtin_ia32_pd512_pd", IX86_BUILTIN_PD512_PD, UNKNOWN, (int) V8DF_FTYPE_V2DF },
32109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
32110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
32111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
32116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
32117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
32118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
32119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
32120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
32121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
32122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
32123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32125 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
32126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
32127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
32128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
32129 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32130 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
32134 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
32135 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
32136 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
32137 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
32138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
32139 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
32140 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
32141 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32142 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32143 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32144 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32145 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32146 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32147 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32148 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32149 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32150 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32151 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32152 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32153 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32154 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32155 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32156 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
32157 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
32158 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
32159 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
32160 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
32161 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
32162 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
32163 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32164 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
32165 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32166 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32167 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32168 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32169 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32170 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32171 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32172 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32173 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32174 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32175 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32176 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32177 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32178 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32179 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32180 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
32181 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
32182 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
32183 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
32184 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
32185 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
32186 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
32187 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
32188 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
32189 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
32190 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
32191 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
32192 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
32193 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
32194 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
32195 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
32196 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
32197 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
32198 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
32199 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
32200 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
32201 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
32202 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
32203 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
32204 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
32205 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
32206 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32207 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
32208 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32209 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32210 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32211 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32212 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32213 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32214 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32215 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32216 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32217 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32218 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32219 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
32220 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32221 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
32222 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32223 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32224 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32225 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
32226 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32227 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
32228 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32229 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32230 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32231 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
32232 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32233 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
32234 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32235 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32236 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32237 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32238 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32239 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
32240 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32241 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
32242 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32243 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32244 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32245 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32246 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32247 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32248 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32249 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32250 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32251 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
32252 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
32253 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32254 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32255 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
32256 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
32257 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
32258 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
32259 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
32260 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
32261 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
32262 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
32263 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
32264 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
32265 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32266 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32267 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32268 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32269 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32270 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32271 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32272 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32273 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32274 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32275 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32276 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32277 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32278 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32279 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32280 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
32281 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32282 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32283 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32284 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32285 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
32286 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
32287 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
32288 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
32289 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32290 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32291 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32292 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32293 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32294 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32295 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
32296 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
32297 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
32298 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
32300 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
32301 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
32302 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
32303 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32304 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32305 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
32306 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32307 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32309 /* Mask arithmetic operations */
32310 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32311 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32312 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
32313 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32314 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32315 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32316 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
32317 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32318 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32319 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
32321 /* SHA */
32322 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32323 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32324 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32325 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
32326 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32327 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32328 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
32330 /* AVX512VL. */
32331 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT },
32332 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT },
32333 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64_256_mask", IX86_BUILTIN_MOVDQA64_256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32334 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64_128_mask", IX86_BUILTIN_MOVDQA64_128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32335 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32_256_mask", IX86_BUILTIN_MOVDQA32_256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32336 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32_128_mask", IX86_BUILTIN_MOVDQA32_128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32337 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_movapd256_mask", IX86_BUILTIN_MOVAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32338 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_movapd128_mask", IX86_BUILTIN_MOVAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32339 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_movaps256_mask", IX86_BUILTIN_MOVAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32340 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_movaps128_mask", IX86_BUILTIN_MOVAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32341 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_movdquhi256_mask", IX86_BUILTIN_MOVDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32342 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_movdquhi128_mask", IX86_BUILTIN_MOVDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32343 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_movdquqi256_mask", IX86_BUILTIN_MOVDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32344 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_movdquqi128_mask", IX86_BUILTIN_MOVDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32345 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4sf3_mask, "__builtin_ia32_minps_mask", IX86_BUILTIN_MINPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32346 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4sf3_mask, "__builtin_ia32_maxps_mask", IX86_BUILTIN_MAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32347 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2df3_mask, "__builtin_ia32_minpd_mask", IX86_BUILTIN_MINPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32348 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2df3_mask, "__builtin_ia32_maxpd_mask", IX86_BUILTIN_MAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32349 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4df3_mask, "__builtin_ia32_maxpd256_mask", IX86_BUILTIN_MAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32350 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8sf3_mask, "__builtin_ia32_maxps256_mask", IX86_BUILTIN_MAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32351 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4df3_mask, "__builtin_ia32_minpd256_mask", IX86_BUILTIN_MINPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32352 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8sf3_mask, "__builtin_ia32_minps256_mask", IX86_BUILTIN_MINPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32353 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4sf3_mask, "__builtin_ia32_mulps_mask", IX86_BUILTIN_MULPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32354 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_divv4sf3_mask, "__builtin_ia32_divps_mask", IX86_BUILTIN_DIVPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32355 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv2df3_mask, "__builtin_ia32_mulpd_mask", IX86_BUILTIN_MULPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32356 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_divv2df3_mask, "__builtin_ia32_divpd_mask", IX86_BUILTIN_DIVPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32357 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv4df3_mask, "__builtin_ia32_divpd256_mask", IX86_BUILTIN_DIVPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32358 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv8sf3_mask, "__builtin_ia32_divps256_mask", IX86_BUILTIN_DIVPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32359 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4df3_mask, "__builtin_ia32_mulpd256_mask", IX86_BUILTIN_MULPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32360 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8sf3_mask, "__builtin_ia32_mulps256_mask", IX86_BUILTIN_MULPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32361 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2df3_mask, "__builtin_ia32_addpd128_mask", IX86_BUILTIN_ADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32362 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4df3_mask, "__builtin_ia32_addpd256_mask", IX86_BUILTIN_ADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32363 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4sf3_mask, "__builtin_ia32_addps128_mask", IX86_BUILTIN_ADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32364 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8sf3_mask, "__builtin_ia32_addps256_mask", IX86_BUILTIN_ADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32365 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2df3_mask, "__builtin_ia32_subpd128_mask", IX86_BUILTIN_SUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32366 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4df3_mask, "__builtin_ia32_subpd256_mask", IX86_BUILTIN_SUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32367 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4sf3_mask, "__builtin_ia32_subps128_mask", IX86_BUILTIN_SUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32368 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8sf3_mask, "__builtin_ia32_subps256_mask", IX86_BUILTIN_SUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32369 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4df3_mask, "__builtin_ia32_xorpd256_mask", IX86_BUILTIN_XORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32370 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2df3_mask, "__builtin_ia32_xorpd128_mask", IX86_BUILTIN_XORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32371 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8sf3_mask, "__builtin_ia32_xorps256_mask", IX86_BUILTIN_XORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32372 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4sf3_mask, "__builtin_ia32_xorps128_mask", IX86_BUILTIN_XORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32373 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4df3_mask, "__builtin_ia32_orpd256_mask", IX86_BUILTIN_ORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32374 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2df3_mask, "__builtin_ia32_orpd128_mask", IX86_BUILTIN_ORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32375 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8sf3_mask, "__builtin_ia32_orps256_mask", IX86_BUILTIN_ORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32376 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4sf3_mask, "__builtin_ia32_orps128_mask", IX86_BUILTIN_ORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32377 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8sf_mask, "__builtin_ia32_broadcastf32x2_256_mask", IX86_BUILTIN_BROADCASTF32x2_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32378 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8si_mask, "__builtin_ia32_broadcasti32x2_256_mask", IX86_BUILTIN_BROADCASTI32x2_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32379 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4si_mask, "__builtin_ia32_broadcasti32x2_128_mask", IX86_BUILTIN_BROADCASTI32x2_128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32380 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4df_mask_1, "__builtin_ia32_broadcastf64x2_256_mask", IX86_BUILTIN_BROADCASTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32381 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4di_mask_1, "__builtin_ia32_broadcasti64x2_256_mask", IX86_BUILTIN_BROADCASTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32382 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8sf_mask_1, "__builtin_ia32_broadcastf32x4_256_mask", IX86_BUILTIN_BROADCASTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32383 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8si_mask_1, "__builtin_ia32_broadcasti32x4_256_mask", IX86_BUILTIN_BROADCASTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32384 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_QI },
32385 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_QI },
32386 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv16hi_mask, "__builtin_ia32_dbpsadbw256_mask", IX86_BUILTIN_DBPSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI },
32387 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI },
32388 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32389 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32390 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32391 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32392 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32393 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32394 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32395 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2uqq128_mask", IX86_BUILTIN_CVTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32396 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin_ia32_cvtpd2udq256_mask", IX86_BUILTIN_CVTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32397 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32398 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32399 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32400 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32401 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32402 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32403 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32404 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32405 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2udq128_mask", IX86_BUILTIN_CVTTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32406 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2dq256_mask", IX86_BUILTIN_CVTTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32407 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvttpd2dq_mask, "__builtin_ia32_cvttpd2dq128_mask", IX86_BUILTIN_CVTTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32408 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2udq256_mask", IX86_BUILTIN_CVTTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32409 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2si2_mask, "__builtin_ia32_cvttpd2udq128_mask", IX86_BUILTIN_CVTTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32410 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2dq256_mask, "__builtin_ia32_cvtpd2dq256_mask", IX86_BUILTIN_CVTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32411 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2dq_mask, "__builtin_ia32_cvtpd2dq128_mask", IX86_BUILTIN_CVTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32412 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4df2_mask, "__builtin_ia32_cvtdq2pd256_mask", IX86_BUILTIN_CVTDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32413 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtdq2pd_mask, "__builtin_ia32_cvtdq2pd128_mask", IX86_BUILTIN_CVTDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32414 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4df2_mask, "__builtin_ia32_cvtudq2pd256_mask", IX86_BUILTIN_CVTUDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32415 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2siv2df2_mask, "__builtin_ia32_cvtudq2pd128_mask", IX86_BUILTIN_CVTUDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32416 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv8siv8sf2_mask, "__builtin_ia32_cvtdq2ps256_mask", IX86_BUILTIN_CVTDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32417 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4sf2_mask, "__builtin_ia32_cvtdq2ps128_mask", IX86_BUILTIN_CVTDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32418 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv8siv8sf2_mask, "__builtin_ia32_cvtudq2ps256_mask", IX86_BUILTIN_CVTUDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32419 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4sf2_mask, "__builtin_ia32_cvtudq2ps128_mask", IX86_BUILTIN_CVTUDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32420 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtps2pd256_mask, "__builtin_ia32_cvtps2pd256_mask", IX86_BUILTIN_CVTPS2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_QI },
32421 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtps2pd_mask, "__builtin_ia32_cvtps2pd128_mask", IX86_BUILTIN_CVTPS2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SF_V2DF_QI },
32422 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv32qi_mask, "__builtin_ia32_pbroadcastb256_mask", IX86_BUILTIN_PBROADCASTB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_SI },
32423 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv32qi_mask, "__builtin_ia32_pbroadcastb256_gpr_mask", IX86_BUILTIN_PBROADCASTB256_GPR_MASK, UNKNOWN, (int) V32QI_FTYPE_QI_V32QI_SI },
32424 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16qi_mask, "__builtin_ia32_pbroadcastb128_mask", IX86_BUILTIN_PBROADCASTB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32425 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16qi_mask, "__builtin_ia32_pbroadcastb128_gpr_mask", IX86_BUILTIN_PBROADCASTB128_GPR_MASK, UNKNOWN, (int) V16QI_FTYPE_QI_V16QI_HI },
32426 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16hi_mask, "__builtin_ia32_pbroadcastw256_mask", IX86_BUILTIN_PBROADCASTW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8HI_V16HI_HI },
32427 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16hi_mask, "__builtin_ia32_pbroadcastw256_gpr_mask", IX86_BUILTIN_PBROADCASTW256_GPR_MASK, UNKNOWN, (int) V16HI_FTYPE_HI_V16HI_HI },
32428 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8hi_mask, "__builtin_ia32_pbroadcastw128_mask", IX86_BUILTIN_PBROADCASTW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32429 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8hi_mask, "__builtin_ia32_pbroadcastw128_gpr_mask", IX86_BUILTIN_PBROADCASTW128_GPR_MASK, UNKNOWN, (int) V8HI_FTYPE_HI_V8HI_QI },
32430 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8si_mask, "__builtin_ia32_pbroadcastd256_mask", IX86_BUILTIN_PBROADCASTD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32431 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8si_mask, "__builtin_ia32_pbroadcastd256_gpr_mask", IX86_BUILTIN_PBROADCASTD256_GPR_MASK, UNKNOWN, (int) V8SI_FTYPE_SI_V8SI_QI },
32432 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4si_mask, "__builtin_ia32_pbroadcastd128_mask", IX86_BUILTIN_PBROADCASTD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32433 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4si_mask, "__builtin_ia32_pbroadcastd128_gpr_mask", IX86_BUILTIN_PBROADCASTD128_GPR_MASK, UNKNOWN, (int) V4SI_FTYPE_SI_V4SI_QI },
32434 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4di_mask, "__builtin_ia32_pbroadcastq256_mask", IX86_BUILTIN_PBROADCASTQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32435 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4di_mask, "__builtin_ia32_pbroadcastq256_gpr_mask", IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
32436 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv2di_mask, "__builtin_ia32_pbroadcastq128_mask", IX86_BUILTIN_PBROADCASTQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32437 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv2di_mask, "__builtin_ia32_pbroadcastq128_gpr_mask", IX86_BUILTIN_PBROADCASTQ128_GPR_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
32438 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8sf_mask, "__builtin_ia32_broadcastss256_mask", IX86_BUILTIN_BROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32439 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4sf_mask, "__builtin_ia32_broadcastss128_mask", IX86_BUILTIN_BROADCASTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32440 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4df_mask, "__builtin_ia32_broadcastsd256_mask", IX86_BUILTIN_BROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32441 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4df, "__builtin_ia32_extractf64x2_256_mask", IX86_BUILTIN_EXTRACTF64X2_256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT_V2DF_QI },
32442 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4di, "__builtin_ia32_extracti64x2_256_mask", IX86_BUILTIN_EXTRACTI64X2_256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT_V2DI_QI },
32443 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8sf, "__builtin_ia32_insertf32x4_256_mask", IX86_BUILTIN_INSERTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI },
32444 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8si, "__builtin_ia32_inserti32x4_256_mask", IX86_BUILTIN_INSERTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI },
32445 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv16qiv16hi2_mask, "__builtin_ia32_pmovsxbw256_mask", IX86_BUILTIN_PMOVSXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32446 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv8qiv8hi2_mask, "__builtin_ia32_pmovsxbw128_mask", IX86_BUILTIN_PMOVSXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32447 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8qiv8si2_mask, "__builtin_ia32_pmovsxbd256_mask", IX86_BUILTIN_PMOVSXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32448 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4qiv4si2_mask, "__builtin_ia32_pmovsxbd128_mask", IX86_BUILTIN_PMOVSXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32449 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4qiv4di2_mask, "__builtin_ia32_pmovsxbq256_mask", IX86_BUILTIN_PMOVSXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32450 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2qiv2di2_mask, "__builtin_ia32_pmovsxbq128_mask", IX86_BUILTIN_PMOVSXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32451 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8hiv8si2_mask, "__builtin_ia32_pmovsxwd256_mask", IX86_BUILTIN_PMOVSXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32452 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4hiv4si2_mask, "__builtin_ia32_pmovsxwd128_mask", IX86_BUILTIN_PMOVSXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32453 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4hiv4di2_mask, "__builtin_ia32_pmovsxwq256_mask", IX86_BUILTIN_PMOVSXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32454 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2hiv2di2_mask, "__builtin_ia32_pmovsxwq128_mask", IX86_BUILTIN_PMOVSXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32455 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4siv4di2_mask, "__builtin_ia32_pmovsxdq256_mask", IX86_BUILTIN_PMOVSXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32456 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2siv2di2_mask, "__builtin_ia32_pmovsxdq128_mask", IX86_BUILTIN_PMOVSXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32457 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv16qiv16hi2_mask, "__builtin_ia32_pmovzxbw256_mask", IX86_BUILTIN_PMOVZXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32458 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv8qiv8hi2_mask, "__builtin_ia32_pmovzxbw128_mask", IX86_BUILTIN_PMOVZXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32459 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8qiv8si2_mask, "__builtin_ia32_pmovzxbd256_mask", IX86_BUILTIN_PMOVZXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32460 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4qiv4si2_mask, "__builtin_ia32_pmovzxbd128_mask", IX86_BUILTIN_PMOVZXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32461 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4qiv4di2_mask, "__builtin_ia32_pmovzxbq256_mask", IX86_BUILTIN_PMOVZXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32462 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2qiv2di2_mask, "__builtin_ia32_pmovzxbq128_mask", IX86_BUILTIN_PMOVZXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32463 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8hiv8si2_mask, "__builtin_ia32_pmovzxwd256_mask", IX86_BUILTIN_PMOVZXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32464 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4hiv4si2_mask, "__builtin_ia32_pmovzxwd128_mask", IX86_BUILTIN_PMOVZXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32465 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4hiv4di2_mask, "__builtin_ia32_pmovzxwq256_mask", IX86_BUILTIN_PMOVZXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32466 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2hiv2di2_mask, "__builtin_ia32_pmovzxwq128_mask", IX86_BUILTIN_PMOVZXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32467 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4siv4di2_mask, "__builtin_ia32_pmovzxdq256_mask", IX86_BUILTIN_PMOVZXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32468 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2siv2di2_mask, "__builtin_ia32_pmovzxdq128_mask", IX86_BUILTIN_PMOVZXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32469 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4df_mask, "__builtin_ia32_reducepd256_mask", IX86_BUILTIN_REDUCEPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32470 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv2df_mask, "__builtin_ia32_reducepd128_mask", IX86_BUILTIN_REDUCEPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32471 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv8sf_mask, "__builtin_ia32_reduceps256_mask", IX86_BUILTIN_REDUCEPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32472 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4sf_mask, "__builtin_ia32_reduceps128_mask", IX86_BUILTIN_REDUCEPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32473 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv2df, "__builtin_ia32_reducesd", IX86_BUILTIN_REDUCESD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32474 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv4sf, "__builtin_ia32_reducess", IX86_BUILTIN_REDUCESS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32475 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32476 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32477 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32478 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32479 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32480 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32481 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32482 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32483 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32484 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v2df_mask, "__builtin_ia32_rcp14pd128_mask", IX86_BUILTIN_RCP14PD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32485 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v8sf_mask, "__builtin_ia32_rcp14ps256_mask", IX86_BUILTIN_RCP14PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32486 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4sf_mask, "__builtin_ia32_rcp14ps128_mask", IX86_BUILTIN_RCP14PS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32487 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4df_mask, "__builtin_ia32_rsqrt14pd256_mask", IX86_BUILTIN_RSQRT14PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32488 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v2df_mask, "__builtin_ia32_rsqrt14pd128_mask", IX86_BUILTIN_RSQRT14PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32489 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v8sf_mask, "__builtin_ia32_rsqrt14ps256_mask", IX86_BUILTIN_RSQRT14PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32490 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4sf_mask, "__builtin_ia32_rsqrt14ps128_mask", IX86_BUILTIN_RSQRT14PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32491 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv4df2_mask, "__builtin_ia32_sqrtpd256_mask", IX86_BUILTIN_SQRTPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32492 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sqrtv2df2_mask, "__builtin_ia32_sqrtpd128_mask", IX86_BUILTIN_SQRTPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32493 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv8sf2_mask, "__builtin_ia32_sqrtps256_mask", IX86_BUILTIN_SQRTPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32494 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_sqrtv4sf2_mask, "__builtin_ia32_sqrtps128_mask", IX86_BUILTIN_SQRTPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32495 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16qi3_mask, "__builtin_ia32_paddb128_mask", IX86_BUILTIN_PADDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32496 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8hi3_mask, "__builtin_ia32_paddw128_mask", IX86_BUILTIN_PADDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32497 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4si3_mask, "__builtin_ia32_paddd128_mask", IX86_BUILTIN_PADDD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32498 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2di3_mask, "__builtin_ia32_paddq128_mask", IX86_BUILTIN_PADDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32499 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16qi3_mask, "__builtin_ia32_psubb128_mask", IX86_BUILTIN_PSUBB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32500 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8hi3_mask, "__builtin_ia32_psubw128_mask", IX86_BUILTIN_PSUBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32501 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4si3_mask, "__builtin_ia32_psubd128_mask", IX86_BUILTIN_PSUBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32502 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2di3_mask, "__builtin_ia32_psubq128_mask", IX86_BUILTIN_PSUBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32503 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv16qi3_mask, "__builtin_ia32_paddsb128_mask", IX86_BUILTIN_PADDSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32504 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv8hi3_mask, "__builtin_ia32_paddsw128_mask", IX86_BUILTIN_PADDSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32505 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv16qi3_mask, "__builtin_ia32_psubsb128_mask", IX86_BUILTIN_PSUBSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32506 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv8hi3_mask, "__builtin_ia32_psubsw128_mask", IX86_BUILTIN_PSUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32507 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv16qi3_mask, "__builtin_ia32_paddusb128_mask", IX86_BUILTIN_PADDUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32508 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv8hi3_mask, "__builtin_ia32_paddusw128_mask", IX86_BUILTIN_PADDUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32509 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv16qi3_mask, "__builtin_ia32_psubusb128_mask", IX86_BUILTIN_PSUBUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32510 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv8hi3_mask, "__builtin_ia32_psubusw128_mask", IX86_BUILTIN_PSUBUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32511 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv32qi3_mask, "__builtin_ia32_paddb256_mask", IX86_BUILTIN_PADDB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32512 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16hi3_mask, "__builtin_ia32_paddw256_mask", IX86_BUILTIN_PADDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32513 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8si3_mask, "__builtin_ia32_paddd256_mask", IX86_BUILTIN_PADDD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32514 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4di3_mask, "__builtin_ia32_paddq256_mask", IX86_BUILTIN_PADDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32515 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv32qi3_mask, "__builtin_ia32_paddsb256_mask", IX86_BUILTIN_PADDSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32516 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv16hi3_mask, "__builtin_ia32_paddsw256_mask", IX86_BUILTIN_PADDSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32517 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv32qi3_mask, "__builtin_ia32_paddusb256_mask", IX86_BUILTIN_PADDUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32518 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv16hi3_mask, "__builtin_ia32_paddusw256_mask", IX86_BUILTIN_PADDUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32519 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv32qi3_mask, "__builtin_ia32_psubb256_mask", IX86_BUILTIN_PSUBB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32520 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16hi3_mask, "__builtin_ia32_psubw256_mask", IX86_BUILTIN_PSUBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32521 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8si3_mask, "__builtin_ia32_psubd256_mask", IX86_BUILTIN_PSUBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32522 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4di3_mask, "__builtin_ia32_psubq256_mask", IX86_BUILTIN_PSUBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32523 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv32qi3_mask, "__builtin_ia32_psubsb256_mask", IX86_BUILTIN_PSUBSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32524 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv16hi3_mask, "__builtin_ia32_psubsw256_mask", IX86_BUILTIN_PSUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32525 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv32qi3_mask, "__builtin_ia32_psubusb256_mask", IX86_BUILTIN_PSUBUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32526 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv16hi3_mask, "__builtin_ia32_psubusw256_mask", IX86_BUILTIN_PSUBUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32527 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_256_mask", IX86_BUILTIN_SHUF_F64x2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32528 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_256_mask", IX86_BUILTIN_SHUF_I64x2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32529 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_256_mask", IX86_BUILTIN_SHUF_I32x4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32530 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_256_mask", IX86_BUILTIN_SHUF_F32x4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32531 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovwb128_mask", IX86_BUILTIN_PMOVWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32532 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovwb256_mask", IX86_BUILTIN_PMOVWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32533 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovswb128_mask", IX86_BUILTIN_PMOVSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32534 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovswb256_mask", IX86_BUILTIN_PMOVSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32535 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovuswb128_mask", IX86_BUILTIN_PMOVUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32536 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovuswb256_mask", IX86_BUILTIN_PMOVUSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32537 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask, "__builtin_ia32_pmovdb128_mask", IX86_BUILTIN_PMOVDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32538 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask, "__builtin_ia32_pmovdb256_mask", IX86_BUILTIN_PMOVDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32539 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask, "__builtin_ia32_pmovsdb128_mask", IX86_BUILTIN_PMOVSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32540 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask, "__builtin_ia32_pmovsdb256_mask", IX86_BUILTIN_PMOVSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32541 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask, "__builtin_ia32_pmovusdb128_mask", IX86_BUILTIN_PMOVUSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32542 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask, "__builtin_ia32_pmovusdb256_mask", IX86_BUILTIN_PMOVUSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32543 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask, "__builtin_ia32_pmovdw128_mask", IX86_BUILTIN_PMOVDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32544 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask, "__builtin_ia32_pmovdw256_mask", IX86_BUILTIN_PMOVDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32545 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask, "__builtin_ia32_pmovsdw128_mask", IX86_BUILTIN_PMOVSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32546 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask, "__builtin_ia32_pmovsdw256_mask", IX86_BUILTIN_PMOVSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32547 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask, "__builtin_ia32_pmovusdw128_mask", IX86_BUILTIN_PMOVUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32548 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask, "__builtin_ia32_pmovusdw256_mask", IX86_BUILTIN_PMOVUSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32549 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask, "__builtin_ia32_pmovqb128_mask", IX86_BUILTIN_PMOVQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32550 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask, "__builtin_ia32_pmovqb256_mask", IX86_BUILTIN_PMOVQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32551 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask, "__builtin_ia32_pmovsqb128_mask", IX86_BUILTIN_PMOVSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32552 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask, "__builtin_ia32_pmovsqb256_mask", IX86_BUILTIN_PMOVSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32553 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask, "__builtin_ia32_pmovusqb128_mask", IX86_BUILTIN_PMOVUSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32554 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask, "__builtin_ia32_pmovusqb256_mask", IX86_BUILTIN_PMOVUSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32555 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask, "__builtin_ia32_pmovqw128_mask", IX86_BUILTIN_PMOVQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32556 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask, "__builtin_ia32_pmovqw256_mask", IX86_BUILTIN_PMOVQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32557 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask, "__builtin_ia32_pmovsqw128_mask", IX86_BUILTIN_PMOVSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32558 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask, "__builtin_ia32_pmovsqw256_mask", IX86_BUILTIN_PMOVSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32559 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask, "__builtin_ia32_pmovusqw128_mask", IX86_BUILTIN_PMOVUSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32560 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask, "__builtin_ia32_pmovusqw256_mask", IX86_BUILTIN_PMOVUSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32561 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask, "__builtin_ia32_pmovqd128_mask", IX86_BUILTIN_PMOVQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32562 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask, "__builtin_ia32_pmovqd256_mask", IX86_BUILTIN_PMOVQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32563 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask, "__builtin_ia32_pmovsqd128_mask", IX86_BUILTIN_PMOVSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32564 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask, "__builtin_ia32_pmovsqd256_mask", IX86_BUILTIN_PMOVSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32565 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask, "__builtin_ia32_pmovusqd128_mask", IX86_BUILTIN_PMOVUSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32566 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask, "__builtin_ia32_pmovusqd256_mask", IX86_BUILTIN_PMOVUSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32567 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4df_mask, "__builtin_ia32_rangepd256_mask", IX86_BUILTIN_RANGEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32568 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv2df_mask, "__builtin_ia32_rangepd128_mask", IX86_BUILTIN_RANGEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32569 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv8sf_mask, "__builtin_ia32_rangeps256_mask", IX86_BUILTIN_RANGEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32570 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4sf_mask, "__builtin_ia32_rangeps128_mask", IX86_BUILTIN_RANGEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32571 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv8sf_mask, "__builtin_ia32_getexpps256_mask", IX86_BUILTIN_GETEXPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32572 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4df_mask, "__builtin_ia32_getexppd256_mask", IX86_BUILTIN_GETEXPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32573 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4sf_mask, "__builtin_ia32_getexpps128_mask", IX86_BUILTIN_GETEXPPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32574 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv2df_mask, "__builtin_ia32_getexppd128_mask", IX86_BUILTIN_GETEXPPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32575 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_mask, "__builtin_ia32_fixupimmpd256_mask", IX86_BUILTIN_FIXUPIMMPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32576 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_maskz, "__builtin_ia32_fixupimmpd256_maskz", IX86_BUILTIN_FIXUPIMMPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32577 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_mask, "__builtin_ia32_fixupimmps256_mask", IX86_BUILTIN_FIXUPIMMPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32578 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_maskz, "__builtin_ia32_fixupimmps256_maskz", IX86_BUILTIN_FIXUPIMMPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32579 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_mask, "__builtin_ia32_fixupimmpd128_mask", IX86_BUILTIN_FIXUPIMMPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32580 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_maskz, "__builtin_ia32_fixupimmpd128_maskz", IX86_BUILTIN_FIXUPIMMPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32581 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_mask, "__builtin_ia32_fixupimmps128_mask", IX86_BUILTIN_FIXUPIMMPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32582 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_maskz, "__builtin_ia32_fixupimmps128_maskz", IX86_BUILTIN_FIXUPIMMPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32583 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4di2_mask, "__builtin_ia32_pabsq256_mask", IX86_BUILTIN_PABSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32584 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv2di2_mask, "__builtin_ia32_pabsq128_mask", IX86_BUILTIN_PABSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32585 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8si2_mask, "__builtin_ia32_pabsd256_mask", IX86_BUILTIN_PABSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32586 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4si2_mask, "__builtin_ia32_pabsd128_mask", IX86_BUILTIN_PABSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32587 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pmulhrswv16hi3_mask , "__builtin_ia32_pmulhrsw256_mask", IX86_BUILTIN_PMULHRSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32588 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pmulhrswv8hi3_mask, "__builtin_ia32_pmulhrsw128_mask", IX86_BUILTIN_PMULHRSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32589 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv8hi3_highpart_mask, "__builtin_ia32_pmulhuw128_mask", IX86_BUILTIN_PMULHUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32590 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv16hi3_highpart_mask, "__builtin_ia32_pmulhuw256_mask" , IX86_BUILTIN_PMULHUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32591 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv16hi3_highpart_mask, "__builtin_ia32_pmulhw256_mask" , IX86_BUILTIN_PMULHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32592 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv8hi3_highpart_mask, "__builtin_ia32_pmulhw128_mask", IX86_BUILTIN_PMULHW128_MASK, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32593 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv16hi3_mask, "__builtin_ia32_pmullw256_mask" , IX86_BUILTIN_PMULLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32594 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8hi3_mask, "__builtin_ia32_pmullw128_mask", IX86_BUILTIN_PMULLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32595 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv4di3_mask, "__builtin_ia32_pmullq256_mask", IX86_BUILTIN_PMULLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32596 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv2di3_mask, "__builtin_ia32_pmullq128_mask", IX86_BUILTIN_PMULLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32597 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4df3_mask, "__builtin_ia32_andpd256_mask", IX86_BUILTIN_ANDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32598 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2df3_mask, "__builtin_ia32_andpd128_mask", IX86_BUILTIN_ANDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32599 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8sf3_mask, "__builtin_ia32_andps256_mask", IX86_BUILTIN_ANDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32600 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4sf3_mask, "__builtin_ia32_andps128_mask", IX86_BUILTIN_ANDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32601 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv4df3_mask, "__builtin_ia32_andnpd256_mask", IX86_BUILTIN_ANDNPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32602 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2df3_mask, "__builtin_ia32_andnpd128_mask", IX86_BUILTIN_ANDNPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32603 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv8sf3_mask, "__builtin_ia32_andnps256_mask", IX86_BUILTIN_ANDNPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32604 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_andnotv4sf3_mask, "__builtin_ia32_andnps128_mask", IX86_BUILTIN_ANDNPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32605 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllwi128_mask", IX86_BUILTIN_PSLLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32606 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslldi128_mask", IX86_BUILTIN_PSLLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32607 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllqi128_mask", IX86_BUILTIN_PSLLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32608 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllw128_mask", IX86_BUILTIN_PSLLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32609 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslld128_mask", IX86_BUILTIN_PSLLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32610 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllq128_mask", IX86_BUILTIN_PSLLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32611 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllwi256_mask", IX86_BUILTIN_PSLLWI256_MASK , UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32612 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllw256_mask", IX86_BUILTIN_PSLLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32613 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslldi256_mask", IX86_BUILTIN_PSLLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32614 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslld256_mask", IX86_BUILTIN_PSLLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32615 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllqi256_mask", IX86_BUILTIN_PSLLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32616 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllq256_mask", IX86_BUILTIN_PSLLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32617 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psradi128_mask", IX86_BUILTIN_PSRADI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32618 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psrad128_mask", IX86_BUILTIN_PSRAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32619 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psradi256_mask", IX86_BUILTIN_PSRADI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32620 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psrad256_mask", IX86_BUILTIN_PSRAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32621 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraqi128_mask", IX86_BUILTIN_PSRAQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32622 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraq128_mask", IX86_BUILTIN_PSRAQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32623 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraqi256_mask", IX86_BUILTIN_PSRAQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32624 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraq256_mask", IX86_BUILTIN_PSRAQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32625 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8si3_mask, "__builtin_ia32_pandd256_mask", IX86_BUILTIN_PANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32626 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4si3_mask, "__builtin_ia32_pandd128_mask", IX86_BUILTIN_PANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32627 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrldi128_mask", IX86_BUILTIN_PSRLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32628 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrld128_mask", IX86_BUILTIN_PSRLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32629 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrldi256_mask", IX86_BUILTIN_PSRLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32630 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrld256_mask", IX86_BUILTIN_PSRLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32631 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlqi128_mask", IX86_BUILTIN_PSRLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32632 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlq128_mask", IX86_BUILTIN_PSRLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32633 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlqi256_mask", IX86_BUILTIN_PSRLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32634 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlq256_mask", IX86_BUILTIN_PSRLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32635 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4di3_mask, "__builtin_ia32_pandq256_mask", IX86_BUILTIN_PANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32636 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2di3_mask, "__builtin_ia32_pandq128_mask", IX86_BUILTIN_PANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32637 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv8si3_mask, "__builtin_ia32_pandnd256_mask", IX86_BUILTIN_PANDND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32638 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv4si3_mask, "__builtin_ia32_pandnd128_mask", IX86_BUILTIN_PANDND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32639 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv4di3_mask, "__builtin_ia32_pandnq256_mask", IX86_BUILTIN_PANDNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32640 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2di3_mask, "__builtin_ia32_pandnq128_mask", IX86_BUILTIN_PANDNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32641 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8si3_mask, "__builtin_ia32_pord256_mask", IX86_BUILTIN_PORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32642 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4si3_mask, "__builtin_ia32_pord128_mask", IX86_BUILTIN_PORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32643 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4di3_mask, "__builtin_ia32_porq256_mask", IX86_BUILTIN_PORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32644 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2di3_mask, "__builtin_ia32_porq128_mask", IX86_BUILTIN_PORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32645 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8si3_mask, "__builtin_ia32_pxord256_mask", IX86_BUILTIN_PXORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32646 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4si3_mask, "__builtin_ia32_pxord128_mask", IX86_BUILTIN_PXORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32647 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4di3_mask, "__builtin_ia32_pxorq256_mask", IX86_BUILTIN_PXORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32648 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2di3_mask, "__builtin_ia32_pxorq128_mask", IX86_BUILTIN_PXORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32649 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packsswb_mask, "__builtin_ia32_packsswb256_mask", IX86_BUILTIN_PACKSSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32650 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packsswb_mask, "__builtin_ia32_packsswb128_mask", IX86_BUILTIN_PACKSSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32651 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packuswb_mask, "__builtin_ia32_packuswb256_mask", IX86_BUILTIN_PACKUSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32652 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packuswb_mask, "__builtin_ia32_packuswb128_mask", IX86_BUILTIN_PACKUSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32653 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev8sf_mask, "__builtin_ia32_rndscaleps_256_mask", IX86_BUILTIN_RNDSCALEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32654 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4df_mask, "__builtin_ia32_rndscalepd_256_mask", IX86_BUILTIN_RNDSCALEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32655 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4sf_mask, "__builtin_ia32_rndscaleps_128_mask", IX86_BUILTIN_RNDSCALEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32656 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev2df_mask, "__builtin_ia32_rndscalepd_128_mask", IX86_BUILTIN_RNDSCALEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32657 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_mask, "__builtin_ia32_pternlogq256_mask", IX86_BUILTIN_VTERNLOGQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32658 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_maskz, "__builtin_ia32_pternlogq256_maskz", IX86_BUILTIN_VTERNLOGQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32659 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_mask, "__builtin_ia32_pternlogd256_mask", IX86_BUILTIN_VTERNLOGD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32660 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_maskz, "__builtin_ia32_pternlogd256_maskz", IX86_BUILTIN_VTERNLOGD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32661 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_mask, "__builtin_ia32_pternlogq128_mask", IX86_BUILTIN_VTERNLOGQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32662 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_maskz, "__builtin_ia32_pternlogq128_maskz", IX86_BUILTIN_VTERNLOGQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32663 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_mask, "__builtin_ia32_pternlogd128_mask", IX86_BUILTIN_VTERNLOGD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32664 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_maskz, "__builtin_ia32_pternlogd128_maskz", IX86_BUILTIN_VTERNLOGD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32665 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4df_mask, "__builtin_ia32_scalefpd256_mask", IX86_BUILTIN_SCALEFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32666 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv8sf_mask, "__builtin_ia32_scalefps256_mask", IX86_BUILTIN_SCALEFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32667 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv2df_mask, "__builtin_ia32_scalefpd128_mask", IX86_BUILTIN_SCALEFPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32668 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4sf_mask, "__builtin_ia32_scalefps128_mask", IX86_BUILTIN_SCALEFPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32669 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask, "__builtin_ia32_vfmaddpd256_mask", IX86_BUILTIN_VFMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32670 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask3, "__builtin_ia32_vfmaddpd256_mask3", IX86_BUILTIN_VFMADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32671 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_maskz, "__builtin_ia32_vfmaddpd256_maskz", IX86_BUILTIN_VFMADDPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32672 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask, "__builtin_ia32_vfmaddpd128_mask", IX86_BUILTIN_VFMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32673 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask3, "__builtin_ia32_vfmaddpd128_mask3", IX86_BUILTIN_VFMADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32674 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_maskz, "__builtin_ia32_vfmaddpd128_maskz", IX86_BUILTIN_VFMADDPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32675 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask, "__builtin_ia32_vfmaddps256_mask", IX86_BUILTIN_VFMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32676 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask3, "__builtin_ia32_vfmaddps256_mask3", IX86_BUILTIN_VFMADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32677 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_maskz, "__builtin_ia32_vfmaddps256_maskz", IX86_BUILTIN_VFMADDPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32678 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask, "__builtin_ia32_vfmaddps128_mask", IX86_BUILTIN_VFMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32679 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask3, "__builtin_ia32_vfmaddps128_mask3", IX86_BUILTIN_VFMADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32680 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_maskz, "__builtin_ia32_vfmaddps128_maskz", IX86_BUILTIN_VFMADDPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32681 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4df_mask3, "__builtin_ia32_vfmsubpd256_mask3", IX86_BUILTIN_VFMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32682 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v2df_mask3, "__builtin_ia32_vfmsubpd128_mask3", IX86_BUILTIN_VFMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32683 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v8sf_mask3, "__builtin_ia32_vfmsubps256_mask3", IX86_BUILTIN_VFMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32684 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4sf_mask3, "__builtin_ia32_vfmsubps128_mask3", IX86_BUILTIN_VFMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32685 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4df_mask, "__builtin_ia32_vfnmaddpd256_mask", IX86_BUILTIN_VFNMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32686 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v2df_mask, "__builtin_ia32_vfnmaddpd128_mask", IX86_BUILTIN_VFNMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32687 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v8sf_mask, "__builtin_ia32_vfnmaddps256_mask", IX86_BUILTIN_VFNMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32688 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4sf_mask, "__builtin_ia32_vfnmaddps128_mask", IX86_BUILTIN_VFNMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32689 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask, "__builtin_ia32_vfnmsubpd256_mask", IX86_BUILTIN_VFNMSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32690 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask3, "__builtin_ia32_vfnmsubpd256_mask3", IX86_BUILTIN_VFNMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32691 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask, "__builtin_ia32_vfnmsubpd128_mask", IX86_BUILTIN_VFNMSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32692 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask3, "__builtin_ia32_vfnmsubpd128_mask3", IX86_BUILTIN_VFNMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32693 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask, "__builtin_ia32_vfnmsubps256_mask", IX86_BUILTIN_VFNMSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32694 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask3, "__builtin_ia32_vfnmsubps256_mask3", IX86_BUILTIN_VFNMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32695 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask, "__builtin_ia32_vfnmsubps128_mask", IX86_BUILTIN_VFNMSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32696 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask3, "__builtin_ia32_vfnmsubps128_mask3", IX86_BUILTIN_VFNMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32697 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask, "__builtin_ia32_vfmaddsubpd256_mask", IX86_BUILTIN_VFMADDSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32698 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask3, "__builtin_ia32_vfmaddsubpd256_mask3", IX86_BUILTIN_VFMADDSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32699 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_maskz, "__builtin_ia32_vfmaddsubpd256_maskz", IX86_BUILTIN_VFMADDSUBPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32700 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask, "__builtin_ia32_vfmaddsubpd128_mask", IX86_BUILTIN_VFMADDSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32701 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask3, "__builtin_ia32_vfmaddsubpd128_mask3", IX86_BUILTIN_VFMADDSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32702 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_maskz, "__builtin_ia32_vfmaddsubpd128_maskz", IX86_BUILTIN_VFMADDSUBPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32703 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask, "__builtin_ia32_vfmaddsubps256_mask", IX86_BUILTIN_VFMADDSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32704 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask3, "__builtin_ia32_vfmaddsubps256_mask3", IX86_BUILTIN_VFMADDSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32705 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_maskz, "__builtin_ia32_vfmaddsubps256_maskz", IX86_BUILTIN_VFMADDSUBPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32706 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask, "__builtin_ia32_vfmaddsubps128_mask", IX86_BUILTIN_VFMADDSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32707 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask3, "__builtin_ia32_vfmaddsubps128_mask3", IX86_BUILTIN_VFMADDSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32708 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_maskz, "__builtin_ia32_vfmaddsubps128_maskz", IX86_BUILTIN_VFMADDSUBPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32709 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4df_mask3, "__builtin_ia32_vfmsubaddpd256_mask3", IX86_BUILTIN_VFMSUBADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32710 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v2df_mask3, "__builtin_ia32_vfmsubaddpd128_mask3", IX86_BUILTIN_VFMSUBADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32711 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3, "__builtin_ia32_vfmsubaddps256_mask3", IX86_BUILTIN_VFMSUBADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32712 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4sf_mask3, "__builtin_ia32_vfmsubaddps128_mask3", IX86_BUILTIN_VFMSUBADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32713 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4df, "__builtin_ia32_insertf64x2_256_mask", IX86_BUILTIN_INSERTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI },
32714 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4di, "__builtin_ia32_inserti64x2_256_mask", IX86_BUILTIN_INSERTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI },
32715 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv16hi_mask, "__builtin_ia32_psrav16hi_mask", IX86_BUILTIN_PSRAVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32716 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv8hi_mask, "__builtin_ia32_psrav8hi_mask", IX86_BUILTIN_PSRAVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32717 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v16hi_mask, "__builtin_ia32_pmaddubsw256_mask", IX86_BUILTIN_PMADDUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_V16HI_HI },
32718 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v8hi_mask, "__builtin_ia32_pmaddubsw128_mask", IX86_BUILTIN_PMADDUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_V8HI_QI },
32719 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v16hi_mask, "__builtin_ia32_pmaddwd256_mask", IX86_BUILTIN_PMADDWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI_V8SI_QI },
32720 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v8hi_mask, "__builtin_ia32_pmaddwd128_mask", IX86_BUILTIN_PMADDWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI_V4SI_QI },
32721 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv16hi_mask, "__builtin_ia32_psrlv16hi_mask", IX86_BUILTIN_PSRLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32722 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv8hi_mask, "__builtin_ia32_psrlv8hi_mask", IX86_BUILTIN_PSRLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32723 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_fix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2dq256_mask", IX86_BUILTIN_CVTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32724 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_fix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2dq128_mask", IX86_BUILTIN_CVTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32725 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2udq256_mask", IX86_BUILTIN_CVTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32726 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2udq128_mask", IX86_BUILTIN_CVTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32727 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv4di_mask, "__builtin_ia32_cvtps2qq256_mask", IX86_BUILTIN_CVTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32728 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv2di_mask, "__builtin_ia32_cvtps2qq128_mask", IX86_BUILTIN_CVTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32729 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv4di_mask, "__builtin_ia32_cvtps2uqq256_mask", IX86_BUILTIN_CVTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32730 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv2di_mask, "__builtin_ia32_cvtps2uqq128_mask", IX86_BUILTIN_CVTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32731 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv8sf_mask, "__builtin_ia32_getmantps256_mask", IX86_BUILTIN_GETMANTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32732 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4sf_mask, "__builtin_ia32_getmantps128_mask", IX86_BUILTIN_GETMANTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32733 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4df_mask, "__builtin_ia32_getmantpd256_mask", IX86_BUILTIN_GETMANTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32734 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv2df_mask, "__builtin_ia32_getmantpd128_mask", IX86_BUILTIN_GETMANTPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32735 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movddup256_mask, "__builtin_ia32_movddup256_mask", IX86_BUILTIN_MOVDDUP256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32736 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_dupv2df_mask, "__builtin_ia32_movddup128_mask", IX86_BUILTIN_MOVDDUP128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32737 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movshdup256_mask, "__builtin_ia32_movshdup256_mask", IX86_BUILTIN_MOVSHDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32738 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movshdup_mask, "__builtin_ia32_movshdup128_mask", IX86_BUILTIN_MOVSHDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32739 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_movsldup256_mask", IX86_BUILTIN_MOVSLDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32740 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32741 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32742 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32743 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32744 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32745 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32746 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32747 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32748 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32749 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32750 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32751 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32752 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_maskz, "__builtin_ia32_vpermt2vard256_maskz", IX86_BUILTIN_VPERMT2VARD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32753 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4di3_mask, "__builtin_ia32_vpermi2varq256_mask", IX86_BUILTIN_VPERMI2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32754 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8si3_mask, "__builtin_ia32_vpermi2vard256_mask", IX86_BUILTIN_VPERMI2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32755 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_mask, "__builtin_ia32_vpermt2varpd256_mask", IX86_BUILTIN_VPERMT2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32756 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_maskz, "__builtin_ia32_vpermt2varpd256_maskz", IX86_BUILTIN_VPERMT2VARPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32757 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_mask, "__builtin_ia32_vpermt2varps256_mask", IX86_BUILTIN_VPERMT2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32758 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_maskz, "__builtin_ia32_vpermt2varps256_maskz", IX86_BUILTIN_VPERMT2VARPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32759 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4df3_mask, "__builtin_ia32_vpermi2varpd256_mask", IX86_BUILTIN_VPERMI2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32760 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8sf3_mask, "__builtin_ia32_vpermi2varps256_mask", IX86_BUILTIN_VPERMI2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32761 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_mask, "__builtin_ia32_vpermt2varq128_mask", IX86_BUILTIN_VPERMT2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32762 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_maskz, "__builtin_ia32_vpermt2varq128_maskz", IX86_BUILTIN_VPERMT2VARQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32763 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_mask, "__builtin_ia32_vpermt2vard128_mask", IX86_BUILTIN_VPERMT2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32764 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_maskz, "__builtin_ia32_vpermt2vard128_maskz", IX86_BUILTIN_VPERMT2VARD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32765 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2di3_mask, "__builtin_ia32_vpermi2varq128_mask", IX86_BUILTIN_VPERMI2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32766 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4si3_mask, "__builtin_ia32_vpermi2vard128_mask", IX86_BUILTIN_VPERMI2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32767 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_mask, "__builtin_ia32_vpermt2varpd128_mask", IX86_BUILTIN_VPERMT2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32768 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_maskz, "__builtin_ia32_vpermt2varpd128_maskz", IX86_BUILTIN_VPERMT2VARPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32769 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_mask, "__builtin_ia32_vpermt2varps128_mask", IX86_BUILTIN_VPERMT2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32770 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_maskz, "__builtin_ia32_vpermt2varps128_maskz", IX86_BUILTIN_VPERMT2VARPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32771 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2df3_mask, "__builtin_ia32_vpermi2varpd128_mask", IX86_BUILTIN_VPERMI2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32772 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4sf3_mask, "__builtin_ia32_vpermi2varps128_mask", IX86_BUILTIN_VPERMI2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32773 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pshufbv32qi3_mask, "__builtin_ia32_pshufb256_mask", IX86_BUILTIN_PSHUFB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32774 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pshufbv16qi3_mask, "__builtin_ia32_pshufb128_mask", IX86_BUILTIN_PSHUFB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32775 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhwv3_mask, "__builtin_ia32_pshufhw256_mask", IX86_BUILTIN_PSHUFHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32776 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhw_mask, "__builtin_ia32_pshufhw128_mask", IX86_BUILTIN_PSHUFHW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32777 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflwv3_mask, "__builtin_ia32_pshuflw256_mask", IX86_BUILTIN_PSHUFLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32778 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflw_mask, "__builtin_ia32_pshuflw128_mask", IX86_BUILTIN_PSHUFLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32779 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufdv3_mask, "__builtin_ia32_pshufd256_mask", IX86_BUILTIN_PSHUFD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32780 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufd_mask, "__builtin_ia32_pshufd128_mask", IX86_BUILTIN_PSHUFD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32781 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufpd256_mask, "__builtin_ia32_shufpd256_mask", IX86_BUILTIN_SHUFPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32782 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_shufpd_mask, "__builtin_ia32_shufpd128_mask", IX86_BUILTIN_SHUFPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32783 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufps256_mask, "__builtin_ia32_shufps256_mask", IX86_BUILTIN_SHUFPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32784 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_shufps_mask, "__builtin_ia32_shufps128_mask", IX86_BUILTIN_SHUFPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32785 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4di_mask, "__builtin_ia32_prolvq256_mask", IX86_BUILTIN_PROLVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32786 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv2di_mask, "__builtin_ia32_prolvq128_mask", IX86_BUILTIN_PROLVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32787 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4di_mask, "__builtin_ia32_prolq256_mask", IX86_BUILTIN_PROLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32788 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv2di_mask, "__builtin_ia32_prolq128_mask", IX86_BUILTIN_PROLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32789 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4di_mask, "__builtin_ia32_prorvq256_mask", IX86_BUILTIN_PRORVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32790 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv2di_mask, "__builtin_ia32_prorvq128_mask", IX86_BUILTIN_PRORVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32791 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4di_mask, "__builtin_ia32_prorq256_mask", IX86_BUILTIN_PRORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32792 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv2di_mask, "__builtin_ia32_prorq128_mask", IX86_BUILTIN_PRORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32793 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv2di_mask, "__builtin_ia32_psravq128_mask", IX86_BUILTIN_PSRAVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32794 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4di_mask, "__builtin_ia32_psravq256_mask", IX86_BUILTIN_PSRAVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32795 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4di_mask, "__builtin_ia32_psllv4di_mask", IX86_BUILTIN_PSLLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32796 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv2di_mask, "__builtin_ia32_psllv2di_mask", IX86_BUILTIN_PSLLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32797 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv8si_mask, "__builtin_ia32_psllv8si_mask", IX86_BUILTIN_PSLLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32798 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4si_mask, "__builtin_ia32_psllv4si_mask", IX86_BUILTIN_PSLLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32799 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv8si_mask, "__builtin_ia32_psrav8si_mask", IX86_BUILTIN_PSRAVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32800 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4si_mask, "__builtin_ia32_psrav4si_mask", IX86_BUILTIN_PSRAVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32801 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4di_mask, "__builtin_ia32_psrlv4di_mask", IX86_BUILTIN_PSRLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32802 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv2di_mask, "__builtin_ia32_psrlv2di_mask", IX86_BUILTIN_PSRLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32803 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv8si_mask, "__builtin_ia32_psrlv8si_mask", IX86_BUILTIN_PSRLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32804 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4si_mask, "__builtin_ia32_psrlv4si_mask", IX86_BUILTIN_PSRLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32805 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psrawi256_mask", IX86_BUILTIN_PSRAWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32806 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psraw256_mask", IX86_BUILTIN_PSRAW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32807 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psrawi128_mask", IX86_BUILTIN_PSRAWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32808 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psraw128_mask", IX86_BUILTIN_PSRAW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32809 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlwi256_mask", IX86_BUILTIN_PSRLWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32810 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlw256_mask", IX86_BUILTIN_PSRLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32811 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlwi128_mask", IX86_BUILTIN_PSRLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32812 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlw128_mask", IX86_BUILTIN_PSRLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32813 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv8si_mask, "__builtin_ia32_prorvd256_mask", IX86_BUILTIN_PRORVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32814 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv8si_mask, "__builtin_ia32_prolvd256_mask", IX86_BUILTIN_PROLVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32815 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv8si_mask, "__builtin_ia32_prord256_mask", IX86_BUILTIN_PRORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32816 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv8si_mask, "__builtin_ia32_prold256_mask", IX86_BUILTIN_PROLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32817 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4si_mask, "__builtin_ia32_prorvd128_mask", IX86_BUILTIN_PRORVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32818 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4si_mask, "__builtin_ia32_prolvd128_mask", IX86_BUILTIN_PROLVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32819 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_ia32_prord128_mask", IX86_BUILTIN_PRORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32820 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32821 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_QI },
32822 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_QI },
32823 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT },
32824 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_QI },
32825 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_QI },
32826 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT },
32827 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) HI_FTYPE_V16QI },
32828 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) SI_FTYPE_V32QI },
32829 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) QI_FTYPE_V8HI },
32830 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv16hi, "__builtin_ia32_cvtw2mask256", IX86_BUILTIN_CVTW2MASK256, UNKNOWN, (int) HI_FTYPE_V16HI },
32831 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv4si, "__builtin_ia32_cvtd2mask128", IX86_BUILTIN_CVTD2MASK128, UNKNOWN, (int) QI_FTYPE_V4SI },
32832 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv8si, "__builtin_ia32_cvtd2mask256", IX86_BUILTIN_CVTD2MASK256, UNKNOWN, (int) QI_FTYPE_V8SI },
32833 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv2di, "__builtin_ia32_cvtq2mask128", IX86_BUILTIN_CVTQ2MASK128, UNKNOWN, (int) QI_FTYPE_V2DI },
32834 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv4di, "__builtin_ia32_cvtq2mask256", IX86_BUILTIN_CVTQ2MASK256, UNKNOWN, (int) QI_FTYPE_V4DI },
32835 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv16qi, "__builtin_ia32_cvtmask2b128", IX86_BUILTIN_CVTMASK2B128, UNKNOWN, (int) V16QI_FTYPE_HI },
32836 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv32qi, "__builtin_ia32_cvtmask2b256", IX86_BUILTIN_CVTMASK2B256, UNKNOWN, (int) V32QI_FTYPE_SI },
32837 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv8hi, "__builtin_ia32_cvtmask2w128", IX86_BUILTIN_CVTMASK2W128, UNKNOWN, (int) V8HI_FTYPE_QI },
32838 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv16hi, "__builtin_ia32_cvtmask2w256", IX86_BUILTIN_CVTMASK2W256, UNKNOWN, (int) V16HI_FTYPE_HI },
32839 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv4si, "__builtin_ia32_cvtmask2d128", IX86_BUILTIN_CVTMASK2D128, UNKNOWN, (int) V4SI_FTYPE_QI },
32840 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv8si, "__builtin_ia32_cvtmask2d256", IX86_BUILTIN_CVTMASK2D256, UNKNOWN, (int) V8SI_FTYPE_QI },
32841 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv2di, "__builtin_ia32_cvtmask2q128", IX86_BUILTIN_CVTMASK2Q128, UNKNOWN, (int) V2DI_FTYPE_QI },
32842 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv4di, "__builtin_ia32_cvtmask2q256", IX86_BUILTIN_CVTMASK2Q256, UNKNOWN, (int) V4DI_FTYPE_QI },
32843 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16qi3_mask, "__builtin_ia32_pcmpeqb128_mask", IX86_BUILTIN_PCMPEQB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32844 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv32qi3_mask, "__builtin_ia32_pcmpeqb256_mask", IX86_BUILTIN_PCMPEQB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32845 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8hi3_mask, "__builtin_ia32_pcmpeqw128_mask", IX86_BUILTIN_PCMPEQW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32846 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16hi3_mask, "__builtin_ia32_pcmpeqw256_mask", IX86_BUILTIN_PCMPEQW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32847 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4si3_mask, "__builtin_ia32_pcmpeqd128_mask", IX86_BUILTIN_PCMPEQD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32848 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8si3_mask, "__builtin_ia32_pcmpeqd256_mask", IX86_BUILTIN_PCMPEQD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32849 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv2di3_mask, "__builtin_ia32_pcmpeqq128_mask", IX86_BUILTIN_PCMPEQQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32850 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4di3_mask, "__builtin_ia32_pcmpeqq256_mask", IX86_BUILTIN_PCMPEQQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32851 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16qi3_mask, "__builtin_ia32_pcmpgtb128_mask", IX86_BUILTIN_PCMPGTB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32852 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv32qi3_mask, "__builtin_ia32_pcmpgtb256_mask", IX86_BUILTIN_PCMPGTB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32853 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8hi3_mask, "__builtin_ia32_pcmpgtw128_mask", IX86_BUILTIN_PCMPGTW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32854 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16hi3_mask, "__builtin_ia32_pcmpgtw256_mask", IX86_BUILTIN_PCMPGTW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32855 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4si3_mask, "__builtin_ia32_pcmpgtd128_mask", IX86_BUILTIN_PCMPGTD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32856 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8si3_mask, "__builtin_ia32_pcmpgtd256_mask", IX86_BUILTIN_PCMPGTD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32857 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv2di3_mask, "__builtin_ia32_pcmpgtq128_mask", IX86_BUILTIN_PCMPGTQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32858 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4di3_mask, "__builtin_ia32_pcmpgtq256_mask", IX86_BUILTIN_PCMPGTQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32859 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16qi3_mask, "__builtin_ia32_ptestmb128", IX86_BUILTIN_PTESTMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32860 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv32qi3_mask, "__builtin_ia32_ptestmb256", IX86_BUILTIN_PTESTMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32861 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8hi3_mask, "__builtin_ia32_ptestmw128", IX86_BUILTIN_PTESTMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32862 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16hi3_mask, "__builtin_ia32_ptestmw256", IX86_BUILTIN_PTESTMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32863 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4si3_mask, "__builtin_ia32_ptestmd128", IX86_BUILTIN_PTESTMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32864 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8si3_mask, "__builtin_ia32_ptestmd256", IX86_BUILTIN_PTESTMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32865 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv2di3_mask, "__builtin_ia32_ptestmq128", IX86_BUILTIN_PTESTMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32866 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4di3_mask, "__builtin_ia32_ptestmq256", IX86_BUILTIN_PTESTMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32867 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16qi3_mask, "__builtin_ia32_ptestnmb128", IX86_BUILTIN_PTESTNMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32868 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv32qi3_mask, "__builtin_ia32_ptestnmb256", IX86_BUILTIN_PTESTNMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32869 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8hi3_mask, "__builtin_ia32_ptestnmw128", IX86_BUILTIN_PTESTNMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32870 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16hi3_mask, "__builtin_ia32_ptestnmw256", IX86_BUILTIN_PTESTNMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32871 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4si3_mask, "__builtin_ia32_ptestnmd128", IX86_BUILTIN_PTESTNMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32872 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8si3_mask, "__builtin_ia32_ptestnmd256", IX86_BUILTIN_PTESTNMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32873 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv2di3_mask, "__builtin_ia32_ptestnmq128", IX86_BUILTIN_PTESTNMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32874 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4di3_mask, "__builtin_ia32_ptestnmq256", IX86_BUILTIN_PTESTNMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32875 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv2di, "__builtin_ia32_broadcastmb128", IX86_BUILTIN_PBROADCASTMB128, UNKNOWN, (int) V2DI_FTYPE_QI },
32876 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv4di, "__builtin_ia32_broadcastmb256", IX86_BUILTIN_PBROADCASTMB256, UNKNOWN, (int) V4DI_FTYPE_QI },
32877 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv4si, "__builtin_ia32_broadcastmw128", IX86_BUILTIN_PBROADCASTMW128, UNKNOWN, (int) V4SI_FTYPE_HI },
32878 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv8si, "__builtin_ia32_broadcastmw256", IX86_BUILTIN_PBROADCASTMW256, UNKNOWN, (int) V8SI_FTYPE_HI },
32879 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4df_mask, "__builtin_ia32_compressdf256_mask", IX86_BUILTIN_COMPRESSPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32880 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2df_mask, "__builtin_ia32_compressdf128_mask", IX86_BUILTIN_COMPRESSPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32881 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8sf_mask, "__builtin_ia32_compresssf256_mask", IX86_BUILTIN_COMPRESSPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32882 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4sf_mask, "__builtin_ia32_compresssf128_mask", IX86_BUILTIN_COMPRESSPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32883 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4di_mask, "__builtin_ia32_compressdi256_mask", IX86_BUILTIN_PCOMPRESSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32884 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2di_mask, "__builtin_ia32_compressdi128_mask", IX86_BUILTIN_PCOMPRESSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32885 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8si_mask, "__builtin_ia32_compresssi256_mask", IX86_BUILTIN_PCOMPRESSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32886 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4si_mask, "__builtin_ia32_compresssi128_mask", IX86_BUILTIN_PCOMPRESSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32887 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expanddf256_mask", IX86_BUILTIN_EXPANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32888 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expanddf128_mask", IX86_BUILTIN_EXPANDPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32889 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandsf256_mask", IX86_BUILTIN_EXPANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32890 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandsf128_mask", IX86_BUILTIN_EXPANDPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32891 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expanddi256_mask", IX86_BUILTIN_PEXPANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32892 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expanddi128_mask", IX86_BUILTIN_PEXPANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32893 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandsi256_mask", IX86_BUILTIN_PEXPANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32894 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandsi128_mask", IX86_BUILTIN_PEXPANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32895 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expanddf256_maskz", IX86_BUILTIN_EXPANDPD256Z, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32896 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expanddf128_maskz", IX86_BUILTIN_EXPANDPD128Z, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32897 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandsf256_maskz", IX86_BUILTIN_EXPANDPS256Z, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32898 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandsf128_maskz", IX86_BUILTIN_EXPANDPS128Z, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32899 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expanddi256_maskz", IX86_BUILTIN_PEXPANDQ256Z, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32900 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expanddi128_maskz", IX86_BUILTIN_PEXPANDQ128Z, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32901 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandsi256_maskz", IX86_BUILTIN_PEXPANDD256Z, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32902 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandsi128_maskz", IX86_BUILTIN_PEXPANDD128Z, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32903 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8si3_mask, "__builtin_ia32_pmaxsd256_mask", IX86_BUILTIN_PMAXSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32904 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8si3_mask, "__builtin_ia32_pminsd256_mask", IX86_BUILTIN_PMINSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32905 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8si3_mask, "__builtin_ia32_pmaxud256_mask", IX86_BUILTIN_PMAXUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32906 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8si3_mask, "__builtin_ia32_pminud256_mask", IX86_BUILTIN_PMINUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32907 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4si3_mask, "__builtin_ia32_pmaxsd128_mask", IX86_BUILTIN_PMAXSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32908 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4si3_mask, "__builtin_ia32_pminsd128_mask", IX86_BUILTIN_PMINSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32909 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4si3_mask, "__builtin_ia32_pmaxud128_mask", IX86_BUILTIN_PMAXUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32910 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4si3_mask, "__builtin_ia32_pminud128_mask", IX86_BUILTIN_PMINUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32911 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4di3_mask, "__builtin_ia32_pmaxsq256_mask", IX86_BUILTIN_PMAXSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32912 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4di3_mask, "__builtin_ia32_pminsq256_mask", IX86_BUILTIN_PMINSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32913 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4di3_mask, "__builtin_ia32_pmaxuq256_mask", IX86_BUILTIN_PMAXUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32914 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4di3_mask, "__builtin_ia32_pminuq256_mask", IX86_BUILTIN_PMINUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32915 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2di3_mask, "__builtin_ia32_pmaxsq128_mask", IX86_BUILTIN_PMAXSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32916 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2di3_mask, "__builtin_ia32_pminsq128_mask", IX86_BUILTIN_PMINSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32917 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv2di3_mask, "__builtin_ia32_pmaxuq128_mask", IX86_BUILTIN_PMAXUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32918 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv2di3_mask, "__builtin_ia32_pminuq128_mask", IX86_BUILTIN_PMINUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32919 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv32qi3_mask, "__builtin_ia32_pminsb256_mask", IX86_BUILTIN_PMINSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32920 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv32qi3_mask, "__builtin_ia32_pminub256_mask", IX86_BUILTIN_PMINUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32921 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv32qi3_mask, "__builtin_ia32_pmaxsb256_mask", IX86_BUILTIN_PMAXSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32922 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv32qi3_mask, "__builtin_ia32_pmaxub256_mask", IX86_BUILTIN_PMAXUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32923 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16qi3_mask, "__builtin_ia32_pminsb128_mask", IX86_BUILTIN_PMINSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32924 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16qi3_mask, "__builtin_ia32_pminub128_mask", IX86_BUILTIN_PMINUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32925 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16qi3_mask, "__builtin_ia32_pmaxsb128_mask", IX86_BUILTIN_PMAXSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32926 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16qi3_mask, "__builtin_ia32_pmaxub128_mask", IX86_BUILTIN_PMAXUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32927 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16hi3_mask, "__builtin_ia32_pminsw256_mask", IX86_BUILTIN_PMINSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32928 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16hi3_mask, "__builtin_ia32_pminuw256_mask", IX86_BUILTIN_PMINUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32929 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16hi3_mask, "__builtin_ia32_pmaxsw256_mask", IX86_BUILTIN_PMAXSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32930 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16hi3_mask, "__builtin_ia32_pmaxuw256_mask", IX86_BUILTIN_PMAXUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32931 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8hi3_mask, "__builtin_ia32_pminsw128_mask", IX86_BUILTIN_PMINSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32932 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8hi3_mask, "__builtin_ia32_pminuw128_mask", IX86_BUILTIN_PMINUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32933 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8hi3_mask, "__builtin_ia32_pmaxsw128_mask", IX86_BUILTIN_PMAXSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32934 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8hi3_mask, "__builtin_ia32_pmaxuw128_mask", IX86_BUILTIN_PMAXUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32935 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4di_mask, "__builtin_ia32_vpconflictdi_256_mask", IX86_BUILTIN_VPCONFLICTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32936 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv8si_mask, "__builtin_ia32_vpconflictsi_256_mask", IX86_BUILTIN_VPCONFLICTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32937 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4di2_mask, "__builtin_ia32_vplzcntq_256_mask", IX86_BUILTIN_VPCLZCNTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32938 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv8si2_mask, "__builtin_ia32_vplzcntd_256_mask", IX86_BUILTIN_VPCLZCNTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32939 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhpd256_mask, "__builtin_ia32_unpckhpd256_mask", IX86_BUILTIN_UNPCKHPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32940 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpckhpd128_mask, "__builtin_ia32_unpckhpd128_mask", IX86_BUILTIN_UNPCKHPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32941 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhps256_mask, "__builtin_ia32_unpckhps256_mask", IX86_BUILTIN_UNPCKHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32942 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4sf_mask, "__builtin_ia32_unpckhps128_mask", IX86_BUILTIN_UNPCKHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32943 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklpd256_mask, "__builtin_ia32_unpcklpd256_mask", IX86_BUILTIN_UNPCKLPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32944 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpcklpd128_mask, "__builtin_ia32_unpcklpd128_mask", IX86_BUILTIN_UNPCKLPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32945 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklps256_mask, "__builtin_ia32_unpcklps256_mask", IX86_BUILTIN_UNPCKLPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32946 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv2di_mask, "__builtin_ia32_vpconflictdi_128_mask", IX86_BUILTIN_VPCONFLICTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32947 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4si_mask, "__builtin_ia32_vpconflictsi_128_mask", IX86_BUILTIN_VPCONFLICTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32948 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv2di2_mask, "__builtin_ia32_vplzcntq_128_mask", IX86_BUILTIN_VPCLZCNTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32949 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4si2_mask, "__builtin_ia32_vplzcntd_128_mask", IX86_BUILTIN_VPCLZCNTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32950 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_unpcklps128_mask, "__builtin_ia32_unpcklps128_mask", IX86_BUILTIN_UNPCKLPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32951 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv8si_mask, "__builtin_ia32_alignd256_mask", IX86_BUILTIN_ALIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32952 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4di_mask, "__builtin_ia32_alignq256_mask", IX86_BUILTIN_ALIGNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32953 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4si_mask, "__builtin_ia32_alignd128_mask", IX86_BUILTIN_ALIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI },
32954 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv2di_mask, "__builtin_ia32_alignq128_mask", IX86_BUILTIN_ALIGNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI },
32955 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph256_mask, "__builtin_ia32_vcvtps2ph256_mask", IX86_BUILTIN_CVTPS2PH256_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT_V8HI_QI },
32956 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph_mask, "__builtin_ia32_vcvtps2ph_mask", IX86_BUILTIN_CVTPS2PH_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT_V8HI_QI },
32957 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps_mask, "__builtin_ia32_vcvtph2ps_mask", IX86_BUILTIN_CVTPH2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V8HI_V4SF_QI },
32958 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps256_mask, "__builtin_ia32_vcvtph2ps256_mask", IX86_BUILTIN_CVTPH2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8HI_V8SF_QI },
32959 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4si_mask, "__builtin_ia32_punpckhdq128_mask", IX86_BUILTIN_PUNPCKHDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32960 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv8si_mask, "__builtin_ia32_punpckhdq256_mask", IX86_BUILTIN_PUNPCKHDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32961 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv2di_mask, "__builtin_ia32_punpckhqdq128_mask", IX86_BUILTIN_PUNPCKHQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32962 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv4di_mask, "__builtin_ia32_punpckhqdq256_mask", IX86_BUILTIN_PUNPCKHQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32963 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv4si_mask, "__builtin_ia32_punpckldq128_mask", IX86_BUILTIN_PUNPCKLDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32964 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv8si_mask, "__builtin_ia32_punpckldq256_mask", IX86_BUILTIN_PUNPCKLDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32965 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv2di_mask, "__builtin_ia32_punpcklqdq128_mask", IX86_BUILTIN_PUNPCKLQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32966 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv4di_mask, "__builtin_ia32_punpcklqdq256_mask", IX86_BUILTIN_PUNPCKLQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32967 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv16qi_mask, "__builtin_ia32_punpckhbw128_mask", IX86_BUILTIN_PUNPCKHBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32968 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv32qi_mask, "__builtin_ia32_punpckhbw256_mask", IX86_BUILTIN_PUNPCKHBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32969 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv8hi_mask, "__builtin_ia32_punpckhwd128_mask", IX86_BUILTIN_PUNPCKHWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32970 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv16hi_mask, "__builtin_ia32_punpckhwd256_mask", IX86_BUILTIN_PUNPCKHWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32971 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv16qi_mask, "__builtin_ia32_punpcklbw128_mask", IX86_BUILTIN_PUNPCKLBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32972 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv32qi_mask, "__builtin_ia32_punpcklbw256_mask", IX86_BUILTIN_PUNPCKLBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32973 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv8hi_mask, "__builtin_ia32_punpcklwd128_mask", IX86_BUILTIN_PUNPCKLWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32974 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv16hi_mask, "__builtin_ia32_punpcklwd256_mask", IX86_BUILTIN_PUNPCKLWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32975 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv16hi_mask, "__builtin_ia32_psllv16hi_mask", IX86_BUILTIN_PSLLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32976 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv8hi_mask, "__builtin_ia32_psllv8hi_mask", IX86_BUILTIN_PSLLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32977 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packssdw_mask, "__builtin_ia32_packssdw256_mask", IX86_BUILTIN_PACKSSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32978 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packssdw_mask, "__builtin_ia32_packssdw128_mask", IX86_BUILTIN_PACKSSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32979 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packusdw_mask, "__builtin_ia32_packusdw256_mask", IX86_BUILTIN_PACKUSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32980 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_packusdw_mask, "__builtin_ia32_packusdw128_mask", IX86_BUILTIN_PACKUSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32981 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv32qi3_mask, "__builtin_ia32_pavgb256_mask", IX86_BUILTIN_PAVGB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32982 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv16hi3_mask, "__builtin_ia32_pavgw256_mask", IX86_BUILTIN_PAVGW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32983 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv16qi3_mask, "__builtin_ia32_pavgb128_mask", IX86_BUILTIN_PAVGB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32984 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv8hi3_mask, "__builtin_ia32_pavgw128_mask", IX86_BUILTIN_PAVGW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32985 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8sf_mask, "__builtin_ia32_permvarsf256_mask", IX86_BUILTIN_VPERMVARSF256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32986 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4df_mask, "__builtin_ia32_permvardf256_mask", IX86_BUILTIN_VPERMVARDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32987 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4df_mask, "__builtin_ia32_permdf256_mask", IX86_BUILTIN_VPERMDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32988 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv32qi2_mask, "__builtin_ia32_pabsb256_mask", IX86_BUILTIN_PABSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32989 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16qi2_mask, "__builtin_ia32_pabsb128_mask", IX86_BUILTIN_PABSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32990 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16hi2_mask, "__builtin_ia32_pabsw256_mask", IX86_BUILTIN_PABSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32991 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8hi2_mask, "__builtin_ia32_pabsw128_mask", IX86_BUILTIN_PABSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32992 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv2df3_mask, "__builtin_ia32_vpermilvarpd_mask", IX86_BUILTIN_VPERMILVARPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32993 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4sf3_mask, "__builtin_ia32_vpermilvarps_mask", IX86_BUILTIN_VPERMILVARPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32994 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4df3_mask, "__builtin_ia32_vpermilvarpd256_mask", IX86_BUILTIN_VPERMILVARPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32995 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv8sf3_mask, "__builtin_ia32_vpermilvarps256_mask", IX86_BUILTIN_VPERMILVARPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32996 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv2df_mask, "__builtin_ia32_vpermilpd_mask", IX86_BUILTIN_VPERMILPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32997 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4sf_mask, "__builtin_ia32_vpermilps_mask", IX86_BUILTIN_VPERMILPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32998 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4df_mask, "__builtin_ia32_vpermilpd256_mask", IX86_BUILTIN_VPERMILPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32999 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv8sf_mask, "__builtin_ia32_vpermilps256_mask", IX86_BUILTIN_VPERMILPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
33000 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4di, "__builtin_ia32_blendmq_256_mask", IX86_BUILTIN_BLENDMQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
33001 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8si, "__builtin_ia32_blendmd_256_mask", IX86_BUILTIN_BLENDMD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
33002 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4df, "__builtin_ia32_blendmpd_256_mask", IX86_BUILTIN_BLENDMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
33003 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8sf, "__builtin_ia32_blendmps_256_mask", IX86_BUILTIN_BLENDMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
33004 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2di, "__builtin_ia32_blendmq_128_mask", IX86_BUILTIN_BLENDMQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
33005 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4si, "__builtin_ia32_blendmd_128_mask", IX86_BUILTIN_BLENDMD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
33006 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2df, "__builtin_ia32_blendmpd_128_mask", IX86_BUILTIN_BLENDMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
33007 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4sf, "__builtin_ia32_blendmps_128_mask", IX86_BUILTIN_BLENDMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
33008 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16hi, "__builtin_ia32_blendmw_256_mask", IX86_BUILTIN_BLENDMW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
33009 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv32qi, "__builtin_ia32_blendmb_256_mask", IX86_BUILTIN_BLENDMB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
33010 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8hi, "__builtin_ia32_blendmw_128_mask", IX86_BUILTIN_BLENDMW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
33011 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16qi, "__builtin_ia32_blendmb_128_mask", IX86_BUILTIN_BLENDMB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
33012 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8si3_mask, "__builtin_ia32_pmulld256_mask", IX86_BUILTIN_PMULLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
33013 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4si3_mask, "__builtin_ia32_pmulld128_mask", IX86_BUILTIN_PMULLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
33014 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v8si_mask, "__builtin_ia32_pmuludq256_mask", IX86_BUILTIN_PMULUDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
33015 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_smult_even_v8si_mask, "__builtin_ia32_pmuldq256_mask", IX86_BUILTIN_PMULDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
33016 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_mulv2siv2di3_mask, "__builtin_ia32_pmuldq128_mask", IX86_BUILTIN_PMULDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
33017 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v4si_mask, "__builtin_ia32_pmuludq128_mask", IX86_BUILTIN_PMULUDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
33018 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2ps256_mask, "__builtin_ia32_cvtpd2ps256_mask", IX86_BUILTIN_CVTPD2PS256_MASK, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_QI },
33019 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2ps_mask, "__builtin_ia32_cvtpd2ps_mask", IX86_BUILTIN_CVTPD2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V2DF_V4SF_QI },
33020 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8si_mask, "__builtin_ia32_permvarsi256_mask", IX86_BUILTIN_VPERMVARSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
33021 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4di_mask, "__builtin_ia32_permvardi256_mask", IX86_BUILTIN_VPERMVARDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33022 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4di_mask, "__builtin_ia32_permdi256_mask", IX86_BUILTIN_VPERMDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
33023 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4di3_mask, "__builtin_ia32_cmpq256_mask", IX86_BUILTIN_CMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
33024 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8si3_mask, "__builtin_ia32_cmpd256_mask", IX86_BUILTIN_CMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
33025 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4di3_mask, "__builtin_ia32_ucmpq256_mask", IX86_BUILTIN_UCMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
33026 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8si3_mask, "__builtin_ia32_ucmpd256_mask", IX86_BUILTIN_UCMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
33027 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv32qi3_mask, "__builtin_ia32_cmpb256_mask", IX86_BUILTIN_CMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
33028 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16hi3_mask, "__builtin_ia32_cmpw256_mask", IX86_BUILTIN_CMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
33029 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv32qi3_mask, "__builtin_ia32_ucmpb256_mask", IX86_BUILTIN_UCMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
33030 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16hi3_mask, "__builtin_ia32_ucmpw256_mask", IX86_BUILTIN_UCMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
33031 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4df3_mask, "__builtin_ia32_cmppd256_mask", IX86_BUILTIN_CMPPD256_MASK, UNKNOWN, (int) QI_FTYPE_V4DF_V4DF_INT_QI },
33032 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8sf3_mask, "__builtin_ia32_cmpps256_mask", IX86_BUILTIN_CMPPS256_MASK, UNKNOWN, (int) QI_FTYPE_V8SF_V8SF_INT_QI },
33033 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2di3_mask, "__builtin_ia32_cmpq128_mask", IX86_BUILTIN_CMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
33034 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4si3_mask, "__builtin_ia32_cmpd128_mask", IX86_BUILTIN_CMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
33035 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv2di3_mask, "__builtin_ia32_ucmpq128_mask", IX86_BUILTIN_UCMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
33036 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4si3_mask, "__builtin_ia32_ucmpd128_mask", IX86_BUILTIN_UCMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
33037 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16qi3_mask, "__builtin_ia32_cmpb128_mask", IX86_BUILTIN_CMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
33038 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8hi3_mask, "__builtin_ia32_cmpw128_mask", IX86_BUILTIN_CMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
33039 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16qi3_mask, "__builtin_ia32_ucmpb128_mask", IX86_BUILTIN_UCMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
33040 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8hi3_mask, "__builtin_ia32_ucmpw128_mask", IX86_BUILTIN_UCMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
33041 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2df3_mask, "__builtin_ia32_cmppd128_mask", IX86_BUILTIN_CMPPD128_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI },
33042 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4sf3_mask, "__builtin_ia32_cmpps128_mask", IX86_BUILTIN_CMPPS128_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI },
33044 /* AVX512DQ. */
33045 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x2_512_mask", IX86_BUILTIN_BROADCASTF32x2_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
33046 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask, "__builtin_ia32_broadcasti32x2_512_mask", IX86_BUILTIN_BROADCASTI32x2_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
33047 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8df_mask_1, "__builtin_ia32_broadcastf64x2_512_mask", IX86_BUILTIN_BROADCASTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
33048 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8di_mask_1, "__builtin_ia32_broadcasti64x2_512_mask", IX86_BUILTIN_BROADCASTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
33049 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask_1, "__builtin_ia32_broadcastf32x8_512_mask", IX86_BUILTIN_BROADCASTF32X8_512, UNKNOWN, (int) V16SF_FTYPE_V8SF_V16SF_HI },
33050 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask_1, "__builtin_ia32_broadcasti32x8_512_mask", IX86_BUILTIN_BROADCASTI32X8_512, UNKNOWN, (int) V16SI_FTYPE_V8SI_V16SI_HI },
33051 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf64x2_mask, "__builtin_ia32_extractf64x2_512_mask", IX86_BUILTIN_EXTRACTF64X2_512, UNKNOWN, (int) V2DF_FTYPE_V8DF_INT_V2DF_QI },
33052 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf32x8_mask, "__builtin_ia32_extractf32x8_mask", IX86_BUILTIN_EXTRACTF32X8, UNKNOWN, (int) V8SF_FTYPE_V16SF_INT_V8SF_QI },
33053 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti64x2_mask, "__builtin_ia32_extracti64x2_512_mask", IX86_BUILTIN_EXTRACTI64X2_512, UNKNOWN, (int) V2DI_FTYPE_V8DI_INT_V2DI_QI },
33054 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti32x8_mask, "__builtin_ia32_extracti32x8_mask", IX86_BUILTIN_EXTRACTI32X8, UNKNOWN, (int) V8SI_FTYPE_V16SI_INT_V8SI_QI },
33055 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv8df_mask, "__builtin_ia32_reducepd512_mask", IX86_BUILTIN_REDUCEPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
33056 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv16sf_mask, "__builtin_ia32_reduceps512_mask", IX86_BUILTIN_REDUCEPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
33057 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_mulv8di3_mask, "__builtin_ia32_pmullq512_mask", IX86_BUILTIN_PMULLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33058 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv8df3_mask, "__builtin_ia32_xorpd512_mask", IX86_BUILTIN_XORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
33059 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv16sf3_mask, "__builtin_ia32_xorps512_mask", IX86_BUILTIN_XORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
33060 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv8df3_mask, "__builtin_ia32_orpd512_mask", IX86_BUILTIN_ORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
33061 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv16sf3_mask, "__builtin_ia32_orps512_mask", IX86_BUILTIN_ORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
33062 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv8df3_mask, "__builtin_ia32_andpd512_mask", IX86_BUILTIN_ANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
33063 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv16sf3_mask, "__builtin_ia32_andps512_mask", IX86_BUILTIN_ANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
33064 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv8df3_mask, "__builtin_ia32_andnpd512_mask", IX86_BUILTIN_ANDNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI},
33065 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv16sf3_mask, "__builtin_ia32_andnps512_mask", IX86_BUILTIN_ANDNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
33066 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf32x8_mask, "__builtin_ia32_insertf32x8_mask", IX86_BUILTIN_INSERTF32X8, UNKNOWN, (int) V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI },
33067 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti32x8_mask, "__builtin_ia32_inserti32x8_mask", IX86_BUILTIN_INSERTI32X8, UNKNOWN, (int) V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI },
33068 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf64x2_mask, "__builtin_ia32_insertf64x2_512_mask", IX86_BUILTIN_INSERTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI },
33069 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti64x2_mask, "__builtin_ia32_inserti64x2_512_mask", IX86_BUILTIN_INSERTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI },
33070 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv8df_mask, "__builtin_ia32_fpclasspd512_mask", IX86_BUILTIN_FPCLASSPD512, UNKNOWN, (int) QI_FTYPE_V8DF_INT_QI },
33071 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv16sf_mask, "__builtin_ia32_fpclassps512_mask", IX86_BUILTIN_FPCLASSPS512, UNKNOWN, (int) HI_FTYPE_V16SF_INT_HI },
33072 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtd2maskv16si, "__builtin_ia32_cvtd2mask512", IX86_BUILTIN_CVTD2MASK512, UNKNOWN, (int) HI_FTYPE_V16SI },
33073 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtq2maskv8di, "__builtin_ia32_cvtq2mask512", IX86_BUILTIN_CVTQ2MASK512, UNKNOWN, (int) QI_FTYPE_V8DI },
33074 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2dv16si, "__builtin_ia32_cvtmask2d512", IX86_BUILTIN_CVTMASK2D512, UNKNOWN, (int) V16SI_FTYPE_HI },
33075 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2qv8di, "__builtin_ia32_cvtmask2q512", IX86_BUILTIN_CVTMASK2Q512, UNKNOWN, (int) V8DI_FTYPE_QI },
33077 /* AVX512BW. */
33078 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpcksi, "__builtin_ia32_kunpcksi", IX86_BUILTIN_KUNPCKWD, UNKNOWN, (int) SI_FTYPE_SI_SI },
33079 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpckdi, "__builtin_ia32_kunpckdi", IX86_BUILTIN_KUNPCKDQ, UNKNOWN, (int) DI_FTYPE_DI_DI },
33080 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packusdw_mask, "__builtin_ia32_packusdw512_mask", IX86_BUILTIN_PACKUSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
33081 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlv4ti3, "__builtin_ia32_pslldq512", IX86_BUILTIN_PSLLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
33082 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrv4ti3, "__builtin_ia32_psrldq512", IX86_BUILTIN_PSRLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
33083 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packssdw_mask, "__builtin_ia32_packssdw512_mask", IX86_BUILTIN_PACKSSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
33084 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv4ti, "__builtin_ia32_palignr512", IX86_BUILTIN_PALIGNR512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_CONVERT },
33085 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv64qi_mask, "__builtin_ia32_palignr512_mask", IX86_BUILTIN_PALIGNR512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT },
33086 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_movdquhi512_mask", IX86_BUILTIN_MOVDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
33087 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_movdquqi512_mask", IX86_BUILTIN_MOVDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
33088 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_psadbw, "__builtin_ia32_psadbw512", IX86_BUILTIN_PSADBW512, UNKNOWN, (int) V8DI_FTYPE_V64QI_V64QI },
33089 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_dbpsadbwv32hi_mask, "__builtin_ia32_dbpsadbw512_mask", IX86_BUILTIN_DBPSADBW512, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI },
33090 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv64qi_mask, "__builtin_ia32_pbroadcastb512_mask", IX86_BUILTIN_PBROADCASTB512, UNKNOWN, (int) V64QI_FTYPE_V16QI_V64QI_DI },
33091 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv64qi_mask, "__builtin_ia32_pbroadcastb512_gpr_mask", IX86_BUILTIN_PBROADCASTB512_GPR, UNKNOWN, (int) V64QI_FTYPE_QI_V64QI_DI },
33092 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv32hi_mask, "__builtin_ia32_pbroadcastw512_mask", IX86_BUILTIN_PBROADCASTW512, UNKNOWN, (int) V32HI_FTYPE_V8HI_V32HI_SI },
33093 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv32hi_mask, "__builtin_ia32_pbroadcastw512_gpr_mask", IX86_BUILTIN_PBROADCASTW512_GPR, UNKNOWN, (int) V32HI_FTYPE_HI_V32HI_SI },
33094 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sign_extendv32qiv32hi2_mask, "__builtin_ia32_pmovsxbw512_mask", IX86_BUILTIN_PMOVSXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
33095 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_zero_extendv32qiv32hi2_mask, "__builtin_ia32_pmovzxbw512_mask", IX86_BUILTIN_PMOVZXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
33096 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_permvarv32hi_mask, "__builtin_ia32_permvarhi512_mask", IX86_BUILTIN_VPERMVARHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33097 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_mask, "__builtin_ia32_vpermt2varhi512_mask", IX86_BUILTIN_VPERMT2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33098 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_maskz, "__builtin_ia32_vpermt2varhi512_maskz", IX86_BUILTIN_VPERMT2VARHI512_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33099 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermi2varv32hi3_mask, "__builtin_ia32_vpermi2varhi512_mask", IX86_BUILTIN_VPERMI2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33100 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv64qi3_mask, "__builtin_ia32_pavgb512_mask", IX86_BUILTIN_PAVGB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33101 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv32hi3_mask, "__builtin_ia32_pavgw512_mask", IX86_BUILTIN_PAVGW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33102 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv64qi3_mask, "__builtin_ia32_paddb512_mask", IX86_BUILTIN_PADDB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33103 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv64qi3_mask, "__builtin_ia32_psubb512_mask", IX86_BUILTIN_PSUBB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33104 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv64qi3_mask, "__builtin_ia32_psubsb512_mask", IX86_BUILTIN_PSUBSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33105 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv64qi3_mask, "__builtin_ia32_paddsb512_mask", IX86_BUILTIN_PADDSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33106 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv64qi3_mask, "__builtin_ia32_psubusb512_mask", IX86_BUILTIN_PSUBUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33107 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv64qi3_mask, "__builtin_ia32_paddusb512_mask", IX86_BUILTIN_PADDUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33108 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv32hi3_mask, "__builtin_ia32_psubw512_mask", IX86_BUILTIN_PSUBW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33109 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv32hi3_mask, "__builtin_ia32_paddw512_mask", IX86_BUILTIN_PADDW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33110 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv32hi3_mask, "__builtin_ia32_psubsw512_mask", IX86_BUILTIN_PSUBSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33111 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv32hi3_mask, "__builtin_ia32_paddsw512_mask", IX86_BUILTIN_PADDSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33112 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv32hi3_mask, "__builtin_ia32_psubusw512_mask", IX86_BUILTIN_PSUBUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33113 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv32hi3_mask, "__builtin_ia32_paddusw512_mask", IX86_BUILTIN_PADDUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33114 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv32hi3_mask, "__builtin_ia32_pmaxuw512_mask", IX86_BUILTIN_PMAXUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33115 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv32hi3_mask, "__builtin_ia32_pmaxsw512_mask", IX86_BUILTIN_PMAXSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33116 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv32hi3_mask, "__builtin_ia32_pminuw512_mask", IX86_BUILTIN_PMINUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33117 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv32hi3_mask, "__builtin_ia32_pminsw512_mask", IX86_BUILTIN_PMINSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33118 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv64qi3_mask, "__builtin_ia32_pmaxub512_mask", IX86_BUILTIN_PMAXUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33119 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv64qi3_mask, "__builtin_ia32_pmaxsb512_mask", IX86_BUILTIN_PMAXSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33120 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv64qi3_mask, "__builtin_ia32_pminub512_mask", IX86_BUILTIN_PMINUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33121 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv64qi3_mask, "__builtin_ia32_pminsb512_mask", IX86_BUILTIN_PMINSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33122 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovwb512_mask", IX86_BUILTIN_PMOVWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
33123 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ss_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovswb512_mask", IX86_BUILTIN_PMOVSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
33124 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_us_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovuswb512_mask", IX86_BUILTIN_PMOVUSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
33125 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_umulhrswv32hi3_mask, "__builtin_ia32_pmulhrsw512_mask", IX86_BUILTIN_PMULHRSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33126 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umulv32hi3_highpart_mask, "__builtin_ia32_pmulhuw512_mask" , IX86_BUILTIN_PMULHUW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33127 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smulv32hi3_highpart_mask, "__builtin_ia32_pmulhw512_mask" , IX86_BUILTIN_PMULHW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33128 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_mulv32hi3_mask, "__builtin_ia32_pmullw512_mask", IX86_BUILTIN_PMULLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33129 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllwi512_mask", IX86_BUILTIN_PSLLWI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
33130 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllw512_mask", IX86_BUILTIN_PSLLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
33131 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packsswb_mask, "__builtin_ia32_packsswb512_mask", IX86_BUILTIN_PACKSSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
33132 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packuswb_mask, "__builtin_ia32_packuswb512_mask", IX86_BUILTIN_PACKUSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
33133 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashrvv32hi_mask, "__builtin_ia32_psrav32hi_mask", IX86_BUILTIN_PSRAVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33134 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddubsw512v32hi_mask, "__builtin_ia32_pmaddubsw512_mask", IX86_BUILTIN_PMADDUBSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_V32HI_SI },
33135 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddwd512v32hi_mask, "__builtin_ia32_pmaddwd512_mask", IX86_BUILTIN_PMADDWD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V32HI_V32HI_V16SI_HI },
33136 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrvv32hi_mask, "__builtin_ia32_psrlv32hi_mask", IX86_BUILTIN_PSRLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33137 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv64qi_mask, "__builtin_ia32_punpckhbw512_mask", IX86_BUILTIN_PUNPCKHBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33138 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv32hi_mask, "__builtin_ia32_punpckhwd512_mask", IX86_BUILTIN_PUNPCKHWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33139 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv64qi_mask, "__builtin_ia32_punpcklbw512_mask", IX86_BUILTIN_PUNPCKLBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33140 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv32hi_mask, "__builtin_ia32_punpcklwd512_mask", IX86_BUILTIN_PUNPCKLWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33141 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufbv64qi3_mask, "__builtin_ia32_pshufb512_mask", IX86_BUILTIN_PSHUFB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33142 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufhwv32hi_mask, "__builtin_ia32_pshufhw512_mask", IX86_BUILTIN_PSHUFHW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
33143 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshuflwv32hi_mask, "__builtin_ia32_pshuflw512_mask", IX86_BUILTIN_PSHUFLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
33144 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psrawi512_mask", IX86_BUILTIN_PSRAWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
33145 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psraw512_mask", IX86_BUILTIN_PSRAW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
33146 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlwi512_mask", IX86_BUILTIN_PSRLWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
33147 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlw512_mask", IX86_BUILTIN_PSRLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
33148 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtb2maskv64qi, "__builtin_ia32_cvtb2mask512", IX86_BUILTIN_CVTB2MASK512, UNKNOWN, (int) DI_FTYPE_V64QI },
33149 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtw2maskv32hi, "__builtin_ia32_cvtw2mask512", IX86_BUILTIN_CVTW2MASK512, UNKNOWN, (int) SI_FTYPE_V32HI },
33150 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2bv64qi, "__builtin_ia32_cvtmask2b512", IX86_BUILTIN_CVTMASK2B512, UNKNOWN, (int) V64QI_FTYPE_DI },
33151 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2wv32hi, "__builtin_ia32_cvtmask2w512", IX86_BUILTIN_CVTMASK2W512, UNKNOWN, (int) V32HI_FTYPE_SI },
33152 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv64qi3_mask, "__builtin_ia32_pcmpeqb512_mask", IX86_BUILTIN_PCMPEQB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
33153 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv32hi3_mask, "__builtin_ia32_pcmpeqw512_mask", IX86_BUILTIN_PCMPEQW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
33154 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv64qi3_mask, "__builtin_ia32_pcmpgtb512_mask", IX86_BUILTIN_PCMPGTB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
33155 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv32hi3_mask, "__builtin_ia32_pcmpgtw512_mask", IX86_BUILTIN_PCMPGTW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
33156 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv64qi3_mask, "__builtin_ia32_ptestmb512", IX86_BUILTIN_PTESTMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
33157 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv32hi3_mask, "__builtin_ia32_ptestmw512", IX86_BUILTIN_PTESTMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
33158 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv64qi3_mask, "__builtin_ia32_ptestnmb512", IX86_BUILTIN_PTESTNMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
33159 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv32hi3_mask, "__builtin_ia32_ptestnmw512", IX86_BUILTIN_PTESTNMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
33160 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlvv32hi_mask, "__builtin_ia32_psllv32hi_mask", IX86_BUILTIN_PSLLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33161 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv64qi2_mask, "__builtin_ia32_pabsb512_mask", IX86_BUILTIN_PABSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
33162 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv32hi2_mask, "__builtin_ia32_pabsw512_mask", IX86_BUILTIN_PABSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
33163 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv32hi, "__builtin_ia32_blendmw_512_mask", IX86_BUILTIN_BLENDMW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
33164 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv64qi, "__builtin_ia32_blendmb_512_mask", IX86_BUILTIN_BLENDMB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
33165 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv64qi3_mask, "__builtin_ia32_cmpb512_mask", IX86_BUILTIN_CMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
33166 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
33167 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
33168 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
33170 /* AVX512IFMA */
33171 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_mask, "__builtin_ia32_vpmadd52luq512_mask", IX86_BUILTIN_VPMADD52LUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33172 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_maskz, "__builtin_ia32_vpmadd52luq512_maskz", IX86_BUILTIN_VPMADD52LUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33173 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_mask, "__builtin_ia32_vpmadd52huq512_mask", IX86_BUILTIN_VPMADD52HUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33174 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_maskz, "__builtin_ia32_vpmadd52huq512_maskz", IX86_BUILTIN_VPMADD52HUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33175 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_mask, "__builtin_ia32_vpmadd52luq256_mask", IX86_BUILTIN_VPMADD52LUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33176 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_maskz, "__builtin_ia32_vpmadd52luq256_maskz", IX86_BUILTIN_VPMADD52LUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33177 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_mask, "__builtin_ia32_vpmadd52huq256_mask", IX86_BUILTIN_VPMADD52HUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33178 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_maskz, "__builtin_ia32_vpmadd52huq256_maskz", IX86_BUILTIN_VPMADD52HUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33179 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_mask, "__builtin_ia32_vpmadd52luq128_mask", IX86_BUILTIN_VPMADD52LUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33180 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_maskz, "__builtin_ia32_vpmadd52luq128_maskz", IX86_BUILTIN_VPMADD52LUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33181 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_mask, "__builtin_ia32_vpmadd52huq128_mask", IX86_BUILTIN_VPMADD52HUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33182 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_maskz, "__builtin_ia32_vpmadd52huq128_maskz", IX86_BUILTIN_VPMADD52HUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33184 /* AVX512VBMI */
33185 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_vpmultishiftqbv64qi_mask, "__builtin_ia32_vpmultishiftqb512_mask", IX86_BUILTIN_VPMULTISHIFTQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33186 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv32qi_mask, "__builtin_ia32_vpmultishiftqb256_mask", IX86_BUILTIN_VPMULTISHIFTQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33187 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv16qi_mask, "__builtin_ia32_vpmultishiftqb128_mask", IX86_BUILTIN_VPMULTISHIFTQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33188 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_permvarv64qi_mask, "__builtin_ia32_permvarqi512_mask", IX86_BUILTIN_VPERMVARQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33189 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_mask, "__builtin_ia32_vpermt2varqi512_mask", IX86_BUILTIN_VPERMT2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33190 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_maskz, "__builtin_ia32_vpermt2varqi512_maskz", IX86_BUILTIN_VPERMT2VARQI512_MASKZ, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33191 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermi2varv64qi3_mask, "__builtin_ia32_vpermi2varqi512_mask", IX86_BUILTIN_VPERMI2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33192 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv32qi_mask, "__builtin_ia32_permvarqi256_mask", IX86_BUILTIN_VPERMVARQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33193 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16qi_mask, "__builtin_ia32_permvarqi128_mask", IX86_BUILTIN_VPERMVARQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33194 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_mask, "__builtin_ia32_vpermt2varqi256_mask", IX86_BUILTIN_VPERMT2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33195 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_maskz, "__builtin_ia32_vpermt2varqi256_maskz", IX86_BUILTIN_VPERMT2VARQI256_MASKZ, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33196 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_mask, "__builtin_ia32_vpermt2varqi128_mask", IX86_BUILTIN_VPERMT2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33197 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_maskz, "__builtin_ia32_vpermt2varqi128_maskz", IX86_BUILTIN_VPERMT2VARQI128_MASKZ, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33198 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv32qi3_mask, "__builtin_ia32_vpermi2varqi256_mask", IX86_BUILTIN_VPERMI2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33199 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16qi3_mask, "__builtin_ia32_vpermi2varqi128_mask", IX86_BUILTIN_VPERMI2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33200 };
33202 /* Builtins with rounding support. */
33204 {
33205 /* AVX512F */
33206 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33207 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33208 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33209 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33210 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
33211 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
33212 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
33213 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
33214 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
33215 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
33216 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
33217 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33218 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
33219 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33220 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
33221 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33222 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
33223 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33224 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
33225 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
33226 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
33227 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
33228 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
33229 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33230 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33231 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33232 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33233 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
33234 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
33235 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
33236 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
33237 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33238 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33239 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33240 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33241 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
33242 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
33243 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
33244 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
33245 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
33246 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
33247 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
33248 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
33249 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33250 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33251 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33252 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33253 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
33254 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
33255 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33256 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33257 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33258 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33259 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33260 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33261 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33262 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33263 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33264 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33265 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33266 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33267 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33268 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33269 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
33270 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
33271 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33272 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33273 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33274 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33275 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33276 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33277 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33278 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33279 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33280 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33281 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33282 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33283 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33284 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33285 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
33286 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33287 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33288 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33289 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33290 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33291 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33292 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33293 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
33294 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33295 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33296 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33297 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33298 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33299 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33300 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33301 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33302 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33303 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33304 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33305 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33306 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33307 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
33308 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
33309 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33310 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33311 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33312 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33313 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33314 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33315 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33316 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33317 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33318 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33319 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33320 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33321 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33322 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33323 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33324 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33326 /* AVX512ER */
33327 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33328 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33329 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33330 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33331 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33332 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33333 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33334 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33335 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33336 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33338 /* AVX512DQ. */
33339 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv2df_round, "__builtin_ia32_rangesd128_round", IX86_BUILTIN_RANGESD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33340 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv4sf_round, "__builtin_ia32_rangess128_round", IX86_BUILTIN_RANGESS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33341 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2qq512_mask", IX86_BUILTIN_CVTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33342 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__builtin_ia32_cvtps2qq512_mask", IX86_BUILTIN_CVTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33343 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33344 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33345 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33346 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33347 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33348 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33349 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33350 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33351 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33352 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33353 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT },
33354 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT },
33355 };
33357 /* Bultins for MPX. */
33359 {
33360 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndstx", IX86_BUILTIN_BNDSTX, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND_PCVOID },
33361 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcl", IX86_BUILTIN_BNDCL, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33362 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcu", IX86_BUILTIN_BNDCU, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33363 };
33365 /* Const builtins for MPX. */
33367 {
33368 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndmk", IX86_BUILTIN_BNDMK, UNKNOWN, (int) BND_FTYPE_PCVOID_ULONG },
33369 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndldx", IX86_BUILTIN_BNDLDX, UNKNOWN, (int) BND_FTYPE_PCVOID_PCVOID },
33370 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_narrow_bounds", IX86_BUILTIN_BNDNARROW, UNKNOWN, (int) PVOID_FTYPE_PCVOID_BND_ULONG },
33371 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndint", IX86_BUILTIN_BNDINT, UNKNOWN, (int) BND_FTYPE_BND_BND },
33372 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_sizeof", IX86_BUILTIN_SIZEOF, UNKNOWN, (int) ULONG_FTYPE_VOID },
33373 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndlower", IX86_BUILTIN_BNDLOWER, UNKNOWN, (int) PVOID_FTYPE_BND },
33374 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndupper", IX86_BUILTIN_BNDUPPER, UNKNOWN, (int) PVOID_FTYPE_BND },
33375 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndret", IX86_BUILTIN_BNDRET, UNKNOWN, (int) BND_FTYPE_PCVOID },
33376 };
33378 /* FMA4 and XOP. */
33379 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
33380 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
33381 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
33382 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
33383 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
33384 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
33385 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
33386 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
33387 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
33388 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
33389 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
33390 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
33391 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
33392 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
33393 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
33394 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
33395 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
33396 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
33397 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
33398 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
33399 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
33400 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
33401 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
33402 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
33403 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
33404 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
33405 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
33406 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
33407 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
33408 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
33409 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
33410 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
33411 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
33412 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
33413 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
33414 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
33415 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
33416 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
33417 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
33418 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
33419 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
33420 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
33421 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
33422 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
33423 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
33424 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
33425 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
33426 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
33427 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
33428 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
33429 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
33430 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
33433 {
33474 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
33475 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
33476 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
33477 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
33478 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
33479 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
33480 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
33482 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33483 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33484 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
33485 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
33486 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
33487 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
33488 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
33490 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
33492 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33493 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33494 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33495 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33496 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33497 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33498 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33499 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33500 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33501 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33502 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33503 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33505 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33506 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
33507 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
33508 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
33509 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
33510 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
33511 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
33512 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
33513 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33514 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
33515 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
33516 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
33517 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33518 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
33519 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
33520 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
33522 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
33523 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
33524 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
33525 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
33526 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
33527 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
33529 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33530 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33531 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33532 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33533 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33534 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33535 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33536 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33537 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33538 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33539 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33540 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33541 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33542 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33543 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33545 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
33546 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33547 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33548 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
33549 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
33550 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
33551 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
33553 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
33554 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33555 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33556 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
33557 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
33558 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
33559 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
33561 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
33562 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33563 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33564 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
33565 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
33566 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
33567 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
33569 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33570 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33571 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33572 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
33573 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
33574 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
33575 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
33577 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
33578 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33579 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33580 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
33581 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
33582 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
33583 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
33585 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
33586 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33587 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33588 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
33589 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
33590 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
33591 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
33593 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
33594 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33595 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33596 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
33597 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
33598 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
33599 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
33601 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33602 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33603 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33604 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
33605 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
33606 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
33607 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
33609 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33610 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33611 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33612 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33613 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33614 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33615 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33616 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33618 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33619 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33620 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33621 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33622 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33623 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33624 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33625 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33627 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
33628 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
33629 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
33630 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
33632 };
33633 \f
33634 /* TM vector builtins. */
33636 /* Reuse the existing x86-specific `struct builtin_description' cause
33637 we're lazy. Add casts to make them fit. */
33639 {
33640 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33641 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33642 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33643 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33644 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33645 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33646 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33648 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33649 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33650 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33651 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33652 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33653 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33654 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33656 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33657 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33658 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33659 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33660 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33661 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33662 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33664 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
33665 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
33666 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
33667 };
33669 /* TM callbacks. */
33671 /* Return the builtin decl needed to load a vector of TYPE. */
33673 static tree
33675 {
33677 {
33679 {
33686 }
33687 }
33689 }
33691 /* Return the builtin decl needed to store a vector of TYPE. */
33693 static tree
33695 {
33697 {
33699 {
33706 }
33707 }
33709 }
33710 \f
33711 /* Initialize the transactional memory vector load/store builtins. */
33713 static void
33715 {
33719 tree decl;
33726 /* If there are no builtins defined, we must be compiling in a
33727 language without trans-mem support. */
33731 /* Use whatever attributes a normal TM load has. */
33735 /* Use whatever attributes a normal TM store has. */
33739 /* Use whatever attributes a normal TM log has. */
33747 {
33751 {
33759 {
33762 }
33764 {
33767 }
33768 else
33769 {
33772 }
33774 /* The builtin without the prefix for
33775 calling it directly. */
33777 attrs);
33778 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
33779 set the TYPE_ATTRIBUTES. */
33783 }
33784 }
33785 }
33787 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
33788 in the current target ISA to allow the user to compile particular modules
33789 with different target specific options that differ from the command line
33790 options. */
33791 static void
33793 {
33798 /* Add all special builtins with variable number of operands. */
33802 {
33808 }
33810 /* Add all builtins with variable number of operands. */
33814 {
33820 }
33822 /* Add all builtins with rounding. */
33826 {
33832 }
33834 /* pcmpestr[im] insns. */
33838 {
33841 else
33844 }
33846 /* pcmpistr[im] insns. */
33850 {
33853 else
33856 }
33858 /* comi/ucomi insns. */
33860 {
33863 else
33866 }
33868 /* SSE */
33874 /* SSE or 3DNow!A */
33877 IX86_BUILTIN_MASKMOVQ);
33879 /* SSE2 */
33888 /* SSE3. */
33894 /* AES */
33908 /* PCLMUL */
33912 /* RDRND */
33919 IX86_BUILTIN_RDRAND64_STEP);
33921 /* AVX2 */
33923 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
33924 IX86_BUILTIN_GATHERSIV2DF);
33927 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
33928 IX86_BUILTIN_GATHERSIV4DF);
33931 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
33932 IX86_BUILTIN_GATHERDIV2DF);
33935 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
33936 IX86_BUILTIN_GATHERDIV4DF);
33939 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
33940 IX86_BUILTIN_GATHERSIV4SF);
33943 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
33944 IX86_BUILTIN_GATHERSIV8SF);
33947 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
33948 IX86_BUILTIN_GATHERDIV4SF);
33951 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
33952 IX86_BUILTIN_GATHERDIV8SF);
33955 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
33956 IX86_BUILTIN_GATHERSIV2DI);
33959 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
33960 IX86_BUILTIN_GATHERSIV4DI);
33963 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
33964 IX86_BUILTIN_GATHERDIV2DI);
33967 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
33968 IX86_BUILTIN_GATHERDIV4DI);
33971 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
33972 IX86_BUILTIN_GATHERSIV4SI);
33975 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
33976 IX86_BUILTIN_GATHERSIV8SI);
33979 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
33980 IX86_BUILTIN_GATHERDIV4SI);
33983 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
33984 IX86_BUILTIN_GATHERDIV8SI);
33987 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
33988 IX86_BUILTIN_GATHERALTSIV4DF);
33991 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
33992 IX86_BUILTIN_GATHERALTDIV8SF);
33995 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
33996 IX86_BUILTIN_GATHERALTSIV4DI);
33999 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
34000 IX86_BUILTIN_GATHERALTDIV8SI);
34002 /* AVX512F */
34004 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
34005 IX86_BUILTIN_GATHER3SIV16SF);
34008 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
34009 IX86_BUILTIN_GATHER3SIV8DF);
34012 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
34013 IX86_BUILTIN_GATHER3DIV16SF);
34016 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
34017 IX86_BUILTIN_GATHER3DIV8DF);
34020 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
34021 IX86_BUILTIN_GATHER3SIV16SI);
34024 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
34025 IX86_BUILTIN_GATHER3SIV8DI);
34028 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
34029 IX86_BUILTIN_GATHER3DIV16SI);
34032 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
34033 IX86_BUILTIN_GATHER3DIV8DI);
34036 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
34037 IX86_BUILTIN_GATHER3ALTSIV8DF);
34040 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
34041 IX86_BUILTIN_GATHER3ALTDIV16SF);
34044 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
34045 IX86_BUILTIN_GATHER3ALTSIV8DI);
34048 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
34049 IX86_BUILTIN_GATHER3ALTDIV16SI);
34052 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
34053 IX86_BUILTIN_SCATTERSIV16SF);
34056 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
34057 IX86_BUILTIN_SCATTERSIV8DF);
34060 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
34061 IX86_BUILTIN_SCATTERDIV16SF);
34064 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
34065 IX86_BUILTIN_SCATTERDIV8DF);
34068 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
34069 IX86_BUILTIN_SCATTERSIV16SI);
34072 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
34073 IX86_BUILTIN_SCATTERSIV8DI);
34076 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
34077 IX86_BUILTIN_SCATTERDIV16SI);
34080 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
34081 IX86_BUILTIN_SCATTERDIV8DI);
34083 /* AVX512VL */
34085 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_QI_INT,
34086 IX86_BUILTIN_GATHER3SIV2DF);
34089 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_QI_INT,
34090 IX86_BUILTIN_GATHER3SIV4DF);
34093 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_QI_INT,
34094 IX86_BUILTIN_GATHER3DIV2DF);
34097 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_QI_INT,
34098 IX86_BUILTIN_GATHER3DIV4DF);
34101 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_QI_INT,
34102 IX86_BUILTIN_GATHER3SIV4SF);
34105 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_QI_INT,
34106 IX86_BUILTIN_GATHER3SIV8SF);
34109 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_QI_INT,
34110 IX86_BUILTIN_GATHER3DIV4SF);
34113 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_QI_INT,
34114 IX86_BUILTIN_GATHER3DIV8SF);
34117 V2DI_FTYPE_V2DI_PCINT64_V4SI_QI_INT,
34118 IX86_BUILTIN_GATHER3SIV2DI);
34121 V4DI_FTYPE_V4DI_PCINT64_V4SI_QI_INT,
34122 IX86_BUILTIN_GATHER3SIV4DI);
34125 V2DI_FTYPE_V2DI_PCINT64_V2DI_QI_INT,
34126 IX86_BUILTIN_GATHER3DIV2DI);
34129 V4DI_FTYPE_V4DI_PCINT64_V4DI_QI_INT,
34130 IX86_BUILTIN_GATHER3DIV4DI);
34133 V4SI_FTYPE_V4SI_PCINT_V4SI_QI_INT,
34134 IX86_BUILTIN_GATHER3SIV4SI);
34137 V8SI_FTYPE_V8SI_PCINT_V8SI_QI_INT,
34138 IX86_BUILTIN_GATHER3SIV8SI);
34141 V4SI_FTYPE_V4SI_PCINT_V2DI_QI_INT,
34142 IX86_BUILTIN_GATHER3DIV4SI);
34145 V4SI_FTYPE_V4SI_PCINT_V4DI_QI_INT,
34146 IX86_BUILTIN_GATHER3DIV8SI);
34149 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
34150 IX86_BUILTIN_GATHER3ALTSIV4DF);
34153 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
34154 IX86_BUILTIN_GATHER3ALTDIV8SF);
34157 V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
34158 IX86_BUILTIN_GATHER3ALTSIV4DI);
34161 V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
34162 IX86_BUILTIN_GATHER3ALTDIV8SI);
34165 VOID_FTYPE_PFLOAT_QI_V8SI_V8SF_INT,
34166 IX86_BUILTIN_SCATTERSIV8SF);
34169 VOID_FTYPE_PFLOAT_QI_V4SI_V4SF_INT,
34170 IX86_BUILTIN_SCATTERSIV4SF);
34173 VOID_FTYPE_PDOUBLE_QI_V4SI_V4DF_INT,
34174 IX86_BUILTIN_SCATTERSIV4DF);
34177 VOID_FTYPE_PDOUBLE_QI_V4SI_V2DF_INT,
34178 IX86_BUILTIN_SCATTERSIV2DF);
34181 VOID_FTYPE_PFLOAT_QI_V4DI_V4SF_INT,
34182 IX86_BUILTIN_SCATTERDIV8SF);
34185 VOID_FTYPE_PFLOAT_QI_V2DI_V4SF_INT,
34186 IX86_BUILTIN_SCATTERDIV4SF);
34189 VOID_FTYPE_PDOUBLE_QI_V4DI_V4DF_INT,
34190 IX86_BUILTIN_SCATTERDIV4DF);
34193 VOID_FTYPE_PDOUBLE_QI_V2DI_V2DF_INT,
34194 IX86_BUILTIN_SCATTERDIV2DF);
34197 VOID_FTYPE_PINT_QI_V8SI_V8SI_INT,
34198 IX86_BUILTIN_SCATTERSIV8SI);
34201 VOID_FTYPE_PINT_QI_V4SI_V4SI_INT,
34202 IX86_BUILTIN_SCATTERSIV4SI);
34205 VOID_FTYPE_PLONGLONG_QI_V4SI_V4DI_INT,
34206 IX86_BUILTIN_SCATTERSIV4DI);
34209 VOID_FTYPE_PLONGLONG_QI_V4SI_V2DI_INT,
34210 IX86_BUILTIN_SCATTERSIV2DI);
34213 VOID_FTYPE_PINT_QI_V4DI_V4SI_INT,
34214 IX86_BUILTIN_SCATTERDIV8SI);
34217 VOID_FTYPE_PINT_QI_V2DI_V4SI_INT,
34218 IX86_BUILTIN_SCATTERDIV4SI);
34221 VOID_FTYPE_PLONGLONG_QI_V4DI_V4DI_INT,
34222 IX86_BUILTIN_SCATTERDIV4DI);
34225 VOID_FTYPE_PLONGLONG_QI_V2DI_V2DI_INT,
34226 IX86_BUILTIN_SCATTERDIV2DI);
34228 /* AVX512PF */
34230 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
34231 IX86_BUILTIN_GATHERPFDPD);
34233 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
34234 IX86_BUILTIN_GATHERPFDPS);
34236 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
34237 IX86_BUILTIN_GATHERPFQPD);
34239 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
34240 IX86_BUILTIN_GATHERPFQPS);
34242 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
34243 IX86_BUILTIN_SCATTERPFDPD);
34245 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
34246 IX86_BUILTIN_SCATTERPFDPS);
34248 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
34249 IX86_BUILTIN_SCATTERPFQPD);
34251 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
34252 IX86_BUILTIN_SCATTERPFQPS);
34254 /* SHA */
34270 /* RTM. */
34274 /* MMX access to the vec_init patterns. */
34279 V4HI_FTYPE_HI_HI_HI_HI,
34280 IX86_BUILTIN_VEC_INIT_V4HI);
34283 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
34284 IX86_BUILTIN_VEC_INIT_V8QI);
34286 /* Access to the vec_extract patterns. */
34308 /* Access to the vec_set patterns. */
34329 /* RDSEED */
34338 /* ADCX */
34343 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34344 IX86_BUILTIN_ADDCARRYX64);
34346 /* SBB */
34351 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34352 IX86_BUILTIN_SBB64);
34354 /* Read/write FLAGS. */
34364 /* CLFLUSHOPT. */
34368 /* CLWB. */
34372 /* MONITORX and MWAITX. */
34378 /* Add FMA4 multi-arg argument instructions */
34380 {
34386 }
34387 }
34389 static void
34391 {
34394 tree decl;
34400 {
34407 /* With no leaf and nothrow flags for MPX builtins
34408 abnormal edges may follow its call when setjmp
34409 presents in the function. Since we may have a lot
34410 of MPX builtins calls it causes lots of useless
34411 edges and enormous PHI nodes. To avoid this we mark
34412 MPX builtins as leaf and nothrow. */
34414 {
34416 NULL_TREE);
34418 }
34419 else
34420 {
34423 }
34424 }
34429 {
34437 {
34439 NULL_TREE);
34441 }
34442 else
34443 {
34446 }
34447 }
34448 }
34450 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
34451 to return a pointer to VERSION_DECL if the outcome of the expression
34452 formed by PREDICATE_CHAIN is true. This function will be called during
34453 version dispatch to decide which function version to execute. It returns
34454 the basic block at the end, to which more conditions can be added. */
34456 static basic_block
34459 {
34460 gimple return_stmt;
34462 gimple convert_stmt;
34463 gimple call_cond_stmt;
34464 gimple if_else_stmt;
34470 gimple_seq gseq;
34487 {
34495 }
34498 {
34513 else
34514 {
34515 gimple assign_stmt;
34516 /* Use MIN_EXPR to check if any integer is zero?.
34517 and_expr_var = min_expr <cond_var, and_expr_var> */
34525 }
34526 }
34529 integer_zero_node,
34559 }
34561 /* This parses the attribute arguments to target in DECL and determines
34562 the right builtin to use to match the platform specification.
34563 It returns the priority value for this version decl. If PREDICATE_LIST
34564 is not NULL, it stores the list of cpu features that need to be checked
34565 before dispatching this function. */
34567 static unsigned int
34569 {
34570 tree attrs;
34572 tree target_node;
34579 /* Priority of i386 features, greater value is higher priority. This is
34580 used to decide the order in which function dispatch must happen. For
34581 instance, a version specialized for SSE4.2 should be checked for dispatch
34582 before a version for SSE3, as SSE4.2 implies SSE3. */
34583 enum feature_priority
34584 {
34586 P_MMX,
34587 P_SSE,
34588 P_SSE2,
34589 P_SSE3,
34590 P_SSSE3,
34591 P_PROC_SSSE3,
34592 P_SSE4_A,
34593 P_PROC_SSE4_A,
34594 P_SSE4_1,
34595 P_SSE4_2,
34596 P_PROC_SSE4_2,
34597 P_POPCNT,
34598 P_AVX,
34599 P_PROC_AVX,
34600 P_BMI,
34601 P_PROC_BMI,
34602 P_FMA4,
34603 P_XOP,
34604 P_PROC_XOP,
34605 P_FMA,
34606 P_PROC_FMA,
34607 P_BMI2,
34608 P_AVX2,
34609 P_PROC_AVX2,
34610 P_AVX512F,
34611 P_PROC_AVX512F
34612 };
34616 /* These are the target attribute strings for which a dispatcher is
34617 available, from fold_builtin_cpu. */
34619 static struct _feature_list
34620 {
34623 }
34625 {
34643 };
34646 static unsigned int NUM_FEATURES
34662 /* Return priority zero for default function. */
34666 /* Handle arch= if specified. For priority, set it to be 1 more than
34667 the best instruction set the processor can handle. For instance, if
34668 there is a version for atom and a version for ssse3 (the highest ISA
34669 priority for atom), the atom version must be checked for dispatch
34670 before the ssse3 version. */
34672 {
34682 {
34684 {
34692 else
34693 /* We translate "arch=corei7" and "arch=nehalem" to
34694 "corei7" so that it will be mapped to M_INTEL_COREI7
34695 as cpu type to cover all M_INTEL_COREI7_XXXs. */
34702 else
34709 else
34753 }
34754 }
34759 {
34763 }
34766 {
34768 /* For a C string literal the length includes the trailing NULL. */
34771 predicate_chain);
34772 }
34773 }
34775 /* Process feature name. */
34782 {
34783 /* Do not process "arch=" */
34785 {
34788 }
34790 {
34792 {
34794 {
34799 predicate_chain);
34800 }
34801 /* Find the maximum priority feature. */
34806 }
34807 }
34809 {
34813 }
34815 }
34819 {
34822 attrs_str);
34824 }
34826 {
34829 }
34832 }
34834 /* This compares the priority of target features in function DECL1
34835 and DECL2. It returns positive value if DECL1 is higher priority,
34836 negative value if DECL2 is higher priority and 0 if they are the
34837 same. */
34839 static int
34841 {
34846 }
34848 /* V1 and V2 point to function versions with different priorities
34849 based on the target ISA. This function compares their priorities. */
34851 static int
34853 {
34855 {
34856 tree version_decl;
34857 tree predicate_chain;
34864 }
34866 /* This function generates the dispatch function for
34867 multi-versioned functions. DISPATCH_DECL is the function which will
34868 contain the dispatch logic. FNDECLS are the function choices for
34869 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
34870 in DISPATCH_DECL in which the dispatch code is generated. */
34872 static int
34876 {
34877 tree default_decl;
34878 gimple ifunc_cpu_init_stmt;
34879 gimple_seq gseq;
34881 tree ele;
34887 struct _function_version_info
34888 {
34889 tree version_decl;
34890 tree predicate_chain;
34898 /*fndecls_p is actually a vector. */
34901 /* At least one more version other than the default. */
34908 /* The first version in the vector is the default decl. */
34914 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
34915 constructors, so explicity call __builtin_cpu_init here. */
34926 {
34930 /* Get attribute string, parse it and find the right predicate decl.
34931 The predicate function could be a lengthy combination of many
34932 features, like arch-type and various isa-variants. */
34943 actual_versions++;
34944 }
34946 /* Sort the versions according to descending order of dispatch priority. The
34947 priority is based on the ISA. This is not a perfect solution. There
34948 could still be ambiguity. If more than one function version is suitable
34949 to execute, which one should be dispatched? In future, allow the user
34950 to specify a dispatch priority next to the version. */
34960 /* dispatch default version at the end. */
34966 }
34968 /* Comparator function to be used in qsort routine to sort attribute
34969 specification strings to "target". */
34971 static int
34973 {
34977 }
34979 /* ARGLIST is the argument to target attribute. This function tokenizes
34980 the comma separated arguments, sorts them and returns a string which
34981 is a unique identifier for the comma separated arguments. It also
34982 replaces non-identifier characters "=,-" with "_". */
34986 {
34987 tree arg;
34996 {
35001 argnum++;
35004 argnum++;
35005 }
35010 {
35016 }
35018 /* Replace "=,-" with "_". */
35031 {
35033 i++;
35035 }
35042 {
35047 }
35052 }
35054 /* This function changes the assembler name for functions that are
35055 versions. If DECL is a function version and has a "target"
35056 attribute, it appends the attribute string to its assembler name. */
35058 static tree
35060 {
35061 tree version_attr;
35069 "Function versions cannot be marked as gnu_inline,"
35078 /* target attribute string cannot be NULL. */
35082 version_string
35093 /* Allow assembler name to be modified if already set. */
35101 }
35103 /* This function returns true if FN1 and FN2 are versions of the same function,
35104 that is, the target strings of the function decls are different. This assumes
35105 that FN1 and FN2 have the same signature. */
35107 static bool
35109 {
35121 /* At least one function decl should have the target attribute specified. */
35125 /* Diagnose missing target attribute if one of the decls is already
35126 multi-versioned. */
35128 {
35130 {
35132 {
35135 }
35138 fn2);
35141 /* Prevent diagnosing of the same error multiple times. */
35146 }
35148 }
35153 /* The sorted target strings must be different for fn1 and fn2
35154 to be versions. */
35157 else
35164 }
35166 static tree
35168 {
35169 /* For function version, add the target suffix to the assembler name. */
35173 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
35175 #endif
35178 }
35180 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
35181 is true, append the full path name of the source file. */
35185 {
35193 /* Get a unique name that can be used globally without any chances
35194 of collision at link time. */
35204 /* Use '.' to concatenate names as it is demangler friendly. */
35207 suffix);
35208 else
35212 }
35214 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
35216 /* Make a dispatcher declaration for the multi-versioned function DECL.
35217 Calls to DECL function will be replaced with calls to the dispatcher
35218 by the front-end. Return the decl created. */
35220 static tree
35222 {
35223 tree func_decl;
35243 /* Mark this func as external, the resolver will flip it again if
35244 it gets generated. */
35246 /* This will be of type IFUNCs have to be externally visible. */
35250 }
35252 #endif
35254 /* Returns true if decl is multi-versioned and DECL is the default function,
35255 that is it is not tagged with target specific optimization. */
35257 static bool
35259 {
35268 }
35270 /* Make a dispatcher declaration for the multi-versioned function DECL.
35271 Calls to DECL function will be replaced with calls to the dispatcher
35272 by the front-end. Returns the decl of the dispatcher function. */
35274 static tree
35276 {
35298 /* Find the default version and make it the first node. */
35300 /* Go to the beginning of the chain. */
35305 {
35310 }
35312 /* If there is no default node, just return NULL. */
35316 /* Make default info the first node. */
35318 {
35325 }
35329 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
35331 {
35336 /* Right now, the dispatching is done via ifunc. */
35342 dispatcher_version_info
35347 /* Set the dispatcher for all the versions. */
35350 {
35353 }
35354 }
35355 else
35356 #endif
35357 {
35359 "multiversioning needs ifunc which is not supported "
35361 }
35364 }
35366 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
35367 it to CHAIN. */
35369 static tree
35371 {
35372 tree attr_name;
35373 tree attr_arg_name;
35374 tree attr_args;
35375 tree attr;
35382 }
35384 /* Make the resolver function decl to dispatch the versions of
35385 a multi-versioned function, DEFAULT_DECL. Create an
35386 empty basic block in the resolver and store the pointer in
35387 EMPTY_BB. Return the decl of the resolver function. */
35389 static tree
35393 {
35398 /* IFUNC's have to be globally visible. So, if the default_decl is
35399 not, then the name of the IFUNC should be made unique. */
35403 /* Append the filename to the resolver function if the versions are
35404 not externally visible. This is because the resolver function has
35405 to be externally visible for the loader to find it. So, appending
35406 the filename will prevent conflicts with a resolver function from
35407 another module which is based on the same version name. */
35410 /* The resolver function should return a (void *). */
35421 /* IFUNC resolvers have to be externally visible. */
35425 /* Resolver is not external, body is generated. */
35435 {
35436 /* In this case, each translation unit with a call to this
35437 versioned function will put out a resolver. Ensure it
35438 is comdat to keep just one copy. */
35441 }
35442 /* Build result decl and add to function_decl. */
35458 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
35462 /* Create the alias for dispatch to resolver here. */
35463 /*cgraph_create_function_alias (dispatch_decl, decl);*/
35467 }
35469 /* Generate the dispatching code body to dispatch multi-versioned function
35470 DECL. The target hook is called to process the "target" attributes and
35471 provide the code to dispatch the right function at run-time. NODE points
35472 to the dispatcher decl whose body will be created. */
35474 static tree
35476 {
35477 tree resolver_decl;
35478 basic_block empty_bb;
35479 tree default_ver_decl;
35495 /* The first version in the chain corresponds to the default version. */
35498 /* node is going to be an alias, so remove the finalized bit. */
35512 {
35514 /* Check for virtual functions here again, as by this time it should
35515 have been determined if this function needs a vtable index or
35516 not. This happens for methods in derived classes that override
35517 virtual methods in base classes but are not explicitly marked as
35518 virtual. */
35523 }
35529 }
35530 /* This builds the processor_model struct type defined in
35531 libgcc/config/i386/cpuinfo.c */
35533 static tree
35535 {
35542 /* The first 3 fields are unsigned int. */
35544 {
35550 }
35552 /* The last field is an array of unsigned integers of size one. */
35563 }
35565 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
35567 static tree
35569 {
35570 tree new_decl;
35573 VAR_DECL,
35575 type);
35588 }
35590 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
35591 into an integer defined in libgcc/config/i386/cpuinfo.c */
35593 static tree
35595 {
35601 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
35602 enum processor_features
35603 {
35605 F_MMX,
35606 F_POPCNT,
35607 F_SSE,
35608 F_SSE2,
35609 F_SSE3,
35610 F_SSSE3,
35611 F_SSE4_1,
35612 F_SSE4_2,
35613 F_AVX,
35614 F_AVX2,
35615 F_SSE4_A,
35616 F_FMA4,
35617 F_XOP,
35618 F_FMA,
35619 F_AVX512F,
35620 F_BMI,
35621 F_BMI2,
35622 F_MAX
35623 };
35625 /* These are the values for vendor types and cpu types and subtypes
35626 in cpuinfo.c. Cpu types and subtypes should be subtracted by
35627 the corresponding start value. */
35628 enum processor_model
35629 {
35631 M_AMD,
35632 M_CPU_TYPE_START,
35633 M_INTEL_BONNELL,
35634 M_INTEL_CORE2,
35635 M_INTEL_COREI7,
35636 M_AMDFAM10H,
35637 M_AMDFAM15H,
35638 M_INTEL_SILVERMONT,
35639 M_INTEL_KNL,
35640 M_AMD_BTVER1,
35641 M_AMD_BTVER2,
35642 M_CPU_SUBTYPE_START,
35643 M_INTEL_COREI7_NEHALEM,
35644 M_INTEL_COREI7_WESTMERE,
35645 M_INTEL_COREI7_SANDYBRIDGE,
35646 M_AMDFAM10H_BARCELONA,
35647 M_AMDFAM10H_SHANGHAI,
35648 M_AMDFAM10H_ISTANBUL,
35649 M_AMDFAM15H_BDVER1,
35650 M_AMDFAM15H_BDVER2,
35651 M_AMDFAM15H_BDVER3,
35652 M_AMDFAM15H_BDVER4,
35653 M_INTEL_COREI7_IVYBRIDGE,
35654 M_INTEL_COREI7_HASWELL,
35655 M_INTEL_COREI7_BROADWELL
35656 };
35658 static struct _arch_names_table
35659 {
35662 }
35664 {
35691 };
35693 static struct _isa_names_table
35694 {
35697 }
35699 {
35718 };
35732 {
35733 /* *args must be a expr that can contain other EXPRS leading to a
35734 STRING_CST. */
35736 {
35739 }
35741 }
35746 {
35747 tree ref;
35748 tree field;
35749 tree final;
35752 unsigned int NUM_ARCH_NAMES
35761 {
35765 }
35770 /* CPU types are stored in the next field. */
35773 {
35776 }
35778 /* CPU subtypes are stored in the next field. */
35780 {
35783 }
35785 /* Get the appropriate field in __cpu_model. */
35789 /* Check the value. */
35793 }
35795 {
35796 tree ref;
35797 tree array_elt;
35798 tree field;
35799 tree final;
35802 unsigned int NUM_ISA_NAMES
35811 {
35815 }
35818 /* Get the last field, which is __cpu_features. */
35822 /* Get the appropriate field: __cpu_model.__cpu_features */
35826 /* Access the 0th element of __cpu_features array. */
35831 /* Return __cpu_model.__cpu_features[0] & field_val */
35835 }
35837 }
35839 static tree
35842 {
35844 {
35849 {
35852 }
35853 }
35855 #ifdef SUBTARGET_FOLD_BUILTIN
35857 #endif
35860 }
35862 /* Make builtins to detect cpu type and features supported. NAME is
35863 the builtin name, CODE is the builtin code, and FTYPE is the function
35864 type of the builtin. */
35866 static void
35869 {
35870 tree decl;
35871 tree type;
35879 }
35881 /* Make builtins to get CPU type and features supported. The created
35882 builtins are :
35884 __builtin_cpu_init (), to detect cpu type and features,
35885 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
35886 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
35887 */
35889 static void
35891 {
35898 }
35900 /* Internal method for ix86_init_builtins. */
35902 static void
35904 {
35916 sysv_va_ref =
35919 fnvoid_va_end_ms =
35921 fnvoid_va_start_ms =
35923 fnvoid_va_end_sysv =
35925 fnvoid_va_start_sysv =
35927 NULL_TREE);
35928 fnvoid_va_copy_ms =
35930 NULL_TREE);
35931 fnvoid_va_copy_sysv =
35947 }
35949 static void
35951 {
35954 /* The __float80 type. */
35957 {
35958 /* The __float80 type. */
35963 }
35966 /* The __float128 type. */
35972 /* This macro is built by i386-builtin-types.awk. */
35973 DEFINE_BUILTIN_PRIMITIVE_TYPES;
35974 }
35976 static void
35978 {
35979 tree t;
35983 /* Builtins to get CPU type and features. */
35986 /* TFmode support builtins. */
35992 /* We will expand them to normal call if SSE isn't available since
35993 they are used by libgcc. */
36013 #ifdef SUBTARGET_INIT_BUILTINS
36014 SUBTARGET_INIT_BUILTINS;
36015 #endif
36016 }
36018 /* Return the ix86 builtin for CODE. */
36020 static tree
36022 {
36027 }
36029 /* Errors in the source file can cause expand_expr to return const0_rtx
36030 where we expect a vector. To avoid crashing, use one of the vector
36031 clear instructions. */
36032 static rtx
36034 {
36038 }
36040 /* Fixup modeless constants to fit required mode. */
36041 static rtx
36043 {
36047 }
36049 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
36051 static rtx
36053 {
36054 rtx pat;
36074 {
36078 }
36092 }
36094 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
36096 static rtx
36100 {
36101 rtx pat;
36109 rtx op;
36110 machine_mode mode;
36116 {
36196 }
36206 {
36213 {
36215 {
36218 {
36236 xop_rotl:
36238 {
36241 gcc_checking_assert
36243 }
36244 else
36245 {
36246 gcc_checking_assert
36257 }
36261 }
36262 }
36263 }
36264 else
36265 {
36266 non_constant:
36270 /* If we aren't optimizing, only allow one memory operand to be
36271 generated. */
36273 num_memory++;
36281 }
36285 }
36288 {
36299 else
36300 {
36306 }
36319 }
36326 }
36328 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
36329 insns with vec_merge. */
36331 static rtx
36333 rtx target)
36334 {
36335 rtx pat;
36362 }
36364 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
36366 static rtx
36369 {
36370 rtx pat;
36375 rtx op2;
36386 /* Swap operands if we have a comparison that isn't available in
36387 hardware. */
36409 }
36411 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
36413 static rtx
36415 rtx target)
36416 {
36417 rtx pat;
36431 /* Swap operands if we have a comparison that isn't available in
36432 hardware. */
36454 const0_rtx)));
36457 }
36459 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
36461 static rtx
36463 rtx target)
36464 {
36465 rtx pat;
36490 }
36492 static rtx
36495 {
36496 rtx pat;
36501 rtx op2;
36528 }
36530 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
36532 static rtx
36534 rtx target)
36535 {
36536 rtx pat;
36568 const0_rtx)));
36571 }
36573 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
36575 static rtx
36578 {
36579 rtx pat;
36617 {
36620 }
36623 {
36632 }
36634 {
36643 }
36644 else
36645 {
36652 }
36660 {
36665 emit_insn
36669 FLAGS_REG),
36670 const0_rtx)));
36672 }
36673 else
36675 }
36678 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
36680 static rtx
36683 {
36684 rtx pat;
36712 {
36715 }
36718 {
36727 }
36729 {
36738 }
36739 else
36740 {
36747 }
36755 {
36760 emit_insn
36764 FLAGS_REG),
36765 const0_rtx)));
36767 }
36768 else
36770 }
36772 /* Subroutine of ix86_expand_builtin to take care of insns with
36773 variable number of operands. */
36775 static rtx
36778 {
36784 struct
36785 {
36786 rtx op;
36787 machine_mode mode;
36798 {
37508 }
37513 {
37516 }
37519 {
37526 }
37527 else
37528 {
37531 }
37534 {
37541 {
37542 /* SIMD shift insns take either an 8-bit immediate or
37543 register as count. But builtin functions take int as
37544 count. If count doesn't match, we put it in register. */
37546 {
37550 }
37551 }
37554 {
37557 {
37666 {
37670 {
37673 }
37679 }
37681 }
37682 }
37683 else
37684 {
37688 /* If we aren't optimizing, only allow one memory operand to
37689 be generated. */
37691 num_memory++;
37696 {
37699 }
37700 else
37701 {
37704 }
37705 }
37709 }
37712 {
37737 }
37744 }
37746 /* Transform pattern of following layout:
37747 (parallel [
37748 set (A B)
37749 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
37750 ])
37751 into:
37752 (set (A B))
37754 Or:
37755 (parallel [ A B
37756 ...
37757 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
37758 ...
37759 ])
37760 into:
37761 (parallel [ A B ... ]) */
37763 static rtx
37765 {
37772 {
37781 }
37782 else
37783 {
37789 {
37794 }
37796 /* No more than 1 occurence was removed. */
37800 }
37801 }
37803 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
37804 with rounding. */
37805 static rtx
37808 {
37825 /* See avxintrin.h for values. */
37827 {
37831 };
37833 {
37838 };
37841 {
37844 }
37846 {
37849 }
37852 {
37855 }
37878 ? CODE_FOR_sse_ucomi_round
37885 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
37887 {
37893 }
37894 else
37895 {
37898 }
37903 set_dst,
37904 const0_rtx)));
37907 }
37909 static rtx
37912 {
37913 rtx pat;
37915 struct
37916 {
37917 rtx op;
37918 machine_mode mode;
37927 {
38010 }
38020 {
38027 {
38029 {
38031 {
38047 }
38048 }
38049 }
38051 {
38053 {
38056 }
38058 /* If there is no rounding use normal version of the pattern. */
38061 }
38062 else
38063 {
38070 {
38073 }
38074 else
38075 {
38078 }
38079 }
38083 }
38086 {
38111 }
38121 }
38123 /* Subroutine of ix86_expand_builtin to take care of special insns
38124 with variable number of operands. */
38126 static rtx
38129 {
38130 tree arg;
38134 struct
38135 {
38136 rtx op;
38137 machine_mode mode;
38146 {
38186 {
38194 }
38213 /* Reserve memory operand for target. */
38216 {
38217 /* These builtins and instructions require the memory
38218 to be properly aligned. */
38237 }
38266 {
38267 /* These builtins and instructions require the memory
38268 to be properly aligned. */
38285 }
38286 /* FALLTHRU */
38324 /* Reserve memory operand for target. */
38351 {
38352 /* These builtins and instructions require the memory
38353 to be properly aligned. */
38376 }
38389 }
38394 {
38399 {
38402 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
38403 on it. Try to improve it using get_pointer_alignment,
38404 and if the special builtin is one that requires strict
38405 mode alignment, also from it's GET_MODE_ALIGNMENT.
38406 Failure to do so could lead to ix86_legitimate_combined_insn
38407 rejecting all changes to such insns. */
38413 }
38414 else
38417 }
38418 else
38419 {
38426 }
38429 {
38438 {
38440 {
38446 else
38449 }
38450 }
38451 else
38452 {
38454 {
38455 /* This must be the memory operand. */
38458 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
38459 on it. Try to improve it using get_pointer_alignment,
38460 and if the special builtin is one that requires strict
38461 mode alignment, also from it's GET_MODE_ALIGNMENT.
38462 Failure to do so could lead to ix86_legitimate_combined_insn
38463 rejecting all changes to such insns. */
38469 }
38470 else
38471 {
38472 /* This must be register. */
38480 else
38481 {
38484 }
38485 }
38486 }
38490 }
38493 {
38508 }
38514 }
38516 /* Return the integer constant in ARG. Constrain it to be in the range
38517 of the subparts of VEC_TYPE; issue an error if not. */
38519 static int
38521 {
38526 {
38529 }
38532 }
38534 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38535 ix86_expand_vector_init. We DO have language-level syntax for this, in
38536 the form of (type){ init-list }. Except that since we can't place emms
38537 instructions from inside the compiler, we can't allow the use of MMX
38538 registers unless the user explicitly asks for it. So we do *not* define
38539 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
38540 we have builtins invoked by mmintrin.h that gives us license to emit
38541 these sorts of instructions. */
38543 static rtx
38545 {
38555 {
38558 }
38565 }
38567 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38568 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
38569 had a language-level syntax for referencing vector elements. */
38571 static rtx
38573 {
38577 rtx op0;
38597 }
38599 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38600 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
38601 a language-level syntax for referencing vector elements. */
38603 static rtx
38605 {
38629 /* OP0 is the source of these builtin functions and shouldn't be
38630 modified. Create a copy, use it and return it as target. */
38636 }
38638 /* Emit conditional move of SRC to DST with condition
38639 OP1 CODE OP2. */
38640 static void
38642 {
38643 rtx t;
38646 {
38650 }
38651 else
38652 {
38658 }
38659 }
38661 /* Choose max of DST and SRC and put it to DST. */
38662 static void
38664 {
38666 }
38668 /* Expand an expression EXP that calls a built-in function,
38669 with result going to TARGET if that's convenient
38670 (and in mode MODE if that's convenient).
38671 SUBTARGET may be used as the target for computing one of EXP's operands.
38672 IGNORE is nonzero if the value is to be ignored. */
38674 static rtx
38677 {
38687 /* For CPU builtins that can be folded, fold first and expand the fold. */
38689 {
38691 {
38692 /* Make it call __cpu_indicator_init in libgcc. */
38698 }
38701 {
38706 }
38707 }
38709 /* Determine whether the builtin function is available under the current ISA.
38710 Originally the builtin was not created if it wasn't applicable to the
38711 current ISA based on the command line switches. With function specific
38712 options, we need to check in the context of the function making the call
38713 whether it is supported. */
38716 {
38722 else
38723 {
38727 }
38729 }
38732 {
38750 /* Builtin arg1 is size of block but instruction op1 should
38751 be (size - 1). */
38842 /* If no bounds were specified for returned value,
38843 then use INIT bounds. It usually happens when
38844 some built-in function is expanded. */
38846 {
38855 }
38861 {
38864 /* Return value and lb. */
38866 /* Bounds. */
38868 /* Size. */
38875 /* Size was passed but we need to use (size - 1) as for bndmk. */
38879 /* Add LB to size and inverse to get UB. */
38889 /* We need to move bounds to memory before any computations. */
38892 else
38893 {
38896 }
38898 /* Generate mem expression to be used for access to LB and UB. */
38904 /* Compute LB. */
38909 /* Compute UB. UB is stored in 1's complement form. Therefore
38910 we also use max here. */
38919 }
38922 {
38940 /* Put first bounds to temporaries. */
38944 {
38948 }
38949 else
38950 {
38954 }
38956 /* Put second bounds to temporaries. */
38960 {
38964 }
38965 else
38966 {
38970 }
38972 /* Compute LB. */
38976 /* Compute UB. UB is stored in 1's complement form. Therefore
38977 we also use max here. */
38984 }
38987 {
38988 tree name;
38989 rtx symbol;
39007 }
39010 {
39021 /* We need to move bounds to memory first. */
39024 else
39025 {
39028 }
39030 /* Generate mem expression to access LB and load it. */
39035 }
39038 {
39049 /* We need to move bounds to memory first. */
39052 else
39053 {
39056 }
39058 /* Generate mem expression to access UB. */
39061 /* We need to inverse all bits of UB. */
39068 }
39073 ? CODE_FOR_mmx_maskmovq
39075 /* Note the arg order is different from the operand order. */
39216 {
39217 REAL_VALUE_TYPE inf;
39218 rtx tmp;
39230 }
39240 {
39246 insn = (TARGET_64BIT
39250 }
39252 {
39253 insn = (TARGET_64BIT
39257 }
39258 else
39259 {
39262 insn = (TARGET_64BIT
39270 {
39273 }
39275 }
39278 {
39279 /* mode is VOIDmode if __builtin_rd* has been called
39280 without lhs. */
39284 }
39287 {
39292 }
39305 {
39326 }
39332 {
39335 }
39361 {
39364 }
39370 {
39374 {
39413 }
39418 }
39419 else
39420 {
39422 {
39443 }
39445 }
39475 ? CODE_FOR_tbm_bextri_si
39478 {
39481 }
39482 else
39483 {
39492 }
39508 rdrand_step:
39515 {
39518 }
39524 /* Emit SImode conditional move. */
39526 {
39529 }
39532 else
39540 const0_rtx);
39559 rdseed_step:
39566 {
39569 }
39575 const0_rtx);
39604 addcarryx:
39612 /* Generate CF from input operand. */
39617 /* Gen ADCX instruction to compute X+Y+CF. */
39632 /* Store the result. */
39635 {
39638 }
39641 /* Return current CF value. */
39683 kortest:
39697 /* Emit kortest. */
39699 /* And use setcc to return result from flags. */
39957 gather_gen:
39958 rtx half;
39971 /* Note the arg order is different from the operand order. */
39982 else
39986 {
40010 else
40017 {
40022 }
40031 else
40038 {
40043 }
40047 }
40049 /* Force memory operand only with base register here. But we
40050 don't want to do it on memory operand for other builtin
40051 functions. */
40064 {
40067 }
40068 else
40069 {
40072 }
40074 {
40077 }
40079 /* Optimize. If mask is known to have all high bits set,
40080 replace op0 with pc_rtx to signal that the instruction
40081 overwrites the whole destination and doesn't use its
40082 previous contents. */
40084 {
40086 {
40089 }
40091 {
40094 {
40098 negative++;
40101 negative++;
40102 }
40105 }
40108 {
40109 /* Recognize also when mask is like:
40110 __v2df src = _mm_setzero_pd ();
40111 __v2df mask = _mm_cmpeq_pd (src, src);
40112 or
40113 __v8sf src = _mm256_setzero_ps ();
40114 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
40115 as that is a cheaper way to load all ones into
40116 a register than having to load a constant from
40117 memory. */
40120 {
40125 {
40132 /* FALLTHRU */
40142 }
40143 }
40144 }
40145 }
40153 {
40179 }
40182 scatter_gen:
40198 /* Force memory operand only with base register here. But we
40199 don't want to do it on memory operand for other builtin
40200 functions. */
40209 {
40212 }
40213 else
40214 {
40217 }
40226 {
40229 }
40238 vec_prefetch_gen:
40258 {
40261 }
40263 {
40266 }
40271 /* Force memory operand only with base register here. But we
40272 don't want to do it on memory operand for other builtin
40273 functions. */
40280 {
40283 }
40286 {
40289 }
40305 {
40308 }
40314 }
40327 {
40331 /* Emit a normal call if SSE isn't available. */
40335 }
40364 }
40366 /* This returns the target-specific builtin with code CODE if
40367 current_function_decl has visibility on this builtin, which is checked
40368 using isa flags. Returns NULL_TREE otherwise. */
40371 {
40375 /* Determine the isa flags of current_function_decl. */
40387 else
40389 }
40391 /* Return function decl for target specific builtin
40392 for given MPX builtin passed i FCODE. */
40393 static tree
40395 {
40397 {
40433 }
40436 }
40438 /* Helper function for ix86_load_bounds and ix86_store_bounds.
40440 Return an address to be used to load/store bounds for pointer
40441 passed in SLOT.
40443 SLOT_NO is an integer constant holding number of a target
40444 dependent special slot to be used in case SLOT is not a memory.
40446 SPECIAL_BASE is a pointer to be used as a base of fake address
40447 to access special slots in Bounds Table. SPECIAL_BASE[-1],
40448 SPECIAL_BASE[-2] etc. will be used as fake pointer locations. */
40450 static rtx
40452 {
40455 /* NULL slot means we pass bounds for pointer not passed to the
40456 function at all. Register slot means we pass pointer in a
40457 register. In both these cases bounds are passed via Bounds
40458 Table. Since we do not have actual pointer stored in memory,
40459 we have to use fake addresses to access Bounds Table. We
40460 start with (special_base - sizeof (void*)) and decrease this
40461 address by pointer size to get addresses for other slots. */
40463 {
40467 }
40468 /* If pointer is passed in a memory then its address is used to
40469 access Bounds Table. */
40471 {
40475 }
40476 else
40480 }
40482 /* Expand pass uses this hook to load bounds for function parameter
40483 PTR passed in SLOT in case its bounds are not passed in a register.
40485 If SLOT is a memory, then bounds are loaded as for regular pointer
40486 loaded from memory. PTR may be NULL in case SLOT is a memory.
40487 In such case value of PTR (if required) may be loaded from SLOT.
40489 If SLOT is NULL or a register then SLOT_NO is an integer constant
40490 holding number of the target dependent special slot which should be
40491 used to obtain bounds.
40493 Return loaded bounds. */
40495 static rtx
40497 {
40499 rtx addr;
40501 /* Get address to be used to access Bounds Table. Special slots start
40502 at the location of return address of the current function. */
40505 /* Load pointer value from a memory if we don't have it. */
40507 {
40510 }
40520 }
40522 /* Expand pass uses this hook to store BOUNDS for call argument PTR
40523 passed in SLOT in case BOUNDS are not passed in a register.
40525 If SLOT is a memory, then BOUNDS are stored as for regular pointer
40526 stored in memory. PTR may be NULL in case SLOT is a memory.
40527 In such case value of PTR (if required) may be loaded from SLOT.
40529 If SLOT is NULL or a register then SLOT_NO is an integer constant
40530 holding number of the target dependent special slot which should be
40531 used to store BOUNDS. */
40533 static void
40535 {
40536 rtx addr;
40538 /* Get address to be used to access Bounds Table. Special slots start
40539 at the location of return address of a called function. */
40542 /* Load pointer value from a memory if we don't have it. */
40544 {
40547 }
40559 }
40561 /* Load and return bounds returned by function in SLOT. */
40563 static rtx
40565 {
40566 rtx res;
40573 }
40575 /* Store BOUNDS returned by function into SLOT. */
40577 static void
40579 {
40582 }
40584 /* Returns a function decl for a vectorized version of the builtin function
40585 with builtin function code FN and the result vector type TYPE, or NULL_TREE
40586 if it is not available. */
40588 static tree
40590 tree type_in)
40591 {
40607 {
40610 {
40617 }
40622 {
40625 }
40630 {
40637 }
40643 /* The round insn does not trap on denormals. */
40648 {
40655 }
40661 /* The round insn does not trap on denormals. */
40666 {
40671 }
40677 /* The round insn does not trap on denormals. */
40682 {
40689 }
40695 /* The round insn does not trap on denormals. */
40700 {
40705 }
40712 {
40717 }
40724 {
40729 }
40735 /* The round insn does not trap on denormals. */
40740 {
40747 }
40753 /* The round insn does not trap on denormals. */
40758 {
40763 }
40768 {
40775 }
40780 {
40787 }
40791 /* The round insn does not trap on denormals. */
40796 {
40801 }
40805 /* The round insn does not trap on denormals. */
40810 {
40815 }
40819 /* The round insn does not trap on denormals. */
40824 {
40829 }
40833 /* The round insn does not trap on denormals. */
40838 {
40843 }
40847 /* The round insn does not trap on denormals. */
40852 {
40857 }
40861 /* The round insn does not trap on denormals. */
40866 {
40871 }
40875 /* The round insn does not trap on denormals. */
40880 {
40885 }
40889 /* The round insn does not trap on denormals. */
40894 {
40899 }
40903 /* The round insn does not trap on denormals. */
40908 {
40913 }
40917 /* The round insn does not trap on denormals. */
40922 {
40927 }
40932 {
40937 }
40942 {
40947 }
40952 }
40954 /* Dispatch to a handler for a vectorization library. */
40957 type_in);
40960 }
40962 /* Handler for an SVML-style interface to
40963 a library with vectorized intrinsics. */
40965 static tree
40967 {
40975 /* The SVML is suitable for unsafe math only. */
40988 {
41035 }
41044 {
41047 }
41048 else
41051 /* Convert to uppercase. */
41056 args;
41058 arity++;
41062 else
41065 /* Build a function declaration for the vectorized function. */
41074 }
41076 /* Handler for an ACML-style interface to
41077 a library with vectorized intrinsics. */
41079 static tree
41081 {
41089 /* The ACML is 64bits only and suitable for unsafe math only as
41090 it does not correctly support parts of IEEE with the required
41091 precision such as denormals. */
41105 {
41135 }
41142 args;
41144 arity++;
41148 else
41151 /* Build a function declaration for the vectorized function. */
41160 }
41162 /* Returns a decl of a function that implements gather load with
41163 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
41164 Return NULL_TREE if it is not available. */
41166 static tree
41169 {
41185 /* v*gather* insn sign extends index to pointer mode. */
41197 {
41201 else
41207 else
41213 else
41219 else
41225 else
41231 else
41237 else
41243 else
41249 else
41255 else
41261 else
41267 else
41272 }
41275 }
41277 /* Returns a code for a target-specific builtin that implements
41278 reciprocal of the function, or NULL_TREE if not available. */
41280 static tree
41282 {
41289 /* Machine dependent builtins. */
41291 {
41292 /* Vectorized version of sqrt to rsqrt conversion. */
41301 }
41302 else
41303 /* Normal builtins. */
41305 {
41306 /* Sqrt to rsqrt conversion. */
41312 }
41313 }
41314 \f
41315 /* Helper for avx_vpermilps256_operand et al. This is also used by
41316 the expansion functions to turn the parallel back into a mask.
41317 The return value is 0 for no match and the imm8+1 for a match. */
41319 int
41321 {
41329 /* Validate that all of the elements are constants, and not totally
41330 out of range. Copy the data into an integral array to make the
41331 subsequent checks easier. */
41333 {
41343 }
41346 {
41348 /* In the 512-bit DFmode case, we can only move elements within
41349 a 128-bit lane. First fill the second part of the mask,
41350 then fallthru. */
41352 {
41356 }
41358 {
41362 }
41363 /* FALLTHRU */
41366 /* In the 256-bit DFmode case, we can only move elements within
41367 a 128-bit lane. */
41369 {
41373 }
41375 {
41379 }
41383 /* In 512 bit SFmode case, permutation in the upper 256 bits
41384 must mirror the permutation in the lower 256-bits. */
41388 /* FALLTHRU */
41391 /* In 256 bit SFmode case, we have full freedom of
41392 movement within the low 128-bit lane, but the high 128-bit
41393 lane must mirror the exact same pattern. */
41398 /* FALLTHRU */
41402 /* In the 128-bit case, we've full freedom in the placement of
41403 the elements from the source operand. */
41410 }
41412 /* Make sure success has a non-zero value by adding one. */
41414 }
41416 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
41417 the expansion functions to turn the parallel back into a mask.
41418 The return value is 0 for no match and the imm8+1 for a match. */
41420 int
41422 {
41430 /* Validate that all of the elements are constants, and not totally
41431 out of range. Copy the data into an integral array to make the
41432 subsequent checks easier. */
41434 {
41444 }
41446 /* Validate that the halves of the permute are halves. */
41454 /* Reconstruct the mask. */
41456 {
41462 }
41464 /* Make sure success has a non-zero value by adding one. */
41466 }
41467 \f
41468 /* Return a register priority for hard reg REGNO. */
41469 static int
41471 {
41472 /* ebp and r13 as the base always wants a displacement, r12 as the
41473 base always wants an index. So discourage their usage in an
41474 address. */
41479 /* New x86-64 int registers result in bigger code size. Discourage
41480 them. */
41483 /* New x86-64 SSE registers result in bigger code size. Discourage
41484 them. */
41487 /* Usage of AX register results in smaller code. Prefer it. */
41491 }
41493 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
41495 Put float CONST_DOUBLE in the constant pool instead of fp regs.
41496 QImode must go into class Q_REGS.
41497 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
41498 movdf to do mem-to-mem moves through integer regs. */
41500 static reg_class_t
41502 {
41505 /* We're only allowed to return a subclass of CLASS. Many of the
41506 following checks fail for NO_REGS, so eliminate that early. */
41510 /* All classes can load zeros. */
41514 /* Force constants into memory if we are loading a (nonzero) constant into
41515 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
41516 instructions to load from a constant. */
41523 /* Prefer SSE regs only, if we can use them for math. */
41527 /* Floating-point constants need more complex checks. */
41529 {
41530 /* General regs can load everything. */
41534 /* Floats can load 0 and 1 plus some others. Note that we eliminated
41535 zero above. We only want to wind up preferring 80387 registers if
41536 we plan on doing computation with them. */
41539 {
41540 /* Limit class to non-sse. */
41549 }
41552 }
41554 /* Generally when we see PLUS here, it's the function invariant
41555 (plus soft-fp const_int). Which can only be computed into general
41556 regs. */
41560 /* QImode constants are easy to load, but non-constant QImode data
41561 must go into Q_REGS. */
41563 {
41569 }
41572 }
41574 /* Discourage putting floating-point values in SSE registers unless
41575 SSE math is being used, and likewise for the 387 registers. */
41576 static reg_class_t
41578 {
41581 /* Restrict the output reload class to the register bank that we are doing
41582 math on. If we would like not to return a subset of CLASS, reject this
41583 alternative: if reload cannot do this, it will still use its choice. */
41589 {
41594 else
41596 }
41599 }
41601 static reg_class_t
41604 {
41605 /* Double-word spills from general registers to non-offsettable memory
41606 references (zero-extended addresses) require special handling. */
41612 {
41614 ? CODE_FOR_reload_noff_load
41616 /* Add the cost of moving address to a temporary. */
41620 }
41622 /* QImode spills from non-QI registers require
41623 intermediate register on 32bit targets. */
41629 {
41634 else
41640 /* Return Q_REGS if the operand is in memory. */
41643 }
41645 /* This condition handles corner case where an expression involving
41646 pointers gets vectorized. We're trying to use the address of a
41647 stack slot as a vector initializer.
41649 (set (reg:V2DI 74 [ vect_cst_.2 ])
41650 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
41652 Eventually frame gets turned into sp+offset like this:
41654 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41655 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41656 (const_int 392 [0x188]))))
41658 That later gets turned into:
41660 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41661 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41662 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
41664 We'll have the following reload recorded:
41666 Reload 0: reload_in (DI) =
41667 (plus:DI (reg/f:DI 7 sp)
41668 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
41669 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41670 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
41671 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
41672 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41673 reload_reg_rtx: (reg:V2DI 22 xmm1)
41675 Which isn't going to work since SSE instructions can't handle scalar
41676 additions. Returning GENERAL_REGS forces the addition into integer
41677 register and reload can handle subsequent reloads without problems. */
41685 }
41687 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
41689 static bool
41691 {
41693 {
41709 }
41712 }
41714 /* If we are copying between general and FP registers, we need a memory
41715 location. The same is true for SSE and MMX registers.
41717 To optimize register_move_cost performance, allow inline variant.
41719 The macro can't work reliably when one of the CLASSES is class containing
41720 registers from multiple units (SSE, MMX, integer). We avoid this by never
41721 combining those units in single alternative in the machine description.
41722 Ensure that this constraint holds to avoid unexpected surprises.
41724 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
41725 enforce these sanity checks. */
41730 {
41739 {
41742 }
41747 /* Between mask and general, we have moves no larger than word size. */
41752 /* ??? This is a lie. We do have moves between mmx/general, and for
41753 mmx/sse2. But by saying we need secondary memory we discourage the
41754 register allocator from using the mmx registers unless needed. */
41759 {
41760 /* SSE1 doesn't have any direct moves from other classes. */
41764 /* If the target says that inter-unit moves are more expensive
41765 than moving through memory, then don't generate them. */
41770 /* Between SSE and general, we have moves no larger than word size. */
41773 }
41776 }
41778 bool
41781 {
41783 }
41785 /* Implement the TARGET_CLASS_MAX_NREGS hook.
41787 On the 80386, this is the size of MODE in words,
41788 except in the FP regs, where a single reg is always enough. */
41790 static unsigned char
41792 {
41794 {
41799 else
41801 }
41802 else
41803 {
41806 else
41808 }
41809 }
41811 /* Return true if the registers in CLASS cannot represent the change from
41812 modes FROM to TO. */
41814 bool
41817 {
41821 /* x87 registers can't do subreg at all, as all values are reformatted
41822 to extended precision. */
41827 {
41828 /* Vector registers do not support QI or HImode loads. If we don't
41829 disallow a change to these modes, reload will assume it's ok to
41830 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
41831 the vec_dupv4hi pattern. */
41834 }
41837 }
41839 /* Return the cost of moving data of mode M between a
41840 register and memory. A value of 2 is the default; this cost is
41841 relative to those in `REGISTER_MOVE_COST'.
41843 This function is used extensively by register_move_cost that is used to
41844 build tables at startup. Make it inline in this case.
41845 When IN is 2, return maximum of in and out move cost.
41847 If moving between registers and memory is more expensive than
41848 between two registers, you should define this macro to express the
41849 relative cost.
41851 Model also increased moving costs of QImode registers in non
41852 Q_REGS classes.
41853 */
41857 {
41860 {
41863 {
41875 }
41879 }
41881 {
41884 {
41896 }
41900 }
41902 {
41905 {
41914 }
41918 }
41920 {
41923 {
41929 else
41934 }
41935 else
41936 {
41941 else
41943 }
41950 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
41957 else
41961 }
41962 }
41964 static int
41967 {
41969 }
41972 /* Return the cost of moving data from a register in class CLASS1 to
41973 one in class CLASS2.
41975 It is not required that the cost always equal 2 when FROM is the same as TO;
41976 on some machines it is expensive to move between registers if they are not
41977 general registers. */
41979 static int
41981 reg_class_t class2_i)
41982 {
41986 /* In case we require secondary memory, compute cost of the store followed
41987 by load. In order to avoid bad register allocation choices, we need
41988 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
41991 {
41997 /* In case of copying from general_purpose_register we may emit multiple
41998 stores followed by single load causing memory size mismatch stall.
41999 Count this as arbitrarily high cost of 20. */
42004 /* In the case of FP/MMX moves, the registers actually overlap, and we
42005 have to switch modes in order to treat them differently. */
42011 }
42013 /* Moves between SSE/MMX and integer unit are expensive. */
42017 /* ??? By keeping returned value relatively high, we limit the number
42018 of moves between integer and MMX/SSE registers for all targets.
42019 Additionally, high value prevents problem with x86_modes_tieable_p(),
42020 where integer modes in MMX/SSE registers are not tieable
42021 because of missing QImode and HImode moves to, from or between
42022 MMX/SSE registers. */
42032 }
42034 /* Return TRUE if hard register REGNO can hold a value of machine-mode
42035 MODE. */
42037 bool
42039 {
42040 /* Flags and only flags can only hold CCmode values. */
42051 || (TARGET_AVX512BW
42056 {
42057 /* We implement the move patterns for all vector modes into and
42058 out of SSE registers, even when no operation instructions
42059 are available. */
42061 /* For AVX-512 we allow, regardless of regno:
42062 - XI mode
42063 - any of 512-bit wide vector mode
42064 - any scalar mode. */
42071 /* TODO check for QI/HI scalars. */
42072 /* AVX512VL allows sse regs16+ for 128/256 bit modes. */
42080 /* xmm16-xmm31 are only available for AVX-512. */
42084 /* OImode and AVX modes are available only when AVX is enabled. */
42091 }
42093 {
42094 /* We implement the move patterns for 3DNOW modes even in MMX mode,
42095 so if the register is available at all, then we can move data of
42096 the given mode into or out of it. */
42099 }
42102 {
42103 /* Take care for QImode values - they can be in non-QI regs,
42104 but then they do cause partial register stalls. */
42109 /* LRA checks if the hard register is OK for the given mode.
42110 QImode values can live in non-QI regs, so we allow all
42111 registers here. */
42115 }
42116 /* We handle both integer and floats in the general purpose registers. */
42123 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
42124 on to use that value in smaller contexts, this can easily force a
42125 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
42126 supporting DImode, allow it. */
42131 }
42133 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
42134 tieable integer mode. */
42136 static bool
42138 {
42140 {
42153 }
42154 }
42156 /* Return true if MODE1 is accessible in a register that can hold MODE2
42157 without copying. That is, all register classes that can hold MODE2
42158 can also hold MODE1. */
42160 bool
42162 {
42170 /* MODE2 being XFmode implies fp stack or general regs, which means we
42171 can tie any smaller floating point modes to it. Note that we do not
42172 tie this with TFmode. */
42176 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
42177 that we can tie it with SFmode. */
42181 /* If MODE2 is only appropriate for an SSE register, then tie with
42182 any other mode acceptable to SSE registers. */
42192 /* If MODE2 is appropriate for an MMX register, then tie
42193 with any other mode acceptable to MMX registers. */
42200 }
42202 /* Return the cost of moving between two registers of mode MODE. */
42204 static int
42206 {
42210 {
42242 }
42244 /* Return the cost of moving between two registers of mode MODE,
42245 assuming that the move will be in pieces of at most UNITS bytes. */
42247 }
42249 /* Compute a (partial) cost for rtx X. Return true if the complete
42250 cost has been computed, and false if subexpressions should be
42251 scanned. In either case, *TOTAL contains the cost result. */
42253 static bool
42256 {
42257 rtx mask;
42264 {
42268 {
42271 }
42283 && !(TARGET_64BIT
42287 /* Use 0 cost for CONST to improve its propagation. */
42290 else
42300 {
42310 }
42312 {
42315 {
42324 }
42325 }
42326 /* Fall back to (MEM (SYMBOL_REF)), since that's where
42327 it'll probably end up. Add a penalty for size. */
42334 /* The zero extensions is often completely free on x86_64, so make
42335 it as cheap as possible. */
42341 else
42353 {
42356 {
42359 }
42362 {
42365 }
42366 }
42367 /* FALLTHRU */
42374 {
42375 /* ??? Should be SSE vector operation cost. */
42376 /* At least for published AMD latencies, this really is the same
42377 as the latency for a simple fpu operation like fabs. */
42378 /* V*QImode is emulated with 1-11 insns. */
42380 {
42383 {
42384 /* For XOP we use vpshab, which requires a broadcast of the
42385 value to the variable shift insn. For constants this
42386 means a V16Q const in mem; even when we can perform the
42387 shift with one insn set the cost to prefer paddb. */
42389 {
42394 }
42396 }
42400 }
42401 else
42403 }
42405 {
42407 {
42410 else
42412 }
42413 else
42414 {
42417 else
42419 }
42420 }
42421 else
42422 {
42427 {
42428 /* Return the cost after shift-and truncation. */
42431 }
42432 else
42434 }
42438 {
42439 rtx sub;
42444 /* ??? SSE scalar/vector cost should be used here. */
42445 /* ??? Bald assumption that fma has the same cost as fmul. */
42449 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
42460 }
42464 {
42465 /* ??? SSE scalar cost should be used here. */
42468 }
42470 {
42473 }
42475 {
42476 /* ??? SSE vector cost should be used here. */
42479 }
42481 {
42482 /* V*QImode is emulated with 7-13 insns. */
42484 {
42491 }
42492 /* V*DImode is emulated with 5-8 insns. */
42494 {
42497 else
42499 }
42500 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
42501 insns, including two PMULUDQ. */
42504 else
42507 }
42508 else
42509 {
42514 {
42517 nbits++;
42518 }
42519 else
42520 /* This is arbitrary. */
42523 /* Compute costs correctly for widening multiplication. */
42527 {
42534 {
42538 else
42540 }
42544 }
42552 }
42559 /* ??? SSE cost should be used here. */
42564 /* ??? SSE vector cost should be used here. */
42566 else
42573 {
42578 {
42581 {
42589 }
42590 }
42593 {
42596 {
42602 }
42603 }
42605 {
42613 }
42614 }
42615 /* FALLTHRU */
42619 {
42620 /* ??? SSE cost should be used here. */
42623 }
42625 {
42628 }
42630 {
42631 /* ??? SSE vector cost should be used here. */
42634 }
42635 /* FALLTHRU */
42642 {
42649 }
42650 /* FALLTHRU */
42654 {
42655 /* ??? SSE cost should be used here. */
42658 }
42660 {
42663 }
42665 {
42666 /* ??? SSE vector cost should be used here. */
42669 }
42670 /* FALLTHRU */
42674 {
42675 /* ??? Should be SSE vector operation cost. */
42676 /* At least for published AMD latencies, this really is the same
42677 as the latency for a simple fpu operation like fabs. */
42679 }
42682 else
42691 {
42692 /* This kind of construct is implemented using test[bwl].
42693 Treat it as if we had an AND. */
42698 }
42700 /* The embedded comparison operand is completely free. */
42714 /* ??? SSE cost should be used here. */
42719 /* ??? SSE vector cost should be used here. */
42725 /* ??? SSE cost should be used here. */
42730 /* ??? SSE vector cost should be used here. */
42742 /* ??? Assume all of these vector manipulation patterns are
42743 recognizable. In which case they all pretty much have the
42744 same cost. */
42749 /* This is masked instruction, assume the same cost,
42750 as nonmasked variant. */
42753 else
42759 }
42760 }
42762 #if TARGET_MACHO
42766 /* Given a symbol name and its associated stub, write out the
42767 definition of the stub. */
42769 void
42771 {
42776 /* For 64-bit we shouldn't get here. */
42779 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
42796 else
42803 {
42805 }
42807 {
42808 /* PIC stub. */
42809 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42815 }
42816 else
42819 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
42820 it needs no stub-binding-helper. */
42827 {
42830 }
42831 else
42836 /* N.B. Keep the correspondence of these
42837 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
42838 old-pic/new-pic/non-pic stubs; altering this will break
42839 compatibility with existing dylibs. */
42841 {
42842 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42844 }
42845 else
42846 /* 16-byte -mdynamic-no-pic stub. */
42852 }
42855 /* Order the registers for register allocator. */
42857 void
42859 {
42863 /* First allocate the local general purpose registers. */
42868 /* Global general purpose registers. */
42873 /* x87 registers come first in case we are doing FP math
42874 using them. */
42879 /* SSE registers. */
42885 /* Extended REX SSE registers. */
42889 /* Mask register. */
42893 /* MPX bound registers. */
42897 /* x87 registers. */
42905 /* Initialize the rest of array as we do not allocate some registers
42906 at all. */
42909 }
42911 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
42912 in struct attribute_spec handler. */
42913 static tree
42915 tree args,
42918 {
42923 {
42925 name);
42928 }
42930 {
42932 name);
42935 }
42937 {
42938 tree cst;
42942 {
42945 name);
42947 }
42950 {
42953 name);
42955 }
42958 }
42961 }
42963 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
42964 struct attribute_spec.handler. */
42965 static tree
42968 {
42973 {
42975 name);
42978 }
42980 /* Can combine regparm with all attributes but fastcall. */
42982 {
42984 {
42986 }
42989 }
42991 {
42993 {
42995 }
42998 }
43001 }
43003 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
43004 struct attribute_spec.handler. */
43005 static tree
43008 {
43011 {
43014 }
43015 else
43019 {
43021 name);
43023 }
43029 {
43031 name);
43033 }
43036 }
43038 static tree
43041 {
43043 {
43045 name);
43047 }
43049 }
43051 static bool
43053 {
43057 }
43059 /* Returns an expression indicating where the this parameter is
43060 located on entry to the FUNCTION. */
43062 static rtx
43064 {
43070 {
43075 else
43078 }
43083 {
43090 {
43095 }
43096 else
43097 {
43100 {
43106 }
43107 }
43109 }
43113 }
43115 /* Determine whether x86_output_mi_thunk can succeed. */
43117 static bool
43119 const_tree function)
43120 {
43121 /* 64-bit can handle anything. */
43125 /* For 32-bit, everything's fine if we have one free register. */
43129 /* Need a free register for vcall_offset. */
43133 /* Need a free register for GOT references. */
43137 /* Otherwise ok. */
43139 }
43141 /* Output the assembler code for a thunk function. THUNK_DECL is the
43142 declaration for the thunk function itself, FUNCTION is the decl for
43143 the target function. DELTA is an immediate constant offset to be
43144 added to THIS. If VCALL_OFFSET is nonzero, the word at
43145 *(*this + vcall_offset) should be added to THIS. */
43147 static void
43150 {
43158 else
43159 {
43165 else
43167 }
43171 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
43172 pull it in now and let DELTA benefit. */
43176 {
43177 /* Put the this parameter into %eax. */
43180 }
43181 else
43184 /* Adjust the this parameter by a fixed constant. */
43186 {
43191 {
43193 {
43197 }
43198 }
43201 }
43203 /* Adjust the this parameter by a value stored in the vtable. */
43205 {
43215 /* Adjust the this parameter. */
43219 {
43223 }
43230 vcall_mem));
43231 else
43233 }
43235 /* If necessary, drop THIS back to its stack slot. */
43241 {
43244 ;
43245 else
43246 {
43250 }
43251 }
43252 else
43253 {
43255 ;
43256 #if TARGET_MACHO
43258 {
43261 }
43263 else
43264 {
43272 }
43273 }
43275 /* Our sibling call patterns do not allow memories, because we have no
43276 predicate that can distinguish between frame and non-frame memory.
43277 For our purposes here, we can get away with (ab)using a jump pattern,
43278 because we're going to do no optimization. */
43280 {
43282 {
43288 }
43289 else
43291 }
43292 else
43293 {
43295 {
43296 // CM_LARGE_PIC always uses pseudo PIC register which is
43297 // uninitialized. Since FUNCTION is local and calling it
43298 // doesn't go through PLT, we use scratch register %r11 as
43299 // PIC register and initialize it here.
43304 }
43307 {
43313 }
43319 }
43322 /* Emit just enough of rest_of_compilation to get the insns emitted.
43323 Note that use_thunk calls assemble_start_function et al. */
43329 }
43331 static void
43333 {
43337 #if TARGET_MACHO
43339 #endif
43346 }
43348 int
43350 {
43351 machine_mode mode;
43364 }
43366 /* Print call to TARGET to FILE. */
43368 static void
43370 {
43373 else
43375 }
43377 /* Output assembler code to FILE to increment profiler label # LABELNO
43378 for profiling a function entry. */
43379 void
43381 {
43385 {
43386 #ifndef NO_PROFILE_COUNTERS
43388 #endif
43392 else
43394 }
43396 {
43397 #ifndef NO_PROFILE_COUNTERS
43400 #endif
43402 }
43403 else
43404 {
43405 #ifndef NO_PROFILE_COUNTERS
43408 #endif
43410 }
43413 {
43417 }
43418 }
43420 /* We don't have exact information about the insn sizes, but we may assume
43421 quite safely that we are informed about all 1 byte insns and memory
43422 address sizes. This is enough to eliminate unnecessary padding in
43423 99% of cases. */
43425 static int
43427 {
43433 /* Discard alignments we've emit and jump instructions. */
43438 /* Important case - calls are always 5 bytes.
43439 It is common to have many calls in the row. */
43448 /* For normal instructions we rely on get_attr_length being exact,
43449 with a few exceptions. */
43451 {
43455 {
43465 /* Otherwise trust get_attr_length. */
43467 }
43472 }
43475 else
43477 }
43479 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43481 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
43482 window. */
43484 static void
43486 {
43491 /* Look for all minimal intervals of instructions containing 4 jumps.
43492 The intervals are bounded by START and INSN. NBYTES is the total
43493 size of instructions in the interval including INSN and not including
43494 START. When the NBYTES is smaller than 16 bytes, it is possible
43495 that the end of START and INSN ends up in the same 16byte page.
43497 The smallest offset in the page INSN can start is the case where START
43498 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
43499 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
43501 Don't consider asm goto as jump, while it can contain a jump, it doesn't
43502 have to, control transfer to label(s) can be performed through other
43503 means, and also we estimate minimum length of all asm stmts as 0. */
43505 {
43509 {
43515 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
43516 already in the current 16 byte page, because otherwise
43517 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
43518 bytes to reach 16 byte boundary. */
43526 {
43528 {
43533 else
43536 }
43537 }
43539 }
43548 njumps++;
43549 else
43553 {
43558 else
43561 }
43568 {
43575 }
43576 }
43577 }
43578 #endif
43580 /* AMD Athlon works faster
43581 when RET is not destination of conditional jump or directly preceded
43582 by other jump instruction. We avoid the penalty by inserting NOP just
43583 before the RET instructions in such cases. */
43584 static void
43586 {
43587 edge e;
43588 edge_iterator ei;
43591 {
43604 {
43605 edge e;
43606 edge_iterator ei;
43611 {
43614 }
43615 }
43617 {
43623 /* Empty functions get branch mispredict even when
43624 the jump destination is not visible to us. */
43627 }
43629 {
43632 }
43633 }
43634 }
43636 /* Count the minimum number of instructions in BB. Return 4 if the
43637 number of instructions >= 4. */
43639 static int
43641 {
43645 /* Count number of instructions in this block. Return 4 if the number
43646 of instructions >= 4. */
43648 {
43649 /* Only happen in exit blocks. */
43657 {
43658 insn_count++;
43661 }
43662 }
43665 }
43668 /* Count the minimum number of instructions in code path in BB.
43669 Return 4 if the number of instructions >= 4. */
43671 static int
43673 {
43674 edge e;
43675 edge_iterator ei;
43678 /* Only bother counting instructions along paths with no
43679 more than 2 basic blocks between entry and exit. Given
43680 that BB has an edge to exit, determine if a predecessor
43681 of BB has an edge from entry. If so, compute the number
43682 of instructions in the predecessor block. If there
43683 happen to be multiple such blocks, compute the minimum. */
43686 {
43687 edge prev_e;
43688 edge_iterator prev_ei;
43691 {
43694 }
43696 {
43698 {
43703 }
43704 }
43705 }
43711 }
43713 /* Pad short function to 4 instructions. */
43715 static void
43717 {
43718 edge e;
43719 edge_iterator ei;
43722 {
43725 {
43728 /* Pad short function. */
43730 {
43733 /* Find epilogue. */
43742 /* Two NOPs count as one instruction. */
43745 }
43746 }
43747 }
43748 }
43750 /* Fix up a Windows system unwinder issue. If an EH region falls through into
43751 the epilogue, the Windows system unwinder will apply epilogue logic and
43752 produce incorrect offsets. This can be avoided by adding a nop between
43753 the last insn that can throw and the first insn of the epilogue. */
43755 static void
43757 {
43758 edge e;
43759 edge_iterator ei;
43762 {
43765 /* Find the beginning of the epilogue. */
43772 /* We only care about preceding insns that can throw. */
43777 /* Do not separate calls from their debug information. */
43783 else
43787 }
43788 }
43790 /* Implement machine specific optimizations. We implement padding of returns
43791 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
43792 static void
43794 {
43795 /* We are freeing block_for_insn in the toplev to keep compatibility
43796 with old MDEP_REORGS that are not CFG based. Recompute it now. */
43803 {
43808 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43811 #endif
43812 }
43813 }
43815 /* Return nonzero when QImode register that must be represented via REX prefix
43816 is used. */
43817 bool
43819 {
43827 }
43829 /* Return true when INSN mentions register that must be encoded using REX
43830 prefix. */
43831 bool
43833 {
43836 {
43841 }
43843 }
43845 /* If profitable, negate (without causing overflow) integer constant
43846 of mode MODE at location LOC. Return true in this case. */
43847 bool
43849 {
43850 HOST_WIDE_INT val;
43856 {
43858 /* DImode x86_64 constants must fit in 32 bits. */
43871 }
43873 /* Avoid overflows. */
43879 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
43880 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
43883 {
43886 }
43889 }
43891 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
43892 optabs would emit if we didn't have TFmode patterns. */
43894 void
43896 {
43931 }
43932 \f
43938 /* Get a vector mode of the same size as the original but with elements
43939 twice as wide. This is only guaranteed to apply to integral vectors. */
43943 {
43944 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
43949 }
43951 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
43952 fill target with val via vec_duplicate. */
43954 static bool
43956 {
43959 rtx dup;
43961 /* First attempt to recognize VAL as-is. */
43965 {
43967 /* If that fails, force VAL into a register. */
43978 }
43980 }
43982 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43983 with all elements equal to VAR. Return true if successful. */
43985 static bool
43988 {
43992 {
43997 /* FALLTHRU */
44017 {
44018 rtx x;
44025 }
44038 {
44042 permute:
44050 /* Extend to SImode using a paradoxical SUBREG. */
44054 /* Insert the SImode value as low element of a V4SImode vector. */
44063 }
44074 widen:
44075 /* Replicate the value once into the next wider mode and recurse. */
44076 {
44078 rtx x;
44095 }
44101 else
44102 {
44111 }
44118 else
44119 {
44128 }
44133 }
44134 }
44136 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
44137 whose ONE_VAR element is VAR, and other elements are zero. Return true
44138 if successful. */
44140 static bool
44143 {
44144 machine_mode vsimode;
44145 rtx new_target;
44150 {
44152 /* For SSE4.1, we normally use vector set. But if the second
44153 element is zero and inter-unit moves are OK, we use movq
44154 instead. */
44156 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
44178 /* Use ix86_expand_vector_set in 64bit mode only. */
44183 }
44186 {
44191 }
44194 {
44199 /* FALLTHRU */
44214 else
44221 {
44222 /* We need to shuffle the value to the correct position, so
44223 create a new pseudo to store the intermediate result. */
44225 /* With SSE2, we can use the integer shuffle insns. */
44227 {
44229 const1_rtx,
44236 }
44238 /* Otherwise convert the intermediate result to V4SFmode and
44239 use the SSE1 shuffle instructions. */
44241 {
44244 }
44245 else
44249 const1_rtx,
44258 }
44273 widen:
44277 /* Zero extend the variable element to SImode and recurse. */
44290 }
44291 }
44293 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
44294 consisting of the values in VALS. It is known that all elements
44295 except ONE_VAR are constants. Return true if successful. */
44297 static bool
44300 {
44302 machine_mode wmode;
44310 {
44315 /* For the two element vectors, it's just as easy to use
44316 the general case. */
44320 /* Use ix86_expand_vector_set in 64bit mode only. */
44342 widen:
44343 /* There's no way to set one QImode entry easily. Combine
44344 the variable value with its adjacent constant value, and
44345 promote to an HImode set. */
44348 {
44353 }
44354 else
44355 {
44358 }
44372 }
44377 }
44379 /* A subroutine of ix86_expand_vector_init_general. Use vector
44380 concatenate to handle the most general case: all values variable,
44381 and none identical. */
44383 static void
44386 {
44389 rtvec v;
44393 {
44396 {
44441 }
44453 {
44468 }
44473 {
44492 }
44497 {
44510 }
44513 half:
44514 /* FIXME: We process inputs backward to help RA. PR 36222. */
44518 {
44523 }
44527 {
44531 {
44535 }
44538 {
44542 }
44545 }
44547 {
44550 {
44554 }
44557 }
44558 else
44564 }
44565 }
44567 /* A subroutine of ix86_expand_vector_init_general. Use vector
44568 interleave to handle the most general case: all values variable,
44569 and none identical. */
44571 static void
44574 {
44583 {
44604 }
44607 {
44608 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
44612 /* Insert the SImode value as low element of V4SImode vector. */
44616 op0),
44618 const1_rtx);
44621 /* Cast the V4SImode vector back to a vector in orignal mode. */
44625 /* Load even elements into the second position. */
44629 const1_rtx));
44631 /* Cast vector to FIRST_IMODE vector. */
44634 }
44636 /* Interleave low FIRST_IMODE vectors. */
44638 {
44642 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
44645 }
44647 /* Interleave low SECOND_IMODE vectors. */
44649 {
44652 {
44657 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
44658 vector. */
44661 }
44664 /* FALLTHRU */
44671 /* Cast the SECOND_IMODE vector back to a vector on original
44672 mode. */
44678 }
44679 }
44681 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
44682 all values variable, and none identical. */
44684 static void
44687 {
44694 {
44699 /* FALLTHRU */
44727 half:
44750 quarter:
44776 /* FALLTHRU */
44782 /* Don't use ix86_expand_vector_init_interleave if we can't
44783 move from GPR to SSE register directly. */
44799 }
44801 {
44803 machine_mode inner_mode;
44813 {
44817 {
44823 else
44824 {
44829 }
44830 }
44833 }
44838 {
44844 }
44846 {
44852 }
44853 else
44855 }
44856 }
44858 /* Initialize vector TARGET via VALS. Suppress the use of MMX
44859 instructions unless MMX_OK is true. */
44861 void
44863 {
44870 rtx x;
44873 {
44883 }
44885 /* Constants are best loaded from the constant pool. */
44887 {
44890 }
44892 /* If all values are identical, broadcast the value. */
44898 /* Values where only one field is non-constant are best loaded from
44899 the pool and overwritten via move later. */
44901 {
44905 one_var))
44910 }
44913 }
44915 void
44917 {
44920 machine_mode half_mode;
44922 rtx tmp;
44924 = {
44931 };
44933 = {
44940 };
44946 {
44950 {
44955 else
44959 }
44971 else
44977 {
44980 /* For the two element vectors, we implement a VEC_CONCAT with
44981 the extraction of the other element. */
44988 else
44993 }
45002 {
45008 /* tmp = target = A B C D */
45010 /* target = A A B B */
45012 /* target = X A B B */
45014 /* target = A X C D */
45021 /* tmp = target = A B C D */
45023 /* tmp = X B C D */
45025 /* target = A B X D */
45032 /* tmp = target = A B C D */
45034 /* tmp = X B C D */
45036 /* target = A B X D */
45044 }
45052 /* Element 0 handled by vec_merge below. */
45054 {
45057 }
45060 {
45061 /* With SSE2, use integer shuffles to swap element 0 and ELT,
45062 store into element 0, then shuffle them back. */
45079 }
45080 else
45081 {
45082 /* For SSE1, we have to reuse the V4SF code. */
45086 }
45139 half:
45140 /* Compute offset. */
45146 /* Extract the half. */
45150 /* Put val in tmp at elt. */
45153 /* Put it back. */
45159 {
45162 }
45167 {
45170 }
45175 {
45178 }
45183 {
45186 }
45191 {
45194 }
45199 {
45202 }
45207 }
45210 {
45216 }
45218 {
45222 }
45223 else
45224 {
45233 }
45234 }
45236 void
45238 {
45242 rtx tmp;
45245 {
45250 /* FALLTHRU */
45263 {
45283 }
45295 {
45297 {
45317 }
45321 }
45322 else
45323 {
45324 /* For SSE1, we have to reuse the V4SF code. */
45328 }
45344 {
45348 else
45352 }
45357 {
45361 else
45365 }
45370 {
45374 else
45378 }
45383 {
45387 else
45391 }
45396 {
45400 else
45404 }
45409 {
45413 else
45417 }
45422 {
45426 else
45430 }
45435 {
45439 else
45443 }
45450 else
45459 else
45468 else
45477 else
45483 /* ??? Could extract the appropriate HImode element and shift. */
45486 }
45489 {
45493 /* Let the rtl optimizers know about the zero extension performed. */
45495 {
45498 }
45501 }
45502 else
45503 {
45510 }
45511 }
45513 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
45514 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
45515 The upper bits of DEST are undefined, though they shouldn't cause
45516 exceptions (some bits from src or all zeros are ok). */
45518 static void
45520 {
45523 {
45527 else
45545 else
45552 else
45560 {
45565 const1_rtx);
45566 }
45567 else
45568 {
45572 }
45594 else
45616 }
45620 }
45622 /* Expand a vector reduction. FN is the binary pattern to reduce;
45623 DEST is the destination; IN is the input vector. */
45625 void
45627 {
45632 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
45636 {
45639 }
45644 {
45649 else
45653 }
45654 }
45655 \f
45656 /* Target hook for scalar_mode_supported_p. */
45657 static bool
45659 {
45664 else
45666 }
45668 /* Implements target hook vector_mode_supported_p. */
45669 static bool
45671 {
45685 }
45687 /* Implement target hook libgcc_floating_mode_supported_p. */
45688 static bool
45690 {
45692 {
45699 #ifdef IX86_NO_LIBGCC_TFMODE
45701 #elif defined IX86_MAYBE_NO_LIBGCC_TFMODE
45703 #else
45705 #endif
45709 }
45710 }
45712 /* Target hook for c_mode_for_suffix. */
45713 static machine_mode
45715 {
45722 }
45724 /* Worker function for TARGET_MD_ASM_ADJUST.
45726 We implement asm flag outputs, and maintain source compatibility
45727 with the old cc0-based compiler. */
45733 {
45741 {
45747 {
45750 }
45760 {
45809 }
45811 {
45814 }
45820 {
45821 /* This is the first asm flag output. Here we put the flags
45822 register in as the real output and adjust the condition to
45823 allow it. */
45827 }
45828 else
45829 {
45830 /* We don't need the flags register as output twice. */
45833 }
45840 {
45843 }
45845 {
45849 }
45851 }
45857 else
45858 {
45859 /* If we had no asm flag outputs, clobber the flags. */
45863 }
45864 }
45866 /* Implements target vector targetm.asm.encode_section_info. */
45868 static void ATTRIBUTE_UNUSED
45870 {
45875 }
45877 /* Worker function for REVERSE_CONDITION. */
45879 enum rtx_code
45881 {
45885 }
45887 /* Output code to perform an x87 FP register move, from OPERANDS[1]
45888 to OPERANDS[0]. */
45892 {
45894 {
45897 {
45901 }
45905 }
45907 {
45911 else
45912 {
45913 /* There is no non-popping store to memory for XFmode.
45914 So if we need one, follow the store with a load. */
45917 else
45919 }
45920 }
45921 else
45923 }
45925 /* Output code to perform a conditional jump to LABEL, if C2 flag in
45926 FP status register is set. */
45928 void
45930 {
45932 rtx temp;
45937 {
45942 }
45943 else
45944 {
45949 }
45953 pc_rtx);
45958 }
45960 /* Output code to perform a log1p XFmode calculation. */
45963 {
45969 rtx test;
45975 XFmode));
45989 }
45991 /* Emit code for round calculation. */
45993 {
46000 rtx insn;
46005 {
46017 }
46020 {
46041 }
46049 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
46051 /* scratch = fxam(op1) */
46054 UNSPEC_FXAM)));
46055 /* e1 = fabs(op1) */
46058 /* e2 = e1 + 0.5 */
46062 /* res = floor(e2) */
46064 {
46068 }
46069 else
46073 {
46076 {
46083 UNSPEC_TRUNC_NOOP)));
46084 }
46100 }
46102 /* flags = signbit(a) */
46105 /* if (flags) then res = -res */
46109 pc_rtx);
46120 }
46122 /* Output code to perform a Newton-Rhapson approximation of a single precision
46123 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
46126 {
46134 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
46138 /* x0 = rcp(b) estimate */
46141 UNSPEC_RCP14)));
46142 else
46144 UNSPEC_RCP)));
46146 /* e0 = x0 * b */
46149 /* e0 = x0 * e0 */
46152 /* e1 = x0 + x0 */
46155 /* x1 = e1 - e0 */
46158 /* res = a * x1 */
46160 }
46162 /* Output code to perform a Newton-Rhapson approximation of a
46163 single precision floating point [reciprocal] square root. */
46167 {
46169 REAL_VALUE_TYPE r;
46186 {
46189 /* There is no 512-bit rsqrt. There is however rsqrt14. */
46192 }
46194 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
46195 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
46199 /* x0 = rsqrt(a) estimate */
46201 unspec)));
46203 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
46205 {
46213 /* Handle masked compare. */
46215 {
46217 /* Imm value 0x4 corresponds to not-equal comparison. */
46220 }
46221 else
46222 {
46226 }
46227 }
46229 /* e0 = x0 * a */
46231 /* e1 = e0 * x0 */
46234 /* e2 = e1 - 3. */
46240 /* e3 = -.5 * x0 */
46242 else
46243 /* e3 = -.5 * e0 */
46245 /* ret = e2 * e3 */
46247 }
46249 #ifdef TARGET_SOLARIS
46250 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
46252 static void
46254 tree decl)
46255 {
46256 /* With Binutils 2.15, the "@unwind" marker must be specified on
46257 every occurrence of the ".eh_frame" section, not just the first
46258 one. */
46261 {
46265 }
46267 #ifndef USE_GAS
46269 {
46272 }
46273 #endif
46276 }
46279 /* Return the mangling of TYPE if it is an extended fundamental type. */
46283 {
46291 {
46293 /* __float128 is "g". */
46296 /* "long double" or __float80 is "e". */
46300 }
46301 }
46303 /* For 32-bit code we can save PIC register setup by using
46304 __stack_chk_fail_local hidden function instead of calling
46305 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
46306 register, so it is better to call __stack_chk_fail directly. */
46308 static tree ATTRIBUTE_UNUSED
46310 {
46311 return TARGET_64BIT
46314 }
46316 /* Select a format to encode pointers in exception handling data. CODE
46317 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
46318 true if the symbol may be affected by dynamic relocations.
46320 ??? All x86 object file formats are capable of representing this.
46321 After all, the relocation needed is the same as for the call insn.
46322 Whether or not a particular assembler allows us to enter such, I
46323 guess we'll have to see. */
46324 int
46326 {
46328 {
46335 }
46340 }
46341 \f
46342 /* Expand copysign from SIGN to the positive value ABS_VALUE
46343 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
46344 the sign-bit. */
46345 static void
46347 {
46351 {
46352 machine_mode vmode;
46358 else
46363 {
46364 /* We need to generate a scalar mode mask in this case. */
46369 }
46370 }
46371 else
46375 }
46377 /* Expand fabs (OP0) and return a new rtx that holds the result. The
46378 mask for masking out the sign-bit is stored in *SMASK, if that is
46379 non-null. */
46380 static rtx
46382 {
46391 else
46395 {
46396 /* We need to generate a scalar mode mask in this case. */
46401 }
46408 }
46410 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
46411 swapping the operands if SWAP_OPERANDS is true. The expanded
46412 code is a forward jump to a newly created label in case the
46413 comparison is true. The generated label rtx is returned. */
46417 {
46420 rtx tmp;
46435 }
46437 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
46438 using comparison code CODE. Operands are swapped for the comparison if
46439 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
46440 static rtx
46443 {
46456 }
46458 /* Generate and return a rtx of mode MODE for 2**n where n is the number
46459 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
46460 static rtx
46462 {
46463 REAL_VALUE_TYPE TWO52r;
46464 rtx TWO52;
46471 }
46473 /* Expand SSE sequence for computing lround from OP1 storing
46474 into OP0. */
46475 void
46477 {
46478 /* C code for the stuff we're doing below:
46479 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
46480 return (long)tmp;
46481 */
46485 rtx adj;
46487 /* load nextafter (0.5, 0.0) */
46492 /* adj = copysign (0.5, op1) */
46496 /* adj = op1 + adj */
46499 /* op0 = (imode)adj */
46501 }
46503 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
46504 into OPERAND0. */
46505 void
46507 {
46508 /* C code for the stuff we're doing below (for do_floor):
46509 xi = (long)op1;
46510 xi -= (double)xi > op1 ? 1 : 0;
46511 return xi;
46512 */
46518 /* reg = (long)op1 */
46522 /* freg = (double)reg */
46526 /* ireg = (freg > op1) ? ireg - 1 : ireg */
46537 }
46539 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
46540 result in OPERAND0. */
46541 void
46543 {
46544 /* C code for the stuff we're doing below:
46545 xa = fabs (operand1);
46546 if (!isless (xa, 2**52))
46547 return operand1;
46548 xa = xa + 2**52 - 2**52;
46549 return copysign (xa, operand1);
46550 */
46558 /* xa = abs (operand1) */
46561 /* if (!isless (xa, TWO52)) goto label; */
46574 }
46576 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46577 into OPERAND0. */
46578 void
46580 {
46581 /* C code for the stuff we expand below.
46582 double xa = fabs (x), x2;
46583 if (!isless (xa, TWO52))
46584 return x;
46585 xa = xa + TWO52 - TWO52;
46586 x2 = copysign (xa, x);
46587 Compensate. Floor:
46588 if (x2 > x)
46589 x2 -= 1;
46590 Compensate. Ceil:
46591 if (x2 < x)
46592 x2 -= -1;
46593 return x2;
46594 */
46601 /* Temporary for holding the result, initialized to the input
46602 operand to ease control flow. */
46606 /* xa = abs (operand1) */
46609 /* if (!isless (xa, TWO52)) goto label; */
46612 /* xa = xa + TWO52 - TWO52; */
46616 /* xa = copysign (xa, operand1) */
46619 /* generate 1.0 or -1.0 */
46624 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46627 /* We always need to subtract here to preserve signed zero. */
46636 }
46638 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46639 into OPERAND0. */
46640 void
46642 {
46643 /* C code for the stuff we expand below.
46644 double xa = fabs (x), x2;
46645 if (!isless (xa, TWO52))
46646 return x;
46647 x2 = (double)(long)x;
46648 Compensate. Floor:
46649 if (x2 > x)
46650 x2 -= 1;
46651 Compensate. Ceil:
46652 if (x2 < x)
46653 x2 += 1;
46654 if (HONOR_SIGNED_ZEROS (mode))
46655 return copysign (x2, x);
46656 return x2;
46657 */
46664 /* Temporary for holding the result, initialized to the input
46665 operand to ease control flow. */
46669 /* xa = abs (operand1) */
46672 /* if (!isless (xa, TWO52)) goto label; */
46675 /* xa = (double)(long)x */
46680 /* generate 1.0 */
46683 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46697 }
46699 /* Expand SSE sequence for computing round from OPERAND1 storing
46700 into OPERAND0. Sequence that works without relying on DImode truncation
46701 via cvttsd2siq that is only available on 64bit targets. */
46702 void
46704 {
46705 /* C code for the stuff we expand below.
46706 double xa = fabs (x), xa2, x2;
46707 if (!isless (xa, TWO52))
46708 return x;
46709 Using the absolute value and copying back sign makes
46710 -0.0 -> -0.0 correct.
46711 xa2 = xa + TWO52 - TWO52;
46712 Compensate.
46713 dxa = xa2 - xa;
46714 if (dxa <= -0.5)
46715 xa2 += 1;
46716 else if (dxa > 0.5)
46717 xa2 -= 1;
46718 x2 = copysign (xa2, x);
46719 return x2;
46720 */
46727 /* Temporary for holding the result, initialized to the input
46728 operand to ease control flow. */
46732 /* xa = abs (operand1) */
46735 /* if (!isless (xa, TWO52)) goto label; */
46738 /* xa2 = xa + TWO52 - TWO52; */
46742 /* dxa = xa2 - xa; */
46745 /* generate 0.5, 1.0 and -0.5 */
46751 /* Compensate. */
46753 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
46757 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
46762 /* res = copysign (xa2, operand1) */
46769 }
46771 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46772 into OPERAND0. */
46773 void
46775 {
46776 /* C code for SSE variant we expand below.
46777 double xa = fabs (x), x2;
46778 if (!isless (xa, TWO52))
46779 return x;
46780 x2 = (double)(long)x;
46781 if (HONOR_SIGNED_ZEROS (mode))
46782 return copysign (x2, x);
46783 return x2;
46784 */
46791 /* Temporary for holding the result, initialized to the input
46792 operand to ease control flow. */
46796 /* xa = abs (operand1) */
46799 /* if (!isless (xa, TWO52)) goto label; */
46802 /* x = (double)(long)x */
46814 }
46816 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46817 into OPERAND0. */
46818 void
46820 {
46825 /* C code for SSE variant we expand below.
46826 double xa = fabs (x), x2;
46827 if (!isless (xa, TWO52))
46828 return x;
46829 xa2 = xa + TWO52 - TWO52;
46830 Compensate:
46831 if (xa2 > xa)
46832 xa2 -= 1.0;
46833 x2 = copysign (xa2, x);
46834 return x2;
46835 */
46839 /* Temporary for holding the result, initialized to the input
46840 operand to ease control flow. */
46844 /* xa = abs (operand1) */
46847 /* if (!isless (xa, TWO52)) goto label; */
46850 /* res = xa + TWO52 - TWO52; */
46855 /* generate 1.0 */
46858 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
46865 /* res = copysign (res, operand1) */
46872 }
46874 /* Expand SSE sequence for computing round from OPERAND1 storing
46875 into OPERAND0. */
46876 void
46878 {
46879 /* C code for the stuff we're doing below:
46880 double xa = fabs (x);
46881 if (!isless (xa, TWO52))
46882 return x;
46883 xa = (double)(long)(xa + nextafter (0.5, 0.0));
46884 return copysign (xa, x);
46885 */
46892 /* Temporary for holding the result, initialized to the input
46893 operand to ease control flow. */
46901 /* load nextafter (0.5, 0.0) */
46906 /* xa = xa + 0.5 */
46910 /* xa = (double)(int64_t)xa */
46915 /* res = copysign (xa, operand1) */
46922 }
46924 /* Expand SSE sequence for computing round
46925 from OP1 storing into OP0 using sse4 round insn. */
46926 void
46928 {
46937 {
46948 }
46950 /* round (a) = trunc (a + copysign (0.5, a)) */
46952 /* load nextafter (0.5, 0.0) */
46958 /* e1 = copysign (0.5, op1) */
46962 /* e2 = op1 + e1 */
46965 /* res = trunc (e2) */
46970 }
46971 \f
46973 /* Table of valid machine attributes. */
46975 {
46976 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
46977 affects_type_identity } */
46978 /* Stdcall attribute says callee is responsible for popping arguments
46979 if they are not variable. */
46982 /* Fastcall attribute says callee is responsible for popping arguments
46983 if they are not variable. */
46986 /* Thiscall attribute says callee is responsible for popping arguments
46987 if they are not variable. */
46990 /* Cdecl attribute says the callee is a normal C declaration */
46993 /* Regparm attribute specifies how many integer arguments are to be
46994 passed in registers. */
46997 /* Sseregparm attribute says we are using x86_64 calling conventions
46998 for FP arguments. */
47001 /* The transactional memory builtins are implicitly regparm or fastcall
47002 depending on the ABI. Override the generic do-nothing attribute that
47003 these builtins were declared with. */
47006 /* force_align_arg_pointer says this function realigns the stack at entry. */
47009 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
47014 #endif
47019 #ifdef SUBTARGET_ATTRIBUTE_TABLE
47020 SUBTARGET_ATTRIBUTE_TABLE,
47021 #endif
47022 /* ms_abi and sysv_abi calling convention function attributes. */
47029 /* End element. */
47031 };
47033 /* Implement targetm.vectorize.builtin_vectorization_cost. */
47034 static int
47037 {
47041 {
47086 }
47087 }
47089 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
47090 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
47091 insn every time. */
47095 /* Initialize vselect_insn. */
47097 static void
47099 {
47101 rtx x;
47112 }
47114 /* Construct (set target (vec_select op0 (parallel perm))) and
47115 return true if that's a valid instruction in the active ISA. */
47117 static bool
47120 {
47146 }
47148 /* Similar, but generate a vec_concat from op0 and op1 as well. */
47150 static bool
47154 {
47155 machine_mode v2mode;
47156 rtx x;
47171 }
47173 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47174 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
47176 static bool
47178 {
47187 && (TARGET_AVX512BW
47189 ;
47191 ;
47193 ;
47195 ;
47196 else
47199 /* This is a blend, not a permute. Elements must stay in their
47200 respective lanes. */
47202 {
47206 }
47211 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
47212 decision should be extracted elsewhere, so that we only try that
47213 sequence once all budget==3 options have been tried. */
47220 {
47250 /* See if bytes move in pairs so we can use pblendw with
47251 an immediate argument, rather than pblendvb with a vector
47252 argument. */
47255 {
47256 use_pblendvb:
47260 finish_pblendvb:
47266 else
47271 }
47276 /* FALLTHRU */
47278 do_subreg:
47285 /* See if bytes move in pairs. If not, vpblendvb must be used. */
47289 /* See if bytes move in quadruplets. If yes, vpblendd
47290 with immediate can be used. */
47295 {
47296 /* See if bytes move the same in both lanes. If yes,
47297 vpblendw with immediate can be used. */
47302 /* Use vpblendw. */
47307 }
47309 /* Use vpblendd. */
47316 /* See if words move in pairs. If yes, vpblendd can be used. */
47321 {
47322 /* See if words move the same in both lanes. If not,
47323 vpblendvb must be used. */
47326 {
47327 /* Use vpblendvb. */
47337 }
47339 /* Use vpblendw. */
47343 }
47345 /* Use vpblendd. */
47352 /* Use vpblendd. */
47360 }
47363 {
47380 }
47384 else
47387 /* This matches five different patterns with the different modes. */
47395 }
47397 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47398 in terms of the variable form of vpermilps.
47400 Note that we will have already failed the immediate input vpermilps,
47401 which requires that the high and low part shuffle be identical; the
47402 variable form doesn't require that. */
47404 static bool
47406 {
47413 /* We can only permute within the 128-bit lane. */
47415 {
47419 }
47425 {
47428 /* Within each 128-bit lane, the elements of op0 are numbered
47429 from 0 and the elements of op1 are numbered from 4. */
47436 }
47443 }
47445 /* Return true if permutation D can be performed as VMODE permutation
47446 instead. */
47448 static bool
47450 {
47465 else
47471 }
47473 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47474 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
47476 static bool
47478 {
47487 {
47489 {
47492 {
47496 /* Use vperm2i128 insn. The pattern uses
47497 V4DImode instead of V2TImode. */
47510 }
47512 }
47513 }
47514 else
47515 {
47517 {
47520 }
47522 {
47526 /* V4DImode should be already handled through
47527 expand_vselect by vpermq instruction. */
47534 {
47535 /* First see if vpermq can be used for
47536 V8SImode/V16HImode/V32QImode. */
47538 {
47546 {
47550 }
47552 }
47554 /* Next see if vpermd can be used. */
47557 }
47558 /* Or if vpermps can be used. */
47563 {
47564 /* vpshufb only works intra lanes, it is not
47565 possible to shuffle bytes in between the lanes. */
47569 }
47570 }
47572 {
47576 /* If vpermq didn't work, vpshufb won't work either. */
47584 {
47585 /* First see if vpermq can be used for
47586 V16SImode/V32HImode/V64QImode. */
47588 {
47596 {
47600 }
47602 }
47604 /* Next see if vpermd can be used. */
47607 }
47608 /* Or if vpermps can be used. */
47612 {
47613 /* vpshufb only works intra lanes, it is not
47614 possible to shuffle bytes in between the lanes. */
47618 }
47619 }
47620 else
47622 }
47633 else
47634 {
47642 else
47646 {
47650 }
47651 }
47662 {
47677 else
47679 }
47680 else
47681 {
47684 }
47689 }
47691 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
47692 in a single instruction. */
47694 static bool
47696 {
47700 /* Check plain VEC_SELECT first, because AVX has instructions that could
47701 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
47702 input where SEL+CONCAT may not. */
47704 {
47710 {
47716 }
47719 {
47723 }
47725 {
47726 /* Use vpbroadcast{b,w,d}. */
47729 {
47772 /* For other modes prefer other shuffles this function creates. */
47774 }
47776 {
47780 }
47781 }
47786 /* There are plenty of patterns in sse.md that are written for
47787 SEL+CONCAT and are not replicated for a single op. Perhaps
47788 that should be changed, to avoid the nastiness here. */
47790 /* Recognize interleave style patterns, which means incrementing
47791 every other permutation operand. */
47793 {
47796 }
47801 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
47803 {
47805 {
47810 }
47815 }
47816 }
47818 /* Finally, try the fully general two operand permute. */
47823 /* Recognize interleave style patterns with reversed operands. */
47825 {
47827 {
47831 else
47834 }
47839 }
47841 /* Try the SSE4.1 blend variable merge instructions. */
47845 /* Try one of the AVX vpermil variable permutations. */
47849 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
47850 vpshufb, vpermd, vpermps or vpermq variable permutation. */
47854 /* Try the AVX2 vpalignr instruction. */
47858 /* Try the AVX512F vpermi2 instructions. */
47863 }
47865 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47866 in terms of a pair of pshuflw + pshufhw instructions. */
47868 static bool
47870 {
47878 /* The two permutations only operate in 64-bit lanes. */
47889 /* Emit the pshuflw. */
47896 /* Emit the pshufhw. */
47904 }
47906 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47907 the permutation using the SSSE3 palignr instruction. This succeeds
47908 when all of the elements in PERM fit within one vector and we merely
47909 need to shift them down so that a single vector permutation has a
47910 chance to succeed. If SINGLE_INSN_ONLY_P, succeed if only
47911 the vpalignr instruction itself can perform the requested permutation. */
47913 static bool
47915 {
47922 /* Even with AVX, palignr only operates on 128-bit vectors,
47923 in AVX2 palignr operates on both 128-bit lanes. */
47933 {
47937 {
47940 }
47949 }
47952 {
47961 }
47963 /* Given that we have SSSE3, we know we'll be able to implement the
47964 single operand permutation after the palignr with pshufb for
47965 128-bit vectors. If SINGLE_INSN_ONLY_P, in_order has to be computed
47966 first. */
47972 {
47977 }
47981 {
47987 else
47992 }
47998 /* For AVX2, test whether we can permute the result in one instruction. */
48000 {
48005 }
48009 {
48013 }
48014 else
48015 {
48020 shift));
48021 }
48025 /* Test for the degenerate case where the alignment by itself
48026 produces the desired permutation. */
48028 {
48031 }
48037 }
48039 /* A subroutine of ix86_expand_vec_perm_const_1. Try to simplify
48040 the permutation using the SSE4_1 pblendv instruction. Potentially
48041 reduces permutation from 2 pshufb and or to 1 pshufb and pblendv. */
48043 static bool
48045 {
48051 /* Use the same checks as in expand_vec_perm_blend. */
48055 ;
48057 ;
48059 ;
48060 else
48063 /* Figure out where permutation elements stay not in their
48064 respective lanes. */
48066 {
48070 }
48071 /* We can pblend the part where elements stay not in their
48072 respective lanes only when these elements are all in one
48073 half of a permutation.
48074 {0 1 8 3 4 5 9 7} is ok as 8, 9 are at not at their respective
48075 lanes, but both 8 and 9 >= 8
48076 {0 1 8 3 4 5 2 7} is not ok as 2 and 8 are not at their
48077 respective lanes and 8 >= 8, but 2 not. */
48083 /* First we apply one operand permutation to the part where
48084 elements stay not in their respective lanes. */
48088 else
48100 else
48105 /* Next we put permuted elements into their positions. */
48109 else
48119 }
48123 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48124 a two vector permutation into a single vector permutation by using
48125 an interleave operation to merge the vectors. */
48127 static bool
48129 {
48138 {
48141 }
48143 {
48146 /* For 32-byte modes allow even d->one_operand_p.
48147 The lack of cross-lane shuffling in some instructions
48148 might prevent a single insn shuffle. */
48151 /* If expand_vec_perm_interleave3 can expand this into
48152 a 3 insn sequence, give up and let it be expanded as
48153 3 insn sequence. While that is one insn longer,
48154 it doesn't need a memory operand and in the common
48155 case that both interleave low and high permutations
48156 with the same operands are adjacent needs 4 insns
48157 for both after CSE. */
48160 }
48161 else
48164 /* Examine from whence the elements come. */
48173 {
48176 /* Split the two input vectors into 4 halves. */
48182 /* If the elements from the low halves use interleave low, and similarly
48183 for interleave high. If the elements are from mis-matched halves, we
48184 can use shufps for V4SF/V4SI or do a DImode shuffle. */
48186 {
48187 /* punpckl* */
48189 {
48194 }
48197 }
48199 {
48200 /* punpckh* */
48202 {
48207 }
48210 }
48212 {
48213 /* shufps */
48215 {
48220 }
48222 {
48223 /* shufpd */
48228 }
48229 }
48231 {
48232 /* shufps */
48234 {
48239 }
48241 {
48242 /* shufpd */
48247 }
48248 }
48249 else
48251 }
48252 else
48253 {
48258 /* Split the two input vectors into 8 quarters. */
48264 {
48267 }
48270 {
48274 }
48276 {
48279 }
48282 {
48284 {
48285 /* Attempt to increase the likelihood that dfinal
48286 shuffle will be intra-lane. */
48288 }
48290 /* vperm2f128 or vperm2i128. */
48292 {
48297 }
48302 {
48306 {
48309 }
48310 }
48311 }
48316 {
48317 /* vpunpckl* */
48319 {
48328 }
48329 }
48332 {
48333 /* vpunpckh* */
48335 {
48344 }
48345 }
48346 else
48348 }
48350 /* Use the remapping array set up above to move the elements from their
48351 swizzled locations into their final destinations. */
48354 {
48357 /* If same_halves is true, both halves of the remapped vector are the
48358 same. Avoid cross-lane accesses if possible. */
48360 {
48363 }
48364 else
48366 }
48368 {
48371 }
48375 /* Test if the final remap can be done with a single insn. For V4SFmode or
48376 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
48389 {
48392 }
48399 }
48401 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48402 a single vector cross-lane permutation into vpermq followed
48403 by any of the single insn permutations. */
48405 static bool
48407 {
48421 {
48424 }
48427 {
48432 }
48445 {
48452 }
48459 {
48464 ;
48467 else
48469 }
48478 }
48480 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
48481 a vector permutation using two instructions, vperm2f128 resp.
48482 vperm2i128 followed by any single in-lane permutation. */
48484 static bool
48486 {
48500 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
48501 immediate. For perm < 16 the second permutation uses
48502 d->op0 as first operand, for perm >= 16 it uses d->op1
48503 as first operand. The second operand is the result of
48504 vperm2[fi]128. */
48506 {
48507 /* Ignore permutations which do not move anything cross-lane. */
48509 {
48510 /* The second shuffle for e.g. V4DFmode has
48511 0123 and ABCD operands.
48512 Ignore AB23, as 23 is already in the second lane
48513 of the first operand. */
48515 /* And 01CD, as 01 is in the first lane of the first
48516 operand. */
48518 /* And 4567, as then the vperm2[fi]128 doesn't change
48519 anything on the original 4567 second operand. */
48521 }
48522 else
48523 {
48524 /* The second shuffle for e.g. V4DFmode has
48525 4567 and ABCD operands.
48526 Ignore AB67, as 67 is already in the second lane
48527 of the first operand. */
48529 /* And 45CD, as 45 is in the first lane of the first
48530 operand. */
48532 /* And 0123, as then the vperm2[fi]128 doesn't change
48533 anything on the original 0123 first operand. */
48535 }
48538 {
48544 else
48546 }
48549 {
48553 }
48554 else
48558 {
48562 /* Found a usable second shuffle. dfirst will be
48563 vperm2f128 on d->op0 and d->op1. */
48575 /* And dsecond is some single insn shuffle, taking
48576 d->op0 and result of vperm2f128 (if perm < 16) or
48577 d->op1 and result of vperm2f128 (otherwise). */
48586 }
48588 /* For one operand, the only useful vperm2f128 permutation is 0x01
48589 aka lanes swap. */
48592 }
48595 }
48597 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48598 a two vector permutation using 2 intra-lane interleave insns
48599 and cross-lane shuffle for 32-byte vectors. */
48601 static bool
48603 {
48610 ;
48612 ;
48613 else
48628 {
48632 else
48638 else
48644 else
48650 else
48656 else
48662 else
48667 }
48671 }
48673 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
48674 a single vector permutation using a single intra-lane vector
48675 permutation, vperm2f128 swapping the lanes and vblend* insn blending
48676 the non-swapped and swapped vectors together. */
48678 static bool
48680 {
48688 || TARGET_AVX2
48697 {
48704 }
48739 }
48741 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
48742 permutation using two vperm2f128, followed by a vshufpd insn blending
48743 the two vectors together. */
48745 static bool
48747 {
48790 }
48792 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
48793 permutation with two pshufb insns and an ior. We should have already
48794 failed all two instruction sequences. */
48796 static bool
48798 {
48812 /* Generate two permutation masks. If the required element is within
48813 the given vector it is shuffled into the proper lane. If the required
48814 element is in the other vector, force a zero into the lane by setting
48815 bit 7 in the permutation mask. */
48818 {
48825 {
48828 }
48829 }
48853 }
48855 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
48856 with two vpshufb insns, vpermq and vpor. We should have already failed
48857 all two or three instruction sequences. */
48859 static bool
48861 {
48876 /* Generate two permutation masks. If the required element is within
48877 the same lane, it is shuffled in. If the required element from the
48878 other lane, force a zero by setting bit 7 in the permutation mask.
48879 In the other mask the mask has non-negative elements if element
48880 is requested from the other lane, but also moved to the other lane,
48881 so that the result of vpshufb can have the two V2TImode halves
48882 swapped. */
48885 {
48890 {
48893 }
48894 }
48903 /* Swap the 128-byte lanes of h into hp. */
48907 const1_rtx));
48924 }
48926 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48927 and extract-odd permutations of two V32QImode and V16QImode operand
48928 with two vpshufb insns, vpor and vpermq. We should have already
48929 failed all two or three instruction sequences. */
48931 static bool
48933 {
48952 /* Generate two permutation masks. In the first permutation mask
48953 the first quarter will contain indexes for the first half
48954 of the op0, the second quarter will contain bit 7 set, third quarter
48955 will contain indexes for the second half of the op0 and the
48956 last quarter bit 7 set. In the second permutation mask
48957 the first quarter will contain bit 7 set, the second quarter
48958 indexes for the first half of the op1, the third quarter bit 7 set
48959 and last quarter indexes for the second half of the op1.
48960 I.e. the first mask e.g. for V32QImode extract even will be:
48961 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
48962 (all values masked with 0xf except for -128) and second mask
48963 for extract even will be
48964 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
48967 {
48973 {
48976 }
48977 }
48996 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
49004 }
49006 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
49007 and extract-odd permutations of two V16QI, V8HI, V16HI or V32QI operands
49008 with two "and" and "pack" or two "shift" and "pack" insns. We should
49009 have already failed all two instruction sequences. */
49011 static bool
49013 {
49017 machine_mode half_mode;
49026 {
49028 /* Required for "pack". */
49039 /* No check as all instructions are SSE2. */
49070 /* Only V8HI, V16QI, V16HI and V32QI modes are more profitable than
49071 general shuffles. */
49073 }
49075 /* Check that permutation is even or odd. */
49090 {
49097 }
49098 else
49099 {
49106 }
49107 /* In AVX2 for 256 bit case we need to permute pack result. */
49109 {
49115 const0_rtx,
49116 const2_rtx,
49117 const1_rtx,
49120 }
49121 else
49125 }
49127 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
49128 and extract-odd permutations. */
49130 static bool
49132 {
49136 {
49143 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
49147 /* Now an unpck[lh]pd will produce the result required. */
49150 else
49156 {
49165 /* Shuffle within the 128-bit lanes to produce:
49166 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
49170 /* Shuffle the lanes around to produce:
49171 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
49175 /* Shuffle within the 128-bit lanes to produce:
49176 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
49179 /* Shuffle within the 128-bit lanes to produce:
49180 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
49183 /* Shuffle the lanes around to produce:
49184 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
49187 }
49194 /* These are always directly implementable by expand_vec_perm_1. */
49202 else
49203 {
49206 /* We need 2*log2(N)-1 operations to achieve odd/even
49207 with interleave. */
49216 else
49219 }
49231 {
49236 else
49241 {
49246 }
49248 }
49256 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
49260 /* Now an vpunpck[lh]qdq will produce the result required. */
49263 else
49270 {
49275 else
49280 {
49285 }
49287 }
49298 /* Shuffle the lanes around into
49299 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
49307 /* Swap the 2nd and 3rd position in each lane into
49308 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
49314 /* Now an vpunpck[lh]qdq will produce
49315 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
49319 else
49328 }
49331 }
49333 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
49334 extract-even and extract-odd permutations. */
49336 static bool
49338 {
49350 }
49352 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
49353 permutations. We assume that expand_vec_perm_1 has already failed. */
49355 static bool
49357 {
49365 {
49368 /* These are special-cased in sse.md so that we can optionally
49369 use the vbroadcast instruction. They expand to two insns
49370 if the input happens to be in a register. */
49377 /* These are always implementable using standard shuffle patterns. */
49382 /* These can be implemented via interleave. We save one insn by
49383 stopping once we have promoted to V4SImode and then use pshufd. */
49386 do
49387 {
49388 rtx dest;
49394 {
49398 }
49405 }
49421 /* For AVX2 broadcasts of the first element vpbroadcast* or
49422 vpermq should be used by expand_vec_perm_1. */
49428 }
49429 }
49431 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
49432 broadcast permutations. */
49434 static bool
49436 {
49448 }
49450 /* Implement arbitrary permutations of two V64QImode operands
49451 will 2 vpermi2w, 2 vpshufb and one vpor instruction. */
49452 static bool
49454 {
49464 machine_mode vmode;
49470 {
49477 }
49479 /* Prepare permutations such that the first one takes care of
49480 putting the even bytes into the right positions or one higher
49481 positions (ds[0]) and the second one takes care of
49482 putting the odd bytes into the right positions or one below
49483 (ds[1]). */
49486 {
49489 {
49492 }
49493 else
49494 {
49497 }
49498 }
49520 }
49522 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
49523 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
49524 all the shorter instruction sequences. */
49526 static bool
49528 {
49544 /* Generate 4 permutation masks. If the required element is within
49545 the same lane, it is shuffled in. If the required element from the
49546 other lane, force a zero by setting bit 7 in the permutation mask.
49547 In the other mask the mask has non-negative elements if element
49548 is requested from the other lane, but also moved to the other lane,
49549 so that the result of vpshufb can have the two V2TImode halves
49550 swapped. */
49553 {
49558 }
49564 {
49572 }
49575 {
49577 {
49580 }
49587 }
49589 /* Swap the 128-byte lanes of h[X]. */
49591 {
49597 const1_rtx));
49599 }
49602 {
49604 {
49607 }
49613 }
49616 {
49618 {
49622 }
49625 }
49635 }
49637 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
49638 With all of the interface bits taken care of, perform the expansion
49639 in D and return true on success. */
49641 static bool
49643 {
49644 /* Try a single instruction expansion. */
49648 /* Try sequences of two instructions. */
49671 /* Try sequences of three instructions. */
49688 /* Try sequences of four instructions. */
49699 /* ??? Look for narrow permutations whose element orderings would
49700 allow the promotion to a wider mode. */
49702 /* ??? Look for sequences of interleave or a wider permute that place
49703 the data into the correct lanes for a half-vector shuffle like
49704 pshuf[lh]w or vpermilps. */
49706 /* ??? Look for sequences of interleave that produce the desired results.
49707 The combinatorics of punpck[lh] get pretty ugly... */
49712 /* Even longer sequences. */
49717 }
49719 /* If a permutation only uses one operand, make it clear. Returns true
49720 if the permutation references both operands. */
49722 static bool
49724 {
49732 {
49738 {
49741 }
49742 /* The elements of PERM do not suggest that only the first operand
49743 is used, but both operands are identical. Allow easier matching
49744 of the permutation by folding the permutation into the single
49745 input vector. */
49746 /* FALLTHRU */
49757 }
49760 }
49762 bool
49764 {
49769 rtx sel;
49786 {
49791 }
49798 /* If the selector says both arguments are needed, but the operands are the
49799 same, the above tried to expand with one_operand_p and flattened selector.
49800 If that didn't work, retry without one_operand_p; we succeeded with that
49801 during testing. */
49803 {
49807 }
49810 }
49812 /* Implement targetm.vectorize.vec_perm_const_ok. */
49814 static bool
49817 {
49826 /* Given sufficient ISA support we can just return true here
49827 for selected vector modes. */
49829 {
49835 /* All implementable with a single vpermi2 insn. */
49840 /* All implementable with a single vpermi2 insn. */
49845 /* Implementable with 2 vpermi2, 2 vpshufb and 1 or insn. */
49853 /* All implementable with a single vpermi2 insn. */
49858 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49863 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49870 /* All implementable with a single vpperm insn. */
49873 /* All implementable with 2 pshufb + 1 ior. */
49879 /* All implementable with shufpd or unpck[lh]pd. */
49883 }
49885 /* Extract the values from the vector CST into the permutation
49886 array in D. */
49889 {
49893 }
49895 /* For all elements from second vector, fold the elements to first. */
49900 /* Check whether the mask can be applied to the vector type. */
49903 /* Implementable with shufps or pshufd. */
49907 /* Otherwise we have to go through the motions and see if we can
49908 figure out how to generate the requested permutation. */
49919 }
49921 void
49923 {
49938 /* We'll either be able to implement the permutation directly... */
49942 /* ... or we use the special-case patterns. */
49944 }
49946 static void
49948 {
49963 {
49966 }
49968 /* Note that for AVX this isn't one instruction. */
49971 }
49974 /* Expand a vector operation CODE for a V*QImode in terms of the
49975 same operation on V*HImode. */
49977 void
49979 {
49981 machine_mode himode;
49991 {
50009 }
50013 {
50015 /* Unpack data such that we've got a source byte in each low byte of
50016 each word. We don't care what goes into the high byte of each word.
50017 Rather than trying to get zero in there, most convenient is to let
50018 it be a copy of the low byte. */
50023 /* FALLTHRU */
50035 /* FALLTHRU */
50045 }
50047 /* Perform the operation. */
50054 /* Merge the data back into the right place. */
50064 {
50065 /* For SSE2, we used an full interleave, so the desired
50066 results are in the even elements. */
50069 }
50070 else
50071 {
50072 /* For AVX, the interleave used above was not cross-lane. So the
50073 extraction is evens but with the second and third quarter swapped.
50074 Happily, that is even one insn shorter than even extraction. */
50077 }
50084 }
50086 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
50087 if op is CONST_VECTOR with all odd elements equal to their
50088 preceding element. */
50090 static bool
50092 {
50102 }
50104 void
50107 {
50110 rtx x;
50118 /* We only play even/odd games with vectors of SImode. */
50121 /* If we're looking for the odd results, shift those members down to
50122 the even slots. For some cpus this is faster than a PSHUFD. */
50124 {
50125 /* For XOP use vpmacsdqh, but only for smult, as it is only
50126 signed. */
50128 {
50132 }
50143 }
50146 {
50149 else
50151 }
50153 {
50156 else
50158 }
50163 else
50164 {
50167 /* The easiest way to implement this without PMULDQ is to go through
50168 the motions as if we are performing a full 64-bit multiply. With
50169 the exception that we need to do less shuffling of the elements. */
50171 /* Compute the sign-extension, aka highparts, of the two operands. */
50177 /* Multiply LO(A) * HI(B), and vice-versa. */
50183 /* Multiply LO(A) * LO(B). */
50187 /* Combine and shift the highparts into place. */
50192 /* Combine high and low parts. */
50195 }
50197 }
50199 void
50202 {
50208 {
50213 {
50214 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
50215 shuffle the elements once so that all elements are in the right
50216 place for immediate use: { A C B D }. */
50221 }
50222 else
50223 {
50224 /* Put the elements into place for the multiply. */
50228 }
50233 /* Shuffle the elements between the lanes. After this we
50234 have { A B E F | C D G H } for each operand. */
50244 /* Shuffle the elements within the lanes. After this we
50245 have { A A B B | C C D D } or { E E F F | G G H H }. */
50286 }
50287 }
50289 void
50291 {
50301 /* Move the results in element 2 down to element 1; we don't care
50302 what goes in elements 2 and 3. Then we can merge the parts
50303 back together with an interleave.
50305 Note that two other sequences were tried:
50306 (1) Use interleaves at the start instead of psrldq, which allows
50307 us to use a single shufps to merge things back at the end.
50308 (2) Use shufps here to combine the two vectors, then pshufd to
50309 put the elements in the correct order.
50310 In both cases the cost of the reformatting stall was too high
50311 and the overall sequence slower. */
50322 }
50324 void
50326 {
50337 {
50338 /* op1: A,B,C,D, op2: E,F,G,H */
50347 /* t1: B,A,D,C */
50354 /* t2: (B*E),(A*F),(D*G),(C*H) */
50357 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
50360 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
50363 /* Multiply lower parts and add all */
50370 }
50371 else
50372 {
50373 machine_mode nmode;
50377 {
50380 }
50382 {
50385 }
50387 {
50390 }
50391 else
50395 /* Multiply low parts. */
50399 /* Shift input vectors right 32 bits so we can multiply high parts. */
50404 /* Multiply high parts by low parts. */
50410 /* Combine and shift the highparts back. */
50414 /* Combine high and low parts. */
50416 }
50420 }
50422 /* Return 1 if control tansfer instruction INSN
50423 should be encoded with bnd prefix.
50424 If insn is NULL then return 1 when control
50425 transfer instructions should be prefixed with
50426 bnd by default for current function. */
50428 bool
50430 {
50431 /* For call insns check special flag. */
50433 {
50437 }
50439 /* All other insns are prefixed only if function is instrumented. */
50441 }
50443 /* Calculate integer abs() using only SSE2 instructions. */
50445 void
50447 {
50452 {
50453 /* For 32-bit signed integer X, the best way to calculate the absolute
50454 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
50466 /* For 16-bit signed integer X, the best way to calculate the absolute
50467 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
50475 /* For 8-bit signed integer X, the best way to calculate the absolute
50476 value of X is min ((unsigned char) X, (unsigned char) (-X)),
50477 as SSE2 provides the PMINUB insn. */
50487 }
50491 }
50493 /* Expand an insert into a vector register through pinsr insn.
50494 Return true if successful. */
50496 bool
50498 {
50506 {
50509 }
50515 {
50520 {
50527 {
50559 }
50573 }
50577 }
50578 }
50579 \f
50580 /* This function returns the calling abi specific va_list type node.
50581 It returns the FNDECL specific va_list type. */
50583 static tree
50585 {
50592 else
50594 }
50596 /* Returns the canonical va_list type specified by TYPE. If there
50597 is no valid TYPE provided, it return NULL_TREE. */
50599 static tree
50601 {
50604 /* Resolve references and pointers to va_list type. */
50613 {
50618 {
50619 /* If va_list is an array type, the argument may have decayed
50620 to a pointer type, e.g. by being passed to another function.
50621 In that case, unwrap both types so that we can compare the
50622 underlying records. */
50625 {
50628 }
50629 }
50636 {
50637 /* If va_list is an array type, the argument may have decayed
50638 to a pointer type, e.g. by being passed to another function.
50639 In that case, unwrap both types so that we can compare the
50640 underlying records. */
50643 {
50646 }
50647 }
50654 {
50655 /* If va_list is an array type, the argument may have decayed
50656 to a pointer type, e.g. by being passed to another function.
50657 In that case, unwrap both types so that we can compare the
50658 underlying records. */
50661 {
50664 }
50665 }
50669 }
50671 }
50673 /* Iterate through the target-specific builtin types for va_list.
50674 IDX denotes the iterator, *PTREE is set to the result type of
50675 the va_list builtin, and *PNAME to its internal type.
50676 Returns zero if there is no element for this index, otherwise
50677 IDX should be increased upon the next call.
50678 Note, do not iterate a base builtin's name like __builtin_va_list.
50679 Used from c_common_nodes_and_builtins. */
50681 static int
50683 {
50685 {
50687 {
50700 }
50701 }
50704 }
50706 #undef TARGET_SCHED_DISPATCH
50707 #define TARGET_SCHED_DISPATCH has_dispatch
50708 #undef TARGET_SCHED_DISPATCH_DO
50709 #define TARGET_SCHED_DISPATCH_DO do_dispatch
50710 #undef TARGET_SCHED_REASSOCIATION_WIDTH
50711 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
50712 #undef TARGET_SCHED_REORDER
50713 #define TARGET_SCHED_REORDER ix86_sched_reorder
50714 #undef TARGET_SCHED_ADJUST_PRIORITY
50715 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
50716 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
50717 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
50718 ix86_dependencies_evaluation_hook
50720 /* The size of the dispatch window is the total number of bytes of
50721 object code allowed in a window. */
50722 #define DISPATCH_WINDOW_SIZE 16
50724 /* Number of dispatch windows considered for scheduling. */
50725 #define MAX_DISPATCH_WINDOWS 3
50727 /* Maximum number of instructions in a window. */
50728 #define MAX_INSN 4
50730 /* Maximum number of immediate operands in a window. */
50731 #define MAX_IMM 4
50733 /* Maximum number of immediate bits allowed in a window. */
50734 #define MAX_IMM_SIZE 128
50736 /* Maximum number of 32 bit immediates allowed in a window. */
50737 #define MAX_IMM_32 4
50739 /* Maximum number of 64 bit immediates allowed in a window. */
50740 #define MAX_IMM_64 2
50742 /* Maximum total of loads or prefetches allowed in a window. */
50743 #define MAX_LOAD 2
50745 /* Maximum total of stores allowed in a window. */
50746 #define MAX_STORE 1
50748 #undef BIG
50749 #define BIG 100
50752 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
50755 disp_load,
50756 disp_store,
50757 disp_load_store,
50758 disp_prefetch,
50759 disp_imm,
50760 disp_imm_32,
50761 disp_imm_64,
50762 disp_branch,
50763 disp_cmp,
50764 disp_jcc,
50765 disp_last
50766 };
50768 /* Number of allowable groups in a dispatch window. It is an array
50769 indexed by dispatch_group enum. 100 is used as a big number,
50770 because the number of these kind of operations does not have any
50771 effect in dispatch window, but we need them for other reasons in
50772 the table. */
50775 };
50781 };
50783 /* Instruction path. */
50789 last_path
50790 };
50792 /* sched_insn_info defines a window to the instructions scheduled in
50793 the basic block. It contains a pointer to the insn_info table and
50794 the instruction scheduled.
50796 Windows are allocated for each basic block and are linked
50797 together. */
50799 rtx insn;
50806 /* Linked list of dispatch windows. This is a two way list of
50807 dispatch windows of a basic block. It contains information about
50808 the number of uops in the window and the total number of
50809 instructions and of bytes in the object code for this dispatch
50810 window. */
50828 /* Immediate valuse used in an insn. */
50830 {
50839 /* Get dispatch group of insn. */
50841 static enum dispatch_group
50843 {
50859 }
50861 /* Return true if insn is a compare instruction. */
50863 static bool
50865 {
50873 }
50875 /* Return true if a dispatch violation encountered. */
50877 static bool
50879 {
50883 }
50885 /* Return true if insn is a branch instruction. */
50887 static bool
50889 {
50891 }
50893 /* Return true if insn is a prefetch instruction. */
50895 static bool
50897 {
50899 }
50901 /* This function initializes a dispatch window and the list container holding a
50902 pointer to the window. */
50904 static void
50906 {
50912 else
50930 {
50936 }
50938 }
50940 /* This function allocates and initializes a dispatch window and the
50941 list container holding a pointer to the window. */
50945 {
50950 }
50952 /* This routine initializes the dispatch scheduling information. It
50953 initiates building dispatch scheduler tables and constructs the
50954 first dispatch window. */
50956 static void
50958 {
50959 /* Allocate a dispatch list and a window. */
50964 }
50966 /* This function returns true if a branch is detected. End of a basic block
50967 does not have to be a branch, but here we assume only branches end a
50968 window. */
50970 static bool
50972 {
50974 }
50976 /* This function is called when the end of a window processing is reached. */
50978 static void
50980 {
50983 {
50988 }
50990 }
50992 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
50993 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
50994 for 48 bytes of instructions. Note that these windows are not dispatch
50995 windows that their sizes are DISPATCH_WINDOW_SIZE. */
50999 {
51001 {
51006 }
51012 }
51014 /* Compute number of immediate operands of an instruction. */
51016 static void
51018 {
51025 {
51032 else
51044 {
51047 }
51052 }
51053 }
51055 /* Return total size of immediate operands of an instruction along with number
51056 of corresponding immediate-operands. It initializes its parameters to zero
51057 befor calling FIND_CONSTANT.
51058 INSN is the input instruction. IMM is the total of immediates.
51059 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
51060 bit immediates. */
51062 static int
51064 {
51072 }
51074 /* This function indicates if an operand of an instruction is an
51075 immediate. */
51077 static bool
51079 {
51088 }
51090 /* Return single or double path for instructions. */
51092 static enum insn_path
51094 {
51104 }
51106 /* Return insn dispatch group. */
51108 static enum dispatch_group
51110 {
51128 }
51130 /* Count number of GROUP restricted instructions in a dispatch
51131 window WINDOW_LIST. */
51133 static int
51135 {
51146 {
51165 }
51178 }
51180 /* This function returns true if insn satisfies dispatch rules on the
51181 last window scheduled. */
51183 static bool
51185 {
51193 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
51194 instructions should be given the lowest priority in the
51195 scheduling process in Haifa scheduler to make sure they will be
51196 scheduled in the same dispatch window as the reference to them. */
51200 /* Check nonrestricted. */
51204 /* Get last dispatch window. */
51209 {
51214 /* Window 1 is full. Go for next window. */
51216 }
51223 /* See if it fits in the first window. */
51225 {
51226 /* The first widow should have only single and double path
51227 uops. */
51233 }
51235 }
51237 /* Add an instruction INSN with NUM_UOPS micro-operations to the
51238 dispatch window WINDOW_LIST. */
51240 static void
51242 {
51260 /* Initialize window with new instruction. */
51281 {
51284 }
51285 }
51287 /* Adds a scheduled instruction, INSN, to the current dispatch window.
51288 If the total bytes of instructions or the number of instructions in
51289 the window exceed allowable, it allocates a new window. */
51291 static void
51293 {
51316 /* Get the last dispatch window. */
51324 else
51327 /* If current window is full, get a new window.
51328 Window number zero is full, if MAX_INSN uops are scheduled in it.
51329 Window number one is full, if window zero's bytes plus window
51330 one's bytes is 32, or if the bytes of the new instruction added
51331 to the total makes it greater than 48, or it has already MAX_INSN
51332 instructions in it. */
51341 {
51344 }
51347 {
51351 {
51354 }
51355 }
51357 {
51362 {
51365 }
51368 }
51369 else
51373 {
51374 /* End of basic block is reached do end-basic-block process. */
51377 }
51378 }
51380 /* Print the dispatch window, WINDOW_NUM, to FILE. */
51382 DEBUG_FUNCTION static void
51384 {
51390 else
51404 {
51407 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
51413 }
51414 }
51416 /* Print to stdout a dispatch window. */
51418 DEBUG_FUNCTION void
51420 {
51422 }
51424 /* Print INSN dispatch information to FILE. */
51426 DEBUG_FUNCTION static void
51428 {
51451 }
51453 /* Print to STDERR the status of the ready list with respect to
51454 dispatch windows. */
51456 DEBUG_FUNCTION void
51458 {
51466 }
51468 /* This routine is the driver of the dispatch scheduler. */
51470 static void
51472 {
51477 }
51479 /* Return TRUE if Dispatch Scheduling is supported. */
51481 static bool
51483 {
51487 {
51503 }
51506 }
51508 /* Implementation of reassociation_width target hook used by
51509 reassoc phase to identify parallelism level in reassociated
51510 tree. Statements tree_code is passed in OPC. Arguments type
51511 is passed in MODE.
51513 Currently parallel reassociation is enabled for Atom
51514 processors only and we set reassociation width to be 2
51515 because Atom may issue up to 2 instructions per cycle.
51517 Return value should be fixed if parallel reassociation is
51518 enabled for other processors. */
51520 static int
51522 {
51523 /* Vector part. */
51525 {
51528 else
51530 }
51532 /* Scalar part. */
51537 else
51539 }
51541 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
51542 place emms and femms instructions. */
51544 static machine_mode
51546 {
51551 {
51570 else
51582 /* FALLTHRU */
51586 }
51587 }
51589 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
51590 vectors. If AVX512F is enabled then try vectorizing with 512bit,
51591 256bit and 128bit vectors. */
51593 static unsigned int
51595 {
51598 }
51600 \f
51602 /* Return class of registers which could be used for pseudo of MODE
51603 and of class RCLASS for spilling instead of memory. Return NO_REGS
51604 if it is not possible or non-profitable. */
51605 static reg_class_t
51607 {
51613 }
51615 /* Implement targetm.vectorize.init_cost. */
51619 {
51623 }
51625 /* Implement targetm.vectorize.add_stmt_cost. */
51627 static unsigned
51631 {
51638 /* Statements in an inner loop relative to the loop being
51639 vectorized are weighted more heavily. The value here is
51640 arbitrary and could potentially be improved with analysis. */
51646 /* We need to multiply all vector stmt cost by 1.7 (estimated cost)
51647 for Silvermont as it has out of order integer pipeline and can execute
51648 2 scalar instruction per tick, but has in order SIMD pipeline. */
51651 {
51655 }
51660 }
51662 /* Implement targetm.vectorize.finish_cost. */
51664 static void
51667 {
51672 }
51674 /* Implement targetm.vectorize.destroy_cost_data. */
51676 static void
51678 {
51680 }
51682 /* Validate target specific memory model bits in VAL. */
51684 static unsigned HOST_WIDE_INT
51686 {
51693 {
51697 }
51700 {
51704 }
51706 {
51710 }
51712 }
51714 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
51715 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
51716 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
51717 or number of vecsize_mangle variants that should be emitted. */
51719 static int
51723 {
51730 {
51734 }
51739 {
51746 /* case SCmode: */
51747 /* case DCmode: */
51753 }
51755 tree t;
51759 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
51761 {
51768 /* case SCmode: */
51769 /* case DCmode: */
51775 }
51778 {
51779 /* Parse here processor clause. If not present, default to 'b'. */
51781 }
51783 {
51784 /* If the function isn't exported, we can pick up just one ISA
51785 for the clones. */
51790 else
51793 }
51794 else
51795 {
51798 }
51800 {
51813 }
51815 {
51818 else
51823 }
51825 }
51827 /* Add target attribute to SIMD clone NODE if needed. */
51829 static void
51831 {
51835 {
51850 }
51860 }
51862 /* If SIMD clone NODE can't be used in a vectorized loop
51863 in current function, return -1, otherwise return a badness of using it
51864 (0 if it is most desirable from vecsize_mangle point of view, 1
51865 slightly less desirable, etc.). */
51867 static int
51869 {
51871 {
51889 }
51890 }
51892 /* This function adjusts the unroll factor based on
51893 the hardware capabilities. For ex, bdver3 has
51894 a loop buffer which makes unrolling of smaller
51895 loops less important. This function decides the
51896 unroll factor using number of memory references
51897 (value 32 is used) as a heuristic. */
51899 static unsigned
51901 {
51910 /* Count the number of memory references within the loop body.
51911 This value determines the unrolling factor for bdver3 and bdver4
51912 architectures. */
51921 {
51926 else
51928 }
51935 }
51938 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
51940 static bool
51942 {
51943 /* For x87 floating point with standard excess precision handling,
51944 there is no adddf3 pattern (since x87 floating point only has
51945 XFmode operations) so the default hook implementation gets this
51946 wrong. */
51948 }
51950 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
51952 static void
51954 {
51959 {
51974 hold_fnclex);
51987 }
51989 {
51998 mxcsr_orig_var,
52008 ldmxcsr_hold_call);
52011 else
52016 ldmxcsr_clear_call);
52017 else
52021 stxmcsr_update_call);
52023 {
52029 exceptions_assign);
52030 }
52031 else
52036 ldmxcsr_update_call);
52037 }
52038 tree atomic_feraiseexcept
52043 atomic_feraiseexcept_call);
52044 }
52046 /* Return mode to be used for bounds or VOIDmode
52047 if bounds are not supported. */
52049 static enum machine_mode
52051 {
52052 /* Do not support pointer checker if MPX
52053 is not enabled. */
52055 {
52060 }
52063 }
52065 /* Return constant used to statically initialize constant bounds.
52067 This function is used to create special bound values. For now
52068 only INIT bounds and NONE bounds are expected. More special
52069 values may be added later. */
52071 static tree
52073 {
52079 /* This function is supposed to be used to create INIT and
52080 NONE bounds only. */
52085 }
52087 /* Generate a list of statements STMTS to initialize pointer bounds
52088 variable VAR with bounds LB and UB. Return the number of generated
52089 statements. */
52091 static int
52093 {
52111 }
52113 #if !TARGET_MACHO && !TARGET_DLLIMPORT_DECL_ATTRIBUTES
52114 /* For i386, common symbol is local only for non-PIE binaries. For
52115 x86-64, common symbol is local only for non-PIE binaries or linker
52116 supports copy reloc in PIE binaries. */
52118 static bool
52120 {
52122 (!flag_pic
52123 || (TARGET_64BIT
52125 }
52126 #endif
52128 /* If MEM is in the form of [base+offset], extract the two parts
52129 of address and set to BASE and OFFSET, otherwise return false. */
52131 static bool
52133 {
52134 rtx addr;
52144 {
52148 }
52154 {
52158 }
52161 }
52163 /* Given OPERANDS of consecutive load/store, check if we can merge
52164 them into move multiple. LOAD is true if they are load instructions.
52165 MODE is the mode of memory operands. */
52167 bool
52170 {
52175 {
52180 }
52181 else
52182 {
52187 }
52194 /* Check if the addresses are in the form of [base+offset]. */
52200 /* Check if the bases are the same. */
52207 /* Check if mem_1 is adjacent to mem_2 and mem_1 has lower address. */
52212 }
52214 /* Initialize the GCC target structure. */
52215 #undef TARGET_RETURN_IN_MEMORY
52216 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
52218 #undef TARGET_LEGITIMIZE_ADDRESS
52219 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
52221 #undef TARGET_ATTRIBUTE_TABLE
52222 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
52223 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
52224 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
52225 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
52226 # undef TARGET_MERGE_DECL_ATTRIBUTES
52227 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
52228 #endif
52230 #undef TARGET_COMP_TYPE_ATTRIBUTES
52231 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
52233 #undef TARGET_INIT_BUILTINS
52234 #define TARGET_INIT_BUILTINS ix86_init_builtins
52235 #undef TARGET_BUILTIN_DECL
52236 #define TARGET_BUILTIN_DECL ix86_builtin_decl
52237 #undef TARGET_EXPAND_BUILTIN
52238 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
52240 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
52241 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
52242 ix86_builtin_vectorized_function
52244 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
52245 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
52247 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
52248 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
52250 #undef TARGET_VECTORIZE_BUILTIN_GATHER
52251 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
52253 #undef TARGET_BUILTIN_RECIPROCAL
52254 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
52256 #undef TARGET_ASM_FUNCTION_EPILOGUE
52257 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
52259 #undef TARGET_ENCODE_SECTION_INFO
52260 #ifndef SUBTARGET_ENCODE_SECTION_INFO
52261 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
52262 #else
52263 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
52264 #endif
52266 #undef TARGET_ASM_OPEN_PAREN
52268 #undef TARGET_ASM_CLOSE_PAREN
52271 #undef TARGET_ASM_BYTE_OP
52272 #define TARGET_ASM_BYTE_OP ASM_BYTE
52274 #undef TARGET_ASM_ALIGNED_HI_OP
52275 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
52276 #undef TARGET_ASM_ALIGNED_SI_OP
52277 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
52278 #ifdef ASM_QUAD
52279 #undef TARGET_ASM_ALIGNED_DI_OP
52280 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
52281 #endif
52283 #undef TARGET_PROFILE_BEFORE_PROLOGUE
52284 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
52286 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
52287 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
52289 #undef TARGET_ASM_UNALIGNED_HI_OP
52290 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
52291 #undef TARGET_ASM_UNALIGNED_SI_OP
52292 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
52293 #undef TARGET_ASM_UNALIGNED_DI_OP
52294 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
52296 #undef TARGET_PRINT_OPERAND
52297 #define TARGET_PRINT_OPERAND ix86_print_operand
52298 #undef TARGET_PRINT_OPERAND_ADDRESS
52299 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
52300 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
52301 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
52302 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
52303 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
52305 #undef TARGET_SCHED_INIT_GLOBAL
52306 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
52307 #undef TARGET_SCHED_ADJUST_COST
52308 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
52309 #undef TARGET_SCHED_ISSUE_RATE
52310 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
52311 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
52312 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
52313 ia32_multipass_dfa_lookahead
52314 #undef TARGET_SCHED_MACRO_FUSION_P
52315 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
52316 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
52317 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
52319 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
52320 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
52322 #undef TARGET_MEMMODEL_CHECK
52323 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
52325 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
52326 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
52328 #ifdef HAVE_AS_TLS
52329 #undef TARGET_HAVE_TLS
52330 #define TARGET_HAVE_TLS true
52331 #endif
52332 #undef TARGET_CANNOT_FORCE_CONST_MEM
52333 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
52334 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
52335 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
52337 #undef TARGET_DELEGITIMIZE_ADDRESS
52338 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
52340 #undef TARGET_MS_BITFIELD_LAYOUT_P
52341 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
52343 #if TARGET_MACHO
52344 #undef TARGET_BINDS_LOCAL_P
52345 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
52346 #else
52347 #undef TARGET_BINDS_LOCAL_P
52348 #define TARGET_BINDS_LOCAL_P ix86_binds_local_p
52349 #endif
52350 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
52351 #undef TARGET_BINDS_LOCAL_P
52352 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
52353 #endif
52355 #undef TARGET_ASM_OUTPUT_MI_THUNK
52356 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
52357 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
52358 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
52360 #undef TARGET_ASM_FILE_START
52361 #define TARGET_ASM_FILE_START x86_file_start
52363 #undef TARGET_OPTION_OVERRIDE
52364 #define TARGET_OPTION_OVERRIDE ix86_option_override
52366 #undef TARGET_REGISTER_MOVE_COST
52367 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
52368 #undef TARGET_MEMORY_MOVE_COST
52369 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
52370 #undef TARGET_RTX_COSTS
52371 #define TARGET_RTX_COSTS ix86_rtx_costs
52372 #undef TARGET_ADDRESS_COST
52373 #define TARGET_ADDRESS_COST ix86_address_cost
52375 #undef TARGET_FIXED_CONDITION_CODE_REGS
52376 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
52377 #undef TARGET_CC_MODES_COMPATIBLE
52378 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
52380 #undef TARGET_MACHINE_DEPENDENT_REORG
52381 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
52383 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
52384 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
52386 #undef TARGET_BUILD_BUILTIN_VA_LIST
52387 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
52389 #undef TARGET_FOLD_BUILTIN
52390 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
52392 #undef TARGET_COMPARE_VERSION_PRIORITY
52393 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
52395 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
52396 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
52397 ix86_generate_version_dispatcher_body
52399 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
52400 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
52401 ix86_get_function_versions_dispatcher
52403 #undef TARGET_ENUM_VA_LIST_P
52404 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
52406 #undef TARGET_FN_ABI_VA_LIST
52407 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
52409 #undef TARGET_CANONICAL_VA_LIST_TYPE
52410 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
52412 #undef TARGET_EXPAND_BUILTIN_VA_START
52413 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
52415 #undef TARGET_MD_ASM_ADJUST
52416 #define TARGET_MD_ASM_ADJUST ix86_md_asm_adjust
52418 #undef TARGET_PROMOTE_PROTOTYPES
52419 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
52420 #undef TARGET_SETUP_INCOMING_VARARGS
52421 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
52422 #undef TARGET_MUST_PASS_IN_STACK
52423 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
52424 #undef TARGET_FUNCTION_ARG_ADVANCE
52425 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
52426 #undef TARGET_FUNCTION_ARG
52427 #define TARGET_FUNCTION_ARG ix86_function_arg
52428 #undef TARGET_INIT_PIC_REG
52429 #define TARGET_INIT_PIC_REG ix86_init_pic_reg
52430 #undef TARGET_USE_PSEUDO_PIC_REG
52431 #define TARGET_USE_PSEUDO_PIC_REG ix86_use_pseudo_pic_reg
52432 #undef TARGET_FUNCTION_ARG_BOUNDARY
52433 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
52434 #undef TARGET_PASS_BY_REFERENCE
52435 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
52436 #undef TARGET_INTERNAL_ARG_POINTER
52437 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
52438 #undef TARGET_UPDATE_STACK_BOUNDARY
52439 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
52440 #undef TARGET_GET_DRAP_RTX
52441 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
52442 #undef TARGET_STRICT_ARGUMENT_NAMING
52443 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
52444 #undef TARGET_STATIC_CHAIN
52445 #define TARGET_STATIC_CHAIN ix86_static_chain
52446 #undef TARGET_TRAMPOLINE_INIT
52447 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
52448 #undef TARGET_RETURN_POPS_ARGS
52449 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
52451 #undef TARGET_LEGITIMATE_COMBINED_INSN
52452 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
52454 #undef TARGET_ASAN_SHADOW_OFFSET
52455 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
52457 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
52458 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
52460 #undef TARGET_SCALAR_MODE_SUPPORTED_P
52461 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
52463 #undef TARGET_VECTOR_MODE_SUPPORTED_P
52464 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
52466 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
52467 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
52468 ix86_libgcc_floating_mode_supported_p
52470 #undef TARGET_C_MODE_FOR_SUFFIX
52471 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
52473 #ifdef HAVE_AS_TLS
52474 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
52475 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
52476 #endif
52478 #ifdef SUBTARGET_INSERT_ATTRIBUTES
52479 #undef TARGET_INSERT_ATTRIBUTES
52480 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
52481 #endif
52483 #undef TARGET_MANGLE_TYPE
52484 #define TARGET_MANGLE_TYPE ix86_mangle_type
52486 #if !TARGET_MACHO
52487 #undef TARGET_STACK_PROTECT_FAIL
52488 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
52489 #endif
52491 #undef TARGET_FUNCTION_VALUE
52492 #define TARGET_FUNCTION_VALUE ix86_function_value
52494 #undef TARGET_FUNCTION_VALUE_REGNO_P
52495 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
52497 #undef TARGET_PROMOTE_FUNCTION_MODE
52498 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
52500 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
52501 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ix86_override_options_after_change
52503 #undef TARGET_MEMBER_TYPE_FORCES_BLK
52504 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
52506 #undef TARGET_INSTANTIATE_DECLS
52507 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
52509 #undef TARGET_SECONDARY_RELOAD
52510 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
52512 #undef TARGET_CLASS_MAX_NREGS
52513 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
52515 #undef TARGET_PREFERRED_RELOAD_CLASS
52516 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
52517 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
52518 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
52519 #undef TARGET_CLASS_LIKELY_SPILLED_P
52520 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
52522 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
52523 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
52524 ix86_builtin_vectorization_cost
52525 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
52526 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
52527 ix86_vectorize_vec_perm_const_ok
52528 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
52529 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
52530 ix86_preferred_simd_mode
52531 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
52532 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
52533 ix86_autovectorize_vector_sizes
52534 #undef TARGET_VECTORIZE_INIT_COST
52535 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
52536 #undef TARGET_VECTORIZE_ADD_STMT_COST
52537 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
52538 #undef TARGET_VECTORIZE_FINISH_COST
52539 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
52540 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
52541 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
52543 #undef TARGET_SET_CURRENT_FUNCTION
52544 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
52546 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
52547 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
52549 #undef TARGET_OPTION_SAVE
52550 #define TARGET_OPTION_SAVE ix86_function_specific_save
52552 #undef TARGET_OPTION_RESTORE
52553 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
52555 #undef TARGET_OPTION_POST_STREAM_IN
52556 #define TARGET_OPTION_POST_STREAM_IN ix86_function_specific_post_stream_in
52558 #undef TARGET_OPTION_PRINT
52559 #define TARGET_OPTION_PRINT ix86_function_specific_print
52561 #undef TARGET_OPTION_FUNCTION_VERSIONS
52562 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
52564 #undef TARGET_CAN_INLINE_P
52565 #define TARGET_CAN_INLINE_P ix86_can_inline_p
52567 #undef TARGET_EXPAND_TO_RTL_HOOK
52568 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
52570 #undef TARGET_LEGITIMATE_ADDRESS_P
52571 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
52573 #undef TARGET_LRA_P
52574 #define TARGET_LRA_P hook_bool_void_true
52576 #undef TARGET_REGISTER_PRIORITY
52577 #define TARGET_REGISTER_PRIORITY ix86_register_priority
52579 #undef TARGET_REGISTER_USAGE_LEVELING_P
52580 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
52582 #undef TARGET_LEGITIMATE_CONSTANT_P
52583 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
52585 #undef TARGET_FRAME_POINTER_REQUIRED
52586 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
52588 #undef TARGET_CAN_ELIMINATE
52589 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
52591 #undef TARGET_EXTRA_LIVE_ON_ENTRY
52592 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
52594 #undef TARGET_ASM_CODE_END
52595 #define TARGET_ASM_CODE_END ix86_code_end
52597 #undef TARGET_CONDITIONAL_REGISTER_USAGE
52598 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
52600 #if TARGET_MACHO
52601 #undef TARGET_INIT_LIBFUNCS
52602 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
52603 #endif
52605 #undef TARGET_LOOP_UNROLL_ADJUST
52606 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
52608 #undef TARGET_SPILL_CLASS
52609 #define TARGET_SPILL_CLASS ix86_spill_class
52611 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
52612 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
52613 ix86_simd_clone_compute_vecsize_and_simdlen
52615 #undef TARGET_SIMD_CLONE_ADJUST
52616 #define TARGET_SIMD_CLONE_ADJUST \
52617 ix86_simd_clone_adjust
52619 #undef TARGET_SIMD_CLONE_USABLE
52620 #define TARGET_SIMD_CLONE_USABLE \
52621 ix86_simd_clone_usable
52623 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
52624 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
52625 ix86_float_exceptions_rounding_supported_p
52627 #undef TARGET_MODE_EMIT
52628 #define TARGET_MODE_EMIT ix86_emit_mode_set
52630 #undef TARGET_MODE_NEEDED
52631 #define TARGET_MODE_NEEDED ix86_mode_needed
52633 #undef TARGET_MODE_AFTER
52634 #define TARGET_MODE_AFTER ix86_mode_after
52636 #undef TARGET_MODE_ENTRY
52637 #define TARGET_MODE_ENTRY ix86_mode_entry
52639 #undef TARGET_MODE_EXIT
52640 #define TARGET_MODE_EXIT ix86_mode_exit
52642 #undef TARGET_MODE_PRIORITY
52643 #define TARGET_MODE_PRIORITY ix86_mode_priority
52645 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
52646 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
52648 #undef TARGET_LOAD_BOUNDS_FOR_ARG
52649 #define TARGET_LOAD_BOUNDS_FOR_ARG ix86_load_bounds
52651 #undef TARGET_STORE_BOUNDS_FOR_ARG
52652 #define TARGET_STORE_BOUNDS_FOR_ARG ix86_store_bounds
52654 #undef TARGET_LOAD_RETURNED_BOUNDS
52655 #define TARGET_LOAD_RETURNED_BOUNDS ix86_load_returned_bounds
52657 #undef TARGET_STORE_RETURNED_BOUNDS
52658 #define TARGET_STORE_RETURNED_BOUNDS ix86_store_returned_bounds
52660 #undef TARGET_CHKP_BOUND_MODE
52661 #define TARGET_CHKP_BOUND_MODE ix86_mpx_bound_mode
52663 #undef TARGET_BUILTIN_CHKP_FUNCTION
52664 #define TARGET_BUILTIN_CHKP_FUNCTION ix86_builtin_mpx_function
52666 #undef TARGET_CHKP_FUNCTION_VALUE_BOUNDS
52667 #define TARGET_CHKP_FUNCTION_VALUE_BOUNDS ix86_function_value_bounds
52669 #undef TARGET_CHKP_MAKE_BOUNDS_CONSTANT
52670 #define TARGET_CHKP_MAKE_BOUNDS_CONSTANT ix86_make_bounds_constant
52672 #undef TARGET_CHKP_INITIALIZE_BOUNDS
52673 #define TARGET_CHKP_INITIALIZE_BOUNDS ix86_initialize_bounds
52675 #undef TARGET_SETUP_INCOMING_VARARG_BOUNDS
52676 #define TARGET_SETUP_INCOMING_VARARG_BOUNDS ix86_setup_incoming_vararg_bounds
52678 #undef TARGET_OFFLOAD_OPTIONS
52679 #define TARGET_OFFLOAD_OPTIONS \
52680 ix86_offload_options
52682 #undef TARGET_ABSOLUTE_BIGGEST_ALIGNMENT
52683 #define TARGET_ABSOLUTE_BIGGEST_ALIGNMENT 512
52686 \f