2004-08-23 Eric Christopher <echristo@redhat.com>
[official-gcc.git] / gcc / config / rs6000 / rs6000.c
blob9da6d2636ae6b9b98dd6835510e366bcf0461282
1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
23 #include "config.h"
24 #include "system.h"
25 #include "coretypes.h"
26 #include "tm.h"
27 #include "rtl.h"
28 #include "regs.h"
29 #include "hard-reg-set.h"
30 #include "real.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
34 #include "flags.h"
35 #include "recog.h"
36 #include "obstack.h"
37 #include "tree.h"
38 #include "expr.h"
39 #include "optabs.h"
40 #include "except.h"
41 #include "function.h"
42 #include "output.h"
43 #include "basic-block.h"
44 #include "integrate.h"
45 #include "toplev.h"
46 #include "ggc.h"
47 #include "hashtab.h"
48 #include "tm_p.h"
49 #include "target.h"
50 #include "target-def.h"
51 #include "langhooks.h"
52 #include "reload.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
56 #if TARGET_XCOFF
57 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
58 #endif
60 #ifndef TARGET_NO_PROTOTYPE
61 #define TARGET_NO_PROTOTYPE 0
62 #endif
64 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
65 #define EASY_VECTOR_15_ADD_SELF(n) ((n) >= 0x10 && (n) <= 0x1e \
66 && !((n) & 1))
68 #define min(A,B) ((A) < (B) ? (A) : (B))
69 #define max(A,B) ((A) > (B) ? (A) : (B))
71 /* Structure used to define the rs6000 stack */
72 typedef struct rs6000_stack {
73 int first_gp_reg_save; /* first callee saved GP register used */
74 int first_fp_reg_save; /* first callee saved FP register used */
75 int first_altivec_reg_save; /* first callee saved AltiVec register used */
76 int lr_save_p; /* true if the link reg needs to be saved */
77 int cr_save_p; /* true if the CR reg needs to be saved */
78 unsigned int vrsave_mask; /* mask of vec registers to save */
79 int toc_save_p; /* true if the TOC needs to be saved */
80 int push_p; /* true if we need to allocate stack space */
81 int calls_p; /* true if the function makes any calls */
82 int world_save_p; /* true if we're saving *everything*:
83 r13-r31, cr, f14-f31, vrsave, v20-v31 */
84 enum rs6000_abi abi; /* which ABI to use */
85 int gp_save_offset; /* offset to save GP regs from initial SP */
86 int fp_save_offset; /* offset to save FP regs from initial SP */
87 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
88 int lr_save_offset; /* offset to save LR from initial SP */
89 int cr_save_offset; /* offset to save CR from initial SP */
90 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
91 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
92 int toc_save_offset; /* offset to save the TOC pointer */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 int varargs_size; /* size to hold V.4 args passed in regs */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int lr_size; /* size to hold LR if not in save_size */
106 int vrsave_size; /* size to hold VRSAVE if not in save_size */
107 int altivec_padding_size; /* size of altivec alignment padding if
108 not in save_size */
109 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
110 int spe_padding_size;
111 int toc_size; /* size to hold TOC if not in save_size */
112 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
113 int spe_64bit_regs_used;
114 } rs6000_stack_t;
116 /* Target cpu type */
118 enum processor_type rs6000_cpu;
119 struct rs6000_cpu_select rs6000_select[3] =
121 /* switch name, tune arch */
122 { (const char *)0, "--with-cpu=", 1, 1 },
123 { (const char *)0, "-mcpu=", 1, 1 },
124 { (const char *)0, "-mtune=", 1, 0 },
127 /* Always emit branch hint bits. */
128 static GTY(()) bool rs6000_always_hint;
130 /* Schedule instructions for group formation. */
131 static GTY(()) bool rs6000_sched_groups;
133 /* Support adjust_priority scheduler hook
134 and -mprioritize-restricted-insns= option. */
135 const char *rs6000_sched_restricted_insns_priority_str;
136 int rs6000_sched_restricted_insns_priority;
138 /* Support for -msched-costly-dep option. */
139 const char *rs6000_sched_costly_dep_str;
140 enum rs6000_dependence_cost rs6000_sched_costly_dep;
142 /* Support for -minsert-sched-nops option. */
143 const char *rs6000_sched_insert_nops_str;
144 enum rs6000_nop_insertion rs6000_sched_insert_nops;
146 /* Size of long double */
147 const char *rs6000_long_double_size_string;
148 int rs6000_long_double_type_size;
150 /* Whether -mabi=altivec has appeared */
151 int rs6000_altivec_abi;
153 /* Whether VRSAVE instructions should be generated. */
154 int rs6000_altivec_vrsave;
156 /* String from -mvrsave= option. */
157 const char *rs6000_altivec_vrsave_string;
159 /* Nonzero if we want SPE ABI extensions. */
160 int rs6000_spe_abi;
162 /* Whether isel instructions should be generated. */
163 int rs6000_isel;
165 /* Whether SPE simd instructions should be generated. */
166 int rs6000_spe;
168 /* Nonzero if floating point operations are done in the GPRs. */
169 int rs6000_float_gprs = 0;
171 /* String from -mfloat-gprs=. */
172 const char *rs6000_float_gprs_string;
174 /* String from -misel=. */
175 const char *rs6000_isel_string;
177 /* String from -mspe=. */
178 const char *rs6000_spe_string;
180 /* Set to nonzero once AIX common-mode calls have been defined. */
181 static GTY(()) int common_mode_defined;
183 /* Save information from a "cmpxx" operation until the branch or scc is
184 emitted. */
185 rtx rs6000_compare_op0, rs6000_compare_op1;
186 int rs6000_compare_fp_p;
188 /* Label number of label created for -mrelocatable, to call to so we can
189 get the address of the GOT section */
190 int rs6000_pic_labelno;
192 #ifdef USING_ELFOS_H
193 /* Which abi to adhere to */
194 const char *rs6000_abi_name;
196 /* Semantics of the small data area */
197 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
199 /* Which small data model to use */
200 const char *rs6000_sdata_name = (char *)0;
202 /* Counter for labels which are to be placed in .fixup. */
203 int fixuplabelno = 0;
204 #endif
206 /* Bit size of immediate TLS offsets and string from which it is decoded. */
207 int rs6000_tls_size = 32;
208 const char *rs6000_tls_size_string;
210 /* ABI enumeration available for subtarget to use. */
211 enum rs6000_abi rs6000_current_abi;
213 /* ABI string from -mabi= option. */
214 const char *rs6000_abi_string;
216 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
217 int dot_symbols;
219 /* Debug flags */
220 const char *rs6000_debug_name;
221 int rs6000_debug_stack; /* debug stack applications */
222 int rs6000_debug_arg; /* debug argument handling */
224 /* Value is TRUE if register/mode pair is accepatable. */
225 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
227 /* Opaque types. */
228 static GTY(()) tree opaque_V2SI_type_node;
229 static GTY(()) tree opaque_V2SF_type_node;
230 static GTY(()) tree opaque_p_V2SI_type_node;
231 static GTY(()) tree V16QI_type_node;
232 static GTY(()) tree V2SI_type_node;
233 static GTY(()) tree V2SF_type_node;
234 static GTY(()) tree V4HI_type_node;
235 static GTY(()) tree V4SI_type_node;
236 static GTY(()) tree V4SF_type_node;
237 static GTY(()) tree V8HI_type_node;
238 static GTY(()) tree unsigned_V16QI_type_node;
239 static GTY(()) tree unsigned_V8HI_type_node;
240 static GTY(()) tree unsigned_V4SI_type_node;
241 static GTY(()) tree bool_char_type_node; /* __bool char */
242 static GTY(()) tree bool_short_type_node; /* __bool short */
243 static GTY(()) tree bool_int_type_node; /* __bool int */
244 static GTY(()) tree pixel_type_node; /* __pixel */
245 static GTY(()) tree bool_V16QI_type_node; /* __vector __bool char */
246 static GTY(()) tree bool_V8HI_type_node; /* __vector __bool short */
247 static GTY(()) tree bool_V4SI_type_node; /* __vector __bool int */
248 static GTY(()) tree pixel_V8HI_type_node; /* __vector __pixel */
250 int rs6000_warn_altivec_long = 1; /* On by default. */
251 const char *rs6000_warn_altivec_long_switch;
253 const char *rs6000_traceback_name;
254 static enum {
255 traceback_default = 0,
256 traceback_none,
257 traceback_part,
258 traceback_full
259 } rs6000_traceback;
261 /* Flag to say the TOC is initialized */
262 int toc_initialized;
263 char toc_label_name[10];
265 /* Alias set for saves and restores from the rs6000 stack. */
266 static GTY(()) int rs6000_sr_alias_set;
268 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
269 The only place that looks at this is rs6000_set_default_type_attributes;
270 everywhere else should rely on the presence or absence of a longcall
271 attribute on the function declaration. */
272 int rs6000_default_long_calls;
273 const char *rs6000_longcall_switch;
275 /* Control alignment for fields within structures. */
276 /* String from -malign-XXXXX. */
277 const char *rs6000_alignment_string;
278 int rs6000_alignment_flags;
280 struct builtin_description
282 /* mask is not const because we're going to alter it below. This
283 nonsense will go away when we rewrite the -march infrastructure
284 to give us more target flag bits. */
285 unsigned int mask;
286 const enum insn_code icode;
287 const char *const name;
288 const enum rs6000_builtins code;
291 /* Target cpu costs. */
293 struct processor_costs {
294 const int mulsi; /* cost of SImode multiplication. */
295 const int mulsi_const; /* cost of SImode multiplication by constant. */
296 const int mulsi_const9; /* cost of SImode mult by short constant. */
297 const int muldi; /* cost of DImode multiplication. */
298 const int divsi; /* cost of SImode division. */
299 const int divdi; /* cost of DImode division. */
300 const int fp; /* cost of simple SFmode and DFmode insns. */
301 const int dmul; /* cost of DFmode multiplication (and fmadd). */
302 const int sdiv; /* cost of SFmode division (fdivs). */
303 const int ddiv; /* cost of DFmode division (fdiv). */
306 const struct processor_costs *rs6000_cost;
308 /* Processor costs (relative to an add) */
310 /* Instruction size costs on 32bit processors. */
311 static const
312 struct processor_costs size32_cost = {
313 COSTS_N_INSNS (1), /* mulsi */
314 COSTS_N_INSNS (1), /* mulsi_const */
315 COSTS_N_INSNS (1), /* mulsi_const9 */
316 COSTS_N_INSNS (1), /* muldi */
317 COSTS_N_INSNS (1), /* divsi */
318 COSTS_N_INSNS (1), /* divdi */
319 COSTS_N_INSNS (1), /* fp */
320 COSTS_N_INSNS (1), /* dmul */
321 COSTS_N_INSNS (1), /* sdiv */
322 COSTS_N_INSNS (1), /* ddiv */
325 /* Instruction size costs on 64bit processors. */
326 static const
327 struct processor_costs size64_cost = {
328 COSTS_N_INSNS (1), /* mulsi */
329 COSTS_N_INSNS (1), /* mulsi_const */
330 COSTS_N_INSNS (1), /* mulsi_const9 */
331 COSTS_N_INSNS (1), /* muldi */
332 COSTS_N_INSNS (1), /* divsi */
333 COSTS_N_INSNS (1), /* divdi */
334 COSTS_N_INSNS (1), /* fp */
335 COSTS_N_INSNS (1), /* dmul */
336 COSTS_N_INSNS (1), /* sdiv */
337 COSTS_N_INSNS (1), /* ddiv */
340 /* Instruction costs on RIOS1 processors. */
341 static const
342 struct processor_costs rios1_cost = {
343 COSTS_N_INSNS (5), /* mulsi */
344 COSTS_N_INSNS (4), /* mulsi_const */
345 COSTS_N_INSNS (3), /* mulsi_const9 */
346 COSTS_N_INSNS (5), /* muldi */
347 COSTS_N_INSNS (19), /* divsi */
348 COSTS_N_INSNS (19), /* divdi */
349 COSTS_N_INSNS (2), /* fp */
350 COSTS_N_INSNS (2), /* dmul */
351 COSTS_N_INSNS (19), /* sdiv */
352 COSTS_N_INSNS (19), /* ddiv */
355 /* Instruction costs on RIOS2 processors. */
356 static const
357 struct processor_costs rios2_cost = {
358 COSTS_N_INSNS (2), /* mulsi */
359 COSTS_N_INSNS (2), /* mulsi_const */
360 COSTS_N_INSNS (2), /* mulsi_const9 */
361 COSTS_N_INSNS (2), /* muldi */
362 COSTS_N_INSNS (13), /* divsi */
363 COSTS_N_INSNS (13), /* divdi */
364 COSTS_N_INSNS (2), /* fp */
365 COSTS_N_INSNS (2), /* dmul */
366 COSTS_N_INSNS (17), /* sdiv */
367 COSTS_N_INSNS (17), /* ddiv */
370 /* Instruction costs on RS64A processors. */
371 static const
372 struct processor_costs rs64a_cost = {
373 COSTS_N_INSNS (20), /* mulsi */
374 COSTS_N_INSNS (12), /* mulsi_const */
375 COSTS_N_INSNS (8), /* mulsi_const9 */
376 COSTS_N_INSNS (34), /* muldi */
377 COSTS_N_INSNS (65), /* divsi */
378 COSTS_N_INSNS (67), /* divdi */
379 COSTS_N_INSNS (4), /* fp */
380 COSTS_N_INSNS (4), /* dmul */
381 COSTS_N_INSNS (31), /* sdiv */
382 COSTS_N_INSNS (31), /* ddiv */
385 /* Instruction costs on MPCCORE processors. */
386 static const
387 struct processor_costs mpccore_cost = {
388 COSTS_N_INSNS (2), /* mulsi */
389 COSTS_N_INSNS (2), /* mulsi_const */
390 COSTS_N_INSNS (2), /* mulsi_const9 */
391 COSTS_N_INSNS (2), /* muldi */
392 COSTS_N_INSNS (6), /* divsi */
393 COSTS_N_INSNS (6), /* divdi */
394 COSTS_N_INSNS (4), /* fp */
395 COSTS_N_INSNS (5), /* dmul */
396 COSTS_N_INSNS (10), /* sdiv */
397 COSTS_N_INSNS (17), /* ddiv */
400 /* Instruction costs on PPC403 processors. */
401 static const
402 struct processor_costs ppc403_cost = {
403 COSTS_N_INSNS (4), /* mulsi */
404 COSTS_N_INSNS (4), /* mulsi_const */
405 COSTS_N_INSNS (4), /* mulsi_const9 */
406 COSTS_N_INSNS (4), /* muldi */
407 COSTS_N_INSNS (33), /* divsi */
408 COSTS_N_INSNS (33), /* divdi */
409 COSTS_N_INSNS (11), /* fp */
410 COSTS_N_INSNS (11), /* dmul */
411 COSTS_N_INSNS (11), /* sdiv */
412 COSTS_N_INSNS (11), /* ddiv */
415 /* Instruction costs on PPC405 processors. */
416 static const
417 struct processor_costs ppc405_cost = {
418 COSTS_N_INSNS (5), /* mulsi */
419 COSTS_N_INSNS (4), /* mulsi_const */
420 COSTS_N_INSNS (3), /* mulsi_const9 */
421 COSTS_N_INSNS (5), /* muldi */
422 COSTS_N_INSNS (35), /* divsi */
423 COSTS_N_INSNS (35), /* divdi */
424 COSTS_N_INSNS (11), /* fp */
425 COSTS_N_INSNS (11), /* dmul */
426 COSTS_N_INSNS (11), /* sdiv */
427 COSTS_N_INSNS (11), /* ddiv */
430 /* Instruction costs on PPC440 processors. */
431 static const
432 struct processor_costs ppc440_cost = {
433 COSTS_N_INSNS (3), /* mulsi */
434 COSTS_N_INSNS (2), /* mulsi_const */
435 COSTS_N_INSNS (2), /* mulsi_const9 */
436 COSTS_N_INSNS (3), /* muldi */
437 COSTS_N_INSNS (34), /* divsi */
438 COSTS_N_INSNS (34), /* divdi */
439 COSTS_N_INSNS (5), /* fp */
440 COSTS_N_INSNS (5), /* dmul */
441 COSTS_N_INSNS (19), /* sdiv */
442 COSTS_N_INSNS (33), /* ddiv */
445 /* Instruction costs on PPC601 processors. */
446 static const
447 struct processor_costs ppc601_cost = {
448 COSTS_N_INSNS (5), /* mulsi */
449 COSTS_N_INSNS (5), /* mulsi_const */
450 COSTS_N_INSNS (5), /* mulsi_const9 */
451 COSTS_N_INSNS (5), /* muldi */
452 COSTS_N_INSNS (36), /* divsi */
453 COSTS_N_INSNS (36), /* divdi */
454 COSTS_N_INSNS (4), /* fp */
455 COSTS_N_INSNS (5), /* dmul */
456 COSTS_N_INSNS (17), /* sdiv */
457 COSTS_N_INSNS (31), /* ddiv */
460 /* Instruction costs on PPC603 processors. */
461 static const
462 struct processor_costs ppc603_cost = {
463 COSTS_N_INSNS (5), /* mulsi */
464 COSTS_N_INSNS (3), /* mulsi_const */
465 COSTS_N_INSNS (2), /* mulsi_const9 */
466 COSTS_N_INSNS (5), /* muldi */
467 COSTS_N_INSNS (37), /* divsi */
468 COSTS_N_INSNS (37), /* divdi */
469 COSTS_N_INSNS (3), /* fp */
470 COSTS_N_INSNS (4), /* dmul */
471 COSTS_N_INSNS (18), /* sdiv */
472 COSTS_N_INSNS (33), /* ddiv */
475 /* Instruction costs on PPC604 processors. */
476 static const
477 struct processor_costs ppc604_cost = {
478 COSTS_N_INSNS (4), /* mulsi */
479 COSTS_N_INSNS (4), /* mulsi_const */
480 COSTS_N_INSNS (4), /* mulsi_const9 */
481 COSTS_N_INSNS (4), /* muldi */
482 COSTS_N_INSNS (20), /* divsi */
483 COSTS_N_INSNS (20), /* divdi */
484 COSTS_N_INSNS (3), /* fp */
485 COSTS_N_INSNS (3), /* dmul */
486 COSTS_N_INSNS (18), /* sdiv */
487 COSTS_N_INSNS (32), /* ddiv */
490 /* Instruction costs on PPC604e processors. */
491 static const
492 struct processor_costs ppc604e_cost = {
493 COSTS_N_INSNS (2), /* mulsi */
494 COSTS_N_INSNS (2), /* mulsi_const */
495 COSTS_N_INSNS (2), /* mulsi_const9 */
496 COSTS_N_INSNS (2), /* muldi */
497 COSTS_N_INSNS (20), /* divsi */
498 COSTS_N_INSNS (20), /* divdi */
499 COSTS_N_INSNS (3), /* fp */
500 COSTS_N_INSNS (3), /* dmul */
501 COSTS_N_INSNS (18), /* sdiv */
502 COSTS_N_INSNS (32), /* ddiv */
505 /* Instruction costs on PPC620 processors. */
506 static const
507 struct processor_costs ppc620_cost = {
508 COSTS_N_INSNS (5), /* mulsi */
509 COSTS_N_INSNS (4), /* mulsi_const */
510 COSTS_N_INSNS (3), /* mulsi_const9 */
511 COSTS_N_INSNS (7), /* muldi */
512 COSTS_N_INSNS (21), /* divsi */
513 COSTS_N_INSNS (37), /* divdi */
514 COSTS_N_INSNS (3), /* fp */
515 COSTS_N_INSNS (3), /* dmul */
516 COSTS_N_INSNS (18), /* sdiv */
517 COSTS_N_INSNS (32), /* ddiv */
520 /* Instruction costs on PPC630 processors. */
521 static const
522 struct processor_costs ppc630_cost = {
523 COSTS_N_INSNS (5), /* mulsi */
524 COSTS_N_INSNS (4), /* mulsi_const */
525 COSTS_N_INSNS (3), /* mulsi_const9 */
526 COSTS_N_INSNS (7), /* muldi */
527 COSTS_N_INSNS (21), /* divsi */
528 COSTS_N_INSNS (37), /* divdi */
529 COSTS_N_INSNS (3), /* fp */
530 COSTS_N_INSNS (3), /* dmul */
531 COSTS_N_INSNS (17), /* sdiv */
532 COSTS_N_INSNS (21), /* ddiv */
535 /* Instruction costs on PPC750 and PPC7400 processors. */
536 static const
537 struct processor_costs ppc750_cost = {
538 COSTS_N_INSNS (5), /* mulsi */
539 COSTS_N_INSNS (3), /* mulsi_const */
540 COSTS_N_INSNS (2), /* mulsi_const9 */
541 COSTS_N_INSNS (5), /* muldi */
542 COSTS_N_INSNS (17), /* divsi */
543 COSTS_N_INSNS (17), /* divdi */
544 COSTS_N_INSNS (3), /* fp */
545 COSTS_N_INSNS (3), /* dmul */
546 COSTS_N_INSNS (17), /* sdiv */
547 COSTS_N_INSNS (31), /* ddiv */
550 /* Instruction costs on PPC7450 processors. */
551 static const
552 struct processor_costs ppc7450_cost = {
553 COSTS_N_INSNS (4), /* mulsi */
554 COSTS_N_INSNS (3), /* mulsi_const */
555 COSTS_N_INSNS (3), /* mulsi_const9 */
556 COSTS_N_INSNS (4), /* muldi */
557 COSTS_N_INSNS (23), /* divsi */
558 COSTS_N_INSNS (23), /* divdi */
559 COSTS_N_INSNS (5), /* fp */
560 COSTS_N_INSNS (5), /* dmul */
561 COSTS_N_INSNS (21), /* sdiv */
562 COSTS_N_INSNS (35), /* ddiv */
565 /* Instruction costs on PPC8540 processors. */
566 static const
567 struct processor_costs ppc8540_cost = {
568 COSTS_N_INSNS (4), /* mulsi */
569 COSTS_N_INSNS (4), /* mulsi_const */
570 COSTS_N_INSNS (4), /* mulsi_const9 */
571 COSTS_N_INSNS (4), /* muldi */
572 COSTS_N_INSNS (19), /* divsi */
573 COSTS_N_INSNS (19), /* divdi */
574 COSTS_N_INSNS (4), /* fp */
575 COSTS_N_INSNS (4), /* dmul */
576 COSTS_N_INSNS (29), /* sdiv */
577 COSTS_N_INSNS (29), /* ddiv */
580 /* Instruction costs on POWER4 and POWER5 processors. */
581 static const
582 struct processor_costs power4_cost = {
583 COSTS_N_INSNS (3), /* mulsi */
584 COSTS_N_INSNS (2), /* mulsi_const */
585 COSTS_N_INSNS (2), /* mulsi_const9 */
586 COSTS_N_INSNS (4), /* muldi */
587 COSTS_N_INSNS (18), /* divsi */
588 COSTS_N_INSNS (34), /* divdi */
589 COSTS_N_INSNS (3), /* fp */
590 COSTS_N_INSNS (3), /* dmul */
591 COSTS_N_INSNS (17), /* sdiv */
592 COSTS_N_INSNS (17), /* ddiv */
596 static bool rs6000_function_ok_for_sibcall (tree, tree);
597 static int num_insns_constant_wide (HOST_WIDE_INT);
598 static void validate_condition_mode (enum rtx_code, enum machine_mode);
599 static rtx rs6000_generate_compare (enum rtx_code);
600 static void rs6000_maybe_dead (rtx);
601 static void rs6000_emit_stack_tie (void);
602 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
603 static rtx spe_synthesize_frame_save (rtx);
604 static bool spe_func_has_64bit_regs_p (void);
605 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
606 int, HOST_WIDE_INT);
607 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
608 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
609 static unsigned rs6000_hash_constant (rtx);
610 static unsigned toc_hash_function (const void *);
611 static int toc_hash_eq (const void *, const void *);
612 static int constant_pool_expr_1 (rtx, int *, int *);
613 static bool constant_pool_expr_p (rtx);
614 static bool toc_relative_expr_p (rtx);
615 static bool legitimate_small_data_p (enum machine_mode, rtx);
616 static bool legitimate_indexed_address_p (rtx, int);
617 static bool legitimate_indirect_address_p (rtx, int);
618 static bool macho_lo_sum_memory_operand (rtx x, enum machine_mode mode);
619 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
620 static struct machine_function * rs6000_init_machine_status (void);
621 static bool rs6000_assemble_integer (rtx, unsigned int, int);
622 #ifdef HAVE_GAS_HIDDEN
623 static void rs6000_assemble_visibility (tree, int);
624 #endif
625 static int rs6000_ra_ever_killed (void);
626 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
627 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
628 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
629 static const char *rs6000_mangle_fundamental_type (tree);
630 extern const struct attribute_spec rs6000_attribute_table[];
631 static void rs6000_set_default_type_attributes (tree);
632 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
633 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
634 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
635 tree);
636 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
637 static bool rs6000_return_in_memory (tree, tree);
638 static void rs6000_file_start (void);
639 #if TARGET_ELF
640 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
641 static void rs6000_elf_asm_out_constructor (rtx, int);
642 static void rs6000_elf_asm_out_destructor (rtx, int);
643 static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
644 static void rs6000_elf_unique_section (tree, int);
645 static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
646 unsigned HOST_WIDE_INT);
647 static void rs6000_elf_encode_section_info (tree, rtx, int)
648 ATTRIBUTE_UNUSED;
649 static bool rs6000_elf_in_small_data_p (tree);
650 #endif
651 #if TARGET_XCOFF
652 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
653 static void rs6000_xcoff_asm_named_section (const char *, unsigned int);
654 static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
655 static void rs6000_xcoff_unique_section (tree, int);
656 static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
657 unsigned HOST_WIDE_INT);
658 static const char * rs6000_xcoff_strip_name_encoding (const char *);
659 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
660 static void rs6000_xcoff_file_start (void);
661 static void rs6000_xcoff_file_end (void);
662 #endif
663 #if TARGET_MACHO
664 static bool rs6000_binds_local_p (tree);
665 #endif
666 static int rs6000_variable_issue (FILE *, int, rtx, int);
667 static bool rs6000_rtx_costs (rtx, int, int, int *);
668 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
669 static bool is_microcoded_insn (rtx);
670 static int is_dispatch_slot_restricted (rtx);
671 static bool is_cracked_insn (rtx);
672 static bool is_branch_slot_insn (rtx);
673 static int rs6000_adjust_priority (rtx, int);
674 static int rs6000_issue_rate (void);
675 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
676 static rtx get_next_active_insn (rtx, rtx);
677 static bool insn_terminates_group_p (rtx , enum group_termination);
678 static bool is_costly_group (rtx *, rtx);
679 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
680 static int redefine_groups (FILE *, int, rtx, rtx);
681 static int pad_groups (FILE *, int, rtx, rtx);
682 static void rs6000_sched_finish (FILE *, int);
683 static int rs6000_use_sched_lookahead (void);
685 static void rs6000_init_builtins (void);
686 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
687 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
688 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
689 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
690 static void altivec_init_builtins (void);
691 static void rs6000_common_init_builtins (void);
692 static void rs6000_init_libfuncs (void);
694 static void enable_mask_for_builtins (struct builtin_description *, int,
695 enum rs6000_builtins,
696 enum rs6000_builtins);
697 static tree build_opaque_vector_type (tree, int);
698 static void spe_init_builtins (void);
699 static rtx spe_expand_builtin (tree, rtx, bool *);
700 static rtx spe_expand_stv_builtin (enum insn_code, tree);
701 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
702 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
703 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
704 static rs6000_stack_t *rs6000_stack_info (void);
705 static void debug_stack_info (rs6000_stack_t *);
707 static rtx altivec_expand_builtin (tree, rtx, bool *);
708 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
709 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
710 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
711 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
712 static rtx altivec_expand_predicate_builtin (enum insn_code,
713 const char *, tree, rtx);
714 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
715 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
716 static void rs6000_parse_abi_options (void);
717 static void rs6000_parse_alignment_option (void);
718 static void rs6000_parse_tls_size_option (void);
719 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
720 static int first_altivec_reg_to_save (void);
721 static unsigned int compute_vrsave_mask (void);
722 static void compute_save_world_info(rs6000_stack_t *info_ptr);
723 static void is_altivec_return_reg (rtx, void *);
724 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
725 int easy_vector_constant (rtx, enum machine_mode);
726 static int easy_vector_same (rtx, enum machine_mode);
727 static int easy_vector_splat_const (int, enum machine_mode);
728 static bool is_ev64_opaque_type (tree);
729 static rtx rs6000_dwarf_register_span (rtx);
730 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
731 static rtx rs6000_tls_get_addr (void);
732 static rtx rs6000_got_sym (void);
733 static inline int rs6000_tls_symbol_ref_1 (rtx *, void *);
734 static const char *rs6000_get_some_local_dynamic_name (void);
735 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
736 static rtx rs6000_complex_function_value (enum machine_mode);
737 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
738 enum machine_mode, tree);
739 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
740 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
741 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
742 enum machine_mode, tree,
743 int *, int);
744 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
745 tree, bool);
746 #if TARGET_MACHO
747 static void macho_branch_islands (void);
748 static void add_compiler_branch_island (tree, tree, int);
749 static int no_previous_def (tree function_name);
750 static tree get_prev_label (tree function_name);
751 #endif
753 static tree rs6000_build_builtin_va_list (void);
754 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
755 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
756 static bool rs6000_vector_mode_supported_p (enum machine_mode);
758 static enum machine_mode rs6000_eh_return_filter_mode (void);
760 /* Hash table stuff for keeping track of TOC entries. */
762 struct toc_hash_struct GTY(())
764 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
765 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
766 rtx key;
767 enum machine_mode key_mode;
768 int labelno;
771 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
773 /* Default register names. */
774 char rs6000_reg_names[][8] =
776 "0", "1", "2", "3", "4", "5", "6", "7",
777 "8", "9", "10", "11", "12", "13", "14", "15",
778 "16", "17", "18", "19", "20", "21", "22", "23",
779 "24", "25", "26", "27", "28", "29", "30", "31",
780 "0", "1", "2", "3", "4", "5", "6", "7",
781 "8", "9", "10", "11", "12", "13", "14", "15",
782 "16", "17", "18", "19", "20", "21", "22", "23",
783 "24", "25", "26", "27", "28", "29", "30", "31",
784 "mq", "lr", "ctr","ap",
785 "0", "1", "2", "3", "4", "5", "6", "7",
786 "xer",
787 /* AltiVec registers. */
788 "0", "1", "2", "3", "4", "5", "6", "7",
789 "8", "9", "10", "11", "12", "13", "14", "15",
790 "16", "17", "18", "19", "20", "21", "22", "23",
791 "24", "25", "26", "27", "28", "29", "30", "31",
792 "vrsave", "vscr",
793 /* SPE registers. */
794 "spe_acc", "spefscr"
797 #ifdef TARGET_REGNAMES
798 static const char alt_reg_names[][8] =
800 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
801 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
802 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
803 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
804 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
805 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
806 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
807 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
808 "mq", "lr", "ctr", "ap",
809 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
810 "xer",
811 /* AltiVec registers. */
812 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
813 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
814 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
815 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
816 "vrsave", "vscr",
817 /* SPE registers. */
818 "spe_acc", "spefscr"
820 #endif
822 #ifndef MASK_STRICT_ALIGN
823 #define MASK_STRICT_ALIGN 0
824 #endif
825 #ifndef TARGET_PROFILE_KERNEL
826 #define TARGET_PROFILE_KERNEL 0
827 #endif
829 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
830 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
832 /* Return 1 for a symbol ref for a thread-local storage symbol. */
833 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
834 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
836 /* Initialize the GCC target structure. */
837 #undef TARGET_ATTRIBUTE_TABLE
838 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
839 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
840 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
842 #undef TARGET_ASM_ALIGNED_DI_OP
843 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
845 /* Default unaligned ops are only provided for ELF. Find the ops needed
846 for non-ELF systems. */
847 #ifndef OBJECT_FORMAT_ELF
848 #if TARGET_XCOFF
849 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
850 64-bit targets. */
851 #undef TARGET_ASM_UNALIGNED_HI_OP
852 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
853 #undef TARGET_ASM_UNALIGNED_SI_OP
854 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
855 #undef TARGET_ASM_UNALIGNED_DI_OP
856 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
857 #else
858 /* For Darwin. */
859 #undef TARGET_ASM_UNALIGNED_HI_OP
860 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
861 #undef TARGET_ASM_UNALIGNED_SI_OP
862 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
863 #undef TARGET_ASM_UNALIGNED_DI_OP
864 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
865 #undef TARGET_ASM_ALIGNED_DI_OP
866 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
867 #endif
868 #endif
870 /* This hook deals with fixups for relocatable code and DI-mode objects
871 in 64-bit code. */
872 #undef TARGET_ASM_INTEGER
873 #define TARGET_ASM_INTEGER rs6000_assemble_integer
875 #ifdef HAVE_GAS_HIDDEN
876 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
877 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
878 #endif
880 #undef TARGET_HAVE_TLS
881 #define TARGET_HAVE_TLS HAVE_AS_TLS
883 #undef TARGET_CANNOT_FORCE_CONST_MEM
884 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
886 #undef TARGET_ASM_FUNCTION_PROLOGUE
887 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
888 #undef TARGET_ASM_FUNCTION_EPILOGUE
889 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
891 #undef TARGET_SCHED_VARIABLE_ISSUE
892 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
894 #undef TARGET_SCHED_ISSUE_RATE
895 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
896 #undef TARGET_SCHED_ADJUST_COST
897 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
898 #undef TARGET_SCHED_ADJUST_PRIORITY
899 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
900 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
901 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
902 #undef TARGET_SCHED_FINISH
903 #define TARGET_SCHED_FINISH rs6000_sched_finish
905 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
906 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
908 #undef TARGET_INIT_BUILTINS
909 #define TARGET_INIT_BUILTINS rs6000_init_builtins
911 #undef TARGET_EXPAND_BUILTIN
912 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
914 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
915 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
917 #undef TARGET_INIT_LIBFUNCS
918 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
920 #if TARGET_MACHO
921 #undef TARGET_BINDS_LOCAL_P
922 #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
923 #endif
925 #undef TARGET_ASM_OUTPUT_MI_THUNK
926 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
928 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
929 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
931 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
932 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
934 #undef TARGET_RTX_COSTS
935 #define TARGET_RTX_COSTS rs6000_rtx_costs
936 #undef TARGET_ADDRESS_COST
937 #define TARGET_ADDRESS_COST hook_int_rtx_0
939 #undef TARGET_VECTOR_OPAQUE_P
940 #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
942 #undef TARGET_DWARF_REGISTER_SPAN
943 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
945 /* On rs6000, function arguments are promoted, as are function return
946 values. */
947 #undef TARGET_PROMOTE_FUNCTION_ARGS
948 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
949 #undef TARGET_PROMOTE_FUNCTION_RETURN
950 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
952 #undef TARGET_RETURN_IN_MEMORY
953 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
955 #undef TARGET_SETUP_INCOMING_VARARGS
956 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
958 /* Always strict argument naming on rs6000. */
959 #undef TARGET_STRICT_ARGUMENT_NAMING
960 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
961 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
962 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
963 #undef TARGET_SPLIT_COMPLEX_ARG
964 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
965 #undef TARGET_MUST_PASS_IN_STACK
966 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
967 #undef TARGET_PASS_BY_REFERENCE
968 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
970 #undef TARGET_BUILD_BUILTIN_VA_LIST
971 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
973 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
974 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
976 #undef TARGET_EH_RETURN_FILTER_MODE
977 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
979 #undef TARGET_VECTOR_MODE_SUPPORTED_P
980 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
982 struct gcc_target targetm = TARGET_INITIALIZER;
985 /* Value is 1 if hard register REGNO can hold a value of machine-mode
986 MODE. */
987 static int
988 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
990 /* The GPRs can hold any mode, but values bigger than one register
991 cannot go past R31. */
992 if (INT_REGNO_P (regno))
993 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
995 /* The float registers can only hold floating modes and DImode. */
996 if (FP_REGNO_P (regno))
997 return
998 (GET_MODE_CLASS (mode) == MODE_FLOAT
999 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1000 || (GET_MODE_CLASS (mode) == MODE_INT
1001 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1003 /* The CR register can only hold CC modes. */
1004 if (CR_REGNO_P (regno))
1005 return GET_MODE_CLASS (mode) == MODE_CC;
1007 if (XER_REGNO_P (regno))
1008 return mode == PSImode;
1010 /* AltiVec only in AldyVec registers. */
1011 if (ALTIVEC_REGNO_P (regno))
1012 return ALTIVEC_VECTOR_MODE (mode);
1014 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1015 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1016 return 1;
1018 /* We cannot put TImode anywhere except general register and it must be
1019 able to fit within the register set. */
1021 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1024 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1025 static void
1026 rs6000_init_hard_regno_mode_ok (void)
1028 int r, m;
1030 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1031 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1032 if (rs6000_hard_regno_mode_ok (r, m))
1033 rs6000_hard_regno_mode_ok_p[m][r] = true;
1036 /* If not otherwise specified by a target, make 'long double' equivalent to
1037 'double'. */
1039 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1040 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1041 #endif
1043 /* Override command line options. Mostly we process the processor
1044 type and sometimes adjust other TARGET_ options. */
1046 void
1047 rs6000_override_options (const char *default_cpu)
1049 size_t i, j;
1050 struct rs6000_cpu_select *ptr;
1051 int set_masks;
1053 /* Simplifications for entries below. */
1055 enum {
1056 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1057 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1060 /* This table occasionally claims that a processor does not support
1061 a particular feature even though it does, but the feature is slower
1062 than the alternative. Thus, it shouldn't be relied on as a
1063 complete description of the processor's support.
1065 Please keep this list in order, and don't forget to update the
1066 documentation in invoke.texi when adding a new processor or
1067 flag. */
1068 static struct ptt
1070 const char *const name; /* Canonical processor name. */
1071 const enum processor_type processor; /* Processor type enum value. */
1072 const int target_enable; /* Target flags to enable. */
1073 } const processor_target_table[]
1074 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1075 {"403", PROCESSOR_PPC403,
1076 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1077 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1078 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
1079 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1080 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
1081 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1082 {"601", PROCESSOR_PPC601,
1083 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1084 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1085 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1086 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1087 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1088 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1089 {"620", PROCESSOR_PPC620,
1090 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1091 {"630", PROCESSOR_PPC630,
1092 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1093 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1094 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1095 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1096 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1097 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1098 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1099 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1100 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1101 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1102 {"970", PROCESSOR_POWER4,
1103 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1104 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1105 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1106 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1107 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1108 {"G5", PROCESSOR_POWER4,
1109 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1110 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1111 {"power2", PROCESSOR_POWER,
1112 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1113 {"power3", PROCESSOR_PPC630,
1114 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1115 {"power4", PROCESSOR_POWER4,
1116 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1117 {"power5", PROCESSOR_POWER5,
1118 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1119 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1120 {"powerpc64", PROCESSOR_POWERPC64,
1121 POWERPC_BASE_MASK | MASK_POWERPC64},
1122 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1123 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1124 {"rios2", PROCESSOR_RIOS2,
1125 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1126 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1127 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1128 {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64},
1131 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1133 /* Some OSs don't support saving the high part of 64-bit registers on
1134 context switch. Other OSs don't support saving Altivec registers.
1135 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1136 settings; if the user wants either, the user must explicitly specify
1137 them and we won't interfere with the user's specification. */
1139 enum {
1140 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1141 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1142 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1143 | MASK_MFCRF)
1146 rs6000_init_hard_regno_mode_ok ();
1148 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1149 #ifdef OS_MISSING_POWERPC64
1150 if (OS_MISSING_POWERPC64)
1151 set_masks &= ~MASK_POWERPC64;
1152 #endif
1153 #ifdef OS_MISSING_ALTIVEC
1154 if (OS_MISSING_ALTIVEC)
1155 set_masks &= ~MASK_ALTIVEC;
1156 #endif
1158 /* Don't override these by the processor default if given explicitly. */
1159 set_masks &= ~(target_flags_explicit
1160 & (MASK_MULTIPLE | MASK_STRING | MASK_SOFT_FLOAT));
1162 /* Identify the processor type. */
1163 rs6000_select[0].string = default_cpu;
1164 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1166 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1168 ptr = &rs6000_select[i];
1169 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1171 for (j = 0; j < ptt_size; j++)
1172 if (! strcmp (ptr->string, processor_target_table[j].name))
1174 if (ptr->set_tune_p)
1175 rs6000_cpu = processor_target_table[j].processor;
1177 if (ptr->set_arch_p)
1179 target_flags &= ~set_masks;
1180 target_flags |= (processor_target_table[j].target_enable
1181 & set_masks);
1183 break;
1186 if (j == ptt_size)
1187 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1191 if (TARGET_E500)
1192 rs6000_isel = 1;
1194 /* If we are optimizing big endian systems for space, use the load/store
1195 multiple and string instructions. */
1196 if (BYTES_BIG_ENDIAN && optimize_size)
1197 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1199 /* Don't allow -mmultiple or -mstring on little endian systems
1200 unless the cpu is a 750, because the hardware doesn't support the
1201 instructions used in little endian mode, and causes an alignment
1202 trap. The 750 does not cause an alignment trap (except when the
1203 target is unaligned). */
1205 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1207 if (TARGET_MULTIPLE)
1209 target_flags &= ~MASK_MULTIPLE;
1210 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1211 warning ("-mmultiple is not supported on little endian systems");
1214 if (TARGET_STRING)
1216 target_flags &= ~MASK_STRING;
1217 if ((target_flags_explicit & MASK_STRING) != 0)
1218 warning ("-mstring is not supported on little endian systems");
1222 /* Set debug flags */
1223 if (rs6000_debug_name)
1225 if (! strcmp (rs6000_debug_name, "all"))
1226 rs6000_debug_stack = rs6000_debug_arg = 1;
1227 else if (! strcmp (rs6000_debug_name, "stack"))
1228 rs6000_debug_stack = 1;
1229 else if (! strcmp (rs6000_debug_name, "arg"))
1230 rs6000_debug_arg = 1;
1231 else
1232 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1235 if (rs6000_traceback_name)
1237 if (! strncmp (rs6000_traceback_name, "full", 4))
1238 rs6000_traceback = traceback_full;
1239 else if (! strncmp (rs6000_traceback_name, "part", 4))
1240 rs6000_traceback = traceback_part;
1241 else if (! strncmp (rs6000_traceback_name, "no", 2))
1242 rs6000_traceback = traceback_none;
1243 else
1244 error ("unknown -mtraceback arg `%s'; expecting `full', `partial' or `none'",
1245 rs6000_traceback_name);
1248 /* Set size of long double */
1249 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1250 if (rs6000_long_double_size_string)
1252 char *tail;
1253 int size = strtol (rs6000_long_double_size_string, &tail, 10);
1254 if (*tail != '\0' || (size != 64 && size != 128))
1255 error ("Unknown switch -mlong-double-%s",
1256 rs6000_long_double_size_string);
1257 else
1258 rs6000_long_double_type_size = size;
1261 /* Set Altivec ABI as default for powerpc64 linux. */
1262 if (TARGET_ELF && TARGET_64BIT)
1264 rs6000_altivec_abi = 1;
1265 rs6000_altivec_vrsave = 1;
1268 /* Handle -mabi= options. */
1269 rs6000_parse_abi_options ();
1271 /* Handle -malign-XXXXX option. */
1272 rs6000_parse_alignment_option ();
1274 /* Handle generic -mFOO=YES/NO options. */
1275 rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string,
1276 &rs6000_altivec_vrsave);
1277 rs6000_parse_yes_no_option ("isel", rs6000_isel_string,
1278 &rs6000_isel);
1279 rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe);
1280 rs6000_parse_yes_no_option ("float-gprs", rs6000_float_gprs_string,
1281 &rs6000_float_gprs);
1283 /* Handle -mtls-size option. */
1284 rs6000_parse_tls_size_option ();
1286 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1287 SUBTARGET_OVERRIDE_OPTIONS;
1288 #endif
1289 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1290 SUBSUBTARGET_OVERRIDE_OPTIONS;
1291 #endif
1293 if (TARGET_E500)
1295 if (TARGET_ALTIVEC)
1296 error ("AltiVec and E500 instructions cannot coexist");
1298 /* The e500 does not have string instructions, and we set
1299 MASK_STRING above when optimizing for size. */
1300 if ((target_flags & MASK_STRING) != 0)
1301 target_flags = target_flags & ~MASK_STRING;
1303 /* No SPE means 64-bit long doubles, even if an E500. */
1304 if (rs6000_spe_string != 0
1305 && !strcmp (rs6000_spe_string, "no"))
1306 rs6000_long_double_type_size = 64;
1308 else if (rs6000_select[1].string != NULL)
1310 /* For the powerpc-eabispe configuration, we set all these by
1311 default, so let's unset them if we manually set another
1312 CPU that is not the E500. */
1313 if (rs6000_abi_string == 0)
1314 rs6000_spe_abi = 0;
1315 if (rs6000_spe_string == 0)
1316 rs6000_spe = 0;
1317 if (rs6000_float_gprs_string == 0)
1318 rs6000_float_gprs = 0;
1319 if (rs6000_isel_string == 0)
1320 rs6000_isel = 0;
1321 if (rs6000_long_double_size_string == 0)
1322 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1325 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1326 && rs6000_cpu != PROCESSOR_POWER5);
1327 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1328 || rs6000_cpu == PROCESSOR_POWER5);
1330 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
1331 using TARGET_OPTIONS to handle a toggle switch, but we're out of
1332 bits in target_flags so TARGET_SWITCHES cannot be used.
1333 Assumption here is that rs6000_longcall_switch points into the
1334 text of the complete option, rather than being a copy, so we can
1335 scan back for the presence or absence of the no- modifier. */
1336 if (rs6000_longcall_switch)
1338 const char *base = rs6000_longcall_switch;
1339 while (base[-1] != 'm') base--;
1341 if (*rs6000_longcall_switch != '\0')
1342 error ("invalid option `%s'", base);
1343 rs6000_default_long_calls = (base[0] != 'n');
1346 /* Handle -m(no-)warn-altivec-long similarly. */
1347 if (rs6000_warn_altivec_long_switch)
1349 const char *base = rs6000_warn_altivec_long_switch;
1350 while (base[-1] != 'm') base--;
1352 if (*rs6000_warn_altivec_long_switch != '\0')
1353 error ("invalid option `%s'", base);
1354 rs6000_warn_altivec_long = (base[0] != 'n');
1357 /* Handle -mprioritize-restricted-insns option. */
1358 rs6000_sched_restricted_insns_priority
1359 = (rs6000_sched_groups ? 1 : 0);
1360 if (rs6000_sched_restricted_insns_priority_str)
1361 rs6000_sched_restricted_insns_priority =
1362 atoi (rs6000_sched_restricted_insns_priority_str);
1364 /* Handle -msched-costly-dep option. */
1365 rs6000_sched_costly_dep
1366 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1367 if (rs6000_sched_costly_dep_str)
1369 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1370 rs6000_sched_costly_dep = no_dep_costly;
1371 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1372 rs6000_sched_costly_dep = all_deps_costly;
1373 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1374 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1375 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1376 rs6000_sched_costly_dep = store_to_load_dep_costly;
1377 else
1378 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1381 /* Handle -minsert-sched-nops option. */
1382 rs6000_sched_insert_nops
1383 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1384 if (rs6000_sched_insert_nops_str)
1386 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1387 rs6000_sched_insert_nops = sched_finish_none;
1388 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1389 rs6000_sched_insert_nops = sched_finish_pad_groups;
1390 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1391 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1392 else
1393 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1396 #ifdef TARGET_REGNAMES
1397 /* If the user desires alternate register names, copy in the
1398 alternate names now. */
1399 if (TARGET_REGNAMES)
1400 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1401 #endif
1403 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
1404 If -maix-struct-return or -msvr4-struct-return was explicitly
1405 used, don't override with the ABI default. */
1406 if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
1408 if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
1409 target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
1410 else
1411 target_flags |= MASK_AIX_STRUCT_RET;
1414 if (TARGET_LONG_DOUBLE_128
1415 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
1416 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1418 /* Allocate an alias set for register saves & restores from stack. */
1419 rs6000_sr_alias_set = new_alias_set ();
1421 if (TARGET_TOC)
1422 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1424 /* We can only guarantee the availability of DI pseudo-ops when
1425 assembling for 64-bit targets. */
1426 if (!TARGET_64BIT)
1428 targetm.asm_out.aligned_op.di = NULL;
1429 targetm.asm_out.unaligned_op.di = NULL;
1432 /* Set maximum branch target alignment at two instructions, eight bytes. */
1433 align_jumps_max_skip = 8;
1434 align_loops_max_skip = 8;
1436 /* Arrange to save and restore machine status around nested functions. */
1437 init_machine_status = rs6000_init_machine_status;
1439 /* We should always be splitting complex arguments, but we can't break
1440 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1441 if (DEFAULT_ABI != ABI_AIX)
1442 targetm.calls.split_complex_arg = NULL;
1444 /* Initialize rs6000_cost with the appropriate target costs. */
1445 if (optimize_size)
1446 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1447 else
1448 switch (rs6000_cpu)
1450 case PROCESSOR_RIOS1:
1451 rs6000_cost = &rios1_cost;
1452 break;
1454 case PROCESSOR_RIOS2:
1455 rs6000_cost = &rios2_cost;
1456 break;
1458 case PROCESSOR_RS64A:
1459 rs6000_cost = &rs64a_cost;
1460 break;
1462 case PROCESSOR_MPCCORE:
1463 rs6000_cost = &mpccore_cost;
1464 break;
1466 case PROCESSOR_PPC403:
1467 rs6000_cost = &ppc403_cost;
1468 break;
1470 case PROCESSOR_PPC405:
1471 rs6000_cost = &ppc405_cost;
1472 break;
1474 case PROCESSOR_PPC440:
1475 rs6000_cost = &ppc440_cost;
1476 break;
1478 case PROCESSOR_PPC601:
1479 rs6000_cost = &ppc601_cost;
1480 break;
1482 case PROCESSOR_PPC603:
1483 rs6000_cost = &ppc603_cost;
1484 break;
1486 case PROCESSOR_PPC604:
1487 rs6000_cost = &ppc604_cost;
1488 break;
1490 case PROCESSOR_PPC604e:
1491 rs6000_cost = &ppc604e_cost;
1492 break;
1494 case PROCESSOR_PPC620:
1495 rs6000_cost = &ppc620_cost;
1496 break;
1498 case PROCESSOR_PPC630:
1499 rs6000_cost = &ppc630_cost;
1500 break;
1502 case PROCESSOR_PPC750:
1503 case PROCESSOR_PPC7400:
1504 rs6000_cost = &ppc750_cost;
1505 break;
1507 case PROCESSOR_PPC7450:
1508 rs6000_cost = &ppc7450_cost;
1509 break;
1511 case PROCESSOR_PPC8540:
1512 rs6000_cost = &ppc8540_cost;
1513 break;
1515 case PROCESSOR_POWER4:
1516 case PROCESSOR_POWER5:
1517 rs6000_cost = &power4_cost;
1518 break;
1520 default:
1521 abort ();
1525 /* Handle generic options of the form -mfoo=yes/no.
1526 NAME is the option name.
1527 VALUE is the option value.
1528 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1529 whether the option value is 'yes' or 'no' respectively. */
1530 static void
1531 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1533 if (value == 0)
1534 return;
1535 else if (!strcmp (value, "yes"))
1536 *flag = 1;
1537 else if (!strcmp (value, "no"))
1538 *flag = 0;
1539 else
1540 error ("unknown -m%s= option specified: '%s'", name, value);
1543 /* Handle -mabi= options. */
1544 static void
1545 rs6000_parse_abi_options (void)
1547 if (rs6000_abi_string == 0)
1548 return;
1549 else if (! strcmp (rs6000_abi_string, "altivec"))
1551 rs6000_altivec_abi = 1;
1552 rs6000_spe_abi = 0;
1554 else if (! strcmp (rs6000_abi_string, "no-altivec"))
1555 rs6000_altivec_abi = 0;
1556 else if (! strcmp (rs6000_abi_string, "spe"))
1558 rs6000_spe_abi = 1;
1559 rs6000_altivec_abi = 0;
1560 if (!TARGET_SPE_ABI)
1561 error ("not configured for ABI: '%s'", rs6000_abi_string);
1564 else if (! strcmp (rs6000_abi_string, "no-spe"))
1565 rs6000_spe_abi = 0;
1566 else
1567 error ("unknown ABI specified: '%s'", rs6000_abi_string);
1570 /* Handle -malign-XXXXXX options. */
1571 static void
1572 rs6000_parse_alignment_option (void)
1574 if (rs6000_alignment_string == 0)
1575 return;
1576 else if (! strcmp (rs6000_alignment_string, "power"))
1577 rs6000_alignment_flags = MASK_ALIGN_POWER;
1578 else if (! strcmp (rs6000_alignment_string, "natural"))
1579 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1580 else
1581 error ("unknown -malign-XXXXX option specified: '%s'",
1582 rs6000_alignment_string);
1585 /* Validate and record the size specified with the -mtls-size option. */
1587 static void
1588 rs6000_parse_tls_size_option (void)
1590 if (rs6000_tls_size_string == 0)
1591 return;
1592 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1593 rs6000_tls_size = 16;
1594 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1595 rs6000_tls_size = 32;
1596 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1597 rs6000_tls_size = 64;
1598 else
1599 error ("bad value `%s' for -mtls-size switch", rs6000_tls_size_string);
1602 void
1603 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1607 /* Do anything needed at the start of the asm file. */
1609 static void
1610 rs6000_file_start (void)
1612 size_t i;
1613 char buffer[80];
1614 const char *start = buffer;
1615 struct rs6000_cpu_select *ptr;
1616 const char *default_cpu = TARGET_CPU_DEFAULT;
1617 FILE *file = asm_out_file;
1619 default_file_start ();
1621 #ifdef TARGET_BI_ARCH
1622 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1623 default_cpu = 0;
1624 #endif
1626 if (flag_verbose_asm)
1628 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1629 rs6000_select[0].string = default_cpu;
1631 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1633 ptr = &rs6000_select[i];
1634 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1636 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1637 start = "";
1641 #ifdef USING_ELFOS_H
1642 switch (rs6000_sdata)
1644 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1645 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1646 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1647 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1650 if (rs6000_sdata && g_switch_value)
1652 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1653 g_switch_value);
1654 start = "";
1656 #endif
1658 if (*start == '\0')
1659 putc ('\n', file);
1663 /* Return nonzero if this function is known to have a null epilogue. */
1666 direct_return (void)
1668 if (reload_completed)
1670 rs6000_stack_t *info = rs6000_stack_info ();
1672 if (info->first_gp_reg_save == 32
1673 && info->first_fp_reg_save == 64
1674 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1675 && ! info->lr_save_p
1676 && ! info->cr_save_p
1677 && info->vrsave_mask == 0
1678 && ! info->push_p)
1679 return 1;
1682 return 0;
1685 /* Returns 1 always. */
1688 any_operand (rtx op ATTRIBUTE_UNUSED,
1689 enum machine_mode mode ATTRIBUTE_UNUSED)
1691 return 1;
1694 /* Returns 1 always. */
1697 any_parallel_operand (rtx op ATTRIBUTE_UNUSED,
1698 enum machine_mode mode ATTRIBUTE_UNUSED)
1700 return 1;
1703 /* Returns 1 if op is the count register. */
1706 count_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1708 if (GET_CODE (op) != REG)
1709 return 0;
1711 if (REGNO (op) == COUNT_REGISTER_REGNUM)
1712 return 1;
1714 if (REGNO (op) > FIRST_PSEUDO_REGISTER)
1715 return 1;
1717 return 0;
1720 /* Returns 1 if op is an altivec register. */
1723 altivec_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1726 return (register_operand (op, mode)
1727 && (GET_CODE (op) != REG
1728 || REGNO (op) > FIRST_PSEUDO_REGISTER
1729 || ALTIVEC_REGNO_P (REGNO (op))));
1733 xer_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1735 if (GET_CODE (op) != REG)
1736 return 0;
1738 if (XER_REGNO_P (REGNO (op)))
1739 return 1;
1741 return 0;
1744 /* Return 1 if OP is a signed 8-bit constant. Int multiplication
1745 by such constants completes more quickly. */
1748 s8bit_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1750 return ( GET_CODE (op) == CONST_INT
1751 && (INTVAL (op) >= -128 && INTVAL (op) <= 127));
1754 /* Return 1 if OP is a constant that can fit in a D field. */
1757 short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1759 return (GET_CODE (op) == CONST_INT
1760 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'));
1763 /* Similar for an unsigned D field. */
1766 u_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1768 return (GET_CODE (op) == CONST_INT
1769 && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K'));
1772 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
1775 non_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1777 return (GET_CODE (op) == CONST_INT
1778 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000);
1781 /* Returns 1 if OP is a CONST_INT that is a positive value
1782 and an exact power of 2. */
1785 exact_log2_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1787 return (GET_CODE (op) == CONST_INT
1788 && INTVAL (op) > 0
1789 && exact_log2 (INTVAL (op)) >= 0);
1792 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
1793 ctr, or lr). */
1796 gpc_reg_operand (rtx op, enum machine_mode mode)
1798 return (register_operand (op, mode)
1799 && (GET_CODE (op) != REG
1800 || (REGNO (op) >= ARG_POINTER_REGNUM
1801 && !XER_REGNO_P (REGNO (op)))
1802 || REGNO (op) < MQ_REGNO));
1805 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1806 CR field. */
1809 cc_reg_operand (rtx op, enum machine_mode mode)
1811 return (register_operand (op, mode)
1812 && (GET_CODE (op) != REG
1813 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1814 || CR_REGNO_P (REGNO (op))));
1817 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1818 CR field that isn't CR0. */
1821 cc_reg_not_cr0_operand (rtx op, enum machine_mode mode)
1823 return (register_operand (op, mode)
1824 && (GET_CODE (op) != REG
1825 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1826 || CR_REGNO_NOT_CR0_P (REGNO (op))));
1829 /* Returns 1 if OP is either a constant integer valid for a D-field or
1830 a non-special register. If a register, it must be in the proper
1831 mode unless MODE is VOIDmode. */
1834 reg_or_short_operand (rtx op, enum machine_mode mode)
1836 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1839 /* Similar, except check if the negation of the constant would be
1840 valid for a D-field. Don't allow a constant zero, since all the
1841 patterns that call this predicate use "addic r1,r2,-constant" on
1842 a constant value to set a carry when r2 is greater or equal to
1843 "constant". That doesn't work for zero. */
1846 reg_or_neg_short_operand (rtx op, enum machine_mode mode)
1848 if (GET_CODE (op) == CONST_INT)
1849 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P') && INTVAL (op) != 0;
1851 return gpc_reg_operand (op, mode);
1854 /* Returns 1 if OP is either a constant integer valid for a DS-field or
1855 a non-special register. If a register, it must be in the proper
1856 mode unless MODE is VOIDmode. */
1859 reg_or_aligned_short_operand (rtx op, enum machine_mode mode)
1861 if (gpc_reg_operand (op, mode))
1862 return 1;
1863 else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3))
1864 return 1;
1866 return 0;
1870 /* Return 1 if the operand is either a register or an integer whose
1871 high-order 16 bits are zero. */
1874 reg_or_u_short_operand (rtx op, enum machine_mode mode)
1876 return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1879 /* Return 1 is the operand is either a non-special register or ANY
1880 constant integer. */
1883 reg_or_cint_operand (rtx op, enum machine_mode mode)
1885 return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode));
1888 /* Return 1 is the operand is either a non-special register or ANY
1889 32-bit signed constant integer. */
1892 reg_or_arith_cint_operand (rtx op, enum machine_mode mode)
1894 return (gpc_reg_operand (op, mode)
1895 || (GET_CODE (op) == CONST_INT
1896 #if HOST_BITS_PER_WIDE_INT != 32
1897 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000)
1898 < (unsigned HOST_WIDE_INT) 0x100000000ll)
1899 #endif
1903 /* Return 1 is the operand is either a non-special register or a 32-bit
1904 signed constant integer valid for 64-bit addition. */
1907 reg_or_add_cint64_operand (rtx op, enum machine_mode mode)
1909 return (gpc_reg_operand (op, mode)
1910 || (GET_CODE (op) == CONST_INT
1911 #if HOST_BITS_PER_WIDE_INT == 32
1912 && INTVAL (op) < 0x7fff8000
1913 #else
1914 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
1915 < 0x100000000ll)
1916 #endif
1920 /* Return 1 is the operand is either a non-special register or a 32-bit
1921 signed constant integer valid for 64-bit subtraction. */
1924 reg_or_sub_cint64_operand (rtx op, enum machine_mode mode)
1926 return (gpc_reg_operand (op, mode)
1927 || (GET_CODE (op) == CONST_INT
1928 #if HOST_BITS_PER_WIDE_INT == 32
1929 && (- INTVAL (op)) < 0x7fff8000
1930 #else
1931 && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
1932 < 0x100000000ll)
1933 #endif
1937 /* Return 1 is the operand is either a non-special register or ANY
1938 32-bit unsigned constant integer. */
1941 reg_or_logical_cint_operand (rtx op, enum machine_mode mode)
1943 if (GET_CODE (op) == CONST_INT)
1945 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
1947 if (GET_MODE_BITSIZE (mode) <= 32)
1948 abort ();
1950 if (INTVAL (op) < 0)
1951 return 0;
1954 return ((INTVAL (op) & GET_MODE_MASK (mode)
1955 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0);
1957 else if (GET_CODE (op) == CONST_DOUBLE)
1959 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1960 || mode != DImode)
1961 abort ();
1963 return CONST_DOUBLE_HIGH (op) == 0;
1965 else
1966 return gpc_reg_operand (op, mode);
1969 /* Return 1 if the operand is an operand that can be loaded via the GOT. */
1972 got_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1974 return (GET_CODE (op) == SYMBOL_REF
1975 || GET_CODE (op) == CONST
1976 || GET_CODE (op) == LABEL_REF);
1979 /* Return 1 if the operand is a simple references that can be loaded via
1980 the GOT (labels involving addition aren't allowed). */
1983 got_no_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1985 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF);
1988 /* Return the number of instructions it takes to form a constant in an
1989 integer register. */
1991 static int
1992 num_insns_constant_wide (HOST_WIDE_INT value)
1994 /* signed constant loadable with {cal|addi} */
1995 if (CONST_OK_FOR_LETTER_P (value, 'I'))
1996 return 1;
1998 /* constant loadable with {cau|addis} */
1999 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
2000 return 1;
2002 #if HOST_BITS_PER_WIDE_INT == 64
2003 else if (TARGET_POWERPC64)
2005 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2006 HOST_WIDE_INT high = value >> 31;
2008 if (high == 0 || high == -1)
2009 return 2;
2011 high >>= 1;
2013 if (low == 0)
2014 return num_insns_constant_wide (high) + 1;
2015 else
2016 return (num_insns_constant_wide (high)
2017 + num_insns_constant_wide (low) + 1);
2019 #endif
2021 else
2022 return 2;
2026 num_insns_constant (rtx op, enum machine_mode mode)
2028 if (GET_CODE (op) == CONST_INT)
2030 #if HOST_BITS_PER_WIDE_INT == 64
2031 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2032 && mask64_operand (op, mode))
2033 return 2;
2034 else
2035 #endif
2036 return num_insns_constant_wide (INTVAL (op));
2039 else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
2041 long l;
2042 REAL_VALUE_TYPE rv;
2044 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2045 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2046 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2049 else if (GET_CODE (op) == CONST_DOUBLE)
2051 HOST_WIDE_INT low;
2052 HOST_WIDE_INT high;
2053 long l[2];
2054 REAL_VALUE_TYPE rv;
2055 int endian = (WORDS_BIG_ENDIAN == 0);
2057 if (mode == VOIDmode || mode == DImode)
2059 high = CONST_DOUBLE_HIGH (op);
2060 low = CONST_DOUBLE_LOW (op);
2062 else
2064 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2065 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2066 high = l[endian];
2067 low = l[1 - endian];
2070 if (TARGET_32BIT)
2071 return (num_insns_constant_wide (low)
2072 + num_insns_constant_wide (high));
2074 else
2076 if (high == 0 && low >= 0)
2077 return num_insns_constant_wide (low);
2079 else if (high == -1 && low < 0)
2080 return num_insns_constant_wide (low);
2082 else if (mask64_operand (op, mode))
2083 return 2;
2085 else if (low == 0)
2086 return num_insns_constant_wide (high) + 1;
2088 else
2089 return (num_insns_constant_wide (high)
2090 + num_insns_constant_wide (low) + 1);
2094 else
2095 abort ();
2098 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a
2099 register with one instruction per word. We only do this if we can
2100 safely read CONST_DOUBLE_{LOW,HIGH}. */
2103 easy_fp_constant (rtx op, enum machine_mode mode)
2105 if (GET_CODE (op) != CONST_DOUBLE
2106 || GET_MODE (op) != mode
2107 || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
2108 return 0;
2110 /* Consider all constants with -msoft-float to be easy. */
2111 if ((TARGET_SOFT_FLOAT || !TARGET_FPRS)
2112 && mode != DImode)
2113 return 1;
2115 /* If we are using V.4 style PIC, consider all constants to be hard. */
2116 if (flag_pic && DEFAULT_ABI == ABI_V4)
2117 return 0;
2119 #ifdef TARGET_RELOCATABLE
2120 /* Similarly if we are using -mrelocatable, consider all constants
2121 to be hard. */
2122 if (TARGET_RELOCATABLE)
2123 return 0;
2124 #endif
2126 if (mode == TFmode)
2128 long k[4];
2129 REAL_VALUE_TYPE rv;
2131 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2132 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
2134 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
2135 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
2136 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
2137 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
2140 else if (mode == DFmode)
2142 long k[2];
2143 REAL_VALUE_TYPE rv;
2145 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2146 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
2148 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
2149 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
2152 else if (mode == SFmode)
2154 long l;
2155 REAL_VALUE_TYPE rv;
2157 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2158 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2160 return num_insns_constant_wide (l) == 1;
2163 else if (mode == DImode)
2164 return ((TARGET_POWERPC64
2165 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
2166 || (num_insns_constant (op, DImode) <= 2));
2168 else if (mode == SImode)
2169 return 1;
2170 else
2171 abort ();
2174 /* Returns the constant for the splat instruction, if exists. */
2176 static int
2177 easy_vector_splat_const (int cst, enum machine_mode mode)
2179 switch (mode)
2181 case V4SImode:
2182 if (EASY_VECTOR_15 (cst)
2183 || EASY_VECTOR_15_ADD_SELF (cst))
2184 return cst;
2185 if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
2186 break;
2187 cst = cst >> 16;
2188 case V8HImode:
2189 if (EASY_VECTOR_15 (cst)
2190 || EASY_VECTOR_15_ADD_SELF (cst))
2191 return cst;
2192 if ((cst & 0xff) != ((cst >> 8) & 0xff))
2193 break;
2194 cst = cst >> 8;
2195 case V16QImode:
2196 if (EASY_VECTOR_15 (cst)
2197 || EASY_VECTOR_15_ADD_SELF (cst))
2198 return cst;
2199 default:
2200 break;
2202 return 0;
2206 /* Return nonzero if all elements of a vector have the same value. */
2208 static int
2209 easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2211 int units, i, cst;
2213 units = CONST_VECTOR_NUNITS (op);
2215 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
2216 for (i = 1; i < units; ++i)
2217 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
2218 break;
2219 if (i == units && easy_vector_splat_const (cst, mode))
2220 return 1;
2221 return 0;
2224 /* Return 1 if the operand is a CONST_INT and can be put into a
2225 register without using memory. */
2228 easy_vector_constant (rtx op, enum machine_mode mode)
2230 int cst, cst2;
2232 if (GET_CODE (op) != CONST_VECTOR
2233 || (!TARGET_ALTIVEC
2234 && !TARGET_SPE))
2235 return 0;
2237 if (zero_constant (op, mode)
2238 && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
2239 || (TARGET_SPE && SPE_VECTOR_MODE (mode))))
2240 return 1;
2242 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
2243 return 0;
2245 if (TARGET_SPE && mode == V1DImode)
2246 return 0;
2248 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
2249 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
2251 /* Limit SPE vectors to 15 bits signed. These we can generate with:
2252 li r0, CONSTANT1
2253 evmergelo r0, r0, r0
2254 li r0, CONSTANT2
2256 I don't know how efficient it would be to allow bigger constants,
2257 considering we'll have an extra 'ori' for every 'li'. I doubt 5
2258 instructions is better than a 64-bit memory load, but I don't
2259 have the e500 timing specs. */
2260 if (TARGET_SPE && mode == V2SImode
2261 && cst >= -0x7fff && cst <= 0x7fff
2262 && cst2 >= -0x7fff && cst2 <= 0x7fff)
2263 return 1;
2265 if (TARGET_ALTIVEC
2266 && easy_vector_same (op, mode))
2268 cst = easy_vector_splat_const (cst, mode);
2269 if (EASY_VECTOR_15_ADD_SELF (cst)
2270 || EASY_VECTOR_15 (cst))
2271 return 1;
2273 return 0;
2276 /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. */
2279 easy_vector_constant_add_self (rtx op, enum machine_mode mode)
2281 int cst;
2282 if (TARGET_ALTIVEC
2283 && GET_CODE (op) == CONST_VECTOR
2284 && easy_vector_same (op, mode))
2286 cst = easy_vector_splat_const (INTVAL (CONST_VECTOR_ELT (op, 0)), mode);
2287 if (EASY_VECTOR_15_ADD_SELF (cst))
2288 return 1;
2290 return 0;
2293 /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
2296 gen_easy_vector_constant_add_self (rtx op)
2298 int i, units;
2299 rtvec v;
2300 units = GET_MODE_NUNITS (GET_MODE (op));
2301 v = rtvec_alloc (units);
2303 for (i = 0; i < units; i++)
2304 RTVEC_ELT (v, i) =
2305 GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1);
2306 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v);
2309 const char *
2310 output_vec_const_move (rtx *operands)
2312 int cst, cst2;
2313 enum machine_mode mode;
2314 rtx dest, vec;
2316 dest = operands[0];
2317 vec = operands[1];
2319 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2320 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2321 mode = GET_MODE (dest);
2323 if (TARGET_ALTIVEC)
2325 if (zero_constant (vec, mode))
2326 return "vxor %0,%0,%0";
2327 else if (easy_vector_constant (vec, mode))
2329 operands[1] = GEN_INT (cst);
2330 switch (mode)
2332 case V4SImode:
2333 if (EASY_VECTOR_15 (cst))
2335 operands[1] = GEN_INT (cst);
2336 return "vspltisw %0,%1";
2338 else if (EASY_VECTOR_15_ADD_SELF (cst))
2339 return "#";
2340 cst = cst >> 16;
2341 case V8HImode:
2342 if (EASY_VECTOR_15 (cst))
2344 operands[1] = GEN_INT (cst);
2345 return "vspltish %0,%1";
2347 else if (EASY_VECTOR_15_ADD_SELF (cst))
2348 return "#";
2349 cst = cst >> 8;
2350 case V16QImode:
2351 if (EASY_VECTOR_15 (cst))
2353 operands[1] = GEN_INT (cst);
2354 return "vspltisb %0,%1";
2356 else if (EASY_VECTOR_15_ADD_SELF (cst))
2357 return "#";
2358 default:
2359 abort ();
2362 else
2363 abort ();
2366 if (TARGET_SPE)
2368 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2369 pattern of V1DI, V4HI, and V2SF.
2371 FIXME: We should probably return # and add post reload
2372 splitters for these, but this way is so easy ;-).
2374 operands[1] = GEN_INT (cst);
2375 operands[2] = GEN_INT (cst2);
2376 if (cst == cst2)
2377 return "li %0,%1\n\tevmergelo %0,%0,%0";
2378 else
2379 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2382 abort ();
2385 /* Return 1 if the operand is the constant 0. This works for scalars
2386 as well as vectors. */
2388 zero_constant (rtx op, enum machine_mode mode)
2390 return op == CONST0_RTX (mode);
2393 /* Return 1 if the operand is 0.0. */
2395 zero_fp_constant (rtx op, enum machine_mode mode)
2397 return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
2400 /* Return 1 if the operand is in volatile memory. Note that during
2401 the RTL generation phase, memory_operand does not return TRUE for
2402 volatile memory references. So this function allows us to
2403 recognize volatile references where its safe. */
2406 volatile_mem_operand (rtx op, enum machine_mode mode)
2408 if (GET_CODE (op) != MEM)
2409 return 0;
2411 if (!MEM_VOLATILE_P (op))
2412 return 0;
2414 if (mode != GET_MODE (op))
2415 return 0;
2417 if (reload_completed)
2418 return memory_operand (op, mode);
2420 if (reload_in_progress)
2421 return strict_memory_address_p (mode, XEXP (op, 0));
2423 return memory_address_p (mode, XEXP (op, 0));
2426 /* Return 1 if the operand is an offsettable memory operand. */
2429 offsettable_mem_operand (rtx op, enum machine_mode mode)
2431 return ((GET_CODE (op) == MEM)
2432 && offsettable_address_p (reload_completed || reload_in_progress,
2433 mode, XEXP (op, 0)));
2436 /* Return 1 if the operand is either an easy FP constant (see above) or
2437 memory. */
2440 mem_or_easy_const_operand (rtx op, enum machine_mode mode)
2442 return memory_operand (op, mode) || easy_fp_constant (op, mode);
2445 /* Return 1 if the operand is either a non-special register or an item
2446 that can be used as the operand of a `mode' add insn. */
2449 add_operand (rtx op, enum machine_mode mode)
2451 if (GET_CODE (op) == CONST_INT)
2452 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
2453 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
2455 return gpc_reg_operand (op, mode);
2458 /* Return 1 if OP is a constant but not a valid add_operand. */
2461 non_add_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2463 return (GET_CODE (op) == CONST_INT
2464 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
2465 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
2468 /* Return 1 if the operand is a non-special register or a constant that
2469 can be used as the operand of an OR or XOR insn on the RS/6000. */
2472 logical_operand (rtx op, enum machine_mode mode)
2474 HOST_WIDE_INT opl, oph;
2476 if (gpc_reg_operand (op, mode))
2477 return 1;
2479 if (GET_CODE (op) == CONST_INT)
2481 opl = INTVAL (op) & GET_MODE_MASK (mode);
2483 #if HOST_BITS_PER_WIDE_INT <= 32
2484 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
2485 return 0;
2486 #endif
2488 else if (GET_CODE (op) == CONST_DOUBLE)
2490 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
2491 abort ();
2493 opl = CONST_DOUBLE_LOW (op);
2494 oph = CONST_DOUBLE_HIGH (op);
2495 if (oph != 0)
2496 return 0;
2498 else
2499 return 0;
2501 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
2502 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
2505 /* Return 1 if C is a constant that is not a logical operand (as
2506 above), but could be split into one. */
2509 non_logical_cint_operand (rtx op, enum machine_mode mode)
2511 return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
2512 && ! logical_operand (op, mode)
2513 && reg_or_logical_cint_operand (op, mode));
2516 /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
2517 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
2518 Reject all ones and all zeros, since these should have been optimized
2519 away and confuse the making of MB and ME. */
2522 mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2524 HOST_WIDE_INT c, lsb;
2526 if (GET_CODE (op) != CONST_INT)
2527 return 0;
2529 c = INTVAL (op);
2531 /* Fail in 64-bit mode if the mask wraps around because the upper
2532 32-bits of the mask will all be 1s, contrary to GCC's internal view. */
2533 if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
2534 return 0;
2536 /* We don't change the number of transitions by inverting,
2537 so make sure we start with the LS bit zero. */
2538 if (c & 1)
2539 c = ~c;
2541 /* Reject all zeros or all ones. */
2542 if (c == 0)
2543 return 0;
2545 /* Find the first transition. */
2546 lsb = c & -c;
2548 /* Invert to look for a second transition. */
2549 c = ~c;
2551 /* Erase first transition. */
2552 c &= -lsb;
2554 /* Find the second transition (if any). */
2555 lsb = c & -c;
2557 /* Match if all the bits above are 1's (or c is zero). */
2558 return c == -lsb;
2561 /* Return 1 for the PowerPC64 rlwinm corner case. */
2564 mask_operand_wrap (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2566 HOST_WIDE_INT c, lsb;
2568 if (GET_CODE (op) != CONST_INT)
2569 return 0;
2571 c = INTVAL (op);
2573 if ((c & 0x80000001) != 0x80000001)
2574 return 0;
2576 c = ~c;
2577 if (c == 0)
2578 return 0;
2580 lsb = c & -c;
2581 c = ~c;
2582 c &= -lsb;
2583 lsb = c & -c;
2584 return c == -lsb;
2587 /* Return 1 if the operand is a constant that is a PowerPC64 mask.
2588 It is if there are no more than one 1->0 or 0->1 transitions.
2589 Reject all zeros, since zero should have been optimized away and
2590 confuses the making of MB and ME. */
2593 mask64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2595 if (GET_CODE (op) == CONST_INT)
2597 HOST_WIDE_INT c, lsb;
2599 c = INTVAL (op);
2601 /* Reject all zeros. */
2602 if (c == 0)
2603 return 0;
2605 /* We don't change the number of transitions by inverting,
2606 so make sure we start with the LS bit zero. */
2607 if (c & 1)
2608 c = ~c;
2610 /* Find the transition, and check that all bits above are 1's. */
2611 lsb = c & -c;
2613 /* Match if all the bits above are 1's (or c is zero). */
2614 return c == -lsb;
2616 return 0;
2619 /* Like mask64_operand, but allow up to three transitions. This
2620 predicate is used by insn patterns that generate two rldicl or
2621 rldicr machine insns. */
2624 mask64_2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2626 if (GET_CODE (op) == CONST_INT)
2628 HOST_WIDE_INT c, lsb;
2630 c = INTVAL (op);
2632 /* Disallow all zeros. */
2633 if (c == 0)
2634 return 0;
2636 /* We don't change the number of transitions by inverting,
2637 so make sure we start with the LS bit zero. */
2638 if (c & 1)
2639 c = ~c;
2641 /* Find the first transition. */
2642 lsb = c & -c;
2644 /* Invert to look for a second transition. */
2645 c = ~c;
2647 /* Erase first transition. */
2648 c &= -lsb;
2650 /* Find the second transition. */
2651 lsb = c & -c;
2653 /* Invert to look for a third transition. */
2654 c = ~c;
2656 /* Erase second transition. */
2657 c &= -lsb;
2659 /* Find the third transition (if any). */
2660 lsb = c & -c;
2662 /* Match if all the bits above are 1's (or c is zero). */
2663 return c == -lsb;
2665 return 0;
2668 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2669 implement ANDing by the mask IN. */
2670 void
2671 build_mask64_2_operands (rtx in, rtx *out)
2673 #if HOST_BITS_PER_WIDE_INT >= 64
2674 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2675 int shift;
2677 if (GET_CODE (in) != CONST_INT)
2678 abort ();
2680 c = INTVAL (in);
2681 if (c & 1)
2683 /* Assume c initially something like 0x00fff000000fffff. The idea
2684 is to rotate the word so that the middle ^^^^^^ group of zeros
2685 is at the MS end and can be cleared with an rldicl mask. We then
2686 rotate back and clear off the MS ^^ group of zeros with a
2687 second rldicl. */
2688 c = ~c; /* c == 0xff000ffffff00000 */
2689 lsb = c & -c; /* lsb == 0x0000000000100000 */
2690 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2691 c = ~c; /* c == 0x00fff000000fffff */
2692 c &= -lsb; /* c == 0x00fff00000000000 */
2693 lsb = c & -c; /* lsb == 0x0000100000000000 */
2694 c = ~c; /* c == 0xff000fffffffffff */
2695 c &= -lsb; /* c == 0xff00000000000000 */
2696 shift = 0;
2697 while ((lsb >>= 1) != 0)
2698 shift++; /* shift == 44 on exit from loop */
2699 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2700 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2701 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2703 else
2705 /* Assume c initially something like 0xff000f0000000000. The idea
2706 is to rotate the word so that the ^^^ middle group of zeros
2707 is at the LS end and can be cleared with an rldicr mask. We then
2708 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2709 a second rldicr. */
2710 lsb = c & -c; /* lsb == 0x0000010000000000 */
2711 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2712 c = ~c; /* c == 0x00fff0ffffffffff */
2713 c &= -lsb; /* c == 0x00fff00000000000 */
2714 lsb = c & -c; /* lsb == 0x0000100000000000 */
2715 c = ~c; /* c == 0xff000fffffffffff */
2716 c &= -lsb; /* c == 0xff00000000000000 */
2717 shift = 0;
2718 while ((lsb >>= 1) != 0)
2719 shift++; /* shift == 44 on exit from loop */
2720 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2721 m1 >>= shift; /* m1 == 0x0000000000000fff */
2722 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2725 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2726 masks will be all 1's. We are guaranteed more than one transition. */
2727 out[0] = GEN_INT (64 - shift);
2728 out[1] = GEN_INT (m1);
2729 out[2] = GEN_INT (shift);
2730 out[3] = GEN_INT (m2);
2731 #else
2732 (void)in;
2733 (void)out;
2734 abort ();
2735 #endif
2738 /* Return 1 if the operand is either a non-special register or a constant
2739 that can be used as the operand of a PowerPC64 logical AND insn. */
2742 and64_operand (rtx op, enum machine_mode mode)
2744 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2745 return (gpc_reg_operand (op, mode) || mask64_operand (op, mode));
2747 return (logical_operand (op, mode) || mask64_operand (op, mode));
2750 /* Like the above, but also match constants that can be implemented
2751 with two rldicl or rldicr insns. */
2754 and64_2_operand (rtx op, enum machine_mode mode)
2756 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2757 return gpc_reg_operand (op, mode) || mask64_2_operand (op, mode);
2759 return logical_operand (op, mode) || mask64_2_operand (op, mode);
2762 /* Return 1 if the operand is either a non-special register or a
2763 constant that can be used as the operand of an RS/6000 logical AND insn. */
2766 and_operand (rtx op, enum machine_mode mode)
2768 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2769 return (gpc_reg_operand (op, mode) || mask_operand (op, mode));
2771 return (logical_operand (op, mode) || mask_operand (op, mode));
2774 /* Return 1 if the operand is a general register or memory operand. */
2777 reg_or_mem_operand (rtx op, enum machine_mode mode)
2779 return (gpc_reg_operand (op, mode)
2780 || memory_operand (op, mode)
2781 || macho_lo_sum_memory_operand (op, mode)
2782 || volatile_mem_operand (op, mode));
2785 /* Return 1 if the operand is a general register or memory operand without
2786 pre_inc or pre_dec which produces invalid form of PowerPC lwa
2787 instruction. */
2790 lwa_operand (rtx op, enum machine_mode mode)
2792 rtx inner = op;
2794 if (reload_completed && GET_CODE (inner) == SUBREG)
2795 inner = SUBREG_REG (inner);
2797 return gpc_reg_operand (inner, mode)
2798 || (memory_operand (inner, mode)
2799 && GET_CODE (XEXP (inner, 0)) != PRE_INC
2800 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
2801 && (GET_CODE (XEXP (inner, 0)) != PLUS
2802 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
2803 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
2806 /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */
2809 symbol_ref_operand (rtx op, enum machine_mode mode)
2811 if (mode != VOIDmode && GET_MODE (op) != mode)
2812 return 0;
2814 return (GET_CODE (op) == SYMBOL_REF
2815 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)));
2818 /* Return 1 if the operand, used inside a MEM, is a valid first argument
2819 to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */
2822 call_operand (rtx op, enum machine_mode mode)
2824 if (mode != VOIDmode && GET_MODE (op) != mode)
2825 return 0;
2827 return (GET_CODE (op) == SYMBOL_REF
2828 || (GET_CODE (op) == REG
2829 && (REGNO (op) == LINK_REGISTER_REGNUM
2830 || REGNO (op) == COUNT_REGISTER_REGNUM
2831 || REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2834 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
2835 this file. */
2838 current_file_function_operand (rtx op,
2839 enum machine_mode mode ATTRIBUTE_UNUSED)
2841 return (GET_CODE (op) == SYMBOL_REF
2842 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
2843 && (SYMBOL_REF_LOCAL_P (op)
2844 || (op == XEXP (DECL_RTL (current_function_decl), 0))));
2847 /* Return 1 if this operand is a valid input for a move insn. */
2850 input_operand (rtx op, enum machine_mode mode)
2852 /* Memory is always valid. */
2853 if (memory_operand (op, mode))
2854 return 1;
2856 /* For floating-point, easy constants are valid. */
2857 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2858 && CONSTANT_P (op)
2859 && easy_fp_constant (op, mode))
2860 return 1;
2862 /* Allow any integer constant. */
2863 if (GET_MODE_CLASS (mode) == MODE_INT
2864 && (GET_CODE (op) == CONST_INT
2865 || GET_CODE (op) == CONST_DOUBLE))
2866 return 1;
2868 /* Allow easy vector constants. */
2869 if (GET_CODE (op) == CONST_VECTOR
2870 && easy_vector_constant (op, mode))
2871 return 1;
2873 /* For floating-point or multi-word mode, the only remaining valid type
2874 is a register. */
2875 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2876 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
2877 return register_operand (op, mode);
2879 /* The only cases left are integral modes one word or smaller (we
2880 do not get called for MODE_CC values). These can be in any
2881 register. */
2882 if (register_operand (op, mode))
2883 return 1;
2885 /* A SYMBOL_REF referring to the TOC is valid. */
2886 if (legitimate_constant_pool_address_p (op))
2887 return 1;
2889 /* A constant pool expression (relative to the TOC) is valid */
2890 if (toc_relative_expr_p (op))
2891 return 1;
2893 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
2894 to be valid. */
2895 if (DEFAULT_ABI == ABI_V4
2896 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
2897 && small_data_operand (op, Pmode))
2898 return 1;
2900 return 0;
2904 /* Darwin, AIX increases natural record alignment to doubleword if the first
2905 field is an FP double while the FP fields remain word aligned. */
2907 unsigned int
2908 rs6000_special_round_type_align (tree type, int computed, int specified)
2910 tree field = TYPE_FIELDS (type);
2912 /* Skip all the static variables only if ABI is greater than
2913 1 or equal to 0. */
2914 while (field != NULL && TREE_CODE (field) == VAR_DECL)
2915 field = TREE_CHAIN (field);
2917 if (field == NULL || field == type || DECL_MODE (field) != DFmode)
2918 return MAX (computed, specified);
2920 return MAX (MAX (computed, specified), 64);
2923 /* Return 1 for an operand in small memory on V.4/eabi. */
2926 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2927 enum machine_mode mode ATTRIBUTE_UNUSED)
2929 #if TARGET_ELF
2930 rtx sym_ref;
2932 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2933 return 0;
2935 if (DEFAULT_ABI != ABI_V4)
2936 return 0;
2938 if (GET_CODE (op) == SYMBOL_REF)
2939 sym_ref = op;
2941 else if (GET_CODE (op) != CONST
2942 || GET_CODE (XEXP (op, 0)) != PLUS
2943 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2944 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2945 return 0;
2947 else
2949 rtx sum = XEXP (op, 0);
2950 HOST_WIDE_INT summand;
2952 /* We have to be careful here, because it is the referenced address
2953 that must be 32k from _SDA_BASE_, not just the symbol. */
2954 summand = INTVAL (XEXP (sum, 1));
2955 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2956 return 0;
2958 sym_ref = XEXP (sum, 0);
2961 return SYMBOL_REF_SMALL_P (sym_ref);
2962 #else
2963 return 0;
2964 #endif
2967 /* Return true, if operand is a memory operand and has a
2968 displacement divisible by 4. */
2971 word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2973 rtx addr;
2974 int off = 0;
2976 if (!memory_operand (op, mode))
2977 return 0;
2979 addr = XEXP (op, 0);
2980 if (GET_CODE (addr) == PLUS
2981 && GET_CODE (XEXP (addr, 0)) == REG
2982 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
2983 off = INTVAL (XEXP (addr, 1));
2985 return (off % 4) == 0;
2988 /* Return true if either operand is a general purpose register. */
2990 bool
2991 gpr_or_gpr_p (rtx op0, rtx op1)
2993 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2994 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2998 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3000 static int
3001 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
3003 switch (GET_CODE(op))
3005 case SYMBOL_REF:
3006 if (RS6000_SYMBOL_REF_TLS_P (op))
3007 return 0;
3008 else if (CONSTANT_POOL_ADDRESS_P (op))
3010 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
3012 *have_sym = 1;
3013 return 1;
3015 else
3016 return 0;
3018 else if (! strcmp (XSTR (op, 0), toc_label_name))
3020 *have_toc = 1;
3021 return 1;
3023 else
3024 return 0;
3025 case PLUS:
3026 case MINUS:
3027 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
3028 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
3029 case CONST:
3030 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
3031 case CONST_INT:
3032 return 1;
3033 default:
3034 return 0;
3038 static bool
3039 constant_pool_expr_p (rtx op)
3041 int have_sym = 0;
3042 int have_toc = 0;
3043 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
3046 static bool
3047 toc_relative_expr_p (rtx op)
3049 int have_sym = 0;
3050 int have_toc = 0;
3051 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
3054 bool
3055 legitimate_constant_pool_address_p (rtx x)
3057 return (TARGET_TOC
3058 && GET_CODE (x) == PLUS
3059 && GET_CODE (XEXP (x, 0)) == REG
3060 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
3061 && constant_pool_expr_p (XEXP (x, 1)));
3064 static bool
3065 legitimate_small_data_p (enum machine_mode mode, rtx x)
3067 return (DEFAULT_ABI == ABI_V4
3068 && !flag_pic && !TARGET_TOC
3069 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
3070 && small_data_operand (x, mode));
3073 /* SPE offset addressing is limited to 5-bits worth of double words. */
3074 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3076 bool
3077 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
3079 unsigned HOST_WIDE_INT offset, extra;
3081 if (GET_CODE (x) != PLUS)
3082 return false;
3083 if (GET_CODE (XEXP (x, 0)) != REG)
3084 return false;
3085 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3086 return false;
3087 if (legitimate_constant_pool_address_p (x))
3088 return true;
3089 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3090 return false;
3092 offset = INTVAL (XEXP (x, 1));
3093 extra = 0;
3094 switch (mode)
3096 case V16QImode:
3097 case V8HImode:
3098 case V4SFmode:
3099 case V4SImode:
3100 /* AltiVec vector modes. Only reg+reg addressing is valid here,
3101 which leaves the only valid constant offset of zero, which by
3102 canonicalization rules is also invalid. */
3103 return false;
3105 case V4HImode:
3106 case V2SImode:
3107 case V1DImode:
3108 case V2SFmode:
3109 /* SPE vector modes. */
3110 return SPE_CONST_OFFSET_OK (offset);
3112 case DFmode:
3113 case DImode:
3114 if (mode == DFmode || !TARGET_POWERPC64)
3115 extra = 4;
3116 else if (offset & 3)
3117 return false;
3118 break;
3120 case TFmode:
3121 case TImode:
3122 if (mode == TFmode || !TARGET_POWERPC64)
3123 extra = 12;
3124 else if (offset & 3)
3125 return false;
3126 else
3127 extra = 8;
3128 break;
3130 default:
3131 break;
3134 offset += 0x8000;
3135 return (offset < 0x10000) && (offset + extra < 0x10000);
3138 static bool
3139 legitimate_indexed_address_p (rtx x, int strict)
3141 rtx op0, op1;
3143 if (GET_CODE (x) != PLUS)
3144 return false;
3145 op0 = XEXP (x, 0);
3146 op1 = XEXP (x, 1);
3148 if (!REG_P (op0) || !REG_P (op1))
3149 return false;
3151 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
3152 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3153 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3154 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
3157 static inline bool
3158 legitimate_indirect_address_p (rtx x, int strict)
3160 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3163 static bool
3164 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3166 if (!TARGET_MACHO || !flag_pic
3167 || mode != SImode || GET_CODE(x) != MEM)
3168 return false;
3169 x = XEXP (x, 0);
3171 if (GET_CODE (x) != LO_SUM)
3172 return false;
3173 if (GET_CODE (XEXP (x, 0)) != REG)
3174 return false;
3175 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3176 return false;
3177 x = XEXP (x, 1);
3179 return CONSTANT_P (x);
3182 static bool
3183 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3185 if (GET_CODE (x) != LO_SUM)
3186 return false;
3187 if (GET_CODE (XEXP (x, 0)) != REG)
3188 return false;
3189 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3190 return false;
3191 x = XEXP (x, 1);
3193 if (TARGET_ELF || TARGET_MACHO)
3195 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3196 return false;
3197 if (TARGET_TOC)
3198 return false;
3199 if (GET_MODE_NUNITS (mode) != 1)
3200 return false;
3201 if (GET_MODE_BITSIZE (mode) > 64)
3202 return false;
3204 return CONSTANT_P (x);
3207 return false;
3211 /* Try machine-dependent ways of modifying an illegitimate address
3212 to be legitimate. If we find one, return the new, valid address.
3213 This is used from only one place: `memory_address' in explow.c.
3215 OLDX is the address as it was before break_out_memory_refs was
3216 called. In some cases it is useful to look at this to decide what
3217 needs to be done.
3219 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3221 It is always safe for this function to do nothing. It exists to
3222 recognize opportunities to optimize the output.
3224 On RS/6000, first check for the sum of a register with a constant
3225 integer that is out of range. If so, generate code to add the
3226 constant with the low-order 16 bits masked to the register and force
3227 this result into another register (this can be done with `cau').
3228 Then generate an address of REG+(CONST&0xffff), allowing for the
3229 possibility of bit 16 being a one.
3231 Then check for the sum of a register and something not constant, try to
3232 load the other things into a register and return the sum. */
3235 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3236 enum machine_mode mode)
3238 if (GET_CODE (x) == SYMBOL_REF)
3240 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3241 if (model != 0)
3242 return rs6000_legitimize_tls_address (x, model);
3245 if (GET_CODE (x) == PLUS
3246 && GET_CODE (XEXP (x, 0)) == REG
3247 && GET_CODE (XEXP (x, 1)) == CONST_INT
3248 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
3250 HOST_WIDE_INT high_int, low_int;
3251 rtx sum;
3252 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3253 high_int = INTVAL (XEXP (x, 1)) - low_int;
3254 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3255 GEN_INT (high_int)), 0);
3256 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3258 else if (GET_CODE (x) == PLUS
3259 && GET_CODE (XEXP (x, 0)) == REG
3260 && GET_CODE (XEXP (x, 1)) != CONST_INT
3261 && GET_MODE_NUNITS (mode) == 1
3262 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3263 || TARGET_POWERPC64
3264 || (mode != DFmode && mode != TFmode))
3265 && (TARGET_POWERPC64 || mode != DImode)
3266 && mode != TImode)
3268 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3269 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3271 else if (ALTIVEC_VECTOR_MODE (mode))
3273 rtx reg;
3275 /* Make sure both operands are registers. */
3276 if (GET_CODE (x) == PLUS)
3277 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3278 force_reg (Pmode, XEXP (x, 1)));
3280 reg = force_reg (Pmode, x);
3281 return reg;
3283 else if (SPE_VECTOR_MODE (mode))
3285 /* We accept [reg + reg] and [reg + OFFSET]. */
3287 if (GET_CODE (x) == PLUS)
3289 rtx op1 = XEXP (x, 0);
3290 rtx op2 = XEXP (x, 1);
3292 op1 = force_reg (Pmode, op1);
3294 if (GET_CODE (op2) != REG
3295 && (GET_CODE (op2) != CONST_INT
3296 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
3297 op2 = force_reg (Pmode, op2);
3299 return gen_rtx_PLUS (Pmode, op1, op2);
3302 return force_reg (Pmode, x);
3304 else if (TARGET_ELF
3305 && TARGET_32BIT
3306 && TARGET_NO_TOC
3307 && ! flag_pic
3308 && GET_CODE (x) != CONST_INT
3309 && GET_CODE (x) != CONST_DOUBLE
3310 && CONSTANT_P (x)
3311 && GET_MODE_NUNITS (mode) == 1
3312 && (GET_MODE_BITSIZE (mode) <= 32
3313 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
3315 rtx reg = gen_reg_rtx (Pmode);
3316 emit_insn (gen_elf_high (reg, x));
3317 return gen_rtx_LO_SUM (Pmode, reg, x);
3319 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3320 && ! flag_pic
3321 #if TARGET_MACHO
3322 && ! MACHO_DYNAMIC_NO_PIC_P
3323 #endif
3324 && GET_CODE (x) != CONST_INT
3325 && GET_CODE (x) != CONST_DOUBLE
3326 && CONSTANT_P (x)
3327 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3328 && mode != DImode
3329 && mode != TImode)
3331 rtx reg = gen_reg_rtx (Pmode);
3332 emit_insn (gen_macho_high (reg, x));
3333 return gen_rtx_LO_SUM (Pmode, reg, x);
3335 else if (TARGET_TOC
3336 && constant_pool_expr_p (x)
3337 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3339 return create_TOC_reference (x);
3341 else
3342 return NULL_RTX;
3345 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
3346 We need to emit DTP-relative relocations. */
3348 void
3349 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3351 switch (size)
3353 case 4:
3354 fputs ("\t.long\t", file);
3355 break;
3356 case 8:
3357 fputs (DOUBLE_INT_ASM_OP, file);
3358 break;
3359 default:
3360 abort ();
3362 output_addr_const (file, x);
3363 fputs ("@dtprel+0x8000", file);
3366 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3368 static GTY(()) rtx rs6000_tls_symbol;
3369 static rtx
3370 rs6000_tls_get_addr (void)
3372 if (!rs6000_tls_symbol)
3373 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3375 return rs6000_tls_symbol;
3378 /* Construct the SYMBOL_REF for TLS GOT references. */
3380 static GTY(()) rtx rs6000_got_symbol;
3381 static rtx
3382 rs6000_got_sym (void)
3384 if (!rs6000_got_symbol)
3386 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3387 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3388 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3391 return rs6000_got_symbol;
3394 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3395 this (thread-local) address. */
3397 static rtx
3398 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3400 rtx dest, insn;
3402 dest = gen_reg_rtx (Pmode);
3403 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3405 rtx tlsreg;
3407 if (TARGET_64BIT)
3409 tlsreg = gen_rtx_REG (Pmode, 13);
3410 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3412 else
3414 tlsreg = gen_rtx_REG (Pmode, 2);
3415 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3417 emit_insn (insn);
3419 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3421 rtx tlsreg, tmp;
3423 tmp = gen_reg_rtx (Pmode);
3424 if (TARGET_64BIT)
3426 tlsreg = gen_rtx_REG (Pmode, 13);
3427 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3429 else
3431 tlsreg = gen_rtx_REG (Pmode, 2);
3432 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3434 emit_insn (insn);
3435 if (TARGET_64BIT)
3436 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3437 else
3438 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3439 emit_insn (insn);
3441 else
3443 rtx r3, got, tga, tmp1, tmp2, eqv;
3445 if (TARGET_64BIT)
3446 got = gen_rtx_REG (Pmode, TOC_REGISTER);
3447 else
3449 if (flag_pic == 1)
3450 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3451 else
3453 rtx gsym = rs6000_got_sym ();
3454 got = gen_reg_rtx (Pmode);
3455 if (flag_pic == 0)
3456 rs6000_emit_move (got, gsym, Pmode);
3457 else
3459 char buf[30];
3460 static int tls_got_labelno = 0;
3461 rtx tempLR, lab, tmp3, mem;
3462 rtx first, last;
3464 ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++);
3465 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
3466 tempLR = gen_reg_rtx (Pmode);
3467 tmp1 = gen_reg_rtx (Pmode);
3468 tmp2 = gen_reg_rtx (Pmode);
3469 tmp3 = gen_reg_rtx (Pmode);
3470 mem = gen_const_mem (Pmode, tmp1);
3472 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab,
3473 gsym));
3474 emit_move_insn (tmp1, tempLR);
3475 emit_move_insn (tmp2, mem);
3476 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3477 last = emit_move_insn (got, tmp3);
3478 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
3479 REG_NOTES (last));
3480 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3481 REG_NOTES (first));
3482 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3483 REG_NOTES (last));
3488 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3490 r3 = gen_rtx_REG (Pmode, 3);
3491 if (TARGET_64BIT)
3492 insn = gen_tls_gd_64 (r3, got, addr);
3493 else
3494 insn = gen_tls_gd_32 (r3, got, addr);
3495 start_sequence ();
3496 emit_insn (insn);
3497 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3498 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3499 insn = emit_call_insn (insn);
3500 CONST_OR_PURE_CALL_P (insn) = 1;
3501 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3502 insn = get_insns ();
3503 end_sequence ();
3504 emit_libcall_block (insn, dest, r3, addr);
3506 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3508 r3 = gen_rtx_REG (Pmode, 3);
3509 if (TARGET_64BIT)
3510 insn = gen_tls_ld_64 (r3, got);
3511 else
3512 insn = gen_tls_ld_32 (r3, got);
3513 start_sequence ();
3514 emit_insn (insn);
3515 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3516 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3517 insn = emit_call_insn (insn);
3518 CONST_OR_PURE_CALL_P (insn) = 1;
3519 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3520 insn = get_insns ();
3521 end_sequence ();
3522 tmp1 = gen_reg_rtx (Pmode);
3523 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3524 UNSPEC_TLSLD);
3525 emit_libcall_block (insn, tmp1, r3, eqv);
3526 if (rs6000_tls_size == 16)
3528 if (TARGET_64BIT)
3529 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3530 else
3531 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3533 else if (rs6000_tls_size == 32)
3535 tmp2 = gen_reg_rtx (Pmode);
3536 if (TARGET_64BIT)
3537 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3538 else
3539 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3540 emit_insn (insn);
3541 if (TARGET_64BIT)
3542 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3543 else
3544 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3546 else
3548 tmp2 = gen_reg_rtx (Pmode);
3549 if (TARGET_64BIT)
3550 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3551 else
3552 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3553 emit_insn (insn);
3554 insn = gen_rtx_SET (Pmode, dest,
3555 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3557 emit_insn (insn);
3559 else
3561 /* IE, or 64 bit offset LE. */
3562 tmp2 = gen_reg_rtx (Pmode);
3563 if (TARGET_64BIT)
3564 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3565 else
3566 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3567 emit_insn (insn);
3568 if (TARGET_64BIT)
3569 insn = gen_tls_tls_64 (dest, tmp2, addr);
3570 else
3571 insn = gen_tls_tls_32 (dest, tmp2, addr);
3572 emit_insn (insn);
3576 return dest;
3579 /* Return 1 if X is a SYMBOL_REF for a TLS symbol. This is used in
3580 instruction definitions. */
3583 rs6000_tls_symbol_ref (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
3585 return RS6000_SYMBOL_REF_TLS_P (x);
3588 /* Return 1 if X contains a thread-local symbol. */
3590 bool
3591 rs6000_tls_referenced_p (rtx x)
3593 if (! TARGET_HAVE_TLS)
3594 return false;
3596 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3599 /* Return 1 if *X is a thread-local symbol. This is the same as
3600 rs6000_tls_symbol_ref except for the type of the unused argument. */
3602 static inline int
3603 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3605 return RS6000_SYMBOL_REF_TLS_P (*x);
3608 /* The convention appears to be to define this wherever it is used.
3609 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3610 is now used here. */
3611 #ifndef REG_MODE_OK_FOR_BASE_P
3612 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3613 #endif
3615 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3616 replace the input X, or the original X if no replacement is called for.
3617 The output parameter *WIN is 1 if the calling macro should goto WIN,
3618 0 if it should not.
3620 For RS/6000, we wish to handle large displacements off a base
3621 register by splitting the addend across an addiu/addis and the mem insn.
3622 This cuts number of extra insns needed from 3 to 1.
3624 On Darwin, we use this to generate code for floating point constants.
3625 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3626 The Darwin code is inside #if TARGET_MACHO because only then is
3627 machopic_function_base_name() defined. */
3629 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3630 int opnum, int type, int ind_levels ATTRIBUTE_UNUSED, int *win)
3632 /* We must recognize output that we have already generated ourselves. */
3633 if (GET_CODE (x) == PLUS
3634 && GET_CODE (XEXP (x, 0)) == PLUS
3635 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3636 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3637 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3639 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3640 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3641 opnum, (enum reload_type)type);
3642 *win = 1;
3643 return x;
3646 #if TARGET_MACHO
3647 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3648 && GET_CODE (x) == LO_SUM
3649 && GET_CODE (XEXP (x, 0)) == PLUS
3650 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3651 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3652 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3653 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3654 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3655 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3656 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3658 /* Result of previous invocation of this function on Darwin
3659 floating point constant. */
3660 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3661 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3662 opnum, (enum reload_type)type);
3663 *win = 1;
3664 return x;
3666 #endif
3667 if (GET_CODE (x) == PLUS
3668 && GET_CODE (XEXP (x, 0)) == REG
3669 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3670 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3671 && GET_CODE (XEXP (x, 1)) == CONST_INT
3672 && !SPE_VECTOR_MODE (mode)
3673 && !ALTIVEC_VECTOR_MODE (mode))
3675 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3676 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3677 HOST_WIDE_INT high
3678 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3680 /* Check for 32-bit overflow. */
3681 if (high + low != val)
3683 *win = 0;
3684 return x;
3687 /* Reload the high part into a base reg; leave the low part
3688 in the mem directly. */
3690 x = gen_rtx_PLUS (GET_MODE (x),
3691 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3692 GEN_INT (high)),
3693 GEN_INT (low));
3695 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3696 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3697 opnum, (enum reload_type)type);
3698 *win = 1;
3699 return x;
3701 #if TARGET_MACHO
3702 if (GET_CODE (x) == SYMBOL_REF
3703 && DEFAULT_ABI == ABI_DARWIN
3704 && !ALTIVEC_VECTOR_MODE (mode)
3705 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3706 /* Don't do this for TFmode, since the result isn't offsettable. */
3707 && mode != TFmode)
3709 if (flag_pic)
3711 rtx offset = gen_rtx_CONST (Pmode,
3712 gen_rtx_MINUS (Pmode, x,
3713 machopic_function_base_sym ()));
3714 x = gen_rtx_LO_SUM (GET_MODE (x),
3715 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3716 gen_rtx_HIGH (Pmode, offset)), offset);
3718 else
3719 x = gen_rtx_LO_SUM (GET_MODE (x),
3720 gen_rtx_HIGH (Pmode, x), x);
3722 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3723 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3724 opnum, (enum reload_type)type);
3725 *win = 1;
3726 return x;
3728 #endif
3729 if (TARGET_TOC
3730 && constant_pool_expr_p (x)
3731 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3733 (x) = create_TOC_reference (x);
3734 *win = 1;
3735 return x;
3737 *win = 0;
3738 return x;
3741 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3742 that is a valid memory address for an instruction.
3743 The MODE argument is the machine mode for the MEM expression
3744 that wants to use this address.
3746 On the RS/6000, there are four valid address: a SYMBOL_REF that
3747 refers to a constant pool entry of an address (or the sum of it
3748 plus a constant), a short (16-bit signed) constant plus a register,
3749 the sum of two registers, or a register indirect, possibly with an
3750 auto-increment. For DFmode and DImode with a constant plus register,
3751 we must ensure that both words are addressable or PowerPC64 with offset
3752 word aligned.
3754 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3755 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3756 adjacent memory cells are accessed by adding word-sized offsets
3757 during assembly output. */
3759 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3761 if (RS6000_SYMBOL_REF_TLS_P (x))
3762 return 0;
3763 if (legitimate_indirect_address_p (x, reg_ok_strict))
3764 return 1;
3765 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3766 && !ALTIVEC_VECTOR_MODE (mode)
3767 && !SPE_VECTOR_MODE (mode)
3768 && TARGET_UPDATE
3769 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3770 return 1;
3771 if (legitimate_small_data_p (mode, x))
3772 return 1;
3773 if (legitimate_constant_pool_address_p (x))
3774 return 1;
3775 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3776 if (! reg_ok_strict
3777 && GET_CODE (x) == PLUS
3778 && GET_CODE (XEXP (x, 0)) == REG
3779 && (XEXP (x, 0) == virtual_stack_vars_rtx
3780 || XEXP (x, 0) == arg_pointer_rtx)
3781 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3782 return 1;
3783 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3784 return 1;
3785 if (mode != TImode
3786 && mode != TFmode
3787 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3788 || TARGET_POWERPC64
3789 || (mode != DFmode && mode != TFmode))
3790 && (TARGET_POWERPC64 || mode != DImode)
3791 && legitimate_indexed_address_p (x, reg_ok_strict))
3792 return 1;
3793 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3794 return 1;
3795 return 0;
3798 /* Go to LABEL if ADDR (a legitimate address expression)
3799 has an effect that depends on the machine mode it is used for.
3801 On the RS/6000 this is true of all integral offsets (since AltiVec
3802 modes don't allow them) or is a pre-increment or decrement.
3804 ??? Except that due to conceptual problems in offsettable_address_p
3805 we can't really report the problems of integral offsets. So leave
3806 this assuming that the adjustable offset must be valid for the
3807 sub-words of a TFmode operand, which is what we had before. */
3809 bool
3810 rs6000_mode_dependent_address (rtx addr)
3812 switch (GET_CODE (addr))
3814 case PLUS:
3815 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3817 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3818 return val + 12 + 0x8000 >= 0x10000;
3820 break;
3822 case LO_SUM:
3823 return true;
3825 case PRE_INC:
3826 case PRE_DEC:
3827 return TARGET_UPDATE;
3829 default:
3830 break;
3833 return false;
3836 /* Return number of consecutive hard regs needed starting at reg REGNO
3837 to hold something of mode MODE.
3838 This is ordinarily the length in words of a value of mode MODE
3839 but can be less for certain modes in special long registers.
3841 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3842 scalar instructions. The upper 32 bits are only available to the
3843 SIMD instructions.
3845 POWER and PowerPC GPRs hold 32 bits worth;
3846 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3849 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3851 if (FP_REGNO_P (regno))
3852 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3854 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3855 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3857 if (ALTIVEC_REGNO_P (regno))
3858 return
3859 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3861 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3864 /* Change register usage conditional on target flags. */
3865 void
3866 rs6000_conditional_register_usage (void)
3868 int i;
3870 /* Set MQ register fixed (already call_used) if not POWER
3871 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3872 be allocated. */
3873 if (! TARGET_POWER)
3874 fixed_regs[64] = 1;
3876 /* 64-bit AIX reserves GPR13 for thread-private data. */
3877 if (TARGET_64BIT)
3878 fixed_regs[13] = call_used_regs[13]
3879 = call_really_used_regs[13] = 1;
3881 /* Conditionally disable FPRs. */
3882 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3883 for (i = 32; i < 64; i++)
3884 fixed_regs[i] = call_used_regs[i]
3885 = call_really_used_regs[i] = 1;
3887 if (DEFAULT_ABI == ABI_V4
3888 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3889 && flag_pic == 2)
3890 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3892 if (DEFAULT_ABI == ABI_V4
3893 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3894 && flag_pic == 1)
3895 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3896 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3897 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3899 if (DEFAULT_ABI == ABI_DARWIN
3900 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3901 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3902 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3903 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3904 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3906 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3907 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3908 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3910 if (TARGET_ALTIVEC)
3911 global_regs[VSCR_REGNO] = 1;
3913 if (TARGET_SPE)
3915 global_regs[SPEFSCR_REGNO] = 1;
3916 fixed_regs[FIXED_SCRATCH]
3917 = call_used_regs[FIXED_SCRATCH]
3918 = call_really_used_regs[FIXED_SCRATCH] = 1;
3921 if (! TARGET_ALTIVEC)
3923 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3924 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3925 call_really_used_regs[VRSAVE_REGNO] = 1;
3928 if (TARGET_ALTIVEC_ABI)
3929 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3930 call_used_regs[i] = call_really_used_regs[i] = 1;
3933 /* Try to output insns to set TARGET equal to the constant C if it can
3934 be done in less than N insns. Do all computations in MODE.
3935 Returns the place where the output has been placed if it can be
3936 done and the insns have been emitted. If it would take more than N
3937 insns, zero is returned and no insns and emitted. */
3940 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3941 rtx source, int n ATTRIBUTE_UNUSED)
3943 rtx result, insn, set;
3944 HOST_WIDE_INT c0, c1;
3946 if (mode == QImode || mode == HImode)
3948 if (dest == NULL)
3949 dest = gen_reg_rtx (mode);
3950 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3951 return dest;
3953 else if (mode == SImode)
3955 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3957 emit_insn (gen_rtx_SET (VOIDmode, result,
3958 GEN_INT (INTVAL (source)
3959 & (~ (HOST_WIDE_INT) 0xffff))));
3960 emit_insn (gen_rtx_SET (VOIDmode, dest,
3961 gen_rtx_IOR (SImode, result,
3962 GEN_INT (INTVAL (source) & 0xffff))));
3963 result = dest;
3965 else if (mode == DImode)
3967 if (GET_CODE (source) == CONST_INT)
3969 c0 = INTVAL (source);
3970 c1 = -(c0 < 0);
3972 else if (GET_CODE (source) == CONST_DOUBLE)
3974 #if HOST_BITS_PER_WIDE_INT >= 64
3975 c0 = CONST_DOUBLE_LOW (source);
3976 c1 = -(c0 < 0);
3977 #else
3978 c0 = CONST_DOUBLE_LOW (source);
3979 c1 = CONST_DOUBLE_HIGH (source);
3980 #endif
3982 else
3983 abort ();
3985 result = rs6000_emit_set_long_const (dest, c0, c1);
3987 else
3988 abort ();
3990 insn = get_last_insn ();
3991 set = single_set (insn);
3992 if (! CONSTANT_P (SET_SRC (set)))
3993 set_unique_reg_note (insn, REG_EQUAL, source);
3995 return result;
3998 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3999 fall back to a straight forward decomposition. We do this to avoid
4000 exponential run times encountered when looking for longer sequences
4001 with rs6000_emit_set_const. */
4002 static rtx
4003 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
4005 if (!TARGET_POWERPC64)
4007 rtx operand1, operand2;
4009 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4010 DImode);
4011 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
4012 DImode);
4013 emit_move_insn (operand1, GEN_INT (c1));
4014 emit_move_insn (operand2, GEN_INT (c2));
4016 else
4018 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4020 ud1 = c1 & 0xffff;
4021 ud2 = (c1 & 0xffff0000) >> 16;
4022 #if HOST_BITS_PER_WIDE_INT >= 64
4023 c2 = c1 >> 32;
4024 #endif
4025 ud3 = c2 & 0xffff;
4026 ud4 = (c2 & 0xffff0000) >> 16;
4028 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4029 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4031 if (ud1 & 0x8000)
4032 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4033 else
4034 emit_move_insn (dest, GEN_INT (ud1));
4037 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4038 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4040 if (ud2 & 0x8000)
4041 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4042 - 0x80000000));
4043 else
4044 emit_move_insn (dest, GEN_INT (ud2 << 16));
4045 if (ud1 != 0)
4046 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4048 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4049 || (ud4 == 0 && ! (ud3 & 0x8000)))
4051 if (ud3 & 0x8000)
4052 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4053 - 0x80000000));
4054 else
4055 emit_move_insn (dest, GEN_INT (ud3 << 16));
4057 if (ud2 != 0)
4058 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
4059 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
4060 if (ud1 != 0)
4061 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4063 else
4065 if (ud4 & 0x8000)
4066 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4067 - 0x80000000));
4068 else
4069 emit_move_insn (dest, GEN_INT (ud4 << 16));
4071 if (ud3 != 0)
4072 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
4074 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
4075 if (ud2 != 0)
4076 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
4077 GEN_INT (ud2 << 16)));
4078 if (ud1 != 0)
4079 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4082 return dest;
4085 /* Helper for the following. Get rid of [r+r] memory refs
4086 in cases where it won't work (TImode, TFmode). */
4088 static void
4089 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4091 if (GET_CODE (operands[0]) == MEM
4092 && GET_CODE (XEXP (operands[0], 0)) != REG
4093 && ! reload_in_progress)
4094 operands[0]
4095 = replace_equiv_address (operands[0],
4096 copy_addr_to_reg (XEXP (operands[0], 0)));
4098 if (GET_CODE (operands[1]) == MEM
4099 && GET_CODE (XEXP (operands[1], 0)) != REG
4100 && ! reload_in_progress)
4101 operands[1]
4102 = replace_equiv_address (operands[1],
4103 copy_addr_to_reg (XEXP (operands[1], 0)));
4106 /* Emit a move from SOURCE to DEST in mode MODE. */
4107 void
4108 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4110 rtx operands[2];
4111 operands[0] = dest;
4112 operands[1] = source;
4114 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4115 if (GET_CODE (operands[1]) == CONST_DOUBLE
4116 && ! FLOAT_MODE_P (mode)
4117 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4119 /* FIXME. This should never happen. */
4120 /* Since it seems that it does, do the safe thing and convert
4121 to a CONST_INT. */
4122 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4124 if (GET_CODE (operands[1]) == CONST_DOUBLE
4125 && ! FLOAT_MODE_P (mode)
4126 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
4127 && CONST_DOUBLE_LOW (operands[1]) >= 0)
4128 || (CONST_DOUBLE_HIGH (operands[1]) == -1
4129 && CONST_DOUBLE_LOW (operands[1]) < 0)))
4130 abort ();
4132 /* Check if GCC is setting up a block move that will end up using FP
4133 registers as temporaries. We must make sure this is acceptable. */
4134 if (GET_CODE (operands[0]) == MEM
4135 && GET_CODE (operands[1]) == MEM
4136 && mode == DImode
4137 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4138 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4139 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4140 ? 32 : MEM_ALIGN (operands[0])))
4141 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4142 ? 32
4143 : MEM_ALIGN (operands[1]))))
4144 && ! MEM_VOLATILE_P (operands [0])
4145 && ! MEM_VOLATILE_P (operands [1]))
4147 emit_move_insn (adjust_address (operands[0], SImode, 0),
4148 adjust_address (operands[1], SImode, 0));
4149 emit_move_insn (adjust_address (operands[0], SImode, 4),
4150 adjust_address (operands[1], SImode, 4));
4151 return;
4154 if (!no_new_pseudos)
4156 if (GET_CODE (operands[1]) == MEM && optimize > 0
4157 && (mode == QImode || mode == HImode || mode == SImode)
4158 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (word_mode))
4160 rtx reg = gen_reg_rtx (word_mode);
4162 emit_insn (gen_rtx_SET (word_mode, reg,
4163 gen_rtx_ZERO_EXTEND (word_mode,
4164 operands[1])));
4165 operands[1] = gen_lowpart (mode, reg);
4167 if (GET_CODE (operands[0]) != REG)
4168 operands[1] = force_reg (mode, operands[1]);
4171 if (mode == SFmode && ! TARGET_POWERPC
4172 && TARGET_HARD_FLOAT && TARGET_FPRS
4173 && GET_CODE (operands[0]) == MEM)
4175 int regnum;
4177 if (reload_in_progress || reload_completed)
4178 regnum = true_regnum (operands[1]);
4179 else if (GET_CODE (operands[1]) == REG)
4180 regnum = REGNO (operands[1]);
4181 else
4182 regnum = -1;
4184 /* If operands[1] is a register, on POWER it may have
4185 double-precision data in it, so truncate it to single
4186 precision. */
4187 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4189 rtx newreg;
4190 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
4191 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4192 operands[1] = newreg;
4196 /* Recognize the case where operand[1] is a reference to thread-local
4197 data and load its address to a register. */
4198 if (GET_CODE (operands[1]) == SYMBOL_REF)
4200 enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
4201 if (model != 0)
4202 operands[1] = rs6000_legitimize_tls_address (operands[1], model);
4205 /* Handle the case where reload calls us with an invalid address. */
4206 if (reload_in_progress && mode == Pmode
4207 && (! general_operand (operands[1], mode)
4208 || ! nonimmediate_operand (operands[0], mode)))
4209 goto emit_set;
4211 /* 128-bit constant floating-point values on Darwin should really be
4212 loaded as two parts. */
4213 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
4214 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
4215 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4217 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4218 know how to get a DFmode SUBREG of a TFmode. */
4219 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
4220 simplify_gen_subreg (DImode, operands[1], mode, 0),
4221 DImode);
4222 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
4223 GET_MODE_SIZE (DImode)),
4224 simplify_gen_subreg (DImode, operands[1], mode,
4225 GET_MODE_SIZE (DImode)),
4226 DImode);
4227 return;
4230 /* FIXME: In the long term, this switch statement should go away
4231 and be replaced by a sequence of tests based on things like
4232 mode == Pmode. */
4233 switch (mode)
4235 case HImode:
4236 case QImode:
4237 if (CONSTANT_P (operands[1])
4238 && GET_CODE (operands[1]) != CONST_INT)
4239 operands[1] = force_const_mem (mode, operands[1]);
4240 break;
4242 case TFmode:
4243 rs6000_eliminate_indexed_memrefs (operands);
4244 /* fall through */
4246 case DFmode:
4247 case SFmode:
4248 if (CONSTANT_P (operands[1])
4249 && ! easy_fp_constant (operands[1], mode))
4250 operands[1] = force_const_mem (mode, operands[1]);
4251 break;
4253 case V16QImode:
4254 case V8HImode:
4255 case V4SFmode:
4256 case V4SImode:
4257 case V4HImode:
4258 case V2SFmode:
4259 case V2SImode:
4260 case V1DImode:
4261 if (CONSTANT_P (operands[1])
4262 && !easy_vector_constant (operands[1], mode))
4263 operands[1] = force_const_mem (mode, operands[1]);
4264 break;
4266 case SImode:
4267 case DImode:
4268 /* Use default pattern for address of ELF small data */
4269 if (TARGET_ELF
4270 && mode == Pmode
4271 && DEFAULT_ABI == ABI_V4
4272 && (GET_CODE (operands[1]) == SYMBOL_REF
4273 || GET_CODE (operands[1]) == CONST)
4274 && small_data_operand (operands[1], mode))
4276 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4277 return;
4280 if (DEFAULT_ABI == ABI_V4
4281 && mode == Pmode && mode == SImode
4282 && flag_pic == 1 && got_operand (operands[1], mode))
4284 emit_insn (gen_movsi_got (operands[0], operands[1]));
4285 return;
4288 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4289 && TARGET_NO_TOC
4290 && ! flag_pic
4291 && mode == Pmode
4292 && CONSTANT_P (operands[1])
4293 && GET_CODE (operands[1]) != HIGH
4294 && GET_CODE (operands[1]) != CONST_INT)
4296 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
4298 /* If this is a function address on -mcall-aixdesc,
4299 convert it to the address of the descriptor. */
4300 if (DEFAULT_ABI == ABI_AIX
4301 && GET_CODE (operands[1]) == SYMBOL_REF
4302 && XSTR (operands[1], 0)[0] == '.')
4304 const char *name = XSTR (operands[1], 0);
4305 rtx new_ref;
4306 while (*name == '.')
4307 name++;
4308 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4309 CONSTANT_POOL_ADDRESS_P (new_ref)
4310 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4311 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4312 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4313 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
4314 operands[1] = new_ref;
4317 if (DEFAULT_ABI == ABI_DARWIN)
4319 #if TARGET_MACHO
4320 if (MACHO_DYNAMIC_NO_PIC_P)
4322 /* Take care of any required data indirection. */
4323 operands[1] = rs6000_machopic_legitimize_pic_address (
4324 operands[1], mode, operands[0]);
4325 if (operands[0] != operands[1])
4326 emit_insn (gen_rtx_SET (VOIDmode,
4327 operands[0], operands[1]));
4328 return;
4330 #endif
4331 if (mode == DImode)
4333 emit_insn (gen_macho_high_di (target, operands[1]));
4334 emit_insn (gen_macho_low_di (operands[0], target, operands[1]));
4336 else
4338 emit_insn (gen_macho_high (target, operands[1]));
4339 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4341 return;
4344 emit_insn (gen_elf_high (target, operands[1]));
4345 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4346 return;
4349 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4350 and we have put it in the TOC, we just need to make a TOC-relative
4351 reference to it. */
4352 if (TARGET_TOC
4353 && GET_CODE (operands[1]) == SYMBOL_REF
4354 && constant_pool_expr_p (operands[1])
4355 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4356 get_pool_mode (operands[1])))
4358 operands[1] = create_TOC_reference (operands[1]);
4360 else if (mode == Pmode
4361 && CONSTANT_P (operands[1])
4362 && ((GET_CODE (operands[1]) != CONST_INT
4363 && ! easy_fp_constant (operands[1], mode))
4364 || (GET_CODE (operands[1]) == CONST_INT
4365 && num_insns_constant (operands[1], mode) > 2)
4366 || (GET_CODE (operands[0]) == REG
4367 && FP_REGNO_P (REGNO (operands[0]))))
4368 && GET_CODE (operands[1]) != HIGH
4369 && ! legitimate_constant_pool_address_p (operands[1])
4370 && ! toc_relative_expr_p (operands[1]))
4372 /* Emit a USE operation so that the constant isn't deleted if
4373 expensive optimizations are turned on because nobody
4374 references it. This should only be done for operands that
4375 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4376 This should not be done for operands that contain LABEL_REFs.
4377 For now, we just handle the obvious case. */
4378 if (GET_CODE (operands[1]) != LABEL_REF)
4379 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4381 #if TARGET_MACHO
4382 /* Darwin uses a special PIC legitimizer. */
4383 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4385 operands[1] =
4386 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4387 operands[0]);
4388 if (operands[0] != operands[1])
4389 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4390 return;
4392 #endif
4394 /* If we are to limit the number of things we put in the TOC and
4395 this is a symbol plus a constant we can add in one insn,
4396 just put the symbol in the TOC and add the constant. Don't do
4397 this if reload is in progress. */
4398 if (GET_CODE (operands[1]) == CONST
4399 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4400 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4401 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4402 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4403 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4404 && ! side_effects_p (operands[0]))
4406 rtx sym =
4407 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4408 rtx other = XEXP (XEXP (operands[1], 0), 1);
4410 sym = force_reg (mode, sym);
4411 if (mode == SImode)
4412 emit_insn (gen_addsi3 (operands[0], sym, other));
4413 else
4414 emit_insn (gen_adddi3 (operands[0], sym, other));
4415 return;
4418 operands[1] = force_const_mem (mode, operands[1]);
4420 if (TARGET_TOC
4421 && constant_pool_expr_p (XEXP (operands[1], 0))
4422 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4423 get_pool_constant (XEXP (operands[1], 0)),
4424 get_pool_mode (XEXP (operands[1], 0))))
4426 operands[1]
4427 = gen_const_mem (mode,
4428 create_TOC_reference (XEXP (operands[1], 0)));
4429 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4432 break;
4434 case TImode:
4435 rs6000_eliminate_indexed_memrefs (operands);
4437 if (TARGET_POWER)
4439 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4440 gen_rtvec (2,
4441 gen_rtx_SET (VOIDmode,
4442 operands[0], operands[1]),
4443 gen_rtx_CLOBBER (VOIDmode,
4444 gen_rtx_SCRATCH (SImode)))));
4445 return;
4447 break;
4449 default:
4450 abort ();
4453 /* Above, we may have called force_const_mem which may have returned
4454 an invalid address. If we can, fix this up; otherwise, reload will
4455 have to deal with it. */
4456 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4457 operands[1] = validize_mem (operands[1]);
4459 emit_set:
4460 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4463 /* Nonzero if we can use a floating-point register to pass this arg. */
4464 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4465 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
4466 && (CUM)->fregno <= FP_ARG_MAX_REG \
4467 && TARGET_HARD_FLOAT && TARGET_FPRS)
4469 /* Nonzero if we can use an AltiVec register to pass this arg. */
4470 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4471 (ALTIVEC_VECTOR_MODE (MODE) \
4472 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4473 && TARGET_ALTIVEC_ABI \
4474 && (NAMED))
4476 /* Return a nonzero value to say to return the function value in
4477 memory, just as large structures are always returned. TYPE will be
4478 the data type of the value, and FNTYPE will be the type of the
4479 function doing the returning, or @code{NULL} for libcalls.
4481 The AIX ABI for the RS/6000 specifies that all structures are
4482 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4483 specifies that structures <= 8 bytes are returned in r3/r4, but a
4484 draft put them in memory, and GCC used to implement the draft
4485 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
4486 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4487 compatibility can change DRAFT_V4_STRUCT_RET to override the
4488 default, and -m switches get the final word. See
4489 rs6000_override_options for more details.
4491 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4492 long double support is enabled. These values are returned in memory.
4494 int_size_in_bytes returns -1 for variable size objects, which go in
4495 memory always. The cast to unsigned makes -1 > 8. */
4497 static bool
4498 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4500 if (AGGREGATE_TYPE_P (type)
4501 && (TARGET_AIX_STRUCT_RET
4502 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4503 return true;
4504 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
4505 return true;
4506 return false;
4509 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4510 for a call to a function whose data type is FNTYPE.
4511 For a library call, FNTYPE is 0.
4513 For incoming args we set the number of arguments in the prototype large
4514 so we never return a PARALLEL. */
4516 void
4517 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4518 rtx libname ATTRIBUTE_UNUSED, int incoming,
4519 int libcall, int n_named_args)
4521 static CUMULATIVE_ARGS zero_cumulative;
4523 *cum = zero_cumulative;
4524 cum->words = 0;
4525 cum->fregno = FP_ARG_MIN_REG;
4526 cum->vregno = ALTIVEC_ARG_MIN_REG;
4527 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4528 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4529 ? CALL_LIBCALL : CALL_NORMAL);
4530 cum->sysv_gregno = GP_ARG_MIN_REG;
4531 cum->stdarg = fntype
4532 && (TYPE_ARG_TYPES (fntype) != 0
4533 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4534 != void_type_node));
4536 cum->nargs_prototype = 0;
4537 if (incoming || cum->prototype)
4538 cum->nargs_prototype = n_named_args;
4540 /* Check for a longcall attribute. */
4541 if (fntype
4542 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4543 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype)))
4544 cum->call_cookie = CALL_LONG;
4546 if (TARGET_DEBUG_ARG)
4548 fprintf (stderr, "\ninit_cumulative_args:");
4549 if (fntype)
4551 tree ret_type = TREE_TYPE (fntype);
4552 fprintf (stderr, " ret code = %s,",
4553 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4556 if (cum->call_cookie & CALL_LONG)
4557 fprintf (stderr, " longcall,");
4559 fprintf (stderr, " proto = %d, nargs = %d\n",
4560 cum->prototype, cum->nargs_prototype);
4563 if (fntype
4564 && !TARGET_ALTIVEC
4565 && TARGET_ALTIVEC_ABI
4566 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4568 error ("Cannot return value in vector register because"
4569 " altivec instructions are disabled, use -maltivec"
4570 " to enable them.");
4574 /* Return true if TYPE must be passed on the stack and not in registers. */
4576 static bool
4577 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4579 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4580 return must_pass_in_stack_var_size (mode, type);
4581 else
4582 return must_pass_in_stack_var_size_or_pad (mode, type);
4585 /* If defined, a C expression which determines whether, and in which
4586 direction, to pad out an argument with extra space. The value
4587 should be of type `enum direction': either `upward' to pad above
4588 the argument, `downward' to pad below, or `none' to inhibit
4589 padding.
4591 For the AIX ABI structs are always stored left shifted in their
4592 argument slot. */
4594 enum direction
4595 function_arg_padding (enum machine_mode mode, tree type)
4597 #ifndef AGGREGATE_PADDING_FIXED
4598 #define AGGREGATE_PADDING_FIXED 0
4599 #endif
4600 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4601 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4602 #endif
4604 if (!AGGREGATE_PADDING_FIXED)
4606 /* GCC used to pass structures of the same size as integer types as
4607 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4608 ie. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4609 passed padded downward, except that -mstrict-align further
4610 muddied the water in that multi-component structures of 2 and 4
4611 bytes in size were passed padded upward.
4613 The following arranges for best compatibility with previous
4614 versions of gcc, but removes the -mstrict-align dependency. */
4615 if (BYTES_BIG_ENDIAN)
4617 HOST_WIDE_INT size = 0;
4619 if (mode == BLKmode)
4621 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4622 size = int_size_in_bytes (type);
4624 else
4625 size = GET_MODE_SIZE (mode);
4627 if (size == 1 || size == 2 || size == 4)
4628 return downward;
4630 return upward;
4633 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4635 if (type != 0 && AGGREGATE_TYPE_P (type))
4636 return upward;
4639 /* Fall back to the default. */
4640 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4643 /* If defined, a C expression that gives the alignment boundary, in bits,
4644 of an argument with the specified mode and type. If it is not defined,
4645 PARM_BOUNDARY is used for all arguments.
4647 V.4 wants long longs to be double word aligned. */
4650 function_arg_boundary (enum machine_mode mode, tree type ATTRIBUTE_UNUSED)
4652 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4653 return 64;
4654 else if (SPE_VECTOR_MODE (mode))
4655 return 64;
4656 else if (ALTIVEC_VECTOR_MODE (mode))
4657 return 128;
4658 else
4659 return PARM_BOUNDARY;
4662 /* Compute the size (in words) of a function argument. */
4664 static unsigned long
4665 rs6000_arg_size (enum machine_mode mode, tree type)
4667 unsigned long size;
4669 if (mode != BLKmode)
4670 size = GET_MODE_SIZE (mode);
4671 else
4672 size = int_size_in_bytes (type);
4674 if (TARGET_32BIT)
4675 return (size + 3) >> 2;
4676 else
4677 return (size + 7) >> 3;
4680 /* Update the data in CUM to advance over an argument
4681 of mode MODE and data type TYPE.
4682 (TYPE is null for libcalls where that information may not be available.)
4684 Note that for args passed by reference, function_arg will be called
4685 with MODE and TYPE set to that of the pointer to the arg, not the arg
4686 itself. */
4688 void
4689 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4690 tree type, int named)
4692 cum->nargs_prototype--;
4694 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4696 bool stack = false;
4698 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4700 cum->vregno++;
4701 if (!TARGET_ALTIVEC)
4702 error ("Cannot pass argument in vector register because"
4703 " altivec instructions are disabled, use -maltivec"
4704 " to enable them.");
4706 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4707 even if it is going to be passed in a vector register.
4708 Darwin does the same for variable-argument functions. */
4709 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4710 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4711 stack = true;
4713 else
4714 stack = true;
4716 if (stack)
4718 int align;
4720 /* Vector parameters must be 16-byte aligned. This places
4721 them at 2 mod 4 in terms of words in 32-bit mode, since
4722 the parameter save area starts at offset 24 from the
4723 stack. In 64-bit mode, they just have to start on an
4724 even word, since the parameter save area is 16-byte
4725 aligned. Space for GPRs is reserved even if the argument
4726 will be passed in memory. */
4727 if (TARGET_32BIT)
4728 align = (2 - cum->words) & 3;
4729 else
4730 align = cum->words & 1;
4731 cum->words += align + rs6000_arg_size (mode, type);
4733 if (TARGET_DEBUG_ARG)
4735 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4736 cum->words, align);
4737 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4738 cum->nargs_prototype, cum->prototype,
4739 GET_MODE_NAME (mode));
4743 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4744 && !cum->stdarg
4745 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4746 cum->sysv_gregno++;
4747 else if (DEFAULT_ABI == ABI_V4)
4749 if (TARGET_HARD_FLOAT && TARGET_FPRS
4750 && (mode == SFmode || mode == DFmode))
4752 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4753 cum->fregno++;
4754 else
4756 if (mode == DFmode)
4757 cum->words += cum->words & 1;
4758 cum->words += rs6000_arg_size (mode, type);
4761 else
4763 int n_words = rs6000_arg_size (mode, type);
4764 int gregno = cum->sysv_gregno;
4766 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4767 (r7,r8) or (r9,r10). As does any other 2 word item such
4768 as complex int due to a historical mistake. */
4769 if (n_words == 2)
4770 gregno += (1 - gregno) & 1;
4772 /* Multi-reg args are not split between registers and stack. */
4773 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4775 /* Long long and SPE vectors are aligned on the stack.
4776 So are other 2 word items such as complex int due to
4777 a historical mistake. */
4778 if (n_words == 2)
4779 cum->words += cum->words & 1;
4780 cum->words += n_words;
4783 /* Note: continuing to accumulate gregno past when we've started
4784 spilling to the stack indicates the fact that we've started
4785 spilling to the stack to expand_builtin_saveregs. */
4786 cum->sysv_gregno = gregno + n_words;
4789 if (TARGET_DEBUG_ARG)
4791 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4792 cum->words, cum->fregno);
4793 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4794 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4795 fprintf (stderr, "mode = %4s, named = %d\n",
4796 GET_MODE_NAME (mode), named);
4799 else
4801 int n_words = rs6000_arg_size (mode, type);
4802 int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4804 /* The simple alignment calculation here works because
4805 function_arg_boundary / PARM_BOUNDARY will only be 1 or 2.
4806 If we ever want to handle alignments larger than 8 bytes for
4807 32-bit or 16 bytes for 64-bit, then we'll need to take into
4808 account the offset to the start of the parm save area. */
4809 align &= cum->words;
4810 cum->words += align + n_words;
4812 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4813 && TARGET_HARD_FLOAT && TARGET_FPRS)
4814 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4816 if (TARGET_DEBUG_ARG)
4818 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4819 cum->words, cum->fregno);
4820 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4821 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4822 fprintf (stderr, "named = %d, align = %d\n", named, align);
4827 /* Determine where to put a SIMD argument on the SPE. */
4829 static rtx
4830 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4831 tree type)
4833 if (cum->stdarg)
4835 int gregno = cum->sysv_gregno;
4836 int n_words = rs6000_arg_size (mode, type);
4838 /* SPE vectors are put in odd registers. */
4839 if (n_words == 2 && (gregno & 1) == 0)
4840 gregno += 1;
4842 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4844 rtx r1, r2;
4845 enum machine_mode m = SImode;
4847 r1 = gen_rtx_REG (m, gregno);
4848 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4849 r2 = gen_rtx_REG (m, gregno + 1);
4850 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4851 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4853 else
4854 return NULL_RTX;
4856 else
4858 if (cum->sysv_gregno <= GP_ARG_MAX_REG)
4859 return gen_rtx_REG (mode, cum->sysv_gregno);
4860 else
4861 return NULL_RTX;
4865 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4867 static rtx
4868 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
4870 int n_units;
4871 int i, k;
4872 rtx rvec[GP_ARG_NUM_REG + 1];
4874 if (align_words >= GP_ARG_NUM_REG)
4875 return NULL_RTX;
4877 n_units = rs6000_arg_size (mode, type);
4879 /* Optimize the simple case where the arg fits in one gpr, except in
4880 the case of BLKmode due to assign_parms assuming that registers are
4881 BITS_PER_WORD wide. */
4882 if (n_units == 0
4883 || (n_units == 1 && mode != BLKmode))
4884 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4886 k = 0;
4887 if (align_words + n_units > GP_ARG_NUM_REG)
4888 /* Not all of the arg fits in gprs. Say that it goes in memory too,
4889 using a magic NULL_RTX component.
4890 FIXME: This is not strictly correct. Only some of the arg
4891 belongs in memory, not all of it. However, there isn't any way
4892 to do this currently, apart from building rtx descriptions for
4893 the pieces of memory we want stored. Due to bugs in the generic
4894 code we can't use the normal function_arg_partial_nregs scheme
4895 with the PARALLEL arg description we emit here.
4896 In any case, the code to store the whole arg to memory is often
4897 more efficient than code to store pieces, and we know that space
4898 is available in the right place for the whole arg. */
4899 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4901 i = 0;
4904 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
4905 rtx off = GEN_INT (i++ * 4);
4906 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
4908 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
4910 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
4913 /* Determine where to put an argument to a function.
4914 Value is zero to push the argument on the stack,
4915 or a hard register in which to store the argument.
4917 MODE is the argument's machine mode.
4918 TYPE is the data type of the argument (as a tree).
4919 This is null for libcalls where that information may
4920 not be available.
4921 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4922 the preceding args and about the function being called.
4923 NAMED is nonzero if this argument is a named parameter
4924 (otherwise it is an extra parameter matching an ellipsis).
4926 On RS/6000 the first eight words of non-FP are normally in registers
4927 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
4928 Under V.4, the first 8 FP args are in registers.
4930 If this is floating-point and no prototype is specified, we use
4931 both an FP and integer register (or possibly FP reg and stack). Library
4932 functions (when CALL_LIBCALL is set) always have the proper types for args,
4933 so we can pass the FP value just in one register. emit_library_function
4934 doesn't support PARALLEL anyway.
4936 Note that for args passed by reference, function_arg will be called
4937 with MODE and TYPE set to that of the pointer to the arg, not the arg
4938 itself. */
4940 struct rtx_def *
4941 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4942 tree type, int named)
4944 enum rs6000_abi abi = DEFAULT_ABI;
4946 /* Return a marker to indicate whether CR1 needs to set or clear the
4947 bit that V.4 uses to say fp args were passed in registers.
4948 Assume that we don't need the marker for software floating point,
4949 or compiler generated library calls. */
4950 if (mode == VOIDmode)
4952 if (abi == ABI_V4
4953 && cum->nargs_prototype < 0
4954 && (cum->call_cookie & CALL_LIBCALL) == 0
4955 && (cum->prototype || TARGET_NO_PROTOTYPE))
4957 /* For the SPE, we need to crxor CR6 always. */
4958 if (TARGET_SPE_ABI)
4959 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
4960 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
4961 return GEN_INT (cum->call_cookie
4962 | ((cum->fregno == FP_ARG_MIN_REG)
4963 ? CALL_V4_SET_FP_ARGS
4964 : CALL_V4_CLEAR_FP_ARGS));
4967 return GEN_INT (cum->call_cookie);
4970 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4971 if (TARGET_64BIT && ! cum->prototype)
4973 /* Vector parameters get passed in vector register
4974 and also in GPRs or memory, in absence of prototype. */
4975 int align_words;
4976 rtx slot;
4977 align_words = (cum->words + 1) & ~1;
4979 if (align_words >= GP_ARG_NUM_REG)
4981 slot = NULL_RTX;
4983 else
4985 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4987 return gen_rtx_PARALLEL (mode,
4988 gen_rtvec (2,
4989 gen_rtx_EXPR_LIST (VOIDmode,
4990 slot, const0_rtx),
4991 gen_rtx_EXPR_LIST (VOIDmode,
4992 gen_rtx_REG (mode, cum->vregno),
4993 const0_rtx)));
4995 else
4996 return gen_rtx_REG (mode, cum->vregno);
4997 else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
4999 if (named || abi == ABI_V4)
5000 return NULL_RTX;
5001 else
5003 /* Vector parameters to varargs functions under AIX or Darwin
5004 get passed in memory and possibly also in GPRs. */
5005 int align, align_words, n_words;
5006 enum machine_mode part_mode;
5008 /* Vector parameters must be 16-byte aligned. This places them at
5009 2 mod 4 in terms of words in 32-bit mode, since the parameter
5010 save area starts at offset 24 from the stack. In 64-bit mode,
5011 they just have to start on an even word, since the parameter
5012 save area is 16-byte aligned. */
5013 if (TARGET_32BIT)
5014 align = (2 - cum->words) & 3;
5015 else
5016 align = cum->words & 1;
5017 align_words = cum->words + align;
5019 /* Out of registers? Memory, then. */
5020 if (align_words >= GP_ARG_NUM_REG)
5021 return NULL_RTX;
5023 if (TARGET_32BIT && TARGET_POWERPC64)
5024 return rs6000_mixed_function_arg (mode, type, align_words);
5026 /* The vector value goes in GPRs. Only the part of the
5027 value in GPRs is reported here. */
5028 part_mode = mode;
5029 n_words = rs6000_arg_size (mode, type);
5030 if (align_words + n_words > GP_ARG_NUM_REG)
5031 /* Fortunately, there are only two possibilities, the value
5032 is either wholly in GPRs or half in GPRs and half not. */
5033 part_mode = DImode;
5035 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5038 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode))
5039 return rs6000_spe_function_arg (cum, mode, type);
5040 else if (abi == ABI_V4)
5042 if (TARGET_HARD_FLOAT && TARGET_FPRS
5043 && (mode == SFmode || mode == DFmode))
5045 if (cum->fregno <= FP_ARG_V4_MAX_REG)
5046 return gen_rtx_REG (mode, cum->fregno);
5047 else
5048 return NULL_RTX;
5050 else
5052 int n_words = rs6000_arg_size (mode, type);
5053 int gregno = cum->sysv_gregno;
5055 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5056 (r7,r8) or (r9,r10). As does any other 2 word item such
5057 as complex int due to a historical mistake. */
5058 if (n_words == 2)
5059 gregno += (1 - gregno) & 1;
5061 /* Multi-reg args are not split between registers and stack. */
5062 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5063 return NULL_RTX;
5065 if (TARGET_32BIT && TARGET_POWERPC64)
5066 return rs6000_mixed_function_arg (mode, type,
5067 gregno - GP_ARG_MIN_REG);
5068 return gen_rtx_REG (mode, gregno);
5071 else
5073 int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5074 int align_words = cum->words + (cum->words & align);
5076 if (USE_FP_FOR_ARG_P (cum, mode, type))
5078 rtx rvec[GP_ARG_NUM_REG + 1];
5079 rtx r;
5080 int k;
5081 bool needs_psave;
5082 enum machine_mode fmode = mode;
5083 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5085 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5087 /* Currently, we only ever need one reg here because complex
5088 doubles are split. */
5089 if (cum->fregno != FP_ARG_MAX_REG || fmode != TFmode)
5090 abort ();
5092 /* Long double split over regs and memory. */
5093 fmode = DFmode;
5096 /* Do we also need to pass this arg in the parameter save
5097 area? */
5098 needs_psave = (type
5099 && (cum->nargs_prototype <= 0
5100 || (DEFAULT_ABI == ABI_AIX
5101 && TARGET_XL_CALL
5102 && align_words >= GP_ARG_NUM_REG)));
5104 if (!needs_psave && mode == fmode)
5105 return gen_rtx_REG (fmode, cum->fregno);
5107 k = 0;
5108 if (needs_psave)
5110 /* Describe the part that goes in gprs or the stack.
5111 This piece must come first, before the fprs. */
5112 if (align_words < GP_ARG_NUM_REG)
5114 unsigned long n_words = rs6000_arg_size (mode, type);
5116 if (align_words + n_words > GP_ARG_NUM_REG
5117 || (TARGET_32BIT && TARGET_POWERPC64))
5119 /* If this is partially on the stack, then we only
5120 include the portion actually in registers here. */
5121 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5122 rtx off;
5125 r = gen_rtx_REG (rmode,
5126 GP_ARG_MIN_REG + align_words);
5127 off = GEN_INT (k * GET_MODE_SIZE (rmode));
5128 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5130 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5132 else
5134 /* The whole arg fits in gprs. */
5135 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5136 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5139 else
5140 /* It's entirely in memory. */
5141 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5144 /* Describe where this piece goes in the fprs. */
5145 r = gen_rtx_REG (fmode, cum->fregno);
5146 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5148 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5150 else if (align_words < GP_ARG_NUM_REG)
5152 if (TARGET_32BIT && TARGET_POWERPC64)
5153 return rs6000_mixed_function_arg (mode, type, align_words);
5155 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5157 else
5158 return NULL_RTX;
5162 /* For an arg passed partly in registers and partly in memory, this is
5163 the number of registers used. For args passed entirely in registers
5164 or entirely in memory, zero. When an arg is described by a PARALLEL,
5165 perhaps using more than one register type, this function returns the
5166 number of registers used by the first element of the PARALLEL. */
5169 function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5170 tree type, int named)
5172 int ret = 0;
5173 int align;
5174 int parm_offset;
5175 int align_words;
5177 if (DEFAULT_ABI == ABI_V4)
5178 return 0;
5180 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5181 && cum->nargs_prototype >= 0)
5182 return 0;
5184 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5185 parm_offset = TARGET_32BIT ? 2 : 0;
5186 align_words = cum->words + ((parm_offset - cum->words) & align);
5188 if (USE_FP_FOR_ARG_P (cum, mode, type)
5189 /* If we are passing this arg in gprs as well, then this function
5190 should return the number of gprs (or memory) partially passed,
5191 *not* the number of fprs. */
5192 && !(type
5193 && (cum->nargs_prototype <= 0
5194 || (DEFAULT_ABI == ABI_AIX
5195 && TARGET_XL_CALL
5196 && align_words >= GP_ARG_NUM_REG))))
5198 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
5199 ret = FP_ARG_MAX_REG + 1 - cum->fregno;
5200 else if (cum->nargs_prototype >= 0)
5201 return 0;
5204 if (align_words < GP_ARG_NUM_REG
5205 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5206 ret = GP_ARG_NUM_REG - align_words;
5208 if (ret != 0 && TARGET_DEBUG_ARG)
5209 fprintf (stderr, "function_arg_partial_nregs: %d\n", ret);
5211 return ret;
5214 /* A C expression that indicates when an argument must be passed by
5215 reference. If nonzero for an argument, a copy of that argument is
5216 made in memory and a pointer to the argument is passed instead of
5217 the argument itself. The pointer is passed in whatever way is
5218 appropriate for passing a pointer to that type.
5220 Under V.4, aggregates and long double are passed by reference.
5222 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5223 reference unless the AltiVec vector extension ABI is in force.
5225 As an extension to all ABIs, variable sized types are passed by
5226 reference. */
5228 static bool
5229 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5230 enum machine_mode mode ATTRIBUTE_UNUSED,
5231 tree type, bool named ATTRIBUTE_UNUSED)
5233 if ((DEFAULT_ABI == ABI_V4
5234 && ((type && AGGREGATE_TYPE_P (type))
5235 || mode == TFmode))
5236 || (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5237 || (type && int_size_in_bytes (type) < 0))
5239 if (TARGET_DEBUG_ARG)
5240 fprintf (stderr, "function_arg_pass_by_reference\n");
5242 return 1;
5244 return 0;
5247 static void
5248 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5250 int i;
5251 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5253 if (nregs == 0)
5254 return;
5256 for (i = 0; i < nregs; i++)
5258 rtx tem = adjust_address_nv (x, reg_mode, i*GET_MODE_SIZE(reg_mode));
5259 if (reload_completed)
5261 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5262 tem = NULL_RTX;
5263 else
5264 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5265 i * GET_MODE_SIZE(reg_mode));
5267 else
5268 tem = replace_equiv_address (tem, XEXP (tem, 0));
5270 if (tem == NULL_RTX)
5271 abort ();
5273 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5278 /* Perform any needed actions needed for a function that is receiving a
5279 variable number of arguments.
5281 CUM is as above.
5283 MODE and TYPE are the mode and type of the current parameter.
5285 PRETEND_SIZE is a variable that should be set to the amount of stack
5286 that must be pushed by the prolog to pretend that our caller pushed
5289 Normally, this macro will push all remaining incoming registers on the
5290 stack and set PRETEND_SIZE to the length of the registers pushed. */
5292 static void
5293 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5294 tree type, int *pretend_size ATTRIBUTE_UNUSED, int no_rtl)
5296 CUMULATIVE_ARGS next_cum;
5297 int reg_size = TARGET_32BIT ? 4 : 8;
5298 rtx save_area = NULL_RTX, mem;
5299 int first_reg_offset, set;
5301 /* Skip the last named argument. */
5302 next_cum = *cum;
5303 function_arg_advance (&next_cum, mode, type, 1);
5305 if (DEFAULT_ABI == ABI_V4)
5307 /* Indicate to allocate space on the stack for varargs save area. */
5308 cfun->machine->sysv_varargs_p = 1;
5309 if (! no_rtl)
5310 save_area = plus_constant (virtual_stack_vars_rtx,
5311 - RS6000_VARARGS_SIZE);
5313 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5315 else
5317 first_reg_offset = next_cum.words;
5318 save_area = virtual_incoming_args_rtx;
5319 cfun->machine->sysv_varargs_p = 0;
5321 if (targetm.calls.must_pass_in_stack (mode, type))
5322 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5325 set = get_varargs_alias_set ();
5326 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
5328 mem = gen_rtx_MEM (BLKmode,
5329 plus_constant (save_area,
5330 first_reg_offset * reg_size)),
5331 set_mem_alias_set (mem, set);
5332 set_mem_align (mem, BITS_PER_WORD);
5334 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5335 GP_ARG_NUM_REG - first_reg_offset);
5338 /* Save FP registers if needed. */
5339 if (DEFAULT_ABI == ABI_V4
5340 && TARGET_HARD_FLOAT && TARGET_FPRS
5341 && ! no_rtl
5342 && next_cum.fregno <= FP_ARG_V4_MAX_REG)
5344 int fregno = next_cum.fregno;
5345 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5346 rtx lab = gen_label_rtx ();
5347 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
5349 emit_jump_insn (gen_rtx_SET (VOIDmode,
5350 pc_rtx,
5351 gen_rtx_IF_THEN_ELSE (VOIDmode,
5352 gen_rtx_NE (VOIDmode, cr1,
5353 const0_rtx),
5354 gen_rtx_LABEL_REF (VOIDmode, lab),
5355 pc_rtx)));
5357 while (fregno <= FP_ARG_V4_MAX_REG)
5359 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5360 set_mem_alias_set (mem, set);
5361 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5362 fregno++;
5363 off += 8;
5366 emit_label (lab);
5370 /* Create the va_list data type. */
5372 static tree
5373 rs6000_build_builtin_va_list (void)
5375 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5377 /* For AIX, prefer 'char *' because that's what the system
5378 header files like. */
5379 if (DEFAULT_ABI != ABI_V4)
5380 return build_pointer_type (char_type_node);
5382 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5383 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5385 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5386 unsigned_char_type_node);
5387 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5388 unsigned_char_type_node);
5389 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5390 every user file. */
5391 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5392 short_unsigned_type_node);
5393 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5394 ptr_type_node);
5395 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5396 ptr_type_node);
5398 DECL_FIELD_CONTEXT (f_gpr) = record;
5399 DECL_FIELD_CONTEXT (f_fpr) = record;
5400 DECL_FIELD_CONTEXT (f_res) = record;
5401 DECL_FIELD_CONTEXT (f_ovf) = record;
5402 DECL_FIELD_CONTEXT (f_sav) = record;
5404 TREE_CHAIN (record) = type_decl;
5405 TYPE_NAME (record) = type_decl;
5406 TYPE_FIELDS (record) = f_gpr;
5407 TREE_CHAIN (f_gpr) = f_fpr;
5408 TREE_CHAIN (f_fpr) = f_res;
5409 TREE_CHAIN (f_res) = f_ovf;
5410 TREE_CHAIN (f_ovf) = f_sav;
5412 layout_type (record);
5414 /* The correct type is an array type of one element. */
5415 return build_array_type (record, build_index_type (size_zero_node));
5418 /* Implement va_start. */
5420 void
5421 rs6000_va_start (tree valist, rtx nextarg)
5423 HOST_WIDE_INT words, n_gpr, n_fpr;
5424 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5425 tree gpr, fpr, ovf, sav, t;
5427 /* Only SVR4 needs something special. */
5428 if (DEFAULT_ABI != ABI_V4)
5430 std_expand_builtin_va_start (valist, nextarg);
5431 return;
5434 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5435 f_fpr = TREE_CHAIN (f_gpr);
5436 f_res = TREE_CHAIN (f_fpr);
5437 f_ovf = TREE_CHAIN (f_res);
5438 f_sav = TREE_CHAIN (f_ovf);
5440 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
5441 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5442 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5443 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5444 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5446 /* Count number of gp and fp argument registers used. */
5447 words = current_function_args_info.words;
5448 n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG;
5449 n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG;
5451 if (TARGET_DEBUG_ARG)
5452 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5453 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5454 words, n_gpr, n_fpr);
5456 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5457 build_int_cst (NULL_TREE, n_gpr, 0));
5458 TREE_SIDE_EFFECTS (t) = 1;
5459 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5461 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5462 build_int_cst (NULL_TREE, n_fpr, 0));
5463 TREE_SIDE_EFFECTS (t) = 1;
5464 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5466 /* Find the overflow area. */
5467 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5468 if (words != 0)
5469 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
5470 build_int_cst (NULL_TREE, words * UNITS_PER_WORD, 0));
5471 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5472 TREE_SIDE_EFFECTS (t) = 1;
5473 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5475 /* Find the register save area. */
5476 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5477 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
5478 build_int_cst (NULL_TREE, -RS6000_VARARGS_SIZE, -1));
5479 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5480 TREE_SIDE_EFFECTS (t) = 1;
5481 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5484 /* Implement va_arg. */
5486 tree
5487 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5489 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5490 tree gpr, fpr, ovf, sav, reg, t, u;
5491 int size, rsize, n_reg, sav_ofs, sav_scale;
5492 tree lab_false, lab_over, addr;
5493 int align;
5494 tree ptrtype = build_pointer_type (type);
5496 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5498 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
5499 return build_fold_indirect_ref (t);
5502 if (DEFAULT_ABI != ABI_V4)
5504 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
5506 tree elem_type = TREE_TYPE (type);
5507 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5508 int elem_size = GET_MODE_SIZE (elem_mode);
5510 if (elem_size < UNITS_PER_WORD)
5512 tree real_part, imag_part;
5513 tree post = NULL_TREE;
5515 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5516 &post);
5517 /* Copy the value into a temporary, lest the formal temporary
5518 be reused out from under us. */
5519 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
5520 append_to_statement_list (post, pre_p);
5522 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5523 post_p);
5525 return build (COMPLEX_EXPR, type, real_part, imag_part);
5529 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5532 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5533 f_fpr = TREE_CHAIN (f_gpr);
5534 f_res = TREE_CHAIN (f_fpr);
5535 f_ovf = TREE_CHAIN (f_res);
5536 f_sav = TREE_CHAIN (f_ovf);
5538 valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist);
5539 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5540 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5541 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5542 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5544 size = int_size_in_bytes (type);
5545 rsize = (size + 3) / 4;
5546 align = 1;
5548 if (TARGET_HARD_FLOAT && TARGET_FPRS
5549 && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode))
5551 /* FP args go in FP registers, if present. */
5552 reg = fpr;
5553 n_reg = 1;
5554 sav_ofs = 8*4;
5555 sav_scale = 8;
5556 if (TYPE_MODE (type) == DFmode)
5557 align = 8;
5559 else
5561 /* Otherwise into GP registers. */
5562 reg = gpr;
5563 n_reg = rsize;
5564 sav_ofs = 0;
5565 sav_scale = 4;
5566 if (n_reg == 2)
5567 align = 8;
5570 /* Pull the value out of the saved registers.... */
5572 lab_over = NULL;
5573 addr = create_tmp_var (ptr_type_node, "addr");
5574 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5576 /* AltiVec vectors never go in registers when -mabi=altivec. */
5577 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5578 align = 16;
5579 else
5581 lab_false = create_artificial_label ();
5582 lab_over = create_artificial_label ();
5584 /* Long long and SPE vectors are aligned in the registers.
5585 As are any other 2 gpr item such as complex int due to a
5586 historical mistake. */
5587 u = reg;
5588 if (n_reg == 2)
5590 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5591 size_int (n_reg - 1));
5592 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5595 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
5596 t = build2 (GE_EXPR, boolean_type_node, u, t);
5597 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5598 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5599 gimplify_and_add (t, pre_p);
5601 t = sav;
5602 if (sav_ofs)
5603 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
5605 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
5606 u = build1 (CONVERT_EXPR, integer_type_node, u);
5607 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
5608 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5610 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5611 gimplify_and_add (t, pre_p);
5613 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5614 gimplify_and_add (t, pre_p);
5616 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5617 append_to_statement_list (t, pre_p);
5619 if (n_reg > 2)
5621 /* Ensure that we don't find any more args in regs.
5622 Alignment has taken care of the n_reg == 2 case. */
5623 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
5624 gimplify_and_add (t, pre_p);
5628 /* ... otherwise out of the overflow area. */
5630 /* Care for on-stack alignment if needed. */
5631 t = ovf;
5632 if (align != 1)
5634 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
5635 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5636 build_int_cst (NULL_TREE, -align, -1));
5638 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5640 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5641 gimplify_and_add (u, pre_p);
5643 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
5644 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5645 gimplify_and_add (t, pre_p);
5647 if (lab_over)
5649 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5650 append_to_statement_list (t, pre_p);
5653 addr = fold_convert (ptrtype, addr);
5654 return build_fold_indirect_ref (addr);
5657 /* Builtins. */
5659 #define def_builtin(MASK, NAME, TYPE, CODE) \
5660 do { \
5661 if ((MASK) & target_flags) \
5662 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
5663 NULL, NULL_TREE); \
5664 } while (0)
5666 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5668 static const struct builtin_description bdesc_3arg[] =
5670 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5671 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5672 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5673 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5674 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5675 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5676 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5677 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5678 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5679 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
5680 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
5681 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5682 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5683 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5684 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5685 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5686 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5687 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5688 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5689 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5690 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5691 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5692 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
5695 /* DST operations: void foo (void *, const int, const char). */
5697 static const struct builtin_description bdesc_dst[] =
5699 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
5700 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
5701 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
5702 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }
5705 /* Simple binary operations: VECc = foo (VECa, VECb). */
5707 static struct builtin_description bdesc_2arg[] =
5709 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
5710 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
5711 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
5712 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
5713 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
5714 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
5715 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
5716 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
5717 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
5718 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
5719 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
5720 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
5721 { MASK_ALTIVEC, CODE_FOR_altivec_vandc, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
5722 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
5723 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
5724 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
5725 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
5726 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
5727 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
5728 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
5729 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
5730 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
5731 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
5732 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
5733 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
5734 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
5735 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
5736 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
5737 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
5738 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
5739 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
5740 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
5741 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
5742 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
5743 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
5744 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
5745 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
5746 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
5747 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
5748 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
5749 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
5750 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
5751 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
5752 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
5753 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
5754 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
5755 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
5756 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
5757 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
5758 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
5759 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
5760 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
5761 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
5762 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
5763 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
5764 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
5765 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
5766 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
5767 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
5768 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
5769 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
5770 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
5771 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
5772 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
5773 { MASK_ALTIVEC, CODE_FOR_altivec_vnor, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
5774 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
5775 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
5776 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
5777 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
5778 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
5779 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
5780 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
5781 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
5782 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
5783 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
5784 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
5785 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
5786 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
5787 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
5788 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
5789 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
5790 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
5791 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
5792 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
5793 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
5794 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
5795 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
5796 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
5797 { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
5798 { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
5799 { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
5800 { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
5801 { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
5802 { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
5803 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
5804 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
5805 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
5806 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
5807 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
5808 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
5809 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
5810 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
5811 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
5812 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
5813 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
5814 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
5815 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
5816 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
5817 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
5818 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
5819 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
5820 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
5821 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
5823 /* Place holder, leave as first spe builtin. */
5824 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
5825 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
5826 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
5827 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
5828 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
5829 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
5830 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
5831 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
5832 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
5833 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
5834 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
5835 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
5836 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
5837 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
5838 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
5839 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
5840 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
5841 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
5842 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
5843 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
5844 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
5845 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
5846 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
5847 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
5848 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
5849 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
5850 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
5851 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
5852 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
5853 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
5854 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
5855 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
5856 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
5857 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
5858 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
5859 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
5860 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
5861 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
5862 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
5863 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
5864 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
5865 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
5866 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
5867 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
5868 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
5869 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
5870 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
5871 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
5872 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
5873 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
5874 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
5875 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
5876 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
5877 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
5878 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
5879 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
5880 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
5881 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
5882 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
5883 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
5884 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
5885 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
5886 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
5887 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
5888 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
5889 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
5890 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
5891 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
5892 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
5893 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
5894 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
5895 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
5896 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
5897 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
5898 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
5899 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
5900 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
5901 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
5902 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
5903 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
5904 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
5905 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
5906 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
5907 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
5908 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
5909 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
5910 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
5911 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
5912 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
5913 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
5914 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
5915 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
5916 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
5917 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
5918 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
5919 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
5920 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
5921 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
5922 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
5923 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
5924 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
5925 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
5926 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
5927 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
5928 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
5929 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
5930 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
5931 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
5932 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
5934 /* SPE binary operations expecting a 5-bit unsigned literal. */
5935 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
5937 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
5938 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
5939 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
5940 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
5941 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
5942 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
5943 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
5944 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
5945 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
5946 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
5947 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
5948 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
5949 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
5950 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
5951 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
5952 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
5953 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
5954 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
5955 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
5956 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
5957 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
5958 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
5959 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
5960 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
5961 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
5962 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
5964 /* Place-holder. Leave as last binary SPE builtin. */
5965 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR },
5968 /* AltiVec predicates. */
5970 struct builtin_description_predicates
5972 const unsigned int mask;
5973 const enum insn_code icode;
5974 const char *opcode;
5975 const char *const name;
5976 const enum rs6000_builtins code;
5979 static const struct builtin_description_predicates bdesc_altivec_preds[] =
5981 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
5982 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
5983 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
5984 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
5985 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
5986 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
5987 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
5988 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
5989 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
5990 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
5991 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
5992 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
5993 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
5996 /* SPE predicates. */
5997 static struct builtin_description bdesc_spe_predicates[] =
5999 /* Place-holder. Leave as first. */
6000 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6001 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6002 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6003 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6004 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6005 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6006 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6007 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6008 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6009 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6010 /* Place-holder. Leave as last. */
6011 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6014 /* SPE evsel predicates. */
6015 static struct builtin_description bdesc_spe_evsel[] =
6017 /* Place-holder. Leave as first. */
6018 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6019 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6020 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6021 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6022 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6023 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6024 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6025 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6026 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6027 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6028 /* Place-holder. Leave as last. */
6029 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6032 /* ABS* operations. */
6034 static const struct builtin_description bdesc_abs[] =
6036 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6037 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6038 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6039 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6040 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6041 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6042 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6045 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6046 foo (VECa). */
6048 static struct builtin_description bdesc_1arg[] =
6050 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6051 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6052 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6053 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6054 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6055 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6056 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6057 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6058 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6059 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6060 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6061 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6062 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6063 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6064 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6065 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6066 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6068 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6069 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6070 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6071 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6072 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6073 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6074 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6075 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6076 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6077 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6078 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6079 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6080 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6081 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6082 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6083 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6084 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6085 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6086 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6087 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6088 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6089 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6090 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6091 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6092 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6093 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
6094 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6095 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6096 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6097 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
6099 /* Place-holder. Leave as last unary SPE builtin. */
6100 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
6103 static rtx
6104 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
6106 rtx pat;
6107 tree arg0 = TREE_VALUE (arglist);
6108 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6109 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6110 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6112 if (icode == CODE_FOR_nothing)
6113 /* Builtin not supported on this processor. */
6114 return 0;
6116 /* If we got invalid arguments bail out before generating bad rtl. */
6117 if (arg0 == error_mark_node)
6118 return const0_rtx;
6120 if (icode == CODE_FOR_altivec_vspltisb
6121 || icode == CODE_FOR_altivec_vspltish
6122 || icode == CODE_FOR_altivec_vspltisw
6123 || icode == CODE_FOR_spe_evsplatfi
6124 || icode == CODE_FOR_spe_evsplati)
6126 /* Only allow 5-bit *signed* literals. */
6127 if (GET_CODE (op0) != CONST_INT
6128 || INTVAL (op0) > 0x1f
6129 || INTVAL (op0) < -0x1f)
6131 error ("argument 1 must be a 5-bit signed literal");
6132 return const0_rtx;
6136 if (target == 0
6137 || GET_MODE (target) != tmode
6138 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6139 target = gen_reg_rtx (tmode);
6141 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6142 op0 = copy_to_mode_reg (mode0, op0);
6144 pat = GEN_FCN (icode) (target, op0);
6145 if (! pat)
6146 return 0;
6147 emit_insn (pat);
6149 return target;
6152 static rtx
6153 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
6155 rtx pat, scratch1, scratch2;
6156 tree arg0 = TREE_VALUE (arglist);
6157 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6158 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6159 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6161 /* If we have invalid arguments, bail out before generating bad rtl. */
6162 if (arg0 == error_mark_node)
6163 return const0_rtx;
6165 if (target == 0
6166 || GET_MODE (target) != tmode
6167 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6168 target = gen_reg_rtx (tmode);
6170 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6171 op0 = copy_to_mode_reg (mode0, op0);
6173 scratch1 = gen_reg_rtx (mode0);
6174 scratch2 = gen_reg_rtx (mode0);
6176 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6177 if (! pat)
6178 return 0;
6179 emit_insn (pat);
6181 return target;
6184 static rtx
6185 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6187 rtx pat;
6188 tree arg0 = TREE_VALUE (arglist);
6189 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6190 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6191 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6192 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6193 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6194 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6196 if (icode == CODE_FOR_nothing)
6197 /* Builtin not supported on this processor. */
6198 return 0;
6200 /* If we got invalid arguments bail out before generating bad rtl. */
6201 if (arg0 == error_mark_node || arg1 == error_mark_node)
6202 return const0_rtx;
6204 if (icode == CODE_FOR_altivec_vcfux
6205 || icode == CODE_FOR_altivec_vcfsx
6206 || icode == CODE_FOR_altivec_vctsxs
6207 || icode == CODE_FOR_altivec_vctuxs
6208 || icode == CODE_FOR_altivec_vspltb
6209 || icode == CODE_FOR_altivec_vsplth
6210 || icode == CODE_FOR_altivec_vspltw
6211 || icode == CODE_FOR_spe_evaddiw
6212 || icode == CODE_FOR_spe_evldd
6213 || icode == CODE_FOR_spe_evldh
6214 || icode == CODE_FOR_spe_evldw
6215 || icode == CODE_FOR_spe_evlhhesplat
6216 || icode == CODE_FOR_spe_evlhhossplat
6217 || icode == CODE_FOR_spe_evlhhousplat
6218 || icode == CODE_FOR_spe_evlwhe
6219 || icode == CODE_FOR_spe_evlwhos
6220 || icode == CODE_FOR_spe_evlwhou
6221 || icode == CODE_FOR_spe_evlwhsplat
6222 || icode == CODE_FOR_spe_evlwwsplat
6223 || icode == CODE_FOR_spe_evrlwi
6224 || icode == CODE_FOR_spe_evslwi
6225 || icode == CODE_FOR_spe_evsrwis
6226 || icode == CODE_FOR_spe_evsubifw
6227 || icode == CODE_FOR_spe_evsrwiu)
6229 /* Only allow 5-bit unsigned literals. */
6230 STRIP_NOPS (arg1);
6231 if (TREE_CODE (arg1) != INTEGER_CST
6232 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6234 error ("argument 2 must be a 5-bit unsigned literal");
6235 return const0_rtx;
6239 if (target == 0
6240 || GET_MODE (target) != tmode
6241 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6242 target = gen_reg_rtx (tmode);
6244 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6245 op0 = copy_to_mode_reg (mode0, op0);
6246 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6247 op1 = copy_to_mode_reg (mode1, op1);
6249 pat = GEN_FCN (icode) (target, op0, op1);
6250 if (! pat)
6251 return 0;
6252 emit_insn (pat);
6254 return target;
6257 static rtx
6258 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6259 tree arglist, rtx target)
6261 rtx pat, scratch;
6262 tree cr6_form = TREE_VALUE (arglist);
6263 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6264 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6265 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6266 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6267 enum machine_mode tmode = SImode;
6268 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6269 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6270 int cr6_form_int;
6272 if (TREE_CODE (cr6_form) != INTEGER_CST)
6274 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6275 return const0_rtx;
6277 else
6278 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6280 if (mode0 != mode1)
6281 abort ();
6283 /* If we have invalid arguments, bail out before generating bad rtl. */
6284 if (arg0 == error_mark_node || arg1 == error_mark_node)
6285 return const0_rtx;
6287 if (target == 0
6288 || GET_MODE (target) != tmode
6289 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6290 target = gen_reg_rtx (tmode);
6292 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6293 op0 = copy_to_mode_reg (mode0, op0);
6294 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6295 op1 = copy_to_mode_reg (mode1, op1);
6297 scratch = gen_reg_rtx (mode0);
6299 pat = GEN_FCN (icode) (scratch, op0, op1,
6300 gen_rtx_SYMBOL_REF (Pmode, opcode));
6301 if (! pat)
6302 return 0;
6303 emit_insn (pat);
6305 /* The vec_any* and vec_all* predicates use the same opcodes for two
6306 different operations, but the bits in CR6 will be different
6307 depending on what information we want. So we have to play tricks
6308 with CR6 to get the right bits out.
6310 If you think this is disgusting, look at the specs for the
6311 AltiVec predicates. */
6313 switch (cr6_form_int)
6315 case 0:
6316 emit_insn (gen_cr6_test_for_zero (target));
6317 break;
6318 case 1:
6319 emit_insn (gen_cr6_test_for_zero_reverse (target));
6320 break;
6321 case 2:
6322 emit_insn (gen_cr6_test_for_lt (target));
6323 break;
6324 case 3:
6325 emit_insn (gen_cr6_test_for_lt_reverse (target));
6326 break;
6327 default:
6328 error ("argument 1 of __builtin_altivec_predicate is out of range");
6329 break;
6332 return target;
6335 static rtx
6336 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6338 rtx pat, addr;
6339 tree arg0 = TREE_VALUE (arglist);
6340 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6341 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6342 enum machine_mode mode0 = Pmode;
6343 enum machine_mode mode1 = Pmode;
6344 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6345 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6347 if (icode == CODE_FOR_nothing)
6348 /* Builtin not supported on this processor. */
6349 return 0;
6351 /* If we got invalid arguments bail out before generating bad rtl. */
6352 if (arg0 == error_mark_node || arg1 == error_mark_node)
6353 return const0_rtx;
6355 if (target == 0
6356 || GET_MODE (target) != tmode
6357 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6358 target = gen_reg_rtx (tmode);
6360 op1 = copy_to_mode_reg (mode1, op1);
6362 if (op0 == const0_rtx)
6364 addr = gen_rtx_MEM (tmode, op1);
6366 else
6368 op0 = copy_to_mode_reg (mode0, op0);
6369 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6372 pat = GEN_FCN (icode) (target, addr);
6374 if (! pat)
6375 return 0;
6376 emit_insn (pat);
6378 return target;
6381 static rtx
6382 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6384 tree arg0 = TREE_VALUE (arglist);
6385 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6386 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6387 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6388 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6389 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6390 rtx pat;
6391 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6392 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6393 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6395 /* Invalid arguments. Bail before doing anything stoopid! */
6396 if (arg0 == error_mark_node
6397 || arg1 == error_mark_node
6398 || arg2 == error_mark_node)
6399 return const0_rtx;
6401 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6402 op0 = copy_to_mode_reg (mode2, op0);
6403 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6404 op1 = copy_to_mode_reg (mode0, op1);
6405 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6406 op2 = copy_to_mode_reg (mode1, op2);
6408 pat = GEN_FCN (icode) (op1, op2, op0);
6409 if (pat)
6410 emit_insn (pat);
6411 return NULL_RTX;
6414 static rtx
6415 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6417 tree arg0 = TREE_VALUE (arglist);
6418 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6419 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6420 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6421 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6422 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6423 rtx pat, addr;
6424 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6425 enum machine_mode mode1 = Pmode;
6426 enum machine_mode mode2 = Pmode;
6428 /* Invalid arguments. Bail before doing anything stoopid! */
6429 if (arg0 == error_mark_node
6430 || arg1 == error_mark_node
6431 || arg2 == error_mark_node)
6432 return const0_rtx;
6434 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6435 op0 = copy_to_mode_reg (tmode, op0);
6437 op2 = copy_to_mode_reg (mode2, op2);
6439 if (op1 == const0_rtx)
6441 addr = gen_rtx_MEM (tmode, op2);
6443 else
6445 op1 = copy_to_mode_reg (mode1, op1);
6446 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6449 pat = GEN_FCN (icode) (addr, op0);
6450 if (pat)
6451 emit_insn (pat);
6452 return NULL_RTX;
6455 static rtx
6456 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
6458 rtx pat;
6459 tree arg0 = TREE_VALUE (arglist);
6460 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6461 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6462 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6463 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6464 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6465 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6466 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6467 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6468 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
6470 if (icode == CODE_FOR_nothing)
6471 /* Builtin not supported on this processor. */
6472 return 0;
6474 /* If we got invalid arguments bail out before generating bad rtl. */
6475 if (arg0 == error_mark_node
6476 || arg1 == error_mark_node
6477 || arg2 == error_mark_node)
6478 return const0_rtx;
6480 if (icode == CODE_FOR_altivec_vsldoi_4sf
6481 || icode == CODE_FOR_altivec_vsldoi_4si
6482 || icode == CODE_FOR_altivec_vsldoi_8hi
6483 || icode == CODE_FOR_altivec_vsldoi_16qi)
6485 /* Only allow 4-bit unsigned literals. */
6486 STRIP_NOPS (arg2);
6487 if (TREE_CODE (arg2) != INTEGER_CST
6488 || TREE_INT_CST_LOW (arg2) & ~0xf)
6490 error ("argument 3 must be a 4-bit unsigned literal");
6491 return const0_rtx;
6495 if (target == 0
6496 || GET_MODE (target) != tmode
6497 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6498 target = gen_reg_rtx (tmode);
6500 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6501 op0 = copy_to_mode_reg (mode0, op0);
6502 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6503 op1 = copy_to_mode_reg (mode1, op1);
6504 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
6505 op2 = copy_to_mode_reg (mode2, op2);
6507 pat = GEN_FCN (icode) (target, op0, op1, op2);
6508 if (! pat)
6509 return 0;
6510 emit_insn (pat);
6512 return target;
6515 /* Expand the lvx builtins. */
6516 static rtx
6517 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
6519 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6520 tree arglist = TREE_OPERAND (exp, 1);
6521 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6522 tree arg0;
6523 enum machine_mode tmode, mode0;
6524 rtx pat, op0;
6525 enum insn_code icode;
6527 switch (fcode)
6529 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
6530 icode = CODE_FOR_altivec_lvx_16qi;
6531 break;
6532 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
6533 icode = CODE_FOR_altivec_lvx_8hi;
6534 break;
6535 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
6536 icode = CODE_FOR_altivec_lvx_4si;
6537 break;
6538 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
6539 icode = CODE_FOR_altivec_lvx_4sf;
6540 break;
6541 default:
6542 *expandedp = false;
6543 return NULL_RTX;
6546 *expandedp = true;
6548 arg0 = TREE_VALUE (arglist);
6549 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6550 tmode = insn_data[icode].operand[0].mode;
6551 mode0 = insn_data[icode].operand[1].mode;
6553 if (target == 0
6554 || GET_MODE (target) != tmode
6555 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6556 target = gen_reg_rtx (tmode);
6558 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6559 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6561 pat = GEN_FCN (icode) (target, op0);
6562 if (! pat)
6563 return 0;
6564 emit_insn (pat);
6565 return target;
6568 /* Expand the stvx builtins. */
6569 static rtx
6570 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6571 bool *expandedp)
6573 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6574 tree arglist = TREE_OPERAND (exp, 1);
6575 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6576 tree arg0, arg1;
6577 enum machine_mode mode0, mode1;
6578 rtx pat, op0, op1;
6579 enum insn_code icode;
6581 switch (fcode)
6583 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
6584 icode = CODE_FOR_altivec_stvx_16qi;
6585 break;
6586 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
6587 icode = CODE_FOR_altivec_stvx_8hi;
6588 break;
6589 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
6590 icode = CODE_FOR_altivec_stvx_4si;
6591 break;
6592 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
6593 icode = CODE_FOR_altivec_stvx_4sf;
6594 break;
6595 default:
6596 *expandedp = false;
6597 return NULL_RTX;
6600 arg0 = TREE_VALUE (arglist);
6601 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6602 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6603 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6604 mode0 = insn_data[icode].operand[0].mode;
6605 mode1 = insn_data[icode].operand[1].mode;
6607 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6608 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6609 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6610 op1 = copy_to_mode_reg (mode1, op1);
6612 pat = GEN_FCN (icode) (op0, op1);
6613 if (pat)
6614 emit_insn (pat);
6616 *expandedp = true;
6617 return NULL_RTX;
6620 /* Expand the dst builtins. */
6621 static rtx
6622 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6623 bool *expandedp)
6625 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6626 tree arglist = TREE_OPERAND (exp, 1);
6627 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6628 tree arg0, arg1, arg2;
6629 enum machine_mode mode0, mode1, mode2;
6630 rtx pat, op0, op1, op2;
6631 struct builtin_description *d;
6632 size_t i;
6634 *expandedp = false;
6636 /* Handle DST variants. */
6637 d = (struct builtin_description *) bdesc_dst;
6638 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
6639 if (d->code == fcode)
6641 arg0 = TREE_VALUE (arglist);
6642 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6643 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6644 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6645 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6646 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6647 mode0 = insn_data[d->icode].operand[0].mode;
6648 mode1 = insn_data[d->icode].operand[1].mode;
6649 mode2 = insn_data[d->icode].operand[2].mode;
6651 /* Invalid arguments, bail out before generating bad rtl. */
6652 if (arg0 == error_mark_node
6653 || arg1 == error_mark_node
6654 || arg2 == error_mark_node)
6655 return const0_rtx;
6657 *expandedp = true;
6658 STRIP_NOPS (arg2);
6659 if (TREE_CODE (arg2) != INTEGER_CST
6660 || TREE_INT_CST_LOW (arg2) & ~0x3)
6662 error ("argument to `%s' must be a 2-bit unsigned literal", d->name);
6663 return const0_rtx;
6666 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
6667 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6668 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
6669 op1 = copy_to_mode_reg (mode1, op1);
6671 pat = GEN_FCN (d->icode) (op0, op1, op2);
6672 if (pat != 0)
6673 emit_insn (pat);
6675 return NULL_RTX;
6678 return NULL_RTX;
6681 /* Expand the builtin in EXP and store the result in TARGET. Store
6682 true in *EXPANDEDP if we found a builtin to expand. */
6683 static rtx
6684 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
6686 struct builtin_description *d;
6687 struct builtin_description_predicates *dp;
6688 size_t i;
6689 enum insn_code icode;
6690 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6691 tree arglist = TREE_OPERAND (exp, 1);
6692 tree arg0;
6693 rtx op0, pat;
6694 enum machine_mode tmode, mode0;
6695 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6697 target = altivec_expand_ld_builtin (exp, target, expandedp);
6698 if (*expandedp)
6699 return target;
6701 target = altivec_expand_st_builtin (exp, target, expandedp);
6702 if (*expandedp)
6703 return target;
6705 target = altivec_expand_dst_builtin (exp, target, expandedp);
6706 if (*expandedp)
6707 return target;
6709 *expandedp = true;
6711 switch (fcode)
6713 case ALTIVEC_BUILTIN_STVX:
6714 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
6715 case ALTIVEC_BUILTIN_STVEBX:
6716 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
6717 case ALTIVEC_BUILTIN_STVEHX:
6718 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
6719 case ALTIVEC_BUILTIN_STVEWX:
6720 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
6721 case ALTIVEC_BUILTIN_STVXL:
6722 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
6724 case ALTIVEC_BUILTIN_MFVSCR:
6725 icode = CODE_FOR_altivec_mfvscr;
6726 tmode = insn_data[icode].operand[0].mode;
6728 if (target == 0
6729 || GET_MODE (target) != tmode
6730 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6731 target = gen_reg_rtx (tmode);
6733 pat = GEN_FCN (icode) (target);
6734 if (! pat)
6735 return 0;
6736 emit_insn (pat);
6737 return target;
6739 case ALTIVEC_BUILTIN_MTVSCR:
6740 icode = CODE_FOR_altivec_mtvscr;
6741 arg0 = TREE_VALUE (arglist);
6742 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6743 mode0 = insn_data[icode].operand[0].mode;
6745 /* If we got invalid arguments bail out before generating bad rtl. */
6746 if (arg0 == error_mark_node)
6747 return const0_rtx;
6749 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6750 op0 = copy_to_mode_reg (mode0, op0);
6752 pat = GEN_FCN (icode) (op0);
6753 if (pat)
6754 emit_insn (pat);
6755 return NULL_RTX;
6757 case ALTIVEC_BUILTIN_DSSALL:
6758 emit_insn (gen_altivec_dssall ());
6759 return NULL_RTX;
6761 case ALTIVEC_BUILTIN_DSS:
6762 icode = CODE_FOR_altivec_dss;
6763 arg0 = TREE_VALUE (arglist);
6764 STRIP_NOPS (arg0);
6765 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6766 mode0 = insn_data[icode].operand[0].mode;
6768 /* If we got invalid arguments bail out before generating bad rtl. */
6769 if (arg0 == error_mark_node)
6770 return const0_rtx;
6772 if (TREE_CODE (arg0) != INTEGER_CST
6773 || TREE_INT_CST_LOW (arg0) & ~0x3)
6775 error ("argument to dss must be a 2-bit unsigned literal");
6776 return const0_rtx;
6779 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6780 op0 = copy_to_mode_reg (mode0, op0);
6782 emit_insn (gen_altivec_dss (op0));
6783 return NULL_RTX;
6785 case ALTIVEC_BUILTIN_COMPILETIME_ERROR:
6786 arg0 = TREE_VALUE (arglist);
6787 while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR)
6788 arg0 = TREE_OPERAND (arg0, 0);
6789 error ("invalid parameter combination for `%s' AltiVec intrinsic",
6790 TREE_STRING_POINTER (arg0));
6792 return const0_rtx;
6795 /* Expand abs* operations. */
6796 d = (struct builtin_description *) bdesc_abs;
6797 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
6798 if (d->code == fcode)
6799 return altivec_expand_abs_builtin (d->icode, arglist, target);
6801 /* Expand the AltiVec predicates. */
6802 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
6803 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
6804 if (dp->code == fcode)
6805 return altivec_expand_predicate_builtin (dp->icode, dp->opcode, arglist, target);
6807 /* LV* are funky. We initialized them differently. */
6808 switch (fcode)
6810 case ALTIVEC_BUILTIN_LVSL:
6811 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
6812 arglist, target);
6813 case ALTIVEC_BUILTIN_LVSR:
6814 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
6815 arglist, target);
6816 case ALTIVEC_BUILTIN_LVEBX:
6817 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
6818 arglist, target);
6819 case ALTIVEC_BUILTIN_LVEHX:
6820 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
6821 arglist, target);
6822 case ALTIVEC_BUILTIN_LVEWX:
6823 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
6824 arglist, target);
6825 case ALTIVEC_BUILTIN_LVXL:
6826 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
6827 arglist, target);
6828 case ALTIVEC_BUILTIN_LVX:
6829 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
6830 arglist, target);
6831 default:
6832 break;
6833 /* Fall through. */
6836 *expandedp = false;
6837 return NULL_RTX;
6840 /* Binops that need to be initialized manually, but can be expanded
6841 automagically by rs6000_expand_binop_builtin. */
6842 static struct builtin_description bdesc_2arg_spe[] =
6844 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
6845 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
6846 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
6847 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
6848 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
6849 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
6850 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
6851 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
6852 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
6853 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
6854 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
6855 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
6856 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
6857 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
6858 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
6859 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
6860 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
6861 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
6862 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
6863 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
6864 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
6865 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
6868 /* Expand the builtin in EXP and store the result in TARGET. Store
6869 true in *EXPANDEDP if we found a builtin to expand.
6871 This expands the SPE builtins that are not simple unary and binary
6872 operations. */
6873 static rtx
6874 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
6876 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6877 tree arglist = TREE_OPERAND (exp, 1);
6878 tree arg1, arg0;
6879 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6880 enum insn_code icode;
6881 enum machine_mode tmode, mode0;
6882 rtx pat, op0;
6883 struct builtin_description *d;
6884 size_t i;
6886 *expandedp = true;
6888 /* Syntax check for a 5-bit unsigned immediate. */
6889 switch (fcode)
6891 case SPE_BUILTIN_EVSTDD:
6892 case SPE_BUILTIN_EVSTDH:
6893 case SPE_BUILTIN_EVSTDW:
6894 case SPE_BUILTIN_EVSTWHE:
6895 case SPE_BUILTIN_EVSTWHO:
6896 case SPE_BUILTIN_EVSTWWE:
6897 case SPE_BUILTIN_EVSTWWO:
6898 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6899 if (TREE_CODE (arg1) != INTEGER_CST
6900 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6902 error ("argument 2 must be a 5-bit unsigned literal");
6903 return const0_rtx;
6905 break;
6906 default:
6907 break;
6910 /* The evsplat*i instructions are not quite generic. */
6911 switch (fcode)
6913 case SPE_BUILTIN_EVSPLATFI:
6914 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
6915 arglist, target);
6916 case SPE_BUILTIN_EVSPLATI:
6917 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
6918 arglist, target);
6919 default:
6920 break;
6923 d = (struct builtin_description *) bdesc_2arg_spe;
6924 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
6925 if (d->code == fcode)
6926 return rs6000_expand_binop_builtin (d->icode, arglist, target);
6928 d = (struct builtin_description *) bdesc_spe_predicates;
6929 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
6930 if (d->code == fcode)
6931 return spe_expand_predicate_builtin (d->icode, arglist, target);
6933 d = (struct builtin_description *) bdesc_spe_evsel;
6934 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
6935 if (d->code == fcode)
6936 return spe_expand_evsel_builtin (d->icode, arglist, target);
6938 switch (fcode)
6940 case SPE_BUILTIN_EVSTDDX:
6941 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
6942 case SPE_BUILTIN_EVSTDHX:
6943 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
6944 case SPE_BUILTIN_EVSTDWX:
6945 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
6946 case SPE_BUILTIN_EVSTWHEX:
6947 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
6948 case SPE_BUILTIN_EVSTWHOX:
6949 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
6950 case SPE_BUILTIN_EVSTWWEX:
6951 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
6952 case SPE_BUILTIN_EVSTWWOX:
6953 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
6954 case SPE_BUILTIN_EVSTDD:
6955 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
6956 case SPE_BUILTIN_EVSTDH:
6957 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
6958 case SPE_BUILTIN_EVSTDW:
6959 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
6960 case SPE_BUILTIN_EVSTWHE:
6961 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
6962 case SPE_BUILTIN_EVSTWHO:
6963 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
6964 case SPE_BUILTIN_EVSTWWE:
6965 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
6966 case SPE_BUILTIN_EVSTWWO:
6967 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
6968 case SPE_BUILTIN_MFSPEFSCR:
6969 icode = CODE_FOR_spe_mfspefscr;
6970 tmode = insn_data[icode].operand[0].mode;
6972 if (target == 0
6973 || GET_MODE (target) != tmode
6974 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6975 target = gen_reg_rtx (tmode);
6977 pat = GEN_FCN (icode) (target);
6978 if (! pat)
6979 return 0;
6980 emit_insn (pat);
6981 return target;
6982 case SPE_BUILTIN_MTSPEFSCR:
6983 icode = CODE_FOR_spe_mtspefscr;
6984 arg0 = TREE_VALUE (arglist);
6985 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6986 mode0 = insn_data[icode].operand[0].mode;
6988 if (arg0 == error_mark_node)
6989 return const0_rtx;
6991 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6992 op0 = copy_to_mode_reg (mode0, op0);
6994 pat = GEN_FCN (icode) (op0);
6995 if (pat)
6996 emit_insn (pat);
6997 return NULL_RTX;
6998 default:
6999 break;
7002 *expandedp = false;
7003 return NULL_RTX;
7006 static rtx
7007 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
7009 rtx pat, scratch, tmp;
7010 tree form = TREE_VALUE (arglist);
7011 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7012 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7013 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7014 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7015 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7016 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7017 int form_int;
7018 enum rtx_code code;
7020 if (TREE_CODE (form) != INTEGER_CST)
7022 error ("argument 1 of __builtin_spe_predicate must be a constant");
7023 return const0_rtx;
7025 else
7026 form_int = TREE_INT_CST_LOW (form);
7028 if (mode0 != mode1)
7029 abort ();
7031 if (arg0 == error_mark_node || arg1 == error_mark_node)
7032 return const0_rtx;
7034 if (target == 0
7035 || GET_MODE (target) != SImode
7036 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7037 target = gen_reg_rtx (SImode);
7039 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7040 op0 = copy_to_mode_reg (mode0, op0);
7041 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7042 op1 = copy_to_mode_reg (mode1, op1);
7044 scratch = gen_reg_rtx (CCmode);
7046 pat = GEN_FCN (icode) (scratch, op0, op1);
7047 if (! pat)
7048 return const0_rtx;
7049 emit_insn (pat);
7051 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7052 _lower_. We use one compare, but look in different bits of the
7053 CR for each variant.
7055 There are 2 elements in each SPE simd type (upper/lower). The CR
7056 bits are set as follows:
7058 BIT0 | BIT 1 | BIT 2 | BIT 3
7059 U | L | (U | L) | (U & L)
7061 So, for an "all" relationship, BIT 3 would be set.
7062 For an "any" relationship, BIT 2 would be set. Etc.
7064 Following traditional nomenclature, these bits map to:
7066 BIT0 | BIT 1 | BIT 2 | BIT 3
7067 LT | GT | EQ | OV
7069 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7072 switch (form_int)
7074 /* All variant. OV bit. */
7075 case 0:
7076 /* We need to get to the OV bit, which is the ORDERED bit. We
7077 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7078 that's ugly and will trigger a validate_condition_mode abort.
7079 So let's just use another pattern. */
7080 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7081 return target;
7082 /* Any variant. EQ bit. */
7083 case 1:
7084 code = EQ;
7085 break;
7086 /* Upper variant. LT bit. */
7087 case 2:
7088 code = LT;
7089 break;
7090 /* Lower variant. GT bit. */
7091 case 3:
7092 code = GT;
7093 break;
7094 default:
7095 error ("argument 1 of __builtin_spe_predicate is out of range");
7096 return const0_rtx;
7099 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7100 emit_move_insn (target, tmp);
7102 return target;
7105 /* The evsel builtins look like this:
7107 e = __builtin_spe_evsel_OP (a, b, c, d);
7109 and work like this:
7111 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7112 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7115 static rtx
7116 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
7118 rtx pat, scratch;
7119 tree arg0 = TREE_VALUE (arglist);
7120 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7121 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7122 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7123 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7124 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7125 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7126 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
7127 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7128 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7130 if (mode0 != mode1)
7131 abort ();
7133 if (arg0 == error_mark_node || arg1 == error_mark_node
7134 || arg2 == error_mark_node || arg3 == error_mark_node)
7135 return const0_rtx;
7137 if (target == 0
7138 || GET_MODE (target) != mode0
7139 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7140 target = gen_reg_rtx (mode0);
7142 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7143 op0 = copy_to_mode_reg (mode0, op0);
7144 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7145 op1 = copy_to_mode_reg (mode0, op1);
7146 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7147 op2 = copy_to_mode_reg (mode0, op2);
7148 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7149 op3 = copy_to_mode_reg (mode0, op3);
7151 /* Generate the compare. */
7152 scratch = gen_reg_rtx (CCmode);
7153 pat = GEN_FCN (icode) (scratch, op0, op1);
7154 if (! pat)
7155 return const0_rtx;
7156 emit_insn (pat);
7158 if (mode0 == V2SImode)
7159 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7160 else
7161 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7163 return target;
7166 /* Expand an expression EXP that calls a built-in function,
7167 with result going to TARGET if that's convenient
7168 (and in mode MODE if that's convenient).
7169 SUBTARGET may be used as the target for computing one of EXP's operands.
7170 IGNORE is nonzero if the value is to be ignored. */
7172 static rtx
7173 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7174 enum machine_mode mode ATTRIBUTE_UNUSED,
7175 int ignore ATTRIBUTE_UNUSED)
7177 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7178 tree arglist = TREE_OPERAND (exp, 1);
7179 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7180 struct builtin_description *d;
7181 size_t i;
7182 rtx ret;
7183 bool success;
7185 if (TARGET_ALTIVEC)
7187 ret = altivec_expand_builtin (exp, target, &success);
7189 if (success)
7190 return ret;
7192 if (TARGET_SPE)
7194 ret = spe_expand_builtin (exp, target, &success);
7196 if (success)
7197 return ret;
7200 if (TARGET_ALTIVEC || TARGET_SPE)
7202 /* Handle simple unary operations. */
7203 d = (struct builtin_description *) bdesc_1arg;
7204 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7205 if (d->code == fcode)
7206 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7208 /* Handle simple binary operations. */
7209 d = (struct builtin_description *) bdesc_2arg;
7210 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7211 if (d->code == fcode)
7212 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7214 /* Handle simple ternary operations. */
7215 d = (struct builtin_description *) bdesc_3arg;
7216 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7217 if (d->code == fcode)
7218 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7221 abort ();
7222 return NULL_RTX;
7225 static tree
7226 build_opaque_vector_type (tree node, int nunits)
7228 node = copy_node (node);
7229 TYPE_MAIN_VARIANT (node) = node;
7230 return build_vector_type (node, nunits);
7233 static void
7234 rs6000_init_builtins (void)
7236 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7237 V2SF_type_node = build_vector_type (float_type_node, 2);
7238 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7239 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7240 V4SF_type_node = build_vector_type (float_type_node, 4);
7241 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7242 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7244 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7245 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7246 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7248 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7249 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7250 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7252 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7253 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7254 'vector unsigned short'. */
7256 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7257 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7258 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7259 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7261 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7262 get_identifier ("__bool char"),
7263 bool_char_type_node));
7264 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7265 get_identifier ("__bool short"),
7266 bool_short_type_node));
7267 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7268 get_identifier ("__bool int"),
7269 bool_int_type_node));
7270 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7271 get_identifier ("__pixel"),
7272 pixel_type_node));
7274 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7275 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7276 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7277 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
7279 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7280 get_identifier ("__vector unsigned char"),
7281 unsigned_V16QI_type_node));
7282 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7283 get_identifier ("__vector signed char"),
7284 V16QI_type_node));
7285 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7286 get_identifier ("__vector __bool char"),
7287 bool_V16QI_type_node));
7289 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7290 get_identifier ("__vector unsigned short"),
7291 unsigned_V8HI_type_node));
7292 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7293 get_identifier ("__vector signed short"),
7294 V8HI_type_node));
7295 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7296 get_identifier ("__vector __bool short"),
7297 bool_V8HI_type_node));
7299 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7300 get_identifier ("__vector unsigned int"),
7301 unsigned_V4SI_type_node));
7302 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7303 get_identifier ("__vector signed int"),
7304 V4SI_type_node));
7305 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7306 get_identifier ("__vector __bool int"),
7307 bool_V4SI_type_node));
7309 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7310 get_identifier ("__vector float"),
7311 V4SF_type_node));
7312 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7313 get_identifier ("__vector __pixel"),
7314 pixel_V8HI_type_node));
7316 if (TARGET_SPE)
7317 spe_init_builtins ();
7318 if (TARGET_ALTIVEC)
7319 altivec_init_builtins ();
7320 if (TARGET_ALTIVEC || TARGET_SPE)
7321 rs6000_common_init_builtins ();
7324 /* Search through a set of builtins and enable the mask bits.
7325 DESC is an array of builtins.
7326 SIZE is the total number of builtins.
7327 START is the builtin enum at which to start.
7328 END is the builtin enum at which to end. */
7329 static void
7330 enable_mask_for_builtins (struct builtin_description *desc, int size,
7331 enum rs6000_builtins start,
7332 enum rs6000_builtins end)
7334 int i;
7336 for (i = 0; i < size; ++i)
7337 if (desc[i].code == start)
7338 break;
7340 if (i == size)
7341 return;
7343 for (; i < size; ++i)
7345 /* Flip all the bits on. */
7346 desc[i].mask = target_flags;
7347 if (desc[i].code == end)
7348 break;
7352 static void
7353 spe_init_builtins (void)
7355 tree endlink = void_list_node;
7356 tree puint_type_node = build_pointer_type (unsigned_type_node);
7357 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
7358 struct builtin_description *d;
7359 size_t i;
7361 tree v2si_ftype_4_v2si
7362 = build_function_type
7363 (opaque_V2SI_type_node,
7364 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7365 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7366 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7367 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7368 endlink)))));
7370 tree v2sf_ftype_4_v2sf
7371 = build_function_type
7372 (opaque_V2SF_type_node,
7373 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7374 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7375 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7376 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7377 endlink)))));
7379 tree int_ftype_int_v2si_v2si
7380 = build_function_type
7381 (integer_type_node,
7382 tree_cons (NULL_TREE, integer_type_node,
7383 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7384 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7385 endlink))));
7387 tree int_ftype_int_v2sf_v2sf
7388 = build_function_type
7389 (integer_type_node,
7390 tree_cons (NULL_TREE, integer_type_node,
7391 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7392 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7393 endlink))));
7395 tree void_ftype_v2si_puint_int
7396 = build_function_type (void_type_node,
7397 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7398 tree_cons (NULL_TREE, puint_type_node,
7399 tree_cons (NULL_TREE,
7400 integer_type_node,
7401 endlink))));
7403 tree void_ftype_v2si_puint_char
7404 = build_function_type (void_type_node,
7405 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7406 tree_cons (NULL_TREE, puint_type_node,
7407 tree_cons (NULL_TREE,
7408 char_type_node,
7409 endlink))));
7411 tree void_ftype_v2si_pv2si_int
7412 = build_function_type (void_type_node,
7413 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7414 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7415 tree_cons (NULL_TREE,
7416 integer_type_node,
7417 endlink))));
7419 tree void_ftype_v2si_pv2si_char
7420 = build_function_type (void_type_node,
7421 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7422 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7423 tree_cons (NULL_TREE,
7424 char_type_node,
7425 endlink))));
7427 tree void_ftype_int
7428 = build_function_type (void_type_node,
7429 tree_cons (NULL_TREE, integer_type_node, endlink));
7431 tree int_ftype_void
7432 = build_function_type (integer_type_node, endlink);
7434 tree v2si_ftype_pv2si_int
7435 = build_function_type (opaque_V2SI_type_node,
7436 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7437 tree_cons (NULL_TREE, integer_type_node,
7438 endlink)));
7440 tree v2si_ftype_puint_int
7441 = build_function_type (opaque_V2SI_type_node,
7442 tree_cons (NULL_TREE, puint_type_node,
7443 tree_cons (NULL_TREE, integer_type_node,
7444 endlink)));
7446 tree v2si_ftype_pushort_int
7447 = build_function_type (opaque_V2SI_type_node,
7448 tree_cons (NULL_TREE, pushort_type_node,
7449 tree_cons (NULL_TREE, integer_type_node,
7450 endlink)));
7452 tree v2si_ftype_signed_char
7453 = build_function_type (opaque_V2SI_type_node,
7454 tree_cons (NULL_TREE, signed_char_type_node,
7455 endlink));
7457 /* The initialization of the simple binary and unary builtins is
7458 done in rs6000_common_init_builtins, but we have to enable the
7459 mask bits here manually because we have run out of `target_flags'
7460 bits. We really need to redesign this mask business. */
7462 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
7463 ARRAY_SIZE (bdesc_2arg),
7464 SPE_BUILTIN_EVADDW,
7465 SPE_BUILTIN_EVXOR);
7466 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
7467 ARRAY_SIZE (bdesc_1arg),
7468 SPE_BUILTIN_EVABS,
7469 SPE_BUILTIN_EVSUBFUSIAAW);
7470 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
7471 ARRAY_SIZE (bdesc_spe_predicates),
7472 SPE_BUILTIN_EVCMPEQ,
7473 SPE_BUILTIN_EVFSTSTLT);
7474 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
7475 ARRAY_SIZE (bdesc_spe_evsel),
7476 SPE_BUILTIN_EVSEL_CMPGTS,
7477 SPE_BUILTIN_EVSEL_FSTSTEQ);
7479 (*lang_hooks.decls.pushdecl)
7480 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
7481 opaque_V2SI_type_node));
7483 /* Initialize irregular SPE builtins. */
7485 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
7486 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
7487 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
7488 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
7489 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
7490 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
7491 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
7492 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
7493 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
7494 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
7495 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
7496 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
7497 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
7498 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
7499 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
7500 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
7501 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
7502 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
7504 /* Loads. */
7505 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
7506 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
7507 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
7508 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
7509 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
7510 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
7511 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
7512 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
7513 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
7514 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
7515 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
7516 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
7517 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
7518 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
7519 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
7520 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
7521 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
7522 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
7523 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
7524 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
7525 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
7526 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
7528 /* Predicates. */
7529 d = (struct builtin_description *) bdesc_spe_predicates;
7530 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
7532 tree type;
7534 switch (insn_data[d->icode].operand[1].mode)
7536 case V2SImode:
7537 type = int_ftype_int_v2si_v2si;
7538 break;
7539 case V2SFmode:
7540 type = int_ftype_int_v2sf_v2sf;
7541 break;
7542 default:
7543 abort ();
7546 def_builtin (d->mask, d->name, type, d->code);
7549 /* Evsel predicates. */
7550 d = (struct builtin_description *) bdesc_spe_evsel;
7551 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
7553 tree type;
7555 switch (insn_data[d->icode].operand[1].mode)
7557 case V2SImode:
7558 type = v2si_ftype_4_v2si;
7559 break;
7560 case V2SFmode:
7561 type = v2sf_ftype_4_v2sf;
7562 break;
7563 default:
7564 abort ();
7567 def_builtin (d->mask, d->name, type, d->code);
7571 static void
7572 altivec_init_builtins (void)
7574 struct builtin_description *d;
7575 struct builtin_description_predicates *dp;
7576 size_t i;
7577 tree pfloat_type_node = build_pointer_type (float_type_node);
7578 tree pint_type_node = build_pointer_type (integer_type_node);
7579 tree pshort_type_node = build_pointer_type (short_integer_type_node);
7580 tree pchar_type_node = build_pointer_type (char_type_node);
7582 tree pvoid_type_node = build_pointer_type (void_type_node);
7584 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
7585 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
7586 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
7587 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
7589 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
7591 tree int_ftype_int_v4si_v4si
7592 = build_function_type_list (integer_type_node,
7593 integer_type_node, V4SI_type_node,
7594 V4SI_type_node, NULL_TREE);
7595 tree v4sf_ftype_pcfloat
7596 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
7597 tree void_ftype_pfloat_v4sf
7598 = build_function_type_list (void_type_node,
7599 pfloat_type_node, V4SF_type_node, NULL_TREE);
7600 tree v4si_ftype_pcint
7601 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
7602 tree void_ftype_pint_v4si
7603 = build_function_type_list (void_type_node,
7604 pint_type_node, V4SI_type_node, NULL_TREE);
7605 tree v8hi_ftype_pcshort
7606 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
7607 tree void_ftype_pshort_v8hi
7608 = build_function_type_list (void_type_node,
7609 pshort_type_node, V8HI_type_node, NULL_TREE);
7610 tree v16qi_ftype_pcchar
7611 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
7612 tree void_ftype_pchar_v16qi
7613 = build_function_type_list (void_type_node,
7614 pchar_type_node, V16QI_type_node, NULL_TREE);
7615 tree void_ftype_v4si
7616 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
7617 tree v8hi_ftype_void
7618 = build_function_type (V8HI_type_node, void_list_node);
7619 tree void_ftype_void
7620 = build_function_type (void_type_node, void_list_node);
7621 tree void_ftype_int
7622 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
7624 tree v16qi_ftype_long_pcvoid
7625 = build_function_type_list (V16QI_type_node,
7626 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7627 tree v8hi_ftype_long_pcvoid
7628 = build_function_type_list (V8HI_type_node,
7629 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7630 tree v4si_ftype_long_pcvoid
7631 = build_function_type_list (V4SI_type_node,
7632 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7634 tree void_ftype_v4si_long_pvoid
7635 = build_function_type_list (void_type_node,
7636 V4SI_type_node, long_integer_type_node,
7637 pvoid_type_node, NULL_TREE);
7638 tree void_ftype_v16qi_long_pvoid
7639 = build_function_type_list (void_type_node,
7640 V16QI_type_node, long_integer_type_node,
7641 pvoid_type_node, NULL_TREE);
7642 tree void_ftype_v8hi_long_pvoid
7643 = build_function_type_list (void_type_node,
7644 V8HI_type_node, long_integer_type_node,
7645 pvoid_type_node, NULL_TREE);
7646 tree int_ftype_int_v8hi_v8hi
7647 = build_function_type_list (integer_type_node,
7648 integer_type_node, V8HI_type_node,
7649 V8HI_type_node, NULL_TREE);
7650 tree int_ftype_int_v16qi_v16qi
7651 = build_function_type_list (integer_type_node,
7652 integer_type_node, V16QI_type_node,
7653 V16QI_type_node, NULL_TREE);
7654 tree int_ftype_int_v4sf_v4sf
7655 = build_function_type_list (integer_type_node,
7656 integer_type_node, V4SF_type_node,
7657 V4SF_type_node, NULL_TREE);
7658 tree v4si_ftype_v4si
7659 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
7660 tree v8hi_ftype_v8hi
7661 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
7662 tree v16qi_ftype_v16qi
7663 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
7664 tree v4sf_ftype_v4sf
7665 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7666 tree void_ftype_pcvoid_int_int
7667 = build_function_type_list (void_type_node,
7668 pcvoid_type_node, integer_type_node,
7669 integer_type_node, NULL_TREE);
7670 tree int_ftype_pcchar
7671 = build_function_type_list (integer_type_node,
7672 pcchar_type_node, NULL_TREE);
7674 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
7675 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
7676 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
7677 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
7678 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
7679 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
7680 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
7681 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
7682 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
7683 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
7684 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
7685 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
7686 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
7687 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
7688 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
7689 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
7690 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
7691 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
7692 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
7693 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
7694 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
7695 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
7696 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
7697 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
7698 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
7699 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
7700 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
7701 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
7702 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
7703 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
7704 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
7705 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
7707 /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */
7708 def_builtin (MASK_ALTIVEC, "__builtin_altivec_compiletime_error", int_ftype_pcchar,
7709 ALTIVEC_BUILTIN_COMPILETIME_ERROR);
7711 /* Add the DST variants. */
7712 d = (struct builtin_description *) bdesc_dst;
7713 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7714 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
7716 /* Initialize the predicates. */
7717 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7718 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7720 enum machine_mode mode1;
7721 tree type;
7723 mode1 = insn_data[dp->icode].operand[1].mode;
7725 switch (mode1)
7727 case V4SImode:
7728 type = int_ftype_int_v4si_v4si;
7729 break;
7730 case V8HImode:
7731 type = int_ftype_int_v8hi_v8hi;
7732 break;
7733 case V16QImode:
7734 type = int_ftype_int_v16qi_v16qi;
7735 break;
7736 case V4SFmode:
7737 type = int_ftype_int_v4sf_v4sf;
7738 break;
7739 default:
7740 abort ();
7743 def_builtin (dp->mask, dp->name, type, dp->code);
7746 /* Initialize the abs* operators. */
7747 d = (struct builtin_description *) bdesc_abs;
7748 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7750 enum machine_mode mode0;
7751 tree type;
7753 mode0 = insn_data[d->icode].operand[0].mode;
7755 switch (mode0)
7757 case V4SImode:
7758 type = v4si_ftype_v4si;
7759 break;
7760 case V8HImode:
7761 type = v8hi_ftype_v8hi;
7762 break;
7763 case V16QImode:
7764 type = v16qi_ftype_v16qi;
7765 break;
7766 case V4SFmode:
7767 type = v4sf_ftype_v4sf;
7768 break;
7769 default:
7770 abort ();
7773 def_builtin (d->mask, d->name, type, d->code);
7777 static void
7778 rs6000_common_init_builtins (void)
7780 struct builtin_description *d;
7781 size_t i;
7783 tree v4sf_ftype_v4sf_v4sf_v16qi
7784 = build_function_type_list (V4SF_type_node,
7785 V4SF_type_node, V4SF_type_node,
7786 V16QI_type_node, NULL_TREE);
7787 tree v4si_ftype_v4si_v4si_v16qi
7788 = build_function_type_list (V4SI_type_node,
7789 V4SI_type_node, V4SI_type_node,
7790 V16QI_type_node, NULL_TREE);
7791 tree v8hi_ftype_v8hi_v8hi_v16qi
7792 = build_function_type_list (V8HI_type_node,
7793 V8HI_type_node, V8HI_type_node,
7794 V16QI_type_node, NULL_TREE);
7795 tree v16qi_ftype_v16qi_v16qi_v16qi
7796 = build_function_type_list (V16QI_type_node,
7797 V16QI_type_node, V16QI_type_node,
7798 V16QI_type_node, NULL_TREE);
7799 tree v4si_ftype_int
7800 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
7801 tree v8hi_ftype_int
7802 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
7803 tree v16qi_ftype_int
7804 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
7805 tree v8hi_ftype_v16qi
7806 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
7807 tree v4sf_ftype_v4sf
7808 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7810 tree v2si_ftype_v2si_v2si
7811 = build_function_type_list (opaque_V2SI_type_node,
7812 opaque_V2SI_type_node,
7813 opaque_V2SI_type_node, NULL_TREE);
7815 tree v2sf_ftype_v2sf_v2sf
7816 = build_function_type_list (opaque_V2SF_type_node,
7817 opaque_V2SF_type_node,
7818 opaque_V2SF_type_node, NULL_TREE);
7820 tree v2si_ftype_int_int
7821 = build_function_type_list (opaque_V2SI_type_node,
7822 integer_type_node, integer_type_node,
7823 NULL_TREE);
7825 tree v2si_ftype_v2si
7826 = build_function_type_list (opaque_V2SI_type_node,
7827 opaque_V2SI_type_node, NULL_TREE);
7829 tree v2sf_ftype_v2sf
7830 = build_function_type_list (opaque_V2SF_type_node,
7831 opaque_V2SF_type_node, NULL_TREE);
7833 tree v2sf_ftype_v2si
7834 = build_function_type_list (opaque_V2SF_type_node,
7835 opaque_V2SI_type_node, NULL_TREE);
7837 tree v2si_ftype_v2sf
7838 = build_function_type_list (opaque_V2SI_type_node,
7839 opaque_V2SF_type_node, NULL_TREE);
7841 tree v2si_ftype_v2si_char
7842 = build_function_type_list (opaque_V2SI_type_node,
7843 opaque_V2SI_type_node,
7844 char_type_node, NULL_TREE);
7846 tree v2si_ftype_int_char
7847 = build_function_type_list (opaque_V2SI_type_node,
7848 integer_type_node, char_type_node, NULL_TREE);
7850 tree v2si_ftype_char
7851 = build_function_type_list (opaque_V2SI_type_node,
7852 char_type_node, NULL_TREE);
7854 tree int_ftype_int_int
7855 = build_function_type_list (integer_type_node,
7856 integer_type_node, integer_type_node,
7857 NULL_TREE);
7859 tree v4si_ftype_v4si_v4si
7860 = build_function_type_list (V4SI_type_node,
7861 V4SI_type_node, V4SI_type_node, NULL_TREE);
7862 tree v4sf_ftype_v4si_int
7863 = build_function_type_list (V4SF_type_node,
7864 V4SI_type_node, integer_type_node, NULL_TREE);
7865 tree v4si_ftype_v4sf_int
7866 = build_function_type_list (V4SI_type_node,
7867 V4SF_type_node, integer_type_node, NULL_TREE);
7868 tree v4si_ftype_v4si_int
7869 = build_function_type_list (V4SI_type_node,
7870 V4SI_type_node, integer_type_node, NULL_TREE);
7871 tree v8hi_ftype_v8hi_int
7872 = build_function_type_list (V8HI_type_node,
7873 V8HI_type_node, integer_type_node, NULL_TREE);
7874 tree v16qi_ftype_v16qi_int
7875 = build_function_type_list (V16QI_type_node,
7876 V16QI_type_node, integer_type_node, NULL_TREE);
7877 tree v16qi_ftype_v16qi_v16qi_int
7878 = build_function_type_list (V16QI_type_node,
7879 V16QI_type_node, V16QI_type_node,
7880 integer_type_node, NULL_TREE);
7881 tree v8hi_ftype_v8hi_v8hi_int
7882 = build_function_type_list (V8HI_type_node,
7883 V8HI_type_node, V8HI_type_node,
7884 integer_type_node, NULL_TREE);
7885 tree v4si_ftype_v4si_v4si_int
7886 = build_function_type_list (V4SI_type_node,
7887 V4SI_type_node, V4SI_type_node,
7888 integer_type_node, NULL_TREE);
7889 tree v4sf_ftype_v4sf_v4sf_int
7890 = build_function_type_list (V4SF_type_node,
7891 V4SF_type_node, V4SF_type_node,
7892 integer_type_node, NULL_TREE);
7893 tree v4sf_ftype_v4sf_v4sf
7894 = build_function_type_list (V4SF_type_node,
7895 V4SF_type_node, V4SF_type_node, NULL_TREE);
7896 tree v4sf_ftype_v4sf_v4sf_v4si
7897 = build_function_type_list (V4SF_type_node,
7898 V4SF_type_node, V4SF_type_node,
7899 V4SI_type_node, NULL_TREE);
7900 tree v4sf_ftype_v4sf_v4sf_v4sf
7901 = build_function_type_list (V4SF_type_node,
7902 V4SF_type_node, V4SF_type_node,
7903 V4SF_type_node, NULL_TREE);
7904 tree v4si_ftype_v4si_v4si_v4si
7905 = build_function_type_list (V4SI_type_node,
7906 V4SI_type_node, V4SI_type_node,
7907 V4SI_type_node, NULL_TREE);
7908 tree v8hi_ftype_v8hi_v8hi
7909 = build_function_type_list (V8HI_type_node,
7910 V8HI_type_node, V8HI_type_node, NULL_TREE);
7911 tree v8hi_ftype_v8hi_v8hi_v8hi
7912 = build_function_type_list (V8HI_type_node,
7913 V8HI_type_node, V8HI_type_node,
7914 V8HI_type_node, NULL_TREE);
7915 tree v4si_ftype_v8hi_v8hi_v4si
7916 = build_function_type_list (V4SI_type_node,
7917 V8HI_type_node, V8HI_type_node,
7918 V4SI_type_node, NULL_TREE);
7919 tree v4si_ftype_v16qi_v16qi_v4si
7920 = build_function_type_list (V4SI_type_node,
7921 V16QI_type_node, V16QI_type_node,
7922 V4SI_type_node, NULL_TREE);
7923 tree v16qi_ftype_v16qi_v16qi
7924 = build_function_type_list (V16QI_type_node,
7925 V16QI_type_node, V16QI_type_node, NULL_TREE);
7926 tree v4si_ftype_v4sf_v4sf
7927 = build_function_type_list (V4SI_type_node,
7928 V4SF_type_node, V4SF_type_node, NULL_TREE);
7929 tree v8hi_ftype_v16qi_v16qi
7930 = build_function_type_list (V8HI_type_node,
7931 V16QI_type_node, V16QI_type_node, NULL_TREE);
7932 tree v4si_ftype_v8hi_v8hi
7933 = build_function_type_list (V4SI_type_node,
7934 V8HI_type_node, V8HI_type_node, NULL_TREE);
7935 tree v8hi_ftype_v4si_v4si
7936 = build_function_type_list (V8HI_type_node,
7937 V4SI_type_node, V4SI_type_node, NULL_TREE);
7938 tree v16qi_ftype_v8hi_v8hi
7939 = build_function_type_list (V16QI_type_node,
7940 V8HI_type_node, V8HI_type_node, NULL_TREE);
7941 tree v4si_ftype_v16qi_v4si
7942 = build_function_type_list (V4SI_type_node,
7943 V16QI_type_node, V4SI_type_node, NULL_TREE);
7944 tree v4si_ftype_v16qi_v16qi
7945 = build_function_type_list (V4SI_type_node,
7946 V16QI_type_node, V16QI_type_node, NULL_TREE);
7947 tree v4si_ftype_v8hi_v4si
7948 = build_function_type_list (V4SI_type_node,
7949 V8HI_type_node, V4SI_type_node, NULL_TREE);
7950 tree v4si_ftype_v8hi
7951 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
7952 tree int_ftype_v4si_v4si
7953 = build_function_type_list (integer_type_node,
7954 V4SI_type_node, V4SI_type_node, NULL_TREE);
7955 tree int_ftype_v4sf_v4sf
7956 = build_function_type_list (integer_type_node,
7957 V4SF_type_node, V4SF_type_node, NULL_TREE);
7958 tree int_ftype_v16qi_v16qi
7959 = build_function_type_list (integer_type_node,
7960 V16QI_type_node, V16QI_type_node, NULL_TREE);
7961 tree int_ftype_v8hi_v8hi
7962 = build_function_type_list (integer_type_node,
7963 V8HI_type_node, V8HI_type_node, NULL_TREE);
7965 /* Add the simple ternary operators. */
7966 d = (struct builtin_description *) bdesc_3arg;
7967 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7970 enum machine_mode mode0, mode1, mode2, mode3;
7971 tree type;
7973 if (d->name == 0 || d->icode == CODE_FOR_nothing)
7974 continue;
7976 mode0 = insn_data[d->icode].operand[0].mode;
7977 mode1 = insn_data[d->icode].operand[1].mode;
7978 mode2 = insn_data[d->icode].operand[2].mode;
7979 mode3 = insn_data[d->icode].operand[3].mode;
7981 /* When all four are of the same mode. */
7982 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
7984 switch (mode0)
7986 case V4SImode:
7987 type = v4si_ftype_v4si_v4si_v4si;
7988 break;
7989 case V4SFmode:
7990 type = v4sf_ftype_v4sf_v4sf_v4sf;
7991 break;
7992 case V8HImode:
7993 type = v8hi_ftype_v8hi_v8hi_v8hi;
7994 break;
7995 case V16QImode:
7996 type = v16qi_ftype_v16qi_v16qi_v16qi;
7997 break;
7998 default:
7999 abort();
8002 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
8004 switch (mode0)
8006 case V4SImode:
8007 type = v4si_ftype_v4si_v4si_v16qi;
8008 break;
8009 case V4SFmode:
8010 type = v4sf_ftype_v4sf_v4sf_v16qi;
8011 break;
8012 case V8HImode:
8013 type = v8hi_ftype_v8hi_v8hi_v16qi;
8014 break;
8015 case V16QImode:
8016 type = v16qi_ftype_v16qi_v16qi_v16qi;
8017 break;
8018 default:
8019 abort();
8022 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
8023 && mode3 == V4SImode)
8024 type = v4si_ftype_v16qi_v16qi_v4si;
8025 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
8026 && mode3 == V4SImode)
8027 type = v4si_ftype_v8hi_v8hi_v4si;
8028 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
8029 && mode3 == V4SImode)
8030 type = v4sf_ftype_v4sf_v4sf_v4si;
8032 /* vchar, vchar, vchar, 4 bit literal. */
8033 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8034 && mode3 == QImode)
8035 type = v16qi_ftype_v16qi_v16qi_int;
8037 /* vshort, vshort, vshort, 4 bit literal. */
8038 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8039 && mode3 == QImode)
8040 type = v8hi_ftype_v8hi_v8hi_int;
8042 /* vint, vint, vint, 4 bit literal. */
8043 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
8044 && mode3 == QImode)
8045 type = v4si_ftype_v4si_v4si_int;
8047 /* vfloat, vfloat, vfloat, 4 bit literal. */
8048 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
8049 && mode3 == QImode)
8050 type = v4sf_ftype_v4sf_v4sf_int;
8052 else
8053 abort ();
8055 def_builtin (d->mask, d->name, type, d->code);
8058 /* Add the simple binary operators. */
8059 d = (struct builtin_description *) bdesc_2arg;
8060 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8062 enum machine_mode mode0, mode1, mode2;
8063 tree type;
8065 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8066 continue;
8068 mode0 = insn_data[d->icode].operand[0].mode;
8069 mode1 = insn_data[d->icode].operand[1].mode;
8070 mode2 = insn_data[d->icode].operand[2].mode;
8072 /* When all three operands are of the same mode. */
8073 if (mode0 == mode1 && mode1 == mode2)
8075 switch (mode0)
8077 case V4SFmode:
8078 type = v4sf_ftype_v4sf_v4sf;
8079 break;
8080 case V4SImode:
8081 type = v4si_ftype_v4si_v4si;
8082 break;
8083 case V16QImode:
8084 type = v16qi_ftype_v16qi_v16qi;
8085 break;
8086 case V8HImode:
8087 type = v8hi_ftype_v8hi_v8hi;
8088 break;
8089 case V2SImode:
8090 type = v2si_ftype_v2si_v2si;
8091 break;
8092 case V2SFmode:
8093 type = v2sf_ftype_v2sf_v2sf;
8094 break;
8095 case SImode:
8096 type = int_ftype_int_int;
8097 break;
8098 default:
8099 abort ();
8103 /* A few other combos we really don't want to do manually. */
8105 /* vint, vfloat, vfloat. */
8106 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8107 type = v4si_ftype_v4sf_v4sf;
8109 /* vshort, vchar, vchar. */
8110 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8111 type = v8hi_ftype_v16qi_v16qi;
8113 /* vint, vshort, vshort. */
8114 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
8115 type = v4si_ftype_v8hi_v8hi;
8117 /* vshort, vint, vint. */
8118 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
8119 type = v8hi_ftype_v4si_v4si;
8121 /* vchar, vshort, vshort. */
8122 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
8123 type = v16qi_ftype_v8hi_v8hi;
8125 /* vint, vchar, vint. */
8126 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
8127 type = v4si_ftype_v16qi_v4si;
8129 /* vint, vchar, vchar. */
8130 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8131 type = v4si_ftype_v16qi_v16qi;
8133 /* vint, vshort, vint. */
8134 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8135 type = v4si_ftype_v8hi_v4si;
8137 /* vint, vint, 5 bit literal. */
8138 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
8139 type = v4si_ftype_v4si_int;
8141 /* vshort, vshort, 5 bit literal. */
8142 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
8143 type = v8hi_ftype_v8hi_int;
8145 /* vchar, vchar, 5 bit literal. */
8146 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
8147 type = v16qi_ftype_v16qi_int;
8149 /* vfloat, vint, 5 bit literal. */
8150 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
8151 type = v4sf_ftype_v4si_int;
8153 /* vint, vfloat, 5 bit literal. */
8154 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
8155 type = v4si_ftype_v4sf_int;
8157 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8158 type = v2si_ftype_int_int;
8160 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8161 type = v2si_ftype_v2si_char;
8163 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
8164 type = v2si_ftype_int_char;
8166 /* int, x, x. */
8167 else if (mode0 == SImode)
8169 switch (mode1)
8171 case V4SImode:
8172 type = int_ftype_v4si_v4si;
8173 break;
8174 case V4SFmode:
8175 type = int_ftype_v4sf_v4sf;
8176 break;
8177 case V16QImode:
8178 type = int_ftype_v16qi_v16qi;
8179 break;
8180 case V8HImode:
8181 type = int_ftype_v8hi_v8hi;
8182 break;
8183 default:
8184 abort ();
8188 else
8189 abort ();
8191 def_builtin (d->mask, d->name, type, d->code);
8194 /* Add the simple unary operators. */
8195 d = (struct builtin_description *) bdesc_1arg;
8196 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8198 enum machine_mode mode0, mode1;
8199 tree type;
8201 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8202 continue;
8204 mode0 = insn_data[d->icode].operand[0].mode;
8205 mode1 = insn_data[d->icode].operand[1].mode;
8207 if (mode0 == V4SImode && mode1 == QImode)
8208 type = v4si_ftype_int;
8209 else if (mode0 == V8HImode && mode1 == QImode)
8210 type = v8hi_ftype_int;
8211 else if (mode0 == V16QImode && mode1 == QImode)
8212 type = v16qi_ftype_int;
8213 else if (mode0 == V4SFmode && mode1 == V4SFmode)
8214 type = v4sf_ftype_v4sf;
8215 else if (mode0 == V8HImode && mode1 == V16QImode)
8216 type = v8hi_ftype_v16qi;
8217 else if (mode0 == V4SImode && mode1 == V8HImode)
8218 type = v4si_ftype_v8hi;
8219 else if (mode0 == V2SImode && mode1 == V2SImode)
8220 type = v2si_ftype_v2si;
8221 else if (mode0 == V2SFmode && mode1 == V2SFmode)
8222 type = v2sf_ftype_v2sf;
8223 else if (mode0 == V2SFmode && mode1 == V2SImode)
8224 type = v2sf_ftype_v2si;
8225 else if (mode0 == V2SImode && mode1 == V2SFmode)
8226 type = v2si_ftype_v2sf;
8227 else if (mode0 == V2SImode && mode1 == QImode)
8228 type = v2si_ftype_char;
8229 else
8230 abort ();
8232 def_builtin (d->mask, d->name, type, d->code);
8236 static void
8237 rs6000_init_libfuncs (void)
8239 if (!TARGET_HARD_FLOAT)
8240 return;
8242 if (DEFAULT_ABI != ABI_V4)
8244 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
8246 /* AIX library routines for float->int conversion. */
8247 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
8248 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
8249 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
8250 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
8253 /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */
8254 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
8255 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
8256 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
8257 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
8259 else
8261 /* 32-bit SVR4 quad floating point routines. */
8263 set_optab_libfunc (add_optab, TFmode, "_q_add");
8264 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
8265 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
8266 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
8267 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
8268 if (TARGET_PPC_GPOPT || TARGET_POWER2)
8269 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
8271 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
8272 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
8273 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
8274 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
8275 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
8276 set_optab_libfunc (le_optab, TFmode, "_q_fle");
8278 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
8279 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
8280 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
8281 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
8282 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
8283 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
8284 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
8289 /* Expand a block clear operation, and return 1 if successful. Return 0
8290 if we should let the compiler generate normal code.
8292 operands[0] is the destination
8293 operands[1] is the length
8294 operands[2] is the alignment */
8297 expand_block_clear (rtx operands[])
8299 rtx orig_dest = operands[0];
8300 rtx bytes_rtx = operands[1];
8301 rtx align_rtx = operands[2];
8302 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
8303 int align;
8304 int bytes;
8305 int offset;
8306 int clear_bytes;
8308 /* If this is not a fixed size move, just call memcpy */
8309 if (! constp)
8310 return 0;
8312 /* If this is not a fixed size alignment, abort */
8313 if (GET_CODE (align_rtx) != CONST_INT)
8314 abort ();
8315 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8317 /* Anything to clear? */
8318 bytes = INTVAL (bytes_rtx);
8319 if (bytes <= 0)
8320 return 1;
8322 if (bytes > (TARGET_POWERPC64 && align >= 32 ? 64 : 32))
8323 return 0;
8325 if (optimize_size && bytes > 16)
8326 return 0;
8328 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
8330 rtx (*mov) (rtx, rtx);
8331 enum machine_mode mode = BLKmode;
8332 rtx dest;
8334 if (bytes >= 8 && TARGET_POWERPC64
8335 /* 64-bit loads and stores require word-aligned
8336 displacements. */
8337 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
8339 clear_bytes = 8;
8340 mode = DImode;
8341 mov = gen_movdi;
8343 else if (bytes >= 4 && !STRICT_ALIGNMENT)
8344 { /* move 4 bytes */
8345 clear_bytes = 4;
8346 mode = SImode;
8347 mov = gen_movsi;
8349 else if (bytes == 2 && !STRICT_ALIGNMENT)
8350 { /* move 2 bytes */
8351 clear_bytes = 2;
8352 mode = HImode;
8353 mov = gen_movhi;
8355 else /* move 1 byte at a time */
8357 clear_bytes = 1;
8358 mode = QImode;
8359 mov = gen_movqi;
8362 dest = adjust_address (orig_dest, mode, offset);
8364 emit_insn ((*mov) (dest, const0_rtx));
8367 return 1;
8371 /* Expand a block move operation, and return 1 if successful. Return 0
8372 if we should let the compiler generate normal code.
8374 operands[0] is the destination
8375 operands[1] is the source
8376 operands[2] is the length
8377 operands[3] is the alignment */
8379 #define MAX_MOVE_REG 4
8382 expand_block_move (rtx operands[])
8384 rtx orig_dest = operands[0];
8385 rtx orig_src = operands[1];
8386 rtx bytes_rtx = operands[2];
8387 rtx align_rtx = operands[3];
8388 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
8389 int align;
8390 int bytes;
8391 int offset;
8392 int move_bytes;
8393 rtx stores[MAX_MOVE_REG];
8394 int num_reg = 0;
8396 /* If this is not a fixed size move, just call memcpy */
8397 if (! constp)
8398 return 0;
8400 /* If this is not a fixed size alignment, abort */
8401 if (GET_CODE (align_rtx) != CONST_INT)
8402 abort ();
8403 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8405 /* Anything to move? */
8406 bytes = INTVAL (bytes_rtx);
8407 if (bytes <= 0)
8408 return 1;
8410 /* store_one_arg depends on expand_block_move to handle at least the size of
8411 reg_parm_stack_space. */
8412 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
8413 return 0;
8415 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
8417 union {
8418 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
8419 rtx (*mov) (rtx, rtx);
8420 } gen_func;
8421 enum machine_mode mode = BLKmode;
8422 rtx src, dest;
8424 if (TARGET_STRING
8425 && bytes > 24 /* move up to 32 bytes at a time */
8426 && ! fixed_regs[5]
8427 && ! fixed_regs[6]
8428 && ! fixed_regs[7]
8429 && ! fixed_regs[8]
8430 && ! fixed_regs[9]
8431 && ! fixed_regs[10]
8432 && ! fixed_regs[11]
8433 && ! fixed_regs[12])
8435 move_bytes = (bytes > 32) ? 32 : bytes;
8436 gen_func.movmemsi = gen_movmemsi_8reg;
8438 else if (TARGET_STRING
8439 && bytes > 16 /* move up to 24 bytes at a time */
8440 && ! fixed_regs[5]
8441 && ! fixed_regs[6]
8442 && ! fixed_regs[7]
8443 && ! fixed_regs[8]
8444 && ! fixed_regs[9]
8445 && ! fixed_regs[10])
8447 move_bytes = (bytes > 24) ? 24 : bytes;
8448 gen_func.movmemsi = gen_movmemsi_6reg;
8450 else if (TARGET_STRING
8451 && bytes > 8 /* move up to 16 bytes at a time */
8452 && ! fixed_regs[5]
8453 && ! fixed_regs[6]
8454 && ! fixed_regs[7]
8455 && ! fixed_regs[8])
8457 move_bytes = (bytes > 16) ? 16 : bytes;
8458 gen_func.movmemsi = gen_movmemsi_4reg;
8460 else if (bytes >= 8 && TARGET_POWERPC64
8461 /* 64-bit loads and stores require word-aligned
8462 displacements. */
8463 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
8465 move_bytes = 8;
8466 mode = DImode;
8467 gen_func.mov = gen_movdi;
8469 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
8470 { /* move up to 8 bytes at a time */
8471 move_bytes = (bytes > 8) ? 8 : bytes;
8472 gen_func.movmemsi = gen_movmemsi_2reg;
8474 else if (bytes >= 4 && !STRICT_ALIGNMENT)
8475 { /* move 4 bytes */
8476 move_bytes = 4;
8477 mode = SImode;
8478 gen_func.mov = gen_movsi;
8480 else if (bytes == 2 && !STRICT_ALIGNMENT)
8481 { /* move 2 bytes */
8482 move_bytes = 2;
8483 mode = HImode;
8484 gen_func.mov = gen_movhi;
8486 else if (TARGET_STRING && bytes > 1)
8487 { /* move up to 4 bytes at a time */
8488 move_bytes = (bytes > 4) ? 4 : bytes;
8489 gen_func.movmemsi = gen_movmemsi_1reg;
8491 else /* move 1 byte at a time */
8493 move_bytes = 1;
8494 mode = QImode;
8495 gen_func.mov = gen_movqi;
8498 src = adjust_address (orig_src, mode, offset);
8499 dest = adjust_address (orig_dest, mode, offset);
8501 if (mode != BLKmode)
8503 rtx tmp_reg = gen_reg_rtx (mode);
8505 emit_insn ((*gen_func.mov) (tmp_reg, src));
8506 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
8509 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
8511 int i;
8512 for (i = 0; i < num_reg; i++)
8513 emit_insn (stores[i]);
8514 num_reg = 0;
8517 if (mode == BLKmode)
8519 /* Move the address into scratch registers. The movmemsi
8520 patterns require zero offset. */
8521 if (!REG_P (XEXP (src, 0)))
8523 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
8524 src = replace_equiv_address (src, src_reg);
8526 set_mem_size (src, GEN_INT (move_bytes));
8528 if (!REG_P (XEXP (dest, 0)))
8530 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
8531 dest = replace_equiv_address (dest, dest_reg);
8533 set_mem_size (dest, GEN_INT (move_bytes));
8535 emit_insn ((*gen_func.movmemsi) (dest, src,
8536 GEN_INT (move_bytes & 31),
8537 align_rtx));
8541 return 1;
8545 /* Return 1 if OP is suitable for a save_world call in prologue. It is
8546 known to be a PARALLEL. */
8548 save_world_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8550 int index;
8551 int i;
8552 rtx elt;
8553 int count = XVECLEN (op, 0);
8555 if (count != 55)
8556 return 0;
8558 index = 0;
8559 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
8560 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
8561 return 0;
8563 for (i=1; i <= 18; i++)
8565 elt = XVECEXP (op, 0, index++);
8566 if (GET_CODE (elt) != SET
8567 || GET_CODE (SET_DEST (elt)) != MEM
8568 || ! memory_operand (SET_DEST (elt), DFmode)
8569 || GET_CODE (SET_SRC (elt)) != REG
8570 || GET_MODE (SET_SRC (elt)) != DFmode)
8571 return 0;
8574 for (i=1; i <= 12; i++)
8576 elt = XVECEXP (op, 0, index++);
8577 if (GET_CODE (elt) != SET
8578 || GET_CODE (SET_DEST (elt)) != MEM
8579 || GET_CODE (SET_SRC (elt)) != REG
8580 || GET_MODE (SET_SRC (elt)) != V4SImode)
8581 return 0;
8584 for (i=1; i <= 19; i++)
8586 elt = XVECEXP (op, 0, index++);
8587 if (GET_CODE (elt) != SET
8588 || GET_CODE (SET_DEST (elt)) != MEM
8589 || ! memory_operand (SET_DEST (elt), Pmode)
8590 || GET_CODE (SET_SRC (elt)) != REG
8591 || GET_MODE (SET_SRC (elt)) != Pmode)
8592 return 0;
8595 elt = XVECEXP (op, 0, index++);
8596 if (GET_CODE (elt) != SET
8597 || GET_CODE (SET_DEST (elt)) != MEM
8598 || ! memory_operand (SET_DEST (elt), Pmode)
8599 || GET_CODE (SET_SRC (elt)) != REG
8600 || REGNO (SET_SRC (elt)) != CR2_REGNO
8601 || GET_MODE (SET_SRC (elt)) != Pmode)
8602 return 0;
8604 if (GET_CODE (XVECEXP (op, 0, index++)) != USE
8605 || GET_CODE (XVECEXP (op, 0, index++)) != USE
8606 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
8607 return 0;
8608 return 1;
8611 /* Return 1 if OP is suitable for a save_world call in prologue. It is
8612 known to be a PARALLEL. */
8614 restore_world_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8616 int index;
8617 int i;
8618 rtx elt;
8619 int count = XVECLEN (op, 0);
8621 if (count != 59)
8622 return 0;
8624 index = 0;
8625 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
8626 || GET_CODE (XVECEXP (op, 0, index++)) != USE
8627 || GET_CODE (XVECEXP (op, 0, index++)) != USE
8628 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
8629 return 0;
8631 elt = XVECEXP (op, 0, index++);
8632 if (GET_CODE (elt) != SET
8633 || GET_CODE (SET_SRC (elt)) != MEM
8634 || ! memory_operand (SET_SRC (elt), Pmode)
8635 || GET_CODE (SET_DEST (elt)) != REG
8636 || REGNO (SET_DEST (elt)) != CR2_REGNO
8637 || GET_MODE (SET_DEST (elt)) != Pmode)
8638 return 0;
8640 for (i=1; i <= 19; i++)
8642 elt = XVECEXP (op, 0, index++);
8643 if (GET_CODE (elt) != SET
8644 || GET_CODE (SET_SRC (elt)) != MEM
8645 || ! memory_operand (SET_SRC (elt), Pmode)
8646 || GET_CODE (SET_DEST (elt)) != REG
8647 || GET_MODE (SET_DEST (elt)) != Pmode)
8648 return 0;
8651 for (i=1; i <= 12; i++)
8653 elt = XVECEXP (op, 0, index++);
8654 if (GET_CODE (elt) != SET
8655 || GET_CODE (SET_SRC (elt)) != MEM
8656 || GET_CODE (SET_DEST (elt)) != REG
8657 || GET_MODE (SET_DEST (elt)) != V4SImode)
8658 return 0;
8661 for (i=1; i <= 18; i++)
8663 elt = XVECEXP (op, 0, index++);
8664 if (GET_CODE (elt) != SET
8665 || GET_CODE (SET_SRC (elt)) != MEM
8666 || ! memory_operand (SET_SRC (elt), DFmode)
8667 || GET_CODE (SET_DEST (elt)) != REG
8668 || GET_MODE (SET_DEST (elt)) != DFmode)
8669 return 0;
8672 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
8673 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
8674 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
8675 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
8676 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
8677 return 0;
8678 return 1;
8682 /* Return 1 if OP is a load multiple operation. It is known to be a
8683 PARALLEL and the first section will be tested. */
8686 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8688 int count = XVECLEN (op, 0);
8689 unsigned int dest_regno;
8690 rtx src_addr;
8691 int i;
8693 /* Perform a quick check so we don't blow up below. */
8694 if (count <= 1
8695 || GET_CODE (XVECEXP (op, 0, 0)) != SET
8696 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
8697 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
8698 return 0;
8700 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
8701 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
8703 for (i = 1; i < count; i++)
8705 rtx elt = XVECEXP (op, 0, i);
8707 if (GET_CODE (elt) != SET
8708 || GET_CODE (SET_DEST (elt)) != REG
8709 || GET_MODE (SET_DEST (elt)) != SImode
8710 || REGNO (SET_DEST (elt)) != dest_regno + i
8711 || GET_CODE (SET_SRC (elt)) != MEM
8712 || GET_MODE (SET_SRC (elt)) != SImode
8713 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
8714 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
8715 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
8716 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
8717 return 0;
8720 return 1;
8723 /* Similar, but tests for store multiple. Here, the second vector element
8724 is a CLOBBER. It will be tested later. */
8727 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8729 int count = XVECLEN (op, 0) - 1;
8730 unsigned int src_regno;
8731 rtx dest_addr;
8732 int i;
8734 /* Perform a quick check so we don't blow up below. */
8735 if (count <= 1
8736 || GET_CODE (XVECEXP (op, 0, 0)) != SET
8737 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
8738 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
8739 return 0;
8741 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
8742 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
8744 for (i = 1; i < count; i++)
8746 rtx elt = XVECEXP (op, 0, i + 1);
8748 if (GET_CODE (elt) != SET
8749 || GET_CODE (SET_SRC (elt)) != REG
8750 || GET_MODE (SET_SRC (elt)) != SImode
8751 || REGNO (SET_SRC (elt)) != src_regno + i
8752 || GET_CODE (SET_DEST (elt)) != MEM
8753 || GET_MODE (SET_DEST (elt)) != SImode
8754 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
8755 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
8756 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
8757 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
8758 return 0;
8761 return 1;
8764 /* Return a string to perform a load_multiple operation.
8765 operands[0] is the vector.
8766 operands[1] is the source address.
8767 operands[2] is the first destination register. */
8769 const char *
8770 rs6000_output_load_multiple (rtx operands[3])
8772 /* We have to handle the case where the pseudo used to contain the address
8773 is assigned to one of the output registers. */
8774 int i, j;
8775 int words = XVECLEN (operands[0], 0);
8776 rtx xop[10];
8778 if (XVECLEN (operands[0], 0) == 1)
8779 return "{l|lwz} %2,0(%1)";
8781 for (i = 0; i < words; i++)
8782 if (refers_to_regno_p (REGNO (operands[2]) + i,
8783 REGNO (operands[2]) + i + 1, operands[1], 0))
8785 if (i == words-1)
8787 xop[0] = GEN_INT (4 * (words-1));
8788 xop[1] = operands[1];
8789 xop[2] = operands[2];
8790 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
8791 return "";
8793 else if (i == 0)
8795 xop[0] = GEN_INT (4 * (words-1));
8796 xop[1] = operands[1];
8797 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
8798 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
8799 return "";
8801 else
8803 for (j = 0; j < words; j++)
8804 if (j != i)
8806 xop[0] = GEN_INT (j * 4);
8807 xop[1] = operands[1];
8808 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
8809 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
8811 xop[0] = GEN_INT (i * 4);
8812 xop[1] = operands[1];
8813 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
8814 return "";
8818 return "{lsi|lswi} %2,%1,%N0";
8821 /* Return 1 for a parallel vrsave operation. */
8824 vrsave_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8826 int count = XVECLEN (op, 0);
8827 unsigned int dest_regno, src_regno;
8828 int i;
8830 if (count <= 1
8831 || GET_CODE (XVECEXP (op, 0, 0)) != SET
8832 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
8833 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE)
8834 return 0;
8836 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
8837 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
8839 if (dest_regno != VRSAVE_REGNO
8840 && src_regno != VRSAVE_REGNO)
8841 return 0;
8843 for (i = 1; i < count; i++)
8845 rtx elt = XVECEXP (op, 0, i);
8847 if (GET_CODE (elt) != CLOBBER
8848 && GET_CODE (elt) != SET)
8849 return 0;
8852 return 1;
8855 /* Return 1 for an PARALLEL suitable for mfcr. */
8858 mfcr_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8860 int count = XVECLEN (op, 0);
8861 int i;
8863 /* Perform a quick check so we don't blow up below. */
8864 if (count < 1
8865 || GET_CODE (XVECEXP (op, 0, 0)) != SET
8866 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
8867 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
8868 return 0;
8870 for (i = 0; i < count; i++)
8872 rtx exp = XVECEXP (op, 0, i);
8873 rtx unspec;
8874 int maskval;
8875 rtx src_reg;
8877 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
8879 if (GET_CODE (src_reg) != REG
8880 || GET_MODE (src_reg) != CCmode
8881 || ! CR_REGNO_P (REGNO (src_reg)))
8882 return 0;
8884 if (GET_CODE (exp) != SET
8885 || GET_CODE (SET_DEST (exp)) != REG
8886 || GET_MODE (SET_DEST (exp)) != SImode
8887 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
8888 return 0;
8889 unspec = SET_SRC (exp);
8890 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
8892 if (GET_CODE (unspec) != UNSPEC
8893 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
8894 || XVECLEN (unspec, 0) != 2
8895 || XVECEXP (unspec, 0, 0) != src_reg
8896 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
8897 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
8898 return 0;
8900 return 1;
8903 /* Return 1 for an PARALLEL suitable for mtcrf. */
8906 mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8908 int count = XVECLEN (op, 0);
8909 int i;
8910 rtx src_reg;
8912 /* Perform a quick check so we don't blow up below. */
8913 if (count < 1
8914 || GET_CODE (XVECEXP (op, 0, 0)) != SET
8915 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
8916 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
8917 return 0;
8918 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
8920 if (GET_CODE (src_reg) != REG
8921 || GET_MODE (src_reg) != SImode
8922 || ! INT_REGNO_P (REGNO (src_reg)))
8923 return 0;
8925 for (i = 0; i < count; i++)
8927 rtx exp = XVECEXP (op, 0, i);
8928 rtx unspec;
8929 int maskval;
8931 if (GET_CODE (exp) != SET
8932 || GET_CODE (SET_DEST (exp)) != REG
8933 || GET_MODE (SET_DEST (exp)) != CCmode
8934 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
8935 return 0;
8936 unspec = SET_SRC (exp);
8937 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
8939 if (GET_CODE (unspec) != UNSPEC
8940 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
8941 || XVECLEN (unspec, 0) != 2
8942 || XVECEXP (unspec, 0, 0) != src_reg
8943 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
8944 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
8945 return 0;
8947 return 1;
8950 /* Return 1 for an PARALLEL suitable for lmw. */
8953 lmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8955 int count = XVECLEN (op, 0);
8956 unsigned int dest_regno;
8957 rtx src_addr;
8958 unsigned int base_regno;
8959 HOST_WIDE_INT offset;
8960 int i;
8962 /* Perform a quick check so we don't blow up below. */
8963 if (count <= 1
8964 || GET_CODE (XVECEXP (op, 0, 0)) != SET
8965 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
8966 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
8967 return 0;
8969 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
8970 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
8972 if (dest_regno > 31
8973 || count != 32 - (int) dest_regno)
8974 return 0;
8976 if (legitimate_indirect_address_p (src_addr, 0))
8978 offset = 0;
8979 base_regno = REGNO (src_addr);
8980 if (base_regno == 0)
8981 return 0;
8983 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0))
8985 offset = INTVAL (XEXP (src_addr, 1));
8986 base_regno = REGNO (XEXP (src_addr, 0));
8988 else
8989 return 0;
8991 for (i = 0; i < count; i++)
8993 rtx elt = XVECEXP (op, 0, i);
8994 rtx newaddr;
8995 rtx addr_reg;
8996 HOST_WIDE_INT newoffset;
8998 if (GET_CODE (elt) != SET
8999 || GET_CODE (SET_DEST (elt)) != REG
9000 || GET_MODE (SET_DEST (elt)) != SImode
9001 || REGNO (SET_DEST (elt)) != dest_regno + i
9002 || GET_CODE (SET_SRC (elt)) != MEM
9003 || GET_MODE (SET_SRC (elt)) != SImode)
9004 return 0;
9005 newaddr = XEXP (SET_SRC (elt), 0);
9006 if (legitimate_indirect_address_p (newaddr, 0))
9008 newoffset = 0;
9009 addr_reg = newaddr;
9011 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
9013 addr_reg = XEXP (newaddr, 0);
9014 newoffset = INTVAL (XEXP (newaddr, 1));
9016 else
9017 return 0;
9018 if (REGNO (addr_reg) != base_regno
9019 || newoffset != offset + 4 * i)
9020 return 0;
9023 return 1;
9026 /* Return 1 for an PARALLEL suitable for stmw. */
9029 stmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9031 int count = XVECLEN (op, 0);
9032 unsigned int src_regno;
9033 rtx dest_addr;
9034 unsigned int base_regno;
9035 HOST_WIDE_INT offset;
9036 int i;
9038 /* Perform a quick check so we don't blow up below. */
9039 if (count <= 1
9040 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9041 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
9042 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
9043 return 0;
9045 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
9046 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
9048 if (src_regno > 31
9049 || count != 32 - (int) src_regno)
9050 return 0;
9052 if (legitimate_indirect_address_p (dest_addr, 0))
9054 offset = 0;
9055 base_regno = REGNO (dest_addr);
9056 if (base_regno == 0)
9057 return 0;
9059 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0))
9061 offset = INTVAL (XEXP (dest_addr, 1));
9062 base_regno = REGNO (XEXP (dest_addr, 0));
9064 else
9065 return 0;
9067 for (i = 0; i < count; i++)
9069 rtx elt = XVECEXP (op, 0, i);
9070 rtx newaddr;
9071 rtx addr_reg;
9072 HOST_WIDE_INT newoffset;
9074 if (GET_CODE (elt) != SET
9075 || GET_CODE (SET_SRC (elt)) != REG
9076 || GET_MODE (SET_SRC (elt)) != SImode
9077 || REGNO (SET_SRC (elt)) != src_regno + i
9078 || GET_CODE (SET_DEST (elt)) != MEM
9079 || GET_MODE (SET_DEST (elt)) != SImode)
9080 return 0;
9081 newaddr = XEXP (SET_DEST (elt), 0);
9082 if (legitimate_indirect_address_p (newaddr, 0))
9084 newoffset = 0;
9085 addr_reg = newaddr;
9087 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
9089 addr_reg = XEXP (newaddr, 0);
9090 newoffset = INTVAL (XEXP (newaddr, 1));
9092 else
9093 return 0;
9094 if (REGNO (addr_reg) != base_regno
9095 || newoffset != offset + 4 * i)
9096 return 0;
9099 return 1;
9102 /* A validation routine: say whether CODE, a condition code, and MODE
9103 match. The other alternatives either don't make sense or should
9104 never be generated. */
9106 static void
9107 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9109 if ((GET_RTX_CLASS (code) != RTX_COMPARE
9110 && GET_RTX_CLASS (code) != RTX_COMM_COMPARE)
9111 || GET_MODE_CLASS (mode) != MODE_CC)
9112 abort ();
9114 /* These don't make sense. */
9115 if ((code == GT || code == LT || code == GE || code == LE)
9116 && mode == CCUNSmode)
9117 abort ();
9119 if ((code == GTU || code == LTU || code == GEU || code == LEU)
9120 && mode != CCUNSmode)
9121 abort ();
9123 if (mode != CCFPmode
9124 && (code == ORDERED || code == UNORDERED
9125 || code == UNEQ || code == LTGT
9126 || code == UNGT || code == UNLT
9127 || code == UNGE || code == UNLE))
9128 abort ();
9130 /* These should never be generated except for
9131 flag_finite_math_only. */
9132 if (mode == CCFPmode
9133 && ! flag_finite_math_only
9134 && (code == LE || code == GE
9135 || code == UNEQ || code == LTGT
9136 || code == UNGT || code == UNLT))
9137 abort ();
9139 /* These are invalid; the information is not there. */
9140 if (mode == CCEQmode
9141 && code != EQ && code != NE)
9142 abort ();
9145 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
9146 We only check the opcode against the mode of the CC value here. */
9149 branch_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9151 enum rtx_code code = GET_CODE (op);
9152 enum machine_mode cc_mode;
9154 if (!COMPARISON_P (op))
9155 return 0;
9157 cc_mode = GET_MODE (XEXP (op, 0));
9158 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
9159 return 0;
9161 validate_condition_mode (code, cc_mode);
9163 return 1;
9166 /* Return 1 if OP is a comparison operation that is valid for a branch
9167 insn and which is true if the corresponding bit in the CC register
9168 is set. */
9171 branch_positive_comparison_operator (rtx op, enum machine_mode mode)
9173 enum rtx_code code;
9175 if (! branch_comparison_operator (op, mode))
9176 return 0;
9178 code = GET_CODE (op);
9179 return (code == EQ || code == LT || code == GT
9180 || code == LTU || code == GTU
9181 || code == UNORDERED);
9184 /* Return 1 if OP is a comparison operation that is valid for an scc
9185 insn: it must be a positive comparison. */
9188 scc_comparison_operator (rtx op, enum machine_mode mode)
9190 return branch_positive_comparison_operator (op, mode);
9194 trap_comparison_operator (rtx op, enum machine_mode mode)
9196 if (mode != VOIDmode && mode != GET_MODE (op))
9197 return 0;
9198 return COMPARISON_P (op);
9202 boolean_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9204 enum rtx_code code = GET_CODE (op);
9205 return (code == AND || code == IOR || code == XOR);
9209 boolean_or_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9211 enum rtx_code code = GET_CODE (op);
9212 return (code == IOR || code == XOR);
9216 min_max_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9218 enum rtx_code code = GET_CODE (op);
9219 return (code == SMIN || code == SMAX || code == UMIN || code == UMAX);
9222 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9223 mask required to convert the result of a rotate insn into a shift
9224 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9227 includes_lshift_p (rtx shiftop, rtx andop)
9229 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9231 shift_mask <<= INTVAL (shiftop);
9233 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9236 /* Similar, but for right shift. */
9239 includes_rshift_p (rtx shiftop, rtx andop)
9241 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9243 shift_mask >>= INTVAL (shiftop);
9245 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9248 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9249 to perform a left shift. It must have exactly SHIFTOP least
9250 significant 0's, then one or more 1's, then zero or more 0's. */
9253 includes_rldic_lshift_p (rtx shiftop, rtx andop)
9255 if (GET_CODE (andop) == CONST_INT)
9257 HOST_WIDE_INT c, lsb, shift_mask;
9259 c = INTVAL (andop);
9260 if (c == 0 || c == ~0)
9261 return 0;
9263 shift_mask = ~0;
9264 shift_mask <<= INTVAL (shiftop);
9266 /* Find the least significant one bit. */
9267 lsb = c & -c;
9269 /* It must coincide with the LSB of the shift mask. */
9270 if (-lsb != shift_mask)
9271 return 0;
9273 /* Invert to look for the next transition (if any). */
9274 c = ~c;
9276 /* Remove the low group of ones (originally low group of zeros). */
9277 c &= -lsb;
9279 /* Again find the lsb, and check we have all 1's above. */
9280 lsb = c & -c;
9281 return c == -lsb;
9283 else if (GET_CODE (andop) == CONST_DOUBLE
9284 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9286 HOST_WIDE_INT low, high, lsb;
9287 HOST_WIDE_INT shift_mask_low, shift_mask_high;
9289 low = CONST_DOUBLE_LOW (andop);
9290 if (HOST_BITS_PER_WIDE_INT < 64)
9291 high = CONST_DOUBLE_HIGH (andop);
9293 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
9294 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
9295 return 0;
9297 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9299 shift_mask_high = ~0;
9300 if (INTVAL (shiftop) > 32)
9301 shift_mask_high <<= INTVAL (shiftop) - 32;
9303 lsb = high & -high;
9305 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
9306 return 0;
9308 high = ~high;
9309 high &= -lsb;
9311 lsb = high & -high;
9312 return high == -lsb;
9315 shift_mask_low = ~0;
9316 shift_mask_low <<= INTVAL (shiftop);
9318 lsb = low & -low;
9320 if (-lsb != shift_mask_low)
9321 return 0;
9323 if (HOST_BITS_PER_WIDE_INT < 64)
9324 high = ~high;
9325 low = ~low;
9326 low &= -lsb;
9328 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9330 lsb = high & -high;
9331 return high == -lsb;
9334 lsb = low & -low;
9335 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9337 else
9338 return 0;
9341 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9342 to perform a left shift. It must have SHIFTOP or more least
9343 significant 0's, with the remainder of the word 1's. */
9346 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
9348 if (GET_CODE (andop) == CONST_INT)
9350 HOST_WIDE_INT c, lsb, shift_mask;
9352 shift_mask = ~0;
9353 shift_mask <<= INTVAL (shiftop);
9354 c = INTVAL (andop);
9356 /* Find the least significant one bit. */
9357 lsb = c & -c;
9359 /* It must be covered by the shift mask.
9360 This test also rejects c == 0. */
9361 if ((lsb & shift_mask) == 0)
9362 return 0;
9364 /* Check we have all 1's above the transition, and reject all 1's. */
9365 return c == -lsb && lsb != 1;
9367 else if (GET_CODE (andop) == CONST_DOUBLE
9368 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9370 HOST_WIDE_INT low, lsb, shift_mask_low;
9372 low = CONST_DOUBLE_LOW (andop);
9374 if (HOST_BITS_PER_WIDE_INT < 64)
9376 HOST_WIDE_INT high, shift_mask_high;
9378 high = CONST_DOUBLE_HIGH (andop);
9380 if (low == 0)
9382 shift_mask_high = ~0;
9383 if (INTVAL (shiftop) > 32)
9384 shift_mask_high <<= INTVAL (shiftop) - 32;
9386 lsb = high & -high;
9388 if ((lsb & shift_mask_high) == 0)
9389 return 0;
9391 return high == -lsb;
9393 if (high != ~0)
9394 return 0;
9397 shift_mask_low = ~0;
9398 shift_mask_low <<= INTVAL (shiftop);
9400 lsb = low & -low;
9402 if ((lsb & shift_mask_low) == 0)
9403 return 0;
9405 return low == -lsb && lsb != 1;
9407 else
9408 return 0;
9411 /* Return 1 if operands will generate a valid arguments to rlwimi
9412 instruction for insert with right shift in 64-bit mode. The mask may
9413 not start on the first bit or stop on the last bit because wrap-around
9414 effects of instruction do not correspond to semantics of RTL insn. */
9417 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
9419 if (INTVAL (startop) < 64
9420 && INTVAL (startop) > 32
9421 && (INTVAL (sizeop) + INTVAL (startop) < 64)
9422 && (INTVAL (sizeop) + INTVAL (startop) > 33)
9423 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
9424 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
9425 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
9426 return 1;
9428 return 0;
9431 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
9432 for lfq and stfq insns iff the registers are hard registers. */
9435 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
9437 /* We might have been passed a SUBREG. */
9438 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
9439 return 0;
9441 /* We might have been passed non floating point registers. */
9442 if (!FP_REGNO_P (REGNO (reg1))
9443 || !FP_REGNO_P (REGNO (reg2)))
9444 return 0;
9446 return (REGNO (reg1) == REGNO (reg2) - 1);
9449 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
9450 addr1 and addr2 must be in consecutive memory locations
9451 (addr2 == addr1 + 8). */
9454 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
9456 rtx addr1, addr2;
9457 unsigned int reg1;
9458 int offset1;
9460 /* The mems cannot be volatile. */
9461 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
9462 return 0;
9464 addr1 = XEXP (mem1, 0);
9465 addr2 = XEXP (mem2, 0);
9467 /* Extract an offset (if used) from the first addr. */
9468 if (GET_CODE (addr1) == PLUS)
9470 /* If not a REG, return zero. */
9471 if (GET_CODE (XEXP (addr1, 0)) != REG)
9472 return 0;
9473 else
9475 reg1 = REGNO (XEXP (addr1, 0));
9476 /* The offset must be constant! */
9477 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
9478 return 0;
9479 offset1 = INTVAL (XEXP (addr1, 1));
9482 else if (GET_CODE (addr1) != REG)
9483 return 0;
9484 else
9486 reg1 = REGNO (addr1);
9487 /* This was a simple (mem (reg)) expression. Offset is 0. */
9488 offset1 = 0;
9491 /* Make sure the second address is a (mem (plus (reg) (const_int)))
9492 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
9493 register as addr1. */
9494 if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
9495 return 1;
9496 if (GET_CODE (addr2) != PLUS)
9497 return 0;
9499 if (GET_CODE (XEXP (addr2, 0)) != REG
9500 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
9501 return 0;
9503 if (reg1 != REGNO (XEXP (addr2, 0)))
9504 return 0;
9506 /* The offset for the second addr must be 8 more than the first addr. */
9507 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
9508 return 0;
9510 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
9511 instructions. */
9512 return 1;
9515 /* Return the register class of a scratch register needed to copy IN into
9516 or out of a register in CLASS in MODE. If it can be done directly,
9517 NO_REGS is returned. */
9519 enum reg_class
9520 secondary_reload_class (enum reg_class class,
9521 enum machine_mode mode ATTRIBUTE_UNUSED,
9522 rtx in)
9524 int regno;
9526 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
9527 #if TARGET_MACHO
9528 && MACHOPIC_INDIRECT
9529 #endif
9532 /* We cannot copy a symbolic operand directly into anything
9533 other than BASE_REGS for TARGET_ELF. So indicate that a
9534 register from BASE_REGS is needed as an intermediate
9535 register.
9537 On Darwin, pic addresses require a load from memory, which
9538 needs a base register. */
9539 if (class != BASE_REGS
9540 && (GET_CODE (in) == SYMBOL_REF
9541 || GET_CODE (in) == HIGH
9542 || GET_CODE (in) == LABEL_REF
9543 || GET_CODE (in) == CONST))
9544 return BASE_REGS;
9547 if (GET_CODE (in) == REG)
9549 regno = REGNO (in);
9550 if (regno >= FIRST_PSEUDO_REGISTER)
9552 regno = true_regnum (in);
9553 if (regno >= FIRST_PSEUDO_REGISTER)
9554 regno = -1;
9557 else if (GET_CODE (in) == SUBREG)
9559 regno = true_regnum (in);
9560 if (regno >= FIRST_PSEUDO_REGISTER)
9561 regno = -1;
9563 else
9564 regno = -1;
9566 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
9567 into anything. */
9568 if (class == GENERAL_REGS || class == BASE_REGS
9569 || (regno >= 0 && INT_REGNO_P (regno)))
9570 return NO_REGS;
9572 /* Constants, memory, and FP registers can go into FP registers. */
9573 if ((regno == -1 || FP_REGNO_P (regno))
9574 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
9575 return NO_REGS;
9577 /* Memory, and AltiVec registers can go into AltiVec registers. */
9578 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
9579 && class == ALTIVEC_REGS)
9580 return NO_REGS;
9582 /* We can copy among the CR registers. */
9583 if ((class == CR_REGS || class == CR0_REGS)
9584 && regno >= 0 && CR_REGNO_P (regno))
9585 return NO_REGS;
9587 /* Otherwise, we need GENERAL_REGS. */
9588 return GENERAL_REGS;
9591 /* Given a comparison operation, return the bit number in CCR to test. We
9592 know this is a valid comparison.
9594 SCC_P is 1 if this is for an scc. That means that %D will have been
9595 used instead of %C, so the bits will be in different places.
9597 Return -1 if OP isn't a valid comparison for some reason. */
9600 ccr_bit (rtx op, int scc_p)
9602 enum rtx_code code = GET_CODE (op);
9603 enum machine_mode cc_mode;
9604 int cc_regnum;
9605 int base_bit;
9606 rtx reg;
9608 if (!COMPARISON_P (op))
9609 return -1;
9611 reg = XEXP (op, 0);
9613 if (GET_CODE (reg) != REG
9614 || ! CR_REGNO_P (REGNO (reg)))
9615 abort ();
9617 cc_mode = GET_MODE (reg);
9618 cc_regnum = REGNO (reg);
9619 base_bit = 4 * (cc_regnum - CR0_REGNO);
9621 validate_condition_mode (code, cc_mode);
9623 /* When generating a sCOND operation, only positive conditions are
9624 allowed. */
9625 if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED
9626 && code != GTU && code != LTU)
9627 abort ();
9629 switch (code)
9631 case NE:
9632 return scc_p ? base_bit + 3 : base_bit + 2;
9633 case EQ:
9634 return base_bit + 2;
9635 case GT: case GTU: case UNLE:
9636 return base_bit + 1;
9637 case LT: case LTU: case UNGE:
9638 return base_bit;
9639 case ORDERED: case UNORDERED:
9640 return base_bit + 3;
9642 case GE: case GEU:
9643 /* If scc, we will have done a cror to put the bit in the
9644 unordered position. So test that bit. For integer, this is ! LT
9645 unless this is an scc insn. */
9646 return scc_p ? base_bit + 3 : base_bit;
9648 case LE: case LEU:
9649 return scc_p ? base_bit + 3 : base_bit + 1;
9651 default:
9652 abort ();
9656 /* Return the GOT register. */
9658 struct rtx_def *
9659 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
9661 /* The second flow pass currently (June 1999) can't update
9662 regs_ever_live without disturbing other parts of the compiler, so
9663 update it here to make the prolog/epilogue code happy. */
9664 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
9665 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9667 current_function_uses_pic_offset_table = 1;
9669 return pic_offset_table_rtx;
9672 /* Function to init struct machine_function.
9673 This will be called, via a pointer variable,
9674 from push_function_context. */
9676 static struct machine_function *
9677 rs6000_init_machine_status (void)
9679 return ggc_alloc_cleared (sizeof (machine_function));
9682 /* These macros test for integers and extract the low-order bits. */
9683 #define INT_P(X) \
9684 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
9685 && GET_MODE (X) == VOIDmode)
9687 #define INT_LOWPART(X) \
9688 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
9691 extract_MB (rtx op)
9693 int i;
9694 unsigned long val = INT_LOWPART (op);
9696 /* If the high bit is zero, the value is the first 1 bit we find
9697 from the left. */
9698 if ((val & 0x80000000) == 0)
9700 if ((val & 0xffffffff) == 0)
9701 abort ();
9703 i = 1;
9704 while (((val <<= 1) & 0x80000000) == 0)
9705 ++i;
9706 return i;
9709 /* If the high bit is set and the low bit is not, or the mask is all
9710 1's, the value is zero. */
9711 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
9712 return 0;
9714 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9715 from the right. */
9716 i = 31;
9717 while (((val >>= 1) & 1) != 0)
9718 --i;
9720 return i;
9724 extract_ME (rtx op)
9726 int i;
9727 unsigned long val = INT_LOWPART (op);
9729 /* If the low bit is zero, the value is the first 1 bit we find from
9730 the right. */
9731 if ((val & 1) == 0)
9733 if ((val & 0xffffffff) == 0)
9734 abort ();
9736 i = 30;
9737 while (((val >>= 1) & 1) == 0)
9738 --i;
9740 return i;
9743 /* If the low bit is set and the high bit is not, or the mask is all
9744 1's, the value is 31. */
9745 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
9746 return 31;
9748 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9749 from the left. */
9750 i = 0;
9751 while (((val <<= 1) & 0x80000000) != 0)
9752 ++i;
9754 return i;
9757 /* Locate some local-dynamic symbol still in use by this function
9758 so that we can print its name in some tls_ld pattern. */
9760 static const char *
9761 rs6000_get_some_local_dynamic_name (void)
9763 rtx insn;
9765 if (cfun->machine->some_ld_name)
9766 return cfun->machine->some_ld_name;
9768 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9769 if (INSN_P (insn)
9770 && for_each_rtx (&PATTERN (insn),
9771 rs6000_get_some_local_dynamic_name_1, 0))
9772 return cfun->machine->some_ld_name;
9774 abort ();
9777 /* Helper function for rs6000_get_some_local_dynamic_name. */
9779 static int
9780 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
9782 rtx x = *px;
9784 if (GET_CODE (x) == SYMBOL_REF)
9786 const char *str = XSTR (x, 0);
9787 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9789 cfun->machine->some_ld_name = str;
9790 return 1;
9794 return 0;
9797 /* Write out a function code label. */
9799 void
9800 rs6000_output_function_entry (FILE *file, const char *fname)
9802 if (fname[0] != '.')
9804 switch (DEFAULT_ABI)
9806 default:
9807 abort ();
9809 case ABI_AIX:
9810 if (DOT_SYMBOLS)
9811 putc ('.', file);
9812 else
9813 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
9814 break;
9816 case ABI_V4:
9817 case ABI_DARWIN:
9818 break;
9821 if (TARGET_AIX)
9822 RS6000_OUTPUT_BASENAME (file, fname);
9823 else
9824 assemble_name (file, fname);
9827 /* Print an operand. Recognize special options, documented below. */
9829 #if TARGET_ELF
9830 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
9831 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
9832 #else
9833 #define SMALL_DATA_RELOC "sda21"
9834 #define SMALL_DATA_REG 0
9835 #endif
9837 void
9838 print_operand (FILE *file, rtx x, int code)
9840 int i;
9841 HOST_WIDE_INT val;
9842 unsigned HOST_WIDE_INT uval;
9844 switch (code)
9846 case '.':
9847 /* Write out an instruction after the call which may be replaced
9848 with glue code by the loader. This depends on the AIX version. */
9849 asm_fprintf (file, RS6000_CALL_GLUE);
9850 return;
9852 /* %a is output_address. */
9854 case 'A':
9855 /* If X is a constant integer whose low-order 5 bits are zero,
9856 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
9857 in the AIX assembler where "sri" with a zero shift count
9858 writes a trash instruction. */
9859 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
9860 putc ('l', file);
9861 else
9862 putc ('r', file);
9863 return;
9865 case 'b':
9866 /* If constant, low-order 16 bits of constant, unsigned.
9867 Otherwise, write normally. */
9868 if (INT_P (x))
9869 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
9870 else
9871 print_operand (file, x, 0);
9872 return;
9874 case 'B':
9875 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
9876 for 64-bit mask direction. */
9877 putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file);
9878 return;
9880 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
9881 output_operand. */
9883 case 'c':
9884 /* X is a CR register. Print the number of the GT bit of the CR. */
9885 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9886 output_operand_lossage ("invalid %%E value");
9887 else
9888 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
9889 return;
9891 case 'D':
9892 /* Like 'J' but get to the EQ bit. */
9893 if (GET_CODE (x) != REG)
9894 abort ();
9896 /* Bit 1 is EQ bit. */
9897 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
9899 /* If we want bit 31, write a shift count of zero, not 32. */
9900 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9901 return;
9903 case 'E':
9904 /* X is a CR register. Print the number of the EQ bit of the CR */
9905 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9906 output_operand_lossage ("invalid %%E value");
9907 else
9908 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
9909 return;
9911 case 'f':
9912 /* X is a CR register. Print the shift count needed to move it
9913 to the high-order four bits. */
9914 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9915 output_operand_lossage ("invalid %%f value");
9916 else
9917 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
9918 return;
9920 case 'F':
9921 /* Similar, but print the count for the rotate in the opposite
9922 direction. */
9923 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9924 output_operand_lossage ("invalid %%F value");
9925 else
9926 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
9927 return;
9929 case 'G':
9930 /* X is a constant integer. If it is negative, print "m",
9931 otherwise print "z". This is to make an aze or ame insn. */
9932 if (GET_CODE (x) != CONST_INT)
9933 output_operand_lossage ("invalid %%G value");
9934 else if (INTVAL (x) >= 0)
9935 putc ('z', file);
9936 else
9937 putc ('m', file);
9938 return;
9940 case 'h':
9941 /* If constant, output low-order five bits. Otherwise, write
9942 normally. */
9943 if (INT_P (x))
9944 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
9945 else
9946 print_operand (file, x, 0);
9947 return;
9949 case 'H':
9950 /* If constant, output low-order six bits. Otherwise, write
9951 normally. */
9952 if (INT_P (x))
9953 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
9954 else
9955 print_operand (file, x, 0);
9956 return;
9958 case 'I':
9959 /* Print `i' if this is a constant, else nothing. */
9960 if (INT_P (x))
9961 putc ('i', file);
9962 return;
9964 case 'j':
9965 /* Write the bit number in CCR for jump. */
9966 i = ccr_bit (x, 0);
9967 if (i == -1)
9968 output_operand_lossage ("invalid %%j code");
9969 else
9970 fprintf (file, "%d", i);
9971 return;
9973 case 'J':
9974 /* Similar, but add one for shift count in rlinm for scc and pass
9975 scc flag to `ccr_bit'. */
9976 i = ccr_bit (x, 1);
9977 if (i == -1)
9978 output_operand_lossage ("invalid %%J code");
9979 else
9980 /* If we want bit 31, write a shift count of zero, not 32. */
9981 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9982 return;
9984 case 'k':
9985 /* X must be a constant. Write the 1's complement of the
9986 constant. */
9987 if (! INT_P (x))
9988 output_operand_lossage ("invalid %%k value");
9989 else
9990 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
9991 return;
9993 case 'K':
9994 /* X must be a symbolic constant on ELF. Write an
9995 expression suitable for an 'addi' that adds in the low 16
9996 bits of the MEM. */
9997 if (GET_CODE (x) != CONST)
9999 print_operand_address (file, x);
10000 fputs ("@l", file);
10002 else
10004 if (GET_CODE (XEXP (x, 0)) != PLUS
10005 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10006 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10007 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10008 output_operand_lossage ("invalid %%K value");
10009 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10010 fputs ("@l", file);
10011 /* For GNU as, there must be a non-alphanumeric character
10012 between 'l' and the number. The '-' is added by
10013 print_operand() already. */
10014 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10015 fputs ("+", file);
10016 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10018 return;
10020 /* %l is output_asm_label. */
10022 case 'L':
10023 /* Write second word of DImode or DFmode reference. Works on register
10024 or non-indexed memory only. */
10025 if (GET_CODE (x) == REG)
10026 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
10027 else if (GET_CODE (x) == MEM)
10029 /* Handle possible auto-increment. Since it is pre-increment and
10030 we have already done it, we can just use an offset of word. */
10031 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10032 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10033 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10034 UNITS_PER_WORD));
10035 else
10036 output_address (XEXP (adjust_address_nv (x, SImode,
10037 UNITS_PER_WORD),
10038 0));
10040 if (small_data_operand (x, GET_MODE (x)))
10041 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10042 reg_names[SMALL_DATA_REG]);
10044 return;
10046 case 'm':
10047 /* MB value for a mask operand. */
10048 if (! mask_operand (x, SImode))
10049 output_operand_lossage ("invalid %%m value");
10051 fprintf (file, "%d", extract_MB (x));
10052 return;
10054 case 'M':
10055 /* ME value for a mask operand. */
10056 if (! mask_operand (x, SImode))
10057 output_operand_lossage ("invalid %%M value");
10059 fprintf (file, "%d", extract_ME (x));
10060 return;
10062 /* %n outputs the negative of its operand. */
10064 case 'N':
10065 /* Write the number of elements in the vector times 4. */
10066 if (GET_CODE (x) != PARALLEL)
10067 output_operand_lossage ("invalid %%N value");
10068 else
10069 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10070 return;
10072 case 'O':
10073 /* Similar, but subtract 1 first. */
10074 if (GET_CODE (x) != PARALLEL)
10075 output_operand_lossage ("invalid %%O value");
10076 else
10077 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10078 return;
10080 case 'p':
10081 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10082 if (! INT_P (x)
10083 || INT_LOWPART (x) < 0
10084 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10085 output_operand_lossage ("invalid %%p value");
10086 else
10087 fprintf (file, "%d", i);
10088 return;
10090 case 'P':
10091 /* The operand must be an indirect memory reference. The result
10092 is the register name. */
10093 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10094 || REGNO (XEXP (x, 0)) >= 32)
10095 output_operand_lossage ("invalid %%P value");
10096 else
10097 fprintf (file, "%s", reg_names[REGNO (XEXP (x, 0))]);
10098 return;
10100 case 'q':
10101 /* This outputs the logical code corresponding to a boolean
10102 expression. The expression may have one or both operands
10103 negated (if one, only the first one). For condition register
10104 logical operations, it will also treat the negated
10105 CR codes as NOTs, but not handle NOTs of them. */
10107 const char *const *t = 0;
10108 const char *s;
10109 enum rtx_code code = GET_CODE (x);
10110 static const char * const tbl[3][3] = {
10111 { "and", "andc", "nor" },
10112 { "or", "orc", "nand" },
10113 { "xor", "eqv", "xor" } };
10115 if (code == AND)
10116 t = tbl[0];
10117 else if (code == IOR)
10118 t = tbl[1];
10119 else if (code == XOR)
10120 t = tbl[2];
10121 else
10122 output_operand_lossage ("invalid %%q value");
10124 if (GET_CODE (XEXP (x, 0)) != NOT)
10125 s = t[0];
10126 else
10128 if (GET_CODE (XEXP (x, 1)) == NOT)
10129 s = t[2];
10130 else
10131 s = t[1];
10134 fputs (s, file);
10136 return;
10138 case 'Q':
10139 if (TARGET_MFCRF)
10140 fputc (',', file);
10141 /* FALLTHRU */
10142 else
10143 return;
10145 case 'R':
10146 /* X is a CR register. Print the mask for `mtcrf'. */
10147 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10148 output_operand_lossage ("invalid %%R value");
10149 else
10150 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10151 return;
10153 case 's':
10154 /* Low 5 bits of 32 - value */
10155 if (! INT_P (x))
10156 output_operand_lossage ("invalid %%s value");
10157 else
10158 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10159 return;
10161 case 'S':
10162 /* PowerPC64 mask position. All 0's is excluded.
10163 CONST_INT 32-bit mask is considered sign-extended so any
10164 transition must occur within the CONST_INT, not on the boundary. */
10165 if (! mask64_operand (x, DImode))
10166 output_operand_lossage ("invalid %%S value");
10168 uval = INT_LOWPART (x);
10170 if (uval & 1) /* Clear Left */
10172 #if HOST_BITS_PER_WIDE_INT > 64
10173 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10174 #endif
10175 i = 64;
10177 else /* Clear Right */
10179 uval = ~uval;
10180 #if HOST_BITS_PER_WIDE_INT > 64
10181 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10182 #endif
10183 i = 63;
10185 while (uval != 0)
10186 --i, uval >>= 1;
10187 if (i < 0)
10188 abort ();
10189 fprintf (file, "%d", i);
10190 return;
10192 case 't':
10193 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10194 if (GET_CODE (x) != REG || GET_MODE (x) != CCmode)
10195 abort ();
10197 /* Bit 3 is OV bit. */
10198 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10200 /* If we want bit 31, write a shift count of zero, not 32. */
10201 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10202 return;
10204 case 'T':
10205 /* Print the symbolic name of a branch target register. */
10206 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
10207 && REGNO (x) != COUNT_REGISTER_REGNUM))
10208 output_operand_lossage ("invalid %%T value");
10209 else if (REGNO (x) == LINK_REGISTER_REGNUM)
10210 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
10211 else
10212 fputs ("ctr", file);
10213 return;
10215 case 'u':
10216 /* High-order 16 bits of constant for use in unsigned operand. */
10217 if (! INT_P (x))
10218 output_operand_lossage ("invalid %%u value");
10219 else
10220 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10221 (INT_LOWPART (x) >> 16) & 0xffff);
10222 return;
10224 case 'v':
10225 /* High-order 16 bits of constant for use in signed operand. */
10226 if (! INT_P (x))
10227 output_operand_lossage ("invalid %%v value");
10228 else
10229 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10230 (INT_LOWPART (x) >> 16) & 0xffff);
10231 return;
10233 case 'U':
10234 /* Print `u' if this has an auto-increment or auto-decrement. */
10235 if (GET_CODE (x) == MEM
10236 && (GET_CODE (XEXP (x, 0)) == PRE_INC
10237 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
10238 putc ('u', file);
10239 return;
10241 case 'V':
10242 /* Print the trap code for this operand. */
10243 switch (GET_CODE (x))
10245 case EQ:
10246 fputs ("eq", file); /* 4 */
10247 break;
10248 case NE:
10249 fputs ("ne", file); /* 24 */
10250 break;
10251 case LT:
10252 fputs ("lt", file); /* 16 */
10253 break;
10254 case LE:
10255 fputs ("le", file); /* 20 */
10256 break;
10257 case GT:
10258 fputs ("gt", file); /* 8 */
10259 break;
10260 case GE:
10261 fputs ("ge", file); /* 12 */
10262 break;
10263 case LTU:
10264 fputs ("llt", file); /* 2 */
10265 break;
10266 case LEU:
10267 fputs ("lle", file); /* 6 */
10268 break;
10269 case GTU:
10270 fputs ("lgt", file); /* 1 */
10271 break;
10272 case GEU:
10273 fputs ("lge", file); /* 5 */
10274 break;
10275 default:
10276 abort ();
10278 break;
10280 case 'w':
10281 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10282 normally. */
10283 if (INT_P (x))
10284 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
10285 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
10286 else
10287 print_operand (file, x, 0);
10288 return;
10290 case 'W':
10291 /* MB value for a PowerPC64 rldic operand. */
10292 val = (GET_CODE (x) == CONST_INT
10293 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
10295 if (val < 0)
10296 i = -1;
10297 else
10298 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
10299 if ((val <<= 1) < 0)
10300 break;
10302 #if HOST_BITS_PER_WIDE_INT == 32
10303 if (GET_CODE (x) == CONST_INT && i >= 0)
10304 i += 32; /* zero-extend high-part was all 0's */
10305 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
10307 val = CONST_DOUBLE_LOW (x);
10309 if (val == 0)
10310 abort ();
10311 else if (val < 0)
10312 --i;
10313 else
10314 for ( ; i < 64; i++)
10315 if ((val <<= 1) < 0)
10316 break;
10318 #endif
10320 fprintf (file, "%d", i + 1);
10321 return;
10323 case 'X':
10324 if (GET_CODE (x) == MEM
10325 && legitimate_indexed_address_p (XEXP (x, 0), 0))
10326 putc ('x', file);
10327 return;
10329 case 'Y':
10330 /* Like 'L', for third word of TImode */
10331 if (GET_CODE (x) == REG)
10332 fprintf (file, "%s", reg_names[REGNO (x) + 2]);
10333 else if (GET_CODE (x) == MEM)
10335 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10336 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10337 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
10338 else
10339 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
10340 if (small_data_operand (x, GET_MODE (x)))
10341 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10342 reg_names[SMALL_DATA_REG]);
10344 return;
10346 case 'z':
10347 /* X is a SYMBOL_REF. Write out the name preceded by a
10348 period and without any trailing data in brackets. Used for function
10349 names. If we are configured for System V (or the embedded ABI) on
10350 the PowerPC, do not emit the period, since those systems do not use
10351 TOCs and the like. */
10352 if (GET_CODE (x) != SYMBOL_REF)
10353 abort ();
10355 /* Mark the decl as referenced so that cgraph will output the function. */
10356 if (SYMBOL_REF_DECL (x))
10357 mark_decl_referenced (SYMBOL_REF_DECL (x));
10359 /* For macho, check to see if we need a stub. */
10360 if (TARGET_MACHO)
10362 const char *name = XSTR (x, 0);
10363 #if TARGET_MACHO
10364 if (MACHOPIC_INDIRECT
10365 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10366 name = machopic_indirection_name (x, /*stub_p=*/true);
10367 #endif
10368 assemble_name (file, name);
10370 else if (!DOT_SYMBOLS)
10371 assemble_name (file, XSTR (x, 0));
10372 else
10373 rs6000_output_function_entry (file, XSTR (x, 0));
10374 return;
10376 case 'Z':
10377 /* Like 'L', for last word of TImode. */
10378 if (GET_CODE (x) == REG)
10379 fprintf (file, "%s", reg_names[REGNO (x) + 3]);
10380 else if (GET_CODE (x) == MEM)
10382 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10383 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10384 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
10385 else
10386 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
10387 if (small_data_operand (x, GET_MODE (x)))
10388 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10389 reg_names[SMALL_DATA_REG]);
10391 return;
10393 /* Print AltiVec or SPE memory operand. */
10394 case 'y':
10396 rtx tmp;
10398 if (GET_CODE (x) != MEM)
10399 abort ();
10401 tmp = XEXP (x, 0);
10403 if (TARGET_E500)
10405 /* Handle [reg]. */
10406 if (GET_CODE (tmp) == REG)
10408 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
10409 break;
10411 /* Handle [reg+UIMM]. */
10412 else if (GET_CODE (tmp) == PLUS &&
10413 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
10415 int x;
10417 if (GET_CODE (XEXP (tmp, 0)) != REG)
10418 abort ();
10420 x = INTVAL (XEXP (tmp, 1));
10421 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
10422 break;
10425 /* Fall through. Must be [reg+reg]. */
10427 if (GET_CODE (tmp) == REG)
10428 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
10429 else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG)
10431 if (REGNO (XEXP (tmp, 0)) == 0)
10432 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
10433 reg_names[ REGNO (XEXP (tmp, 0)) ]);
10434 else
10435 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
10436 reg_names[ REGNO (XEXP (tmp, 1)) ]);
10438 else
10439 abort ();
10440 break;
10443 case 0:
10444 if (GET_CODE (x) == REG)
10445 fprintf (file, "%s", reg_names[REGNO (x)]);
10446 else if (GET_CODE (x) == MEM)
10448 /* We need to handle PRE_INC and PRE_DEC here, since we need to
10449 know the width from the mode. */
10450 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
10451 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
10452 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10453 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
10454 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
10455 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10456 else
10457 output_address (XEXP (x, 0));
10459 else
10460 output_addr_const (file, x);
10461 return;
10463 case '&':
10464 assemble_name (file, rs6000_get_some_local_dynamic_name ());
10465 return;
10467 default:
10468 output_operand_lossage ("invalid %%xn code");
10472 /* Print the address of an operand. */
10474 void
10475 print_operand_address (FILE *file, rtx x)
10477 if (GET_CODE (x) == REG)
10478 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
10479 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
10480 || GET_CODE (x) == LABEL_REF)
10482 output_addr_const (file, x);
10483 if (small_data_operand (x, GET_MODE (x)))
10484 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10485 reg_names[SMALL_DATA_REG]);
10486 else if (TARGET_TOC)
10487 abort ();
10489 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
10491 if (REGNO (XEXP (x, 0)) == 0)
10492 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
10493 reg_names[ REGNO (XEXP (x, 0)) ]);
10494 else
10495 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
10496 reg_names[ REGNO (XEXP (x, 1)) ]);
10498 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
10499 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
10500 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
10501 #if TARGET_ELF
10502 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10503 && CONSTANT_P (XEXP (x, 1)))
10505 output_addr_const (file, XEXP (x, 1));
10506 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10508 #endif
10509 #if TARGET_MACHO
10510 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10511 && CONSTANT_P (XEXP (x, 1)))
10513 fprintf (file, "lo16(");
10514 output_addr_const (file, XEXP (x, 1));
10515 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10517 #endif
10518 else if (legitimate_constant_pool_address_p (x))
10520 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
10522 rtx contains_minus = XEXP (x, 1);
10523 rtx minus, symref;
10524 const char *name;
10526 /* Find the (minus (sym) (toc)) buried in X, and temporarily
10527 turn it into (sym) for output_addr_const. */
10528 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
10529 contains_minus = XEXP (contains_minus, 0);
10531 minus = XEXP (contains_minus, 0);
10532 symref = XEXP (minus, 0);
10533 XEXP (contains_minus, 0) = symref;
10534 if (TARGET_ELF)
10536 char *newname;
10538 name = XSTR (symref, 0);
10539 newname = alloca (strlen (name) + sizeof ("@toc"));
10540 strcpy (newname, name);
10541 strcat (newname, "@toc");
10542 XSTR (symref, 0) = newname;
10544 output_addr_const (file, XEXP (x, 1));
10545 if (TARGET_ELF)
10546 XSTR (symref, 0) = name;
10547 XEXP (contains_minus, 0) = minus;
10549 else
10550 output_addr_const (file, XEXP (x, 1));
10552 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
10554 else
10555 abort ();
10558 /* Target hook for assembling integer objects. The PowerPC version has
10559 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
10560 is defined. It also needs to handle DI-mode objects on 64-bit
10561 targets. */
10563 static bool
10564 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
10566 #ifdef RELOCATABLE_NEEDS_FIXUP
10567 /* Special handling for SI values. */
10568 if (size == 4 && aligned_p)
10570 extern int in_toc_section (void);
10571 static int recurse = 0;
10573 /* For -mrelocatable, we mark all addresses that need to be fixed up
10574 in the .fixup section. */
10575 if (TARGET_RELOCATABLE
10576 && !in_toc_section ()
10577 && !in_text_section ()
10578 && !in_unlikely_text_section ()
10579 && !recurse
10580 && GET_CODE (x) != CONST_INT
10581 && GET_CODE (x) != CONST_DOUBLE
10582 && CONSTANT_P (x))
10584 char buf[256];
10586 recurse = 1;
10587 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
10588 fixuplabelno++;
10589 ASM_OUTPUT_LABEL (asm_out_file, buf);
10590 fprintf (asm_out_file, "\t.long\t(");
10591 output_addr_const (asm_out_file, x);
10592 fprintf (asm_out_file, ")@fixup\n");
10593 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
10594 ASM_OUTPUT_ALIGN (asm_out_file, 2);
10595 fprintf (asm_out_file, "\t.long\t");
10596 assemble_name (asm_out_file, buf);
10597 fprintf (asm_out_file, "\n\t.previous\n");
10598 recurse = 0;
10599 return true;
10601 /* Remove initial .'s to turn a -mcall-aixdesc function
10602 address into the address of the descriptor, not the function
10603 itself. */
10604 else if (GET_CODE (x) == SYMBOL_REF
10605 && XSTR (x, 0)[0] == '.'
10606 && DEFAULT_ABI == ABI_AIX)
10608 const char *name = XSTR (x, 0);
10609 while (*name == '.')
10610 name++;
10612 fprintf (asm_out_file, "\t.long\t%s\n", name);
10613 return true;
10616 #endif /* RELOCATABLE_NEEDS_FIXUP */
10617 return default_assemble_integer (x, size, aligned_p);
10620 #ifdef HAVE_GAS_HIDDEN
10621 /* Emit an assembler directive to set symbol visibility for DECL to
10622 VISIBILITY_TYPE. */
10624 static void
10625 rs6000_assemble_visibility (tree decl, int vis)
10627 /* Functions need to have their entry point symbol visibility set as
10628 well as their descriptor symbol visibility. */
10629 if (DEFAULT_ABI == ABI_AIX
10630 && DOT_SYMBOLS
10631 && TREE_CODE (decl) == FUNCTION_DECL)
10633 static const char * const visibility_types[] = {
10634 NULL, "internal", "hidden", "protected"
10637 const char *name, *type;
10639 name = ((* targetm.strip_name_encoding)
10640 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
10641 type = visibility_types[vis];
10643 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
10644 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
10646 else
10647 default_assemble_visibility (decl, vis);
10649 #endif
10651 enum rtx_code
10652 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
10654 /* Reversal of FP compares takes care -- an ordered compare
10655 becomes an unordered compare and vice versa. */
10656 if (mode == CCFPmode
10657 && (!flag_finite_math_only
10658 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
10659 || code == UNEQ || code == LTGT))
10660 return reverse_condition_maybe_unordered (code);
10661 else
10662 return reverse_condition (code);
10665 /* Generate a compare for CODE. Return a brand-new rtx that
10666 represents the result of the compare. */
10668 static rtx
10669 rs6000_generate_compare (enum rtx_code code)
10671 enum machine_mode comp_mode;
10672 rtx compare_result;
10674 if (rs6000_compare_fp_p)
10675 comp_mode = CCFPmode;
10676 else if (code == GTU || code == LTU
10677 || code == GEU || code == LEU)
10678 comp_mode = CCUNSmode;
10679 else
10680 comp_mode = CCmode;
10682 /* First, the compare. */
10683 compare_result = gen_reg_rtx (comp_mode);
10685 /* SPE FP compare instructions on the GPRs. Yuck! */
10686 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10687 && rs6000_compare_fp_p)
10689 rtx cmp, or1, or2, or_result, compare_result2;
10691 /* Note: The E500 comparison instructions set the GT bit (x +
10692 1), on success. This explains the mess. */
10694 switch (code)
10696 case EQ: case UNEQ: case NE: case LTGT:
10697 cmp = flag_finite_math_only
10698 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
10699 rs6000_compare_op1)
10700 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
10701 rs6000_compare_op1);
10702 break;
10703 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
10704 cmp = flag_finite_math_only
10705 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
10706 rs6000_compare_op1)
10707 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
10708 rs6000_compare_op1);
10709 break;
10710 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
10711 cmp = flag_finite_math_only
10712 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
10713 rs6000_compare_op1)
10714 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
10715 rs6000_compare_op1);
10716 break;
10717 default:
10718 abort ();
10721 /* Synthesize LE and GE from LT/GT || EQ. */
10722 if (code == LE || code == GE || code == LEU || code == GEU)
10724 emit_insn (cmp);
10726 switch (code)
10728 case LE: code = LT; break;
10729 case GE: code = GT; break;
10730 case LEU: code = LT; break;
10731 case GEU: code = GT; break;
10732 default: abort ();
10735 or1 = gen_reg_rtx (SImode);
10736 or2 = gen_reg_rtx (SImode);
10737 or_result = gen_reg_rtx (CCEQmode);
10738 compare_result2 = gen_reg_rtx (CCFPmode);
10740 /* Do the EQ. */
10741 cmp = flag_finite_math_only
10742 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
10743 rs6000_compare_op1)
10744 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
10745 rs6000_compare_op1);
10746 emit_insn (cmp);
10748 or1 = gen_rtx_GT (SImode, compare_result, const0_rtx);
10749 or2 = gen_rtx_GT (SImode, compare_result2, const0_rtx);
10751 /* OR them together. */
10752 cmp = gen_rtx_SET (VOIDmode, or_result,
10753 gen_rtx_COMPARE (CCEQmode,
10754 gen_rtx_IOR (SImode, or1, or2),
10755 const_true_rtx));
10756 compare_result = or_result;
10757 code = EQ;
10759 else
10761 if (code == NE || code == LTGT)
10762 code = NE;
10763 else
10764 code = EQ;
10767 emit_insn (cmp);
10769 else
10770 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
10771 gen_rtx_COMPARE (comp_mode,
10772 rs6000_compare_op0,
10773 rs6000_compare_op1)));
10775 /* Some kinds of FP comparisons need an OR operation;
10776 under flag_finite_math_only we don't bother. */
10777 if (rs6000_compare_fp_p
10778 && ! flag_finite_math_only
10779 && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
10780 && (code == LE || code == GE
10781 || code == UNEQ || code == LTGT
10782 || code == UNGT || code == UNLT))
10784 enum rtx_code or1, or2;
10785 rtx or1_rtx, or2_rtx, compare2_rtx;
10786 rtx or_result = gen_reg_rtx (CCEQmode);
10788 switch (code)
10790 case LE: or1 = LT; or2 = EQ; break;
10791 case GE: or1 = GT; or2 = EQ; break;
10792 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
10793 case LTGT: or1 = LT; or2 = GT; break;
10794 case UNGT: or1 = UNORDERED; or2 = GT; break;
10795 case UNLT: or1 = UNORDERED; or2 = LT; break;
10796 default: abort ();
10798 validate_condition_mode (or1, comp_mode);
10799 validate_condition_mode (or2, comp_mode);
10800 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
10801 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
10802 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
10803 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
10804 const_true_rtx);
10805 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
10807 compare_result = or_result;
10808 code = EQ;
10811 validate_condition_mode (code, GET_MODE (compare_result));
10813 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
10817 /* Emit the RTL for an sCOND pattern. */
10819 void
10820 rs6000_emit_sCOND (enum rtx_code code, rtx result)
10822 rtx condition_rtx;
10823 enum machine_mode op_mode;
10824 enum rtx_code cond_code;
10826 condition_rtx = rs6000_generate_compare (code);
10827 cond_code = GET_CODE (condition_rtx);
10829 if (TARGET_E500 && rs6000_compare_fp_p
10830 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10832 rtx t;
10834 PUT_MODE (condition_rtx, SImode);
10835 t = XEXP (condition_rtx, 0);
10837 if (cond_code != NE && cond_code != EQ)
10838 abort ();
10840 if (cond_code == NE)
10841 emit_insn (gen_e500_flip_eq_bit (t, t));
10843 emit_insn (gen_move_from_CR_eq_bit (result, t));
10844 return;
10847 if (cond_code == NE
10848 || cond_code == GE || cond_code == LE
10849 || cond_code == GEU || cond_code == LEU
10850 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
10852 rtx not_result = gen_reg_rtx (CCEQmode);
10853 rtx not_op, rev_cond_rtx;
10854 enum machine_mode cc_mode;
10856 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
10858 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
10859 SImode, XEXP (condition_rtx, 0), const0_rtx);
10860 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
10861 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
10862 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
10865 op_mode = GET_MODE (rs6000_compare_op0);
10866 if (op_mode == VOIDmode)
10867 op_mode = GET_MODE (rs6000_compare_op1);
10869 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
10871 PUT_MODE (condition_rtx, DImode);
10872 convert_move (result, condition_rtx, 0);
10874 else
10876 PUT_MODE (condition_rtx, SImode);
10877 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
10881 /* Emit a branch of kind CODE to location LOC. */
10883 void
10884 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
10886 rtx condition_rtx, loc_ref;
10888 condition_rtx = rs6000_generate_compare (code);
10889 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
10890 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
10891 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
10892 loc_ref, pc_rtx)));
10895 /* Return the string to output a conditional branch to LABEL, which is
10896 the operand number of the label, or -1 if the branch is really a
10897 conditional return.
10899 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
10900 condition code register and its mode specifies what kind of
10901 comparison we made.
10903 REVERSED is nonzero if we should reverse the sense of the comparison.
10905 INSN is the insn. */
10907 char *
10908 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
10910 static char string[64];
10911 enum rtx_code code = GET_CODE (op);
10912 rtx cc_reg = XEXP (op, 0);
10913 enum machine_mode mode = GET_MODE (cc_reg);
10914 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
10915 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
10916 int really_reversed = reversed ^ need_longbranch;
10917 char *s = string;
10918 const char *ccode;
10919 const char *pred;
10920 rtx note;
10922 validate_condition_mode (code, mode);
10924 /* Work out which way this really branches. We could use
10925 reverse_condition_maybe_unordered here always but this
10926 makes the resulting assembler clearer. */
10927 if (really_reversed)
10929 /* Reversal of FP compares takes care -- an ordered compare
10930 becomes an unordered compare and vice versa. */
10931 if (mode == CCFPmode)
10932 code = reverse_condition_maybe_unordered (code);
10933 else
10934 code = reverse_condition (code);
10937 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
10939 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
10940 to the GT bit. */
10941 if (code == EQ)
10942 /* Opposite of GT. */
10943 code = GT;
10944 else if (code == NE)
10945 code = UNLE;
10946 else
10947 abort ();
10950 switch (code)
10952 /* Not all of these are actually distinct opcodes, but
10953 we distinguish them for clarity of the resulting assembler. */
10954 case NE: case LTGT:
10955 ccode = "ne"; break;
10956 case EQ: case UNEQ:
10957 ccode = "eq"; break;
10958 case GE: case GEU:
10959 ccode = "ge"; break;
10960 case GT: case GTU: case UNGT:
10961 ccode = "gt"; break;
10962 case LE: case LEU:
10963 ccode = "le"; break;
10964 case LT: case LTU: case UNLT:
10965 ccode = "lt"; break;
10966 case UNORDERED: ccode = "un"; break;
10967 case ORDERED: ccode = "nu"; break;
10968 case UNGE: ccode = "nl"; break;
10969 case UNLE: ccode = "ng"; break;
10970 default:
10971 abort ();
10974 /* Maybe we have a guess as to how likely the branch is.
10975 The old mnemonics don't have a way to specify this information. */
10976 pred = "";
10977 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
10978 if (note != NULL_RTX)
10980 /* PROB is the difference from 50%. */
10981 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
10983 /* Only hint for highly probable/improbable branches on newer
10984 cpus as static prediction overrides processor dynamic
10985 prediction. For older cpus we may as well always hint, but
10986 assume not taken for branches that are very close to 50% as a
10987 mispredicted taken branch is more expensive than a
10988 mispredicted not-taken branch. */
10989 if (rs6000_always_hint
10990 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
10992 if (abs (prob) > REG_BR_PROB_BASE / 20
10993 && ((prob > 0) ^ need_longbranch))
10994 pred = "+";
10995 else
10996 pred = "-";
11000 if (label == NULL)
11001 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11002 else
11003 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11005 /* We need to escape any '%' characters in the reg_names string.
11006 Assume they'd only be the first character.... */
11007 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11008 *s++ = '%';
11009 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11011 if (label != NULL)
11013 /* If the branch distance was too far, we may have to use an
11014 unconditional branch to go the distance. */
11015 if (need_longbranch)
11016 s += sprintf (s, ",$+8\n\tb %s", label);
11017 else
11018 s += sprintf (s, ",%s", label);
11021 return string;
11024 /* Return the string to flip the EQ bit on a CR. */
11025 char *
11026 output_e500_flip_eq_bit (rtx dst, rtx src)
11028 static char string[64];
11029 int a, b;
11031 if (GET_CODE (dst) != REG || ! CR_REGNO_P (REGNO (dst))
11032 || GET_CODE (src) != REG || ! CR_REGNO_P (REGNO (src)))
11033 abort ();
11035 /* EQ bit. */
11036 a = 4 * (REGNO (dst) - CR0_REGNO) + 2;
11037 b = 4 * (REGNO (src) - CR0_REGNO) + 2;
11039 sprintf (string, "crnot %d,%d", a, b);
11040 return string;
11043 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
11044 operands of the last comparison is nonzero/true, FALSE_COND if it
11045 is zero/false. Return 0 if the hardware has no such operation. */
11048 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11050 enum rtx_code code = GET_CODE (op);
11051 rtx op0 = rs6000_compare_op0;
11052 rtx op1 = rs6000_compare_op1;
11053 REAL_VALUE_TYPE c1;
11054 enum machine_mode compare_mode = GET_MODE (op0);
11055 enum machine_mode result_mode = GET_MODE (dest);
11056 rtx temp;
11058 /* These modes should always match. */
11059 if (GET_MODE (op1) != compare_mode
11060 /* In the isel case however, we can use a compare immediate, so
11061 op1 may be a small constant. */
11062 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
11063 return 0;
11064 if (GET_MODE (true_cond) != result_mode)
11065 return 0;
11066 if (GET_MODE (false_cond) != result_mode)
11067 return 0;
11069 /* First, work out if the hardware can do this at all, or
11070 if it's too slow.... */
11071 if (! rs6000_compare_fp_p)
11073 if (TARGET_ISEL)
11074 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
11075 return 0;
11077 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
11078 && GET_MODE_CLASS (compare_mode) == MODE_FLOAT)
11079 return 0;
11081 /* Eliminate half of the comparisons by switching operands, this
11082 makes the remaining code simpler. */
11083 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
11084 || code == LTGT || code == LT || code == UNLE)
11086 code = reverse_condition_maybe_unordered (code);
11087 temp = true_cond;
11088 true_cond = false_cond;
11089 false_cond = temp;
11092 /* UNEQ and LTGT take four instructions for a comparison with zero,
11093 it'll probably be faster to use a branch here too. */
11094 if (code == UNEQ && HONOR_NANS (compare_mode))
11095 return 0;
11097 if (GET_CODE (op1) == CONST_DOUBLE)
11098 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
11100 /* We're going to try to implement comparisons by performing
11101 a subtract, then comparing against zero. Unfortunately,
11102 Inf - Inf is NaN which is not zero, and so if we don't
11103 know that the operand is finite and the comparison
11104 would treat EQ different to UNORDERED, we can't do it. */
11105 if (HONOR_INFINITIES (compare_mode)
11106 && code != GT && code != UNGE
11107 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
11108 /* Constructs of the form (a OP b ? a : b) are safe. */
11109 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
11110 || (! rtx_equal_p (op0, true_cond)
11111 && ! rtx_equal_p (op1, true_cond))))
11112 return 0;
11113 /* At this point we know we can use fsel. */
11115 /* Reduce the comparison to a comparison against zero. */
11116 temp = gen_reg_rtx (compare_mode);
11117 emit_insn (gen_rtx_SET (VOIDmode, temp,
11118 gen_rtx_MINUS (compare_mode, op0, op1)));
11119 op0 = temp;
11120 op1 = CONST0_RTX (compare_mode);
11122 /* If we don't care about NaNs we can reduce some of the comparisons
11123 down to faster ones. */
11124 if (! HONOR_NANS (compare_mode))
11125 switch (code)
11127 case GT:
11128 code = LE;
11129 temp = true_cond;
11130 true_cond = false_cond;
11131 false_cond = temp;
11132 break;
11133 case UNGE:
11134 code = GE;
11135 break;
11136 case UNEQ:
11137 code = EQ;
11138 break;
11139 default:
11140 break;
11143 /* Now, reduce everything down to a GE. */
11144 switch (code)
11146 case GE:
11147 break;
11149 case LE:
11150 temp = gen_reg_rtx (compare_mode);
11151 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11152 op0 = temp;
11153 break;
11155 case ORDERED:
11156 temp = gen_reg_rtx (compare_mode);
11157 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
11158 op0 = temp;
11159 break;
11161 case EQ:
11162 temp = gen_reg_rtx (compare_mode);
11163 emit_insn (gen_rtx_SET (VOIDmode, temp,
11164 gen_rtx_NEG (compare_mode,
11165 gen_rtx_ABS (compare_mode, op0))));
11166 op0 = temp;
11167 break;
11169 case UNGE:
11170 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
11171 temp = gen_reg_rtx (result_mode);
11172 emit_insn (gen_rtx_SET (VOIDmode, temp,
11173 gen_rtx_IF_THEN_ELSE (result_mode,
11174 gen_rtx_GE (VOIDmode,
11175 op0, op1),
11176 true_cond, false_cond)));
11177 false_cond = true_cond;
11178 true_cond = temp;
11180 temp = gen_reg_rtx (compare_mode);
11181 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11182 op0 = temp;
11183 break;
11185 case GT:
11186 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
11187 temp = gen_reg_rtx (result_mode);
11188 emit_insn (gen_rtx_SET (VOIDmode, temp,
11189 gen_rtx_IF_THEN_ELSE (result_mode,
11190 gen_rtx_GE (VOIDmode,
11191 op0, op1),
11192 true_cond, false_cond)));
11193 true_cond = false_cond;
11194 false_cond = temp;
11196 temp = gen_reg_rtx (compare_mode);
11197 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11198 op0 = temp;
11199 break;
11201 default:
11202 abort ();
11205 emit_insn (gen_rtx_SET (VOIDmode, dest,
11206 gen_rtx_IF_THEN_ELSE (result_mode,
11207 gen_rtx_GE (VOIDmode,
11208 op0, op1),
11209 true_cond, false_cond)));
11210 return 1;
11213 /* Same as above, but for ints (isel). */
11215 static int
11216 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11218 rtx condition_rtx, cr;
11220 /* All isel implementations thus far are 32-bits. */
11221 if (GET_MODE (rs6000_compare_op0) != SImode)
11222 return 0;
11224 /* We still have to do the compare, because isel doesn't do a
11225 compare, it just looks at the CRx bits set by a previous compare
11226 instruction. */
11227 condition_rtx = rs6000_generate_compare (GET_CODE (op));
11228 cr = XEXP (condition_rtx, 0);
11230 if (GET_MODE (cr) == CCmode)
11231 emit_insn (gen_isel_signed (dest, condition_rtx,
11232 true_cond, false_cond, cr));
11233 else
11234 emit_insn (gen_isel_unsigned (dest, condition_rtx,
11235 true_cond, false_cond, cr));
11237 return 1;
11240 const char *
11241 output_isel (rtx *operands)
11243 enum rtx_code code;
11245 code = GET_CODE (operands[1]);
11246 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
11248 PUT_CODE (operands[1], reverse_condition (code));
11249 return "isel %0,%3,%2,%j1";
11251 else
11252 return "isel %0,%2,%3,%j1";
11255 void
11256 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
11258 enum machine_mode mode = GET_MODE (op0);
11259 enum rtx_code c;
11260 rtx target;
11262 if (code == SMAX || code == SMIN)
11263 c = GE;
11264 else
11265 c = GEU;
11267 if (code == SMAX || code == UMAX)
11268 target = emit_conditional_move (dest, c, op0, op1, mode,
11269 op0, op1, mode, 0);
11270 else
11271 target = emit_conditional_move (dest, c, op0, op1, mode,
11272 op1, op0, mode, 0);
11273 if (target == NULL_RTX)
11274 abort ();
11275 if (target != dest)
11276 emit_move_insn (dest, target);
11279 /* Emit instructions to move SRC to DST. Called by splitters for
11280 multi-register moves. It will emit at most one instruction for
11281 each register that is accessed; that is, it won't emit li/lis pairs
11282 (or equivalent for 64-bit code). One of SRC or DST must be a hard
11283 register. */
11285 void
11286 rs6000_split_multireg_move (rtx dst, rtx src)
11288 /* The register number of the first register being moved. */
11289 int reg;
11290 /* The mode that is to be moved. */
11291 enum machine_mode mode;
11292 /* The mode that the move is being done in, and its size. */
11293 enum machine_mode reg_mode;
11294 int reg_mode_size;
11295 /* The number of registers that will be moved. */
11296 int nregs;
11298 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
11299 mode = GET_MODE (dst);
11300 nregs = HARD_REGNO_NREGS (reg, mode);
11301 if (FP_REGNO_P (reg))
11302 reg_mode = DFmode;
11303 else if (ALTIVEC_REGNO_P (reg))
11304 reg_mode = V16QImode;
11305 else
11306 reg_mode = word_mode;
11307 reg_mode_size = GET_MODE_SIZE (reg_mode);
11309 if (reg_mode_size * nregs != GET_MODE_SIZE (mode))
11310 abort ();
11312 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
11314 /* Move register range backwards, if we might have destructive
11315 overlap. */
11316 int i;
11317 for (i = nregs - 1; i >= 0; i--)
11318 emit_insn (gen_rtx_SET (VOIDmode,
11319 simplify_gen_subreg (reg_mode, dst, mode,
11320 i * reg_mode_size),
11321 simplify_gen_subreg (reg_mode, src, mode,
11322 i * reg_mode_size)));
11324 else
11326 int i;
11327 int j = -1;
11328 bool used_update = false;
11330 if (MEM_P (src) && INT_REGNO_P (reg))
11332 rtx breg;
11334 if (GET_CODE (XEXP (src, 0)) == PRE_INC
11335 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
11337 rtx delta_rtx;
11338 breg = XEXP (XEXP (src, 0), 0);
11339 delta_rtx = GET_CODE (XEXP (src, 0)) == PRE_INC
11340 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
11341 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src)));
11342 emit_insn (TARGET_32BIT
11343 ? gen_addsi3 (breg, breg, delta_rtx)
11344 : gen_adddi3 (breg, breg, delta_rtx));
11345 src = gen_rtx_MEM (mode, breg);
11347 else if (! offsettable_memref_p (src))
11349 rtx newsrc, basereg;
11350 basereg = gen_rtx_REG (Pmode, reg);
11351 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
11352 newsrc = gen_rtx_MEM (GET_MODE (src), basereg);
11353 MEM_COPY_ATTRIBUTES (newsrc, src);
11354 src = newsrc;
11357 /* We have now address involving an base register only.
11358 If we use one of the registers to address memory,
11359 we have change that register last. */
11361 breg = (GET_CODE (XEXP (src, 0)) == PLUS
11362 ? XEXP (XEXP (src, 0), 0)
11363 : XEXP (src, 0));
11365 if (!REG_P (breg))
11366 abort();
11368 if (REGNO (breg) >= REGNO (dst)
11369 && REGNO (breg) < REGNO (dst) + nregs)
11370 j = REGNO (breg) - REGNO (dst);
11373 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
11375 rtx breg;
11377 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
11378 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
11380 rtx delta_rtx;
11381 breg = XEXP (XEXP (dst, 0), 0);
11382 delta_rtx = GET_CODE (XEXP (dst, 0)) == PRE_INC
11383 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
11384 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst)));
11386 /* We have to update the breg before doing the store.
11387 Use store with update, if available. */
11389 if (TARGET_UPDATE)
11391 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
11392 emit_insn (TARGET_32BIT
11393 ? gen_movsi_update (breg, breg, delta_rtx, nsrc)
11394 : gen_movdi_update (breg, breg, delta_rtx, nsrc));
11395 used_update = true;
11397 else
11398 emit_insn (TARGET_32BIT
11399 ? gen_addsi3 (breg, breg, delta_rtx)
11400 : gen_adddi3 (breg, breg, delta_rtx));
11401 dst = gen_rtx_MEM (mode, breg);
11403 else if (! offsettable_memref_p (dst))
11404 abort ();
11407 for (i = 0; i < nregs; i++)
11409 /* Calculate index to next subword. */
11410 ++j;
11411 if (j == nregs)
11412 j = 0;
11414 /* If compiler already emited move of first word by
11415 store with update, no need to do anything. */
11416 if (j == 0 && used_update)
11417 continue;
11419 emit_insn (gen_rtx_SET (VOIDmode,
11420 simplify_gen_subreg (reg_mode, dst, mode,
11421 j * reg_mode_size),
11422 simplify_gen_subreg (reg_mode, src, mode,
11423 j * reg_mode_size)));
11429 /* This page contains routines that are used to determine what the
11430 function prologue and epilogue code will do and write them out. */
11432 /* Return the first fixed-point register that is required to be
11433 saved. 32 if none. */
11436 first_reg_to_save (void)
11438 int first_reg;
11440 /* Find lowest numbered live register. */
11441 for (first_reg = 13; first_reg <= 31; first_reg++)
11442 if (regs_ever_live[first_reg]
11443 && (! call_used_regs[first_reg]
11444 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
11445 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
11446 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
11447 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
11448 break;
11450 #if TARGET_MACHO
11451 if (flag_pic
11452 && current_function_uses_pic_offset_table
11453 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
11454 return RS6000_PIC_OFFSET_TABLE_REGNUM;
11455 #endif
11457 return first_reg;
11460 /* Similar, for FP regs. */
11463 first_fp_reg_to_save (void)
11465 int first_reg;
11467 /* Find lowest numbered live register. */
11468 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
11469 if (regs_ever_live[first_reg])
11470 break;
11472 return first_reg;
11475 /* Similar, for AltiVec regs. */
11477 static int
11478 first_altivec_reg_to_save (void)
11480 int i;
11482 /* Stack frame remains as is unless we are in AltiVec ABI. */
11483 if (! TARGET_ALTIVEC_ABI)
11484 return LAST_ALTIVEC_REGNO + 1;
11486 /* Find lowest numbered live register. */
11487 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
11488 if (regs_ever_live[i])
11489 break;
11491 return i;
11494 /* Return a 32-bit mask of the AltiVec registers we need to set in
11495 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
11496 the 32-bit word is 0. */
11498 static unsigned int
11499 compute_vrsave_mask (void)
11501 unsigned int i, mask = 0;
11503 /* First, find out if we use _any_ altivec registers. */
11504 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
11505 if (regs_ever_live[i])
11506 mask |= ALTIVEC_REG_BIT (i);
11508 if (mask == 0)
11509 return mask;
11511 /* Next, remove the argument registers from the set. These must
11512 be in the VRSAVE mask set by the caller, so we don't need to add
11513 them in again. More importantly, the mask we compute here is
11514 used to generate CLOBBERs in the set_vrsave insn, and we do not
11515 wish the argument registers to die. */
11516 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
11517 mask &= ~ALTIVEC_REG_BIT (i);
11519 /* Similarly, remove the return value from the set. */
11521 bool yes = false;
11522 diddle_return_value (is_altivec_return_reg, &yes);
11523 if (yes)
11524 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
11527 return mask;
11530 /* For a very restricted set of circumstances, we can cut down the
11531 size of prologs/epilogs by calling our own save/restore-the-world
11532 routines. */
11534 static void
11535 compute_save_world_info(rs6000_stack_t *info_ptr)
11537 info_ptr->world_save_p =
11538 (DEFAULT_ABI == ABI_DARWIN)
11539 && ! (current_function_calls_setjmp && flag_exceptions)
11540 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
11541 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
11542 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
11543 && info_ptr->cr_save_p;
11545 /* This will not work in conjunction with sibcalls. Make sure there
11546 are none. (This check is expensive, but seldom executed.) */
11547 if ( info_ptr->world_save_p )
11549 rtx insn;
11550 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
11551 if ( GET_CODE (insn) == CALL_INSN
11552 && SIBLING_CALL_P (insn))
11554 info_ptr->world_save_p = 0;
11555 break;
11559 if (info_ptr->world_save_p)
11561 /* Even if we're not touching VRsave, make sure there's room on the
11562 stack for it, if it looks like we're calling SAVE_WORLD, which
11563 will attempt to save it. */
11564 info_ptr->vrsave_size = 4;
11566 /* "Save" the VRsave register too if we're saving the world. */
11567 if (info_ptr->vrsave_mask == 0)
11568 info_ptr->vrsave_mask = compute_vrsave_mask ();
11570 /* Because the Darwin register save/restore routines only handle
11571 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistancy
11572 check and abort if there's something worng. */
11573 if (info_ptr->first_fp_reg_save < FIRST_SAVED_FP_REGNO
11574 || info_ptr->first_altivec_reg_save < FIRST_SAVED_ALTIVEC_REGNO)
11575 abort ();
11577 return;
11581 static void
11582 is_altivec_return_reg (rtx reg, void *xyes)
11584 bool *yes = (bool *) xyes;
11585 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
11586 *yes = true;
11590 /* Calculate the stack information for the current function. This is
11591 complicated by having two separate calling sequences, the AIX calling
11592 sequence and the V.4 calling sequence.
11594 AIX (and Darwin/Mac OS X) stack frames look like:
11595 32-bit 64-bit
11596 SP----> +---------------------------------------+
11597 | back chain to caller | 0 0
11598 +---------------------------------------+
11599 | saved CR | 4 8 (8-11)
11600 +---------------------------------------+
11601 | saved LR | 8 16
11602 +---------------------------------------+
11603 | reserved for compilers | 12 24
11604 +---------------------------------------+
11605 | reserved for binders | 16 32
11606 +---------------------------------------+
11607 | saved TOC pointer | 20 40
11608 +---------------------------------------+
11609 | Parameter save area (P) | 24 48
11610 +---------------------------------------+
11611 | Alloca space (A) | 24+P etc.
11612 +---------------------------------------+
11613 | Local variable space (L) | 24+P+A
11614 +---------------------------------------+
11615 | Float/int conversion temporary (X) | 24+P+A+L
11616 +---------------------------------------+
11617 | Save area for AltiVec registers (W) | 24+P+A+L+X
11618 +---------------------------------------+
11619 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
11620 +---------------------------------------+
11621 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
11622 +---------------------------------------+
11623 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
11624 +---------------------------------------+
11625 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
11626 +---------------------------------------+
11627 old SP->| back chain to caller's caller |
11628 +---------------------------------------+
11630 The required alignment for AIX configurations is two words (i.e., 8
11631 or 16 bytes).
11634 V.4 stack frames look like:
11636 SP----> +---------------------------------------+
11637 | back chain to caller | 0
11638 +---------------------------------------+
11639 | caller's saved LR | 4
11640 +---------------------------------------+
11641 | Parameter save area (P) | 8
11642 +---------------------------------------+
11643 | Alloca space (A) | 8+P
11644 +---------------------------------------+
11645 | Varargs save area (V) | 8+P+A
11646 +---------------------------------------+
11647 | Local variable space (L) | 8+P+A+V
11648 +---------------------------------------+
11649 | Float/int conversion temporary (X) | 8+P+A+V+L
11650 +---------------------------------------+
11651 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
11652 +---------------------------------------+
11653 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
11654 +---------------------------------------+
11655 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
11656 +---------------------------------------+
11657 | SPE: area for 64-bit GP registers |
11658 +---------------------------------------+
11659 | SPE alignment padding |
11660 +---------------------------------------+
11661 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
11662 +---------------------------------------+
11663 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
11664 +---------------------------------------+
11665 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
11666 +---------------------------------------+
11667 old SP->| back chain to caller's caller |
11668 +---------------------------------------+
11670 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
11671 given. (But note below and in sysv4.h that we require only 8 and
11672 may round up the size of our stack frame anyways. The historical
11673 reason is early versions of powerpc-linux which didn't properly
11674 align the stack at program startup. A happy side-effect is that
11675 -mno-eabi libraries can be used with -meabi programs.)
11677 The EABI configuration defaults to the V.4 layout. However,
11678 the stack alignment requirements may differ. If -mno-eabi is not
11679 given, the required stack alignment is 8 bytes; if -mno-eabi is
11680 given, the required alignment is 16 bytes. (But see V.4 comment
11681 above.) */
11683 #ifndef ABI_STACK_BOUNDARY
11684 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
11685 #endif
11687 static rs6000_stack_t *
11688 rs6000_stack_info (void)
11690 static rs6000_stack_t info, zero_info;
11691 rs6000_stack_t *info_ptr = &info;
11692 int reg_size = TARGET_32BIT ? 4 : 8;
11693 int ehrd_size;
11694 HOST_WIDE_INT non_fixed_size;
11696 /* Zero all fields portably. */
11697 info = zero_info;
11699 if (TARGET_SPE)
11701 /* Cache value so we don't rescan instruction chain over and over. */
11702 if (cfun->machine->insn_chain_scanned_p == 0)
11704 cfun->machine->insn_chain_scanned_p = 1;
11705 info_ptr->spe_64bit_regs_used = (int) spe_func_has_64bit_regs_p ();
11709 /* Select which calling sequence. */
11710 info_ptr->abi = DEFAULT_ABI;
11712 /* Calculate which registers need to be saved & save area size. */
11713 info_ptr->first_gp_reg_save = first_reg_to_save ();
11714 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
11715 even if it currently looks like we won't. */
11716 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
11717 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
11718 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
11719 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
11720 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
11721 else
11722 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
11724 /* For the SPE, we have an additional upper 32-bits on each GPR.
11725 Ideally we should save the entire 64-bits only when the upper
11726 half is used in SIMD instructions. Since we only record
11727 registers live (not the size they are used in), this proves
11728 difficult because we'd have to traverse the instruction chain at
11729 the right time, taking reload into account. This is a real pain,
11730 so we opt to save the GPRs in 64-bits always if but one register
11731 gets used in 64-bits. Otherwise, all the registers in the frame
11732 get saved in 32-bits.
11734 So... since when we save all GPRs (except the SP) in 64-bits, the
11735 traditional GP save area will be empty. */
11736 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
11737 info_ptr->gp_size = 0;
11739 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
11740 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
11742 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
11743 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
11744 - info_ptr->first_altivec_reg_save);
11746 /* Does this function call anything? */
11747 info_ptr->calls_p = (! current_function_is_leaf
11748 || cfun->machine->ra_needs_full_frame);
11750 /* Determine if we need to save the link register. */
11751 if (rs6000_ra_ever_killed ()
11752 || (DEFAULT_ABI == ABI_AIX
11753 && current_function_profile
11754 && !TARGET_PROFILE_KERNEL)
11755 #ifdef TARGET_RELOCATABLE
11756 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
11757 #endif
11758 || (info_ptr->first_fp_reg_save != 64
11759 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
11760 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
11761 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
11762 || (DEFAULT_ABI == ABI_DARWIN
11763 && flag_pic
11764 && current_function_uses_pic_offset_table)
11765 || info_ptr->calls_p)
11767 info_ptr->lr_save_p = 1;
11768 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
11771 /* Determine if we need to save the condition code registers. */
11772 if (regs_ever_live[CR2_REGNO]
11773 || regs_ever_live[CR3_REGNO]
11774 || regs_ever_live[CR4_REGNO])
11776 info_ptr->cr_save_p = 1;
11777 if (DEFAULT_ABI == ABI_V4)
11778 info_ptr->cr_size = reg_size;
11781 /* If the current function calls __builtin_eh_return, then we need
11782 to allocate stack space for registers that will hold data for
11783 the exception handler. */
11784 if (current_function_calls_eh_return)
11786 unsigned int i;
11787 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
11788 continue;
11790 /* SPE saves EH registers in 64-bits. */
11791 ehrd_size = i * (TARGET_SPE_ABI
11792 && info_ptr->spe_64bit_regs_used != 0
11793 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
11795 else
11796 ehrd_size = 0;
11798 /* Determine various sizes. */
11799 info_ptr->reg_size = reg_size;
11800 info_ptr->fixed_size = RS6000_SAVE_AREA;
11801 info_ptr->varargs_size = RS6000_VARARGS_AREA;
11802 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
11803 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
11804 TARGET_ALTIVEC ? 16 : 8);
11806 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
11807 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
11808 else
11809 info_ptr->spe_gp_size = 0;
11811 if (TARGET_ALTIVEC_ABI)
11812 info_ptr->vrsave_mask = compute_vrsave_mask ();
11813 else
11814 info_ptr->vrsave_mask = 0;
11816 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
11817 info_ptr->vrsave_size = 4;
11818 else
11819 info_ptr->vrsave_size = 0;
11821 compute_save_world_info (info_ptr);
11823 /* Calculate the offsets. */
11824 switch (DEFAULT_ABI)
11826 case ABI_NONE:
11827 default:
11828 abort ();
11830 case ABI_AIX:
11831 case ABI_DARWIN:
11832 info_ptr->fp_save_offset = - info_ptr->fp_size;
11833 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
11835 if (TARGET_ALTIVEC_ABI)
11837 info_ptr->vrsave_save_offset
11838 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
11840 /* Align stack so vector save area is on a quadword boundary. */
11841 if (info_ptr->altivec_size != 0)
11842 info_ptr->altivec_padding_size
11843 = 16 - (-info_ptr->vrsave_save_offset % 16);
11844 else
11845 info_ptr->altivec_padding_size = 0;
11847 info_ptr->altivec_save_offset
11848 = info_ptr->vrsave_save_offset
11849 - info_ptr->altivec_padding_size
11850 - info_ptr->altivec_size;
11852 /* Adjust for AltiVec case. */
11853 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
11855 else
11856 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
11857 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
11858 info_ptr->lr_save_offset = 2*reg_size;
11859 break;
11861 case ABI_V4:
11862 info_ptr->fp_save_offset = - info_ptr->fp_size;
11863 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
11864 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
11866 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
11868 /* Align stack so SPE GPR save area is aligned on a
11869 double-word boundary. */
11870 if (info_ptr->spe_gp_size != 0)
11871 info_ptr->spe_padding_size
11872 = 8 - (-info_ptr->cr_save_offset % 8);
11873 else
11874 info_ptr->spe_padding_size = 0;
11876 info_ptr->spe_gp_save_offset
11877 = info_ptr->cr_save_offset
11878 - info_ptr->spe_padding_size
11879 - info_ptr->spe_gp_size;
11881 /* Adjust for SPE case. */
11882 info_ptr->toc_save_offset
11883 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
11885 else if (TARGET_ALTIVEC_ABI)
11887 info_ptr->vrsave_save_offset
11888 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
11890 /* Align stack so vector save area is on a quadword boundary. */
11891 if (info_ptr->altivec_size != 0)
11892 info_ptr->altivec_padding_size
11893 = 16 - (-info_ptr->vrsave_save_offset % 16);
11894 else
11895 info_ptr->altivec_padding_size = 0;
11897 info_ptr->altivec_save_offset
11898 = info_ptr->vrsave_save_offset
11899 - info_ptr->altivec_padding_size
11900 - info_ptr->altivec_size;
11902 /* Adjust for AltiVec case. */
11903 info_ptr->toc_save_offset
11904 = info_ptr->altivec_save_offset - info_ptr->toc_size;
11906 else
11907 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
11908 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
11909 info_ptr->lr_save_offset = reg_size;
11910 break;
11913 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
11914 + info_ptr->gp_size
11915 + info_ptr->altivec_size
11916 + info_ptr->altivec_padding_size
11917 + info_ptr->spe_gp_size
11918 + info_ptr->spe_padding_size
11919 + ehrd_size
11920 + info_ptr->cr_size
11921 + info_ptr->lr_size
11922 + info_ptr->vrsave_size
11923 + info_ptr->toc_size,
11924 (TARGET_ALTIVEC_ABI || ABI_DARWIN)
11925 ? 16 : 8);
11927 non_fixed_size = (info_ptr->vars_size
11928 + info_ptr->parm_size
11929 + info_ptr->save_size
11930 + info_ptr->varargs_size);
11932 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
11933 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
11935 /* Determine if we need to allocate any stack frame:
11937 For AIX we need to push the stack if a frame pointer is needed
11938 (because the stack might be dynamically adjusted), if we are
11939 debugging, if we make calls, or if the sum of fp_save, gp_save,
11940 and local variables are more than the space needed to save all
11941 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
11942 + 18*8 = 288 (GPR13 reserved).
11944 For V.4 we don't have the stack cushion that AIX uses, but assume
11945 that the debugger can handle stackless frames. */
11947 if (info_ptr->calls_p)
11948 info_ptr->push_p = 1;
11950 else if (DEFAULT_ABI == ABI_V4)
11951 info_ptr->push_p = non_fixed_size != 0;
11953 else if (frame_pointer_needed)
11954 info_ptr->push_p = 1;
11956 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
11957 info_ptr->push_p = 1;
11959 else
11960 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
11962 /* Zero offsets if we're not saving those registers. */
11963 if (info_ptr->fp_size == 0)
11964 info_ptr->fp_save_offset = 0;
11966 if (info_ptr->gp_size == 0)
11967 info_ptr->gp_save_offset = 0;
11969 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
11970 info_ptr->altivec_save_offset = 0;
11972 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
11973 info_ptr->vrsave_save_offset = 0;
11975 if (! TARGET_SPE_ABI
11976 || info_ptr->spe_64bit_regs_used == 0
11977 || info_ptr->spe_gp_size == 0)
11978 info_ptr->spe_gp_save_offset = 0;
11980 if (! info_ptr->lr_save_p)
11981 info_ptr->lr_save_offset = 0;
11983 if (! info_ptr->cr_save_p)
11984 info_ptr->cr_save_offset = 0;
11986 if (! info_ptr->toc_save_p)
11987 info_ptr->toc_save_offset = 0;
11989 return info_ptr;
11992 /* Return true if the current function uses any GPRs in 64-bit SIMD
11993 mode. */
11995 static bool
11996 spe_func_has_64bit_regs_p (void)
11998 rtx insns, insn;
12000 /* Functions that save and restore all the call-saved registers will
12001 need to save/restore the registers in 64-bits. */
12002 if (current_function_calls_eh_return
12003 || current_function_calls_setjmp
12004 || current_function_has_nonlocal_goto)
12005 return true;
12007 insns = get_insns ();
12009 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
12011 if (INSN_P (insn))
12013 rtx i;
12015 i = PATTERN (insn);
12016 if (GET_CODE (i) == SET
12017 && SPE_VECTOR_MODE (GET_MODE (SET_SRC (i))))
12018 return true;
12022 return false;
12025 static void
12026 debug_stack_info (rs6000_stack_t *info)
12028 const char *abi_string;
12030 if (! info)
12031 info = rs6000_stack_info ();
12033 fprintf (stderr, "\nStack information for function %s:\n",
12034 ((current_function_decl && DECL_NAME (current_function_decl))
12035 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
12036 : "<unknown>"));
12038 switch (info->abi)
12040 default: abi_string = "Unknown"; break;
12041 case ABI_NONE: abi_string = "NONE"; break;
12042 case ABI_AIX: abi_string = "AIX"; break;
12043 case ABI_DARWIN: abi_string = "Darwin"; break;
12044 case ABI_V4: abi_string = "V.4"; break;
12047 fprintf (stderr, "\tABI = %5s\n", abi_string);
12049 if (TARGET_ALTIVEC_ABI)
12050 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
12052 if (TARGET_SPE_ABI)
12053 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
12055 if (info->first_gp_reg_save != 32)
12056 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
12058 if (info->first_fp_reg_save != 64)
12059 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
12061 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
12062 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
12063 info->first_altivec_reg_save);
12065 if (info->lr_save_p)
12066 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
12068 if (info->cr_save_p)
12069 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
12071 if (info->toc_save_p)
12072 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
12074 if (info->vrsave_mask)
12075 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
12077 if (info->push_p)
12078 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
12080 if (info->calls_p)
12081 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
12083 if (info->gp_save_offset)
12084 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
12086 if (info->fp_save_offset)
12087 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
12089 if (info->altivec_save_offset)
12090 fprintf (stderr, "\taltivec_save_offset = %5d\n",
12091 info->altivec_save_offset);
12093 if (info->spe_gp_save_offset)
12094 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
12095 info->spe_gp_save_offset);
12097 if (info->vrsave_save_offset)
12098 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
12099 info->vrsave_save_offset);
12101 if (info->lr_save_offset)
12102 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
12104 if (info->cr_save_offset)
12105 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
12107 if (info->toc_save_offset)
12108 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
12110 if (info->varargs_save_offset)
12111 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
12113 if (info->total_size)
12114 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
12115 info->total_size);
12117 if (info->varargs_size)
12118 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
12120 if (info->vars_size)
12121 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
12122 info->vars_size);
12124 if (info->parm_size)
12125 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
12127 if (info->fixed_size)
12128 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
12130 if (info->gp_size)
12131 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
12133 if (info->spe_gp_size)
12134 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
12136 if (info->fp_size)
12137 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
12139 if (info->altivec_size)
12140 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
12142 if (info->vrsave_size)
12143 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
12145 if (info->altivec_padding_size)
12146 fprintf (stderr, "\taltivec_padding_size= %5d\n",
12147 info->altivec_padding_size);
12149 if (info->spe_padding_size)
12150 fprintf (stderr, "\tspe_padding_size = %5d\n",
12151 info->spe_padding_size);
12153 if (info->lr_size)
12154 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
12156 if (info->cr_size)
12157 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
12159 if (info->toc_size)
12160 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
12162 if (info->save_size)
12163 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
12165 if (info->reg_size != 4)
12166 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
12168 fprintf (stderr, "\n");
12172 rs6000_return_addr (int count, rtx frame)
12174 /* Currently we don't optimize very well between prolog and body
12175 code and for PIC code the code can be actually quite bad, so
12176 don't try to be too clever here. */
12177 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
12179 cfun->machine->ra_needs_full_frame = 1;
12181 return
12182 gen_rtx_MEM
12183 (Pmode,
12184 memory_address
12185 (Pmode,
12186 plus_constant (copy_to_reg
12187 (gen_rtx_MEM (Pmode,
12188 memory_address (Pmode, frame))),
12189 RETURN_ADDRESS_OFFSET)));
12192 cfun->machine->ra_need_lr = 1;
12193 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
12196 /* Say whether a function is a candidate for sibcall handling or not.
12197 We do not allow indirect calls to be optimized into sibling calls.
12198 Also, we can't do it if there are any vector parameters; there's
12199 nowhere to put the VRsave code so it works; note that functions with
12200 vector parameters are required to have a prototype, so the argument
12201 type info must be available here. (The tail recursion case can work
12202 with vector parameters, but there's no way to distinguish here.) */
12203 static bool
12204 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
12206 tree type;
12207 if (decl)
12209 if (TARGET_ALTIVEC_VRSAVE)
12211 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
12212 type; type = TREE_CHAIN (type))
12214 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
12215 return false;
12218 if (DEFAULT_ABI == ABI_DARWIN
12219 || (*targetm.binds_local_p) (decl))
12221 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
12223 if (!lookup_attribute ("longcall", attr_list)
12224 || lookup_attribute ("shortcall", attr_list))
12225 return true;
12228 return false;
12231 static int
12232 rs6000_ra_ever_killed (void)
12234 rtx top;
12235 rtx reg;
12236 rtx insn;
12238 if (current_function_is_thunk)
12239 return 0;
12241 /* regs_ever_live has LR marked as used if any sibcalls are present,
12242 but this should not force saving and restoring in the
12243 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
12244 clobbers LR, so that is inappropriate. */
12246 /* Also, the prologue can generate a store into LR that
12247 doesn't really count, like this:
12249 move LR->R0
12250 bcl to set PIC register
12251 move LR->R31
12252 move R0->LR
12254 When we're called from the epilogue, we need to avoid counting
12255 this as a store. */
12257 push_topmost_sequence ();
12258 top = get_insns ();
12259 pop_topmost_sequence ();
12260 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
12262 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
12264 if (INSN_P (insn))
12266 if (FIND_REG_INC_NOTE (insn, reg))
12267 return 1;
12268 else if (GET_CODE (insn) == CALL_INSN
12269 && !SIBLING_CALL_P (insn))
12270 return 1;
12271 else if (set_of (reg, insn) != NULL_RTX
12272 && !prologue_epilogue_contains (insn))
12273 return 1;
12276 return 0;
12279 /* Add a REG_MAYBE_DEAD note to the insn. */
12280 static void
12281 rs6000_maybe_dead (rtx insn)
12283 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
12284 const0_rtx,
12285 REG_NOTES (insn));
12288 /* Emit instructions needed to load the TOC register.
12289 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
12290 a constant pool; or for SVR4 -fpic. */
12292 void
12293 rs6000_emit_load_toc_table (int fromprolog)
12295 rtx dest, insn;
12296 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
12298 if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
12300 rtx temp = (fromprolog
12301 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12302 : gen_reg_rtx (Pmode));
12303 insn = emit_insn (gen_load_toc_v4_pic_si (temp));
12304 if (fromprolog)
12305 rs6000_maybe_dead (insn);
12306 insn = emit_move_insn (dest, temp);
12307 if (fromprolog)
12308 rs6000_maybe_dead (insn);
12310 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
12312 char buf[30];
12313 rtx tempLR = (fromprolog
12314 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12315 : gen_reg_rtx (Pmode));
12316 rtx temp0 = (fromprolog
12317 ? gen_rtx_REG (Pmode, 0)
12318 : gen_reg_rtx (Pmode));
12319 rtx symF;
12321 /* possibly create the toc section */
12322 if (! toc_initialized)
12324 toc_section ();
12325 function_section (current_function_decl);
12328 if (fromprolog)
12330 rtx symL;
12332 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
12333 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12335 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
12336 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12338 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
12339 symF)));
12340 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
12341 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
12342 symL,
12343 symF)));
12345 else
12347 rtx tocsym;
12348 static int reload_toc_labelno = 0;
12350 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
12352 ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
12353 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12355 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym));
12356 emit_move_insn (dest, tempLR);
12357 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
12359 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
12360 if (fromprolog)
12361 rs6000_maybe_dead (insn);
12363 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
12365 /* This is for AIX code running in non-PIC ELF32. */
12366 char buf[30];
12367 rtx realsym;
12368 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
12369 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12371 insn = emit_insn (gen_elf_high (dest, realsym));
12372 if (fromprolog)
12373 rs6000_maybe_dead (insn);
12374 insn = emit_insn (gen_elf_low (dest, dest, realsym));
12375 if (fromprolog)
12376 rs6000_maybe_dead (insn);
12378 else if (DEFAULT_ABI == ABI_AIX)
12380 if (TARGET_32BIT)
12381 insn = emit_insn (gen_load_toc_aix_si (dest));
12382 else
12383 insn = emit_insn (gen_load_toc_aix_di (dest));
12384 if (fromprolog)
12385 rs6000_maybe_dead (insn);
12387 else
12388 abort ();
12391 /* Emit instructions to restore the link register after determining where
12392 its value has been stored. */
12394 void
12395 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
12397 rs6000_stack_t *info = rs6000_stack_info ();
12398 rtx operands[2];
12400 operands[0] = source;
12401 operands[1] = scratch;
12403 if (info->lr_save_p)
12405 rtx frame_rtx = stack_pointer_rtx;
12406 HOST_WIDE_INT sp_offset = 0;
12407 rtx tmp;
12409 if (frame_pointer_needed
12410 || current_function_calls_alloca
12411 || info->total_size > 32767)
12413 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
12414 frame_rtx = operands[1];
12416 else if (info->push_p)
12417 sp_offset = info->total_size;
12419 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
12420 tmp = gen_rtx_MEM (Pmode, tmp);
12421 emit_move_insn (tmp, operands[0]);
12423 else
12424 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
12427 static GTY(()) int set = -1;
12430 get_TOC_alias_set (void)
12432 if (set == -1)
12433 set = new_alias_set ();
12434 return set;
12437 /* This returns nonzero if the current function uses the TOC. This is
12438 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
12439 is generated by the ABI_V4 load_toc_* patterns. */
12440 #if TARGET_ELF
12441 static int
12442 uses_TOC (void)
12444 rtx insn;
12446 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12447 if (INSN_P (insn))
12449 rtx pat = PATTERN (insn);
12450 int i;
12452 if (GET_CODE (pat) == PARALLEL)
12453 for (i = 0; i < XVECLEN (pat, 0); i++)
12455 rtx sub = XVECEXP (pat, 0, i);
12456 if (GET_CODE (sub) == USE)
12458 sub = XEXP (sub, 0);
12459 if (GET_CODE (sub) == UNSPEC
12460 && XINT (sub, 1) == UNSPEC_TOC)
12461 return 1;
12465 return 0;
12467 #endif
12470 create_TOC_reference (rtx symbol)
12472 return gen_rtx_PLUS (Pmode,
12473 gen_rtx_REG (Pmode, TOC_REGISTER),
12474 gen_rtx_CONST (Pmode,
12475 gen_rtx_MINUS (Pmode, symbol,
12476 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
12479 /* If _Unwind_* has been called from within the same module,
12480 toc register is not guaranteed to be saved to 40(1) on function
12481 entry. Save it there in that case. */
12483 void
12484 rs6000_aix_emit_builtin_unwind_init (void)
12486 rtx mem;
12487 rtx stack_top = gen_reg_rtx (Pmode);
12488 rtx opcode_addr = gen_reg_rtx (Pmode);
12489 rtx opcode = gen_reg_rtx (SImode);
12490 rtx tocompare = gen_reg_rtx (SImode);
12491 rtx no_toc_save_needed = gen_label_rtx ();
12493 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
12494 emit_move_insn (stack_top, mem);
12496 mem = gen_rtx_MEM (Pmode,
12497 gen_rtx_PLUS (Pmode, stack_top,
12498 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
12499 emit_move_insn (opcode_addr, mem);
12500 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
12501 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
12502 : 0xE8410028, SImode));
12504 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
12505 SImode, NULL_RTX, NULL_RTX,
12506 no_toc_save_needed);
12508 mem = gen_rtx_MEM (Pmode,
12509 gen_rtx_PLUS (Pmode, stack_top,
12510 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
12511 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
12512 emit_label (no_toc_save_needed);
12515 /* This ties together stack memory (MEM with an alias set of
12516 rs6000_sr_alias_set) and the change to the stack pointer. */
12518 static void
12519 rs6000_emit_stack_tie (void)
12521 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
12523 set_mem_alias_set (mem, rs6000_sr_alias_set);
12524 emit_insn (gen_stack_tie (mem));
12527 /* Emit the correct code for allocating stack space, as insns.
12528 If COPY_R12, make sure a copy of the old frame is left in r12.
12529 The generated code may use hard register 0 as a temporary. */
12531 static void
12532 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
12534 rtx insn;
12535 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
12536 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
12537 rtx todec = GEN_INT (-size);
12539 if (current_function_limit_stack)
12541 if (REG_P (stack_limit_rtx)
12542 && REGNO (stack_limit_rtx) > 1
12543 && REGNO (stack_limit_rtx) <= 31)
12545 emit_insn (TARGET_32BIT
12546 ? gen_addsi3 (tmp_reg,
12547 stack_limit_rtx,
12548 GEN_INT (size))
12549 : gen_adddi3 (tmp_reg,
12550 stack_limit_rtx,
12551 GEN_INT (size)));
12553 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
12554 const0_rtx));
12556 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
12557 && TARGET_32BIT
12558 && DEFAULT_ABI == ABI_V4)
12560 rtx toload = gen_rtx_CONST (VOIDmode,
12561 gen_rtx_PLUS (Pmode,
12562 stack_limit_rtx,
12563 GEN_INT (size)));
12565 emit_insn (gen_elf_high (tmp_reg, toload));
12566 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
12567 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
12568 const0_rtx));
12570 else
12571 warning ("stack limit expression is not supported");
12574 if (copy_r12 || ! TARGET_UPDATE)
12575 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
12577 if (TARGET_UPDATE)
12579 if (size > 32767)
12581 /* Need a note here so that try_split doesn't get confused. */
12582 if (get_last_insn() == NULL_RTX)
12583 emit_note (NOTE_INSN_DELETED);
12584 insn = emit_move_insn (tmp_reg, todec);
12585 try_split (PATTERN (insn), insn, 0);
12586 todec = tmp_reg;
12589 insn = emit_insn (TARGET_32BIT
12590 ? gen_movsi_update (stack_reg, stack_reg,
12591 todec, stack_reg)
12592 : gen_movdi_update (stack_reg, stack_reg,
12593 todec, stack_reg));
12595 else
12597 insn = emit_insn (TARGET_32BIT
12598 ? gen_addsi3 (stack_reg, stack_reg, todec)
12599 : gen_adddi3 (stack_reg, stack_reg, todec));
12600 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
12601 gen_rtx_REG (Pmode, 12));
12604 RTX_FRAME_RELATED_P (insn) = 1;
12605 REG_NOTES (insn) =
12606 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12607 gen_rtx_SET (VOIDmode, stack_reg,
12608 gen_rtx_PLUS (Pmode, stack_reg,
12609 GEN_INT (-size))),
12610 REG_NOTES (insn));
12613 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
12614 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
12615 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
12616 deduce these equivalences by itself so it wasn't necessary to hold
12617 its hand so much. */
12619 static void
12620 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
12621 rtx reg2, rtx rreg)
12623 rtx real, temp;
12625 /* copy_rtx will not make unique copies of registers, so we need to
12626 ensure we don't have unwanted sharing here. */
12627 if (reg == reg2)
12628 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
12630 if (reg == rreg)
12631 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
12633 real = copy_rtx (PATTERN (insn));
12635 if (reg2 != NULL_RTX)
12636 real = replace_rtx (real, reg2, rreg);
12638 real = replace_rtx (real, reg,
12639 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
12640 STACK_POINTER_REGNUM),
12641 GEN_INT (val)));
12643 /* We expect that 'real' is either a SET or a PARALLEL containing
12644 SETs (and possibly other stuff). In a PARALLEL, all the SETs
12645 are important so they all have to be marked RTX_FRAME_RELATED_P. */
12647 if (GET_CODE (real) == SET)
12649 rtx set = real;
12651 temp = simplify_rtx (SET_SRC (set));
12652 if (temp)
12653 SET_SRC (set) = temp;
12654 temp = simplify_rtx (SET_DEST (set));
12655 if (temp)
12656 SET_DEST (set) = temp;
12657 if (GET_CODE (SET_DEST (set)) == MEM)
12659 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
12660 if (temp)
12661 XEXP (SET_DEST (set), 0) = temp;
12664 else if (GET_CODE (real) == PARALLEL)
12666 int i;
12667 for (i = 0; i < XVECLEN (real, 0); i++)
12668 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
12670 rtx set = XVECEXP (real, 0, i);
12672 temp = simplify_rtx (SET_SRC (set));
12673 if (temp)
12674 SET_SRC (set) = temp;
12675 temp = simplify_rtx (SET_DEST (set));
12676 if (temp)
12677 SET_DEST (set) = temp;
12678 if (GET_CODE (SET_DEST (set)) == MEM)
12680 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
12681 if (temp)
12682 XEXP (SET_DEST (set), 0) = temp;
12684 RTX_FRAME_RELATED_P (set) = 1;
12687 else
12688 abort ();
12690 if (TARGET_SPE)
12691 real = spe_synthesize_frame_save (real);
12693 RTX_FRAME_RELATED_P (insn) = 1;
12694 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12695 real,
12696 REG_NOTES (insn));
12699 /* Given an SPE frame note, return a PARALLEL of SETs with the
12700 original note, plus a synthetic register save. */
12702 static rtx
12703 spe_synthesize_frame_save (rtx real)
12705 rtx synth, offset, reg, real2;
12707 if (GET_CODE (real) != SET
12708 || GET_MODE (SET_SRC (real)) != V2SImode)
12709 return real;
12711 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
12712 frame related note. The parallel contains a set of the register
12713 being saved, and another set to a synthetic register (n+1200).
12714 This is so we can differentiate between 64-bit and 32-bit saves.
12715 Words cannot describe this nastiness. */
12717 if (GET_CODE (SET_DEST (real)) != MEM
12718 || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS
12719 || GET_CODE (SET_SRC (real)) != REG)
12720 abort ();
12722 /* Transform:
12723 (set (mem (plus (reg x) (const y)))
12724 (reg z))
12725 into:
12726 (set (mem (plus (reg x) (const y+4)))
12727 (reg z+1200))
12730 real2 = copy_rtx (real);
12731 PUT_MODE (SET_DEST (real2), SImode);
12732 reg = SET_SRC (real2);
12733 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
12734 synth = copy_rtx (real2);
12736 if (BYTES_BIG_ENDIAN)
12738 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
12739 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
12742 reg = SET_SRC (synth);
12744 synth = replace_rtx (synth, reg,
12745 gen_rtx_REG (SImode, REGNO (reg) + 1200));
12747 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
12748 synth = replace_rtx (synth, offset,
12749 GEN_INT (INTVAL (offset)
12750 + (BYTES_BIG_ENDIAN ? 0 : 4)));
12752 RTX_FRAME_RELATED_P (synth) = 1;
12753 RTX_FRAME_RELATED_P (real2) = 1;
12754 if (BYTES_BIG_ENDIAN)
12755 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
12756 else
12757 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
12759 return real;
12762 /* Returns an insn that has a vrsave set operation with the
12763 appropriate CLOBBERs. */
12765 static rtx
12766 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
12768 int nclobs, i;
12769 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
12770 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
12772 clobs[0]
12773 = gen_rtx_SET (VOIDmode,
12774 vrsave,
12775 gen_rtx_UNSPEC_VOLATILE (SImode,
12776 gen_rtvec (2, reg, vrsave),
12777 30));
12779 nclobs = 1;
12781 /* We need to clobber the registers in the mask so the scheduler
12782 does not move sets to VRSAVE before sets of AltiVec registers.
12784 However, if the function receives nonlocal gotos, reload will set
12785 all call saved registers live. We will end up with:
12787 (set (reg 999) (mem))
12788 (parallel [ (set (reg vrsave) (unspec blah))
12789 (clobber (reg 999))])
12791 The clobber will cause the store into reg 999 to be dead, and
12792 flow will attempt to delete an epilogue insn. In this case, we
12793 need an unspec use/set of the register. */
12795 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12796 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
12798 if (!epiloguep || call_used_regs [i])
12799 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
12800 gen_rtx_REG (V4SImode, i));
12801 else
12803 rtx reg = gen_rtx_REG (V4SImode, i);
12805 clobs[nclobs++]
12806 = gen_rtx_SET (VOIDmode,
12807 reg,
12808 gen_rtx_UNSPEC (V4SImode,
12809 gen_rtvec (1, reg), 27));
12813 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
12815 for (i = 0; i < nclobs; ++i)
12816 XVECEXP (insn, 0, i) = clobs[i];
12818 return insn;
12821 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
12822 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
12824 static void
12825 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
12826 unsigned int regno, int offset, HOST_WIDE_INT total_size)
12828 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
12829 rtx replacea, replaceb;
12831 int_rtx = GEN_INT (offset);
12833 /* Some cases that need register indexed addressing. */
12834 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
12835 || (TARGET_SPE_ABI
12836 && SPE_VECTOR_MODE (mode)
12837 && !SPE_CONST_OFFSET_OK (offset)))
12839 /* Whomever calls us must make sure r11 is available in the
12840 flow path of instructions in the prologue. */
12841 offset_rtx = gen_rtx_REG (Pmode, 11);
12842 emit_move_insn (offset_rtx, int_rtx);
12844 replacea = offset_rtx;
12845 replaceb = int_rtx;
12847 else
12849 offset_rtx = int_rtx;
12850 replacea = NULL_RTX;
12851 replaceb = NULL_RTX;
12854 reg = gen_rtx_REG (mode, regno);
12855 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
12856 mem = gen_rtx_MEM (mode, addr);
12857 set_mem_alias_set (mem, rs6000_sr_alias_set);
12859 insn = emit_move_insn (mem, reg);
12861 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
12864 /* Emit an offset memory reference suitable for a frame store, while
12865 converting to a valid addressing mode. */
12867 static rtx
12868 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
12870 rtx int_rtx, offset_rtx;
12872 int_rtx = GEN_INT (offset);
12874 if (TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
12876 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12877 emit_move_insn (offset_rtx, int_rtx);
12879 else
12880 offset_rtx = int_rtx;
12882 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
12885 #ifndef TARGET_FIX_AND_CONTINUE
12886 #define TARGET_FIX_AND_CONTINUE 0
12887 #endif
12889 /* Emit function prologue as insns. */
12891 void
12892 rs6000_emit_prologue (void)
12894 rs6000_stack_t *info = rs6000_stack_info ();
12895 enum machine_mode reg_mode = Pmode;
12896 int reg_size = TARGET_32BIT ? 4 : 8;
12897 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
12898 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
12899 rtx frame_reg_rtx = sp_reg_rtx;
12900 rtx cr_save_rtx = NULL_RTX;
12901 rtx insn;
12902 int saving_FPRs_inline;
12903 int using_store_multiple;
12904 HOST_WIDE_INT sp_offset = 0;
12906 if (TARGET_FIX_AND_CONTINUE)
12908 /* gdb on darwin arranges to forward a function from the old
12909 address by modifying the first 4 instructions of the function
12910 to branch to the overriding function. This is necessary to
12911 permit function pointers that point to the old function to
12912 actually forward to the new function. */
12913 emit_insn (gen_nop ());
12914 emit_insn (gen_nop ());
12915 emit_insn (gen_nop ());
12916 emit_insn (gen_nop ());
12919 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12921 reg_mode = V2SImode;
12922 reg_size = 8;
12925 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
12926 && (!TARGET_SPE_ABI
12927 || info->spe_64bit_regs_used == 0)
12928 && info->first_gp_reg_save < 31);
12929 saving_FPRs_inline = (info->first_fp_reg_save == 64
12930 || FP_SAVE_INLINE (info->first_fp_reg_save)
12931 || current_function_calls_eh_return
12932 || cfun->machine->ra_need_lr);
12934 /* For V.4, update stack before we do any saving and set back pointer. */
12935 if (info->push_p
12936 && (DEFAULT_ABI == ABI_V4
12937 || current_function_calls_eh_return))
12939 if (info->total_size < 32767)
12940 sp_offset = info->total_size;
12941 else
12942 frame_reg_rtx = frame_ptr_rtx;
12943 rs6000_emit_allocate_stack (info->total_size,
12944 (frame_reg_rtx != sp_reg_rtx
12945 && (info->cr_save_p
12946 || info->lr_save_p
12947 || info->first_fp_reg_save < 64
12948 || info->first_gp_reg_save < 32
12949 )));
12950 if (frame_reg_rtx != sp_reg_rtx)
12951 rs6000_emit_stack_tie ();
12954 /* Handle world saves specially here. */
12955 if (info->world_save_p)
12957 int i, j, sz;
12958 rtx treg;
12959 rtvec p;
12961 /* save_world expects lr in r0. */
12962 if (info->lr_save_p)
12964 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
12965 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
12966 RTX_FRAME_RELATED_P (insn) = 1;
12969 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
12970 assumptions about the offsets of various bits of the stack
12971 frame. Abort if things aren't what they should be. */
12972 if (info->gp_save_offset != -220
12973 || info->fp_save_offset != -144
12974 || info->lr_save_offset != 8
12975 || info->cr_save_offset != 4
12976 || !info->push_p
12977 || !info->lr_save_p
12978 || (current_function_calls_eh_return && info->ehrd_offset != -432)
12979 || (info->vrsave_save_offset != -224
12980 || info->altivec_save_offset != (-224 -16 -192)))
12981 abort ();
12983 treg = gen_rtx_REG (SImode, 11);
12984 emit_move_insn (treg, GEN_INT (-info->total_size));
12986 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
12987 in R11. It also clobbers R12, so beware! */
12989 /* Preserve CR2 for save_world prologues */
12990 sz = 6;
12991 sz += 32 - info->first_gp_reg_save;
12992 sz += 64 - info->first_fp_reg_save;
12993 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
12994 p = rtvec_alloc (sz);
12995 j = 0;
12996 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
12997 gen_rtx_REG (Pmode,
12998 LINK_REGISTER_REGNUM));
12999 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
13000 gen_rtx_SYMBOL_REF (Pmode,
13001 "*save_world"));
13002 /* We do floats first so that the instruction pattern matches
13003 properly. */
13004 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13006 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13007 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13008 GEN_INT (info->fp_save_offset
13009 + sp_offset + 8 * i));
13010 rtx mem = gen_rtx_MEM (DFmode, addr);
13011 set_mem_alias_set (mem, rs6000_sr_alias_set);
13013 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13015 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
13017 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
13018 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13019 GEN_INT (info->altivec_save_offset
13020 + sp_offset + 16 * i));
13021 rtx mem = gen_rtx_MEM (V4SImode, addr);
13022 set_mem_alias_set (mem, rs6000_sr_alias_set);
13024 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13026 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13028 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13029 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13030 GEN_INT (info->gp_save_offset
13031 + sp_offset + reg_size * i));
13032 rtx mem = gen_rtx_MEM (reg_mode, addr);
13033 set_mem_alias_set (mem, rs6000_sr_alias_set);
13035 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13039 /* CR register traditionally saved as CR2. */
13040 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
13041 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13042 GEN_INT (info->cr_save_offset
13043 + sp_offset));
13044 rtx mem = gen_rtx_MEM (reg_mode, addr);
13045 set_mem_alias_set (mem, rs6000_sr_alias_set);
13047 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13049 /* Prevent any attempt to delete the setting of r0 and treg! */
13050 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
13051 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
13052 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
13054 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13055 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13056 NULL_RTX, NULL_RTX);
13058 if (current_function_calls_eh_return)
13060 unsigned int i;
13061 for (i = 0; ; ++i)
13063 unsigned int regno = EH_RETURN_DATA_REGNO (i);
13064 if (regno == INVALID_REGNUM)
13065 break;
13066 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
13067 info->ehrd_offset + sp_offset
13068 + reg_size * (int) i,
13069 info->total_size);
13074 /* Save AltiVec registers if needed. */
13075 if (! info->world_save_p && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
13077 int i;
13079 /* There should be a non inline version of this, for when we
13080 are saving lots of vector registers. */
13081 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
13082 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13084 rtx areg, savereg, mem;
13085 int offset;
13087 offset = info->altivec_save_offset + sp_offset
13088 + 16 * (i - info->first_altivec_reg_save);
13090 savereg = gen_rtx_REG (V4SImode, i);
13092 areg = gen_rtx_REG (Pmode, 0);
13093 emit_move_insn (areg, GEN_INT (offset));
13095 /* AltiVec addressing mode is [reg+reg]. */
13096 mem = gen_rtx_MEM (V4SImode,
13097 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
13099 set_mem_alias_set (mem, rs6000_sr_alias_set);
13101 insn = emit_move_insn (mem, savereg);
13103 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13104 areg, GEN_INT (offset));
13108 /* VRSAVE is a bit vector representing which AltiVec registers
13109 are used. The OS uses this to determine which vector
13110 registers to save on a context switch. We need to save
13111 VRSAVE on the stack frame, add whatever AltiVec registers we
13112 used in this function, and do the corresponding magic in the
13113 epilogue. */
13115 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
13116 && ! info->world_save_p && info->vrsave_mask != 0)
13118 rtx reg, mem, vrsave;
13119 int offset;
13121 /* Get VRSAVE onto a GPR. */
13122 reg = gen_rtx_REG (SImode, 12);
13123 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
13124 if (TARGET_MACHO)
13125 emit_insn (gen_get_vrsave_internal (reg));
13126 else
13127 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
13129 /* Save VRSAVE. */
13130 offset = info->vrsave_save_offset + sp_offset;
13132 = gen_rtx_MEM (SImode,
13133 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
13134 set_mem_alias_set (mem, rs6000_sr_alias_set);
13135 insn = emit_move_insn (mem, reg);
13137 /* Include the registers in the mask. */
13138 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
13140 insn = emit_insn (generate_set_vrsave (reg, info, 0));
13143 /* If we use the link register, get it into r0. */
13144 if (! info->world_save_p && info->lr_save_p)
13146 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
13147 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
13148 RTX_FRAME_RELATED_P (insn) = 1;
13151 /* If we need to save CR, put it into r12. */
13152 if (! info->world_save_p && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
13154 rtx set;
13156 cr_save_rtx = gen_rtx_REG (SImode, 12);
13157 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
13158 RTX_FRAME_RELATED_P (insn) = 1;
13159 /* Now, there's no way that dwarf2out_frame_debug_expr is going
13160 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
13161 But that's OK. All we have to do is specify that _one_ condition
13162 code register is saved in this stack slot. The thrower's epilogue
13163 will then restore all the call-saved registers.
13164 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
13165 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
13166 gen_rtx_REG (SImode, CR2_REGNO));
13167 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13168 set,
13169 REG_NOTES (insn));
13172 /* Do any required saving of fpr's. If only one or two to save, do
13173 it ourselves. Otherwise, call function. */
13174 if (! info->world_save_p && saving_FPRs_inline)
13176 int i;
13177 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13178 if ((regs_ever_live[info->first_fp_reg_save+i]
13179 && ! call_used_regs[info->first_fp_reg_save+i]))
13180 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
13181 info->first_fp_reg_save + i,
13182 info->fp_save_offset + sp_offset + 8 * i,
13183 info->total_size);
13185 else if (! info->world_save_p && info->first_fp_reg_save != 64)
13187 int i;
13188 char rname[30];
13189 const char *alloc_rname;
13190 rtvec p;
13191 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
13193 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
13194 gen_rtx_REG (Pmode,
13195 LINK_REGISTER_REGNUM));
13196 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
13197 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
13198 alloc_rname = ggc_strdup (rname);
13199 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
13200 gen_rtx_SYMBOL_REF (Pmode,
13201 alloc_rname));
13202 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13204 rtx addr, reg, mem;
13205 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13206 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13207 GEN_INT (info->fp_save_offset
13208 + sp_offset + 8*i));
13209 mem = gen_rtx_MEM (DFmode, addr);
13210 set_mem_alias_set (mem, rs6000_sr_alias_set);
13212 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
13214 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13215 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13216 NULL_RTX, NULL_RTX);
13219 /* Save GPRs. This is done as a PARALLEL if we are using
13220 the store-multiple instructions. */
13221 if (! info->world_save_p && using_store_multiple)
13223 rtvec p;
13224 int i;
13225 p = rtvec_alloc (32 - info->first_gp_reg_save);
13226 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13228 rtx addr, reg, mem;
13229 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13230 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13231 GEN_INT (info->gp_save_offset
13232 + sp_offset
13233 + reg_size * i));
13234 mem = gen_rtx_MEM (reg_mode, addr);
13235 set_mem_alias_set (mem, rs6000_sr_alias_set);
13237 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
13239 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13240 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13241 NULL_RTX, NULL_RTX);
13243 else if (! info->world_save_p)
13245 int i;
13246 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13247 if ((regs_ever_live[info->first_gp_reg_save+i]
13248 && (! call_used_regs[info->first_gp_reg_save+i]
13249 || (i+info->first_gp_reg_save
13250 == RS6000_PIC_OFFSET_TABLE_REGNUM
13251 && TARGET_TOC && TARGET_MINIMAL_TOC)))
13252 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
13253 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
13254 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
13256 rtx addr, reg, mem;
13257 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13259 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13261 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
13262 rtx b;
13264 if (!SPE_CONST_OFFSET_OK (offset))
13266 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13267 emit_move_insn (b, GEN_INT (offset));
13269 else
13270 b = GEN_INT (offset);
13272 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
13273 mem = gen_rtx_MEM (V2SImode, addr);
13274 set_mem_alias_set (mem, rs6000_sr_alias_set);
13275 insn = emit_move_insn (mem, reg);
13277 if (GET_CODE (b) == CONST_INT)
13278 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13279 NULL_RTX, NULL_RTX);
13280 else
13281 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13282 b, GEN_INT (offset));
13284 else
13286 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13287 GEN_INT (info->gp_save_offset
13288 + sp_offset
13289 + reg_size * i));
13290 mem = gen_rtx_MEM (reg_mode, addr);
13291 set_mem_alias_set (mem, rs6000_sr_alias_set);
13293 insn = emit_move_insn (mem, reg);
13294 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13295 NULL_RTX, NULL_RTX);
13300 /* ??? There's no need to emit actual instructions here, but it's the
13301 easiest way to get the frame unwind information emitted. */
13302 if (! info->world_save_p && current_function_calls_eh_return)
13304 unsigned int i, regno;
13306 /* In AIX ABI we need to pretend we save r2 here. */
13307 if (TARGET_AIX)
13309 rtx addr, reg, mem;
13311 reg = gen_rtx_REG (reg_mode, 2);
13312 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13313 GEN_INT (sp_offset + 5 * reg_size));
13314 mem = gen_rtx_MEM (reg_mode, addr);
13315 set_mem_alias_set (mem, rs6000_sr_alias_set);
13317 insn = emit_move_insn (mem, reg);
13318 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13319 NULL_RTX, NULL_RTX);
13320 PATTERN (insn) = gen_blockage ();
13323 for (i = 0; ; ++i)
13325 regno = EH_RETURN_DATA_REGNO (i);
13326 if (regno == INVALID_REGNUM)
13327 break;
13329 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
13330 info->ehrd_offset + sp_offset
13331 + reg_size * (int) i,
13332 info->total_size);
13336 /* Save lr if we used it. */
13337 if (! info->world_save_p && info->lr_save_p)
13339 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13340 GEN_INT (info->lr_save_offset + sp_offset));
13341 rtx reg = gen_rtx_REG (Pmode, 0);
13342 rtx mem = gen_rtx_MEM (Pmode, addr);
13343 /* This should not be of rs6000_sr_alias_set, because of
13344 __builtin_return_address. */
13346 insn = emit_move_insn (mem, reg);
13347 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13348 NULL_RTX, NULL_RTX);
13351 /* Save CR if we use any that must be preserved. */
13352 if (! info->world_save_p && info->cr_save_p)
13354 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13355 GEN_INT (info->cr_save_offset + sp_offset));
13356 rtx mem = gen_rtx_MEM (SImode, addr);
13357 /* See the large comment above about why CR2_REGNO is used. */
13358 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
13360 set_mem_alias_set (mem, rs6000_sr_alias_set);
13362 /* If r12 was used to hold the original sp, copy cr into r0 now
13363 that it's free. */
13364 if (REGNO (frame_reg_rtx) == 12)
13366 rtx set;
13368 cr_save_rtx = gen_rtx_REG (SImode, 0);
13369 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
13370 RTX_FRAME_RELATED_P (insn) = 1;
13371 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
13372 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13373 set,
13374 REG_NOTES (insn));
13377 insn = emit_move_insn (mem, cr_save_rtx);
13379 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13380 NULL_RTX, NULL_RTX);
13383 /* Update stack and set back pointer unless this is V.4,
13384 for which it was done previously. */
13385 if (! info->world_save_p && info->push_p
13386 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
13387 rs6000_emit_allocate_stack (info->total_size, FALSE);
13389 /* Set frame pointer, if needed. */
13390 if (frame_pointer_needed)
13392 insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
13393 sp_reg_rtx);
13394 RTX_FRAME_RELATED_P (insn) = 1;
13397 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
13398 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
13399 || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
13400 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
13402 /* If emit_load_toc_table will use the link register, we need to save
13403 it. We use R12 for this purpose because emit_load_toc_table
13404 can use register 0. This allows us to use a plain 'blr' to return
13405 from the procedure more often. */
13406 int save_LR_around_toc_setup = (TARGET_ELF
13407 && DEFAULT_ABI != ABI_AIX
13408 && flag_pic
13409 && ! info->lr_save_p
13410 && EXIT_BLOCK_PTR->pred != NULL);
13411 if (save_LR_around_toc_setup)
13413 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13415 insn = emit_move_insn (frame_ptr_rtx, lr);
13416 rs6000_maybe_dead (insn);
13417 RTX_FRAME_RELATED_P (insn) = 1;
13419 rs6000_emit_load_toc_table (TRUE);
13421 insn = emit_move_insn (lr, frame_ptr_rtx);
13422 rs6000_maybe_dead (insn);
13423 RTX_FRAME_RELATED_P (insn) = 1;
13425 else
13426 rs6000_emit_load_toc_table (TRUE);
13429 #if TARGET_MACHO
13430 if (DEFAULT_ABI == ABI_DARWIN
13431 && flag_pic && current_function_uses_pic_offset_table)
13433 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13434 rtx src = machopic_function_base_sym ();
13436 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
13438 insn = emit_move_insn (gen_rtx_REG (Pmode,
13439 RS6000_PIC_OFFSET_TABLE_REGNUM),
13440 lr);
13441 rs6000_maybe_dead (insn);
13443 #endif
13446 /* Write function prologue. */
13448 static void
13449 rs6000_output_function_prologue (FILE *file,
13450 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13452 rs6000_stack_t *info = rs6000_stack_info ();
13454 if (TARGET_DEBUG_STACK)
13455 debug_stack_info (info);
13457 /* Write .extern for any function we will call to save and restore
13458 fp values. */
13459 if (info->first_fp_reg_save < 64
13460 && !FP_SAVE_INLINE (info->first_fp_reg_save))
13461 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
13462 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
13463 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
13464 RESTORE_FP_SUFFIX);
13466 /* Write .extern for AIX common mode routines, if needed. */
13467 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
13469 fputs ("\t.extern __mulh\n", file);
13470 fputs ("\t.extern __mull\n", file);
13471 fputs ("\t.extern __divss\n", file);
13472 fputs ("\t.extern __divus\n", file);
13473 fputs ("\t.extern __quoss\n", file);
13474 fputs ("\t.extern __quous\n", file);
13475 common_mode_defined = 1;
13478 if (! HAVE_prologue)
13480 start_sequence ();
13482 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
13483 the "toplevel" insn chain. */
13484 emit_note (NOTE_INSN_DELETED);
13485 rs6000_emit_prologue ();
13486 emit_note (NOTE_INSN_DELETED);
13488 /* Expand INSN_ADDRESSES so final() doesn't crash. */
13490 rtx insn;
13491 unsigned addr = 0;
13492 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
13494 INSN_ADDRESSES_NEW (insn, addr);
13495 addr += 4;
13499 if (TARGET_DEBUG_STACK)
13500 debug_rtx_list (get_insns (), 100);
13501 final (get_insns (), file, FALSE, FALSE);
13502 end_sequence ();
13505 rs6000_pic_labelno++;
13508 /* Emit function epilogue as insns.
13510 At present, dwarf2out_frame_debug_expr doesn't understand
13511 register restores, so we don't bother setting RTX_FRAME_RELATED_P
13512 anywhere in the epilogue. Most of the insns below would in any case
13513 need special notes to explain where r11 is in relation to the stack. */
13515 void
13516 rs6000_emit_epilogue (int sibcall)
13518 rs6000_stack_t *info;
13519 int restoring_FPRs_inline;
13520 int using_load_multiple;
13521 int using_mfcr_multiple;
13522 int use_backchain_to_restore_sp;
13523 int sp_offset = 0;
13524 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
13525 rtx frame_reg_rtx = sp_reg_rtx;
13526 enum machine_mode reg_mode = Pmode;
13527 int reg_size = TARGET_32BIT ? 4 : 8;
13528 int i;
13530 info = rs6000_stack_info ();
13532 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13534 reg_mode = V2SImode;
13535 reg_size = 8;
13538 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
13539 && (!TARGET_SPE_ABI
13540 || info->spe_64bit_regs_used == 0)
13541 && info->first_gp_reg_save < 31);
13542 restoring_FPRs_inline = (sibcall
13543 || current_function_calls_eh_return
13544 || info->first_fp_reg_save == 64
13545 || FP_SAVE_INLINE (info->first_fp_reg_save));
13546 use_backchain_to_restore_sp = (frame_pointer_needed
13547 || current_function_calls_alloca
13548 || info->total_size > 32767);
13549 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
13550 || rs6000_cpu == PROCESSOR_PPC603
13551 || rs6000_cpu == PROCESSOR_PPC750
13552 || optimize_size);
13554 if (info->world_save_p)
13556 int i, j;
13557 char rname[30];
13558 const char *alloc_rname;
13559 rtvec p;
13561 /* eh_rest_world_r10 will return to the location saved in the LR
13562 stack slot (which is not likely to be our caller.)
13563 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
13564 rest_world is similar, except any R10 parameter is ignored.
13565 The exception-handling stuff that was here in 2.95 is no
13566 longer necessary. */
13568 p = rtvec_alloc (9
13570 + 32 - info->first_gp_reg_save
13571 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
13572 + 63 + 1 - info->first_fp_reg_save);
13574 strcpy (rname, (current_function_calls_eh_return) ?
13575 "*eh_rest_world_r10" : "*rest_world");
13576 alloc_rname = ggc_strdup (rname);
13578 j = 0;
13579 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
13580 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
13581 gen_rtx_REG (Pmode,
13582 LINK_REGISTER_REGNUM));
13583 RTVEC_ELT (p, j++)
13584 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
13585 /* The instruction pattern requires a clobber here;
13586 it is shared with the restVEC helper. */
13587 RTVEC_ELT (p, j++)
13588 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
13591 /* CR register traditionally saved as CR2. */
13592 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
13593 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13594 GEN_INT (info->cr_save_offset));
13595 rtx mem = gen_rtx_MEM (reg_mode, addr);
13596 set_mem_alias_set (mem, rs6000_sr_alias_set);
13598 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13601 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13603 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13604 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13605 GEN_INT (info->gp_save_offset
13606 + reg_size * i));
13607 rtx mem = gen_rtx_MEM (reg_mode, addr);
13608 set_mem_alias_set (mem, rs6000_sr_alias_set);
13610 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13612 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
13614 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
13615 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13616 GEN_INT (info->altivec_save_offset
13617 + 16 * i));
13618 rtx mem = gen_rtx_MEM (V4SImode, addr);
13619 set_mem_alias_set (mem, rs6000_sr_alias_set);
13621 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13623 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
13625 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13626 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13627 GEN_INT (info->fp_save_offset
13628 + 8 * i));
13629 rtx mem = gen_rtx_MEM (DFmode, addr);
13630 set_mem_alias_set (mem, rs6000_sr_alias_set);
13632 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13634 RTVEC_ELT (p, j++)
13635 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
13636 RTVEC_ELT (p, j++)
13637 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
13638 RTVEC_ELT (p, j++)
13639 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
13640 RTVEC_ELT (p, j++)
13641 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
13642 RTVEC_ELT (p, j++)
13643 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
13644 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
13646 return;
13649 /* If we have a frame pointer, a call to alloca, or a large stack
13650 frame, restore the old stack pointer using the backchain. Otherwise,
13651 we know what size to update it with. */
13652 if (use_backchain_to_restore_sp)
13654 /* Under V.4, don't reset the stack pointer until after we're done
13655 loading the saved registers. */
13656 if (DEFAULT_ABI == ABI_V4)
13657 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
13659 emit_move_insn (frame_reg_rtx,
13660 gen_rtx_MEM (Pmode, sp_reg_rtx));
13663 else if (info->push_p)
13665 if (DEFAULT_ABI == ABI_V4
13666 || current_function_calls_eh_return)
13667 sp_offset = info->total_size;
13668 else
13670 emit_insn (TARGET_32BIT
13671 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
13672 GEN_INT (info->total_size))
13673 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
13674 GEN_INT (info->total_size)));
13678 /* Restore AltiVec registers if needed. */
13679 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
13681 int i;
13683 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
13684 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13686 rtx addr, areg, mem;
13688 areg = gen_rtx_REG (Pmode, 0);
13689 emit_move_insn
13690 (areg, GEN_INT (info->altivec_save_offset
13691 + sp_offset
13692 + 16 * (i - info->first_altivec_reg_save)));
13694 /* AltiVec addressing mode is [reg+reg]. */
13695 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
13696 mem = gen_rtx_MEM (V4SImode, addr);
13697 set_mem_alias_set (mem, rs6000_sr_alias_set);
13699 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
13703 /* Restore VRSAVE if needed. */
13704 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
13705 && info->vrsave_mask != 0)
13707 rtx addr, mem, reg;
13709 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13710 GEN_INT (info->vrsave_save_offset + sp_offset));
13711 mem = gen_rtx_MEM (SImode, addr);
13712 set_mem_alias_set (mem, rs6000_sr_alias_set);
13713 reg = gen_rtx_REG (SImode, 12);
13714 emit_move_insn (reg, mem);
13716 emit_insn (generate_set_vrsave (reg, info, 1));
13719 /* Get the old lr if we saved it. */
13720 if (info->lr_save_p)
13722 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
13723 info->lr_save_offset + sp_offset);
13725 set_mem_alias_set (mem, rs6000_sr_alias_set);
13727 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
13730 /* Get the old cr if we saved it. */
13731 if (info->cr_save_p)
13733 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13734 GEN_INT (info->cr_save_offset + sp_offset));
13735 rtx mem = gen_rtx_MEM (SImode, addr);
13737 set_mem_alias_set (mem, rs6000_sr_alias_set);
13739 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
13742 /* Set LR here to try to overlap restores below. */
13743 if (info->lr_save_p)
13744 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
13745 gen_rtx_REG (Pmode, 0));
13747 /* Load exception handler data registers, if needed. */
13748 if (current_function_calls_eh_return)
13750 unsigned int i, regno;
13752 if (TARGET_AIX)
13754 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13755 GEN_INT (sp_offset + 5 * reg_size));
13756 rtx mem = gen_rtx_MEM (reg_mode, addr);
13758 set_mem_alias_set (mem, rs6000_sr_alias_set);
13760 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
13763 for (i = 0; ; ++i)
13765 rtx mem;
13767 regno = EH_RETURN_DATA_REGNO (i);
13768 if (regno == INVALID_REGNUM)
13769 break;
13771 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
13772 info->ehrd_offset + sp_offset
13773 + reg_size * (int) i);
13774 set_mem_alias_set (mem, rs6000_sr_alias_set);
13776 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
13780 /* Restore GPRs. This is done as a PARALLEL if we are using
13781 the load-multiple instructions. */
13782 if (using_load_multiple)
13784 rtvec p;
13785 p = rtvec_alloc (32 - info->first_gp_reg_save);
13786 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13788 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13789 GEN_INT (info->gp_save_offset
13790 + sp_offset
13791 + reg_size * i));
13792 rtx mem = gen_rtx_MEM (reg_mode, addr);
13794 set_mem_alias_set (mem, rs6000_sr_alias_set);
13796 RTVEC_ELT (p, i) =
13797 gen_rtx_SET (VOIDmode,
13798 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
13799 mem);
13801 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13803 else
13804 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13805 if ((regs_ever_live[info->first_gp_reg_save+i]
13806 && (! call_used_regs[info->first_gp_reg_save+i]
13807 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
13808 && TARGET_TOC && TARGET_MINIMAL_TOC)))
13809 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
13810 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
13811 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
13813 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13814 GEN_INT (info->gp_save_offset
13815 + sp_offset
13816 + reg_size * i));
13817 rtx mem = gen_rtx_MEM (reg_mode, addr);
13819 /* Restore 64-bit quantities for SPE. */
13820 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13822 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
13823 rtx b;
13825 if (!SPE_CONST_OFFSET_OK (offset))
13827 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13828 emit_move_insn (b, GEN_INT (offset));
13830 else
13831 b = GEN_INT (offset);
13833 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
13834 mem = gen_rtx_MEM (V2SImode, addr);
13837 set_mem_alias_set (mem, rs6000_sr_alias_set);
13839 emit_move_insn (gen_rtx_REG (reg_mode,
13840 info->first_gp_reg_save + i), mem);
13843 /* Restore fpr's if we need to do it without calling a function. */
13844 if (restoring_FPRs_inline)
13845 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13846 if ((regs_ever_live[info->first_fp_reg_save+i]
13847 && ! call_used_regs[info->first_fp_reg_save+i]))
13849 rtx addr, mem;
13850 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13851 GEN_INT (info->fp_save_offset
13852 + sp_offset
13853 + 8 * i));
13854 mem = gen_rtx_MEM (DFmode, addr);
13855 set_mem_alias_set (mem, rs6000_sr_alias_set);
13857 emit_move_insn (gen_rtx_REG (DFmode,
13858 info->first_fp_reg_save + i),
13859 mem);
13862 /* If we saved cr, restore it here. Just those that were used. */
13863 if (info->cr_save_p)
13865 rtx r12_rtx = gen_rtx_REG (SImode, 12);
13866 int count = 0;
13868 if (using_mfcr_multiple)
13870 for (i = 0; i < 8; i++)
13871 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
13872 count++;
13873 if (count == 0)
13874 abort ();
13877 if (using_mfcr_multiple && count > 1)
13879 rtvec p;
13880 int ndx;
13882 p = rtvec_alloc (count);
13884 ndx = 0;
13885 for (i = 0; i < 8; i++)
13886 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
13888 rtvec r = rtvec_alloc (2);
13889 RTVEC_ELT (r, 0) = r12_rtx;
13890 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
13891 RTVEC_ELT (p, ndx) =
13892 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
13893 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
13894 ndx++;
13896 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13897 if (ndx != count)
13898 abort ();
13900 else
13901 for (i = 0; i < 8; i++)
13902 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
13904 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
13905 CR0_REGNO+i),
13906 r12_rtx));
13910 /* If this is V.4, unwind the stack pointer after all of the loads
13911 have been done. We need to emit a block here so that sched
13912 doesn't decide to move the sp change before the register restores
13913 (which may not have any obvious dependency on the stack). This
13914 doesn't hurt performance, because there is no scheduling that can
13915 be done after this point. */
13916 if (DEFAULT_ABI == ABI_V4
13917 || current_function_calls_eh_return)
13919 if (frame_reg_rtx != sp_reg_rtx)
13920 rs6000_emit_stack_tie ();
13922 if (use_backchain_to_restore_sp)
13924 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
13926 else if (sp_offset != 0)
13928 emit_insn (TARGET_32BIT
13929 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
13930 GEN_INT (sp_offset))
13931 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
13932 GEN_INT (sp_offset)));
13936 if (current_function_calls_eh_return)
13938 rtx sa = EH_RETURN_STACKADJ_RTX;
13939 emit_insn (TARGET_32BIT
13940 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
13941 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
13944 if (!sibcall)
13946 rtvec p;
13947 if (! restoring_FPRs_inline)
13948 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
13949 else
13950 p = rtvec_alloc (2);
13952 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
13953 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
13954 gen_rtx_REG (Pmode,
13955 LINK_REGISTER_REGNUM));
13957 /* If we have to restore more than two FP registers, branch to the
13958 restore function. It will return to our caller. */
13959 if (! restoring_FPRs_inline)
13961 int i;
13962 char rname[30];
13963 const char *alloc_rname;
13965 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
13966 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
13967 alloc_rname = ggc_strdup (rname);
13968 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
13969 gen_rtx_SYMBOL_REF (Pmode,
13970 alloc_rname));
13972 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13974 rtx addr, mem;
13975 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
13976 GEN_INT (info->fp_save_offset + 8*i));
13977 mem = gen_rtx_MEM (DFmode, addr);
13978 set_mem_alias_set (mem, rs6000_sr_alias_set);
13980 RTVEC_ELT (p, i+3) =
13981 gen_rtx_SET (VOIDmode,
13982 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
13983 mem);
13987 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
13991 /* Write function epilogue. */
13993 static void
13994 rs6000_output_function_epilogue (FILE *file,
13995 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13997 rs6000_stack_t *info = rs6000_stack_info ();
13999 if (! HAVE_epilogue)
14001 rtx insn = get_last_insn ();
14002 /* If the last insn was a BARRIER, we don't have to write anything except
14003 the trace table. */
14004 if (GET_CODE (insn) == NOTE)
14005 insn = prev_nonnote_insn (insn);
14006 if (insn == 0 || GET_CODE (insn) != BARRIER)
14008 /* This is slightly ugly, but at least we don't have two
14009 copies of the epilogue-emitting code. */
14010 start_sequence ();
14012 /* A NOTE_INSN_DELETED is supposed to be at the start
14013 and end of the "toplevel" insn chain. */
14014 emit_note (NOTE_INSN_DELETED);
14015 rs6000_emit_epilogue (FALSE);
14016 emit_note (NOTE_INSN_DELETED);
14018 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14020 rtx insn;
14021 unsigned addr = 0;
14022 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14024 INSN_ADDRESSES_NEW (insn, addr);
14025 addr += 4;
14029 if (TARGET_DEBUG_STACK)
14030 debug_rtx_list (get_insns (), 100);
14031 final (get_insns (), file, FALSE, FALSE);
14032 end_sequence ();
14036 #if TARGET_MACHO
14037 macho_branch_islands ();
14038 /* Mach-O doesn't support labels at the end of objects, so if
14039 it looks like we might want one, insert a NOP. */
14041 rtx insn = get_last_insn ();
14042 while (insn
14043 && NOTE_P (insn)
14044 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
14045 insn = PREV_INSN (insn);
14046 if (insn
14047 && (LABEL_P (insn)
14048 || (NOTE_P (insn)
14049 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
14050 fputs ("\tnop\n", file);
14052 #endif
14054 /* Output a traceback table here. See /usr/include/sys/debug.h for info
14055 on its format.
14057 We don't output a traceback table if -finhibit-size-directive was
14058 used. The documentation for -finhibit-size-directive reads
14059 ``don't output a @code{.size} assembler directive, or anything
14060 else that would cause trouble if the function is split in the
14061 middle, and the two halves are placed at locations far apart in
14062 memory.'' The traceback table has this property, since it
14063 includes the offset from the start of the function to the
14064 traceback table itself.
14066 System V.4 Powerpc's (and the embedded ABI derived from it) use a
14067 different traceback table. */
14068 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
14069 && rs6000_traceback != traceback_none)
14071 const char *fname = NULL;
14072 const char *language_string = lang_hooks.name;
14073 int fixed_parms = 0, float_parms = 0, parm_info = 0;
14074 int i;
14075 int optional_tbtab;
14077 if (rs6000_traceback == traceback_full)
14078 optional_tbtab = 1;
14079 else if (rs6000_traceback == traceback_part)
14080 optional_tbtab = 0;
14081 else
14082 optional_tbtab = !optimize_size && !TARGET_ELF;
14084 if (optional_tbtab)
14086 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
14087 while (*fname == '.') /* V.4 encodes . in the name */
14088 fname++;
14090 /* Need label immediately before tbtab, so we can compute
14091 its offset from the function start. */
14092 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
14093 ASM_OUTPUT_LABEL (file, fname);
14096 /* The .tbtab pseudo-op can only be used for the first eight
14097 expressions, since it can't handle the possibly variable
14098 length fields that follow. However, if you omit the optional
14099 fields, the assembler outputs zeros for all optional fields
14100 anyways, giving each variable length field is minimum length
14101 (as defined in sys/debug.h). Thus we can not use the .tbtab
14102 pseudo-op at all. */
14104 /* An all-zero word flags the start of the tbtab, for debuggers
14105 that have to find it by searching forward from the entry
14106 point or from the current pc. */
14107 fputs ("\t.long 0\n", file);
14109 /* Tbtab format type. Use format type 0. */
14110 fputs ("\t.byte 0,", file);
14112 /* Language type. Unfortunately, there does not seem to be any
14113 official way to discover the language being compiled, so we
14114 use language_string.
14115 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
14116 Java is 13. Objective-C is 14. */
14117 if (! strcmp (language_string, "GNU C"))
14118 i = 0;
14119 else if (! strcmp (language_string, "GNU F77")
14120 || ! strcmp (language_string, "GNU F95"))
14121 i = 1;
14122 else if (! strcmp (language_string, "GNU Pascal"))
14123 i = 2;
14124 else if (! strcmp (language_string, "GNU Ada"))
14125 i = 3;
14126 else if (! strcmp (language_string, "GNU C++"))
14127 i = 9;
14128 else if (! strcmp (language_string, "GNU Java"))
14129 i = 13;
14130 else if (! strcmp (language_string, "GNU Objective-C"))
14131 i = 14;
14132 else
14133 abort ();
14134 fprintf (file, "%d,", i);
14136 /* 8 single bit fields: global linkage (not set for C extern linkage,
14137 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
14138 from start of procedure stored in tbtab, internal function, function
14139 has controlled storage, function has no toc, function uses fp,
14140 function logs/aborts fp operations. */
14141 /* Assume that fp operations are used if any fp reg must be saved. */
14142 fprintf (file, "%d,",
14143 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
14145 /* 6 bitfields: function is interrupt handler, name present in
14146 proc table, function calls alloca, on condition directives
14147 (controls stack walks, 3 bits), saves condition reg, saves
14148 link reg. */
14149 /* The `function calls alloca' bit seems to be set whenever reg 31 is
14150 set up as a frame pointer, even when there is no alloca call. */
14151 fprintf (file, "%d,",
14152 ((optional_tbtab << 6)
14153 | ((optional_tbtab & frame_pointer_needed) << 5)
14154 | (info->cr_save_p << 1)
14155 | (info->lr_save_p)));
14157 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
14158 (6 bits). */
14159 fprintf (file, "%d,",
14160 (info->push_p << 7) | (64 - info->first_fp_reg_save));
14162 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
14163 fprintf (file, "%d,", (32 - first_reg_to_save ()));
14165 if (optional_tbtab)
14167 /* Compute the parameter info from the function decl argument
14168 list. */
14169 tree decl;
14170 int next_parm_info_bit = 31;
14172 for (decl = DECL_ARGUMENTS (current_function_decl);
14173 decl; decl = TREE_CHAIN (decl))
14175 rtx parameter = DECL_INCOMING_RTL (decl);
14176 enum machine_mode mode = GET_MODE (parameter);
14178 if (GET_CODE (parameter) == REG)
14180 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
14182 int bits;
14184 float_parms++;
14186 if (mode == SFmode)
14187 bits = 0x2;
14188 else if (mode == DFmode || mode == TFmode)
14189 bits = 0x3;
14190 else
14191 abort ();
14193 /* If only one bit will fit, don't or in this entry. */
14194 if (next_parm_info_bit > 0)
14195 parm_info |= (bits << (next_parm_info_bit - 1));
14196 next_parm_info_bit -= 2;
14198 else
14200 fixed_parms += ((GET_MODE_SIZE (mode)
14201 + (UNITS_PER_WORD - 1))
14202 / UNITS_PER_WORD);
14203 next_parm_info_bit -= 1;
14209 /* Number of fixed point parameters. */
14210 /* This is actually the number of words of fixed point parameters; thus
14211 an 8 byte struct counts as 2; and thus the maximum value is 8. */
14212 fprintf (file, "%d,", fixed_parms);
14214 /* 2 bitfields: number of floating point parameters (7 bits), parameters
14215 all on stack. */
14216 /* This is actually the number of fp registers that hold parameters;
14217 and thus the maximum value is 13. */
14218 /* Set parameters on stack bit if parameters are not in their original
14219 registers, regardless of whether they are on the stack? Xlc
14220 seems to set the bit when not optimizing. */
14221 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
14223 if (! optional_tbtab)
14224 return;
14226 /* Optional fields follow. Some are variable length. */
14228 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
14229 11 double float. */
14230 /* There is an entry for each parameter in a register, in the order that
14231 they occur in the parameter list. Any intervening arguments on the
14232 stack are ignored. If the list overflows a long (max possible length
14233 34 bits) then completely leave off all elements that don't fit. */
14234 /* Only emit this long if there was at least one parameter. */
14235 if (fixed_parms || float_parms)
14236 fprintf (file, "\t.long %d\n", parm_info);
14238 /* Offset from start of code to tb table. */
14239 fputs ("\t.long ", file);
14240 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
14241 if (TARGET_AIX)
14242 RS6000_OUTPUT_BASENAME (file, fname);
14243 else
14244 assemble_name (file, fname);
14245 putc ('-', file);
14246 rs6000_output_function_entry (file, fname);
14247 putc ('\n', file);
14249 /* Interrupt handler mask. */
14250 /* Omit this long, since we never set the interrupt handler bit
14251 above. */
14253 /* Number of CTL (controlled storage) anchors. */
14254 /* Omit this long, since the has_ctl bit is never set above. */
14256 /* Displacement into stack of each CTL anchor. */
14257 /* Omit this list of longs, because there are no CTL anchors. */
14259 /* Length of function name. */
14260 if (*fname == '*')
14261 ++fname;
14262 fprintf (file, "\t.short %d\n", (int) strlen (fname));
14264 /* Function name. */
14265 assemble_string (fname, strlen (fname));
14267 /* Register for alloca automatic storage; this is always reg 31.
14268 Only emit this if the alloca bit was set above. */
14269 if (frame_pointer_needed)
14270 fputs ("\t.byte 31\n", file);
14272 fputs ("\t.align 2\n", file);
14276 /* A C compound statement that outputs the assembler code for a thunk
14277 function, used to implement C++ virtual function calls with
14278 multiple inheritance. The thunk acts as a wrapper around a virtual
14279 function, adjusting the implicit object parameter before handing
14280 control off to the real function.
14282 First, emit code to add the integer DELTA to the location that
14283 contains the incoming first argument. Assume that this argument
14284 contains a pointer, and is the one used to pass the `this' pointer
14285 in C++. This is the incoming argument *before* the function
14286 prologue, e.g. `%o0' on a sparc. The addition must preserve the
14287 values of all other incoming arguments.
14289 After the addition, emit code to jump to FUNCTION, which is a
14290 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
14291 not touch the return address. Hence returning from FUNCTION will
14292 return to whoever called the current `thunk'.
14294 The effect must be as if FUNCTION had been called directly with the
14295 adjusted first argument. This macro is responsible for emitting
14296 all of the code for a thunk function; output_function_prologue()
14297 and output_function_epilogue() are not invoked.
14299 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
14300 been extracted from it.) It might possibly be useful on some
14301 targets, but probably not.
14303 If you do not define this macro, the target-independent code in the
14304 C++ frontend will generate a less efficient heavyweight thunk that
14305 calls FUNCTION instead of jumping to it. The generic approach does
14306 not support varargs. */
14308 static void
14309 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
14310 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
14311 tree function)
14313 rtx this, insn, funexp;
14315 reload_completed = 1;
14316 epilogue_completed = 1;
14317 no_new_pseudos = 1;
14318 reset_block_changes ();
14320 /* Mark the end of the (empty) prologue. */
14321 emit_note (NOTE_INSN_PROLOGUE_END);
14323 /* Find the "this" pointer. If the function returns a structure,
14324 the structure return pointer is in r3. */
14325 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
14326 this = gen_rtx_REG (Pmode, 4);
14327 else
14328 this = gen_rtx_REG (Pmode, 3);
14330 /* Apply the constant offset, if required. */
14331 if (delta)
14333 rtx delta_rtx = GEN_INT (delta);
14334 emit_insn (TARGET_32BIT
14335 ? gen_addsi3 (this, this, delta_rtx)
14336 : gen_adddi3 (this, this, delta_rtx));
14339 /* Apply the offset from the vtable, if required. */
14340 if (vcall_offset)
14342 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
14343 rtx tmp = gen_rtx_REG (Pmode, 12);
14345 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
14346 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
14348 emit_insn (TARGET_32BIT
14349 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
14350 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
14351 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
14353 else
14355 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
14357 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
14359 emit_insn (TARGET_32BIT
14360 ? gen_addsi3 (this, this, tmp)
14361 : gen_adddi3 (this, this, tmp));
14364 /* Generate a tail call to the target function. */
14365 if (!TREE_USED (function))
14367 assemble_external (function);
14368 TREE_USED (function) = 1;
14370 funexp = XEXP (DECL_RTL (function), 0);
14371 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
14373 #if TARGET_MACHO
14374 if (MACHOPIC_INDIRECT)
14375 funexp = machopic_indirect_call_target (funexp);
14376 #endif
14378 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
14379 generate sibcall RTL explicitly to avoid constraint abort. */
14380 insn = emit_call_insn (
14381 gen_rtx_PARALLEL (VOIDmode,
14382 gen_rtvec (4,
14383 gen_rtx_CALL (VOIDmode,
14384 funexp, const0_rtx),
14385 gen_rtx_USE (VOIDmode, const0_rtx),
14386 gen_rtx_USE (VOIDmode,
14387 gen_rtx_REG (SImode,
14388 LINK_REGISTER_REGNUM)),
14389 gen_rtx_RETURN (VOIDmode))));
14390 SIBLING_CALL_P (insn) = 1;
14391 emit_barrier ();
14393 /* Run just enough of rest_of_compilation to get the insns emitted.
14394 There's not really enough bulk here to make other passes such as
14395 instruction scheduling worth while. Note that use_thunk calls
14396 assemble_start_function and assemble_end_function. */
14397 insn = get_insns ();
14398 insn_locators_initialize ();
14399 shorten_branches (insn);
14400 final_start_function (insn, file, 1);
14401 final (insn, file, 1, 0);
14402 final_end_function ();
14404 reload_completed = 0;
14405 epilogue_completed = 0;
14406 no_new_pseudos = 0;
14409 /* A quick summary of the various types of 'constant-pool tables'
14410 under PowerPC:
14412 Target Flags Name One table per
14413 AIX (none) AIX TOC object file
14414 AIX -mfull-toc AIX TOC object file
14415 AIX -mminimal-toc AIX minimal TOC translation unit
14416 SVR4/EABI (none) SVR4 SDATA object file
14417 SVR4/EABI -fpic SVR4 pic object file
14418 SVR4/EABI -fPIC SVR4 PIC translation unit
14419 SVR4/EABI -mrelocatable EABI TOC function
14420 SVR4/EABI -maix AIX TOC object file
14421 SVR4/EABI -maix -mminimal-toc
14422 AIX minimal TOC translation unit
14424 Name Reg. Set by entries contains:
14425 made by addrs? fp? sum?
14427 AIX TOC 2 crt0 as Y option option
14428 AIX minimal TOC 30 prolog gcc Y Y option
14429 SVR4 SDATA 13 crt0 gcc N Y N
14430 SVR4 pic 30 prolog ld Y not yet N
14431 SVR4 PIC 30 prolog gcc Y option option
14432 EABI TOC 30 prolog gcc Y option option
14436 /* Hash functions for the hash table. */
14438 static unsigned
14439 rs6000_hash_constant (rtx k)
14441 enum rtx_code code = GET_CODE (k);
14442 enum machine_mode mode = GET_MODE (k);
14443 unsigned result = (code << 3) ^ mode;
14444 const char *format;
14445 int flen, fidx;
14447 format = GET_RTX_FORMAT (code);
14448 flen = strlen (format);
14449 fidx = 0;
14451 switch (code)
14453 case LABEL_REF:
14454 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
14456 case CONST_DOUBLE:
14457 if (mode != VOIDmode)
14458 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
14459 flen = 2;
14460 break;
14462 case CODE_LABEL:
14463 fidx = 3;
14464 break;
14466 default:
14467 break;
14470 for (; fidx < flen; fidx++)
14471 switch (format[fidx])
14473 case 's':
14475 unsigned i, len;
14476 const char *str = XSTR (k, fidx);
14477 len = strlen (str);
14478 result = result * 613 + len;
14479 for (i = 0; i < len; i++)
14480 result = result * 613 + (unsigned) str[i];
14481 break;
14483 case 'u':
14484 case 'e':
14485 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
14486 break;
14487 case 'i':
14488 case 'n':
14489 result = result * 613 + (unsigned) XINT (k, fidx);
14490 break;
14491 case 'w':
14492 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
14493 result = result * 613 + (unsigned) XWINT (k, fidx);
14494 else
14496 size_t i;
14497 for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++)
14498 result = result * 613 + (unsigned) (XWINT (k, fidx)
14499 >> CHAR_BIT * i);
14501 break;
14502 case '0':
14503 break;
14504 default:
14505 abort ();
14508 return result;
14511 static unsigned
14512 toc_hash_function (const void *hash_entry)
14514 const struct toc_hash_struct *thc =
14515 (const struct toc_hash_struct *) hash_entry;
14516 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
14519 /* Compare H1 and H2 for equivalence. */
14521 static int
14522 toc_hash_eq (const void *h1, const void *h2)
14524 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
14525 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
14527 if (((const struct toc_hash_struct *) h1)->key_mode
14528 != ((const struct toc_hash_struct *) h2)->key_mode)
14529 return 0;
14531 return rtx_equal_p (r1, r2);
14534 /* These are the names given by the C++ front-end to vtables, and
14535 vtable-like objects. Ideally, this logic should not be here;
14536 instead, there should be some programmatic way of inquiring as
14537 to whether or not an object is a vtable. */
14539 #define VTABLE_NAME_P(NAME) \
14540 (strncmp ("_vt.", name, strlen("_vt.")) == 0 \
14541 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
14542 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
14543 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
14544 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
14546 void
14547 rs6000_output_symbol_ref (FILE *file, rtx x)
14549 /* Currently C++ toc references to vtables can be emitted before it
14550 is decided whether the vtable is public or private. If this is
14551 the case, then the linker will eventually complain that there is
14552 a reference to an unknown section. Thus, for vtables only,
14553 we emit the TOC reference to reference the symbol and not the
14554 section. */
14555 const char *name = XSTR (x, 0);
14557 if (VTABLE_NAME_P (name))
14559 RS6000_OUTPUT_BASENAME (file, name);
14561 else
14562 assemble_name (file, name);
14565 /* Output a TOC entry. We derive the entry name from what is being
14566 written. */
14568 void
14569 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
14571 char buf[256];
14572 const char *name = buf;
14573 const char *real_name;
14574 rtx base = x;
14575 int offset = 0;
14577 if (TARGET_NO_TOC)
14578 abort ();
14580 /* When the linker won't eliminate them, don't output duplicate
14581 TOC entries (this happens on AIX if there is any kind of TOC,
14582 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
14583 CODE_LABELs. */
14584 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
14586 struct toc_hash_struct *h;
14587 void * * found;
14589 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
14590 time because GGC is not initialized at that point. */
14591 if (toc_hash_table == NULL)
14592 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
14593 toc_hash_eq, NULL);
14595 h = ggc_alloc (sizeof (*h));
14596 h->key = x;
14597 h->key_mode = mode;
14598 h->labelno = labelno;
14600 found = htab_find_slot (toc_hash_table, h, 1);
14601 if (*found == NULL)
14602 *found = h;
14603 else /* This is indeed a duplicate.
14604 Set this label equal to that label. */
14606 fputs ("\t.set ", file);
14607 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
14608 fprintf (file, "%d,", labelno);
14609 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
14610 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
14611 found)->labelno));
14612 return;
14616 /* If we're going to put a double constant in the TOC, make sure it's
14617 aligned properly when strict alignment is on. */
14618 if (GET_CODE (x) == CONST_DOUBLE
14619 && STRICT_ALIGNMENT
14620 && GET_MODE_BITSIZE (mode) >= 64
14621 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
14622 ASM_OUTPUT_ALIGN (file, 3);
14625 (*targetm.asm_out.internal_label) (file, "LC", labelno);
14627 /* Handle FP constants specially. Note that if we have a minimal
14628 TOC, things we put here aren't actually in the TOC, so we can allow
14629 FP constants. */
14630 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
14632 REAL_VALUE_TYPE rv;
14633 long k[4];
14635 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14636 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
14638 if (TARGET_64BIT)
14640 if (TARGET_MINIMAL_TOC)
14641 fputs (DOUBLE_INT_ASM_OP, file);
14642 else
14643 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
14644 k[0] & 0xffffffff, k[1] & 0xffffffff,
14645 k[2] & 0xffffffff, k[3] & 0xffffffff);
14646 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
14647 k[0] & 0xffffffff, k[1] & 0xffffffff,
14648 k[2] & 0xffffffff, k[3] & 0xffffffff);
14649 return;
14651 else
14653 if (TARGET_MINIMAL_TOC)
14654 fputs ("\t.long ", file);
14655 else
14656 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
14657 k[0] & 0xffffffff, k[1] & 0xffffffff,
14658 k[2] & 0xffffffff, k[3] & 0xffffffff);
14659 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
14660 k[0] & 0xffffffff, k[1] & 0xffffffff,
14661 k[2] & 0xffffffff, k[3] & 0xffffffff);
14662 return;
14665 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
14667 REAL_VALUE_TYPE rv;
14668 long k[2];
14670 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14671 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
14673 if (TARGET_64BIT)
14675 if (TARGET_MINIMAL_TOC)
14676 fputs (DOUBLE_INT_ASM_OP, file);
14677 else
14678 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
14679 k[0] & 0xffffffff, k[1] & 0xffffffff);
14680 fprintf (file, "0x%lx%08lx\n",
14681 k[0] & 0xffffffff, k[1] & 0xffffffff);
14682 return;
14684 else
14686 if (TARGET_MINIMAL_TOC)
14687 fputs ("\t.long ", file);
14688 else
14689 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
14690 k[0] & 0xffffffff, k[1] & 0xffffffff);
14691 fprintf (file, "0x%lx,0x%lx\n",
14692 k[0] & 0xffffffff, k[1] & 0xffffffff);
14693 return;
14696 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
14698 REAL_VALUE_TYPE rv;
14699 long l;
14701 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14702 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
14704 if (TARGET_64BIT)
14706 if (TARGET_MINIMAL_TOC)
14707 fputs (DOUBLE_INT_ASM_OP, file);
14708 else
14709 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
14710 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
14711 return;
14713 else
14715 if (TARGET_MINIMAL_TOC)
14716 fputs ("\t.long ", file);
14717 else
14718 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
14719 fprintf (file, "0x%lx\n", l & 0xffffffff);
14720 return;
14723 else if (GET_MODE (x) == VOIDmode
14724 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
14726 unsigned HOST_WIDE_INT low;
14727 HOST_WIDE_INT high;
14729 if (GET_CODE (x) == CONST_DOUBLE)
14731 low = CONST_DOUBLE_LOW (x);
14732 high = CONST_DOUBLE_HIGH (x);
14734 else
14735 #if HOST_BITS_PER_WIDE_INT == 32
14737 low = INTVAL (x);
14738 high = (low & 0x80000000) ? ~0 : 0;
14740 #else
14742 low = INTVAL (x) & 0xffffffff;
14743 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
14745 #endif
14747 /* TOC entries are always Pmode-sized, but since this
14748 is a bigendian machine then if we're putting smaller
14749 integer constants in the TOC we have to pad them.
14750 (This is still a win over putting the constants in
14751 a separate constant pool, because then we'd have
14752 to have both a TOC entry _and_ the actual constant.)
14754 For a 32-bit target, CONST_INT values are loaded and shifted
14755 entirely within `low' and can be stored in one TOC entry. */
14757 if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
14758 abort ();/* It would be easy to make this work, but it doesn't now. */
14760 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
14762 #if HOST_BITS_PER_WIDE_INT == 32
14763 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
14764 POINTER_SIZE, &low, &high, 0);
14765 #else
14766 low |= high << 32;
14767 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
14768 high = (HOST_WIDE_INT) low >> 32;
14769 low &= 0xffffffff;
14770 #endif
14773 if (TARGET_64BIT)
14775 if (TARGET_MINIMAL_TOC)
14776 fputs (DOUBLE_INT_ASM_OP, file);
14777 else
14778 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
14779 (long) high & 0xffffffff, (long) low & 0xffffffff);
14780 fprintf (file, "0x%lx%08lx\n",
14781 (long) high & 0xffffffff, (long) low & 0xffffffff);
14782 return;
14784 else
14786 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
14788 if (TARGET_MINIMAL_TOC)
14789 fputs ("\t.long ", file);
14790 else
14791 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
14792 (long) high & 0xffffffff, (long) low & 0xffffffff);
14793 fprintf (file, "0x%lx,0x%lx\n",
14794 (long) high & 0xffffffff, (long) low & 0xffffffff);
14796 else
14798 if (TARGET_MINIMAL_TOC)
14799 fputs ("\t.long ", file);
14800 else
14801 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
14802 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
14804 return;
14808 if (GET_CODE (x) == CONST)
14810 if (GET_CODE (XEXP (x, 0)) != PLUS)
14811 abort ();
14813 base = XEXP (XEXP (x, 0), 0);
14814 offset = INTVAL (XEXP (XEXP (x, 0), 1));
14817 if (GET_CODE (base) == SYMBOL_REF)
14818 name = XSTR (base, 0);
14819 else if (GET_CODE (base) == LABEL_REF)
14820 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
14821 else if (GET_CODE (base) == CODE_LABEL)
14822 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
14823 else
14824 abort ();
14826 real_name = (*targetm.strip_name_encoding) (name);
14827 if (TARGET_MINIMAL_TOC)
14828 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
14829 else
14831 fprintf (file, "\t.tc %s", real_name);
14833 if (offset < 0)
14834 fprintf (file, ".N%d", - offset);
14835 else if (offset)
14836 fprintf (file, ".P%d", offset);
14838 fputs ("[TC],", file);
14841 /* Currently C++ toc references to vtables can be emitted before it
14842 is decided whether the vtable is public or private. If this is
14843 the case, then the linker will eventually complain that there is
14844 a TOC reference to an unknown section. Thus, for vtables only,
14845 we emit the TOC reference to reference the symbol and not the
14846 section. */
14847 if (VTABLE_NAME_P (name))
14849 RS6000_OUTPUT_BASENAME (file, name);
14850 if (offset < 0)
14851 fprintf (file, "%d", offset);
14852 else if (offset > 0)
14853 fprintf (file, "+%d", offset);
14855 else
14856 output_addr_const (file, x);
14857 putc ('\n', file);
14860 /* Output an assembler pseudo-op to write an ASCII string of N characters
14861 starting at P to FILE.
14863 On the RS/6000, we have to do this using the .byte operation and
14864 write out special characters outside the quoted string.
14865 Also, the assembler is broken; very long strings are truncated,
14866 so we must artificially break them up early. */
14868 void
14869 output_ascii (FILE *file, const char *p, int n)
14871 char c;
14872 int i, count_string;
14873 const char *for_string = "\t.byte \"";
14874 const char *for_decimal = "\t.byte ";
14875 const char *to_close = NULL;
14877 count_string = 0;
14878 for (i = 0; i < n; i++)
14880 c = *p++;
14881 if (c >= ' ' && c < 0177)
14883 if (for_string)
14884 fputs (for_string, file);
14885 putc (c, file);
14887 /* Write two quotes to get one. */
14888 if (c == '"')
14890 putc (c, file);
14891 ++count_string;
14894 for_string = NULL;
14895 for_decimal = "\"\n\t.byte ";
14896 to_close = "\"\n";
14897 ++count_string;
14899 if (count_string >= 512)
14901 fputs (to_close, file);
14903 for_string = "\t.byte \"";
14904 for_decimal = "\t.byte ";
14905 to_close = NULL;
14906 count_string = 0;
14909 else
14911 if (for_decimal)
14912 fputs (for_decimal, file);
14913 fprintf (file, "%d", c);
14915 for_string = "\n\t.byte \"";
14916 for_decimal = ", ";
14917 to_close = "\n";
14918 count_string = 0;
14922 /* Now close the string if we have written one. Then end the line. */
14923 if (to_close)
14924 fputs (to_close, file);
14927 /* Generate a unique section name for FILENAME for a section type
14928 represented by SECTION_DESC. Output goes into BUF.
14930 SECTION_DESC can be any string, as long as it is different for each
14931 possible section type.
14933 We name the section in the same manner as xlc. The name begins with an
14934 underscore followed by the filename (after stripping any leading directory
14935 names) with the last period replaced by the string SECTION_DESC. If
14936 FILENAME does not contain a period, SECTION_DESC is appended to the end of
14937 the name. */
14939 void
14940 rs6000_gen_section_name (char **buf, const char *filename,
14941 const char *section_desc)
14943 const char *q, *after_last_slash, *last_period = 0;
14944 char *p;
14945 int len;
14947 after_last_slash = filename;
14948 for (q = filename; *q; q++)
14950 if (*q == '/')
14951 after_last_slash = q + 1;
14952 else if (*q == '.')
14953 last_period = q;
14956 len = strlen (after_last_slash) + strlen (section_desc) + 2;
14957 *buf = (char *) xmalloc (len);
14959 p = *buf;
14960 *p++ = '_';
14962 for (q = after_last_slash; *q; q++)
14964 if (q == last_period)
14966 strcpy (p, section_desc);
14967 p += strlen (section_desc);
14968 break;
14971 else if (ISALNUM (*q))
14972 *p++ = *q;
14975 if (last_period == 0)
14976 strcpy (p, section_desc);
14977 else
14978 *p = '\0';
14981 /* Emit profile function. */
14983 void
14984 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
14986 if (TARGET_PROFILE_KERNEL)
14987 return;
14989 if (DEFAULT_ABI == ABI_AIX)
14991 #ifndef NO_PROFILE_COUNTERS
14992 # define NO_PROFILE_COUNTERS 0
14993 #endif
14994 if (NO_PROFILE_COUNTERS)
14995 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
14996 else
14998 char buf[30];
14999 const char *label_name;
15000 rtx fun;
15002 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
15003 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
15004 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
15006 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
15007 fun, Pmode);
15010 else if (DEFAULT_ABI == ABI_DARWIN)
15012 const char *mcount_name = RS6000_MCOUNT;
15013 int caller_addr_regno = LINK_REGISTER_REGNUM;
15015 /* Be conservative and always set this, at least for now. */
15016 current_function_uses_pic_offset_table = 1;
15018 #if TARGET_MACHO
15019 /* For PIC code, set up a stub and collect the caller's address
15020 from r0, which is where the prologue puts it. */
15021 if (MACHOPIC_INDIRECT
15022 && current_function_uses_pic_offset_table)
15023 caller_addr_regno = 0;
15024 #endif
15025 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
15026 0, VOIDmode, 1,
15027 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
15031 /* Write function profiler code. */
15033 void
15034 output_function_profiler (FILE *file, int labelno)
15036 char buf[100];
15037 int save_lr = 8;
15039 switch (DEFAULT_ABI)
15041 default:
15042 abort ();
15044 case ABI_V4:
15045 save_lr = 4;
15046 if (!TARGET_32BIT)
15048 warning ("no profiling of 64-bit code for this ABI");
15049 return;
15051 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
15052 fprintf (file, "\tmflr %s\n", reg_names[0]);
15053 if (flag_pic == 1)
15055 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
15056 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
15057 reg_names[0], save_lr, reg_names[1]);
15058 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
15059 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
15060 assemble_name (file, buf);
15061 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
15063 else if (flag_pic > 1)
15065 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
15066 reg_names[0], save_lr, reg_names[1]);
15067 /* Now, we need to get the address of the label. */
15068 fputs ("\tbl 1f\n\t.long ", file);
15069 assemble_name (file, buf);
15070 fputs ("-.\n1:", file);
15071 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
15072 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
15073 reg_names[0], reg_names[11]);
15074 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
15075 reg_names[0], reg_names[0], reg_names[11]);
15077 else
15079 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
15080 assemble_name (file, buf);
15081 fputs ("@ha\n", file);
15082 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
15083 reg_names[0], save_lr, reg_names[1]);
15084 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
15085 assemble_name (file, buf);
15086 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
15089 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
15090 fprintf (file, "\tbl %s%s\n",
15091 RS6000_MCOUNT, flag_pic ? "@plt" : "");
15092 break;
15094 case ABI_AIX:
15095 case ABI_DARWIN:
15096 if (!TARGET_PROFILE_KERNEL)
15098 /* Don't do anything, done in output_profile_hook (). */
15100 else
15102 if (TARGET_32BIT)
15103 abort ();
15105 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
15106 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
15108 if (cfun->static_chain_decl != NULL)
15110 asm_fprintf (file, "\tstd %s,24(%s)\n",
15111 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
15112 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
15113 asm_fprintf (file, "\tld %s,24(%s)\n",
15114 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
15116 else
15117 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
15119 break;
15124 /* Power4 load update and store update instructions are cracked into a
15125 load or store and an integer insn which are executed in the same cycle.
15126 Branches have their own dispatch slot which does not count against the
15127 GCC issue rate, but it changes the program flow so there are no other
15128 instructions to issue in this cycle. */
15130 static int
15131 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
15132 int verbose ATTRIBUTE_UNUSED,
15133 rtx insn, int more)
15135 if (GET_CODE (PATTERN (insn)) == USE
15136 || GET_CODE (PATTERN (insn)) == CLOBBER)
15137 return more;
15139 if (rs6000_sched_groups)
15141 if (is_microcoded_insn (insn))
15142 return 0;
15143 else if (is_cracked_insn (insn))
15144 return more > 2 ? more - 2 : 0;
15147 return more - 1;
15150 /* Adjust the cost of a scheduling dependency. Return the new cost of
15151 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
15153 static int
15154 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn ATTRIBUTE_UNUSED,
15155 int cost)
15157 if (! recog_memoized (insn))
15158 return 0;
15160 if (REG_NOTE_KIND (link) != 0)
15161 return 0;
15163 if (REG_NOTE_KIND (link) == 0)
15165 /* Data dependency; DEP_INSN writes a register that INSN reads
15166 some cycles later. */
15167 switch (get_attr_type (insn))
15169 case TYPE_JMPREG:
15170 /* Tell the first scheduling pass about the latency between
15171 a mtctr and bctr (and mtlr and br/blr). The first
15172 scheduling pass will not know about this latency since
15173 the mtctr instruction, which has the latency associated
15174 to it, will be generated by reload. */
15175 return TARGET_POWER ? 5 : 4;
15176 case TYPE_BRANCH:
15177 /* Leave some extra cycles between a compare and its
15178 dependent branch, to inhibit expensive mispredicts. */
15179 if ((rs6000_cpu_attr == CPU_PPC603
15180 || rs6000_cpu_attr == CPU_PPC604
15181 || rs6000_cpu_attr == CPU_PPC604E
15182 || rs6000_cpu_attr == CPU_PPC620
15183 || rs6000_cpu_attr == CPU_PPC630
15184 || rs6000_cpu_attr == CPU_PPC750
15185 || rs6000_cpu_attr == CPU_PPC7400
15186 || rs6000_cpu_attr == CPU_PPC7450
15187 || rs6000_cpu_attr == CPU_POWER4
15188 || rs6000_cpu_attr == CPU_POWER5)
15189 && recog_memoized (dep_insn)
15190 && (INSN_CODE (dep_insn) >= 0)
15191 && (get_attr_type (dep_insn) == TYPE_CMP
15192 || get_attr_type (dep_insn) == TYPE_COMPARE
15193 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
15194 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
15195 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
15196 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
15197 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
15198 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
15199 return cost + 2;
15200 default:
15201 break;
15203 /* Fall out to return default cost. */
15206 return cost;
15209 /* The function returns a true if INSN is microcoded.
15210 Return false otherwise. */
15212 static bool
15213 is_microcoded_insn (rtx insn)
15215 if (!insn || !INSN_P (insn)
15216 || GET_CODE (PATTERN (insn)) == USE
15217 || GET_CODE (PATTERN (insn)) == CLOBBER)
15218 return false;
15220 if (rs6000_sched_groups)
15222 enum attr_type type = get_attr_type (insn);
15223 if (type == TYPE_LOAD_EXT_U
15224 || type == TYPE_LOAD_EXT_UX
15225 || type == TYPE_LOAD_UX
15226 || type == TYPE_STORE_UX
15227 || type == TYPE_MFCR)
15228 return true;
15231 return false;
15234 /* The function returns a nonzero value if INSN can be scheduled only
15235 as the first insn in a dispatch group ("dispatch-slot restricted").
15236 In this case, the returned value indicates how many dispatch slots
15237 the insn occupies (at the beginning of the group).
15238 Return 0 otherwise. */
15240 static int
15241 is_dispatch_slot_restricted (rtx insn)
15243 enum attr_type type;
15245 if (!rs6000_sched_groups)
15246 return 0;
15248 if (!insn
15249 || insn == NULL_RTX
15250 || GET_CODE (insn) == NOTE
15251 || GET_CODE (PATTERN (insn)) == USE
15252 || GET_CODE (PATTERN (insn)) == CLOBBER)
15253 return 0;
15255 type = get_attr_type (insn);
15257 switch (type)
15259 case TYPE_MFCR:
15260 case TYPE_MFCRF:
15261 case TYPE_MTCR:
15262 case TYPE_DELAYED_CR:
15263 case TYPE_CR_LOGICAL:
15264 case TYPE_MTJMPR:
15265 case TYPE_MFJMPR:
15266 return 1;
15267 case TYPE_IDIV:
15268 case TYPE_LDIV:
15269 return 2;
15270 default:
15271 if (rs6000_cpu == PROCESSOR_POWER5
15272 && is_cracked_insn (insn))
15273 return 2;
15274 return 0;
15278 /* The function returns true if INSN is cracked into 2 instructions
15279 by the processor (and therefore occupies 2 issue slots). */
15281 static bool
15282 is_cracked_insn (rtx insn)
15284 if (!insn || !INSN_P (insn)
15285 || GET_CODE (PATTERN (insn)) == USE
15286 || GET_CODE (PATTERN (insn)) == CLOBBER)
15287 return false;
15289 if (rs6000_sched_groups)
15291 enum attr_type type = get_attr_type (insn);
15292 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
15293 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
15294 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
15295 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
15296 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
15297 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
15298 || type == TYPE_IDIV || type == TYPE_LDIV
15299 || type == TYPE_INSERT_WORD)
15300 return true;
15303 return false;
15306 /* The function returns true if INSN can be issued only from
15307 the branch slot. */
15309 static bool
15310 is_branch_slot_insn (rtx insn)
15312 if (!insn || !INSN_P (insn)
15313 || GET_CODE (PATTERN (insn)) == USE
15314 || GET_CODE (PATTERN (insn)) == CLOBBER)
15315 return false;
15317 if (rs6000_sched_groups)
15319 enum attr_type type = get_attr_type (insn);
15320 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
15321 return true;
15322 return false;
15325 return false;
15328 /* A C statement (sans semicolon) to update the integer scheduling
15329 priority INSN_PRIORITY (INSN). Increase the priority to execute the
15330 INSN earlier, reduce the priority to execute INSN later. Do not
15331 define this macro if you do not need to adjust the scheduling
15332 priorities of insns. */
15334 static int
15335 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
15337 /* On machines (like the 750) which have asymmetric integer units,
15338 where one integer unit can do multiply and divides and the other
15339 can't, reduce the priority of multiply/divide so it is scheduled
15340 before other integer operations. */
15342 #if 0
15343 if (! INSN_P (insn))
15344 return priority;
15346 if (GET_CODE (PATTERN (insn)) == USE)
15347 return priority;
15349 switch (rs6000_cpu_attr) {
15350 case CPU_PPC750:
15351 switch (get_attr_type (insn))
15353 default:
15354 break;
15356 case TYPE_IMUL:
15357 case TYPE_IDIV:
15358 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
15359 priority, priority);
15360 if (priority >= 0 && priority < 0x01000000)
15361 priority >>= 3;
15362 break;
15365 #endif
15367 if (is_dispatch_slot_restricted (insn)
15368 && reload_completed
15369 && current_sched_info->sched_max_insns_priority
15370 && rs6000_sched_restricted_insns_priority)
15373 /* Prioritize insns that can be dispatched only in the first dispatch slot. */
15374 if (rs6000_sched_restricted_insns_priority == 1)
15375 /* Attach highest priority to insn. This means that in
15376 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
15377 precede 'priority' (critical path) considerations. */
15378 return current_sched_info->sched_max_insns_priority;
15379 else if (rs6000_sched_restricted_insns_priority == 2)
15380 /* Increase priority of insn by a minimal amount. This means that in
15381 haifa-sched.c:ready_sort(), only 'priority' (critical path) considerations
15382 precede dispatch-slot restriction considerations. */
15383 return (priority + 1);
15386 return priority;
15389 /* Return how many instructions the machine can issue per cycle. */
15391 static int
15392 rs6000_issue_rate (void)
15394 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
15395 if (!reload_completed)
15396 return 1;
15398 switch (rs6000_cpu_attr) {
15399 case CPU_RIOS1: /* ? */
15400 case CPU_RS64A:
15401 case CPU_PPC601: /* ? */
15402 case CPU_PPC7450:
15403 return 3;
15404 case CPU_PPC440:
15405 case CPU_PPC603:
15406 case CPU_PPC750:
15407 case CPU_PPC7400:
15408 case CPU_PPC8540:
15409 return 2;
15410 case CPU_RIOS2:
15411 case CPU_PPC604:
15412 case CPU_PPC604E:
15413 case CPU_PPC620:
15414 case CPU_PPC630:
15415 return 4;
15416 case CPU_POWER4:
15417 case CPU_POWER5:
15418 return 5;
15419 default:
15420 return 1;
15424 /* Return how many instructions to look ahead for better insn
15425 scheduling. */
15427 static int
15428 rs6000_use_sched_lookahead (void)
15430 if (rs6000_cpu_attr == CPU_PPC8540)
15431 return 4;
15432 return 0;
15435 /* Determine is PAT refers to memory. */
15437 static bool
15438 is_mem_ref (rtx pat)
15440 const char * fmt;
15441 int i, j;
15442 bool ret = false;
15444 if (GET_CODE (pat) == MEM)
15445 return true;
15447 /* Recursively process the pattern. */
15448 fmt = GET_RTX_FORMAT (GET_CODE (pat));
15450 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
15452 if (fmt[i] == 'e')
15453 ret |= is_mem_ref (XEXP (pat, i));
15454 else if (fmt[i] == 'E')
15455 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
15456 ret |= is_mem_ref (XVECEXP (pat, i, j));
15459 return ret;
15462 /* Determine if PAT is a PATTERN of a load insn. */
15464 static bool
15465 is_load_insn1 (rtx pat)
15467 if (!pat || pat == NULL_RTX)
15468 return false;
15470 if (GET_CODE (pat) == SET)
15471 return is_mem_ref (SET_SRC (pat));
15473 if (GET_CODE (pat) == PARALLEL)
15475 int i;
15477 for (i = 0; i < XVECLEN (pat, 0); i++)
15478 if (is_load_insn1 (XVECEXP (pat, 0, i)))
15479 return true;
15482 return false;
15485 /* Determine if INSN loads from memory. */
15487 static bool
15488 is_load_insn (rtx insn)
15490 if (!insn || !INSN_P (insn))
15491 return false;
15493 if (GET_CODE (insn) == CALL_INSN)
15494 return false;
15496 return is_load_insn1 (PATTERN (insn));
15499 /* Determine if PAT is a PATTERN of a store insn. */
15501 static bool
15502 is_store_insn1 (rtx pat)
15504 if (!pat || pat == NULL_RTX)
15505 return false;
15507 if (GET_CODE (pat) == SET)
15508 return is_mem_ref (SET_DEST (pat));
15510 if (GET_CODE (pat) == PARALLEL)
15512 int i;
15514 for (i = 0; i < XVECLEN (pat, 0); i++)
15515 if (is_store_insn1 (XVECEXP (pat, 0, i)))
15516 return true;
15519 return false;
15522 /* Determine if INSN stores to memory. */
15524 static bool
15525 is_store_insn (rtx insn)
15527 if (!insn || !INSN_P (insn))
15528 return false;
15530 return is_store_insn1 (PATTERN (insn));
15533 /* Returns whether the dependence between INSN and NEXT is considered
15534 costly by the given target. */
15536 static bool
15537 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost, int distance)
15539 /* If the flag is not enbled - no dependence is considered costly;
15540 allow all dependent insns in the same group.
15541 This is the most aggressive option. */
15542 if (rs6000_sched_costly_dep == no_dep_costly)
15543 return false;
15545 /* If the flag is set to 1 - a dependence is always considered costly;
15546 do not allow dependent instructions in the same group.
15547 This is the most conservative option. */
15548 if (rs6000_sched_costly_dep == all_deps_costly)
15549 return true;
15551 if (rs6000_sched_costly_dep == store_to_load_dep_costly
15552 && is_load_insn (next)
15553 && is_store_insn (insn))
15554 /* Prevent load after store in the same group. */
15555 return true;
15557 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
15558 && is_load_insn (next)
15559 && is_store_insn (insn)
15560 && (!link || (int) REG_NOTE_KIND (link) == 0))
15561 /* Prevent load after store in the same group if it is a true dependence. */
15562 return true;
15564 /* The flag is set to X; dependences with latency >= X are considered costly,
15565 and will not be scheduled in the same group. */
15566 if (rs6000_sched_costly_dep <= max_dep_latency
15567 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
15568 return true;
15570 return false;
15573 /* Return the next insn after INSN that is found before TAIL is reached,
15574 skipping any "non-active" insns - insns that will not actually occupy
15575 an issue slot. Return NULL_RTX if such an insn is not found. */
15577 static rtx
15578 get_next_active_insn (rtx insn, rtx tail)
15580 rtx next_insn;
15582 if (!insn || insn == tail)
15583 return NULL_RTX;
15585 next_insn = NEXT_INSN (insn);
15587 while (next_insn
15588 && next_insn != tail
15589 && (GET_CODE(next_insn) == NOTE
15590 || GET_CODE (PATTERN (next_insn)) == USE
15591 || GET_CODE (PATTERN (next_insn)) == CLOBBER))
15593 next_insn = NEXT_INSN (next_insn);
15596 if (!next_insn || next_insn == tail)
15597 return NULL_RTX;
15599 return next_insn;
15602 /* Return whether the presence of INSN causes a dispatch group termination
15603 of group WHICH_GROUP.
15605 If WHICH_GROUP == current_group, this function will return true if INSN
15606 causes the termination of the current group (i.e, the dispatch group to
15607 which INSN belongs). This means that INSN will be the last insn in the
15608 group it belongs to.
15610 If WHICH_GROUP == previous_group, this function will return true if INSN
15611 causes the termination of the previous group (i.e, the dispatch group that
15612 precedes the group to which INSN belongs). This means that INSN will be
15613 the first insn in the group it belongs to). */
15615 static bool
15616 insn_terminates_group_p (rtx insn, enum group_termination which_group)
15618 enum attr_type type;
15620 if (! insn)
15621 return false;
15623 type = get_attr_type (insn);
15625 if (is_microcoded_insn (insn))
15626 return true;
15628 if (which_group == current_group)
15630 if (is_branch_slot_insn (insn))
15631 return true;
15632 return false;
15634 else if (which_group == previous_group)
15636 if (is_dispatch_slot_restricted (insn))
15637 return true;
15638 return false;
15641 return false;
15644 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
15645 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
15647 static bool
15648 is_costly_group (rtx *group_insns, rtx next_insn)
15650 int i;
15651 rtx link;
15652 int cost;
15653 int issue_rate = rs6000_issue_rate ();
15655 for (i = 0; i < issue_rate; i++)
15657 rtx insn = group_insns[i];
15658 if (!insn)
15659 continue;
15660 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
15662 rtx next = XEXP (link, 0);
15663 if (next == next_insn)
15665 cost = insn_cost (insn, link, next_insn);
15666 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
15667 return true;
15672 return false;
15675 /* Utility of the function redefine_groups.
15676 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
15677 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
15678 to keep it "far" (in a separate group) from GROUP_INSNS, following
15679 one of the following schemes, depending on the value of the flag
15680 -minsert_sched_nops = X:
15681 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
15682 in order to force NEXT_INSN into a separate group.
15683 (2) X < sched_finish_regroup_exact: insert exactly X nops.
15684 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
15685 insertion (has a group just ended, how many vacant issue slots remain in the
15686 last group, and how many dispatch groups were encountered so far). */
15688 static int
15689 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns, rtx next_insn,
15690 bool *group_end, int can_issue_more, int *group_count)
15692 rtx nop;
15693 bool force;
15694 int issue_rate = rs6000_issue_rate ();
15695 bool end = *group_end;
15696 int i;
15698 if (next_insn == NULL_RTX)
15699 return can_issue_more;
15701 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
15702 return can_issue_more;
15704 force = is_costly_group (group_insns, next_insn);
15705 if (!force)
15706 return can_issue_more;
15708 if (sched_verbose > 6)
15709 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
15710 *group_count ,can_issue_more);
15712 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
15714 if (*group_end)
15715 can_issue_more = 0;
15717 /* Since only a branch can be issued in the last issue_slot, it is
15718 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
15719 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
15720 in this case the last nop will start a new group and the branch will be
15721 forced to the new group. */
15722 if (can_issue_more && !is_branch_slot_insn (next_insn))
15723 can_issue_more--;
15725 while (can_issue_more > 0)
15727 nop = gen_nop();
15728 emit_insn_before (nop, next_insn);
15729 can_issue_more--;
15732 *group_end = true;
15733 return 0;
15736 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
15738 int n_nops = rs6000_sched_insert_nops;
15740 /* Nops can't be issued from the branch slot, so the effective
15741 issue_rate for nops is 'issue_rate - 1'. */
15742 if (can_issue_more == 0)
15743 can_issue_more = issue_rate;
15744 can_issue_more--;
15745 if (can_issue_more == 0)
15747 can_issue_more = issue_rate - 1;
15748 (*group_count)++;
15749 end = true;
15750 for (i = 0; i < issue_rate; i++)
15752 group_insns[i] = 0;
15756 while (n_nops > 0)
15758 nop = gen_nop ();
15759 emit_insn_before (nop, next_insn);
15760 if (can_issue_more == issue_rate - 1) /* new group begins */
15761 end = false;
15762 can_issue_more--;
15763 if (can_issue_more == 0)
15765 can_issue_more = issue_rate - 1;
15766 (*group_count)++;
15767 end = true;
15768 for (i = 0; i < issue_rate; i++)
15770 group_insns[i] = 0;
15773 n_nops--;
15776 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
15777 can_issue_more++;
15779 *group_end = /* Is next_insn going to start a new group? */
15780 (end
15781 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
15782 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
15783 || (can_issue_more < issue_rate &&
15784 insn_terminates_group_p (next_insn, previous_group)));
15785 if (*group_end && end)
15786 (*group_count)--;
15788 if (sched_verbose > 6)
15789 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
15790 *group_count, can_issue_more);
15791 return can_issue_more;
15794 return can_issue_more;
15797 /* This function tries to synch the dispatch groups that the compiler "sees"
15798 with the dispatch groups that the processor dispatcher is expected to
15799 form in practice. It tries to achieve this synchronization by forcing the
15800 estimated processor grouping on the compiler (as opposed to the function
15801 'pad_goups' which tries to force the scheduler's grouping on the processor).
15803 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
15804 examines the (estimated) dispatch groups that will be formed by the processor
15805 dispatcher. It marks these group boundaries to reflect the estimated
15806 processor grouping, overriding the grouping that the scheduler had marked.
15807 Depending on the value of the flag '-minsert-sched-nops' this function can
15808 force certain insns into separate groups or force a certain distance between
15809 them by inserting nops, for example, if there exists a "costly dependence"
15810 between the insns.
15812 The function estimates the group boundaries that the processor will form as
15813 folllows: It keeps track of how many vacant issue slots are available after
15814 each insn. A subsequent insn will start a new group if one of the following
15815 4 cases applies:
15816 - no more vacant issue slots remain in the current dispatch group.
15817 - only the last issue slot, which is the branch slot, is vacant, but the next
15818 insn is not a branch.
15819 - only the last 2 or less issue slots, including the branch slot, are vacant,
15820 which means that a cracked insn (which occupies two issue slots) can't be
15821 issued in this group.
15822 - less than 'issue_rate' slots are vacant, and the next insn always needs to
15823 start a new group. */
15825 static int
15826 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
15828 rtx insn, next_insn;
15829 int issue_rate;
15830 int can_issue_more;
15831 int slot, i;
15832 bool group_end;
15833 int group_count = 0;
15834 rtx *group_insns;
15836 /* Initialize. */
15837 issue_rate = rs6000_issue_rate ();
15838 group_insns = alloca (issue_rate * sizeof (rtx));
15839 for (i = 0; i < issue_rate; i++)
15841 group_insns[i] = 0;
15843 can_issue_more = issue_rate;
15844 slot = 0;
15845 insn = get_next_active_insn (prev_head_insn, tail);
15846 group_end = false;
15848 while (insn != NULL_RTX)
15850 slot = (issue_rate - can_issue_more);
15851 group_insns[slot] = insn;
15852 can_issue_more =
15853 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
15854 if (insn_terminates_group_p (insn, current_group))
15855 can_issue_more = 0;
15857 next_insn = get_next_active_insn (insn, tail);
15858 if (next_insn == NULL_RTX)
15859 return group_count + 1;
15861 group_end = /* Is next_insn going to start a new group? */
15862 (can_issue_more == 0
15863 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
15864 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
15865 || (can_issue_more < issue_rate &&
15866 insn_terminates_group_p (next_insn, previous_group)));
15868 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
15869 next_insn, &group_end, can_issue_more, &group_count);
15871 if (group_end)
15873 group_count++;
15874 can_issue_more = 0;
15875 for (i = 0; i < issue_rate; i++)
15877 group_insns[i] = 0;
15881 if (GET_MODE (next_insn) == TImode && can_issue_more)
15882 PUT_MODE(next_insn, VOIDmode);
15883 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
15884 PUT_MODE (next_insn, TImode);
15886 insn = next_insn;
15887 if (can_issue_more == 0)
15888 can_issue_more = issue_rate;
15889 } /* while */
15891 return group_count;
15894 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
15895 dispatch group boundaries that the scheduler had marked. Pad with nops
15896 any dispatch groups which have vacant issue slots, in order to force the
15897 scheduler's grouping on the processor dispatcher. The function
15898 returns the number of dispatch groups found. */
15900 static int
15901 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
15903 rtx insn, next_insn;
15904 rtx nop;
15905 int issue_rate;
15906 int can_issue_more;
15907 int group_end;
15908 int group_count = 0;
15910 /* Initialize issue_rate. */
15911 issue_rate = rs6000_issue_rate ();
15912 can_issue_more = issue_rate;
15914 insn = get_next_active_insn (prev_head_insn, tail);
15915 next_insn = get_next_active_insn (insn, tail);
15917 while (insn != NULL_RTX)
15919 can_issue_more =
15920 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
15922 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
15924 if (next_insn == NULL_RTX)
15925 break;
15927 if (group_end)
15929 /* If the scheduler had marked group termination at this location
15930 (between insn and next_indn), and neither insn nor next_insn will
15931 force group termination, pad the group with nops to force group
15932 termination. */
15933 if (can_issue_more
15934 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
15935 && !insn_terminates_group_p (insn, current_group)
15936 && !insn_terminates_group_p (next_insn, previous_group))
15938 if (!is_branch_slot_insn(next_insn))
15939 can_issue_more--;
15941 while (can_issue_more)
15943 nop = gen_nop ();
15944 emit_insn_before (nop, next_insn);
15945 can_issue_more--;
15949 can_issue_more = issue_rate;
15950 group_count++;
15953 insn = next_insn;
15954 next_insn = get_next_active_insn (insn, tail);
15957 return group_count;
15960 /* The following function is called at the end of scheduling BB.
15961 After reload, it inserts nops at insn group bundling. */
15963 static void
15964 rs6000_sched_finish (FILE *dump, int sched_verbose)
15966 int n_groups;
15968 if (sched_verbose)
15969 fprintf (dump, "=== Finishing schedule.\n");
15971 if (reload_completed && rs6000_sched_groups)
15973 if (rs6000_sched_insert_nops == sched_finish_none)
15974 return;
15976 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
15977 n_groups = pad_groups (dump, sched_verbose,
15978 current_sched_info->prev_head,
15979 current_sched_info->next_tail);
15980 else
15981 n_groups = redefine_groups (dump, sched_verbose,
15982 current_sched_info->prev_head,
15983 current_sched_info->next_tail);
15985 if (sched_verbose >= 6)
15987 fprintf (dump, "ngroups = %d\n", n_groups);
15988 print_rtl (dump, current_sched_info->prev_head);
15989 fprintf (dump, "Done finish_sched\n");
15994 /* Length in units of the trampoline for entering a nested function. */
15997 rs6000_trampoline_size (void)
15999 int ret = 0;
16001 switch (DEFAULT_ABI)
16003 default:
16004 abort ();
16006 case ABI_AIX:
16007 ret = (TARGET_32BIT) ? 12 : 24;
16008 break;
16010 case ABI_DARWIN:
16011 case ABI_V4:
16012 ret = (TARGET_32BIT) ? 40 : 48;
16013 break;
16016 return ret;
16019 /* Emit RTL insns to initialize the variable parts of a trampoline.
16020 FNADDR is an RTX for the address of the function's pure code.
16021 CXT is an RTX for the static chain value for the function. */
16023 void
16024 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
16026 enum machine_mode pmode = Pmode;
16027 int regsize = (TARGET_32BIT) ? 4 : 8;
16028 rtx ctx_reg = force_reg (pmode, cxt);
16030 switch (DEFAULT_ABI)
16032 default:
16033 abort ();
16035 /* Macros to shorten the code expansions below. */
16036 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
16037 #define MEM_PLUS(addr,offset) \
16038 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
16040 /* Under AIX, just build the 3 word function descriptor */
16041 case ABI_AIX:
16043 rtx fn_reg = gen_reg_rtx (pmode);
16044 rtx toc_reg = gen_reg_rtx (pmode);
16045 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
16046 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
16047 emit_move_insn (MEM_DEREF (addr), fn_reg);
16048 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
16049 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
16051 break;
16053 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
16054 case ABI_DARWIN:
16055 case ABI_V4:
16056 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
16057 FALSE, VOIDmode, 4,
16058 addr, pmode,
16059 GEN_INT (rs6000_trampoline_size ()), SImode,
16060 fnaddr, pmode,
16061 ctx_reg, pmode);
16062 break;
16065 return;
16069 /* Table of valid machine attributes. */
16071 const struct attribute_spec rs6000_attribute_table[] =
16073 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
16074 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
16075 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
16076 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
16077 { NULL, 0, 0, false, false, false, NULL }
16080 /* Handle the "altivec" attribute. The attribute may have
16081 arguments as follows:
16083 __attribute__((altivec(vector__)))
16084 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
16085 __attribute__((altivec(bool__))) (always followed by 'unsigned')
16087 and may appear more than once (e.g., 'vector bool char') in a
16088 given declaration. */
16090 static tree
16091 rs6000_handle_altivec_attribute (tree *node, tree name, tree args,
16092 int flags ATTRIBUTE_UNUSED,
16093 bool *no_add_attrs)
16095 tree type = *node, result = NULL_TREE;
16096 enum machine_mode mode;
16097 int unsigned_p;
16098 char altivec_type
16099 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
16100 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
16101 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
16102 : '?');
16104 while (POINTER_TYPE_P (type)
16105 || TREE_CODE (type) == FUNCTION_TYPE
16106 || TREE_CODE (type) == METHOD_TYPE
16107 || TREE_CODE (type) == ARRAY_TYPE)
16108 type = TREE_TYPE (type);
16110 mode = TYPE_MODE (type);
16112 if (rs6000_warn_altivec_long
16113 && (type == long_unsigned_type_node || type == long_integer_type_node))
16114 warning ("use of 'long' in AltiVec types is deprecated; use 'int'");
16116 switch (altivec_type)
16118 case 'v':
16119 unsigned_p = TYPE_UNSIGNED (type);
16120 switch (mode)
16122 case SImode:
16123 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
16124 break;
16125 case HImode:
16126 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
16127 break;
16128 case QImode:
16129 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
16130 break;
16131 case SFmode: result = V4SF_type_node; break;
16132 /* If the user says 'vector int bool', we may be handed the 'bool'
16133 attribute _before_ the 'vector' attribute, and so select the proper
16134 type in the 'b' case below. */
16135 case V4SImode: case V8HImode: case V16QImode: result = type;
16136 default: break;
16138 break;
16139 case 'b':
16140 switch (mode)
16142 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
16143 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
16144 case QImode: case V16QImode: result = bool_V16QI_type_node;
16145 default: break;
16147 break;
16148 case 'p':
16149 switch (mode)
16151 case V8HImode: result = pixel_V8HI_type_node;
16152 default: break;
16154 default: break;
16157 if (result && result != type && TYPE_READONLY (type))
16158 result = build_qualified_type (result, TYPE_QUAL_CONST);
16160 *no_add_attrs = true; /* No need to hang on to the attribute. */
16162 if (!result)
16163 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name));
16164 else
16165 *node = reconstruct_complex_type (*node, result);
16167 return NULL_TREE;
16170 /* AltiVec defines four built-in scalar types that serve as vector
16171 elements; we must teach the compiler how to mangle them. */
16173 static const char *
16174 rs6000_mangle_fundamental_type (tree type)
16176 if (type == bool_char_type_node) return "U6__boolc";
16177 if (type == bool_short_type_node) return "U6__bools";
16178 if (type == pixel_type_node) return "u7__pixel";
16179 if (type == bool_int_type_node) return "U6__booli";
16181 /* For all other types, use normal C++ mangling. */
16182 return NULL;
16185 /* Handle a "longcall" or "shortcall" attribute; arguments as in
16186 struct attribute_spec.handler. */
16188 static tree
16189 rs6000_handle_longcall_attribute (tree *node, tree name,
16190 tree args ATTRIBUTE_UNUSED,
16191 int flags ATTRIBUTE_UNUSED,
16192 bool *no_add_attrs)
16194 if (TREE_CODE (*node) != FUNCTION_TYPE
16195 && TREE_CODE (*node) != FIELD_DECL
16196 && TREE_CODE (*node) != TYPE_DECL)
16198 warning ("`%s' attribute only applies to functions",
16199 IDENTIFIER_POINTER (name));
16200 *no_add_attrs = true;
16203 return NULL_TREE;
16206 /* Set longcall attributes on all functions declared when
16207 rs6000_default_long_calls is true. */
16208 static void
16209 rs6000_set_default_type_attributes (tree type)
16211 if (rs6000_default_long_calls
16212 && (TREE_CODE (type) == FUNCTION_TYPE
16213 || TREE_CODE (type) == METHOD_TYPE))
16214 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
16215 NULL_TREE,
16216 TYPE_ATTRIBUTES (type));
16219 /* Return a reference suitable for calling a function with the
16220 longcall attribute. */
16222 struct rtx_def *
16223 rs6000_longcall_ref (rtx call_ref)
16225 const char *call_name;
16226 tree node;
16228 if (GET_CODE (call_ref) != SYMBOL_REF)
16229 return call_ref;
16231 /* System V adds '.' to the internal name, so skip them. */
16232 call_name = XSTR (call_ref, 0);
16233 if (*call_name == '.')
16235 while (*call_name == '.')
16236 call_name++;
16238 node = get_identifier (call_name);
16239 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
16242 return force_reg (Pmode, call_ref);
16245 #ifdef USING_ELFOS_H
16247 /* A C statement or statements to switch to the appropriate section
16248 for output of RTX in mode MODE. You can assume that RTX is some
16249 kind of constant in RTL. The argument MODE is redundant except in
16250 the case of a `const_int' rtx. Select the section by calling
16251 `text_section' or one of the alternatives for other sections.
16253 Do not define this macro if you put all constants in the read-only
16254 data section. */
16256 static void
16257 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
16258 unsigned HOST_WIDE_INT align)
16260 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
16261 toc_section ();
16262 else
16263 default_elf_select_rtx_section (mode, x, align);
16266 /* A C statement or statements to switch to the appropriate
16267 section for output of DECL. DECL is either a `VAR_DECL' node
16268 or a constant of some sort. RELOC indicates whether forming
16269 the initial value of DECL requires link-time relocations. */
16271 static void
16272 rs6000_elf_select_section (tree decl, int reloc,
16273 unsigned HOST_WIDE_INT align)
16275 /* Pretend that we're always building for a shared library when
16276 ABI_AIX, because otherwise we end up with dynamic relocations
16277 in read-only sections. This happens for function pointers,
16278 references to vtables in typeinfo, and probably other cases. */
16279 default_elf_select_section_1 (decl, reloc, align,
16280 flag_pic || DEFAULT_ABI == ABI_AIX);
16283 /* A C statement to build up a unique section name, expressed as a
16284 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
16285 RELOC indicates whether the initial value of EXP requires
16286 link-time relocations. If you do not define this macro, GCC will use
16287 the symbol name prefixed by `.' as the section name. Note - this
16288 macro can now be called for uninitialized data items as well as
16289 initialized data and functions. */
16291 static void
16292 rs6000_elf_unique_section (tree decl, int reloc)
16294 /* As above, pretend that we're always building for a shared library
16295 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
16296 default_unique_section_1 (decl, reloc,
16297 flag_pic || DEFAULT_ABI == ABI_AIX);
16300 /* For a SYMBOL_REF, set generic flags and then perform some
16301 target-specific processing.
16303 When the AIX ABI is requested on a non-AIX system, replace the
16304 function name with the real name (with a leading .) rather than the
16305 function descriptor name. This saves a lot of overriding code to
16306 read the prefixes. */
16308 static void
16309 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
16311 default_encode_section_info (decl, rtl, first);
16313 if (first
16314 && TREE_CODE (decl) == FUNCTION_DECL
16315 && !TARGET_AIX
16316 && DEFAULT_ABI == ABI_AIX)
16318 rtx sym_ref = XEXP (rtl, 0);
16319 size_t len = strlen (XSTR (sym_ref, 0));
16320 char *str = alloca (len + 2);
16321 str[0] = '.';
16322 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
16323 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
16327 static bool
16328 rs6000_elf_in_small_data_p (tree decl)
16330 if (rs6000_sdata == SDATA_NONE)
16331 return false;
16333 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
16335 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
16336 if (strcmp (section, ".sdata") == 0
16337 || strcmp (section, ".sdata2") == 0
16338 || strcmp (section, ".sbss") == 0
16339 || strcmp (section, ".sbss2") == 0
16340 || strcmp (section, ".PPC.EMB.sdata0") == 0
16341 || strcmp (section, ".PPC.EMB.sbss0") == 0)
16342 return true;
16344 else
16346 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
16348 if (size > 0
16349 && (unsigned HOST_WIDE_INT) size <= g_switch_value
16350 /* If it's not public, and we're not going to reference it there,
16351 there's no need to put it in the small data section. */
16352 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
16353 return true;
16356 return false;
16359 #endif /* USING_ELFOS_H */
16362 /* Return a REG that occurs in ADDR with coefficient 1.
16363 ADDR can be effectively incremented by incrementing REG.
16365 r0 is special and we must not select it as an address
16366 register by this routine since our caller will try to
16367 increment the returned register via an "la" instruction. */
16369 struct rtx_def *
16370 find_addr_reg (rtx addr)
16372 while (GET_CODE (addr) == PLUS)
16374 if (GET_CODE (XEXP (addr, 0)) == REG
16375 && REGNO (XEXP (addr, 0)) != 0)
16376 addr = XEXP (addr, 0);
16377 else if (GET_CODE (XEXP (addr, 1)) == REG
16378 && REGNO (XEXP (addr, 1)) != 0)
16379 addr = XEXP (addr, 1);
16380 else if (CONSTANT_P (XEXP (addr, 0)))
16381 addr = XEXP (addr, 1);
16382 else if (CONSTANT_P (XEXP (addr, 1)))
16383 addr = XEXP (addr, 0);
16384 else
16385 abort ();
16387 if (GET_CODE (addr) == REG && REGNO (addr) != 0)
16388 return addr;
16389 abort ();
16392 void
16393 rs6000_fatal_bad_address (rtx op)
16395 fatal_insn ("bad address", op);
16398 #if TARGET_MACHO
16400 #if 0
16401 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
16402 reference and a constant. */
16405 symbolic_operand (rtx op)
16407 switch (GET_CODE (op))
16409 case SYMBOL_REF:
16410 case LABEL_REF:
16411 return 1;
16412 case CONST:
16413 op = XEXP (op, 0);
16414 return (GET_CODE (op) == SYMBOL_REF ||
16415 (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
16416 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
16417 && GET_CODE (XEXP (op, 1)) == CONST_INT);
16418 default:
16419 return 0;
16422 #endif
16424 #if TARGET_MACHO
16426 static tree branch_island_list = 0;
16428 /* Remember to generate a branch island for far calls to the given
16429 function. */
16431 static void
16432 add_compiler_branch_island (tree label_name, tree function_name, int line_number)
16434 tree branch_island = build_tree_list (function_name, label_name);
16435 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number, 0);
16436 TREE_CHAIN (branch_island) = branch_island_list;
16437 branch_island_list = branch_island;
16440 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
16441 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
16442 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
16443 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
16445 /* Generate far-jump branch islands for everything on the
16446 branch_island_list. Invoked immediately after the last instruction
16447 of the epilogue has been emitted; the branch-islands must be
16448 appended to, and contiguous with, the function body. Mach-O stubs
16449 are generated in machopic_output_stub(). */
16451 static void
16452 macho_branch_islands (void)
16454 char tmp_buf[512];
16455 tree branch_island;
16457 for (branch_island = branch_island_list;
16458 branch_island;
16459 branch_island = TREE_CHAIN (branch_island))
16461 const char *label =
16462 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
16463 const char *name =
16464 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
16465 char name_buf[512];
16466 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
16467 if (name[0] == '*' || name[0] == '&')
16468 strcpy (name_buf, name+1);
16469 else
16471 name_buf[0] = '_';
16472 strcpy (name_buf+1, name);
16474 strcpy (tmp_buf, "\n");
16475 strcat (tmp_buf, label);
16476 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
16477 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
16478 fprintf (asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n",
16479 BRANCH_ISLAND_LINE_NUMBER(branch_island));
16480 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
16481 if (flag_pic)
16483 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
16484 strcat (tmp_buf, label);
16485 strcat (tmp_buf, "_pic\n");
16486 strcat (tmp_buf, label);
16487 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
16489 strcat (tmp_buf, "\taddis r11,r11,ha16(");
16490 strcat (tmp_buf, name_buf);
16491 strcat (tmp_buf, " - ");
16492 strcat (tmp_buf, label);
16493 strcat (tmp_buf, "_pic)\n");
16495 strcat (tmp_buf, "\tmtlr r0\n");
16497 strcat (tmp_buf, "\taddi r12,r11,lo16(");
16498 strcat (tmp_buf, name_buf);
16499 strcat (tmp_buf, " - ");
16500 strcat (tmp_buf, label);
16501 strcat (tmp_buf, "_pic)\n");
16503 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
16505 else
16507 strcat (tmp_buf, ":\nlis r12,hi16(");
16508 strcat (tmp_buf, name_buf);
16509 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
16510 strcat (tmp_buf, name_buf);
16511 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
16513 output_asm_insn (tmp_buf, 0);
16514 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
16515 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
16516 fprintf(asm_out_file, "\t.stabd 68,0," HOST_WIDE_INT_PRINT_UNSIGNED "\n",
16517 BRANCH_ISLAND_LINE_NUMBER (branch_island));
16518 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
16521 branch_island_list = 0;
16524 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
16525 already there or not. */
16527 static int
16528 no_previous_def (tree function_name)
16530 tree branch_island;
16531 for (branch_island = branch_island_list;
16532 branch_island;
16533 branch_island = TREE_CHAIN (branch_island))
16534 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
16535 return 0;
16536 return 1;
16539 /* GET_PREV_LABEL gets the label name from the previous definition of
16540 the function. */
16542 static tree
16543 get_prev_label (tree function_name)
16545 tree branch_island;
16546 for (branch_island = branch_island_list;
16547 branch_island;
16548 branch_island = TREE_CHAIN (branch_island))
16549 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
16550 return BRANCH_ISLAND_LABEL_NAME (branch_island);
16551 return 0;
16554 /* INSN is either a function call or a millicode call. It may have an
16555 unconditional jump in its delay slot.
16557 CALL_DEST is the routine we are calling. */
16559 char *
16560 output_call (rtx insn, rtx *operands, int dest_operand_number, int cookie_operand_number)
16562 static char buf[256];
16563 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
16564 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
16566 tree labelname;
16567 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
16569 if (no_previous_def (funname))
16571 int line_number = 0;
16572 rtx label_rtx = gen_label_rtx ();
16573 char *label_buf, temp_buf[256];
16574 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
16575 CODE_LABEL_NUMBER (label_rtx));
16576 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
16577 labelname = get_identifier (label_buf);
16578 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
16579 if (insn)
16580 line_number = NOTE_LINE_NUMBER (insn);
16581 add_compiler_branch_island (labelname, funname, line_number);
16583 else
16584 labelname = get_prev_label (funname);
16586 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
16587 instruction will reach 'foo', otherwise link as 'bl L42'".
16588 "L42" should be a 'branch island', that will do a far jump to
16589 'foo'. Branch islands are generated in
16590 macho_branch_islands(). */
16591 sprintf (buf, "jbsr %%z%d,%.246s",
16592 dest_operand_number, IDENTIFIER_POINTER (labelname));
16594 else
16595 sprintf (buf, "bl %%z%d", dest_operand_number);
16596 return buf;
16599 #endif /* TARGET_MACHO */
16601 /* Generate PIC and indirect symbol stubs. */
16603 void
16604 machopic_output_stub (FILE *file, const char *symb, const char *stub)
16606 unsigned int length;
16607 char *symbol_name, *lazy_ptr_name;
16608 char *local_label_0;
16609 static int label = 0;
16611 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
16612 symb = (*targetm.strip_name_encoding) (symb);
16615 length = strlen (symb);
16616 symbol_name = alloca (length + 32);
16617 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
16619 lazy_ptr_name = alloca (length + 32);
16620 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
16622 if (flag_pic == 2)
16623 machopic_picsymbol_stub1_section ();
16624 else
16625 machopic_symbol_stub1_section ();
16627 if (flag_pic == 2)
16629 fprintf (file, "\t.align 5\n");
16631 fprintf (file, "%s:\n", stub);
16632 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16634 label++;
16635 local_label_0 = alloca (sizeof("\"L0000000000$spb\""));
16636 sprintf (local_label_0, "\"L%011d$spb\"", label);
16638 fprintf (file, "\tmflr r0\n");
16639 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
16640 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
16641 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
16642 lazy_ptr_name, local_label_0);
16643 fprintf (file, "\tmtlr r0\n");
16644 fprintf (file, "\tlwzu r12,lo16(%s-%s)(r11)\n",
16645 lazy_ptr_name, local_label_0);
16646 fprintf (file, "\tmtctr r12\n");
16647 fprintf (file, "\tbctr\n");
16649 else
16651 fprintf (file, "\t.align 4\n");
16653 fprintf (file, "%s:\n", stub);
16654 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16656 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
16657 fprintf (file, "\tlwzu r12,lo16(%s)(r11)\n", lazy_ptr_name);
16658 fprintf (file, "\tmtctr r12\n");
16659 fprintf (file, "\tbctr\n");
16662 machopic_lazy_symbol_ptr_section ();
16663 fprintf (file, "%s:\n", lazy_ptr_name);
16664 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16665 fprintf (file, "%sdyld_stub_binding_helper\n",
16666 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
16669 /* Legitimize PIC addresses. If the address is already
16670 position-independent, we return ORIG. Newly generated
16671 position-independent addresses go into a reg. This is REG if non
16672 zero, otherwise we allocate register(s) as necessary. */
16674 #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000)
16677 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
16678 rtx reg)
16680 rtx base, offset;
16682 if (reg == NULL && ! reload_in_progress && ! reload_completed)
16683 reg = gen_reg_rtx (Pmode);
16685 if (GET_CODE (orig) == CONST)
16687 if (GET_CODE (XEXP (orig, 0)) == PLUS
16688 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
16689 return orig;
16691 if (GET_CODE (XEXP (orig, 0)) == PLUS)
16693 /* Use a different reg for the intermediate value, as
16694 it will be marked UNCHANGING. */
16695 rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
16697 base =
16698 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
16699 Pmode, reg_temp);
16700 offset =
16701 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
16702 Pmode, reg);
16704 else
16705 abort ();
16707 if (GET_CODE (offset) == CONST_INT)
16709 if (SMALL_INT (offset))
16710 return plus_constant (base, INTVAL (offset));
16711 else if (! reload_in_progress && ! reload_completed)
16712 offset = force_reg (Pmode, offset);
16713 else
16715 rtx mem = force_const_mem (Pmode, orig);
16716 return machopic_legitimize_pic_address (mem, Pmode, reg);
16719 return gen_rtx_PLUS (Pmode, base, offset);
16722 /* Fall back on generic machopic code. */
16723 return machopic_legitimize_pic_address (orig, mode, reg);
16726 /* This is just a placeholder to make linking work without having to
16727 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
16728 ever needed for Darwin (not too likely!) this would have to get a
16729 real definition. */
16731 void
16732 toc_section (void)
16736 #endif /* TARGET_MACHO */
16738 #if TARGET_ELF
16739 static unsigned int
16740 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
16742 return default_section_type_flags_1 (decl, name, reloc,
16743 flag_pic || DEFAULT_ABI == ABI_AIX);
16746 /* Record an element in the table of global constructors. SYMBOL is
16747 a SYMBOL_REF of the function to be called; PRIORITY is a number
16748 between 0 and MAX_INIT_PRIORITY.
16750 This differs from default_named_section_asm_out_constructor in
16751 that we have special handling for -mrelocatable. */
16753 static void
16754 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
16756 const char *section = ".ctors";
16757 char buf[16];
16759 if (priority != DEFAULT_INIT_PRIORITY)
16761 sprintf (buf, ".ctors.%.5u",
16762 /* Invert the numbering so the linker puts us in the proper
16763 order; constructors are run from right to left, and the
16764 linker sorts in increasing order. */
16765 MAX_INIT_PRIORITY - priority);
16766 section = buf;
16769 named_section_flags (section, SECTION_WRITE);
16770 assemble_align (POINTER_SIZE);
16772 if (TARGET_RELOCATABLE)
16774 fputs ("\t.long (", asm_out_file);
16775 output_addr_const (asm_out_file, symbol);
16776 fputs (")@fixup\n", asm_out_file);
16778 else
16779 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
16782 static void
16783 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
16785 const char *section = ".dtors";
16786 char buf[16];
16788 if (priority != DEFAULT_INIT_PRIORITY)
16790 sprintf (buf, ".dtors.%.5u",
16791 /* Invert the numbering so the linker puts us in the proper
16792 order; constructors are run from right to left, and the
16793 linker sorts in increasing order. */
16794 MAX_INIT_PRIORITY - priority);
16795 section = buf;
16798 named_section_flags (section, SECTION_WRITE);
16799 assemble_align (POINTER_SIZE);
16801 if (TARGET_RELOCATABLE)
16803 fputs ("\t.long (", asm_out_file);
16804 output_addr_const (asm_out_file, symbol);
16805 fputs (")@fixup\n", asm_out_file);
16807 else
16808 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
16811 void
16812 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
16814 if (TARGET_64BIT)
16816 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
16817 ASM_OUTPUT_LABEL (file, name);
16818 fputs (DOUBLE_INT_ASM_OP, file);
16819 rs6000_output_function_entry (file, name);
16820 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
16821 if (DOT_SYMBOLS)
16823 fputs ("\t.size\t", file);
16824 assemble_name (file, name);
16825 fputs (",24\n\t.type\t.", file);
16826 assemble_name (file, name);
16827 fputs (",@function\n", file);
16828 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
16830 fputs ("\t.globl\t.", file);
16831 assemble_name (file, name);
16832 putc ('\n', file);
16835 else
16836 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
16837 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
16838 rs6000_output_function_entry (file, name);
16839 fputs (":\n", file);
16840 return;
16843 if (TARGET_RELOCATABLE
16844 && (get_pool_size () != 0 || current_function_profile)
16845 && uses_TOC ())
16847 char buf[256];
16849 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
16851 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
16852 fprintf (file, "\t.long ");
16853 assemble_name (file, buf);
16854 putc ('-', file);
16855 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
16856 assemble_name (file, buf);
16857 putc ('\n', file);
16860 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
16861 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
16863 if (DEFAULT_ABI == ABI_AIX)
16865 const char *desc_name, *orig_name;
16867 orig_name = (*targetm.strip_name_encoding) (name);
16868 desc_name = orig_name;
16869 while (*desc_name == '.')
16870 desc_name++;
16872 if (TREE_PUBLIC (decl))
16873 fprintf (file, "\t.globl %s\n", desc_name);
16875 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
16876 fprintf (file, "%s:\n", desc_name);
16877 fprintf (file, "\t.long %s\n", orig_name);
16878 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
16879 if (DEFAULT_ABI == ABI_AIX)
16880 fputs ("\t.long 0\n", file);
16881 fprintf (file, "\t.previous\n");
16883 ASM_OUTPUT_LABEL (file, name);
16885 #endif
16887 #if TARGET_XCOFF
16888 static void
16889 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
16891 fputs (GLOBAL_ASM_OP, stream);
16892 RS6000_OUTPUT_BASENAME (stream, name);
16893 putc ('\n', stream);
16896 static void
16897 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags)
16899 int smclass;
16900 static const char * const suffix[3] = { "PR", "RO", "RW" };
16902 if (flags & SECTION_CODE)
16903 smclass = 0;
16904 else if (flags & SECTION_WRITE)
16905 smclass = 2;
16906 else
16907 smclass = 1;
16909 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
16910 (flags & SECTION_CODE) ? "." : "",
16911 name, suffix[smclass], flags & SECTION_ENTSIZE);
16914 static void
16915 rs6000_xcoff_select_section (tree decl, int reloc,
16916 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
16918 if (decl_readonly_section_1 (decl, reloc, 1))
16920 if (TREE_PUBLIC (decl))
16921 read_only_data_section ();
16922 else
16923 read_only_private_data_section ();
16925 else
16927 if (TREE_PUBLIC (decl))
16928 data_section ();
16929 else
16930 private_data_section ();
16934 static void
16935 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
16937 const char *name;
16939 /* Use select_section for private and uninitialized data. */
16940 if (!TREE_PUBLIC (decl)
16941 || DECL_COMMON (decl)
16942 || DECL_INITIAL (decl) == NULL_TREE
16943 || DECL_INITIAL (decl) == error_mark_node
16944 || (flag_zero_initialized_in_bss
16945 && initializer_zerop (DECL_INITIAL (decl))))
16946 return;
16948 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
16949 name = (*targetm.strip_name_encoding) (name);
16950 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
16953 /* Select section for constant in constant pool.
16955 On RS/6000, all constants are in the private read-only data area.
16956 However, if this is being placed in the TOC it must be output as a
16957 toc entry. */
16959 static void
16960 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
16961 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
16963 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
16964 toc_section ();
16965 else
16966 read_only_private_data_section ();
16969 /* Remove any trailing [DS] or the like from the symbol name. */
16971 static const char *
16972 rs6000_xcoff_strip_name_encoding (const char *name)
16974 size_t len;
16975 if (*name == '*')
16976 name++;
16977 len = strlen (name);
16978 if (name[len - 1] == ']')
16979 return ggc_alloc_string (name, len - 4);
16980 else
16981 return name;
16984 /* Section attributes. AIX is always PIC. */
16986 static unsigned int
16987 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
16989 unsigned int align;
16990 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
16992 /* Align to at least UNIT size. */
16993 if (flags & SECTION_CODE)
16994 align = MIN_UNITS_PER_WORD;
16995 else
16996 /* Increase alignment of large objects if not already stricter. */
16997 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
16998 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
16999 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
17001 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
17004 /* Output at beginning of assembler file.
17006 Initialize the section names for the RS/6000 at this point.
17008 Specify filename, including full path, to assembler.
17010 We want to go into the TOC section so at least one .toc will be emitted.
17011 Also, in order to output proper .bs/.es pairs, we need at least one static
17012 [RW] section emitted.
17014 Finally, declare mcount when profiling to make the assembler happy. */
17016 static void
17017 rs6000_xcoff_file_start (void)
17019 rs6000_gen_section_name (&xcoff_bss_section_name,
17020 main_input_filename, ".bss_");
17021 rs6000_gen_section_name (&xcoff_private_data_section_name,
17022 main_input_filename, ".rw_");
17023 rs6000_gen_section_name (&xcoff_read_only_section_name,
17024 main_input_filename, ".ro_");
17026 fputs ("\t.file\t", asm_out_file);
17027 output_quoted_string (asm_out_file, main_input_filename);
17028 fputc ('\n', asm_out_file);
17029 toc_section ();
17030 if (write_symbols != NO_DEBUG)
17031 private_data_section ();
17032 text_section ();
17033 if (profile_flag)
17034 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
17035 rs6000_file_start ();
17038 /* Output at end of assembler file.
17039 On the RS/6000, referencing data should automatically pull in text. */
17041 static void
17042 rs6000_xcoff_file_end (void)
17044 text_section ();
17045 fputs ("_section_.text:\n", asm_out_file);
17046 data_section ();
17047 fputs (TARGET_32BIT
17048 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
17049 asm_out_file);
17051 #endif /* TARGET_XCOFF */
17053 #if TARGET_MACHO
17054 /* Cross-module name binding. Darwin does not support overriding
17055 functions at dynamic-link time. */
17057 static bool
17058 rs6000_binds_local_p (tree decl)
17060 return default_binds_local_p_1 (decl, 0);
17062 #endif
17064 /* Compute a (partial) cost for rtx X. Return true if the complete
17065 cost has been computed, and false if subexpressions should be
17066 scanned. In either case, *TOTAL contains the cost result. */
17068 static bool
17069 rs6000_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED,
17070 int *total)
17072 enum machine_mode mode = GET_MODE (x);
17074 switch (code)
17076 /* On the RS/6000, if it is valid in the insn, it is free. */
17077 case CONST_INT:
17078 if (((outer_code == SET
17079 || outer_code == PLUS
17080 || outer_code == MINUS)
17081 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
17082 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
17083 || ((outer_code == IOR || outer_code == XOR)
17084 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
17085 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
17086 || ((outer_code == DIV || outer_code == UDIV
17087 || outer_code == MOD || outer_code == UMOD)
17088 && exact_log2 (INTVAL (x)) >= 0)
17089 || (outer_code == AND
17090 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
17091 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
17092 || mask_operand (x, VOIDmode)))
17093 || outer_code == ASHIFT
17094 || outer_code == ASHIFTRT
17095 || outer_code == LSHIFTRT
17096 || outer_code == ROTATE
17097 || outer_code == ROTATERT
17098 || outer_code == ZERO_EXTRACT
17099 || (outer_code == MULT
17100 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
17101 || (outer_code == COMPARE
17102 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
17103 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K'))))
17105 *total = 0;
17106 return true;
17108 else if ((outer_code == PLUS
17109 && reg_or_add_cint64_operand (x, VOIDmode))
17110 || (outer_code == MINUS
17111 && reg_or_sub_cint64_operand (x, VOIDmode))
17112 || ((outer_code == SET
17113 || outer_code == IOR
17114 || outer_code == XOR)
17115 && (INTVAL (x)
17116 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
17118 *total = COSTS_N_INSNS (1);
17119 return true;
17121 /* FALLTHRU */
17123 case CONST_DOUBLE:
17124 if (mode == DImode
17125 && ((outer_code == AND
17126 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
17127 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
17128 || mask64_operand (x, DImode)))
17129 || ((outer_code == IOR || outer_code == XOR)
17130 && CONST_DOUBLE_HIGH (x) == 0
17131 && (CONST_DOUBLE_LOW (x)
17132 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
17134 *total = 0;
17135 return true;
17137 else if (mode == DImode
17138 && (outer_code == SET
17139 || outer_code == IOR
17140 || outer_code == XOR)
17141 && CONST_DOUBLE_HIGH (x) == 0)
17143 *total = COSTS_N_INSNS (1);
17144 return true;
17146 /* FALLTHRU */
17148 case CONST:
17149 case HIGH:
17150 case SYMBOL_REF:
17151 case MEM:
17152 /* When optimizing for size, MEM should be slightly more expensive
17153 than generating address, e.g., (plus (reg) (const)).
17154 L1 cache latecy is about two instructions. */
17155 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
17156 return true;
17158 case LABEL_REF:
17159 *total = 0;
17160 return true;
17162 case PLUS:
17163 if (mode == DFmode)
17165 if (GET_CODE (XEXP (x, 0)) == MULT)
17167 /* FNMA accounted in outer NEG. */
17168 if (outer_code == NEG)
17169 *total = rs6000_cost->dmul - rs6000_cost->fp;
17170 else
17171 *total = rs6000_cost->dmul;
17173 else
17174 *total = rs6000_cost->fp;
17176 else if (mode == SFmode)
17178 /* FNMA accounted in outer NEG. */
17179 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
17180 *total = 0;
17181 else
17182 *total = rs6000_cost->fp;
17184 else if (GET_CODE (XEXP (x, 0)) == MULT)
17186 /* The rs6000 doesn't have shift-and-add instructions. */
17187 rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total);
17188 *total += COSTS_N_INSNS (1);
17190 else
17191 *total = COSTS_N_INSNS (1);
17192 return false;
17194 case MINUS:
17195 if (mode == DFmode)
17197 if (GET_CODE (XEXP (x, 0)) == MULT)
17199 /* FNMA accounted in outer NEG. */
17200 if (outer_code == NEG)
17201 *total = 0;
17202 else
17203 *total = rs6000_cost->dmul;
17205 else
17206 *total = rs6000_cost->fp;
17208 else if (mode == SFmode)
17210 /* FNMA accounted in outer NEG. */
17211 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
17212 *total = 0;
17213 else
17214 *total = rs6000_cost->fp;
17216 else if (GET_CODE (XEXP (x, 0)) == MULT)
17218 /* The rs6000 doesn't have shift-and-sub instructions. */
17219 rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total);
17220 *total += COSTS_N_INSNS (1);
17222 else
17223 *total = COSTS_N_INSNS (1);
17224 return false;
17226 case MULT:
17227 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
17229 if (INTVAL (XEXP (x, 1)) >= -256
17230 && INTVAL (XEXP (x, 1)) <= 255)
17231 *total = rs6000_cost->mulsi_const9;
17232 else
17233 *total = rs6000_cost->mulsi_const;
17235 /* FMA accounted in outer PLUS/MINUS. */
17236 else if ((mode == DFmode || mode == SFmode)
17237 && (outer_code == PLUS || outer_code == MINUS))
17238 *total = 0;
17239 else if (mode == DFmode)
17240 *total = rs6000_cost->dmul;
17241 else if (mode == SFmode)
17242 *total = rs6000_cost->fp;
17243 else if (mode == DImode)
17244 *total = rs6000_cost->muldi;
17245 else
17246 *total = rs6000_cost->mulsi;
17247 return false;
17249 case DIV:
17250 case MOD:
17251 if (FLOAT_MODE_P (mode))
17253 *total = mode == DFmode ? rs6000_cost->ddiv
17254 : rs6000_cost->sdiv;
17255 return false;
17257 /* FALLTHRU */
17259 case UDIV:
17260 case UMOD:
17261 if (GET_CODE (XEXP (x, 1)) == CONST_INT
17262 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
17264 if (code == DIV || code == MOD)
17265 /* Shift, addze */
17266 *total = COSTS_N_INSNS (2);
17267 else
17268 /* Shift */
17269 *total = COSTS_N_INSNS (1);
17271 else
17273 if (GET_MODE (XEXP (x, 1)) == DImode)
17274 *total = rs6000_cost->divdi;
17275 else
17276 *total = rs6000_cost->divsi;
17278 /* Add in shift and subtract for MOD. */
17279 if (code == MOD || code == UMOD)
17280 *total += COSTS_N_INSNS (2);
17281 return false;
17283 case FFS:
17284 *total = COSTS_N_INSNS (4);
17285 return false;
17287 case NOT:
17288 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
17290 *total = 0;
17291 return false;
17293 /* FALLTHRU */
17295 case AND:
17296 case IOR:
17297 case XOR:
17298 case ZERO_EXTRACT:
17299 *total = COSTS_N_INSNS (1);
17300 return false;
17302 case ASHIFT:
17303 case ASHIFTRT:
17304 case LSHIFTRT:
17305 case ROTATE:
17306 case ROTATERT:
17307 /* Handle mul_highpart. */
17308 if (outer_code == TRUNCATE
17309 && GET_CODE (XEXP (x, 0)) == MULT)
17311 if (mode == DImode)
17312 *total = rs6000_cost->muldi;
17313 else
17314 *total = rs6000_cost->mulsi;
17315 return true;
17317 else if (outer_code == AND)
17318 *total = 0;
17319 else
17320 *total = COSTS_N_INSNS (1);
17321 return false;
17323 case SIGN_EXTEND:
17324 case ZERO_EXTEND:
17325 if (GET_CODE (XEXP (x, 0)) == MEM)
17326 *total = 0;
17327 else
17328 *total = COSTS_N_INSNS (1);
17329 return false;
17331 case COMPARE:
17332 case NEG:
17333 case ABS:
17334 if (!FLOAT_MODE_P (mode))
17336 *total = COSTS_N_INSNS (1);
17337 return false;
17339 /* FALLTHRU */
17341 case FLOAT:
17342 case UNSIGNED_FLOAT:
17343 case FIX:
17344 case UNSIGNED_FIX:
17345 case FLOAT_EXTEND:
17346 case FLOAT_TRUNCATE:
17347 *total = rs6000_cost->fp;
17348 return false;
17350 case UNSPEC:
17351 switch (XINT (x, 1))
17353 case UNSPEC_FRSP:
17354 *total = rs6000_cost->fp;
17355 return true;
17357 default:
17358 break;
17360 break;
17362 case CALL:
17363 case IF_THEN_ELSE:
17364 if (optimize_size)
17366 *total = COSTS_N_INSNS (1);
17367 return true;
17369 else if (FLOAT_MODE_P (mode)
17370 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
17372 *total = rs6000_cost->fp;
17373 return false;
17376 break;
17378 default:
17379 break;
17382 return false;
17385 /* A C expression returning the cost of moving data from a register of class
17386 CLASS1 to one of CLASS2. */
17389 rs6000_register_move_cost (enum machine_mode mode,
17390 enum reg_class from, enum reg_class to)
17392 /* Moves from/to GENERAL_REGS. */
17393 if (reg_classes_intersect_p (to, GENERAL_REGS)
17394 || reg_classes_intersect_p (from, GENERAL_REGS))
17396 if (! reg_classes_intersect_p (to, GENERAL_REGS))
17397 from = to;
17399 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
17400 return (rs6000_memory_move_cost (mode, from, 0)
17401 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
17403 /* It's more expensive to move CR_REGS than CR0_REGS because of the shift.... */
17404 else if (from == CR_REGS)
17405 return 4;
17407 else
17408 /* A move will cost one instruction per GPR moved. */
17409 return 2 * HARD_REGNO_NREGS (0, mode);
17412 /* Moving between two similar registers is just one instruction. */
17413 else if (reg_classes_intersect_p (to, from))
17414 return mode == TFmode ? 4 : 2;
17416 /* Everything else has to go through GENERAL_REGS. */
17417 else
17418 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
17419 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
17422 /* A C expressions returning the cost of moving data of MODE from a register to
17423 or from memory. */
17426 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
17427 int in ATTRIBUTE_UNUSED)
17429 if (reg_classes_intersect_p (class, GENERAL_REGS))
17430 return 4 * HARD_REGNO_NREGS (0, mode);
17431 else if (reg_classes_intersect_p (class, FLOAT_REGS))
17432 return 4 * HARD_REGNO_NREGS (32, mode);
17433 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
17434 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
17435 else
17436 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
17439 /* Return an RTX representing where to find the function value of a
17440 function returning MODE. */
17441 static rtx
17442 rs6000_complex_function_value (enum machine_mode mode)
17444 unsigned int regno;
17445 rtx r1, r2;
17446 enum machine_mode inner = GET_MODE_INNER (mode);
17447 unsigned int inner_bytes = GET_MODE_SIZE (inner);
17449 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
17450 regno = FP_ARG_RETURN;
17451 else
17453 regno = GP_ARG_RETURN;
17455 /* 32-bit is OK since it'll go in r3/r4. */
17456 if (TARGET_32BIT && inner_bytes >= 4)
17457 return gen_rtx_REG (mode, regno);
17460 if (inner_bytes >= 8)
17461 return gen_rtx_REG (mode, regno);
17463 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
17464 const0_rtx);
17465 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
17466 GEN_INT (inner_bytes));
17467 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
17470 /* Define how to find the value returned by a function.
17471 VALTYPE is the data type of the value (as a tree).
17472 If the precise function being called is known, FUNC is its FUNCTION_DECL;
17473 otherwise, FUNC is 0.
17475 On the SPE, both FPs and vectors are returned in r3.
17477 On RS/6000 an integer value is in r3 and a floating-point value is in
17478 fp1, unless -msoft-float. */
17481 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
17483 enum machine_mode mode;
17484 unsigned int regno;
17486 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
17488 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
17489 return gen_rtx_PARALLEL (DImode,
17490 gen_rtvec (2,
17491 gen_rtx_EXPR_LIST (VOIDmode,
17492 gen_rtx_REG (SImode, GP_ARG_RETURN),
17493 const0_rtx),
17494 gen_rtx_EXPR_LIST (VOIDmode,
17495 gen_rtx_REG (SImode,
17496 GP_ARG_RETURN + 1),
17497 GEN_INT (4))));
17500 if ((INTEGRAL_TYPE_P (valtype)
17501 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
17502 || POINTER_TYPE_P (valtype))
17503 mode = TARGET_32BIT ? SImode : DImode;
17504 else
17505 mode = TYPE_MODE (valtype);
17507 if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
17508 regno = FP_ARG_RETURN;
17509 else if (TREE_CODE (valtype) == COMPLEX_TYPE
17510 && targetm.calls.split_complex_arg)
17511 return rs6000_complex_function_value (mode);
17512 else if (TREE_CODE (valtype) == VECTOR_TYPE
17513 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
17514 && ALTIVEC_VECTOR_MODE(mode))
17515 regno = ALTIVEC_ARG_RETURN;
17516 else
17517 regno = GP_ARG_RETURN;
17519 return gen_rtx_REG (mode, regno);
17522 /* Define how to find the value returned by a library function
17523 assuming the value has mode MODE. */
17525 rs6000_libcall_value (enum machine_mode mode)
17527 unsigned int regno;
17529 if (GET_MODE_CLASS (mode) == MODE_FLOAT
17530 && TARGET_HARD_FLOAT && TARGET_FPRS)
17531 regno = FP_ARG_RETURN;
17532 else if (ALTIVEC_VECTOR_MODE (mode)
17533 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
17534 regno = ALTIVEC_ARG_RETURN;
17535 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
17536 return rs6000_complex_function_value (mode);
17537 else
17538 regno = GP_ARG_RETURN;
17540 return gen_rtx_REG (mode, regno);
17543 /* Define the offset between two registers, FROM to be eliminated and its
17544 replacement TO, at the start of a routine. */
17545 HOST_WIDE_INT
17546 rs6000_initial_elimination_offset (int from, int to)
17548 rs6000_stack_t *info = rs6000_stack_info ();
17549 HOST_WIDE_INT offset;
17551 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
17552 offset = info->push_p ? 0 : -info->total_size;
17553 else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
17554 offset = info->total_size;
17555 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
17556 offset = info->push_p ? info->total_size : 0;
17557 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
17558 offset = 0;
17559 else
17560 abort ();
17562 return offset;
17565 /* Return true if TYPE is of type __ev64_opaque__. */
17567 static bool
17568 is_ev64_opaque_type (tree type)
17570 return (TARGET_SPE
17571 && (type == opaque_V2SI_type_node
17572 || type == opaque_V2SF_type_node
17573 || type == opaque_p_V2SI_type_node));
17576 static rtx
17577 rs6000_dwarf_register_span (rtx reg)
17579 unsigned regno;
17581 if (!TARGET_SPE || !SPE_VECTOR_MODE (GET_MODE (reg)))
17582 return NULL_RTX;
17584 regno = REGNO (reg);
17586 /* The duality of the SPE register size wreaks all kinds of havoc.
17587 This is a way of distinguishing r0 in 32-bits from r0 in
17588 64-bits. */
17589 return
17590 gen_rtx_PARALLEL (VOIDmode,
17591 BYTES_BIG_ENDIAN
17592 ? gen_rtvec (2,
17593 gen_rtx_REG (SImode, regno + 1200),
17594 gen_rtx_REG (SImode, regno))
17595 : gen_rtvec (2,
17596 gen_rtx_REG (SImode, regno),
17597 gen_rtx_REG (SImode, regno + 1200)));
17600 /* Map internal gcc register numbers to DWARF2 register numbers. */
17602 unsigned int
17603 rs6000_dbx_register_number (unsigned int regno)
17605 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
17606 return regno;
17607 if (regno == MQ_REGNO)
17608 return 100;
17609 if (regno == LINK_REGISTER_REGNUM)
17610 return 108;
17611 if (regno == COUNT_REGISTER_REGNUM)
17612 return 109;
17613 if (CR_REGNO_P (regno))
17614 return regno - CR0_REGNO + 86;
17615 if (regno == XER_REGNO)
17616 return 101;
17617 if (ALTIVEC_REGNO_P (regno))
17618 return regno - FIRST_ALTIVEC_REGNO + 1124;
17619 if (regno == VRSAVE_REGNO)
17620 return 356;
17621 if (regno == VSCR_REGNO)
17622 return 67;
17623 if (regno == SPE_ACC_REGNO)
17624 return 99;
17625 if (regno == SPEFSCR_REGNO)
17626 return 612;
17627 /* SPE high reg number. We get these values of regno from
17628 rs6000_dwarf_register_span. */
17629 if (regno >= 1200 && regno < 1232)
17630 return regno;
17632 abort ();
17635 /* target hook eh_return_filter_mode */
17636 static enum machine_mode
17637 rs6000_eh_return_filter_mode (void)
17639 return TARGET_32BIT ? SImode : word_mode;
17642 /* Target hook for vector_mode_supported_p. */
17643 static bool
17644 rs6000_vector_mode_supported_p (enum machine_mode mode)
17647 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
17648 return true;
17650 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
17651 return true;
17653 else
17654 return false;
17657 #include "gt-rs6000.h"