1 /* Perform simple optimizations to clean up the result of reload.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
33 #include "insn-config.h"
39 #include "basic-block.h"
49 #include "tree-pass.h"
53 static int reload_cse_noop_set_p (rtx
);
54 static void reload_cse_simplify (rtx
, rtx
);
55 static void reload_cse_regs_1 (rtx
);
56 static int reload_cse_simplify_set (rtx
, rtx
);
57 static int reload_cse_simplify_operands (rtx
, rtx
);
59 static void reload_combine (void);
60 static void reload_combine_note_use (rtx
*, rtx
);
61 static void reload_combine_note_store (rtx
, rtx
, void *);
63 static void reload_cse_move2add (rtx
);
64 static void move2add_note_store (rtx
, rtx
, void *);
66 /* Call cse / combine like post-reload optimization phases.
67 FIRST is the first instruction. */
69 reload_cse_regs (rtx first ATTRIBUTE_UNUSED
)
71 reload_cse_regs_1 (first
);
73 reload_cse_move2add (first
);
74 if (flag_expensive_optimizations
)
75 reload_cse_regs_1 (first
);
78 /* See whether a single set SET is a noop. */
80 reload_cse_noop_set_p (rtx set
)
82 if (cselib_reg_set_mode (SET_DEST (set
)) != GET_MODE (SET_DEST (set
)))
85 return rtx_equal_for_cselib_p (SET_DEST (set
), SET_SRC (set
));
88 /* Try to simplify INSN. */
90 reload_cse_simplify (rtx insn
, rtx testreg
)
92 rtx body
= PATTERN (insn
);
94 if (GET_CODE (body
) == SET
)
98 /* Simplify even if we may think it is a no-op.
99 We may think a memory load of a value smaller than WORD_SIZE
100 is redundant because we haven't taken into account possible
101 implicit extension. reload_cse_simplify_set() will bring
102 this out, so it's safer to simplify before we delete. */
103 count
+= reload_cse_simplify_set (body
, insn
);
105 if (!count
&& reload_cse_noop_set_p (body
))
107 rtx value
= SET_DEST (body
);
109 && ! REG_FUNCTION_VALUE_P (value
))
111 delete_insn_and_edges (insn
);
116 apply_change_group ();
118 reload_cse_simplify_operands (insn
, testreg
);
120 else if (GET_CODE (body
) == PARALLEL
)
124 rtx value
= NULL_RTX
;
126 /* Registers mentioned in the clobber list for an asm cannot be reused
127 within the body of the asm. Invalidate those registers now so that
128 we don't try to substitute values for them. */
129 if (asm_noperands (body
) >= 0)
131 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
133 rtx part
= XVECEXP (body
, 0, i
);
134 if (GET_CODE (part
) == CLOBBER
&& REG_P (XEXP (part
, 0)))
135 cselib_invalidate_rtx (XEXP (part
, 0));
139 /* If every action in a PARALLEL is a noop, we can delete
140 the entire PARALLEL. */
141 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
143 rtx part
= XVECEXP (body
, 0, i
);
144 if (GET_CODE (part
) == SET
)
146 if (! reload_cse_noop_set_p (part
))
148 if (REG_P (SET_DEST (part
))
149 && REG_FUNCTION_VALUE_P (SET_DEST (part
)))
153 value
= SET_DEST (part
);
156 else if (GET_CODE (part
) != CLOBBER
)
162 delete_insn_and_edges (insn
);
163 /* We're done with this insn. */
167 /* It's not a no-op, but we can try to simplify it. */
168 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
169 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
170 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
173 apply_change_group ();
175 reload_cse_simplify_operands (insn
, testreg
);
179 /* Do a very simple CSE pass over the hard registers.
181 This function detects no-op moves where we happened to assign two
182 different pseudo-registers to the same hard register, and then
183 copied one to the other. Reload will generate a useless
184 instruction copying a register to itself.
186 This function also detects cases where we load a value from memory
187 into two different registers, and (if memory is more expensive than
188 registers) changes it to simply copy the first register into the
191 Another optimization is performed that scans the operands of each
192 instruction to see whether the value is already available in a
193 hard register. It then replaces the operand with the hard register
194 if possible, much like an optional reload would. */
197 reload_cse_regs_1 (rtx first
)
200 rtx testreg
= gen_rtx_REG (VOIDmode
, -1);
203 init_alias_analysis ();
205 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
208 reload_cse_simplify (insn
, testreg
);
210 cselib_process_insn (insn
);
214 end_alias_analysis ();
218 /* Try to simplify a single SET instruction. SET is the set pattern.
219 INSN is the instruction it came from.
220 This function only handles one case: if we set a register to a value
221 which is not a register, we try to find that value in some other register
222 and change the set into a register copy. */
225 reload_cse_simplify_set (rtx set
, rtx insn
)
230 enum reg_class dclass
;
233 struct elt_loc_list
*l
;
234 #ifdef LOAD_EXTEND_OP
235 enum rtx_code extend_op
= UNKNOWN
;
238 dreg
= true_regnum (SET_DEST (set
));
243 if (side_effects_p (src
) || true_regnum (src
) >= 0)
246 dclass
= REGNO_REG_CLASS (dreg
);
248 #ifdef LOAD_EXTEND_OP
249 /* When replacing a memory with a register, we need to honor assumptions
250 that combine made wrt the contents of sign bits. We'll do this by
251 generating an extend instruction instead of a reg->reg copy. Thus
252 the destination must be a register that we can widen. */
254 && GET_MODE_BITSIZE (GET_MODE (src
)) < BITS_PER_WORD
255 && (extend_op
= LOAD_EXTEND_OP (GET_MODE (src
))) != UNKNOWN
256 && !REG_P (SET_DEST (set
)))
260 val
= cselib_lookup (src
, GET_MODE (SET_DEST (set
)), 0);
264 /* If memory loads are cheaper than register copies, don't change them. */
266 old_cost
= MEMORY_MOVE_COST (GET_MODE (src
), dclass
, 1);
267 else if (REG_P (src
))
268 old_cost
= REGISTER_MOVE_COST (GET_MODE (src
),
269 REGNO_REG_CLASS (REGNO (src
)), dclass
);
271 old_cost
= rtx_cost (src
, SET
);
273 for (l
= val
->locs
; l
; l
= l
->next
)
275 rtx this_rtx
= l
->loc
;
278 if (CONSTANT_P (this_rtx
) && ! references_value_p (this_rtx
, 0))
280 #ifdef LOAD_EXTEND_OP
281 if (extend_op
!= UNKNOWN
)
283 HOST_WIDE_INT this_val
;
285 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
286 constants, such as SYMBOL_REF, cannot be extended. */
287 if (GET_CODE (this_rtx
) != CONST_INT
)
290 this_val
= INTVAL (this_rtx
);
294 this_val
&= GET_MODE_MASK (GET_MODE (src
));
297 /* ??? In theory we're already extended. */
298 if (this_val
== trunc_int_for_mode (this_val
, GET_MODE (src
)))
303 this_rtx
= GEN_INT (this_val
);
306 this_cost
= rtx_cost (this_rtx
, SET
);
308 else if (REG_P (this_rtx
))
310 #ifdef LOAD_EXTEND_OP
311 if (extend_op
!= UNKNOWN
)
313 this_rtx
= gen_rtx_fmt_e (extend_op
, word_mode
, this_rtx
);
314 this_cost
= rtx_cost (this_rtx
, SET
);
318 this_cost
= REGISTER_MOVE_COST (GET_MODE (this_rtx
),
319 REGNO_REG_CLASS (REGNO (this_rtx
)),
325 /* If equal costs, prefer registers over anything else. That
326 tends to lead to smaller instructions on some machines. */
327 if (this_cost
< old_cost
328 || (this_cost
== old_cost
330 && !REG_P (SET_SRC (set
))))
332 #ifdef LOAD_EXTEND_OP
333 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set
))) < BITS_PER_WORD
334 && extend_op
!= UNKNOWN
335 #ifdef CANNOT_CHANGE_MODE_CLASS
336 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
338 REGNO_REG_CLASS (REGNO (SET_DEST (set
))))
342 rtx wide_dest
= gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
)));
343 ORIGINAL_REGNO (wide_dest
) = ORIGINAL_REGNO (SET_DEST (set
));
344 validate_change (insn
, &SET_DEST (set
), wide_dest
, 1);
348 validate_change (insn
, &SET_SRC (set
), copy_rtx (this_rtx
), 1);
349 old_cost
= this_cost
, did_change
= 1;
356 /* Try to replace operands in INSN with equivalent values that are already
357 in registers. This can be viewed as optional reloading.
359 For each non-register operand in the insn, see if any hard regs are
360 known to be equivalent to that operand. Record the alternatives which
361 can accept these hard registers. Among all alternatives, select the
362 ones which are better or equal to the one currently matching, where
363 "better" is in terms of '?' and '!' constraints. Among the remaining
364 alternatives, select the one which replaces most operands with
368 reload_cse_simplify_operands (rtx insn
, rtx testreg
)
372 /* For each operand, all registers that are equivalent to it. */
373 HARD_REG_SET equiv_regs
[MAX_RECOG_OPERANDS
];
375 const char *constraints
[MAX_RECOG_OPERANDS
];
377 /* Vector recording how bad an alternative is. */
378 int *alternative_reject
;
379 /* Vector recording how many registers can be introduced by choosing
381 int *alternative_nregs
;
382 /* Array of vectors recording, for each operand and each alternative,
383 which hard register to substitute, or -1 if the operand should be
385 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
386 /* Array of alternatives, sorted in order of decreasing desirability. */
387 int *alternative_order
;
391 if (recog_data
.n_alternatives
== 0 || recog_data
.n_operands
== 0)
394 /* Figure out which alternative currently matches. */
395 if (! constrain_operands (1))
396 fatal_insn_not_found (insn
);
398 alternative_reject
= alloca (recog_data
.n_alternatives
* sizeof (int));
399 alternative_nregs
= alloca (recog_data
.n_alternatives
* sizeof (int));
400 alternative_order
= alloca (recog_data
.n_alternatives
* sizeof (int));
401 memset (alternative_reject
, 0, recog_data
.n_alternatives
* sizeof (int));
402 memset (alternative_nregs
, 0, recog_data
.n_alternatives
* sizeof (int));
404 /* For each operand, find out which regs are equivalent. */
405 for (i
= 0; i
< recog_data
.n_operands
; i
++)
408 struct elt_loc_list
*l
;
410 enum machine_mode mode
;
412 CLEAR_HARD_REG_SET (equiv_regs
[i
]);
414 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
415 right, so avoid the problem here. Likewise if we have a constant
416 and the insn pattern doesn't tell us the mode we need. */
417 if (LABEL_P (recog_data
.operand
[i
])
418 || (CONSTANT_P (recog_data
.operand
[i
])
419 && recog_data
.operand_mode
[i
] == VOIDmode
))
422 op
= recog_data
.operand
[i
];
423 mode
= GET_MODE (op
);
424 #ifdef LOAD_EXTEND_OP
426 && GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
427 && LOAD_EXTEND_OP (mode
) != UNKNOWN
)
429 rtx set
= single_set (insn
);
431 /* We might have multiple sets, some of which do implicit
432 extension. Punt on this for now. */
435 /* If the destination is also a MEM or a STRICT_LOW_PART, no
437 Also, if there is an explicit extension, we don't have to
438 worry about an implicit one. */
439 else if (MEM_P (SET_DEST (set
))
440 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
441 || GET_CODE (SET_SRC (set
)) == ZERO_EXTEND
442 || GET_CODE (SET_SRC (set
)) == SIGN_EXTEND
)
443 ; /* Continue ordinary processing. */
444 #ifdef CANNOT_CHANGE_MODE_CLASS
445 /* If the register cannot change mode to word_mode, it follows that
446 it cannot have been used in word_mode. */
447 else if (REG_P (SET_DEST (set
))
448 && CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
450 REGNO_REG_CLASS (REGNO (SET_DEST (set
)))))
451 ; /* Continue ordinary processing. */
453 /* If this is a straight load, make the extension explicit. */
454 else if (REG_P (SET_DEST (set
))
455 && recog_data
.n_operands
== 2
456 && SET_SRC (set
) == op
457 && SET_DEST (set
) == recog_data
.operand
[1-i
])
459 validate_change (insn
, recog_data
.operand_loc
[i
],
460 gen_rtx_fmt_e (LOAD_EXTEND_OP (mode
),
463 validate_change (insn
, recog_data
.operand_loc
[1-i
],
464 gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
))),
466 if (! apply_change_group ())
468 return reload_cse_simplify_operands (insn
, testreg
);
471 /* ??? There might be arithmetic operations with memory that are
472 safe to optimize, but is it worth the trouble? */
475 #endif /* LOAD_EXTEND_OP */
476 v
= cselib_lookup (op
, recog_data
.operand_mode
[i
], 0);
480 for (l
= v
->locs
; l
; l
= l
->next
)
482 SET_HARD_REG_BIT (equiv_regs
[i
], REGNO (l
->loc
));
485 for (i
= 0; i
< recog_data
.n_operands
; i
++)
487 enum machine_mode mode
;
491 op_alt_regno
[i
] = alloca (recog_data
.n_alternatives
* sizeof (int));
492 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
493 op_alt_regno
[i
][j
] = -1;
495 p
= constraints
[i
] = recog_data
.constraints
[i
];
496 mode
= recog_data
.operand_mode
[i
];
498 /* Add the reject values for each alternative given by the constraints
507 alternative_reject
[j
] += 3;
509 alternative_reject
[j
] += 300;
512 /* We won't change operands which are already registers. We
513 also don't want to modify output operands. */
514 regno
= true_regnum (recog_data
.operand
[i
]);
516 || constraints
[i
][0] == '='
517 || constraints
[i
][0] == '+')
520 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
522 int class = (int) NO_REGS
;
524 if (! TEST_HARD_REG_BIT (equiv_regs
[i
], regno
))
527 SET_REGNO (testreg
, regno
);
528 PUT_MODE (testreg
, mode
);
530 /* We found a register equal to this operand. Now look for all
531 alternatives that can accept this register and have not been
532 assigned a register they can use yet. */
541 case '=': case '+': case '?':
542 case '#': case '&': case '!':
544 case '0': case '1': case '2': case '3': case '4':
545 case '5': case '6': case '7': case '8': case '9':
546 case 'm': case '<': case '>': case 'V': case 'o':
547 case 'E': case 'F': case 'G': case 'H':
548 case 's': case 'i': case 'n':
549 case 'I': case 'J': case 'K': case 'L':
550 case 'M': case 'N': case 'O': case 'P':
552 /* These don't say anything we care about. */
556 class = reg_class_subunion
[(int) class][(int) GENERAL_REGS
];
561 = (reg_class_subunion
563 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c
, p
)]);
567 /* See if REGNO fits this alternative, and set it up as the
568 replacement register if we don't have one for this
569 alternative yet and the operand being replaced is not
570 a cheap CONST_INT. */
571 if (op_alt_regno
[i
][j
] == -1
572 && reg_fits_class_p (testreg
, class, 0, mode
)
573 && (GET_CODE (recog_data
.operand
[i
]) != CONST_INT
574 || (rtx_cost (recog_data
.operand
[i
], SET
)
575 > rtx_cost (testreg
, SET
))))
577 alternative_nregs
[j
]++;
578 op_alt_regno
[i
][j
] = regno
;
581 class = (int) NO_REGS
;
584 p
+= CONSTRAINT_LEN (c
, p
);
592 /* Record all alternatives which are better or equal to the currently
593 matching one in the alternative_order array. */
594 for (i
= j
= 0; i
< recog_data
.n_alternatives
; i
++)
595 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
596 alternative_order
[j
++] = i
;
597 recog_data
.n_alternatives
= j
;
599 /* Sort it. Given a small number of alternatives, a dumb algorithm
600 won't hurt too much. */
601 for (i
= 0; i
< recog_data
.n_alternatives
- 1; i
++)
604 int best_reject
= alternative_reject
[alternative_order
[i
]];
605 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
608 for (j
= i
+ 1; j
< recog_data
.n_alternatives
; j
++)
610 int this_reject
= alternative_reject
[alternative_order
[j
]];
611 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
613 if (this_reject
< best_reject
614 || (this_reject
== best_reject
&& this_nregs
> best_nregs
))
617 best_reject
= this_reject
;
618 best_nregs
= this_nregs
;
622 tmp
= alternative_order
[best
];
623 alternative_order
[best
] = alternative_order
[i
];
624 alternative_order
[i
] = tmp
;
627 /* Substitute the operands as determined by op_alt_regno for the best
629 j
= alternative_order
[0];
631 for (i
= 0; i
< recog_data
.n_operands
; i
++)
633 enum machine_mode mode
= recog_data
.operand_mode
[i
];
634 if (op_alt_regno
[i
][j
] == -1)
637 validate_change (insn
, recog_data
.operand_loc
[i
],
638 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
641 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
643 int op
= recog_data
.dup_num
[i
];
644 enum machine_mode mode
= recog_data
.operand_mode
[op
];
646 if (op_alt_regno
[op
][j
] == -1)
649 validate_change (insn
, recog_data
.dup_loc
[i
],
650 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
653 return apply_change_group ();
656 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
658 This code might also be useful when reload gave up on reg+reg addressing
659 because of clashes between the return register and INDEX_REG_CLASS. */
661 /* The maximum number of uses of a register we can keep track of to
662 replace them with reg+reg addressing. */
663 #define RELOAD_COMBINE_MAX_USES 6
665 /* INSN is the insn where a register has ben used, and USEP points to the
666 location of the register within the rtl. */
667 struct reg_use
{ rtx insn
, *usep
; };
669 /* If the register is used in some unknown fashion, USE_INDEX is negative.
670 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
671 indicates where it becomes live again.
672 Otherwise, USE_INDEX is the index of the last encountered use of the
673 register (which is first among these we have seen since we scan backwards),
674 OFFSET contains the constant offset that is added to the register in
675 all encountered uses, and USE_RUID indicates the first encountered, i.e.
677 STORE_RUID is always meaningful if we only want to use a value in a
678 register in a different place: it denotes the next insn in the insn
679 stream (i.e. the last encountered) that sets or clobbers the register. */
682 struct reg_use reg_use
[RELOAD_COMBINE_MAX_USES
];
687 } reg_state
[FIRST_PSEUDO_REGISTER
];
689 /* Reverse linear uid. This is increased in reload_combine while scanning
690 the instructions from last to first. It is used to set last_label_ruid
691 and the store_ruid / use_ruid fields in reg_state. */
692 static int reload_combine_ruid
;
694 #define LABEL_LIVE(LABEL) \
695 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
698 reload_combine (void)
701 int first_index_reg
= -1;
702 int last_index_reg
= 0;
707 int min_labelno
, n_labels
;
708 HARD_REG_SET ever_live_at_start
, *label_live
;
710 /* If reg+reg can be used in offsetable memory addresses, the main chunk of
711 reload has already used it where appropriate, so there is no use in
712 trying to generate it now. */
713 if (double_reg_address_ok
&& INDEX_REG_CLASS
!= NO_REGS
)
716 /* To avoid wasting too much time later searching for an index register,
717 determine the minimum and maximum index register numbers. */
718 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
719 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], r
))
721 if (first_index_reg
== -1)
727 /* If no index register is available, we can quit now. */
728 if (first_index_reg
== -1)
731 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
732 information is a bit fuzzy immediately after reload, but it's
733 still good enough to determine which registers are live at a jump
735 min_labelno
= get_first_label_num ();
736 n_labels
= max_label_num () - min_labelno
;
737 label_live
= XNEWVEC (HARD_REG_SET
, n_labels
);
738 CLEAR_HARD_REG_SET (ever_live_at_start
);
740 FOR_EACH_BB_REVERSE (bb
)
747 REG_SET_TO_HARD_REG_SET (live
, DF_LIVE_IN (bb
));
748 compute_use_by_pseudos (&live
, DF_LIVE_IN (bb
));
749 COPY_HARD_REG_SET (LABEL_LIVE (insn
), live
);
750 IOR_HARD_REG_SET (ever_live_at_start
, live
);
754 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
755 last_label_ruid
= reload_combine_ruid
= 0;
756 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
758 reg_state
[r
].store_ruid
= reload_combine_ruid
;
760 reg_state
[r
].use_index
= -1;
762 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
765 for (insn
= get_last_insn (); insn
; insn
= PREV_INSN (insn
))
769 /* We cannot do our optimization across labels. Invalidating all the use
770 information we have would be costly, so we just note where the label
771 is and then later disable any optimization that would cross it. */
773 last_label_ruid
= reload_combine_ruid
;
774 else if (BARRIER_P (insn
))
775 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
777 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
782 reload_combine_ruid
++;
784 /* Look for (set (REGX) (CONST_INT))
785 (set (REGX) (PLUS (REGX) (REGY)))
789 (set (REGZ) (CONST_INT))
791 ... (MEM (PLUS (REGZ) (REGY)))... .
793 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
794 and that we know all uses of REGX before it dies.
795 Also, explicitly check that REGX != REGY; our life information
796 does not yet show whether REGY changes in this insn. */
797 set
= single_set (insn
);
799 && REG_P (SET_DEST (set
))
800 && (hard_regno_nregs
[REGNO (SET_DEST (set
))]
801 [GET_MODE (SET_DEST (set
))]
803 && GET_CODE (SET_SRC (set
)) == PLUS
804 && REG_P (XEXP (SET_SRC (set
), 1))
805 && rtx_equal_p (XEXP (SET_SRC (set
), 0), SET_DEST (set
))
806 && !rtx_equal_p (XEXP (SET_SRC (set
), 1), SET_DEST (set
))
807 && last_label_ruid
< reg_state
[REGNO (SET_DEST (set
))].use_ruid
)
809 rtx reg
= SET_DEST (set
);
810 rtx plus
= SET_SRC (set
);
811 rtx base
= XEXP (plus
, 1);
812 rtx prev
= prev_nonnote_insn (insn
);
813 rtx prev_set
= prev
? single_set (prev
) : NULL_RTX
;
814 unsigned int regno
= REGNO (reg
);
815 rtx const_reg
= NULL_RTX
;
816 rtx reg_sum
= NULL_RTX
;
818 /* Now, we need an index register.
819 We'll set index_reg to this index register, const_reg to the
820 register that is to be loaded with the constant
821 (denoted as REGZ in the substitution illustration above),
822 and reg_sum to the register-register that we want to use to
823 substitute uses of REG (typically in MEMs) with.
824 First check REG and BASE for being index registers;
825 we can use them even if they are not dead. */
826 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], regno
)
827 || TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
835 /* Otherwise, look for a free index register. Since we have
836 checked above that neither REG nor BASE are index registers,
837 if we find anything at all, it will be different from these
839 for (i
= first_index_reg
; i
<= last_index_reg
; i
++)
841 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
843 && reg_state
[i
].use_index
== RELOAD_COMBINE_MAX_USES
844 && reg_state
[i
].store_ruid
<= reg_state
[regno
].use_ruid
845 && hard_regno_nregs
[i
][GET_MODE (reg
)] == 1)
847 rtx index_reg
= gen_rtx_REG (GET_MODE (reg
), i
);
849 const_reg
= index_reg
;
850 reg_sum
= gen_rtx_PLUS (GET_MODE (reg
), index_reg
, base
);
856 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
857 (REGY), i.e. BASE, is not clobbered before the last use we'll
860 && GET_CODE (SET_SRC (prev_set
)) == CONST_INT
861 && rtx_equal_p (SET_DEST (prev_set
), reg
)
862 && reg_state
[regno
].use_index
>= 0
863 && (reg_state
[REGNO (base
)].store_ruid
864 <= reg_state
[regno
].use_ruid
)
869 /* Change destination register and, if necessary, the
870 constant value in PREV, the constant loading instruction. */
871 validate_change (prev
, &SET_DEST (prev_set
), const_reg
, 1);
872 if (reg_state
[regno
].offset
!= const0_rtx
)
873 validate_change (prev
,
875 GEN_INT (INTVAL (SET_SRC (prev_set
))
876 + INTVAL (reg_state
[regno
].offset
)),
879 /* Now for every use of REG that we have recorded, replace REG
881 for (i
= reg_state
[regno
].use_index
;
882 i
< RELOAD_COMBINE_MAX_USES
; i
++)
883 validate_change (reg_state
[regno
].reg_use
[i
].insn
,
884 reg_state
[regno
].reg_use
[i
].usep
,
885 /* Each change must have its own
887 copy_rtx (reg_sum
), 1);
889 if (apply_change_group ())
891 /* Delete the reg-reg addition. */
894 if (reg_state
[regno
].offset
!= const0_rtx
)
895 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
897 remove_reg_equal_equiv_notes (prev
);
899 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
900 reg_state
[REGNO (const_reg
)].store_ruid
901 = reload_combine_ruid
;
907 note_stores (PATTERN (insn
), reload_combine_note_store
, NULL
);
913 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
914 if (call_used_regs
[r
])
916 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
917 reg_state
[r
].store_ruid
= reload_combine_ruid
;
920 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
921 link
= XEXP (link
, 1))
923 rtx usage_rtx
= XEXP (XEXP (link
, 0), 0);
924 if (REG_P (usage_rtx
))
927 unsigned int start_reg
= REGNO (usage_rtx
);
928 unsigned int num_regs
=
929 hard_regno_nregs
[start_reg
][GET_MODE (usage_rtx
)];
930 unsigned int end_reg
= start_reg
+ num_regs
- 1;
931 for (i
= start_reg
; i
<= end_reg
; i
++)
932 if (GET_CODE (XEXP (link
, 0)) == CLOBBER
)
934 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
935 reg_state
[i
].store_ruid
= reload_combine_ruid
;
938 reg_state
[i
].use_index
= -1;
943 else if (JUMP_P (insn
)
944 && GET_CODE (PATTERN (insn
)) != RETURN
)
946 /* Non-spill registers might be used at the call destination in
947 some unknown fashion, so we have to mark the unknown use. */
950 if ((condjump_p (insn
) || condjump_in_parallel_p (insn
))
951 && JUMP_LABEL (insn
))
952 live
= &LABEL_LIVE (JUMP_LABEL (insn
));
954 live
= &ever_live_at_start
;
956 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
957 if (TEST_HARD_REG_BIT (*live
, i
))
958 reg_state
[i
].use_index
= -1;
961 reload_combine_note_use (&PATTERN (insn
), insn
);
962 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
964 if (REG_NOTE_KIND (note
) == REG_INC
965 && REG_P (XEXP (note
, 0)))
967 int regno
= REGNO (XEXP (note
, 0));
969 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
970 reg_state
[regno
].use_index
= -1;
978 /* Check if DST is a register or a subreg of a register; if it is,
979 update reg_state[regno].store_ruid and reg_state[regno].use_index
980 accordingly. Called via note_stores from reload_combine. */
983 reload_combine_note_store (rtx dst
, rtx set
, void *data ATTRIBUTE_UNUSED
)
987 enum machine_mode mode
= GET_MODE (dst
);
989 if (GET_CODE (dst
) == SUBREG
)
991 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
992 GET_MODE (SUBREG_REG (dst
)),
995 dst
= SUBREG_REG (dst
);
999 regno
+= REGNO (dst
);
1001 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
1002 careful with registers / register parts that are not full words.
1003 Similarly for ZERO_EXTRACT. */
1004 if (GET_CODE (set
) != SET
1005 || GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
1006 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
1008 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1010 reg_state
[i
].use_index
= -1;
1011 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1016 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1018 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1019 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
1024 /* XP points to a piece of rtl that has to be checked for any uses of
1026 *XP is the pattern of INSN, or a part of it.
1027 Called from reload_combine, and recursively by itself. */
1029 reload_combine_note_use (rtx
*xp
, rtx insn
)
1032 enum rtx_code code
= x
->code
;
1035 rtx offset
= const0_rtx
; /* For the REG case below. */
1040 if (REG_P (SET_DEST (x
)))
1042 reload_combine_note_use (&SET_SRC (x
), insn
);
1048 /* If this is the USE of a return value, we can't change it. */
1049 if (REG_P (XEXP (x
, 0)) && REG_FUNCTION_VALUE_P (XEXP (x
, 0)))
1051 /* Mark the return register as used in an unknown fashion. */
1052 rtx reg
= XEXP (x
, 0);
1053 int regno
= REGNO (reg
);
1054 int nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
1056 while (--nregs
>= 0)
1057 reg_state
[regno
+ nregs
].use_index
= -1;
1063 if (REG_P (SET_DEST (x
)))
1065 /* No spurious CLOBBERs of pseudo registers may remain. */
1066 gcc_assert (REGNO (SET_DEST (x
)) < FIRST_PSEUDO_REGISTER
);
1072 /* We are interested in (plus (reg) (const_int)) . */
1073 if (!REG_P (XEXP (x
, 0))
1074 || GET_CODE (XEXP (x
, 1)) != CONST_INT
)
1076 offset
= XEXP (x
, 1);
1081 int regno
= REGNO (x
);
1085 /* No spurious USEs of pseudo registers may remain. */
1086 gcc_assert (regno
< FIRST_PSEUDO_REGISTER
);
1088 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
1090 /* We can't substitute into multi-hard-reg uses. */
1093 while (--nregs
>= 0)
1094 reg_state
[regno
+ nregs
].use_index
= -1;
1098 /* If this register is already used in some unknown fashion, we
1100 If we decrement the index from zero to -1, we can't store more
1101 uses, so this register becomes used in an unknown fashion. */
1102 use_index
= --reg_state
[regno
].use_index
;
1106 if (use_index
!= RELOAD_COMBINE_MAX_USES
- 1)
1108 /* We have found another use for a register that is already
1109 used later. Check if the offsets match; if not, mark the
1110 register as used in an unknown fashion. */
1111 if (! rtx_equal_p (offset
, reg_state
[regno
].offset
))
1113 reg_state
[regno
].use_index
= -1;
1119 /* This is the first use of this register we have seen since we
1120 marked it as dead. */
1121 reg_state
[regno
].offset
= offset
;
1122 reg_state
[regno
].use_ruid
= reload_combine_ruid
;
1124 reg_state
[regno
].reg_use
[use_index
].insn
= insn
;
1125 reg_state
[regno
].reg_use
[use_index
].usep
= xp
;
1133 /* Recursively process the components of X. */
1134 fmt
= GET_RTX_FORMAT (code
);
1135 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1138 reload_combine_note_use (&XEXP (x
, i
), insn
);
1139 else if (fmt
[i
] == 'E')
1141 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1142 reload_combine_note_use (&XVECEXP (x
, i
, j
), insn
);
1147 /* See if we can reduce the cost of a constant by replacing a move
1148 with an add. We track situations in which a register is set to a
1149 constant or to a register plus a constant. */
1150 /* We cannot do our optimization across labels. Invalidating all the
1151 information about register contents we have would be costly, so we
1152 use move2add_last_label_luid to note where the label is and then
1153 later disable any optimization that would cross it.
1154 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
1155 reg_set_luid[n] is greater than move2add_last_label_luid. */
1156 static int reg_set_luid
[FIRST_PSEUDO_REGISTER
];
1158 /* If reg_base_reg[n] is negative, register n has been set to
1159 reg_offset[n] in mode reg_mode[n] .
1160 If reg_base_reg[n] is non-negative, register n has been set to the
1161 sum of reg_offset[n] and the value of register reg_base_reg[n]
1162 before reg_set_luid[n], calculated in mode reg_mode[n] . */
1163 static HOST_WIDE_INT reg_offset
[FIRST_PSEUDO_REGISTER
];
1164 static int reg_base_reg
[FIRST_PSEUDO_REGISTER
];
1165 static enum machine_mode reg_mode
[FIRST_PSEUDO_REGISTER
];
1167 /* move2add_luid is linearly increased while scanning the instructions
1168 from first to last. It is used to set reg_set_luid in
1169 reload_cse_move2add and move2add_note_store. */
1170 static int move2add_luid
;
1172 /* move2add_last_label_luid is set whenever a label is found. Labels
1173 invalidate all previously collected reg_offset data. */
1174 static int move2add_last_label_luid
;
1176 /* ??? We don't know how zero / sign extension is handled, hence we
1177 can't go from a narrower to a wider mode. */
1178 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
1179 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
1180 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
1181 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
1182 GET_MODE_BITSIZE (INMODE))))
1185 reload_cse_move2add (rtx first
)
1190 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
1191 reg_set_luid
[i
] = 0;
1193 move2add_last_label_luid
= 0;
1195 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
), move2add_luid
++)
1201 move2add_last_label_luid
= move2add_luid
;
1202 /* We're going to increment move2add_luid twice after a
1203 label, so that we can use move2add_last_label_luid + 1 as
1204 the luid for constants. */
1208 if (! INSN_P (insn
))
1210 pat
= PATTERN (insn
);
1211 /* For simplicity, we only perform this optimization on
1212 straightforward SETs. */
1213 if (GET_CODE (pat
) == SET
1214 && REG_P (SET_DEST (pat
)))
1216 rtx reg
= SET_DEST (pat
);
1217 int regno
= REGNO (reg
);
1218 rtx src
= SET_SRC (pat
);
1220 /* Check if we have valid information on the contents of this
1221 register in the mode of REG. */
1222 if (reg_set_luid
[regno
] > move2add_last_label_luid
1223 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg
), reg_mode
[regno
])
1224 && dbg_cnt (cse2_move2add
))
1226 /* Try to transform (set (REGX) (CONST_INT A))
1228 (set (REGX) (CONST_INT B))
1230 (set (REGX) (CONST_INT A))
1232 (set (REGX) (plus (REGX) (CONST_INT B-A)))
1234 (set (REGX) (CONST_INT A))
1236 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
1239 if (GET_CODE (src
) == CONST_INT
&& reg_base_reg
[regno
] < 0)
1241 rtx new_src
= gen_int_mode (INTVAL (src
) - reg_offset
[regno
],
1243 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1244 use (set (reg) (reg)) instead.
1245 We don't delete this insn, nor do we convert it into a
1246 note, to avoid losing register notes or the return
1247 value flag. jump2 already knows how to get rid of
1249 if (new_src
== const0_rtx
)
1251 /* If the constants are different, this is a
1252 truncation, that, if turned into (set (reg)
1253 (reg)), would be discarded. Maybe we should
1254 try a truncMN pattern? */
1255 if (INTVAL (src
) == reg_offset
[regno
])
1256 validate_change (insn
, &SET_SRC (pat
), reg
, 0);
1258 else if (rtx_cost (new_src
, PLUS
) < rtx_cost (src
, SET
)
1259 && have_add2_insn (reg
, new_src
))
1261 rtx tem
= gen_rtx_PLUS (GET_MODE (reg
), reg
, new_src
);
1262 validate_change (insn
, &SET_SRC (pat
), tem
, 0);
1264 else if (GET_MODE (reg
) != BImode
)
1266 enum machine_mode narrow_mode
;
1267 for (narrow_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
1268 narrow_mode
!= VOIDmode
1269 && narrow_mode
!= GET_MODE (reg
);
1270 narrow_mode
= GET_MODE_WIDER_MODE (narrow_mode
))
1272 if (have_insn_for (STRICT_LOW_PART
, narrow_mode
)
1273 && ((reg_offset
[regno
]
1274 & ~GET_MODE_MASK (narrow_mode
))
1276 & ~GET_MODE_MASK (narrow_mode
))))
1278 rtx narrow_reg
= gen_rtx_REG (narrow_mode
,
1280 rtx narrow_src
= gen_int_mode (INTVAL (src
),
1283 gen_rtx_SET (VOIDmode
,
1284 gen_rtx_STRICT_LOW_PART (VOIDmode
,
1287 if (validate_change (insn
, &PATTERN (insn
),
1293 reg_set_luid
[regno
] = move2add_luid
;
1294 reg_mode
[regno
] = GET_MODE (reg
);
1295 reg_offset
[regno
] = INTVAL (src
);
1299 /* Try to transform (set (REGX) (REGY))
1300 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1303 (set (REGX) (PLUS (REGX) (CONST_INT B)))
1306 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1308 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
1309 else if (REG_P (src
)
1310 && reg_set_luid
[regno
] == reg_set_luid
[REGNO (src
)]
1311 && reg_base_reg
[regno
] == reg_base_reg
[REGNO (src
)]
1312 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg
),
1313 reg_mode
[REGNO (src
)]))
1315 rtx next
= next_nonnote_insn (insn
);
1318 set
= single_set (next
);
1320 && SET_DEST (set
) == reg
1321 && GET_CODE (SET_SRC (set
)) == PLUS
1322 && XEXP (SET_SRC (set
), 0) == reg
1323 && GET_CODE (XEXP (SET_SRC (set
), 1)) == CONST_INT
)
1325 rtx src3
= XEXP (SET_SRC (set
), 1);
1326 HOST_WIDE_INT added_offset
= INTVAL (src3
);
1327 HOST_WIDE_INT base_offset
= reg_offset
[REGNO (src
)];
1328 HOST_WIDE_INT regno_offset
= reg_offset
[regno
];
1330 gen_int_mode (added_offset
1336 if (new_src
== const0_rtx
)
1337 /* See above why we create (set (reg) (reg)) here. */
1339 = validate_change (next
, &SET_SRC (set
), reg
, 0);
1340 else if ((rtx_cost (new_src
, PLUS
)
1341 < COSTS_N_INSNS (1) + rtx_cost (src3
, SET
))
1342 && have_add2_insn (reg
, new_src
))
1344 rtx newpat
= gen_rtx_SET (VOIDmode
,
1346 gen_rtx_PLUS (GET_MODE (reg
),
1350 = validate_change (next
, &PATTERN (next
),
1356 reg_mode
[regno
] = GET_MODE (reg
);
1358 trunc_int_for_mode (added_offset
+ base_offset
,
1366 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
1368 if (REG_NOTE_KIND (note
) == REG_INC
1369 && REG_P (XEXP (note
, 0)))
1371 /* Reset the information about this register. */
1372 int regno
= REGNO (XEXP (note
, 0));
1373 if (regno
< FIRST_PSEUDO_REGISTER
)
1374 reg_set_luid
[regno
] = 0;
1377 note_stores (PATTERN (insn
), move2add_note_store
, NULL
);
1379 /* If INSN is a conditional branch, we try to extract an
1380 implicit set out of it. */
1381 if (any_condjump_p (insn
))
1383 rtx cnd
= fis_get_condition (insn
);
1386 && GET_CODE (cnd
) == NE
1387 && REG_P (XEXP (cnd
, 0))
1388 && !reg_set_p (XEXP (cnd
, 0), insn
)
1389 /* The following two checks, which are also in
1390 move2add_note_store, are intended to reduce the
1391 number of calls to gen_rtx_SET to avoid memory
1392 allocation if possible. */
1393 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd
, 0)))
1394 && hard_regno_nregs
[REGNO (XEXP (cnd
, 0))][GET_MODE (XEXP (cnd
, 0))] == 1
1395 && GET_CODE (XEXP (cnd
, 1)) == CONST_INT
)
1398 gen_rtx_SET (VOIDmode
, XEXP (cnd
, 0), XEXP (cnd
, 1));
1399 move2add_note_store (SET_DEST (implicit_set
), implicit_set
, 0);
1403 /* If this is a CALL_INSN, all call used registers are stored with
1407 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
1409 if (call_used_regs
[i
])
1410 /* Reset the information about this register. */
1411 reg_set_luid
[i
] = 0;
1417 /* SET is a SET or CLOBBER that sets DST.
1418 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
1419 Called from reload_cse_move2add via note_stores. */
1422 move2add_note_store (rtx dst
, rtx set
, void *data ATTRIBUTE_UNUSED
)
1424 unsigned int regno
= 0;
1425 unsigned int nregs
= 0;
1427 enum machine_mode mode
= GET_MODE (dst
);
1429 if (GET_CODE (dst
) == SUBREG
)
1431 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
1432 GET_MODE (SUBREG_REG (dst
)),
1435 nregs
= subreg_nregs (dst
);
1436 dst
= SUBREG_REG (dst
);
1439 /* Some targets do argument pushes without adding REG_INC notes. */
1443 dst
= XEXP (dst
, 0);
1444 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
1445 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
)
1446 reg_set_luid
[REGNO (XEXP (dst
, 0))] = 0;
1452 regno
+= REGNO (dst
);
1454 nregs
= hard_regno_nregs
[regno
][mode
];
1456 if (SCALAR_INT_MODE_P (GET_MODE (dst
))
1457 && nregs
== 1 && GET_CODE (set
) == SET
1458 && GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
1459 && GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
)
1461 rtx src
= SET_SRC (set
);
1463 HOST_WIDE_INT offset
;
1465 /* This may be different from mode, if SET_DEST (set) is a
1467 enum machine_mode dst_mode
= GET_MODE (dst
);
1469 switch (GET_CODE (src
))
1472 if (REG_P (XEXP (src
, 0)))
1474 base_reg
= XEXP (src
, 0);
1476 if (GET_CODE (XEXP (src
, 1)) == CONST_INT
)
1477 offset
= INTVAL (XEXP (src
, 1));
1478 else if (REG_P (XEXP (src
, 1))
1479 && (reg_set_luid
[REGNO (XEXP (src
, 1))]
1480 > move2add_last_label_luid
)
1481 && (MODES_OK_FOR_MOVE2ADD
1482 (dst_mode
, reg_mode
[REGNO (XEXP (src
, 1))])))
1484 if (reg_base_reg
[REGNO (XEXP (src
, 1))] < 0)
1485 offset
= reg_offset
[REGNO (XEXP (src
, 1))];
1486 /* Maybe the first register is known to be a
1488 else if (reg_set_luid
[REGNO (base_reg
)]
1489 > move2add_last_label_luid
1490 && (MODES_OK_FOR_MOVE2ADD
1491 (dst_mode
, reg_mode
[REGNO (XEXP (src
, 1))]))
1492 && reg_base_reg
[REGNO (base_reg
)] < 0)
1494 offset
= reg_offset
[REGNO (base_reg
)];
1495 base_reg
= XEXP (src
, 1);
1514 /* Start tracking the register as a constant. */
1515 reg_base_reg
[regno
] = -1;
1516 reg_offset
[regno
] = INTVAL (SET_SRC (set
));
1517 /* We assign the same luid to all registers set to constants. */
1518 reg_set_luid
[regno
] = move2add_last_label_luid
+ 1;
1519 reg_mode
[regno
] = mode
;
1524 /* Invalidate the contents of the register. */
1525 reg_set_luid
[regno
] = 0;
1529 base_regno
= REGNO (base_reg
);
1530 /* If information about the base register is not valid, set it
1531 up as a new base register, pretending its value is known
1532 starting from the current insn. */
1533 if (reg_set_luid
[base_regno
] <= move2add_last_label_luid
)
1535 reg_base_reg
[base_regno
] = base_regno
;
1536 reg_offset
[base_regno
] = 0;
1537 reg_set_luid
[base_regno
] = move2add_luid
;
1538 reg_mode
[base_regno
] = mode
;
1540 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode
,
1541 reg_mode
[base_regno
]))
1544 reg_mode
[regno
] = mode
;
1546 /* Copy base information from our base register. */
1547 reg_set_luid
[regno
] = reg_set_luid
[base_regno
];
1548 reg_base_reg
[regno
] = reg_base_reg
[base_regno
];
1550 /* Compute the sum of the offsets or constants. */
1551 reg_offset
[regno
] = trunc_int_for_mode (offset
1552 + reg_offset
[base_regno
],
1557 unsigned int endregno
= regno
+ nregs
;
1559 for (i
= regno
; i
< endregno
; i
++)
1560 /* Reset the information about this register. */
1561 reg_set_luid
[i
] = 0;
1566 gate_handle_postreload (void)
1568 return (optimize
> 0);
1573 rest_of_handle_postreload (void)
1575 if (!dbg_cnt (postreload_cse
))
1578 /* Do a very simple CSE pass over just the hard registers. */
1579 reload_cse_regs (get_insns ());
1580 /* Reload_cse_regs can eliminate potentially-trapping MEMs.
1581 Remove any EH edges associated with them. */
1582 if (flag_non_call_exceptions
)
1583 purge_all_dead_edges ();
1588 struct tree_opt_pass pass_postreload_cse
=
1590 "postreload", /* name */
1591 gate_handle_postreload
, /* gate */
1592 rest_of_handle_postreload
, /* execute */
1595 0, /* static_pass_number */
1596 TV_RELOAD_CSE_REGS
, /* tv_id */
1597 0, /* properties_required */
1598 0, /* properties_provided */
1599 0, /* properties_destroyed */
1600 0, /* todo_flags_start */
1602 TODO_dump_func
, /* todo_flags_finish */