| blob | d78f4e7f1759d83bccbabdd1cf7725d5ee7affbd |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
91 /* This file should be included last. */
98 #ifndef CHECK_STACK_LIMIT
99 #define CHECK_STACK_LIMIT (-1)
100 #endif
102 /* Return index of given mode in mult and division cost tables. */
103 #define MODE_INDEX(mode) \
104 ((mode) == QImode ? 0 \
105 : (mode) == HImode ? 1 \
106 : (mode) == SImode ? 2 \
107 : (mode) == DImode ? 3 \
108 : 4)
110 /* Processor costs (relative to an add) */
111 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
112 #define COSTS_N_BYTES(N) ((N) * 2)
114 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
123 const
146 in QImode, HImode and SImode.
147 Relative to reg-reg move (2). */
151 in SFmode, DFmode and XFmode */
153 in SFmode, DFmode and XFmode */
156 in SImode and DImode */
158 in SImode and DImode */
161 in SImode, DImode and TImode */
163 in SImode, DImode and TImode */
176 ix86_size_memcpy,
177 ix86_size_memset,
189 };
191 /* Processor costs (relative to an add) */
194 DUMMY_STRINGOP_ALGS};
197 DUMMY_STRINGOP_ALGS};
199 static const
222 in QImode, HImode and SImode.
223 Relative to reg-reg move (2). */
227 in SFmode, DFmode and XFmode */
229 in SFmode, DFmode and XFmode */
232 in SImode and DImode */
234 in SImode and DImode */
237 in SImode, DImode and TImode */
239 in SImode, DImode and TImode */
252 i386_memcpy,
253 i386_memset,
265 };
269 DUMMY_STRINGOP_ALGS};
272 DUMMY_STRINGOP_ALGS};
274 static const
297 in QImode, HImode and SImode.
298 Relative to reg-reg move (2). */
302 in SFmode, DFmode and XFmode */
304 in SFmode, DFmode and XFmode */
307 in SImode and DImode */
309 in SImode and DImode */
312 in SImode, DImode and TImode */
314 in SImode, DImode and TImode */
317 shared for code and data, so 4kB is
318 not really precise. */
329 i486_memcpy,
330 i486_memset,
342 };
346 DUMMY_STRINGOP_ALGS};
349 DUMMY_STRINGOP_ALGS};
351 static const
374 in QImode, HImode and SImode.
375 Relative to reg-reg move (2). */
379 in SFmode, DFmode and XFmode */
381 in SFmode, DFmode and XFmode */
384 in SImode and DImode */
386 in SImode and DImode */
389 in SImode, DImode and TImode */
391 in SImode, DImode and TImode */
404 pentium_memcpy,
405 pentium_memset,
417 };
419 static const
442 in QImode, HImode and SImode.
443 Relative to reg-reg move (2). */
447 in SFmode, DFmode and XFmode */
449 in SFmode, DFmode and XFmode */
452 in SImode and DImode */
454 in SImode and DImode */
457 in SImode, DImode and TImode */
459 in SImode, DImode and TImode */
472 pentium_memcpy,
473 pentium_memset,
485 };
487 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
488 (we ensure the alignment). For small blocks inline loop is still a
489 noticeable win, for bigger blocks either rep movsl or rep movsb is
490 way to go. Rep movsb has apparently more expensive startup time in CPU,
491 but after 4K the difference is down in the noise. */
496 DUMMY_STRINGOP_ALGS};
501 DUMMY_STRINGOP_ALGS};
502 static const
525 in QImode, HImode and SImode.
526 Relative to reg-reg move (2). */
530 in SFmode, DFmode and XFmode */
532 in SFmode, DFmode and XFmode */
535 in SImode and DImode */
537 in SImode and DImode */
540 in SImode, DImode and TImode */
542 in SImode, DImode and TImode */
555 pentiumpro_memcpy,
556 pentiumpro_memset,
568 };
572 DUMMY_STRINGOP_ALGS};
575 DUMMY_STRINGOP_ALGS};
576 static const
599 in QImode, HImode and SImode.
600 Relative to reg-reg move (2). */
604 in SFmode, DFmode and XFmode */
606 in SFmode, DFmode and XFmode */
610 in SImode and DImode */
612 in SImode and DImode */
615 in SImode, DImode and TImode */
617 in SImode, DImode and TImode */
630 geode_memcpy,
631 geode_memset,
643 };
647 DUMMY_STRINGOP_ALGS};
650 DUMMY_STRINGOP_ALGS};
651 static const
674 in QImode, HImode and SImode.
675 Relative to reg-reg move (2). */
679 in SFmode, DFmode and XFmode */
681 in SFmode, DFmode and XFmode */
684 in SImode and DImode */
686 in SImode and DImode */
689 in SImode, DImode and TImode */
691 in SImode, DImode and TImode */
695 have integrated l2 cache, but
696 optimizing for k6 is not important
697 enough to worry about that. */
707 k6_memcpy,
708 k6_memset,
720 };
722 /* For some reason, Athlon deals better with REP prefix (relative to loops)
723 compared to K8. Alignment becomes important after 8 bytes for memcpy and
724 128 bytes for memset. */
727 DUMMY_STRINGOP_ALGS};
730 DUMMY_STRINGOP_ALGS};
731 static const
754 in QImode, HImode and SImode.
755 Relative to reg-reg move (2). */
759 in SFmode, DFmode and XFmode */
761 in SFmode, DFmode and XFmode */
764 in SImode and DImode */
766 in SImode and DImode */
769 in SImode, DImode and TImode */
771 in SImode, DImode and TImode */
784 athlon_memcpy,
785 athlon_memset,
797 };
799 /* K8 has optimized REP instruction for medium sized blocks, but for very
800 small blocks it is better to use loop. For large blocks, libcall can
801 do nontemporary accesses and beat inline considerably. */
812 static const
835 in QImode, HImode and SImode.
836 Relative to reg-reg move (2). */
840 in SFmode, DFmode and XFmode */
842 in SFmode, DFmode and XFmode */
845 in SImode and DImode */
847 in SImode and DImode */
850 in SImode, DImode and TImode */
852 in SImode, DImode and TImode */
857 /* New AMD processors never drop prefetches; if they cannot be performed
858 immediately, they are queued. We set number of simultaneous prefetches
859 to a large constant to reflect this (it probably is not a good idea not
860 to limit number of prefetches at all, as their execution also takes some
861 time). */
871 k8_memcpy,
872 k8_memset,
884 };
886 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
887 very small blocks it is better to use loop. For large blocks, libcall can
888 do nontemporary accesses and beat inline considerably. */
921 in QImode, HImode and SImode.
922 Relative to reg-reg move (2). */
926 in SFmode, DFmode and XFmode */
928 in SFmode, DFmode and XFmode */
931 in SImode and DImode */
933 in SImode and DImode */
936 in SImode, DImode and TImode */
938 in SImode, DImode and TImode */
940 /* On K8:
941 MOVD reg64, xmmreg Double FSTORE 4
942 MOVD reg32, xmmreg Double FSTORE 4
943 On AMDFAM10:
944 MOVD reg64, xmmreg Double FADD 3
945 1/1 1/1
946 MOVD reg32, xmmreg Double FADD 3
947 1/1 1/1 */
951 /* New AMD processors never drop prefetches; if they cannot be performed
952 immediately, they are queued. We set number of simultaneous prefetches
953 to a large constant to reflect this (it probably is not a good idea not
954 to limit number of prefetches at all, as their execution also takes some
955 time). */
965 amdfam10_memcpy,
966 amdfam10_memset,
978 };
980 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
981 very small blocks it is better to use loop. For large blocks, libcall
982 can do nontemporary accesses and beat inline considerably. */
1016 in QImode, HImode and SImode.
1017 Relative to reg-reg move (2). */
1021 in SFmode, DFmode and XFmode */
1023 in SFmode, DFmode and XFmode */
1026 in SImode and DImode */
1028 in SImode and DImode */
1031 in SImode, DImode and TImode */
1033 in SImode, DImode and TImode */
1035 /* On K8:
1036 MOVD reg64, xmmreg Double FSTORE 4
1037 MOVD reg32, xmmreg Double FSTORE 4
1038 On AMDFAM10:
1039 MOVD reg64, xmmreg Double FADD 3
1040 1/1 1/1
1041 MOVD reg32, xmmreg Double FADD 3
1042 1/1 1/1 */
1046 /* New AMD processors never drop prefetches; if they cannot be performed
1047 immediately, they are queued. We set number of simultaneous prefetches
1048 to a large constant to reflect this (it probably is not a good idea not
1049 to limit number of prefetches at all, as their execution also takes some
1050 time). */
1060 bdver1_memcpy,
1061 bdver1_memset,
1073 };
1075 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1076 very small blocks it is better to use loop. For large blocks, libcall
1077 can do nontemporary accesses and beat inline considerably. */
1112 in QImode, HImode and SImode.
1113 Relative to reg-reg move (2). */
1117 in SFmode, DFmode and XFmode */
1119 in SFmode, DFmode and XFmode */
1122 in SImode and DImode */
1124 in SImode and DImode */
1127 in SImode, DImode and TImode */
1129 in SImode, DImode and TImode */
1131 /* On K8:
1132 MOVD reg64, xmmreg Double FSTORE 4
1133 MOVD reg32, xmmreg Double FSTORE 4
1134 On AMDFAM10:
1135 MOVD reg64, xmmreg Double FADD 3
1136 1/1 1/1
1137 MOVD reg32, xmmreg Double FADD 3
1138 1/1 1/1 */
1142 /* New AMD processors never drop prefetches; if they cannot be performed
1143 immediately, they are queued. We set number of simultaneous prefetches
1144 to a large constant to reflect this (it probably is not a good idea not
1145 to limit number of prefetches at all, as their execution also takes some
1146 time). */
1156 bdver2_memcpy,
1157 bdver2_memset,
1169 };
1172 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1173 very small blocks it is better to use loop. For large blocks, libcall
1174 can do nontemporary accesses and beat inline considerably. */
1207 in QImode, HImode and SImode.
1208 Relative to reg-reg move (2). */
1212 in SFmode, DFmode and XFmode */
1214 in SFmode, DFmode and XFmode */
1217 in SImode and DImode */
1219 in SImode and DImode */
1222 in SImode, DImode and TImode */
1224 in SImode, DImode and TImode */
1229 /* New AMD processors never drop prefetches; if they cannot be performed
1230 immediately, they are queued. We set number of simultaneous prefetches
1231 to a large constant to reflect this (it probably is not a good idea not
1232 to limit number of prefetches at all, as their execution also takes some
1233 time). */
1243 bdver3_memcpy,
1244 bdver3_memset,
1256 };
1258 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1259 very small blocks it is better to use loop. For large blocks, libcall
1260 can do nontemporary accesses and beat inline considerably. */
1293 in QImode, HImode and SImode.
1294 Relative to reg-reg move (2). */
1298 in SFmode, DFmode and XFmode */
1300 in SFmode, DFmode and XFmode */
1303 in SImode and DImode */
1305 in SImode and DImode */
1308 in SImode, DImode and TImode */
1310 in SImode, DImode and TImode */
1315 /* New AMD processors never drop prefetches; if they cannot be performed
1316 immediately, they are queued. We set number of simultaneous prefetches
1317 to a large constant to reflect this (it probably is not a good idea not
1318 to limit number of prefetches at all, as their execution also takes some
1319 time). */
1329 bdver4_memcpy,
1330 bdver4_memset,
1342 };
1344 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1345 very small blocks it is better to use loop. For large blocks, libcall can
1346 do nontemporary accesses and beat inline considerably. */
1379 in QImode, HImode and SImode.
1380 Relative to reg-reg move (2). */
1384 in SFmode, DFmode and XFmode */
1386 in SFmode, DFmode and XFmode */
1389 in SImode and DImode */
1391 in SImode and DImode */
1394 in SImode, DImode and TImode */
1396 in SImode, DImode and TImode */
1398 /* On K8:
1399 MOVD reg64, xmmreg Double FSTORE 4
1400 MOVD reg32, xmmreg Double FSTORE 4
1401 On AMDFAM10:
1402 MOVD reg64, xmmreg Double FADD 3
1403 1/1 1/1
1404 MOVD reg32, xmmreg Double FADD 3
1405 1/1 1/1 */
1418 btver1_memcpy,
1419 btver1_memset,
1431 };
1465 in QImode, HImode and SImode.
1466 Relative to reg-reg move (2). */
1470 in SFmode, DFmode and XFmode */
1472 in SFmode, DFmode and XFmode */
1475 in SImode and DImode */
1477 in SImode and DImode */
1480 in SImode, DImode and TImode */
1482 in SImode, DImode and TImode */
1484 /* On K8:
1485 MOVD reg64, xmmreg Double FSTORE 4
1486 MOVD reg32, xmmreg Double FSTORE 4
1487 On AMDFAM10:
1488 MOVD reg64, xmmreg Double FADD 3
1489 1/1 1/1
1490 MOVD reg32, xmmreg Double FADD 3
1491 1/1 1/1 */
1503 btver2_memcpy,
1504 btver2_memset,
1516 };
1520 DUMMY_STRINGOP_ALGS};
1524 DUMMY_STRINGOP_ALGS};
1526 static const
1549 in QImode, HImode and SImode.
1550 Relative to reg-reg move (2). */
1554 in SFmode, DFmode and XFmode */
1556 in SFmode, DFmode and XFmode */
1559 in SImode and DImode */
1561 in SImode and DImode */
1564 in SImode, DImode and TImode */
1566 in SImode, DImode and TImode */
1579 pentium4_memcpy,
1580 pentium4_memset,
1592 };
1605 static const
1628 in QImode, HImode and SImode.
1629 Relative to reg-reg move (2). */
1633 in SFmode, DFmode and XFmode */
1635 in SFmode, DFmode and XFmode */
1638 in SImode and DImode */
1640 in SImode and DImode */
1643 in SImode, DImode and TImode */
1645 in SImode, DImode and TImode */
1658 nocona_memcpy,
1659 nocona_memset,
1671 };
1682 static const
1705 in QImode, HImode and SImode.
1706 Relative to reg-reg move (2). */
1710 in SFmode, DFmode and XFmode */
1712 in SFmode, DFmode and XFmode */
1715 in SImode and DImode */
1717 in SImode and DImode */
1720 in SImode, DImode and TImode */
1722 in SImode, DImode and TImode */
1735 atom_memcpy,
1736 atom_memset,
1748 };
1759 static const
1782 in QImode, HImode and SImode.
1783 Relative to reg-reg move (2). */
1787 in SFmode, DFmode and XFmode */
1789 in SFmode, DFmode and XFmode */
1792 in SImode and DImode */
1794 in SImode and DImode */
1797 in SImode, DImode and TImode */
1799 in SImode, DImode and TImode */
1812 slm_memcpy,
1813 slm_memset,
1825 };
1836 static const
1859 in QImode, HImode and SImode.
1860 Relative to reg-reg move (2). */
1864 in SFmode, DFmode and XFmode */
1866 in SFmode, DFmode and XFmode */
1869 in SImode and DImode */
1871 in SImode and DImode */
1874 in SImode, DImode and TImode */
1876 in SImode, DImode and TImode */
1889 intel_memcpy,
1890 intel_memset,
1902 };
1904 /* Generic should produce code tuned for Core-i7 (and newer chips)
1905 and btver1 (and newer chips). */
1917 static const
1920 /* On all chips taken into consideration lea is 2 cycles and more. With
1921 this cost however our current implementation of synth_mult results in
1922 use of unnecessary temporary registers causing regression on several
1923 SPECfp benchmarks. */
1944 in QImode, HImode and SImode.
1945 Relative to reg-reg move (2). */
1949 in SFmode, DFmode and XFmode */
1951 in SFmode, DFmode and XFmode */
1954 in SImode and DImode */
1956 in SImode and DImode */
1959 in SImode, DImode and TImode */
1961 in SImode, DImode and TImode */
1967 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1968 value is increased to perhaps more appropriate value of 5. */
1976 generic_memcpy,
1977 generic_memset,
1989 };
1991 /* core_cost should produce code tuned for Core familly of CPUs. */
2004 static const
2007 /* On all chips taken into consideration lea is 2 cycles and more. With
2008 this cost however our current implementation of synth_mult results in
2009 use of unnecessary temporary registers causing regression on several
2010 SPECfp benchmarks. */
2031 in QImode, HImode and SImode.
2032 Relative to reg-reg move (2). */
2036 in SFmode, DFmode and XFmode */
2038 in SFmode, DFmode and XFmode */
2041 in SImode and DImode */
2043 in SImode and DImode */
2046 in SImode, DImode and TImode */
2048 in SImode, DImode and TImode */
2054 /* FIXME perhaps more appropriate value is 5. */
2062 core_memcpy,
2063 core_memset,
2075 };
2078 /* Set by -mtune. */
2081 /* Set by -mtune or -Os. */
2084 /* Processor feature/optimization bitmasks. */
2085 #define m_386 (1<<PROCESSOR_I386)
2086 #define m_486 (1<<PROCESSOR_I486)
2087 #define m_PENT (1<<PROCESSOR_PENTIUM)
2088 #define m_IAMCU (1<<PROCESSOR_IAMCU)
2089 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2090 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2091 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2092 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2093 #define m_CORE2 (1<<PROCESSOR_CORE2)
2094 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2095 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2096 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2097 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2098 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2099 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2100 #define m_KNL (1<<PROCESSOR_KNL)
2101 #define m_INTEL (1<<PROCESSOR_INTEL)
2103 #define m_GEODE (1<<PROCESSOR_GEODE)
2104 #define m_K6 (1<<PROCESSOR_K6)
2105 #define m_K6_GEODE (m_K6 | m_GEODE)
2106 #define m_K8 (1<<PROCESSOR_K8)
2107 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2108 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2109 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2110 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2111 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2112 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2113 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2114 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2115 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2116 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2117 #define m_BTVER (m_BTVER1 | m_BTVER2)
2118 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2120 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2123 #undef DEF_TUNE
2124 #define DEF_TUNE(tune, name, selector) name,
2126 #undef DEF_TUNE
2127 };
2129 /* Feature tests against the various tunings. */
2132 /* Feature tests against the various tunings used to create ix86_tune_features
2133 based on the processor mask. */
2135 #undef DEF_TUNE
2136 #define DEF_TUNE(tune, name, selector) selector,
2138 #undef DEF_TUNE
2139 };
2141 /* Feature tests against the various architecture variations. */
2144 /* Feature tests against the various architecture variations, used to create
2145 ix86_arch_features based on the processor mask. */
2147 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2150 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2153 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2156 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2159 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2161 };
2163 /* In case the average insn count for single function invocation is
2164 lower than this constant, emit fast (but longer) prologue and
2165 epilogue code. */
2166 #define FAST_PROLOGUE_INSN_COUNT 20
2168 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2173 /* Array of the smallest class containing reg number REGNO, indexed by
2174 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2177 {
2178 /* ax, dx, cx, bx */
2180 /* si, di, bp, sp */
2182 /* FP registers */
2185 /* arg pointer */
2186 NON_Q_REGS,
2187 /* flags, fpsr, fpcr, frame */
2189 /* SSE registers */
2192 /* MMX registers */
2195 /* REX registers */
2198 /* SSE REX registers */
2201 /* AVX-512 SSE registers */
2206 /* Mask registers. */
2209 /* MPX bound registers */
2211 };
2213 /* The "default" register map used in 32bit mode. */
2216 {
2228 };
2230 /* The "default" register map used in 64bit mode. */
2233 {
2245 };
2247 /* Define the register numbers to be used in Dwarf debugging information.
2248 The SVR4 reference port C compiler uses the following register numbers
2249 in its Dwarf output code:
2250 0 for %eax (gcc regno = 0)
2251 1 for %ecx (gcc regno = 2)
2252 2 for %edx (gcc regno = 1)
2253 3 for %ebx (gcc regno = 3)
2254 4 for %esp (gcc regno = 7)
2255 5 for %ebp (gcc regno = 6)
2256 6 for %esi (gcc regno = 4)
2257 7 for %edi (gcc regno = 5)
2258 The following three DWARF register numbers are never generated by
2259 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2260 believes these numbers have these meanings.
2261 8 for %eip (no gcc equivalent)
2262 9 for %eflags (gcc regno = 17)
2263 10 for %trapno (no gcc equivalent)
2264 It is not at all clear how we should number the FP stack registers
2265 for the x86 architecture. If the version of SDB on x86/svr4 were
2266 a bit less brain dead with respect to floating-point then we would
2267 have a precedent to follow with respect to DWARF register numbers
2268 for x86 FP registers, but the SDB on x86/svr4 is so completely
2269 broken with respect to FP registers that it is hardly worth thinking
2270 of it as something to strive for compatibility with.
2271 The version of x86/svr4 SDB I have at the moment does (partially)
2272 seem to believe that DWARF register number 11 is associated with
2273 the x86 register %st(0), but that's about all. Higher DWARF
2274 register numbers don't seem to be associated with anything in
2275 particular, and even for DWARF regno 11, SDB only seems to under-
2276 stand that it should say that a variable lives in %st(0) (when
2277 asked via an `=' command) if we said it was in DWARF regno 11,
2278 but SDB still prints garbage when asked for the value of the
2279 variable in question (via a `/' command).
2280 (Also note that the labels SDB prints for various FP stack regs
2281 when doing an `x' command are all wrong.)
2282 Note that these problems generally don't affect the native SVR4
2283 C compiler because it doesn't allow the use of -O with -g and
2284 because when it is *not* optimizing, it allocates a memory
2285 location for each floating-point variable, and the memory
2286 location is what gets described in the DWARF AT_location
2287 attribute for the variable in question.
2288 Regardless of the severe mental illness of the x86/svr4 SDB, we
2289 do something sensible here and we use the following DWARF
2290 register numbers. Note that these are all stack-top-relative
2291 numbers.
2292 11 for %st(0) (gcc regno = 8)
2293 12 for %st(1) (gcc regno = 9)
2294 13 for %st(2) (gcc regno = 10)
2295 14 for %st(3) (gcc regno = 11)
2296 15 for %st(4) (gcc regno = 12)
2297 16 for %st(5) (gcc regno = 13)
2298 17 for %st(6) (gcc regno = 14)
2299 18 for %st(7) (gcc regno = 15)
2300 */
2302 {
2314 };
2316 /* Define parameter passing and return registers. */
2319 {
2321 };
2324 {
2326 };
2329 {
2331 };
2333 /* Additional registers that are clobbered by SYSV calls. */
2336 {
2341 };
2343 /* Define the structure for the machine field in struct function. */
2348 rtx rtl;
2350 };
2352 /* Structure describing stack frame layout.
2353 Stack grows downward:
2355 [arguments]
2356 <- ARG_POINTER
2357 saved pc
2359 saved static chain if ix86_static_chain_on_stack
2361 saved frame pointer if frame_pointer_needed
2362 <- HARD_FRAME_POINTER
2363 [saved regs]
2364 <- regs_save_offset
2365 [padding0]
2367 [saved SSE regs]
2368 <- sse_regs_save_offset
2369 [padding1] |
2370 | <- FRAME_POINTER
2371 [va_arg registers] |
2372 |
2373 [frame] |
2374 |
2375 [padding2] | = to_allocate
2376 <- STACK_POINTER
2377 */
2378 struct ix86_frame
2379 {
2386 /* The offsets relative to ARG_POINTER. */
2387 HOST_WIDE_INT frame_pointer_offset;
2388 HOST_WIDE_INT hard_frame_pointer_offset;
2389 HOST_WIDE_INT stack_pointer_offset;
2390 HOST_WIDE_INT hfp_save_offset;
2391 HOST_WIDE_INT reg_save_offset;
2392 HOST_WIDE_INT sse_reg_save_offset;
2394 /* When save_regs_using_mov is set, emit prologue using
2395 move instead of push instructions. */
2397 };
2399 /* Which cpu are we scheduling for. */
2402 /* Which cpu are we optimizing for. */
2405 /* Which instruction set architecture to use. */
2408 /* True if processor has SSE prefetch instruction. */
2411 /* -mstackrealign option */
2429 /* Preferred alignment for stack boundary in bits. */
2432 /* Alignment for incoming stack boundary in bits specified at
2433 command line. */
2436 /* Default alignment for incoming stack boundary in bits. */
2439 /* Alignment for incoming stack boundary in bits. */
2442 /* Calling abi specific va_list type nodes. */
2446 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2450 /* Fence to use after loop using movnt. */
2451 tree x86_mfence;
2453 /* Register class used for passing given 64bit part of the argument.
2454 These represent classes as documented by the PS ABI, with the exception
2455 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2456 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2458 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2459 whenever possible (upper half does contain padding). */
2460 enum x86_64_reg_class
2461 {
2462 X86_64_NO_CLASS,
2463 X86_64_INTEGER_CLASS,
2464 X86_64_INTEGERSI_CLASS,
2465 X86_64_SSE_CLASS,
2466 X86_64_SSESF_CLASS,
2467 X86_64_SSEDF_CLASS,
2468 X86_64_SSEUP_CLASS,
2469 X86_64_X87_CLASS,
2470 X86_64_X87UP_CLASS,
2471 X86_64_COMPLEX_X87_CLASS,
2472 X86_64_MEMORY_CLASS
2473 };
2475 #define MAX_CLASSES 8
2477 /* Table of constants used by fldpi, fldln2, etc.... */
2481 \f
2486 const_tree);
2498 enum ix86_function_specific_strings
2499 {
2500 IX86_FUNCTION_SPECIFIC_ARCH,
2501 IX86_FUNCTION_SPECIFIC_TUNE,
2502 IX86_FUNCTION_SPECIFIC_MAX
2503 };
2525 \f
2526 #ifndef SUBTARGET32_DEFAULT_CPU
2528 #endif
2530 /* Whether -mtune= or -march= were specified */
2534 /* Vectorization library interface and handlers. */
2540 /* Processor target table, indexed by processor number */
2541 struct ptt
2542 {
2550 };
2552 /* This table must be in sync with enum processor_type in i386.h. */
2554 {
2582 };
2583 \f
2584 static unsigned int
2586 {
2589 /* vzeroupper instructions are inserted immediately after reload to
2590 account for possible spills from 256bit registers. The pass
2591 reuses mode switching infrastructure by re-running mode insertion
2592 pass, so disable entities that have already been processed. */
2598 /* Call optimize_mode_switching. */
2601 }
2606 {
2616 };
2619 {
2623 {}
2625 /* opt_pass methods: */
2627 {
2631 }
2634 {
2636 }
2642 rtl_opt_pass *
2644 {
2646 }
2648 /* Return true if a red-zone is in use. */
2652 {
2654 }
2655 \f
2656 /* Return a string that documents the current -m options. The caller is
2657 responsible for freeing the string. */
2663 {
2664 struct ix86_target_opts
2665 {
2668 };
2670 /* This table is ordered so that options like -msse4.2 that imply
2671 preceding options while match those first. */
2673 {
2727 };
2729 /* Flag options. */
2731 {
2760 };
2777 /* Add -march= option. */
2779 {
2782 }
2784 /* Add -mtune= option. */
2786 {
2789 }
2791 /* Add -m32/-m64/-mx32. */
2793 {
2796 else
2798 isa &= ~ (OPTION_MASK_ISA_64BIT
2799 | OPTION_MASK_ABI_64
2801 }
2802 else
2806 /* Pick out the options in isa options. */
2808 {
2810 {
2813 }
2814 }
2817 {
2820 isa);
2821 }
2823 /* Add flag options. */
2825 {
2827 {
2830 }
2831 }
2834 {
2837 }
2839 /* Add -fpmath= option. */
2841 {
2844 {
2859 }
2860 }
2862 /* Any options? */
2868 /* Size the string. */
2872 {
2877 }
2879 /* Build the string. */
2884 {
2891 {
2893 line_len++;
2896 {
2900 }
2901 }
2905 {
2909 }
2910 }
2916 }
2918 /* Return true, if profiling code should be emitted before
2919 prologue. Otherwise it returns false.
2920 Note: For x86 with "hotfix" it is sorried. */
2921 static bool
2923 {
2925 }
2927 /* Function that is callable from the debugger to print the current
2928 options. */
2929 void ATTRIBUTE_UNUSED
2931 {
2937 {
2940 }
2941 else
2945 }
2948 #define DEF_ENUM
2949 #define DEF_ALG(alg, name) #name,
2951 #undef DEF_ENUM
2952 #undef DEF_ALG
2953 };
2955 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2956 The string is of the following form (or comma separated list of it):
2958 strategy_alg:max_size:[align|noalign]
2960 where the full size range for the strategy is either [0, max_size] or
2961 [min_size, max_size], in which min_size is the max_size + 1 of the
2962 preceding range. The last size range must have max_size == -1.
2964 Examples:
2966 1.
2967 -mmemcpy-strategy=libcall:-1:noalign
2969 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2972 2.
2973 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2975 This is to tell the compiler to use the following strategy for memset
2976 1) when the expected size is between [1, 16], use rep_8byte strategy;
2977 2) when the size is between [17, 2048], use vector_loop;
2978 3) when the size is > 2048, use libcall. */
2980 struct stringop_size_range
2981 {
2983 stringop_alg alg;
2985 };
2987 static void
2989 {
2997 else
3002 do
3003 {
3013 {
3017 }
3020 {
3024 }
3031 {
3033 alg_name,
3036 }
3040 {
3041 /* rep; movq isn't available in 32-bit code. */
3044 alg_name,
3047 }
3055 else
3056 {
3060 }
3061 n++;
3063 }
3067 {
3072 }
3075 {
3079 }
3081 /* Now override the default algs array. */
3083 {
3089 }
3090 }
3092 \f
3093 /* parse -mtune-ctrl= option. When DUMP is true,
3094 print the features that are explicitly set. */
3096 static void
3098 {
3106 do
3107 {
3114 {
3115 curr_feature_string++;
3117 }
3119 {
3121 {
3127 }
3128 }
3133 }
3136 }
3138 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3139 processor type. */
3141 static void
3143 {
3148 {
3151 else
3153 }
3156 {
3161 }
3164 }
3167 /* Default align_* from the processor table. */
3169 static void
3171 {
3173 {
3176 }
3178 {
3181 }
3183 {
3185 }
3186 }
3188 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE hook. */
3190 static void
3192 {
3194 }
3196 /* Override various settings based on options. If MAIN_ARGS_P, the
3197 options are from the command line, otherwise they are from
3198 attributes. */
3200 static void
3204 {
3212 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3213 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3214 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3215 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3216 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3217 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3218 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3219 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3220 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3221 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3222 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3223 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3224 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3225 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3226 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3227 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3228 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3229 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3230 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3231 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3232 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3233 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3234 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3235 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3236 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3237 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3238 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3239 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3240 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3241 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3242 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3243 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3244 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3245 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3246 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3247 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3248 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3249 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3250 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3251 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3252 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3253 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3254 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3255 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3256 #define PTA_MPX (HOST_WIDE_INT_1 << 44)
3257 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3258 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3259 #define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
3260 #define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
3261 #define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
3262 #define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
3263 #define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
3264 #define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
3265 #define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 53)
3266 #define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 54)
3267 #define PTA_CLWB (HOST_WIDE_INT_1 << 55)
3268 #define PTA_PCOMMIT (HOST_WIDE_INT_1 << 56)
3269 #define PTA_MWAITX (HOST_WIDE_INT_1 << 57)
3271 #define PTA_CORE2 \
3272 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3273 | PTA_CX16 | PTA_FXSR)
3274 #define PTA_NEHALEM \
3275 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3276 #define PTA_WESTMERE \
3277 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3278 #define PTA_SANDYBRIDGE \
3279 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3280 #define PTA_IVYBRIDGE \
3281 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3282 #define PTA_HASWELL \
3283 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3284 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3285 #define PTA_BROADWELL \
3286 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3287 #define PTA_SKYLAKE \
3288 (PTA_BROADWELL | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES)
3289 #define PTA_KNL \
3290 (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
3291 #define PTA_BONNELL \
3292 (PTA_CORE2 | PTA_MOVBE)
3293 #define PTA_SILVERMONT \
3294 (PTA_WESTMERE | PTA_MOVBE)
3296 /* if this reaches 64, need to widen struct pta flags below */
3298 static struct pta
3299 {
3304 }
3306 {
3341 PTA_SANDYBRIDGE},
3343 PTA_SANDYBRIDGE},
3345 PTA_IVYBRIDGE},
3347 PTA_IVYBRIDGE},
3440 PTA_64BIT
3442 };
3444 /* -mrecip options. */
3445 static struct
3446 {
3449 }
3451 {
3458 };
3462 /* Set up prefix/suffix so the error messages refer to either the command
3463 line argument, or the attribute(target). */
3465 {
3469 }
3470 else
3471 {
3475 }
3477 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3478 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3481 #ifdef TARGET_BI_ARCH
3482 else
3483 {
3484 #if TARGET_BI_ARCH == 1
3485 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3486 is on and OPTION_MASK_ABI_X32 is off. We turn off
3487 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3488 -mx32. */
3491 #else
3492 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3493 on and OPTION_MASK_ABI_64 is off. We turn off
3494 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3495 -m64 or OPTION_MASK_CODE16 is turned on by -m16. */
3499 #endif
3504 }
3505 #endif
3508 {
3509 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3510 OPTION_MASK_ABI_64 for TARGET_X32. */
3513 }
3516 | OPTION_MASK_ABI_X32
3519 {
3520 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3521 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3524 }
3526 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3527 SUBTARGET_OVERRIDE_OPTIONS;
3528 #endif
3530 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3531 SUBSUBTARGET_OVERRIDE_OPTIONS;
3532 #endif
3534 /* -fPIC is the default for x86_64. */
3538 /* Need to check -mtune=generic first. */
3540 {
3541 /* As special support for cross compilers we read -mtune=native
3542 as -mtune=generic. With native compilers we won't see the
3543 -mtune=native, as it was changed by the driver. */
3545 {
3547 }
3552 }
3553 else
3554 {
3558 {
3559 opts->x_ix86_tune_string
3562 }
3564 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3565 or defaulted. We need to use a sensible tune option. */
3567 {
3569 }
3570 }
3574 {
3575 /* rep; movq isn't available in 32-bit code. */
3578 }
3581 opts->x_ix86_arch_string
3584 else
3588 {
3596 }
3597 else
3604 /* For targets using ms ABI enable ms-extensions, if not
3605 explicit turned off. For non-ms ABI we turn off this
3606 option. */
3611 {
3613 {
3657 {
3660 }
3668 }
3669 }
3670 else
3671 {
3672 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3673 use of rip-relative addressing. This eliminates fixups that
3674 would otherwise be needed if this object is to be placed in a
3675 DLL, and is essentially just as efficient as direct addressing. */
3681 else
3683 }
3685 {
3688 }
3696 {
3699 /* Default cpu tuning to the architecture. */
3880 }
3889 {
3890 /* Verify that x87/MMX/SSE/AVX is off for -miamcu. */
3894 | OPTION_MASK_ISA_SSE
3900 }
3918 {
3922 {
3924 {
3926 {
3934 }
3935 else
3938 }
3939 }
3940 /* Intel CPUs have always interpreted SSE prefetch instructions as
3941 NOPs; so, we can enable SSE prefetch instructions even when
3942 -mtune (rather than -march) points us to a processor that has them.
3943 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3944 higher processors. */
3949 }
3957 #ifndef USE_IX86_FRAME_POINTER
3958 #define USE_IX86_FRAME_POINTER 0
3959 #endif
3961 #ifndef USE_X86_64_FRAME_POINTER
3962 #define USE_X86_64_FRAME_POINTER 0
3963 #endif
3965 /* Set the default values for switches whose default depends on TARGET_64BIT
3966 in case they weren't overwritten by command line options. */
3968 {
3976 opts->x_flag_unwind_tables
3980 }
3981 else
3982 {
3984 opts->x_flag_omit_frame_pointer
3989 {
3990 /* Intel MCU psABI specifies that -freg-struct-return should
3991 be on. Instead of setting DEFAULT_PCC_STRUCT_RETURN to 1,
3992 we check -miamcu so that -freg-struct-return is always
3993 turned on if -miamcu is used. */
3996 else
3998 }
3999 }
4002 /* TODO: ix86_cost should be chosen at instruction or function granuality
4003 so for cold code we use size_cost even in !optimize_size compilation. */
4006 else
4009 /* Arrange to set up i386_stack_locals for all functions. */
4012 /* Validate -mregparm= value. */
4014 {
4020 {
4024 }
4025 }
4030 /* Default align_* from the processor table. */
4033 /* Provide default for -mbranch-cost= value. */
4038 {
4039 opts->x_target_flags
4042 /* Enable by default the SSE and MMX builtins. Do allow the user to
4043 explicitly disable any of these. In particular, disabling SSE and
4044 MMX for kernel code is extremely useful. */
4046 opts->x_ix86_isa_flags
4053 }
4054 else
4055 {
4056 opts->x_target_flags
4060 opts->x_ix86_isa_flags
4063 /* i386 ABI does not specify red zone. It still makes sense to use it
4064 when programmer takes care to stack from being destroyed. */
4067 }
4069 /* Keep nonleaf frame pointers. */
4075 /* If we're doing fast math, we don't care about comparison order
4076 wrt NaNs. This lets us use a shorter comparison sequence. */
4080 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
4081 since the insns won't need emulation. */
4085 /* Likewise, if the target doesn't have a 387, or we've specified
4086 software floating point, don't use 387 inline intrinsics. */
4090 /* Turn on MMX builtins for -msse. */
4092 opts->x_ix86_isa_flags
4095 /* Enable SSE prefetch. */
4100 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
4103 opts->x_ix86_isa_flags
4106 /* Enable popcnt instruction for -msse4.2 or -mabm. */
4109 opts->x_ix86_isa_flags
4112 /* Enable lzcnt instruction for -mabm. */
4114 opts->x_ix86_isa_flags
4117 /* Validate -mpreferred-stack-boundary= value or default it to
4118 PREFERRED_STACK_BOUNDARY_DEFAULT. */
4121 {
4128 {
4132 else
4135 }
4136 else
4137 ix86_preferred_stack_boundary
4139 }
4141 /* Set the default value for -mstackrealign. */
4147 /* Validate -mincoming-stack-boundary= value or default it to
4148 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
4151 {
4159 else
4160 {
4161 ix86_user_incoming_stack_boundary
4163 ix86_incoming_stack_boundary
4165 }
4166 }
4168 #ifndef NO_PROFILE_COUNTERS
4171 #endif
4175 /* Accept -msseregparm only if at least SSE support is enabled. */
4181 {
4183 {
4185 {
4188 }
4191 {
4194 }
4195 }
4196 }
4197 /* For all chips supporting SSE2, -mfpmath=sse performs better than
4198 fpmath=387. The second is however default at many targets since the
4199 extra 80bit precision of temporaries is considered to be part of ABI.
4200 Overwrite the default at least for -ffast-math.
4201 TODO: -mfpmath=both seems to produce same performing code with bit
4202 smaller binaries. It is however not clear if register allocation is
4203 ready for this setting.
4204 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
4205 codegen. We may switch to 387 with -ffast-math for size optimized
4206 functions. */
4210 else
4213 /* If the i387 is disabled, then do not return values in it. */
4217 /* Use external vectorized library in vectorizing intrinsics. */
4220 {
4231 }
4237 /* If stack probes are required, the space used for large function
4238 arguments on the stack must also be probed, so enable
4239 -maccumulate-outgoing-args so this happens in the prologue. */
4242 {
4247 }
4249 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4250 {
4256 }
4258 /* When scheduling description is not available, disable scheduler pass
4259 so it won't slow down the compilation and make x87 code slower. */
4280 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4282 && HAVE_prefetch
4288 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4289 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4294 {
4297 {
4299 ix86_gen_tls_local_dynamic_base_64
4301 }
4302 else
4303 {
4305 ix86_gen_tls_local_dynamic_base_64
4307 }
4308 }
4309 else
4313 {
4324 }
4325 else
4326 {
4337 }
4339 #ifdef USE_IX86_CLD
4340 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4343 #endif
4346 {
4351 }
4353 {
4357 }
4359 {
4360 #if defined(PROFILE_BEFORE_PROLOGUE)
4362 #else
4364 #endif
4365 }
4375 /* Enable 128-bit AVX instruction generation
4376 for the auto-vectorizer. */
4382 {
4389 {
4392 {
4394 q++;
4395 }
4396 else
4401 else
4402 {
4405 {
4408 }
4411 {
4415 }
4416 }
4421 else
4423 }
4424 }
4431 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4432 for 64-bit Bionic. Also default long double to 64-bit for Intel
4433 MCU psABI. */
4438 ? MASK_LONG_DOUBLE_128
4441 /* Only one of them can be active. */
4445 /* Save the initial options in case the user does function specific
4446 options. */
4448 target_option_default_node = target_option_current_node
4451 /* Handle stack protector */
4453 opts->x_ix86_stack_protector_guard
4456 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4458 {
4462 }
4465 {
4469 }
4470 }
4472 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4474 static void
4476 {
4478 struct register_pass_info insert_vzeroupper_info
4481 };
4486 /* This needs to be done at start up. It's convenient to do it here. */
4488 }
4490 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
4493 {
4497 }
4499 /* Update register usage after having seen the compiler flags. */
4501 static void
4503 {
4506 /* For 32-bit targets, squash the REX registers. */
4508 {
4515 }
4517 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4525 {
4526 /* Set/reset conditionally defined registers from
4527 CALL_USED_REGISTERS initializer. */
4531 /* Calculate registers of CLOBBERED_REGS register set
4532 as call used registers from GENERAL_REGS register set. */
4536 }
4538 /* If MMX is disabled, squash the registers. */
4544 /* If SSE is disabled, squash the registers. */
4550 /* If the FPU is disabled, squash the registers. */
4556 /* If AVX512F is disabled, squash the registers. */
4558 {
4564 }
4566 /* If MPX is disabled, squash the registers. */
4570 }
4572 \f
4573 /* Save the current options */
4575 static void
4578 {
4614 /* The fields are char but the variables are not; make sure the
4615 values fit in the fields. */
4620 }
4622 /* Restore the current options */
4624 static void
4627 {
4633 /* We don't change -fPIC. */
4671 /* TODO: ix86_cost should be chosen at instruction or function granuality
4672 so for cold code we use size_cost even in !optimize_size compilation. */
4675 else
4678 /* Recreate the arch feature tests if the arch changed */
4680 {
4685 }
4687 /* Recreate the tune optimization tests */
4690 }
4692 /* Adjust target options after streaming them in. This is mainly about
4693 reconciling them with global options. */
4695 static void
4697 {
4698 /* flag_pic is a global option, but ix86_cmodel is target saved option
4699 partly computed from flag_pic. If flag_pic is on, adjust x_ix86_cmodel
4700 for PIC, or error out. */
4703 {
4722 }
4723 else
4725 {
4740 }
4741 }
4743 /* Print the current options */
4745 static void
4748 {
4766 {
4769 }
4770 }
4772 \f
4773 /* Inner function to process the attribute((target(...))), take an argument and
4774 set the current options from the argument. If we have a list, recursively go
4775 over the list. */
4777 static bool
4782 {
4786 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4787 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4788 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4789 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4790 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4792 enum ix86_opt_type
4793 {
4794 ix86_opt_unknown,
4795 ix86_opt_yes,
4796 ix86_opt_no,
4797 ix86_opt_str,
4798 ix86_opt_enum,
4799 ix86_opt_isa
4800 };
4802 static const struct
4803 {
4810 /* isa options */
4864 /* enum options */
4867 /* string options */
4871 /* flag options */
4873 OPT_mcld,
4874 MASK_CLD),
4877 OPT_mfancy_math_387,
4878 MASK_NO_FANCY_MATH_387),
4881 OPT_mieee_fp,
4882 MASK_IEEE_FP),
4885 OPT_minline_all_stringops,
4886 MASK_INLINE_ALL_STRINGOPS),
4889 OPT_minline_stringops_dynamically,
4890 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4893 OPT_mno_align_stringops,
4894 MASK_NO_ALIGN_STRINGOPS),
4897 OPT_mrecip,
4898 MASK_RECIP),
4900 };
4902 /* If this is a list, recurse to get the options. */
4904 {
4911 enum_opts_set))
4915 }
4918 {
4921 }
4923 /* Handle multiple arguments separated by commas. */
4927 {
4941 {
4945 }
4946 else
4947 {
4950 }
4952 /* Recognize no-xxx. */
4954 {
4958 }
4959 else
4962 /* Find the option. */
4966 {
4974 {
4979 }
4980 }
4982 /* Process the option. */
4984 {
4987 }
4990 {
4996 }
4999 {
5005 else
5007 }
5010 {
5012 {
5015 }
5016 else
5018 }
5021 {
5029 global_dc);
5030 else
5031 {
5034 }
5035 }
5037 else
5039 }
5042 }
5044 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
5046 tree
5050 {
5065 /* Process each of the options on the chain. */
5070 /* If the changed options are different from the default, rerun
5071 ix86_option_override_internal, and then save the options away.
5072 The string options are attribute options, and will be undone
5073 when we copy the save structure. */
5079 {
5080 /* If we are using the default tune= or arch=, undo the string assigned,
5081 and use the default. */
5092 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
5097 {
5100 }
5102 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
5105 /* Add any builtin functions with the new isa if any. */
5108 /* Save the current options unless we are validating options for
5109 #pragma. */
5116 /* Free up memory allocated to hold the strings */
5119 }
5122 }
5124 /* Hook to validate attribute((target("string"))). */
5126 static bool
5129 tree args,
5131 {
5136 /* attribute((target("default"))) does nothing, beyond
5137 affecting multi-versioning. */
5146 /* Get the optimization options of the current function. */
5152 /* Init func_options. */
5160 /* Initialize func_options to the default before its target options can
5161 be set. */
5174 {
5179 }
5182 }
5184 \f
5185 /* Hook to determine if one function can safely inline another. */
5187 static bool
5189 {
5194 /* If callee has no option attributes, then it is ok to inline. */
5198 /* If caller has no option attributes, but callee does then it is not ok to
5199 inline. */
5203 else
5204 {
5208 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
5209 can inline a SSE2 function but a SSE2 function can't inline a SSE4
5210 function. */
5215 /* See if we have the same non-isa options. */
5219 /* See if arch, tune, etc. are the same. */
5232 else
5234 }
5237 }
5239 \f
5240 /* Remember the last target of ix86_set_current_function. */
5243 /* Set targets globals to the default (or current #pragma GCC target
5244 if active). Invalidate ix86_previous_fndecl cache. */
5246 void
5248 {
5255 else
5258 }
5260 /* Establish appropriate back-end context for processing the function
5261 FNDECL. The argument might be NULL to indicate processing at top
5262 level, outside of any function scope. */
5263 static void
5265 {
5266 /* Only change the context if the function changes. This hook is called
5267 several times in the course of compiling a function, and we don't want to
5268 slow things down too much or call target_reinit when it isn't safe. */
5272 tree old_tree;
5277 else
5281 {
5285 }
5292 {
5298 else
5300 }
5302 }
5304 \f
5305 /* Return true if this goes in large data/bss. */
5307 static bool
5309 {
5313 /* Functions are never large data. */
5317 /* Automatic variables are never large data. */
5322 {
5328 }
5329 else
5330 {
5333 /* If this is an incomplete type with size 0, then we can't put it
5334 in data because it might be too big when completed. Also,
5335 int_size_in_bytes returns -1 if size can vary or is larger than
5336 an integer in which case also it is safer to assume that it goes in
5337 large data. */
5340 }
5343 }
5345 /* Switch to the appropriate section for output of DECL.
5346 DECL is either a `VAR_DECL' node or a constant of some sort.
5347 RELOC indicates whether forming the initial value of DECL requires
5348 link-time relocations. */
5353 {
5355 {
5359 {
5393 /* We don't split these for medium model. Place them into
5394 default sections and hope for best. */
5396 }
5398 {
5399 /* We might get called with string constants, but get_named_section
5400 doesn't like them as they are not DECLs. Also, we need to set
5401 flags in that case. */
5405 }
5406 }
5408 }
5410 /* Select a set of attributes for section NAME based on the properties
5411 of DECL and whether or not RELOC indicates that DECL's initializer
5412 might contain runtime relocations. */
5414 static unsigned int ATTRIBUTE_UNUSED
5416 {
5430 }
5432 /* Build up a unique section name, expressed as a
5433 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5434 RELOC indicates whether the initial value of EXP requires
5435 link-time relocations. */
5437 static void ATTRIBUTE_UNUSED
5439 {
5441 {
5443 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5447 {
5471 /* We don't split these for medium model. Place them into
5472 default sections and hope for best. */
5474 }
5476 {
5483 /* If we're using one_only, then there needs to be a .gnu.linkonce
5484 prefix to the section name. */
5491 }
5492 }
5494 }
5496 #ifdef COMMON_ASM_OP
5497 /* This says how to output assembler code to declare an
5498 uninitialized external linkage data object.
5500 For medium model x86-64 we need to use .largecomm opcode for
5501 large objects. */
5502 void
5506 {
5510 else
5515 }
5516 #endif
5518 /* Utility function for targets to use in implementing
5519 ASM_OUTPUT_ALIGNED_BSS. */
5521 void
5524 {
5528 else
5531 #ifdef ASM_DECLARE_OBJECT_NAME
5534 #else
5535 /* Standard thing is just output label for the object. */
5539 }
5540 \f
5541 /* Decide whether we must probe the stack before any space allocation
5542 on this target. It's essentially TARGET_STACK_PROBE except when
5543 -fstack-check causes the stack to be already probed differently. */
5545 bool
5547 {
5548 /* Do not probe the stack twice if static stack checking is enabled. */
5553 }
5554 \f
5555 /* Decide whether we can make a sibling call to a function. DECL is the
5556 declaration of the function being targeted by the call and EXP is the
5557 CALL_EXPR representing the call. */
5559 static bool
5561 {
5565 /* If we are generating position-independent code, we cannot sibcall
5566 optimize direct calls to global functions, as the PLT requires
5567 %ebx be live. (Darwin does not have a PLT.) */
5569 && !TARGET_64BIT
5570 && flag_pic
5571 && flag_plt
5575 /* If we need to align the outgoing stack, then sibcalling would
5576 unalign the stack, which may break the called function. */
5582 {
5585 }
5586 else
5587 {
5588 /* We're looking at the CALL_EXPR, we need the type of the function. */
5593 }
5595 /* Check that the return value locations are the same. Like
5596 if we are returning floats on the 80387 register stack, we cannot
5597 make a sibcall from a function that doesn't return a float to a
5598 function that does or, conversely, from a function that does return
5599 a float to a function that doesn't; the necessary stack adjustment
5600 would not be executed. This is also the place we notice
5601 differences in the return value ABI. Note that it is ok for one
5602 of the functions to have void return type as long as the return
5603 value of the other is passed in a register. */
5608 {
5611 }
5613 ;
5618 {
5619 /* The SYSV ABI has more call-clobbered registers;
5620 disallow sibcalls from MS to SYSV. */
5624 }
5625 else
5626 {
5627 /* If this call is indirect, we'll need to be able to use a
5628 call-clobbered register for the address of the target function.
5629 Make sure that all such registers are not used for passing
5630 parameters. Note that DLLIMPORT functions are indirect. */
5633 {
5634 /* Check if regparm >= 3 since arg_reg_available is set to
5635 false if regparm == 0. If regparm is 1 or 2, there is
5636 always a call-clobbered register available.
5638 ??? The symbol indirect call doesn't need a call-clobbered
5639 register. But we don't know if this is a symbol indirect
5640 call or not here. */
5644 }
5645 }
5647 /* Otherwise okay. That also includes certain types of indirect calls. */
5649 }
5651 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5652 and "sseregparm" calling convention attributes;
5653 arguments as in struct attribute_spec.handler. */
5655 static tree
5657 tree args,
5660 {
5665 {
5667 name);
5670 }
5672 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5674 {
5675 tree cst;
5678 {
5680 }
5683 {
5685 }
5689 {
5692 name);
5694 }
5696 {
5700 }
5703 }
5706 {
5707 /* Do not warn when emulating the MS ABI. */
5712 name);
5715 }
5717 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5719 {
5721 {
5723 }
5725 {
5727 }
5729 {
5731 }
5733 {
5735 }
5736 }
5738 /* Can combine stdcall with fastcall (redundant), regparm and
5739 sseregparm. */
5741 {
5743 {
5745 }
5747 {
5749 }
5751 {
5753 }
5754 }
5756 /* Can combine cdecl with regparm and sseregparm. */
5758 {
5760 {
5762 }
5764 {
5766 }
5768 {
5770 }
5771 }
5773 {
5776 name);
5778 {
5780 }
5782 {
5784 }
5786 {
5788 }
5789 }
5791 /* Can combine sseregparm with all attributes. */
5794 }
5796 /* The transactional memory builtins are implicitly regparm or fastcall
5797 depending on the ABI. Override the generic do-nothing attribute that
5798 these builtins were declared with, and replace it with one of the two
5799 attributes that we expect elsewhere. */
5801 static tree
5804 {
5805 tree alt;
5807 /* In no case do we want to add the placeholder attribute. */
5810 /* The 64-bit ABI is unchanged for transactional memory. */
5814 /* ??? Is there a better way to validate 32-bit windows? We have
5815 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5818 else
5819 {
5822 }
5826 }
5828 /* This function determines from TYPE the calling-convention. */
5830 unsigned int
5832 {
5835 tree attrs;
5842 {
5852 /* Regparam isn't allowed for thiscall and fastcall. */
5854 {
5859 }
5863 }
5870 || is_stdarg
5876 }
5878 /* Return 0 if the attributes for two types are incompatible, 1 if they
5879 are compatible, and 2 if they are nearly compatible (which causes a
5880 warning to be generated). */
5882 static int
5884 {
5900 }
5901 \f
5902 /* Return the regparm value for a function with the indicated TYPE and DECL.
5903 DECL may be NULL when calling function indirectly
5904 or considering a libcall. */
5906 static int
5908 {
5909 tree attr;
5920 {
5923 {
5926 }
5927 }
5933 /* Use register calling convention for local functions when possible. */
5936 {
5941 /* Caller and callee must agree on the calling convention, so
5942 checking here just optimize means that with
5943 __attribute__((optimize (...))) caller could use regparm convention
5944 and callee not, or vice versa. Instead look at whether the callee
5945 is optimized or not. */
5948 {
5951 {
5954 /* Make sure no regparm register is taken by a
5955 fixed register variable. */
5957 local_regparm++)
5961 /* We don't want to use regparm(3) for nested functions as
5962 these use a static chain pointer in the third argument. */
5966 /* Save a register for the split stack. */
5970 /* Each fixed register usage increases register pressure,
5971 so less registers should be used for argument passing.
5972 This functionality can be overriden by an explicit
5973 regparm value. */
5976 globals++;
5978 local_regparm
5983 }
5984 }
5985 }
5988 }
5990 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5991 DFmode (2) arguments in SSE registers for a function with the
5992 indicated TYPE and DECL. DECL may be NULL when calling function
5993 indirectly or considering a libcall. Return -1 if any FP parameter
5994 should be rejected by error. This is used in siutation we imply SSE
5995 calling convetion but the function is called from another function with
5996 SSE disabled. Otherwise return 0. */
5998 static int
6000 {
6003 /* Use SSE registers to pass SFmode and DFmode arguments if requested
6004 by the sseregparm attribute. */
6007 {
6009 {
6011 {
6015 else
6018 }
6020 }
6023 }
6032 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
6033 (and DFmode for SSE2) arguments in SSE registers. */
6035 /* TARGET_SSE_MATH */
6039 {
6042 {
6043 /* Refuse to produce wrong code when local function with SSE enabled
6044 is called from SSE disabled function.
6045 FIXME: We need a way to detect these cases cross-ltrans partition
6046 and avoid using SSE calling conventions on local functions called
6047 from function with SSE disabled. For now at least delay the
6048 warning until we know we are going to produce wrong code.
6049 See PR66047 */
6054 }
6055 }
6058 }
6060 /* Return true if EAX is live at the start of the function. Used by
6061 ix86_expand_prologue to determine if we need special help before
6062 calling allocate_stack_worker. */
6064 static bool
6066 {
6067 /* Cheat. Don't bother working forward from ix86_function_regparm
6068 to the function type to whether an actual argument is located in
6069 eax. Instead just look at cfg info, which is still close enough
6070 to correct at this point. This gives false positives for broken
6071 functions that might use uninitialized data that happens to be
6072 allocated in eax, but who cares? */
6074 }
6076 static bool
6078 {
6079 tree attr;
6082 {
6088 /* For 32-bit MS-ABI the default is to keep aggregate
6089 return pointer. */
6092 }
6094 }
6096 /* Value is the number of bytes of arguments automatically
6097 popped when returning from a subroutine call.
6098 FUNDECL is the declaration node of the function (as a tree),
6099 FUNTYPE is the data type of the function (as a tree),
6100 or for a library call it is an identifier node for the subroutine name.
6101 SIZE is the number of bytes of arguments passed on the stack.
6103 On the 80386, the RTD insn may be used to pop them if the number
6104 of args is fixed, but if the number is variable then the caller
6105 must pop them all. RTD can't be used for library calls now
6106 because the library is compiled with the Unix compiler.
6107 Use of RTD is a selectable option, since it is incompatible with
6108 standard Unix calling sequences. If the option is not selected,
6109 the caller must always pop the args.
6111 The attribute stdcall is equivalent to RTD on a per module basis. */
6113 static int
6115 {
6118 /* None of the 64-bit ABIs pop arguments. */
6129 /* Lose any fake structure return argument if it is passed on the stack. */
6132 {
6136 }
6139 }
6141 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
6143 static bool
6145 {
6146 /* Check operand constraints in case hard registers were propagated
6147 into insn pattern. This check prevents combine pass from
6148 generating insn patterns with invalid hard register operands.
6149 These invalid insns can eventually confuse reload to error out
6150 with a spill failure. See also PRs 46829 and 46843. */
6152 {
6161 {
6169 /* For pre-AVX disallow unaligned loads/stores where the
6170 instructions don't support it. */
6174 {
6178 }
6180 /* A unary operator may be accepted by the predicate, but it
6181 is irrelevant for matching constraints. */
6186 {
6194 }
6201 /* Operand has no constraints, anything is OK. */
6206 {
6211 && operands_match_p
6215 {
6218 }
6219 }
6223 }
6224 }
6227 }
6228 \f
6229 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
6231 static unsigned HOST_WIDE_INT
6233 {
6237 }
6238 \f
6239 /* Argument support functions. */
6241 /* Return true when register may be used to pass function parameters. */
6242 bool
6244 {
6253 {
6257 else
6263 }
6269 /* TODO: The function should depend on current function ABI but
6270 builtins.c would need updating then. Therefore we use the
6271 default ABI. */
6274 /* RAX is used as hidden argument to va_arg functions. */
6280 else
6288 }
6290 /* Return if we do not know how to pass TYPE solely in registers. */
6292 static bool
6294 {
6298 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
6299 The layout_type routine is crafty and tries to trick us into passing
6300 currently unsupported vector types on the stack by using TImode. */
6303 }
6305 /* It returns the size, in bytes, of the area reserved for arguments passed
6306 in registers for the function represented by fndecl dependent to the used
6307 abi format. */
6308 int
6310 {
6314 else
6319 }
6321 /* We add this as a workaround in order to use libc_has_function
6322 hook in i386.md. */
6323 bool
6325 {
6327 }
6329 /* Returns value SYSV_ABI, MS_ABI dependent on fntype,
6330 specifying the call abi used. */
6331 enum calling_abi
6333 {
6341 {
6346 }
6352 }
6354 static enum calling_abi
6356 {
6358 }
6360 /* Returns value SYSV_ABI, MS_ABI dependent on cfun,
6361 specifying the call abi used. */
6362 enum calling_abi
6364 {
6366 }
6368 static bool
6370 {
6372 {
6376 else
6378 }
6380 }
6382 /* Write the extra assembler code needed to declare a function properly. */
6384 void
6386 tree decl)
6387 {
6391 {
6397 }
6399 #ifdef SUBTARGET_ASM_UNWIND_INIT
6401 #endif
6405 /* Output magic byte marker, if hot-patch attribute is set. */
6407 {
6409 {
6410 /* leaq [%rsp + 0], %rsp */
6413 }
6414 else
6415 {
6416 /* movl.s %edi, %edi
6417 push %ebp
6418 movl.s %esp, %ebp */
6421 }
6422 }
6423 }
6425 /* regclass.c */
6428 /* Implementation of call abi switching target hook. Specific to FNDECL
6429 the specific call register sets are set. See also
6430 ix86_conditional_register_usage for more details. */
6431 void
6433 {
6435 }
6437 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6438 expensive re-initialization of init_regs each time we switch function context
6439 since this is needed only during RTL expansion. */
6440 static void
6442 {
6446 }
6448 /* Return 1 if pseudo register should be created and used to hold
6449 GOT address for PIC code. */
6450 bool
6452 {
6459 }
6461 /* Initialize large model PIC register. */
6463 static void
6465 {
6467 rtx tmp_reg;
6476 label));
6480 }
6482 /* Create and initialize PIC register if required. */
6483 static void
6485 {
6486 edge entry_edge;
6495 {
6498 else
6500 }
6501 else
6502 {
6503 /* If there is future mcount call in the function it is more profitable
6504 to emit SET_GOT into ABI defined REAL_PIC_OFFSET_TABLE_REGNUM. */
6513 }
6521 }
6523 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6524 for a call to a function whose data type is FNTYPE.
6525 For a library call, FNTYPE is 0. */
6527 void
6531 tree fndecl,
6533 {
6540 {
6543 {
6547 }
6548 else
6550 }
6551 else
6556 /* Set up the number of registers to use for passing arguments. */
6559 {
6561 ? X86_64_REGPARM_MAX
6563 }
6565 {
6568 {
6570 ? X86_64_SSE_REGPARM_MAX
6572 }
6573 }
6581 /* Because type might mismatch in between caller and callee, we need to
6582 use actual type of function for local calls.
6583 FIXME: cgraph_analyze can be told to actually record if function uses
6584 va_start so for local functions maybe_vaarg can be made aggressive
6585 helping K&R code.
6586 FIXME: once typesytem is fixed, we won't need this code anymore. */
6600 {
6601 /* If there are variable arguments, then we won't pass anything
6602 in registers in 32-bit mode. */
6604 {
6606 /* Since in 32-bit, variable arguments are always passed on
6607 stack, there is scratch register available for indirect
6608 sibcall. */
6617 }
6619 /* Use ecx and edx registers if function has fastcall attribute,
6620 else look for regparm information. */
6622 {
6625 {
6628 }
6630 {
6633 }
6634 else
6636 }
6638 /* Set up the number of SSE registers used for passing SFmode
6639 and DFmode arguments. Warn for mismatching ABI. */
6641 }
6644 }
6646 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6647 But in the case of vector types, it is some vector mode.
6649 When we have only some of our vector isa extensions enabled, then there
6650 are some modes for which vector_mode_supported_p is false. For these
6651 modes, the generic vector support in gcc will choose some non-vector mode
6652 in order to implement the type. By computing the natural mode, we'll
6653 select the proper ABI location for the operand and not depend on whatever
6654 the middle-end decides to do with these vector types.
6656 The midde-end can't deal with the vector types > 16 bytes. In this
6657 case, we return the original mode and warn ABI change if CUM isn't
6658 NULL.
6660 If INT_RETURN is true, warn ABI change if the vector mode isn't
6661 available for function return value. */
6663 static machine_mode
6666 {
6670 {
6673 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6675 {
6680 else
6683 /* Get the mode which has this inner mode and number of units. */
6687 {
6689 {
6694 {
6698 }
6700 {
6704 }
6707 }
6709 {
6714 {
6718 }
6720 {
6724 }
6727 }
6729 && !TARGET_SSE
6731 {
6736 {
6740 }
6742 {
6746 }
6747 }
6749 && !TARGET_MMX
6751 {
6756 {
6760 }
6762 {
6766 }
6767 }
6769 }
6772 }
6773 }
6776 }
6778 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6779 this may not agree with the mode that the type system has chosen for the
6780 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6781 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6783 static rtx
6786 {
6787 rtx tmp;
6791 else
6792 {
6796 }
6799 }
6801 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6802 of this code is to classify each 8bytes of incoming argument by the register
6803 class and assign registers accordingly. */
6805 /* Return the union class of CLASS1 and CLASS2.
6806 See the x86-64 PS ABI for details. */
6808 static enum x86_64_reg_class
6810 {
6811 /* Rule #1: If both classes are equal, this is the resulting class. */
6815 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6816 the other class. */
6822 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6826 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6834 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6835 MEMORY is used. */
6844 /* Rule #6: Otherwise class SSE is used. */
6846 }
6848 /* Classify the argument of type TYPE and mode MODE.
6849 CLASSES will be filled by the register class used to pass each word
6850 of the operand. The number of words is returned. In case the parameter
6851 should be passed in memory, 0 is returned. As a special case for zero
6852 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6854 BIT_OFFSET is used internally for handling records and specifies offset
6855 of the offset in bits modulo 512 to avoid overflow cases.
6857 See the x86-64 PS ABI for details.
6858 */
6860 static int
6863 {
6864 HOST_WIDE_INT bytes =
6866 int words
6869 /* Variable sized entities are always passed/returned in memory. */
6878 {
6880 tree field;
6883 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6890 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6891 signalize memory class, so handle it as special case. */
6893 {
6896 }
6898 /* Classify each field of record and merge classes. */
6900 {
6902 /* And now merge the fields of structure. */
6904 {
6906 {
6912 /* Bitfields are always classified as integer. Handle them
6913 early, since later code would consider them to be
6914 misaligned integers. */
6916 {
6925 }
6926 else
6927 {
6932 /* Flexible array member is ignored. */
6939 {
6943 {
6946 "the ABI of passing struct with"
6947 " a flexible array member has"
6949 }
6951 }
6953 subclasses,
6963 }
6964 }
6965 }
6969 /* Arrays are handled as small records. */
6970 {
6977 /* The partial classes are now full classes. */
6988 }
6991 /* Unions are similar to RECORD_TYPE but offset is always 0.
6992 */
6994 {
6996 {
7004 bit_offset);
7009 }
7010 }
7015 }
7018 {
7019 /* When size > 16 bytes, if the first one isn't
7020 X86_64_SSE_CLASS or any other ones aren't
7021 X86_64_SSEUP_CLASS, everything should be passed in
7022 memory. */
7029 }
7031 /* Final merger cleanup. */
7033 {
7034 /* If one class is MEMORY, everything should be passed in
7035 memory. */
7039 /* The X86_64_SSEUP_CLASS should be always preceded by
7040 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
7044 {
7045 /* The first one should never be X86_64_SSEUP_CLASS. */
7048 }
7050 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
7051 everything should be passed in memory. */
7054 {
7057 /* The first one should never be X86_64_X87UP_CLASS. */
7060 {
7063 "the ABI of passing union with long double"
7065 }
7067 }
7068 }
7070 }
7072 /* Compute alignment needed. We align all types to natural boundaries with
7073 exception of XFmode that is aligned to 64bits. */
7075 {
7084 /* Misaligned fields are always returned in memory. */
7087 }
7089 /* for V1xx modes, just use the base mode */
7094 /* Classification of atomic types. */
7096 {
7112 {
7115 /* Analyze last 128 bits only. */
7119 {
7122 }
7124 {
7127 }
7129 {
7133 }
7135 {
7138 }
7139 else
7141 }
7148 /* OImode shouldn't be used directly. */
7155 else
7173 else
7174 {
7178 {
7181 "the ABI of passing structure with complex float"
7183 }
7186 }
7195 /* This modes is larger than 16 bytes. */
7253 else
7257 }
7258 }
7260 /* Examine the argument and return set number of register required in each
7261 class. Return true iff parameter should be passed in memory. */
7263 static bool
7266 {
7277 {
7298 }
7301 }
7303 /* Construct container for the argument used by GCC interface. See
7304 FUNCTION_ARG for the detailed description. */
7306 static rtx
7310 {
7311 /* The following variables hold the static issued_error state. */
7316 machine_mode tmpmode;
7325 rtx ret;
7336 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
7337 some less clueful developer tries to use floating-point anyway. */
7339 {
7341 {
7343 {
7346 }
7347 }
7349 {
7352 }
7354 }
7356 /* Likewise, error if the ABI requires us to return values in the
7357 x87 registers and the user specified -mno-80387. */
7363 {
7365 {
7368 }
7370 }
7372 /* First construct simple cases. Avoid SCmode, since we want to use
7373 single register to pass this type. */
7376 {
7391 /* Zero sized array, struct or class. */
7395 }
7434 /* Otherwise figure out the entries of the PARALLEL. */
7436 {
7440 {
7445 /* Merge TImodes on aligned occasions here too. */
7447 tmpmode
7451 else
7453 /* We've requested 24 bytes we
7454 don't have mode for. Use DImode. */
7461 intreg++;
7469 sse_regno++;
7477 sse_regno++;
7482 {
7488 {
7490 i++;
7491 }
7492 else
7517 }
7523 sse_regno++;
7527 }
7528 }
7530 /* Empty aligned struct, union or class. */
7538 }
7540 /* Update the data in CUM to advance over an argument of mode MODE
7541 and data type TYPE. (TYPE is null for libcalls where that information
7542 may not be available.)
7544 Return a number of integer regsiters advanced over. */
7546 static int
7549 HOST_WIDE_INT words)
7550 {
7555 {
7556 /* Intel MCU psABI passes scalars and aggregates no larger than 8
7557 bytes in registers. */
7561 }
7564 {
7571 /* FALLTHRU */
7577 pass_in_reg:
7584 {
7588 }
7592 /* OImode shouldn't be used directly. */
7605 /* FALLTHRU */
7627 {
7632 {
7635 }
7636 }
7646 {
7651 {
7654 }
7655 }
7657 }
7659 {
7665 }
7668 }
7670 static int
7673 {
7676 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7683 {
7689 }
7690 else
7691 {
7696 }
7697 }
7699 static int
7701 HOST_WIDE_INT words)
7702 {
7703 /* Otherwise, this should be passed indirect. */
7708 {
7712 }
7714 }
7716 /* Update the data in CUM to advance over an argument of mode MODE and
7717 data type TYPE. (TYPE is null for libcalls where that information
7718 may not be available.) */
7720 static void
7723 {
7730 else
7739 {
7740 /* If we pass bounds in BT then just update remained bounds count. */
7742 {
7745 }
7747 /* Update remained number of bounds to force. */
7754 }
7756 /* The first arg not going to Bounds Tables resets this counter. */
7758 /* For unnamed args we always pass bounds to avoid bounds mess when
7759 passed and received types do not match. If bounds do not follow
7760 unnamed arg, still pretend required number of bounds were passed. */
7762 {
7765 }
7768 {
7773 else
7775 }
7776 else
7779 /* For stdarg we expect bounds to be passed for each value passed
7780 in register. */
7783 /* For pointers passed in memory we expect bounds passed in Bounds
7784 Table. */
7787 }
7789 /* Define where to put the arguments to a function.
7790 Value is zero to push the argument on the stack,
7791 or a hard register in which to store the argument.
7793 MODE is the argument's machine mode.
7794 TYPE is the data type of the argument (as a tree).
7795 This is null for libcalls where that information may
7796 not be available.
7797 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7798 the preceding args and about the function being called.
7799 NAMED is nonzero if this argument is a named parameter
7800 (otherwise it is an extra parameter matching an ellipsis). */
7802 static rtx
7806 {
7808 /* Avoid the AL settings for the Unix64 ABI. */
7813 {
7814 /* Intel MCU psABI passes scalars and aggregates no larger than 8
7815 bytes in registers. */
7819 }
7822 {
7829 /* FALLTHRU */
7834 pass_in_reg:
7836 {
7839 /* Fastcall allocates the first two DWORD (SImode) or
7840 smaller arguments to ECX and EDX if it isn't an
7841 aggregate type . */
7843 {
7849 /* ECX not EAX is the first allocated register. */
7852 }
7854 }
7867 /* FALLTHRU */
7869 /* In 32bit, we pass TImode in xmm registers. */
7877 {
7881 }
7886 /* OImode and XImode shouldn't be used directly. */
7902 {
7906 }
7916 {
7920 }
7922 }
7924 {
7930 }
7933 }
7935 static rtx
7938 {
7939 /* Handle a hidden AL argument containing number of registers
7940 for varargs x86-64 functions. */
7944 ? X86_64_SSE_REGPARM_MAX
7949 {
7965 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7969 }
7975 }
7977 static rtx
7980 HOST_WIDE_INT bytes)
7981 {
7984 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7985 We use value of -2 to specify that current function call is MSABI. */
7989 /* If we've run out of registers, it goes on the stack. */
7995 /* Only floating point modes are passed in anything but integer regs. */
7997 {
8000 else
8001 {
8004 /* Unnamed floating parameters are passed in both the
8005 SSE and integer registers. */
8011 }
8012 }
8013 /* Handle aggregated types passed in register. */
8015 {
8020 }
8023 }
8025 /* Return where to put the arguments to a function.
8026 Return zero to push the argument on the stack, or a hard register in which to store the argument.
8028 MODE is the argument's machine mode. TYPE is the data type of the
8029 argument. It is null for libcalls where that information may not be
8030 available. CUM gives information about the preceding args and about
8031 the function being called. NAMED is nonzero if this argument is a
8032 named parameter (otherwise it is an extra parameter matching an
8033 ellipsis). */
8035 static rtx
8038 {
8042 rtx arg;
8044 /* All pointer bounds argumntas are handled separately here. */
8047 {
8048 /* Return NULL if bounds are forced to go in Bounds Table. */
8051 /* Return the next available bound reg if any. */
8054 /* Return the next special slot number otherwise. */
8055 else
8059 }
8063 else
8067 /* To simplify the code below, represent vector types with a vector mode
8068 even if MMX/SSE are not active. */
8073 {
8078 else
8080 }
8081 else
8085 }
8087 /* A C expression that indicates when an argument must be passed by
8088 reference. If nonzero for an argument, a copy of that argument is
8089 made in memory and a pointer to the argument is passed instead of
8090 the argument itself. The pointer is passed in whatever way is
8091 appropriate for passing a pointer to that type. */
8093 static bool
8096 {
8099 /* Bounds are never passed by reference. */
8105 {
8108 /* See Windows x64 Software Convention. */
8110 {
8114 {
8115 /* Arrays are passed by reference. */
8120 {
8121 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
8122 are passed by reference. */
8124 }
8125 }
8127 /* __m128 is passed by reference. */
8129 }
8132 }
8135 }
8137 /* Return true when TYPE should be 128bit aligned for 32bit argument
8138 passing ABI. XXX: This function is obsolete and is only used for
8139 checking psABI compatibility with previous versions of GCC. */
8141 static bool
8143 {
8155 {
8156 /* Walk the aggregates recursively. */
8158 {
8162 {
8163 tree field;
8165 /* Walk all the structure fields. */
8167 {
8171 }
8173 }
8176 /* Just for use if some languages passes arrays by value. */
8183 }
8184 }
8186 }
8188 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
8189 XXX: This function is obsolete and is only used for checking psABI
8190 compatibility with previous versions of GCC. */
8192 static unsigned int
8195 {
8196 /* In 32bit, only _Decimal128 and __float128 are aligned to their
8197 natural boundaries. */
8199 {
8200 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
8201 make an exception for SSE modes since these require 128bit
8202 alignment.
8204 The handling here differs from field_alignment. ICC aligns MMX
8205 arguments to 4 byte boundaries, while structure fields are aligned
8206 to 8 byte boundaries. */
8208 {
8211 }
8212 else
8213 {
8216 }
8217 }
8221 }
8223 /* Return true when TYPE should be 128bit aligned for 32bit argument
8224 passing ABI. */
8226 static bool
8228 {
8238 {
8239 /* Walk the aggregates recursively. */
8241 {
8245 {
8246 tree field;
8248 /* Walk all the structure fields. */
8250 field;
8252 {
8256 }
8258 }
8261 /* Just for use if some languages passes arrays by value. */
8268 }
8269 }
8270 else
8274 }
8276 /* Gives the alignment boundary, in bits, of an argument with the
8277 specified mode and type. */
8279 static unsigned int
8281 {
8284 {
8285 /* Since the main variant type is used for call, we convert it to
8286 the main variant type. */
8289 }
8290 else
8294 else
8295 {
8300 {
8301 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
8303 {
8306 }
8312 }
8315 && !warned
8317 saved_align))
8318 {
8321 "The ABI for passing parameters with %d-byte"
8324 }
8325 }
8328 }
8330 /* Return true if N is a possible register number of function value. */
8332 static bool
8334 {
8336 {
8349 /* Complex values are returned in %st(0)/%st(1) pair. */
8352 /* TODO: The function should depend on current function ABI but
8353 builtins.c would need updating then. Therefore we use the
8354 default ABI. */
8359 /* Complex values are returned in %xmm0/%xmm1 pair. */
8368 }
8371 }
8373 /* Define how to find the value returned by a function.
8374 VALTYPE is the data type of the value (as a tree).
8375 If the precise function being called is known, FUNC is its FUNCTION_DECL;
8376 otherwise, FUNC is 0. */
8378 static rtx
8381 {
8384 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
8385 we normally prevent this case when mmx is not available. However
8386 some ABIs may require the result to be returned like DImode. */
8390 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
8391 we prevent this case when sse is not available. However some ABIs
8392 may require the result to be returned like integer TImode. */
8397 /* 32-byte vector modes in %ymm0. */
8401 /* 64-byte vector modes in %zmm0. */
8405 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
8408 else
8409 /* Most things go in %eax. */
8412 /* Override FP return register with %xmm0 for local functions when
8413 SSE math is enabled or for functions with sseregparm attribute. */
8415 {
8418 {
8423 }
8427 }
8429 /* OImode shouldn't be used directly. */
8433 }
8435 static rtx
8437 const_tree valtype)
8438 {
8439 rtx ret;
8441 /* Handle libcalls, which don't provide a type node. */
8443 {
8447 {
8466 }
8469 }
8471 {
8472 /* Pointers are always returned in word_mode. */
8474 }
8480 /* For zero sized structures, construct_container returns NULL, but we
8481 need to keep rest of compiler happy by returning meaningful value. */
8486 }
8488 static rtx
8490 const_tree valtype)
8491 {
8495 {
8497 {
8516 }
8517 }
8519 }
8521 static rtx
8524 {
8539 else
8541 }
8543 static rtx
8545 {
8551 }
8553 /* Return an RTX representing a place where a function returns
8554 or recieves pointer bounds or NULL if no bounds are returned.
8556 VALTYPE is a data type of a value returned by the function.
8558 FN_DECL_OR_TYPE is a tree node representing FUNCTION_DECL
8559 or FUNCTION_TYPE of the function.
8561 If OUTGOING is false, return a place in which the caller will
8562 see the return value. Otherwise, return a place where a
8563 function returns a value. */
8565 static rtx
8567 const_tree fntype_or_decl ATTRIBUTE_UNUSED,
8569 {
8575 {
8576 bitmap slots;
8578 bitmap_iterator bi;
8586 {
8591 }
8597 }
8598 else
8602 }
8604 /* Pointer function arguments and return values are promoted to
8605 word_mode. */
8607 static machine_mode
8611 {
8613 {
8616 }
8618 for_return);
8619 }
8621 /* Return true if a structure, union or array with MODE containing FIELD
8622 should be accessed using BLKmode. */
8624 static bool
8626 {
8627 /* Union with XFmode must be in BLKmode. */
8631 }
8633 rtx
8635 {
8637 }
8639 /* Return true iff type is returned in memory. */
8641 static bool
8643 {
8644 #ifdef SUBTARGET_RETURN_IN_MEMORY
8646 #else
8648 HOST_WIDE_INT size;
8654 {
8656 {
8659 /* __m128 is returned in xmm0. */
8668 /* Otherwise, the size must be exactly in [1248]. */
8670 }
8671 else
8672 {
8677 }
8678 }
8679 else
8680 {
8683 /* Intel MCU psABI returns scalars and aggregates no larger than 8
8684 bytes in registers. */
8695 {
8696 /* User-created vectors small enough to fit in EAX. */
8700 /* Unless ABI prescibes otherwise,
8701 MMX/3dNow values are returned in MM0 if available. */
8706 /* SSE values are returned in XMM0 if available. */
8710 /* AVX values are returned in YMM0 if available. */
8714 /* AVX512F values are returned in ZMM0 if available. */
8717 }
8725 /* OImode shouldn't be used directly. */
8729 }
8730 #endif
8731 }
8733 \f
8734 /* Create the va_list data type. */
8736 static tree
8738 {
8747 unsigned_type_node);
8750 unsigned_type_node);
8753 ptr_type_node);
8756 ptr_type_node);
8775 /* The correct type is an array type of one element. */
8777 }
8779 /* Setup the builtin va_list data type and for 64-bit the additional
8780 calling convention specific va_list data types. */
8782 static tree
8784 {
8786 {
8787 /* Initialize ABI specific va_list builtin types. */
8793 /* For MS_ABI we use plain pointer to argument area. */
8798 }
8799 else
8800 {
8801 /* For i386 we use plain pointer to argument area. */
8803 }
8804 }
8806 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8808 static void
8810 {
8812 alias_set_type set;
8815 /* GPR size of varargs save area. */
8818 else
8821 /* FPR size of varargs save area. We don't need it if we don't pass
8822 anything in SSE registers. */
8825 else
8839 {
8847 }
8850 {
8851 machine_mode smode;
8853 rtx test;
8855 /* Now emit code to save SSE registers. The AX parameter contains number
8856 of SSE parameter registers used to call this function, though all we
8857 actually check here is the zero/non-zero status. */
8862 label));
8864 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8865 we used movdqa (i.e. TImode) instead? Perhaps even better would
8866 be if we could determine the real mode of the data, via a hook
8867 into pass_stdarg. Ignore all that for now. */
8877 {
8886 }
8889 }
8890 }
8892 static void
8894 {
8898 /* Reset to zero, as there might be a sysv vaarg used
8899 before. */
8904 {
8915 }
8916 }
8918 static void
8921 {
8923 CUMULATIVE_ARGS next_cum;
8924 tree fntype;
8926 /* This argument doesn't appear to be used anymore. Which is good,
8927 because the old code here didn't suppress rtl generation. */
8935 /* For varargs, we do not want to skip the dummy va_dcl argument.
8936 For stdargs, we do want to skip the last named argument. */
8944 else
8946 }
8948 static void
8951 tree type,
8954 {
8956 CUMULATIVE_ARGS next_cum;
8957 tree fntype;
8958 rtx save_area;
8963 /* Do nothing if we use plain pointer to argument area. */
8969 /* For varargs, we do not want to skip the dummy va_dcl argument.
8970 For stdargs, we do want to skip the last named argument. */
8984 {
8988 rtx bounds;
8992 else
8993 {
8994 rtx ldx_addr =
9001 }
9007 bnd_reg++;
9008 }
9009 }
9012 /* Checks if TYPE is of kind va_list char *. */
9014 static bool
9016 {
9017 tree canonic;
9019 /* For 32-bit it is always true. */
9025 }
9027 /* Implement va_start. */
9029 static void
9031 {
9035 tree type;
9036 rtx ovf_rtx;
9040 {
9043 /* When we are splitting the stack, we can't refer to the stack
9044 arguments using internal_arg_pointer, because they may be on
9045 the old stack. The split stack prologue will arrange to
9046 leave a pointer to the old stack arguments in a scratch
9047 register, which we here copy to a pseudo-register. The split
9048 stack prologue can't set the pseudo-register directly because
9049 it (the prologue) runs before any registers have been saved. */
9053 {
9054 rtx reg;
9068 }
9069 }
9071 /* Only 64bit target needs something special. */
9073 {
9076 else
9077 {
9087 /* Store zero bounds for va_list. */
9091 next));
9093 }
9095 }
9104 /* The following should be folded into the MEM_REF offset. */
9114 /* Count number of gp and fp argument registers used. */
9120 {
9126 }
9129 {
9135 }
9137 /* Find the overflow area. */
9141 else
9147 /* Store zero bounds for overflow area pointer. */
9156 {
9157 /* Find the register save area.
9158 Prologue of the function save it right above stack frame. */
9164 /* Store zero bounds for save area pointer. */
9171 }
9172 }
9174 /* Implement va_arg. */
9176 static tree
9179 {
9186 rtx container;
9188 tree ptrtype;
9189 machine_mode nat_mode;
9192 /* Only 64bit target needs something special. */
9216 {
9229 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
9231 {
9234 }
9242 }
9244 /* Pull the value out of the saved registers. */
9249 {
9263 /* In case we are passing structure, verify that it is consecutive block
9264 on the register save area. If not we need to do moves. */
9266 {
9267 /* Verify that all registers are strictly consecutive */
9269 {
9273 {
9278 }
9279 }
9280 else
9281 {
9285 {
9290 }
9291 }
9292 }
9294 {
9297 }
9298 else
9299 {
9302 }
9304 /* First ensure that we fit completely in registers. */
9306 {
9313 }
9315 {
9323 }
9325 /* Compute index to start of area used for integer regs. */
9327 {
9328 /* int_addr = gpr + sav; */
9331 }
9333 {
9334 /* sse_addr = fpr + sav; */
9337 }
9339 {
9343 /* addr = &temp; */
9348 {
9352 tree piece_type;
9353 tree addr_type;
9354 tree daddr_type;
9363 {
9368 }
9372 else
9379 {
9382 }
9383 else
9384 {
9387 }
9394 {
9399 }
9400 else
9401 {
9402 tree copy
9407 }
9409 }
9410 }
9413 {
9417 }
9420 {
9424 }
9429 }
9431 /* ... otherwise out of the overflow area. */
9433 /* When we align parameter on stack for caller, if the parameter
9434 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
9435 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
9436 here with caller. */
9441 /* Care for on-stack alignment if needed. */
9444 else
9445 {
9450 }
9467 }
9468 \f
9469 /* Return true if OPNUM's MEM should be matched
9470 in movabs* patterns. */
9472 bool
9474 {
9486 }
9487 \f
9488 /* Initialize the table of extra 80387 mathematical constants. */
9490 static void
9492 {
9494 {
9500 };
9504 {
9506 /* Ensure each constant is rounded to XFmode precision. */
9509 }
9512 }
9514 /* Return non-zero if the constant is something that
9515 can be loaded with a special instruction. */
9517 int
9519 {
9522 REAL_VALUE_TYPE r;
9534 /* For XFmode constants, try to find a special 80387 instruction when
9535 optimizing for size or on those CPUs that benefit from them. */
9538 {
9547 }
9549 /* Load of the constant -0.0 or -1.0 will be split as
9550 fldz;fchs or fld1;fchs sequence. */
9557 }
9559 /* Return the opcode of the special instruction to be used to load
9560 the constant X. */
9564 {
9566 {
9586 }
9587 }
9589 /* Return the CONST_DOUBLE representing the 80387 constant that is
9590 loaded by the specified special instruction. The argument IDX
9591 matches the return value from standard_80387_constant_p. */
9593 rtx
9595 {
9602 {
9613 }
9616 XFmode);
9617 }
9619 /* Return 1 if X is all 0s and 2 if x is all 1s
9620 in supported SSE/AVX vector mode. */
9622 int
9624 {
9625 machine_mode mode;
9636 {
9657 }
9660 }
9662 /* Return the opcode of the special instruction to be used to load
9663 the constant X. */
9667 {
9669 {
9672 {
9699 }
9709 else
9714 }
9716 }
9718 /* Returns true if OP contains a symbol reference */
9720 bool
9722 {
9731 {
9733 {
9739 }
9743 }
9746 }
9748 /* Return true if it is appropriate to emit `ret' instructions in the
9749 body of a function. Do this only if the epilogue is simple, needing a
9750 couple of insns. Prior to reloading, we can't tell how many registers
9751 must be saved, so return false then. Return false if there is no frame
9752 marker to de-allocate. */
9754 bool
9756 {
9762 /* Don't allow more than 32k pop, since that's all we can do
9763 with one instruction. */
9770 }
9771 \f
9772 /* Value should be nonzero if functions must have frame pointers.
9773 Zero means the frame pointer need not be set up (and parms may
9774 be accessed via the stack pointer) in functions that seem suitable. */
9776 static bool
9778 {
9779 /* If we accessed previous frames, then the generated code expects
9780 to be able to access the saved ebp value in our frame. */
9784 /* Several x86 os'es need a frame pointer for other reasons,
9785 usually pertaining to setjmp. */
9789 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9793 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9794 allocation is 4GB. */
9798 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9799 turns off the frame pointer by default. Turn it back on now if
9800 we've not got a leaf function. */
9810 }
9812 /* Record that the current function accesses previous call frames. */
9814 void
9816 {
9818 }
9819 \f
9820 #ifndef USE_HIDDEN_LINKONCE
9821 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9822 # define USE_HIDDEN_LINKONCE 1
9823 # else
9824 # define USE_HIDDEN_LINKONCE 0
9825 # endif
9826 #endif
9830 /* Fills in the label name that should be used for a pc thunk for
9831 the given register. */
9833 static void
9835 {
9840 else
9842 }
9845 /* This function generates code for -fpic that loads %ebx with
9846 the return address of the caller and then returns. */
9848 static void
9850 {
9855 {
9857 tree decl;
9873 #if TARGET_MACHO
9875 {
9884 }
9885 else
9886 #endif
9888 {
9899 }
9900 else
9901 {
9904 }
9910 /* Make sure unwind info is emitted for the thunk if needed. */
9913 /* Pad stack IP move with 4 instructions (two NOPs count
9914 as one instruction). */
9916 {
9921 }
9932 }
9936 }
9938 /* Emit code for the SET_GOT patterns. */
9942 {
9948 {
9949 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9954 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9955 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9956 an unadorned address. */
9961 }
9966 {
9968 /* We don't need a pic base, we're not producing pic. */
9975 }
9976 else
9977 {
9986 #if TARGET_MACHO
9987 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9988 This is what will be referenced by the Mach-O PIC subsystem. */
9992 /* When we are restoring the pic base at the site of a nonlocal label,
9993 and we decided to emit the pic base above, we will still output a
9994 local label used for calculating the correction offset (even though
9995 the offset will be 0 in that case). */
9999 #endif
10000 }
10006 }
10008 /* Generate an "push" pattern for input ARG. */
10010 static rtx
10012 {
10024 stack_pointer_rtx)),
10025 arg);
10026 }
10028 /* Generate an "pop" pattern for input ARG. */
10030 static rtx
10032 {
10039 stack_pointer_rtx)));
10040 }
10042 /* Return >= 0 if there is an unused call-clobbered register available
10043 for the entire function. */
10045 static unsigned int
10047 {
10054 {
10056 /* Can't use the same register for both PIC and DRAP. */
10059 else
10064 }
10067 }
10069 /* Return TRUE if we need to save REGNO. */
10071 static bool
10073 {
10076 {
10078 {
10079 /* REAL_PIC_OFFSET_TABLE_REGNUM used by call to
10080 _mcount in prologue. */
10083 }
10090 }
10093 {
10096 {
10102 }
10103 }
10114 }
10116 /* Return number of saved general prupose registers. */
10118 static int
10120 {
10126 nregs ++;
10128 }
10130 /* Return number of saved SSE registrers. */
10132 static int
10134 {
10142 nregs ++;
10144 }
10146 /* Given FROM and TO register numbers, say whether this elimination is
10147 allowed. If stack alignment is needed, we can only replace argument
10148 pointer with hard frame pointer, or replace frame pointer with stack
10149 pointer. Otherwise, frame pointer elimination is automatically
10150 handled and all other eliminations are valid. */
10152 static bool
10154 {
10160 else
10162 }
10164 /* Return the offset between two registers, one to be eliminated, and the other
10165 its replacement, at the start of a routine. */
10167 HOST_WIDE_INT
10169 {
10178 else
10179 {
10187 }
10188 }
10190 /* In a dynamically-aligned function, we can't know the offset from
10191 stack pointer to frame pointer, so we must ensure that setjmp
10192 eliminates fp against the hard fp (%ebp) rather than trying to
10193 index from %esp up to the top of the frame across a gap that is
10194 of unknown (at compile-time) size. */
10195 static rtx
10197 {
10199 }
10201 /* When using -fsplit-stack, the allocation routines set a field in
10202 the TCB to the bottom of the stack plus this much space, measured
10203 in bytes. */
10205 #define SPLIT_STACK_AVAILABLE 256
10207 /* Fill structure ix86_frame about frame of currently computed function. */
10209 static void
10211 {
10213 HOST_WIDE_INT offset;
10216 HOST_WIDE_INT to_allocate;
10221 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
10222 function prologues and leaf. */
10226 {
10229 }
10230 /* preferred_stack_boundary is never updated for call
10231 expanded from tls descriptor. Update it here. We don't update it in
10232 expand stage because according to the comments before
10233 ix86_current_function_calls_tls_descriptor, tls calls may be optimized
10234 away. */
10237 {
10241 }
10250 /* For SEH we have to limit the amount of code movement into the prologue.
10251 At present we do this via a BLOCKAGE, at which point there's very little
10252 scheduling that can be done, which means that there's very little point
10253 in doing anything except PUSHs. */
10257 /* During reload iteration the amount of registers saved can change.
10258 Recompute the value as needed. Do not recompute when amount of registers
10259 didn't change as reload does multiple calls to the function and does not
10260 expect the decision to change within single iteration. */
10263 {
10269 /* The fast prologue uses move instead of push to save registers. This
10270 is significantly longer, but also executes faster as modern hardware
10271 can execute the moves in parallel, but can't do that for push/pop.
10273 Be careful about choosing what prologue to emit: When function takes
10274 many instructions to execute we may use slow version as well as in
10275 case function is known to be outside hot spot (this is known with
10276 feedback only). Weight the size of function by number of registers
10277 to save as it is cheap to use one or two push instructions but very
10278 slow to use many of them. */
10282 || (flag_branch_probabilities
10285 else
10288 }
10290 frame->save_regs_using_mov
10292 /* If static stack checking is enabled and done with probes,
10293 the registers need to be saved before allocating the frame. */
10296 /* Skip return address. */
10299 /* Skip pushed static chain. */
10303 /* Skip saved base pointer. */
10308 /* The traditional frame pointer location is at the top of the frame. */
10311 /* Register save area */
10315 /* On SEH target, registers are pushed just before the frame pointer
10316 location. */
10320 /* Align and set SSE register save area. */
10322 {
10323 /* The only ABI that has saved SSE registers (Win64) also has a
10324 16-byte aligned default stack, and thus we don't need to be
10325 within the re-aligned local stack frame to save them. */
10329 }
10332 /* The re-aligned stack starts here. Values before this point are not
10333 directly comparable with values below this point. In order to make
10334 sure that no value happens to be the same before and after, force
10335 the alignment computation below to add a non-zero value. */
10339 /* Va-arg area */
10343 /* Align start of frame for local function. */
10352 /* Frame pointer points here. */
10357 /* Add outgoing arguments area. Can be skipped if we eliminated
10358 all the function calls as dead code.
10359 Skipping is however impossible when function calls alloca. Alloca
10360 expander assumes that last crtl->outgoing_args_size
10361 of stack frame are unused. */
10365 {
10368 }
10369 else
10372 /* Align stack boundary. Only needed if we're calling another function
10373 or using alloca. */
10378 /* We've reached end of stack frame. */
10381 /* Size prologue needs to allocate. */
10392 {
10398 }
10399 else
10403 /* The SEH frame pointer location is near the bottom of the frame.
10404 This is enforced by the fact that the difference between the
10405 stack pointer and the frame pointer is limited to 240 bytes in
10406 the unwind data structure. */
10408 {
10409 HOST_WIDE_INT diff;
10411 /* If we can leave the frame pointer where it is, do so. Also, returns
10412 the establisher frame for __builtin_frame_address (0). */
10417 {
10418 /* Ideally we'd determine what portion of the local stack frame
10419 (within the constraint of the lowest 240) is most heavily used.
10420 But without that complication, simply bias the frame pointer
10421 by 128 bytes so as to maximize the amount of the local stack
10422 frame that is addressable with 8-bit offsets. */
10424 }
10425 }
10426 }
10428 /* This is semi-inlined memory_address_length, but simplified
10429 since we know that we're always dealing with reg+offset, and
10430 to avoid having to create and discard all that rtl. */
10434 {
10438 {
10439 /* EBP and R13 cannot be encoded without an offset. */
10441 }
10445 /* ESP and R12 must be encoded with a SIB byte. */
10447 len++;
10450 }
10452 /* Return an RTX that points to CFA_OFFSET within the stack frame.
10453 The valid base registers are taken from CFUN->MACHINE->FS. */
10455 static rtx
10457 {
10463 {
10464 /* Choose the base register most likely to allow the most scheduling
10465 opportunities. Generally FP is valid throughout the function,
10466 while DRAP must be reloaded within the epilogue. But choose either
10467 over the SP due to increased encoding size. */
10470 {
10473 }
10475 {
10478 }
10480 {
10483 }
10484 }
10485 else
10486 {
10487 HOST_WIDE_INT toffset;
10490 /* Choose the base register with the smallest address encoding.
10491 With a tie, choose FP > DRAP > SP. */
10493 {
10497 }
10499 {
10503 {
10507 }
10508 }
10510 {
10514 {
10518 }
10519 }
10520 }
10524 }
10526 /* Emit code to save registers in the prologue. */
10528 static void
10530 {
10536 {
10539 }
10540 }
10542 /* Emit a single register save at CFA - CFA_OFFSET. */
10544 static void
10546 HOST_WIDE_INT cfa_offset)
10547 {
10555 /* For SSE saves, we need to indicate the 128-bit alignment. */
10566 /* When saving registers into a re-aligned local stack frame, avoid
10567 any tricky guessing by dwarf2out. */
10569 {
10573 {
10574 /* A bit of a hack. We force the DRAP register to be saved in
10575 the re-aligned stack frame, which provides us with a copy
10576 of the CFA that will last past the prologue. Install it. */
10582 }
10583 else
10584 {
10585 /* The frame pointer is a stable reference within the
10586 aligned frame. Use it. */
10592 }
10593 }
10595 /* The memory may not be relative to the current CFA register,
10596 which means that we may need to generate a new pattern for
10597 use by the unwind info. */
10599 {
10604 }
10605 }
10607 /* Emit code to save registers using MOV insns.
10608 First register is stored at CFA - CFA_OFFSET. */
10609 static void
10611 {
10616 {
10619 }
10620 }
10622 /* Emit code to save SSE registers using MOV insns.
10623 First register is stored at CFA - CFA_OFFSET. */
10624 static void
10626 {
10631 {
10634 }
10635 }
10639 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
10640 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
10641 Don't add the note if the previously saved value will be left untouched
10642 within stack red-zone till return, as unwinders can find the same value
10643 in the register and on the stack. */
10645 static void
10647 {
10653 {
10656 }
10657 else
10658 queued_cfa_restores
10660 }
10662 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
10664 static void
10666 {
10667 rtx last;
10671 ;
10676 }
10678 /* Expand prologue or epilogue stack adjustment.
10679 The pattern exist to put a dependency on all ebp-based memory accesses.
10680 STYLE should be negative if instructions should be marked as frame related,
10681 zero if %r11 register is live and cannot be freely used and positive
10682 otherwise. */
10684 static void
10687 {
10689 rtx insn;
10696 else
10697 {
10698 rtx tmp;
10699 /* r11 is used by indirect sibcall return as well, set before the
10700 epilogue and used after the epilogue. */
10703 else
10704 {
10708 }
10714 }
10721 {
10722 rtx r;
10732 }
10734 {
10737 {
10741 }
10742 }
10745 {
10750 {
10753 }
10755 {
10758 }
10759 else
10760 {
10761 /* Else there are two possibilities: SP itself, which we set
10762 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10763 taken care of this by hand along the eh_return path. */
10766 }
10770 }
10771 }
10773 /* Find an available register to be used as dynamic realign argument
10774 pointer regsiter. Such a register will be written in prologue and
10775 used in begin of body, so it must not be
10776 1. parameter passing register.
10777 2. GOT pointer.
10778 We reuse static-chain register if it is available. Otherwise, we
10779 use DI for i386 and R13 for x86-64. We chose R13 since it has
10780 shorter encoding.
10782 Return: the regno of chosen register. */
10784 static unsigned int
10786 {
10790 {
10791 /* Use R13 for nested function or function need static chain.
10792 Since function with tail call may use any caller-saved
10793 registers in epilogue, DRAP must not use caller-saved
10794 register in such case. */
10799 }
10800 else
10801 {
10802 /* Use DI for nested function or function need static chain.
10803 Since function with tail call may use any caller-saved
10804 registers in epilogue, DRAP must not use caller-saved
10805 register in such case. */
10809 /* Reuse static chain register if it isn't used for parameter
10810 passing. */
10812 {
10816 }
10818 }
10819 }
10821 /* Return minimum incoming stack alignment. */
10823 static unsigned int
10825 {
10828 /* Prefer the one specified at command line. */
10831 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10832 if -mstackrealign is used, it isn't used for sibcall check and
10833 estimated stack alignment is 128bit. */
10835 && !TARGET_64BIT
10836 && ix86_force_align_arg_pointer
10839 else
10842 /* Incoming stack alignment can be changed on individual functions
10843 via force_align_arg_pointer attribute. We use the smallest
10844 incoming stack boundary. */
10850 /* The incoming stack frame has to be aligned at least at
10851 parm_stack_boundary. */
10855 /* Stack at entrance of main is aligned by runtime. We use the
10856 smallest incoming stack boundary. */
10864 }
10866 /* Update incoming stack boundary and estimated stack alignment. */
10868 static void
10870 {
10871 ix86_incoming_stack_boundary
10874 /* x86_64 vararg needs 16byte stack alignment for register save
10875 area. */
10880 }
10882 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10883 needed or an rtx for DRAP otherwise. */
10885 static rtx
10887 {
10892 {
10893 /* Assign DRAP to vDRAP and returns vDRAP */
10895 rtx drap_vreg;
10896 rtx arg_ptr;
10909 {
10912 }
10914 }
10915 else
10917 }
10919 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10921 static rtx
10923 {
10925 }
10928 rtx reg;
10930 };
10932 /* Return a short-lived scratch register for use on function entry.
10933 In 32-bit mode, it is valid only after the registers are saved
10934 in the prologue. This register must be released by means of
10935 release_scratch_register_on_entry once it is dead. */
10937 static void
10939 {
10945 {
10946 /* We always use R11 in 64-bit mode. */
10948 }
10949 else
10950 {
10952 bool fastcall_p
10954 bool thiscall_p
10958 int drap_regno
10961 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10962 for the static chain register. */
10966 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10967 for the static chain register. */
10972 /* ecx is the static chain register. */
10974 && !static_chain_p
10979 /* esi is the static chain register. */
10985 else
10986 {
10989 }
10990 }
10994 {
10997 }
10998 }
11000 /* Release a scratch register obtained from the preceding function. */
11002 static void
11004 {
11006 {
11010 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
11016 }
11017 }
11019 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
11021 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
11023 static void
11025 {
11026 /* We skip the probe for the first interval + a small dope of 4 words and
11027 probe that many bytes past the specified size to maintain a protection
11028 area at the botton of the stack. */
11032 /* See if we have a constant small number of probes to generate. If so,
11033 that's the easy case. The run-time loop is made up of 11 insns in the
11034 generic case while the compile-time loop is made up of 3+2*(n-1) insns
11035 for n # of intervals. */
11037 {
11041 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
11042 values of N from 1 until it exceeds SIZE. If only one probe is
11043 needed, this will not generate any code. Then adjust and probe
11044 to PROBE_INTERVAL + SIZE. */
11046 {
11048 {
11051 }
11052 else
11059 }
11063 else
11071 /* Adjust back to account for the additional first interval. */
11075 }
11077 /* Otherwise, do the same as above, but in a loop. Note that we must be
11078 extra careful with variables wrapping around because we might be at
11079 the very top (or the very bottom) of the address space and we have
11080 to be able to handle this case properly; in particular, we use an
11081 equality test for the loop condition. */
11082 else
11083 {
11084 HOST_WIDE_INT rounded_size;
11090 /* Step 1: round SIZE to the previous multiple of the interval. */
11095 /* Step 2: compute initial and final value of the loop counter. */
11097 /* SP = SP_0 + PROBE_INTERVAL. */
11102 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
11106 stack_pointer_rtx)));
11109 /* Step 3: the loop
11111 while (SP != LAST_ADDR)
11112 {
11113 SP = SP + PROBE_INTERVAL
11114 probe at SP
11115 }
11117 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
11118 values of N from 1 until it is equal to ROUNDED_SIZE. */
11123 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
11124 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
11127 {
11132 }
11134 /* Adjust back to account for the additional first interval. */
11140 }
11144 /* Even if the stack pointer isn't the CFA register, we need to correctly
11145 describe the adjustments made to it, in particular differentiate the
11146 frame-related ones from the frame-unrelated ones. */
11148 {
11161 }
11163 /* Make sure nothing is scheduled before we are done. */
11165 }
11167 /* Adjust the stack pointer up to REG while probing it. */
11171 {
11181 /* Jump to END_LAB if SP == LAST_ADDR. */
11189 /* SP = SP + PROBE_INTERVAL. */
11193 /* Probe at SP. */
11204 }
11206 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
11207 inclusive. These are offsets from the current stack pointer. */
11209 static void
11211 {
11212 /* See if we have a constant small number of probes to generate. If so,
11213 that's the easy case. The run-time loop is made up of 7 insns in the
11214 generic case while the compile-time loop is made up of n insns for n #
11215 of intervals. */
11217 {
11218 HOST_WIDE_INT i;
11220 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
11221 it exceeds SIZE. If only one probe is needed, this will not
11222 generate any code. Then probe at FIRST + SIZE. */
11229 }
11231 /* Otherwise, do the same as above, but in a loop. Note that we must be
11232 extra careful with variables wrapping around because we might be at
11233 the very top (or the very bottom) of the address space and we have
11234 to be able to handle this case properly; in particular, we use an
11235 equality test for the loop condition. */
11236 else
11237 {
11244 /* Step 1: round SIZE to the previous multiple of the interval. */
11249 /* Step 2: compute initial and final value of the loop counter. */
11251 /* TEST_OFFSET = FIRST. */
11254 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
11258 /* Step 3: the loop
11260 while (TEST_ADDR != LAST_ADDR)
11261 {
11262 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11263 probe at TEST_ADDR
11264 }
11266 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11267 until it is equal to ROUNDED_SIZE. */
11272 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11273 that SIZE is equal to ROUNDED_SIZE. */
11278 stack_pointer_rtx,
11283 }
11285 /* Make sure nothing is scheduled before we are done. */
11287 }
11289 /* Probe a range of stack addresses from REG to END, inclusive. These are
11290 offsets from the current stack pointer. */
11294 {
11304 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11312 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11316 /* Probe at TEST_ADDR. */
11329 }
11331 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
11332 to be generated in correct form. */
11333 static void
11335 {
11336 /* Check if stack realign is really needed after reload, and
11337 stores result in cfun */
11338 unsigned int incoming_stack_boundary
11347 {
11348 /* After stack_realign_needed is finalized, we can't no longer
11349 change it. */
11352 }
11354 /* If the only reason for frame_pointer_needed is that we conservatively
11355 assumed stack realignment might be needed, but in the end nothing that
11356 needed the stack alignment had been spilled, clear frame_pointer_needed
11357 and say we don't need stack realignment. */
11359 && frame_pointer_needed
11361 && flag_omit_frame_pointer
11363 && !ix86_current_function_calls_tls_descriptor
11372 {
11374 basic_block bb;
11381 HARD_FRAME_POINTER_REGNUM);
11383 {
11388 set_up_by_prologue))
11389 {
11393 }
11394 }
11396 /* If drap has been set, but it actually isn't live at the start
11397 of the function, there is no reason to set it up. */
11399 {
11402 {
11405 }
11406 }
11407 else
11422 }
11426 }
11428 /* Delete SET_GOT right after entry block if it is allocated to reg. */
11430 static void
11432 {
11438 {
11441 {
11447 }
11448 }
11449 }
11451 /* Expand the prologue into a bunch of separate insns. */
11453 void
11455 {
11459 HOST_WIDE_INT allocate;
11466 /* DRAP should not coexist with stack_realign_fp */
11471 /* Initialize CFA state for before the prologue. */
11475 /* Track SP offset to the CFA. We continue tracking this after we've
11476 swapped the CFA register away from SP. In the case of re-alignment
11477 this is fudged; we're interested to offsets within the local frame. */
11484 {
11485 /* We should have already generated an error for any use of
11486 ms_hook on a nested function. */
11489 /* Check if profiling is active and we shall use profiling before
11490 prologue variant. If so sorry. */
11495 /* In ix86_asm_output_function_label we emitted:
11496 8b ff movl.s %edi,%edi
11497 55 push %ebp
11498 8b ec movl.s %esp,%ebp
11500 This matches the hookable function prologue in Win32 API
11501 functions in Microsoft Windows XP Service Pack 2 and newer.
11502 Wine uses this to enable Windows apps to hook the Win32 API
11503 functions provided by Wine.
11505 What that means is that we've already set up the frame pointer. */
11509 {
11512 /* We've decided to use the frame pointer already set up.
11513 Describe this to the unwinder by pretending that both
11514 push and mov insns happen right here.
11516 Putting the unwind info here at the end of the ms_hook
11517 is done so that we can make absolutely certain we get
11518 the required byte sequence at the start of the function,
11519 rather than relying on an assembler that can produce
11520 the exact encoding required.
11522 However it does mean (in the unpatched case) that we have
11523 a 1 insn window where the asynchronous unwind info is
11524 incorrect. However, if we placed the unwind info at
11525 its correct location we would have incorrect unwind info
11526 in the patched case. Which is probably all moot since
11527 I don't expect Wine generates dwarf2 unwind info for the
11528 system libraries that use this feature. */
11534 stack_pointer_rtx);
11542 /* Note that gen_push incremented m->fs.cfa_offset, even
11543 though we didn't emit the push insn here. */
11547 }
11548 else
11549 {
11550 /* The frame pointer is not needed so pop %ebp again.
11551 This leaves us with a pristine state. */
11553 }
11554 }
11556 /* The first insn of a function that accepts its static chain on the
11557 stack is to push the register that would be filled in by a direct
11558 call. This insn will be skipped by the trampoline. */
11560 {
11565 /* We don't want to interpret this push insn as a register save,
11566 only as a stack adjustment. The real copy of the register as
11567 a save will be done later, if needed. */
11572 }
11574 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
11575 of DRAP is needed and stack realignment is really needed after reload */
11577 {
11580 /* Only need to push parameter pointer reg if it is caller saved. */
11582 {
11583 /* Push arg pointer reg */
11586 }
11588 /* Grab the argument pointer. */
11595 /* Align the stack. */
11597 stack_pointer_rtx,
11601 /* Replicate the return address on the stack so that return
11602 address can be reached via (argp - 1) slot. This is needed
11603 to implement macro RETURN_ADDR_RTX and intrinsic function
11604 expand_builtin_return_addr etc. */
11610 /* For the purposes of frame and register save area addressing,
11611 we've started over with a new frame. */
11616 {
11617 /* Replicate static chain on the stack so that static chain
11618 can be reached via (argp - 2) slot. This is needed for
11619 nested function with stack realignment. */
11622 }
11623 }
11629 {
11630 /* Note: AT&T enter does NOT have reversed args. Enter is probably
11631 slower on all targets. Also sdb doesn't like it. */
11635 /* Push registers now, before setting the frame pointer
11636 on SEH target. */
11638 && TARGET_SEH
11640 {
11644 }
11647 {
11655 }
11656 }
11659 {
11660 /* If saving registers via PUSH, do so now. */
11662 {
11666 }
11668 /* When using red zone we may start register saving before allocating
11669 the stack frame saving one cycle of the prologue. However, avoid
11670 doing this if we have to probe the stack; at least on x86_64 the
11671 stack probe can turn into a call that clobbers a red zone location. */
11673 && (! TARGET_STACK_PROBE
11675 {
11678 }
11679 }
11682 {
11686 /* The computation of the size of the re-aligned stack frame means
11687 that we must allocate the size of the register save area before
11688 performing the actual alignment. Otherwise we cannot guarantee
11689 that there's enough storage above the realignment point. */
11696 /* Align the stack. */
11698 stack_pointer_rtx,
11701 /* For the purposes of register save area addressing, the stack
11702 pointer is no longer valid. As for the value of sp_offset,
11703 see ix86_compute_frame_layout, which we need to match in order
11704 to pass verification of stack_pointer_offset at the end. */
11707 }
11712 {
11713 /* We start to count from ARG_POINTER. */
11716 /* If it was realigned, take into account the fake frame. */
11718 {
11725 /* This over-estimates by 1 minimal-stack-alignment-unit but
11726 mitigates that by counting in the new return address slot. */
11727 current_function_dynamic_stack_size
11729 }
11732 }
11734 /* On SEH target with very large frame size, allocate an area to save
11735 SSE registers (as the very large allocation won't be described). */
11739 {
11740 HOST_WIDE_INT sse_size =
11745 /* No need to do stack checking as the area will be immediately
11746 written. */
11753 }
11755 /* The stack has already been decremented by the instruction calling us
11756 so probe if the size is non-negative to preserve the protection area. */
11758 {
11759 /* We expect the registers to be saved when probes are used. */
11763 {
11766 {
11769 }
11770 }
11771 else
11772 {
11779 {
11781 {
11784 }
11785 else
11787 }
11788 else
11789 {
11791 {
11795 }
11796 else
11798 }
11799 }
11800 }
11803 ;
11806 {
11810 }
11811 else
11812 {
11824 {
11827 /* Note that SEH directives need to continue tracking the stack
11828 pointer even after the frame pointer has been set up. */
11830 {
11838 }
11839 }
11842 {
11847 {
11855 }
11856 }
11861 /* Use the fact that AX still contains ALLOCATE. */
11863 ? gen_pro_epilogue_adjust_stack_di_sub
11870 {
11878 }
11881 /* Use stack_pointer_rtx for relative addressing so that code
11882 works for realigned stack, too. */
11884 {
11891 }
11893 {
11898 }
11899 }
11902 /* If we havn't already set up the frame pointer, do so now. */
11904 {
11916 }
11923 /* For the mcount profiling on 32 bit PIC mode we need to emit SET_GOT
11924 in PROLOGUE. */
11926 {
11932 /* Deleting already emmitted SET_GOT if exist and allocated to
11933 REAL_PIC_OFFSET_TABLE_REGNUM. */
11935 }
11938 {
11939 /* vDRAP is setup but after reload it turns out stack realign
11940 isn't necessary, here we will emit prologue to setup DRAP
11941 without stack realign adjustment */
11944 }
11946 /* Prevent instructions from being scheduled into register save push
11947 sequence when access to the redzone area is done through frame pointer.
11948 The offset between the frame pointer and the stack pointer is calculated
11949 relative to the value of the stack pointer at the end of the function
11950 prologue, and moving instructions that access redzone area via frame
11951 pointer inside push sequence violates this assumption. */
11955 /* Emit cld instruction if stringops are used in the function. */
11959 /* SEH requires that the prologue end within 256 bytes of the start of
11960 the function. Prevent instruction schedules that would extend that.
11961 Further, prevent alloca modifications to the stack pointer from being
11962 combined with prologue modifications. */
11965 }
11967 /* Emit code to restore REG using a POP insn. */
11969 static void
11971 {
11980 {
11981 /* Previously we'd represented the CFA as an expression
11982 like *(%ebp - 8). We've just popped that value from
11983 the stack, which means we need to reset the CFA to
11984 the drap register. This will remain until we restore
11985 the stack pointer. */
11989 /* This means that the DRAP register is valid for addressing too. */
11992 }
11995 {
12002 }
12004 /* When the frame pointer is the CFA, and we pop it, we are
12005 swapping back to the stack pointer as the CFA. This happens
12006 for stack frames that don't allocate other data, so we assume
12007 the stack pointer is now pointing at the return address, i.e.
12008 the function entry state, which makes the offset be 1 word. */
12010 {
12013 {
12021 }
12022 }
12023 }
12025 /* Emit code to restore saved registers using POP insns. */
12027 static void
12029 {
12035 }
12037 /* Emit code and notes for the LEAVE instruction. */
12039 static void
12041 {
12053 {
12061 }
12064 }
12066 /* Emit code to restore saved registers using MOV insns.
12067 First register is restored from CFA - CFA_OFFSET. */
12068 static void
12071 {
12077 {
12079 rtx mem;
12087 {
12088 /* Previously we'd represented the CFA as an expression
12089 like *(%ebp - 8). We've just popped that value from
12090 the stack, which means we need to reset the CFA to
12091 the drap register. This will remain until we restore
12092 the stack pointer. */
12096 /* This means that the DRAP register is valid for addressing. */
12098 }
12099 else
12103 }
12104 }
12106 /* Emit code to restore saved registers using MOV insns.
12107 First register is restored from CFA - CFA_OFFSET. */
12108 static void
12111 {
12116 {
12118 rtx mem;
12128 }
12129 }
12131 /* Restore function stack, frame, and registers. */
12133 void
12135 {
12151 /* The FP must be valid if the frame pointer is present. */
12156 /* We must have *some* valid pointer to the stack frame. */
12159 /* The DRAP is never valid at this point. */
12162 /* See the comment about red zone and frame
12163 pointer usage in ix86_expand_prologue. */
12170 /* Determine the CFA offset of the end of the red-zone. */
12173 {
12174 /* The red-zone begins below the return address. */
12177 /* When the register save area is in the aligned portion of
12178 the stack, determine the maximum runtime displacement that
12179 matches up with the aligned frame. */
12183 }
12185 /* Special care must be taken for the normal return case of a function
12186 using eh_return: the eax and edx registers are marked as saved, but
12187 not restored along this path. Adjust the save location to match. */
12191 /* EH_RETURN requires the use of moves to function properly. */
12194 /* SEH requires the use of pops to identify the epilogue. */
12197 /* If we're only restoring one register and sp is not valid then
12198 using a move instruction to restore the register since it's
12199 less work than reloading sp and popping the register. */
12212 && TARGET_USE_LEAVE
12216 else
12220 {
12221 /* Ensure that the entire register save area is addressable via
12222 the stack pointer, if we will restore via sp. */
12227 {
12231 style,
12233 }
12234 }
12236 /* If there are any SSE registers to restore, then we have to do it
12237 via moves, since there's obviously no pop for SSE regs. */
12243 {
12244 rtx t;
12249 /* eh_return epilogues need %ecx added to the stack pointer. */
12251 {
12255 /* Stack align doesn't work with eh_return. */
12257 /* Neither does regparm nested functions. */
12261 {
12269 /* Note that we use SA as a temporary CFA, as the return
12270 address is at the proper place relative to it. We
12271 pretend this happens at the FP restore insn because
12272 prior to this insn the FP would be stored at the wrong
12273 offset relative to SA, and after this insn we have no
12274 other reasonable register to use for the CFA. We don't
12275 bother resetting the CFA to the SP for the duration of
12276 the return insn. */
12289 }
12290 else
12291 {
12299 {
12303 UNITS_PER_WORD));
12305 }
12306 }
12309 }
12310 }
12311 else
12312 {
12313 /* SEH requires that the function end with (1) a stack adjustment
12314 if necessary, (2) a sequence of pops, and (3) a return or
12315 jump instruction. Prevent insns from the function body from
12316 being scheduled into this sequence. */
12318 {
12319 /* Prevent a catch region from being adjacent to the standard
12320 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
12321 several other flags that would be interesting to test are
12322 not yet set up. */
12325 else
12327 }
12329 /* First step is to deallocate the stack frame so that we can
12330 pop the registers. Also do it on SEH target for very large
12331 frame as the emitted instructions aren't allowed by the ABI in
12332 epilogues. */
12334 || (TARGET_SEH
12337 {
12342 }
12344 {
12348 style,
12350 }
12353 }
12355 /* If we used a stack pointer and haven't already got rid of it,
12356 then do so now. */
12358 {
12359 /* If the stack pointer is valid and pointing at the frame
12360 pointer store address, then we only need a pop. */
12363 /* Leave results in shorter dependency chains on CPUs that are
12364 able to grok it fast. */
12369 else
12370 {
12372 hard_frame_pointer_rtx,
12375 }
12376 }
12379 {
12407 }
12409 /* At this point the stack pointer must be valid, and we must have
12410 restored all of the registers. We may not have deallocated the
12411 entire stack frame. We've delayed this until now because it may
12412 be possible to merge the local stack deallocation with the
12413 deallocation forced by ix86_static_chain_on_stack. */
12418 {
12422 }
12423 else
12426 /* Sibcall epilogues don't want a return instruction. */
12428 {
12431 }
12434 {
12437 /* i386 can only pop 64K bytes. If asked to pop more, pop return
12438 address, do explicit add, and jump indirectly to the caller. */
12441 {
12445 /* There is no "pascal" calling convention in any 64bit ABI. */
12461 }
12462 else
12464 }
12465 else
12468 /* Restore the state back to the state from the prologue,
12469 so that it's correct for the next epilogue. */
12471 }
12473 /* Reset from the function's potential modifications. */
12475 static void
12477 {
12481 #if TARGET_MACHO
12482 /* Mach-O doesn't support labels at the end of objects, so if
12483 it looks like we might want one, insert a NOP. */
12484 {
12490 {
12491 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
12492 notes only, instead set their CODE_LABEL_NUMBER to -1,
12493 otherwise there would be code generation differences
12494 in between -g and -g0. */
12498 }
12508 }
12509 #endif
12511 }
12513 /* Return a scratch register to use in the split stack prologue. The
12514 split stack prologue is used for -fsplit-stack. It is the first
12515 instructions in the function, even before the regular prologue.
12516 The scratch register can be any caller-saved register which is not
12517 used for parameters or for the static chain. */
12519 static unsigned int
12521 {
12524 else
12525 {
12538 {
12540 {
12544 }
12546 }
12548 {
12552 }
12554 {
12557 else
12558 {
12560 {
12564 }
12566 }
12567 }
12568 else
12569 {
12570 /* FIXME: We could make this work by pushing a register
12571 around the addition and comparison. */
12574 }
12575 }
12576 }
12578 /* A SYMBOL_REF for the function which allocates new stackspace for
12579 -fsplit-stack. */
12583 /* A SYMBOL_REF for the more stack function when using the large
12584 model. */
12588 /* Handle -fsplit-stack. These are the first instructions in the
12589 function, even before the regular prologue. */
12591 void
12593 {
12595 HOST_WIDE_INT allocate;
12601 rtx fn;
12609 /* This is the label we will branch to if we have enough stack
12610 space. We expect the basic block reordering pass to reverse this
12611 branch if optimizing, so that we branch in the unlikely case. */
12614 /* We need to compare the stack pointer minus the frame size with
12615 the stack boundary in the TCB. The stack boundary always gives
12616 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
12617 can compare directly. Otherwise we need to do an addition. */
12620 UNSPEC_STACK_CHECK);
12625 else
12626 {
12628 rtx offset;
12630 /* We need a scratch register to hold the stack pointer minus
12631 the required frame size. Since this is the very start of the
12632 function, the scratch register can be any caller-saved
12633 register which is not used for parameters. */
12640 {
12641 /* We don't use ix86_gen_add3 in this case because it will
12642 want to split to lea, but when not optimizing the insn
12643 will not be split after this point. */
12646 offset)));
12647 }
12648 else
12649 {
12652 stack_pointer_rtx));
12653 }
12655 }
12661 /* Mark the jump as very likely to be taken. */
12666 {
12669 }
12672 /* Get more stack space. We pass in the desired stack space and the
12673 size of the arguments to copy to the new stack. In 32-bit mode
12674 we push the parameters; __morestack will return on a new stack
12675 anyhow. In 64-bit mode we pass the parameters in r10 and
12676 r11. */
12681 {
12687 /* If this function uses a static chain, it will be in %r10.
12688 Preserve it across the call to __morestack. */
12690 {
12691 rtx rax;
12696 }
12700 {
12701 HOST_WIDE_INT argval;
12704 /* When using the large model we need to load the address
12705 into a register, and we've run out of registers. So we
12706 switch to a different calling convention, and we call a
12707 different function: __morestack_large. We pass the
12708 argument size in the upper 32 bits of r10 and pass the
12709 frame size in the lower 32 bits. */
12714 {
12715 split_stack_fn_large =
12718 }
12720 {
12722 rtx x;
12731 UNSPEC_GOT);
12737 }
12738 else
12745 }
12746 else
12747 {
12751 }
12754 }
12755 else
12756 {
12759 }
12765 /* In order to make call/return prediction work right, we now need
12766 to execute a return instruction. See
12767 libgcc/config/i386/morestack.S for the details on how this works.
12769 For flow purposes gcc must not see this as a return
12770 instruction--we need control flow to continue at the subsequent
12771 label. Therefore, we use an unspec. */
12775 /* If we are in 64-bit mode and this function uses a static chain,
12776 we saved %r10 in %rax before calling _morestack. */
12781 /* If this function calls va_start, we need to store a pointer to
12782 the arguments on the old stack, because they may not have been
12783 all copied to the new stack. At this point the old stack can be
12784 found at the frame pointer value used by __morestack, because
12785 __morestack has set that up before calling back to us. Here we
12786 store that pointer in a scratch register, and in
12787 ix86_expand_prologue we store the scratch register in a stack
12788 slot. */
12790 {
12792 rtx frame_reg;
12799 /* 64-bit:
12800 fp -> old fp value
12801 return address within this function
12802 return address of caller of this function
12803 stack arguments
12804 So we add three words to get to the stack arguments.
12806 32-bit:
12807 fp -> old fp value
12808 return address within this function
12809 first argument to __morestack
12810 second argument to __morestack
12811 return address of caller of this function
12812 stack arguments
12813 So we add five words to get to the stack arguments.
12814 */
12825 }
12830 /* If this function calls va_start, we now have to set the scratch
12831 register for the case where we do not call __morestack. In this
12832 case we need to set it based on the stack pointer. */
12834 {
12841 }
12842 }
12844 /* We may have to tell the dataflow pass that the split stack prologue
12845 is initializing a scratch register. */
12847 static void
12849 {
12851 {
12854 }
12855 }
12856 \f
12857 /* Extract the parts of an RTL expression that is a valid memory address
12858 for an instruction. Return 0 if the structure of the address is
12859 grossly off. Return -1 if the address contains ASHIFT, so it is not
12860 strictly valid, but still used for computing length of lea instruction. */
12862 int
12864 {
12869 rtx tmp;
12873 /* Allow zero-extended SImode addresses,
12874 they will be emitted with addr32 prefix. */
12876 {
12879 {
12883 }
12886 {
12893 }
12894 }
12896 /* Allow SImode subregs of DImode addresses,
12897 they will be emitted with addr32 prefix. */
12899 {
12902 {
12906 }
12907 }
12912 {
12915 else
12917 }
12919 {
12924 do
12925 {
12930 }
12937 {
12940 {
12965 /* FALLTHRU */
12969 && TARGET_TLS_DIRECT_SEG_REFS
12972 else
12979 /* FALLTHRU */
12986 else
13001 }
13002 }
13003 }
13005 {
13008 }
13010 {
13011 /* We're called for lea too, which implements ashift on occasion. */
13021 }
13022 else
13026 {
13028 ;
13031 ;
13032 else
13034 }
13036 /* Extract the integral value of scale. */
13038 {
13042 }
13047 /* Avoid useless 0 displacement. */
13051 /* Allow arg pointer and stack pointer as index if there is not scaling. */
13056 {
13059 }
13061 /* Special case: %ebp cannot be encoded as a base without a displacement.
13062 Similarly %r13. */
13064 && base_reg
13073 /* Special case: on K6, [%esi] makes the instruction vector decoded.
13074 Avoid this by transforming to [%esi+0].
13075 Reload calls address legitimization without cfun defined, so we need
13076 to test cfun for being non-NULL. */
13082 /* Special case: encode reg+reg instead of reg*2. */
13086 /* Special case: scaling cannot be encoded without base or displacement. */
13097 }
13098 \f
13099 /* Return cost of the memory address x.
13100 For i386, it is better to use a complex address than let gcc copy
13101 the address into a reg and make a new pseudo. But not if the address
13102 requires to two regs - that would mean more pseudos with longer
13103 lifetimes. */
13104 static int
13106 {
13118 /* Attempt to minimize number of registers in the address by increasing
13119 address cost for each used register. We don't increase address cost
13120 for "pic_offset_table_rtx". When a memopt with "pic_offset_table_rtx"
13121 is not invariant itself it most likely means that base or index is not
13122 invariant. Therefore only "pic_offset_table_rtx" could be hoisted out,
13123 which is not profitable for x86. */
13127 || !pic_offset_table_rtx
13130 cost++;
13135 || !pic_offset_table_rtx
13138 cost++;
13140 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
13141 since it's predecode logic can't detect the length of instructions
13142 and it degenerates to vector decoded. Increase cost of such
13143 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
13144 to split such addresses or even refuse such addresses at all.
13146 Following addressing modes are affected:
13147 [base+scale*index]
13148 [scale*index+disp]
13149 [base+index]
13151 The first and last case may be avoidable by explicitly coding the zero in
13152 memory address, but I don't have AMD-K6 machine handy to check this
13153 theory. */
13162 }
13163 \f
13164 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
13165 this is used for to form addresses to local data when -fPIC is in
13166 use. */
13168 static bool
13170 {
13173 }
13175 /* Determine if a given RTX is a valid constant. We already know this
13176 satisfies CONSTANT_P. */
13178 static bool
13180 {
13181 /* Pointer bounds constants are not valid. */
13186 {
13191 {
13195 }
13200 /* Only some unspecs are valid as "constants". */
13203 {
13219 }
13221 /* We must have drilled down to a symbol. */
13226 /* FALLTHRU */
13229 /* TLS symbols are never valid. */
13233 /* DLLIMPORT symbols are never valid. */
13238 #if TARGET_MACHO
13239 /* mdynamic-no-pic */
13242 #endif
13256 }
13258 /* Otherwise we handle everything else in the move patterns. */
13260 }
13262 /* Determine if it's legal to put X into the constant pool. This
13263 is not possible for the address of thread-local symbols, which
13264 is checked above. */
13266 static bool
13268 {
13269 /* We can always put integral constants and vectors in memory. */
13271 {
13280 }
13282 }
13284 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
13285 otherwise zero. */
13287 static bool
13289 {
13295 }
13298 /* Nonzero if the constant value X is a legitimate general operand
13299 when generating PIC code. It is given that flag_pic is on and
13300 that X satisfies CONSTANT_P. */
13302 bool
13304 {
13305 rtx inner;
13308 {
13315 /* Only some unspecs are valid as "constants". */
13318 {
13331 }
13332 /* FALLTHRU */
13340 }
13341 }
13343 /* Determine if a given CONST RTX is a valid memory displacement
13344 in PIC mode. */
13346 bool
13348 {
13351 /* In 64bit mode we can allow direct addresses of symbols and labels
13352 when they are not dynamic symbols. */
13354 {
13358 {
13382 /* FALLTHRU */
13385 /* TLS references should always be enclosed in UNSPEC.
13386 The dllimported symbol needs always to be resolved. */
13392 {
13400 /* Function-symbols need to be resolved only for
13401 large-model.
13402 For the small-model we don't need to resolve anything
13403 here. */
13408 /* Non-external symbols don't need to be resolved for
13409 large, and medium-model. */
13414 }
13417 || (HAVE_LD_PIE_COPYRELOC
13418 && flag_pie
13427 }
13428 }
13434 {
13435 /* We are unsafe to allow PLUS expressions. This limit allowed distance
13436 of GOT tables. We should not need these anyway. */
13448 }
13452 {
13457 }
13466 {
13470 /* We need to check for both symbols and labels because VxWorks loads
13471 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
13472 details. */
13476 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
13477 While ABI specify also 32bit relocation but we don't produce it in
13478 small PIC model at all. */
13500 }
13503 }
13505 /* Determine if op is suitable RTX for an address register.
13506 Return naked register if a register or a register subreg is
13507 found, otherwise return NULL_RTX. */
13509 static rtx
13511 {
13514 /* Only SImode or DImode registers can form the address. */
13521 {
13529 /* Don't allow SUBREGs that span more than a word. It can
13530 lead to spill failures when the register is one word out
13531 of a two word structure. */
13535 /* Allow only SUBREGs of non-eliminable hard registers. */
13538 }
13540 /* Op is not a register. */
13542 }
13544 /* Recognizes RTL expressions that are valid memory addresses for an
13545 instruction. The MODE argument is the machine mode for the MEM
13546 expression that wants to use this address.
13548 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
13549 convert common non-canonical forms to canonical form so that they will
13550 be recognized. */
13552 static bool
13554 {
13557 HOST_WIDE_INT scale;
13561 /* Decomposition failed. */
13570 /* Validate base register. */
13572 {
13580 /* Base is not valid. */
13582 }
13584 /* Validate index register. */
13586 {
13594 /* Index is not valid. */
13596 }
13598 /* Index and base should have the same mode. */
13603 /* Address override works only on the (%reg) part of %fs:(%reg). */
13609 /* Validate scale factor. */
13611 {
13613 /* Scale without index. */
13617 /* Scale is not a valid multiplier. */
13619 }
13621 /* Validate displacement. */
13623 {
13628 {
13629 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
13630 used. While ABI specify also 32bit relocations, we don't produce
13631 them at all and use IP relative instead. */
13638 /* 64bit address unspec. */
13658 /* Invalid address unspec. */
13660 }
13663 && (flag_pic
13664 || (TARGET_MACHO
13665 #if TARGET_MACHO
13666 && MACHOPIC_INDIRECT
13668 #endif
13669 )))
13670 {
13672 is_legitimate_pic:
13674 {
13675 /* foo@dtpoff(%rX) is ok. */
13682 /* Non-constant pic memory reference. */
13684 }
13687 /* Displacement is an invalid pic construct. */
13689 #if TARGET_MACHO
13692 /* displacment must be referenced via non_lazy_pointer */
13694 #endif
13696 /* This code used to verify that a symbolic pic displacement
13697 includes the pic_offset_table_rtx register.
13699 While this is good idea, unfortunately these constructs may
13700 be created by "adds using lea" optimization for incorrect
13701 code like:
13703 int a;
13704 int foo(int i)
13705 {
13706 return *(&a+i);
13707 }
13709 This code is nonsensical, but results in addressing
13710 GOT table with pic_offset_table_rtx base. We can't
13711 just refuse it easily, since it gets matched by
13712 "addsi3" pattern, that later gets split to lea in the
13713 case output register differs from input. While this
13714 can be handled by separate addsi pattern for this case
13715 that never results in lea, this seems to be easier and
13716 correct fix for crash to disable this test. */
13717 }
13724 /* Displacement is not constant. */
13728 /* Displacement is out of range. */
13730 /* In x32 mode, constant addresses are sign extended to 64bit, so
13731 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13736 }
13738 /* Everything looks valid. */
13740 }
13742 /* Determine if a given RTX is a valid constant address. */
13744 bool
13746 {
13748 }
13749 \f
13750 /* Return a unique alias set for the GOT. */
13752 static alias_set_type
13754 {
13759 }
13761 /* Return a legitimate reference for ORIG (an address) using the
13762 register REG. If REG is 0, a new pseudo is generated.
13764 There are two types of references that must be handled:
13766 1. Global data references must load the address from the GOT, via
13767 the PIC reg. An insn is emitted to do this load, and the reg is
13768 returned.
13770 2. Static data references, constant pool addresses, and code labels
13771 compute the address as an offset from the GOT, whose base is in
13772 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13773 differentiate them from global data objects. The returned
13774 address is the PIC reg + an unspec constant.
13776 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13777 reg also appears in the address. */
13779 static rtx
13781 {
13785 #if TARGET_MACHO
13787 {
13790 /* Use the generic Mach-O PIC machinery. */
13792 }
13793 #endif
13796 {
13800 }
13806 {
13807 rtx tmpreg;
13808 /* This symbol may be referenced via a displacement from the PIC
13809 base address (@GOTOFF). */
13814 {
13816 UNSPEC_GOTOFF);
13818 }
13819 else
13824 else
13829 {
13833 }
13834 else
13836 }
13838 {
13839 /* This symbol may be referenced via a displacement from the PIC
13840 base address (@GOTOFF). */
13845 {
13847 UNSPEC_GOTOFF);
13849 }
13850 else
13856 {
13859 }
13860 }
13862 /* We can't use @GOTOFF for text labels on VxWorks;
13863 see gotoff_operand. */
13865 {
13870 /* For x64 PE-COFF there is no GOT table. So we use address
13871 directly. */
13873 {
13881 }
13883 {
13891 /* Use directly gen_movsi, otherwise the address is loaded
13892 into register for CSE. We don't want to CSE this addresses,
13893 instead we CSE addresses from the GOT table, so skip this. */
13896 }
13897 else
13898 {
13899 /* This symbol must be referenced via a load from the
13900 Global Offset Table (@GOT). */
13914 }
13915 }
13916 else
13917 {
13920 {
13922 {
13925 }
13926 else
13928 }
13930 {
13933 /* We must match stuff we generate before. Assume the only
13934 unspecs that can get here are ours. Not that we could do
13935 anything with them anyway.... */
13941 }
13943 {
13946 /* Check first to see if this is a constant offset from a @GOTOFF
13947 symbol reference. */
13950 {
13952 {
13954 UNSPEC_GOTOFF);
13960 {
13963 }
13964 }
13965 else
13966 {
13969 {
13973 }
13974 }
13975 }
13976 else
13977 {
13980 new_rtx
13984 {
13987 {
13990 new_rtx
13992 }
13993 else
13995 }
13996 else
13997 {
13998 /* For %rip addressing, we have to use just disp32, not
13999 base nor index. */
14006 {
14009 }
14011 }
14012 }
14013 }
14014 }
14016 }
14017 \f
14018 /* Load the thread pointer. If TO_REG is true, force it into a register. */
14020 static rtx
14022 {
14026 {
14031 }
14037 }
14039 /* Construct the SYMBOL_REF for the tls_get_addr function. */
14043 static rtx
14045 {
14047 {
14053 }
14056 {
14058 UNSPEC_PLTOFF);
14061 }
14064 }
14066 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
14070 rtx
14072 {
14074 {
14075 ix86_tls_module_base_symbol
14080 }
14083 }
14085 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
14086 false if we expect this to be used for a memory address and true if
14087 we expect to load the address into a register. */
14089 static rtx
14091 {
14097 /* Fall back to global dynamic model if tool chain cannot support local
14098 dynamic. */
14105 {
14110 {
14113 else
14114 {
14117 }
14118 }
14121 {
14124 else
14134 }
14135 else
14136 {
14140 {
14145 emit_call_insn
14155 }
14156 else
14158 }
14165 {
14168 else
14169 {
14172 }
14173 }
14176 {
14181 else
14187 }
14188 else
14189 {
14193 {
14196 rtx eqv;
14199 emit_call_insn
14204 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
14205 share the LD_BASE result with other LD model accesses. */
14207 UNSPEC_TLS_LD_BASE);
14211 }
14212 else
14214 }
14222 {
14229 }
14234 {
14236 {
14237 /* The Sun linker took the AMD64 TLS spec literally
14238 and can only handle %rax as destination of the
14239 initial executable code sequence. */
14244 }
14246 /* Generate DImode references to avoid %fs:(%reg32)
14247 problems and linker IE->LE relaxation bug. */
14251 }
14253 {
14256 }
14258 {
14262 }
14263 else
14264 {
14267 }
14277 {
14282 }
14283 else
14284 {
14288 }
14298 {
14302 }
14303 else
14304 {
14308 }
14313 }
14316 }
14318 /* Create or return the unique __imp_DECL dllimport symbol corresponding
14319 to symbol DECL if BEIMPORT is true. Otherwise create or return the
14320 unique refptr-DECL symbol corresponding to symbol DECL. */
14323 {
14327 {
14329 }
14331 static int
14333 {
14335 }
14336 };
14340 static tree
14342 {
14348 tree to;
14349 rtx rtl;
14376 else
14389 {
14391 #ifdef SUB_TARGET_RECORD_STUB
14393 #endif
14394 }
14403 }
14405 /* Expand SYMBOL into its corresponding far-addresse symbol.
14406 WANT_REG is true if we require the result be a register. */
14408 static rtx
14410 {
14411 tree imp_decl;
14412 rtx x;
14421 }
14423 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
14424 true if we require the result be a register. */
14426 static rtx
14428 {
14429 tree imp_decl;
14430 rtx x;
14439 }
14441 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
14442 is true if we require the result be a register. */
14444 static rtx
14446 {
14451 {
14458 {
14461 }
14462 }
14478 {
14481 }
14483 }
14485 /* Try machine-dependent ways of modifying an illegitimate address
14486 to be legitimate. If we find one, return the new, valid address.
14487 This macro is used in only one place: `memory_address' in explow.c.
14489 OLDX is the address as it was before break_out_memory_refs was called.
14490 In some cases it is useful to look at this to decide what needs to be done.
14492 It is always safe for this macro to do nothing. It exists to recognize
14493 opportunities to optimize the output.
14495 For the 80386, we handle X+REG by loading X into a register R and
14496 using R+REG. R will go in a general reg and indexing will be used.
14497 However, if REG is a broken-out memory address or multiplication,
14498 nothing needs to be done because REG can certainly go in a general reg.
14500 When -fpic is used, special handling is needed for symbolic references.
14501 See comments by legitimize_pic_address in i386.c for details. */
14503 static rtx
14505 {
14516 {
14520 }
14523 {
14527 }
14532 #if TARGET_MACHO
14535 #endif
14537 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
14541 {
14546 }
14549 {
14550 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
14555 {
14561 }
14566 {
14572 }
14574 /* Put multiply first if it isn't already. */
14576 {
14579 }
14581 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
14582 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
14583 created by virtual register instantiation, register elimination, and
14584 similar optimizations. */
14586 {
14592 }
14594 /* Canonicalize
14595 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
14596 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
14601 {
14602 rtx constant;
14606 {
14609 }
14611 {
14614 }
14615 else
14619 {
14626 }
14627 }
14633 {
14636 }
14639 {
14642 }
14650 {
14653 }
14659 {
14663 {
14666 }
14670 }
14673 {
14677 {
14680 }
14684 }
14685 }
14688 }
14689 \f
14690 /* Print an integer constant expression in assembler syntax. Addition
14691 and subtraction are the only arithmetic that may appear in these
14692 expressions. FILE is the stdio stream to write to, X is the rtx, and
14693 CODE is the operand print code from the output string. */
14695 static void
14697 {
14701 {
14710 else
14711 {
14714 /* Mark the decl as referenced so that cgraph will
14715 output the function. */
14719 #if TARGET_MACHO
14723 #endif
14725 }
14733 /* FALLTHRU */
14744 /* This used to output parentheses around the expression,
14745 but that does not work on the 386 (either ATT or BSD assembler). */
14750 /* We can't handle floating point constants;
14751 TARGET_PRINT_OPERAND must handle them. */
14756 /* Some assemblers need integer constants to appear first. */
14758 {
14762 }
14763 else
14764 {
14769 }
14784 {
14788 }
14793 {
14812 /* FIXME: This might be @TPOFF in Sun ld too. */
14821 else
14831 else
14837 #if TARGET_MACHO
14842 #endif
14846 }
14851 }
14852 }
14854 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14855 We need to emit DTP-relative relocations. */
14857 static void ATTRIBUTE_UNUSED
14859 {
14864 {
14872 }
14873 }
14875 /* Return true if X is a representation of the PIC register. This copes
14876 with calls from ix86_find_base_term, where the register might have
14877 been replaced by a cselib value. */
14879 static bool
14881 {
14888 {
14896 }
14897 else
14899 }
14901 /* Helper function for ix86_delegitimize_address.
14902 Attempt to delegitimize TLS local-exec accesses. */
14904 static rtx
14906 {
14931 {
14936 }
14942 }
14944 /* In the name of slightly smaller debug output, and to cater to
14945 general assembler lossage, recognize PIC+GOTOFF and turn it back
14946 into a direct symbol reference.
14948 On Darwin, this is necessary to avoid a crash, because Darwin
14949 has a different PIC label for each routine but the DWARF debugging
14950 information is not associated with any particular routine, so it's
14951 necessary to remove references to the PIC label from RTL stored by
14952 the DWARF output code. */
14954 static rtx
14956 {
14958 /* addend is NULL or some rtx if x is something+GOTOFF where
14959 something doesn't include the PIC register. */
14961 /* reg_addend is NULL or a multiple of some register. */
14963 /* const_addend is NULL or a const_int. */
14965 /* This is the result, or NULL. */
14974 {
14981 {
14987 }
14994 {
14997 {
15002 }
15004 }
15009 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
15010 and -mcmodel=medium -fpic. */
15011 }
15018 /* %ebx + GOT/GOTOFF */
15019 ;
15021 {
15022 /* %ebx + %reg * scale + GOT/GOTOFF */
15028 else
15029 {
15032 }
15033 }
15034 else
15040 {
15043 }
15064 {
15065 /* If the rest of original X doesn't involve the PIC register, add
15066 addend and subtract pic_offset_table_rtx. This can happen e.g.
15067 for code like:
15068 leal (%ebx, %ecx, 4), %ecx
15069 ...
15070 movl foo@GOTOFF(%ecx), %edx
15071 in which case we return (%ecx - %ebx) + foo
15072 or (%ecx - _GLOBAL_OFFSET_TABLE_) + foo if pseudo_pic_reg
15073 and reload has completed. */
15077 pic_offset_table_rtx),
15078 result);
15080 {
15084 }
15085 else
15087 }
15089 {
15093 }
15095 }
15097 /* If X is a machine specific address (i.e. a symbol or label being
15098 referenced as a displacement from the GOT implemented using an
15099 UNSPEC), then return the base term. Otherwise return X. */
15101 rtx
15103 {
15104 rtx term;
15107 {
15120 }
15123 }
15124 \f
15125 static void
15128 {
15132 {
15135 }
15140 {
15143 {
15162 }
15166 {
15185 }
15192 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
15193 Those same assemblers have the same but opposite lossage on cmov. */
15196 else
15201 {
15214 }
15221 else
15226 {
15239 }
15246 else
15256 else
15267 }
15269 }
15271 /* Print the name of register X to FILE based on its machine mode and number.
15272 If CODE is 'w', pretend the mode is HImode.
15273 If CODE is 'b', pretend the mode is QImode.
15274 If CODE is 'k', pretend the mode is SImode.
15275 If CODE is 'q', pretend the mode is DImode.
15276 If CODE is 'x', pretend the mode is V4SFmode.
15277 If CODE is 't', pretend the mode is V8SFmode.
15278 If CODE is 'g', pretend the mode is V16SFmode.
15279 If CODE is 'h', pretend the reg is the 'high' byte register.
15280 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
15281 If CODE is 'd', duplicate the operand for AVX instruction.
15282 */
15284 void
15286 {
15296 {
15300 }
15303 {
15306 }
15324 else
15338 {
15346 normal:
15362 {
15367 }
15371 }
15375 /* Irritatingly, AMD extended registers use
15376 different naming convention: "r%d[bwd]" */
15378 {
15381 {
15395 /* no suffix */
15400 }
15402 }
15405 {
15408 else
15410 }
15411 }
15413 /* Meaning of CODE:
15414 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
15415 C -- print opcode suffix for set/cmov insn.
15416 c -- like C, but print reversed condition
15417 F,f -- likewise, but for floating-point.
15418 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
15419 otherwise nothing
15420 R -- print embeded rounding and sae.
15421 r -- print only sae.
15422 z -- print the opcode suffix for the size of the current operand.
15423 Z -- likewise, with special suffixes for x87 instructions.
15424 * -- print a star (in certain assembler syntax)
15425 A -- print an absolute memory reference.
15426 E -- print address with DImode register names if TARGET_64BIT.
15427 w -- print the operand as if it's a "word" (HImode) even if it isn't.
15428 s -- print a shift double count, followed by the assemblers argument
15429 delimiter.
15430 b -- print the QImode name of the register for the indicated operand.
15431 %b0 would print %al if operands[0] is reg 0.
15432 w -- likewise, print the HImode name of the register.
15433 k -- likewise, print the SImode name of the register.
15434 q -- likewise, print the DImode name of the register.
15435 x -- likewise, print the V4SFmode name of the register.
15436 t -- likewise, print the V8SFmode name of the register.
15437 g -- likewise, print the V16SFmode name of the register.
15438 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
15439 y -- print "st(0)" instead of "st" as a register.
15440 d -- print duplicated register operand for AVX instruction.
15441 D -- print condition for SSE cmp instruction.
15442 P -- if PIC, print an @PLT suffix.
15443 p -- print raw symbol name.
15444 X -- don't print any sort of PIC '@' suffix for a symbol.
15445 & -- print some in-use local-dynamic symbol name.
15446 H -- print a memory address offset by 8; used for sse high-parts
15447 Y -- print condition for XOP pcom* instruction.
15448 + -- print a branch hint as 'cs' or 'ds' prefix
15449 ; -- print a semicolon (after prefixes due to bug in older gas).
15450 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
15451 @ -- print a segment register of thread base pointer load
15452 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
15453 ! -- print MPX prefix for jxx/call/ret instructions if required.
15454 */
15456 void
15458 {
15460 {
15462 {
15465 {
15471 /* Intel syntax. For absolute addresses, registers should not
15472 be surrounded by braces. */
15474 {
15479 }
15484 }
15490 /* Wrap address in an UNSPEC to declare special handling. */
15528 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15533 {
15547 output_operand_lossage
15550 }
15553 #endif
15558 {
15559 /* Opcodes don't get size suffixes if using Intel opcodes. */
15564 {
15582 output_operand_lossage
15585 }
15586 }
15589 warning
15591 /* FALLTHRU */
15594 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
15599 {
15601 {
15603 #ifdef HAVE_AS_IX86_FILDS
15605 #endif
15613 #ifdef HAVE_AS_IX86_FILDQ
15615 #else
15617 #endif
15622 }
15623 }
15625 {
15626 /* 387 opcodes don't get size suffixes
15627 if the operands are registers. */
15632 {
15648 }
15649 }
15650 else
15651 {
15652 output_operand_lossage
15655 }
15657 output_operand_lossage
15678 {
15681 }
15686 {
15737 }
15741 /* Little bit of braindamage here. The SSE compare instructions
15742 does use completely different names for the comparisons that the
15743 fp conditional moves. */
15745 {
15748 {
15751 }
15757 {
15760 }
15766 {
15769 }
15778 {
15781 }
15787 {
15790 }
15796 {
15799 }
15810 }
15815 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15818 #endif
15823 {
15827 }
15831 file);
15836 {
15840 }
15841 /* It doesn't actually matter what mode we use here, as we're
15842 only going to use this for printing. */
15844 /* Output 'qword ptr' for intel assembler dialect. */
15853 #ifdef HAVE_AS_IX86_HLE
15855 #else
15857 #endif
15859 #ifdef HAVE_AS_IX86_HLE
15861 #else
15863 #endif
15864 /* We do not want to print value of the operand. */
15893 {
15908 }
15921 {
15926 else
15929 }
15932 {
15933 rtx x;
15942 {
15947 {
15949 bool cputaken
15952 /* Emit hints only in the case default branch prediction
15953 heuristics would fail. */
15955 {
15956 /* We use 3e (DS) prefix for taken branches and
15957 2e (CS) prefix for not taken branches. */
15960 else
15962 }
15963 }
15964 }
15966 }
15969 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15971 #endif
15978 /* The kernel uses a different segment register for performance
15979 reasons; a system call would not have to trash the userspace
15980 segment register, which would be expensive. */
15983 else
16003 }
16004 }
16010 {
16011 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
16014 {
16017 {
16026 else
16033 }
16035 /* Check for explicit size override (codes 'b', 'w', 'k',
16036 'q' and 'x') */
16050 }
16053 /* Avoid (%rip) for call operands. */
16059 else
16061 }
16064 {
16065 REAL_VALUE_TYPE r;
16073 /* Sign extend 32bit SFmode immediate to 8 bytes. */
16077 else
16079 }
16082 {
16083 REAL_VALUE_TYPE r;
16092 }
16094 /* These float cases don't actually occur as immediate operands. */
16096 {
16101 }
16103 else
16104 {
16105 /* We have patterns that allow zero sets of memory, for instance.
16106 In 64-bit mode, we should probably support all 8-byte vectors,
16107 since we can in fact encode that into an immediate. */
16109 {
16112 }
16115 {
16117 {
16120 }
16123 {
16126 else
16128 }
16129 }
16134 else
16136 }
16137 }
16139 static bool
16141 {
16144 }
16145 \f
16146 /* Print a memory operand whose address is ADDR. */
16148 static void
16150 {
16159 {
16166 }
16168 {
16172 }
16174 {
16178 {
16181 }
16184 }
16186 {
16191 }
16192 else
16203 {
16214 }
16216 /* Use one byte shorter RIP relative addressing for 64bit mode. */
16218 {
16230 }
16232 {
16233 /* Displacement only requires special attention. */
16236 {
16240 }
16243 else
16245 }
16246 else
16247 {
16248 /* Print SImode register names to force addr32 prefix. */
16250 {
16251 #ifdef ENABLE_CHECKING
16254 {
16265 }
16266 #endif
16269 }
16271 && TARGET_X32
16272 && disp
16275 {
16276 /* X32 runs in 64-bit mode, where displacement, DISP, in
16277 address DISP(%r64), is encoded as 32-bit immediate sign-
16278 extended from 32-bit to 64-bit. For -0x40000300(%r64),
16279 address is %r64 + 0xffffffffbffffd00. When %r64 <
16280 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
16281 which is invalid for x32. The correct address is %r64
16282 - 0x40000300 == 0xf7ffdd64. To properly encode
16283 -0x40000300(%r64) for x32, we zero-extend negative
16284 displacement by forcing addr32 prefix which truncates
16285 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
16286 zero-extend all negative displacements, including -1(%rsp).
16287 However, for small negative displacements, sign-extension
16288 won't cause overflow. We only zero-extend negative
16289 displacements if they < -16*1024*1024, which is also used
16290 to check legitimate address displacements for PIC. */
16292 }
16295 {
16297 {
16302 else
16304 }
16310 {
16315 }
16317 }
16318 else
16319 {
16323 {
16324 /* Pull out the offset of a symbol; print any symbol itself. */
16328 {
16332 }
16340 else
16342 }
16346 {
16349 {
16353 }
16354 }
16357 else
16361 {
16366 }
16368 }
16369 }
16370 }
16372 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
16374 static bool
16376 {
16377 rtx op;
16384 {
16387 /* FIXME: This might be @TPOFF in Sun ld. */
16398 else
16410 else
16417 #if TARGET_MACHO
16423 #endif
16426 {
16431 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
16433 #else
16435 #endif
16438 }
16443 }
16446 }
16447 \f
16448 /* Split one or more double-mode RTL references into pairs of half-mode
16449 references. The RTL can be REG, offsettable MEM, integer constant, or
16450 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
16451 split and "num" is its length. lo_half and hi_half are output arrays
16452 that parallel "operands". */
16454 void
16457 {
16458 machine_mode half_mode;
16462 {
16471 }
16476 {
16479 /* simplify_subreg refuse to split volatile memory addresses,
16480 but we still have to handle it. */
16482 {
16485 }
16486 else
16487 {
16494 }
16495 }
16496 }
16497 \f
16498 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
16499 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
16500 is the expression of the binary operation. The output may either be
16501 emitted here, or returned to the caller, like all output_* functions.
16503 There is no guarantee that the operands are the same mode, as they
16504 might be within FLOAT or FLOAT_EXTEND expressions. */
16506 #ifndef SYSV386_COMPAT
16507 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
16508 wants to fix the assemblers because that causes incompatibility
16509 with gcc. No-one wants to fix gcc because that causes
16510 incompatibility with assemblers... You can use the option of
16511 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
16512 #define SYSV386_COMPAT 1
16513 #endif
16517 {
16523 #ifdef ENABLE_CHECKING
16524 /* Even if we do not want to check the inputs, this documents input
16525 constraints. Which helps in understanding the following code. */
16535 else
16537 #endif
16540 {
16545 else
16554 else
16563 else
16572 else
16579 }
16582 {
16584 {
16588 else
16590 }
16591 else
16592 {
16596 else
16598 }
16600 }
16604 {
16610 /* know operands[0] == operands[1]. */
16613 {
16616 }
16619 {
16621 /* How is it that we are storing to a dead operand[2]?
16622 Well, presumably operands[1] is dead too. We can't
16623 store the result to st(0) as st(0) gets popped on this
16624 instruction. Instead store to operands[2] (which I
16625 think has to be st(1)). st(1) will be popped later.
16626 gcc <= 2.8.1 didn't have this check and generated
16627 assembly code that the Unixware assembler rejected. */
16629 else
16632 }
16636 else
16643 {
16646 }
16649 {
16652 }
16655 {
16656 #if SYSV386_COMPAT
16657 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
16658 derived assemblers, confusingly reverse the direction of
16659 the operation for fsub{r} and fdiv{r} when the
16660 destination register is not st(0). The Intel assembler
16661 doesn't have this brain damage. Read !SYSV386_COMPAT to
16662 figure out what the hardware really does. */
16665 else
16667 #else
16669 /* As above for fmul/fadd, we can't store to st(0). */
16671 else
16673 #endif
16675 }
16678 {
16679 #if SYSV386_COMPAT
16682 else
16684 #else
16687 else
16689 #endif
16691 }
16694 {
16697 else
16700 }
16702 {
16703 #if SYSV386_COMPAT
16705 #else
16707 #endif
16708 }
16709 else
16710 {
16711 #if SYSV386_COMPAT
16713 #else
16715 #endif
16716 }
16721 }
16725 }
16727 /* Check if a 256bit AVX register is referenced inside of EXP. */
16729 static bool
16731 {
16737 }
16739 /* Return needed mode for entity in optimize_mode_switching pass. */
16741 static int
16743 {
16745 {
16746 rtx link;
16748 /* Needed mode is set to AVX_U128_CLEAN if there are
16749 no 256bit modes used in function arguments. */
16751 link;
16753 {
16755 {
16760 }
16761 }
16764 }
16766 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16767 changes state only when a 256bit register is written to, but we need
16768 to prevent the compiler from moving optimal insertion point above
16769 eventual read from 256bit register. */
16776 }
16778 /* Return mode that i387 must be switched into
16779 prior to the execution of insn. */
16781 static int
16783 {
16786 /* The mode UNINITIALIZED is used to store control word after a
16787 function call or ASM pattern. The mode ANY specify that function
16788 has no requirements on the control word and make no changes in the
16789 bits we are interested in. */
16803 {
16826 }
16829 }
16831 /* Return mode that entity must be switched into
16832 prior to the execution of insn. */
16834 static int
16836 {
16838 {
16848 }
16850 }
16852 /* Check if a 256bit AVX register is referenced in stores. */
16854 static void
16856 {
16858 {
16861 }
16862 }
16864 /* Calculate mode of upper 128bit AVX registers after the insn. */
16866 static int
16868 {
16875 /* We know that state is clean after CALL insn if there are no
16876 256bit registers used in the function return register. */
16878 {
16883 }
16885 /* Otherwise, return current mode. Remember that if insn
16886 references AVX 256bit registers, the mode was already changed
16887 to DIRTY from MODE_NEEDED. */
16889 }
16891 /* Return the mode that an insn results in. */
16893 static int
16895 {
16897 {
16907 }
16908 }
16910 static int
16912 {
16913 tree arg;
16915 /* Entry mode is set to AVX_U128_DIRTY if there are
16916 256bit modes used in function arguments. */
16919 {
16924 }
16927 }
16929 /* Return a mode that ENTITY is assumed to be
16930 switched to at function entry. */
16932 static int
16934 {
16936 {
16946 }
16947 }
16949 static int
16951 {
16954 /* Exit mode is set to AVX_U128_DIRTY if there are
16955 256bit modes used in the function return register. */
16960 }
16962 /* Return a mode that ENTITY is assumed to be
16963 switched to at function exit. */
16965 static int
16967 {
16969 {
16979 }
16980 }
16982 static int
16984 {
16986 }
16988 /* Output code to initialize control word copies used by trunc?f?i and
16989 rounding patterns. CURRENT_MODE is set to current control word,
16990 while NEW_MODE is set to new control word. */
16992 static void
16994 {
16996 rtx new_mode;
17007 {
17009 {
17011 /* round toward zero (truncate) */
17017 /* round down toward -oo */
17024 /* round up toward +oo */
17031 /* mask precision exception for nearbyint() */
17038 }
17039 }
17040 else
17041 {
17043 {
17045 /* round toward zero (truncate) */
17051 /* round down toward -oo */
17057 /* round up toward +oo */
17063 /* mask precision exception for nearbyint() */
17070 }
17071 }
17077 }
17079 /* Emit vzeroupper. */
17081 void
17083 {
17086 /* Cancel automatic vzeroupper insertion if there are
17087 live call-saved SSE registers at the insertion point. */
17099 }
17101 /* Generate one or more insns to set ENTITY to MODE. */
17103 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
17104 is the set of hard registers live at the point where the insn(s)
17105 are to be inserted. */
17107 static void
17109 HARD_REG_SET regs_live)
17110 {
17112 {
17127 }
17128 }
17130 /* Output code for INSN to convert a float to a signed int. OPERANDS
17131 are the insn operands. The output may be [HSD]Imode and the input
17132 operand may be [SDX]Fmode. */
17136 {
17141 /* Jump through a hoop or two for DImode, since the hardware has no
17142 non-popping instruction. We used to do this a different way, but
17143 that was somewhat fragile and broke with post-reload splitters. */
17153 else
17154 {
17159 else
17163 }
17166 }
17168 /* Output code for x87 ffreep insn. The OPNO argument, which may only
17169 have the values zero or one, indicates the ffreep insn's operand
17170 from the OPERANDS array. */
17174 {
17176 #ifdef HAVE_AS_IX86_FFREEP
17178 #else
17179 {
17189 }
17190 #endif
17193 }
17196 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
17197 should be used. UNORDERED_P is true when fucom should be used. */
17201 {
17207 {
17210 }
17211 else
17212 {
17215 }
17218 {
17222 else
17224 else
17227 else
17229 }
17236 {
17238 {
17241 }
17242 else
17244 }
17247 && stack_top_dies
17250 {
17251 /* If both the top of the 387 stack dies, and the other operand
17252 is also a stack register that dies, then this must be a
17253 `fcompp' float compare */
17256 {
17257 /* There is no double popping fcomi variant. Fortunately,
17258 eflags is immune from the fstp's cc clobbering. */
17261 else
17264 }
17265 else
17266 {
17269 else
17271 }
17272 }
17273 else
17274 {
17275 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
17278 {
17286 NULL,
17287 NULL,
17294 NULL,
17295 NULL,
17296 NULL,
17297 NULL
17298 };
17313 }
17314 }
17316 void
17318 {
17321 #ifdef ASM_QUAD
17324 #else
17326 #endif
17329 }
17331 void
17333 {
17336 #ifdef ASM_QUAD
17339 #else
17341 #endif
17342 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
17348 #if TARGET_MACHO
17350 {
17354 }
17355 #endif
17356 else
17359 }
17360 \f
17361 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
17362 for the target. */
17364 void
17366 {
17367 rtx tmp;
17369 /* We play register width games, which are only valid after reload. */
17372 /* Avoid HImode and its attendant prefix byte. */
17378 {
17381 }
17384 }
17386 /* X is an unchanging MEM. If it is a constant pool reference, return
17387 the constant pool rtx, else NULL. */
17389 rtx
17391 {
17398 }
17400 void
17402 {
17410 {
17411 rtx tmp;
17415 {
17421 }
17424 }
17428 {
17431 rtx tmp;
17436 else
17440 {
17447 }
17448 }
17452 {
17454 {
17455 #if TARGET_MACHO
17456 /* dynamic-no-pic */
17458 {
17465 }
17467 {
17471 }
17474 else
17475 {
17483 }
17484 /* dynamic-no-pic */
17485 #endif
17486 }
17487 else
17488 {
17492 {
17498 }
17499 }
17500 }
17501 else
17502 {
17513 /* Force large constants in 64bit compilation into register
17514 to get them CSEed. */
17525 {
17526 /* If we are loading a floating point constant to a register,
17527 force the value to memory now, since we'll get better code
17528 out the back end. */
17532 {
17537 }
17538 }
17539 }
17542 }
17544 void
17546 {
17553 /* Force constants other than zero into memory. We do not know how
17554 the instructions used to build constants modify the upper 64 bits
17555 of the register, once we have that information we may be able
17556 to handle some of them more efficiently. */
17565 /* We need to check memory alignment for SSE mode since attribute
17566 can make operands unaligned. */
17571 {
17574 /* ix86_expand_vector_move_misalign() does not like constants ... */
17580 /* ... nor both arguments in memory. */
17588 }
17590 /* Make operand1 a register if it isn't already. */
17594 {
17597 }
17600 }
17602 /* Split 32-byte AVX unaligned load and store if needed. */
17604 static void
17606 {
17607 rtx m;
17611 machine_mode mode;
17614 {
17635 }
17638 {
17641 {
17648 }
17649 /* Normal *mov<mode>_internal pattern will handle
17650 unaligned loads just fine if misaligned_operand
17651 is true, and without the UNSPEC it can be combined
17652 with arithmetic instructions. */
17655 else
17657 }
17659 {
17662 {
17667 }
17668 else
17670 }
17671 else
17673 }
17675 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17676 straight to ix86_expand_vector_move. */
17677 /* Code generation for scalar reg-reg moves of single and double precision data:
17678 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17679 movaps reg, reg
17680 else
17681 movss reg, reg
17682 if (x86_sse_partial_reg_dependency == true)
17683 movapd reg, reg
17684 else
17685 movsd reg, reg
17687 Code generation for scalar loads of double precision data:
17688 if (x86_sse_split_regs == true)
17689 movlpd mem, reg (gas syntax)
17690 else
17691 movsd mem, reg
17693 Code generation for unaligned packed loads of single precision data
17694 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17695 if (x86_sse_unaligned_move_optimal)
17696 movups mem, reg
17698 if (x86_sse_partial_reg_dependency == true)
17699 {
17700 xorps reg, reg
17701 movlps mem, reg
17702 movhps mem+8, reg
17703 }
17704 else
17705 {
17706 movlps mem, reg
17707 movhps mem+8, reg
17708 }
17710 Code generation for unaligned packed loads of double precision data
17711 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17712 if (x86_sse_unaligned_move_optimal)
17713 movupd mem, reg
17715 if (x86_sse_split_regs == true)
17716 {
17717 movlpd mem, reg
17718 movhpd mem+8, reg
17719 }
17720 else
17721 {
17722 movsd mem, reg
17723 movhpd mem+8, reg
17724 }
17725 */
17727 void
17729 {
17738 {
17740 {
17744 {
17746 {
17749 }
17750 else
17752 }
17754 /* FALLTHRU */
17758 {
17773 }
17779 else
17787 }
17790 }
17794 {
17796 {
17800 {
17802 {
17805 }
17806 else
17808 }
17810 /* FALLTHRU */
17820 }
17823 }
17826 {
17827 /* Normal *mov<mode>_internal pattern will handle
17828 unaligned loads just fine if misaligned_operand
17829 is true, and without the UNSPEC it can be combined
17830 with arithmetic instructions. */
17836 /* ??? If we have typed data, then it would appear that using
17837 movdqu is the only way to get unaligned data loaded with
17838 integer type. */
17840 {
17842 {
17845 }
17847 /* We will eventually emit movups based on insn attributes. */
17851 }
17853 {
17854 rtx zero;
17857 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17858 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17860 {
17861 /* We will eventually emit movups based on insn attributes. */
17864 }
17866 /* When SSE registers are split into halves, we can avoid
17867 writing to the top half twice. */
17869 {
17872 }
17873 else
17874 {
17875 /* ??? Not sure about the best option for the Intel chips.
17876 The following would seem to satisfy; the register is
17877 entirely cleared, breaking the dependency chain. We
17878 then store to the upper half, with a dependency depth
17879 of one. A rumor has it that Intel recommends two movsd
17880 followed by an unpacklpd, but this is unconfirmed. And
17881 given that the dependency depth of the unpacklpd would
17882 still be one, I'm not sure why this would be better. */
17884 }
17890 }
17891 else
17892 {
17893 rtx t;
17896 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17897 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17899 {
17901 {
17904 }
17911 }
17915 else
17920 else
17929 }
17930 }
17932 {
17934 {
17937 /* We will eventually emit movups based on insn attributes. */
17939 }
17941 {
17943 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17944 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17946 /* We will eventually emit movups based on insn attributes. */
17948 else
17949 {
17954 }
17955 }
17956 else
17957 {
17962 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17963 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17965 {
17968 }
17969 else
17970 {
17975 }
17976 }
17977 }
17978 else
17980 }
17982 /* Helper function of ix86_fixup_binary_operands to canonicalize
17983 operand order. Returns true if the operands should be swapped. */
17985 static bool
17987 rtx operands[])
17988 {
17993 /* If the operation is not commutative, we can't do anything. */
17997 /* Highest priority is that src1 should match dst. */
18003 /* Next highest priority is that immediate constants come second. */
18009 /* Lowest priority is that memory references should come second. */
18016 }
18019 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
18020 destination to use for the operation. If different from the true
18021 destination in operands[0], a copy operation will be required. */
18023 rtx
18025 rtx operands[])
18026 {
18031 /* Canonicalize operand order. */
18033 {
18034 /* It is invalid to swap operands of different modes. */
18038 }
18040 /* Both source operands cannot be in memory. */
18042 {
18043 /* Optimization: Only read from memory once. */
18045 {
18048 }
18051 else
18053 }
18055 /* If the destination is memory, and we do not have matching source
18056 operands, do things in registers. */
18060 /* Source 1 cannot be a constant. */
18064 /* Source 1 cannot be a non-matching memory. */
18068 /* Improve address combine. */
18077 }
18079 /* Similarly, but assume that the destination has already been
18080 set up properly. */
18082 void
18085 {
18088 }
18090 /* Attempt to expand a binary operator. Make the expansion closer to the
18091 actual machine, then just general_operand, which will allow 3 separate
18092 memory references (one output, two input) in a single insn. */
18094 void
18096 rtx operands[])
18097 {
18104 /* Emit the instruction. */
18111 {
18112 /* This is going to be an LEA; avoid splitting it later. */
18114 }
18115 else
18116 {
18119 }
18121 /* Fix up the destination if needed. */
18124 }
18126 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
18127 the given OPERANDS. */
18129 void
18131 rtx operands[])
18132 {
18135 {
18138 }
18140 {
18143 }
18144 /* Optimize (__m128i) d | (__m128i) e and similar code
18145 when d and e are float vectors into float vector logical
18146 insn. In C/C++ without using intrinsics there is no other way
18147 to express vector logical operation on float vectors than
18148 to cast them temporarily to integer vectors. */
18150 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
18159 {
18160 rtx dst;
18162 {
18171 {
18174 }
18175 else
18176 {
18181 }
18192 }
18193 }
18202 }
18204 /* Return TRUE or FALSE depending on whether the binary operator meets the
18205 appropriate constraints. */
18207 bool
18210 {
18215 /* Both source operands cannot be in memory. */
18219 /* Canonicalize operand order for commutative operators. */
18223 /* If the destination is memory, we must have a matching source operand. */
18227 /* Source 1 cannot be a constant. */
18231 /* Source 1 cannot be a non-matching memory. */
18233 /* Support "andhi/andsi/anddi" as a zero-extending move. */
18241 }
18243 /* Attempt to expand a unary operator. Make the expansion closer to the
18244 actual machine, then just general_operand, which will allow 2 separate
18245 memory references (one output, one input) in a single insn. */
18247 void
18249 rtx operands[])
18250 {
18257 /* If the destination is memory, and we do not have matching source
18258 operands, do things in registers. */
18260 {
18263 else
18265 }
18267 /* When source operand is memory, destination must match. */
18271 /* Emit the instruction. */
18277 else
18278 {
18281 }
18283 /* Fix up the destination if needed. */
18286 }
18288 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
18289 divisor are within the range [0-255]. */
18291 void
18294 {
18303 {
18316 }
18323 /* Use 8bit unsigned divimod if dividend and divisor are within
18324 the range [0-255]. */
18333 pc_rtx);
18338 /* Generate original signed/unsigned divimod. */
18343 /* Branch to the end. */
18347 /* Generate 8bit unsigned divide. */
18349 /* Don't use operands[0] for result of 8bit divide since not all
18350 registers support QImode ZERO_EXTRACT. */
18357 {
18360 }
18361 else
18362 {
18365 }
18367 /* Extract remainder from AH. */
18371 else
18372 {
18373 /* Need a new scratch register since the old one has result
18374 of 8bit divide. */
18378 }
18381 /* Zero extend quotient from AL. */
18387 }
18389 #define LEA_MAX_STALL (3)
18390 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
18392 /* Increase given DISTANCE in half-cycles according to
18393 dependencies between PREV and NEXT instructions.
18394 Add 1 half-cycle if there is no dependency and
18395 go to next cycle if there is some dependecy. */
18397 static unsigned int
18399 {
18415 }
18417 /* Function checks if instruction INSN defines register number
18418 REGNO1 or REGNO2. */
18420 static bool
18423 {
18424 df_ref def;
18434 }
18436 /* Function checks if instruction INSN uses register number
18437 REGNO as a part of address expression. */
18439 static bool
18441 {
18442 df_ref use;
18449 }
18451 /* Search backward for non-agu definition of register number REGNO1
18452 or register number REGNO2 in basic block starting from instruction
18453 START up to head of basic block or instruction INSN.
18455 Function puts true value into *FOUND var if definition was found
18456 and false otherwise.
18458 Distance in half-cycles between START and found instruction or head
18459 of BB is added to DISTANCE and returned. */
18461 static int
18465 {
18475 {
18477 {
18480 {
18483 {
18486 }
18487 }
18490 }
18495 }
18498 }
18500 /* Search backward for non-agu definition of register number REGNO1
18501 or register number REGNO2 in INSN's basic block until
18502 1. Pass LEA_SEARCH_THRESHOLD instructions, or
18503 2. Reach neighbour BBs boundary, or
18504 3. Reach agu definition.
18505 Returns the distance between the non-agu definition point and INSN.
18506 If no definition point, returns -1. */
18508 static int
18511 {
18522 {
18523 edge e;
18524 edge_iterator ei;
18529 {
18532 }
18538 else
18539 {
18544 {
18545 int bb_dist
18551 {
18558 }
18559 }
18562 }
18563 }
18565 /* get_attr_type may modify recog data. We want to make sure
18566 that recog data is valid for instruction INSN, on which
18567 distance_non_agu_define is called. INSN is unchanged here. */
18574 }
18576 /* Return the distance in half-cycles between INSN and the next
18577 insn that uses register number REGNO in memory address added
18578 to DISTANCE. Return -1 if REGNO0 is set.
18580 Put true value into *FOUND if register usage was found and
18581 false otherwise.
18582 Put true value into *REDEFINED if register redefinition was
18583 found and false otherwise. */
18585 static int
18589 {
18598 {
18601 /* If insn and start belong to the same bb, set prev to insn,
18602 so the call to increase_distance will increase the distance
18603 between insns by 1. */
18605 }
18610 {
18612 {
18615 {
18616 /* Return DISTANCE if OP0 is used in memory
18617 address in NEXT. */
18620 }
18623 {
18624 /* Return -1 if OP0 is set in NEXT. */
18627 }
18630 }
18636 }
18639 }
18641 /* Return the distance between INSN and the next insn that uses
18642 register number REGNO0 in memory address. Return -1 if no such
18643 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18645 static int
18647 {
18659 {
18660 edge e;
18661 edge_iterator ei;
18666 {
18669 }
18675 else
18676 {
18682 {
18683 int bb_dist
18688 {
18695 }
18696 }
18699 }
18700 }
18706 }
18708 /* Define this macro to tune LEA priority vs ADD, it take effect when
18709 there is a dilemma of choicing LEA or ADD
18710 Negative value: ADD is more preferred than LEA
18711 Zero: Netrual
18712 Positive value: LEA is more preferred than ADD*/
18713 #define IX86_LEA_PRIORITY 0
18715 /* Return true if usage of lea INSN has performance advantage
18716 over a sequence of instructions. Instructions sequence has
18717 SPLIT_COST cycles higher latency than lea latency. */
18719 static bool
18722 {
18725 /* For Silvermont if using a 2-source or 3-source LEA for
18726 non-destructive destination purposes, or due to wanting
18727 ability to use SCALE, the use of LEA is justified. */
18729 {
18737 }
18743 {
18744 /* If there is no non AGU operand definition, no AGU
18745 operand usage and split cost is 0 then both lea
18746 and non lea variants have same priority. Currently
18747 we prefer lea for 64 bit code and non lea on 32 bit
18748 code. */
18751 else
18753 }
18755 /* With longer definitions distance lea is more preferable.
18756 Here we change it to take into account splitting cost and
18757 lea priority. */
18760 /* If there is no use in memory addess then we just check
18761 that split cost exceeds AGU stall. */
18765 /* If this insn has both backward non-agu dependence and forward
18766 agu dependence, the one with short distance takes effect. */
18768 }
18770 /* Return true if it is legal to clobber flags by INSN and
18771 false otherwise. */
18773 static bool
18775 {
18777 df_ref use;
18778 bitmap live;
18781 {
18783 {
18790 }
18796 }
18800 }
18802 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18803 move and add to avoid AGU stalls. */
18805 bool
18807 {
18810 /* Check if we need to optimize. */
18814 /* Check it is correct to split here. */
18822 /* We need to split only adds with non destructive
18823 destination operand. */
18826 else
18828 }
18830 /* Return true if we should emit lea instruction instead of mov
18831 instruction. */
18833 bool
18835 {
18838 /* Check if we need to optimize. */
18842 /* Use lea for reg to reg moves only. */
18850 }
18852 /* Return true if we need to split lea into a sequence of
18853 instructions to avoid AGU stalls. */
18855 bool
18857 {
18863 /* Check we need to optimize. */
18867 /* The "at least two components" test below might not catch simple
18868 move or zero extension insns if parts.base is non-NULL and parts.disp
18869 is const0_rtx as the only components in the address, e.g. if the
18870 register is %rbp or %r13. As this test is much cheaper and moves or
18871 zero extensions are the common case, do this check first. */
18877 /* Check if it is OK to split here. */
18884 /* There should be at least two components in the address. */
18889 /* We should not split into add if non legitimate pic
18890 operand is used as displacement. */
18905 /* Compute how many cycles we will add to execution time
18906 if split lea into a sequence of instructions. */
18908 {
18909 /* Have to use mov instruction if non desctructive
18910 destination form is used. */
18914 /* Have to add index to base if both exist. */
18918 /* Have to use shift and adds if scale is 2 or greater. */
18920 {
18925 else
18927 }
18929 /* Have to use add instruction with immediate if
18930 disp is non zero. */
18934 /* Subtract the price of lea. */
18936 }
18940 }
18942 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18943 matches destination. RTX includes clobber of FLAGS_REG. */
18945 static void
18948 {
18955 }
18957 /* Return true if regno1 def is nearest to the insn. */
18959 static bool
18961 {
18968 {
18970 {
18973 }
18979 }
18981 /* None of the regs is defined in the bb. */
18983 }
18985 /* Split lea instructions into a sequence of instructions
18986 which are executed on ALU to avoid AGU stalls.
18987 It is assumed that it is allowed to clobber flags register
18988 at lea position. */
18990 void
18992 {
19008 {
19011 }
19014 {
19017 }
19023 {
19024 /* Case r1 = r1 + ... */
19026 {
19027 /* If we have a case r1 = r1 + C * r2 then we
19028 should use multiplication which is very
19029 expensive. Assume cost model is wrong if we
19030 have such case here. */
19035 }
19036 else
19037 {
19038 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
19042 /* Use shift for scaling. */
19051 }
19052 }
19054 {
19057 }
19058 else
19059 {
19061 {
19064 }
19066 {
19069 }
19070 else
19071 {
19076 else
19077 {
19078 rtx tmp1;
19080 /* Find better operand for SET instruction, depending
19081 on which definition is farther from the insn. */
19084 else
19094 }
19097 }
19101 }
19102 }
19104 /* Return true if it is ok to optimize an ADD operation to LEA
19105 operation to avoid flag register consumation. For most processors,
19106 ADD is faster than LEA. For the processors like BONNELL, if the
19107 destination register of LEA holds an actual address which will be
19108 used soon, LEA is better and otherwise ADD is better. */
19110 bool
19112 {
19117 /* If a = b + c, (a!=b && a!=c), must use lea form. */
19125 }
19127 /* Return true if destination reg of SET_BODY is shift count of
19128 USE_BODY. */
19130 static bool
19132 {
19133 rtx set_dest;
19134 rtx shift_rtx;
19137 /* Retrieve destination of SET_BODY. */
19139 {
19148 use_body))
19153 }
19155 /* Retrieve shift count of USE_BODY. */
19157 {
19169 }
19177 {
19180 /* Return true if shift count is dest of SET_BODY. */
19182 {
19183 /* Add check since it can be invoked before register
19184 allocation in pre-reload schedule. */
19190 }
19191 }
19194 }
19196 /* Return true if destination reg of SET_INSN is shift count of
19197 USE_INSN. */
19199 bool
19201 {
19204 }
19206 /* Return TRUE or FALSE depending on whether the unary operator meets the
19207 appropriate constraints. */
19209 bool
19211 machine_mode,
19213 {
19214 /* If one of operands is memory, source and destination must match. */
19220 }
19222 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
19223 are ok, keeping in mind the possible movddup alternative. */
19225 bool
19227 {
19233 }
19235 /* Post-reload splitter for converting an SF or DFmode value in an
19236 SSE register into an unsigned SImode. */
19238 void
19240 {
19241 machine_mode vecmode;
19251 /* Load up the value into the low element. We must ensure that the other
19252 elements are valid floats -- zero is the easiest such value. */
19254 {
19257 else
19259 }
19260 else
19261 {
19266 else
19268 }
19288 else
19293 }
19295 /* Convert an unsigned DImode value into a DFmode, using only SSE.
19296 Expects the 64-bit DImode to be supplied in a pair of integral
19297 registers. Requires SSE2; will use SSE3 if available. For x86_32,
19298 -mfpmath=sse, !optimize_size only. */
19300 void
19302 {
19306 rtx x;
19312 {
19315 }
19316 else
19317 {
19321 }
19329 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
19332 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
19333 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
19334 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
19335 (0x1.0p84 + double(fp_value_hi_xmm)).
19336 Note these exponents differ by 32. */
19340 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
19341 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
19350 /* Add the upper and lower DFmode values together. */
19353 else
19354 {
19358 }
19361 }
19363 /* Not used, but eases macroization of patterns. */
19364 void
19366 {
19368 }
19370 /* Convert an unsigned SImode value into a DFmode. Only currently used
19371 for SSE, but applicable anywhere. */
19373 void
19375 {
19376 REAL_VALUE_TYPE TWO31r;
19391 }
19393 /* Convert a signed DImode value into a DFmode. Only used for SSE in
19394 32-bit mode; otherwise we have a direct convert instruction. */
19396 void
19398 {
19399 REAL_VALUE_TYPE TWO32r;
19417 }
19419 /* Convert an unsigned SImode value into a SFmode, using only SSE.
19420 For x86_32, -mfpmath=sse, !optimize_size only. */
19421 void
19423 {
19424 REAL_VALUE_TYPE ONE16r;
19443 }
19445 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
19446 a vector of unsigned ints VAL to vector of floats TARGET. */
19448 void
19450 {
19452 REAL_VALUE_TYPE TWO16r;
19459 else
19464 OPTAB_DIRECT);
19475 OPTAB_DIRECT);
19477 OPTAB_DIRECT);
19480 }
19482 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
19483 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
19484 This is done by doing just signed conversion if < 0x1p31, and otherwise by
19485 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
19487 rtx
19489 {
19490 REAL_VALUE_TYPE TWO31r;
19505 {
19511 }
19520 OPTAB_DIRECT);
19521 else
19522 {
19528 OPTAB_DIRECT);
19529 }
19532 }
19534 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
19535 then replicate the value for all elements of the vector
19536 register. */
19538 rtx
19540 {
19542 rtvec v;
19543 machine_mode scalar_mode;
19546 {
19579 }
19580 }
19582 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
19583 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
19584 for an SSE register. If VECT is true, then replicate the mask for
19585 all elements of the vector register. If INVERT is true, then create
19586 a mask excluding the sign bit. */
19588 rtx
19590 {
19592 wide_int w;
19596 {
19625 }
19633 /* Force this value into the low part of a fp vector constant. */
19642 }
19644 /* Generate code for floating point ABS or NEG. */
19646 void
19648 rtx operands[])
19649 {
19660 {
19666 }
19668 /* NEG and ABS performed with SSE use bitwise mask operations.
19669 Create the appropriate mask now. */
19672 else
19682 {
19684 rtvec par;
19689 else
19690 {
19693 }
19695 }
19696 else
19698 }
19700 /* Expand a copysign operation. Special case operand 0 being a constant. */
19702 void
19704 {
19718 else
19722 {
19729 {
19732 else
19733 {
19737 }
19738 }
19748 else
19752 }
19753 else
19754 {
19764 else
19768 }
19769 }
19771 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19772 be a constant, and so has already been expanded into a vector constant. */
19774 void
19776 {
19792 {
19795 }
19796 }
19798 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19799 so we have to do two masks. */
19801 void
19803 {
19818 {
19819 /* Shouldn't happen often (it's useless, obviously), but when it does
19820 we'd generate incorrect code if we continue below. */
19823 }
19826 {
19837 }
19838 else
19839 {
19841 {
19843 }
19845 {
19849 }
19853 {
19856 }
19858 {
19863 }
19865 }
19869 }
19871 /* Return TRUE or FALSE depending on whether the first SET in INSN
19872 has source and destination with matching CC modes, and that the
19873 CC mode is at least as constrained as REQ_MODE. */
19875 bool
19877 {
19878 rtx set;
19879 machine_mode set_mode;
19889 {
19899 /* FALLTHRU */
19903 /* FALLTHRU */
19907 /* FALLTHRU */
19922 }
19925 }
19927 /* Generate insn patterns to do an integer compare of OPERANDS. */
19929 static rtx
19931 {
19932 machine_mode cmpmode;
19938 /* This is very simple, but making the interface the same as in the
19939 FP case makes the rest of the code easier. */
19943 /* Return the test that should be put into the flags user, i.e.
19944 the bcc, scc, or cmov instruction. */
19946 }
19948 /* Figure out whether to use ordered or unordered fp comparisons.
19949 Return the appropriate mode to use. */
19951 machine_mode
19953 {
19954 /* ??? In order to make all comparisons reversible, we do all comparisons
19955 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19956 all forms trapping and nontrapping comparisons, we can make inequality
19957 comparisons trapping again, since it results in better code when using
19958 FCOM based compares. */
19960 }
19962 machine_mode
19964 {
19968 {
19971 }
19974 {
19975 /* Only zero flag is needed. */
19979 /* Codes needing carry flag. */
19982 /* Detect overflow checks. They need just the carry flag. */
19986 else
19991 /* Codes possibly doable only with sign flag when
19992 comparing against zero. */
19997 else
19998 /* For other cases Carry flag is not required. */
20000 /* Codes doable only with sign flag when comparing
20001 against zero, but we miss jump instruction for it
20002 so we need to use relational tests against overflow
20003 that thus needs to be zero. */
20008 else
20010 /* strcmp pattern do (use flags) and combine may ask us for proper
20011 mode. */
20016 }
20017 }
20019 /* Return the fixed registers used for condition codes. */
20021 static bool
20023 {
20027 }
20029 /* If two condition code modes are compatible, return a condition code
20030 mode which is compatible with both. Otherwise, return
20031 VOIDmode. */
20033 static machine_mode
20035 {
20052 {
20067 {
20082 }
20086 /* These are only compatible with themselves, which we already
20087 checked above. */
20089 }
20090 }
20093 /* Return a comparison we can do and that it is equivalent to
20094 swap_condition (code) apart possibly from orderedness.
20095 But, never change orderedness if TARGET_IEEE_FP, returning
20096 UNKNOWN in that case if necessary. */
20098 static enum rtx_code
20100 {
20102 {
20113 }
20114 }
20116 /* Return cost of comparison CODE using the best strategy for performance.
20117 All following functions do use number of instructions as a cost metrics.
20118 In future this should be tweaked to compute bytes for optimize_size and
20119 take into account performance of various instructions on various CPUs. */
20121 static int
20123 {
20126 /* The cost of code using bit-twiddling on %ah. */
20128 {
20151 }
20154 {
20161 }
20162 }
20164 /* Return strategy to use for floating-point. We assume that fcomi is always
20165 preferrable where available, since that is also true when looking at size
20166 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
20168 enum ix86_fpcmp_strategy
20170 {
20171 /* Do fcomi/sahf based test when profitable. */
20180 }
20182 /* Swap, force into registers, or otherwise massage the two operands
20183 to a fp comparison. The operands are updated in place; the new
20184 comparison code is returned. */
20186 static enum rtx_code
20188 {
20194 /* All of the unordered compare instructions only work on registers.
20195 The same is true of the fcomi compare instructions. The XFmode
20196 compare instructions require registers except when comparing
20197 against zero or when converting operand 1 from fixed point to
20198 floating point. */
20207 {
20210 }
20211 else
20212 {
20213 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
20214 things around if they appear profitable, otherwise force op0
20215 into a register. */
20221 {
20224 {
20227 }
20228 }
20234 {
20239 {
20242 }
20243 else
20245 }
20246 }
20248 /* Try to rearrange the comparison to make it cheaper. */
20252 {
20257 }
20262 }
20264 /* Convert comparison codes we use to represent FP comparison to integer
20265 code that will result in proper branch. Return UNKNOWN if no such code
20266 is available. */
20268 enum rtx_code
20270 {
20272 {
20295 }
20296 }
20298 /* Generate insn patterns to do a floating point compare of OPERANDS. */
20300 static rtx
20302 {
20309 /* Do fcomi/sahf based test when profitable. */
20311 {
20331 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
20338 /* In the unordered case, we have to check C2 for NaN's, which
20339 doesn't happen to work out to anything nice combination-wise.
20340 So do some bit twiddling on the value we've got in AH to come
20341 up with an appropriate set of condition codes. */
20345 {
20349 {
20352 }
20353 else
20354 {
20360 }
20365 {
20370 }
20371 else
20372 {
20375 }
20380 {
20383 }
20384 else
20385 {
20389 }
20394 {
20400 }
20401 else
20402 {
20405 }
20410 {
20415 }
20416 else
20417 {
20420 }
20425 {
20430 }
20431 else
20432 {
20435 }
20449 }
20454 }
20456 /* Return the test that should be put into the flags user, i.e.
20457 the bcc, scc, or cmov instruction. */
20460 const0_rtx);
20461 }
20463 static rtx
20465 {
20466 rtx ret;
20472 {
20475 }
20476 else
20480 }
20482 void
20484 {
20486 rtx tmp;
20489 {
20496 simple:
20500 pc_rtx);
20508 /* Expand DImode branch into multiple compare+branch. */
20509 {
20513 machine_mode submode;
20516 {
20519 }
20526 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
20527 avoid two branches. This costs one extra insn, so disable when
20528 optimizing for size. */
20533 {
20551 }
20553 /* Otherwise, if we are doing less-than or greater-or-equal-than,
20554 op1 is a constant and the low word is zero, then we can just
20555 examine the high word. Similarly for low word -1 and
20556 less-or-equal-than or greater-than. */
20560 {
20563 {
20566 }
20570 {
20573 }
20577 }
20579 /* Otherwise, we need two or three jumps. */
20588 {
20602 }
20604 /*
20605 * a < b =>
20606 * if (hi(a) < hi(b)) goto true;
20607 * if (hi(a) > hi(b)) goto false;
20608 * if (lo(a) < lo(b)) goto true;
20609 * false:
20610 */
20622 }
20627 }
20628 }
20630 /* Split branch based on floating point condition. */
20631 void
20634 {
20635 rtx condition;
20636 rtx i;
20639 {
20642 }
20645 tmp);
20653 }
20655 void
20657 {
20658 rtx ret;
20665 }
20667 /* Expand comparison setting or clearing carry flag. Return true when
20668 successful and set pop for the operation. */
20669 static bool
20671 {
20672 machine_mode mode =
20675 /* Do not handle double-mode compares that go through special path. */
20680 {
20681 rtx compare_op;
20686 /* Shortcut: following common codes never translate
20687 into carry flag compares. */
20692 /* These comparisons require zero flag; swap operands so they won't. */
20695 {
20698 }
20700 /* Try to expand the comparison and verify that we end up with
20701 carry flag based comparison. This fails to be true only when
20702 we decide to expand comparison using arithmetic that is not
20703 too common scenario. */
20712 else
20721 }
20727 {
20732 /* Convert a==0 into (unsigned)a<1. */
20741 /* Convert a>b into b<a or a>=b-1. */
20745 {
20747 /* Bail out on overflow. We still can swap operands but that
20748 would force loading of the constant into register. */
20753 }
20754 else
20755 {
20758 }
20761 /* Convert a>=0 into (unsigned)a<0x80000000. */
20779 }
20780 /* Swapping operands may cause constant to appear as first operand. */
20782 {
20786 }
20790 }
20792 bool
20794 {
20797 rtx compare_op;
20819 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20820 HImode insns, we'd be swallowed in word prefix ops. */
20826 {
20830 HOST_WIDE_INT diff;
20833 /* Sign bit compares are better done using shifts than we do by using
20834 sbb. */
20837 {
20838 /* Detect overlap between destination and compare sources. */
20842 {
20843 rtx flags;
20852 {
20854 compare_code
20856 }
20858 /* To simplify rest of code, restrict to the GEU case. */
20860 {
20864 }
20865 else
20866 {
20869 reverse_condition_maybe_unordered
20871 else
20874 }
20883 else
20886 }
20887 else
20888 {
20891 else
20892 {
20895 }
20897 }
20900 {
20901 /*
20902 * cmpl op0,op1
20903 * sbbl dest,dest
20904 * [addl dest, ct]
20905 *
20906 * Size 5 - 8.
20907 */
20912 }
20914 {
20915 /*
20916 * cmpl op0,op1
20917 * sbbl dest,dest
20918 * orl $ct, dest
20919 *
20920 * Size 8.
20921 */
20925 }
20927 {
20928 /*
20929 * cmpl op0,op1
20930 * sbbl dest,dest
20931 * notl dest
20932 * [addl dest, cf]
20933 *
20934 * Size 8 - 11.
20935 */
20941 }
20942 else
20943 {
20944 /*
20945 * cmpl op0,op1
20946 * sbbl dest,dest
20947 * [notl dest]
20948 * andl cf - ct, dest
20949 * [addl dest, ct]
20950 *
20951 * Size 8 - 11.
20952 */
20955 {
20959 }
20969 }
20975 }
20978 {
20983 {
20986 /* We may be reversing unordered compare to normal compare, that
20987 is not valid in general (we may convert non-trapping condition
20988 to trapping one), however on i386 we currently emit all
20989 comparisons unordered. */
20991 }
20992 else
20995 {
20999 }
21000 }
21005 {
21010 {
21015 }
21016 }
21018 /* Optimize dest = (op0 < 0) ? -1 : cf. */
21022 {
21023 /* If lea code below could be used, only optimize
21024 if it results in a 2 insn sequence. */
21030 {
21031 /*
21032 * notl op1 (if necessary)
21033 * sarl $31, op1
21034 * orl cf, op1
21035 */
21037 {
21041 }
21052 }
21053 }
21061 {
21062 /*
21063 * xorl dest,dest
21064 * cmpl op1,op2
21065 * setcc dest
21066 * lea cf(dest*(ct-cf)),dest
21067 *
21068 * Size 14.
21069 *
21070 * This also catches the degenerate setcc-only case.
21071 */
21073 rtx tmp;
21079 /* On x86_64 the lea instruction operates on Pmode, so we need
21080 to get arithmetics done in proper mode to match. */
21083 else
21084 {
21085 rtx out1;
21088 nops++;
21090 {
21092 nops++;
21093 }
21094 }
21096 {
21098 nops++;
21099 }
21101 {
21104 else
21106 }
21111 }
21113 /*
21114 * General case: Jumpful:
21115 * xorl dest,dest cmpl op1, op2
21116 * cmpl op1, op2 movl ct, dest
21117 * setcc dest jcc 1f
21118 * decl dest movl cf, dest
21119 * andl (cf-ct),dest 1:
21120 * addl ct,dest
21121 *
21122 * Size 20. Size 14.
21123 *
21124 * This is reasonably steep, but branch mispredict costs are
21125 * high on modern cpus, so consider failing only if optimizing
21126 * for space.
21127 */
21132 {
21134 {
21139 {
21142 /* We may be reversing unordered compare to normal compare,
21143 that is not valid in general (we may convert non-trapping
21144 condition to trapping one), however on i386 we currently
21145 emit all comparisons unordered. */
21147 }
21148 else
21149 {
21153 }
21156 {
21160 }
21161 }
21164 {
21165 /* notl op1 (if needed)
21166 sarl $31, op1
21167 andl (cf-ct), op1
21168 addl ct, op1
21170 For x < 0 (resp. x <= -1) there will be no notl,
21171 so if possible swap the constants to get rid of the
21172 complement.
21173 True/false will be -1/0 while code below (store flag
21174 followed by decrement) is 0/-1, so the constants need
21175 to be exchanged once more. */
21178 {
21181 }
21182 else
21186 }
21187 else
21188 {
21192 constm1_rtx,
21194 }
21206 }
21207 }
21210 {
21211 /* Try a few things more with specific constants and a variable. */
21213 optab op;
21219 /* If one of the two operands is an interesting constant, load a
21220 constant with the above and mask it in with a logical operation. */
21223 {
21229 else
21231 }
21233 {
21239 else
21241 }
21242 else
21249 /* Recurse to get the constant loaded. */
21253 /* Mask in the interesting variable. */
21255 OPTAB_WIDEN);
21260 }
21262 /*
21263 * For comparison with above,
21264 *
21265 * movl cf,dest
21266 * movl ct,tmp
21267 * cmpl op1,op2
21268 * cmovcc tmp,dest
21269 *
21270 * Size 15.
21271 */
21293 }
21295 /* Swap, force into registers, or otherwise massage the two operands
21296 to an sse comparison with a mask result. Thus we differ a bit from
21297 ix86_prepare_fp_compare_args which expects to produce a flags result.
21299 The DEST operand exists to help determine whether to commute commutative
21300 operators. The POP0/POP1 operands are updated in place. The new
21301 comparison code is returned, or UNKNOWN if not implementable. */
21303 static enum rtx_code
21306 {
21308 {
21311 /* AVX supports all the needed comparisons. */
21314 /* We have no LTGT as an operator. We could implement it with
21315 NE & ORDERED, but this requires an extra temporary. It's
21316 not clear that it's worth it. */
21323 /* These are supported directly. */
21330 /* AVX has 3 operand comparisons, no need to swap anything. */
21333 /* For commutative operators, try to canonicalize the destination
21334 operand to be first in the comparison - this helps reload to
21335 avoid extra moves. */
21338 /* FALLTHRU */
21344 /* These are not supported directly before AVX, and furthermore
21345 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
21346 comparison operands to transform into something that is
21347 supported. */
21354 }
21357 }
21359 /* Detect conditional moves that exactly match min/max operational
21360 semantics. Note that this is IEEE safe, as long as we don't
21361 interchange the operands.
21363 Returns FALSE if this conditional move doesn't match a MIN/MAX,
21364 and TRUE if the operation is successful and instructions are emitted. */
21366 static bool
21369 {
21370 machine_mode mode;
21372 rtx tmp;
21375 ;
21378 else
21385 else
21390 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
21391 but MODE may be a vector mode and thus not appropriate. */
21393 {
21395 rtvec v;
21400 }
21401 else
21402 {
21405 }
21409 }
21411 /* Expand an sse vector comparison. Return the register with the result. */
21413 static rtx
21416 {
21420 /* In general case result of comparison can differ from operands' type. */
21421 machine_mode cmp_mode;
21423 /* In AVX512F the result of comparison is an integer mask. */
21425 rtx x;
21428 {
21433 }
21434 else
21447 /* Compare patterns for int modes are unspec in AVX512F only. */
21449 {
21453 {
21470 }
21473 {
21476 }
21477 }
21481 {
21484 }
21485 else
21489 }
21491 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
21492 operations. This is used for both scalar and vector conditional moves. */
21494 static void
21496 {
21500 /* In AVX512F the result of comparison is an integer mask. */
21508 {
21510 }
21513 {
21517 }
21520 {
21525 }
21528 {
21532 }
21535 {
21542 op_true,
21543 op_false)));
21544 }
21545 else
21546 {
21556 {
21570 {
21577 }
21592 {
21599 }
21623 }
21626 {
21630 }
21631 else
21632 {
21638 else
21650 }
21651 }
21652 }
21654 /* Expand a floating-point conditional move. Return true if successful. */
21656 bool
21658 {
21666 {
21667 machine_mode cmode;
21669 /* Since we've no cmove for sse registers, don't force bad register
21670 allocation just to gain access to it. Deny movcc when the
21671 comparison mode doesn't match the move mode. */
21690 }
21697 /* The floating point conditional move instructions don't directly
21698 support conditions resulting from a signed integer comparison. */
21702 {
21707 }
21714 }
21716 /* Expand a floating-point vector conditional move; a vcond operation
21717 rather than a movcc operation. */
21719 bool
21721 {
21723 rtx cmp;
21728 {
21729 rtx temp;
21731 {
21748 }
21750 OPTAB_DIRECT);
21753 }
21763 }
21765 /* Expand a signed/unsigned integral vector conditional move. */
21767 bool
21769 {
21779 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21780 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21789 {
21793 {
21799 }
21802 {
21808 }
21809 }
21818 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21822 ;
21823 else
21824 {
21825 /* Canonicalize the comparison to EQ, GT, GTU. */
21827 {
21844 /* FALLTHRU */
21854 }
21856 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21858 {
21860 {
21862 /* SSE4.1 supports EQ. */
21869 /* SSE4.2 supports GT/GTU. */
21876 }
21877 }
21879 /* Unsigned parallel compare is not supported by the hardware.
21880 Play some tricks to turn this into a signed comparison
21881 against 0. */
21883 {
21887 {
21894 {
21899 {
21908 }
21909 /* Subtract (-(INT MAX) - 1) from both operands to make
21910 them signed. */
21921 }
21930 /* Perform a parallel unsigned saturating subtraction. */
21942 }
21943 }
21944 }
21946 /* Allow the comparison to be done in one mode, but the movcc to
21947 happen in another mode. */
21949 {
21952 }
21953 else
21954 {
21960 }
21965 }
21967 /* AVX512F does support 64-byte integer vector operations,
21968 thus the longest vector we are faced with is V64QImode. */
21969 #define MAX_VECT_LEN 64
21971 struct expand_vec_perm_d
21972 {
21975 machine_mode vmode;
21979 };
21981 static bool
21984 {
21985 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21986 expander, so args are either in d, or in op0, op1 etc. */
21992 {
22023 {
22026 }
22030 {
22033 }
22037 {
22040 }
22056 {
22059 }
22063 {
22066 }
22070 {
22073 }
22077 }
22082 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
22083 expander, so args are either in d, or in op0, op1 etc. */
22085 {
22093 }
22097 }
22099 /* Expand a variable vector permutation. */
22101 void
22103 {
22114 /* Number of elements in the vector. */
22123 {
22125 {
22126 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
22127 an constant shuffle operand. With a tiny bit of effort we can
22128 use VPERMD instead. A re-interpretation stall for V4DFmode is
22129 unfortunate but there's no avoiding it.
22130 Similarly for V16HImode we don't have instructions for variable
22131 shuffling, while for V32QImode we can use after preparing suitable
22132 masks vpshufb; vpshufb; vpermq; vpor. */
22135 {
22139 }
22140 else
22141 {
22145 }
22148 /* Replicate the low bits of the V4DImode mask into V8SImode:
22149 mask = { A B C D }
22150 t1 = { A A B B C C D D }. */
22158 else
22161 /* Multiply the shuffle indicies by two. */
22163 OPTAB_DIRECT);
22165 /* Add one to the odd shuffle indicies:
22166 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
22168 {
22171 }
22175 OPTAB_DIRECT);
22177 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
22182 }
22185 {
22187 /* The VPERMD and VPERMPS instructions already properly ignore
22188 the high bits of the shuffle elements. No need for us to
22189 perform an AND ourselves. */
22191 {
22196 }
22197 else
22198 {
22204 }
22211 else
22212 {
22218 }
22222 /* By combining the two 128-bit input vectors into one 256-bit
22223 input vector, we can use VPERMD and VPERMPS for the full
22224 two-operand shuffle. */
22256 /* From mask create two adjusted masks, which contain the same
22257 bits as mask in the low 7 bits of each vector element.
22258 The first mask will have the most significant bit clear
22259 if it requests element from the same 128-bit lane
22260 and MSB set if it requests element from the other 128-bit lane.
22261 The second mask will have the opposite values of the MSB,
22262 and additionally will have its 128-bit lanes swapped.
22263 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
22264 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
22265 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
22266 stands for other 12 bytes. */
22267 /* The bit whether element is from the same lane or the other
22268 lane is bit 4, so shift it up by 3 to the MSB position. */
22272 /* Clear MSB bits from the mask just in case it had them set. */
22274 /* After this t1 will have MSB set for elements from other lane. */
22276 /* Clear bits other than MSB. */
22278 /* Or in the lower bits from mask into t3. */
22280 /* And invert MSB bits in t1, so MSB is set for elements from the same
22281 lane. */
22283 /* Swap 128-bit lanes in t3. */
22288 /* And or in the lower bits from mask into t1. */
22291 {
22292 /* Each of these shuffles will put 0s in places where
22293 element from the other 128-bit lane is needed, otherwise
22294 will shuffle in the requested value. */
22298 /* For t3 the 128-bit lanes are swapped again. */
22303 /* And oring both together leads to the result. */
22310 }
22313 /* Similarly to the above one_operand_shuffle code,
22314 just for repeated twice for each operand. merge_two:
22315 code will merge the two results together. */
22339 }
22340 }
22343 {
22344 /* The XOP VPPERM insn supports three inputs. By ignoring the
22345 one_operand_shuffle special case, we avoid creating another
22346 set of constant vectors in memory. */
22349 /* mask = mask & {2*w-1, ...} */
22351 }
22352 else
22353 {
22354 /* mask = mask & {w-1, ...} */
22356 }
22364 /* For non-QImode operations, convert the word permutation control
22365 into a byte permutation control. */
22367 {
22372 /* Convert mask to vector of chars. */
22375 /* Replicate each of the input bytes into byte positions:
22376 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
22377 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
22378 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
22385 else
22388 /* Convert it into the byte positions by doing
22389 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
22395 }
22397 /* The actual shuffle operations all operate on V16QImode. */
22402 {
22409 }
22411 {
22418 }
22419 else
22420 {
22424 /* Shuffle the two input vectors independently. */
22430 merge_two:
22431 /* Then merge them together. The key is whether any given control
22432 element contained a bit set that indicates the second word. */
22436 {
22437 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
22438 more shuffle to convert the V2DI input mask into a V4SI
22439 input mask. At which point the masking that expand_int_vcond
22440 will work as desired. */
22448 }
22470 }
22471 }
22473 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
22474 true if we should do zero extension, else sign extension. HIGH_P is
22475 true if we want the N/2 high elements, else the low elements. */
22477 void
22479 {
22481 rtx tmp;
22484 {
22490 {
22494 else
22497 extract
22503 else
22506 extract
22512 else
22515 extract
22521 else
22524 extract
22530 else
22533 extract
22539 else
22542 extract
22548 else
22554 else
22560 else
22565 }
22568 {
22571 }
22573 {
22574 /* Shift higher 8 bytes to lower 8 bytes. */
22579 }
22580 else
22584 }
22585 else
22586 {
22590 {
22594 else
22600 else
22606 else
22611 }
22615 else
22622 }
22623 }
22625 /* Expand conditional increment or decrement using adb/sbb instructions.
22626 The default case using setcc followed by the conditional move can be
22627 done by generic code. */
22628 bool
22630 {
22632 rtx flags;
22634 rtx compare_op;
22637 machine_mode mode;
22652 {
22655 }
22658 {
22662 reverse_condition_maybe_unordered
22664 else
22666 }
22670 /* Construct either adc or sbb insn. */
22672 {
22674 {
22689 }
22690 }
22691 else
22692 {
22694 {
22709 }
22710 }
22714 }
22717 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22718 but works for floating pointer parameters and nonoffsetable memories.
22719 For pushes, it returns just stack offsets; the values will be saved
22720 in the right order. Maximally three parts are generated. */
22722 static int
22724 {
22729 else
22735 /* Optimize constant pool reference to immediates. This is used by fp
22736 moves, that force all constants to memory to allow combining. */
22738 {
22742 }
22745 {
22746 /* The only non-offsetable memories we handle are pushes. */
22755 }
22758 {
22760 /* Caution: if we looked through a constant pool memory above,
22761 the operand may actually have a different mode now. That's
22762 ok, since we want to pun this all the way back to an integer. */
22766 }
22769 {
22772 else
22773 {
22777 {
22781 }
22783 {
22788 }
22790 {
22791 REAL_VALUE_TYPE r;
22796 {
22803 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22804 long double may not be 80-bit. */
22813 }
22816 }
22817 else
22819 }
22820 }
22821 else
22822 {
22826 {
22829 {
22833 }
22835 {
22839 }
22841 {
22842 REAL_VALUE_TYPE r;
22848 /* real_to_target puts 32-bit pieces in each long. */
22850 gen_int_mode
22853 DImode);
22857 else
22859 gen_int_mode
22862 DImode);
22863 }
22864 else
22866 }
22867 }
22870 }
22872 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22873 Return false when normal moves are needed; true when all required
22874 insns have been emitted. Operands 2-4 contain the input values
22875 int the correct order; operands 5-7 contain the output values. */
22877 void
22879 {
22887 /* The DFmode expanders may ask us to move double.
22888 For 64bit target this is single move. By hiding the fact
22889 here we simplify i386.md splitters. */
22891 {
22892 /* Optimize constant pool reference to immediates. This is used by
22893 fp moves, that force all constants to memory to allow combining. */
22900 {
22903 }
22904 else
22909 }
22911 /* The only non-offsettable memory we handle is push. */
22914 else
22921 /* When emitting push, take care for source operands on the stack. */
22924 {
22927 /* Compensate for the stack decrement by 4. */
22932 /* src_base refers to the stack pointer and is
22933 automatically decreased by emitted push. */
22937 }
22939 /* We need to do copy in the right order in case an address register
22940 of the source overlaps the destination. */
22942 {
22943 rtx tmp;
22946 {
22950 collisions++;
22951 }
22953 /* Collision in the middle part can be handled by reordering. */
22955 {
22958 }
22962 {
22964 {
22967 }
22968 else
22969 {
22972 }
22973 }
22975 /* If there are more collisions, we can't handle it by reordering.
22976 Do an lea to the last part and use only one colliding move. */
22978 {
22985 /* Handle the case when the last part isn't valid for lea.
22986 Happens in 64-bit mode storing the 12-byte XFmode. */
22992 {
22997 {
22998 /* It is not valid to use %gs: or %fs: in
22999 lea though, so we need to remove it from the
23000 address used for lea and add it to each individual
23001 memory loads instead. */
23005 {
23007 {
23013 {
23017 }
23018 }
23022 }
23024 }
23025 }
23031 {
23036 }
23037 }
23038 }
23041 {
23043 {
23045 {
23050 }
23052 {
23055 }
23056 }
23057 else
23058 {
23059 /* In 64bit mode we don't have 32bit push available. In case this is
23060 register, it is OK - we will just use larger counterpart. We also
23061 retype memory - these comes from attempt to avoid REX prefix on
23062 moving of second half of TFmode value. */
23064 {
23066 {
23077 }
23081 }
23082 }
23086 }
23088 /* Choose correct order to not overwrite the source before it is copied. */
23098 {
23100 {
23103 }
23104 }
23105 else
23106 {
23108 {
23111 }
23112 }
23114 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
23116 {
23125 }
23131 }
23133 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
23134 left shift by a constant, either using a single shift or
23135 a sequence of add instructions. */
23137 static void
23139 {
23145 {
23149 }
23150 else
23151 {
23154 }
23155 }
23157 void
23159 {
23168 {
23173 {
23179 }
23180 else
23181 {
23189 }
23191 }
23198 {
23199 /* Assuming we've chosen a QImode capable registers, then 1 << N
23200 can be done with two 32/64-bit shifts, no branches, no cmoves. */
23202 {
23218 }
23220 /* Otherwise, we can get the same results by manually performing
23221 a bit extract operation on bit 5/6, and then performing the two
23222 shifts. The two methods of getting 0/1 into low/high are exactly
23223 the same size. Avoiding the shift in the bit extract case helps
23224 pentium4 a bit; no one else seems to care much either way. */
23225 else
23226 {
23227 machine_mode half_mode;
23231 HOST_WIDE_INT bits;
23232 rtx x;
23235 {
23241 }
23242 else
23243 {
23249 }
23253 else
23261 }
23266 }
23269 {
23270 /* For -1 << N, we can avoid the shld instruction, because we
23271 know that we're shifting 0...31/63 ones into a -1. */
23275 else
23277 }
23278 else
23279 {
23287 }
23292 {
23298 }
23299 else
23300 {
23305 }
23306 }
23308 void
23310 {
23320 {
23325 {
23331 }
23333 {
23342 }
23343 else
23344 {
23352 }
23353 }
23354 else
23355 {
23367 {
23375 scratch));
23376 }
23377 else
23378 {
23383 }
23384 }
23385 }
23387 void
23389 {
23399 {
23404 {
23411 }
23412 else
23413 {
23421 }
23422 }
23423 else
23424 {
23436 {
23442 scratch));
23443 }
23444 else
23445 {
23450 }
23451 }
23452 }
23454 /* Predict just emitted jump instruction to be taken with probability PROB. */
23455 static void
23457 {
23461 }
23463 /* Helper function for the string operations below. Dest VARIABLE whether
23464 it is aligned to VALUE bytes. If true, jump to the label. */
23467 {
23472 else
23478 else
23481 }
23483 /* Adjust COUNTER by the VALUE. */
23484 static void
23486 {
23491 }
23493 /* Zero extend possibly SImode EXP to Pmode register. */
23494 rtx
23496 {
23498 }
23500 /* Divide COUNTREG by SCALE. */
23501 static rtx
23503 {
23504 rtx sc;
23516 }
23518 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
23519 DImode for constant loop counts. */
23521 static machine_mode
23523 {
23531 }
23533 /* Copy the address to a Pmode register. This is used for x32 to
23534 truncate DImode TLS address to a SImode register. */
23536 static rtx
23538 {
23539 rtx reg;
23541 {
23545 }
23546 else
23547 {
23552 }
23553 }
23555 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
23556 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
23557 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
23558 memory by VALUE (supposed to be in MODE).
23560 The size is rounded down to whole number of chunk size moved at once.
23561 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
23564 static void
23569 {
23576 rtx size;
23585 /* Those two should combine. */
23587 {
23591 }
23598 /* This assert could be relaxed - in this case we'll need to compute
23599 smallest power of two, containing in PIECE_SIZE_N and pass it to
23600 offset_address. */
23606 {
23610 /* When unrolling for chips that reorder memory reads and writes,
23611 we can save registers by using single temporary.
23612 Also using 4 temporaries is overkill in 32bit mode. */
23614 {
23616 {
23618 {
23619 destmem =
23621 srcmem =
23623 }
23625 }
23626 }
23627 else
23628 {
23632 {
23635 {
23636 srcmem =
23638 }
23640 }
23642 {
23644 {
23645 destmem =
23647 }
23649 }
23650 }
23651 }
23652 else
23654 {
23656 destmem =
23659 }
23669 {
23675 else
23677 }
23678 else
23686 {
23691 }
23693 }
23695 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
23696 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
23697 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
23698 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
23699 ORIG_VALUE is the original value passed to memset to fill the memory with.
23700 Other arguments have same meaning as for previous function. */
23702 static void
23705 rtx count,
23707 {
23708 rtx destexp;
23709 rtx srcexp;
23710 rtx countreg;
23711 HOST_WIDE_INT rounded_count;
23713 /* If possible, it is shorter to use rep movs.
23714 TODO: Maybe it is better to move this logic to decide_alg. */
23725 {
23729 }
23730 else
23733 {
23738 }
23743 {
23746 }
23747 else
23748 {
23752 {
23756 }
23757 else
23760 {
23765 }
23766 else
23767 {
23770 }
23773 }
23774 }
23776 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23777 DESTMEM.
23778 SRC is passed by pointer to be updated on return.
23779 Return value is updated DST. */
23780 static rtx
23782 HOST_WIDE_INT size_to_move)
23783 {
23786 machine_mode move_mode;
23789 /* Find the widest mode in which we could perform moves.
23790 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23791 it until move of such size is supported. */
23796 {
23800 }
23802 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23803 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23805 {
23810 {
23814 }
23815 }
23821 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23825 {
23826 /* We move from memory to memory, so we'll need to do it via
23827 a temporary register. */
23838 piece_size);
23840 piece_size);
23841 }
23843 /* Update DST and SRC rtx. */
23846 }
23848 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23849 static void
23852 {
23855 {
23860 /* For now MAX_SIZE should be a power of 2. This assert could be
23861 relaxed, but it'll require a bit more complicated epilogue
23862 expanding. */
23865 {
23868 }
23870 }
23872 {
23878 }
23880 /* When there are stringops, we can cheaply increase dest and src pointers.
23881 Otherwise we save code size by maintaining offset (zero is readily
23882 available from preceding rep operation) and using x86 addressing modes.
23883 */
23885 {
23887 {
23894 }
23896 {
23903 }
23905 {
23912 }
23913 }
23914 else
23915 {
23917 rtx tmp;
23920 {
23931 }
23933 {
23946 }
23948 {
23957 }
23958 }
23959 }
23961 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23962 with value PROMOTED_VAL.
23963 SRC is passed by pointer to be updated on return.
23964 Return value is updated DST. */
23965 static rtx
23967 HOST_WIDE_INT size_to_move)
23968 {
23971 machine_mode move_mode;
23974 /* Find the widest mode in which we could perform moves.
23975 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23976 it until move of such size is supported. */
23981 {
23984 }
23991 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23995 {
23997 {
24000 piece_size);
24002 }
24010 piece_size);
24011 }
24013 /* Update DST rtx. */
24015 }
24016 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
24017 static void
24020 {
24021 count =
24027 }
24029 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
24030 static void
24033 {
24034 rtx dest;
24037 {
24042 /* For now MAX_SIZE should be a power of 2. This assert could be
24043 relaxed, but it'll require a bit more complicated epilogue
24044 expanding. */
24047 {
24049 {
24052 else
24054 }
24055 }
24057 }
24059 {
24062 }
24064 {
24067 {
24072 }
24073 else
24074 {
24083 }
24086 }
24088 {
24091 {
24094 }
24095 else
24096 {
24101 }
24104 }
24106 {
24112 }
24114 {
24120 }
24122 {
24128 }
24129 }
24131 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
24132 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
24133 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
24134 ignored.
24135 Return value is updated DESTMEM. */
24136 static rtx
24141 {
24144 {
24146 {
24149 {
24152 else
24154 }
24155 else
24161 }
24162 }
24164 }
24166 /* Test if COUNT&SIZE is nonzero and if so, expand movme
24167 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
24168 and jump to DONE_LABEL. */
24169 static void
24175 {
24178 rtx modesize;
24181 /* If we do not have vector value to copy, we must reduce size. */
24183 {
24185 {
24190 }
24191 else
24193 }
24194 else
24195 {
24196 /* Choose appropriate vector mode. */
24202 }
24207 {
24210 else
24211 {
24214 }
24216 }
24222 {
24226 }
24228 {
24231 else
24232 {
24235 }
24237 }
24243 }
24245 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
24246 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
24247 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
24248 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
24249 DONE_LABEL is a label after the whole copying sequence. The label is created
24250 on demand if *DONE_LABEL is NULL.
24251 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
24252 bounds after the initial copies.
24254 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
24255 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
24256 we will dispatch to a library call for large blocks.
24258 In pseudocode we do:
24260 if (COUNT < SIZE)
24261 {
24262 Assume that SIZE is 4. Bigger sizes are handled analogously
24263 if (COUNT & 4)
24264 {
24265 copy 4 bytes from SRCPTR to DESTPTR
24266 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
24267 goto done_label
24268 }
24269 if (!COUNT)
24270 goto done_label;
24271 copy 1 byte from SRCPTR to DESTPTR
24272 if (COUNT & 2)
24273 {
24274 copy 2 bytes from SRCPTR to DESTPTR
24275 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
24276 }
24277 }
24278 else
24279 {
24280 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
24281 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
24283 OLD_DESPTR = DESTPTR;
24284 Align DESTPTR up to DESIRED_ALIGN
24285 SRCPTR += DESTPTR - OLD_DESTPTR
24286 COUNT -= DEST_PTR - OLD_DESTPTR
24287 if (DYNAMIC_CHECK)
24288 Round COUNT down to multiple of SIZE
24289 << optional caller supplied zero size guard is here >>
24290 << optional caller suppplied dynamic check is here >>
24291 << caller supplied main copy loop is here >>
24292 }
24293 done_label:
24294 */
24295 static void
24298 machine_mode mode,
24308 {
24311 rtx modesize;
24313 rtx mode_value;
24315 /* Chose proper value to copy. */
24318 else
24322 /* See if block is big or small, handle small blocks. */
24324 {
24335 /* Handle sizes > 3. */
24342 /* Nothing to copy? Jump to DONE_LABEL if so */
24346 /* Do a byte copy. */
24350 else
24351 {
24354 }
24356 /* Handle sizes 2 and 3. */
24363 else
24364 {
24369 }
24375 }
24376 else
24380 /* Start memcpy for COUNT >= SIZE. */
24382 {
24385 }
24387 /* Copy first desired_align bytes. */
24393 {
24396 else
24397 {
24400 }
24403 }
24406 /* Copy last SIZE bytes. */
24413 else
24414 {
24420 }
24422 {
24426 else
24427 {
24430 }
24431 }
24433 /* Align destination. */
24435 {
24439 /* Align destptr up, place it to new register. */
24448 /* See how many bytes we skipped. */
24452 /* Adjust srcptr and count. */
24458 /* We copied at most size + prolog_size. */
24461 else
24464 /* Our loops always round down the bock size, but for dispatch to library
24465 we need precise value. */
24469 }
24470 else
24471 {
24473 /* Decrease count, so we won't end up copying last word twice. */
24477 else
24481 }
24482 }
24485 /* This function is like the previous one, except here we know how many bytes
24486 need to be copied. That allows us to update alignment not only of DST, which
24487 is returned, but also of SRC, which is passed as a pointer for that
24488 reason. */
24489 static rtx
24494 {
24502 {
24506 }
24511 {
24513 {
24515 {
24518 else
24520 }
24521 else
24524 }
24525 }
24532 {
24538 {
24541 {
24545 }
24550 }
24554 }
24557 }
24559 /* Return true if ALG can be used in current context.
24560 Assume we expand memset if MEMSET is true. */
24561 static bool
24563 {
24568 /* Algorithms using the rep prefix want at least edi and ecx;
24569 additionally, memset wants eax and memcpy wants esi. Don't
24570 consider such algorithms if the user has appropriated those
24571 registers for their own purposes. */
24578 }
24580 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
24581 static enum stringop_alg
24585 {
24596 /* Even if the string operation call is cold, we still might spend a lot
24597 of time processing large blocks. */
24603 else
24609 else
24612 /* See maximal size for user defined algorithm. */
24614 {
24621 }
24623 /* If expected size is not known but max size is small enough
24624 so inline version is a win, set expected size into
24625 the range. */
24630 /* If user specified the algorithm, honnor it if possible. */
24634 /* rep; movq or rep; movl is the smallest variant. */
24636 {
24641 else
24644 }
24645 /* Very tiny blocks are best handled via the loop, REP is expensive to
24646 setup. */
24650 {
24654 {
24655 /* We get here if the algorithms that were not libcall-based
24656 were rep-prefix based and we are unable to use rep prefixes
24657 based on global register usage. Break out of the loop and
24658 use the heuristic below. */
24662 {
24666 {
24669 }
24670 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
24671 last non-libcall inline algorithm. */
24673 {
24674 /* When the current size is best to be copied by a libcall,
24675 but we are still forced to inline, run the heuristic below
24676 that will pick code for medium sized blocks. */
24678 {
24681 }
24684 }
24686 {
24689 }
24690 }
24691 }
24692 }
24693 /* When asked to inline the call anyway, try to pick meaningful choice.
24694 We look for maximal size of block that is faster to copy by hand and
24695 take blocks of at most of that size guessing that average size will
24696 be roughly half of the block.
24698 If this turns out to be bad, we might simply specify the preferred
24699 choice in ix86_costs. */
24703 {
24706 /* If there aren't any usable algorithms, then recursing on
24707 smaller sizes isn't going to find anything. Just return the
24708 simple byte-at-a-time copy loop. */
24710 {
24711 /* Pick something reasonable. */
24715 }
24723 else
24726 }
24729 }
24731 /* Decide on alignment. We know that the operand is already aligned to ALIGN
24732 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
24733 static int
24737 machine_mode move_mode)
24738 {
24749 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
24750 copying whole cacheline at once. */
24763 }
24766 /* Helper function for memcpy. For QImode value 0xXY produce
24767 0xXYXYXYXY of wide specified by MODE. This is essentially
24768 a * 0x10101010, but we can do slightly better than
24769 synth_mult by unwinding the sequence by hand on CPUs with
24770 slow multiply. */
24771 static rtx
24773 {
24775 rtx tmp;
24782 {
24790 }
24799 nops--;
24804 {
24808 OPTAB_DIRECT);
24809 }
24810 else
24811 {
24817 else
24819 else
24820 {
24823 reg =
24825 }
24835 }
24836 }
24838 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24839 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24840 alignment from ALIGN to DESIRED_ALIGN. */
24841 static rtx
24844 {
24845 rtx promoted_val;
24854 else
24858 }
24860 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24861 operations when profitable. The code depends upon architecture, block size
24862 and alignment, but always has one of the following overall structures:
24864 Aligned move sequence:
24866 1) Prologue guard: Conditional that jumps up to epilogues for small
24867 blocks that can be handled by epilogue alone. This is faster
24868 but also needed for correctness, since prologue assume the block
24869 is larger than the desired alignment.
24871 Optional dynamic check for size and libcall for large
24872 blocks is emitted here too, with -minline-stringops-dynamically.
24874 2) Prologue: copy first few bytes in order to get destination
24875 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24876 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24877 copied. We emit either a jump tree on power of two sized
24878 blocks, or a byte loop.
24880 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24881 with specified algorithm.
24883 4) Epilogue: code copying tail of the block that is too small to be
24884 handled by main body (or up to size guarded by prologue guard).
24886 Misaligned move sequence
24888 1) missaligned move prologue/epilogue containing:
24889 a) Prologue handling small memory blocks and jumping to done_label
24890 (skipped if blocks are known to be large enough)
24891 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24892 needed by single possibly misaligned move
24893 (skipped if alignment is not needed)
24894 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24896 2) Zero size guard dispatching to done_label, if needed
24898 3) dispatch to library call, if needed,
24900 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24901 with specified algorithm. */
24902 bool
24908 {
24909 rtx destreg;
24912 rtx tmp;
24928 /* TODO: Once value ranges are available, fill in proper data. */
24936 /* i386 can do misaligned access on reasonably increased cost. */
24940 /* ALIGN is the minimum of destination and source alignment, but we care here
24941 just about destination alignment. */
24947 {
24950 /* When COUNT is 0, there is nothing to do. */
24953 }
24954 else
24955 {
24964 }
24966 /* Make sure we don't need to care about overflow later on. */
24970 /* Step 0: Decide on preferred algorithm, desired alignment and
24971 size of chunks to be copied by main loop. */
24973 issetmem,
24980 /* For now vector-version of memset is generated only for memory zeroing, as
24981 creating of promoted vector value is very cheap in this case. */
24994 {
25013 /* Find the widest supported mode. */
25019 /* Find the corresponding vector mode with the same size as MOVE_MODE.
25020 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
25022 {
25027 }
25039 }
25047 /* Step 1: Prologue guard. */
25049 /* Alignment code needs count to be in register. */
25051 {
25054 {
25055 align_bytes
25059 else
25061 }
25064 }
25067 /* Misaligned move sequences handle both prologue and epilogue at once.
25068 Default code generation results in a smaller code for large alignments
25069 and also avoids redundant job when sizes are known precisely. */
25070 misaligned_prologue_used
25071 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
25077 /* Do the cheap promotion to allow better CSE across the
25078 main loop and epilogue (ie one load of the big constant in the
25079 front of all code.
25080 For now the misaligned move sequences do not have fast path
25081 without broadcasting. */
25083 {
25085 {
25091 }
25092 else
25093 {
25096 }
25097 }
25098 /* Misaligned move sequences handles both prologues and epilogues at once.
25099 Default code generation results in smaller code for large alignments and
25100 also avoids redundant job when sizes are known precisely. */
25102 {
25103 /* Misaligned move prologue handled small blocks by itself. */
25104 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
25109 desired_align < align
25119 {
25120 /* It is possible that we copied enough so the main loop will not
25121 execute. */
25131 else
25133 }
25134 }
25135 /* Ensure that alignment prologue won't copy past end of block. */
25137 {
25139 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
25140 Make sure it is power of 2. */
25143 /* To improve performance of small blocks, we jump around the VAL
25144 promoting mode. This mean that if the promoted VAL is not constant,
25145 we might not use it in the epilogue and have to use byte
25146 loop variant. */
25151 {
25152 /* If main algorithm works on QImode, no epilogue is needed.
25153 For small sizes just don't align anything. */
25156 else
25158 }
25161 {
25168 else
25170 }
25171 }
25173 /* Emit code to decide on runtime whether library call or inline should be
25174 used. */
25176 {
25178 {
25180 {
25184 }
25185 }
25186 else
25187 {
25197 else
25201 }
25202 }
25204 /* Step 2: Alignment prologue. */
25205 /* Do the expensive promotion once we branched off the small blocks. */
25211 {
25213 {
25214 /* Except for the first move in prologue, we no longer know
25215 constant offset in aliasing info. It don't seems to worth
25216 the pain to maintain it for the first move, so throw away
25217 the info early. */
25224 issetmem);
25225 /* At most desired_align - align bytes are copied. */
25228 else
25230 }
25231 else
25232 {
25233 /* If we know how many bytes need to be stored before dst is
25234 sufficiently aligned, maintain aliasing info accurately. */
25236 srcreg,
25237 promoted_val,
25238 vec_promoted_val,
25239 desired_align,
25240 align_bytes,
25241 issetmem);
25248 }
25255 {
25256 /* It is possible that we copied enough so the main loop will not
25257 execute. */
25267 else
25269 }
25270 }
25272 {
25279 }
25283 /* Step 3: Main loop. */
25286 {
25309 }
25310 /* Adjust properly the offset of src and dest memory for aliasing. */
25312 {
25318 }
25319 else
25320 {
25324 }
25326 /* Step 4: Epilogue to copy the remaining bytes. */
25327 epilogue:
25329 {
25330 /* When the main loop is done, COUNT_EXP might hold original count,
25331 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
25332 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
25333 bytes. Compensate if needed. */
25336 {
25337 tmp =
25340 OPTAB_DIRECT);
25343 }
25346 }
25349 {
25352 epilogue_size_needed);
25353 else
25354 {
25358 epilogue_size_needed);
25359 else
25361 epilogue_size_needed);
25362 }
25363 }
25367 }
25370 /* Expand the appropriate insns for doing strlen if not just doing
25371 repnz; scasb
25373 out = result, initialized with the start address
25374 align_rtx = alignment of the address.
25375 scratch = scratch register, initialized with the startaddress when
25376 not aligned, otherwise undefined
25378 This is just the body. It needs the initializations mentioned above and
25379 some address computing at the end. These things are done in i386.md. */
25381 static void
25383 {
25385 rtx tmp;
25390 rtx mem;
25393 rtx cmp;
25399 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
25401 /* Is there a known alignment and is it less than 4? */
25403 {
25406 /* Is there a known alignment and is it not 2? */
25408 {
25412 /* Leave just the 3 lower bits. */
25422 }
25423 else
25424 {
25425 /* Since the alignment is 2, we have to check 2 or 0 bytes;
25426 check if is aligned to 4 - byte. */
25433 }
25437 /* Now compare the bytes. */
25439 /* Compare the first n unaligned byte on a byte per byte basis. */
25443 /* Increment the address. */
25446 /* Not needed with an alignment of 2 */
25448 {
25452 end_0_label);
25457 }
25460 end_0_label);
25463 }
25465 /* Generate loop to check 4 bytes at a time. It is not a good idea to
25466 align this loop. It gives only huge programs, but does not help to
25467 speed up. */
25474 /* This formula yields a nonzero result iff one of the bytes is zero.
25475 This saves three branches inside loop and many cycles. */
25483 align_4_label);
25486 {
25492 /* If zero is not in the first two bytes, move two bytes forward. */
25498 reg,
25499 tmpreg)));
25500 /* Emit lea manually to avoid clobbering of flags. */
25507 reg2,
25508 out)));
25509 }
25510 else
25511 {
25513 /* Is zero in the first two bytes? */
25520 pc_rtx);
25524 /* Not in the first two. Move two bytes forward. */
25530 }
25532 /* Avoid branch in fixing the byte. */
25540 }
25542 /* Expand strlen. */
25544 bool
25546 {
25549 /* The generic case of strlen expander is long. Avoid it's
25550 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
25553 && !TARGET_INLINE_ALL_STRINGOPS
25563 {
25564 /* Well it seems that some optimizer does not combine a call like
25565 foo(strlen(bar), strlen(bar));
25566 when the move and the subtraction is done here. It does calculate
25567 the length just once when these instructions are done inside of
25568 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
25569 often used and I use one fewer register for the lifetime of
25570 output_strlen_unroll() this is better. */
25576 /* strlensi_unroll_1 returns the address of the zero at the end of
25577 the string, like memchr(), so compute the length by subtracting
25578 the start address. */
25580 }
25581 else
25582 {
25583 rtx unspec;
25585 /* Can't use this if the user has appropriated eax, ecx, or edi. */
25598 /* If .md starts supporting :P, this can be done in .md. */
25604 }
25606 }
25608 /* For given symbol (function) construct code to compute address of it's PLT
25609 entry in large x86-64 PIC model. */
25610 static rtx
25612 {
25625 }
25627 rtx
25629 rtx callarg2,
25631 {
25641 {
25642 #if TARGET_MACHO
25645 #endif
25646 }
25647 else
25648 {
25649 /* Static functions and indirect calls don't need the pic register. Also,
25650 check if PLT was explicitly avoided via no-plt or "noplt" attribute, making
25651 it an indirect call. */
25653 && (!TARGET_64BIT
25658 && flag_plt
25662 {
25666 pic_offset_table_rtx);
25667 }
25668 }
25670 /* Skip setting up RAX register for -mskip-rax-setup when there are no
25671 parameters passed in vector registers. */
25676 {
25680 }
25683 && !TARGET_PECOFF
25691 {
25694 }
25699 {
25700 /* We should add bounds as destination register in case
25701 pointer with bounds may be returned. */
25703 {
25707 {
25712 }
25713 else
25714 {
25718 }
25719 }
25722 }
25726 {
25730 }
25734 {
25735 int const cregs_size
25740 {
25745 }
25746 }
25755 }
25757 /* Return true if the function being called was marked with attribute "noplt"
25758 or using -fno-plt and we are compiling for non-PIC and x86_64. We need to
25759 handle the non-PIC case in the backend because there is no easy interface
25760 for the front-end to force non-PLT calls to use the GOT. This is currently
25761 used only with 64-bit ELF targets to call the function marked "noplt"
25762 indirectly. */
25764 static bool
25766 {
25780 }
25782 /* Output the assembly for a call instruction. */
25786 {
25792 {
25797 /* SEH epilogue detection requires the indirect branch case
25798 to include REX.W. */
25801 else
25806 }
25808 /* SEH unwinding can require an extra nop to be emitted in several
25809 circumstances. Determine if we have one of those. */
25811 {
25815 {
25816 /* If we get to another real insn, we don't need the nop. */
25820 /* If we get to the epilogue note, prevent a catch region from
25821 being adjacent to the standard epilogue sequence. If non-
25822 call-exceptions, we'll have done this during epilogue emission. */
25824 && !flag_non_call_exceptions
25826 {
25829 }
25830 }
25832 /* If we didn't find a real insn following the call, prevent the
25833 unwinder from looking into the next function. */
25836 }
25842 else
25851 }
25852 \f
25853 /* Clear stack slot assignments remembered from previous functions.
25854 This is called from INIT_EXPANDERS once before RTL is emitted for each
25855 function. */
25859 {
25867 }
25869 /* Return a MEM corresponding to a stack slot with mode MODE.
25870 Allocate a new slot if necessary.
25872 The RTL for a function can have several slots available: N is
25873 which slot to use. */
25875 rtx
25877 {
25894 }
25896 static void
25898 {
25904 }
25905 \f
25906 /* Check whether x86 address PARTS is a pc-relative address. */
25908 static bool
25910 {
25918 {
25920 {
25937 }
25938 }
25940 }
25942 /* Calculate the length of the memory address in the instruction encoding.
25943 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25944 or other prefixes. We never generate addr32 prefix for LEA insn. */
25946 int
25948 {
25965 /* If this is not LEA instruction, add the length of addr32 prefix. */
25970 len++;
25984 /* Rule of thumb:
25985 - esp as the base always wants an index,
25986 - ebp as the base always wants a displacement,
25987 - r12 as the base always wants an index,
25988 - r13 as the base always wants a displacement. */
25990 /* Register Indirect. */
25992 {
25993 /* esp (for its index) and ebp (for its displacement) need
25994 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25995 code. */
26002 len++;
26003 }
26005 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
26006 is not disp32, but disp32(%rip), so for disp32
26007 SIB byte is needed, unless print_operand_address
26008 optimizes it into disp32(%rip) or (%rip) is implied
26009 by UNSPEC. */
26011 {
26014 len++;
26015 }
26016 else
26017 {
26018 /* Find the length of the displacement constant. */
26020 {
26023 else
26025 }
26026 /* ebp always wants a displacement. Similarly r13. */
26028 len++;
26030 /* An index requires the two-byte modrm form.... */
26032 /* ...like esp (or r12), which always wants an index. */
26036 len++;
26037 }
26040 }
26042 /* Compute default value for "length_immediate" attribute. When SHORTFORM
26043 is set, expect that insn have 8bit immediate alternative. */
26044 int
26046 {
26052 {
26057 {
26060 {
26072 }
26074 {
26077 }
26078 }
26080 {
26090 /* Immediates for DImode instructions are encoded
26091 as 32bit sign extended values. */
26097 }
26098 }
26100 }
26102 /* Compute default value for "length_address" attribute. */
26103 int
26105 {
26109 {
26120 }
26125 {
26128 {
26133 constraints++;
26136 ;
26137 /* Skip ignored operands. */
26140 }
26142 }
26144 }
26146 /* Compute default value for "length_vex" attribute. It includes
26147 2 or 3 byte VEX prefix and 1 opcode byte. */
26149 int
26152 {
26155 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
26156 byte VEX prefix. */
26160 /* We can always use 2 byte VEX prefix in 32bit. */
26168 {
26169 /* REX.W bit uses 3 byte VEX prefix. */
26173 }
26174 else
26175 {
26176 /* REX.X or REX.B bits use 3 byte VEX prefix. */
26180 }
26183 }
26184 \f
26185 /* Return the maximum number of instructions a cpu can issue. */
26187 static int
26189 {
26191 {
26224 }
26225 }
26227 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
26228 by DEP_INSN and nothing set by DEP_INSN. */
26230 static bool
26232 {
26235 /* Simplify the test for uninteresting insns. */
26243 {
26246 }
26251 {
26254 }
26255 else
26261 /* This test is true if the dependent insn reads the flags but
26262 not any other potentially set register. */
26270 }
26272 /* Return true iff USE_INSN has a memory address with operands set by
26273 SET_INSN. */
26275 bool
26277 {
26282 {
26285 }
26287 }
26289 /* Helper function for exact_store_load_dependency.
26290 Return true if addr is found in insn. */
26291 static bool
26293 {
26300 {
26306 CASE_CONST_ANY:
26315 }
26319 {
26321 {
26331 }
26332 }
26334 }
26336 /* Return true if there exists exact dependency for store & load, i.e.
26337 the same memory address is used in them. */
26338 static bool
26340 {
26354 }
26356 static int
26358 {
26364 /* Anti and output dependencies have zero cost on all CPUs. */
26370 /* If we can't recognize the insns, we can't really do anything. */
26378 {
26381 /* Address Generation Interlock adds a cycle of latency. */
26383 {
26394 }
26398 /* ??? Compares pair with jump/setcc. */
26402 /* Floating point stores require value to be ready one cycle earlier. */
26410 /* INT->FP conversion is expensive. */
26414 /* There is one cycle extra latency between an FP op and a store. */
26424 /* Show ability of reorder buffer to hide latency of load by executing
26425 in parallel with previous instruction in case
26426 previous instruction is not needed to compute the address. */
26429 {
26430 /* Claim moves to take one cycle, as core can issue one load
26431 at time and the next load can start cycle later. */
26436 cost--;
26437 }
26441 /* The esp dependency is resolved before
26442 the instruction is really finished. */
26447 /* INT->FP conversion is expensive. */
26453 /* Show ability of reorder buffer to hide latency of load by executing
26454 in parallel with previous instruction in case
26455 previous instruction is not needed to compute the address. */
26458 {
26459 /* Claim moves to take one cycle, as core can issue one load
26460 at time and the next load can start cycle later. */
26466 else
26468 }
26479 /* Stack engine allows to execute push&pop instructions in parall. */
26483 /* FALLTHRU */
26489 /* Show ability of reorder buffer to hide latency of load by executing
26490 in parallel with previous instruction in case
26491 previous instruction is not needed to compute the address. */
26494 {
26498 /* Because of the difference between the length of integer and
26499 floating unit pipeline preparation stages, the memory operands
26500 for floating point are cheaper.
26502 ??? For Athlon it the difference is most probably 2. */
26505 else
26510 else
26512 }
26519 /* Stack engine allows to execute push&pop instructions in parall. */
26526 /* Show ability of reorder buffer to hide latency of load by executing
26527 in parallel with previous instruction in case
26528 previous instruction is not needed to compute the address. */
26531 {
26534 else
26536 }
26545 /* Increase cost of integer loads. */
26548 {
26551 {
26554 else
26555 {
26556 /* Increase cost of ld/st for short int types only
26557 because of store forwarding issue. */
26561 {
26562 /* Increase cost of store/load insn if exact
26563 dependence exists and it is load insn. */
26568 }
26569 }
26570 }
26571 }
26575 }
26578 }
26580 /* How many alternative schedules to try. This should be as wide as the
26581 scheduling freedom in the DFA, but no wider. Making this value too
26582 large results extra work for the scheduler. */
26584 static int
26586 {
26588 {
26601 /* We use lookahead value 4 for BD both before and after reload
26602 schedules. Plan is to have value 8 included for O3. */
26613 /* Generally, we want haifa-sched:max_issue() to look ahead as far
26614 as many instructions can be executed on a cycle, i.e.,
26615 issue_rate. I wonder why tuning for many CPUs does not do this. */
26618 /* Don't use lookahead for pre-reload schedule to save compile time. */
26623 }
26624 }
26626 /* Return true if target platform supports macro-fusion. */
26628 static bool
26630 {
26632 }
26634 /* Check whether current microarchitecture support macro fusion
26635 for insn pair "CONDGEN + CONDJMP". Refer to
26636 "Intel Architectures Optimization Reference Manual". */
26638 static bool
26640 {
26661 {
26666 {
26670 else
26672 }
26673 }
26680 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
26681 supported. */
26688 /* No fusion for RIP-relative address. */
26695 ix86_address parts;
26701 }
26706 /* Check whether conditional jump use Sign or Overflow Flags. */
26714 /* Return true for TYPE_TEST and TYPE_ICMP. */
26719 /* The following is the case that macro-fusion for alu + jmp. */
26723 /* No fusion for alu op with memory destination operand. */
26728 /* Macro-fusion for inc/dec + unsigned conditional jump is not
26729 supported. */
26738 }
26740 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
26741 execution. It is applied if
26742 (1) IMUL instruction is on the top of list;
26743 (2) There exists the only producer of independent IMUL instruction in
26744 ready list.
26745 Return index of IMUL producer if it was found and -1 otherwise. */
26746 static int
26748 {
26751 sd_iterator_def sd_it;
26752 dep_t dep;
26759 /* Check that IMUL instruction is on the top of ready list. */
26768 /* Search for producer of independent IMUL instruction. */
26770 {
26774 /* Skip IMUL instruction. */
26784 {
26785 rtx con;
26796 {
26797 sd_iterator_def sd_it1;
26798 dep_t dep1;
26799 /* Check if there is no other dependee for IMUL. */
26802 {
26803 rtx pro;
26809 }
26812 }
26813 }
26816 }
26818 }
26820 /* Try to find the best candidate on the top of ready list if two insns
26821 have the same priority - candidate is best if its dependees were
26822 scheduled earlier. Applied for Silvermont only.
26823 Return true if top 2 insns must be interchanged. */
26824 static bool
26826 {
26829 rtx set;
26830 sd_iterator_def sd_it;
26831 dep_t dep;
26834 #define INSN_TICK(INSN) (HID (INSN)->tick)
26855 {
26858 /* Determine winner more precise. */
26860 {
26861 rtx pro;
26867 }
26869 {
26870 rtx pro;
26876 }
26879 {
26880 /* Determine winner - load must win. */
26886 }
26888 }
26890 #undef INSN_TICK
26891 }
26893 /* Perform possible reodering of ready list for Atom/Silvermont only.
26894 Return issue rate. */
26895 static int
26898 {
26905 /* Set up issue rate. */
26908 /* Do reodering for BONNELL/SILVERMONT only. */
26912 /* Nothing to do if ready list contains only 1 instruction. */
26916 /* Do reodering for post-reload scheduler only. */
26921 {
26926 /* Put IMUL producer (ready[index]) at the top of ready list. */
26932 }
26934 /* Skip selective scheduling since HID is not populated in it. */
26938 {
26942 /* Swap 2 top elements of ready list. */
26946 }
26948 }
26950 static bool
26953 /* Returns true if lhs of insn is HW function argument register and set up
26954 is_spilled to true if it is likely spilled HW register. */
26955 static bool
26957 {
26958 rtx dst;
26962 /* Call instructions are not movable, ignore it. */
26973 {
26974 /* Is it likely spilled HW register? */
26979 }
26981 }
26983 /* Add output dependencies for chain of function adjacent arguments if only
26984 there is a move to likely spilled HW register. Return first argument
26985 if at least one dependence was added or NULL otherwise. */
26988 {
26996 /* Find nearest to call argument passing instruction. */
26998 {
27007 }
27011 {
27018 {
27021 }
27023 {
27024 /* Add output depdendence between two function arguments if chain
27025 of output arguments contains likely spilled HW registers. */
27029 }
27030 else
27032 }
27036 }
27038 /* Add output or anti dependency from insn to first_arg to restrict its code
27039 motion. */
27040 static void
27042 {
27043 rtx set;
27044 rtx tmp;
27046 /* Add anti dependencies for bounds stores. */
27051 {
27054 }
27061 {
27062 /* Add output dependency to the first function argument. */
27065 }
27066 /* Add anti dependency. */
27068 }
27070 /* Avoid cross block motion of function argument through adding dependency
27071 from the first non-jump instruction in bb. */
27072 static void
27074 {
27078 {
27080 {
27083 {
27086 }
27087 }
27091 }
27092 }
27094 /* Hook for pre-reload schedule - avoid motion of function arguments
27095 passed in likely spilled HW registers. */
27096 static void
27098 {
27107 {
27110 {
27111 /* Add dependee for first argument to predecessors if only
27112 region contains more than one block. */
27116 /* Skip trivial regions and region head blocks that can have
27117 predecessors outside of region. */
27119 {
27120 edge e;
27121 edge_iterator ei;
27123 /* Regions are SCCs with the exception of selective
27124 scheduling with pipelining of outer blocks enabled.
27125 So also check that immediate predecessors of a non-head
27126 block are in the same region. */
27128 {
27129 /* Avoid creating of loop-carried dependencies through
27130 using topological ordering in the region. */
27134 }
27135 }
27139 }
27140 }
27143 }
27145 /* Hook for pre-reload schedule - set priority of moves from likely spilled
27146 HW registers to maximum, to schedule them at soon as possible. These are
27147 moves from function argument registers at the top of the function entry
27148 and moves from function return value registers after call. */
27149 static int
27151 {
27152 rtx set;
27162 {
27169 }
27172 }
27174 /* Model decoder of Core 2/i7.
27175 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
27176 track the instruction fetch block boundaries and make sure that long
27177 (9+ bytes) instructions are assigned to D0. */
27179 /* Maximum length of an insn that can be handled by
27180 a secondary decoder unit. '8' for Core 2/i7. */
27183 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
27184 '16' for Core 2/i7. */
27187 /* Maximum number of instructions decoder can handle per cycle.
27188 '6' for Core 2/i7. */
27192 ix86_first_cycle_multipass_data_t;
27194 const_ix86_first_cycle_multipass_data_t;
27196 /* A variable to store target state across calls to max_issue within
27197 one cycle. */
27201 /* Initialize DATA. */
27202 static void
27204 {
27205 ix86_first_cycle_multipass_data_t data
27212 }
27214 /* Advancing the cycle; reset ifetch block counts. */
27215 static void
27217 {
27224 }
27228 /* Filter out insns from ready_try that the core will not be able to issue
27229 on current cycle due to decoder. */
27230 static void
27231 core2i7_first_cycle_multipass_filter_ready_try
27234 {
27236 {
27247 (!first_cycle_insn_p
27249 /* ... or it would not fit into the ifetch block ... */
27251 /* ... or the decoder is full already ... */
27253 /* ... mask the insn out. */
27254 {
27259 }
27260 }
27261 }
27263 /* Prepare for a new round of multipass lookahead scheduling. */
27264 static void
27268 {
27269 ix86_first_cycle_multipass_data_t data
27271 const_ix86_first_cycle_multipass_data_t prev_data
27274 /* Restore the state from the end of the previous round. */
27278 /* Filter instructions that cannot be issued on current cycle due to
27279 decoder restrictions. */
27281 first_cycle_insn_p);
27282 }
27284 /* INSN is being issued in current solution. Account for its impact on
27285 the decoder model. */
27286 static void
27290 {
27291 ix86_first_cycle_multipass_data_t data
27293 const_ix86_first_cycle_multipass_data_t prev_data
27303 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
27305 {
27308 }
27310 {
27314 }
27317 /* Filter out insns from ready_try that the core will not be able to issue
27318 on current cycle due to decoder. */
27321 }
27323 /* Revert the effect on ready_try. */
27324 static void
27328 {
27329 const_ix86_first_cycle_multipass_data_t data
27332 sbitmap_iterator sbi;
27336 {
27338 }
27339 }
27341 /* Save the result of multipass lookahead scheduling for the next round. */
27342 static void
27344 {
27345 const_ix86_first_cycle_multipass_data_t data
27347 ix86_first_cycle_multipass_data_t next_data
27351 {
27354 }
27355 }
27357 /* Deallocate target data. */
27358 static void
27360 {
27361 ix86_first_cycle_multipass_data_t data
27365 {
27369 }
27370 }
27372 /* Prepare for scheduling pass. */
27373 static void
27375 {
27376 /* Install scheduling hooks for current CPU. Some of these hooks are used
27377 in time-critical parts of the scheduler, so we only set them up when
27378 they are actually used. */
27380 {
27385 /* Do not perform multipass scheduling for pre-reload schedule
27386 to save compile time. */
27388 {
27404 /* Set decoder parameters. */
27409 }
27410 /* ... Fall through ... */
27420 }
27421 }
27423 \f
27424 /* Compute the alignment given to a constant that is being placed in memory.
27425 EXP is the constant and ALIGN is the alignment that the object would
27426 ordinarily have.
27427 The value of this function is used instead of that alignment to align
27428 the object. */
27430 int
27432 {
27435 {
27440 }
27446 }
27448 /* Compute the alignment for a variable for Intel MCU psABI. TYPE is
27449 the data type, and ALIGN is the alignment that the object would
27450 ordinarily have. */
27452 static int
27454 {
27460 /* Intel MCU psABI specifies scalar types > 4 bytes aligned to 4
27461 bytes. */
27464 {
27473 }
27474 }
27476 /* Compute the alignment for a static variable.
27477 TYPE is the data type, and ALIGN is the alignment that
27478 the object would ordinarily have. The value of this function is used
27479 instead of that alignment to align the object. */
27481 int
27483 {
27484 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
27485 for symbols from other compilation units or symbols that don't need
27486 to bind locally. In order to preserve some ABI compatibility with
27487 those compilers, ensure we don't decrease alignment from what we
27488 used to assume. */
27492 /* A data structure, equal or greater than the size of a cache line
27493 (64 bytes in the Pentium 4 and other recent Intel processors, including
27494 processors based on Intel Core microarchitecture) should be aligned
27495 so that its base address is a multiple of a cache line size. */
27497 int max_align
27504 {
27508 }
27517 {
27524 }
27526 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27527 to 16byte boundary. */
27529 {
27536 }
27542 {
27547 }
27549 {
27556 }
27561 {
27566 }
27569 {
27574 }
27577 }
27579 /* Compute the alignment for a local variable or a stack slot. EXP is
27580 the data type or decl itself, MODE is the widest mode available and
27581 ALIGN is the alignment that the object would ordinarily have. The
27582 value of this macro is used instead of that alignment to align the
27583 object. */
27585 unsigned int
27588 {
27592 {
27595 }
27596 else
27597 {
27600 }
27602 /* Don't do dynamic stack realignment for long long objects with
27603 -mpreferred-stack-boundary=2. */
27612 /* If TYPE is NULL, we are allocating a stack slot for caller-save
27613 register in MODE. We will return the largest alignment of XF
27614 and DF. */
27616 {
27620 }
27622 /* Don't increase alignment for Intel MCU psABI. */
27626 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27627 to 16byte boundary. Exact wording is:
27629 An array uses the same alignment as its elements, except that a local or
27630 global array variable of length at least 16 bytes or
27631 a C99 variable-length array variable always has alignment of at least 16 bytes.
27633 This was added to allow use of aligned SSE instructions at arrays. This
27634 rule is meant for static storage (where compiler can not do the analysis
27635 by itself). We follow it for automatic variables only when convenient.
27636 We fully control everything in the function compiled and functions from
27637 other unit can not rely on the alignment.
27639 Exclude va_list type. It is the common case of local array where
27640 we can not benefit from the alignment.
27642 TODO: Probably one should optimize for size only when var is not escaping. */
27645 {
27655 }
27657 {
27662 }
27664 {
27670 }
27675 {
27680 }
27683 {
27689 }
27691 }
27693 /* Compute the minimum required alignment for dynamic stack realignment
27694 purposes for a local variable, parameter or a stack slot. EXP is
27695 the data type or decl itself, MODE is its mode and ALIGN is the
27696 alignment that the object would ordinarily have. */
27698 unsigned int
27701 {
27705 {
27708 }
27709 else
27710 {
27713 }
27718 /* Don't do dynamic stack realignment for long long objects with
27719 -mpreferred-stack-boundary=2. */
27726 }
27727 \f
27728 /* Find a location for the static chain incoming to a nested function.
27729 This is a register, unless all free registers are used by arguments. */
27731 static rtx
27733 {
27736 /* While this function won't be called by the middle-end when a static
27737 chain isn't needed, it's also used throughout the backend so it's
27738 easiest to keep this check centralized. */
27743 {
27744 /* We always use R10 in 64-bit mode. */
27746 }
27747 else
27748 {
27752 /* By default in 32-bit mode we use ECX to pass the static chain. */
27756 {
27759 }
27760 else
27761 {
27764 }
27768 {
27769 /* Fastcall functions use ecx/edx for arguments, which leaves
27770 us with EAX for the static chain.
27771 Thiscall functions use ecx for arguments, which also
27772 leaves us with EAX for the static chain. */
27774 }
27776 {
27777 /* Thiscall functions use ecx for arguments, which leaves
27778 us with EAX and EDX for the static chain.
27779 We are using for abi-compatibility EAX. */
27781 }
27783 {
27784 /* For regparm 3, we have no free call-clobbered registers in
27785 which to store the static chain. In order to implement this,
27786 we have the trampoline push the static chain to the stack.
27787 However, we can't push a value below the return address when
27788 we call the nested function directly, so we have to use an
27789 alternate entry point. For this we use ESI, and have the
27790 alternate entry point push ESI, so that things appear the
27791 same once we're executing the nested function. */
27793 {
27799 }
27801 }
27802 }
27805 }
27807 /* Emit RTL insns to initialize the variable parts of a trampoline.
27808 FNDECL is the decl of the target address; M_TRAMP is a MEM for
27809 the trampoline, and CHAIN_VALUE is an RTX for the static chain
27810 to be passed to the target function. */
27812 static void
27814 {
27822 {
27825 /* Load the function address to r11. Try to load address using
27826 the shorter movl instead of movabs. We may want to support
27827 movq for kernel mode, but kernel does not use trampolines at
27828 the moment. FNADDR is a 32bit address and may not be in
27829 DImode when ptr_mode == SImode. Always use movl in this
27830 case. */
27833 {
27842 }
27843 else
27844 {
27851 }
27853 /* Load static chain using movabs to r10. Use the shorter movl
27854 instead of movabs when ptr_mode == SImode. */
27856 {
27859 }
27860 else
27861 {
27864 }
27873 /* Jump to r11; the last (unused) byte is a nop, only there to
27874 pad the write out to a single 32-bit store. */
27878 }
27879 else
27880 {
27883 /* Depending on the static chain location, either load a register
27884 with a constant, or push the constant to the stack. All of the
27885 instructions are the same size. */
27888 {
27890 {
27897 }
27898 }
27899 else
27914 /* Compute offset from the end of the jmp to the target function.
27915 In the case in which the trampoline stores the static chain on
27916 the stack, we need to skip the first insn which pushes the
27917 (call-saved) register static chain; this push is 1 byte. */
27924 }
27928 #ifdef HAVE_ENABLE_EXECUTE_STACK
27929 #ifdef CHECK_EXECUTE_STACK_ENABLED
27931 #endif
27934 #endif
27935 }
27936 \f
27937 /* The following file contains several enumerations and data structures
27938 built from the definitions in i386-builtin-types.def. */
27942 /* Table for the ix86 builtin non-function types. */
27945 /* Retrieve an element from the above table, building some of
27946 the types lazily. */
27948 static tree
27950 {
27962 {
27963 machine_mode mode;
27970 }
27971 else
27972 {
27978 else
27986 }
27990 }
27992 /* Table for the ix86 builtin function types. */
27995 /* Retrieve an element from the above table, building some of
27996 the types lazily. */
27998 static tree
28000 {
28001 tree type;
28010 {
28018 {
28021 }
28024 }
28025 else
28026 {
28032 }
28036 }
28039 /* Codes for all the SSE/MMX builtins. */
28040 enum ix86_builtins
28041 {
28042 IX86_BUILTIN_ADDPS,
28043 IX86_BUILTIN_ADDSS,
28044 IX86_BUILTIN_DIVPS,
28045 IX86_BUILTIN_DIVSS,
28046 IX86_BUILTIN_MULPS,
28047 IX86_BUILTIN_MULSS,
28048 IX86_BUILTIN_SUBPS,
28049 IX86_BUILTIN_SUBSS,
28051 IX86_BUILTIN_CMPEQPS,
28052 IX86_BUILTIN_CMPLTPS,
28053 IX86_BUILTIN_CMPLEPS,
28054 IX86_BUILTIN_CMPGTPS,
28055 IX86_BUILTIN_CMPGEPS,
28056 IX86_BUILTIN_CMPNEQPS,
28057 IX86_BUILTIN_CMPNLTPS,
28058 IX86_BUILTIN_CMPNLEPS,
28059 IX86_BUILTIN_CMPNGTPS,
28060 IX86_BUILTIN_CMPNGEPS,
28061 IX86_BUILTIN_CMPORDPS,
28062 IX86_BUILTIN_CMPUNORDPS,
28063 IX86_BUILTIN_CMPEQSS,
28064 IX86_BUILTIN_CMPLTSS,
28065 IX86_BUILTIN_CMPLESS,
28066 IX86_BUILTIN_CMPNEQSS,
28067 IX86_BUILTIN_CMPNLTSS,
28068 IX86_BUILTIN_CMPNLESS,
28069 IX86_BUILTIN_CMPORDSS,
28070 IX86_BUILTIN_CMPUNORDSS,
28072 IX86_BUILTIN_COMIEQSS,
28073 IX86_BUILTIN_COMILTSS,
28074 IX86_BUILTIN_COMILESS,
28075 IX86_BUILTIN_COMIGTSS,
28076 IX86_BUILTIN_COMIGESS,
28077 IX86_BUILTIN_COMINEQSS,
28078 IX86_BUILTIN_UCOMIEQSS,
28079 IX86_BUILTIN_UCOMILTSS,
28080 IX86_BUILTIN_UCOMILESS,
28081 IX86_BUILTIN_UCOMIGTSS,
28082 IX86_BUILTIN_UCOMIGESS,
28083 IX86_BUILTIN_UCOMINEQSS,
28085 IX86_BUILTIN_CVTPI2PS,
28086 IX86_BUILTIN_CVTPS2PI,
28087 IX86_BUILTIN_CVTSI2SS,
28088 IX86_BUILTIN_CVTSI642SS,
28089 IX86_BUILTIN_CVTSS2SI,
28090 IX86_BUILTIN_CVTSS2SI64,
28091 IX86_BUILTIN_CVTTPS2PI,
28092 IX86_BUILTIN_CVTTSS2SI,
28093 IX86_BUILTIN_CVTTSS2SI64,
28095 IX86_BUILTIN_MAXPS,
28096 IX86_BUILTIN_MAXSS,
28097 IX86_BUILTIN_MINPS,
28098 IX86_BUILTIN_MINSS,
28100 IX86_BUILTIN_LOADUPS,
28101 IX86_BUILTIN_STOREUPS,
28102 IX86_BUILTIN_MOVSS,
28104 IX86_BUILTIN_MOVHLPS,
28105 IX86_BUILTIN_MOVLHPS,
28106 IX86_BUILTIN_LOADHPS,
28107 IX86_BUILTIN_LOADLPS,
28108 IX86_BUILTIN_STOREHPS,
28109 IX86_BUILTIN_STORELPS,
28111 IX86_BUILTIN_MASKMOVQ,
28112 IX86_BUILTIN_MOVMSKPS,
28113 IX86_BUILTIN_PMOVMSKB,
28115 IX86_BUILTIN_MOVNTPS,
28116 IX86_BUILTIN_MOVNTQ,
28118 IX86_BUILTIN_LOADDQU,
28119 IX86_BUILTIN_STOREDQU,
28121 IX86_BUILTIN_PACKSSWB,
28122 IX86_BUILTIN_PACKSSDW,
28123 IX86_BUILTIN_PACKUSWB,
28125 IX86_BUILTIN_PADDB,
28126 IX86_BUILTIN_PADDW,
28127 IX86_BUILTIN_PADDD,
28128 IX86_BUILTIN_PADDQ,
28129 IX86_BUILTIN_PADDSB,
28130 IX86_BUILTIN_PADDSW,
28131 IX86_BUILTIN_PADDUSB,
28132 IX86_BUILTIN_PADDUSW,
28133 IX86_BUILTIN_PSUBB,
28134 IX86_BUILTIN_PSUBW,
28135 IX86_BUILTIN_PSUBD,
28136 IX86_BUILTIN_PSUBQ,
28137 IX86_BUILTIN_PSUBSB,
28138 IX86_BUILTIN_PSUBSW,
28139 IX86_BUILTIN_PSUBUSB,
28140 IX86_BUILTIN_PSUBUSW,
28142 IX86_BUILTIN_PAND,
28143 IX86_BUILTIN_PANDN,
28144 IX86_BUILTIN_POR,
28145 IX86_BUILTIN_PXOR,
28147 IX86_BUILTIN_PAVGB,
28148 IX86_BUILTIN_PAVGW,
28150 IX86_BUILTIN_PCMPEQB,
28151 IX86_BUILTIN_PCMPEQW,
28152 IX86_BUILTIN_PCMPEQD,
28153 IX86_BUILTIN_PCMPGTB,
28154 IX86_BUILTIN_PCMPGTW,
28155 IX86_BUILTIN_PCMPGTD,
28157 IX86_BUILTIN_PMADDWD,
28159 IX86_BUILTIN_PMAXSW,
28160 IX86_BUILTIN_PMAXUB,
28161 IX86_BUILTIN_PMINSW,
28162 IX86_BUILTIN_PMINUB,
28164 IX86_BUILTIN_PMULHUW,
28165 IX86_BUILTIN_PMULHW,
28166 IX86_BUILTIN_PMULLW,
28168 IX86_BUILTIN_PSADBW,
28169 IX86_BUILTIN_PSHUFW,
28171 IX86_BUILTIN_PSLLW,
28172 IX86_BUILTIN_PSLLD,
28173 IX86_BUILTIN_PSLLQ,
28174 IX86_BUILTIN_PSRAW,
28175 IX86_BUILTIN_PSRAD,
28176 IX86_BUILTIN_PSRLW,
28177 IX86_BUILTIN_PSRLD,
28178 IX86_BUILTIN_PSRLQ,
28179 IX86_BUILTIN_PSLLWI,
28180 IX86_BUILTIN_PSLLDI,
28181 IX86_BUILTIN_PSLLQI,
28182 IX86_BUILTIN_PSRAWI,
28183 IX86_BUILTIN_PSRADI,
28184 IX86_BUILTIN_PSRLWI,
28185 IX86_BUILTIN_PSRLDI,
28186 IX86_BUILTIN_PSRLQI,
28188 IX86_BUILTIN_PUNPCKHBW,
28189 IX86_BUILTIN_PUNPCKHWD,
28190 IX86_BUILTIN_PUNPCKHDQ,
28191 IX86_BUILTIN_PUNPCKLBW,
28192 IX86_BUILTIN_PUNPCKLWD,
28193 IX86_BUILTIN_PUNPCKLDQ,
28195 IX86_BUILTIN_SHUFPS,
28197 IX86_BUILTIN_RCPPS,
28198 IX86_BUILTIN_RCPSS,
28199 IX86_BUILTIN_RSQRTPS,
28200 IX86_BUILTIN_RSQRTPS_NR,
28201 IX86_BUILTIN_RSQRTSS,
28202 IX86_BUILTIN_RSQRTF,
28203 IX86_BUILTIN_SQRTPS,
28204 IX86_BUILTIN_SQRTPS_NR,
28205 IX86_BUILTIN_SQRTSS,
28207 IX86_BUILTIN_UNPCKHPS,
28208 IX86_BUILTIN_UNPCKLPS,
28210 IX86_BUILTIN_ANDPS,
28211 IX86_BUILTIN_ANDNPS,
28212 IX86_BUILTIN_ORPS,
28213 IX86_BUILTIN_XORPS,
28215 IX86_BUILTIN_EMMS,
28216 IX86_BUILTIN_LDMXCSR,
28217 IX86_BUILTIN_STMXCSR,
28218 IX86_BUILTIN_SFENCE,
28220 IX86_BUILTIN_FXSAVE,
28221 IX86_BUILTIN_FXRSTOR,
28222 IX86_BUILTIN_FXSAVE64,
28223 IX86_BUILTIN_FXRSTOR64,
28225 IX86_BUILTIN_XSAVE,
28226 IX86_BUILTIN_XRSTOR,
28227 IX86_BUILTIN_XSAVE64,
28228 IX86_BUILTIN_XRSTOR64,
28230 IX86_BUILTIN_XSAVEOPT,
28231 IX86_BUILTIN_XSAVEOPT64,
28233 IX86_BUILTIN_XSAVEC,
28234 IX86_BUILTIN_XSAVEC64,
28236 IX86_BUILTIN_XSAVES,
28237 IX86_BUILTIN_XRSTORS,
28238 IX86_BUILTIN_XSAVES64,
28239 IX86_BUILTIN_XRSTORS64,
28241 /* 3DNow! Original */
28242 IX86_BUILTIN_FEMMS,
28243 IX86_BUILTIN_PAVGUSB,
28244 IX86_BUILTIN_PF2ID,
28245 IX86_BUILTIN_PFACC,
28246 IX86_BUILTIN_PFADD,
28247 IX86_BUILTIN_PFCMPEQ,
28248 IX86_BUILTIN_PFCMPGE,
28249 IX86_BUILTIN_PFCMPGT,
28250 IX86_BUILTIN_PFMAX,
28251 IX86_BUILTIN_PFMIN,
28252 IX86_BUILTIN_PFMUL,
28253 IX86_BUILTIN_PFRCP,
28254 IX86_BUILTIN_PFRCPIT1,
28255 IX86_BUILTIN_PFRCPIT2,
28256 IX86_BUILTIN_PFRSQIT1,
28257 IX86_BUILTIN_PFRSQRT,
28258 IX86_BUILTIN_PFSUB,
28259 IX86_BUILTIN_PFSUBR,
28260 IX86_BUILTIN_PI2FD,
28261 IX86_BUILTIN_PMULHRW,
28263 /* 3DNow! Athlon Extensions */
28264 IX86_BUILTIN_PF2IW,
28265 IX86_BUILTIN_PFNACC,
28266 IX86_BUILTIN_PFPNACC,
28267 IX86_BUILTIN_PI2FW,
28268 IX86_BUILTIN_PSWAPDSI,
28269 IX86_BUILTIN_PSWAPDSF,
28271 /* SSE2 */
28272 IX86_BUILTIN_ADDPD,
28273 IX86_BUILTIN_ADDSD,
28274 IX86_BUILTIN_DIVPD,
28275 IX86_BUILTIN_DIVSD,
28276 IX86_BUILTIN_MULPD,
28277 IX86_BUILTIN_MULSD,
28278 IX86_BUILTIN_SUBPD,
28279 IX86_BUILTIN_SUBSD,
28281 IX86_BUILTIN_CMPEQPD,
28282 IX86_BUILTIN_CMPLTPD,
28283 IX86_BUILTIN_CMPLEPD,
28284 IX86_BUILTIN_CMPGTPD,
28285 IX86_BUILTIN_CMPGEPD,
28286 IX86_BUILTIN_CMPNEQPD,
28287 IX86_BUILTIN_CMPNLTPD,
28288 IX86_BUILTIN_CMPNLEPD,
28289 IX86_BUILTIN_CMPNGTPD,
28290 IX86_BUILTIN_CMPNGEPD,
28291 IX86_BUILTIN_CMPORDPD,
28292 IX86_BUILTIN_CMPUNORDPD,
28293 IX86_BUILTIN_CMPEQSD,
28294 IX86_BUILTIN_CMPLTSD,
28295 IX86_BUILTIN_CMPLESD,
28296 IX86_BUILTIN_CMPNEQSD,
28297 IX86_BUILTIN_CMPNLTSD,
28298 IX86_BUILTIN_CMPNLESD,
28299 IX86_BUILTIN_CMPORDSD,
28300 IX86_BUILTIN_CMPUNORDSD,
28302 IX86_BUILTIN_COMIEQSD,
28303 IX86_BUILTIN_COMILTSD,
28304 IX86_BUILTIN_COMILESD,
28305 IX86_BUILTIN_COMIGTSD,
28306 IX86_BUILTIN_COMIGESD,
28307 IX86_BUILTIN_COMINEQSD,
28308 IX86_BUILTIN_UCOMIEQSD,
28309 IX86_BUILTIN_UCOMILTSD,
28310 IX86_BUILTIN_UCOMILESD,
28311 IX86_BUILTIN_UCOMIGTSD,
28312 IX86_BUILTIN_UCOMIGESD,
28313 IX86_BUILTIN_UCOMINEQSD,
28315 IX86_BUILTIN_MAXPD,
28316 IX86_BUILTIN_MAXSD,
28317 IX86_BUILTIN_MINPD,
28318 IX86_BUILTIN_MINSD,
28320 IX86_BUILTIN_ANDPD,
28321 IX86_BUILTIN_ANDNPD,
28322 IX86_BUILTIN_ORPD,
28323 IX86_BUILTIN_XORPD,
28325 IX86_BUILTIN_SQRTPD,
28326 IX86_BUILTIN_SQRTSD,
28328 IX86_BUILTIN_UNPCKHPD,
28329 IX86_BUILTIN_UNPCKLPD,
28331 IX86_BUILTIN_SHUFPD,
28333 IX86_BUILTIN_LOADUPD,
28334 IX86_BUILTIN_STOREUPD,
28335 IX86_BUILTIN_MOVSD,
28337 IX86_BUILTIN_LOADHPD,
28338 IX86_BUILTIN_LOADLPD,
28340 IX86_BUILTIN_CVTDQ2PD,
28341 IX86_BUILTIN_CVTDQ2PS,
28343 IX86_BUILTIN_CVTPD2DQ,
28344 IX86_BUILTIN_CVTPD2PI,
28345 IX86_BUILTIN_CVTPD2PS,
28346 IX86_BUILTIN_CVTTPD2DQ,
28347 IX86_BUILTIN_CVTTPD2PI,
28349 IX86_BUILTIN_CVTPI2PD,
28350 IX86_BUILTIN_CVTSI2SD,
28351 IX86_BUILTIN_CVTSI642SD,
28353 IX86_BUILTIN_CVTSD2SI,
28354 IX86_BUILTIN_CVTSD2SI64,
28355 IX86_BUILTIN_CVTSD2SS,
28356 IX86_BUILTIN_CVTSS2SD,
28357 IX86_BUILTIN_CVTTSD2SI,
28358 IX86_BUILTIN_CVTTSD2SI64,
28360 IX86_BUILTIN_CVTPS2DQ,
28361 IX86_BUILTIN_CVTPS2PD,
28362 IX86_BUILTIN_CVTTPS2DQ,
28364 IX86_BUILTIN_MOVNTI,
28365 IX86_BUILTIN_MOVNTI64,
28366 IX86_BUILTIN_MOVNTPD,
28367 IX86_BUILTIN_MOVNTDQ,
28369 IX86_BUILTIN_MOVQ128,
28371 /* SSE2 MMX */
28372 IX86_BUILTIN_MASKMOVDQU,
28373 IX86_BUILTIN_MOVMSKPD,
28374 IX86_BUILTIN_PMOVMSKB128,
28376 IX86_BUILTIN_PACKSSWB128,
28377 IX86_BUILTIN_PACKSSDW128,
28378 IX86_BUILTIN_PACKUSWB128,
28380 IX86_BUILTIN_PADDB128,
28381 IX86_BUILTIN_PADDW128,
28382 IX86_BUILTIN_PADDD128,
28383 IX86_BUILTIN_PADDQ128,
28384 IX86_BUILTIN_PADDSB128,
28385 IX86_BUILTIN_PADDSW128,
28386 IX86_BUILTIN_PADDUSB128,
28387 IX86_BUILTIN_PADDUSW128,
28388 IX86_BUILTIN_PSUBB128,
28389 IX86_BUILTIN_PSUBW128,
28390 IX86_BUILTIN_PSUBD128,
28391 IX86_BUILTIN_PSUBQ128,
28392 IX86_BUILTIN_PSUBSB128,
28393 IX86_BUILTIN_PSUBSW128,
28394 IX86_BUILTIN_PSUBUSB128,
28395 IX86_BUILTIN_PSUBUSW128,
28397 IX86_BUILTIN_PAND128,
28398 IX86_BUILTIN_PANDN128,
28399 IX86_BUILTIN_POR128,
28400 IX86_BUILTIN_PXOR128,
28402 IX86_BUILTIN_PAVGB128,
28403 IX86_BUILTIN_PAVGW128,
28405 IX86_BUILTIN_PCMPEQB128,
28406 IX86_BUILTIN_PCMPEQW128,
28407 IX86_BUILTIN_PCMPEQD128,
28408 IX86_BUILTIN_PCMPGTB128,
28409 IX86_BUILTIN_PCMPGTW128,
28410 IX86_BUILTIN_PCMPGTD128,
28412 IX86_BUILTIN_PMADDWD128,
28414 IX86_BUILTIN_PMAXSW128,
28415 IX86_BUILTIN_PMAXUB128,
28416 IX86_BUILTIN_PMINSW128,
28417 IX86_BUILTIN_PMINUB128,
28419 IX86_BUILTIN_PMULUDQ,
28420 IX86_BUILTIN_PMULUDQ128,
28421 IX86_BUILTIN_PMULHUW128,
28422 IX86_BUILTIN_PMULHW128,
28423 IX86_BUILTIN_PMULLW128,
28425 IX86_BUILTIN_PSADBW128,
28426 IX86_BUILTIN_PSHUFHW,
28427 IX86_BUILTIN_PSHUFLW,
28428 IX86_BUILTIN_PSHUFD,
28430 IX86_BUILTIN_PSLLDQI128,
28431 IX86_BUILTIN_PSLLWI128,
28432 IX86_BUILTIN_PSLLDI128,
28433 IX86_BUILTIN_PSLLQI128,
28434 IX86_BUILTIN_PSRAWI128,
28435 IX86_BUILTIN_PSRADI128,
28436 IX86_BUILTIN_PSRLDQI128,
28437 IX86_BUILTIN_PSRLWI128,
28438 IX86_BUILTIN_PSRLDI128,
28439 IX86_BUILTIN_PSRLQI128,
28441 IX86_BUILTIN_PSLLDQ128,
28442 IX86_BUILTIN_PSLLW128,
28443 IX86_BUILTIN_PSLLD128,
28444 IX86_BUILTIN_PSLLQ128,
28445 IX86_BUILTIN_PSRAW128,
28446 IX86_BUILTIN_PSRAD128,
28447 IX86_BUILTIN_PSRLW128,
28448 IX86_BUILTIN_PSRLD128,
28449 IX86_BUILTIN_PSRLQ128,
28451 IX86_BUILTIN_PUNPCKHBW128,
28452 IX86_BUILTIN_PUNPCKHWD128,
28453 IX86_BUILTIN_PUNPCKHDQ128,
28454 IX86_BUILTIN_PUNPCKHQDQ128,
28455 IX86_BUILTIN_PUNPCKLBW128,
28456 IX86_BUILTIN_PUNPCKLWD128,
28457 IX86_BUILTIN_PUNPCKLDQ128,
28458 IX86_BUILTIN_PUNPCKLQDQ128,
28460 IX86_BUILTIN_CLFLUSH,
28461 IX86_BUILTIN_MFENCE,
28462 IX86_BUILTIN_LFENCE,
28463 IX86_BUILTIN_PAUSE,
28465 IX86_BUILTIN_FNSTENV,
28466 IX86_BUILTIN_FLDENV,
28467 IX86_BUILTIN_FNSTSW,
28468 IX86_BUILTIN_FNCLEX,
28470 IX86_BUILTIN_BSRSI,
28471 IX86_BUILTIN_BSRDI,
28472 IX86_BUILTIN_RDPMC,
28473 IX86_BUILTIN_RDTSC,
28474 IX86_BUILTIN_RDTSCP,
28475 IX86_BUILTIN_ROLQI,
28476 IX86_BUILTIN_ROLHI,
28477 IX86_BUILTIN_RORQI,
28478 IX86_BUILTIN_RORHI,
28480 /* SSE3. */
28481 IX86_BUILTIN_ADDSUBPS,
28482 IX86_BUILTIN_HADDPS,
28483 IX86_BUILTIN_HSUBPS,
28484 IX86_BUILTIN_MOVSHDUP,
28485 IX86_BUILTIN_MOVSLDUP,
28486 IX86_BUILTIN_ADDSUBPD,
28487 IX86_BUILTIN_HADDPD,
28488 IX86_BUILTIN_HSUBPD,
28489 IX86_BUILTIN_LDDQU,
28491 IX86_BUILTIN_MONITOR,
28492 IX86_BUILTIN_MWAIT,
28494 /* SSSE3. */
28495 IX86_BUILTIN_PHADDW,
28496 IX86_BUILTIN_PHADDD,
28497 IX86_BUILTIN_PHADDSW,
28498 IX86_BUILTIN_PHSUBW,
28499 IX86_BUILTIN_PHSUBD,
28500 IX86_BUILTIN_PHSUBSW,
28501 IX86_BUILTIN_PMADDUBSW,
28502 IX86_BUILTIN_PMULHRSW,
28503 IX86_BUILTIN_PSHUFB,
28504 IX86_BUILTIN_PSIGNB,
28505 IX86_BUILTIN_PSIGNW,
28506 IX86_BUILTIN_PSIGND,
28507 IX86_BUILTIN_PALIGNR,
28508 IX86_BUILTIN_PABSB,
28509 IX86_BUILTIN_PABSW,
28510 IX86_BUILTIN_PABSD,
28512 IX86_BUILTIN_PHADDW128,
28513 IX86_BUILTIN_PHADDD128,
28514 IX86_BUILTIN_PHADDSW128,
28515 IX86_BUILTIN_PHSUBW128,
28516 IX86_BUILTIN_PHSUBD128,
28517 IX86_BUILTIN_PHSUBSW128,
28518 IX86_BUILTIN_PMADDUBSW128,
28519 IX86_BUILTIN_PMULHRSW128,
28520 IX86_BUILTIN_PSHUFB128,
28521 IX86_BUILTIN_PSIGNB128,
28522 IX86_BUILTIN_PSIGNW128,
28523 IX86_BUILTIN_PSIGND128,
28524 IX86_BUILTIN_PALIGNR128,
28525 IX86_BUILTIN_PABSB128,
28526 IX86_BUILTIN_PABSW128,
28527 IX86_BUILTIN_PABSD128,
28529 /* AMDFAM10 - SSE4A New Instructions. */
28530 IX86_BUILTIN_MOVNTSD,
28531 IX86_BUILTIN_MOVNTSS,
28532 IX86_BUILTIN_EXTRQI,
28533 IX86_BUILTIN_EXTRQ,
28534 IX86_BUILTIN_INSERTQI,
28535 IX86_BUILTIN_INSERTQ,
28537 /* SSE4.1. */
28538 IX86_BUILTIN_BLENDPD,
28539 IX86_BUILTIN_BLENDPS,
28540 IX86_BUILTIN_BLENDVPD,
28541 IX86_BUILTIN_BLENDVPS,
28542 IX86_BUILTIN_PBLENDVB128,
28543 IX86_BUILTIN_PBLENDW128,
28545 IX86_BUILTIN_DPPD,
28546 IX86_BUILTIN_DPPS,
28548 IX86_BUILTIN_INSERTPS128,
28550 IX86_BUILTIN_MOVNTDQA,
28551 IX86_BUILTIN_MPSADBW128,
28552 IX86_BUILTIN_PACKUSDW128,
28553 IX86_BUILTIN_PCMPEQQ,
28554 IX86_BUILTIN_PHMINPOSUW128,
28556 IX86_BUILTIN_PMAXSB128,
28557 IX86_BUILTIN_PMAXSD128,
28558 IX86_BUILTIN_PMAXUD128,
28559 IX86_BUILTIN_PMAXUW128,
28561 IX86_BUILTIN_PMINSB128,
28562 IX86_BUILTIN_PMINSD128,
28563 IX86_BUILTIN_PMINUD128,
28564 IX86_BUILTIN_PMINUW128,
28566 IX86_BUILTIN_PMOVSXBW128,
28567 IX86_BUILTIN_PMOVSXBD128,
28568 IX86_BUILTIN_PMOVSXBQ128,
28569 IX86_BUILTIN_PMOVSXWD128,
28570 IX86_BUILTIN_PMOVSXWQ128,
28571 IX86_BUILTIN_PMOVSXDQ128,
28573 IX86_BUILTIN_PMOVZXBW128,
28574 IX86_BUILTIN_PMOVZXBD128,
28575 IX86_BUILTIN_PMOVZXBQ128,
28576 IX86_BUILTIN_PMOVZXWD128,
28577 IX86_BUILTIN_PMOVZXWQ128,
28578 IX86_BUILTIN_PMOVZXDQ128,
28580 IX86_BUILTIN_PMULDQ128,
28581 IX86_BUILTIN_PMULLD128,
28583 IX86_BUILTIN_ROUNDSD,
28584 IX86_BUILTIN_ROUNDSS,
28586 IX86_BUILTIN_ROUNDPD,
28587 IX86_BUILTIN_ROUNDPS,
28589 IX86_BUILTIN_FLOORPD,
28590 IX86_BUILTIN_CEILPD,
28591 IX86_BUILTIN_TRUNCPD,
28592 IX86_BUILTIN_RINTPD,
28593 IX86_BUILTIN_ROUNDPD_AZ,
28595 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
28596 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
28597 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
28599 IX86_BUILTIN_FLOORPS,
28600 IX86_BUILTIN_CEILPS,
28601 IX86_BUILTIN_TRUNCPS,
28602 IX86_BUILTIN_RINTPS,
28603 IX86_BUILTIN_ROUNDPS_AZ,
28605 IX86_BUILTIN_FLOORPS_SFIX,
28606 IX86_BUILTIN_CEILPS_SFIX,
28607 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
28609 IX86_BUILTIN_PTESTZ,
28610 IX86_BUILTIN_PTESTC,
28611 IX86_BUILTIN_PTESTNZC,
28613 IX86_BUILTIN_VEC_INIT_V2SI,
28614 IX86_BUILTIN_VEC_INIT_V4HI,
28615 IX86_BUILTIN_VEC_INIT_V8QI,
28616 IX86_BUILTIN_VEC_EXT_V2DF,
28617 IX86_BUILTIN_VEC_EXT_V2DI,
28618 IX86_BUILTIN_VEC_EXT_V4SF,
28619 IX86_BUILTIN_VEC_EXT_V4SI,
28620 IX86_BUILTIN_VEC_EXT_V8HI,
28621 IX86_BUILTIN_VEC_EXT_V2SI,
28622 IX86_BUILTIN_VEC_EXT_V4HI,
28623 IX86_BUILTIN_VEC_EXT_V16QI,
28624 IX86_BUILTIN_VEC_SET_V2DI,
28625 IX86_BUILTIN_VEC_SET_V4SF,
28626 IX86_BUILTIN_VEC_SET_V4SI,
28627 IX86_BUILTIN_VEC_SET_V8HI,
28628 IX86_BUILTIN_VEC_SET_V4HI,
28629 IX86_BUILTIN_VEC_SET_V16QI,
28631 IX86_BUILTIN_VEC_PACK_SFIX,
28632 IX86_BUILTIN_VEC_PACK_SFIX256,
28634 /* SSE4.2. */
28635 IX86_BUILTIN_CRC32QI,
28636 IX86_BUILTIN_CRC32HI,
28637 IX86_BUILTIN_CRC32SI,
28638 IX86_BUILTIN_CRC32DI,
28640 IX86_BUILTIN_PCMPESTRI128,
28641 IX86_BUILTIN_PCMPESTRM128,
28642 IX86_BUILTIN_PCMPESTRA128,
28643 IX86_BUILTIN_PCMPESTRC128,
28644 IX86_BUILTIN_PCMPESTRO128,
28645 IX86_BUILTIN_PCMPESTRS128,
28646 IX86_BUILTIN_PCMPESTRZ128,
28647 IX86_BUILTIN_PCMPISTRI128,
28648 IX86_BUILTIN_PCMPISTRM128,
28649 IX86_BUILTIN_PCMPISTRA128,
28650 IX86_BUILTIN_PCMPISTRC128,
28651 IX86_BUILTIN_PCMPISTRO128,
28652 IX86_BUILTIN_PCMPISTRS128,
28653 IX86_BUILTIN_PCMPISTRZ128,
28655 IX86_BUILTIN_PCMPGTQ,
28657 /* AES instructions */
28658 IX86_BUILTIN_AESENC128,
28659 IX86_BUILTIN_AESENCLAST128,
28660 IX86_BUILTIN_AESDEC128,
28661 IX86_BUILTIN_AESDECLAST128,
28662 IX86_BUILTIN_AESIMC128,
28663 IX86_BUILTIN_AESKEYGENASSIST128,
28665 /* PCLMUL instruction */
28666 IX86_BUILTIN_PCLMULQDQ128,
28668 /* AVX */
28669 IX86_BUILTIN_ADDPD256,
28670 IX86_BUILTIN_ADDPS256,
28671 IX86_BUILTIN_ADDSUBPD256,
28672 IX86_BUILTIN_ADDSUBPS256,
28673 IX86_BUILTIN_ANDPD256,
28674 IX86_BUILTIN_ANDPS256,
28675 IX86_BUILTIN_ANDNPD256,
28676 IX86_BUILTIN_ANDNPS256,
28677 IX86_BUILTIN_BLENDPD256,
28678 IX86_BUILTIN_BLENDPS256,
28679 IX86_BUILTIN_BLENDVPD256,
28680 IX86_BUILTIN_BLENDVPS256,
28681 IX86_BUILTIN_DIVPD256,
28682 IX86_BUILTIN_DIVPS256,
28683 IX86_BUILTIN_DPPS256,
28684 IX86_BUILTIN_HADDPD256,
28685 IX86_BUILTIN_HADDPS256,
28686 IX86_BUILTIN_HSUBPD256,
28687 IX86_BUILTIN_HSUBPS256,
28688 IX86_BUILTIN_MAXPD256,
28689 IX86_BUILTIN_MAXPS256,
28690 IX86_BUILTIN_MINPD256,
28691 IX86_BUILTIN_MINPS256,
28692 IX86_BUILTIN_MULPD256,
28693 IX86_BUILTIN_MULPS256,
28694 IX86_BUILTIN_ORPD256,
28695 IX86_BUILTIN_ORPS256,
28696 IX86_BUILTIN_SHUFPD256,
28697 IX86_BUILTIN_SHUFPS256,
28698 IX86_BUILTIN_SUBPD256,
28699 IX86_BUILTIN_SUBPS256,
28700 IX86_BUILTIN_XORPD256,
28701 IX86_BUILTIN_XORPS256,
28702 IX86_BUILTIN_CMPSD,
28703 IX86_BUILTIN_CMPSS,
28704 IX86_BUILTIN_CMPPD,
28705 IX86_BUILTIN_CMPPS,
28706 IX86_BUILTIN_CMPPD256,
28707 IX86_BUILTIN_CMPPS256,
28708 IX86_BUILTIN_CVTDQ2PD256,
28709 IX86_BUILTIN_CVTDQ2PS256,
28710 IX86_BUILTIN_CVTPD2PS256,
28711 IX86_BUILTIN_CVTPS2DQ256,
28712 IX86_BUILTIN_CVTPS2PD256,
28713 IX86_BUILTIN_CVTTPD2DQ256,
28714 IX86_BUILTIN_CVTPD2DQ256,
28715 IX86_BUILTIN_CVTTPS2DQ256,
28716 IX86_BUILTIN_EXTRACTF128PD256,
28717 IX86_BUILTIN_EXTRACTF128PS256,
28718 IX86_BUILTIN_EXTRACTF128SI256,
28719 IX86_BUILTIN_VZEROALL,
28720 IX86_BUILTIN_VZEROUPPER,
28721 IX86_BUILTIN_VPERMILVARPD,
28722 IX86_BUILTIN_VPERMILVARPS,
28723 IX86_BUILTIN_VPERMILVARPD256,
28724 IX86_BUILTIN_VPERMILVARPS256,
28725 IX86_BUILTIN_VPERMILPD,
28726 IX86_BUILTIN_VPERMILPS,
28727 IX86_BUILTIN_VPERMILPD256,
28728 IX86_BUILTIN_VPERMILPS256,
28729 IX86_BUILTIN_VPERMIL2PD,
28730 IX86_BUILTIN_VPERMIL2PS,
28731 IX86_BUILTIN_VPERMIL2PD256,
28732 IX86_BUILTIN_VPERMIL2PS256,
28733 IX86_BUILTIN_VPERM2F128PD256,
28734 IX86_BUILTIN_VPERM2F128PS256,
28735 IX86_BUILTIN_VPERM2F128SI256,
28736 IX86_BUILTIN_VBROADCASTSS,
28737 IX86_BUILTIN_VBROADCASTSD256,
28738 IX86_BUILTIN_VBROADCASTSS256,
28739 IX86_BUILTIN_VBROADCASTPD256,
28740 IX86_BUILTIN_VBROADCASTPS256,
28741 IX86_BUILTIN_VINSERTF128PD256,
28742 IX86_BUILTIN_VINSERTF128PS256,
28743 IX86_BUILTIN_VINSERTF128SI256,
28744 IX86_BUILTIN_LOADUPD256,
28745 IX86_BUILTIN_LOADUPS256,
28746 IX86_BUILTIN_STOREUPD256,
28747 IX86_BUILTIN_STOREUPS256,
28748 IX86_BUILTIN_LDDQU256,
28749 IX86_BUILTIN_MOVNTDQ256,
28750 IX86_BUILTIN_MOVNTPD256,
28751 IX86_BUILTIN_MOVNTPS256,
28752 IX86_BUILTIN_LOADDQU256,
28753 IX86_BUILTIN_STOREDQU256,
28754 IX86_BUILTIN_MASKLOADPD,
28755 IX86_BUILTIN_MASKLOADPS,
28756 IX86_BUILTIN_MASKSTOREPD,
28757 IX86_BUILTIN_MASKSTOREPS,
28758 IX86_BUILTIN_MASKLOADPD256,
28759 IX86_BUILTIN_MASKLOADPS256,
28760 IX86_BUILTIN_MASKSTOREPD256,
28761 IX86_BUILTIN_MASKSTOREPS256,
28762 IX86_BUILTIN_MOVSHDUP256,
28763 IX86_BUILTIN_MOVSLDUP256,
28764 IX86_BUILTIN_MOVDDUP256,
28766 IX86_BUILTIN_SQRTPD256,
28767 IX86_BUILTIN_SQRTPS256,
28768 IX86_BUILTIN_SQRTPS_NR256,
28769 IX86_BUILTIN_RSQRTPS256,
28770 IX86_BUILTIN_RSQRTPS_NR256,
28772 IX86_BUILTIN_RCPPS256,
28774 IX86_BUILTIN_ROUNDPD256,
28775 IX86_BUILTIN_ROUNDPS256,
28777 IX86_BUILTIN_FLOORPD256,
28778 IX86_BUILTIN_CEILPD256,
28779 IX86_BUILTIN_TRUNCPD256,
28780 IX86_BUILTIN_RINTPD256,
28781 IX86_BUILTIN_ROUNDPD_AZ256,
28783 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
28784 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
28785 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
28787 IX86_BUILTIN_FLOORPS256,
28788 IX86_BUILTIN_CEILPS256,
28789 IX86_BUILTIN_TRUNCPS256,
28790 IX86_BUILTIN_RINTPS256,
28791 IX86_BUILTIN_ROUNDPS_AZ256,
28793 IX86_BUILTIN_FLOORPS_SFIX256,
28794 IX86_BUILTIN_CEILPS_SFIX256,
28795 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
28797 IX86_BUILTIN_UNPCKHPD256,
28798 IX86_BUILTIN_UNPCKLPD256,
28799 IX86_BUILTIN_UNPCKHPS256,
28800 IX86_BUILTIN_UNPCKLPS256,
28802 IX86_BUILTIN_SI256_SI,
28803 IX86_BUILTIN_PS256_PS,
28804 IX86_BUILTIN_PD256_PD,
28805 IX86_BUILTIN_SI_SI256,
28806 IX86_BUILTIN_PS_PS256,
28807 IX86_BUILTIN_PD_PD256,
28809 IX86_BUILTIN_VTESTZPD,
28810 IX86_BUILTIN_VTESTCPD,
28811 IX86_BUILTIN_VTESTNZCPD,
28812 IX86_BUILTIN_VTESTZPS,
28813 IX86_BUILTIN_VTESTCPS,
28814 IX86_BUILTIN_VTESTNZCPS,
28815 IX86_BUILTIN_VTESTZPD256,
28816 IX86_BUILTIN_VTESTCPD256,
28817 IX86_BUILTIN_VTESTNZCPD256,
28818 IX86_BUILTIN_VTESTZPS256,
28819 IX86_BUILTIN_VTESTCPS256,
28820 IX86_BUILTIN_VTESTNZCPS256,
28821 IX86_BUILTIN_PTESTZ256,
28822 IX86_BUILTIN_PTESTC256,
28823 IX86_BUILTIN_PTESTNZC256,
28825 IX86_BUILTIN_MOVMSKPD256,
28826 IX86_BUILTIN_MOVMSKPS256,
28828 /* AVX2 */
28829 IX86_BUILTIN_MPSADBW256,
28830 IX86_BUILTIN_PABSB256,
28831 IX86_BUILTIN_PABSW256,
28832 IX86_BUILTIN_PABSD256,
28833 IX86_BUILTIN_PACKSSDW256,
28834 IX86_BUILTIN_PACKSSWB256,
28835 IX86_BUILTIN_PACKUSDW256,
28836 IX86_BUILTIN_PACKUSWB256,
28837 IX86_BUILTIN_PADDB256,
28838 IX86_BUILTIN_PADDW256,
28839 IX86_BUILTIN_PADDD256,
28840 IX86_BUILTIN_PADDQ256,
28841 IX86_BUILTIN_PADDSB256,
28842 IX86_BUILTIN_PADDSW256,
28843 IX86_BUILTIN_PADDUSB256,
28844 IX86_BUILTIN_PADDUSW256,
28845 IX86_BUILTIN_PALIGNR256,
28846 IX86_BUILTIN_AND256I,
28847 IX86_BUILTIN_ANDNOT256I,
28848 IX86_BUILTIN_PAVGB256,
28849 IX86_BUILTIN_PAVGW256,
28850 IX86_BUILTIN_PBLENDVB256,
28851 IX86_BUILTIN_PBLENDVW256,
28852 IX86_BUILTIN_PCMPEQB256,
28853 IX86_BUILTIN_PCMPEQW256,
28854 IX86_BUILTIN_PCMPEQD256,
28855 IX86_BUILTIN_PCMPEQQ256,
28856 IX86_BUILTIN_PCMPGTB256,
28857 IX86_BUILTIN_PCMPGTW256,
28858 IX86_BUILTIN_PCMPGTD256,
28859 IX86_BUILTIN_PCMPGTQ256,
28860 IX86_BUILTIN_PHADDW256,
28861 IX86_BUILTIN_PHADDD256,
28862 IX86_BUILTIN_PHADDSW256,
28863 IX86_BUILTIN_PHSUBW256,
28864 IX86_BUILTIN_PHSUBD256,
28865 IX86_BUILTIN_PHSUBSW256,
28866 IX86_BUILTIN_PMADDUBSW256,
28867 IX86_BUILTIN_PMADDWD256,
28868 IX86_BUILTIN_PMAXSB256,
28869 IX86_BUILTIN_PMAXSW256,
28870 IX86_BUILTIN_PMAXSD256,
28871 IX86_BUILTIN_PMAXUB256,
28872 IX86_BUILTIN_PMAXUW256,
28873 IX86_BUILTIN_PMAXUD256,
28874 IX86_BUILTIN_PMINSB256,
28875 IX86_BUILTIN_PMINSW256,
28876 IX86_BUILTIN_PMINSD256,
28877 IX86_BUILTIN_PMINUB256,
28878 IX86_BUILTIN_PMINUW256,
28879 IX86_BUILTIN_PMINUD256,
28880 IX86_BUILTIN_PMOVMSKB256,
28881 IX86_BUILTIN_PMOVSXBW256,
28882 IX86_BUILTIN_PMOVSXBD256,
28883 IX86_BUILTIN_PMOVSXBQ256,
28884 IX86_BUILTIN_PMOVSXWD256,
28885 IX86_BUILTIN_PMOVSXWQ256,
28886 IX86_BUILTIN_PMOVSXDQ256,
28887 IX86_BUILTIN_PMOVZXBW256,
28888 IX86_BUILTIN_PMOVZXBD256,
28889 IX86_BUILTIN_PMOVZXBQ256,
28890 IX86_BUILTIN_PMOVZXWD256,
28891 IX86_BUILTIN_PMOVZXWQ256,
28892 IX86_BUILTIN_PMOVZXDQ256,
28893 IX86_BUILTIN_PMULDQ256,
28894 IX86_BUILTIN_PMULHRSW256,
28895 IX86_BUILTIN_PMULHUW256,
28896 IX86_BUILTIN_PMULHW256,
28897 IX86_BUILTIN_PMULLW256,
28898 IX86_BUILTIN_PMULLD256,
28899 IX86_BUILTIN_PMULUDQ256,
28900 IX86_BUILTIN_POR256,
28901 IX86_BUILTIN_PSADBW256,
28902 IX86_BUILTIN_PSHUFB256,
28903 IX86_BUILTIN_PSHUFD256,
28904 IX86_BUILTIN_PSHUFHW256,
28905 IX86_BUILTIN_PSHUFLW256,
28906 IX86_BUILTIN_PSIGNB256,
28907 IX86_BUILTIN_PSIGNW256,
28908 IX86_BUILTIN_PSIGND256,
28909 IX86_BUILTIN_PSLLDQI256,
28910 IX86_BUILTIN_PSLLWI256,
28911 IX86_BUILTIN_PSLLW256,
28912 IX86_BUILTIN_PSLLDI256,
28913 IX86_BUILTIN_PSLLD256,
28914 IX86_BUILTIN_PSLLQI256,
28915 IX86_BUILTIN_PSLLQ256,
28916 IX86_BUILTIN_PSRAWI256,
28917 IX86_BUILTIN_PSRAW256,
28918 IX86_BUILTIN_PSRADI256,
28919 IX86_BUILTIN_PSRAD256,
28920 IX86_BUILTIN_PSRLDQI256,
28921 IX86_BUILTIN_PSRLWI256,
28922 IX86_BUILTIN_PSRLW256,
28923 IX86_BUILTIN_PSRLDI256,
28924 IX86_BUILTIN_PSRLD256,
28925 IX86_BUILTIN_PSRLQI256,
28926 IX86_BUILTIN_PSRLQ256,
28927 IX86_BUILTIN_PSUBB256,
28928 IX86_BUILTIN_PSUBW256,
28929 IX86_BUILTIN_PSUBD256,
28930 IX86_BUILTIN_PSUBQ256,
28931 IX86_BUILTIN_PSUBSB256,
28932 IX86_BUILTIN_PSUBSW256,
28933 IX86_BUILTIN_PSUBUSB256,
28934 IX86_BUILTIN_PSUBUSW256,
28935 IX86_BUILTIN_PUNPCKHBW256,
28936 IX86_BUILTIN_PUNPCKHWD256,
28937 IX86_BUILTIN_PUNPCKHDQ256,
28938 IX86_BUILTIN_PUNPCKHQDQ256,
28939 IX86_BUILTIN_PUNPCKLBW256,
28940 IX86_BUILTIN_PUNPCKLWD256,
28941 IX86_BUILTIN_PUNPCKLDQ256,
28942 IX86_BUILTIN_PUNPCKLQDQ256,
28943 IX86_BUILTIN_PXOR256,
28944 IX86_BUILTIN_MOVNTDQA256,
28945 IX86_BUILTIN_VBROADCASTSS_PS,
28946 IX86_BUILTIN_VBROADCASTSS_PS256,
28947 IX86_BUILTIN_VBROADCASTSD_PD256,
28948 IX86_BUILTIN_VBROADCASTSI256,
28949 IX86_BUILTIN_PBLENDD256,
28950 IX86_BUILTIN_PBLENDD128,
28951 IX86_BUILTIN_PBROADCASTB256,
28952 IX86_BUILTIN_PBROADCASTW256,
28953 IX86_BUILTIN_PBROADCASTD256,
28954 IX86_BUILTIN_PBROADCASTQ256,
28955 IX86_BUILTIN_PBROADCASTB128,
28956 IX86_BUILTIN_PBROADCASTW128,
28957 IX86_BUILTIN_PBROADCASTD128,
28958 IX86_BUILTIN_PBROADCASTQ128,
28959 IX86_BUILTIN_VPERMVARSI256,
28960 IX86_BUILTIN_VPERMDF256,
28961 IX86_BUILTIN_VPERMVARSF256,
28962 IX86_BUILTIN_VPERMDI256,
28963 IX86_BUILTIN_VPERMTI256,
28964 IX86_BUILTIN_VEXTRACT128I256,
28965 IX86_BUILTIN_VINSERT128I256,
28966 IX86_BUILTIN_MASKLOADD,
28967 IX86_BUILTIN_MASKLOADQ,
28968 IX86_BUILTIN_MASKLOADD256,
28969 IX86_BUILTIN_MASKLOADQ256,
28970 IX86_BUILTIN_MASKSTORED,
28971 IX86_BUILTIN_MASKSTOREQ,
28972 IX86_BUILTIN_MASKSTORED256,
28973 IX86_BUILTIN_MASKSTOREQ256,
28974 IX86_BUILTIN_PSLLVV4DI,
28975 IX86_BUILTIN_PSLLVV2DI,
28976 IX86_BUILTIN_PSLLVV8SI,
28977 IX86_BUILTIN_PSLLVV4SI,
28978 IX86_BUILTIN_PSRAVV8SI,
28979 IX86_BUILTIN_PSRAVV4SI,
28980 IX86_BUILTIN_PSRLVV4DI,
28981 IX86_BUILTIN_PSRLVV2DI,
28982 IX86_BUILTIN_PSRLVV8SI,
28983 IX86_BUILTIN_PSRLVV4SI,
28985 IX86_BUILTIN_GATHERSIV2DF,
28986 IX86_BUILTIN_GATHERSIV4DF,
28987 IX86_BUILTIN_GATHERDIV2DF,
28988 IX86_BUILTIN_GATHERDIV4DF,
28989 IX86_BUILTIN_GATHERSIV4SF,
28990 IX86_BUILTIN_GATHERSIV8SF,
28991 IX86_BUILTIN_GATHERDIV4SF,
28992 IX86_BUILTIN_GATHERDIV8SF,
28993 IX86_BUILTIN_GATHERSIV2DI,
28994 IX86_BUILTIN_GATHERSIV4DI,
28995 IX86_BUILTIN_GATHERDIV2DI,
28996 IX86_BUILTIN_GATHERDIV4DI,
28997 IX86_BUILTIN_GATHERSIV4SI,
28998 IX86_BUILTIN_GATHERSIV8SI,
28999 IX86_BUILTIN_GATHERDIV4SI,
29000 IX86_BUILTIN_GATHERDIV8SI,
29002 /* AVX512F */
29003 IX86_BUILTIN_SI512_SI256,
29004 IX86_BUILTIN_PD512_PD256,
29005 IX86_BUILTIN_PS512_PS256,
29006 IX86_BUILTIN_SI512_SI,
29007 IX86_BUILTIN_PD512_PD,
29008 IX86_BUILTIN_PS512_PS,
29009 IX86_BUILTIN_ADDPD512,
29010 IX86_BUILTIN_ADDPS512,
29011 IX86_BUILTIN_ADDSD_ROUND,
29012 IX86_BUILTIN_ADDSS_ROUND,
29013 IX86_BUILTIN_ALIGND512,
29014 IX86_BUILTIN_ALIGNQ512,
29015 IX86_BUILTIN_BLENDMD512,
29016 IX86_BUILTIN_BLENDMPD512,
29017 IX86_BUILTIN_BLENDMPS512,
29018 IX86_BUILTIN_BLENDMQ512,
29019 IX86_BUILTIN_BROADCASTF32X4_512,
29020 IX86_BUILTIN_BROADCASTF64X4_512,
29021 IX86_BUILTIN_BROADCASTI32X4_512,
29022 IX86_BUILTIN_BROADCASTI64X4_512,
29023 IX86_BUILTIN_BROADCASTSD512,
29024 IX86_BUILTIN_BROADCASTSS512,
29025 IX86_BUILTIN_CMPD512,
29026 IX86_BUILTIN_CMPPD512,
29027 IX86_BUILTIN_CMPPS512,
29028 IX86_BUILTIN_CMPQ512,
29029 IX86_BUILTIN_CMPSD_MASK,
29030 IX86_BUILTIN_CMPSS_MASK,
29031 IX86_BUILTIN_COMIDF,
29032 IX86_BUILTIN_COMISF,
29033 IX86_BUILTIN_COMPRESSPD512,
29034 IX86_BUILTIN_COMPRESSPDSTORE512,
29035 IX86_BUILTIN_COMPRESSPS512,
29036 IX86_BUILTIN_COMPRESSPSSTORE512,
29037 IX86_BUILTIN_CVTDQ2PD512,
29038 IX86_BUILTIN_CVTDQ2PS512,
29039 IX86_BUILTIN_CVTPD2DQ512,
29040 IX86_BUILTIN_CVTPD2PS512,
29041 IX86_BUILTIN_CVTPD2UDQ512,
29042 IX86_BUILTIN_CVTPH2PS512,
29043 IX86_BUILTIN_CVTPS2DQ512,
29044 IX86_BUILTIN_CVTPS2PD512,
29045 IX86_BUILTIN_CVTPS2PH512,
29046 IX86_BUILTIN_CVTPS2UDQ512,
29047 IX86_BUILTIN_CVTSD2SS_ROUND,
29048 IX86_BUILTIN_CVTSI2SD64,
29049 IX86_BUILTIN_CVTSI2SS32,
29050 IX86_BUILTIN_CVTSI2SS64,
29051 IX86_BUILTIN_CVTSS2SD_ROUND,
29052 IX86_BUILTIN_CVTTPD2DQ512,
29053 IX86_BUILTIN_CVTTPD2UDQ512,
29054 IX86_BUILTIN_CVTTPS2DQ512,
29055 IX86_BUILTIN_CVTTPS2UDQ512,
29056 IX86_BUILTIN_CVTUDQ2PD512,
29057 IX86_BUILTIN_CVTUDQ2PS512,
29058 IX86_BUILTIN_CVTUSI2SD32,
29059 IX86_BUILTIN_CVTUSI2SD64,
29060 IX86_BUILTIN_CVTUSI2SS32,
29061 IX86_BUILTIN_CVTUSI2SS64,
29062 IX86_BUILTIN_DIVPD512,
29063 IX86_BUILTIN_DIVPS512,
29064 IX86_BUILTIN_DIVSD_ROUND,
29065 IX86_BUILTIN_DIVSS_ROUND,
29066 IX86_BUILTIN_EXPANDPD512,
29067 IX86_BUILTIN_EXPANDPD512Z,
29068 IX86_BUILTIN_EXPANDPDLOAD512,
29069 IX86_BUILTIN_EXPANDPDLOAD512Z,
29070 IX86_BUILTIN_EXPANDPS512,
29071 IX86_BUILTIN_EXPANDPS512Z,
29072 IX86_BUILTIN_EXPANDPSLOAD512,
29073 IX86_BUILTIN_EXPANDPSLOAD512Z,
29074 IX86_BUILTIN_EXTRACTF32X4,
29075 IX86_BUILTIN_EXTRACTF64X4,
29076 IX86_BUILTIN_EXTRACTI32X4,
29077 IX86_BUILTIN_EXTRACTI64X4,
29078 IX86_BUILTIN_FIXUPIMMPD512_MASK,
29079 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
29080 IX86_BUILTIN_FIXUPIMMPS512_MASK,
29081 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
29082 IX86_BUILTIN_FIXUPIMMSD128_MASK,
29083 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
29084 IX86_BUILTIN_FIXUPIMMSS128_MASK,
29085 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
29086 IX86_BUILTIN_GETEXPPD512,
29087 IX86_BUILTIN_GETEXPPS512,
29088 IX86_BUILTIN_GETEXPSD128,
29089 IX86_BUILTIN_GETEXPSS128,
29090 IX86_BUILTIN_GETMANTPD512,
29091 IX86_BUILTIN_GETMANTPS512,
29092 IX86_BUILTIN_GETMANTSD128,
29093 IX86_BUILTIN_GETMANTSS128,
29094 IX86_BUILTIN_INSERTF32X4,
29095 IX86_BUILTIN_INSERTF64X4,
29096 IX86_BUILTIN_INSERTI32X4,
29097 IX86_BUILTIN_INSERTI64X4,
29098 IX86_BUILTIN_LOADAPD512,
29099 IX86_BUILTIN_LOADAPS512,
29100 IX86_BUILTIN_LOADDQUDI512,
29101 IX86_BUILTIN_LOADDQUSI512,
29102 IX86_BUILTIN_LOADUPD512,
29103 IX86_BUILTIN_LOADUPS512,
29104 IX86_BUILTIN_MAXPD512,
29105 IX86_BUILTIN_MAXPS512,
29106 IX86_BUILTIN_MAXSD_ROUND,
29107 IX86_BUILTIN_MAXSS_ROUND,
29108 IX86_BUILTIN_MINPD512,
29109 IX86_BUILTIN_MINPS512,
29110 IX86_BUILTIN_MINSD_ROUND,
29111 IX86_BUILTIN_MINSS_ROUND,
29112 IX86_BUILTIN_MOVAPD512,
29113 IX86_BUILTIN_MOVAPS512,
29114 IX86_BUILTIN_MOVDDUP512,
29115 IX86_BUILTIN_MOVDQA32LOAD512,
29116 IX86_BUILTIN_MOVDQA32STORE512,
29117 IX86_BUILTIN_MOVDQA32_512,
29118 IX86_BUILTIN_MOVDQA64LOAD512,
29119 IX86_BUILTIN_MOVDQA64STORE512,
29120 IX86_BUILTIN_MOVDQA64_512,
29121 IX86_BUILTIN_MOVNTDQ512,
29122 IX86_BUILTIN_MOVNTDQA512,
29123 IX86_BUILTIN_MOVNTPD512,
29124 IX86_BUILTIN_MOVNTPS512,
29125 IX86_BUILTIN_MOVSHDUP512,
29126 IX86_BUILTIN_MOVSLDUP512,
29127 IX86_BUILTIN_MULPD512,
29128 IX86_BUILTIN_MULPS512,
29129 IX86_BUILTIN_MULSD_ROUND,
29130 IX86_BUILTIN_MULSS_ROUND,
29131 IX86_BUILTIN_PABSD512,
29132 IX86_BUILTIN_PABSQ512,
29133 IX86_BUILTIN_PADDD512,
29134 IX86_BUILTIN_PADDQ512,
29135 IX86_BUILTIN_PANDD512,
29136 IX86_BUILTIN_PANDND512,
29137 IX86_BUILTIN_PANDNQ512,
29138 IX86_BUILTIN_PANDQ512,
29139 IX86_BUILTIN_PBROADCASTD512,
29140 IX86_BUILTIN_PBROADCASTD512_GPR,
29141 IX86_BUILTIN_PBROADCASTMB512,
29142 IX86_BUILTIN_PBROADCASTMW512,
29143 IX86_BUILTIN_PBROADCASTQ512,
29144 IX86_BUILTIN_PBROADCASTQ512_GPR,
29145 IX86_BUILTIN_PCMPEQD512_MASK,
29146 IX86_BUILTIN_PCMPEQQ512_MASK,
29147 IX86_BUILTIN_PCMPGTD512_MASK,
29148 IX86_BUILTIN_PCMPGTQ512_MASK,
29149 IX86_BUILTIN_PCOMPRESSD512,
29150 IX86_BUILTIN_PCOMPRESSDSTORE512,
29151 IX86_BUILTIN_PCOMPRESSQ512,
29152 IX86_BUILTIN_PCOMPRESSQSTORE512,
29153 IX86_BUILTIN_PEXPANDD512,
29154 IX86_BUILTIN_PEXPANDD512Z,
29155 IX86_BUILTIN_PEXPANDDLOAD512,
29156 IX86_BUILTIN_PEXPANDDLOAD512Z,
29157 IX86_BUILTIN_PEXPANDQ512,
29158 IX86_BUILTIN_PEXPANDQ512Z,
29159 IX86_BUILTIN_PEXPANDQLOAD512,
29160 IX86_BUILTIN_PEXPANDQLOAD512Z,
29161 IX86_BUILTIN_PMAXSD512,
29162 IX86_BUILTIN_PMAXSQ512,
29163 IX86_BUILTIN_PMAXUD512,
29164 IX86_BUILTIN_PMAXUQ512,
29165 IX86_BUILTIN_PMINSD512,
29166 IX86_BUILTIN_PMINSQ512,
29167 IX86_BUILTIN_PMINUD512,
29168 IX86_BUILTIN_PMINUQ512,
29169 IX86_BUILTIN_PMOVDB512,
29170 IX86_BUILTIN_PMOVDB512_MEM,
29171 IX86_BUILTIN_PMOVDW512,
29172 IX86_BUILTIN_PMOVDW512_MEM,
29173 IX86_BUILTIN_PMOVQB512,
29174 IX86_BUILTIN_PMOVQB512_MEM,
29175 IX86_BUILTIN_PMOVQD512,
29176 IX86_BUILTIN_PMOVQD512_MEM,
29177 IX86_BUILTIN_PMOVQW512,
29178 IX86_BUILTIN_PMOVQW512_MEM,
29179 IX86_BUILTIN_PMOVSDB512,
29180 IX86_BUILTIN_PMOVSDB512_MEM,
29181 IX86_BUILTIN_PMOVSDW512,
29182 IX86_BUILTIN_PMOVSDW512_MEM,
29183 IX86_BUILTIN_PMOVSQB512,
29184 IX86_BUILTIN_PMOVSQB512_MEM,
29185 IX86_BUILTIN_PMOVSQD512,
29186 IX86_BUILTIN_PMOVSQD512_MEM,
29187 IX86_BUILTIN_PMOVSQW512,
29188 IX86_BUILTIN_PMOVSQW512_MEM,
29189 IX86_BUILTIN_PMOVSXBD512,
29190 IX86_BUILTIN_PMOVSXBQ512,
29191 IX86_BUILTIN_PMOVSXDQ512,
29192 IX86_BUILTIN_PMOVSXWD512,
29193 IX86_BUILTIN_PMOVSXWQ512,
29194 IX86_BUILTIN_PMOVUSDB512,
29195 IX86_BUILTIN_PMOVUSDB512_MEM,
29196 IX86_BUILTIN_PMOVUSDW512,
29197 IX86_BUILTIN_PMOVUSDW512_MEM,
29198 IX86_BUILTIN_PMOVUSQB512,
29199 IX86_BUILTIN_PMOVUSQB512_MEM,
29200 IX86_BUILTIN_PMOVUSQD512,
29201 IX86_BUILTIN_PMOVUSQD512_MEM,
29202 IX86_BUILTIN_PMOVUSQW512,
29203 IX86_BUILTIN_PMOVUSQW512_MEM,
29204 IX86_BUILTIN_PMOVZXBD512,
29205 IX86_BUILTIN_PMOVZXBQ512,
29206 IX86_BUILTIN_PMOVZXDQ512,
29207 IX86_BUILTIN_PMOVZXWD512,
29208 IX86_BUILTIN_PMOVZXWQ512,
29209 IX86_BUILTIN_PMULDQ512,
29210 IX86_BUILTIN_PMULLD512,
29211 IX86_BUILTIN_PMULUDQ512,
29212 IX86_BUILTIN_PORD512,
29213 IX86_BUILTIN_PORQ512,
29214 IX86_BUILTIN_PROLD512,
29215 IX86_BUILTIN_PROLQ512,
29216 IX86_BUILTIN_PROLVD512,
29217 IX86_BUILTIN_PROLVQ512,
29218 IX86_BUILTIN_PRORD512,
29219 IX86_BUILTIN_PRORQ512,
29220 IX86_BUILTIN_PRORVD512,
29221 IX86_BUILTIN_PRORVQ512,
29222 IX86_BUILTIN_PSHUFD512,
29223 IX86_BUILTIN_PSLLD512,
29224 IX86_BUILTIN_PSLLDI512,
29225 IX86_BUILTIN_PSLLQ512,
29226 IX86_BUILTIN_PSLLQI512,
29227 IX86_BUILTIN_PSLLVV16SI,
29228 IX86_BUILTIN_PSLLVV8DI,
29229 IX86_BUILTIN_PSRAD512,
29230 IX86_BUILTIN_PSRADI512,
29231 IX86_BUILTIN_PSRAQ512,
29232 IX86_BUILTIN_PSRAQI512,
29233 IX86_BUILTIN_PSRAVV16SI,
29234 IX86_BUILTIN_PSRAVV8DI,
29235 IX86_BUILTIN_PSRLD512,
29236 IX86_BUILTIN_PSRLDI512,
29237 IX86_BUILTIN_PSRLQ512,
29238 IX86_BUILTIN_PSRLQI512,
29239 IX86_BUILTIN_PSRLVV16SI,
29240 IX86_BUILTIN_PSRLVV8DI,
29241 IX86_BUILTIN_PSUBD512,
29242 IX86_BUILTIN_PSUBQ512,
29243 IX86_BUILTIN_PTESTMD512,
29244 IX86_BUILTIN_PTESTMQ512,
29245 IX86_BUILTIN_PTESTNMD512,
29246 IX86_BUILTIN_PTESTNMQ512,
29247 IX86_BUILTIN_PUNPCKHDQ512,
29248 IX86_BUILTIN_PUNPCKHQDQ512,
29249 IX86_BUILTIN_PUNPCKLDQ512,
29250 IX86_BUILTIN_PUNPCKLQDQ512,
29251 IX86_BUILTIN_PXORD512,
29252 IX86_BUILTIN_PXORQ512,
29253 IX86_BUILTIN_RCP14PD512,
29254 IX86_BUILTIN_RCP14PS512,
29255 IX86_BUILTIN_RCP14SD,
29256 IX86_BUILTIN_RCP14SS,
29257 IX86_BUILTIN_RNDSCALEPD,
29258 IX86_BUILTIN_RNDSCALEPS,
29259 IX86_BUILTIN_RNDSCALESD,
29260 IX86_BUILTIN_RNDSCALESS,
29261 IX86_BUILTIN_RSQRT14PD512,
29262 IX86_BUILTIN_RSQRT14PS512,
29263 IX86_BUILTIN_RSQRT14SD,
29264 IX86_BUILTIN_RSQRT14SS,
29265 IX86_BUILTIN_SCALEFPD512,
29266 IX86_BUILTIN_SCALEFPS512,
29267 IX86_BUILTIN_SCALEFSD,
29268 IX86_BUILTIN_SCALEFSS,
29269 IX86_BUILTIN_SHUFPD512,
29270 IX86_BUILTIN_SHUFPS512,
29271 IX86_BUILTIN_SHUF_F32x4,
29272 IX86_BUILTIN_SHUF_F64x2,
29273 IX86_BUILTIN_SHUF_I32x4,
29274 IX86_BUILTIN_SHUF_I64x2,
29275 IX86_BUILTIN_SQRTPD512,
29276 IX86_BUILTIN_SQRTPD512_MASK,
29277 IX86_BUILTIN_SQRTPS512_MASK,
29278 IX86_BUILTIN_SQRTPS_NR512,
29279 IX86_BUILTIN_SQRTSD_ROUND,
29280 IX86_BUILTIN_SQRTSS_ROUND,
29281 IX86_BUILTIN_STOREAPD512,
29282 IX86_BUILTIN_STOREAPS512,
29283 IX86_BUILTIN_STOREDQUDI512,
29284 IX86_BUILTIN_STOREDQUSI512,
29285 IX86_BUILTIN_STOREUPD512,
29286 IX86_BUILTIN_STOREUPS512,
29287 IX86_BUILTIN_SUBPD512,
29288 IX86_BUILTIN_SUBPS512,
29289 IX86_BUILTIN_SUBSD_ROUND,
29290 IX86_BUILTIN_SUBSS_ROUND,
29291 IX86_BUILTIN_UCMPD512,
29292 IX86_BUILTIN_UCMPQ512,
29293 IX86_BUILTIN_UNPCKHPD512,
29294 IX86_BUILTIN_UNPCKHPS512,
29295 IX86_BUILTIN_UNPCKLPD512,
29296 IX86_BUILTIN_UNPCKLPS512,
29297 IX86_BUILTIN_VCVTSD2SI32,
29298 IX86_BUILTIN_VCVTSD2SI64,
29299 IX86_BUILTIN_VCVTSD2USI32,
29300 IX86_BUILTIN_VCVTSD2USI64,
29301 IX86_BUILTIN_VCVTSS2SI32,
29302 IX86_BUILTIN_VCVTSS2SI64,
29303 IX86_BUILTIN_VCVTSS2USI32,
29304 IX86_BUILTIN_VCVTSS2USI64,
29305 IX86_BUILTIN_VCVTTSD2SI32,
29306 IX86_BUILTIN_VCVTTSD2SI64,
29307 IX86_BUILTIN_VCVTTSD2USI32,
29308 IX86_BUILTIN_VCVTTSD2USI64,
29309 IX86_BUILTIN_VCVTTSS2SI32,
29310 IX86_BUILTIN_VCVTTSS2SI64,
29311 IX86_BUILTIN_VCVTTSS2USI32,
29312 IX86_BUILTIN_VCVTTSS2USI64,
29313 IX86_BUILTIN_VFMADDPD512_MASK,
29314 IX86_BUILTIN_VFMADDPD512_MASK3,
29315 IX86_BUILTIN_VFMADDPD512_MASKZ,
29316 IX86_BUILTIN_VFMADDPS512_MASK,
29317 IX86_BUILTIN_VFMADDPS512_MASK3,
29318 IX86_BUILTIN_VFMADDPS512_MASKZ,
29319 IX86_BUILTIN_VFMADDSD3_ROUND,
29320 IX86_BUILTIN_VFMADDSS3_ROUND,
29321 IX86_BUILTIN_VFMADDSUBPD512_MASK,
29322 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
29323 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
29324 IX86_BUILTIN_VFMADDSUBPS512_MASK,
29325 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
29326 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
29327 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
29328 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
29329 IX86_BUILTIN_VFMSUBPD512_MASK3,
29330 IX86_BUILTIN_VFMSUBPS512_MASK3,
29331 IX86_BUILTIN_VFMSUBSD3_MASK3,
29332 IX86_BUILTIN_VFMSUBSS3_MASK3,
29333 IX86_BUILTIN_VFNMADDPD512_MASK,
29334 IX86_BUILTIN_VFNMADDPS512_MASK,
29335 IX86_BUILTIN_VFNMSUBPD512_MASK,
29336 IX86_BUILTIN_VFNMSUBPD512_MASK3,
29337 IX86_BUILTIN_VFNMSUBPS512_MASK,
29338 IX86_BUILTIN_VFNMSUBPS512_MASK3,
29339 IX86_BUILTIN_VPCLZCNTD512,
29340 IX86_BUILTIN_VPCLZCNTQ512,
29341 IX86_BUILTIN_VPCONFLICTD512,
29342 IX86_BUILTIN_VPCONFLICTQ512,
29343 IX86_BUILTIN_VPERMDF512,
29344 IX86_BUILTIN_VPERMDI512,
29345 IX86_BUILTIN_VPERMI2VARD512,
29346 IX86_BUILTIN_VPERMI2VARPD512,
29347 IX86_BUILTIN_VPERMI2VARPS512,
29348 IX86_BUILTIN_VPERMI2VARQ512,
29349 IX86_BUILTIN_VPERMILPD512,
29350 IX86_BUILTIN_VPERMILPS512,
29351 IX86_BUILTIN_VPERMILVARPD512,
29352 IX86_BUILTIN_VPERMILVARPS512,
29353 IX86_BUILTIN_VPERMT2VARD512,
29354 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
29355 IX86_BUILTIN_VPERMT2VARPD512,
29356 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
29357 IX86_BUILTIN_VPERMT2VARPS512,
29358 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
29359 IX86_BUILTIN_VPERMT2VARQ512,
29360 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
29361 IX86_BUILTIN_VPERMVARDF512,
29362 IX86_BUILTIN_VPERMVARDI512,
29363 IX86_BUILTIN_VPERMVARSF512,
29364 IX86_BUILTIN_VPERMVARSI512,
29365 IX86_BUILTIN_VTERNLOGD512_MASK,
29366 IX86_BUILTIN_VTERNLOGD512_MASKZ,
29367 IX86_BUILTIN_VTERNLOGQ512_MASK,
29368 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
29370 /* Mask arithmetic operations */
29371 IX86_BUILTIN_KAND16,
29372 IX86_BUILTIN_KANDN16,
29373 IX86_BUILTIN_KNOT16,
29374 IX86_BUILTIN_KOR16,
29375 IX86_BUILTIN_KORTESTC16,
29376 IX86_BUILTIN_KORTESTZ16,
29377 IX86_BUILTIN_KUNPCKBW,
29378 IX86_BUILTIN_KXNOR16,
29379 IX86_BUILTIN_KXOR16,
29380 IX86_BUILTIN_KMOV16,
29382 /* AVX512VL. */
29383 IX86_BUILTIN_PMOVUSQD256_MEM,
29384 IX86_BUILTIN_PMOVUSQD128_MEM,
29385 IX86_BUILTIN_PMOVSQD256_MEM,
29386 IX86_BUILTIN_PMOVSQD128_MEM,
29387 IX86_BUILTIN_PMOVQD256_MEM,
29388 IX86_BUILTIN_PMOVQD128_MEM,
29389 IX86_BUILTIN_PMOVUSQW256_MEM,
29390 IX86_BUILTIN_PMOVUSQW128_MEM,
29391 IX86_BUILTIN_PMOVSQW256_MEM,
29392 IX86_BUILTIN_PMOVSQW128_MEM,
29393 IX86_BUILTIN_PMOVQW256_MEM,
29394 IX86_BUILTIN_PMOVQW128_MEM,
29395 IX86_BUILTIN_PMOVUSQB256_MEM,
29396 IX86_BUILTIN_PMOVUSQB128_MEM,
29397 IX86_BUILTIN_PMOVSQB256_MEM,
29398 IX86_BUILTIN_PMOVSQB128_MEM,
29399 IX86_BUILTIN_PMOVQB256_MEM,
29400 IX86_BUILTIN_PMOVQB128_MEM,
29401 IX86_BUILTIN_PMOVUSDW256_MEM,
29402 IX86_BUILTIN_PMOVUSDW128_MEM,
29403 IX86_BUILTIN_PMOVSDW256_MEM,
29404 IX86_BUILTIN_PMOVSDW128_MEM,
29405 IX86_BUILTIN_PMOVDW256_MEM,
29406 IX86_BUILTIN_PMOVDW128_MEM,
29407 IX86_BUILTIN_PMOVUSDB256_MEM,
29408 IX86_BUILTIN_PMOVUSDB128_MEM,
29409 IX86_BUILTIN_PMOVSDB256_MEM,
29410 IX86_BUILTIN_PMOVSDB128_MEM,
29411 IX86_BUILTIN_PMOVDB256_MEM,
29412 IX86_BUILTIN_PMOVDB128_MEM,
29413 IX86_BUILTIN_MOVDQA64LOAD256_MASK,
29414 IX86_BUILTIN_MOVDQA64LOAD128_MASK,
29415 IX86_BUILTIN_MOVDQA32LOAD256_MASK,
29416 IX86_BUILTIN_MOVDQA32LOAD128_MASK,
29417 IX86_BUILTIN_MOVDQA64STORE256_MASK,
29418 IX86_BUILTIN_MOVDQA64STORE128_MASK,
29419 IX86_BUILTIN_MOVDQA32STORE256_MASK,
29420 IX86_BUILTIN_MOVDQA32STORE128_MASK,
29421 IX86_BUILTIN_LOADAPD256_MASK,
29422 IX86_BUILTIN_LOADAPD128_MASK,
29423 IX86_BUILTIN_LOADAPS256_MASK,
29424 IX86_BUILTIN_LOADAPS128_MASK,
29425 IX86_BUILTIN_STOREAPD256_MASK,
29426 IX86_BUILTIN_STOREAPD128_MASK,
29427 IX86_BUILTIN_STOREAPS256_MASK,
29428 IX86_BUILTIN_STOREAPS128_MASK,
29429 IX86_BUILTIN_LOADUPD256_MASK,
29430 IX86_BUILTIN_LOADUPD128_MASK,
29431 IX86_BUILTIN_LOADUPS256_MASK,
29432 IX86_BUILTIN_LOADUPS128_MASK,
29433 IX86_BUILTIN_STOREUPD256_MASK,
29434 IX86_BUILTIN_STOREUPD128_MASK,
29435 IX86_BUILTIN_STOREUPS256_MASK,
29436 IX86_BUILTIN_STOREUPS128_MASK,
29437 IX86_BUILTIN_LOADDQUDI256_MASK,
29438 IX86_BUILTIN_LOADDQUDI128_MASK,
29439 IX86_BUILTIN_LOADDQUSI256_MASK,
29440 IX86_BUILTIN_LOADDQUSI128_MASK,
29441 IX86_BUILTIN_LOADDQUHI256_MASK,
29442 IX86_BUILTIN_LOADDQUHI128_MASK,
29443 IX86_BUILTIN_LOADDQUQI256_MASK,
29444 IX86_BUILTIN_LOADDQUQI128_MASK,
29445 IX86_BUILTIN_STOREDQUDI256_MASK,
29446 IX86_BUILTIN_STOREDQUDI128_MASK,
29447 IX86_BUILTIN_STOREDQUSI256_MASK,
29448 IX86_BUILTIN_STOREDQUSI128_MASK,
29449 IX86_BUILTIN_STOREDQUHI256_MASK,
29450 IX86_BUILTIN_STOREDQUHI128_MASK,
29451 IX86_BUILTIN_STOREDQUQI256_MASK,
29452 IX86_BUILTIN_STOREDQUQI128_MASK,
29453 IX86_BUILTIN_COMPRESSPDSTORE256,
29454 IX86_BUILTIN_COMPRESSPDSTORE128,
29455 IX86_BUILTIN_COMPRESSPSSTORE256,
29456 IX86_BUILTIN_COMPRESSPSSTORE128,
29457 IX86_BUILTIN_PCOMPRESSQSTORE256,
29458 IX86_BUILTIN_PCOMPRESSQSTORE128,
29459 IX86_BUILTIN_PCOMPRESSDSTORE256,
29460 IX86_BUILTIN_PCOMPRESSDSTORE128,
29461 IX86_BUILTIN_EXPANDPDLOAD256,
29462 IX86_BUILTIN_EXPANDPDLOAD128,
29463 IX86_BUILTIN_EXPANDPSLOAD256,
29464 IX86_BUILTIN_EXPANDPSLOAD128,
29465 IX86_BUILTIN_PEXPANDQLOAD256,
29466 IX86_BUILTIN_PEXPANDQLOAD128,
29467 IX86_BUILTIN_PEXPANDDLOAD256,
29468 IX86_BUILTIN_PEXPANDDLOAD128,
29469 IX86_BUILTIN_EXPANDPDLOAD256Z,
29470 IX86_BUILTIN_EXPANDPDLOAD128Z,
29471 IX86_BUILTIN_EXPANDPSLOAD256Z,
29472 IX86_BUILTIN_EXPANDPSLOAD128Z,
29473 IX86_BUILTIN_PEXPANDQLOAD256Z,
29474 IX86_BUILTIN_PEXPANDQLOAD128Z,
29475 IX86_BUILTIN_PEXPANDDLOAD256Z,
29476 IX86_BUILTIN_PEXPANDDLOAD128Z,
29477 IX86_BUILTIN_PALIGNR256_MASK,
29478 IX86_BUILTIN_PALIGNR128_MASK,
29479 IX86_BUILTIN_MOVDQA64_256_MASK,
29480 IX86_BUILTIN_MOVDQA64_128_MASK,
29481 IX86_BUILTIN_MOVDQA32_256_MASK,
29482 IX86_BUILTIN_MOVDQA32_128_MASK,
29483 IX86_BUILTIN_MOVAPD256_MASK,
29484 IX86_BUILTIN_MOVAPD128_MASK,
29485 IX86_BUILTIN_MOVAPS256_MASK,
29486 IX86_BUILTIN_MOVAPS128_MASK,
29487 IX86_BUILTIN_MOVDQUHI256_MASK,
29488 IX86_BUILTIN_MOVDQUHI128_MASK,
29489 IX86_BUILTIN_MOVDQUQI256_MASK,
29490 IX86_BUILTIN_MOVDQUQI128_MASK,
29491 IX86_BUILTIN_MINPS128_MASK,
29492 IX86_BUILTIN_MAXPS128_MASK,
29493 IX86_BUILTIN_MINPD128_MASK,
29494 IX86_BUILTIN_MAXPD128_MASK,
29495 IX86_BUILTIN_MAXPD256_MASK,
29496 IX86_BUILTIN_MAXPS256_MASK,
29497 IX86_BUILTIN_MINPD256_MASK,
29498 IX86_BUILTIN_MINPS256_MASK,
29499 IX86_BUILTIN_MULPS128_MASK,
29500 IX86_BUILTIN_DIVPS128_MASK,
29501 IX86_BUILTIN_MULPD128_MASK,
29502 IX86_BUILTIN_DIVPD128_MASK,
29503 IX86_BUILTIN_DIVPD256_MASK,
29504 IX86_BUILTIN_DIVPS256_MASK,
29505 IX86_BUILTIN_MULPD256_MASK,
29506 IX86_BUILTIN_MULPS256_MASK,
29507 IX86_BUILTIN_ADDPD128_MASK,
29508 IX86_BUILTIN_ADDPD256_MASK,
29509 IX86_BUILTIN_ADDPS128_MASK,
29510 IX86_BUILTIN_ADDPS256_MASK,
29511 IX86_BUILTIN_SUBPD128_MASK,
29512 IX86_BUILTIN_SUBPD256_MASK,
29513 IX86_BUILTIN_SUBPS128_MASK,
29514 IX86_BUILTIN_SUBPS256_MASK,
29515 IX86_BUILTIN_XORPD256_MASK,
29516 IX86_BUILTIN_XORPD128_MASK,
29517 IX86_BUILTIN_XORPS256_MASK,
29518 IX86_BUILTIN_XORPS128_MASK,
29519 IX86_BUILTIN_ORPD256_MASK,
29520 IX86_BUILTIN_ORPD128_MASK,
29521 IX86_BUILTIN_ORPS256_MASK,
29522 IX86_BUILTIN_ORPS128_MASK,
29523 IX86_BUILTIN_BROADCASTF32x2_256,
29524 IX86_BUILTIN_BROADCASTI32x2_256,
29525 IX86_BUILTIN_BROADCASTI32x2_128,
29526 IX86_BUILTIN_BROADCASTF64X2_256,
29527 IX86_BUILTIN_BROADCASTI64X2_256,
29528 IX86_BUILTIN_BROADCASTF32X4_256,
29529 IX86_BUILTIN_BROADCASTI32X4_256,
29530 IX86_BUILTIN_EXTRACTF32X4_256,
29531 IX86_BUILTIN_EXTRACTI32X4_256,
29532 IX86_BUILTIN_DBPSADBW256,
29533 IX86_BUILTIN_DBPSADBW128,
29534 IX86_BUILTIN_CVTTPD2QQ256,
29535 IX86_BUILTIN_CVTTPD2QQ128,
29536 IX86_BUILTIN_CVTTPD2UQQ256,
29537 IX86_BUILTIN_CVTTPD2UQQ128,
29538 IX86_BUILTIN_CVTPD2QQ256,
29539 IX86_BUILTIN_CVTPD2QQ128,
29540 IX86_BUILTIN_CVTPD2UQQ256,
29541 IX86_BUILTIN_CVTPD2UQQ128,
29542 IX86_BUILTIN_CVTPD2UDQ256_MASK,
29543 IX86_BUILTIN_CVTPD2UDQ128_MASK,
29544 IX86_BUILTIN_CVTTPS2QQ256,
29545 IX86_BUILTIN_CVTTPS2QQ128,
29546 IX86_BUILTIN_CVTTPS2UQQ256,
29547 IX86_BUILTIN_CVTTPS2UQQ128,
29548 IX86_BUILTIN_CVTTPS2DQ256_MASK,
29549 IX86_BUILTIN_CVTTPS2DQ128_MASK,
29550 IX86_BUILTIN_CVTTPS2UDQ256,
29551 IX86_BUILTIN_CVTTPS2UDQ128,
29552 IX86_BUILTIN_CVTTPD2DQ256_MASK,
29553 IX86_BUILTIN_CVTTPD2DQ128_MASK,
29554 IX86_BUILTIN_CVTTPD2UDQ256_MASK,
29555 IX86_BUILTIN_CVTTPD2UDQ128_MASK,
29556 IX86_BUILTIN_CVTPD2DQ256_MASK,
29557 IX86_BUILTIN_CVTPD2DQ128_MASK,
29558 IX86_BUILTIN_CVTDQ2PD256_MASK,
29559 IX86_BUILTIN_CVTDQ2PD128_MASK,
29560 IX86_BUILTIN_CVTUDQ2PD256_MASK,
29561 IX86_BUILTIN_CVTUDQ2PD128_MASK,
29562 IX86_BUILTIN_CVTDQ2PS256_MASK,
29563 IX86_BUILTIN_CVTDQ2PS128_MASK,
29564 IX86_BUILTIN_CVTUDQ2PS256_MASK,
29565 IX86_BUILTIN_CVTUDQ2PS128_MASK,
29566 IX86_BUILTIN_CVTPS2PD256_MASK,
29567 IX86_BUILTIN_CVTPS2PD128_MASK,
29568 IX86_BUILTIN_PBROADCASTB256_MASK,
29569 IX86_BUILTIN_PBROADCASTB256_GPR_MASK,
29570 IX86_BUILTIN_PBROADCASTB128_MASK,
29571 IX86_BUILTIN_PBROADCASTB128_GPR_MASK,
29572 IX86_BUILTIN_PBROADCASTW256_MASK,
29573 IX86_BUILTIN_PBROADCASTW256_GPR_MASK,
29574 IX86_BUILTIN_PBROADCASTW128_MASK,
29575 IX86_BUILTIN_PBROADCASTW128_GPR_MASK,
29576 IX86_BUILTIN_PBROADCASTD256_MASK,
29577 IX86_BUILTIN_PBROADCASTD256_GPR_MASK,
29578 IX86_BUILTIN_PBROADCASTD128_MASK,
29579 IX86_BUILTIN_PBROADCASTD128_GPR_MASK,
29580 IX86_BUILTIN_PBROADCASTQ256_MASK,
29581 IX86_BUILTIN_PBROADCASTQ256_GPR_MASK,
29582 IX86_BUILTIN_PBROADCASTQ128_MASK,
29583 IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
29584 IX86_BUILTIN_BROADCASTSS256,
29585 IX86_BUILTIN_BROADCASTSS128,
29586 IX86_BUILTIN_BROADCASTSD256,
29587 IX86_BUILTIN_EXTRACTF64X2_256,
29588 IX86_BUILTIN_EXTRACTI64X2_256,
29589 IX86_BUILTIN_INSERTF32X4_256,
29590 IX86_BUILTIN_INSERTI32X4_256,
29591 IX86_BUILTIN_PMOVSXBW256_MASK,
29592 IX86_BUILTIN_PMOVSXBW128_MASK,
29593 IX86_BUILTIN_PMOVSXBD256_MASK,
29594 IX86_BUILTIN_PMOVSXBD128_MASK,
29595 IX86_BUILTIN_PMOVSXBQ256_MASK,
29596 IX86_BUILTIN_PMOVSXBQ128_MASK,
29597 IX86_BUILTIN_PMOVSXWD256_MASK,
29598 IX86_BUILTIN_PMOVSXWD128_MASK,
29599 IX86_BUILTIN_PMOVSXWQ256_MASK,
29600 IX86_BUILTIN_PMOVSXWQ128_MASK,
29601 IX86_BUILTIN_PMOVSXDQ256_MASK,
29602 IX86_BUILTIN_PMOVSXDQ128_MASK,
29603 IX86_BUILTIN_PMOVZXBW256_MASK,
29604 IX86_BUILTIN_PMOVZXBW128_MASK,
29605 IX86_BUILTIN_PMOVZXBD256_MASK,
29606 IX86_BUILTIN_PMOVZXBD128_MASK,
29607 IX86_BUILTIN_PMOVZXBQ256_MASK,
29608 IX86_BUILTIN_PMOVZXBQ128_MASK,
29609 IX86_BUILTIN_PMOVZXWD256_MASK,
29610 IX86_BUILTIN_PMOVZXWD128_MASK,
29611 IX86_BUILTIN_PMOVZXWQ256_MASK,
29612 IX86_BUILTIN_PMOVZXWQ128_MASK,
29613 IX86_BUILTIN_PMOVZXDQ256_MASK,
29614 IX86_BUILTIN_PMOVZXDQ128_MASK,
29615 IX86_BUILTIN_REDUCEPD256_MASK,
29616 IX86_BUILTIN_REDUCEPD128_MASK,
29617 IX86_BUILTIN_REDUCEPS256_MASK,
29618 IX86_BUILTIN_REDUCEPS128_MASK,
29619 IX86_BUILTIN_REDUCESD_MASK,
29620 IX86_BUILTIN_REDUCESS_MASK,
29621 IX86_BUILTIN_VPERMVARHI256_MASK,
29622 IX86_BUILTIN_VPERMVARHI128_MASK,
29623 IX86_BUILTIN_VPERMT2VARHI256,
29624 IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
29625 IX86_BUILTIN_VPERMT2VARHI128,
29626 IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
29627 IX86_BUILTIN_VPERMI2VARHI256,
29628 IX86_BUILTIN_VPERMI2VARHI128,
29629 IX86_BUILTIN_RCP14PD256,
29630 IX86_BUILTIN_RCP14PD128,
29631 IX86_BUILTIN_RCP14PS256,
29632 IX86_BUILTIN_RCP14PS128,
29633 IX86_BUILTIN_RSQRT14PD256_MASK,
29634 IX86_BUILTIN_RSQRT14PD128_MASK,
29635 IX86_BUILTIN_RSQRT14PS256_MASK,
29636 IX86_BUILTIN_RSQRT14PS128_MASK,
29637 IX86_BUILTIN_SQRTPD256_MASK,
29638 IX86_BUILTIN_SQRTPD128_MASK,
29639 IX86_BUILTIN_SQRTPS256_MASK,
29640 IX86_BUILTIN_SQRTPS128_MASK,
29641 IX86_BUILTIN_PADDB128_MASK,
29642 IX86_BUILTIN_PADDW128_MASK,
29643 IX86_BUILTIN_PADDD128_MASK,
29644 IX86_BUILTIN_PADDQ128_MASK,
29645 IX86_BUILTIN_PSUBB128_MASK,
29646 IX86_BUILTIN_PSUBW128_MASK,
29647 IX86_BUILTIN_PSUBD128_MASK,
29648 IX86_BUILTIN_PSUBQ128_MASK,
29649 IX86_BUILTIN_PADDSB128_MASK,
29650 IX86_BUILTIN_PADDSW128_MASK,
29651 IX86_BUILTIN_PSUBSB128_MASK,
29652 IX86_BUILTIN_PSUBSW128_MASK,
29653 IX86_BUILTIN_PADDUSB128_MASK,
29654 IX86_BUILTIN_PADDUSW128_MASK,
29655 IX86_BUILTIN_PSUBUSB128_MASK,
29656 IX86_BUILTIN_PSUBUSW128_MASK,
29657 IX86_BUILTIN_PADDB256_MASK,
29658 IX86_BUILTIN_PADDW256_MASK,
29659 IX86_BUILTIN_PADDD256_MASK,
29660 IX86_BUILTIN_PADDQ256_MASK,
29661 IX86_BUILTIN_PADDSB256_MASK,
29662 IX86_BUILTIN_PADDSW256_MASK,
29663 IX86_BUILTIN_PADDUSB256_MASK,
29664 IX86_BUILTIN_PADDUSW256_MASK,
29665 IX86_BUILTIN_PSUBB256_MASK,
29666 IX86_BUILTIN_PSUBW256_MASK,
29667 IX86_BUILTIN_PSUBD256_MASK,
29668 IX86_BUILTIN_PSUBQ256_MASK,
29669 IX86_BUILTIN_PSUBSB256_MASK,
29670 IX86_BUILTIN_PSUBSW256_MASK,
29671 IX86_BUILTIN_PSUBUSB256_MASK,
29672 IX86_BUILTIN_PSUBUSW256_MASK,
29673 IX86_BUILTIN_SHUF_F64x2_256,
29674 IX86_BUILTIN_SHUF_I64x2_256,
29675 IX86_BUILTIN_SHUF_I32x4_256,
29676 IX86_BUILTIN_SHUF_F32x4_256,
29677 IX86_BUILTIN_PMOVWB128,
29678 IX86_BUILTIN_PMOVWB256,
29679 IX86_BUILTIN_PMOVSWB128,
29680 IX86_BUILTIN_PMOVSWB256,
29681 IX86_BUILTIN_PMOVUSWB128,
29682 IX86_BUILTIN_PMOVUSWB256,
29683 IX86_BUILTIN_PMOVDB128,
29684 IX86_BUILTIN_PMOVDB256,
29685 IX86_BUILTIN_PMOVSDB128,
29686 IX86_BUILTIN_PMOVSDB256,
29687 IX86_BUILTIN_PMOVUSDB128,
29688 IX86_BUILTIN_PMOVUSDB256,
29689 IX86_BUILTIN_PMOVDW128,
29690 IX86_BUILTIN_PMOVDW256,
29691 IX86_BUILTIN_PMOVSDW128,
29692 IX86_BUILTIN_PMOVSDW256,
29693 IX86_BUILTIN_PMOVUSDW128,
29694 IX86_BUILTIN_PMOVUSDW256,
29695 IX86_BUILTIN_PMOVQB128,
29696 IX86_BUILTIN_PMOVQB256,
29697 IX86_BUILTIN_PMOVSQB128,
29698 IX86_BUILTIN_PMOVSQB256,
29699 IX86_BUILTIN_PMOVUSQB128,
29700 IX86_BUILTIN_PMOVUSQB256,
29701 IX86_BUILTIN_PMOVQW128,
29702 IX86_BUILTIN_PMOVQW256,
29703 IX86_BUILTIN_PMOVSQW128,
29704 IX86_BUILTIN_PMOVSQW256,
29705 IX86_BUILTIN_PMOVUSQW128,
29706 IX86_BUILTIN_PMOVUSQW256,
29707 IX86_BUILTIN_PMOVQD128,
29708 IX86_BUILTIN_PMOVQD256,
29709 IX86_BUILTIN_PMOVSQD128,
29710 IX86_BUILTIN_PMOVSQD256,
29711 IX86_BUILTIN_PMOVUSQD128,
29712 IX86_BUILTIN_PMOVUSQD256,
29713 IX86_BUILTIN_RANGEPD256,
29714 IX86_BUILTIN_RANGEPD128,
29715 IX86_BUILTIN_RANGEPS256,
29716 IX86_BUILTIN_RANGEPS128,
29717 IX86_BUILTIN_GETEXPPS256,
29718 IX86_BUILTIN_GETEXPPD256,
29719 IX86_BUILTIN_GETEXPPS128,
29720 IX86_BUILTIN_GETEXPPD128,
29721 IX86_BUILTIN_FIXUPIMMPD256_MASK,
29722 IX86_BUILTIN_FIXUPIMMPD256_MASKZ,
29723 IX86_BUILTIN_FIXUPIMMPS256_MASK,
29724 IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
29725 IX86_BUILTIN_FIXUPIMMPD128_MASK,
29726 IX86_BUILTIN_FIXUPIMMPD128_MASKZ,
29727 IX86_BUILTIN_FIXUPIMMPS128_MASK,
29728 IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
29729 IX86_BUILTIN_PABSQ256,
29730 IX86_BUILTIN_PABSQ128,
29731 IX86_BUILTIN_PABSD256_MASK,
29732 IX86_BUILTIN_PABSD128_MASK,
29733 IX86_BUILTIN_PMULHRSW256_MASK,
29734 IX86_BUILTIN_PMULHRSW128_MASK,
29735 IX86_BUILTIN_PMULHUW128_MASK,
29736 IX86_BUILTIN_PMULHUW256_MASK,
29737 IX86_BUILTIN_PMULHW256_MASK,
29738 IX86_BUILTIN_PMULHW128_MASK,
29739 IX86_BUILTIN_PMULLW256_MASK,
29740 IX86_BUILTIN_PMULLW128_MASK,
29741 IX86_BUILTIN_PMULLQ256,
29742 IX86_BUILTIN_PMULLQ128,
29743 IX86_BUILTIN_ANDPD256_MASK,
29744 IX86_BUILTIN_ANDPD128_MASK,
29745 IX86_BUILTIN_ANDPS256_MASK,
29746 IX86_BUILTIN_ANDPS128_MASK,
29747 IX86_BUILTIN_ANDNPD256_MASK,
29748 IX86_BUILTIN_ANDNPD128_MASK,
29749 IX86_BUILTIN_ANDNPS256_MASK,
29750 IX86_BUILTIN_ANDNPS128_MASK,
29751 IX86_BUILTIN_PSLLWI128_MASK,
29752 IX86_BUILTIN_PSLLDI128_MASK,
29753 IX86_BUILTIN_PSLLQI128_MASK,
29754 IX86_BUILTIN_PSLLW128_MASK,
29755 IX86_BUILTIN_PSLLD128_MASK,
29756 IX86_BUILTIN_PSLLQ128_MASK,
29757 IX86_BUILTIN_PSLLWI256_MASK ,
29758 IX86_BUILTIN_PSLLW256_MASK,
29759 IX86_BUILTIN_PSLLDI256_MASK,
29760 IX86_BUILTIN_PSLLD256_MASK,
29761 IX86_BUILTIN_PSLLQI256_MASK,
29762 IX86_BUILTIN_PSLLQ256_MASK,
29763 IX86_BUILTIN_PSRADI128_MASK,
29764 IX86_BUILTIN_PSRAD128_MASK,
29765 IX86_BUILTIN_PSRADI256_MASK,
29766 IX86_BUILTIN_PSRAD256_MASK,
29767 IX86_BUILTIN_PSRAQI128_MASK,
29768 IX86_BUILTIN_PSRAQ128_MASK,
29769 IX86_BUILTIN_PSRAQI256_MASK,
29770 IX86_BUILTIN_PSRAQ256_MASK,
29771 IX86_BUILTIN_PANDD256,
29772 IX86_BUILTIN_PANDD128,
29773 IX86_BUILTIN_PSRLDI128_MASK,
29774 IX86_BUILTIN_PSRLD128_MASK,
29775 IX86_BUILTIN_PSRLDI256_MASK,
29776 IX86_BUILTIN_PSRLD256_MASK,
29777 IX86_BUILTIN_PSRLQI128_MASK,
29778 IX86_BUILTIN_PSRLQ128_MASK,
29779 IX86_BUILTIN_PSRLQI256_MASK,
29780 IX86_BUILTIN_PSRLQ256_MASK,
29781 IX86_BUILTIN_PANDQ256,
29782 IX86_BUILTIN_PANDQ128,
29783 IX86_BUILTIN_PANDND256,
29784 IX86_BUILTIN_PANDND128,
29785 IX86_BUILTIN_PANDNQ256,
29786 IX86_BUILTIN_PANDNQ128,
29787 IX86_BUILTIN_PORD256,
29788 IX86_BUILTIN_PORD128,
29789 IX86_BUILTIN_PORQ256,
29790 IX86_BUILTIN_PORQ128,
29791 IX86_BUILTIN_PXORD256,
29792 IX86_BUILTIN_PXORD128,
29793 IX86_BUILTIN_PXORQ256,
29794 IX86_BUILTIN_PXORQ128,
29795 IX86_BUILTIN_PACKSSWB256_MASK,
29796 IX86_BUILTIN_PACKSSWB128_MASK,
29797 IX86_BUILTIN_PACKUSWB256_MASK,
29798 IX86_BUILTIN_PACKUSWB128_MASK,
29799 IX86_BUILTIN_RNDSCALEPS256,
29800 IX86_BUILTIN_RNDSCALEPD256,
29801 IX86_BUILTIN_RNDSCALEPS128,
29802 IX86_BUILTIN_RNDSCALEPD128,
29803 IX86_BUILTIN_VTERNLOGQ256_MASK,
29804 IX86_BUILTIN_VTERNLOGQ256_MASKZ,
29805 IX86_BUILTIN_VTERNLOGD256_MASK,
29806 IX86_BUILTIN_VTERNLOGD256_MASKZ,
29807 IX86_BUILTIN_VTERNLOGQ128_MASK,
29808 IX86_BUILTIN_VTERNLOGQ128_MASKZ,
29809 IX86_BUILTIN_VTERNLOGD128_MASK,
29810 IX86_BUILTIN_VTERNLOGD128_MASKZ,
29811 IX86_BUILTIN_SCALEFPD256,
29812 IX86_BUILTIN_SCALEFPS256,
29813 IX86_BUILTIN_SCALEFPD128,
29814 IX86_BUILTIN_SCALEFPS128,
29815 IX86_BUILTIN_VFMADDPD256_MASK,
29816 IX86_BUILTIN_VFMADDPD256_MASK3,
29817 IX86_BUILTIN_VFMADDPD256_MASKZ,
29818 IX86_BUILTIN_VFMADDPD128_MASK,
29819 IX86_BUILTIN_VFMADDPD128_MASK3,
29820 IX86_BUILTIN_VFMADDPD128_MASKZ,
29821 IX86_BUILTIN_VFMADDPS256_MASK,
29822 IX86_BUILTIN_VFMADDPS256_MASK3,
29823 IX86_BUILTIN_VFMADDPS256_MASKZ,
29824 IX86_BUILTIN_VFMADDPS128_MASK,
29825 IX86_BUILTIN_VFMADDPS128_MASK3,
29826 IX86_BUILTIN_VFMADDPS128_MASKZ,
29827 IX86_BUILTIN_VFMSUBPD256_MASK3,
29828 IX86_BUILTIN_VFMSUBPD128_MASK3,
29829 IX86_BUILTIN_VFMSUBPS256_MASK3,
29830 IX86_BUILTIN_VFMSUBPS128_MASK3,
29831 IX86_BUILTIN_VFNMADDPD256_MASK,
29832 IX86_BUILTIN_VFNMADDPD128_MASK,
29833 IX86_BUILTIN_VFNMADDPS256_MASK,
29834 IX86_BUILTIN_VFNMADDPS128_MASK,
29835 IX86_BUILTIN_VFNMSUBPD256_MASK,
29836 IX86_BUILTIN_VFNMSUBPD256_MASK3,
29837 IX86_BUILTIN_VFNMSUBPD128_MASK,
29838 IX86_BUILTIN_VFNMSUBPD128_MASK3,
29839 IX86_BUILTIN_VFNMSUBPS256_MASK,
29840 IX86_BUILTIN_VFNMSUBPS256_MASK3,
29841 IX86_BUILTIN_VFNMSUBPS128_MASK,
29842 IX86_BUILTIN_VFNMSUBPS128_MASK3,
29843 IX86_BUILTIN_VFMADDSUBPD256_MASK,
29844 IX86_BUILTIN_VFMADDSUBPD256_MASK3,
29845 IX86_BUILTIN_VFMADDSUBPD256_MASKZ,
29846 IX86_BUILTIN_VFMADDSUBPD128_MASK,
29847 IX86_BUILTIN_VFMADDSUBPD128_MASK3,
29848 IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
29849 IX86_BUILTIN_VFMADDSUBPS256_MASK,
29850 IX86_BUILTIN_VFMADDSUBPS256_MASK3,
29851 IX86_BUILTIN_VFMADDSUBPS256_MASKZ,
29852 IX86_BUILTIN_VFMADDSUBPS128_MASK,
29853 IX86_BUILTIN_VFMADDSUBPS128_MASK3,
29854 IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
29855 IX86_BUILTIN_VFMSUBADDPD256_MASK3,
29856 IX86_BUILTIN_VFMSUBADDPD128_MASK3,
29857 IX86_BUILTIN_VFMSUBADDPS256_MASK3,
29858 IX86_BUILTIN_VFMSUBADDPS128_MASK3,
29859 IX86_BUILTIN_INSERTF64X2_256,
29860 IX86_BUILTIN_INSERTI64X2_256,
29861 IX86_BUILTIN_PSRAVV16HI,
29862 IX86_BUILTIN_PSRAVV8HI,
29863 IX86_BUILTIN_PMADDUBSW256_MASK,
29864 IX86_BUILTIN_PMADDUBSW128_MASK,
29865 IX86_BUILTIN_PMADDWD256_MASK,
29866 IX86_BUILTIN_PMADDWD128_MASK,
29867 IX86_BUILTIN_PSRLVV16HI,
29868 IX86_BUILTIN_PSRLVV8HI,
29869 IX86_BUILTIN_CVTPS2DQ256_MASK,
29870 IX86_BUILTIN_CVTPS2DQ128_MASK,
29871 IX86_BUILTIN_CVTPS2UDQ256,
29872 IX86_BUILTIN_CVTPS2UDQ128,
29873 IX86_BUILTIN_CVTPS2QQ256,
29874 IX86_BUILTIN_CVTPS2QQ128,
29875 IX86_BUILTIN_CVTPS2UQQ256,
29876 IX86_BUILTIN_CVTPS2UQQ128,
29877 IX86_BUILTIN_GETMANTPS256,
29878 IX86_BUILTIN_GETMANTPS128,
29879 IX86_BUILTIN_GETMANTPD256,
29880 IX86_BUILTIN_GETMANTPD128,
29881 IX86_BUILTIN_MOVDDUP256_MASK,
29882 IX86_BUILTIN_MOVDDUP128_MASK,
29883 IX86_BUILTIN_MOVSHDUP256_MASK,
29884 IX86_BUILTIN_MOVSHDUP128_MASK,
29885 IX86_BUILTIN_MOVSLDUP256_MASK,
29886 IX86_BUILTIN_MOVSLDUP128_MASK,
29887 IX86_BUILTIN_CVTQQ2PS256,
29888 IX86_BUILTIN_CVTQQ2PS128,
29889 IX86_BUILTIN_CVTUQQ2PS256,
29890 IX86_BUILTIN_CVTUQQ2PS128,
29891 IX86_BUILTIN_CVTQQ2PD256,
29892 IX86_BUILTIN_CVTQQ2PD128,
29893 IX86_BUILTIN_CVTUQQ2PD256,
29894 IX86_BUILTIN_CVTUQQ2PD128,
29895 IX86_BUILTIN_VPERMT2VARQ256,
29896 IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
29897 IX86_BUILTIN_VPERMT2VARD256,
29898 IX86_BUILTIN_VPERMT2VARD256_MASKZ,
29899 IX86_BUILTIN_VPERMI2VARQ256,
29900 IX86_BUILTIN_VPERMI2VARD256,
29901 IX86_BUILTIN_VPERMT2VARPD256,
29902 IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
29903 IX86_BUILTIN_VPERMT2VARPS256,
29904 IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
29905 IX86_BUILTIN_VPERMI2VARPD256,
29906 IX86_BUILTIN_VPERMI2VARPS256,
29907 IX86_BUILTIN_VPERMT2VARQ128,
29908 IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
29909 IX86_BUILTIN_VPERMT2VARD128,
29910 IX86_BUILTIN_VPERMT2VARD128_MASKZ,
29911 IX86_BUILTIN_VPERMI2VARQ128,
29912 IX86_BUILTIN_VPERMI2VARD128,
29913 IX86_BUILTIN_VPERMT2VARPD128,
29914 IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
29915 IX86_BUILTIN_VPERMT2VARPS128,
29916 IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
29917 IX86_BUILTIN_VPERMI2VARPD128,
29918 IX86_BUILTIN_VPERMI2VARPS128,
29919 IX86_BUILTIN_PSHUFB256_MASK,
29920 IX86_BUILTIN_PSHUFB128_MASK,
29921 IX86_BUILTIN_PSHUFHW256_MASK,
29922 IX86_BUILTIN_PSHUFHW128_MASK,
29923 IX86_BUILTIN_PSHUFLW256_MASK,
29924 IX86_BUILTIN_PSHUFLW128_MASK,
29925 IX86_BUILTIN_PSHUFD256_MASK,
29926 IX86_BUILTIN_PSHUFD128_MASK,
29927 IX86_BUILTIN_SHUFPD256_MASK,
29928 IX86_BUILTIN_SHUFPD128_MASK,
29929 IX86_BUILTIN_SHUFPS256_MASK,
29930 IX86_BUILTIN_SHUFPS128_MASK,
29931 IX86_BUILTIN_PROLVQ256,
29932 IX86_BUILTIN_PROLVQ128,
29933 IX86_BUILTIN_PROLQ256,
29934 IX86_BUILTIN_PROLQ128,
29935 IX86_BUILTIN_PRORVQ256,
29936 IX86_BUILTIN_PRORVQ128,
29937 IX86_BUILTIN_PRORQ256,
29938 IX86_BUILTIN_PRORQ128,
29939 IX86_BUILTIN_PSRAVQ128,
29940 IX86_BUILTIN_PSRAVQ256,
29941 IX86_BUILTIN_PSLLVV4DI_MASK,
29942 IX86_BUILTIN_PSLLVV2DI_MASK,
29943 IX86_BUILTIN_PSLLVV8SI_MASK,
29944 IX86_BUILTIN_PSLLVV4SI_MASK,
29945 IX86_BUILTIN_PSRAVV8SI_MASK,
29946 IX86_BUILTIN_PSRAVV4SI_MASK,
29947 IX86_BUILTIN_PSRLVV4DI_MASK,
29948 IX86_BUILTIN_PSRLVV2DI_MASK,
29949 IX86_BUILTIN_PSRLVV8SI_MASK,
29950 IX86_BUILTIN_PSRLVV4SI_MASK,
29951 IX86_BUILTIN_PSRAWI256_MASK,
29952 IX86_BUILTIN_PSRAW256_MASK,
29953 IX86_BUILTIN_PSRAWI128_MASK,
29954 IX86_BUILTIN_PSRAW128_MASK,
29955 IX86_BUILTIN_PSRLWI256_MASK,
29956 IX86_BUILTIN_PSRLW256_MASK,
29957 IX86_BUILTIN_PSRLWI128_MASK,
29958 IX86_BUILTIN_PSRLW128_MASK,
29959 IX86_BUILTIN_PRORVD256,
29960 IX86_BUILTIN_PROLVD256,
29961 IX86_BUILTIN_PRORD256,
29962 IX86_BUILTIN_PROLD256,
29963 IX86_BUILTIN_PRORVD128,
29964 IX86_BUILTIN_PROLVD128,
29965 IX86_BUILTIN_PRORD128,
29966 IX86_BUILTIN_PROLD128,
29967 IX86_BUILTIN_FPCLASSPD256,
29968 IX86_BUILTIN_FPCLASSPD128,
29969 IX86_BUILTIN_FPCLASSSD,
29970 IX86_BUILTIN_FPCLASSPS256,
29971 IX86_BUILTIN_FPCLASSPS128,
29972 IX86_BUILTIN_FPCLASSSS,
29973 IX86_BUILTIN_CVTB2MASK128,
29974 IX86_BUILTIN_CVTB2MASK256,
29975 IX86_BUILTIN_CVTW2MASK128,
29976 IX86_BUILTIN_CVTW2MASK256,
29977 IX86_BUILTIN_CVTD2MASK128,
29978 IX86_BUILTIN_CVTD2MASK256,
29979 IX86_BUILTIN_CVTQ2MASK128,
29980 IX86_BUILTIN_CVTQ2MASK256,
29981 IX86_BUILTIN_CVTMASK2B128,
29982 IX86_BUILTIN_CVTMASK2B256,
29983 IX86_BUILTIN_CVTMASK2W128,
29984 IX86_BUILTIN_CVTMASK2W256,
29985 IX86_BUILTIN_CVTMASK2D128,
29986 IX86_BUILTIN_CVTMASK2D256,
29987 IX86_BUILTIN_CVTMASK2Q128,
29988 IX86_BUILTIN_CVTMASK2Q256,
29989 IX86_BUILTIN_PCMPEQB128_MASK,
29990 IX86_BUILTIN_PCMPEQB256_MASK,
29991 IX86_BUILTIN_PCMPEQW128_MASK,
29992 IX86_BUILTIN_PCMPEQW256_MASK,
29993 IX86_BUILTIN_PCMPEQD128_MASK,
29994 IX86_BUILTIN_PCMPEQD256_MASK,
29995 IX86_BUILTIN_PCMPEQQ128_MASK,
29996 IX86_BUILTIN_PCMPEQQ256_MASK,
29997 IX86_BUILTIN_PCMPGTB128_MASK,
29998 IX86_BUILTIN_PCMPGTB256_MASK,
29999 IX86_BUILTIN_PCMPGTW128_MASK,
30000 IX86_BUILTIN_PCMPGTW256_MASK,
30001 IX86_BUILTIN_PCMPGTD128_MASK,
30002 IX86_BUILTIN_PCMPGTD256_MASK,
30003 IX86_BUILTIN_PCMPGTQ128_MASK,
30004 IX86_BUILTIN_PCMPGTQ256_MASK,
30005 IX86_BUILTIN_PTESTMB128,
30006 IX86_BUILTIN_PTESTMB256,
30007 IX86_BUILTIN_PTESTMW128,
30008 IX86_BUILTIN_PTESTMW256,
30009 IX86_BUILTIN_PTESTMD128,
30010 IX86_BUILTIN_PTESTMD256,
30011 IX86_BUILTIN_PTESTMQ128,
30012 IX86_BUILTIN_PTESTMQ256,
30013 IX86_BUILTIN_PTESTNMB128,
30014 IX86_BUILTIN_PTESTNMB256,
30015 IX86_BUILTIN_PTESTNMW128,
30016 IX86_BUILTIN_PTESTNMW256,
30017 IX86_BUILTIN_PTESTNMD128,
30018 IX86_BUILTIN_PTESTNMD256,
30019 IX86_BUILTIN_PTESTNMQ128,
30020 IX86_BUILTIN_PTESTNMQ256,
30021 IX86_BUILTIN_PBROADCASTMB128,
30022 IX86_BUILTIN_PBROADCASTMB256,
30023 IX86_BUILTIN_PBROADCASTMW128,
30024 IX86_BUILTIN_PBROADCASTMW256,
30025 IX86_BUILTIN_COMPRESSPD256,
30026 IX86_BUILTIN_COMPRESSPD128,
30027 IX86_BUILTIN_COMPRESSPS256,
30028 IX86_BUILTIN_COMPRESSPS128,
30029 IX86_BUILTIN_PCOMPRESSQ256,
30030 IX86_BUILTIN_PCOMPRESSQ128,
30031 IX86_BUILTIN_PCOMPRESSD256,
30032 IX86_BUILTIN_PCOMPRESSD128,
30033 IX86_BUILTIN_EXPANDPD256,
30034 IX86_BUILTIN_EXPANDPD128,
30035 IX86_BUILTIN_EXPANDPS256,
30036 IX86_BUILTIN_EXPANDPS128,
30037 IX86_BUILTIN_PEXPANDQ256,
30038 IX86_BUILTIN_PEXPANDQ128,
30039 IX86_BUILTIN_PEXPANDD256,
30040 IX86_BUILTIN_PEXPANDD128,
30041 IX86_BUILTIN_EXPANDPD256Z,
30042 IX86_BUILTIN_EXPANDPD128Z,
30043 IX86_BUILTIN_EXPANDPS256Z,
30044 IX86_BUILTIN_EXPANDPS128Z,
30045 IX86_BUILTIN_PEXPANDQ256Z,
30046 IX86_BUILTIN_PEXPANDQ128Z,
30047 IX86_BUILTIN_PEXPANDD256Z,
30048 IX86_BUILTIN_PEXPANDD128Z,
30049 IX86_BUILTIN_PMAXSD256_MASK,
30050 IX86_BUILTIN_PMINSD256_MASK,
30051 IX86_BUILTIN_PMAXUD256_MASK,
30052 IX86_BUILTIN_PMINUD256_MASK,
30053 IX86_BUILTIN_PMAXSD128_MASK,
30054 IX86_BUILTIN_PMINSD128_MASK,
30055 IX86_BUILTIN_PMAXUD128_MASK,
30056 IX86_BUILTIN_PMINUD128_MASK,
30057 IX86_BUILTIN_PMAXSQ256_MASK,
30058 IX86_BUILTIN_PMINSQ256_MASK,
30059 IX86_BUILTIN_PMAXUQ256_MASK,
30060 IX86_BUILTIN_PMINUQ256_MASK,
30061 IX86_BUILTIN_PMAXSQ128_MASK,
30062 IX86_BUILTIN_PMINSQ128_MASK,
30063 IX86_BUILTIN_PMAXUQ128_MASK,
30064 IX86_BUILTIN_PMINUQ128_MASK,
30065 IX86_BUILTIN_PMINSB256_MASK,
30066 IX86_BUILTIN_PMINUB256_MASK,
30067 IX86_BUILTIN_PMAXSB256_MASK,
30068 IX86_BUILTIN_PMAXUB256_MASK,
30069 IX86_BUILTIN_PMINSB128_MASK,
30070 IX86_BUILTIN_PMINUB128_MASK,
30071 IX86_BUILTIN_PMAXSB128_MASK,
30072 IX86_BUILTIN_PMAXUB128_MASK,
30073 IX86_BUILTIN_PMINSW256_MASK,
30074 IX86_BUILTIN_PMINUW256_MASK,
30075 IX86_BUILTIN_PMAXSW256_MASK,
30076 IX86_BUILTIN_PMAXUW256_MASK,
30077 IX86_BUILTIN_PMINSW128_MASK,
30078 IX86_BUILTIN_PMINUW128_MASK,
30079 IX86_BUILTIN_PMAXSW128_MASK,
30080 IX86_BUILTIN_PMAXUW128_MASK,
30081 IX86_BUILTIN_VPCONFLICTQ256,
30082 IX86_BUILTIN_VPCONFLICTD256,
30083 IX86_BUILTIN_VPCLZCNTQ256,
30084 IX86_BUILTIN_VPCLZCNTD256,
30085 IX86_BUILTIN_UNPCKHPD256_MASK,
30086 IX86_BUILTIN_UNPCKHPD128_MASK,
30087 IX86_BUILTIN_UNPCKHPS256_MASK,
30088 IX86_BUILTIN_UNPCKHPS128_MASK,
30089 IX86_BUILTIN_UNPCKLPD256_MASK,
30090 IX86_BUILTIN_UNPCKLPD128_MASK,
30091 IX86_BUILTIN_UNPCKLPS256_MASK,
30092 IX86_BUILTIN_VPCONFLICTQ128,
30093 IX86_BUILTIN_VPCONFLICTD128,
30094 IX86_BUILTIN_VPCLZCNTQ128,
30095 IX86_BUILTIN_VPCLZCNTD128,
30096 IX86_BUILTIN_UNPCKLPS128_MASK,
30097 IX86_BUILTIN_ALIGND256,
30098 IX86_BUILTIN_ALIGNQ256,
30099 IX86_BUILTIN_ALIGND128,
30100 IX86_BUILTIN_ALIGNQ128,
30101 IX86_BUILTIN_CVTPS2PH256_MASK,
30102 IX86_BUILTIN_CVTPS2PH_MASK,
30103 IX86_BUILTIN_CVTPH2PS_MASK,
30104 IX86_BUILTIN_CVTPH2PS256_MASK,
30105 IX86_BUILTIN_PUNPCKHDQ128_MASK,
30106 IX86_BUILTIN_PUNPCKHDQ256_MASK,
30107 IX86_BUILTIN_PUNPCKHQDQ128_MASK,
30108 IX86_BUILTIN_PUNPCKHQDQ256_MASK,
30109 IX86_BUILTIN_PUNPCKLDQ128_MASK,
30110 IX86_BUILTIN_PUNPCKLDQ256_MASK,
30111 IX86_BUILTIN_PUNPCKLQDQ128_MASK,
30112 IX86_BUILTIN_PUNPCKLQDQ256_MASK,
30113 IX86_BUILTIN_PUNPCKHBW128_MASK,
30114 IX86_BUILTIN_PUNPCKHBW256_MASK,
30115 IX86_BUILTIN_PUNPCKHWD128_MASK,
30116 IX86_BUILTIN_PUNPCKHWD256_MASK,
30117 IX86_BUILTIN_PUNPCKLBW128_MASK,
30118 IX86_BUILTIN_PUNPCKLBW256_MASK,
30119 IX86_BUILTIN_PUNPCKLWD128_MASK,
30120 IX86_BUILTIN_PUNPCKLWD256_MASK,
30121 IX86_BUILTIN_PSLLVV16HI,
30122 IX86_BUILTIN_PSLLVV8HI,
30123 IX86_BUILTIN_PACKSSDW256_MASK,
30124 IX86_BUILTIN_PACKSSDW128_MASK,
30125 IX86_BUILTIN_PACKUSDW256_MASK,
30126 IX86_BUILTIN_PACKUSDW128_MASK,
30127 IX86_BUILTIN_PAVGB256_MASK,
30128 IX86_BUILTIN_PAVGW256_MASK,
30129 IX86_BUILTIN_PAVGB128_MASK,
30130 IX86_BUILTIN_PAVGW128_MASK,
30131 IX86_BUILTIN_VPERMVARSF256_MASK,
30132 IX86_BUILTIN_VPERMVARDF256_MASK,
30133 IX86_BUILTIN_VPERMDF256_MASK,
30134 IX86_BUILTIN_PABSB256_MASK,
30135 IX86_BUILTIN_PABSB128_MASK,
30136 IX86_BUILTIN_PABSW256_MASK,
30137 IX86_BUILTIN_PABSW128_MASK,
30138 IX86_BUILTIN_VPERMILVARPD_MASK,
30139 IX86_BUILTIN_VPERMILVARPS_MASK,
30140 IX86_BUILTIN_VPERMILVARPD256_MASK,
30141 IX86_BUILTIN_VPERMILVARPS256_MASK,
30142 IX86_BUILTIN_VPERMILPD_MASK,
30143 IX86_BUILTIN_VPERMILPS_MASK,
30144 IX86_BUILTIN_VPERMILPD256_MASK,
30145 IX86_BUILTIN_VPERMILPS256_MASK,
30146 IX86_BUILTIN_BLENDMQ256,
30147 IX86_BUILTIN_BLENDMD256,
30148 IX86_BUILTIN_BLENDMPD256,
30149 IX86_BUILTIN_BLENDMPS256,
30150 IX86_BUILTIN_BLENDMQ128,
30151 IX86_BUILTIN_BLENDMD128,
30152 IX86_BUILTIN_BLENDMPD128,
30153 IX86_BUILTIN_BLENDMPS128,
30154 IX86_BUILTIN_BLENDMW256,
30155 IX86_BUILTIN_BLENDMB256,
30156 IX86_BUILTIN_BLENDMW128,
30157 IX86_BUILTIN_BLENDMB128,
30158 IX86_BUILTIN_PMULLD256_MASK,
30159 IX86_BUILTIN_PMULLD128_MASK,
30160 IX86_BUILTIN_PMULUDQ256_MASK,
30161 IX86_BUILTIN_PMULDQ256_MASK,
30162 IX86_BUILTIN_PMULDQ128_MASK,
30163 IX86_BUILTIN_PMULUDQ128_MASK,
30164 IX86_BUILTIN_CVTPD2PS256_MASK,
30165 IX86_BUILTIN_CVTPD2PS_MASK,
30166 IX86_BUILTIN_VPERMVARSI256_MASK,
30167 IX86_BUILTIN_VPERMVARDI256_MASK,
30168 IX86_BUILTIN_VPERMDI256_MASK,
30169 IX86_BUILTIN_CMPQ256,
30170 IX86_BUILTIN_CMPD256,
30171 IX86_BUILTIN_UCMPQ256,
30172 IX86_BUILTIN_UCMPD256,
30173 IX86_BUILTIN_CMPB256,
30174 IX86_BUILTIN_CMPW256,
30175 IX86_BUILTIN_UCMPB256,
30176 IX86_BUILTIN_UCMPW256,
30177 IX86_BUILTIN_CMPPD256_MASK,
30178 IX86_BUILTIN_CMPPS256_MASK,
30179 IX86_BUILTIN_CMPQ128,
30180 IX86_BUILTIN_CMPD128,
30181 IX86_BUILTIN_UCMPQ128,
30182 IX86_BUILTIN_UCMPD128,
30183 IX86_BUILTIN_CMPB128,
30184 IX86_BUILTIN_CMPW128,
30185 IX86_BUILTIN_UCMPB128,
30186 IX86_BUILTIN_UCMPW128,
30187 IX86_BUILTIN_CMPPD128_MASK,
30188 IX86_BUILTIN_CMPPS128_MASK,
30190 IX86_BUILTIN_GATHER3SIV8SF,
30191 IX86_BUILTIN_GATHER3SIV4SF,
30192 IX86_BUILTIN_GATHER3SIV4DF,
30193 IX86_BUILTIN_GATHER3SIV2DF,
30194 IX86_BUILTIN_GATHER3DIV8SF,
30195 IX86_BUILTIN_GATHER3DIV4SF,
30196 IX86_BUILTIN_GATHER3DIV4DF,
30197 IX86_BUILTIN_GATHER3DIV2DF,
30198 IX86_BUILTIN_GATHER3SIV8SI,
30199 IX86_BUILTIN_GATHER3SIV4SI,
30200 IX86_BUILTIN_GATHER3SIV4DI,
30201 IX86_BUILTIN_GATHER3SIV2DI,
30202 IX86_BUILTIN_GATHER3DIV8SI,
30203 IX86_BUILTIN_GATHER3DIV4SI,
30204 IX86_BUILTIN_GATHER3DIV4DI,
30205 IX86_BUILTIN_GATHER3DIV2DI,
30206 IX86_BUILTIN_SCATTERSIV8SF,
30207 IX86_BUILTIN_SCATTERSIV4SF,
30208 IX86_BUILTIN_SCATTERSIV4DF,
30209 IX86_BUILTIN_SCATTERSIV2DF,
30210 IX86_BUILTIN_SCATTERDIV8SF,
30211 IX86_BUILTIN_SCATTERDIV4SF,
30212 IX86_BUILTIN_SCATTERDIV4DF,
30213 IX86_BUILTIN_SCATTERDIV2DF,
30214 IX86_BUILTIN_SCATTERSIV8SI,
30215 IX86_BUILTIN_SCATTERSIV4SI,
30216 IX86_BUILTIN_SCATTERSIV4DI,
30217 IX86_BUILTIN_SCATTERSIV2DI,
30218 IX86_BUILTIN_SCATTERDIV8SI,
30219 IX86_BUILTIN_SCATTERDIV4SI,
30220 IX86_BUILTIN_SCATTERDIV4DI,
30221 IX86_BUILTIN_SCATTERDIV2DI,
30223 /* AVX512DQ. */
30224 IX86_BUILTIN_RANGESD128,
30225 IX86_BUILTIN_RANGESS128,
30226 IX86_BUILTIN_KUNPCKWD,
30227 IX86_BUILTIN_KUNPCKDQ,
30228 IX86_BUILTIN_BROADCASTF32x2_512,
30229 IX86_BUILTIN_BROADCASTI32x2_512,
30230 IX86_BUILTIN_BROADCASTF64X2_512,
30231 IX86_BUILTIN_BROADCASTI64X2_512,
30232 IX86_BUILTIN_BROADCASTF32X8_512,
30233 IX86_BUILTIN_BROADCASTI32X8_512,
30234 IX86_BUILTIN_EXTRACTF64X2_512,
30235 IX86_BUILTIN_EXTRACTF32X8,
30236 IX86_BUILTIN_EXTRACTI64X2_512,
30237 IX86_BUILTIN_EXTRACTI32X8,
30238 IX86_BUILTIN_REDUCEPD512_MASK,
30239 IX86_BUILTIN_REDUCEPS512_MASK,
30240 IX86_BUILTIN_PMULLQ512,
30241 IX86_BUILTIN_XORPD512,
30242 IX86_BUILTIN_XORPS512,
30243 IX86_BUILTIN_ORPD512,
30244 IX86_BUILTIN_ORPS512,
30245 IX86_BUILTIN_ANDPD512,
30246 IX86_BUILTIN_ANDPS512,
30247 IX86_BUILTIN_ANDNPD512,
30248 IX86_BUILTIN_ANDNPS512,
30249 IX86_BUILTIN_INSERTF32X8,
30250 IX86_BUILTIN_INSERTI32X8,
30251 IX86_BUILTIN_INSERTF64X2_512,
30252 IX86_BUILTIN_INSERTI64X2_512,
30253 IX86_BUILTIN_FPCLASSPD512,
30254 IX86_BUILTIN_FPCLASSPS512,
30255 IX86_BUILTIN_CVTD2MASK512,
30256 IX86_BUILTIN_CVTQ2MASK512,
30257 IX86_BUILTIN_CVTMASK2D512,
30258 IX86_BUILTIN_CVTMASK2Q512,
30259 IX86_BUILTIN_CVTPD2QQ512,
30260 IX86_BUILTIN_CVTPS2QQ512,
30261 IX86_BUILTIN_CVTPD2UQQ512,
30262 IX86_BUILTIN_CVTPS2UQQ512,
30263 IX86_BUILTIN_CVTQQ2PS512,
30264 IX86_BUILTIN_CVTUQQ2PS512,
30265 IX86_BUILTIN_CVTQQ2PD512,
30266 IX86_BUILTIN_CVTUQQ2PD512,
30267 IX86_BUILTIN_CVTTPS2QQ512,
30268 IX86_BUILTIN_CVTTPS2UQQ512,
30269 IX86_BUILTIN_CVTTPD2QQ512,
30270 IX86_BUILTIN_CVTTPD2UQQ512,
30271 IX86_BUILTIN_RANGEPS512,
30272 IX86_BUILTIN_RANGEPD512,
30274 /* AVX512BW. */
30275 IX86_BUILTIN_PACKUSDW512,
30276 IX86_BUILTIN_PACKSSDW512,
30277 IX86_BUILTIN_LOADDQUHI512_MASK,
30278 IX86_BUILTIN_LOADDQUQI512_MASK,
30279 IX86_BUILTIN_PSLLDQ512,
30280 IX86_BUILTIN_PSRLDQ512,
30281 IX86_BUILTIN_STOREDQUHI512_MASK,
30282 IX86_BUILTIN_STOREDQUQI512_MASK,
30283 IX86_BUILTIN_PALIGNR512,
30284 IX86_BUILTIN_PALIGNR512_MASK,
30285 IX86_BUILTIN_MOVDQUHI512_MASK,
30286 IX86_BUILTIN_MOVDQUQI512_MASK,
30287 IX86_BUILTIN_PSADBW512,
30288 IX86_BUILTIN_DBPSADBW512,
30289 IX86_BUILTIN_PBROADCASTB512,
30290 IX86_BUILTIN_PBROADCASTB512_GPR,
30291 IX86_BUILTIN_PBROADCASTW512,
30292 IX86_BUILTIN_PBROADCASTW512_GPR,
30293 IX86_BUILTIN_PMOVSXBW512_MASK,
30294 IX86_BUILTIN_PMOVZXBW512_MASK,
30295 IX86_BUILTIN_VPERMVARHI512_MASK,
30296 IX86_BUILTIN_VPERMT2VARHI512,
30297 IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
30298 IX86_BUILTIN_VPERMI2VARHI512,
30299 IX86_BUILTIN_PAVGB512,
30300 IX86_BUILTIN_PAVGW512,
30301 IX86_BUILTIN_PADDB512,
30302 IX86_BUILTIN_PSUBB512,
30303 IX86_BUILTIN_PSUBSB512,
30304 IX86_BUILTIN_PADDSB512,
30305 IX86_BUILTIN_PSUBUSB512,
30306 IX86_BUILTIN_PADDUSB512,
30307 IX86_BUILTIN_PSUBW512,
30308 IX86_BUILTIN_PADDW512,
30309 IX86_BUILTIN_PSUBSW512,
30310 IX86_BUILTIN_PADDSW512,
30311 IX86_BUILTIN_PSUBUSW512,
30312 IX86_BUILTIN_PADDUSW512,
30313 IX86_BUILTIN_PMAXUW512,
30314 IX86_BUILTIN_PMAXSW512,
30315 IX86_BUILTIN_PMINUW512,
30316 IX86_BUILTIN_PMINSW512,
30317 IX86_BUILTIN_PMAXUB512,
30318 IX86_BUILTIN_PMAXSB512,
30319 IX86_BUILTIN_PMINUB512,
30320 IX86_BUILTIN_PMINSB512,
30321 IX86_BUILTIN_PMOVWB512,
30322 IX86_BUILTIN_PMOVSWB512,
30323 IX86_BUILTIN_PMOVUSWB512,
30324 IX86_BUILTIN_PMULHRSW512_MASK,
30325 IX86_BUILTIN_PMULHUW512_MASK,
30326 IX86_BUILTIN_PMULHW512_MASK,
30327 IX86_BUILTIN_PMULLW512_MASK,
30328 IX86_BUILTIN_PSLLWI512_MASK,
30329 IX86_BUILTIN_PSLLW512_MASK,
30330 IX86_BUILTIN_PACKSSWB512,
30331 IX86_BUILTIN_PACKUSWB512,
30332 IX86_BUILTIN_PSRAVV32HI,
30333 IX86_BUILTIN_PMADDUBSW512_MASK,
30334 IX86_BUILTIN_PMADDWD512_MASK,
30335 IX86_BUILTIN_PSRLVV32HI,
30336 IX86_BUILTIN_PUNPCKHBW512,
30337 IX86_BUILTIN_PUNPCKHWD512,
30338 IX86_BUILTIN_PUNPCKLBW512,
30339 IX86_BUILTIN_PUNPCKLWD512,
30340 IX86_BUILTIN_PSHUFB512,
30341 IX86_BUILTIN_PSHUFHW512,
30342 IX86_BUILTIN_PSHUFLW512,
30343 IX86_BUILTIN_PSRAWI512,
30344 IX86_BUILTIN_PSRAW512,
30345 IX86_BUILTIN_PSRLWI512,
30346 IX86_BUILTIN_PSRLW512,
30347 IX86_BUILTIN_CVTB2MASK512,
30348 IX86_BUILTIN_CVTW2MASK512,
30349 IX86_BUILTIN_CVTMASK2B512,
30350 IX86_BUILTIN_CVTMASK2W512,
30351 IX86_BUILTIN_PCMPEQB512_MASK,
30352 IX86_BUILTIN_PCMPEQW512_MASK,
30353 IX86_BUILTIN_PCMPGTB512_MASK,
30354 IX86_BUILTIN_PCMPGTW512_MASK,
30355 IX86_BUILTIN_PTESTMB512,
30356 IX86_BUILTIN_PTESTMW512,
30357 IX86_BUILTIN_PTESTNMB512,
30358 IX86_BUILTIN_PTESTNMW512,
30359 IX86_BUILTIN_PSLLVV32HI,
30360 IX86_BUILTIN_PABSB512,
30361 IX86_BUILTIN_PABSW512,
30362 IX86_BUILTIN_BLENDMW512,
30363 IX86_BUILTIN_BLENDMB512,
30364 IX86_BUILTIN_CMPB512,
30365 IX86_BUILTIN_CMPW512,
30366 IX86_BUILTIN_UCMPB512,
30367 IX86_BUILTIN_UCMPW512,
30369 /* Alternate 4 and 8 element gather/scatter for the vectorizer
30370 where all operands are 32-byte or 64-byte wide respectively. */
30371 IX86_BUILTIN_GATHERALTSIV4DF,
30372 IX86_BUILTIN_GATHERALTDIV8SF,
30373 IX86_BUILTIN_GATHERALTSIV4DI,
30374 IX86_BUILTIN_GATHERALTDIV8SI,
30375 IX86_BUILTIN_GATHER3ALTDIV16SF,
30376 IX86_BUILTIN_GATHER3ALTDIV16SI,
30377 IX86_BUILTIN_GATHER3ALTSIV4DF,
30378 IX86_BUILTIN_GATHER3ALTDIV8SF,
30379 IX86_BUILTIN_GATHER3ALTSIV4DI,
30380 IX86_BUILTIN_GATHER3ALTDIV8SI,
30381 IX86_BUILTIN_GATHER3ALTSIV8DF,
30382 IX86_BUILTIN_GATHER3ALTSIV8DI,
30383 IX86_BUILTIN_GATHER3DIV16SF,
30384 IX86_BUILTIN_GATHER3DIV16SI,
30385 IX86_BUILTIN_GATHER3DIV8DF,
30386 IX86_BUILTIN_GATHER3DIV8DI,
30387 IX86_BUILTIN_GATHER3SIV16SF,
30388 IX86_BUILTIN_GATHER3SIV16SI,
30389 IX86_BUILTIN_GATHER3SIV8DF,
30390 IX86_BUILTIN_GATHER3SIV8DI,
30391 IX86_BUILTIN_SCATTERALTSIV8DF,
30392 IX86_BUILTIN_SCATTERALTDIV16SF,
30393 IX86_BUILTIN_SCATTERALTSIV8DI,
30394 IX86_BUILTIN_SCATTERALTDIV16SI,
30395 IX86_BUILTIN_SCATTERDIV16SF,
30396 IX86_BUILTIN_SCATTERDIV16SI,
30397 IX86_BUILTIN_SCATTERDIV8DF,
30398 IX86_BUILTIN_SCATTERDIV8DI,
30399 IX86_BUILTIN_SCATTERSIV16SF,
30400 IX86_BUILTIN_SCATTERSIV16SI,
30401 IX86_BUILTIN_SCATTERSIV8DF,
30402 IX86_BUILTIN_SCATTERSIV8DI,
30404 /* AVX512PF */
30405 IX86_BUILTIN_GATHERPFQPD,
30406 IX86_BUILTIN_GATHERPFDPS,
30407 IX86_BUILTIN_GATHERPFDPD,
30408 IX86_BUILTIN_GATHERPFQPS,
30409 IX86_BUILTIN_SCATTERPFDPD,
30410 IX86_BUILTIN_SCATTERPFDPS,
30411 IX86_BUILTIN_SCATTERPFQPD,
30412 IX86_BUILTIN_SCATTERPFQPS,
30414 /* AVX-512ER */
30415 IX86_BUILTIN_EXP2PD_MASK,
30416 IX86_BUILTIN_EXP2PS_MASK,
30417 IX86_BUILTIN_EXP2PS,
30418 IX86_BUILTIN_RCP28PD,
30419 IX86_BUILTIN_RCP28PS,
30420 IX86_BUILTIN_RCP28SD,
30421 IX86_BUILTIN_RCP28SS,
30422 IX86_BUILTIN_RSQRT28PD,
30423 IX86_BUILTIN_RSQRT28PS,
30424 IX86_BUILTIN_RSQRT28SD,
30425 IX86_BUILTIN_RSQRT28SS,
30427 /* AVX-512IFMA */
30428 IX86_BUILTIN_VPMADD52LUQ512,
30429 IX86_BUILTIN_VPMADD52HUQ512,
30430 IX86_BUILTIN_VPMADD52LUQ256,
30431 IX86_BUILTIN_VPMADD52HUQ256,
30432 IX86_BUILTIN_VPMADD52LUQ128,
30433 IX86_BUILTIN_VPMADD52HUQ128,
30434 IX86_BUILTIN_VPMADD52LUQ512_MASKZ,
30435 IX86_BUILTIN_VPMADD52HUQ512_MASKZ,
30436 IX86_BUILTIN_VPMADD52LUQ256_MASKZ,
30437 IX86_BUILTIN_VPMADD52HUQ256_MASKZ,
30438 IX86_BUILTIN_VPMADD52LUQ128_MASKZ,
30439 IX86_BUILTIN_VPMADD52HUQ128_MASKZ,
30441 /* AVX-512VBMI */
30442 IX86_BUILTIN_VPMULTISHIFTQB512,
30443 IX86_BUILTIN_VPMULTISHIFTQB256,
30444 IX86_BUILTIN_VPMULTISHIFTQB128,
30445 IX86_BUILTIN_VPERMVARQI512_MASK,
30446 IX86_BUILTIN_VPERMT2VARQI512,
30447 IX86_BUILTIN_VPERMT2VARQI512_MASKZ,
30448 IX86_BUILTIN_VPERMI2VARQI512,
30449 IX86_BUILTIN_VPERMVARQI256_MASK,
30450 IX86_BUILTIN_VPERMVARQI128_MASK,
30451 IX86_BUILTIN_VPERMT2VARQI256,
30452 IX86_BUILTIN_VPERMT2VARQI256_MASKZ,
30453 IX86_BUILTIN_VPERMT2VARQI128,
30454 IX86_BUILTIN_VPERMT2VARQI128_MASKZ,
30455 IX86_BUILTIN_VPERMI2VARQI256,
30456 IX86_BUILTIN_VPERMI2VARQI128,
30458 /* SHA builtins. */
30459 IX86_BUILTIN_SHA1MSG1,
30460 IX86_BUILTIN_SHA1MSG2,
30461 IX86_BUILTIN_SHA1NEXTE,
30462 IX86_BUILTIN_SHA1RNDS4,
30463 IX86_BUILTIN_SHA256MSG1,
30464 IX86_BUILTIN_SHA256MSG2,
30465 IX86_BUILTIN_SHA256RNDS2,
30467 /* CLWB instructions. */
30468 IX86_BUILTIN_CLWB,
30470 /* PCOMMIT instructions. */
30471 IX86_BUILTIN_PCOMMIT,
30473 /* CLFLUSHOPT instructions. */
30474 IX86_BUILTIN_CLFLUSHOPT,
30476 /* TFmode support builtins. */
30477 IX86_BUILTIN_INFQ,
30478 IX86_BUILTIN_HUGE_VALQ,
30479 IX86_BUILTIN_FABSQ,
30480 IX86_BUILTIN_COPYSIGNQ,
30482 /* Vectorizer support builtins. */
30483 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
30484 IX86_BUILTIN_CPYSGNPS,
30485 IX86_BUILTIN_CPYSGNPD,
30486 IX86_BUILTIN_CPYSGNPS256,
30487 IX86_BUILTIN_CPYSGNPS512,
30488 IX86_BUILTIN_CPYSGNPD256,
30489 IX86_BUILTIN_CPYSGNPD512,
30490 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
30491 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
30494 /* FMA4 instructions. */
30495 IX86_BUILTIN_VFMADDSS,
30496 IX86_BUILTIN_VFMADDSD,
30497 IX86_BUILTIN_VFMADDPS,
30498 IX86_BUILTIN_VFMADDPD,
30499 IX86_BUILTIN_VFMADDPS256,
30500 IX86_BUILTIN_VFMADDPD256,
30501 IX86_BUILTIN_VFMADDSUBPS,
30502 IX86_BUILTIN_VFMADDSUBPD,
30503 IX86_BUILTIN_VFMADDSUBPS256,
30504 IX86_BUILTIN_VFMADDSUBPD256,
30506 /* FMA3 instructions. */
30507 IX86_BUILTIN_VFMADDSS3,
30508 IX86_BUILTIN_VFMADDSD3,
30510 /* XOP instructions. */
30511 IX86_BUILTIN_VPCMOV,
30512 IX86_BUILTIN_VPCMOV_V2DI,
30513 IX86_BUILTIN_VPCMOV_V4SI,
30514 IX86_BUILTIN_VPCMOV_V8HI,
30515 IX86_BUILTIN_VPCMOV_V16QI,
30516 IX86_BUILTIN_VPCMOV_V4SF,
30517 IX86_BUILTIN_VPCMOV_V2DF,
30518 IX86_BUILTIN_VPCMOV256,
30519 IX86_BUILTIN_VPCMOV_V4DI256,
30520 IX86_BUILTIN_VPCMOV_V8SI256,
30521 IX86_BUILTIN_VPCMOV_V16HI256,
30522 IX86_BUILTIN_VPCMOV_V32QI256,
30523 IX86_BUILTIN_VPCMOV_V8SF256,
30524 IX86_BUILTIN_VPCMOV_V4DF256,
30526 IX86_BUILTIN_VPPERM,
30528 IX86_BUILTIN_VPMACSSWW,
30529 IX86_BUILTIN_VPMACSWW,
30530 IX86_BUILTIN_VPMACSSWD,
30531 IX86_BUILTIN_VPMACSWD,
30532 IX86_BUILTIN_VPMACSSDD,
30533 IX86_BUILTIN_VPMACSDD,
30534 IX86_BUILTIN_VPMACSSDQL,
30535 IX86_BUILTIN_VPMACSSDQH,
30536 IX86_BUILTIN_VPMACSDQL,
30537 IX86_BUILTIN_VPMACSDQH,
30538 IX86_BUILTIN_VPMADCSSWD,
30539 IX86_BUILTIN_VPMADCSWD,
30541 IX86_BUILTIN_VPHADDBW,
30542 IX86_BUILTIN_VPHADDBD,
30543 IX86_BUILTIN_VPHADDBQ,
30544 IX86_BUILTIN_VPHADDWD,
30545 IX86_BUILTIN_VPHADDWQ,
30546 IX86_BUILTIN_VPHADDDQ,
30547 IX86_BUILTIN_VPHADDUBW,
30548 IX86_BUILTIN_VPHADDUBD,
30549 IX86_BUILTIN_VPHADDUBQ,
30550 IX86_BUILTIN_VPHADDUWD,
30551 IX86_BUILTIN_VPHADDUWQ,
30552 IX86_BUILTIN_VPHADDUDQ,
30553 IX86_BUILTIN_VPHSUBBW,
30554 IX86_BUILTIN_VPHSUBWD,
30555 IX86_BUILTIN_VPHSUBDQ,
30557 IX86_BUILTIN_VPROTB,
30558 IX86_BUILTIN_VPROTW,
30559 IX86_BUILTIN_VPROTD,
30560 IX86_BUILTIN_VPROTQ,
30561 IX86_BUILTIN_VPROTB_IMM,
30562 IX86_BUILTIN_VPROTW_IMM,
30563 IX86_BUILTIN_VPROTD_IMM,
30564 IX86_BUILTIN_VPROTQ_IMM,
30566 IX86_BUILTIN_VPSHLB,
30567 IX86_BUILTIN_VPSHLW,
30568 IX86_BUILTIN_VPSHLD,
30569 IX86_BUILTIN_VPSHLQ,
30570 IX86_BUILTIN_VPSHAB,
30571 IX86_BUILTIN_VPSHAW,
30572 IX86_BUILTIN_VPSHAD,
30573 IX86_BUILTIN_VPSHAQ,
30575 IX86_BUILTIN_VFRCZSS,
30576 IX86_BUILTIN_VFRCZSD,
30577 IX86_BUILTIN_VFRCZPS,
30578 IX86_BUILTIN_VFRCZPD,
30579 IX86_BUILTIN_VFRCZPS256,
30580 IX86_BUILTIN_VFRCZPD256,
30582 IX86_BUILTIN_VPCOMEQUB,
30583 IX86_BUILTIN_VPCOMNEUB,
30584 IX86_BUILTIN_VPCOMLTUB,
30585 IX86_BUILTIN_VPCOMLEUB,
30586 IX86_BUILTIN_VPCOMGTUB,
30587 IX86_BUILTIN_VPCOMGEUB,
30588 IX86_BUILTIN_VPCOMFALSEUB,
30589 IX86_BUILTIN_VPCOMTRUEUB,
30591 IX86_BUILTIN_VPCOMEQUW,
30592 IX86_BUILTIN_VPCOMNEUW,
30593 IX86_BUILTIN_VPCOMLTUW,
30594 IX86_BUILTIN_VPCOMLEUW,
30595 IX86_BUILTIN_VPCOMGTUW,
30596 IX86_BUILTIN_VPCOMGEUW,
30597 IX86_BUILTIN_VPCOMFALSEUW,
30598 IX86_BUILTIN_VPCOMTRUEUW,
30600 IX86_BUILTIN_VPCOMEQUD,
30601 IX86_BUILTIN_VPCOMNEUD,
30602 IX86_BUILTIN_VPCOMLTUD,
30603 IX86_BUILTIN_VPCOMLEUD,
30604 IX86_BUILTIN_VPCOMGTUD,
30605 IX86_BUILTIN_VPCOMGEUD,
30606 IX86_BUILTIN_VPCOMFALSEUD,
30607 IX86_BUILTIN_VPCOMTRUEUD,
30609 IX86_BUILTIN_VPCOMEQUQ,
30610 IX86_BUILTIN_VPCOMNEUQ,
30611 IX86_BUILTIN_VPCOMLTUQ,
30612 IX86_BUILTIN_VPCOMLEUQ,
30613 IX86_BUILTIN_VPCOMGTUQ,
30614 IX86_BUILTIN_VPCOMGEUQ,
30615 IX86_BUILTIN_VPCOMFALSEUQ,
30616 IX86_BUILTIN_VPCOMTRUEUQ,
30618 IX86_BUILTIN_VPCOMEQB,
30619 IX86_BUILTIN_VPCOMNEB,
30620 IX86_BUILTIN_VPCOMLTB,
30621 IX86_BUILTIN_VPCOMLEB,
30622 IX86_BUILTIN_VPCOMGTB,
30623 IX86_BUILTIN_VPCOMGEB,
30624 IX86_BUILTIN_VPCOMFALSEB,
30625 IX86_BUILTIN_VPCOMTRUEB,
30627 IX86_BUILTIN_VPCOMEQW,
30628 IX86_BUILTIN_VPCOMNEW,
30629 IX86_BUILTIN_VPCOMLTW,
30630 IX86_BUILTIN_VPCOMLEW,
30631 IX86_BUILTIN_VPCOMGTW,
30632 IX86_BUILTIN_VPCOMGEW,
30633 IX86_BUILTIN_VPCOMFALSEW,
30634 IX86_BUILTIN_VPCOMTRUEW,
30636 IX86_BUILTIN_VPCOMEQD,
30637 IX86_BUILTIN_VPCOMNED,
30638 IX86_BUILTIN_VPCOMLTD,
30639 IX86_BUILTIN_VPCOMLED,
30640 IX86_BUILTIN_VPCOMGTD,
30641 IX86_BUILTIN_VPCOMGED,
30642 IX86_BUILTIN_VPCOMFALSED,
30643 IX86_BUILTIN_VPCOMTRUED,
30645 IX86_BUILTIN_VPCOMEQQ,
30646 IX86_BUILTIN_VPCOMNEQ,
30647 IX86_BUILTIN_VPCOMLTQ,
30648 IX86_BUILTIN_VPCOMLEQ,
30649 IX86_BUILTIN_VPCOMGTQ,
30650 IX86_BUILTIN_VPCOMGEQ,
30651 IX86_BUILTIN_VPCOMFALSEQ,
30652 IX86_BUILTIN_VPCOMTRUEQ,
30654 /* LWP instructions. */
30655 IX86_BUILTIN_LLWPCB,
30656 IX86_BUILTIN_SLWPCB,
30657 IX86_BUILTIN_LWPVAL32,
30658 IX86_BUILTIN_LWPVAL64,
30659 IX86_BUILTIN_LWPINS32,
30660 IX86_BUILTIN_LWPINS64,
30662 IX86_BUILTIN_CLZS,
30664 /* RTM */
30665 IX86_BUILTIN_XBEGIN,
30666 IX86_BUILTIN_XEND,
30667 IX86_BUILTIN_XABORT,
30668 IX86_BUILTIN_XTEST,
30670 /* MPX */
30671 IX86_BUILTIN_BNDMK,
30672 IX86_BUILTIN_BNDSTX,
30673 IX86_BUILTIN_BNDLDX,
30674 IX86_BUILTIN_BNDCL,
30675 IX86_BUILTIN_BNDCU,
30676 IX86_BUILTIN_BNDRET,
30677 IX86_BUILTIN_BNDNARROW,
30678 IX86_BUILTIN_BNDINT,
30679 IX86_BUILTIN_SIZEOF,
30680 IX86_BUILTIN_BNDLOWER,
30681 IX86_BUILTIN_BNDUPPER,
30683 /* BMI instructions. */
30684 IX86_BUILTIN_BEXTR32,
30685 IX86_BUILTIN_BEXTR64,
30686 IX86_BUILTIN_CTZS,
30688 /* TBM instructions. */
30689 IX86_BUILTIN_BEXTRI32,
30690 IX86_BUILTIN_BEXTRI64,
30692 /* BMI2 instructions. */
30693 IX86_BUILTIN_BZHI32,
30694 IX86_BUILTIN_BZHI64,
30695 IX86_BUILTIN_PDEP32,
30696 IX86_BUILTIN_PDEP64,
30697 IX86_BUILTIN_PEXT32,
30698 IX86_BUILTIN_PEXT64,
30700 /* ADX instructions. */
30701 IX86_BUILTIN_ADDCARRYX32,
30702 IX86_BUILTIN_ADDCARRYX64,
30704 /* SBB instructions. */
30705 IX86_BUILTIN_SBB32,
30706 IX86_BUILTIN_SBB64,
30708 /* FSGSBASE instructions. */
30709 IX86_BUILTIN_RDFSBASE32,
30710 IX86_BUILTIN_RDFSBASE64,
30711 IX86_BUILTIN_RDGSBASE32,
30712 IX86_BUILTIN_RDGSBASE64,
30713 IX86_BUILTIN_WRFSBASE32,
30714 IX86_BUILTIN_WRFSBASE64,
30715 IX86_BUILTIN_WRGSBASE32,
30716 IX86_BUILTIN_WRGSBASE64,
30718 /* RDRND instructions. */
30719 IX86_BUILTIN_RDRAND16_STEP,
30720 IX86_BUILTIN_RDRAND32_STEP,
30721 IX86_BUILTIN_RDRAND64_STEP,
30723 /* RDSEED instructions. */
30724 IX86_BUILTIN_RDSEED16_STEP,
30725 IX86_BUILTIN_RDSEED32_STEP,
30726 IX86_BUILTIN_RDSEED64_STEP,
30728 /* F16C instructions. */
30729 IX86_BUILTIN_CVTPH2PS,
30730 IX86_BUILTIN_CVTPH2PS256,
30731 IX86_BUILTIN_CVTPS2PH,
30732 IX86_BUILTIN_CVTPS2PH256,
30734 /* MONITORX and MWAITX instrucions. */
30735 IX86_BUILTIN_MONITORX,
30736 IX86_BUILTIN_MWAITX,
30738 /* CFString built-in for darwin */
30739 IX86_BUILTIN_CFSTRING,
30741 /* Builtins to get CPU type and supported features. */
30742 IX86_BUILTIN_CPU_INIT,
30743 IX86_BUILTIN_CPU_IS,
30744 IX86_BUILTIN_CPU_SUPPORTS,
30746 /* Read/write FLAGS register built-ins. */
30747 IX86_BUILTIN_READ_FLAGS,
30748 IX86_BUILTIN_WRITE_FLAGS,
30750 IX86_BUILTIN_MAX
30751 };
30753 /* Table for the ix86 builtin decls. */
30756 /* Table of all of the builtin functions that are possible with different ISA's
30757 but are waiting to be built until a function is declared to use that
30758 ISA. */
30767 };
30771 /* Bits that can still enable any inclusion of a builtin. */
30774 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
30775 of which isa_flags to use in the ix86_builtins_isa array. Stores the
30776 function decl in the ix86_builtins array. Returns the function decl or
30777 NULL_TREE, if the builtin was not added.
30779 If the front end has a special hook for builtin functions, delay adding
30780 builtin functions that aren't in the current ISA until the ISA is changed
30781 with function specific optimization. Doing so, can save about 300K for the
30782 default compiler. When the builtin is expanded, check at that time whether
30783 it is valid.
30785 If the front end doesn't have a special hook, record all builtins, even if
30786 it isn't an instruction set in the current ISA in case the user uses
30787 function specific options for a different ISA, so that we don't get scope
30788 errors if a builtin is added in the middle of a function scope. */
30794 {
30798 {
30807 {
30813 }
30814 else
30815 {
30816 /* Just a MASK where set_and_not_built_p == true can potentially
30817 include a builtin. */
30826 }
30827 }
30830 }
30832 /* Like def_builtin, but also marks the function decl "const". */
30837 {
30841 else
30845 }
30847 /* Add any new builtin functions for a given ISA that may not have been
30848 declared. This saves a bit of space compared to adding all of the
30849 declarations to the tree, even if we didn't use them. */
30851 static void
30853 {
30857 /* Bits in ISA value can be removed from potential isa values. */
30865 {
30868 {
30871 /* Don't define the builtin again. */
30877 NULL_TREE);
30884 NULL_TREE);
30887 }
30888 }
30891 }
30893 /* Bits for builtin_description.flag. */
30895 /* Set when we don't support the comparison natively, and should
30896 swap_comparison in order to support it. */
30897 #define BUILTIN_DESC_SWAP_OPERANDS 1
30899 struct builtin_description
30900 {
30907 };
30910 {
30911 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
30912 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
30913 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
30914 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
30915 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
30916 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
30917 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
30918 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
30919 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
30920 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
30921 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
30922 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
30923 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
30924 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
30925 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
30926 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
30927 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
30928 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
30929 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
30930 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
30931 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
30932 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
30933 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
30934 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
30935 };
30938 {
30939 /* SSE4.2 */
30940 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
30941 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
30942 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
30943 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
30944 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
30945 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
30946 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
30947 };
30950 {
30951 /* SSE4.2 */
30952 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
30953 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
30954 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
30955 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
30956 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
30957 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
30958 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
30959 };
30961 /* Special builtins with variable number of arguments. */
30963 {
30964 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
30965 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
30966 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
30968 /* 80387 (for use internally for atomic compound assignment). */
30969 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
30970 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
30971 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) USHORT_FTYPE_VOID },
30972 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
30974 /* MMX */
30975 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30977 /* 3DNow! */
30978 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30980 /* FXSR, XSAVE, XSAVEOPT, XSAVEC and XSAVES. */
30981 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
30982 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
30983 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30984 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30985 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30986 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xsaves", IX86_BUILTIN_XSAVES, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30987 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xrstors", IX86_BUILTIN_XRSTORS, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30988 { OPTION_MASK_ISA_XSAVEC, CODE_FOR_nothing, "__builtin_ia32_xsavec", IX86_BUILTIN_XSAVEC, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30990 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30991 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30992 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30993 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30994 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30995 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaves64", IX86_BUILTIN_XSAVES64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30996 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30997 { OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30999 /* SSE */
31000 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
31001 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
31002 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
31004 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
31005 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
31006 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
31007 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
31009 /* SSE or 3DNow!A */
31010 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
31011 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
31013 /* SSE2 */
31014 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
31015 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
31016 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
31017 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
31018 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
31019 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
31020 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
31021 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
31022 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
31023 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
31025 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
31026 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
31028 /* SSE3 */
31029 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
31031 /* SSE4.1 */
31032 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
31034 /* SSE4A */
31035 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
31036 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
31038 /* AVX */
31039 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
31040 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
31042 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
31043 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
31044 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
31045 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
31046 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
31048 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
31049 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
31050 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
31051 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
31052 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
31053 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
31054 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
31056 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
31057 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
31058 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
31060 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
31061 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
31062 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
31063 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
31064 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
31065 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
31066 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
31067 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
31069 /* AVX2 */
31070 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
31071 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
31072 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
31073 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
31074 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
31075 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
31076 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
31077 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
31078 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
31080 /* AVX512F */
31081 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_UHI },
31082 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_UHI },
31083 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_UQI },
31084 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_UQI },
31085 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_UHI },
31086 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_UHI },
31087 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_UHI },
31088 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_UHI },
31089 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_UQI },
31090 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_UQI },
31091 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_UQI },
31092 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_UQI },
31093 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_UHI },
31094 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_UQI },
31095 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_UQI },
31096 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_UHI },
31097 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_UHI },
31098 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_UHI },
31099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_UQI },
31100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_UQI },
31101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
31102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
31103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
31104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
31105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_UHI },
31106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_UQI },
31107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_UQI },
31108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_UQI },
31109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_UQI },
31110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_UQI },
31111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_UQI },
31112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_UQI },
31113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_UQI },
31114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_UHI },
31115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_UHI },
31116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_UHI },
31117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_UQI },
31118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_UQI },
31119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_UQI },
31120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_UHI },
31121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_UHI },
31122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_UHI },
31123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_UHI },
31124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_UHI },
31125 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_UHI },
31126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_UQI },
31127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_UQI },
31129 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
31130 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
31131 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
31132 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
31133 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
31134 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
31136 /* FSGSBASE */
31137 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
31138 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
31139 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
31140 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
31141 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
31142 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
31143 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
31144 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
31146 /* RTM */
31147 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
31148 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
31149 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
31151 /* AVX512BW */
31152 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_loaddquhi512_mask", IX86_BUILTIN_LOADDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_USI },
31153 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_loaddquqi512_mask", IX86_BUILTIN_LOADDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_UDI },
31154 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv32hi_mask, "__builtin_ia32_storedquhi512_mask", IX86_BUILTIN_STOREDQUHI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV32HI_V32HI_USI },
31155 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_UDI },
31157 /* AVX512VL */
31158 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_UHI },
31159 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_loaddquhi128_mask", IX86_BUILTIN_LOADDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_UQI },
31160 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_loaddquqi256_mask", IX86_BUILTIN_LOADDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_USI },
31161 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_loaddquqi128_mask", IX86_BUILTIN_LOADDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_UHI },
31162 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64load256_mask", IX86_BUILTIN_MOVDQA64LOAD256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_UQI },
31163 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64load128_mask", IX86_BUILTIN_MOVDQA64LOAD128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_UQI },
31164 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32load256_mask", IX86_BUILTIN_MOVDQA32LOAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_UQI },
31165 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32load128_mask", IX86_BUILTIN_MOVDQA32LOAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_UQI },
31166 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4di_mask, "__builtin_ia32_movdqa64store256_mask", IX86_BUILTIN_MOVDQA64STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_UQI },
31167 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2di_mask, "__builtin_ia32_movdqa64store128_mask", IX86_BUILTIN_MOVDQA64STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_UQI },
31168 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8si_mask, "__builtin_ia32_movdqa32store256_mask", IX86_BUILTIN_MOVDQA32STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_UQI },
31169 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4si_mask, "__builtin_ia32_movdqa32store128_mask", IX86_BUILTIN_MOVDQA32STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_UQI },
31170 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_loadapd256_mask", IX86_BUILTIN_LOADAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_UQI },
31171 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_loadapd128_mask", IX86_BUILTIN_LOADAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_UQI },
31172 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_loadaps256_mask", IX86_BUILTIN_LOADAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_UQI },
31173 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_loadaps128_mask", IX86_BUILTIN_LOADAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_UQI },
31174 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4df_mask, "__builtin_ia32_storeapd256_mask", IX86_BUILTIN_STOREAPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_UQI },
31175 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2df_mask, "__builtin_ia32_storeapd128_mask", IX86_BUILTIN_STOREAPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_UQI },
31176 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8sf_mask, "__builtin_ia32_storeaps256_mask", IX86_BUILTIN_STOREAPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_UQI },
31177 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4sf_mask, "__builtin_ia32_storeaps128_mask", IX86_BUILTIN_STOREAPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_UQI },
31178 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadupd256_mask, "__builtin_ia32_loadupd256_mask", IX86_BUILTIN_LOADUPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_UQI },
31179 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loadupd_mask, "__builtin_ia32_loadupd128_mask", IX86_BUILTIN_LOADUPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_UQI },
31180 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadups256_mask, "__builtin_ia32_loadups256_mask", IX86_BUILTIN_LOADUPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_UQI },
31181 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_loadups_mask, "__builtin_ia32_loadups128_mask", IX86_BUILTIN_LOADUPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_UQI },
31182 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd256_mask, "__builtin_ia32_storeupd256_mask", IX86_BUILTIN_STOREUPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_UQI },
31183 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd_mask, "__builtin_ia32_storeupd128_mask", IX86_BUILTIN_STOREUPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_UQI },
31184 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups256_mask, "__builtin_ia32_storeups256_mask", IX86_BUILTIN_STOREUPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_UQI },
31185 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups_mask, "__builtin_ia32_storeups128_mask", IX86_BUILTIN_STOREUPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_UQI },
31186 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv4di_mask, "__builtin_ia32_loaddqudi256_mask", IX86_BUILTIN_LOADDQUDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_UQI },
31187 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv2di_mask, "__builtin_ia32_loaddqudi128_mask", IX86_BUILTIN_LOADDQUDI128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_UQI },
31188 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv8si_mask, "__builtin_ia32_loaddqusi256_mask", IX86_BUILTIN_LOADDQUSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_UQI },
31189 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv4si_mask, "__builtin_ia32_loaddqusi128_mask", IX86_BUILTIN_LOADDQUSI128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_UQI },
31190 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4di_mask, "__builtin_ia32_storedqudi256_mask", IX86_BUILTIN_STOREDQUDI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_UQI },
31191 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv2di_mask, "__builtin_ia32_storedqudi128_mask", IX86_BUILTIN_STOREDQUDI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_UQI },
31192 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8si_mask, "__builtin_ia32_storedqusi256_mask", IX86_BUILTIN_STOREDQUSI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_UQI },
31193 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4si_mask, "__builtin_ia32_storedqusi128_mask", IX86_BUILTIN_STOREDQUSI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_UQI },
31194 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16hi_mask, "__builtin_ia32_storedquhi256_mask", IX86_BUILTIN_STOREDQUHI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16HI_UHI },
31195 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8hi_mask, "__builtin_ia32_storedquhi128_mask", IX86_BUILTIN_STOREDQUHI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8HI_UQI },
31196 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv32qi_mask, "__builtin_ia32_storedquqi256_mask", IX86_BUILTIN_STOREDQUQI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV32QI_V32QI_USI },
31197 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16qi_mask, "__builtin_ia32_storedquqi128_mask", IX86_BUILTIN_STOREDQUQI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16QI_UHI },
31198 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4df_mask, "__builtin_ia32_compressstoredf256_mask", IX86_BUILTIN_COMPRESSPDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_UQI },
31199 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2df_mask, "__builtin_ia32_compressstoredf128_mask", IX86_BUILTIN_COMPRESSPDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_UQI },
31200 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8sf_mask, "__builtin_ia32_compressstoresf256_mask", IX86_BUILTIN_COMPRESSPSSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_UQI },
31201 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4sf_mask, "__builtin_ia32_compressstoresf128_mask", IX86_BUILTIN_COMPRESSPSSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_UQI },
31202 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4di_mask, "__builtin_ia32_compressstoredi256_mask", IX86_BUILTIN_PCOMPRESSQSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_UQI },
31203 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2di_mask, "__builtin_ia32_compressstoredi128_mask", IX86_BUILTIN_PCOMPRESSQSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_UQI },
31204 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8si_mask, "__builtin_ia32_compressstoresi256_mask", IX86_BUILTIN_PCOMPRESSDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_UQI },
31205 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4si_mask, "__builtin_ia32_compressstoresi128_mask", IX86_BUILTIN_PCOMPRESSDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_UQI },
31206 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expandloaddf256_mask", IX86_BUILTIN_EXPANDPDLOAD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_UQI },
31207 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expandloaddf128_mask", IX86_BUILTIN_EXPANDPDLOAD128, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_UQI },
31208 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandloadsf256_mask", IX86_BUILTIN_EXPANDPSLOAD256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_UQI },
31209 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandloadsf128_mask", IX86_BUILTIN_EXPANDPSLOAD128, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_UQI },
31210 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expandloaddi256_mask", IX86_BUILTIN_PEXPANDQLOAD256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_UQI },
31211 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expandloaddi128_mask", IX86_BUILTIN_PEXPANDQLOAD128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_UQI },
31212 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandloadsi256_mask", IX86_BUILTIN_PEXPANDDLOAD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_UQI },
31213 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandloadsi128_mask", IX86_BUILTIN_PEXPANDDLOAD128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_UQI },
31214 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expandloaddf256_maskz", IX86_BUILTIN_EXPANDPDLOAD256Z, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_UQI },
31215 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expandloaddf128_maskz", IX86_BUILTIN_EXPANDPDLOAD128Z, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_UQI },
31216 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandloadsf256_maskz", IX86_BUILTIN_EXPANDPSLOAD256Z, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_UQI },
31217 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandloadsf128_maskz", IX86_BUILTIN_EXPANDPSLOAD128Z, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_UQI },
31218 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expandloaddi256_maskz", IX86_BUILTIN_PEXPANDQLOAD256Z, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_UQI },
31219 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expandloaddi128_maskz", IX86_BUILTIN_PEXPANDQLOAD128Z, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_UQI },
31220 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandloadsi256_maskz", IX86_BUILTIN_PEXPANDDLOAD256Z, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_UQI },
31221 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandloadsi128_maskz", IX86_BUILTIN_PEXPANDDLOAD128Z, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_UQI },
31222 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask_store, "__builtin_ia32_pmovqd256mem_mask", IX86_BUILTIN_PMOVQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_UQI },
31223 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask_store, "__builtin_ia32_pmovqd128mem_mask", IX86_BUILTIN_PMOVQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_UQI },
31224 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask_store, "__builtin_ia32_pmovsqd256mem_mask", IX86_BUILTIN_PMOVSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_UQI },
31225 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask_store, "__builtin_ia32_pmovsqd128mem_mask", IX86_BUILTIN_PMOVSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_UQI },
31226 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask_store, "__builtin_ia32_pmovusqd256mem_mask", IX86_BUILTIN_PMOVUSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_UQI },
31227 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask_store, "__builtin_ia32_pmovusqd128mem_mask", IX86_BUILTIN_PMOVUSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_UQI },
31228 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovqw256mem_mask", IX86_BUILTIN_PMOVQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_UQI },
31229 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovqw128mem_mask", IX86_BUILTIN_PMOVQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_UQI },
31230 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovsqw256mem_mask", IX86_BUILTIN_PMOVSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_UQI },
31231 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovsqw128mem_mask", IX86_BUILTIN_PMOVSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_UQI },
31232 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovusqw256mem_mask", IX86_BUILTIN_PMOVUSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_UQI },
31233 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovusqw128mem_mask", IX86_BUILTIN_PMOVUSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_UQI },
31234 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovqb256mem_mask", IX86_BUILTIN_PMOVQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_UQI },
31235 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovqb128mem_mask", IX86_BUILTIN_PMOVQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_UQI },
31236 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovsqb256mem_mask", IX86_BUILTIN_PMOVSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_UQI },
31237 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovsqb128mem_mask", IX86_BUILTIN_PMOVSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_UQI },
31238 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovusqb256mem_mask", IX86_BUILTIN_PMOVUSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_UQI },
31239 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovusqb128mem_mask", IX86_BUILTIN_PMOVUSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_UQI },
31240 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovdb256mem_mask", IX86_BUILTIN_PMOVDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_UQI },
31241 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovdb128mem_mask", IX86_BUILTIN_PMOVDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_UQI },
31242 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovsdb256mem_mask", IX86_BUILTIN_PMOVSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_UQI },
31243 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovsdb128mem_mask", IX86_BUILTIN_PMOVSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_UQI },
31244 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovusdb256mem_mask", IX86_BUILTIN_PMOVUSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_UQI },
31245 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovusdb128mem_mask", IX86_BUILTIN_PMOVUSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_UQI },
31246 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovdw256mem_mask", IX86_BUILTIN_PMOVDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_UQI },
31247 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovdw128mem_mask", IX86_BUILTIN_PMOVDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_UQI },
31248 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovsdw256mem_mask", IX86_BUILTIN_PMOVSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_UQI },
31249 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_UQI },
31250 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_UQI },
31251 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_UQI },
31253 /* PCOMMIT. */
31254 { OPTION_MASK_ISA_PCOMMIT, CODE_FOR_pcommit, "__builtin_ia32_pcommit", IX86_BUILTIN_PCOMMIT, UNKNOWN, (int) VOID_FTYPE_VOID },
31255 };
31257 /* Builtins with variable number of arguments. */
31259 {
31260 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
31261 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
31262 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
31263 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
31264 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
31265 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
31266 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
31268 /* MMX */
31269 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31270 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31271 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31272 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31273 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31274 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31276 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31277 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31278 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31279 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31280 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31281 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31282 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31283 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31285 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31286 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31288 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31289 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31290 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31291 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31293 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31294 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31295 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31296 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31297 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31298 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31300 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31301 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31302 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31303 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31304 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
31305 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
31307 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31308 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
31309 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31311 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
31313 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31314 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31315 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31316 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31317 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31318 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31320 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31321 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31322 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31323 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31324 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31325 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31327 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31328 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31329 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31330 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31332 /* 3DNow! */
31333 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31334 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31335 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31336 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31338 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31339 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31340 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31341 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31342 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31343 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31344 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31345 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31346 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31347 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31348 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31349 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31350 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31351 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31352 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31354 /* 3DNow!A */
31355 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31356 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31357 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31358 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31359 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31360 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31362 /* SSE */
31363 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
31364 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31365 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31366 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31367 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31368 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31369 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31370 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31371 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31372 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31373 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31374 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31376 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31378 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31379 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31380 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31381 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31382 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31383 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31384 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31385 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31387 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31388 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31389 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31390 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31391 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31392 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31393 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31394 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31395 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31396 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31397 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
31398 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31399 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31400 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31401 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31402 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31403 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31404 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31405 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31406 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31408 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31409 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31410 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31411 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31413 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31414 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31415 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31416 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31418 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31420 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31421 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31422 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31423 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31424 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31426 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
31427 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
31428 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
31430 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
31432 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31433 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31434 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31436 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
31437 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
31439 /* SSE MMX or 3Dnow!A */
31440 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31441 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31442 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31444 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31445 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31446 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31447 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31449 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
31450 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
31452 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
31454 /* SSE2 */
31455 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31457 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
31458 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
31459 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31460 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
31461 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
31463 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31464 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31465 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
31466 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31467 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31469 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
31471 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31472 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31473 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31474 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31476 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31477 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
31478 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31480 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31481 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31482 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31483 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31484 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31485 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31486 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31487 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31489 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31490 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31491 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31492 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31493 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
31494 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31495 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31496 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31497 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31498 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31499 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31500 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31501 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31502 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31503 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31504 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31505 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31506 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31507 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31508 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31510 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31511 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31512 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31513 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31515 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31516 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31517 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31518 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31520 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31522 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31523 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31524 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31526 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31528 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31529 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31530 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31531 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31532 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31533 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31534 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31535 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31537 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31538 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31539 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31540 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31541 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31542 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31543 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31544 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31546 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31547 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
31549 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31550 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31551 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31552 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31554 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31555 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31557 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31558 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31559 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31560 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31561 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31562 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31564 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31565 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31566 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31567 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31569 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31570 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31571 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31572 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31573 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31574 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31575 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31576 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31578 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31579 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31580 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31582 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31583 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
31585 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
31586 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31588 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
31590 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
31591 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
31592 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
31593 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
31595 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31596 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31597 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31598 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31599 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31600 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31601 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31603 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31604 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31605 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31606 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31607 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31608 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31609 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31611 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31612 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31613 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31614 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31616 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
31617 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31618 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31620 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
31622 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31624 /* SSE2 MMX */
31625 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31626 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31628 /* SSE3 */
31629 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
31630 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31632 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31633 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31634 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31635 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31636 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31637 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31639 /* SSSE3 */
31640 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31641 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
31642 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31643 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
31644 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31645 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31647 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31648 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31649 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31650 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31651 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31652 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31653 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31654 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31655 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31656 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31657 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31658 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31659 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
31660 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
31661 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31662 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31663 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31664 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31665 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31666 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31667 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31668 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31669 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31670 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31672 /* SSSE3. */
31673 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
31674 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
31676 /* SSE4.1 */
31677 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31678 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31679 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
31680 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
31681 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31682 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31683 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31684 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
31685 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
31686 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
31688 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31689 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31690 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31691 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31692 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31693 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31694 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31695 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31696 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31697 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31698 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31699 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31700 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31702 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31703 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31704 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31705 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31706 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31707 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31708 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31709 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31710 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31711 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31712 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31713 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31715 /* SSE4.1 */
31716 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31717 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31718 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31719 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31721 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
31722 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
31723 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
31724 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
31726 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31727 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31729 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31730 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31732 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
31733 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
31734 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
31735 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
31737 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
31738 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
31740 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31741 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31743 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31744 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31745 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptestv2di, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31747 /* SSE4.2 */
31748 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31749 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
31750 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
31751 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31752 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31754 /* SSE4A */
31755 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
31756 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
31757 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
31758 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31760 /* AES */
31761 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
31762 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31764 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31765 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31766 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31767 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31769 /* PCLMUL */
31770 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
31772 /* AVX */
31773 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31774 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31775 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31776 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31777 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31778 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31779 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31780 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31781 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31782 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31783 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31784 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31785 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31786 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31787 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31788 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31789 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31790 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31791 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31792 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31793 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31794 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31795 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31796 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31797 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31798 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31800 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
31801 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
31802 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
31803 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31805 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31806 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31807 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
31808 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
31809 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31810 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31811 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31812 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31813 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31814 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31815 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31816 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31817 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31818 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
31819 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
31820 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
31821 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
31822 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
31823 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
31824 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31825 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
31826 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31827 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31828 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31829 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31830 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31831 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31832 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31833 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31834 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31835 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31836 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
31837 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
31838 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
31840 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31841 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31842 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31844 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31845 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31846 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31847 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31848 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31850 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31852 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31853 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31855 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
31856 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
31857 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
31858 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
31860 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31861 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31863 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31864 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31866 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
31867 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
31868 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
31869 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
31871 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
31872 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
31874 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31875 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31877 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31878 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31879 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31880 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31882 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31883 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31884 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31885 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
31886 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
31887 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
31889 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31890 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31891 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31892 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31893 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31894 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31895 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31896 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31897 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31898 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31899 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31900 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31901 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptestv4di, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31902 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptestv4di, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31903 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptestv4di, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31905 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
31906 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
31908 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31909 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31911 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31913 /* AVX2 */
31914 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
31915 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
31916 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
31917 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
31918 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31919 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31920 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31921 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31922 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31923 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31924 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31925 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31926 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31927 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31928 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31929 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31930 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
31931 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31932 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31933 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31934 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31935 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
31936 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
31937 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31938 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31939 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31940 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31941 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31942 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31943 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31944 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31945 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31946 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31947 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31948 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31949 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31950 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31951 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31952 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
31953 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31954 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31955 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31956 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31957 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31958 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31959 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31960 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31961 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31962 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31963 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31964 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31965 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
31966 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31967 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31968 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31969 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31970 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31971 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31972 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31973 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31974 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31975 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31976 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31977 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31978 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31979 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31980 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31981 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31982 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31983 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31984 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31985 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31986 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31987 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31988 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
31989 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31990 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31991 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31992 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31993 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31994 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31995 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31996 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31997 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31998 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31999 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
32000 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
32001 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
32002 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
32003 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
32004 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
32005 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
32006 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
32007 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
32008 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
32009 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
32010 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
32011 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
32012 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32013 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
32014 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32015 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32016 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32017 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
32018 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32019 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
32020 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32021 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
32022 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32023 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32024 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32025 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
32026 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32027 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32028 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32029 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
32030 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
32031 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
32032 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
32033 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
32034 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
32035 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
32036 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
32037 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
32038 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
32039 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
32040 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
32041 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
32042 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
32043 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32044 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
32045 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
32046 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
32047 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
32048 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vextractf128v4di, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
32049 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vinsertf128v4di, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
32050 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32051 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
32052 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32053 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32054 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32055 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32056 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32057 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
32058 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32059 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32061 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
32063 /* BMI */
32064 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32065 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32066 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
32068 /* TBM */
32069 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32070 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32072 /* F16C */
32073 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
32074 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
32075 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
32076 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
32078 /* BMI2 */
32079 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32080 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32081 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32082 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32083 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32084 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32086 /* AVX512F */
32087 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_256si, "__builtin_ia32_si512_256si", IX86_BUILTIN_SI512_SI256, UNKNOWN, (int) V16SI_FTYPE_V8SI },
32088 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_256ps, "__builtin_ia32_ps512_256ps", IX86_BUILTIN_PS512_PS256, UNKNOWN, (int) V16SF_FTYPE_V8SF },
32089 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_256pd, "__builtin_ia32_pd512_256pd", IX86_BUILTIN_PD512_PD256, UNKNOWN, (int) V8DF_FTYPE_V4DF },
32090 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_si, "__builtin_ia32_si512_si", IX86_BUILTIN_SI512_SI, UNKNOWN, (int) V16SI_FTYPE_V4SI },
32091 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_ps, "__builtin_ia32_ps512_ps", IX86_BUILTIN_PS512_PS, UNKNOWN, (int) V16SF_FTYPE_V4SF },
32092 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_pd, "__builtin_ia32_pd512_pd", IX86_BUILTIN_PD512_PD, UNKNOWN, (int) V8DF_FTYPE_V2DF },
32093 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_UHI },
32094 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_UQI },
32095 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_UHI },
32096 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI },
32097 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI },
32098 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_UQI },
32099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_UHI },
32100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_UQI },
32101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_UHI },
32102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_UQI },
32103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_UQI },
32104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_UHI },
32105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) UHI_FTYPE_V16SI_V16SI_INT_UHI },
32106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) UQI_FTYPE_V8DI_V8DI_INT_UQI },
32107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI },
32108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI },
32109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_UQI },
32110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_UHI },
32111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_UQI },
32112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
32113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI },
32114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI },
32115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI },
32116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI },
32117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_UQI },
32118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_UQI },
32119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_UQI },
32120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_UQI },
32121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_UHI },
32122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_UQI },
32123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_UHI },
32124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_UQI },
32125 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI },
32126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI },
32127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI },
32128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_UHI },
32129 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_UQI },
32130 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI },
32131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI },
32132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_UHI },
32133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_UQI },
32134 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32135 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32136 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32137 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32139 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32140 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_UHI },
32141 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_UHI },
32142 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_UQI },
32143 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_UHI },
32144 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_UQI },
32145 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_UQI },
32146 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) UHI_FTYPE_V16SI_V16SI_UHI },
32147 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) UQI_FTYPE_V8DI_V8DI_UQI },
32148 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) UHI_FTYPE_V16SI_V16SI_UHI },
32149 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) UQI_FTYPE_V8DI_V8DI_UQI },
32150 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_UHI },
32151 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_UQI },
32152 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_UHI },
32153 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_UHI },
32154 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_UQI },
32155 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_UQI },
32156 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32157 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32158 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32159 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32160 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32161 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32162 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32163 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32164 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_UHI },
32165 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_UHI },
32166 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_UQI },
32167 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_UQI },
32168 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_UQI },
32169 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_UHI },
32170 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_UHI },
32171 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_UQI },
32172 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_UQI },
32173 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_UQI },
32174 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_UHI },
32175 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_UQI },
32176 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_UQI },
32177 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_UHI },
32178 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_UQI },
32179 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_UHI },
32180 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_UHI },
32181 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_UQI },
32182 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_UQI },
32183 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_UQI },
32184 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_UHI },
32185 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_UQI },
32186 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_UQI },
32187 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_UHI },
32188 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_UQI },
32189 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_UQI },
32190 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32191 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_UQI },
32192 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32193 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32194 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_UHI },
32195 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_UQI },
32196 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32197 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32198 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_UHI },
32199 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_UQI },
32200 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32201 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32202 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_UHI },
32203 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_UHI },
32204 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_UHI },
32205 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_UQI },
32206 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_UQI },
32207 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32208 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32209 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_UHI },
32210 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_UHI },
32211 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_UQI },
32212 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_UQI },
32213 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32214 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32215 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_UHI },
32216 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_UHI },
32217 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_UQI },
32218 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_UQI },
32219 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32220 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32221 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32222 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32223 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) UHI_FTYPE_V16SI_V16SI_UHI },
32224 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) UQI_FTYPE_V8DI_V8DI_UQI },
32225 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) UHI_FTYPE_V16SI_V16SI_UHI },
32226 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) UQI_FTYPE_V8DI_V8DI_UQI },
32227 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32228 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32229 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32230 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32231 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32232 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32233 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI },
32234 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI },
32235 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
32236 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
32237 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_UQI },
32238 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_UHI },
32239 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
32240 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
32241 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_UQI },
32242 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_UHI },
32243 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_UHI },
32244 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_UQI },
32245 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_UHI },
32246 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_UQI },
32247 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) UHI_FTYPE_V16SI_V16SI_INT_UHI },
32248 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) UQI_FTYPE_V8DI_V8DI_INT_UQI },
32249 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI },
32250 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_UHI },
32251 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI },
32252 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_UHI },
32253 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_UHI },
32254 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_UQI },
32255 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_UHI },
32256 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_UQI },
32257 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_UQI },
32258 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_UQI },
32259 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32260 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_UQI },
32261 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_UHI },
32262 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32263 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_UQI },
32264 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_UHI },
32265 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_UQI },
32266 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_UHI },
32267 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32268 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32269 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_UQI },
32270 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_UQI },
32271 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_UHI },
32272 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_UHI },
32273 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32274 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32275 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_UQI },
32276 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
32277 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_UHI },
32278 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_UHI },
32279 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_UHI },
32280 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_UHI },
32281 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_UQI },
32282 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_UQI },
32284 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
32285 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
32286 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
32287 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32288 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32289 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
32290 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32291 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32293 /* Mask arithmetic operations */
32294 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) UHI_FTYPE_UHI_UHI },
32295 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) UHI_FTYPE_UHI_UHI },
32296 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) UHI_FTYPE_UHI },
32297 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) UHI_FTYPE_UHI_UHI },
32298 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) UHI_FTYPE_UHI_UHI },
32299 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) UHI_FTYPE_UHI_UHI },
32300 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) UHI_FTYPE_UHI_UHI },
32301 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) UHI_FTYPE_UHI_UHI },
32302 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) UHI_FTYPE_UHI_UHI },
32303 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) UHI_FTYPE_UHI },
32305 /* SHA */
32306 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32307 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32308 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32309 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
32310 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32311 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32312 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
32314 /* AVX512VL. */
32315 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_USI_CONVERT },
32316 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_UHI_CONVERT },
32317 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64_256_mask", IX86_BUILTIN_MOVDQA64_256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_UQI },
32318 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64_128_mask", IX86_BUILTIN_MOVDQA64_128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UQI },
32319 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32_256_mask", IX86_BUILTIN_MOVDQA32_256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_UQI },
32320 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32_128_mask", IX86_BUILTIN_MOVDQA32_128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_UQI },
32321 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_movapd256_mask", IX86_BUILTIN_MOVAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_UQI },
32322 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_movapd128_mask", IX86_BUILTIN_MOVAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_UQI },
32323 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_movaps256_mask", IX86_BUILTIN_MOVAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_UQI },
32324 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_movaps128_mask", IX86_BUILTIN_MOVAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32325 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_movdquhi256_mask", IX86_BUILTIN_MOVDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_UHI },
32326 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_movdquhi128_mask", IX86_BUILTIN_MOVDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_UQI },
32327 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_movdquqi256_mask", IX86_BUILTIN_MOVDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_USI },
32328 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_movdquqi128_mask", IX86_BUILTIN_MOVDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_UHI },
32329 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4sf3_mask, "__builtin_ia32_minps_mask", IX86_BUILTIN_MINPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32330 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4sf3_mask, "__builtin_ia32_maxps_mask", IX86_BUILTIN_MAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32331 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2df3_mask, "__builtin_ia32_minpd_mask", IX86_BUILTIN_MINPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32332 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2df3_mask, "__builtin_ia32_maxpd_mask", IX86_BUILTIN_MAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32333 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4df3_mask, "__builtin_ia32_maxpd256_mask", IX86_BUILTIN_MAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32334 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8sf3_mask, "__builtin_ia32_maxps256_mask", IX86_BUILTIN_MAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32335 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4df3_mask, "__builtin_ia32_minpd256_mask", IX86_BUILTIN_MINPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32336 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8sf3_mask, "__builtin_ia32_minps256_mask", IX86_BUILTIN_MINPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32337 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4sf3_mask, "__builtin_ia32_mulps_mask", IX86_BUILTIN_MULPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32338 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_divv4sf3_mask, "__builtin_ia32_divps_mask", IX86_BUILTIN_DIVPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32339 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv2df3_mask, "__builtin_ia32_mulpd_mask", IX86_BUILTIN_MULPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32340 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_divv2df3_mask, "__builtin_ia32_divpd_mask", IX86_BUILTIN_DIVPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32341 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv4df3_mask, "__builtin_ia32_divpd256_mask", IX86_BUILTIN_DIVPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32342 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv8sf3_mask, "__builtin_ia32_divps256_mask", IX86_BUILTIN_DIVPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32343 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4df3_mask, "__builtin_ia32_mulpd256_mask", IX86_BUILTIN_MULPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32344 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8sf3_mask, "__builtin_ia32_mulps256_mask", IX86_BUILTIN_MULPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32345 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2df3_mask, "__builtin_ia32_addpd128_mask", IX86_BUILTIN_ADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32346 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4df3_mask, "__builtin_ia32_addpd256_mask", IX86_BUILTIN_ADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32347 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4sf3_mask, "__builtin_ia32_addps128_mask", IX86_BUILTIN_ADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32348 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8sf3_mask, "__builtin_ia32_addps256_mask", IX86_BUILTIN_ADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32349 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2df3_mask, "__builtin_ia32_subpd128_mask", IX86_BUILTIN_SUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32350 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4df3_mask, "__builtin_ia32_subpd256_mask", IX86_BUILTIN_SUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32351 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4sf3_mask, "__builtin_ia32_subps128_mask", IX86_BUILTIN_SUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32352 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8sf3_mask, "__builtin_ia32_subps256_mask", IX86_BUILTIN_SUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32353 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4df3_mask, "__builtin_ia32_xorpd256_mask", IX86_BUILTIN_XORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32354 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2df3_mask, "__builtin_ia32_xorpd128_mask", IX86_BUILTIN_XORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32355 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8sf3_mask, "__builtin_ia32_xorps256_mask", IX86_BUILTIN_XORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32356 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4sf3_mask, "__builtin_ia32_xorps128_mask", IX86_BUILTIN_XORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32357 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4df3_mask, "__builtin_ia32_orpd256_mask", IX86_BUILTIN_ORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32358 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2df3_mask, "__builtin_ia32_orpd128_mask", IX86_BUILTIN_ORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32359 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8sf3_mask, "__builtin_ia32_orps256_mask", IX86_BUILTIN_ORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32360 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4sf3_mask, "__builtin_ia32_orps128_mask", IX86_BUILTIN_ORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32361 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8sf_mask, "__builtin_ia32_broadcastf32x2_256_mask", IX86_BUILTIN_BROADCASTF32x2_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_UQI },
32362 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8si_mask, "__builtin_ia32_broadcasti32x2_256_mask", IX86_BUILTIN_BROADCASTI32x2_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_UQI },
32363 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4si_mask, "__builtin_ia32_broadcasti32x2_128_mask", IX86_BUILTIN_BROADCASTI32x2_128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_UQI },
32364 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4df_mask_1, "__builtin_ia32_broadcastf64x2_256_mask", IX86_BUILTIN_BROADCASTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_UQI },
32365 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4di_mask_1, "__builtin_ia32_broadcasti64x2_256_mask", IX86_BUILTIN_BROADCASTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_UQI },
32366 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8sf_mask_1, "__builtin_ia32_broadcastf32x4_256_mask", IX86_BUILTIN_BROADCASTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_UQI },
32367 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8si_mask_1, "__builtin_ia32_broadcasti32x4_256_mask", IX86_BUILTIN_BROADCASTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_UQI },
32368 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_UQI },
32369 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_UQI },
32370 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv16hi_mask, "__builtin_ia32_dbpsadbw256_mask", IX86_BUILTIN_DBPSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_UHI },
32371 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_UQI },
32372 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI },
32373 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_UQI },
32374 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI },
32375 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_UQI },
32376 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI },
32377 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_UQI },
32378 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_UQI },
32379 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2uqq128_mask", IX86_BUILTIN_CVTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_UQI },
32380 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin_ia32_cvtpd2udq256_mask", IX86_BUILTIN_CVTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_UQI },
32381 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_UQI },
32382 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_UQI },
32383 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_UQI },
32384 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_UQI },
32385 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_UQI },
32386 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI },
32387 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_UQI },
32388 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI },
32389 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2udq128_mask", IX86_BUILTIN_CVTTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_UQI },
32390 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2dq256_mask", IX86_BUILTIN_CVTTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_UQI },
32391 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvttpd2dq_mask, "__builtin_ia32_cvttpd2dq128_mask", IX86_BUILTIN_CVTTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_UQI },
32392 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2udq256_mask", IX86_BUILTIN_CVTTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_UQI },
32393 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2si2_mask, "__builtin_ia32_cvttpd2udq128_mask", IX86_BUILTIN_CVTTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_UQI },
32394 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2dq256_mask, "__builtin_ia32_cvtpd2dq256_mask", IX86_BUILTIN_CVTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_UQI },
32395 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2dq_mask, "__builtin_ia32_cvtpd2dq128_mask", IX86_BUILTIN_CVTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_UQI },
32396 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4df2_mask, "__builtin_ia32_cvtdq2pd256_mask", IX86_BUILTIN_CVTDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_UQI },
32397 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtdq2pd_mask, "__builtin_ia32_cvtdq2pd128_mask", IX86_BUILTIN_CVTDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_UQI },
32398 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4df2_mask, "__builtin_ia32_cvtudq2pd256_mask", IX86_BUILTIN_CVTUDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_UQI },
32399 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2siv2df2_mask, "__builtin_ia32_cvtudq2pd128_mask", IX86_BUILTIN_CVTUDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_UQI },
32400 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv8siv8sf2_mask, "__builtin_ia32_cvtdq2ps256_mask", IX86_BUILTIN_CVTDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_UQI },
32401 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4sf2_mask, "__builtin_ia32_cvtdq2ps128_mask", IX86_BUILTIN_CVTDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_UQI },
32402 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv8siv8sf2_mask, "__builtin_ia32_cvtudq2ps256_mask", IX86_BUILTIN_CVTUDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_UQI },
32403 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4sf2_mask, "__builtin_ia32_cvtudq2ps128_mask", IX86_BUILTIN_CVTUDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_UQI },
32404 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtps2pd256_mask, "__builtin_ia32_cvtps2pd256_mask", IX86_BUILTIN_CVTPS2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_UQI },
32405 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtps2pd_mask, "__builtin_ia32_cvtps2pd128_mask", IX86_BUILTIN_CVTPS2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SF_V2DF_UQI },
32406 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv32qi_mask, "__builtin_ia32_pbroadcastb256_mask", IX86_BUILTIN_PBROADCASTB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_USI },
32407 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv32qi_mask, "__builtin_ia32_pbroadcastb256_gpr_mask", IX86_BUILTIN_PBROADCASTB256_GPR_MASK, UNKNOWN, (int) V32QI_FTYPE_QI_V32QI_USI },
32408 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16qi_mask, "__builtin_ia32_pbroadcastb128_mask", IX86_BUILTIN_PBROADCASTB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_UHI },
32409 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16qi_mask, "__builtin_ia32_pbroadcastb128_gpr_mask", IX86_BUILTIN_PBROADCASTB128_GPR_MASK, UNKNOWN, (int) V16QI_FTYPE_QI_V16QI_UHI },
32410 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16hi_mask, "__builtin_ia32_pbroadcastw256_mask", IX86_BUILTIN_PBROADCASTW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8HI_V16HI_UHI },
32411 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16hi_mask, "__builtin_ia32_pbroadcastw256_gpr_mask", IX86_BUILTIN_PBROADCASTW256_GPR_MASK, UNKNOWN, (int) V16HI_FTYPE_HI_V16HI_UHI },
32412 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8hi_mask, "__builtin_ia32_pbroadcastw128_mask", IX86_BUILTIN_PBROADCASTW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_UQI },
32413 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8hi_mask, "__builtin_ia32_pbroadcastw128_gpr_mask", IX86_BUILTIN_PBROADCASTW128_GPR_MASK, UNKNOWN, (int) V8HI_FTYPE_HI_V8HI_UQI },
32414 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8si_mask, "__builtin_ia32_pbroadcastd256_mask", IX86_BUILTIN_PBROADCASTD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_UQI },
32415 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8si_mask, "__builtin_ia32_pbroadcastd256_gpr_mask", IX86_BUILTIN_PBROADCASTD256_GPR_MASK, UNKNOWN, (int) V8SI_FTYPE_SI_V8SI_UQI },
32416 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4si_mask, "__builtin_ia32_pbroadcastd128_mask", IX86_BUILTIN_PBROADCASTD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_UQI },
32417 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4si_mask, "__builtin_ia32_pbroadcastd128_gpr_mask", IX86_BUILTIN_PBROADCASTD128_GPR_MASK, UNKNOWN, (int) V4SI_FTYPE_SI_V4SI_UQI },
32418 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4di_mask, "__builtin_ia32_pbroadcastq256_mask", IX86_BUILTIN_PBROADCASTQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_UQI },
32419 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4di_mask, "__builtin_ia32_pbroadcastq256_gpr_mask", IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_UQI },
32420 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv2di_mask, "__builtin_ia32_pbroadcastq128_mask", IX86_BUILTIN_PBROADCASTQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UQI },
32421 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv2di_mask, "__builtin_ia32_pbroadcastq128_gpr_mask", IX86_BUILTIN_PBROADCASTQ128_GPR_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_UQI },
32422 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8sf_mask, "__builtin_ia32_broadcastss256_mask", IX86_BUILTIN_BROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_UQI },
32423 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4sf_mask, "__builtin_ia32_broadcastss128_mask", IX86_BUILTIN_BROADCASTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32424 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4df_mask, "__builtin_ia32_broadcastsd256_mask", IX86_BUILTIN_BROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_UQI },
32425 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4df, "__builtin_ia32_extractf64x2_256_mask", IX86_BUILTIN_EXTRACTF64X2_256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT_V2DF_UQI },
32426 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4di, "__builtin_ia32_extracti64x2_256_mask", IX86_BUILTIN_EXTRACTI64X2_256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT_V2DI_UQI },
32427 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8sf, "__builtin_ia32_insertf32x4_256_mask", IX86_BUILTIN_INSERTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT_V8SF_UQI },
32428 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8si, "__builtin_ia32_inserti32x4_256_mask", IX86_BUILTIN_INSERTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT_V8SI_UQI },
32429 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv16qiv16hi2_mask, "__builtin_ia32_pmovsxbw256_mask", IX86_BUILTIN_PMOVSXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_UHI },
32430 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv8qiv8hi2_mask, "__builtin_ia32_pmovsxbw128_mask", IX86_BUILTIN_PMOVSXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_UQI },
32431 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8qiv8si2_mask, "__builtin_ia32_pmovsxbd256_mask", IX86_BUILTIN_PMOVSXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_UQI },
32432 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4qiv4si2_mask, "__builtin_ia32_pmovsxbd128_mask", IX86_BUILTIN_PMOVSXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_UQI },
32433 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4qiv4di2_mask, "__builtin_ia32_pmovsxbq256_mask", IX86_BUILTIN_PMOVSXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_UQI },
32434 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2qiv2di2_mask, "__builtin_ia32_pmovsxbq128_mask", IX86_BUILTIN_PMOVSXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_UQI },
32435 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8hiv8si2_mask, "__builtin_ia32_pmovsxwd256_mask", IX86_BUILTIN_PMOVSXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_UQI },
32436 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4hiv4si2_mask, "__builtin_ia32_pmovsxwd128_mask", IX86_BUILTIN_PMOVSXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_UQI },
32437 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4hiv4di2_mask, "__builtin_ia32_pmovsxwq256_mask", IX86_BUILTIN_PMOVSXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_UQI },
32438 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2hiv2di2_mask, "__builtin_ia32_pmovsxwq128_mask", IX86_BUILTIN_PMOVSXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_UQI },
32439 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4siv4di2_mask, "__builtin_ia32_pmovsxdq256_mask", IX86_BUILTIN_PMOVSXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_UQI },
32440 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2siv2di2_mask, "__builtin_ia32_pmovsxdq128_mask", IX86_BUILTIN_PMOVSXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_UQI },
32441 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv16qiv16hi2_mask, "__builtin_ia32_pmovzxbw256_mask", IX86_BUILTIN_PMOVZXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_UHI },
32442 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv8qiv8hi2_mask, "__builtin_ia32_pmovzxbw128_mask", IX86_BUILTIN_PMOVZXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_UQI },
32443 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8qiv8si2_mask, "__builtin_ia32_pmovzxbd256_mask", IX86_BUILTIN_PMOVZXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_UQI },
32444 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4qiv4si2_mask, "__builtin_ia32_pmovzxbd128_mask", IX86_BUILTIN_PMOVZXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_UQI },
32445 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4qiv4di2_mask, "__builtin_ia32_pmovzxbq256_mask", IX86_BUILTIN_PMOVZXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_UQI },
32446 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2qiv2di2_mask, "__builtin_ia32_pmovzxbq128_mask", IX86_BUILTIN_PMOVZXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_UQI },
32447 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8hiv8si2_mask, "__builtin_ia32_pmovzxwd256_mask", IX86_BUILTIN_PMOVZXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_UQI },
32448 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4hiv4si2_mask, "__builtin_ia32_pmovzxwd128_mask", IX86_BUILTIN_PMOVZXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_UQI },
32449 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4hiv4di2_mask, "__builtin_ia32_pmovzxwq256_mask", IX86_BUILTIN_PMOVZXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_UQI },
32450 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2hiv2di2_mask, "__builtin_ia32_pmovzxwq128_mask", IX86_BUILTIN_PMOVZXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_UQI },
32451 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4siv4di2_mask, "__builtin_ia32_pmovzxdq256_mask", IX86_BUILTIN_PMOVZXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_UQI },
32452 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2siv2di2_mask, "__builtin_ia32_pmovzxdq128_mask", IX86_BUILTIN_PMOVZXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_UQI },
32453 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4df_mask, "__builtin_ia32_reducepd256_mask", IX86_BUILTIN_REDUCEPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_UQI },
32454 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv2df_mask, "__builtin_ia32_reducepd128_mask", IX86_BUILTIN_REDUCEPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_UQI },
32455 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv8sf_mask, "__builtin_ia32_reduceps256_mask", IX86_BUILTIN_REDUCEPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_UQI },
32456 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4sf_mask, "__builtin_ia32_reduceps128_mask", IX86_BUILTIN_REDUCEPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_UQI },
32457 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv2df, "__builtin_ia32_reducesd", IX86_BUILTIN_REDUCESD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32458 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv4sf, "__builtin_ia32_reducess", IX86_BUILTIN_REDUCESS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32459 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32460 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32461 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32462 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32463 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32464 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32465 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32466 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32467 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_UQI },
32468 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v2df_mask, "__builtin_ia32_rcp14pd128_mask", IX86_BUILTIN_RCP14PD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_UQI },
32469 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v8sf_mask, "__builtin_ia32_rcp14ps256_mask", IX86_BUILTIN_RCP14PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_UQI },
32470 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4sf_mask, "__builtin_ia32_rcp14ps128_mask", IX86_BUILTIN_RCP14PS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32471 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4df_mask, "__builtin_ia32_rsqrt14pd256_mask", IX86_BUILTIN_RSQRT14PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_UQI },
32472 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v2df_mask, "__builtin_ia32_rsqrt14pd128_mask", IX86_BUILTIN_RSQRT14PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_UQI },
32473 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v8sf_mask, "__builtin_ia32_rsqrt14ps256_mask", IX86_BUILTIN_RSQRT14PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_UQI },
32474 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4sf_mask, "__builtin_ia32_rsqrt14ps128_mask", IX86_BUILTIN_RSQRT14PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32475 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv4df2_mask, "__builtin_ia32_sqrtpd256_mask", IX86_BUILTIN_SQRTPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_UQI },
32476 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sqrtv2df2_mask, "__builtin_ia32_sqrtpd128_mask", IX86_BUILTIN_SQRTPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_UQI },
32477 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv8sf2_mask, "__builtin_ia32_sqrtps256_mask", IX86_BUILTIN_SQRTPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_UQI },
32478 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_sqrtv4sf2_mask, "__builtin_ia32_sqrtps128_mask", IX86_BUILTIN_SQRTPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32479 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16qi3_mask, "__builtin_ia32_paddb128_mask", IX86_BUILTIN_PADDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32480 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8hi3_mask, "__builtin_ia32_paddw128_mask", IX86_BUILTIN_PADDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32481 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4si3_mask, "__builtin_ia32_paddd128_mask", IX86_BUILTIN_PADDD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32482 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2di3_mask, "__builtin_ia32_paddq128_mask", IX86_BUILTIN_PADDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32483 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16qi3_mask, "__builtin_ia32_psubb128_mask", IX86_BUILTIN_PSUBB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32484 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8hi3_mask, "__builtin_ia32_psubw128_mask", IX86_BUILTIN_PSUBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32485 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4si3_mask, "__builtin_ia32_psubd128_mask", IX86_BUILTIN_PSUBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32486 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2di3_mask, "__builtin_ia32_psubq128_mask", IX86_BUILTIN_PSUBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32487 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv16qi3_mask, "__builtin_ia32_paddsb128_mask", IX86_BUILTIN_PADDSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32488 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv8hi3_mask, "__builtin_ia32_paddsw128_mask", IX86_BUILTIN_PADDSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32489 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv16qi3_mask, "__builtin_ia32_psubsb128_mask", IX86_BUILTIN_PSUBSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32490 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv8hi3_mask, "__builtin_ia32_psubsw128_mask", IX86_BUILTIN_PSUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32491 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv16qi3_mask, "__builtin_ia32_paddusb128_mask", IX86_BUILTIN_PADDUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32492 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv8hi3_mask, "__builtin_ia32_paddusw128_mask", IX86_BUILTIN_PADDUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32493 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv16qi3_mask, "__builtin_ia32_psubusb128_mask", IX86_BUILTIN_PSUBUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32494 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv8hi3_mask, "__builtin_ia32_psubusw128_mask", IX86_BUILTIN_PSUBUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32495 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv32qi3_mask, "__builtin_ia32_paddb256_mask", IX86_BUILTIN_PADDB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32496 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16hi3_mask, "__builtin_ia32_paddw256_mask", IX86_BUILTIN_PADDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32497 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8si3_mask, "__builtin_ia32_paddd256_mask", IX86_BUILTIN_PADDD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32498 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4di3_mask, "__builtin_ia32_paddq256_mask", IX86_BUILTIN_PADDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32499 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv32qi3_mask, "__builtin_ia32_paddsb256_mask", IX86_BUILTIN_PADDSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32500 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv16hi3_mask, "__builtin_ia32_paddsw256_mask", IX86_BUILTIN_PADDSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32501 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv32qi3_mask, "__builtin_ia32_paddusb256_mask", IX86_BUILTIN_PADDUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32502 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv16hi3_mask, "__builtin_ia32_paddusw256_mask", IX86_BUILTIN_PADDUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32503 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv32qi3_mask, "__builtin_ia32_psubb256_mask", IX86_BUILTIN_PSUBB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32504 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16hi3_mask, "__builtin_ia32_psubw256_mask", IX86_BUILTIN_PSUBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32505 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8si3_mask, "__builtin_ia32_psubd256_mask", IX86_BUILTIN_PSUBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32506 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4di3_mask, "__builtin_ia32_psubq256_mask", IX86_BUILTIN_PSUBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32507 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv32qi3_mask, "__builtin_ia32_psubsb256_mask", IX86_BUILTIN_PSUBSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32508 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv16hi3_mask, "__builtin_ia32_psubsw256_mask", IX86_BUILTIN_PSUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32509 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv32qi3_mask, "__builtin_ia32_psubusb256_mask", IX86_BUILTIN_PSUBUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32510 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv16hi3_mask, "__builtin_ia32_psubusw256_mask", IX86_BUILTIN_PSUBUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32511 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_256_mask", IX86_BUILTIN_SHUF_F64x2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_UQI },
32512 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_256_mask", IX86_BUILTIN_SHUF_I64x2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_UQI },
32513 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_256_mask", IX86_BUILTIN_SHUF_I32x4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_UQI },
32514 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_256_mask", IX86_BUILTIN_SHUF_F32x4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_UQI },
32515 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovwb128_mask", IX86_BUILTIN_PMOVWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_UQI },
32516 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovwb256_mask", IX86_BUILTIN_PMOVWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_UHI },
32517 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovswb128_mask", IX86_BUILTIN_PMOVSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_UQI },
32518 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovswb256_mask", IX86_BUILTIN_PMOVSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_UHI },
32519 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovuswb128_mask", IX86_BUILTIN_PMOVUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_UQI },
32520 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovuswb256_mask", IX86_BUILTIN_PMOVUSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_UHI },
32521 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask, "__builtin_ia32_pmovdb128_mask", IX86_BUILTIN_PMOVDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_UQI },
32522 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask, "__builtin_ia32_pmovdb256_mask", IX86_BUILTIN_PMOVDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_UQI },
32523 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask, "__builtin_ia32_pmovsdb128_mask", IX86_BUILTIN_PMOVSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_UQI },
32524 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask, "__builtin_ia32_pmovsdb256_mask", IX86_BUILTIN_PMOVSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_UQI },
32525 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask, "__builtin_ia32_pmovusdb128_mask", IX86_BUILTIN_PMOVUSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_UQI },
32526 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask, "__builtin_ia32_pmovusdb256_mask", IX86_BUILTIN_PMOVUSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_UQI },
32527 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask, "__builtin_ia32_pmovdw128_mask", IX86_BUILTIN_PMOVDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_UQI },
32528 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask, "__builtin_ia32_pmovdw256_mask", IX86_BUILTIN_PMOVDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_UQI },
32529 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask, "__builtin_ia32_pmovsdw128_mask", IX86_BUILTIN_PMOVSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_UQI },
32530 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask, "__builtin_ia32_pmovsdw256_mask", IX86_BUILTIN_PMOVSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_UQI },
32531 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask, "__builtin_ia32_pmovusdw128_mask", IX86_BUILTIN_PMOVUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_UQI },
32532 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask, "__builtin_ia32_pmovusdw256_mask", IX86_BUILTIN_PMOVUSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_UQI },
32533 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask, "__builtin_ia32_pmovqb128_mask", IX86_BUILTIN_PMOVQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_UQI },
32534 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask, "__builtin_ia32_pmovqb256_mask", IX86_BUILTIN_PMOVQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_UQI },
32535 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask, "__builtin_ia32_pmovsqb128_mask", IX86_BUILTIN_PMOVSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_UQI },
32536 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask, "__builtin_ia32_pmovsqb256_mask", IX86_BUILTIN_PMOVSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_UQI },
32537 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask, "__builtin_ia32_pmovusqb128_mask", IX86_BUILTIN_PMOVUSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_UQI },
32538 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask, "__builtin_ia32_pmovusqb256_mask", IX86_BUILTIN_PMOVUSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_UQI },
32539 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask, "__builtin_ia32_pmovqw128_mask", IX86_BUILTIN_PMOVQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_UQI },
32540 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask, "__builtin_ia32_pmovqw256_mask", IX86_BUILTIN_PMOVQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_UQI },
32541 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask, "__builtin_ia32_pmovsqw128_mask", IX86_BUILTIN_PMOVSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_UQI },
32542 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask, "__builtin_ia32_pmovsqw256_mask", IX86_BUILTIN_PMOVSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_UQI },
32543 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask, "__builtin_ia32_pmovusqw128_mask", IX86_BUILTIN_PMOVUSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_UQI },
32544 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask, "__builtin_ia32_pmovusqw256_mask", IX86_BUILTIN_PMOVUSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_UQI },
32545 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask, "__builtin_ia32_pmovqd128_mask", IX86_BUILTIN_PMOVQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_UQI },
32546 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask, "__builtin_ia32_pmovqd256_mask", IX86_BUILTIN_PMOVQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_UQI },
32547 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask, "__builtin_ia32_pmovsqd128_mask", IX86_BUILTIN_PMOVSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_UQI },
32548 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask, "__builtin_ia32_pmovsqd256_mask", IX86_BUILTIN_PMOVSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_UQI },
32549 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask, "__builtin_ia32_pmovusqd128_mask", IX86_BUILTIN_PMOVUSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_UQI },
32550 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask, "__builtin_ia32_pmovusqd256_mask", IX86_BUILTIN_PMOVUSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_UQI },
32551 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4df_mask, "__builtin_ia32_rangepd256_mask", IX86_BUILTIN_RANGEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_UQI },
32552 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv2df_mask, "__builtin_ia32_rangepd128_mask", IX86_BUILTIN_RANGEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_UQI },
32553 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv8sf_mask, "__builtin_ia32_rangeps256_mask", IX86_BUILTIN_RANGEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_UQI },
32554 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4sf_mask, "__builtin_ia32_rangeps128_mask", IX86_BUILTIN_RANGEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_UQI },
32555 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv8sf_mask, "__builtin_ia32_getexpps256_mask", IX86_BUILTIN_GETEXPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_UQI },
32556 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4df_mask, "__builtin_ia32_getexppd256_mask", IX86_BUILTIN_GETEXPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_UQI },
32557 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4sf_mask, "__builtin_ia32_getexpps128_mask", IX86_BUILTIN_GETEXPPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32558 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv2df_mask, "__builtin_ia32_getexppd128_mask", IX86_BUILTIN_GETEXPPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_UQI },
32559 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_mask, "__builtin_ia32_fixupimmpd256_mask", IX86_BUILTIN_FIXUPIMMPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_UQI },
32560 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_maskz, "__builtin_ia32_fixupimmpd256_maskz", IX86_BUILTIN_FIXUPIMMPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_UQI },
32561 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_mask, "__builtin_ia32_fixupimmps256_mask", IX86_BUILTIN_FIXUPIMMPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_UQI },
32562 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_maskz, "__builtin_ia32_fixupimmps256_maskz", IX86_BUILTIN_FIXUPIMMPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_UQI },
32563 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_mask, "__builtin_ia32_fixupimmpd128_mask", IX86_BUILTIN_FIXUPIMMPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_UQI },
32564 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_maskz, "__builtin_ia32_fixupimmpd128_maskz", IX86_BUILTIN_FIXUPIMMPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_UQI },
32565 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_mask, "__builtin_ia32_fixupimmps128_mask", IX86_BUILTIN_FIXUPIMMPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_UQI },
32566 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_maskz, "__builtin_ia32_fixupimmps128_maskz", IX86_BUILTIN_FIXUPIMMPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_UQI },
32567 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4di2_mask, "__builtin_ia32_pabsq256_mask", IX86_BUILTIN_PABSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_UQI },
32568 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv2di2_mask, "__builtin_ia32_pabsq128_mask", IX86_BUILTIN_PABSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UQI },
32569 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8si2_mask, "__builtin_ia32_pabsd256_mask", IX86_BUILTIN_PABSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_UQI },
32570 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4si2_mask, "__builtin_ia32_pabsd128_mask", IX86_BUILTIN_PABSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_UQI },
32571 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pmulhrswv16hi3_mask , "__builtin_ia32_pmulhrsw256_mask", IX86_BUILTIN_PMULHRSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32572 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pmulhrswv8hi3_mask, "__builtin_ia32_pmulhrsw128_mask", IX86_BUILTIN_PMULHRSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32573 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv8hi3_highpart_mask, "__builtin_ia32_pmulhuw128_mask", IX86_BUILTIN_PMULHUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32574 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv16hi3_highpart_mask, "__builtin_ia32_pmulhuw256_mask" , IX86_BUILTIN_PMULHUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32575 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv16hi3_highpart_mask, "__builtin_ia32_pmulhw256_mask" , IX86_BUILTIN_PMULHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32576 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv8hi3_highpart_mask, "__builtin_ia32_pmulhw128_mask", IX86_BUILTIN_PMULHW128_MASK, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32577 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv16hi3_mask, "__builtin_ia32_pmullw256_mask" , IX86_BUILTIN_PMULLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32578 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8hi3_mask, "__builtin_ia32_pmullw128_mask", IX86_BUILTIN_PMULLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32579 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv4di3_mask, "__builtin_ia32_pmullq256_mask", IX86_BUILTIN_PMULLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32580 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv2di3_mask, "__builtin_ia32_pmullq128_mask", IX86_BUILTIN_PMULLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32581 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4df3_mask, "__builtin_ia32_andpd256_mask", IX86_BUILTIN_ANDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32582 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2df3_mask, "__builtin_ia32_andpd128_mask", IX86_BUILTIN_ANDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32583 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8sf3_mask, "__builtin_ia32_andps256_mask", IX86_BUILTIN_ANDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32584 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4sf3_mask, "__builtin_ia32_andps128_mask", IX86_BUILTIN_ANDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32585 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv4df3_mask, "__builtin_ia32_andnpd256_mask", IX86_BUILTIN_ANDNPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32586 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2df3_mask, "__builtin_ia32_andnpd128_mask", IX86_BUILTIN_ANDNPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32587 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv8sf3_mask, "__builtin_ia32_andnps256_mask", IX86_BUILTIN_ANDNPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32588 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_andnotv4sf3_mask, "__builtin_ia32_andnps128_mask", IX86_BUILTIN_ANDNPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32589 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllwi128_mask", IX86_BUILTIN_PSLLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_UQI },
32590 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslldi128_mask", IX86_BUILTIN_PSLLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_UQI },
32591 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllqi128_mask", IX86_BUILTIN_PSLLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_UQI },
32592 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllw128_mask", IX86_BUILTIN_PSLLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32593 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslld128_mask", IX86_BUILTIN_PSLLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32594 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllq128_mask", IX86_BUILTIN_PSLLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32595 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllwi256_mask", IX86_BUILTIN_PSLLWI256_MASK , UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_UHI },
32596 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllw256_mask", IX86_BUILTIN_PSLLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_UHI },
32597 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslldi256_mask", IX86_BUILTIN_PSLLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_UQI },
32598 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslld256_mask", IX86_BUILTIN_PSLLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_UQI },
32599 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllqi256_mask", IX86_BUILTIN_PSLLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_UQI },
32600 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllq256_mask", IX86_BUILTIN_PSLLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_UQI },
32601 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psradi128_mask", IX86_BUILTIN_PSRADI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_UQI },
32602 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psrad128_mask", IX86_BUILTIN_PSRAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32603 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psradi256_mask", IX86_BUILTIN_PSRADI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_UQI },
32604 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psrad256_mask", IX86_BUILTIN_PSRAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_UQI },
32605 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraqi128_mask", IX86_BUILTIN_PSRAQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_UQI },
32606 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraq128_mask", IX86_BUILTIN_PSRAQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32607 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraqi256_mask", IX86_BUILTIN_PSRAQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_UQI },
32608 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraq256_mask", IX86_BUILTIN_PSRAQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_UQI },
32609 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8si3_mask, "__builtin_ia32_pandd256_mask", IX86_BUILTIN_PANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32610 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4si3_mask, "__builtin_ia32_pandd128_mask", IX86_BUILTIN_PANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32611 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrldi128_mask", IX86_BUILTIN_PSRLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_UQI },
32612 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrld128_mask", IX86_BUILTIN_PSRLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32613 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrldi256_mask", IX86_BUILTIN_PSRLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_UQI },
32614 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrld256_mask", IX86_BUILTIN_PSRLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_UQI },
32615 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlqi128_mask", IX86_BUILTIN_PSRLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_UQI },
32616 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlq128_mask", IX86_BUILTIN_PSRLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32617 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlqi256_mask", IX86_BUILTIN_PSRLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_UQI },
32618 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlq256_mask", IX86_BUILTIN_PSRLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_UQI },
32619 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4di3_mask, "__builtin_ia32_pandq256_mask", IX86_BUILTIN_PANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32620 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2di3_mask, "__builtin_ia32_pandq128_mask", IX86_BUILTIN_PANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32621 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv8si3_mask, "__builtin_ia32_pandnd256_mask", IX86_BUILTIN_PANDND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32622 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv4si3_mask, "__builtin_ia32_pandnd128_mask", IX86_BUILTIN_PANDND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32623 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv4di3_mask, "__builtin_ia32_pandnq256_mask", IX86_BUILTIN_PANDNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32624 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2di3_mask, "__builtin_ia32_pandnq128_mask", IX86_BUILTIN_PANDNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32625 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8si3_mask, "__builtin_ia32_pord256_mask", IX86_BUILTIN_PORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32626 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4si3_mask, "__builtin_ia32_pord128_mask", IX86_BUILTIN_PORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32627 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4di3_mask, "__builtin_ia32_porq256_mask", IX86_BUILTIN_PORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32628 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2di3_mask, "__builtin_ia32_porq128_mask", IX86_BUILTIN_PORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32629 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8si3_mask, "__builtin_ia32_pxord256_mask", IX86_BUILTIN_PXORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32630 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4si3_mask, "__builtin_ia32_pxord128_mask", IX86_BUILTIN_PXORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32631 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4di3_mask, "__builtin_ia32_pxorq256_mask", IX86_BUILTIN_PXORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32632 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2di3_mask, "__builtin_ia32_pxorq128_mask", IX86_BUILTIN_PXORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32633 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packsswb_mask, "__builtin_ia32_packsswb256_mask", IX86_BUILTIN_PACKSSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_USI },
32634 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packsswb_mask, "__builtin_ia32_packsswb128_mask", IX86_BUILTIN_PACKSSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_UHI },
32635 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packuswb_mask, "__builtin_ia32_packuswb256_mask", IX86_BUILTIN_PACKUSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_USI },
32636 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packuswb_mask, "__builtin_ia32_packuswb128_mask", IX86_BUILTIN_PACKUSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_UHI },
32637 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev8sf_mask, "__builtin_ia32_rndscaleps_256_mask", IX86_BUILTIN_RNDSCALEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_UQI },
32638 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4df_mask, "__builtin_ia32_rndscalepd_256_mask", IX86_BUILTIN_RNDSCALEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_UQI },
32639 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4sf_mask, "__builtin_ia32_rndscaleps_128_mask", IX86_BUILTIN_RNDSCALEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_UQI },
32640 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev2df_mask, "__builtin_ia32_rndscalepd_128_mask", IX86_BUILTIN_RNDSCALEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_UQI },
32641 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_mask, "__builtin_ia32_pternlogq256_mask", IX86_BUILTIN_VTERNLOGQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_UQI },
32642 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_maskz, "__builtin_ia32_pternlogq256_maskz", IX86_BUILTIN_VTERNLOGQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_UQI },
32643 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_mask, "__builtin_ia32_pternlogd256_mask", IX86_BUILTIN_VTERNLOGD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_UQI },
32644 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_maskz, "__builtin_ia32_pternlogd256_maskz", IX86_BUILTIN_VTERNLOGD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_UQI },
32645 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_mask, "__builtin_ia32_pternlogq128_mask", IX86_BUILTIN_VTERNLOGQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_UQI },
32646 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_maskz, "__builtin_ia32_pternlogq128_maskz", IX86_BUILTIN_VTERNLOGQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_UQI },
32647 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_mask, "__builtin_ia32_pternlogd128_mask", IX86_BUILTIN_VTERNLOGD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_UQI },
32648 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_maskz, "__builtin_ia32_pternlogd128_maskz", IX86_BUILTIN_VTERNLOGD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_UQI },
32649 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4df_mask, "__builtin_ia32_scalefpd256_mask", IX86_BUILTIN_SCALEFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32650 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv8sf_mask, "__builtin_ia32_scalefps256_mask", IX86_BUILTIN_SCALEFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32651 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv2df_mask, "__builtin_ia32_scalefpd128_mask", IX86_BUILTIN_SCALEFPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32652 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4sf_mask, "__builtin_ia32_scalefps128_mask", IX86_BUILTIN_SCALEFPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32653 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask, "__builtin_ia32_vfmaddpd256_mask", IX86_BUILTIN_VFMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32654 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask3, "__builtin_ia32_vfmaddpd256_mask3", IX86_BUILTIN_VFMADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32655 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_maskz, "__builtin_ia32_vfmaddpd256_maskz", IX86_BUILTIN_VFMADDPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32656 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask, "__builtin_ia32_vfmaddpd128_mask", IX86_BUILTIN_VFMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32657 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask3, "__builtin_ia32_vfmaddpd128_mask3", IX86_BUILTIN_VFMADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32658 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_maskz, "__builtin_ia32_vfmaddpd128_maskz", IX86_BUILTIN_VFMADDPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32659 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask, "__builtin_ia32_vfmaddps256_mask", IX86_BUILTIN_VFMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32660 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask3, "__builtin_ia32_vfmaddps256_mask3", IX86_BUILTIN_VFMADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32661 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_maskz, "__builtin_ia32_vfmaddps256_maskz", IX86_BUILTIN_VFMADDPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32662 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask, "__builtin_ia32_vfmaddps128_mask", IX86_BUILTIN_VFMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32663 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask3, "__builtin_ia32_vfmaddps128_mask3", IX86_BUILTIN_VFMADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32664 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_maskz, "__builtin_ia32_vfmaddps128_maskz", IX86_BUILTIN_VFMADDPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32665 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4df_mask3, "__builtin_ia32_vfmsubpd256_mask3", IX86_BUILTIN_VFMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32666 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v2df_mask3, "__builtin_ia32_vfmsubpd128_mask3", IX86_BUILTIN_VFMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32667 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v8sf_mask3, "__builtin_ia32_vfmsubps256_mask3", IX86_BUILTIN_VFMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32668 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4sf_mask3, "__builtin_ia32_vfmsubps128_mask3", IX86_BUILTIN_VFMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32669 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4df_mask, "__builtin_ia32_vfnmaddpd256_mask", IX86_BUILTIN_VFNMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32670 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v2df_mask, "__builtin_ia32_vfnmaddpd128_mask", IX86_BUILTIN_VFNMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32671 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v8sf_mask, "__builtin_ia32_vfnmaddps256_mask", IX86_BUILTIN_VFNMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32672 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4sf_mask, "__builtin_ia32_vfnmaddps128_mask", IX86_BUILTIN_VFNMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32673 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask, "__builtin_ia32_vfnmsubpd256_mask", IX86_BUILTIN_VFNMSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32674 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask3, "__builtin_ia32_vfnmsubpd256_mask3", IX86_BUILTIN_VFNMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32675 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask, "__builtin_ia32_vfnmsubpd128_mask", IX86_BUILTIN_VFNMSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32676 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask3, "__builtin_ia32_vfnmsubpd128_mask3", IX86_BUILTIN_VFNMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32677 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask, "__builtin_ia32_vfnmsubps256_mask", IX86_BUILTIN_VFNMSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32678 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask3, "__builtin_ia32_vfnmsubps256_mask3", IX86_BUILTIN_VFNMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32679 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask, "__builtin_ia32_vfnmsubps128_mask", IX86_BUILTIN_VFNMSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32680 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask3, "__builtin_ia32_vfnmsubps128_mask3", IX86_BUILTIN_VFNMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32681 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask, "__builtin_ia32_vfmaddsubpd256_mask", IX86_BUILTIN_VFMADDSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32682 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask3, "__builtin_ia32_vfmaddsubpd256_mask3", IX86_BUILTIN_VFMADDSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32683 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_maskz, "__builtin_ia32_vfmaddsubpd256_maskz", IX86_BUILTIN_VFMADDSUBPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32684 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask, "__builtin_ia32_vfmaddsubpd128_mask", IX86_BUILTIN_VFMADDSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32685 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask3, "__builtin_ia32_vfmaddsubpd128_mask3", IX86_BUILTIN_VFMADDSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32686 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_maskz, "__builtin_ia32_vfmaddsubpd128_maskz", IX86_BUILTIN_VFMADDSUBPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32687 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask, "__builtin_ia32_vfmaddsubps256_mask", IX86_BUILTIN_VFMADDSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32688 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask3, "__builtin_ia32_vfmaddsubps256_mask3", IX86_BUILTIN_VFMADDSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32689 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_maskz, "__builtin_ia32_vfmaddsubps256_maskz", IX86_BUILTIN_VFMADDSUBPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32690 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask, "__builtin_ia32_vfmaddsubps128_mask", IX86_BUILTIN_VFMADDSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32691 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask3, "__builtin_ia32_vfmaddsubps128_mask3", IX86_BUILTIN_VFMADDSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32692 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_maskz, "__builtin_ia32_vfmaddsubps128_maskz", IX86_BUILTIN_VFMADDSUBPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32693 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4df_mask3, "__builtin_ia32_vfmsubaddpd256_mask3", IX86_BUILTIN_VFMSUBADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32694 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v2df_mask3, "__builtin_ia32_vfmsubaddpd128_mask3", IX86_BUILTIN_VFMSUBADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32695 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3, "__builtin_ia32_vfmsubaddps256_mask3", IX86_BUILTIN_VFMSUBADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32696 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4sf_mask3, "__builtin_ia32_vfmsubaddps128_mask3", IX86_BUILTIN_VFMSUBADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32697 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4df, "__builtin_ia32_insertf64x2_256_mask", IX86_BUILTIN_INSERTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT_V4DF_UQI },
32698 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4di, "__builtin_ia32_inserti64x2_256_mask", IX86_BUILTIN_INSERTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT_V4DI_UQI },
32699 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv16hi_mask, "__builtin_ia32_psrav16hi_mask", IX86_BUILTIN_PSRAVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32700 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv8hi_mask, "__builtin_ia32_psrav8hi_mask", IX86_BUILTIN_PSRAVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32701 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v16hi_mask, "__builtin_ia32_pmaddubsw256_mask", IX86_BUILTIN_PMADDUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_V16HI_UHI },
32702 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v8hi_mask, "__builtin_ia32_pmaddubsw128_mask", IX86_BUILTIN_PMADDUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_V8HI_UQI },
32703 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v16hi_mask, "__builtin_ia32_pmaddwd256_mask", IX86_BUILTIN_PMADDWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI_V8SI_UQI },
32704 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v8hi_mask, "__builtin_ia32_pmaddwd128_mask", IX86_BUILTIN_PMADDWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI_V4SI_UQI },
32705 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv16hi_mask, "__builtin_ia32_psrlv16hi_mask", IX86_BUILTIN_PSRLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32706 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv8hi_mask, "__builtin_ia32_psrlv8hi_mask", IX86_BUILTIN_PSRLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32707 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_fix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2dq256_mask", IX86_BUILTIN_CVTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI },
32708 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_fix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2dq128_mask", IX86_BUILTIN_CVTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_UQI },
32709 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2udq256_mask", IX86_BUILTIN_CVTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_UQI },
32710 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2udq128_mask", IX86_BUILTIN_CVTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_UQI },
32711 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv4di_mask, "__builtin_ia32_cvtps2qq256_mask", IX86_BUILTIN_CVTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_UQI },
32712 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv2di_mask, "__builtin_ia32_cvtps2qq128_mask", IX86_BUILTIN_CVTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_UQI },
32713 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv4di_mask, "__builtin_ia32_cvtps2uqq256_mask", IX86_BUILTIN_CVTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_UQI },
32714 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv2di_mask, "__builtin_ia32_cvtps2uqq128_mask", IX86_BUILTIN_CVTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_UQI },
32715 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv8sf_mask, "__builtin_ia32_getmantps256_mask", IX86_BUILTIN_GETMANTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_UQI },
32716 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4sf_mask, "__builtin_ia32_getmantps128_mask", IX86_BUILTIN_GETMANTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_UQI },
32717 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4df_mask, "__builtin_ia32_getmantpd256_mask", IX86_BUILTIN_GETMANTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_UQI },
32718 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv2df_mask, "__builtin_ia32_getmantpd128_mask", IX86_BUILTIN_GETMANTPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_UQI },
32719 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movddup256_mask, "__builtin_ia32_movddup256_mask", IX86_BUILTIN_MOVDDUP256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_UQI },
32720 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_dupv2df_mask, "__builtin_ia32_movddup128_mask", IX86_BUILTIN_MOVDDUP128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_UQI },
32721 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movshdup256_mask, "__builtin_ia32_movshdup256_mask", IX86_BUILTIN_MOVSHDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_UQI },
32722 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movshdup_mask, "__builtin_ia32_movshdup128_mask", IX86_BUILTIN_MOVSHDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32723 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_movsldup256_mask", IX86_BUILTIN_MOVSLDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_UQI },
32724 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32725 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_UQI },
32726 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_UQI },
32727 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_UQI },
32728 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_UQI },
32729 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_UQI },
32730 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_UQI },
32731 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_UQI },
32732 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_UQI },
32733 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32734 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32735 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32736 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_maskz, "__builtin_ia32_vpermt2vard256_maskz", IX86_BUILTIN_VPERMT2VARD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32737 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4di3_mask, "__builtin_ia32_vpermi2varq256_mask", IX86_BUILTIN_VPERMI2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32738 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8si3_mask, "__builtin_ia32_vpermi2vard256_mask", IX86_BUILTIN_VPERMI2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32739 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_mask, "__builtin_ia32_vpermt2varpd256_mask", IX86_BUILTIN_VPERMT2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_UQI },
32740 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_maskz, "__builtin_ia32_vpermt2varpd256_maskz", IX86_BUILTIN_VPERMT2VARPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_UQI },
32741 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_mask, "__builtin_ia32_vpermt2varps256_mask", IX86_BUILTIN_VPERMT2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_UQI },
32742 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_maskz, "__builtin_ia32_vpermt2varps256_maskz", IX86_BUILTIN_VPERMT2VARPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_UQI },
32743 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4df3_mask, "__builtin_ia32_vpermi2varpd256_mask", IX86_BUILTIN_VPERMI2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_UQI },
32744 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8sf3_mask, "__builtin_ia32_vpermi2varps256_mask", IX86_BUILTIN_VPERMI2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_UQI },
32745 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_mask, "__builtin_ia32_vpermt2varq128_mask", IX86_BUILTIN_VPERMT2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32746 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_maskz, "__builtin_ia32_vpermt2varq128_maskz", IX86_BUILTIN_VPERMT2VARQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32747 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_mask, "__builtin_ia32_vpermt2vard128_mask", IX86_BUILTIN_VPERMT2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32748 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_maskz, "__builtin_ia32_vpermt2vard128_maskz", IX86_BUILTIN_VPERMT2VARD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32749 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2di3_mask, "__builtin_ia32_vpermi2varq128_mask", IX86_BUILTIN_VPERMI2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32750 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4si3_mask, "__builtin_ia32_vpermi2vard128_mask", IX86_BUILTIN_VPERMI2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32751 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_mask, "__builtin_ia32_vpermt2varpd128_mask", IX86_BUILTIN_VPERMT2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_UQI },
32752 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_maskz, "__builtin_ia32_vpermt2varpd128_maskz", IX86_BUILTIN_VPERMT2VARPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_UQI },
32753 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_mask, "__builtin_ia32_vpermt2varps128_mask", IX86_BUILTIN_VPERMT2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_UQI },
32754 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_maskz, "__builtin_ia32_vpermt2varps128_maskz", IX86_BUILTIN_VPERMT2VARPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_UQI },
32755 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2df3_mask, "__builtin_ia32_vpermi2varpd128_mask", IX86_BUILTIN_VPERMI2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_UQI },
32756 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4sf3_mask, "__builtin_ia32_vpermi2varps128_mask", IX86_BUILTIN_VPERMI2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_UQI },
32757 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pshufbv32qi3_mask, "__builtin_ia32_pshufb256_mask", IX86_BUILTIN_PSHUFB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32758 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pshufbv16qi3_mask, "__builtin_ia32_pshufb128_mask", IX86_BUILTIN_PSHUFB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32759 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhwv3_mask, "__builtin_ia32_pshufhw256_mask", IX86_BUILTIN_PSHUFHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_UHI },
32760 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhw_mask, "__builtin_ia32_pshufhw128_mask", IX86_BUILTIN_PSHUFHW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_UQI },
32761 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflwv3_mask, "__builtin_ia32_pshuflw256_mask", IX86_BUILTIN_PSHUFLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_UHI },
32762 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflw_mask, "__builtin_ia32_pshuflw128_mask", IX86_BUILTIN_PSHUFLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_UQI },
32763 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufdv3_mask, "__builtin_ia32_pshufd256_mask", IX86_BUILTIN_PSHUFD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_UQI },
32764 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufd_mask, "__builtin_ia32_pshufd128_mask", IX86_BUILTIN_PSHUFD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_UQI },
32765 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufpd256_mask, "__builtin_ia32_shufpd256_mask", IX86_BUILTIN_SHUFPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_UQI },
32766 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_shufpd_mask, "__builtin_ia32_shufpd128_mask", IX86_BUILTIN_SHUFPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_UQI },
32767 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufps256_mask, "__builtin_ia32_shufps256_mask", IX86_BUILTIN_SHUFPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_UQI },
32768 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_shufps_mask, "__builtin_ia32_shufps128_mask", IX86_BUILTIN_SHUFPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_UQI },
32769 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4di_mask, "__builtin_ia32_prolvq256_mask", IX86_BUILTIN_PROLVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32770 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv2di_mask, "__builtin_ia32_prolvq128_mask", IX86_BUILTIN_PROLVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32771 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4di_mask, "__builtin_ia32_prolq256_mask", IX86_BUILTIN_PROLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_UQI },
32772 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv2di_mask, "__builtin_ia32_prolq128_mask", IX86_BUILTIN_PROLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_UQI },
32773 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4di_mask, "__builtin_ia32_prorvq256_mask", IX86_BUILTIN_PRORVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32774 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv2di_mask, "__builtin_ia32_prorvq128_mask", IX86_BUILTIN_PRORVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32775 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4di_mask, "__builtin_ia32_prorq256_mask", IX86_BUILTIN_PRORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_UQI },
32776 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv2di_mask, "__builtin_ia32_prorq128_mask", IX86_BUILTIN_PRORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_UQI },
32777 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv2di_mask, "__builtin_ia32_psravq128_mask", IX86_BUILTIN_PSRAVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32778 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4di_mask, "__builtin_ia32_psravq256_mask", IX86_BUILTIN_PSRAVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32779 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4di_mask, "__builtin_ia32_psllv4di_mask", IX86_BUILTIN_PSLLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32780 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv2di_mask, "__builtin_ia32_psllv2di_mask", IX86_BUILTIN_PSLLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32781 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv8si_mask, "__builtin_ia32_psllv8si_mask", IX86_BUILTIN_PSLLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32782 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4si_mask, "__builtin_ia32_psllv4si_mask", IX86_BUILTIN_PSLLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32783 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv8si_mask, "__builtin_ia32_psrav8si_mask", IX86_BUILTIN_PSRAVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32784 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4si_mask, "__builtin_ia32_psrav4si_mask", IX86_BUILTIN_PSRAVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32785 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4di_mask, "__builtin_ia32_psrlv4di_mask", IX86_BUILTIN_PSRLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32786 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv2di_mask, "__builtin_ia32_psrlv2di_mask", IX86_BUILTIN_PSRLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32787 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv8si_mask, "__builtin_ia32_psrlv8si_mask", IX86_BUILTIN_PSRLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32788 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4si_mask, "__builtin_ia32_psrlv4si_mask", IX86_BUILTIN_PSRLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32789 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psrawi256_mask", IX86_BUILTIN_PSRAWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_UHI },
32790 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psraw256_mask", IX86_BUILTIN_PSRAW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_UHI },
32791 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psrawi128_mask", IX86_BUILTIN_PSRAWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_UQI },
32792 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psraw128_mask", IX86_BUILTIN_PSRAW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32793 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlwi256_mask", IX86_BUILTIN_PSRLWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_UHI },
32794 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlw256_mask", IX86_BUILTIN_PSRLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_UHI },
32795 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlwi128_mask", IX86_BUILTIN_PSRLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_UQI },
32796 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlw128_mask", IX86_BUILTIN_PSRLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32797 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv8si_mask, "__builtin_ia32_prorvd256_mask", IX86_BUILTIN_PRORVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32798 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv8si_mask, "__builtin_ia32_prolvd256_mask", IX86_BUILTIN_PROLVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32799 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv8si_mask, "__builtin_ia32_prord256_mask", IX86_BUILTIN_PRORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_UQI },
32800 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv8si_mask, "__builtin_ia32_prold256_mask", IX86_BUILTIN_PROLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_UQI },
32801 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4si_mask, "__builtin_ia32_prorvd128_mask", IX86_BUILTIN_PRORVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32802 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4si_mask, "__builtin_ia32_prolvd128_mask", IX86_BUILTIN_PROLVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32803 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_ia32_prord128_mask", IX86_BUILTIN_PRORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_UQI },
32804 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_UQI },
32805 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_UQI },
32806 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_UQI },
32807 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT },
32808 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_UQI },
32809 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_UQI },
32810 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT },
32811 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) UHI_FTYPE_V16QI },
32812 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) USI_FTYPE_V32QI },
32813 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) UQI_FTYPE_V8HI },
32814 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv16hi, "__builtin_ia32_cvtw2mask256", IX86_BUILTIN_CVTW2MASK256, UNKNOWN, (int) UHI_FTYPE_V16HI },
32815 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv4si, "__builtin_ia32_cvtd2mask128", IX86_BUILTIN_CVTD2MASK128, UNKNOWN, (int) UQI_FTYPE_V4SI },
32816 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv8si, "__builtin_ia32_cvtd2mask256", IX86_BUILTIN_CVTD2MASK256, UNKNOWN, (int) UQI_FTYPE_V8SI },
32817 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv2di, "__builtin_ia32_cvtq2mask128", IX86_BUILTIN_CVTQ2MASK128, UNKNOWN, (int) UQI_FTYPE_V2DI },
32818 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv4di, "__builtin_ia32_cvtq2mask256", IX86_BUILTIN_CVTQ2MASK256, UNKNOWN, (int) UQI_FTYPE_V4DI },
32819 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv16qi, "__builtin_ia32_cvtmask2b128", IX86_BUILTIN_CVTMASK2B128, UNKNOWN, (int) V16QI_FTYPE_UHI },
32820 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv32qi, "__builtin_ia32_cvtmask2b256", IX86_BUILTIN_CVTMASK2B256, UNKNOWN, (int) V32QI_FTYPE_USI },
32821 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv8hi, "__builtin_ia32_cvtmask2w128", IX86_BUILTIN_CVTMASK2W128, UNKNOWN, (int) V8HI_FTYPE_UQI },
32822 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv16hi, "__builtin_ia32_cvtmask2w256", IX86_BUILTIN_CVTMASK2W256, UNKNOWN, (int) V16HI_FTYPE_UHI },
32823 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv4si, "__builtin_ia32_cvtmask2d128", IX86_BUILTIN_CVTMASK2D128, UNKNOWN, (int) V4SI_FTYPE_UQI },
32824 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv8si, "__builtin_ia32_cvtmask2d256", IX86_BUILTIN_CVTMASK2D256, UNKNOWN, (int) V8SI_FTYPE_UQI },
32825 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv2di, "__builtin_ia32_cvtmask2q128", IX86_BUILTIN_CVTMASK2Q128, UNKNOWN, (int) V2DI_FTYPE_UQI },
32826 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv4di, "__builtin_ia32_cvtmask2q256", IX86_BUILTIN_CVTMASK2Q256, UNKNOWN, (int) V4DI_FTYPE_UQI },
32827 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16qi3_mask, "__builtin_ia32_pcmpeqb128_mask", IX86_BUILTIN_PCMPEQB128_MASK, UNKNOWN, (int) UHI_FTYPE_V16QI_V16QI_UHI },
32828 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv32qi3_mask, "__builtin_ia32_pcmpeqb256_mask", IX86_BUILTIN_PCMPEQB256_MASK, UNKNOWN, (int) USI_FTYPE_V32QI_V32QI_USI },
32829 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8hi3_mask, "__builtin_ia32_pcmpeqw128_mask", IX86_BUILTIN_PCMPEQW128_MASK, UNKNOWN, (int) UQI_FTYPE_V8HI_V8HI_UQI },
32830 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16hi3_mask, "__builtin_ia32_pcmpeqw256_mask", IX86_BUILTIN_PCMPEQW256_MASK, UNKNOWN, (int) UHI_FTYPE_V16HI_V16HI_UHI },
32831 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4si3_mask, "__builtin_ia32_pcmpeqd128_mask", IX86_BUILTIN_PCMPEQD128_MASK, UNKNOWN, (int) UQI_FTYPE_V4SI_V4SI_UQI },
32832 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8si3_mask, "__builtin_ia32_pcmpeqd256_mask", IX86_BUILTIN_PCMPEQD256_MASK, UNKNOWN, (int) UQI_FTYPE_V8SI_V8SI_UQI },
32833 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv2di3_mask, "__builtin_ia32_pcmpeqq128_mask", IX86_BUILTIN_PCMPEQQ128_MASK, UNKNOWN, (int) UQI_FTYPE_V2DI_V2DI_UQI },
32834 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4di3_mask, "__builtin_ia32_pcmpeqq256_mask", IX86_BUILTIN_PCMPEQQ256_MASK, UNKNOWN, (int) UQI_FTYPE_V4DI_V4DI_UQI },
32835 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16qi3_mask, "__builtin_ia32_pcmpgtb128_mask", IX86_BUILTIN_PCMPGTB128_MASK, UNKNOWN, (int) UHI_FTYPE_V16QI_V16QI_UHI },
32836 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv32qi3_mask, "__builtin_ia32_pcmpgtb256_mask", IX86_BUILTIN_PCMPGTB256_MASK, UNKNOWN, (int) USI_FTYPE_V32QI_V32QI_USI },
32837 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8hi3_mask, "__builtin_ia32_pcmpgtw128_mask", IX86_BUILTIN_PCMPGTW128_MASK, UNKNOWN, (int) UQI_FTYPE_V8HI_V8HI_UQI },
32838 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16hi3_mask, "__builtin_ia32_pcmpgtw256_mask", IX86_BUILTIN_PCMPGTW256_MASK, UNKNOWN, (int) UHI_FTYPE_V16HI_V16HI_UHI },
32839 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4si3_mask, "__builtin_ia32_pcmpgtd128_mask", IX86_BUILTIN_PCMPGTD128_MASK, UNKNOWN, (int) UQI_FTYPE_V4SI_V4SI_UQI },
32840 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8si3_mask, "__builtin_ia32_pcmpgtd256_mask", IX86_BUILTIN_PCMPGTD256_MASK, UNKNOWN, (int) UQI_FTYPE_V8SI_V8SI_UQI },
32841 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv2di3_mask, "__builtin_ia32_pcmpgtq128_mask", IX86_BUILTIN_PCMPGTQ128_MASK, UNKNOWN, (int) UQI_FTYPE_V2DI_V2DI_UQI },
32842 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4di3_mask, "__builtin_ia32_pcmpgtq256_mask", IX86_BUILTIN_PCMPGTQ256_MASK, UNKNOWN, (int) UQI_FTYPE_V4DI_V4DI_UQI },
32843 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16qi3_mask, "__builtin_ia32_ptestmb128", IX86_BUILTIN_PTESTMB128, UNKNOWN, (int) UHI_FTYPE_V16QI_V16QI_UHI },
32844 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv32qi3_mask, "__builtin_ia32_ptestmb256", IX86_BUILTIN_PTESTMB256, UNKNOWN, (int) USI_FTYPE_V32QI_V32QI_USI },
32845 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8hi3_mask, "__builtin_ia32_ptestmw128", IX86_BUILTIN_PTESTMW128, UNKNOWN, (int) UQI_FTYPE_V8HI_V8HI_UQI },
32846 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16hi3_mask, "__builtin_ia32_ptestmw256", IX86_BUILTIN_PTESTMW256, UNKNOWN, (int) UHI_FTYPE_V16HI_V16HI_UHI },
32847 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4si3_mask, "__builtin_ia32_ptestmd128", IX86_BUILTIN_PTESTMD128, UNKNOWN, (int) UQI_FTYPE_V4SI_V4SI_UQI },
32848 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8si3_mask, "__builtin_ia32_ptestmd256", IX86_BUILTIN_PTESTMD256, UNKNOWN, (int) UQI_FTYPE_V8SI_V8SI_UQI },
32849 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv2di3_mask, "__builtin_ia32_ptestmq128", IX86_BUILTIN_PTESTMQ128, UNKNOWN, (int) UQI_FTYPE_V2DI_V2DI_UQI },
32850 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4di3_mask, "__builtin_ia32_ptestmq256", IX86_BUILTIN_PTESTMQ256, UNKNOWN, (int) UQI_FTYPE_V4DI_V4DI_UQI },
32851 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16qi3_mask, "__builtin_ia32_ptestnmb128", IX86_BUILTIN_PTESTNMB128, UNKNOWN, (int) UHI_FTYPE_V16QI_V16QI_UHI },
32852 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv32qi3_mask, "__builtin_ia32_ptestnmb256", IX86_BUILTIN_PTESTNMB256, UNKNOWN, (int) USI_FTYPE_V32QI_V32QI_USI },
32853 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8hi3_mask, "__builtin_ia32_ptestnmw128", IX86_BUILTIN_PTESTNMW128, UNKNOWN, (int) UQI_FTYPE_V8HI_V8HI_UQI },
32854 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16hi3_mask, "__builtin_ia32_ptestnmw256", IX86_BUILTIN_PTESTNMW256, UNKNOWN, (int) UHI_FTYPE_V16HI_V16HI_UHI },
32855 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4si3_mask, "__builtin_ia32_ptestnmd128", IX86_BUILTIN_PTESTNMD128, UNKNOWN, (int) UQI_FTYPE_V4SI_V4SI_UQI },
32856 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8si3_mask, "__builtin_ia32_ptestnmd256", IX86_BUILTIN_PTESTNMD256, UNKNOWN, (int) UQI_FTYPE_V8SI_V8SI_UQI },
32857 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv2di3_mask, "__builtin_ia32_ptestnmq128", IX86_BUILTIN_PTESTNMQ128, UNKNOWN, (int) UQI_FTYPE_V2DI_V2DI_UQI },
32858 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4di3_mask, "__builtin_ia32_ptestnmq256", IX86_BUILTIN_PTESTNMQ256, UNKNOWN, (int) UQI_FTYPE_V4DI_V4DI_UQI },
32859 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv2di, "__builtin_ia32_broadcastmb128", IX86_BUILTIN_PBROADCASTMB128, UNKNOWN, (int) V2DI_FTYPE_UQI },
32860 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv4di, "__builtin_ia32_broadcastmb256", IX86_BUILTIN_PBROADCASTMB256, UNKNOWN, (int) V4DI_FTYPE_UQI },
32861 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv4si, "__builtin_ia32_broadcastmw128", IX86_BUILTIN_PBROADCASTMW128, UNKNOWN, (int) V4SI_FTYPE_UHI },
32862 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv8si, "__builtin_ia32_broadcastmw256", IX86_BUILTIN_PBROADCASTMW256, UNKNOWN, (int) V8SI_FTYPE_UHI },
32863 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4df_mask, "__builtin_ia32_compressdf256_mask", IX86_BUILTIN_COMPRESSPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_UQI },
32864 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2df_mask, "__builtin_ia32_compressdf128_mask", IX86_BUILTIN_COMPRESSPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_UQI },
32865 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8sf_mask, "__builtin_ia32_compresssf256_mask", IX86_BUILTIN_COMPRESSPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_UQI },
32866 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4sf_mask, "__builtin_ia32_compresssf128_mask", IX86_BUILTIN_COMPRESSPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32867 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4di_mask, "__builtin_ia32_compressdi256_mask", IX86_BUILTIN_PCOMPRESSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_UQI },
32868 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2di_mask, "__builtin_ia32_compressdi128_mask", IX86_BUILTIN_PCOMPRESSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UQI },
32869 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8si_mask, "__builtin_ia32_compresssi256_mask", IX86_BUILTIN_PCOMPRESSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_UQI },
32870 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4si_mask, "__builtin_ia32_compresssi128_mask", IX86_BUILTIN_PCOMPRESSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_UQI },
32871 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expanddf256_mask", IX86_BUILTIN_EXPANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_UQI },
32872 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expanddf128_mask", IX86_BUILTIN_EXPANDPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_UQI },
32873 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandsf256_mask", IX86_BUILTIN_EXPANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_UQI },
32874 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandsf128_mask", IX86_BUILTIN_EXPANDPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32875 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expanddi256_mask", IX86_BUILTIN_PEXPANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_UQI },
32876 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expanddi128_mask", IX86_BUILTIN_PEXPANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UQI },
32877 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandsi256_mask", IX86_BUILTIN_PEXPANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_UQI },
32878 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandsi128_mask", IX86_BUILTIN_PEXPANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_UQI },
32879 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expanddf256_maskz", IX86_BUILTIN_EXPANDPD256Z, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_UQI },
32880 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expanddf128_maskz", IX86_BUILTIN_EXPANDPD128Z, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_UQI },
32881 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandsf256_maskz", IX86_BUILTIN_EXPANDPS256Z, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_UQI },
32882 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandsf128_maskz", IX86_BUILTIN_EXPANDPS128Z, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32883 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expanddi256_maskz", IX86_BUILTIN_PEXPANDQ256Z, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_UQI },
32884 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expanddi128_maskz", IX86_BUILTIN_PEXPANDQ128Z, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UQI },
32885 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandsi256_maskz", IX86_BUILTIN_PEXPANDD256Z, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_UQI },
32886 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandsi128_maskz", IX86_BUILTIN_PEXPANDD128Z, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_UQI },
32887 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8si3_mask, "__builtin_ia32_pmaxsd256_mask", IX86_BUILTIN_PMAXSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32888 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8si3_mask, "__builtin_ia32_pminsd256_mask", IX86_BUILTIN_PMINSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32889 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8si3_mask, "__builtin_ia32_pmaxud256_mask", IX86_BUILTIN_PMAXUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32890 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8si3_mask, "__builtin_ia32_pminud256_mask", IX86_BUILTIN_PMINUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32891 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4si3_mask, "__builtin_ia32_pmaxsd128_mask", IX86_BUILTIN_PMAXSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32892 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4si3_mask, "__builtin_ia32_pminsd128_mask", IX86_BUILTIN_PMINSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32893 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4si3_mask, "__builtin_ia32_pmaxud128_mask", IX86_BUILTIN_PMAXUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32894 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4si3_mask, "__builtin_ia32_pminud128_mask", IX86_BUILTIN_PMINUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32895 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4di3_mask, "__builtin_ia32_pmaxsq256_mask", IX86_BUILTIN_PMAXSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32896 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4di3_mask, "__builtin_ia32_pminsq256_mask", IX86_BUILTIN_PMINSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32897 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4di3_mask, "__builtin_ia32_pmaxuq256_mask", IX86_BUILTIN_PMAXUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32898 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4di3_mask, "__builtin_ia32_pminuq256_mask", IX86_BUILTIN_PMINUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32899 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2di3_mask, "__builtin_ia32_pmaxsq128_mask", IX86_BUILTIN_PMAXSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32900 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2di3_mask, "__builtin_ia32_pminsq128_mask", IX86_BUILTIN_PMINSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32901 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv2di3_mask, "__builtin_ia32_pmaxuq128_mask", IX86_BUILTIN_PMAXUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32902 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv2di3_mask, "__builtin_ia32_pminuq128_mask", IX86_BUILTIN_PMINUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32903 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv32qi3_mask, "__builtin_ia32_pminsb256_mask", IX86_BUILTIN_PMINSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32904 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv32qi3_mask, "__builtin_ia32_pminub256_mask", IX86_BUILTIN_PMINUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32905 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv32qi3_mask, "__builtin_ia32_pmaxsb256_mask", IX86_BUILTIN_PMAXSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32906 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv32qi3_mask, "__builtin_ia32_pmaxub256_mask", IX86_BUILTIN_PMAXUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32907 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16qi3_mask, "__builtin_ia32_pminsb128_mask", IX86_BUILTIN_PMINSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32908 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16qi3_mask, "__builtin_ia32_pminub128_mask", IX86_BUILTIN_PMINUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32909 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16qi3_mask, "__builtin_ia32_pmaxsb128_mask", IX86_BUILTIN_PMAXSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32910 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16qi3_mask, "__builtin_ia32_pmaxub128_mask", IX86_BUILTIN_PMAXUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32911 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16hi3_mask, "__builtin_ia32_pminsw256_mask", IX86_BUILTIN_PMINSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32912 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16hi3_mask, "__builtin_ia32_pminuw256_mask", IX86_BUILTIN_PMINUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32913 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16hi3_mask, "__builtin_ia32_pmaxsw256_mask", IX86_BUILTIN_PMAXSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32914 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16hi3_mask, "__builtin_ia32_pmaxuw256_mask", IX86_BUILTIN_PMAXUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32915 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8hi3_mask, "__builtin_ia32_pminsw128_mask", IX86_BUILTIN_PMINSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32916 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8hi3_mask, "__builtin_ia32_pminuw128_mask", IX86_BUILTIN_PMINUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32917 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8hi3_mask, "__builtin_ia32_pmaxsw128_mask", IX86_BUILTIN_PMAXSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32918 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8hi3_mask, "__builtin_ia32_pmaxuw128_mask", IX86_BUILTIN_PMAXUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32919 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4di_mask, "__builtin_ia32_vpconflictdi_256_mask", IX86_BUILTIN_VPCONFLICTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_UQI },
32920 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv8si_mask, "__builtin_ia32_vpconflictsi_256_mask", IX86_BUILTIN_VPCONFLICTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_UQI },
32921 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4di2_mask, "__builtin_ia32_vplzcntq_256_mask", IX86_BUILTIN_VPCLZCNTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_UQI },
32922 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv8si2_mask, "__builtin_ia32_vplzcntd_256_mask", IX86_BUILTIN_VPCLZCNTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_UQI },
32923 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhpd256_mask, "__builtin_ia32_unpckhpd256_mask", IX86_BUILTIN_UNPCKHPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32924 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpckhpd128_mask, "__builtin_ia32_unpckhpd128_mask", IX86_BUILTIN_UNPCKHPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32925 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhps256_mask, "__builtin_ia32_unpckhps256_mask", IX86_BUILTIN_UNPCKHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32926 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4sf_mask, "__builtin_ia32_unpckhps128_mask", IX86_BUILTIN_UNPCKHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32927 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklpd256_mask, "__builtin_ia32_unpcklpd256_mask", IX86_BUILTIN_UNPCKLPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_UQI },
32928 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpcklpd128_mask, "__builtin_ia32_unpcklpd128_mask", IX86_BUILTIN_UNPCKLPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_UQI },
32929 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklps256_mask, "__builtin_ia32_unpcklps256_mask", IX86_BUILTIN_UNPCKLPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_UQI },
32930 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv2di_mask, "__builtin_ia32_vpconflictdi_128_mask", IX86_BUILTIN_VPCONFLICTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UQI },
32931 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4si_mask, "__builtin_ia32_vpconflictsi_128_mask", IX86_BUILTIN_VPCONFLICTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_UQI },
32932 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv2di2_mask, "__builtin_ia32_vplzcntq_128_mask", IX86_BUILTIN_VPCLZCNTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UQI },
32933 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4si2_mask, "__builtin_ia32_vplzcntd_128_mask", IX86_BUILTIN_VPCLZCNTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_UQI },
32934 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_unpcklps128_mask, "__builtin_ia32_unpcklps128_mask", IX86_BUILTIN_UNPCKLPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_UQI },
32935 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv8si_mask, "__builtin_ia32_alignd256_mask", IX86_BUILTIN_ALIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_UQI },
32936 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4di_mask, "__builtin_ia32_alignq256_mask", IX86_BUILTIN_ALIGNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_UQI },
32937 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4si_mask, "__builtin_ia32_alignd128_mask", IX86_BUILTIN_ALIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_UQI },
32938 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv2di_mask, "__builtin_ia32_alignq128_mask", IX86_BUILTIN_ALIGNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_UQI },
32939 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph256_mask, "__builtin_ia32_vcvtps2ph256_mask", IX86_BUILTIN_CVTPS2PH256_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT_V8HI_UQI },
32940 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph_mask, "__builtin_ia32_vcvtps2ph_mask", IX86_BUILTIN_CVTPS2PH_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT_V8HI_UQI },
32941 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps_mask, "__builtin_ia32_vcvtph2ps_mask", IX86_BUILTIN_CVTPH2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V8HI_V4SF_UQI },
32942 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps256_mask, "__builtin_ia32_vcvtph2ps256_mask", IX86_BUILTIN_CVTPH2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8HI_V8SF_UQI },
32943 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4si_mask, "__builtin_ia32_punpckhdq128_mask", IX86_BUILTIN_PUNPCKHDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32944 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv8si_mask, "__builtin_ia32_punpckhdq256_mask", IX86_BUILTIN_PUNPCKHDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32945 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv2di_mask, "__builtin_ia32_punpckhqdq128_mask", IX86_BUILTIN_PUNPCKHQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32946 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv4di_mask, "__builtin_ia32_punpckhqdq256_mask", IX86_BUILTIN_PUNPCKHQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32947 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv4si_mask, "__builtin_ia32_punpckldq128_mask", IX86_BUILTIN_PUNPCKLDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32948 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv8si_mask, "__builtin_ia32_punpckldq256_mask", IX86_BUILTIN_PUNPCKLDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32949 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv2di_mask, "__builtin_ia32_punpcklqdq128_mask", IX86_BUILTIN_PUNPCKLQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
32950 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv4di_mask, "__builtin_ia32_punpcklqdq256_mask", IX86_BUILTIN_PUNPCKLQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
32951 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv16qi_mask, "__builtin_ia32_punpckhbw128_mask", IX86_BUILTIN_PUNPCKHBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32952 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv32qi_mask, "__builtin_ia32_punpckhbw256_mask", IX86_BUILTIN_PUNPCKHBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32953 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv8hi_mask, "__builtin_ia32_punpckhwd128_mask", IX86_BUILTIN_PUNPCKHWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32954 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv16hi_mask, "__builtin_ia32_punpckhwd256_mask", IX86_BUILTIN_PUNPCKHWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32955 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv16qi_mask, "__builtin_ia32_punpcklbw128_mask", IX86_BUILTIN_PUNPCKLBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32956 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv32qi_mask, "__builtin_ia32_punpcklbw256_mask", IX86_BUILTIN_PUNPCKLBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32957 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv8hi_mask, "__builtin_ia32_punpcklwd128_mask", IX86_BUILTIN_PUNPCKLWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32958 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv16hi_mask, "__builtin_ia32_punpcklwd256_mask", IX86_BUILTIN_PUNPCKLWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32959 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv16hi_mask, "__builtin_ia32_psllv16hi_mask", IX86_BUILTIN_PSLLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32960 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv8hi_mask, "__builtin_ia32_psllv8hi_mask", IX86_BUILTIN_PSLLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32961 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packssdw_mask, "__builtin_ia32_packssdw256_mask", IX86_BUILTIN_PACKSSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_UHI },
32962 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packssdw_mask, "__builtin_ia32_packssdw128_mask", IX86_BUILTIN_PACKSSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_UQI },
32963 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packusdw_mask, "__builtin_ia32_packusdw256_mask", IX86_BUILTIN_PACKUSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_UHI },
32964 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_packusdw_mask, "__builtin_ia32_packusdw128_mask", IX86_BUILTIN_PACKUSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_UQI },
32965 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv32qi3_mask, "__builtin_ia32_pavgb256_mask", IX86_BUILTIN_PAVGB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
32966 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv16hi3_mask, "__builtin_ia32_pavgw256_mask", IX86_BUILTIN_PAVGW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_UHI },
32967 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv16qi3_mask, "__builtin_ia32_pavgb128_mask", IX86_BUILTIN_PAVGB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
32968 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv8hi3_mask, "__builtin_ia32_pavgw128_mask", IX86_BUILTIN_PAVGW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_UQI },
32969 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8sf_mask, "__builtin_ia32_permvarsf256_mask", IX86_BUILTIN_VPERMVARSF256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_UQI },
32970 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4df_mask, "__builtin_ia32_permvardf256_mask", IX86_BUILTIN_VPERMVARDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_UQI },
32971 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4df_mask, "__builtin_ia32_permdf256_mask", IX86_BUILTIN_VPERMDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_UQI },
32972 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv32qi2_mask, "__builtin_ia32_pabsb256_mask", IX86_BUILTIN_PABSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_USI },
32973 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16qi2_mask, "__builtin_ia32_pabsb128_mask", IX86_BUILTIN_PABSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_UHI },
32974 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16hi2_mask, "__builtin_ia32_pabsw256_mask", IX86_BUILTIN_PABSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_UHI },
32975 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8hi2_mask, "__builtin_ia32_pabsw128_mask", IX86_BUILTIN_PABSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_UQI },
32976 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv2df3_mask, "__builtin_ia32_vpermilvarpd_mask", IX86_BUILTIN_VPERMILVARPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_UQI },
32977 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4sf3_mask, "__builtin_ia32_vpermilvarps_mask", IX86_BUILTIN_VPERMILVARPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_UQI },
32978 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4df3_mask, "__builtin_ia32_vpermilvarpd256_mask", IX86_BUILTIN_VPERMILVARPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_UQI },
32979 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv8sf3_mask, "__builtin_ia32_vpermilvarps256_mask", IX86_BUILTIN_VPERMILVARPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_UQI },
32980 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv2df_mask, "__builtin_ia32_vpermilpd_mask", IX86_BUILTIN_VPERMILPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_UQI },
32981 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4sf_mask, "__builtin_ia32_vpermilps_mask", IX86_BUILTIN_VPERMILPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_UQI },
32982 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4df_mask, "__builtin_ia32_vpermilpd256_mask", IX86_BUILTIN_VPERMILPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_UQI },
32983 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv8sf_mask, "__builtin_ia32_vpermilps256_mask", IX86_BUILTIN_VPERMILPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_UQI },
32984 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4di, "__builtin_ia32_blendmq_256_mask", IX86_BUILTIN_BLENDMQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_UQI },
32985 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8si, "__builtin_ia32_blendmd_256_mask", IX86_BUILTIN_BLENDMD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_UQI },
32986 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4df, "__builtin_ia32_blendmpd_256_mask", IX86_BUILTIN_BLENDMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_UQI },
32987 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8sf, "__builtin_ia32_blendmps_256_mask", IX86_BUILTIN_BLENDMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_UQI },
32988 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2di, "__builtin_ia32_blendmq_128_mask", IX86_BUILTIN_BLENDMQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UQI },
32989 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4si, "__builtin_ia32_blendmd_128_mask", IX86_BUILTIN_BLENDMD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_UQI },
32990 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2df, "__builtin_ia32_blendmpd_128_mask", IX86_BUILTIN_BLENDMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_UQI },
32991 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4sf, "__builtin_ia32_blendmps_128_mask", IX86_BUILTIN_BLENDMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_UQI },
32992 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16hi, "__builtin_ia32_blendmw_256_mask", IX86_BUILTIN_BLENDMW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_UHI },
32993 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv32qi, "__builtin_ia32_blendmb_256_mask", IX86_BUILTIN_BLENDMB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_USI },
32994 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8hi, "__builtin_ia32_blendmw_128_mask", IX86_BUILTIN_BLENDMW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_UQI },
32995 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16qi, "__builtin_ia32_blendmb_128_mask", IX86_BUILTIN_BLENDMB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_UHI },
32996 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8si3_mask, "__builtin_ia32_pmulld256_mask", IX86_BUILTIN_PMULLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
32997 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4si3_mask, "__builtin_ia32_pmulld128_mask", IX86_BUILTIN_PMULLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_UQI },
32998 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v8si_mask, "__builtin_ia32_pmuludq256_mask", IX86_BUILTIN_PMULUDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_UQI },
32999 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_smult_even_v8si_mask, "__builtin_ia32_pmuldq256_mask", IX86_BUILTIN_PMULDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_UQI },
33000 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_mulv2siv2di3_mask, "__builtin_ia32_pmuldq128_mask", IX86_BUILTIN_PMULDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_UQI },
33001 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v4si_mask, "__builtin_ia32_pmuludq128_mask", IX86_BUILTIN_PMULUDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_UQI },
33002 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2ps256_mask, "__builtin_ia32_cvtpd2ps256_mask", IX86_BUILTIN_CVTPD2PS256_MASK, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_UQI },
33003 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2ps_mask, "__builtin_ia32_cvtpd2ps_mask", IX86_BUILTIN_CVTPD2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V2DF_V4SF_UQI },
33004 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8si_mask, "__builtin_ia32_permvarsi256_mask", IX86_BUILTIN_VPERMVARSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_UQI },
33005 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4di_mask, "__builtin_ia32_permvardi256_mask", IX86_BUILTIN_VPERMVARDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
33006 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4di_mask, "__builtin_ia32_permdi256_mask", IX86_BUILTIN_VPERMDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_UQI },
33007 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4di3_mask, "__builtin_ia32_cmpq256_mask", IX86_BUILTIN_CMPQ256, UNKNOWN, (int) UQI_FTYPE_V4DI_V4DI_INT_UQI },
33008 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8si3_mask, "__builtin_ia32_cmpd256_mask", IX86_BUILTIN_CMPD256, UNKNOWN, (int) UQI_FTYPE_V8SI_V8SI_INT_UQI },
33009 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4di3_mask, "__builtin_ia32_ucmpq256_mask", IX86_BUILTIN_UCMPQ256, UNKNOWN, (int) UQI_FTYPE_V4DI_V4DI_INT_UQI },
33010 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8si3_mask, "__builtin_ia32_ucmpd256_mask", IX86_BUILTIN_UCMPD256, UNKNOWN, (int) UQI_FTYPE_V8SI_V8SI_INT_UQI },
33011 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv32qi3_mask, "__builtin_ia32_cmpb256_mask", IX86_BUILTIN_CMPB256, UNKNOWN, (int) USI_FTYPE_V32QI_V32QI_INT_USI },
33012 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16hi3_mask, "__builtin_ia32_cmpw256_mask", IX86_BUILTIN_CMPW256, UNKNOWN, (int) UHI_FTYPE_V16HI_V16HI_INT_UHI },
33013 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv32qi3_mask, "__builtin_ia32_ucmpb256_mask", IX86_BUILTIN_UCMPB256, UNKNOWN, (int) USI_FTYPE_V32QI_V32QI_INT_USI },
33014 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16hi3_mask, "__builtin_ia32_ucmpw256_mask", IX86_BUILTIN_UCMPW256, UNKNOWN, (int) UHI_FTYPE_V16HI_V16HI_INT_UHI },
33015 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4df3_mask, "__builtin_ia32_cmppd256_mask", IX86_BUILTIN_CMPPD256_MASK, UNKNOWN, (int) QI_FTYPE_V4DF_V4DF_INT_UQI },
33016 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8sf3_mask, "__builtin_ia32_cmpps256_mask", IX86_BUILTIN_CMPPS256_MASK, UNKNOWN, (int) QI_FTYPE_V8SF_V8SF_INT_UQI },
33017 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2di3_mask, "__builtin_ia32_cmpq128_mask", IX86_BUILTIN_CMPQ128, UNKNOWN, (int) UQI_FTYPE_V2DI_V2DI_INT_UQI },
33018 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4si3_mask, "__builtin_ia32_cmpd128_mask", IX86_BUILTIN_CMPD128, UNKNOWN, (int) UQI_FTYPE_V4SI_V4SI_INT_UQI },
33019 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv2di3_mask, "__builtin_ia32_ucmpq128_mask", IX86_BUILTIN_UCMPQ128, UNKNOWN, (int) UQI_FTYPE_V2DI_V2DI_INT_UQI },
33020 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4si3_mask, "__builtin_ia32_ucmpd128_mask", IX86_BUILTIN_UCMPD128, UNKNOWN, (int) UQI_FTYPE_V4SI_V4SI_INT_UQI },
33021 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16qi3_mask, "__builtin_ia32_cmpb128_mask", IX86_BUILTIN_CMPB128, UNKNOWN, (int) UHI_FTYPE_V16QI_V16QI_INT_UHI },
33022 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8hi3_mask, "__builtin_ia32_cmpw128_mask", IX86_BUILTIN_CMPW128, UNKNOWN, (int) UQI_FTYPE_V8HI_V8HI_INT_UQI },
33023 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16qi3_mask, "__builtin_ia32_ucmpb128_mask", IX86_BUILTIN_UCMPB128, UNKNOWN, (int) UHI_FTYPE_V16QI_V16QI_INT_UHI },
33024 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8hi3_mask, "__builtin_ia32_ucmpw128_mask", IX86_BUILTIN_UCMPW128, UNKNOWN, (int) UQI_FTYPE_V8HI_V8HI_INT_UQI },
33025 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2df3_mask, "__builtin_ia32_cmppd128_mask", IX86_BUILTIN_CMPPD128_MASK, UNKNOWN, (int) UQI_FTYPE_V2DF_V2DF_INT_UQI },
33026 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4sf3_mask, "__builtin_ia32_cmpps128_mask", IX86_BUILTIN_CMPPS128_MASK, UNKNOWN, (int) UQI_FTYPE_V4SF_V4SF_INT_UQI },
33028 /* AVX512DQ. */
33029 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x2_512_mask", IX86_BUILTIN_BROADCASTF32x2_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_UHI },
33030 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask, "__builtin_ia32_broadcasti32x2_512_mask", IX86_BUILTIN_BROADCASTI32x2_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_UHI },
33031 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8df_mask_1, "__builtin_ia32_broadcastf64x2_512_mask", IX86_BUILTIN_BROADCASTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_UQI },
33032 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8di_mask_1, "__builtin_ia32_broadcasti64x2_512_mask", IX86_BUILTIN_BROADCASTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_UQI },
33033 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask_1, "__builtin_ia32_broadcastf32x8_512_mask", IX86_BUILTIN_BROADCASTF32X8_512, UNKNOWN, (int) V16SF_FTYPE_V8SF_V16SF_UHI },
33034 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask_1, "__builtin_ia32_broadcasti32x8_512_mask", IX86_BUILTIN_BROADCASTI32X8_512, UNKNOWN, (int) V16SI_FTYPE_V8SI_V16SI_UHI },
33035 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf64x2_mask, "__builtin_ia32_extractf64x2_512_mask", IX86_BUILTIN_EXTRACTF64X2_512, UNKNOWN, (int) V2DF_FTYPE_V8DF_INT_V2DF_UQI },
33036 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf32x8_mask, "__builtin_ia32_extractf32x8_mask", IX86_BUILTIN_EXTRACTF32X8, UNKNOWN, (int) V8SF_FTYPE_V16SF_INT_V8SF_UQI },
33037 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti64x2_mask, "__builtin_ia32_extracti64x2_512_mask", IX86_BUILTIN_EXTRACTI64X2_512, UNKNOWN, (int) V2DI_FTYPE_V8DI_INT_V2DI_UQI },
33038 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti32x8_mask, "__builtin_ia32_extracti32x8_mask", IX86_BUILTIN_EXTRACTI32X8, UNKNOWN, (int) V8SI_FTYPE_V16SI_INT_V8SI_UQI },
33039 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv8df_mask, "__builtin_ia32_reducepd512_mask", IX86_BUILTIN_REDUCEPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_UQI },
33040 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv16sf_mask, "__builtin_ia32_reduceps512_mask", IX86_BUILTIN_REDUCEPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_UHI },
33041 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_mulv8di3_mask, "__builtin_ia32_pmullq512_mask", IX86_BUILTIN_PMULLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
33042 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv8df3_mask, "__builtin_ia32_xorpd512_mask", IX86_BUILTIN_XORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI },
33043 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv16sf3_mask, "__builtin_ia32_xorps512_mask", IX86_BUILTIN_XORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_UHI },
33044 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv8df3_mask, "__builtin_ia32_orpd512_mask", IX86_BUILTIN_ORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI },
33045 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv16sf3_mask, "__builtin_ia32_orps512_mask", IX86_BUILTIN_ORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_UHI },
33046 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv8df3_mask, "__builtin_ia32_andpd512_mask", IX86_BUILTIN_ANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI },
33047 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv16sf3_mask, "__builtin_ia32_andps512_mask", IX86_BUILTIN_ANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_UHI },
33048 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv8df3_mask, "__builtin_ia32_andnpd512_mask", IX86_BUILTIN_ANDNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI},
33049 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv16sf3_mask, "__builtin_ia32_andnps512_mask", IX86_BUILTIN_ANDNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_UHI },
33050 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf32x8_mask, "__builtin_ia32_insertf32x8_mask", IX86_BUILTIN_INSERTF32X8, UNKNOWN, (int) V16SF_FTYPE_V16SF_V8SF_INT_V16SF_UHI },
33051 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti32x8_mask, "__builtin_ia32_inserti32x8_mask", IX86_BUILTIN_INSERTI32X8, UNKNOWN, (int) V16SI_FTYPE_V16SI_V8SI_INT_V16SI_UHI },
33052 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf64x2_mask, "__builtin_ia32_insertf64x2_512_mask", IX86_BUILTIN_INSERTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V2DF_INT_V8DF_UQI },
33053 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti64x2_mask, "__builtin_ia32_inserti64x2_512_mask", IX86_BUILTIN_INSERTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_INT_V8DI_UQI },
33054 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv8df_mask, "__builtin_ia32_fpclasspd512_mask", IX86_BUILTIN_FPCLASSPD512, UNKNOWN, (int) QI_FTYPE_V8DF_INT_UQI },
33055 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv16sf_mask, "__builtin_ia32_fpclassps512_mask", IX86_BUILTIN_FPCLASSPS512, UNKNOWN, (int) HI_FTYPE_V16SF_INT_UHI },
33056 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtd2maskv16si, "__builtin_ia32_cvtd2mask512", IX86_BUILTIN_CVTD2MASK512, UNKNOWN, (int) UHI_FTYPE_V16SI },
33057 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtq2maskv8di, "__builtin_ia32_cvtq2mask512", IX86_BUILTIN_CVTQ2MASK512, UNKNOWN, (int) UQI_FTYPE_V8DI },
33058 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2dv16si, "__builtin_ia32_cvtmask2d512", IX86_BUILTIN_CVTMASK2D512, UNKNOWN, (int) V16SI_FTYPE_UHI },
33059 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2qv8di, "__builtin_ia32_cvtmask2q512", IX86_BUILTIN_CVTMASK2Q512, UNKNOWN, (int) V8DI_FTYPE_UQI },
33061 /* AVX512BW. */
33062 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpcksi, "__builtin_ia32_kunpcksi", IX86_BUILTIN_KUNPCKWD, UNKNOWN, (int) USI_FTYPE_USI_USI },
33063 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpckdi, "__builtin_ia32_kunpckdi", IX86_BUILTIN_KUNPCKDQ, UNKNOWN, (int) UDI_FTYPE_UDI_UDI },
33064 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packusdw_mask, "__builtin_ia32_packusdw512_mask", IX86_BUILTIN_PACKUSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_USI },
33065 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlv4ti3, "__builtin_ia32_pslldq512", IX86_BUILTIN_PSLLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
33066 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrv4ti3, "__builtin_ia32_psrldq512", IX86_BUILTIN_PSRLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
33067 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packssdw_mask, "__builtin_ia32_packssdw512_mask", IX86_BUILTIN_PACKSSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_USI },
33068 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv4ti, "__builtin_ia32_palignr512", IX86_BUILTIN_PALIGNR512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_CONVERT },
33069 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv64qi_mask, "__builtin_ia32_palignr512_mask", IX86_BUILTIN_PALIGNR512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_UDI_CONVERT },
33070 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_movdquhi512_mask", IX86_BUILTIN_MOVDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_USI },
33071 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_movdquqi512_mask", IX86_BUILTIN_MOVDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_UDI },
33072 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_psadbw, "__builtin_ia32_psadbw512", IX86_BUILTIN_PSADBW512, UNKNOWN, (int) V8DI_FTYPE_V64QI_V64QI },
33073 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_dbpsadbwv32hi_mask, "__builtin_ia32_dbpsadbw512_mask", IX86_BUILTIN_DBPSADBW512, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_USI },
33074 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv64qi_mask, "__builtin_ia32_pbroadcastb512_mask", IX86_BUILTIN_PBROADCASTB512, UNKNOWN, (int) V64QI_FTYPE_V16QI_V64QI_UDI },
33075 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv64qi_mask, "__builtin_ia32_pbroadcastb512_gpr_mask", IX86_BUILTIN_PBROADCASTB512_GPR, UNKNOWN, (int) V64QI_FTYPE_QI_V64QI_UDI },
33076 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv32hi_mask, "__builtin_ia32_pbroadcastw512_mask", IX86_BUILTIN_PBROADCASTW512, UNKNOWN, (int) V32HI_FTYPE_V8HI_V32HI_USI },
33077 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv32hi_mask, "__builtin_ia32_pbroadcastw512_gpr_mask", IX86_BUILTIN_PBROADCASTW512_GPR, UNKNOWN, (int) V32HI_FTYPE_HI_V32HI_USI },
33078 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sign_extendv32qiv32hi2_mask, "__builtin_ia32_pmovsxbw512_mask", IX86_BUILTIN_PMOVSXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_USI },
33079 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_zero_extendv32qiv32hi2_mask, "__builtin_ia32_pmovzxbw512_mask", IX86_BUILTIN_PMOVZXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_USI },
33080 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_permvarv32hi_mask, "__builtin_ia32_permvarhi512_mask", IX86_BUILTIN_VPERMVARHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33081 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_mask, "__builtin_ia32_vpermt2varhi512_mask", IX86_BUILTIN_VPERMT2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33082 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_maskz, "__builtin_ia32_vpermt2varhi512_maskz", IX86_BUILTIN_VPERMT2VARHI512_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33083 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermi2varv32hi3_mask, "__builtin_ia32_vpermi2varhi512_mask", IX86_BUILTIN_VPERMI2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33084 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv64qi3_mask, "__builtin_ia32_pavgb512_mask", IX86_BUILTIN_PAVGB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33085 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv32hi3_mask, "__builtin_ia32_pavgw512_mask", IX86_BUILTIN_PAVGW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33086 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv64qi3_mask, "__builtin_ia32_paddb512_mask", IX86_BUILTIN_PADDB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33087 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv64qi3_mask, "__builtin_ia32_psubb512_mask", IX86_BUILTIN_PSUBB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33088 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv64qi3_mask, "__builtin_ia32_psubsb512_mask", IX86_BUILTIN_PSUBSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33089 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv64qi3_mask, "__builtin_ia32_paddsb512_mask", IX86_BUILTIN_PADDSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33090 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv64qi3_mask, "__builtin_ia32_psubusb512_mask", IX86_BUILTIN_PSUBUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33091 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv64qi3_mask, "__builtin_ia32_paddusb512_mask", IX86_BUILTIN_PADDUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33092 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv32hi3_mask, "__builtin_ia32_psubw512_mask", IX86_BUILTIN_PSUBW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33093 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv32hi3_mask, "__builtin_ia32_paddw512_mask", IX86_BUILTIN_PADDW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33094 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv32hi3_mask, "__builtin_ia32_psubsw512_mask", IX86_BUILTIN_PSUBSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33095 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv32hi3_mask, "__builtin_ia32_paddsw512_mask", IX86_BUILTIN_PADDSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33096 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv32hi3_mask, "__builtin_ia32_psubusw512_mask", IX86_BUILTIN_PSUBUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33097 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv32hi3_mask, "__builtin_ia32_paddusw512_mask", IX86_BUILTIN_PADDUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33098 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv32hi3_mask, "__builtin_ia32_pmaxuw512_mask", IX86_BUILTIN_PMAXUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33099 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv32hi3_mask, "__builtin_ia32_pmaxsw512_mask", IX86_BUILTIN_PMAXSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33100 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv32hi3_mask, "__builtin_ia32_pminuw512_mask", IX86_BUILTIN_PMINUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33101 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv32hi3_mask, "__builtin_ia32_pminsw512_mask", IX86_BUILTIN_PMINSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33102 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv64qi3_mask, "__builtin_ia32_pmaxub512_mask", IX86_BUILTIN_PMAXUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33103 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv64qi3_mask, "__builtin_ia32_pmaxsb512_mask", IX86_BUILTIN_PMAXSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33104 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv64qi3_mask, "__builtin_ia32_pminub512_mask", IX86_BUILTIN_PMINUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33105 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv64qi3_mask, "__builtin_ia32_pminsb512_mask", IX86_BUILTIN_PMINSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33106 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovwb512_mask", IX86_BUILTIN_PMOVWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_USI },
33107 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ss_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovswb512_mask", IX86_BUILTIN_PMOVSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_USI },
33108 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_us_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovuswb512_mask", IX86_BUILTIN_PMOVUSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_USI },
33109 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_umulhrswv32hi3_mask, "__builtin_ia32_pmulhrsw512_mask", IX86_BUILTIN_PMULHRSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33110 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umulv32hi3_highpart_mask, "__builtin_ia32_pmulhuw512_mask" , IX86_BUILTIN_PMULHUW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33111 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smulv32hi3_highpart_mask, "__builtin_ia32_pmulhw512_mask" , IX86_BUILTIN_PMULHW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33112 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_mulv32hi3_mask, "__builtin_ia32_pmullw512_mask", IX86_BUILTIN_PMULLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33113 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllwi512_mask", IX86_BUILTIN_PSLLWI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_USI },
33114 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllw512_mask", IX86_BUILTIN_PSLLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_USI },
33115 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packsswb_mask, "__builtin_ia32_packsswb512_mask", IX86_BUILTIN_PACKSSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_UDI },
33116 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packuswb_mask, "__builtin_ia32_packuswb512_mask", IX86_BUILTIN_PACKUSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_UDI },
33117 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashrvv32hi_mask, "__builtin_ia32_psrav32hi_mask", IX86_BUILTIN_PSRAVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33118 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddubsw512v32hi_mask, "__builtin_ia32_pmaddubsw512_mask", IX86_BUILTIN_PMADDUBSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_V32HI_USI },
33119 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddwd512v32hi_mask, "__builtin_ia32_pmaddwd512_mask", IX86_BUILTIN_PMADDWD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V32HI_V32HI_V16SI_UHI },
33120 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrvv32hi_mask, "__builtin_ia32_psrlv32hi_mask", IX86_BUILTIN_PSRLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33121 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv64qi_mask, "__builtin_ia32_punpckhbw512_mask", IX86_BUILTIN_PUNPCKHBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33122 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv32hi_mask, "__builtin_ia32_punpckhwd512_mask", IX86_BUILTIN_PUNPCKHWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33123 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv64qi_mask, "__builtin_ia32_punpcklbw512_mask", IX86_BUILTIN_PUNPCKLBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33124 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv32hi_mask, "__builtin_ia32_punpcklwd512_mask", IX86_BUILTIN_PUNPCKLWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33125 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufbv64qi3_mask, "__builtin_ia32_pshufb512_mask", IX86_BUILTIN_PSHUFB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33126 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufhwv32hi_mask, "__builtin_ia32_pshufhw512_mask", IX86_BUILTIN_PSHUFHW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_USI },
33127 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshuflwv32hi_mask, "__builtin_ia32_pshuflw512_mask", IX86_BUILTIN_PSHUFLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_USI },
33128 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psrawi512_mask", IX86_BUILTIN_PSRAWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_USI },
33129 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psraw512_mask", IX86_BUILTIN_PSRAW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_USI },
33130 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlwi512_mask", IX86_BUILTIN_PSRLWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_USI },
33131 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlw512_mask", IX86_BUILTIN_PSRLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_USI },
33132 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtb2maskv64qi, "__builtin_ia32_cvtb2mask512", IX86_BUILTIN_CVTB2MASK512, UNKNOWN, (int) UDI_FTYPE_V64QI },
33133 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtw2maskv32hi, "__builtin_ia32_cvtw2mask512", IX86_BUILTIN_CVTW2MASK512, UNKNOWN, (int) USI_FTYPE_V32HI },
33134 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2bv64qi, "__builtin_ia32_cvtmask2b512", IX86_BUILTIN_CVTMASK2B512, UNKNOWN, (int) V64QI_FTYPE_UDI },
33135 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2wv32hi, "__builtin_ia32_cvtmask2w512", IX86_BUILTIN_CVTMASK2W512, UNKNOWN, (int) V32HI_FTYPE_USI },
33136 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv64qi3_mask, "__builtin_ia32_pcmpeqb512_mask", IX86_BUILTIN_PCMPEQB512_MASK, UNKNOWN, (int) UDI_FTYPE_V64QI_V64QI_UDI },
33137 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv32hi3_mask, "__builtin_ia32_pcmpeqw512_mask", IX86_BUILTIN_PCMPEQW512_MASK, UNKNOWN, (int) USI_FTYPE_V32HI_V32HI_USI },
33138 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv64qi3_mask, "__builtin_ia32_pcmpgtb512_mask", IX86_BUILTIN_PCMPGTB512_MASK, UNKNOWN, (int) UDI_FTYPE_V64QI_V64QI_UDI },
33139 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv32hi3_mask, "__builtin_ia32_pcmpgtw512_mask", IX86_BUILTIN_PCMPGTW512_MASK, UNKNOWN, (int) USI_FTYPE_V32HI_V32HI_USI },
33140 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv64qi3_mask, "__builtin_ia32_ptestmb512", IX86_BUILTIN_PTESTMB512, UNKNOWN, (int) UDI_FTYPE_V64QI_V64QI_UDI },
33141 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv32hi3_mask, "__builtin_ia32_ptestmw512", IX86_BUILTIN_PTESTMW512, UNKNOWN, (int) USI_FTYPE_V32HI_V32HI_USI },
33142 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv64qi3_mask, "__builtin_ia32_ptestnmb512", IX86_BUILTIN_PTESTNMB512, UNKNOWN, (int) UDI_FTYPE_V64QI_V64QI_UDI },
33143 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv32hi3_mask, "__builtin_ia32_ptestnmw512", IX86_BUILTIN_PTESTNMW512, UNKNOWN, (int) USI_FTYPE_V32HI_V32HI_USI },
33144 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlvv32hi_mask, "__builtin_ia32_psllv32hi_mask", IX86_BUILTIN_PSLLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_USI },
33145 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv64qi2_mask, "__builtin_ia32_pabsb512_mask", IX86_BUILTIN_PABSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_UDI },
33146 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv32hi2_mask, "__builtin_ia32_pabsw512_mask", IX86_BUILTIN_PABSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_USI },
33147 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv32hi, "__builtin_ia32_blendmw_512_mask", IX86_BUILTIN_BLENDMW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_USI },
33148 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv64qi, "__builtin_ia32_blendmb_512_mask", IX86_BUILTIN_BLENDMB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_UDI },
33149 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv64qi3_mask, "__builtin_ia32_cmpb512_mask", IX86_BUILTIN_CMPB512, UNKNOWN, (int) UDI_FTYPE_V64QI_V64QI_INT_UDI },
33150 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) USI_FTYPE_V32HI_V32HI_INT_USI },
33151 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) UDI_FTYPE_V64QI_V64QI_INT_UDI },
33152 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) USI_FTYPE_V32HI_V32HI_INT_USI },
33154 /* AVX512IFMA */
33155 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_mask, "__builtin_ia32_vpmadd52luq512_mask", IX86_BUILTIN_VPMADD52LUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
33156 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_maskz, "__builtin_ia32_vpmadd52luq512_maskz", IX86_BUILTIN_VPMADD52LUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
33157 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_mask, "__builtin_ia32_vpmadd52huq512_mask", IX86_BUILTIN_VPMADD52HUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
33158 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_maskz, "__builtin_ia32_vpmadd52huq512_maskz", IX86_BUILTIN_VPMADD52HUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_UQI },
33159 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_mask, "__builtin_ia32_vpmadd52luq256_mask", IX86_BUILTIN_VPMADD52LUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
33160 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_maskz, "__builtin_ia32_vpmadd52luq256_maskz", IX86_BUILTIN_VPMADD52LUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
33161 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_mask, "__builtin_ia32_vpmadd52huq256_mask", IX86_BUILTIN_VPMADD52HUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
33162 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_maskz, "__builtin_ia32_vpmadd52huq256_maskz", IX86_BUILTIN_VPMADD52HUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_UQI },
33163 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_mask, "__builtin_ia32_vpmadd52luq128_mask", IX86_BUILTIN_VPMADD52LUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
33164 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_maskz, "__builtin_ia32_vpmadd52luq128_maskz", IX86_BUILTIN_VPMADD52LUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
33165 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_mask, "__builtin_ia32_vpmadd52huq128_mask", IX86_BUILTIN_VPMADD52HUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
33166 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_maskz, "__builtin_ia32_vpmadd52huq128_maskz", IX86_BUILTIN_VPMADD52HUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_UQI },
33168 /* AVX512VBMI */
33169 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_vpmultishiftqbv64qi_mask, "__builtin_ia32_vpmultishiftqb512_mask", IX86_BUILTIN_VPMULTISHIFTQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33170 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv32qi_mask, "__builtin_ia32_vpmultishiftqb256_mask", IX86_BUILTIN_VPMULTISHIFTQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
33171 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv16qi_mask, "__builtin_ia32_vpmultishiftqb128_mask", IX86_BUILTIN_VPMULTISHIFTQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
33172 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_permvarv64qi_mask, "__builtin_ia32_permvarqi512_mask", IX86_BUILTIN_VPERMVARQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33173 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_mask, "__builtin_ia32_vpermt2varqi512_mask", IX86_BUILTIN_VPERMT2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33174 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_maskz, "__builtin_ia32_vpermt2varqi512_maskz", IX86_BUILTIN_VPERMT2VARQI512_MASKZ, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33175 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermi2varv64qi3_mask, "__builtin_ia32_vpermi2varqi512_mask", IX86_BUILTIN_VPERMI2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_UDI },
33176 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv32qi_mask, "__builtin_ia32_permvarqi256_mask", IX86_BUILTIN_VPERMVARQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
33177 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16qi_mask, "__builtin_ia32_permvarqi128_mask", IX86_BUILTIN_VPERMVARQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
33178 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_mask, "__builtin_ia32_vpermt2varqi256_mask", IX86_BUILTIN_VPERMT2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
33179 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_maskz, "__builtin_ia32_vpermt2varqi256_maskz", IX86_BUILTIN_VPERMT2VARQI256_MASKZ, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
33180 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_mask, "__builtin_ia32_vpermt2varqi128_mask", IX86_BUILTIN_VPERMT2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
33181 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_maskz, "__builtin_ia32_vpermt2varqi128_maskz", IX86_BUILTIN_VPERMT2VARQI128_MASKZ, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
33182 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv32qi3_mask, "__builtin_ia32_vpermi2varqi256_mask", IX86_BUILTIN_VPERMI2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_USI },
33183 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16qi3_mask, "__builtin_ia32_vpermi2varqi128_mask", IX86_BUILTIN_VPERMI2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_UHI },
33184 };
33186 /* Builtins with rounding support. */
33188 {
33189 /* AVX512F */
33190 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33191 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33192 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33193 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33194 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) UQI_FTYPE_V8DF_V8DF_INT_UQI_INT },
33195 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) UHI_FTYPE_V16SF_V16SF_INT_UHI_INT },
33196 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) UQI_FTYPE_V2DF_V2DF_INT_UQI_INT },
33197 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) UQI_FTYPE_V4SF_V4SF_INT_UQI_INT },
33198 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
33199 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
33200 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
33201 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33202 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
33203 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33204 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
33205 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33206 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
33207 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33208 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
33209 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
33210 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
33211 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
33212 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
33213 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33214 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33215 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33216 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33217 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
33218 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
33219 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
33220 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
33221 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33222 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33223 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33224 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33225 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
33226 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
33227 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
33228 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
33229 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
33230 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
33231 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
33232 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
33233 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33234 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33235 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33236 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33237 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
33238 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
33239 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33240 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33241 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33242 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33243 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33244 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33245 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33246 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33247 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33248 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33249 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33250 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33251 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33252 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33253 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
33254 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
33255 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33256 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33257 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33258 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33259 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33260 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33261 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33262 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33263 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33264 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33265 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33266 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33267 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33268 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33269 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
33270 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33271 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33272 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33273 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33274 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33275 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33276 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33277 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
33278 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33279 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33280 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33281 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33282 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33283 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33284 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33285 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33286 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33287 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33288 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33289 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33290 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33291 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
33292 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
33293 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33294 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33295 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33296 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33297 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33298 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33299 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33300 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33301 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33302 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33303 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33304 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33305 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33306 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_UQI_INT },
33307 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33308 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33310 /* AVX512ER */
33311 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33312 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33313 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33314 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33315 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33316 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33317 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33318 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33319 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33320 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33322 /* AVX512DQ. */
33323 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv2df_round, "__builtin_ia32_rangesd128_round", IX86_BUILTIN_RANGESD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33324 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv4sf_round, "__builtin_ia32_rangess128_round", IX86_BUILTIN_RANGESS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33325 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2qq512_mask", IX86_BUILTIN_CVTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33326 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__builtin_ia32_cvtps2qq512_mask", IX86_BUILTIN_CVTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33327 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33328 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33329 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33330 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33331 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33332 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33333 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33334 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33335 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33336 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33337 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT },
33338 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT },
33339 };
33341 /* Bultins for MPX. */
33343 {
33344 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndstx", IX86_BUILTIN_BNDSTX, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND_PCVOID },
33345 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcl", IX86_BUILTIN_BNDCL, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33346 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcu", IX86_BUILTIN_BNDCU, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33347 };
33349 /* Const builtins for MPX. */
33351 {
33352 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndmk", IX86_BUILTIN_BNDMK, UNKNOWN, (int) BND_FTYPE_PCVOID_ULONG },
33353 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndldx", IX86_BUILTIN_BNDLDX, UNKNOWN, (int) BND_FTYPE_PCVOID_PCVOID },
33354 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_narrow_bounds", IX86_BUILTIN_BNDNARROW, UNKNOWN, (int) PVOID_FTYPE_PCVOID_BND_ULONG },
33355 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndint", IX86_BUILTIN_BNDINT, UNKNOWN, (int) BND_FTYPE_BND_BND },
33356 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_sizeof", IX86_BUILTIN_SIZEOF, UNKNOWN, (int) ULONG_FTYPE_VOID },
33357 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndlower", IX86_BUILTIN_BNDLOWER, UNKNOWN, (int) PVOID_FTYPE_BND },
33358 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndupper", IX86_BUILTIN_BNDUPPER, UNKNOWN, (int) PVOID_FTYPE_BND },
33359 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndret", IX86_BUILTIN_BNDRET, UNKNOWN, (int) BND_FTYPE_PCVOID },
33360 };
33362 /* FMA4 and XOP. */
33363 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
33364 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
33365 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
33366 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
33367 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
33368 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
33369 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
33370 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
33371 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
33372 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
33373 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
33374 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
33375 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
33376 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
33377 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
33378 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
33379 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
33380 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
33381 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
33382 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
33383 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
33384 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
33385 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
33386 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
33387 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
33388 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
33389 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
33390 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
33391 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
33392 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
33393 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
33394 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
33395 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
33396 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
33397 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
33398 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
33399 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
33400 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
33401 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
33402 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
33403 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
33404 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
33405 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
33406 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
33407 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
33408 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
33409 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
33410 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
33411 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
33412 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
33413 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
33414 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
33417 {
33458 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
33459 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
33460 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
33461 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
33462 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
33463 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
33464 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
33466 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33467 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33468 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
33469 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
33470 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
33471 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
33472 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
33474 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
33476 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33477 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33478 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33479 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33480 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33481 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33482 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33483 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33484 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33485 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33486 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33487 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33489 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33490 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
33491 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
33492 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
33493 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
33494 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
33495 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
33496 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
33497 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33498 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
33499 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
33500 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
33501 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33502 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
33503 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
33504 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
33506 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
33507 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
33508 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
33509 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
33510 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
33511 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
33513 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33514 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33515 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33516 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33517 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33518 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33519 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33520 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33521 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33522 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33523 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33524 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33525 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33526 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33527 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33529 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
33530 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33531 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33532 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
33533 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
33534 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
33535 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
33537 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
33538 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33539 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33540 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
33541 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
33542 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
33543 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
33545 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
33546 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33547 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33548 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
33549 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
33550 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
33551 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
33553 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33554 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33555 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33556 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
33557 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
33558 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
33559 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
33561 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
33562 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33563 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33564 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
33565 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
33566 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
33567 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
33569 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
33570 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33571 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33572 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
33573 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
33574 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
33575 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
33577 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
33578 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33579 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33580 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
33581 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
33582 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
33583 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
33585 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33586 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33587 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33588 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
33589 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
33590 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
33591 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
33593 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33594 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33595 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33596 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33597 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33598 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33599 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33600 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33602 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33603 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33604 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33605 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33606 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33607 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33608 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33609 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33611 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
33612 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
33613 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
33614 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
33616 };
33617 \f
33618 /* TM vector builtins. */
33620 /* Reuse the existing x86-specific `struct builtin_description' cause
33621 we're lazy. Add casts to make them fit. */
33623 {
33624 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33625 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33626 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33627 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33628 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33629 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33630 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33632 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33633 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33634 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33635 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33636 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33637 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33638 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33640 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33641 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33642 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33643 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33644 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33645 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33646 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33648 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
33649 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
33650 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
33651 };
33653 /* TM callbacks. */
33655 /* Return the builtin decl needed to load a vector of TYPE. */
33657 static tree
33659 {
33661 {
33663 {
33670 }
33671 }
33673 }
33675 /* Return the builtin decl needed to store a vector of TYPE. */
33677 static tree
33679 {
33681 {
33683 {
33690 }
33691 }
33693 }
33694 \f
33695 /* Initialize the transactional memory vector load/store builtins. */
33697 static void
33699 {
33703 tree decl;
33710 /* If there are no builtins defined, we must be compiling in a
33711 language without trans-mem support. */
33715 /* Use whatever attributes a normal TM load has. */
33719 /* Use whatever attributes a normal TM store has. */
33723 /* Use whatever attributes a normal TM log has. */
33731 {
33735 {
33743 {
33746 }
33748 {
33751 }
33752 else
33753 {
33756 }
33758 /* The builtin without the prefix for
33759 calling it directly. */
33761 attrs);
33762 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
33763 set the TYPE_ATTRIBUTES. */
33767 }
33768 }
33769 }
33771 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
33772 in the current target ISA to allow the user to compile particular modules
33773 with different target specific options that differ from the command line
33774 options. */
33775 static void
33777 {
33782 /* Add all special builtins with variable number of operands. */
33786 {
33792 }
33794 /* Add all builtins with variable number of operands. */
33798 {
33804 }
33806 /* Add all builtins with rounding. */
33810 {
33816 }
33818 /* pcmpestr[im] insns. */
33822 {
33825 else
33828 }
33830 /* pcmpistr[im] insns. */
33834 {
33837 else
33840 }
33842 /* comi/ucomi insns. */
33844 {
33847 else
33850 }
33852 /* SSE */
33858 /* SSE or 3DNow!A */
33861 IX86_BUILTIN_MASKMOVQ);
33863 /* SSE2 */
33872 /* SSE3. */
33878 /* AES */
33892 /* PCLMUL */
33896 /* RDRND */
33903 IX86_BUILTIN_RDRAND64_STEP);
33905 /* AVX2 */
33907 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
33908 IX86_BUILTIN_GATHERSIV2DF);
33911 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
33912 IX86_BUILTIN_GATHERSIV4DF);
33915 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
33916 IX86_BUILTIN_GATHERDIV2DF);
33919 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
33920 IX86_BUILTIN_GATHERDIV4DF);
33923 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
33924 IX86_BUILTIN_GATHERSIV4SF);
33927 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
33928 IX86_BUILTIN_GATHERSIV8SF);
33931 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
33932 IX86_BUILTIN_GATHERDIV4SF);
33935 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
33936 IX86_BUILTIN_GATHERDIV8SF);
33939 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
33940 IX86_BUILTIN_GATHERSIV2DI);
33943 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
33944 IX86_BUILTIN_GATHERSIV4DI);
33947 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
33948 IX86_BUILTIN_GATHERDIV2DI);
33951 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
33952 IX86_BUILTIN_GATHERDIV4DI);
33955 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
33956 IX86_BUILTIN_GATHERSIV4SI);
33959 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
33960 IX86_BUILTIN_GATHERSIV8SI);
33963 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
33964 IX86_BUILTIN_GATHERDIV4SI);
33967 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
33968 IX86_BUILTIN_GATHERDIV8SI);
33971 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
33972 IX86_BUILTIN_GATHERALTSIV4DF);
33975 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
33976 IX86_BUILTIN_GATHERALTDIV8SF);
33979 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
33980 IX86_BUILTIN_GATHERALTSIV4DI);
33983 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
33984 IX86_BUILTIN_GATHERALTDIV8SI);
33986 /* AVX512F */
33988 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
33989 IX86_BUILTIN_GATHER3SIV16SF);
33992 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
33993 IX86_BUILTIN_GATHER3SIV8DF);
33996 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
33997 IX86_BUILTIN_GATHER3DIV16SF);
34000 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
34001 IX86_BUILTIN_GATHER3DIV8DF);
34004 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
34005 IX86_BUILTIN_GATHER3SIV16SI);
34008 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
34009 IX86_BUILTIN_GATHER3SIV8DI);
34012 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
34013 IX86_BUILTIN_GATHER3DIV16SI);
34016 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
34017 IX86_BUILTIN_GATHER3DIV8DI);
34020 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
34021 IX86_BUILTIN_GATHER3ALTSIV8DF);
34024 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
34025 IX86_BUILTIN_GATHER3ALTDIV16SF);
34028 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
34029 IX86_BUILTIN_GATHER3ALTSIV8DI);
34032 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
34033 IX86_BUILTIN_GATHER3ALTDIV16SI);
34036 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
34037 IX86_BUILTIN_SCATTERSIV16SF);
34040 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
34041 IX86_BUILTIN_SCATTERSIV8DF);
34044 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
34045 IX86_BUILTIN_SCATTERDIV16SF);
34048 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
34049 IX86_BUILTIN_SCATTERDIV8DF);
34052 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
34053 IX86_BUILTIN_SCATTERSIV16SI);
34056 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
34057 IX86_BUILTIN_SCATTERSIV8DI);
34060 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
34061 IX86_BUILTIN_SCATTERDIV16SI);
34064 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
34065 IX86_BUILTIN_SCATTERDIV8DI);
34067 /* AVX512VL */
34069 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_QI_INT,
34070 IX86_BUILTIN_GATHER3SIV2DF);
34073 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_QI_INT,
34074 IX86_BUILTIN_GATHER3SIV4DF);
34077 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_QI_INT,
34078 IX86_BUILTIN_GATHER3DIV2DF);
34081 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_QI_INT,
34082 IX86_BUILTIN_GATHER3DIV4DF);
34085 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_QI_INT,
34086 IX86_BUILTIN_GATHER3SIV4SF);
34089 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_QI_INT,
34090 IX86_BUILTIN_GATHER3SIV8SF);
34093 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_QI_INT,
34094 IX86_BUILTIN_GATHER3DIV4SF);
34097 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_QI_INT,
34098 IX86_BUILTIN_GATHER3DIV8SF);
34101 V2DI_FTYPE_V2DI_PCINT64_V4SI_QI_INT,
34102 IX86_BUILTIN_GATHER3SIV2DI);
34105 V4DI_FTYPE_V4DI_PCINT64_V4SI_QI_INT,
34106 IX86_BUILTIN_GATHER3SIV4DI);
34109 V2DI_FTYPE_V2DI_PCINT64_V2DI_QI_INT,
34110 IX86_BUILTIN_GATHER3DIV2DI);
34113 V4DI_FTYPE_V4DI_PCINT64_V4DI_QI_INT,
34114 IX86_BUILTIN_GATHER3DIV4DI);
34117 V4SI_FTYPE_V4SI_PCINT_V4SI_QI_INT,
34118 IX86_BUILTIN_GATHER3SIV4SI);
34121 V8SI_FTYPE_V8SI_PCINT_V8SI_QI_INT,
34122 IX86_BUILTIN_GATHER3SIV8SI);
34125 V4SI_FTYPE_V4SI_PCINT_V2DI_QI_INT,
34126 IX86_BUILTIN_GATHER3DIV4SI);
34129 V4SI_FTYPE_V4SI_PCINT_V4DI_QI_INT,
34130 IX86_BUILTIN_GATHER3DIV8SI);
34133 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
34134 IX86_BUILTIN_GATHER3ALTSIV4DF);
34137 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
34138 IX86_BUILTIN_GATHER3ALTDIV8SF);
34141 V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
34142 IX86_BUILTIN_GATHER3ALTSIV4DI);
34145 V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
34146 IX86_BUILTIN_GATHER3ALTDIV8SI);
34149 VOID_FTYPE_PFLOAT_QI_V8SI_V8SF_INT,
34150 IX86_BUILTIN_SCATTERSIV8SF);
34153 VOID_FTYPE_PFLOAT_QI_V4SI_V4SF_INT,
34154 IX86_BUILTIN_SCATTERSIV4SF);
34157 VOID_FTYPE_PDOUBLE_QI_V4SI_V4DF_INT,
34158 IX86_BUILTIN_SCATTERSIV4DF);
34161 VOID_FTYPE_PDOUBLE_QI_V4SI_V2DF_INT,
34162 IX86_BUILTIN_SCATTERSIV2DF);
34165 VOID_FTYPE_PFLOAT_QI_V4DI_V4SF_INT,
34166 IX86_BUILTIN_SCATTERDIV8SF);
34169 VOID_FTYPE_PFLOAT_QI_V2DI_V4SF_INT,
34170 IX86_BUILTIN_SCATTERDIV4SF);
34173 VOID_FTYPE_PDOUBLE_QI_V4DI_V4DF_INT,
34174 IX86_BUILTIN_SCATTERDIV4DF);
34177 VOID_FTYPE_PDOUBLE_QI_V2DI_V2DF_INT,
34178 IX86_BUILTIN_SCATTERDIV2DF);
34181 VOID_FTYPE_PINT_QI_V8SI_V8SI_INT,
34182 IX86_BUILTIN_SCATTERSIV8SI);
34185 VOID_FTYPE_PINT_QI_V4SI_V4SI_INT,
34186 IX86_BUILTIN_SCATTERSIV4SI);
34189 VOID_FTYPE_PLONGLONG_QI_V4SI_V4DI_INT,
34190 IX86_BUILTIN_SCATTERSIV4DI);
34193 VOID_FTYPE_PLONGLONG_QI_V4SI_V2DI_INT,
34194 IX86_BUILTIN_SCATTERSIV2DI);
34197 VOID_FTYPE_PINT_QI_V4DI_V4SI_INT,
34198 IX86_BUILTIN_SCATTERDIV8SI);
34201 VOID_FTYPE_PINT_QI_V2DI_V4SI_INT,
34202 IX86_BUILTIN_SCATTERDIV4SI);
34205 VOID_FTYPE_PLONGLONG_QI_V4DI_V4DI_INT,
34206 IX86_BUILTIN_SCATTERDIV4DI);
34209 VOID_FTYPE_PLONGLONG_QI_V2DI_V2DI_INT,
34210 IX86_BUILTIN_SCATTERDIV2DI);
34212 VOID_FTYPE_PDOUBLE_QI_V16SI_V8DF_INT,
34213 IX86_BUILTIN_SCATTERALTSIV8DF);
34216 VOID_FTYPE_PFLOAT_HI_V8DI_V16SF_INT,
34217 IX86_BUILTIN_SCATTERALTDIV16SF);
34220 VOID_FTYPE_PLONGLONG_QI_V16SI_V8DI_INT,
34221 IX86_BUILTIN_SCATTERALTSIV8DI);
34224 VOID_FTYPE_PINT_HI_V8DI_V16SI_INT,
34225 IX86_BUILTIN_SCATTERALTDIV16SI);
34227 /* AVX512PF */
34229 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
34230 IX86_BUILTIN_GATHERPFDPD);
34232 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
34233 IX86_BUILTIN_GATHERPFDPS);
34235 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
34236 IX86_BUILTIN_GATHERPFQPD);
34238 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
34239 IX86_BUILTIN_GATHERPFQPS);
34241 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
34242 IX86_BUILTIN_SCATTERPFDPD);
34244 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
34245 IX86_BUILTIN_SCATTERPFDPS);
34247 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
34248 IX86_BUILTIN_SCATTERPFQPD);
34250 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
34251 IX86_BUILTIN_SCATTERPFQPS);
34253 /* SHA */
34269 /* RTM. */
34273 /* MMX access to the vec_init patterns. */
34278 V4HI_FTYPE_HI_HI_HI_HI,
34279 IX86_BUILTIN_VEC_INIT_V4HI);
34282 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
34283 IX86_BUILTIN_VEC_INIT_V8QI);
34285 /* Access to the vec_extract patterns. */
34307 /* Access to the vec_set patterns. */
34328 /* RDSEED */
34337 /* ADCX */
34342 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34343 IX86_BUILTIN_ADDCARRYX64);
34345 /* SBB */
34350 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34351 IX86_BUILTIN_SBB64);
34353 /* Read/write FLAGS. */
34363 /* CLFLUSHOPT. */
34367 /* CLWB. */
34371 /* MONITORX and MWAITX. */
34377 /* Add FMA4 multi-arg argument instructions */
34379 {
34385 }
34386 }
34388 static void
34390 {
34393 tree decl;
34399 {
34406 /* With no leaf and nothrow flags for MPX builtins
34407 abnormal edges may follow its call when setjmp
34408 presents in the function. Since we may have a lot
34409 of MPX builtins calls it causes lots of useless
34410 edges and enormous PHI nodes. To avoid this we mark
34411 MPX builtins as leaf and nothrow. */
34413 {
34415 NULL_TREE);
34417 }
34418 else
34419 {
34422 }
34423 }
34428 {
34436 {
34438 NULL_TREE);
34440 }
34441 else
34442 {
34445 }
34446 }
34447 }
34449 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
34450 to return a pointer to VERSION_DECL if the outcome of the expression
34451 formed by PREDICATE_CHAIN is true. This function will be called during
34452 version dispatch to decide which function version to execute. It returns
34453 the basic block at the end, to which more conditions can be added. */
34455 static basic_block
34458 {
34459 gimple return_stmt;
34461 gimple convert_stmt;
34462 gimple call_cond_stmt;
34463 gimple if_else_stmt;
34469 gimple_seq gseq;
34486 {
34494 }
34497 {
34512 else
34513 {
34514 gimple assign_stmt;
34515 /* Use MIN_EXPR to check if any integer is zero?.
34516 and_expr_var = min_expr <cond_var, and_expr_var> */
34524 }
34525 }
34528 integer_zero_node,
34558 }
34560 /* This parses the attribute arguments to target in DECL and determines
34561 the right builtin to use to match the platform specification.
34562 It returns the priority value for this version decl. If PREDICATE_LIST
34563 is not NULL, it stores the list of cpu features that need to be checked
34564 before dispatching this function. */
34566 static unsigned int
34568 {
34569 tree attrs;
34571 tree target_node;
34578 /* Priority of i386 features, greater value is higher priority. This is
34579 used to decide the order in which function dispatch must happen. For
34580 instance, a version specialized for SSE4.2 should be checked for dispatch
34581 before a version for SSE3, as SSE4.2 implies SSE3. */
34582 enum feature_priority
34583 {
34585 P_MMX,
34586 P_SSE,
34587 P_SSE2,
34588 P_SSE3,
34589 P_SSSE3,
34590 P_PROC_SSSE3,
34591 P_SSE4_A,
34592 P_PROC_SSE4_A,
34593 P_SSE4_1,
34594 P_SSE4_2,
34595 P_PROC_SSE4_2,
34596 P_POPCNT,
34597 P_AES,
34598 P_PCLMUL,
34599 P_AVX,
34600 P_PROC_AVX,
34601 P_BMI,
34602 P_PROC_BMI,
34603 P_FMA4,
34604 P_XOP,
34605 P_PROC_XOP,
34606 P_FMA,
34607 P_PROC_FMA,
34608 P_BMI2,
34609 P_AVX2,
34610 P_PROC_AVX2,
34611 P_AVX512F,
34612 P_PROC_AVX512F
34613 };
34617 /* These are the target attribute strings for which a dispatcher is
34618 available, from fold_builtin_cpu. */
34620 static struct _feature_list
34621 {
34624 }
34626 {
34646 };
34649 static unsigned int NUM_FEATURES
34665 /* Return priority zero for default function. */
34669 /* Handle arch= if specified. For priority, set it to be 1 more than
34670 the best instruction set the processor can handle. For instance, if
34671 there is a version for atom and a version for ssse3 (the highest ISA
34672 priority for atom), the atom version must be checked for dispatch
34673 before the ssse3 version. */
34675 {
34685 {
34687 {
34695 else
34696 /* We translate "arch=corei7" and "arch=nehalem" to
34697 "corei7" so that it will be mapped to M_INTEL_COREI7
34698 as cpu type to cover all M_INTEL_COREI7_XXXs. */
34705 else
34712 else
34756 }
34757 }
34762 {
34766 }
34769 {
34771 /* For a C string literal the length includes the trailing NULL. */
34774 predicate_chain);
34775 }
34776 }
34778 /* Process feature name. */
34785 {
34786 /* Do not process "arch=" */
34788 {
34791 }
34793 {
34795 {
34797 {
34802 predicate_chain);
34803 }
34804 /* Find the maximum priority feature. */
34809 }
34810 }
34812 {
34816 }
34818 }
34822 {
34825 attrs_str);
34827 }
34829 {
34832 }
34835 }
34837 /* This compares the priority of target features in function DECL1
34838 and DECL2. It returns positive value if DECL1 is higher priority,
34839 negative value if DECL2 is higher priority and 0 if they are the
34840 same. */
34842 static int
34844 {
34849 }
34851 /* V1 and V2 point to function versions with different priorities
34852 based on the target ISA. This function compares their priorities. */
34854 static int
34856 {
34858 {
34859 tree version_decl;
34860 tree predicate_chain;
34867 }
34869 /* This function generates the dispatch function for
34870 multi-versioned functions. DISPATCH_DECL is the function which will
34871 contain the dispatch logic. FNDECLS are the function choices for
34872 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
34873 in DISPATCH_DECL in which the dispatch code is generated. */
34875 static int
34879 {
34880 tree default_decl;
34881 gimple ifunc_cpu_init_stmt;
34882 gimple_seq gseq;
34884 tree ele;
34890 struct _function_version_info
34891 {
34892 tree version_decl;
34893 tree predicate_chain;
34901 /*fndecls_p is actually a vector. */
34904 /* At least one more version other than the default. */
34911 /* The first version in the vector is the default decl. */
34917 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
34918 constructors, so explicity call __builtin_cpu_init here. */
34929 {
34933 /* Get attribute string, parse it and find the right predicate decl.
34934 The predicate function could be a lengthy combination of many
34935 features, like arch-type and various isa-variants. */
34946 actual_versions++;
34947 }
34949 /* Sort the versions according to descending order of dispatch priority. The
34950 priority is based on the ISA. This is not a perfect solution. There
34951 could still be ambiguity. If more than one function version is suitable
34952 to execute, which one should be dispatched? In future, allow the user
34953 to specify a dispatch priority next to the version. */
34963 /* dispatch default version at the end. */
34969 }
34971 /* Comparator function to be used in qsort routine to sort attribute
34972 specification strings to "target". */
34974 static int
34976 {
34980 }
34982 /* ARGLIST is the argument to target attribute. This function tokenizes
34983 the comma separated arguments, sorts them and returns a string which
34984 is a unique identifier for the comma separated arguments. It also
34985 replaces non-identifier characters "=,-" with "_". */
34989 {
34990 tree arg;
34999 {
35004 argnum++;
35007 argnum++;
35008 }
35013 {
35019 }
35021 /* Replace "=,-" with "_". */
35034 {
35036 i++;
35038 }
35045 {
35050 }
35055 }
35057 /* This function changes the assembler name for functions that are
35058 versions. If DECL is a function version and has a "target"
35059 attribute, it appends the attribute string to its assembler name. */
35061 static tree
35063 {
35064 tree version_attr;
35072 "Function versions cannot be marked as gnu_inline,"
35081 /* target attribute string cannot be NULL. */
35085 version_string
35096 /* Allow assembler name to be modified if already set. */
35104 }
35106 /* This function returns true if FN1 and FN2 are versions of the same function,
35107 that is, the target strings of the function decls are different. This assumes
35108 that FN1 and FN2 have the same signature. */
35110 static bool
35112 {
35124 /* At least one function decl should have the target attribute specified. */
35128 /* Diagnose missing target attribute if one of the decls is already
35129 multi-versioned. */
35131 {
35133 {
35135 {
35138 }
35141 fn2);
35144 /* Prevent diagnosing of the same error multiple times. */
35149 }
35151 }
35156 /* The sorted target strings must be different for fn1 and fn2
35157 to be versions. */
35160 else
35167 }
35169 static tree
35171 {
35172 /* For function version, add the target suffix to the assembler name. */
35176 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
35178 #endif
35181 }
35183 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
35184 is true, append the full path name of the source file. */
35188 {
35196 /* Get a unique name that can be used globally without any chances
35197 of collision at link time. */
35207 /* Use '.' to concatenate names as it is demangler friendly. */
35210 suffix);
35211 else
35215 }
35217 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
35219 /* Make a dispatcher declaration for the multi-versioned function DECL.
35220 Calls to DECL function will be replaced with calls to the dispatcher
35221 by the front-end. Return the decl created. */
35223 static tree
35225 {
35226 tree func_decl;
35246 /* Mark this func as external, the resolver will flip it again if
35247 it gets generated. */
35249 /* This will be of type IFUNCs have to be externally visible. */
35253 }
35255 #endif
35257 /* Returns true if decl is multi-versioned and DECL is the default function,
35258 that is it is not tagged with target specific optimization. */
35260 static bool
35262 {
35271 }
35273 /* Make a dispatcher declaration for the multi-versioned function DECL.
35274 Calls to DECL function will be replaced with calls to the dispatcher
35275 by the front-end. Returns the decl of the dispatcher function. */
35277 static tree
35279 {
35301 /* Find the default version and make it the first node. */
35303 /* Go to the beginning of the chain. */
35308 {
35313 }
35315 /* If there is no default node, just return NULL. */
35319 /* Make default info the first node. */
35321 {
35328 }
35332 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
35334 {
35339 /* Right now, the dispatching is done via ifunc. */
35345 dispatcher_version_info
35350 /* Set the dispatcher for all the versions. */
35353 {
35356 }
35357 }
35358 else
35359 #endif
35360 {
35362 "multiversioning needs ifunc which is not supported "
35364 }
35367 }
35369 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
35370 it to CHAIN. */
35372 static tree
35374 {
35375 tree attr_name;
35376 tree attr_arg_name;
35377 tree attr_args;
35378 tree attr;
35385 }
35387 /* Make the resolver function decl to dispatch the versions of
35388 a multi-versioned function, DEFAULT_DECL. Create an
35389 empty basic block in the resolver and store the pointer in
35390 EMPTY_BB. Return the decl of the resolver function. */
35392 static tree
35396 {
35401 /* IFUNC's have to be globally visible. So, if the default_decl is
35402 not, then the name of the IFUNC should be made unique. */
35406 /* Append the filename to the resolver function if the versions are
35407 not externally visible. This is because the resolver function has
35408 to be externally visible for the loader to find it. So, appending
35409 the filename will prevent conflicts with a resolver function from
35410 another module which is based on the same version name. */
35413 /* The resolver function should return a (void *). */
35424 /* IFUNC resolvers have to be externally visible. */
35428 /* Resolver is not external, body is generated. */
35438 {
35439 /* In this case, each translation unit with a call to this
35440 versioned function will put out a resolver. Ensure it
35441 is comdat to keep just one copy. */
35444 }
35445 /* Build result decl and add to function_decl. */
35461 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
35465 /* Create the alias for dispatch to resolver here. */
35466 /*cgraph_create_function_alias (dispatch_decl, decl);*/
35470 }
35472 /* Generate the dispatching code body to dispatch multi-versioned function
35473 DECL. The target hook is called to process the "target" attributes and
35474 provide the code to dispatch the right function at run-time. NODE points
35475 to the dispatcher decl whose body will be created. */
35477 static tree
35479 {
35480 tree resolver_decl;
35481 basic_block empty_bb;
35482 tree default_ver_decl;
35498 /* The first version in the chain corresponds to the default version. */
35501 /* node is going to be an alias, so remove the finalized bit. */
35515 {
35517 /* Check for virtual functions here again, as by this time it should
35518 have been determined if this function needs a vtable index or
35519 not. This happens for methods in derived classes that override
35520 virtual methods in base classes but are not explicitly marked as
35521 virtual. */
35526 }
35532 }
35533 /* This builds the processor_model struct type defined in
35534 libgcc/config/i386/cpuinfo.c */
35536 static tree
35538 {
35545 /* The first 3 fields are unsigned int. */
35547 {
35553 }
35555 /* The last field is an array of unsigned integers of size one. */
35566 }
35568 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
35570 static tree
35572 {
35573 tree new_decl;
35576 VAR_DECL,
35578 type);
35591 }
35593 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
35594 into an integer defined in libgcc/config/i386/cpuinfo.c */
35596 static tree
35598 {
35604 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
35605 enum processor_features
35606 {
35608 F_MMX,
35609 F_POPCNT,
35610 F_SSE,
35611 F_SSE2,
35612 F_SSE3,
35613 F_SSSE3,
35614 F_SSE4_1,
35615 F_SSE4_2,
35616 F_AVX,
35617 F_AVX2,
35618 F_SSE4_A,
35619 F_FMA4,
35620 F_XOP,
35621 F_FMA,
35622 F_AVX512F,
35623 F_BMI,
35624 F_BMI2,
35625 F_AES,
35626 F_PCLMUL,
35627 F_MAX
35628 };
35630 /* These are the values for vendor types and cpu types and subtypes
35631 in cpuinfo.c. Cpu types and subtypes should be subtracted by
35632 the corresponding start value. */
35633 enum processor_model
35634 {
35636 M_AMD,
35637 M_CPU_TYPE_START,
35638 M_INTEL_BONNELL,
35639 M_INTEL_CORE2,
35640 M_INTEL_COREI7,
35641 M_AMDFAM10H,
35642 M_AMDFAM15H,
35643 M_INTEL_SILVERMONT,
35644 M_INTEL_KNL,
35645 M_AMD_BTVER1,
35646 M_AMD_BTVER2,
35647 M_CPU_SUBTYPE_START,
35648 M_INTEL_COREI7_NEHALEM,
35649 M_INTEL_COREI7_WESTMERE,
35650 M_INTEL_COREI7_SANDYBRIDGE,
35651 M_AMDFAM10H_BARCELONA,
35652 M_AMDFAM10H_SHANGHAI,
35653 M_AMDFAM10H_ISTANBUL,
35654 M_AMDFAM15H_BDVER1,
35655 M_AMDFAM15H_BDVER2,
35656 M_AMDFAM15H_BDVER3,
35657 M_AMDFAM15H_BDVER4,
35658 M_INTEL_COREI7_IVYBRIDGE,
35659 M_INTEL_COREI7_HASWELL,
35660 M_INTEL_COREI7_BROADWELL,
35661 M_INTEL_COREI7_SKYLAKE
35662 };
35664 static struct _arch_names_table
35665 {
35668 }
35670 {
35698 };
35700 static struct _isa_names_table
35701 {
35704 }
35706 {
35727 };
35741 {
35742 /* *args must be a expr that can contain other EXPRS leading to a
35743 STRING_CST. */
35745 {
35748 }
35750 }
35755 {
35756 tree ref;
35757 tree field;
35758 tree final;
35761 unsigned int NUM_ARCH_NAMES
35770 {
35774 }
35779 /* CPU types are stored in the next field. */
35782 {
35785 }
35787 /* CPU subtypes are stored in the next field. */
35789 {
35792 }
35794 /* Get the appropriate field in __cpu_model. */
35798 /* Check the value. */
35802 }
35804 {
35805 tree ref;
35806 tree array_elt;
35807 tree field;
35808 tree final;
35811 unsigned int NUM_ISA_NAMES
35820 {
35824 }
35827 /* Get the last field, which is __cpu_features. */
35831 /* Get the appropriate field: __cpu_model.__cpu_features */
35835 /* Access the 0th element of __cpu_features array. */
35840 /* Return __cpu_model.__cpu_features[0] & field_val */
35844 }
35846 }
35848 static tree
35851 {
35853 {
35858 {
35861 }
35862 }
35864 #ifdef SUBTARGET_FOLD_BUILTIN
35866 #endif
35869 }
35871 /* Make builtins to detect cpu type and features supported. NAME is
35872 the builtin name, CODE is the builtin code, and FTYPE is the function
35873 type of the builtin. */
35875 static void
35878 {
35879 tree decl;
35880 tree type;
35888 }
35890 /* Make builtins to get CPU type and features supported. The created
35891 builtins are :
35893 __builtin_cpu_init (), to detect cpu type and features,
35894 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
35895 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
35896 */
35898 static void
35900 {
35907 }
35909 /* Internal method for ix86_init_builtins. */
35911 static void
35913 {
35925 sysv_va_ref =
35928 fnvoid_va_end_ms =
35930 fnvoid_va_start_ms =
35932 fnvoid_va_end_sysv =
35934 fnvoid_va_start_sysv =
35936 NULL_TREE);
35937 fnvoid_va_copy_ms =
35939 NULL_TREE);
35940 fnvoid_va_copy_sysv =
35956 }
35958 static void
35960 {
35963 /* The __float80 type. */
35966 {
35967 /* The __float80 type. */
35972 }
35975 /* The __float128 type. */
35981 /* This macro is built by i386-builtin-types.awk. */
35982 DEFINE_BUILTIN_PRIMITIVE_TYPES;
35983 }
35985 static void
35987 {
35988 tree t;
35992 /* Builtins to get CPU type and features. */
35995 /* TFmode support builtins. */
36001 /* We will expand them to normal call if SSE isn't available since
36002 they are used by libgcc. */
36022 #ifdef SUBTARGET_INIT_BUILTINS
36023 SUBTARGET_INIT_BUILTINS;
36024 #endif
36025 }
36027 /* Return the ix86 builtin for CODE. */
36029 static tree
36031 {
36036 }
36038 /* Errors in the source file can cause expand_expr to return const0_rtx
36039 where we expect a vector. To avoid crashing, use one of the vector
36040 clear instructions. */
36041 static rtx
36043 {
36047 }
36049 /* Fixup modeless constants to fit required mode. */
36050 static rtx
36052 {
36056 }
36058 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
36060 static rtx
36062 {
36063 rtx pat;
36083 {
36087 }
36101 }
36103 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
36105 static rtx
36109 {
36110 rtx pat;
36118 rtx op;
36119 machine_mode mode;
36125 {
36205 }
36215 {
36222 {
36224 {
36227 {
36245 xop_rotl:
36247 {
36250 gcc_checking_assert
36252 }
36253 else
36254 {
36255 gcc_checking_assert
36266 }
36270 }
36271 }
36272 }
36273 else
36274 {
36275 non_constant:
36279 /* If we aren't optimizing, only allow one memory operand to be
36280 generated. */
36282 num_memory++;
36290 }
36294 }
36297 {
36308 else
36309 {
36315 }
36328 }
36335 }
36337 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
36338 insns with vec_merge. */
36340 static rtx
36342 rtx target)
36343 {
36344 rtx pat;
36371 }
36373 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
36375 static rtx
36378 {
36379 rtx pat;
36384 rtx op2;
36395 /* Swap operands if we have a comparison that isn't available in
36396 hardware. */
36418 }
36420 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
36422 static rtx
36424 rtx target)
36425 {
36426 rtx pat;
36440 /* Swap operands if we have a comparison that isn't available in
36441 hardware. */
36463 const0_rtx)));
36466 }
36468 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
36470 static rtx
36472 rtx target)
36473 {
36474 rtx pat;
36499 }
36501 static rtx
36504 {
36505 rtx pat;
36510 rtx op2;
36537 }
36539 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
36541 static rtx
36543 rtx target)
36544 {
36545 rtx pat;
36577 const0_rtx)));
36580 }
36582 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
36584 static rtx
36587 {
36588 rtx pat;
36626 {
36629 }
36632 {
36641 }
36643 {
36652 }
36653 else
36654 {
36661 }
36669 {
36674 emit_insn
36678 FLAGS_REG),
36679 const0_rtx)));
36681 }
36682 else
36684 }
36687 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
36689 static rtx
36692 {
36693 rtx pat;
36721 {
36724 }
36727 {
36736 }
36738 {
36747 }
36748 else
36749 {
36756 }
36764 {
36769 emit_insn
36773 FLAGS_REG),
36774 const0_rtx)));
36776 }
36777 else
36779 }
36781 /* Subroutine of ix86_expand_builtin to take care of insns with
36782 variable number of operands. */
36784 static rtx
36787 {
36793 struct
36794 {
36795 rtx op;
36796 machine_mode mode;
36807 {
37462 }
37467 {
37470 }
37473 {
37480 }
37481 else
37482 {
37485 }
37488 {
37495 {
37496 /* SIMD shift insns take either an 8-bit immediate or
37497 register as count. But builtin functions take int as
37498 count. If count doesn't match, we put it in register. */
37500 {
37504 }
37505 }
37508 {
37511 {
37620 {
37624 {
37627 }
37633 }
37635 }
37636 }
37637 else
37638 {
37642 /* If we aren't optimizing, only allow one memory operand to
37643 be generated. */
37645 num_memory++;
37650 {
37653 }
37654 else
37655 {
37658 }
37659 }
37663 }
37666 {
37691 }
37698 }
37700 /* Transform pattern of following layout:
37701 (parallel [
37702 set (A B)
37703 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
37704 ])
37705 into:
37706 (set (A B))
37708 Or:
37709 (parallel [ A B
37710 ...
37711 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
37712 ...
37713 ])
37714 into:
37715 (parallel [ A B ... ]) */
37717 static rtx
37719 {
37726 {
37735 }
37736 else
37737 {
37743 {
37748 }
37750 /* No more than 1 occurence was removed. */
37754 }
37755 }
37757 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
37758 with rounding. */
37759 static rtx
37762 {
37779 /* See avxintrin.h for values. */
37781 {
37785 };
37787 {
37792 };
37795 {
37798 }
37800 {
37803 }
37806 {
37809 }
37832 ? CODE_FOR_sse_ucomi_round
37839 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
37841 {
37847 }
37848 else
37849 {
37852 }
37857 set_dst,
37858 const0_rtx)));
37861 }
37863 static rtx
37866 {
37867 rtx pat;
37869 struct
37870 {
37871 rtx op;
37872 machine_mode mode;
37881 {
37964 }
37974 {
37981 {
37983 {
37985 {
38001 }
38002 }
38003 }
38005 {
38007 {
38010 }
38012 /* If there is no rounding use normal version of the pattern. */
38015 }
38016 else
38017 {
38024 {
38027 }
38028 else
38029 {
38032 }
38033 }
38037 }
38040 {
38065 }
38075 }
38077 /* Subroutine of ix86_expand_builtin to take care of special insns
38078 with variable number of operands. */
38080 static rtx
38083 {
38084 tree arg;
38088 struct
38089 {
38090 rtx op;
38091 machine_mode mode;
38100 {
38136 {
38144 }
38163 /* Reserve memory operand for target. */
38166 {
38167 /* These builtins and instructions require the memory
38168 to be properly aligned. */
38187 }
38216 {
38217 /* These builtins and instructions require the memory
38218 to be properly aligned. */
38235 }
38236 /* FALLTHRU */
38272 /* Reserve memory operand for target. */
38297 {
38298 /* These builtins and instructions require the memory
38299 to be properly aligned. */
38322 }
38335 }
38340 {
38345 {
38348 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
38349 on it. Try to improve it using get_pointer_alignment,
38350 and if the special builtin is one that requires strict
38351 mode alignment, also from it's GET_MODE_ALIGNMENT.
38352 Failure to do so could lead to ix86_legitimate_combined_insn
38353 rejecting all changes to such insns. */
38359 }
38360 else
38363 }
38364 else
38365 {
38372 }
38375 {
38384 {
38386 {
38392 else
38395 }
38396 }
38397 else
38398 {
38400 {
38401 /* This must be the memory operand. */
38404 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
38405 on it. Try to improve it using get_pointer_alignment,
38406 and if the special builtin is one that requires strict
38407 mode alignment, also from it's GET_MODE_ALIGNMENT.
38408 Failure to do so could lead to ix86_legitimate_combined_insn
38409 rejecting all changes to such insns. */
38415 }
38416 else
38417 {
38418 /* This must be register. */
38426 else
38427 {
38430 }
38431 }
38432 }
38436 }
38439 {
38454 }
38460 }
38462 /* Return the integer constant in ARG. Constrain it to be in the range
38463 of the subparts of VEC_TYPE; issue an error if not. */
38465 static int
38467 {
38472 {
38475 }
38478 }
38480 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38481 ix86_expand_vector_init. We DO have language-level syntax for this, in
38482 the form of (type){ init-list }. Except that since we can't place emms
38483 instructions from inside the compiler, we can't allow the use of MMX
38484 registers unless the user explicitly asks for it. So we do *not* define
38485 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
38486 we have builtins invoked by mmintrin.h that gives us license to emit
38487 these sorts of instructions. */
38489 static rtx
38491 {
38501 {
38504 }
38511 }
38513 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38514 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
38515 had a language-level syntax for referencing vector elements. */
38517 static rtx
38519 {
38523 rtx op0;
38543 }
38545 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38546 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
38547 a language-level syntax for referencing vector elements. */
38549 static rtx
38551 {
38575 /* OP0 is the source of these builtin functions and shouldn't be
38576 modified. Create a copy, use it and return it as target. */
38582 }
38584 /* Emit conditional move of SRC to DST with condition
38585 OP1 CODE OP2. */
38586 static void
38588 {
38589 rtx t;
38592 {
38596 }
38597 else
38598 {
38604 }
38605 }
38607 /* Choose max of DST and SRC and put it to DST. */
38608 static void
38610 {
38612 }
38614 /* Expand an expression EXP that calls a built-in function,
38615 with result going to TARGET if that's convenient
38616 (and in mode MODE if that's convenient).
38617 SUBTARGET may be used as the target for computing one of EXP's operands.
38618 IGNORE is nonzero if the value is to be ignored. */
38620 static rtx
38623 {
38633 /* For CPU builtins that can be folded, fold first and expand the fold. */
38635 {
38637 {
38638 /* Make it call __cpu_indicator_init in libgcc. */
38644 }
38647 {
38652 }
38653 }
38655 /* Determine whether the builtin function is available under the current ISA.
38656 Originally the builtin was not created if it wasn't applicable to the
38657 current ISA based on the command line switches. With function specific
38658 options, we need to check in the context of the function making the call
38659 whether it is supported. */
38662 {
38668 else
38669 {
38673 }
38675 }
38678 {
38696 /* Builtin arg1 is size of block but instruction op1 should
38697 be (size - 1). */
38788 /* If no bounds were specified for returned value,
38789 then use INIT bounds. It usually happens when
38790 some built-in function is expanded. */
38792 {
38801 }
38807 {
38810 /* Return value and lb. */
38812 /* Bounds. */
38814 /* Size. */
38821 /* Size was passed but we need to use (size - 1) as for bndmk. */
38825 /* Add LB to size and inverse to get UB. */
38835 /* We need to move bounds to memory before any computations. */
38838 else
38839 {
38842 }
38844 /* Generate mem expression to be used for access to LB and UB. */
38850 /* Compute LB. */
38855 /* Compute UB. UB is stored in 1's complement form. Therefore
38856 we also use max here. */
38865 }
38868 {
38886 /* Put first bounds to temporaries. */
38890 {
38894 }
38895 else
38896 {
38900 }
38902 /* Put second bounds to temporaries. */
38906 {
38910 }
38911 else
38912 {
38916 }
38918 /* Compute LB. */
38922 /* Compute UB. UB is stored in 1's complement form. Therefore
38923 we also use max here. */
38930 }
38933 {
38934 tree name;
38935 rtx symbol;
38953 }
38956 {
38967 /* We need to move bounds to memory first. */
38970 else
38971 {
38974 }
38976 /* Generate mem expression to access LB and load it. */
38981 }
38984 {
38995 /* We need to move bounds to memory first. */
38998 else
38999 {
39002 }
39004 /* Generate mem expression to access UB. */
39007 /* We need to inverse all bits of UB. */
39014 }
39019 ? CODE_FOR_mmx_maskmovq
39021 /* Note the arg order is different from the operand order. */
39162 {
39163 REAL_VALUE_TYPE inf;
39164 rtx tmp;
39176 }
39186 {
39192 insn = (TARGET_64BIT
39196 }
39198 {
39199 insn = (TARGET_64BIT
39203 }
39204 else
39205 {
39208 insn = (TARGET_64BIT
39216 {
39219 }
39221 }
39224 {
39225 /* mode is VOIDmode if __builtin_rd* has been called
39226 without lhs. */
39230 }
39233 {
39238 }
39251 {
39272 }
39278 {
39281 }
39307 {
39310 }
39316 {
39320 {
39359 }
39364 }
39365 else
39366 {
39368 {
39389 }
39391 }
39421 ? CODE_FOR_tbm_bextri_si
39424 {
39427 }
39428 else
39429 {
39438 }
39454 rdrand_step:
39461 {
39464 }
39470 /* Emit SImode conditional move. */
39472 {
39475 }
39478 else
39486 const0_rtx);
39505 rdseed_step:
39512 {
39515 }
39521 const0_rtx);
39550 handlecarry:
39569 {
39572 }
39574 /* Generate CF from input operand. */
39577 /* Generate instruction that consumes CF. */
39584 /* Return current CF value. */
39591 /* Store the result. */
39630 kortest:
39644 /* Emit kortest. */
39646 /* And use setcc to return result from flags. */
39916 gather_gen:
39917 rtx half;
39930 /* Note the arg order is different from the operand order. */
39941 else
39945 {
39969 else
39976 {
39981 }
39990 else
39997 {
40002 }
40006 }
40008 /* Force memory operand only with base register here. But we
40009 don't want to do it on memory operand for other builtin
40010 functions. */
40023 {
40026 }
40027 else
40028 {
40031 }
40033 {
40036 }
40038 /* Optimize. If mask is known to have all high bits set,
40039 replace op0 with pc_rtx to signal that the instruction
40040 overwrites the whole destination and doesn't use its
40041 previous contents. */
40043 {
40045 {
40048 }
40050 {
40053 {
40057 negative++;
40060 negative++;
40061 }
40064 }
40067 {
40068 /* Recognize also when mask is like:
40069 __v2df src = _mm_setzero_pd ();
40070 __v2df mask = _mm_cmpeq_pd (src, src);
40071 or
40072 __v8sf src = _mm256_setzero_ps ();
40073 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
40074 as that is a cheaper way to load all ones into
40075 a register than having to load a constant from
40076 memory. */
40079 {
40084 {
40091 /* FALLTHRU */
40101 }
40102 }
40103 }
40104 }
40112 {
40138 }
40141 scatter_gen:
40157 /* Scatter instruction stores operand op3 to memory with
40158 indices from op2 and scale from op4 under writemask op1.
40159 If index operand op2 has more elements then source operand
40160 op3 one need to use only its low half. And vice versa. */
40162 {
40176 else
40185 }
40187 /* Force memory operand only with base register here. But we
40188 don't want to do it on memory operand for other builtin
40189 functions. */
40198 {
40201 }
40202 else
40203 {
40206 }
40215 {
40218 }
40227 vec_prefetch_gen:
40247 {
40250 }
40252 {
40255 }
40260 /* Force memory operand only with base register here. But we
40261 don't want to do it on memory operand for other builtin
40262 functions. */
40269 {
40272 }
40275 {
40278 }
40294 {
40297 }
40303 }
40316 {
40320 /* Emit a normal call if SSE isn't available. */
40324 }
40353 }
40355 /* This returns the target-specific builtin with code CODE if
40356 current_function_decl has visibility on this builtin, which is checked
40357 using isa flags. Returns NULL_TREE otherwise. */
40360 {
40364 /* Determine the isa flags of current_function_decl. */
40376 else
40378 }
40380 /* Return function decl for target specific builtin
40381 for given MPX builtin passed i FCODE. */
40382 static tree
40384 {
40386 {
40422 }
40425 }
40427 /* Helper function for ix86_load_bounds and ix86_store_bounds.
40429 Return an address to be used to load/store bounds for pointer
40430 passed in SLOT.
40432 SLOT_NO is an integer constant holding number of a target
40433 dependent special slot to be used in case SLOT is not a memory.
40435 SPECIAL_BASE is a pointer to be used as a base of fake address
40436 to access special slots in Bounds Table. SPECIAL_BASE[-1],
40437 SPECIAL_BASE[-2] etc. will be used as fake pointer locations. */
40439 static rtx
40441 {
40444 /* NULL slot means we pass bounds for pointer not passed to the
40445 function at all. Register slot means we pass pointer in a
40446 register. In both these cases bounds are passed via Bounds
40447 Table. Since we do not have actual pointer stored in memory,
40448 we have to use fake addresses to access Bounds Table. We
40449 start with (special_base - sizeof (void*)) and decrease this
40450 address by pointer size to get addresses for other slots. */
40452 {
40456 }
40457 /* If pointer is passed in a memory then its address is used to
40458 access Bounds Table. */
40460 {
40464 }
40465 else
40469 }
40471 /* Expand pass uses this hook to load bounds for function parameter
40472 PTR passed in SLOT in case its bounds are not passed in a register.
40474 If SLOT is a memory, then bounds are loaded as for regular pointer
40475 loaded from memory. PTR may be NULL in case SLOT is a memory.
40476 In such case value of PTR (if required) may be loaded from SLOT.
40478 If SLOT is NULL or a register then SLOT_NO is an integer constant
40479 holding number of the target dependent special slot which should be
40480 used to obtain bounds.
40482 Return loaded bounds. */
40484 static rtx
40486 {
40488 rtx addr;
40490 /* Get address to be used to access Bounds Table. Special slots start
40491 at the location of return address of the current function. */
40494 /* Load pointer value from a memory if we don't have it. */
40496 {
40499 }
40509 }
40511 /* Expand pass uses this hook to store BOUNDS for call argument PTR
40512 passed in SLOT in case BOUNDS are not passed in a register.
40514 If SLOT is a memory, then BOUNDS are stored as for regular pointer
40515 stored in memory. PTR may be NULL in case SLOT is a memory.
40516 In such case value of PTR (if required) may be loaded from SLOT.
40518 If SLOT is NULL or a register then SLOT_NO is an integer constant
40519 holding number of the target dependent special slot which should be
40520 used to store BOUNDS. */
40522 static void
40524 {
40525 rtx addr;
40527 /* Get address to be used to access Bounds Table. Special slots start
40528 at the location of return address of a called function. */
40531 /* Load pointer value from a memory if we don't have it. */
40533 {
40536 }
40548 }
40550 /* Load and return bounds returned by function in SLOT. */
40552 static rtx
40554 {
40555 rtx res;
40562 }
40564 /* Store BOUNDS returned by function into SLOT. */
40566 static void
40568 {
40571 }
40573 /* Returns a function decl for a vectorized version of the builtin function
40574 with builtin function code FN and the result vector type TYPE, or NULL_TREE
40575 if it is not available. */
40577 static tree
40579 tree type_in)
40580 {
40596 {
40599 {
40606 }
40611 {
40614 }
40619 {
40626 }
40632 /* The round insn does not trap on denormals. */
40637 {
40644 }
40650 /* The round insn does not trap on denormals. */
40655 {
40660 }
40666 /* The round insn does not trap on denormals. */
40671 {
40678 }
40684 /* The round insn does not trap on denormals. */
40689 {
40694 }
40701 {
40706 }
40713 {
40718 }
40724 /* The round insn does not trap on denormals. */
40729 {
40736 }
40742 /* The round insn does not trap on denormals. */
40747 {
40752 }
40757 {
40764 }
40769 {
40776 }
40780 /* The round insn does not trap on denormals. */
40785 {
40790 }
40794 /* The round insn does not trap on denormals. */
40799 {
40804 }
40808 /* The round insn does not trap on denormals. */
40813 {
40818 }
40822 /* The round insn does not trap on denormals. */
40827 {
40832 }
40836 /* The round insn does not trap on denormals. */
40841 {
40846 }
40850 /* The round insn does not trap on denormals. */
40855 {
40860 }
40864 /* The round insn does not trap on denormals. */
40869 {
40874 }
40878 /* The round insn does not trap on denormals. */
40883 {
40888 }
40892 /* The round insn does not trap on denormals. */
40897 {
40902 }
40906 /* The round insn does not trap on denormals. */
40911 {
40916 }
40921 {
40926 }
40931 {
40936 }
40941 }
40943 /* Dispatch to a handler for a vectorization library. */
40946 type_in);
40949 }
40951 /* Handler for an SVML-style interface to
40952 a library with vectorized intrinsics. */
40954 static tree
40956 {
40964 /* The SVML is suitable for unsafe math only. */
40977 {
41024 }
41033 {
41036 }
41037 else
41040 /* Convert to uppercase. */
41045 args;
41047 arity++;
41051 else
41054 /* Build a function declaration for the vectorized function. */
41063 }
41065 /* Handler for an ACML-style interface to
41066 a library with vectorized intrinsics. */
41068 static tree
41070 {
41078 /* The ACML is 64bits only and suitable for unsafe math only as
41079 it does not correctly support parts of IEEE with the required
41080 precision such as denormals. */
41094 {
41124 }
41131 args;
41133 arity++;
41137 else
41140 /* Build a function declaration for the vectorized function. */
41149 }
41151 /* Returns a decl of a function that implements gather load with
41152 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
41153 Return NULL_TREE if it is not available. */
41155 static tree
41158 {
41174 /* v*gather* insn sign extends index to pointer mode. */
41186 {
41190 else
41196 else
41202 else
41208 else
41214 else
41220 else
41226 else
41232 else
41238 else
41244 else
41250 else
41256 else
41261 }
41264 }
41266 /* Returns a decl of a function that implements scatter store with
41267 register type VECTYPE and index type INDEX_TYPE and SCALE.
41268 Return NULL_TREE if it is not available. */
41270 static tree
41273 {
41289 /* v*scatter* insn sign extends index to pointer mode. */
41294 /* Scale can be 1, 2, 4 or 8. */
41302 {
41317 }
41320 }
41322 /* Returns a code for a target-specific builtin that implements
41323 reciprocal of the function, or NULL_TREE if not available. */
41325 static tree
41327 {
41334 /* Machine dependent builtins. */
41336 {
41337 /* Vectorized version of sqrt to rsqrt conversion. */
41346 }
41347 else
41348 /* Normal builtins. */
41350 {
41351 /* Sqrt to rsqrt conversion. */
41357 }
41358 }
41359 \f
41360 /* Helper for avx_vpermilps256_operand et al. This is also used by
41361 the expansion functions to turn the parallel back into a mask.
41362 The return value is 0 for no match and the imm8+1 for a match. */
41364 int
41366 {
41374 /* Validate that all of the elements are constants, and not totally
41375 out of range. Copy the data into an integral array to make the
41376 subsequent checks easier. */
41378 {
41388 }
41391 {
41393 /* In the 512-bit DFmode case, we can only move elements within
41394 a 128-bit lane. First fill the second part of the mask,
41395 then fallthru. */
41397 {
41401 }
41403 {
41407 }
41408 /* FALLTHRU */
41411 /* In the 256-bit DFmode case, we can only move elements within
41412 a 128-bit lane. */
41414 {
41418 }
41420 {
41424 }
41428 /* In 512 bit SFmode case, permutation in the upper 256 bits
41429 must mirror the permutation in the lower 256-bits. */
41433 /* FALLTHRU */
41436 /* In 256 bit SFmode case, we have full freedom of
41437 movement within the low 128-bit lane, but the high 128-bit
41438 lane must mirror the exact same pattern. */
41443 /* FALLTHRU */
41447 /* In the 128-bit case, we've full freedom in the placement of
41448 the elements from the source operand. */
41455 }
41457 /* Make sure success has a non-zero value by adding one. */
41459 }
41461 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
41462 the expansion functions to turn the parallel back into a mask.
41463 The return value is 0 for no match and the imm8+1 for a match. */
41465 int
41467 {
41475 /* Validate that all of the elements are constants, and not totally
41476 out of range. Copy the data into an integral array to make the
41477 subsequent checks easier. */
41479 {
41489 }
41491 /* Validate that the halves of the permute are halves. */
41499 /* Reconstruct the mask. */
41501 {
41507 }
41509 /* Make sure success has a non-zero value by adding one. */
41511 }
41512 \f
41513 /* Return a register priority for hard reg REGNO. */
41514 static int
41516 {
41517 /* ebp and r13 as the base always wants a displacement, r12 as the
41518 base always wants an index. So discourage their usage in an
41519 address. */
41524 /* New x86-64 int registers result in bigger code size. Discourage
41525 them. */
41528 /* New x86-64 SSE registers result in bigger code size. Discourage
41529 them. */
41532 /* Usage of AX register results in smaller code. Prefer it. */
41536 }
41538 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
41540 Put float CONST_DOUBLE in the constant pool instead of fp regs.
41541 QImode must go into class Q_REGS.
41542 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
41543 movdf to do mem-to-mem moves through integer regs. */
41545 static reg_class_t
41547 {
41550 /* We're only allowed to return a subclass of CLASS. Many of the
41551 following checks fail for NO_REGS, so eliminate that early. */
41555 /* All classes can load zeros. */
41559 /* Force constants into memory if we are loading a (nonzero) constant into
41560 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
41561 instructions to load from a constant. */
41568 /* Prefer SSE regs only, if we can use them for math. */
41572 /* Floating-point constants need more complex checks. */
41574 {
41575 /* General regs can load everything. */
41579 /* Floats can load 0 and 1 plus some others. Note that we eliminated
41580 zero above. We only want to wind up preferring 80387 registers if
41581 we plan on doing computation with them. */
41584 {
41585 /* Limit class to non-sse. */
41594 }
41597 }
41599 /* Generally when we see PLUS here, it's the function invariant
41600 (plus soft-fp const_int). Which can only be computed into general
41601 regs. */
41605 /* QImode constants are easy to load, but non-constant QImode data
41606 must go into Q_REGS. */
41608 {
41614 }
41617 }
41619 /* Discourage putting floating-point values in SSE registers unless
41620 SSE math is being used, and likewise for the 387 registers. */
41621 static reg_class_t
41623 {
41626 /* Restrict the output reload class to the register bank that we are doing
41627 math on. If we would like not to return a subset of CLASS, reject this
41628 alternative: if reload cannot do this, it will still use its choice. */
41634 {
41639 else
41641 }
41644 }
41646 static reg_class_t
41649 {
41650 /* Double-word spills from general registers to non-offsettable memory
41651 references (zero-extended addresses) require special handling. */
41657 {
41659 ? CODE_FOR_reload_noff_load
41661 /* Add the cost of moving address to a temporary. */
41665 }
41667 /* QImode spills from non-QI registers require
41668 intermediate register on 32bit targets. */
41674 {
41679 else
41685 /* Return Q_REGS if the operand is in memory. */
41688 }
41690 /* This condition handles corner case where an expression involving
41691 pointers gets vectorized. We're trying to use the address of a
41692 stack slot as a vector initializer.
41694 (set (reg:V2DI 74 [ vect_cst_.2 ])
41695 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
41697 Eventually frame gets turned into sp+offset like this:
41699 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41700 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41701 (const_int 392 [0x188]))))
41703 That later gets turned into:
41705 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41706 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41707 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
41709 We'll have the following reload recorded:
41711 Reload 0: reload_in (DI) =
41712 (plus:DI (reg/f:DI 7 sp)
41713 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
41714 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41715 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
41716 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
41717 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41718 reload_reg_rtx: (reg:V2DI 22 xmm1)
41720 Which isn't going to work since SSE instructions can't handle scalar
41721 additions. Returning GENERAL_REGS forces the addition into integer
41722 register and reload can handle subsequent reloads without problems. */
41730 }
41732 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
41734 static bool
41736 {
41738 {
41754 }
41757 }
41759 /* If we are copying between general and FP registers, we need a memory
41760 location. The same is true for SSE and MMX registers.
41762 To optimize register_move_cost performance, allow inline variant.
41764 The macro can't work reliably when one of the CLASSES is class containing
41765 registers from multiple units (SSE, MMX, integer). We avoid this by never
41766 combining those units in single alternative in the machine description.
41767 Ensure that this constraint holds to avoid unexpected surprises.
41769 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
41770 enforce these sanity checks. */
41775 {
41784 {
41787 }
41792 /* Between mask and general, we have moves no larger than word size. */
41797 /* ??? This is a lie. We do have moves between mmx/general, and for
41798 mmx/sse2. But by saying we need secondary memory we discourage the
41799 register allocator from using the mmx registers unless needed. */
41804 {
41805 /* SSE1 doesn't have any direct moves from other classes. */
41809 /* If the target says that inter-unit moves are more expensive
41810 than moving through memory, then don't generate them. */
41815 /* Between SSE and general, we have moves no larger than word size. */
41818 }
41821 }
41823 bool
41826 {
41828 }
41830 /* Implement the TARGET_CLASS_MAX_NREGS hook.
41832 On the 80386, this is the size of MODE in words,
41833 except in the FP regs, where a single reg is always enough. */
41835 static unsigned char
41837 {
41839 {
41844 else
41846 }
41847 else
41848 {
41851 else
41853 }
41854 }
41856 /* Return true if the registers in CLASS cannot represent the change from
41857 modes FROM to TO. */
41859 bool
41862 {
41866 /* x87 registers can't do subreg at all, as all values are reformatted
41867 to extended precision. */
41872 {
41873 /* Vector registers do not support QI or HImode loads. If we don't
41874 disallow a change to these modes, reload will assume it's ok to
41875 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
41876 the vec_dupv4hi pattern. */
41879 }
41882 }
41884 /* Return the cost of moving data of mode M between a
41885 register and memory. A value of 2 is the default; this cost is
41886 relative to those in `REGISTER_MOVE_COST'.
41888 This function is used extensively by register_move_cost that is used to
41889 build tables at startup. Make it inline in this case.
41890 When IN is 2, return maximum of in and out move cost.
41892 If moving between registers and memory is more expensive than
41893 between two registers, you should define this macro to express the
41894 relative cost.
41896 Model also increased moving costs of QImode registers in non
41897 Q_REGS classes.
41898 */
41902 {
41905 {
41908 {
41920 }
41924 }
41926 {
41929 {
41941 }
41945 }
41947 {
41950 {
41959 }
41963 }
41965 {
41968 {
41974 else
41979 }
41980 else
41981 {
41986 else
41988 }
41995 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
42002 else
42006 }
42007 }
42009 static int
42012 {
42014 }
42017 /* Return the cost of moving data from a register in class CLASS1 to
42018 one in class CLASS2.
42020 It is not required that the cost always equal 2 when FROM is the same as TO;
42021 on some machines it is expensive to move between registers if they are not
42022 general registers. */
42024 static int
42026 reg_class_t class2_i)
42027 {
42031 /* In case we require secondary memory, compute cost of the store followed
42032 by load. In order to avoid bad register allocation choices, we need
42033 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
42036 {
42042 /* In case of copying from general_purpose_register we may emit multiple
42043 stores followed by single load causing memory size mismatch stall.
42044 Count this as arbitrarily high cost of 20. */
42049 /* In the case of FP/MMX moves, the registers actually overlap, and we
42050 have to switch modes in order to treat them differently. */
42056 }
42058 /* Moves between SSE/MMX and integer unit are expensive. */
42062 /* ??? By keeping returned value relatively high, we limit the number
42063 of moves between integer and MMX/SSE registers for all targets.
42064 Additionally, high value prevents problem with x86_modes_tieable_p(),
42065 where integer modes in MMX/SSE registers are not tieable
42066 because of missing QImode and HImode moves to, from or between
42067 MMX/SSE registers. */
42077 }
42079 /* Return TRUE if hard register REGNO can hold a value of machine-mode
42080 MODE. */
42082 bool
42084 {
42085 /* Flags and only flags can only hold CCmode values. */
42096 || (TARGET_AVX512BW
42101 {
42102 /* We implement the move patterns for all vector modes into and
42103 out of SSE registers, even when no operation instructions
42104 are available. */
42106 /* For AVX-512 we allow, regardless of regno:
42107 - XI mode
42108 - any of 512-bit wide vector mode
42109 - any scalar mode. */
42116 /* TODO check for QI/HI scalars. */
42117 /* AVX512VL allows sse regs16+ for 128/256 bit modes. */
42125 /* xmm16-xmm31 are only available for AVX-512. */
42129 /* OImode and AVX modes are available only when AVX is enabled. */
42136 }
42138 {
42139 /* We implement the move patterns for 3DNOW modes even in MMX mode,
42140 so if the register is available at all, then we can move data of
42141 the given mode into or out of it. */
42144 }
42147 {
42148 /* Take care for QImode values - they can be in non-QI regs,
42149 but then they do cause partial register stalls. */
42154 /* LRA checks if the hard register is OK for the given mode.
42155 QImode values can live in non-QI regs, so we allow all
42156 registers here. */
42160 }
42161 /* We handle both integer and floats in the general purpose registers. */
42168 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
42169 on to use that value in smaller contexts, this can easily force a
42170 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
42171 supporting DImode, allow it. */
42176 }
42178 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
42179 tieable integer mode. */
42181 static bool
42183 {
42185 {
42198 }
42199 }
42201 /* Return true if MODE1 is accessible in a register that can hold MODE2
42202 without copying. That is, all register classes that can hold MODE2
42203 can also hold MODE1. */
42205 bool
42207 {
42215 /* MODE2 being XFmode implies fp stack or general regs, which means we
42216 can tie any smaller floating point modes to it. Note that we do not
42217 tie this with TFmode. */
42221 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
42222 that we can tie it with SFmode. */
42226 /* If MODE2 is only appropriate for an SSE register, then tie with
42227 any other mode acceptable to SSE registers. */
42237 /* If MODE2 is appropriate for an MMX register, then tie
42238 with any other mode acceptable to MMX registers. */
42245 }
42247 /* Return the cost of moving between two registers of mode MODE. */
42249 static int
42251 {
42255 {
42287 }
42289 /* Return the cost of moving between two registers of mode MODE,
42290 assuming that the move will be in pieces of at most UNITS bytes. */
42292 }
42294 /* Compute a (partial) cost for rtx X. Return true if the complete
42295 cost has been computed, and false if subexpressions should be
42296 scanned. In either case, *TOTAL contains the cost result. */
42298 static bool
42301 {
42302 rtx mask;
42308 {
42312 {
42315 }
42327 && !(TARGET_64BIT
42331 /* Use 0 cost for CONST to improve its propagation. */
42334 else
42344 {
42354 }
42356 {
42359 {
42368 }
42369 }
42370 /* Fall back to (MEM (SYMBOL_REF)), since that's where
42371 it'll probably end up. Add a penalty for size. */
42378 /* The zero extensions is often completely free on x86_64, so make
42379 it as cheap as possible. */
42385 else
42397 {
42400 {
42403 }
42406 {
42409 }
42410 }
42411 /* FALLTHRU */
42418 {
42419 /* ??? Should be SSE vector operation cost. */
42420 /* At least for published AMD latencies, this really is the same
42421 as the latency for a simple fpu operation like fabs. */
42422 /* V*QImode is emulated with 1-11 insns. */
42424 {
42427 {
42428 /* For XOP we use vpshab, which requires a broadcast of the
42429 value to the variable shift insn. For constants this
42430 means a V16Q const in mem; even when we can perform the
42431 shift with one insn set the cost to prefer paddb. */
42433 {
42438 }
42440 }
42444 }
42445 else
42447 }
42449 {
42451 {
42454 else
42456 }
42457 else
42458 {
42461 else
42463 }
42464 }
42465 else
42466 {
42471 {
42472 /* Return the cost after shift-and truncation. */
42475 }
42476 else
42478 }
42482 {
42483 rtx sub;
42488 /* ??? SSE scalar/vector cost should be used here. */
42489 /* ??? Bald assumption that fma has the same cost as fmul. */
42493 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
42504 }
42508 {
42509 /* ??? SSE scalar cost should be used here. */
42512 }
42514 {
42517 }
42519 {
42520 /* ??? SSE vector cost should be used here. */
42523 }
42525 {
42526 /* V*QImode is emulated with 7-13 insns. */
42528 {
42535 }
42536 /* V*DImode is emulated with 5-8 insns. */
42538 {
42541 else
42543 }
42544 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
42545 insns, including two PMULUDQ. */
42548 else
42551 }
42552 else
42553 {
42558 {
42561 nbits++;
42562 }
42563 else
42564 /* This is arbitrary. */
42567 /* Compute costs correctly for widening multiplication. */
42571 {
42578 {
42582 else
42584 }
42588 }
42596 }
42603 /* ??? SSE cost should be used here. */
42608 /* ??? SSE vector cost should be used here. */
42610 else
42617 {
42622 {
42625 {
42634 }
42635 }
42638 {
42641 {
42648 }
42649 }
42651 {
42660 }
42661 }
42662 /* FALLTHRU */
42666 {
42667 /* ??? SSE cost should be used here. */
42670 }
42672 {
42675 }
42677 {
42678 /* ??? SSE vector cost should be used here. */
42681 }
42682 /* FALLTHRU */
42689 {
42696 }
42697 /* FALLTHRU */
42701 {
42702 /* ??? SSE cost should be used here. */
42705 }
42707 {
42710 }
42712 {
42713 /* ??? SSE vector cost should be used here. */
42716 }
42717 /* FALLTHRU */
42721 {
42722 /* ??? Should be SSE vector operation cost. */
42723 /* At least for published AMD latencies, this really is the same
42724 as the latency for a simple fpu operation like fabs. */
42726 }
42729 else
42738 {
42739 /* This kind of construct is implemented using test[bwl].
42740 Treat it as if we had an AND. */
42747 }
42749 /* The embedded comparison operand is completely free. */
42763 /* ??? SSE cost should be used here. */
42768 /* ??? SSE vector cost should be used here. */
42774 /* ??? SSE cost should be used here. */
42779 /* ??? SSE vector cost should be used here. */
42791 /* ??? Assume all of these vector manipulation patterns are
42792 recognizable. In which case they all pretty much have the
42793 same cost. */
42798 /* This is masked instruction, assume the same cost,
42799 as nonmasked variant. */
42802 else
42808 }
42809 }
42811 #if TARGET_MACHO
42815 /* Given a symbol name and its associated stub, write out the
42816 definition of the stub. */
42818 void
42820 {
42825 /* For 64-bit we shouldn't get here. */
42828 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
42845 else
42852 {
42854 }
42856 {
42857 /* PIC stub. */
42858 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42864 }
42865 else
42868 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
42869 it needs no stub-binding-helper. */
42876 {
42879 }
42880 else
42885 /* N.B. Keep the correspondence of these
42886 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
42887 old-pic/new-pic/non-pic stubs; altering this will break
42888 compatibility with existing dylibs. */
42890 {
42891 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42893 }
42894 else
42895 /* 16-byte -mdynamic-no-pic stub. */
42901 }
42904 /* Order the registers for register allocator. */
42906 void
42908 {
42912 /* First allocate the local general purpose registers. */
42917 /* Global general purpose registers. */
42922 /* x87 registers come first in case we are doing FP math
42923 using them. */
42928 /* SSE registers. */
42934 /* Extended REX SSE registers. */
42938 /* Mask register. */
42942 /* MPX bound registers. */
42946 /* x87 registers. */
42954 /* Initialize the rest of array as we do not allocate some registers
42955 at all. */
42958 }
42960 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
42961 in struct attribute_spec handler. */
42962 static tree
42964 tree args,
42967 {
42972 {
42974 name);
42977 }
42979 {
42981 name);
42984 }
42986 {
42987 tree cst;
42991 {
42994 name);
42996 }
42999 {
43002 name);
43004 }
43007 }
43010 }
43012 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
43013 struct attribute_spec.handler. */
43014 static tree
43017 {
43022 {
43024 name);
43027 }
43029 /* Can combine regparm with all attributes but fastcall. */
43031 {
43033 {
43035 }
43038 }
43040 {
43042 {
43044 }
43047 }
43050 }
43052 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
43053 struct attribute_spec.handler. */
43054 static tree
43057 {
43060 {
43063 }
43064 else
43068 {
43070 name);
43072 }
43078 {
43080 name);
43082 }
43085 }
43087 static tree
43090 {
43092 {
43094 name);
43096 }
43098 }
43100 static bool
43102 {
43106 }
43108 /* Returns an expression indicating where the this parameter is
43109 located on entry to the FUNCTION. */
43111 static rtx
43113 {
43119 {
43124 else
43127 }
43132 {
43139 {
43144 }
43145 else
43146 {
43149 {
43155 }
43156 }
43158 }
43162 }
43164 /* Determine whether x86_output_mi_thunk can succeed. */
43166 static bool
43168 const_tree function)
43169 {
43170 /* 64-bit can handle anything. */
43174 /* For 32-bit, everything's fine if we have one free register. */
43178 /* Need a free register for vcall_offset. */
43182 /* Need a free register for GOT references. */
43186 /* Otherwise ok. */
43188 }
43190 /* Output the assembler code for a thunk function. THUNK_DECL is the
43191 declaration for the thunk function itself, FUNCTION is the decl for
43192 the target function. DELTA is an immediate constant offset to be
43193 added to THIS. If VCALL_OFFSET is nonzero, the word at
43194 *(*this + vcall_offset) should be added to THIS. */
43196 static void
43199 {
43207 else
43208 {
43214 else
43216 }
43220 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
43221 pull it in now and let DELTA benefit. */
43225 {
43226 /* Put the this parameter into %eax. */
43229 }
43230 else
43233 /* Adjust the this parameter by a fixed constant. */
43235 {
43240 {
43242 {
43246 }
43247 }
43250 }
43252 /* Adjust the this parameter by a value stored in the vtable. */
43254 {
43264 /* Adjust the this parameter. */
43268 {
43272 }
43279 vcall_mem));
43280 else
43282 }
43284 /* If necessary, drop THIS back to its stack slot. */
43290 {
43293 ;
43294 else
43295 {
43299 }
43300 }
43301 else
43302 {
43304 ;
43305 #if TARGET_MACHO
43307 {
43310 }
43312 else
43313 {
43321 }
43322 }
43324 /* Our sibling call patterns do not allow memories, because we have no
43325 predicate that can distinguish between frame and non-frame memory.
43326 For our purposes here, we can get away with (ab)using a jump pattern,
43327 because we're going to do no optimization. */
43329 {
43331 {
43337 }
43338 else
43340 }
43341 else
43342 {
43344 {
43345 // CM_LARGE_PIC always uses pseudo PIC register which is
43346 // uninitialized. Since FUNCTION is local and calling it
43347 // doesn't go through PLT, we use scratch register %r11 as
43348 // PIC register and initialize it here.
43353 }
43356 {
43362 }
43368 }
43371 /* Emit just enough of rest_of_compilation to get the insns emitted.
43372 Note that use_thunk calls assemble_start_function et al. */
43378 }
43380 static void
43382 {
43386 #if TARGET_MACHO
43388 #endif
43395 }
43397 int
43399 {
43400 machine_mode mode;
43413 }
43415 /* Print call to TARGET to FILE. */
43417 static void
43419 {
43422 else
43424 }
43426 /* Output assembler code to FILE to increment profiler label # LABELNO
43427 for profiling a function entry. */
43428 void
43430 {
43434 {
43435 #ifndef NO_PROFILE_COUNTERS
43437 #endif
43441 else
43443 }
43445 {
43446 #ifndef NO_PROFILE_COUNTERS
43449 #endif
43451 }
43452 else
43453 {
43454 #ifndef NO_PROFILE_COUNTERS
43457 #endif
43459 }
43462 {
43466 }
43467 }
43469 /* We don't have exact information about the insn sizes, but we may assume
43470 quite safely that we are informed about all 1 byte insns and memory
43471 address sizes. This is enough to eliminate unnecessary padding in
43472 99% of cases. */
43474 static int
43476 {
43482 /* Discard alignments we've emit and jump instructions. */
43487 /* Important case - calls are always 5 bytes.
43488 It is common to have many calls in the row. */
43497 /* For normal instructions we rely on get_attr_length being exact,
43498 with a few exceptions. */
43500 {
43504 {
43514 /* Otherwise trust get_attr_length. */
43516 }
43521 }
43524 else
43526 }
43528 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43530 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
43531 window. */
43533 static void
43535 {
43540 /* Look for all minimal intervals of instructions containing 4 jumps.
43541 The intervals are bounded by START and INSN. NBYTES is the total
43542 size of instructions in the interval including INSN and not including
43543 START. When the NBYTES is smaller than 16 bytes, it is possible
43544 that the end of START and INSN ends up in the same 16byte page.
43546 The smallest offset in the page INSN can start is the case where START
43547 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
43548 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
43550 Don't consider asm goto as jump, while it can contain a jump, it doesn't
43551 have to, control transfer to label(s) can be performed through other
43552 means, and also we estimate minimum length of all asm stmts as 0. */
43554 {
43558 {
43564 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
43565 already in the current 16 byte page, because otherwise
43566 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
43567 bytes to reach 16 byte boundary. */
43575 {
43577 {
43582 else
43585 }
43586 }
43588 }
43597 njumps++;
43598 else
43602 {
43607 else
43610 }
43617 {
43624 }
43625 }
43626 }
43627 #endif
43629 /* AMD Athlon works faster
43630 when RET is not destination of conditional jump or directly preceded
43631 by other jump instruction. We avoid the penalty by inserting NOP just
43632 before the RET instructions in such cases. */
43633 static void
43635 {
43636 edge e;
43637 edge_iterator ei;
43640 {
43653 {
43654 edge e;
43655 edge_iterator ei;
43660 {
43663 }
43664 }
43666 {
43672 /* Empty functions get branch mispredict even when
43673 the jump destination is not visible to us. */
43676 }
43678 {
43681 }
43682 }
43683 }
43685 /* Count the minimum number of instructions in BB. Return 4 if the
43686 number of instructions >= 4. */
43688 static int
43690 {
43694 /* Count number of instructions in this block. Return 4 if the number
43695 of instructions >= 4. */
43697 {
43698 /* Only happen in exit blocks. */
43706 {
43707 insn_count++;
43710 }
43711 }
43714 }
43717 /* Count the minimum number of instructions in code path in BB.
43718 Return 4 if the number of instructions >= 4. */
43720 static int
43722 {
43723 edge e;
43724 edge_iterator ei;
43727 /* Only bother counting instructions along paths with no
43728 more than 2 basic blocks between entry and exit. Given
43729 that BB has an edge to exit, determine if a predecessor
43730 of BB has an edge from entry. If so, compute the number
43731 of instructions in the predecessor block. If there
43732 happen to be multiple such blocks, compute the minimum. */
43735 {
43736 edge prev_e;
43737 edge_iterator prev_ei;
43740 {
43743 }
43745 {
43747 {
43752 }
43753 }
43754 }
43760 }
43762 /* Pad short function to 4 instructions. */
43764 static void
43766 {
43767 edge e;
43768 edge_iterator ei;
43771 {
43774 {
43777 /* Pad short function. */
43779 {
43782 /* Find epilogue. */
43791 /* Two NOPs count as one instruction. */
43794 }
43795 }
43796 }
43797 }
43799 /* Fix up a Windows system unwinder issue. If an EH region falls through into
43800 the epilogue, the Windows system unwinder will apply epilogue logic and
43801 produce incorrect offsets. This can be avoided by adding a nop between
43802 the last insn that can throw and the first insn of the epilogue. */
43804 static void
43806 {
43807 edge e;
43808 edge_iterator ei;
43811 {
43814 /* Find the beginning of the epilogue. */
43821 /* We only care about preceding insns that can throw. */
43826 /* Do not separate calls from their debug information. */
43832 else
43836 }
43837 }
43839 /* Implement machine specific optimizations. We implement padding of returns
43840 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
43841 static void
43843 {
43844 /* We are freeing block_for_insn in the toplev to keep compatibility
43845 with old MDEP_REORGS that are not CFG based. Recompute it now. */
43852 {
43857 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43860 #endif
43861 }
43862 }
43864 /* Return nonzero when QImode register that must be represented via REX prefix
43865 is used. */
43866 bool
43868 {
43876 }
43878 /* Return true when INSN mentions register that must be encoded using REX
43879 prefix. */
43880 bool
43882 {
43885 {
43890 }
43892 }
43894 /* If profitable, negate (without causing overflow) integer constant
43895 of mode MODE at location LOC. Return true in this case. */
43896 bool
43898 {
43899 HOST_WIDE_INT val;
43905 {
43907 /* DImode x86_64 constants must fit in 32 bits. */
43920 }
43922 /* Avoid overflows. */
43928 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
43929 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
43932 {
43935 }
43938 }
43940 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
43941 optabs would emit if we didn't have TFmode patterns. */
43943 void
43945 {
43980 }
43981 \f
43987 /* Get a vector mode of the same size as the original but with elements
43988 twice as wide. This is only guaranteed to apply to integral vectors. */
43992 {
43993 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
43998 }
44000 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
44001 fill target with val via vec_duplicate. */
44003 static bool
44005 {
44008 rtx dup;
44010 /* First attempt to recognize VAL as-is. */
44014 {
44016 /* If that fails, force VAL into a register. */
44027 }
44029 }
44031 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
44032 with all elements equal to VAR. Return true if successful. */
44034 static bool
44037 {
44041 {
44046 /* FALLTHRU */
44066 {
44067 rtx x;
44074 }
44087 {
44091 permute:
44099 /* Extend to SImode using a paradoxical SUBREG. */
44103 /* Insert the SImode value as low element of a V4SImode vector. */
44112 }
44123 widen:
44124 /* Replicate the value once into the next wider mode and recurse. */
44125 {
44127 rtx x;
44144 }
44150 else
44151 {
44160 }
44167 else
44168 {
44177 }
44182 }
44183 }
44185 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
44186 whose ONE_VAR element is VAR, and other elements are zero. Return true
44187 if successful. */
44189 static bool
44192 {
44193 machine_mode vsimode;
44194 rtx new_target;
44199 {
44201 /* For SSE4.1, we normally use vector set. But if the second
44202 element is zero and inter-unit moves are OK, we use movq
44203 instead. */
44205 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
44227 /* Use ix86_expand_vector_set in 64bit mode only. */
44232 }
44235 {
44240 }
44243 {
44248 /* FALLTHRU */
44263 else
44270 {
44271 /* We need to shuffle the value to the correct position, so
44272 create a new pseudo to store the intermediate result. */
44274 /* With SSE2, we can use the integer shuffle insns. */
44276 {
44278 const1_rtx,
44285 }
44287 /* Otherwise convert the intermediate result to V4SFmode and
44288 use the SSE1 shuffle instructions. */
44290 {
44293 }
44294 else
44298 const1_rtx,
44307 }
44322 widen:
44326 /* Zero extend the variable element to SImode and recurse. */
44339 }
44340 }
44342 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
44343 consisting of the values in VALS. It is known that all elements
44344 except ONE_VAR are constants. Return true if successful. */
44346 static bool
44349 {
44351 machine_mode wmode;
44359 {
44364 /* For the two element vectors, it's just as easy to use
44365 the general case. */
44369 /* Use ix86_expand_vector_set in 64bit mode only. */
44391 widen:
44392 /* There's no way to set one QImode entry easily. Combine
44393 the variable value with its adjacent constant value, and
44394 promote to an HImode set. */
44397 {
44402 }
44403 else
44404 {
44407 }
44421 }
44426 }
44428 /* A subroutine of ix86_expand_vector_init_general. Use vector
44429 concatenate to handle the most general case: all values variable,
44430 and none identical. */
44432 static void
44435 {
44438 rtvec v;
44442 {
44445 {
44490 }
44502 {
44517 }
44522 {
44541 }
44546 {
44559 }
44562 half:
44563 /* FIXME: We process inputs backward to help RA. PR 36222. */
44567 {
44572 }
44576 {
44580 {
44584 }
44587 {
44591 }
44594 }
44596 {
44599 {
44603 }
44606 }
44607 else
44613 }
44614 }
44616 /* A subroutine of ix86_expand_vector_init_general. Use vector
44617 interleave to handle the most general case: all values variable,
44618 and none identical. */
44620 static void
44623 {
44632 {
44653 }
44656 {
44657 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
44661 /* Insert the SImode value as low element of V4SImode vector. */
44665 op0),
44667 const1_rtx);
44670 /* Cast the V4SImode vector back to a vector in orignal mode. */
44674 /* Load even elements into the second position. */
44678 const1_rtx));
44680 /* Cast vector to FIRST_IMODE vector. */
44683 }
44685 /* Interleave low FIRST_IMODE vectors. */
44687 {
44691 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
44694 }
44696 /* Interleave low SECOND_IMODE vectors. */
44698 {
44701 {
44706 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
44707 vector. */
44710 }
44713 /* FALLTHRU */
44720 /* Cast the SECOND_IMODE vector back to a vector on original
44721 mode. */
44727 }
44728 }
44730 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
44731 all values variable, and none identical. */
44733 static void
44736 {
44743 {
44748 /* FALLTHRU */
44776 half:
44799 quarter:
44825 /* FALLTHRU */
44831 /* Don't use ix86_expand_vector_init_interleave if we can't
44832 move from GPR to SSE register directly. */
44848 }
44850 {
44852 machine_mode inner_mode;
44862 {
44866 {
44872 else
44873 {
44878 }
44879 }
44882 }
44887 {
44893 }
44895 {
44901 }
44902 else
44904 }
44905 }
44907 /* Initialize vector TARGET via VALS. Suppress the use of MMX
44908 instructions unless MMX_OK is true. */
44910 void
44912 {
44919 rtx x;
44922 {
44932 }
44934 /* Constants are best loaded from the constant pool. */
44936 {
44939 }
44941 /* If all values are identical, broadcast the value. */
44947 /* Values where only one field is non-constant are best loaded from
44948 the pool and overwritten via move later. */
44950 {
44954 one_var))
44959 }
44962 }
44964 void
44966 {
44969 machine_mode half_mode;
44971 rtx tmp;
44973 = {
44980 };
44982 = {
44989 };
44995 {
44999 {
45004 else
45008 }
45020 else
45026 {
45029 /* For the two element vectors, we implement a VEC_CONCAT with
45030 the extraction of the other element. */
45037 else
45042 }
45051 {
45057 /* tmp = target = A B C D */
45059 /* target = A A B B */
45061 /* target = X A B B */
45063 /* target = A X C D */
45070 /* tmp = target = A B C D */
45072 /* tmp = X B C D */
45074 /* target = A B X D */
45081 /* tmp = target = A B C D */
45083 /* tmp = X B C D */
45085 /* target = A B X D */
45093 }
45101 /* Element 0 handled by vec_merge below. */
45103 {
45106 }
45109 {
45110 /* With SSE2, use integer shuffles to swap element 0 and ELT,
45111 store into element 0, then shuffle them back. */
45128 }
45129 else
45130 {
45131 /* For SSE1, we have to reuse the V4SF code. */
45135 }
45188 half:
45189 /* Compute offset. */
45195 /* Extract the half. */
45199 /* Put val in tmp at elt. */
45202 /* Put it back. */
45208 {
45211 }
45216 {
45219 }
45224 {
45227 }
45232 {
45235 }
45240 {
45243 }
45248 {
45251 }
45256 }
45259 {
45265 }
45267 {
45271 }
45272 else
45273 {
45282 }
45283 }
45285 void
45287 {
45291 rtx tmp;
45294 {
45299 /* FALLTHRU */
45312 {
45332 }
45344 {
45346 {
45366 }
45370 }
45371 else
45372 {
45373 /* For SSE1, we have to reuse the V4SF code. */
45377 }
45393 {
45397 else
45401 }
45406 {
45410 else
45414 }
45419 {
45423 else
45427 }
45432 {
45436 else
45440 }
45445 {
45449 else
45453 }
45458 {
45462 else
45466 }
45471 {
45475 else
45479 }
45484 {
45488 else
45492 }
45499 else
45508 else
45517 else
45526 else
45532 /* ??? Could extract the appropriate HImode element and shift. */
45535 }
45538 {
45542 /* Let the rtl optimizers know about the zero extension performed. */
45544 {
45547 }
45550 }
45551 else
45552 {
45559 }
45560 }
45562 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
45563 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
45564 The upper bits of DEST are undefined, though they shouldn't cause
45565 exceptions (some bits from src or all zeros are ok). */
45567 static void
45569 {
45572 {
45576 else
45594 else
45601 else
45609 {
45614 const1_rtx);
45615 }
45616 else
45617 {
45621 }
45643 else
45665 }
45669 }
45671 /* Expand a vector reduction. FN is the binary pattern to reduce;
45672 DEST is the destination; IN is the input vector. */
45674 void
45676 {
45681 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
45685 {
45688 }
45693 {
45698 else
45702 }
45703 }
45704 \f
45705 /* Target hook for scalar_mode_supported_p. */
45706 static bool
45708 {
45713 else
45715 }
45717 /* Implements target hook vector_mode_supported_p. */
45718 static bool
45720 {
45734 }
45736 /* Implement target hook libgcc_floating_mode_supported_p. */
45737 static bool
45739 {
45741 {
45748 #ifdef IX86_NO_LIBGCC_TFMODE
45750 #elif defined IX86_MAYBE_NO_LIBGCC_TFMODE
45752 #else
45754 #endif
45758 }
45759 }
45761 /* Target hook for c_mode_for_suffix. */
45762 static machine_mode
45764 {
45771 }
45773 /* Worker function for TARGET_MD_ASM_ADJUST.
45775 We implement asm flag outputs, and maintain source compatibility
45776 with the old cc0-based compiler. */
45782 {
45790 {
45796 {
45799 }
45809 {
45858 }
45860 {
45863 }
45869 {
45870 /* This is the first asm flag output. Here we put the flags
45871 register in as the real output and adjust the condition to
45872 allow it. */
45876 }
45877 else
45878 {
45879 /* We don't need the flags register as output twice. */
45882 }
45889 {
45892 }
45898 {
45904 {
45909 }
45910 else
45912 }
45915 {
45920 }
45921 else
45923 }
45929 else
45930 {
45931 /* If we had no asm flag outputs, clobber the flags. */
45935 }
45936 }
45938 /* Implements target vector targetm.asm.encode_section_info. */
45940 static void ATTRIBUTE_UNUSED
45942 {
45947 }
45949 /* Worker function for REVERSE_CONDITION. */
45951 enum rtx_code
45953 {
45957 }
45959 /* Output code to perform an x87 FP register move, from OPERANDS[1]
45960 to OPERANDS[0]. */
45964 {
45966 {
45969 {
45973 }
45977 }
45979 {
45983 else
45984 {
45985 /* There is no non-popping store to memory for XFmode.
45986 So if we need one, follow the store with a load. */
45989 else
45991 }
45992 }
45993 else
45995 }
45997 /* Output code to perform a conditional jump to LABEL, if C2 flag in
45998 FP status register is set. */
46000 void
46002 {
46004 rtx temp;
46009 {
46014 }
46015 else
46016 {
46021 }
46025 pc_rtx);
46030 }
46032 /* Output code to perform a log1p XFmode calculation. */
46035 {
46041 rtx test;
46047 XFmode));
46061 }
46063 /* Emit code for round calculation. */
46065 {
46072 rtx insn;
46077 {
46089 }
46092 {
46113 }
46121 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
46123 /* scratch = fxam(op1) */
46126 UNSPEC_FXAM)));
46127 /* e1 = fabs(op1) */
46130 /* e2 = e1 + 0.5 */
46134 /* res = floor(e2) */
46136 {
46140 }
46141 else
46145 {
46148 {
46155 UNSPEC_TRUNC_NOOP)));
46156 }
46172 }
46174 /* flags = signbit(a) */
46177 /* if (flags) then res = -res */
46181 pc_rtx);
46192 }
46194 /* Output code to perform a Newton-Rhapson approximation of a single precision
46195 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
46198 {
46206 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
46210 /* x0 = rcp(b) estimate */
46213 UNSPEC_RCP14)));
46214 else
46216 UNSPEC_RCP)));
46218 /* e0 = x0 * b */
46221 /* e0 = x0 * e0 */
46224 /* e1 = x0 + x0 */
46227 /* x1 = e1 - e0 */
46230 /* res = a * x1 */
46232 }
46234 /* Output code to perform a Newton-Rhapson approximation of a
46235 single precision floating point [reciprocal] square root. */
46239 {
46241 REAL_VALUE_TYPE r;
46258 {
46261 /* There is no 512-bit rsqrt. There is however rsqrt14. */
46264 }
46266 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
46267 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
46271 /* x0 = rsqrt(a) estimate */
46273 unspec)));
46275 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
46277 {
46285 /* Handle masked compare. */
46287 {
46289 /* Imm value 0x4 corresponds to not-equal comparison. */
46292 }
46293 else
46294 {
46298 }
46299 }
46301 /* e0 = x0 * a */
46303 /* e1 = e0 * x0 */
46306 /* e2 = e1 - 3. */
46312 /* e3 = -.5 * x0 */
46314 else
46315 /* e3 = -.5 * e0 */
46317 /* ret = e2 * e3 */
46319 }
46321 #ifdef TARGET_SOLARIS
46322 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
46324 static void
46326 tree decl)
46327 {
46328 /* With Binutils 2.15, the "@unwind" marker must be specified on
46329 every occurrence of the ".eh_frame" section, not just the first
46330 one. */
46333 {
46337 }
46339 #ifndef USE_GAS
46341 {
46344 }
46345 #endif
46348 }
46351 /* Return the mangling of TYPE if it is an extended fundamental type. */
46355 {
46363 {
46365 /* __float128 is "g". */
46368 /* "long double" or __float80 is "e". */
46372 }
46373 }
46375 /* For 32-bit code we can save PIC register setup by using
46376 __stack_chk_fail_local hidden function instead of calling
46377 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
46378 register, so it is better to call __stack_chk_fail directly. */
46380 static tree ATTRIBUTE_UNUSED
46382 {
46383 return TARGET_64BIT
46386 }
46388 /* Select a format to encode pointers in exception handling data. CODE
46389 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
46390 true if the symbol may be affected by dynamic relocations.
46392 ??? All x86 object file formats are capable of representing this.
46393 After all, the relocation needed is the same as for the call insn.
46394 Whether or not a particular assembler allows us to enter such, I
46395 guess we'll have to see. */
46396 int
46398 {
46400 {
46407 }
46412 }
46413 \f
46414 /* Expand copysign from SIGN to the positive value ABS_VALUE
46415 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
46416 the sign-bit. */
46417 static void
46419 {
46423 {
46424 machine_mode vmode;
46430 else
46435 {
46436 /* We need to generate a scalar mode mask in this case. */
46441 }
46442 }
46443 else
46447 }
46449 /* Expand fabs (OP0) and return a new rtx that holds the result. The
46450 mask for masking out the sign-bit is stored in *SMASK, if that is
46451 non-null. */
46452 static rtx
46454 {
46463 else
46467 {
46468 /* We need to generate a scalar mode mask in this case. */
46473 }
46480 }
46482 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
46483 swapping the operands if SWAP_OPERANDS is true. The expanded
46484 code is a forward jump to a newly created label in case the
46485 comparison is true. The generated label rtx is returned. */
46489 {
46492 rtx tmp;
46507 }
46509 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
46510 using comparison code CODE. Operands are swapped for the comparison if
46511 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
46512 static rtx
46515 {
46528 }
46530 /* Generate and return a rtx of mode MODE for 2**n where n is the number
46531 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
46532 static rtx
46534 {
46535 REAL_VALUE_TYPE TWO52r;
46536 rtx TWO52;
46543 }
46545 /* Expand SSE sequence for computing lround from OP1 storing
46546 into OP0. */
46547 void
46549 {
46550 /* C code for the stuff we're doing below:
46551 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
46552 return (long)tmp;
46553 */
46557 rtx adj;
46559 /* load nextafter (0.5, 0.0) */
46564 /* adj = copysign (0.5, op1) */
46568 /* adj = op1 + adj */
46571 /* op0 = (imode)adj */
46573 }
46575 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
46576 into OPERAND0. */
46577 void
46579 {
46580 /* C code for the stuff we're doing below (for do_floor):
46581 xi = (long)op1;
46582 xi -= (double)xi > op1 ? 1 : 0;
46583 return xi;
46584 */
46590 /* reg = (long)op1 */
46594 /* freg = (double)reg */
46598 /* ireg = (freg > op1) ? ireg - 1 : ireg */
46609 }
46611 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
46612 result in OPERAND0. */
46613 void
46615 {
46616 /* C code for the stuff we're doing below:
46617 xa = fabs (operand1);
46618 if (!isless (xa, 2**52))
46619 return operand1;
46620 xa = xa + 2**52 - 2**52;
46621 return copysign (xa, operand1);
46622 */
46630 /* xa = abs (operand1) */
46633 /* if (!isless (xa, TWO52)) goto label; */
46646 }
46648 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46649 into OPERAND0. */
46650 void
46652 {
46653 /* C code for the stuff we expand below.
46654 double xa = fabs (x), x2;
46655 if (!isless (xa, TWO52))
46656 return x;
46657 xa = xa + TWO52 - TWO52;
46658 x2 = copysign (xa, x);
46659 Compensate. Floor:
46660 if (x2 > x)
46661 x2 -= 1;
46662 Compensate. Ceil:
46663 if (x2 < x)
46664 x2 -= -1;
46665 return x2;
46666 */
46673 /* Temporary for holding the result, initialized to the input
46674 operand to ease control flow. */
46678 /* xa = abs (operand1) */
46681 /* if (!isless (xa, TWO52)) goto label; */
46684 /* xa = xa + TWO52 - TWO52; */
46688 /* xa = copysign (xa, operand1) */
46691 /* generate 1.0 or -1.0 */
46696 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46699 /* We always need to subtract here to preserve signed zero. */
46708 }
46710 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46711 into OPERAND0. */
46712 void
46714 {
46715 /* C code for the stuff we expand below.
46716 double xa = fabs (x), x2;
46717 if (!isless (xa, TWO52))
46718 return x;
46719 x2 = (double)(long)x;
46720 Compensate. Floor:
46721 if (x2 > x)
46722 x2 -= 1;
46723 Compensate. Ceil:
46724 if (x2 < x)
46725 x2 += 1;
46726 if (HONOR_SIGNED_ZEROS (mode))
46727 return copysign (x2, x);
46728 return x2;
46729 */
46736 /* Temporary for holding the result, initialized to the input
46737 operand to ease control flow. */
46741 /* xa = abs (operand1) */
46744 /* if (!isless (xa, TWO52)) goto label; */
46747 /* xa = (double)(long)x */
46752 /* generate 1.0 */
46755 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46769 }
46771 /* Expand SSE sequence for computing round from OPERAND1 storing
46772 into OPERAND0. Sequence that works without relying on DImode truncation
46773 via cvttsd2siq that is only available on 64bit targets. */
46774 void
46776 {
46777 /* C code for the stuff we expand below.
46778 double xa = fabs (x), xa2, x2;
46779 if (!isless (xa, TWO52))
46780 return x;
46781 Using the absolute value and copying back sign makes
46782 -0.0 -> -0.0 correct.
46783 xa2 = xa + TWO52 - TWO52;
46784 Compensate.
46785 dxa = xa2 - xa;
46786 if (dxa <= -0.5)
46787 xa2 += 1;
46788 else if (dxa > 0.5)
46789 xa2 -= 1;
46790 x2 = copysign (xa2, x);
46791 return x2;
46792 */
46799 /* Temporary for holding the result, initialized to the input
46800 operand to ease control flow. */
46804 /* xa = abs (operand1) */
46807 /* if (!isless (xa, TWO52)) goto label; */
46810 /* xa2 = xa + TWO52 - TWO52; */
46814 /* dxa = xa2 - xa; */
46817 /* generate 0.5, 1.0 and -0.5 */
46823 /* Compensate. */
46825 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
46829 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
46834 /* res = copysign (xa2, operand1) */
46841 }
46843 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46844 into OPERAND0. */
46845 void
46847 {
46848 /* C code for SSE variant we expand below.
46849 double xa = fabs (x), x2;
46850 if (!isless (xa, TWO52))
46851 return x;
46852 x2 = (double)(long)x;
46853 if (HONOR_SIGNED_ZEROS (mode))
46854 return copysign (x2, x);
46855 return x2;
46856 */
46863 /* Temporary for holding the result, initialized to the input
46864 operand to ease control flow. */
46868 /* xa = abs (operand1) */
46871 /* if (!isless (xa, TWO52)) goto label; */
46874 /* x = (double)(long)x */
46886 }
46888 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46889 into OPERAND0. */
46890 void
46892 {
46897 /* C code for SSE variant we expand below.
46898 double xa = fabs (x), x2;
46899 if (!isless (xa, TWO52))
46900 return x;
46901 xa2 = xa + TWO52 - TWO52;
46902 Compensate:
46903 if (xa2 > xa)
46904 xa2 -= 1.0;
46905 x2 = copysign (xa2, x);
46906 return x2;
46907 */
46911 /* Temporary for holding the result, initialized to the input
46912 operand to ease control flow. */
46916 /* xa = abs (operand1) */
46919 /* if (!isless (xa, TWO52)) goto label; */
46922 /* res = xa + TWO52 - TWO52; */
46927 /* generate 1.0 */
46930 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
46937 /* res = copysign (res, operand1) */
46944 }
46946 /* Expand SSE sequence for computing round from OPERAND1 storing
46947 into OPERAND0. */
46948 void
46950 {
46951 /* C code for the stuff we're doing below:
46952 double xa = fabs (x);
46953 if (!isless (xa, TWO52))
46954 return x;
46955 xa = (double)(long)(xa + nextafter (0.5, 0.0));
46956 return copysign (xa, x);
46957 */
46964 /* Temporary for holding the result, initialized to the input
46965 operand to ease control flow. */
46973 /* load nextafter (0.5, 0.0) */
46978 /* xa = xa + 0.5 */
46982 /* xa = (double)(int64_t)xa */
46987 /* res = copysign (xa, operand1) */
46994 }
46996 /* Expand SSE sequence for computing round
46997 from OP1 storing into OP0 using sse4 round insn. */
46998 void
47000 {
47009 {
47020 }
47022 /* round (a) = trunc (a + copysign (0.5, a)) */
47024 /* load nextafter (0.5, 0.0) */
47030 /* e1 = copysign (0.5, op1) */
47034 /* e2 = op1 + e1 */
47037 /* res = trunc (e2) */
47042 }
47043 \f
47045 /* Table of valid machine attributes. */
47047 {
47048 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
47049 affects_type_identity } */
47050 /* Stdcall attribute says callee is responsible for popping arguments
47051 if they are not variable. */
47054 /* Fastcall attribute says callee is responsible for popping arguments
47055 if they are not variable. */
47058 /* Thiscall attribute says callee is responsible for popping arguments
47059 if they are not variable. */
47062 /* Cdecl attribute says the callee is a normal C declaration */
47065 /* Regparm attribute specifies how many integer arguments are to be
47066 passed in registers. */
47069 /* Sseregparm attribute says we are using x86_64 calling conventions
47070 for FP arguments. */
47073 /* The transactional memory builtins are implicitly regparm or fastcall
47074 depending on the ABI. Override the generic do-nothing attribute that
47075 these builtins were declared with. */
47078 /* force_align_arg_pointer says this function realigns the stack at entry. */
47081 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
47086 #endif
47091 #ifdef SUBTARGET_ATTRIBUTE_TABLE
47092 SUBTARGET_ATTRIBUTE_TABLE,
47093 #endif
47094 /* ms_abi and sysv_abi calling convention function attributes. */
47101 /* End element. */
47103 };
47105 /* Implement targetm.vectorize.builtin_vectorization_cost. */
47106 static int
47109 {
47113 {
47158 }
47159 }
47161 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
47162 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
47163 insn every time. */
47167 /* Initialize vselect_insn. */
47169 static void
47171 {
47173 rtx x;
47184 }
47186 /* Construct (set target (vec_select op0 (parallel perm))) and
47187 return true if that's a valid instruction in the active ISA. */
47189 static bool
47192 {
47218 }
47220 /* Similar, but generate a vec_concat from op0 and op1 as well. */
47222 static bool
47226 {
47227 machine_mode v2mode;
47228 rtx x;
47243 }
47245 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47246 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
47248 static bool
47250 {
47259 && (TARGET_AVX512BW
47261 ;
47263 ;
47265 ;
47267 ;
47268 else
47271 /* This is a blend, not a permute. Elements must stay in their
47272 respective lanes. */
47274 {
47278 }
47283 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
47284 decision should be extracted elsewhere, so that we only try that
47285 sequence once all budget==3 options have been tried. */
47292 {
47322 /* See if bytes move in pairs so we can use pblendw with
47323 an immediate argument, rather than pblendvb with a vector
47324 argument. */
47327 {
47328 use_pblendvb:
47332 finish_pblendvb:
47338 else
47343 }
47348 /* FALLTHRU */
47350 do_subreg:
47357 /* See if bytes move in pairs. If not, vpblendvb must be used. */
47361 /* See if bytes move in quadruplets. If yes, vpblendd
47362 with immediate can be used. */
47367 {
47368 /* See if bytes move the same in both lanes. If yes,
47369 vpblendw with immediate can be used. */
47374 /* Use vpblendw. */
47379 }
47381 /* Use vpblendd. */
47388 /* See if words move in pairs. If yes, vpblendd can be used. */
47393 {
47394 /* See if words move the same in both lanes. If not,
47395 vpblendvb must be used. */
47398 {
47399 /* Use vpblendvb. */
47409 }
47411 /* Use vpblendw. */
47415 }
47417 /* Use vpblendd. */
47424 /* Use vpblendd. */
47432 }
47435 {
47452 }
47456 else
47459 /* This matches five different patterns with the different modes. */
47467 }
47469 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47470 in terms of the variable form of vpermilps.
47472 Note that we will have already failed the immediate input vpermilps,
47473 which requires that the high and low part shuffle be identical; the
47474 variable form doesn't require that. */
47476 static bool
47478 {
47485 /* We can only permute within the 128-bit lane. */
47487 {
47491 }
47497 {
47500 /* Within each 128-bit lane, the elements of op0 are numbered
47501 from 0 and the elements of op1 are numbered from 4. */
47508 }
47515 }
47517 /* Return true if permutation D can be performed as VMODE permutation
47518 instead. */
47520 static bool
47522 {
47537 else
47543 }
47545 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47546 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
47548 static bool
47550 {
47559 {
47561 {
47564 {
47568 /* Use vperm2i128 insn. The pattern uses
47569 V4DImode instead of V2TImode. */
47582 }
47584 }
47585 }
47586 else
47587 {
47589 {
47592 }
47594 {
47598 /* V4DImode should be already handled through
47599 expand_vselect by vpermq instruction. */
47606 {
47607 /* First see if vpermq can be used for
47608 V8SImode/V16HImode/V32QImode. */
47610 {
47618 {
47622 }
47624 }
47626 /* Next see if vpermd can be used. */
47629 }
47630 /* Or if vpermps can be used. */
47635 {
47636 /* vpshufb only works intra lanes, it is not
47637 possible to shuffle bytes in between the lanes. */
47641 }
47642 }
47644 {
47648 /* If vpermq didn't work, vpshufb won't work either. */
47656 {
47657 /* First see if vpermq can be used for
47658 V16SImode/V32HImode/V64QImode. */
47660 {
47668 {
47672 }
47674 }
47676 /* Next see if vpermd can be used. */
47679 }
47680 /* Or if vpermps can be used. */
47684 {
47685 /* vpshufb only works intra lanes, it is not
47686 possible to shuffle bytes in between the lanes. */
47690 }
47691 }
47692 else
47694 }
47705 else
47706 {
47714 else
47718 {
47722 }
47723 }
47734 {
47749 else
47751 }
47752 else
47753 {
47756 }
47761 }
47763 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
47764 in a single instruction. */
47766 static bool
47768 {
47772 /* Check plain VEC_SELECT first, because AVX has instructions that could
47773 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
47774 input where SEL+CONCAT may not. */
47776 {
47782 {
47788 }
47791 {
47795 }
47797 {
47798 /* Use vpbroadcast{b,w,d}. */
47801 {
47844 /* For other modes prefer other shuffles this function creates. */
47846 }
47848 {
47852 }
47853 }
47858 /* There are plenty of patterns in sse.md that are written for
47859 SEL+CONCAT and are not replicated for a single op. Perhaps
47860 that should be changed, to avoid the nastiness here. */
47862 /* Recognize interleave style patterns, which means incrementing
47863 every other permutation operand. */
47865 {
47868 }
47873 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
47875 {
47877 {
47882 }
47887 }
47888 }
47890 /* Finally, try the fully general two operand permute. */
47895 /* Recognize interleave style patterns with reversed operands. */
47897 {
47899 {
47903 else
47906 }
47911 }
47913 /* Try the SSE4.1 blend variable merge instructions. */
47917 /* Try one of the AVX vpermil variable permutations. */
47921 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
47922 vpshufb, vpermd, vpermps or vpermq variable permutation. */
47926 /* Try the AVX2 vpalignr instruction. */
47930 /* Try the AVX512F vpermi2 instructions. */
47935 }
47937 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47938 in terms of a pair of pshuflw + pshufhw instructions. */
47940 static bool
47942 {
47950 /* The two permutations only operate in 64-bit lanes. */
47961 /* Emit the pshuflw. */
47968 /* Emit the pshufhw. */
47976 }
47978 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47979 the permutation using the SSSE3 palignr instruction. This succeeds
47980 when all of the elements in PERM fit within one vector and we merely
47981 need to shift them down so that a single vector permutation has a
47982 chance to succeed. If SINGLE_INSN_ONLY_P, succeed if only
47983 the vpalignr instruction itself can perform the requested permutation. */
47985 static bool
47987 {
47994 /* Even with AVX, palignr only operates on 128-bit vectors,
47995 in AVX2 palignr operates on both 128-bit lanes. */
48005 {
48009 {
48012 }
48021 }
48024 {
48033 }
48035 /* Given that we have SSSE3, we know we'll be able to implement the
48036 single operand permutation after the palignr with pshufb for
48037 128-bit vectors. If SINGLE_INSN_ONLY_P, in_order has to be computed
48038 first. */
48044 {
48049 }
48053 {
48059 else
48064 }
48070 /* For AVX2, test whether we can permute the result in one instruction. */
48072 {
48077 }
48081 {
48085 }
48086 else
48087 {
48092 shift));
48093 }
48097 /* Test for the degenerate case where the alignment by itself
48098 produces the desired permutation. */
48100 {
48103 }
48109 }
48111 /* A subroutine of ix86_expand_vec_perm_const_1. Try to simplify
48112 the permutation using the SSE4_1 pblendv instruction. Potentially
48113 reduces permutation from 2 pshufb and or to 1 pshufb and pblendv. */
48115 static bool
48117 {
48123 /* Use the same checks as in expand_vec_perm_blend. */
48127 ;
48129 ;
48131 ;
48132 else
48135 /* Figure out where permutation elements stay not in their
48136 respective lanes. */
48138 {
48142 }
48143 /* We can pblend the part where elements stay not in their
48144 respective lanes only when these elements are all in one
48145 half of a permutation.
48146 {0 1 8 3 4 5 9 7} is ok as 8, 9 are at not at their respective
48147 lanes, but both 8 and 9 >= 8
48148 {0 1 8 3 4 5 2 7} is not ok as 2 and 8 are not at their
48149 respective lanes and 8 >= 8, but 2 not. */
48155 /* First we apply one operand permutation to the part where
48156 elements stay not in their respective lanes. */
48160 else
48172 else
48177 /* Next we put permuted elements into their positions. */
48181 else
48191 }
48195 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48196 a two vector permutation into a single vector permutation by using
48197 an interleave operation to merge the vectors. */
48199 static bool
48201 {
48210 {
48213 }
48215 {
48218 /* For 32-byte modes allow even d->one_operand_p.
48219 The lack of cross-lane shuffling in some instructions
48220 might prevent a single insn shuffle. */
48223 /* If expand_vec_perm_interleave3 can expand this into
48224 a 3 insn sequence, give up and let it be expanded as
48225 3 insn sequence. While that is one insn longer,
48226 it doesn't need a memory operand and in the common
48227 case that both interleave low and high permutations
48228 with the same operands are adjacent needs 4 insns
48229 for both after CSE. */
48232 }
48233 else
48236 /* Examine from whence the elements come. */
48245 {
48248 /* Split the two input vectors into 4 halves. */
48254 /* If the elements from the low halves use interleave low, and similarly
48255 for interleave high. If the elements are from mis-matched halves, we
48256 can use shufps for V4SF/V4SI or do a DImode shuffle. */
48258 {
48259 /* punpckl* */
48261 {
48266 }
48269 }
48271 {
48272 /* punpckh* */
48274 {
48279 }
48282 }
48284 {
48285 /* shufps */
48287 {
48292 }
48294 {
48295 /* shufpd */
48300 }
48301 }
48303 {
48304 /* shufps */
48306 {
48311 }
48313 {
48314 /* shufpd */
48319 }
48320 }
48321 else
48323 }
48324 else
48325 {
48330 /* Split the two input vectors into 8 quarters. */
48336 {
48339 }
48342 {
48346 }
48348 {
48351 }
48354 {
48356 {
48357 /* Attempt to increase the likelihood that dfinal
48358 shuffle will be intra-lane. */
48360 }
48362 /* vperm2f128 or vperm2i128. */
48364 {
48369 }
48374 {
48378 {
48381 }
48382 }
48383 }
48388 {
48389 /* vpunpckl* */
48391 {
48400 }
48401 }
48404 {
48405 /* vpunpckh* */
48407 {
48416 }
48417 }
48418 else
48420 }
48422 /* Use the remapping array set up above to move the elements from their
48423 swizzled locations into their final destinations. */
48426 {
48429 /* If same_halves is true, both halves of the remapped vector are the
48430 same. Avoid cross-lane accesses if possible. */
48432 {
48435 }
48436 else
48438 }
48440 {
48443 }
48447 /* Test if the final remap can be done with a single insn. For V4SFmode or
48448 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
48461 {
48464 }
48471 }
48473 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48474 a single vector cross-lane permutation into vpermq followed
48475 by any of the single insn permutations. */
48477 static bool
48479 {
48493 {
48496 }
48499 {
48504 }
48517 {
48524 }
48531 {
48536 ;
48539 else
48541 }
48550 }
48552 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
48553 a vector permutation using two instructions, vperm2f128 resp.
48554 vperm2i128 followed by any single in-lane permutation. */
48556 static bool
48558 {
48572 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
48573 immediate. For perm < 16 the second permutation uses
48574 d->op0 as first operand, for perm >= 16 it uses d->op1
48575 as first operand. The second operand is the result of
48576 vperm2[fi]128. */
48578 {
48579 /* Ignore permutations which do not move anything cross-lane. */
48581 {
48582 /* The second shuffle for e.g. V4DFmode has
48583 0123 and ABCD operands.
48584 Ignore AB23, as 23 is already in the second lane
48585 of the first operand. */
48587 /* And 01CD, as 01 is in the first lane of the first
48588 operand. */
48590 /* And 4567, as then the vperm2[fi]128 doesn't change
48591 anything on the original 4567 second operand. */
48593 }
48594 else
48595 {
48596 /* The second shuffle for e.g. V4DFmode has
48597 4567 and ABCD operands.
48598 Ignore AB67, as 67 is already in the second lane
48599 of the first operand. */
48601 /* And 45CD, as 45 is in the first lane of the first
48602 operand. */
48604 /* And 0123, as then the vperm2[fi]128 doesn't change
48605 anything on the original 0123 first operand. */
48607 }
48610 {
48616 else
48618 }
48621 {
48625 }
48626 else
48630 {
48634 /* Found a usable second shuffle. dfirst will be
48635 vperm2f128 on d->op0 and d->op1. */
48647 /* And dsecond is some single insn shuffle, taking
48648 d->op0 and result of vperm2f128 (if perm < 16) or
48649 d->op1 and result of vperm2f128 (otherwise). */
48658 }
48660 /* For one operand, the only useful vperm2f128 permutation is 0x01
48661 aka lanes swap. */
48664 }
48667 }
48669 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48670 a two vector permutation using 2 intra-lane interleave insns
48671 and cross-lane shuffle for 32-byte vectors. */
48673 static bool
48675 {
48682 ;
48684 ;
48685 else
48700 {
48704 else
48710 else
48716 else
48722 else
48728 else
48734 else
48739 }
48743 }
48745 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
48746 a single vector permutation using a single intra-lane vector
48747 permutation, vperm2f128 swapping the lanes and vblend* insn blending
48748 the non-swapped and swapped vectors together. */
48750 static bool
48752 {
48760 || TARGET_AVX2
48769 {
48776 }
48811 }
48813 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
48814 permutation using two vperm2f128, followed by a vshufpd insn blending
48815 the two vectors together. */
48817 static bool
48819 {
48862 }
48864 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
48865 permutation with two pshufb insns and an ior. We should have already
48866 failed all two instruction sequences. */
48868 static bool
48870 {
48884 /* Generate two permutation masks. If the required element is within
48885 the given vector it is shuffled into the proper lane. If the required
48886 element is in the other vector, force a zero into the lane by setting
48887 bit 7 in the permutation mask. */
48890 {
48897 {
48900 }
48901 }
48925 }
48927 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
48928 with two vpshufb insns, vpermq and vpor. We should have already failed
48929 all two or three instruction sequences. */
48931 static bool
48933 {
48948 /* Generate two permutation masks. If the required element is within
48949 the same lane, it is shuffled in. If the required element from the
48950 other lane, force a zero by setting bit 7 in the permutation mask.
48951 In the other mask the mask has non-negative elements if element
48952 is requested from the other lane, but also moved to the other lane,
48953 so that the result of vpshufb can have the two V2TImode halves
48954 swapped. */
48957 {
48962 {
48965 }
48966 }
48975 /* Swap the 128-byte lanes of h into hp. */
48979 const1_rtx));
48996 }
48998 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48999 and extract-odd permutations of two V32QImode and V16QImode operand
49000 with two vpshufb insns, vpor and vpermq. We should have already
49001 failed all two or three instruction sequences. */
49003 static bool
49005 {
49024 /* Generate two permutation masks. In the first permutation mask
49025 the first quarter will contain indexes for the first half
49026 of the op0, the second quarter will contain bit 7 set, third quarter
49027 will contain indexes for the second half of the op0 and the
49028 last quarter bit 7 set. In the second permutation mask
49029 the first quarter will contain bit 7 set, the second quarter
49030 indexes for the first half of the op1, the third quarter bit 7 set
49031 and last quarter indexes for the second half of the op1.
49032 I.e. the first mask e.g. for V32QImode extract even will be:
49033 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
49034 (all values masked with 0xf except for -128) and second mask
49035 for extract even will be
49036 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
49039 {
49045 {
49048 }
49049 }
49068 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
49076 }
49078 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
49079 and extract-odd permutations of two V16QI, V8HI, V16HI or V32QI operands
49080 with two "and" and "pack" or two "shift" and "pack" insns. We should
49081 have already failed all two instruction sequences. */
49083 static bool
49085 {
49089 machine_mode half_mode;
49098 {
49100 /* Required for "pack". */
49111 /* No check as all instructions are SSE2. */
49142 /* Only V8HI, V16QI, V16HI and V32QI modes are more profitable than
49143 general shuffles. */
49145 }
49147 /* Check that permutation is even or odd. */
49162 {
49169 }
49170 else
49171 {
49178 }
49179 /* In AVX2 for 256 bit case we need to permute pack result. */
49181 {
49187 const0_rtx,
49188 const2_rtx,
49189 const1_rtx,
49192 }
49193 else
49197 }
49199 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
49200 and extract-odd permutations. */
49202 static bool
49204 {
49208 {
49215 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
49219 /* Now an unpck[lh]pd will produce the result required. */
49222 else
49228 {
49237 /* Shuffle within the 128-bit lanes to produce:
49238 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
49242 /* Shuffle the lanes around to produce:
49243 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
49247 /* Shuffle within the 128-bit lanes to produce:
49248 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
49251 /* Shuffle within the 128-bit lanes to produce:
49252 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
49255 /* Shuffle the lanes around to produce:
49256 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
49259 }
49266 /* These are always directly implementable by expand_vec_perm_1. */
49274 else
49275 {
49278 /* We need 2*log2(N)-1 operations to achieve odd/even
49279 with interleave. */
49288 else
49291 }
49303 {
49308 else
49313 {
49318 }
49320 }
49328 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
49332 /* Now an vpunpck[lh]qdq will produce the result required. */
49335 else
49342 {
49347 else
49352 {
49357 }
49359 }
49370 /* Shuffle the lanes around into
49371 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
49379 /* Swap the 2nd and 3rd position in each lane into
49380 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
49386 /* Now an vpunpck[lh]qdq will produce
49387 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
49391 else
49400 }
49403 }
49405 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
49406 extract-even and extract-odd permutations. */
49408 static bool
49410 {
49422 }
49424 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
49425 permutations. We assume that expand_vec_perm_1 has already failed. */
49427 static bool
49429 {
49437 {
49440 /* These are special-cased in sse.md so that we can optionally
49441 use the vbroadcast instruction. They expand to two insns
49442 if the input happens to be in a register. */
49449 /* These are always implementable using standard shuffle patterns. */
49454 /* These can be implemented via interleave. We save one insn by
49455 stopping once we have promoted to V4SImode and then use pshufd. */
49458 do
49459 {
49460 rtx dest;
49466 {
49470 }
49477 }
49493 /* For AVX2 broadcasts of the first element vpbroadcast* or
49494 vpermq should be used by expand_vec_perm_1. */
49500 }
49501 }
49503 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
49504 broadcast permutations. */
49506 static bool
49508 {
49520 }
49522 /* Implement arbitrary permutations of two V64QImode operands
49523 will 2 vpermi2w, 2 vpshufb and one vpor instruction. */
49524 static bool
49526 {
49536 machine_mode vmode;
49542 {
49549 }
49551 /* Prepare permutations such that the first one takes care of
49552 putting the even bytes into the right positions or one higher
49553 positions (ds[0]) and the second one takes care of
49554 putting the odd bytes into the right positions or one below
49555 (ds[1]). */
49558 {
49561 {
49564 }
49565 else
49566 {
49569 }
49570 }
49592 }
49594 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
49595 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
49596 all the shorter instruction sequences. */
49598 static bool
49600 {
49616 /* Generate 4 permutation masks. If the required element is within
49617 the same lane, it is shuffled in. If the required element from the
49618 other lane, force a zero by setting bit 7 in the permutation mask.
49619 In the other mask the mask has non-negative elements if element
49620 is requested from the other lane, but also moved to the other lane,
49621 so that the result of vpshufb can have the two V2TImode halves
49622 swapped. */
49625 {
49630 }
49636 {
49644 }
49647 {
49649 {
49652 }
49659 }
49661 /* Swap the 128-byte lanes of h[X]. */
49663 {
49669 const1_rtx));
49671 }
49674 {
49676 {
49679 }
49685 }
49688 {
49690 {
49694 }
49697 }
49707 }
49709 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
49710 With all of the interface bits taken care of, perform the expansion
49711 in D and return true on success. */
49713 static bool
49715 {
49716 /* Try a single instruction expansion. */
49720 /* Try sequences of two instructions. */
49743 /* Try sequences of three instructions. */
49760 /* Try sequences of four instructions. */
49771 /* ??? Look for narrow permutations whose element orderings would
49772 allow the promotion to a wider mode. */
49774 /* ??? Look for sequences of interleave or a wider permute that place
49775 the data into the correct lanes for a half-vector shuffle like
49776 pshuf[lh]w or vpermilps. */
49778 /* ??? Look for sequences of interleave that produce the desired results.
49779 The combinatorics of punpck[lh] get pretty ugly... */
49784 /* Even longer sequences. */
49789 }
49791 /* If a permutation only uses one operand, make it clear. Returns true
49792 if the permutation references both operands. */
49794 static bool
49796 {
49804 {
49810 {
49813 }
49814 /* The elements of PERM do not suggest that only the first operand
49815 is used, but both operands are identical. Allow easier matching
49816 of the permutation by folding the permutation into the single
49817 input vector. */
49818 /* FALLTHRU */
49829 }
49832 }
49834 bool
49836 {
49841 rtx sel;
49858 {
49863 }
49870 /* If the selector says both arguments are needed, but the operands are the
49871 same, the above tried to expand with one_operand_p and flattened selector.
49872 If that didn't work, retry without one_operand_p; we succeeded with that
49873 during testing. */
49875 {
49879 }
49882 }
49884 /* Implement targetm.vectorize.vec_perm_const_ok. */
49886 static bool
49889 {
49898 /* Given sufficient ISA support we can just return true here
49899 for selected vector modes. */
49901 {
49907 /* All implementable with a single vpermi2 insn. */
49912 /* All implementable with a single vpermi2 insn. */
49917 /* Implementable with 2 vpermi2, 2 vpshufb and 1 or insn. */
49925 /* All implementable with a single vpermi2 insn. */
49930 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49935 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49942 /* All implementable with a single vpperm insn. */
49945 /* All implementable with 2 pshufb + 1 ior. */
49951 /* All implementable with shufpd or unpck[lh]pd. */
49955 }
49957 /* Extract the values from the vector CST into the permutation
49958 array in D. */
49961 {
49965 }
49967 /* For all elements from second vector, fold the elements to first. */
49972 /* Check whether the mask can be applied to the vector type. */
49975 /* Implementable with shufps or pshufd. */
49979 /* Otherwise we have to go through the motions and see if we can
49980 figure out how to generate the requested permutation. */
49991 }
49993 void
49995 {
50010 /* We'll either be able to implement the permutation directly... */
50014 /* ... or we use the special-case patterns. */
50016 }
50018 static void
50020 {
50035 {
50038 }
50040 /* Note that for AVX this isn't one instruction. */
50043 }
50046 /* Expand a vector operation CODE for a V*QImode in terms of the
50047 same operation on V*HImode. */
50049 void
50051 {
50053 machine_mode himode;
50063 {
50081 }
50085 {
50087 /* Unpack data such that we've got a source byte in each low byte of
50088 each word. We don't care what goes into the high byte of each word.
50089 Rather than trying to get zero in there, most convenient is to let
50090 it be a copy of the low byte. */
50095 /* FALLTHRU */
50107 /* FALLTHRU */
50117 }
50119 /* Perform the operation. */
50126 /* Merge the data back into the right place. */
50136 {
50137 /* For SSE2, we used an full interleave, so the desired
50138 results are in the even elements. */
50141 }
50142 else
50143 {
50144 /* For AVX, the interleave used above was not cross-lane. So the
50145 extraction is evens but with the second and third quarter swapped.
50146 Happily, that is even one insn shorter than even extraction. */
50149 }
50156 }
50158 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
50159 if op is CONST_VECTOR with all odd elements equal to their
50160 preceding element. */
50162 static bool
50164 {
50174 }
50176 void
50179 {
50182 rtx x;
50190 /* We only play even/odd games with vectors of SImode. */
50193 /* If we're looking for the odd results, shift those members down to
50194 the even slots. For some cpus this is faster than a PSHUFD. */
50196 {
50197 /* For XOP use vpmacsdqh, but only for smult, as it is only
50198 signed. */
50200 {
50204 }
50215 }
50218 {
50221 else
50223 }
50225 {
50228 else
50230 }
50235 else
50236 {
50239 /* The easiest way to implement this without PMULDQ is to go through
50240 the motions as if we are performing a full 64-bit multiply. With
50241 the exception that we need to do less shuffling of the elements. */
50243 /* Compute the sign-extension, aka highparts, of the two operands. */
50249 /* Multiply LO(A) * HI(B), and vice-versa. */
50255 /* Multiply LO(A) * LO(B). */
50259 /* Combine and shift the highparts into place. */
50264 /* Combine high and low parts. */
50267 }
50269 }
50271 void
50274 {
50280 {
50285 {
50286 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
50287 shuffle the elements once so that all elements are in the right
50288 place for immediate use: { A C B D }. */
50293 }
50294 else
50295 {
50296 /* Put the elements into place for the multiply. */
50300 }
50305 /* Shuffle the elements between the lanes. After this we
50306 have { A B E F | C D G H } for each operand. */
50316 /* Shuffle the elements within the lanes. After this we
50317 have { A A B B | C C D D } or { E E F F | G G H H }. */
50358 }
50359 }
50361 void
50363 {
50373 /* Move the results in element 2 down to element 1; we don't care
50374 what goes in elements 2 and 3. Then we can merge the parts
50375 back together with an interleave.
50377 Note that two other sequences were tried:
50378 (1) Use interleaves at the start instead of psrldq, which allows
50379 us to use a single shufps to merge things back at the end.
50380 (2) Use shufps here to combine the two vectors, then pshufd to
50381 put the elements in the correct order.
50382 In both cases the cost of the reformatting stall was too high
50383 and the overall sequence slower. */
50394 }
50396 void
50398 {
50409 {
50410 /* op1: A,B,C,D, op2: E,F,G,H */
50419 /* t1: B,A,D,C */
50426 /* t2: (B*E),(A*F),(D*G),(C*H) */
50429 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
50432 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
50435 /* Multiply lower parts and add all */
50442 }
50443 else
50444 {
50445 machine_mode nmode;
50449 {
50452 }
50454 {
50457 }
50459 {
50462 }
50463 else
50467 /* Multiply low parts. */
50471 /* Shift input vectors right 32 bits so we can multiply high parts. */
50476 /* Multiply high parts by low parts. */
50482 /* Combine and shift the highparts back. */
50486 /* Combine high and low parts. */
50488 }
50492 }
50494 /* Return 1 if control tansfer instruction INSN
50495 should be encoded with bnd prefix.
50496 If insn is NULL then return 1 when control
50497 transfer instructions should be prefixed with
50498 bnd by default for current function. */
50500 bool
50502 {
50503 /* For call insns check special flag. */
50505 {
50509 }
50511 /* All other insns are prefixed only if function is instrumented. */
50513 }
50515 /* Calculate integer abs() using only SSE2 instructions. */
50517 void
50519 {
50524 {
50525 /* For 32-bit signed integer X, the best way to calculate the absolute
50526 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
50537 /* For 16-bit signed integer X, the best way to calculate the absolute
50538 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
50546 /* For 8-bit signed integer X, the best way to calculate the absolute
50547 value of X is min ((unsigned char) X, (unsigned char) (-X)),
50548 as SSE2 provides the PMINUB insn. */
50558 }
50562 }
50564 /* Expand an extract from a vector register through pextr insn.
50565 Return true if successful. */
50567 bool
50569 {
50577 {
50578 /* Reject non-lowpart subregs. */
50582 }
50585 {
50588 }
50591 {
50598 {
50605 {
50633 }
50635 /* Reject extractions from misaligned positions. */
50641 else
50644 /* Construct insn pattern. */
50648 /* Let the rtl optimizers know about the zero extension performed. */
50650 {
50653 }
50660 }
50664 }
50665 }
50667 /* Expand an insert into a vector register through pinsr insn.
50668 Return true if successful. */
50670 bool
50672 {
50680 {
50683 }
50686 {
50693 {
50696 rtx d;
50701 {
50733 }
50735 /* Reject insertions to misaligned positions. */
50740 {
50744 {
50756 }
50757 else
50759 }
50763 else
50772 }
50776 }
50777 }
50778 \f
50779 /* This function returns the calling abi specific va_list type node.
50780 It returns the FNDECL specific va_list type. */
50782 static tree
50784 {
50791 else
50793 }
50795 /* Returns the canonical va_list type specified by TYPE. If there
50796 is no valid TYPE provided, it return NULL_TREE. */
50798 static tree
50800 {
50803 /* Resolve references and pointers to va_list type. */
50812 {
50817 {
50818 /* If va_list is an array type, the argument may have decayed
50819 to a pointer type, e.g. by being passed to another function.
50820 In that case, unwrap both types so that we can compare the
50821 underlying records. */
50824 {
50827 }
50828 }
50835 {
50836 /* If va_list is an array type, the argument may have decayed
50837 to a pointer type, e.g. by being passed to another function.
50838 In that case, unwrap both types so that we can compare the
50839 underlying records. */
50842 {
50845 }
50846 }
50853 {
50854 /* If va_list is an array type, the argument may have decayed
50855 to a pointer type, e.g. by being passed to another function.
50856 In that case, unwrap both types so that we can compare the
50857 underlying records. */
50860 {
50863 }
50864 }
50868 }
50870 }
50872 /* Iterate through the target-specific builtin types for va_list.
50873 IDX denotes the iterator, *PTREE is set to the result type of
50874 the va_list builtin, and *PNAME to its internal type.
50875 Returns zero if there is no element for this index, otherwise
50876 IDX should be increased upon the next call.
50877 Note, do not iterate a base builtin's name like __builtin_va_list.
50878 Used from c_common_nodes_and_builtins. */
50880 static int
50882 {
50884 {
50886 {
50899 }
50900 }
50903 }
50905 #undef TARGET_SCHED_DISPATCH
50906 #define TARGET_SCHED_DISPATCH has_dispatch
50907 #undef TARGET_SCHED_DISPATCH_DO
50908 #define TARGET_SCHED_DISPATCH_DO do_dispatch
50909 #undef TARGET_SCHED_REASSOCIATION_WIDTH
50910 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
50911 #undef TARGET_SCHED_REORDER
50912 #define TARGET_SCHED_REORDER ix86_sched_reorder
50913 #undef TARGET_SCHED_ADJUST_PRIORITY
50914 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
50915 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
50916 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
50917 ix86_dependencies_evaluation_hook
50919 /* The size of the dispatch window is the total number of bytes of
50920 object code allowed in a window. */
50921 #define DISPATCH_WINDOW_SIZE 16
50923 /* Number of dispatch windows considered for scheduling. */
50924 #define MAX_DISPATCH_WINDOWS 3
50926 /* Maximum number of instructions in a window. */
50927 #define MAX_INSN 4
50929 /* Maximum number of immediate operands in a window. */
50930 #define MAX_IMM 4
50932 /* Maximum number of immediate bits allowed in a window. */
50933 #define MAX_IMM_SIZE 128
50935 /* Maximum number of 32 bit immediates allowed in a window. */
50936 #define MAX_IMM_32 4
50938 /* Maximum number of 64 bit immediates allowed in a window. */
50939 #define MAX_IMM_64 2
50941 /* Maximum total of loads or prefetches allowed in a window. */
50942 #define MAX_LOAD 2
50944 /* Maximum total of stores allowed in a window. */
50945 #define MAX_STORE 1
50947 #undef BIG
50948 #define BIG 100
50951 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
50954 disp_load,
50955 disp_store,
50956 disp_load_store,
50957 disp_prefetch,
50958 disp_imm,
50959 disp_imm_32,
50960 disp_imm_64,
50961 disp_branch,
50962 disp_cmp,
50963 disp_jcc,
50964 disp_last
50965 };
50967 /* Number of allowable groups in a dispatch window. It is an array
50968 indexed by dispatch_group enum. 100 is used as a big number,
50969 because the number of these kind of operations does not have any
50970 effect in dispatch window, but we need them for other reasons in
50971 the table. */
50974 };
50980 };
50982 /* Instruction path. */
50988 last_path
50989 };
50991 /* sched_insn_info defines a window to the instructions scheduled in
50992 the basic block. It contains a pointer to the insn_info table and
50993 the instruction scheduled.
50995 Windows are allocated for each basic block and are linked
50996 together. */
50998 rtx insn;
51005 /* Linked list of dispatch windows. This is a two way list of
51006 dispatch windows of a basic block. It contains information about
51007 the number of uops in the window and the total number of
51008 instructions and of bytes in the object code for this dispatch
51009 window. */
51027 /* Immediate valuse used in an insn. */
51029 {
51038 /* Get dispatch group of insn. */
51040 static enum dispatch_group
51042 {
51058 }
51060 /* Return true if insn is a compare instruction. */
51062 static bool
51064 {
51072 }
51074 /* Return true if a dispatch violation encountered. */
51076 static bool
51078 {
51082 }
51084 /* Return true if insn is a branch instruction. */
51086 static bool
51088 {
51090 }
51092 /* Return true if insn is a prefetch instruction. */
51094 static bool
51096 {
51098 }
51100 /* This function initializes a dispatch window and the list container holding a
51101 pointer to the window. */
51103 static void
51105 {
51111 else
51129 {
51135 }
51137 }
51139 /* This function allocates and initializes a dispatch window and the
51140 list container holding a pointer to the window. */
51144 {
51149 }
51151 /* This routine initializes the dispatch scheduling information. It
51152 initiates building dispatch scheduler tables and constructs the
51153 first dispatch window. */
51155 static void
51157 {
51158 /* Allocate a dispatch list and a window. */
51163 }
51165 /* This function returns true if a branch is detected. End of a basic block
51166 does not have to be a branch, but here we assume only branches end a
51167 window. */
51169 static bool
51171 {
51173 }
51175 /* This function is called when the end of a window processing is reached. */
51177 static void
51179 {
51182 {
51187 }
51189 }
51191 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
51192 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
51193 for 48 bytes of instructions. Note that these windows are not dispatch
51194 windows that their sizes are DISPATCH_WINDOW_SIZE. */
51198 {
51200 {
51205 }
51211 }
51213 /* Compute number of immediate operands of an instruction. */
51215 static void
51217 {
51224 {
51231 else
51243 {
51246 }
51251 }
51252 }
51254 /* Return total size of immediate operands of an instruction along with number
51255 of corresponding immediate-operands. It initializes its parameters to zero
51256 befor calling FIND_CONSTANT.
51257 INSN is the input instruction. IMM is the total of immediates.
51258 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
51259 bit immediates. */
51261 static int
51263 {
51271 }
51273 /* This function indicates if an operand of an instruction is an
51274 immediate. */
51276 static bool
51278 {
51287 }
51289 /* Return single or double path for instructions. */
51291 static enum insn_path
51293 {
51303 }
51305 /* Return insn dispatch group. */
51307 static enum dispatch_group
51309 {
51327 }
51329 /* Count number of GROUP restricted instructions in a dispatch
51330 window WINDOW_LIST. */
51332 static int
51334 {
51345 {
51364 }
51377 }
51379 /* This function returns true if insn satisfies dispatch rules on the
51380 last window scheduled. */
51382 static bool
51384 {
51392 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
51393 instructions should be given the lowest priority in the
51394 scheduling process in Haifa scheduler to make sure they will be
51395 scheduled in the same dispatch window as the reference to them. */
51399 /* Check nonrestricted. */
51403 /* Get last dispatch window. */
51408 {
51413 /* Window 1 is full. Go for next window. */
51415 }
51422 /* See if it fits in the first window. */
51424 {
51425 /* The first widow should have only single and double path
51426 uops. */
51432 }
51434 }
51436 /* Add an instruction INSN with NUM_UOPS micro-operations to the
51437 dispatch window WINDOW_LIST. */
51439 static void
51441 {
51459 /* Initialize window with new instruction. */
51480 {
51483 }
51484 }
51486 /* Adds a scheduled instruction, INSN, to the current dispatch window.
51487 If the total bytes of instructions or the number of instructions in
51488 the window exceed allowable, it allocates a new window. */
51490 static void
51492 {
51515 /* Get the last dispatch window. */
51523 else
51526 /* If current window is full, get a new window.
51527 Window number zero is full, if MAX_INSN uops are scheduled in it.
51528 Window number one is full, if window zero's bytes plus window
51529 one's bytes is 32, or if the bytes of the new instruction added
51530 to the total makes it greater than 48, or it has already MAX_INSN
51531 instructions in it. */
51540 {
51543 }
51546 {
51550 {
51553 }
51554 }
51556 {
51561 {
51564 }
51567 }
51568 else
51572 {
51573 /* End of basic block is reached do end-basic-block process. */
51576 }
51577 }
51579 /* Print the dispatch window, WINDOW_NUM, to FILE. */
51581 DEBUG_FUNCTION static void
51583 {
51589 else
51603 {
51606 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
51612 }
51613 }
51615 /* Print to stdout a dispatch window. */
51617 DEBUG_FUNCTION void
51619 {
51621 }
51623 /* Print INSN dispatch information to FILE. */
51625 DEBUG_FUNCTION static void
51627 {
51650 }
51652 /* Print to STDERR the status of the ready list with respect to
51653 dispatch windows. */
51655 DEBUG_FUNCTION void
51657 {
51665 }
51667 /* This routine is the driver of the dispatch scheduler. */
51669 static void
51671 {
51676 }
51678 /* Return TRUE if Dispatch Scheduling is supported. */
51680 static bool
51682 {
51686 {
51702 }
51705 }
51707 /* Implementation of reassociation_width target hook used by
51708 reassoc phase to identify parallelism level in reassociated
51709 tree. Statements tree_code is passed in OPC. Arguments type
51710 is passed in MODE.
51712 Currently parallel reassociation is enabled for Atom
51713 processors only and we set reassociation width to be 2
51714 because Atom may issue up to 2 instructions per cycle.
51716 Return value should be fixed if parallel reassociation is
51717 enabled for other processors. */
51719 static int
51721 {
51722 /* Vector part. */
51724 {
51727 else
51729 }
51731 /* Scalar part. */
51736 else
51738 }
51740 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
51741 place emms and femms instructions. */
51743 static machine_mode
51745 {
51750 {
51769 else
51781 /* FALLTHRU */
51785 }
51786 }
51788 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
51789 vectors. If AVX512F is enabled then try vectorizing with 512bit,
51790 256bit and 128bit vectors. */
51792 static unsigned int
51794 {
51797 }
51799 \f
51801 /* Return class of registers which could be used for pseudo of MODE
51802 and of class RCLASS for spilling instead of memory. Return NO_REGS
51803 if it is not possible or non-profitable. */
51804 static reg_class_t
51806 {
51812 }
51814 /* Implement targetm.vectorize.init_cost. */
51818 {
51822 }
51824 /* Implement targetm.vectorize.add_stmt_cost. */
51826 static unsigned
51830 {
51837 /* Statements in an inner loop relative to the loop being
51838 vectorized are weighted more heavily. The value here is
51839 arbitrary and could potentially be improved with analysis. */
51845 /* We need to multiply all vector stmt cost by 1.7 (estimated cost)
51846 for Silvermont as it has out of order integer pipeline and can execute
51847 2 scalar instruction per tick, but has in order SIMD pipeline. */
51850 {
51854 }
51859 }
51861 /* Implement targetm.vectorize.finish_cost. */
51863 static void
51866 {
51871 }
51873 /* Implement targetm.vectorize.destroy_cost_data. */
51875 static void
51877 {
51879 }
51881 /* Validate target specific memory model bits in VAL. */
51883 static unsigned HOST_WIDE_INT
51885 {
51892 {
51896 }
51899 {
51903 }
51905 {
51909 }
51911 }
51913 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
51914 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
51915 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
51916 or number of vecsize_mangle variants that should be emitted. */
51918 static int
51922 {
51929 {
51933 }
51938 {
51945 /* case SCmode: */
51946 /* case DCmode: */
51952 }
51954 tree t;
51958 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
51960 {
51967 /* case SCmode: */
51968 /* case DCmode: */
51974 }
51977 {
51978 /* Parse here processor clause. If not present, default to 'b'. */
51980 }
51982 {
51983 /* If the function isn't exported, we can pick up just one ISA
51984 for the clones. */
51989 else
51992 }
51993 else
51994 {
51997 }
51999 {
52012 }
52014 {
52017 else
52022 }
52024 }
52026 /* Add target attribute to SIMD clone NODE if needed. */
52028 static void
52030 {
52034 {
52049 }
52059 }
52061 /* If SIMD clone NODE can't be used in a vectorized loop
52062 in current function, return -1, otherwise return a badness of using it
52063 (0 if it is most desirable from vecsize_mangle point of view, 1
52064 slightly less desirable, etc.). */
52066 static int
52068 {
52070 {
52088 }
52089 }
52091 /* This function adjusts the unroll factor based on
52092 the hardware capabilities. For ex, bdver3 has
52093 a loop buffer which makes unrolling of smaller
52094 loops less important. This function decides the
52095 unroll factor using number of memory references
52096 (value 32 is used) as a heuristic. */
52098 static unsigned
52100 {
52109 /* Count the number of memory references within the loop body.
52110 This value determines the unrolling factor for bdver3 and bdver4
52111 architectures. */
52120 {
52125 else
52127 }
52134 }
52137 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
52139 static bool
52141 {
52142 /* For x87 floating point with standard excess precision handling,
52143 there is no adddf3 pattern (since x87 floating point only has
52144 XFmode operations) so the default hook implementation gets this
52145 wrong. */
52147 }
52149 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
52151 static void
52153 {
52158 {
52173 hold_fnclex);
52186 }
52188 {
52197 mxcsr_orig_var,
52207 ldmxcsr_hold_call);
52210 else
52215 ldmxcsr_clear_call);
52216 else
52220 stxmcsr_update_call);
52222 {
52228 exceptions_assign);
52229 }
52230 else
52235 ldmxcsr_update_call);
52236 }
52237 tree atomic_feraiseexcept
52242 atomic_feraiseexcept_call);
52243 }
52245 /* Return mode to be used for bounds or VOIDmode
52246 if bounds are not supported. */
52248 static enum machine_mode
52250 {
52251 /* Do not support pointer checker if MPX
52252 is not enabled. */
52254 {
52259 }
52262 }
52264 /* Return constant used to statically initialize constant bounds.
52266 This function is used to create special bound values. For now
52267 only INIT bounds and NONE bounds are expected. More special
52268 values may be added later. */
52270 static tree
52272 {
52278 /* This function is supposed to be used to create INIT and
52279 NONE bounds only. */
52284 }
52286 /* Generate a list of statements STMTS to initialize pointer bounds
52287 variable VAR with bounds LB and UB. Return the number of generated
52288 statements. */
52290 static int
52292 {
52310 }
52312 #if !TARGET_MACHO && !TARGET_DLLIMPORT_DECL_ATTRIBUTES
52313 /* For i386, common symbol is local only for non-PIE binaries. For
52314 x86-64, common symbol is local only for non-PIE binaries or linker
52315 supports copy reloc in PIE binaries. */
52317 static bool
52319 {
52321 (!flag_pic
52322 || (TARGET_64BIT
52324 }
52325 #endif
52327 /* If MEM is in the form of [base+offset], extract the two parts
52328 of address and set to BASE and OFFSET, otherwise return false. */
52330 static bool
52332 {
52333 rtx addr;
52343 {
52347 }
52353 {
52357 }
52360 }
52362 /* Given OPERANDS of consecutive load/store, check if we can merge
52363 them into move multiple. LOAD is true if they are load instructions.
52364 MODE is the mode of memory operands. */
52366 bool
52369 {
52374 {
52379 }
52380 else
52381 {
52386 }
52393 /* Check if the addresses are in the form of [base+offset]. */
52399 /* Check if the bases are the same. */
52406 /* Check if mem_1 is adjacent to mem_2 and mem_1 has lower address. */
52411 }
52413 /* Initialize the GCC target structure. */
52414 #undef TARGET_RETURN_IN_MEMORY
52415 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
52417 #undef TARGET_LEGITIMIZE_ADDRESS
52418 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
52420 #undef TARGET_ATTRIBUTE_TABLE
52421 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
52422 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
52423 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
52424 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
52425 # undef TARGET_MERGE_DECL_ATTRIBUTES
52426 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
52427 #endif
52429 #undef TARGET_COMP_TYPE_ATTRIBUTES
52430 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
52432 #undef TARGET_INIT_BUILTINS
52433 #define TARGET_INIT_BUILTINS ix86_init_builtins
52434 #undef TARGET_BUILTIN_DECL
52435 #define TARGET_BUILTIN_DECL ix86_builtin_decl
52436 #undef TARGET_EXPAND_BUILTIN
52437 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
52439 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
52440 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
52441 ix86_builtin_vectorized_function
52443 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
52444 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
52446 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
52447 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
52449 #undef TARGET_VECTORIZE_BUILTIN_GATHER
52450 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
52452 #undef TARGET_VECTORIZE_BUILTIN_SCATTER
52453 #define TARGET_VECTORIZE_BUILTIN_SCATTER ix86_vectorize_builtin_scatter
52455 #undef TARGET_BUILTIN_RECIPROCAL
52456 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
52458 #undef TARGET_ASM_FUNCTION_EPILOGUE
52459 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
52461 #undef TARGET_ENCODE_SECTION_INFO
52462 #ifndef SUBTARGET_ENCODE_SECTION_INFO
52463 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
52464 #else
52465 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
52466 #endif
52468 #undef TARGET_ASM_OPEN_PAREN
52470 #undef TARGET_ASM_CLOSE_PAREN
52473 #undef TARGET_ASM_BYTE_OP
52474 #define TARGET_ASM_BYTE_OP ASM_BYTE
52476 #undef TARGET_ASM_ALIGNED_HI_OP
52477 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
52478 #undef TARGET_ASM_ALIGNED_SI_OP
52479 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
52480 #ifdef ASM_QUAD
52481 #undef TARGET_ASM_ALIGNED_DI_OP
52482 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
52483 #endif
52485 #undef TARGET_PROFILE_BEFORE_PROLOGUE
52486 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
52488 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
52489 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
52491 #undef TARGET_ASM_UNALIGNED_HI_OP
52492 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
52493 #undef TARGET_ASM_UNALIGNED_SI_OP
52494 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
52495 #undef TARGET_ASM_UNALIGNED_DI_OP
52496 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
52498 #undef TARGET_PRINT_OPERAND
52499 #define TARGET_PRINT_OPERAND ix86_print_operand
52500 #undef TARGET_PRINT_OPERAND_ADDRESS
52501 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
52502 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
52503 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
52504 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
52505 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
52507 #undef TARGET_SCHED_INIT_GLOBAL
52508 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
52509 #undef TARGET_SCHED_ADJUST_COST
52510 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
52511 #undef TARGET_SCHED_ISSUE_RATE
52512 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
52513 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
52514 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
52515 ia32_multipass_dfa_lookahead
52516 #undef TARGET_SCHED_MACRO_FUSION_P
52517 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
52518 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
52519 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
52521 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
52522 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
52524 #undef TARGET_MEMMODEL_CHECK
52525 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
52527 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
52528 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
52530 #ifdef HAVE_AS_TLS
52531 #undef TARGET_HAVE_TLS
52532 #define TARGET_HAVE_TLS true
52533 #endif
52534 #undef TARGET_CANNOT_FORCE_CONST_MEM
52535 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
52536 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
52537 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
52539 #undef TARGET_DELEGITIMIZE_ADDRESS
52540 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
52542 #undef TARGET_MS_BITFIELD_LAYOUT_P
52543 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
52545 #if TARGET_MACHO
52546 #undef TARGET_BINDS_LOCAL_P
52547 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
52548 #else
52549 #undef TARGET_BINDS_LOCAL_P
52550 #define TARGET_BINDS_LOCAL_P ix86_binds_local_p
52551 #endif
52552 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
52553 #undef TARGET_BINDS_LOCAL_P
52554 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
52555 #endif
52557 #undef TARGET_ASM_OUTPUT_MI_THUNK
52558 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
52559 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
52560 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
52562 #undef TARGET_ASM_FILE_START
52563 #define TARGET_ASM_FILE_START x86_file_start
52565 #undef TARGET_OPTION_OVERRIDE
52566 #define TARGET_OPTION_OVERRIDE ix86_option_override
52568 #undef TARGET_REGISTER_MOVE_COST
52569 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
52570 #undef TARGET_MEMORY_MOVE_COST
52571 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
52572 #undef TARGET_RTX_COSTS
52573 #define TARGET_RTX_COSTS ix86_rtx_costs
52574 #undef TARGET_ADDRESS_COST
52575 #define TARGET_ADDRESS_COST ix86_address_cost
52577 #undef TARGET_FIXED_CONDITION_CODE_REGS
52578 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
52579 #undef TARGET_CC_MODES_COMPATIBLE
52580 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
52582 #undef TARGET_MACHINE_DEPENDENT_REORG
52583 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
52585 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
52586 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
52588 #undef TARGET_BUILD_BUILTIN_VA_LIST
52589 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
52591 #undef TARGET_FOLD_BUILTIN
52592 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
52594 #undef TARGET_COMPARE_VERSION_PRIORITY
52595 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
52597 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
52598 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
52599 ix86_generate_version_dispatcher_body
52601 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
52602 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
52603 ix86_get_function_versions_dispatcher
52605 #undef TARGET_ENUM_VA_LIST_P
52606 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
52608 #undef TARGET_FN_ABI_VA_LIST
52609 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
52611 #undef TARGET_CANONICAL_VA_LIST_TYPE
52612 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
52614 #undef TARGET_EXPAND_BUILTIN_VA_START
52615 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
52617 #undef TARGET_MD_ASM_ADJUST
52618 #define TARGET_MD_ASM_ADJUST ix86_md_asm_adjust
52620 #undef TARGET_PROMOTE_PROTOTYPES
52621 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
52622 #undef TARGET_SETUP_INCOMING_VARARGS
52623 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
52624 #undef TARGET_MUST_PASS_IN_STACK
52625 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
52626 #undef TARGET_FUNCTION_ARG_ADVANCE
52627 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
52628 #undef TARGET_FUNCTION_ARG
52629 #define TARGET_FUNCTION_ARG ix86_function_arg
52630 #undef TARGET_INIT_PIC_REG
52631 #define TARGET_INIT_PIC_REG ix86_init_pic_reg
52632 #undef TARGET_USE_PSEUDO_PIC_REG
52633 #define TARGET_USE_PSEUDO_PIC_REG ix86_use_pseudo_pic_reg
52634 #undef TARGET_FUNCTION_ARG_BOUNDARY
52635 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
52636 #undef TARGET_PASS_BY_REFERENCE
52637 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
52638 #undef TARGET_INTERNAL_ARG_POINTER
52639 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
52640 #undef TARGET_UPDATE_STACK_BOUNDARY
52641 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
52642 #undef TARGET_GET_DRAP_RTX
52643 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
52644 #undef TARGET_STRICT_ARGUMENT_NAMING
52645 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
52646 #undef TARGET_STATIC_CHAIN
52647 #define TARGET_STATIC_CHAIN ix86_static_chain
52648 #undef TARGET_TRAMPOLINE_INIT
52649 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
52650 #undef TARGET_RETURN_POPS_ARGS
52651 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
52653 #undef TARGET_LEGITIMATE_COMBINED_INSN
52654 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
52656 #undef TARGET_ASAN_SHADOW_OFFSET
52657 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
52659 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
52660 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
52662 #undef TARGET_SCALAR_MODE_SUPPORTED_P
52663 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
52665 #undef TARGET_VECTOR_MODE_SUPPORTED_P
52666 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
52668 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
52669 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
52670 ix86_libgcc_floating_mode_supported_p
52672 #undef TARGET_C_MODE_FOR_SUFFIX
52673 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
52675 #ifdef HAVE_AS_TLS
52676 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
52677 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
52678 #endif
52680 #ifdef SUBTARGET_INSERT_ATTRIBUTES
52681 #undef TARGET_INSERT_ATTRIBUTES
52682 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
52683 #endif
52685 #undef TARGET_MANGLE_TYPE
52686 #define TARGET_MANGLE_TYPE ix86_mangle_type
52688 #if !TARGET_MACHO
52689 #undef TARGET_STACK_PROTECT_FAIL
52690 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
52691 #endif
52693 #undef TARGET_FUNCTION_VALUE
52694 #define TARGET_FUNCTION_VALUE ix86_function_value
52696 #undef TARGET_FUNCTION_VALUE_REGNO_P
52697 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
52699 #undef TARGET_PROMOTE_FUNCTION_MODE
52700 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
52702 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
52703 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ix86_override_options_after_change
52705 #undef TARGET_MEMBER_TYPE_FORCES_BLK
52706 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
52708 #undef TARGET_INSTANTIATE_DECLS
52709 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
52711 #undef TARGET_SECONDARY_RELOAD
52712 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
52714 #undef TARGET_CLASS_MAX_NREGS
52715 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
52717 #undef TARGET_PREFERRED_RELOAD_CLASS
52718 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
52719 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
52720 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
52721 #undef TARGET_CLASS_LIKELY_SPILLED_P
52722 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
52724 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
52725 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
52726 ix86_builtin_vectorization_cost
52727 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
52728 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
52729 ix86_vectorize_vec_perm_const_ok
52730 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
52731 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
52732 ix86_preferred_simd_mode
52733 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
52734 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
52735 ix86_autovectorize_vector_sizes
52736 #undef TARGET_VECTORIZE_INIT_COST
52737 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
52738 #undef TARGET_VECTORIZE_ADD_STMT_COST
52739 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
52740 #undef TARGET_VECTORIZE_FINISH_COST
52741 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
52742 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
52743 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
52745 #undef TARGET_SET_CURRENT_FUNCTION
52746 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
52748 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
52749 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
52751 #undef TARGET_OPTION_SAVE
52752 #define TARGET_OPTION_SAVE ix86_function_specific_save
52754 #undef TARGET_OPTION_RESTORE
52755 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
52757 #undef TARGET_OPTION_POST_STREAM_IN
52758 #define TARGET_OPTION_POST_STREAM_IN ix86_function_specific_post_stream_in
52760 #undef TARGET_OPTION_PRINT
52761 #define TARGET_OPTION_PRINT ix86_function_specific_print
52763 #undef TARGET_OPTION_FUNCTION_VERSIONS
52764 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
52766 #undef TARGET_CAN_INLINE_P
52767 #define TARGET_CAN_INLINE_P ix86_can_inline_p
52769 #undef TARGET_EXPAND_TO_RTL_HOOK
52770 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
52772 #undef TARGET_LEGITIMATE_ADDRESS_P
52773 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
52775 #undef TARGET_LRA_P
52776 #define TARGET_LRA_P hook_bool_void_true
52778 #undef TARGET_REGISTER_PRIORITY
52779 #define TARGET_REGISTER_PRIORITY ix86_register_priority
52781 #undef TARGET_REGISTER_USAGE_LEVELING_P
52782 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
52784 #undef TARGET_LEGITIMATE_CONSTANT_P
52785 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
52787 #undef TARGET_FRAME_POINTER_REQUIRED
52788 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
52790 #undef TARGET_CAN_ELIMINATE
52791 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
52793 #undef TARGET_EXTRA_LIVE_ON_ENTRY
52794 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
52796 #undef TARGET_ASM_CODE_END
52797 #define TARGET_ASM_CODE_END ix86_code_end
52799 #undef TARGET_CONDITIONAL_REGISTER_USAGE
52800 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
52802 #if TARGET_MACHO
52803 #undef TARGET_INIT_LIBFUNCS
52804 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
52805 #endif
52807 #undef TARGET_LOOP_UNROLL_ADJUST
52808 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
52810 #undef TARGET_SPILL_CLASS
52811 #define TARGET_SPILL_CLASS ix86_spill_class
52813 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
52814 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
52815 ix86_simd_clone_compute_vecsize_and_simdlen
52817 #undef TARGET_SIMD_CLONE_ADJUST
52818 #define TARGET_SIMD_CLONE_ADJUST \
52819 ix86_simd_clone_adjust
52821 #undef TARGET_SIMD_CLONE_USABLE
52822 #define TARGET_SIMD_CLONE_USABLE \
52823 ix86_simd_clone_usable
52825 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
52826 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
52827 ix86_float_exceptions_rounding_supported_p
52829 #undef TARGET_MODE_EMIT
52830 #define TARGET_MODE_EMIT ix86_emit_mode_set
52832 #undef TARGET_MODE_NEEDED
52833 #define TARGET_MODE_NEEDED ix86_mode_needed
52835 #undef TARGET_MODE_AFTER
52836 #define TARGET_MODE_AFTER ix86_mode_after
52838 #undef TARGET_MODE_ENTRY
52839 #define TARGET_MODE_ENTRY ix86_mode_entry
52841 #undef TARGET_MODE_EXIT
52842 #define TARGET_MODE_EXIT ix86_mode_exit
52844 #undef TARGET_MODE_PRIORITY
52845 #define TARGET_MODE_PRIORITY ix86_mode_priority
52847 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
52848 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
52850 #undef TARGET_LOAD_BOUNDS_FOR_ARG
52851 #define TARGET_LOAD_BOUNDS_FOR_ARG ix86_load_bounds
52853 #undef TARGET_STORE_BOUNDS_FOR_ARG
52854 #define TARGET_STORE_BOUNDS_FOR_ARG ix86_store_bounds
52856 #undef TARGET_LOAD_RETURNED_BOUNDS
52857 #define TARGET_LOAD_RETURNED_BOUNDS ix86_load_returned_bounds
52859 #undef TARGET_STORE_RETURNED_BOUNDS
52860 #define TARGET_STORE_RETURNED_BOUNDS ix86_store_returned_bounds
52862 #undef TARGET_CHKP_BOUND_MODE
52863 #define TARGET_CHKP_BOUND_MODE ix86_mpx_bound_mode
52865 #undef TARGET_BUILTIN_CHKP_FUNCTION
52866 #define TARGET_BUILTIN_CHKP_FUNCTION ix86_builtin_mpx_function
52868 #undef TARGET_CHKP_FUNCTION_VALUE_BOUNDS
52869 #define TARGET_CHKP_FUNCTION_VALUE_BOUNDS ix86_function_value_bounds
52871 #undef TARGET_CHKP_MAKE_BOUNDS_CONSTANT
52872 #define TARGET_CHKP_MAKE_BOUNDS_CONSTANT ix86_make_bounds_constant
52874 #undef TARGET_CHKP_INITIALIZE_BOUNDS
52875 #define TARGET_CHKP_INITIALIZE_BOUNDS ix86_initialize_bounds
52877 #undef TARGET_SETUP_INCOMING_VARARG_BOUNDS
52878 #define TARGET_SETUP_INCOMING_VARARG_BOUNDS ix86_setup_incoming_vararg_bounds
52880 #undef TARGET_OFFLOAD_OPTIONS
52881 #define TARGET_OFFLOAD_OPTIONS \
52882 ix86_offload_options
52884 #undef TARGET_ABSOLUTE_BIGGEST_ALIGNMENT
52885 #define TARGET_ABSOLUTE_BIGGEST_ALIGNMENT 512
52888 \f