2 Copyright (C) 1998-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
31 #include "basic-block.h"
34 #include "tree-pass.h"
38 /* We want target macros for the mode switching code to be able to refer
39 to instruction attribute values. */
40 #include "insn-attr.h"
42 #ifdef OPTIMIZE_MODE_SWITCHING
44 /* The algorithm for setting the modes consists of scanning the insn list
45 and finding all the insns which require a specific mode. Each insn gets
46 a unique struct seginfo element. These structures are inserted into a list
47 for each basic block. For each entity, there is an array of bb_info over
48 the flow graph basic blocks (local var 'bb_info'), and contains a list
49 of all insns within that basic block, in the order they are encountered.
51 For each entity, any basic block WITHOUT any insns requiring a specific
52 mode are given a single entry, without a mode. (Each basic block
53 in the flow graph must have at least one entry in the segment table.)
55 The LCM algorithm is then run over the flow graph to determine where to
56 place the sets to the highest-priority value in respect of first the first
57 insn in any one block. Any adjustments required to the transparency
58 vectors are made, then the next iteration starts for the next-lower
59 priority mode, till for each entity all modes are exhausted.
61 More details are located in the code for optimize_mode_switching(). */
63 /* This structure contains the information for each insn which requires
64 either single or double mode to be set.
65 MODE is the mode this insn must be executed in.
66 INSN_PTR is the insn to be executed (may be the note that marks the
67 beginning of a basic block).
68 BBNUM is the flow graph basic block this insn occurs in.
69 NEXT is the next insn in the same basic block. */
76 HARD_REG_SET regs_live
;
81 struct seginfo
*seginfo
;
85 /* These bitmaps are used for the LCM algorithm. */
87 static sbitmap
*antic
;
88 static sbitmap
*transp
;
91 static struct seginfo
* new_seginfo (int, rtx
, int, HARD_REG_SET
);
92 static void add_seginfo (struct bb_info
*, struct seginfo
*);
93 static void reg_dies (rtx
, HARD_REG_SET
*);
94 static void reg_becomes_live (rtx
, const_rtx
, void *);
95 static void make_preds_opaque (basic_block
, int);
98 /* This function will allocate a new BBINFO structure, initialized
99 with the MODE, INSN, and basic block BB parameters. */
101 static struct seginfo
*
102 new_seginfo (int mode
, rtx insn
, int bb
, HARD_REG_SET regs_live
)
105 ptr
= XNEW (struct seginfo
);
107 ptr
->insn_ptr
= insn
;
110 COPY_HARD_REG_SET (ptr
->regs_live
, regs_live
);
114 /* Add a seginfo element to the end of a list.
115 HEAD is a pointer to the list beginning.
116 INFO is the structure to be linked in. */
119 add_seginfo (struct bb_info
*head
, struct seginfo
*info
)
123 if (head
->seginfo
== NULL
)
124 head
->seginfo
= info
;
128 while (ptr
->next
!= NULL
)
134 /* Make all predecessors of basic block B opaque, recursively, till we hit
135 some that are already non-transparent, or an edge where aux is set; that
136 denotes that a mode set is to be done on that edge.
137 J is the bit number in the bitmaps that corresponds to the entity that
138 we are currently handling mode-switching for. */
141 make_preds_opaque (basic_block b
, int j
)
146 FOR_EACH_EDGE (e
, ei
, b
->preds
)
148 basic_block pb
= e
->src
;
150 if (e
->aux
|| ! bitmap_bit_p (transp
[pb
->index
], j
))
153 bitmap_clear_bit (transp
[pb
->index
], j
);
154 make_preds_opaque (pb
, j
);
158 /* Record in LIVE that register REG died. */
161 reg_dies (rtx reg
, HARD_REG_SET
*live
)
169 if (regno
< FIRST_PSEUDO_REGISTER
)
170 remove_from_hard_reg_set (live
, GET_MODE (reg
), regno
);
173 /* Record in LIVE that register REG became live.
174 This is called via note_stores. */
177 reg_becomes_live (rtx reg
, const_rtx setter ATTRIBUTE_UNUSED
, void *live
)
181 if (GET_CODE (reg
) == SUBREG
)
182 reg
= SUBREG_REG (reg
);
188 if (regno
< FIRST_PSEUDO_REGISTER
)
189 add_to_hard_reg_set ((HARD_REG_SET
*) live
, GET_MODE (reg
), regno
);
192 /* Make sure if MODE_ENTRY is defined the MODE_EXIT is defined
194 #if defined (MODE_ENTRY) != defined (MODE_EXIT)
195 #error "Both MODE_ENTRY and MODE_EXIT must be defined"
198 #if defined (MODE_ENTRY) && defined (MODE_EXIT)
199 /* Split the fallthrough edge to the exit block, so that we can note
200 that there NORMAL_MODE is required. Return the new block if it's
201 inserted before the exit block. Otherwise return null. */
204 create_pre_exit (int n_entities
, int *entity_map
, const int *num_modes
)
208 basic_block pre_exit
;
210 /* The only non-call predecessor at this stage is a block with a
211 fallthrough edge; there can be at most one, but there could be
212 none at all, e.g. when exit is called. */
214 FOR_EACH_EDGE (eg
, ei
, EXIT_BLOCK_PTR
->preds
)
215 if (eg
->flags
& EDGE_FALLTHRU
)
217 basic_block src_bb
= eg
->src
;
218 rtx last_insn
, ret_reg
;
220 gcc_assert (!pre_exit
);
221 /* If this function returns a value at the end, we have to
222 insert the final mode switch before the return value copy
223 to its hard register. */
224 if (EDGE_COUNT (EXIT_BLOCK_PTR
->preds
) == 1
225 && NONJUMP_INSN_P ((last_insn
= BB_END (src_bb
)))
226 && GET_CODE (PATTERN (last_insn
)) == USE
227 && GET_CODE ((ret_reg
= XEXP (PATTERN (last_insn
), 0))) == REG
)
229 int ret_start
= REGNO (ret_reg
);
230 int nregs
= hard_regno_nregs
[ret_start
][GET_MODE (ret_reg
)];
231 int ret_end
= ret_start
+ nregs
;
232 bool short_block
= false;
233 bool multi_reg_return
= false;
234 bool forced_late_switch
= false;
235 rtx before_return_copy
;
239 rtx return_copy
= PREV_INSN (last_insn
);
240 rtx return_copy_pat
, copy_reg
;
241 int copy_start
, copy_num
;
244 if (NONDEBUG_INSN_P (return_copy
))
246 /* When using SJLJ exceptions, the call to the
247 unregister function is inserted between the
248 clobber of the return value and the copy.
249 We do not want to split the block before this
250 or any other call; if we have not found the
251 copy yet, the copy must have been deleted. */
252 if (CALL_P (return_copy
))
257 return_copy_pat
= PATTERN (return_copy
);
258 switch (GET_CODE (return_copy_pat
))
261 /* Skip USEs of multiple return registers.
262 __builtin_apply pattern is also handled here. */
263 if (GET_CODE (XEXP (return_copy_pat
, 0)) == REG
264 && (targetm
.calls
.function_value_regno_p
265 (REGNO (XEXP (return_copy_pat
, 0)))))
267 multi_reg_return
= true;
268 last_insn
= return_copy
;
274 /* Skip barrier insns. */
275 if (!MEM_VOLATILE_P (return_copy_pat
))
281 case UNSPEC_VOLATILE
:
282 last_insn
= return_copy
;
289 /* If the return register is not (in its entirety)
290 likely spilled, the return copy might be
291 partially or completely optimized away. */
292 return_copy_pat
= single_set (return_copy
);
293 if (!return_copy_pat
)
295 return_copy_pat
= PATTERN (return_copy
);
296 if (GET_CODE (return_copy_pat
) != CLOBBER
)
300 /* This might be (clobber (reg [<result>]))
301 when not optimizing. Then check if
302 the previous insn is the clobber for
303 the return register. */
304 copy_reg
= SET_DEST (return_copy_pat
);
305 if (GET_CODE (copy_reg
) == REG
306 && !HARD_REGISTER_NUM_P (REGNO (copy_reg
)))
308 if (INSN_P (PREV_INSN (return_copy
)))
310 return_copy
= PREV_INSN (return_copy
);
311 return_copy_pat
= PATTERN (return_copy
);
312 if (GET_CODE (return_copy_pat
) != CLOBBER
)
318 copy_reg
= SET_DEST (return_copy_pat
);
319 if (GET_CODE (copy_reg
) == REG
)
320 copy_start
= REGNO (copy_reg
);
321 else if (GET_CODE (copy_reg
) == SUBREG
322 && GET_CODE (SUBREG_REG (copy_reg
)) == REG
)
323 copy_start
= REGNO (SUBREG_REG (copy_reg
));
326 /* When control reaches end of non-void function,
327 there are no return copy insns at all. This
328 avoids an ice on that invalid function. */
329 if (ret_start
+ nregs
== ret_end
)
333 if (!targetm
.calls
.function_value_regno_p (copy_start
))
337 = hard_regno_nregs
[copy_start
][GET_MODE (copy_reg
)];
339 /* If the return register is not likely spilled, - as is
340 the case for floating point on SH4 - then it might
341 be set by an arithmetic operation that needs a
342 different mode than the exit block. */
343 for (j
= n_entities
- 1; j
>= 0; j
--)
345 int e
= entity_map
[j
];
346 int mode
= MODE_NEEDED (e
, return_copy
);
348 if (mode
!= num_modes
[e
] && mode
!= MODE_EXIT (e
))
353 /* __builtin_return emits a sequence of loads to all
354 return registers. One of them might require
355 another mode than MODE_EXIT, even if it is
356 unrelated to the return value, so we want to put
357 the final mode switch after it. */
359 && targetm
.calls
.function_value_regno_p
361 forced_late_switch
= true;
363 /* For the SH4, floating point loads depend on fpscr,
364 thus we might need to put the final mode switch
365 after the return value copy. That is still OK,
366 because a floating point return value does not
367 conflict with address reloads. */
368 if (copy_start
>= ret_start
369 && copy_start
+ copy_num
<= ret_end
370 && OBJECT_P (SET_SRC (return_copy_pat
)))
371 forced_late_switch
= true;
376 last_insn
= return_copy
;
380 if (copy_start
>= ret_start
381 && copy_start
+ copy_num
<= ret_end
)
383 else if (!multi_reg_return
384 || !targetm
.calls
.function_value_regno_p
387 last_insn
= return_copy
;
389 /* ??? Exception handling can lead to the return value
390 copy being already separated from the return value use,
392 Similarly, conditionally returning without a value,
393 and conditionally using builtin_return can lead to an
395 if (return_copy
== BB_HEAD (src_bb
))
400 last_insn
= return_copy
;
404 /* If we didn't see a full return value copy, verify that there
405 is a plausible reason for this. If some, but not all of the
406 return register is likely spilled, we can expect that there
407 is a copy for the likely spilled part. */
409 || forced_late_switch
411 || !(targetm
.class_likely_spilled_p
412 (REGNO_REG_CLASS (ret_start
)))
414 != hard_regno_nregs
[ret_start
][GET_MODE (ret_reg
)])
415 /* For multi-hard-register floating point
416 values, sometimes the likely-spilled part
417 is ordinarily copied first, then the other
418 part is set with an arithmetic operation.
419 This doesn't actually cause reload
420 failures, so let it pass. */
421 || (GET_MODE_CLASS (GET_MODE (ret_reg
)) != MODE_INT
424 if (!NOTE_INSN_BASIC_BLOCK_P (last_insn
))
427 = emit_note_before (NOTE_INSN_DELETED
, last_insn
);
428 /* Instructions preceding LAST_INSN in the same block might
429 require a different mode than MODE_EXIT, so if we might
430 have such instructions, keep them in a separate block
432 src_bb
= split_block (src_bb
,
433 PREV_INSN (before_return_copy
))->dest
;
436 before_return_copy
= last_insn
;
437 pre_exit
= split_block (src_bb
, before_return_copy
)->src
;
441 pre_exit
= split_edge (eg
);
449 /* Find all insns that need a particular mode setting, and insert the
450 necessary mode switches. Return true if we did work. */
453 optimize_mode_switching (void)
460 struct edge_list
*edge_list
;
461 static const int num_modes
[] = NUM_MODES_FOR_MODE_SWITCHING
;
462 #define N_ENTITIES ARRAY_SIZE (num_modes)
463 int entity_map
[N_ENTITIES
];
464 struct bb_info
*bb_info
[N_ENTITIES
];
467 int max_num_modes
= 0;
468 bool emitted ATTRIBUTE_UNUSED
= false;
469 basic_block post_entry ATTRIBUTE_UNUSED
, pre_exit ATTRIBUTE_UNUSED
;
471 for (e
= N_ENTITIES
- 1, n_entities
= 0; e
>= 0; e
--)
472 if (OPTIMIZE_MODE_SWITCHING (e
))
474 int entry_exit_extra
= 0;
476 /* Create the list of segments within each basic block.
477 If NORMAL_MODE is defined, allow for two extra
478 blocks split from the entry and exit block. */
479 #if defined (MODE_ENTRY) && defined (MODE_EXIT)
480 entry_exit_extra
= 3;
483 = XCNEWVEC (struct bb_info
, last_basic_block
+ entry_exit_extra
);
484 entity_map
[n_entities
++] = e
;
485 if (num_modes
[e
] > max_num_modes
)
486 max_num_modes
= num_modes
[e
];
492 #if defined (MODE_ENTRY) && defined (MODE_EXIT)
493 /* Split the edge from the entry block, so that we can note that
494 there NORMAL_MODE is supplied. */
495 post_entry
= split_edge (single_succ_edge (ENTRY_BLOCK_PTR
));
496 pre_exit
= create_pre_exit (n_entities
, entity_map
, num_modes
);
501 /* Create the bitmap vectors. */
503 antic
= sbitmap_vector_alloc (last_basic_block
, n_entities
);
504 transp
= sbitmap_vector_alloc (last_basic_block
, n_entities
);
505 comp
= sbitmap_vector_alloc (last_basic_block
, n_entities
);
507 bitmap_vector_ones (transp
, last_basic_block
);
509 for (j
= n_entities
- 1; j
>= 0; j
--)
511 int e
= entity_map
[j
];
512 int no_mode
= num_modes
[e
];
513 struct bb_info
*info
= bb_info
[j
];
515 /* Determine what the first use (if any) need for a mode of entity E is.
516 This will be the mode that is anticipatable for this block.
517 Also compute the initial transparency settings. */
521 int last_mode
= no_mode
;
522 bool any_set_required
= false;
523 HARD_REG_SET live_now
;
525 REG_SET_TO_HARD_REG_SET (live_now
, df_get_live_in (bb
));
527 /* Pretend the mode is clobbered across abnormal edges. */
531 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
532 if (e
->flags
& EDGE_COMPLEX
)
536 ptr
= new_seginfo (no_mode
, BB_HEAD (bb
), bb
->index
, live_now
);
537 add_seginfo (info
+ bb
->index
, ptr
);
538 bitmap_clear_bit (transp
[bb
->index
], j
);
542 FOR_BB_INSNS (bb
, insn
)
546 int mode
= MODE_NEEDED (e
, insn
);
549 if (mode
!= no_mode
&& mode
!= last_mode
)
551 any_set_required
= true;
553 ptr
= new_seginfo (mode
, insn
, bb
->index
, live_now
);
554 add_seginfo (info
+ bb
->index
, ptr
);
555 bitmap_clear_bit (transp
[bb
->index
], j
);
558 last_mode
= MODE_AFTER (e
, last_mode
, insn
);
560 /* Update LIVE_NOW. */
561 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
562 if (REG_NOTE_KIND (link
) == REG_DEAD
)
563 reg_dies (XEXP (link
, 0), &live_now
);
565 note_stores (PATTERN (insn
), reg_becomes_live
, &live_now
);
566 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
567 if (REG_NOTE_KIND (link
) == REG_UNUSED
)
568 reg_dies (XEXP (link
, 0), &live_now
);
572 info
[bb
->index
].computing
= last_mode
;
573 /* Check for blocks without ANY mode requirements.
574 N.B. because of MODE_AFTER, last_mode might still be different
576 if (!any_set_required
)
578 ptr
= new_seginfo (no_mode
, BB_END (bb
), bb
->index
, live_now
);
579 add_seginfo (info
+ bb
->index
, ptr
);
582 #if defined (MODE_ENTRY) && defined (MODE_EXIT)
584 int mode
= MODE_ENTRY (e
);
590 /* By always making this nontransparent, we save
591 an extra check in make_preds_opaque. We also
592 need this to avoid confusing pre_edge_lcm when
593 antic is cleared but transp and comp are set. */
594 bitmap_clear_bit (transp
[bb
->index
], j
);
596 /* Insert a fake computing definition of MODE into entry
597 blocks which compute no mode. This represents the mode on
599 info
[bb
->index
].computing
= mode
;
602 info
[pre_exit
->index
].seginfo
->mode
= MODE_EXIT (e
);
605 #endif /* NORMAL_MODE */
608 kill
= sbitmap_vector_alloc (last_basic_block
, n_entities
);
609 for (i
= 0; i
< max_num_modes
; i
++)
611 int current_mode
[N_ENTITIES
];
615 /* Set the anticipatable and computing arrays. */
616 bitmap_vector_clear (antic
, last_basic_block
);
617 bitmap_vector_clear (comp
, last_basic_block
);
618 for (j
= n_entities
- 1; j
>= 0; j
--)
620 int m
= current_mode
[j
] = MODE_PRIORITY_TO_MODE (entity_map
[j
], i
);
621 struct bb_info
*info
= bb_info
[j
];
625 if (info
[bb
->index
].seginfo
->mode
== m
)
626 bitmap_set_bit (antic
[bb
->index
], j
);
628 if (info
[bb
->index
].computing
== m
)
629 bitmap_set_bit (comp
[bb
->index
], j
);
633 /* Calculate the optimal locations for the
634 placement mode switches to modes with priority I. */
637 bitmap_not (kill
[bb
->index
], transp
[bb
->index
]);
638 edge_list
= pre_edge_lcm (n_entities
, transp
, comp
, antic
,
639 kill
, &insert
, &del
);
641 for (j
= n_entities
- 1; j
>= 0; j
--)
643 /* Insert all mode sets that have been inserted by lcm. */
644 int no_mode
= num_modes
[entity_map
[j
]];
646 /* Wherever we have moved a mode setting upwards in the flow graph,
647 the blocks between the new setting site and the now redundant
648 computation ceases to be transparent for any lower-priority
649 mode of the same entity. First set the aux field of each
650 insertion site edge non-transparent, then propagate the new
651 non-transparency from the redundant computation upwards till
652 we hit an insertion site or an already non-transparent block. */
653 for (e
= NUM_EDGES (edge_list
) - 1; e
>= 0; e
--)
655 edge eg
= INDEX_EDGE (edge_list
, e
);
658 HARD_REG_SET live_at_edge
;
663 if (! bitmap_bit_p (insert
[e
], j
))
668 mode
= current_mode
[j
];
671 REG_SET_TO_HARD_REG_SET (live_at_edge
, df_get_live_out (src_bb
));
673 rtl_profile_for_edge (eg
);
675 EMIT_MODE_SET (entity_map
[j
], mode
, live_at_edge
);
676 mode_set
= get_insns ();
678 default_rtl_profile ();
680 /* Do not bother to insert empty sequence. */
681 if (mode_set
== NULL_RTX
)
684 /* We should not get an abnormal edge here. */
685 gcc_assert (! (eg
->flags
& EDGE_ABNORMAL
));
688 insert_insn_on_edge (mode_set
, eg
);
691 FOR_EACH_BB_REVERSE (bb
)
692 if (bitmap_bit_p (del
[bb
->index
], j
))
694 make_preds_opaque (bb
, j
);
695 /* Cancel the 'deleted' mode set. */
696 bb_info
[j
][bb
->index
].seginfo
->mode
= no_mode
;
700 sbitmap_vector_free (del
);
701 sbitmap_vector_free (insert
);
702 clear_aux_for_edges ();
703 free_edge_list (edge_list
);
706 /* Now output the remaining mode sets in all the segments. */
707 for (j
= n_entities
- 1; j
>= 0; j
--)
709 int no_mode
= num_modes
[entity_map
[j
]];
711 FOR_EACH_BB_REVERSE (bb
)
713 struct seginfo
*ptr
, *next
;
714 for (ptr
= bb_info
[j
][bb
->index
].seginfo
; ptr
; ptr
= next
)
717 if (ptr
->mode
!= no_mode
)
721 rtl_profile_for_bb (bb
);
723 EMIT_MODE_SET (entity_map
[j
], ptr
->mode
, ptr
->regs_live
);
724 mode_set
= get_insns ();
727 /* Insert MODE_SET only if it is nonempty. */
728 if (mode_set
!= NULL_RTX
)
731 if (NOTE_INSN_BASIC_BLOCK_P (ptr
->insn_ptr
))
732 emit_insn_after (mode_set
, ptr
->insn_ptr
);
734 emit_insn_before (mode_set
, ptr
->insn_ptr
);
737 default_rtl_profile ();
747 /* Finished. Free up all the things we've allocated. */
748 sbitmap_vector_free (kill
);
749 sbitmap_vector_free (antic
);
750 sbitmap_vector_free (transp
);
751 sbitmap_vector_free (comp
);
754 commit_edge_insertions ();
756 #if defined (MODE_ENTRY) && defined (MODE_EXIT)
757 cleanup_cfg (CLEANUP_NO_INSN_DEL
);
759 if (!need_commit
&& !emitted
)
766 #endif /* OPTIMIZE_MODE_SWITCHING */
769 gate_mode_switching (void)
771 #ifdef OPTIMIZE_MODE_SWITCHING
779 rest_of_handle_mode_switching (void)
781 #ifdef OPTIMIZE_MODE_SWITCHING
782 optimize_mode_switching ();
783 #endif /* OPTIMIZE_MODE_SWITCHING */
790 const pass_data pass_data_mode_switching
=
793 "mode_sw", /* name */
794 OPTGROUP_NONE
, /* optinfo_flags */
796 true, /* has_execute */
797 TV_MODE_SWITCH
, /* tv_id */
798 0, /* properties_required */
799 0, /* properties_provided */
800 0, /* properties_destroyed */
801 0, /* todo_flags_start */
802 ( TODO_df_finish
| TODO_verify_rtl_sharing
| 0 ), /* todo_flags_finish */
805 class pass_mode_switching
: public rtl_opt_pass
808 pass_mode_switching (gcc::context
*ctxt
)
809 : rtl_opt_pass (pass_data_mode_switching
, ctxt
)
812 /* opt_pass methods: */
813 /* The epiphany backend creates a second instance of this pass, so we need
815 opt_pass
* clone () { return new pass_mode_switching (m_ctxt
); }
816 bool gate () { return gate_mode_switching (); }
817 unsigned int execute () { return rest_of_handle_mode_switching (); }
819 }; // class pass_mode_switching
824 make_pass_mode_switching (gcc::context
*ctxt
)
826 return new pass_mode_switching (ctxt
);