1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010-2013 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for 3 passes: constraint pass,
23 inheritance/split pass, and pass for undoing failed inheritance and
26 The major goal of constraint pass is to transform RTL to satisfy
27 insn and address constraints by:
28 o choosing insn alternatives;
29 o generating *reload insns* (or reloads in brief) and *reload
30 pseudos* which will get necessary hard registers later;
31 o substituting pseudos with equivalent values and removing the
32 instructions that initialized those pseudos.
34 The constraint pass has biggest and most complicated code in LRA.
35 There are a lot of important details like:
36 o reuse of input reload pseudos to simplify reload pseudo
38 o some heuristics to choose insn alternative to improve the
42 The pass is mimicking former reload pass in alternative choosing
43 because the reload pass is oriented to current machine description
44 model. It might be changed if the machine description model is
47 There is special code for preventing all LRA and this pass cycling
50 On the first iteration of the pass we process every instruction and
51 choose an alternative for each one. On subsequent iterations we try
52 to avoid reprocessing instructions if we can be sure that the old
53 choice is still valid.
55 The inheritance/spilt pass is to transform code to achieve
56 ineheritance and live range splitting. It is done on backward
59 The inheritance optimization goal is to reuse values in hard
60 registers. There is analogous optimization in old reload pass. The
61 inheritance is achieved by following transformation:
63 reload_p1 <- p reload_p1 <- p
64 ... new_p <- reload_p1
66 reload_p2 <- p reload_p2 <- new_p
68 where p is spilled and not changed between the insns. Reload_p1 is
69 also called *original pseudo* and new_p is called *inheritance
72 The subsequent assignment pass will try to assign the same (or
73 another if it is not possible) hard register to new_p as to
74 reload_p1 or reload_p2.
76 If the assignment pass fails to assign a hard register to new_p,
77 this file will undo the inheritance and restore the original code.
78 This is because implementing the above sequence with a spilled
79 new_p would make the code much worse. The inheritance is done in
80 EBB scope. The above is just a simplified example to get an idea
81 of the inheritance as the inheritance is also done for non-reload
84 Splitting (transformation) is also done in EBB scope on the same
85 pass as the inheritance:
87 r <- ... or ... <- r r <- ... or ... <- r
88 ... s <- r (new insn -- save)
90 ... r <- s (new insn -- restore)
93 The *split pseudo* s is assigned to the hard register of the
94 original pseudo or hard register r.
97 o In EBBs with high register pressure for global pseudos (living
98 in at least 2 BBs) and assigned to hard registers when there
99 are more one reloads needing the hard registers;
100 o for pseudos needing save/restore code around calls.
102 If the split pseudo still has the same hard register as the
103 original pseudo after the subsequent assignment pass or the
104 original pseudo was split, the opposite transformation is done on
105 the same pass for undoing inheritance. */
111 #include "coretypes.h"
113 #include "hard-reg-set.h"
117 #include "insn-config.h"
118 #include "insn-codes.h"
121 #include "addresses.h"
123 #include "function.h"
125 #include "basic-block.h"
130 #include "rtl-error.h"
133 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
134 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
136 static int bb_reload_num
;
138 /* The current insn being processed and corresponding its single set
139 (NULL otherwise), its data (basic block, the insn data, the insn
140 static data, and the mode of each operand). */
141 static rtx curr_insn
;
142 static rtx curr_insn_set
;
143 static basic_block curr_bb
;
144 static lra_insn_recog_data_t curr_id
;
145 static struct lra_static_insn_data
*curr_static_id
;
146 static enum machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
150 /* Start numbers for new registers and insns at the current constraints
152 static int new_regno_start
;
153 static int new_insn_uid_start
;
155 /* If LOC is nonnull, strip any outer subreg from it. */
157 strip_subreg (rtx
*loc
)
159 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
162 /* Return hard regno of REGNO or if it is was not assigned to a hard
163 register, use a hard register from its allocno class. */
165 get_try_hard_regno (int regno
)
168 enum reg_class rclass
;
170 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
171 hard_regno
= lra_get_regno_hard_regno (regno
);
174 rclass
= lra_get_allocno_class (regno
);
175 if (rclass
== NO_REGS
)
177 return ira_class_hard_regs
[rclass
][0];
180 /* Return final hard regno (plus offset) which will be after
181 elimination. We do this for matching constraints because the final
182 hard regno could have a different class. */
184 get_final_hard_regno (int hard_regno
, int offset
)
188 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
189 return hard_regno
+ offset
;
192 /* Return hard regno of X after removing subreg and making
193 elimination. If X is not a register or subreg of register, return
194 -1. For pseudo use its assignment. */
196 get_hard_regno (rtx x
)
199 int offset
, hard_regno
;
202 if (GET_CODE (x
) == SUBREG
)
203 reg
= SUBREG_REG (x
);
206 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
207 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
211 if (GET_CODE (x
) == SUBREG
)
212 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
213 SUBREG_BYTE (x
), GET_MODE (x
));
214 return get_final_hard_regno (hard_regno
, offset
);
217 /* If REGNO is a hard register or has been allocated a hard register,
218 return the class of that register. If REGNO is a reload pseudo
219 created by the current constraints pass, return its allocno class.
220 Return NO_REGS otherwise. */
221 static enum reg_class
222 get_reg_class (int regno
)
226 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
227 hard_regno
= lra_get_regno_hard_regno (regno
);
230 hard_regno
= get_final_hard_regno (hard_regno
, 0);
231 return REGNO_REG_CLASS (hard_regno
);
233 if (regno
>= new_regno_start
)
234 return lra_get_allocno_class (regno
);
238 /* Return true if REG satisfies (or will satisfy) reg class constraint
239 CL. Use elimination first if REG is a hard register. If REG is a
240 reload pseudo created by this constraints pass, assume that it will
241 be allocated a hard register from its allocno class, but allow that
242 class to be narrowed to CL if it is currently a superset of CL.
244 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
245 REGNO (reg), or NO_REGS if no change in its class was needed. */
247 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
249 enum reg_class rclass
, common_class
;
250 enum machine_mode reg_mode
;
251 int class_size
, hard_regno
, nregs
, i
, j
;
252 int regno
= REGNO (reg
);
254 if (new_class
!= NULL
)
255 *new_class
= NO_REGS
;
256 if (regno
< FIRST_PSEUDO_REGISTER
)
259 rtx
*final_loc
= &final_reg
;
261 lra_eliminate_reg_if_possible (final_loc
);
262 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
264 reg_mode
= GET_MODE (reg
);
265 rclass
= get_reg_class (regno
);
266 if (regno
< new_regno_start
267 /* Do not allow the constraints for reload instructions to
268 influence the classes of new pseudos. These reloads are
269 typically moves that have many alternatives, and restricting
270 reload pseudos for one alternative may lead to situations
271 where other reload pseudos are no longer allocatable. */
272 || INSN_UID (curr_insn
) >= new_insn_uid_start
)
273 /* When we don't know what class will be used finally for reload
274 pseudos, we use ALL_REGS. */
275 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
276 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
277 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
278 lra_no_alloc_regs
)));
281 common_class
= ira_reg_class_subset
[rclass
][cl
];
282 if (new_class
!= NULL
)
283 *new_class
= common_class
;
284 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
287 /* Check that there are enough allocatable regs. */
288 class_size
= ira_class_hard_regs_num
[common_class
];
289 for (i
= 0; i
< class_size
; i
++)
291 hard_regno
= ira_class_hard_regs
[common_class
][i
];
292 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
295 for (j
= 0; j
< nregs
; j
++)
296 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
297 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
307 /* Return true if REGNO satisfies a memory constraint. */
311 return get_reg_class (regno
) == NO_REGS
;
314 /* If we have decided to substitute X with another value, return that
315 value, otherwise return X. */
317 get_equiv_substitution (rtx x
)
322 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
323 || ! ira_reg_equiv
[regno
].defined_p
324 || ! ira_reg_equiv
[regno
].profitable_p
325 || lra_get_regno_hard_regno (regno
) >= 0)
327 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
329 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
331 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
336 /* Set up curr_operand_mode. */
338 init_curr_operand_mode (void)
340 int nop
= curr_static_id
->n_operands
;
341 for (int i
= 0; i
< nop
; i
++)
343 enum machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
344 if (mode
== VOIDmode
)
346 /* The .md mode for address operands is the mode of the
347 addressed value rather than the mode of the address itself. */
348 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
351 mode
= curr_static_id
->operand
[i
].mode
;
353 curr_operand_mode
[i
] = mode
;
359 /* The page contains code to reuse input reloads. */
361 /* Structure describes input reload of the current insns. */
364 /* Reloaded value. */
366 /* Reload pseudo used. */
370 /* The number of elements in the following array. */
371 static int curr_insn_input_reloads_num
;
372 /* Array containing info about input reloads. It is used to find the
373 same input reload and reuse the reload pseudo in this case. */
374 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
376 /* Initiate data concerning reuse of input reloads for the current
379 init_curr_insn_input_reloads (void)
381 curr_insn_input_reloads_num
= 0;
384 /* Change class of pseudo REGNO to NEW_CLASS. Print info about it
385 using TITLE. Output a new line if NL_P. */
387 change_class (int regno
, enum reg_class new_class
,
388 const char *title
, bool nl_p
)
390 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
);
391 if (lra_dump_file
!= NULL
)
392 fprintf (lra_dump_file
, "%s to class %s for r%d",
393 title
, reg_class_names
[new_class
], regno
);
394 setup_reg_classes (regno
, new_class
, NO_REGS
, new_class
);
395 if (lra_dump_file
!= NULL
&& nl_p
)
396 fprintf (lra_dump_file
, "\n");
399 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
400 created input reload pseudo (only if TYPE is not OP_OUT). The
401 result pseudo is returned through RESULT_REG. Return TRUE if we
402 created a new pseudo, FALSE if we reused the already created input
403 reload pseudo. Use TITLE to describe new registers for debug
406 get_reload_reg (enum op_type type
, enum machine_mode mode
, rtx original
,
407 enum reg_class rclass
, const char *title
, rtx
*result_reg
)
410 enum reg_class new_class
;
415 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
418 /* Prevent reuse value of expression with side effects,
419 e.g. volatile memory. */
420 if (! side_effects_p (original
))
421 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
422 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
423 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
425 rtx reg
= curr_insn_input_reloads
[i
].reg
;
427 /* If input is equal to original and both are VOIDmode,
428 GET_MODE (reg) might be still different from mode.
429 Ensure we don't return *result_reg with wrong mode. */
430 if (GET_MODE (reg
) != mode
)
432 if (GET_MODE_SIZE (GET_MODE (reg
)) < GET_MODE_SIZE (mode
))
434 reg
= lowpart_subreg (mode
, reg
, GET_MODE (reg
));
435 if (reg
== NULL_RTX
|| GET_CODE (reg
) != SUBREG
)
439 if (lra_dump_file
!= NULL
)
441 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
442 dump_value_slim (lra_dump_file
, original
, 1);
444 if (new_class
!= lra_get_allocno_class (regno
))
445 change_class (regno
, new_class
, ", change", false);
446 if (lra_dump_file
!= NULL
)
447 fprintf (lra_dump_file
, "\n");
450 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
451 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
452 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
453 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
459 /* The page contains code to extract memory address parts. */
461 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
463 ok_for_index_p_nonstrict (rtx reg
)
465 unsigned regno
= REGNO (reg
);
467 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
470 /* A version of regno_ok_for_base_p for use here, when all pseudos
471 should count as OK. Arguments as for regno_ok_for_base_p. */
473 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
474 enum rtx_code outer_code
, enum rtx_code index_code
)
476 unsigned regno
= REGNO (reg
);
478 if (regno
>= FIRST_PSEUDO_REGISTER
)
480 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
485 /* The page contains major code to choose the current insn alternative
486 and generate reloads for it. */
488 /* Return the offset from REGNO of the least significant register
491 This function is used to tell whether two registers satisfy
492 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
494 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
495 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
497 lra_constraint_offset (int regno
, enum machine_mode mode
)
499 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
500 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
501 && SCALAR_INT_MODE_P (mode
))
502 return hard_regno_nregs
[regno
][mode
] - 1;
506 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
507 if they are the same hard reg, and has special hacks for
508 auto-increment and auto-decrement. This is specifically intended for
509 process_alt_operands to use in determining whether two operands
510 match. X is the operand whose number is the lower of the two.
512 It is supposed that X is the output operand and Y is the input
513 operand. Y_HARD_REGNO is the final hard regno of register Y or
514 register in subreg Y as we know it now. Otherwise, it is a
517 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
520 RTX_CODE code
= GET_CODE (x
);
525 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
526 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
530 i
= get_hard_regno (x
);
534 if ((j
= y_hard_regno
) < 0)
537 i
+= lra_constraint_offset (i
, GET_MODE (x
));
538 j
+= lra_constraint_offset (j
, GET_MODE (y
));
543 /* If two operands must match, because they are really a single
544 operand of an assembler insn, then two post-increments are invalid
545 because the assembler insn would increment only once. On the
546 other hand, a post-increment matches ordinary indexing if the
547 post-increment is the output operand. */
548 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
549 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
551 /* Two pre-increments are invalid because the assembler insn would
552 increment only once. On the other hand, a pre-increment matches
553 ordinary indexing if the pre-increment is the input operand. */
554 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
555 || GET_CODE (y
) == PRE_MODIFY
)
556 return operands_match_p (x
, XEXP (y
, 0), -1);
560 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
561 && x
== SUBREG_REG (y
))
563 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
564 && SUBREG_REG (x
) == y
)
567 /* Now we have disposed of all the cases in which different rtx
569 if (code
!= GET_CODE (y
))
572 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
573 if (GET_MODE (x
) != GET_MODE (y
))
582 return XEXP (x
, 0) == XEXP (y
, 0);
584 return XSTR (x
, 0) == XSTR (y
, 0);
590 /* Compare the elements. If any pair of corresponding elements fail
591 to match, return false for the whole things. */
593 fmt
= GET_RTX_FORMAT (code
);
594 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
600 if (XWINT (x
, i
) != XWINT (y
, i
))
605 if (XINT (x
, i
) != XINT (y
, i
))
610 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
619 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
621 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
623 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
629 /* It is believed that rtx's at this level will never
630 contain anything but integers and other rtx's, except for
631 within LABEL_REFs and SYMBOL_REFs. */
639 /* True if X is a constant that can be forced into the constant pool.
640 MODE is the mode of the operand, or VOIDmode if not known. */
641 #define CONST_POOL_OK_P(MODE, X) \
642 ((MODE) != VOIDmode \
644 && GET_CODE (X) != HIGH \
645 && !targetm.cannot_force_const_mem (MODE, X))
647 /* True if C is a non-empty register class that has too few registers
648 to be safely used as a reload target class. */
649 #define SMALL_REGISTER_CLASS_P(C) \
650 (reg_class_size [(C)] == 1 \
651 || (reg_class_size [(C)] >= 1 && targetm.class_likely_spilled_p (C)))
653 /* If REG is a reload pseudo, try to make its class satisfying CL. */
655 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
657 enum reg_class rclass
;
659 /* Do not make more accurate class from reloads generated. They are
660 mostly moves with a lot of constraints. Making more accurate
661 class may results in very narrow class and impossibility of find
662 registers for several reloads of one insn. */
663 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
665 if (GET_CODE (reg
) == SUBREG
)
666 reg
= SUBREG_REG (reg
);
667 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
669 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
670 change_class (REGNO (reg
), rclass
, " Change", true);
673 /* Generate reloads for matching OUT and INS (array of input operand
674 numbers with end marker -1) with reg class GOAL_CLASS. Add input
675 and output reloads correspondingly to the lists *BEFORE and *AFTER.
676 OUT might be negative. In this case we generate input reloads for
677 matched input operands INS. */
679 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
680 rtx
*before
, rtx
*after
)
683 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
684 enum machine_mode inmode
, outmode
;
685 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
686 rtx out_rtx
= out
< 0 ? in_rtx
: *curr_id
->operand_loc
[out
];
688 inmode
= curr_operand_mode
[ins
[0]];
689 outmode
= out
< 0 ? inmode
: curr_operand_mode
[out
];
690 push_to_sequence (*before
);
691 if (inmode
!= outmode
)
693 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
696 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
698 if (SCALAR_INT_MODE_P (inmode
))
699 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
701 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
702 LRA_SUBREG_P (new_out_reg
) = 1;
703 /* If the input reg is dying here, we can use the same hard
704 register for REG and IN_RTX. We do it only for original
705 pseudos as reload pseudos can die although original
706 pseudos still live where reload pseudos dies. */
707 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
708 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
709 lra_assign_reg_val (REGNO (in_rtx
), REGNO (reg
));
714 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
716 if (SCALAR_INT_MODE_P (outmode
))
717 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
719 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
720 /* NEW_IN_REG is non-paradoxical subreg. We don't want
721 NEW_OUT_REG living above. We add clobber clause for
722 this. This is just a temporary clobber. We can remove
723 it at the end of LRA work. */
724 clobber
= emit_clobber (new_out_reg
);
725 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
726 LRA_SUBREG_P (new_in_reg
) = 1;
727 if (GET_CODE (in_rtx
) == SUBREG
)
729 rtx subreg_reg
= SUBREG_REG (in_rtx
);
731 /* If SUBREG_REG is dying here and sub-registers IN_RTX
732 and NEW_IN_REG are similar, we can use the same hard
733 register for REG and SUBREG_REG. */
734 if (REG_P (subreg_reg
)
735 && (int) REGNO (subreg_reg
) < lra_new_regno_start
736 && GET_MODE (subreg_reg
) == outmode
737 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
738 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
739 lra_assign_reg_val (REGNO (subreg_reg
), REGNO (reg
));
745 /* Pseudos have values -- see comments for lra_reg_info.
746 Different pseudos with the same value do not conflict even if
747 they live in the same place. When we create a pseudo we
748 assign value of original pseudo (if any) from which we
749 created the new pseudo. If we create the pseudo from the
750 input pseudo, the new pseudo will no conflict with the input
751 pseudo which is wrong when the input pseudo lives after the
752 insn and as the new pseudo value is changed by the insn
753 output. Therefore we create the new pseudo from the output.
755 We cannot reuse the current output register because we might
756 have a situation like "a <- a op b", where the constraints
757 force the second input operand ("b") to match the output
758 operand ("a"). "b" must then be copied into a new register
759 so that it doesn't clobber the current value of "a". */
761 new_in_reg
= new_out_reg
762 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
765 /* In operand can be got from transformations before processing insn
766 constraints. One example of such transformations is subreg
767 reloading (see function simplify_operand_subreg). The new
768 pseudos created by the transformations might have inaccurate
769 class (ALL_REGS) and we should make their classes more
771 narrow_reload_pseudo_class (in_rtx
, goal_class
);
772 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
773 *before
= get_insns ();
775 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
778 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
779 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
780 *curr_id
->operand_loc
[in
] = new_in_reg
;
782 lra_update_dups (curr_id
, ins
);
785 /* See a comment for the input operand above. */
786 narrow_reload_pseudo_class (out_rtx
, goal_class
);
787 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
790 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
792 *after
= get_insns ();
795 *curr_id
->operand_loc
[out
] = new_out_reg
;
796 lra_update_dup (curr_id
, out
);
799 /* Return register class which is union of all reg classes in insn
800 constraint alternative string starting with P. */
801 static enum reg_class
802 reg_class_from_constraints (const char *p
)
805 enum reg_class op_class
= NO_REGS
;
808 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
815 op_class
= (reg_class_subunion
816 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
822 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
826 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
828 #ifdef EXTRA_CONSTRAINT_STR
829 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
831 = (reg_class_subunion
832 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
839 = reg_class_subunion
[op_class
][REG_CLASS_FROM_CONSTRAINT (c
, p
)];
842 while ((p
+= len
), c
);
846 /* If OP is a register, return the class of the register as per
847 get_reg_class, otherwise return NO_REGS. */
848 static inline enum reg_class
849 get_op_class (rtx op
)
851 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
854 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
855 otherwise. If modes of MEM_PSEUDO and VAL are different, use
856 SUBREG for VAL to make them equal. */
858 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
860 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
862 /* Usually size of mem_pseudo is greater than val size but in
863 rare cases it can be less as it can be defined by target
864 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */
867 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
868 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
870 LRA_SUBREG_P (val
) = 1;
874 mem_pseudo
= gen_lowpart_SUBREG (GET_MODE (val
), mem_pseudo
);
875 LRA_SUBREG_P (mem_pseudo
) = 1;
879 ? gen_move_insn (mem_pseudo
, val
)
880 : gen_move_insn (val
, mem_pseudo
));
883 /* Process a special case insn (register move), return true if we
884 don't need to process it anymore. INSN should be a single set
885 insn. Set up that RTL was changed through CHANGE_P and macro
886 SECONDARY_MEMORY_NEEDED says to use secondary memory through
889 check_and_process_move (bool *change_p
, bool *sec_mem_p ATTRIBUTE_UNUSED
)
892 rtx dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, before
, scratch_reg
;
893 enum reg_class dclass
, sclass
, secondary_class
;
894 enum machine_mode sreg_mode
;
895 secondary_reload_info sri
;
897 lra_assert (curr_insn_set
!= NULL_RTX
);
898 dreg
= dest
= SET_DEST (curr_insn_set
);
899 sreg
= src
= SET_SRC (curr_insn_set
);
900 if (GET_CODE (dest
) == SUBREG
)
901 dreg
= SUBREG_REG (dest
);
902 if (GET_CODE (src
) == SUBREG
)
903 sreg
= SUBREG_REG (src
);
904 if (! (REG_P (dreg
) || MEM_P (dreg
)) || ! (REG_P (sreg
) || MEM_P (sreg
)))
906 sclass
= dclass
= NO_REGS
;
908 dclass
= get_reg_class (REGNO (dreg
));
909 if (dclass
== ALL_REGS
)
910 /* ALL_REGS is used for new pseudos created by transformations
911 like reload of SUBREG_REG (see function
912 simplify_operand_subreg). We don't know their class yet. We
913 should figure out the class from processing the insn
914 constraints not in this fast path function. Even if ALL_REGS
915 were a right class for the pseudo, secondary_... hooks usually
916 are not define for ALL_REGS. */
918 sreg_mode
= GET_MODE (sreg
);
921 sclass
= get_reg_class (REGNO (sreg
));
922 if (sclass
== ALL_REGS
)
923 /* See comments above. */
925 if (sclass
== NO_REGS
&& dclass
== NO_REGS
)
927 #ifdef SECONDARY_MEMORY_NEEDED
928 if (SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
))
929 #ifdef SECONDARY_MEMORY_NEEDED_MODE
930 && ((sclass
!= NO_REGS
&& dclass
!= NO_REGS
)
931 || GET_MODE (src
) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
)))
939 if (! REG_P (dreg
) || ! REG_P (sreg
))
942 sri
.icode
= CODE_FOR_nothing
;
944 secondary_class
= NO_REGS
;
945 /* Set up hard register for a reload pseudo for hook
946 secondary_reload because some targets just ignore unassigned
947 pseudos in the hook. */
948 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
950 dregno
= REGNO (dreg
);
951 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
955 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
957 sregno
= REGNO (sreg
);
958 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
962 if (sclass
!= NO_REGS
)
964 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
965 (reg_class_t
) sclass
,
966 GET_MODE (src
), &sri
);
967 if (sclass
== NO_REGS
968 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
969 && dclass
!= NO_REGS
))
971 enum reg_class old_sclass
= secondary_class
;
972 secondary_reload_info old_sri
= sri
;
975 sri
.icode
= CODE_FOR_nothing
;
978 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
979 (reg_class_t
) dclass
,
981 /* Check the target hook consistency. */
983 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
984 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
985 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
988 reg_renumber
[sregno
] = -1;
990 reg_renumber
[dregno
] = -1;
991 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
995 if (secondary_class
!= NO_REGS
)
996 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
1000 if (old_sreg
!= sreg
)
1001 sreg
= copy_rtx (sreg
);
1002 if (sri
.icode
== CODE_FOR_nothing
)
1003 lra_emit_move (new_reg
, sreg
);
1006 enum reg_class scratch_class
;
1008 scratch_class
= (reg_class_from_constraints
1009 (insn_data
[sri
.icode
].operand
[2].constraint
));
1010 scratch_reg
= (lra_create_new_reg_with_unique_value
1011 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
1012 scratch_class
, "scratch"));
1013 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
1014 sreg
, scratch_reg
));
1016 before
= get_insns ();
1018 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Inserting the move");
1019 if (new_reg
!= NULL_RTX
)
1021 if (GET_CODE (src
) == SUBREG
)
1022 SUBREG_REG (src
) = new_reg
;
1024 SET_SRC (curr_insn_set
) = new_reg
;
1028 if (lra_dump_file
!= NULL
)
1030 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1031 dump_insn_slim (lra_dump_file
, curr_insn
);
1033 lra_set_insn_deleted (curr_insn
);
1039 /* The following data describe the result of process_alt_operands.
1040 The data are used in curr_insn_transform to generate reloads. */
1042 /* The chosen reg classes which should be used for the corresponding
1044 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1045 /* True if the operand should be the same as another operand and that
1046 other operand does not need a reload. */
1047 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1048 /* True if the operand does not need a reload. */
1049 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1050 /* True if the operand can be offsetable memory. */
1051 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1052 /* The number of an operand to which given operand can be matched to. */
1053 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1054 /* The number of elements in the following array. */
1055 static int goal_alt_dont_inherit_ops_num
;
1056 /* Numbers of operands whose reload pseudos should not be inherited. */
1057 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1058 /* True if the insn commutative operands should be swapped. */
1059 static bool goal_alt_swapped
;
1060 /* The chosen insn alternative. */
1061 static int goal_alt_number
;
1063 /* The following five variables are used to choose the best insn
1064 alternative. They reflect final characteristics of the best
1067 /* Number of necessary reloads and overall cost reflecting the
1068 previous value and other unpleasantness of the best alternative. */
1069 static int best_losers
, best_overall
;
1070 /* Overall number hard registers used for reloads. For example, on
1071 some targets we need 2 general registers to reload DFmode and only
1072 one floating point register. */
1073 static int best_reload_nregs
;
1074 /* Overall number reflecting distances of previous reloading the same
1075 value. The distances are counted from the current BB start. It is
1076 used to improve inheritance chances. */
1077 static int best_reload_sum
;
1079 /* True if the current insn should have no correspondingly input or
1081 static bool no_input_reloads_p
, no_output_reloads_p
;
1083 /* True if we swapped the commutative operands in the current
1085 static int curr_swapped
;
1087 /* Arrange for address element *LOC to be a register of class CL.
1088 Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an
1089 automodified value; handle that case by adding the required output
1090 reloads to list AFTER. Return true if the RTL was changed. */
1092 process_addr_reg (rtx
*loc
, rtx
*before
, rtx
*after
, enum reg_class cl
)
1095 enum reg_class rclass
, new_class
;
1098 enum machine_mode mode
;
1099 bool before_p
= false;
1101 loc
= strip_subreg (loc
);
1103 mode
= GET_MODE (reg
);
1106 /* Always reload memory in an address even if the target supports
1108 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1113 regno
= REGNO (reg
);
1114 rclass
= get_reg_class (regno
);
1115 if ((*loc
= get_equiv_substitution (reg
)) != reg
)
1117 if (lra_dump_file
!= NULL
)
1119 fprintf (lra_dump_file
,
1120 "Changing pseudo %d in address of insn %u on equiv ",
1121 REGNO (reg
), INSN_UID (curr_insn
));
1122 dump_value_slim (lra_dump_file
, *loc
, 1);
1123 fprintf (lra_dump_file
, "\n");
1125 *loc
= copy_rtx (*loc
);
1127 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1130 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1131 mode
, reg
, cl
, "address", &new_reg
))
1134 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1136 change_class (regno
, new_class
, " Change", true);
1144 push_to_sequence (*before
);
1145 lra_emit_move (new_reg
, reg
);
1146 *before
= get_insns ();
1153 lra_emit_move (reg
, new_reg
);
1155 *after
= get_insns ();
1161 /* Insert move insn in simplify_operand_subreg. BEFORE returns
1162 the insn to be inserted before curr insn. AFTER returns the
1163 the insn to be inserted after curr insn. ORIGREG and NEWREG
1164 are the original reg and new reg for reload. */
1166 insert_move_for_subreg (rtx
*before
, rtx
*after
, rtx origreg
, rtx newreg
)
1170 push_to_sequence (*before
);
1171 lra_emit_move (newreg
, origreg
);
1172 *before
= get_insns ();
1178 lra_emit_move (origreg
, newreg
);
1180 *after
= get_insns ();
1185 /* Make reloads for subreg in operand NOP with internal subreg mode
1186 REG_MODE, add new reloads for further processing. Return true if
1187 any reload was generated. */
1189 simplify_operand_subreg (int nop
, enum machine_mode reg_mode
)
1193 enum machine_mode mode
;
1195 rtx operand
= *curr_id
->operand_loc
[nop
];
1196 enum reg_class regclass
;
1199 before
= after
= NULL_RTX
;
1201 if (GET_CODE (operand
) != SUBREG
)
1204 mode
= GET_MODE (operand
);
1205 reg
= SUBREG_REG (operand
);
1206 type
= curr_static_id
->operand
[nop
].type
;
1207 /* If we change address for paradoxical subreg of memory, the
1208 address might violate the necessary alignment or the access might
1209 be slow. So take this into consideration. We should not worry
1210 about access beyond allocated memory for paradoxical memory
1211 subregs as we don't substitute such equiv memory (see processing
1212 equivalences in function lra_constraints) and because for spilled
1213 pseudos we allocate stack memory enough for the biggest
1214 corresponding paradoxical subreg. */
1216 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1217 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1218 || (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
))
1220 alter_subreg (curr_id
->operand_loc
[nop
], false);
1223 /* Put constant into memory when we have mixed modes. It generates
1224 a better code in most cases as it does not need a secondary
1225 reload memory. It also prevents LRA looping when LRA is using
1226 secondary reload memory again and again. */
1227 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1228 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1230 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1231 alter_subreg (curr_id
->operand_loc
[nop
], false);
1234 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1235 if there may be a problem accessing OPERAND in the outer
1238 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1239 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1240 /* Don't reload paradoxical subregs because we could be looping
1241 having repeatedly final regno out of hard regs range. */
1242 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1243 >= hard_regno_nregs
[hard_regno
][mode
])
1244 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1245 SUBREG_BYTE (operand
), mode
) < 0
1246 /* Don't reload subreg for matching reload. It is actually
1247 valid subreg in LRA. */
1248 && ! LRA_SUBREG_P (operand
))
1249 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1251 /* The class will be defined later in curr_insn_transform. */
1252 enum reg_class rclass
1253 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1255 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, reg_mode
, reg
,
1256 rclass
, "subreg reg", &new_reg
))
1258 bool insert_before
, insert_after
;
1259 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1261 insert_before
= (type
!= OP_OUT
1262 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
));
1263 insert_after
= (type
!= OP_IN
);
1264 insert_move_for_subreg (insert_before
? &before
: NULL
,
1265 insert_after
? &after
: NULL
,
1268 SUBREG_REG (operand
) = new_reg
;
1269 lra_process_new_insns (curr_insn
, before
, after
,
1270 "Inserting subreg reload");
1273 /* Force a reload for a paradoxical subreg. For paradoxical subreg,
1274 IRA allocates hardreg to the inner pseudo reg according to its mode
1275 instead of the outermode, so the size of the hardreg may not be enough
1276 to contain the outermode operand, in that case we may need to insert
1277 reload for the reg. For the following two types of paradoxical subreg,
1278 we need to insert reload:
1279 1. If the op_type is OP_IN, and the hardreg could not be paired with
1280 other hardreg to contain the outermode operand
1281 (checked by in_hard_reg_set_p), we need to insert the reload.
1282 2. If the op_type is OP_OUT or OP_INOUT.
1284 Here is a paradoxical subreg example showing how the reload is generated:
1286 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1287 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64}
1289 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example
1290 here, if reg107 is assigned to hardreg R15, because R15 is the last
1291 hardreg, compiler cannot find another hardreg to pair with R15 to
1292 contain TImode data. So we insert a TImode reload reg180 for it.
1293 After reload is inserted:
1295 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0)
1296 (reg:DI 107 [ __comp ])) -1
1297 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ])
1298 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64}
1300 Two reload hard registers will be allocated to reg180 to save TImode data
1302 else if (REG_P (reg
)
1303 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1304 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1305 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1306 < hard_regno_nregs
[hard_regno
][mode
])
1307 && (regclass
= lra_get_allocno_class (REGNO (reg
)))
1309 || !in_hard_reg_set_p (reg_class_contents
[regclass
],
1312 /* The class will be defined later in curr_insn_transform. */
1313 enum reg_class rclass
1314 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1316 if (get_reload_reg (curr_static_id
->operand
[nop
].type
, mode
, reg
,
1317 rclass
, "paradoxical subreg", &new_reg
))
1320 bool insert_before
, insert_after
;
1322 PUT_MODE (new_reg
, mode
);
1323 subreg
= simplify_gen_subreg (GET_MODE (reg
), new_reg
, mode
, 0);
1324 bitmap_set_bit (&lra_subreg_reload_pseudos
, REGNO (new_reg
));
1326 insert_before
= (type
!= OP_OUT
);
1327 insert_after
= (type
!= OP_IN
);
1328 insert_move_for_subreg (insert_before
? &before
: NULL
,
1329 insert_after
? &after
: NULL
,
1332 SUBREG_REG (operand
) = new_reg
;
1333 lra_process_new_insns (curr_insn
, before
, after
,
1334 "Inserting paradoxical subreg reload");
1340 /* Return TRUE if X refers for a hard register from SET. */
1342 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1344 int i
, j
, x_hard_regno
;
1345 enum machine_mode mode
;
1351 code
= GET_CODE (x
);
1352 mode
= GET_MODE (x
);
1356 code
= GET_CODE (x
);
1357 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1358 mode
= GET_MODE (x
);
1363 x_hard_regno
= get_hard_regno (x
);
1364 return (x_hard_regno
>= 0
1365 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1369 struct address_info ad
;
1371 decompose_mem_address (&ad
, x
);
1372 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1374 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1377 fmt
= GET_RTX_FORMAT (code
);
1378 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1382 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1385 else if (fmt
[i
] == 'E')
1387 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1388 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1395 /* Return true if OP is a spilled pseudo. */
1397 spilled_pseudo_p (rtx op
)
1400 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1403 /* Return true if X is a general constant. */
1405 general_constant_p (rtx x
)
1407 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1411 reg_in_class_p (rtx reg
, enum reg_class cl
)
1414 return get_reg_class (REGNO (reg
)) == NO_REGS
;
1415 return in_class_p (reg
, cl
, NULL
);
1418 /* Major function to choose the current insn alternative and what
1419 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1420 negative we should consider only this alternative. Return false if
1421 we can not choose the alternative or find how to reload the
1424 process_alt_operands (int only_alternative
)
1427 int nop
, overall
, nalt
;
1428 int n_alternatives
= curr_static_id
->n_alternatives
;
1429 int n_operands
= curr_static_id
->n_operands
;
1430 /* LOSERS counts the operands that don't fit this alternative and
1431 would require loading. */
1433 /* REJECT is a count of how undesirable this alternative says it is
1434 if any reloading is required. If the alternative matches exactly
1435 then REJECT is ignored, but otherwise it gets this much counted
1436 against it in addition to the reloading needed. */
1438 /* The number of elements in the following array. */
1439 int early_clobbered_regs_num
;
1440 /* Numbers of operands which are early clobber registers. */
1441 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1442 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1443 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1444 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1445 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1446 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1447 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1448 /* The number of elements in the following array. */
1449 int curr_alt_dont_inherit_ops_num
;
1450 /* Numbers of operands whose reload pseudos should not be inherited. */
1451 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1453 /* The register when the operand is a subreg of register, otherwise the
1455 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1456 /* The register if the operand is a register or subreg of register,
1458 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1459 int hard_regno
[MAX_RECOG_OPERANDS
];
1460 enum machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1461 int reload_nregs
, reload_sum
;
1465 /* Calculate some data common for all alternatives to speed up the
1467 for (nop
= 0; nop
< n_operands
; nop
++)
1469 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1470 /* The real hard regno of the operand after the allocation. */
1471 hard_regno
[nop
] = get_hard_regno (op
);
1473 operand_reg
[nop
] = op
;
1474 biggest_mode
[nop
] = GET_MODE (operand_reg
[nop
]);
1475 if (GET_CODE (operand_reg
[nop
]) == SUBREG
)
1477 operand_reg
[nop
] = SUBREG_REG (operand_reg
[nop
]);
1478 if (GET_MODE_SIZE (biggest_mode
[nop
])
1479 < GET_MODE_SIZE (GET_MODE (operand_reg
[nop
])))
1480 biggest_mode
[nop
] = GET_MODE (operand_reg
[nop
]);
1482 if (REG_P (operand_reg
[nop
]))
1483 no_subreg_reg_operand
[nop
] = operand_reg
[nop
];
1485 operand_reg
[nop
] = NULL_RTX
;
1488 /* The constraints are made of several alternatives. Each operand's
1489 constraint looks like foo,bar,... with commas separating the
1490 alternatives. The first alternatives for all operands go
1491 together, the second alternatives go together, etc.
1493 First loop over alternatives. */
1494 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1496 /* Loop over operands for one constraint alternative. */
1497 #if HAVE_ATTR_enabled
1498 if (curr_id
->alternative_enabled_p
!= NULL
1499 && ! curr_id
->alternative_enabled_p
[nalt
])
1503 if (only_alternative
>= 0 && nalt
!= only_alternative
)
1507 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1508 for (nop
= 0; nop
< n_operands
; nop
++)
1510 int inc
= (curr_static_id
1511 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1512 if (lra_dump_file
!= NULL
&& inc
!= 0)
1513 fprintf (lra_dump_file
,
1514 " Staticly defined alt reject+=%d\n", inc
);
1517 early_clobbered_regs_num
= 0;
1519 for (nop
= 0; nop
< n_operands
; nop
++)
1523 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1524 bool win
, did_match
, offmemok
, early_clobber_p
;
1525 /* false => this operand can be reloaded somehow for this
1528 /* true => this operand can be reloaded if the alternative
1531 /* True if a constant forced into memory would be OK for
1534 enum reg_class this_alternative
, this_costly_alternative
;
1535 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1536 bool this_alternative_match_win
, this_alternative_win
;
1537 bool this_alternative_offmemok
;
1539 enum machine_mode mode
;
1541 opalt_num
= nalt
* n_operands
+ nop
;
1542 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1544 /* Fast track for no constraints at all. */
1545 curr_alt
[nop
] = NO_REGS
;
1546 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1547 curr_alt_win
[nop
] = true;
1548 curr_alt_match_win
[nop
] = false;
1549 curr_alt_offmemok
[nop
] = false;
1550 curr_alt_matches
[nop
] = -1;
1554 op
= no_subreg_reg_operand
[nop
];
1555 mode
= curr_operand_mode
[nop
];
1557 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1560 early_clobber_p
= false;
1561 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1563 this_costly_alternative
= this_alternative
= NO_REGS
;
1564 /* We update set of possible hard regs besides its class
1565 because reg class might be inaccurate. For example,
1566 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1567 is translated in HI_REGS because classes are merged by
1568 pairs and there is no accurate intermediate class. */
1569 CLEAR_HARD_REG_SET (this_alternative_set
);
1570 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1571 this_alternative_win
= false;
1572 this_alternative_match_win
= false;
1573 this_alternative_offmemok
= false;
1574 this_alternative_matches
= -1;
1576 /* An empty constraint should be excluded by the fast
1578 lra_assert (*p
!= 0 && *p
!= ',');
1580 /* Scan this alternative's specs for this operand; set WIN
1581 if the operand fits any letter in this alternative.
1582 Otherwise, clear BADOP if this operand could fit some
1583 letter after reloads, or set WINREG if this operand could
1584 fit after reloads provided the constraint allows some
1589 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1598 case '=': case '+': case '?': case '*': case '!':
1599 case ' ': case '\t':
1603 /* We only support one commutative marker, the first
1604 one. We already set commutative above. */
1608 early_clobber_p
= true;
1612 /* Ignore rest of this alternative. */
1616 case '0': case '1': case '2': case '3': case '4':
1617 case '5': case '6': case '7': case '8': case '9':
1622 m
= strtoul (p
, &end
, 10);
1625 lra_assert (nop
> m
);
1627 this_alternative_matches
= m
;
1628 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1629 /* We are supposed to match a previous operand.
1630 If we do, we win if that one did. If we do
1631 not, count both of the operands as losers.
1632 (This is too conservative, since most of the
1633 time only a single reload insn will be needed
1634 to make the two operands win. As a result,
1635 this alternative may be rejected when it is
1636 actually desirable.) */
1638 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1639 *curr_id
->operand_loc
[m
], m_hregno
))
1641 /* We should reject matching of an early
1642 clobber operand if the matching operand is
1643 not dying in the insn. */
1644 if (! curr_static_id
->operand
[m
].early_clobber
1645 || operand_reg
[nop
] == NULL_RTX
1646 || (find_regno_note (curr_insn
, REG_DEAD
,
1648 || REGNO (op
) == REGNO (operand_reg
[m
])))
1653 /* If we are matching a non-offsettable
1654 address where an offsettable address was
1655 expected, then we must reject this
1656 combination, because we can't reload
1658 if (curr_alt_offmemok
[m
]
1659 && MEM_P (*curr_id
->operand_loc
[m
])
1660 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1666 /* Operands don't match. Both operands must
1667 allow a reload register, otherwise we
1668 cannot make them match. */
1669 if (curr_alt
[m
] == NO_REGS
)
1671 /* Retroactively mark the operand we had to
1672 match as a loser, if it wasn't already and
1673 it wasn't matched to a register constraint
1674 (e.g it might be matched by memory). */
1676 && (operand_reg
[m
] == NULL_RTX
1677 || hard_regno
[m
] < 0))
1681 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1682 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1685 /* We prefer no matching alternatives because
1686 it gives more freedom in RA. */
1687 if (operand_reg
[nop
] == NULL_RTX
1688 || (find_regno_note (curr_insn
, REG_DEAD
,
1689 REGNO (operand_reg
[nop
]))
1692 if (lra_dump_file
!= NULL
)
1695 " %d Matching alt: reject+=2\n",
1700 /* If we have to reload this operand and some
1701 previous operand also had to match the same
1702 thing as this operand, we don't know how to do
1704 if (!match_p
|| !curr_alt_win
[m
])
1706 for (i
= 0; i
< nop
; i
++)
1707 if (curr_alt_matches
[i
] == m
)
1715 /* This can be fixed with reloads if the operand
1716 we are supposed to match can be fixed with
1719 this_alternative
= curr_alt
[m
];
1720 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1721 winreg
= this_alternative
!= NO_REGS
;
1726 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1728 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1729 IOR_HARD_REG_SET (this_alternative_set
,
1730 reg_class_contents
[cl
]);
1733 this_costly_alternative
1734 = reg_class_subunion
[this_costly_alternative
][cl
];
1735 IOR_HARD_REG_SET (this_costly_alternative_set
,
1736 reg_class_contents
[cl
]);
1742 case TARGET_MEM_CONSTRAINT
:
1743 if (MEM_P (op
) || spilled_pseudo_p (op
))
1745 /* We can put constant or pseudo value into memory
1746 to satisfy the constraint. */
1747 if (CONST_POOL_OK_P (mode
, op
) || REG_P (op
))
1754 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1755 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1761 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1762 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1766 /* Memory op whose address is not offsettable. */
1769 && ! offsettable_nonstrict_memref_p (op
))
1773 /* Memory operand whose address is offsettable. */
1776 && offsettable_nonstrict_memref_p (op
))
1777 || spilled_pseudo_p (op
))
1779 /* We can put constant or pseudo value into memory
1780 or make memory address offsetable to satisfy the
1782 if (CONST_POOL_OK_P (mode
, op
) || MEM_P (op
) || REG_P (op
))
1790 if (GET_CODE (op
) == CONST_DOUBLE
1791 || (GET_CODE (op
) == CONST_VECTOR
1792 && (GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)))
1798 if (CONST_DOUBLE_AS_FLOAT_P (op
)
1799 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
1804 if (CONST_SCALAR_INT_P (op
))
1808 if (general_constant_p (op
))
1813 if (CONST_SCALAR_INT_P (op
))
1825 if (CONST_INT_P (op
)
1826 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
1831 /* This constraint should be excluded by the fast
1838 || general_constant_p (op
)
1839 || spilled_pseudo_p (op
))
1841 /* Drop through into 'r' case. */
1845 = reg_class_subunion
[this_alternative
][GENERAL_REGS
];
1846 IOR_HARD_REG_SET (this_alternative_set
,
1847 reg_class_contents
[GENERAL_REGS
]);
1850 this_costly_alternative
1851 = (reg_class_subunion
1852 [this_costly_alternative
][GENERAL_REGS
]);
1853 IOR_HARD_REG_SET (this_costly_alternative_set
,
1854 reg_class_contents
[GENERAL_REGS
]);
1859 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
1861 #ifdef EXTRA_CONSTRAINT_STR
1862 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
1864 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1866 else if (spilled_pseudo_p (op
))
1869 /* If we didn't already win, we can reload
1870 constants via force_const_mem or put the
1871 pseudo value into memory, or make other
1872 memory by reloading the address like for
1874 if (CONST_POOL_OK_P (mode
, op
)
1875 || MEM_P (op
) || REG_P (op
))
1881 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1883 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1886 /* If we didn't already win, we can reload
1887 the address into a base register. */
1888 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1891 = reg_class_subunion
[this_alternative
][cl
];
1892 IOR_HARD_REG_SET (this_alternative_set
,
1893 reg_class_contents
[cl
]);
1896 this_costly_alternative
1897 = (reg_class_subunion
1898 [this_costly_alternative
][cl
]);
1899 IOR_HARD_REG_SET (this_costly_alternative_set
,
1900 reg_class_contents
[cl
]);
1906 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1912 cl
= REG_CLASS_FROM_CONSTRAINT (c
, p
);
1913 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1914 IOR_HARD_REG_SET (this_alternative_set
,
1915 reg_class_contents
[cl
]);
1918 this_costly_alternative
1919 = reg_class_subunion
[this_costly_alternative
][cl
];
1920 IOR_HARD_REG_SET (this_costly_alternative_set
,
1921 reg_class_contents
[cl
]);
1924 if (mode
== BLKmode
)
1929 if (hard_regno
[nop
] >= 0
1930 && in_hard_reg_set_p (this_alternative_set
,
1931 mode
, hard_regno
[nop
]))
1933 else if (hard_regno
[nop
] < 0
1934 && in_class_p (op
, this_alternative
, NULL
))
1939 if (c
!= ' ' && c
!= '\t')
1940 costly_p
= c
== '*';
1942 while ((p
+= len
), c
);
1944 scratch_p
= (operand_reg
[nop
] != NULL_RTX
1945 && lra_former_scratch_p (REGNO (operand_reg
[nop
])));
1946 /* Record which operands fit this alternative. */
1949 this_alternative_win
= true;
1950 if (operand_reg
[nop
] != NULL_RTX
)
1952 if (hard_regno
[nop
] >= 0)
1954 if (in_hard_reg_set_p (this_costly_alternative_set
,
1955 mode
, hard_regno
[nop
]))
1957 if (lra_dump_file
!= NULL
)
1958 fprintf (lra_dump_file
,
1959 " %d Costly set: reject++\n",
1966 /* Prefer won reg to spilled pseudo under other
1967 equal conditions for possibe inheritance. */
1970 if (lra_dump_file
!= NULL
)
1973 " %d Non pseudo reload: reject++\n",
1977 if (in_class_p (operand_reg
[nop
],
1978 this_costly_alternative
, NULL
))
1980 if (lra_dump_file
!= NULL
)
1983 " %d Non pseudo costly reload:"
1989 /* We simulate the behaviour of old reload here.
1990 Although scratches need hard registers and it
1991 might result in spilling other pseudos, no reload
1992 insns are generated for the scratches. So it
1993 might cost something but probably less than old
1994 reload pass believes. */
1997 if (lra_dump_file
!= NULL
)
1998 fprintf (lra_dump_file
,
1999 " %d Scratch win: reject+=2\n",
2006 this_alternative_match_win
= true;
2009 int const_to_mem
= 0;
2012 /* If this alternative asks for a specific reg class, see if there
2013 is at least one allocatable register in that class. */
2015 = (this_alternative
== NO_REGS
2016 || (hard_reg_set_subset_p
2017 (reg_class_contents
[this_alternative
],
2018 lra_no_alloc_regs
)));
2020 /* For asms, verify that the class for this alternative is possible
2021 for the mode that is specified. */
2022 if (!no_regs_p
&& INSN_CODE (curr_insn
) < 0)
2025 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2026 if (HARD_REGNO_MODE_OK (i
, mode
)
2027 && in_hard_reg_set_p (reg_class_contents
[this_alternative
], mode
, i
))
2029 if (i
== FIRST_PSEUDO_REGISTER
)
2033 /* If this operand accepts a register, and if the
2034 register class has at least one allocatable register,
2035 then this operand can be reloaded. */
2036 if (winreg
&& !no_regs_p
)
2042 this_alternative_offmemok
= offmemok
;
2043 if (this_costly_alternative
!= NO_REGS
)
2045 if (lra_dump_file
!= NULL
)
2046 fprintf (lra_dump_file
,
2047 " %d Costly loser: reject++\n", nop
);
2050 /* If the operand is dying, has a matching constraint,
2051 and satisfies constraints of the matched operand
2052 which failed to satisfy the own constraints, we do
2053 not need to generate a reload insn for this
2055 if (!(this_alternative_matches
>= 0
2056 && !curr_alt_win
[this_alternative_matches
]
2058 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
2059 && (hard_regno
[nop
] >= 0
2060 ? in_hard_reg_set_p (this_alternative_set
,
2061 mode
, hard_regno
[nop
])
2062 : in_class_p (op
, this_alternative
, NULL
))))
2064 /* Strict_low_part requires to reload the register
2065 not the sub-register. In this case we should
2066 check that a final reload hard reg can hold the
2068 if (curr_static_id
->operand
[nop
].strict_low
2070 && hard_regno
[nop
] < 0
2071 && GET_CODE (*curr_id
->operand_loc
[nop
]) == SUBREG
2072 && ira_class_hard_regs_num
[this_alternative
] > 0
2073 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs
2074 [this_alternative
][0],
2076 (*curr_id
->operand_loc
[nop
])))
2080 if (operand_reg
[nop
] != NULL_RTX
2081 /* Output operands and matched input operands are
2082 not inherited. The following conditions do not
2083 exactly describe the previous statement but they
2084 are pretty close. */
2085 && curr_static_id
->operand
[nop
].type
!= OP_OUT
2086 && (this_alternative_matches
< 0
2087 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
2089 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
2093 if (last_reload
> bb_reload_num
)
2094 reload_sum
+= last_reload
- bb_reload_num
;
2096 /* If this is a constant that is reloaded into the
2097 desired class by copying it to memory first, count
2098 that as another reload. This is consistent with
2099 other code and is required to avoid choosing another
2100 alternative when the constant is moved into memory.
2101 Note that the test here is precisely the same as in
2102 the code below that calls force_const_mem. */
2103 if (CONST_POOL_OK_P (mode
, op
)
2104 && ((targetm
.preferred_reload_class
2105 (op
, this_alternative
) == NO_REGS
)
2106 || no_input_reloads_p
))
2113 /* Alternative loses if it requires a type of reload not
2114 permitted for this insn. We can always reload
2115 objects with a REG_UNUSED note. */
2116 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
2117 && no_output_reloads_p
2118 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
2119 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
2120 && no_input_reloads_p
&& ! const_to_mem
))
2123 /* Check strong discouragement of reload of non-constant
2124 into class THIS_ALTERNATIVE. */
2125 if (! CONSTANT_P (op
) && ! no_regs_p
2126 && (targetm
.preferred_reload_class
2127 (op
, this_alternative
) == NO_REGS
2128 || (curr_static_id
->operand
[nop
].type
== OP_OUT
2129 && (targetm
.preferred_output_reload_class
2130 (op
, this_alternative
) == NO_REGS
))))
2132 if (lra_dump_file
!= NULL
)
2133 fprintf (lra_dump_file
,
2134 " %d Non-prefered reload: reject+=%d\n",
2135 nop
, LRA_MAX_REJECT
);
2136 reject
+= LRA_MAX_REJECT
;
2139 if (! (MEM_P (op
) && offmemok
)
2140 && ! (const_to_mem
&& constmemok
))
2142 /* We prefer to reload pseudos over reloading other
2143 things, since such reloads may be able to be
2144 eliminated later. So bump REJECT in other cases.
2145 Don't do this in the case where we are forcing a
2146 constant into memory and it will then win since
2147 we don't want to have a different alternative
2149 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
2151 if (lra_dump_file
!= NULL
)
2154 " %d Non-pseudo reload: reject+=2\n",
2161 += ira_reg_class_max_nregs
[this_alternative
][mode
];
2163 if (SMALL_REGISTER_CLASS_P (this_alternative
))
2165 if (lra_dump_file
!= NULL
)
2168 " %d Small class reload: reject+=%d\n",
2169 nop
, LRA_LOSER_COST_FACTOR
/ 2);
2170 reject
+= LRA_LOSER_COST_FACTOR
/ 2;
2174 /* We are trying to spill pseudo into memory. It is
2175 usually more costly than moving to a hard register
2176 although it might takes the same number of
2178 if (no_regs_p
&& REG_P (op
) && hard_regno
[nop
] >= 0)
2180 if (lra_dump_file
!= NULL
)
2183 " %d Spill pseudo in memory: reject+=3\n",
2188 #ifdef SECONDARY_MEMORY_NEEDED
2189 /* If reload requires moving value through secondary
2190 memory, it will need one more insn at least. */
2191 if (this_alternative
!= NO_REGS
2192 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
2193 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
2194 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
2196 || (curr_static_id
->operand
[nop
].type
!= OP_IN
2197 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
2201 /* Input reloads can be inherited more often than output
2202 reloads can be removed, so penalize output
2204 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
2206 if (lra_dump_file
!= NULL
)
2209 " %d Non input pseudo reload: reject++\n",
2215 if (early_clobber_p
&& ! scratch_p
)
2217 if (lra_dump_file
!= NULL
)
2218 fprintf (lra_dump_file
,
2219 " %d Early clobber: reject++\n", nop
);
2222 /* ??? We check early clobbers after processing all operands
2223 (see loop below) and there we update the costs more.
2224 Should we update the cost (may be approximately) here
2225 because of early clobber register reloads or it is a rare
2226 or non-important thing to be worth to do it. */
2227 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
2228 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
2230 if (lra_dump_file
!= NULL
)
2231 fprintf (lra_dump_file
,
2232 " alt=%d,overall=%d,losers=%d -- refuse\n",
2233 nalt
, overall
, losers
);
2237 curr_alt
[nop
] = this_alternative
;
2238 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
2239 curr_alt_win
[nop
] = this_alternative_win
;
2240 curr_alt_match_win
[nop
] = this_alternative_match_win
;
2241 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
2242 curr_alt_matches
[nop
] = this_alternative_matches
;
2244 if (this_alternative_matches
>= 0
2245 && !did_match
&& !this_alternative_win
)
2246 curr_alt_win
[this_alternative_matches
] = false;
2248 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
2249 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2251 if (curr_insn_set
!= NULL_RTX
&& n_operands
== 2
2252 /* Prevent processing non-move insns. */
2253 && (GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
2254 || SET_SRC (curr_insn_set
) == no_subreg_reg_operand
[1])
2255 && ((! curr_alt_win
[0] && ! curr_alt_win
[1]
2256 && REG_P (no_subreg_reg_operand
[0])
2257 && REG_P (no_subreg_reg_operand
[1])
2258 && (reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2259 || reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0])))
2260 || (! curr_alt_win
[0] && curr_alt_win
[1]
2261 && REG_P (no_subreg_reg_operand
[1])
2262 && reg_in_class_p (no_subreg_reg_operand
[1], curr_alt
[0]))
2263 || (curr_alt_win
[0] && ! curr_alt_win
[1]
2264 && REG_P (no_subreg_reg_operand
[0])
2265 && reg_in_class_p (no_subreg_reg_operand
[0], curr_alt
[1])
2266 && (! CONST_POOL_OK_P (curr_operand_mode
[1],
2267 no_subreg_reg_operand
[1])
2268 || (targetm
.preferred_reload_class
2269 (no_subreg_reg_operand
[1],
2270 (enum reg_class
) curr_alt
[1]) != NO_REGS
))
2271 /* If it is a result of recent elimination in move
2272 insn we can transform it into an add still by
2273 using this alternative. */
2274 && GET_CODE (no_subreg_reg_operand
[1]) != PLUS
)))
2276 /* We have a move insn and a new reload insn will be similar
2277 to the current insn. We should avoid such situation as it
2278 results in LRA cycling. */
2279 overall
+= LRA_MAX_REJECT
;
2282 curr_alt_dont_inherit_ops_num
= 0;
2283 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2285 int i
, j
, clobbered_hard_regno
, first_conflict_j
, last_conflict_j
;
2286 HARD_REG_SET temp_set
;
2288 i
= early_clobbered_nops
[nop
];
2289 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2290 || hard_regno
[i
] < 0)
2292 lra_assert (operand_reg
[i
] != NULL_RTX
);
2293 clobbered_hard_regno
= hard_regno
[i
];
2294 CLEAR_HARD_REG_SET (temp_set
);
2295 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2296 first_conflict_j
= last_conflict_j
= -1;
2297 for (j
= 0; j
< n_operands
; j
++)
2299 /* We don't want process insides of match_operator and
2300 match_parallel because otherwise we would process
2301 their operands once again generating a wrong
2303 || curr_static_id
->operand
[j
].is_operator
)
2305 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2306 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2308 /* If we don't reload j-th operand, check conflicts. */
2309 else if ((curr_alt_win
[j
] || curr_alt_match_win
[j
])
2310 && uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2312 if (first_conflict_j
< 0)
2313 first_conflict_j
= j
;
2314 last_conflict_j
= j
;
2316 if (last_conflict_j
< 0)
2318 /* If earlyclobber operand conflicts with another
2319 non-matching operand which is actually the same register
2320 as the earlyclobber operand, it is better to reload the
2321 another operand as an operand matching the earlyclobber
2322 operand can be also the same. */
2323 if (first_conflict_j
== last_conflict_j
2324 && operand_reg
[last_conflict_j
]
2325 != NULL_RTX
&& ! curr_alt_match_win
[last_conflict_j
]
2326 && REGNO (operand_reg
[i
]) == REGNO (operand_reg
[last_conflict_j
]))
2328 curr_alt_win
[last_conflict_j
] = false;
2329 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++]
2332 /* Early clobber was already reflected in REJECT. */
2333 lra_assert (reject
> 0);
2334 if (lra_dump_file
!= NULL
)
2337 " %d Conflict early clobber reload: reject--\n",
2340 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2344 /* We need to reload early clobbered register and the
2345 matched registers. */
2346 for (j
= 0; j
< n_operands
; j
++)
2347 if (curr_alt_matches
[j
] == i
)
2349 curr_alt_match_win
[j
] = false;
2351 overall
+= LRA_LOSER_COST_FACTOR
;
2353 if (! curr_alt_match_win
[i
])
2354 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2357 /* Remember pseudos used for match reloads are never
2359 lra_assert (curr_alt_matches
[i
] >= 0);
2360 curr_alt_win
[curr_alt_matches
[i
]] = false;
2362 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2364 /* Early clobber was already reflected in REJECT. */
2365 lra_assert (reject
> 0);
2366 if (lra_dump_file
!= NULL
)
2369 " %d Matched conflict early clobber reloads:"
2373 overall
+= LRA_LOSER_COST_FACTOR
- 1;
2376 if (lra_dump_file
!= NULL
)
2377 fprintf (lra_dump_file
, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n",
2378 nalt
, overall
, losers
, reload_nregs
);
2380 /* If this alternative can be made to work by reloading, and it
2381 needs less reloading than the others checked so far, record
2382 it as the chosen goal for reloading. */
2383 if ((best_losers
!= 0 && losers
== 0)
2384 || (((best_losers
== 0 && losers
== 0)
2385 || (best_losers
!= 0 && losers
!= 0))
2386 && (best_overall
> overall
2387 || (best_overall
== overall
2388 /* If the cost of the reloads is the same,
2389 prefer alternative which requires minimal
2390 number of reload regs. */
2391 && (reload_nregs
< best_reload_nregs
2392 || (reload_nregs
== best_reload_nregs
2393 && (best_reload_sum
< reload_sum
2394 || (best_reload_sum
== reload_sum
2395 && nalt
< goal_alt_number
))))))))
2397 for (nop
= 0; nop
< n_operands
; nop
++)
2399 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2400 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2401 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2402 goal_alt
[nop
] = curr_alt
[nop
];
2403 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2405 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2406 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2407 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2408 goal_alt_swapped
= curr_swapped
;
2409 best_overall
= overall
;
2410 best_losers
= losers
;
2411 best_reload_nregs
= reload_nregs
;
2412 best_reload_sum
= reload_sum
;
2413 goal_alt_number
= nalt
;
2416 /* Everything is satisfied. Do not process alternatives
2425 /* Return 1 if ADDR is a valid memory address for mode MODE in address
2426 space AS, and check that each pseudo has the proper kind of hard
2429 valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2430 rtx addr
, addr_space_t as
)
2432 #ifdef GO_IF_LEGITIMATE_ADDRESS
2433 lra_assert (ADDR_SPACE_GENERIC_P (as
));
2434 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
2440 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
2444 /* Return whether address AD is valid. */
2447 valid_address_p (struct address_info
*ad
)
2449 /* Some ports do not check displacements for eliminable registers,
2450 so we replace them temporarily with the elimination target. */
2451 rtx saved_base_reg
= NULL_RTX
;
2452 rtx saved_index_reg
= NULL_RTX
;
2453 rtx
*base_term
= strip_subreg (ad
->base_term
);
2454 rtx
*index_term
= strip_subreg (ad
->index_term
);
2455 if (base_term
!= NULL
)
2457 saved_base_reg
= *base_term
;
2458 lra_eliminate_reg_if_possible (base_term
);
2459 if (ad
->base_term2
!= NULL
)
2460 *ad
->base_term2
= *ad
->base_term
;
2462 if (index_term
!= NULL
)
2464 saved_index_reg
= *index_term
;
2465 lra_eliminate_reg_if_possible (index_term
);
2467 bool ok_p
= valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
2468 if (saved_base_reg
!= NULL_RTX
)
2470 *base_term
= saved_base_reg
;
2471 if (ad
->base_term2
!= NULL
)
2472 *ad
->base_term2
= *ad
->base_term
;
2474 if (saved_index_reg
!= NULL_RTX
)
2475 *index_term
= saved_index_reg
;
2479 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2481 base_plus_disp_to_reg (struct address_info
*ad
)
2486 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2487 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2488 get_index_code (ad
));
2489 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2491 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2495 /* Return true if we can add a displacement to address AD, even if that
2496 makes the address invalid. The fix-up code requires any new address
2497 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2499 can_add_disp_p (struct address_info
*ad
)
2501 return (!ad
->autoinc_p
2502 && ad
->segment
== NULL
2503 && ad
->base
== ad
->base_term
2504 && ad
->disp
== ad
->disp_term
);
2507 /* Make equiv substitution in address AD. Return true if a substitution
2510 equiv_address_substitution (struct address_info
*ad
)
2512 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2513 HOST_WIDE_INT disp
, scale
;
2516 base_term
= strip_subreg (ad
->base_term
);
2517 if (base_term
== NULL
)
2518 base_reg
= new_base_reg
= NULL_RTX
;
2521 base_reg
= *base_term
;
2522 new_base_reg
= get_equiv_substitution (base_reg
);
2524 index_term
= strip_subreg (ad
->index_term
);
2525 if (index_term
== NULL
)
2526 index_reg
= new_index_reg
= NULL_RTX
;
2529 index_reg
= *index_term
;
2530 new_index_reg
= get_equiv_substitution (index_reg
);
2532 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2536 if (lra_dump_file
!= NULL
)
2538 fprintf (lra_dump_file
, "Changing address in insn %d ",
2539 INSN_UID (curr_insn
));
2540 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2542 if (base_reg
!= new_base_reg
)
2544 if (REG_P (new_base_reg
))
2546 *base_term
= new_base_reg
;
2549 else if (GET_CODE (new_base_reg
) == PLUS
2550 && REG_P (XEXP (new_base_reg
, 0))
2551 && CONST_INT_P (XEXP (new_base_reg
, 1))
2552 && can_add_disp_p (ad
))
2554 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2555 *base_term
= XEXP (new_base_reg
, 0);
2558 if (ad
->base_term2
!= NULL
)
2559 *ad
->base_term2
= *ad
->base_term
;
2561 if (index_reg
!= new_index_reg
)
2563 if (REG_P (new_index_reg
))
2565 *index_term
= new_index_reg
;
2568 else if (GET_CODE (new_index_reg
) == PLUS
2569 && REG_P (XEXP (new_index_reg
, 0))
2570 && CONST_INT_P (XEXP (new_index_reg
, 1))
2571 && can_add_disp_p (ad
)
2572 && (scale
= get_index_scale (ad
)))
2574 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2575 *index_term
= XEXP (new_index_reg
, 0);
2581 if (ad
->disp
!= NULL
)
2582 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2585 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2586 update_address (ad
);
2590 if (lra_dump_file
!= NULL
)
2593 fprintf (lra_dump_file
, " -- no change\n");
2596 fprintf (lra_dump_file
, " on equiv ");
2597 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2598 fprintf (lra_dump_file
, "\n");
2604 /* Major function to make reloads for an address in operand NOP.
2605 The supported cases are:
2607 1) an address that existed before LRA started, at which point it
2608 must have been valid. These addresses are subject to elimination
2609 and may have become invalid due to the elimination offset being out
2612 2) an address created by forcing a constant to memory
2613 (force_const_to_mem). The initial form of these addresses might
2614 not be valid, and it is this function's job to make them valid.
2616 3) a frame address formed from a register and a (possibly zero)
2617 constant offset. As above, these addresses might not be valid and
2618 this function must make them so.
2620 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2621 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2622 address. Return true for any RTL change. */
2624 process_address (int nop
, rtx
*before
, rtx
*after
)
2626 struct address_info ad
;
2628 rtx op
= *curr_id
->operand_loc
[nop
];
2629 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2632 if (constraint
[0] == 'p'
2633 || EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
))
2634 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2635 else if (MEM_P (op
))
2636 decompose_mem_address (&ad
, op
);
2637 else if (GET_CODE (op
) == SUBREG
2638 && MEM_P (SUBREG_REG (op
)))
2639 decompose_mem_address (&ad
, SUBREG_REG (op
));
2642 change_p
= equiv_address_substitution (&ad
);
2643 if (ad
.base_term
!= NULL
2644 && (process_addr_reg
2645 (ad
.base_term
, before
,
2647 && !(REG_P (*ad
.base_term
)
2648 && find_regno_note (curr_insn
, REG_DEAD
,
2649 REGNO (*ad
.base_term
)) != NULL_RTX
)
2651 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2652 get_index_code (&ad
)))))
2655 if (ad
.base_term2
!= NULL
)
2656 *ad
.base_term2
= *ad
.base_term
;
2658 if (ad
.index_term
!= NULL
2659 && process_addr_reg (ad
.index_term
, before
, NULL
, INDEX_REG_CLASS
))
2662 #ifdef EXTRA_CONSTRAINT_STR
2663 /* Target hooks sometimes reject extra constraint addresses -- use
2664 EXTRA_CONSTRAINT_STR for the validation. */
2665 if (constraint
[0] != 'p'
2666 && EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
)
2667 && EXTRA_CONSTRAINT_STR (op
, constraint
[0], constraint
))
2671 /* There are three cases where the shape of *AD.INNER may now be invalid:
2673 1) the original address was valid, but either elimination or
2674 equiv_address_substitution was applied and that made
2675 the address invalid.
2677 2) the address is an invalid symbolic address created by
2680 3) the address is a frame address with an invalid offset.
2682 All these cases involve a non-autoinc address, so there is no
2683 point revalidating other types. */
2684 if (ad
.autoinc_p
|| valid_address_p (&ad
))
2687 /* Any index existed before LRA started, so we can assume that the
2688 presence and shape of the index is valid. */
2689 push_to_sequence (*before
);
2690 lra_assert (ad
.disp
== ad
.disp_term
);
2691 if (ad
.base
== NULL
)
2693 if (ad
.index
== NULL
)
2696 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2698 rtx addr
= *ad
.inner
;
2700 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "addr");
2704 rtx last
= get_last_insn ();
2706 /* addr => lo_sum (new_base, addr), case (2) above. */
2707 insn
= emit_insn (gen_rtx_SET
2709 gen_rtx_HIGH (Pmode
, copy_rtx (addr
))));
2710 code
= recog_memoized (insn
);
2713 *ad
.inner
= gen_rtx_LO_SUM (Pmode
, new_reg
, addr
);
2714 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2716 /* Try to put lo_sum into register. */
2717 insn
= emit_insn (gen_rtx_SET
2719 gen_rtx_LO_SUM (Pmode
, new_reg
, addr
)));
2720 code
= recog_memoized (insn
);
2723 *ad
.inner
= new_reg
;
2724 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2734 delete_insns_since (last
);
2739 /* addr => new_base, case (2) above. */
2740 lra_emit_move (new_reg
, addr
);
2741 *ad
.inner
= new_reg
;
2746 /* index * scale + disp => new base + index * scale,
2748 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2749 GET_CODE (*ad
.index
));
2751 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2752 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2753 lra_emit_move (new_reg
, *ad
.disp
);
2754 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2755 new_reg
, *ad
.index
);
2758 else if (ad
.index
== NULL
)
2762 rtx set
, insns
, last_insn
;
2763 /* base + disp => new base, cases (1) and (3) above. */
2764 /* Another option would be to reload the displacement into an
2765 index register. However, postreload has code to optimize
2766 address reloads that have the same base and different
2767 displacements, so reloading into an index register would
2768 not necessarily be a win. */
2770 new_reg
= base_plus_disp_to_reg (&ad
);
2771 insns
= get_insns ();
2772 last_insn
= get_last_insn ();
2773 /* If we generated at least two insns, try last insn source as
2774 an address. If we succeed, we generate one less insn. */
2775 if (last_insn
!= insns
&& (set
= single_set (last_insn
)) != NULL_RTX
2776 && GET_CODE (SET_SRC (set
)) == PLUS
2777 && REG_P (XEXP (SET_SRC (set
), 0))
2778 && CONSTANT_P (XEXP (SET_SRC (set
), 1)))
2780 *ad
.inner
= SET_SRC (set
);
2781 if (valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2783 *ad
.base_term
= XEXP (SET_SRC (set
), 0);
2784 *ad
.disp_term
= XEXP (SET_SRC (set
), 1);
2785 cl
= base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2786 get_index_code (&ad
));
2787 regno
= REGNO (*ad
.base_term
);
2788 if (regno
>= FIRST_PSEUDO_REGISTER
2789 && cl
!= lra_get_allocno_class (regno
))
2790 change_class (regno
, cl
, " Change", true);
2791 new_reg
= SET_SRC (set
);
2792 delete_insns_since (PREV_INSN (last_insn
));
2797 *ad
.inner
= new_reg
;
2801 /* base + scale * index + disp => new base + scale * index,
2803 new_reg
= base_plus_disp_to_reg (&ad
);
2804 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2805 new_reg
, *ad
.index
);
2807 *before
= get_insns ();
2812 /* Emit insns to reload VALUE into a new register. VALUE is an
2813 auto-increment or auto-decrement RTX whose operand is a register or
2814 memory location; so reloading involves incrementing that location.
2815 IN is either identical to VALUE, or some cheaper place to reload
2816 value being incremented/decremented from.
2818 INC_AMOUNT is the number to increment or decrement by (always
2819 positive and ignored for POST_MODIFY/PRE_MODIFY).
2821 Return pseudo containing the result. */
2823 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
2825 /* REG or MEM to be copied and incremented. */
2826 rtx incloc
= XEXP (value
, 0);
2827 /* Nonzero if increment after copying. */
2828 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
2829 || GET_CODE (value
) == POST_MODIFY
);
2834 rtx real_in
= in
== value
? incloc
: in
;
2838 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
2840 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
2841 || GET_CODE (XEXP (value
, 1)) == MINUS
);
2842 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
2843 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
2844 inc
= XEXP (XEXP (value
, 1), 1);
2848 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
2849 inc_amount
= -inc_amount
;
2851 inc
= GEN_INT (inc_amount
);
2854 if (! post
&& REG_P (incloc
))
2857 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
2860 if (real_in
!= result
)
2862 /* First copy the location to the result register. */
2863 lra_assert (REG_P (result
));
2864 emit_insn (gen_move_insn (result
, real_in
));
2867 /* We suppose that there are insns to add/sub with the constant
2868 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
2869 old reload worked with this assumption. If the assumption
2870 becomes wrong, we should use approach in function
2871 base_plus_disp_to_reg. */
2874 /* See if we can directly increment INCLOC. */
2875 last
= get_last_insn ();
2876 add_insn
= emit_insn (plus_p
2877 ? gen_add2_insn (incloc
, inc
)
2878 : gen_sub2_insn (incloc
, inc
));
2880 code
= recog_memoized (add_insn
);
2883 if (! post
&& result
!= incloc
)
2884 emit_insn (gen_move_insn (result
, incloc
));
2887 delete_insns_since (last
);
2890 /* If couldn't do the increment directly, must increment in RESULT.
2891 The way we do this depends on whether this is pre- or
2892 post-increment. For pre-increment, copy INCLOC to the reload
2893 register, increment it there, then save back. */
2896 if (real_in
!= result
)
2897 emit_insn (gen_move_insn (result
, real_in
));
2899 emit_insn (gen_add2_insn (result
, inc
));
2901 emit_insn (gen_sub2_insn (result
, inc
));
2902 if (result
!= incloc
)
2903 emit_insn (gen_move_insn (incloc
, result
));
2909 Because this might be a jump insn or a compare, and because
2910 RESULT may not be available after the insn in an input
2911 reload, we must do the incrementing before the insn being
2914 We have already copied IN to RESULT. Increment the copy in
2915 RESULT, save that back, then decrement RESULT so it has
2916 the original value. */
2918 emit_insn (gen_add2_insn (result
, inc
));
2920 emit_insn (gen_sub2_insn (result
, inc
));
2921 emit_insn (gen_move_insn (incloc
, result
));
2922 /* Restore non-modified value for the result. We prefer this
2923 way because it does not require an additional hard
2927 if (CONST_INT_P (inc
))
2928 emit_insn (gen_add2_insn (result
,
2929 gen_int_mode (-INTVAL (inc
),
2930 GET_MODE (result
))));
2932 emit_insn (gen_sub2_insn (result
, inc
));
2935 emit_insn (gen_add2_insn (result
, inc
));
2940 /* Return true if the current move insn does not need processing as we
2941 already know that it satisfies its constraints. */
2943 simple_move_p (void)
2946 enum reg_class dclass
, sclass
;
2948 lra_assert (curr_insn_set
!= NULL_RTX
);
2949 dest
= SET_DEST (curr_insn_set
);
2950 src
= SET_SRC (curr_insn_set
);
2951 return ((dclass
= get_op_class (dest
)) != NO_REGS
2952 && (sclass
= get_op_class (src
)) != NO_REGS
2953 /* The backend guarantees that register moves of cost 2
2954 never need reloads. */
2955 && targetm
.register_move_cost (GET_MODE (src
), dclass
, sclass
) == 2);
2958 /* Swap operands NOP and NOP + 1. */
2960 swap_operands (int nop
)
2962 enum machine_mode mode
= curr_operand_mode
[nop
];
2963 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
2964 curr_operand_mode
[nop
+ 1] = mode
;
2965 rtx x
= *curr_id
->operand_loc
[nop
];
2966 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
2967 *curr_id
->operand_loc
[nop
+ 1] = x
;
2968 /* Swap the duplicates too. */
2969 lra_update_dup (curr_id
, nop
);
2970 lra_update_dup (curr_id
, nop
+ 1);
2973 /* Main entry point of the constraint code: search the body of the
2974 current insn to choose the best alternative. It is mimicking insn
2975 alternative cost calculation model of former reload pass. That is
2976 because machine descriptions were written to use this model. This
2977 model can be changed in future. Make commutative operand exchange
2980 Return true if some RTL changes happened during function call. */
2982 curr_insn_transform (void)
2988 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
2989 signed char match_inputs
[MAX_RECOG_OPERANDS
+ 1];
2992 /* Flag that the insn has been changed through a transformation. */
2995 #ifdef SECONDARY_MEMORY_NEEDED
2998 int max_regno_before
;
2999 int reused_alternative_num
;
3001 curr_insn_set
= single_set (curr_insn
);
3002 if (curr_insn_set
!= NULL_RTX
&& simple_move_p ())
3005 no_input_reloads_p
= no_output_reloads_p
= false;
3006 goal_alt_number
= -1;
3007 change_p
= sec_mem_p
= false;
3008 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
3009 reloads; neither are insns that SET cc0. Insns that use CC0 are
3010 not allowed to have any input reloads. */
3011 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
3012 no_output_reloads_p
= true;
3015 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
3016 no_input_reloads_p
= true;
3017 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
3018 no_output_reloads_p
= true;
3021 n_operands
= curr_static_id
->n_operands
;
3022 n_alternatives
= curr_static_id
->n_alternatives
;
3024 /* Just return "no reloads" if insn has no operands with
3026 if (n_operands
== 0 || n_alternatives
== 0)
3029 max_regno_before
= max_reg_num ();
3031 for (i
= 0; i
< n_operands
; i
++)
3033 goal_alt_matched
[i
][0] = -1;
3034 goal_alt_matches
[i
] = -1;
3037 commutative
= curr_static_id
->commutative
;
3039 /* Now see what we need for pseudos that didn't get hard regs or got
3040 the wrong kind of hard reg. For this, we must consider all the
3041 operands together against the register constraints. */
3043 best_losers
= best_overall
= INT_MAX
;
3044 best_reload_sum
= 0;
3046 curr_swapped
= false;
3047 goal_alt_swapped
= false;
3049 /* Make equivalence substitution and memory subreg elimination
3050 before address processing because an address legitimacy can
3051 depend on memory mode. */
3052 for (i
= 0; i
< n_operands
; i
++)
3054 rtx op
= *curr_id
->operand_loc
[i
];
3055 rtx subst
, old
= op
;
3056 bool op_change_p
= false;
3058 if (GET_CODE (old
) == SUBREG
)
3059 old
= SUBREG_REG (old
);
3060 subst
= get_equiv_substitution (old
);
3063 subst
= copy_rtx (subst
);
3064 lra_assert (REG_P (old
));
3065 if (GET_CODE (op
) == SUBREG
)
3066 SUBREG_REG (op
) = subst
;
3068 *curr_id
->operand_loc
[i
] = subst
;
3069 if (lra_dump_file
!= NULL
)
3071 fprintf (lra_dump_file
,
3072 "Changing pseudo %d in operand %i of insn %u on equiv ",
3073 REGNO (old
), i
, INSN_UID (curr_insn
));
3074 dump_value_slim (lra_dump_file
, subst
, 1);
3075 fprintf (lra_dump_file
, "\n");
3077 op_change_p
= change_p
= true;
3079 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
3082 lra_update_dup (curr_id
, i
);
3086 /* Reload address registers and displacements. We do it before
3087 finding an alternative because of memory constraints. */
3088 before
= after
= NULL_RTX
;
3089 for (i
= 0; i
< n_operands
; i
++)
3090 if (! curr_static_id
->operand
[i
].is_operator
3091 && process_address (i
, &before
, &after
))
3094 lra_update_dup (curr_id
, i
);
3098 /* If we've changed the instruction then any alternative that
3099 we chose previously may no longer be valid. */
3100 lra_set_used_insn_alternative (curr_insn
, -1);
3102 if (curr_insn_set
!= NULL_RTX
3103 && check_and_process_move (&change_p
, &sec_mem_p
))
3108 reused_alternative_num
= curr_id
->used_insn_alternative
;
3109 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
3110 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
3111 reused_alternative_num
, INSN_UID (curr_insn
));
3113 if (process_alt_operands (reused_alternative_num
))
3116 /* If insn is commutative (it's safe to exchange a certain pair of
3117 operands) then we need to try each alternative twice, the second
3118 time matching those two operands as if we had exchanged them. To
3119 do this, really exchange them in operands.
3121 If we have just tried the alternatives the second time, return
3122 operands to normal and drop through. */
3124 if (reused_alternative_num
< 0 && commutative
>= 0)
3126 curr_swapped
= !curr_swapped
;
3129 swap_operands (commutative
);
3133 swap_operands (commutative
);
3136 if (! alt_p
&& ! sec_mem_p
)
3138 /* No alternative works with reloads?? */
3139 if (INSN_CODE (curr_insn
) >= 0)
3140 fatal_insn ("unable to generate reloads for:", curr_insn
);
3141 error_for_asm (curr_insn
,
3142 "inconsistent operand constraints in an %<asm%>");
3143 /* Avoid further trouble with this insn. */
3144 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
3145 lra_invalidate_insn_data (curr_insn
);
3149 /* If the best alternative is with operands 1 and 2 swapped, swap
3150 them. Update the operand numbers of any reloads already
3153 if (goal_alt_swapped
)
3155 if (lra_dump_file
!= NULL
)
3156 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
3157 INSN_UID (curr_insn
));
3159 /* Swap the duplicates too. */
3160 swap_operands (commutative
);
3164 #ifdef SECONDARY_MEMORY_NEEDED
3165 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
3166 too conservatively. So we use the secondary memory only if there
3167 is no any alternative without reloads. */
3168 use_sec_mem_p
= false;
3170 use_sec_mem_p
= true;
3173 for (i
= 0; i
< n_operands
; i
++)
3174 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
3176 use_sec_mem_p
= i
< n_operands
;
3181 rtx new_reg
, src
, dest
, rld
;
3182 enum machine_mode sec_mode
, rld_mode
;
3184 lra_assert (sec_mem_p
);
3185 lra_assert (curr_static_id
->operand
[0].type
== OP_OUT
3186 && curr_static_id
->operand
[1].type
== OP_IN
);
3187 dest
= *curr_id
->operand_loc
[0];
3188 src
= *curr_id
->operand_loc
[1];
3189 rld
= (GET_MODE_SIZE (GET_MODE (dest
)) <= GET_MODE_SIZE (GET_MODE (src
))
3191 rld_mode
= GET_MODE (rld
);
3192 #ifdef SECONDARY_MEMORY_NEEDED_MODE
3193 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (rld_mode
);
3195 sec_mode
= rld_mode
;
3197 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
3198 NO_REGS
, "secondary");
3199 /* If the mode is changed, it should be wider. */
3200 lra_assert (GET_MODE_SIZE (sec_mode
) >= GET_MODE_SIZE (rld_mode
));
3201 if (sec_mode
!= rld_mode
)
3203 /* If the target says specifically to use another mode for
3204 secondary memory moves we can not reuse the original
3206 after
= emit_spill_move (false, new_reg
, dest
);
3207 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3208 "Inserting the sec. move");
3209 /* We may have non null BEFORE here (e.g. after address
3211 push_to_sequence (before
);
3212 before
= emit_spill_move (true, new_reg
, src
);
3214 before
= get_insns ();
3216 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Changing on");
3217 lra_set_insn_deleted (curr_insn
);
3219 else if (dest
== rld
)
3221 *curr_id
->operand_loc
[0] = new_reg
;
3222 after
= emit_spill_move (false, new_reg
, dest
);
3223 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
3224 "Inserting the sec. move");
3228 *curr_id
->operand_loc
[1] = new_reg
;
3229 /* See comments above. */
3230 push_to_sequence (before
);
3231 before
= emit_spill_move (true, new_reg
, src
);
3233 before
= get_insns ();
3235 lra_process_new_insns (curr_insn
, before
, NULL_RTX
,
3236 "Inserting the sec. move");
3238 lra_update_insn_regno_info (curr_insn
);
3243 lra_assert (goal_alt_number
>= 0);
3244 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
3246 if (lra_dump_file
!= NULL
)
3250 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
3251 goal_alt_number
, INSN_UID (curr_insn
));
3252 for (i
= 0; i
< n_operands
; i
++)
3254 p
= (curr_static_id
->operand_alternative
3255 [goal_alt_number
* n_operands
+ i
].constraint
);
3258 fprintf (lra_dump_file
, " (%d) ", i
);
3259 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
3260 fputc (*p
, lra_dump_file
);
3262 if (INSN_CODE (curr_insn
) >= 0
3263 && (p
= get_insn_name (INSN_CODE (curr_insn
))) != NULL
)
3264 fprintf (lra_dump_file
, " {%s}", p
);
3265 fprintf (lra_dump_file
, "\n");
3268 /* Right now, for any pair of operands I and J that are required to
3269 match, with J < I, goal_alt_matches[I] is J. Add I to
3270 goal_alt_matched[J]. */
3272 for (i
= 0; i
< n_operands
; i
++)
3273 if ((j
= goal_alt_matches
[i
]) >= 0)
3275 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
3277 /* We allow matching one output operand and several input
3280 || (curr_static_id
->operand
[j
].type
== OP_OUT
3281 && curr_static_id
->operand
[i
].type
== OP_IN
3282 && (curr_static_id
->operand
3283 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
3284 goal_alt_matched
[j
][k
] = i
;
3285 goal_alt_matched
[j
][k
+ 1] = -1;
3288 for (i
= 0; i
< n_operands
; i
++)
3289 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
3291 /* Any constants that aren't allowed and can't be reloaded into
3292 registers are here changed into memory references. */
3293 for (i
= 0; i
< n_operands
; i
++)
3294 if (goal_alt_win
[i
])
3297 enum reg_class new_class
;
3298 rtx reg
= *curr_id
->operand_loc
[i
];
3300 if (GET_CODE (reg
) == SUBREG
)
3301 reg
= SUBREG_REG (reg
);
3303 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
3305 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
3307 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
3310 change_class (regno
, new_class
, " Change", true);
3316 const char *constraint
;
3318 rtx op
= *curr_id
->operand_loc
[i
];
3319 rtx subreg
= NULL_RTX
;
3320 enum machine_mode mode
= curr_operand_mode
[i
];
3322 if (GET_CODE (op
) == SUBREG
)
3325 op
= SUBREG_REG (op
);
3326 mode
= GET_MODE (op
);
3329 if (CONST_POOL_OK_P (mode
, op
)
3330 && ((targetm
.preferred_reload_class
3331 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
3332 || no_input_reloads_p
))
3334 rtx tem
= force_const_mem (mode
, op
);
3337 if (subreg
!= NULL_RTX
)
3338 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
3340 *curr_id
->operand_loc
[i
] = tem
;
3341 lra_update_dup (curr_id
, i
);
3342 process_address (i
, &before
, &after
);
3344 /* If the alternative accepts constant pool refs directly
3345 there will be no reload needed at all. */
3346 if (subreg
!= NULL_RTX
)
3348 /* Skip alternatives before the one requested. */
3349 constraint
= (curr_static_id
->operand_alternative
3350 [goal_alt_number
* n_operands
+ i
].constraint
);
3352 (c
= *constraint
) && c
!= ',' && c
!= '#';
3353 constraint
+= CONSTRAINT_LEN (c
, constraint
))
3355 if (c
== TARGET_MEM_CONSTRAINT
|| c
== 'o')
3357 #ifdef EXTRA_CONSTRAINT_STR
3358 if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
)
3359 && EXTRA_CONSTRAINT_STR (tem
, c
, constraint
))
3363 if (c
== '\0' || c
== ',' || c
== '#')
3366 goal_alt_win
[i
] = true;
3370 for (i
= 0; i
< n_operands
; i
++)
3373 bool optional_p
= false;
3375 rtx op
= *curr_id
->operand_loc
[i
];
3377 if (goal_alt_win
[i
])
3379 if (goal_alt
[i
] == NO_REGS
3381 /* When we assign NO_REGS it means that we will not
3382 assign a hard register to the scratch pseudo by
3383 assigment pass and the scratch pseudo will be
3384 spilled. Spilled scratch pseudos are transformed
3385 back to scratches at the LRA end. */
3386 && lra_former_scratch_operand_p (curr_insn
, i
))
3388 int regno
= REGNO (op
);
3389 change_class (regno
, NO_REGS
, " Change", true);
3390 if (lra_get_regno_hard_regno (regno
) >= 0)
3391 /* We don't have to mark all insn affected by the
3392 spilled pseudo as there is only one such insn, the
3394 reg_renumber
[regno
] = -1;
3396 /* We can do an optional reload. If the pseudo got a hard
3397 reg, we might improve the code through inheritance. If
3398 it does not get a hard register we coalesce memory/memory
3399 moves later. Ignore move insns to avoid cycling. */
3401 && lra_undo_inheritance_iter
< LRA_MAX_INHERITANCE_PASSES
3402 && goal_alt
[i
] != NO_REGS
&& REG_P (op
)
3403 && (regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
3404 && ! lra_former_scratch_p (regno
)
3405 && reg_renumber
[regno
] < 0
3406 && (curr_insn_set
== NULL_RTX
3407 || !((REG_P (SET_SRC (curr_insn_set
))
3408 || MEM_P (SET_SRC (curr_insn_set
))
3409 || GET_CODE (SET_SRC (curr_insn_set
)) == SUBREG
)
3410 && (REG_P (SET_DEST (curr_insn_set
))
3411 || MEM_P (SET_DEST (curr_insn_set
))
3412 || GET_CODE (SET_DEST (curr_insn_set
)) == SUBREG
))))
3418 /* Operands that match previous ones have already been handled. */
3419 if (goal_alt_matches
[i
] >= 0)
3422 /* We should not have an operand with a non-offsettable address
3423 appearing where an offsettable address will do. It also may
3424 be a case when the address should be special in other words
3425 not a general one (e.g. it needs no index reg). */
3426 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
3428 enum reg_class rclass
;
3429 rtx
*loc
= &XEXP (op
, 0);
3430 enum rtx_code code
= GET_CODE (*loc
);
3432 push_to_sequence (before
);
3433 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
3435 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
3436 new_reg
= emit_inc (rclass
, *loc
, *loc
,
3437 /* This value does not matter for MODIFY. */
3438 GET_MODE_SIZE (GET_MODE (op
)));
3439 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
,
3440 "offsetable address", &new_reg
))
3441 lra_emit_move (new_reg
, *loc
);
3442 before
= get_insns ();
3445 lra_update_dup (curr_id
, i
);
3447 else if (goal_alt_matched
[i
][0] == -1)
3449 enum machine_mode mode
;
3451 int hard_regno
, byte
;
3452 enum op_type type
= curr_static_id
->operand
[i
].type
;
3454 loc
= curr_id
->operand_loc
[i
];
3455 mode
= curr_operand_mode
[i
];
3456 if (GET_CODE (*loc
) == SUBREG
)
3458 reg
= SUBREG_REG (*loc
);
3459 byte
= SUBREG_BYTE (*loc
);
3461 /* Strict_low_part requires reload the register not
3462 the sub-register. */
3463 && (curr_static_id
->operand
[i
].strict_low
3464 || (GET_MODE_SIZE (mode
)
3465 <= GET_MODE_SIZE (GET_MODE (reg
))
3467 = get_try_hard_regno (REGNO (reg
))) >= 0
3468 && (simplify_subreg_regno
3470 GET_MODE (reg
), byte
, mode
) < 0)
3471 && (goal_alt
[i
] == NO_REGS
3472 || (simplify_subreg_regno
3473 (ira_class_hard_regs
[goal_alt
[i
]][0],
3474 GET_MODE (reg
), byte
, mode
) >= 0)))))
3476 loc
= &SUBREG_REG (*loc
);
3477 mode
= GET_MODE (*loc
);
3481 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
], "", &new_reg
)
3484 push_to_sequence (before
);
3485 lra_emit_move (new_reg
, old
);
3486 before
= get_insns ();
3491 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3494 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3496 after
= get_insns ();
3500 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3501 if (goal_alt_dont_inherit_ops
[j
] == i
)
3503 lra_set_regno_unique_value (REGNO (new_reg
));
3506 lra_update_dup (curr_id
, i
);
3508 else if (curr_static_id
->operand
[i
].type
== OP_IN
3509 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3512 /* generate reloads for input and matched outputs. */
3513 match_inputs
[0] = i
;
3514 match_inputs
[1] = -1;
3515 match_reload (goal_alt_matched
[i
][0], match_inputs
,
3516 goal_alt
[i
], &before
, &after
);
3518 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3519 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3521 /* Generate reloads for output and matched inputs. */
3522 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3523 else if (curr_static_id
->operand
[i
].type
== OP_IN
3524 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3527 /* Generate reloads for matched inputs. */
3528 match_inputs
[0] = i
;
3529 for (j
= 0; (k
= goal_alt_matched
[i
][j
]) >= 0; j
++)
3530 match_inputs
[j
+ 1] = k
;
3531 match_inputs
[j
+ 1] = -1;
3532 match_reload (-1, match_inputs
, goal_alt
[i
], &before
, &after
);
3535 /* We must generate code in any case when function
3536 process_alt_operands decides that it is possible. */
3540 lra_assert (REG_P (op
));
3542 op
= *curr_id
->operand_loc
[i
]; /* Substitution. */
3543 if (GET_CODE (op
) == SUBREG
)
3544 op
= SUBREG_REG (op
);
3545 gcc_assert (REG_P (op
) && (int) REGNO (op
) >= new_regno_start
);
3546 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (op
));
3547 lra_reg_info
[REGNO (op
)].restore_regno
= regno
;
3548 if (lra_dump_file
!= NULL
)
3549 fprintf (lra_dump_file
,
3550 " Making reload reg %d for reg %d optional\n",
3554 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3555 || max_regno_before
!= max_reg_num ())
3559 lra_update_operator_dups (curr_id
);
3560 /* Something changes -- process the insn. */
3561 lra_update_insn_regno_info (curr_insn
);
3563 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3567 /* Return true if X is in LIST. */
3569 in_list_p (rtx x
, rtx list
)
3571 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3572 if (XEXP (list
, 0) == x
)
3577 /* Return true if X contains an allocatable hard register (if
3578 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3580 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3586 code
= GET_CODE (x
);
3589 int regno
= REGNO (x
);
3590 HARD_REG_SET alloc_regs
;
3594 if (regno
>= FIRST_PSEUDO_REGISTER
)
3595 regno
= lra_get_regno_hard_regno (regno
);
3598 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3599 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3603 if (regno
< FIRST_PSEUDO_REGISTER
)
3607 return lra_get_regno_hard_regno (regno
) < 0;
3610 fmt
= GET_RTX_FORMAT (code
);
3611 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3615 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3618 else if (fmt
[i
] == 'E')
3620 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3621 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3628 /* Process all regs in location *LOC and change them on equivalent
3629 substitution. Return true if any change was done. */
3631 loc_equivalence_change_p (rtx
*loc
)
3633 rtx subst
, reg
, x
= *loc
;
3634 bool result
= false;
3635 enum rtx_code code
= GET_CODE (x
);
3641 reg
= SUBREG_REG (x
);
3642 if ((subst
= get_equiv_substitution (reg
)) != reg
3643 && GET_MODE (subst
) == VOIDmode
)
3645 /* We cannot reload debug location. Simplify subreg here
3646 while we know the inner mode. */
3647 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
3648 GET_MODE (reg
), SUBREG_BYTE (x
));
3652 if (code
== REG
&& (subst
= get_equiv_substitution (x
)) != x
)
3658 /* Scan all the operand sub-expressions. */
3659 fmt
= GET_RTX_FORMAT (code
);
3660 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3663 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
3664 else if (fmt
[i
] == 'E')
3665 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3667 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
3672 /* Similar to loc_equivalence_change_p, but for use as
3673 simplify_replace_fn_rtx callback. */
3675 loc_equivalence_callback (rtx loc
, const_rtx
, void *)
3680 rtx subst
= get_equiv_substitution (loc
);
3687 /* Maximum number of generated reload insns per an insn. It is for
3688 preventing this pass cycling in a bug case. */
3689 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
3691 /* The current iteration number of this LRA pass. */
3692 int lra_constraint_iter
;
3694 /* The current iteration number of this LRA pass after the last spill
3696 int lra_constraint_iter_after_spill
;
3698 /* True if we substituted equiv which needs checking register
3699 allocation correctness because the equivalent value contains
3700 allocatable hard registers or when we restore multi-register
3702 bool lra_risky_transformations_p
;
3704 /* Return true if REGNO is referenced in more than one block. */
3706 multi_block_pseudo_p (int regno
)
3708 basic_block bb
= NULL
;
3712 if (regno
< FIRST_PSEUDO_REGISTER
)
3715 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
3717 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
3718 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
3723 /* Return true if LIST contains a deleted insn. */
3725 contains_deleted_insn_p (rtx list
)
3727 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3728 if (NOTE_P (XEXP (list
, 0))
3729 && NOTE_KIND (XEXP (list
, 0)) == NOTE_INSN_DELETED
)
3734 /* Return true if X contains a pseudo dying in INSN. */
3736 dead_pseudo_p (rtx x
, rtx insn
)
3743 return (insn
!= NULL_RTX
3744 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
3745 code
= GET_CODE (x
);
3746 fmt
= GET_RTX_FORMAT (code
);
3747 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3751 if (dead_pseudo_p (XEXP (x
, i
), insn
))
3754 else if (fmt
[i
] == 'E')
3756 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3757 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
3764 /* Return true if INSN contains a dying pseudo in INSN right hand
3767 insn_rhs_dead_pseudo_p (rtx insn
)
3769 rtx set
= single_set (insn
);
3771 gcc_assert (set
!= NULL
);
3772 return dead_pseudo_p (SET_SRC (set
), insn
);
3775 /* Return true if any init insn of REGNO contains a dying pseudo in
3776 insn right hand side. */
3778 init_insn_rhs_dead_pseudo_p (int regno
)
3780 rtx insns
= ira_reg_equiv
[regno
].init_insns
;
3785 return insn_rhs_dead_pseudo_p (insns
);
3786 for (; insns
!= NULL_RTX
; insns
= XEXP (insns
, 1))
3787 if (insn_rhs_dead_pseudo_p (XEXP (insns
, 0)))
3792 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is
3793 reverse only if we have one init insn with given REGNO as a
3796 reverse_equiv_p (int regno
)
3800 if ((insns
= ira_reg_equiv
[regno
].init_insns
) == NULL_RTX
)
3802 if (! INSN_P (XEXP (insns
, 0))
3803 || XEXP (insns
, 1) != NULL_RTX
)
3805 if ((set
= single_set (XEXP (insns
, 0))) == NULL_RTX
)
3807 return REG_P (SET_SRC (set
)) && (int) REGNO (SET_SRC (set
)) == regno
;
3810 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We
3811 call this function only for non-reverse equivalence. */
3813 contains_reloaded_insn_p (int regno
)
3816 rtx list
= ira_reg_equiv
[regno
].init_insns
;
3818 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3819 if ((set
= single_set (XEXP (list
, 0))) == NULL_RTX
3820 || ! REG_P (SET_DEST (set
))
3821 || (int) REGNO (SET_DEST (set
)) != regno
)
3826 /* Entry function of LRA constraint pass. Return true if the
3827 constraint pass did change the code. */
3829 lra_constraints (bool first_p
)
3832 int i
, hard_regno
, new_insns_num
;
3833 unsigned int min_len
, new_min_len
, uid
;
3834 rtx set
, x
, reg
, dest_reg
;
3835 basic_block last_bb
;
3836 bitmap_head equiv_insn_bitmap
;
3839 lra_constraint_iter
++;
3840 if (lra_dump_file
!= NULL
)
3841 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
3842 lra_constraint_iter
);
3843 lra_constraint_iter_after_spill
++;
3844 if (lra_constraint_iter_after_spill
> LRA_MAX_CONSTRAINT_ITERATION_NUMBER
)
3846 ("Maximum number of LRA constraint passes is achieved (%d)\n",
3847 LRA_MAX_CONSTRAINT_ITERATION_NUMBER
);
3849 lra_risky_transformations_p
= false;
3850 new_insn_uid_start
= get_max_uid ();
3851 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
3852 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
3853 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3854 if (lra_reg_info
[i
].nrefs
!= 0)
3856 ira_reg_equiv
[i
].profitable_p
= true;
3857 reg
= regno_reg_rtx
[i
];
3858 if ((hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3862 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
3863 for (j
= 0; j
< nregs
; j
++)
3864 df_set_regs_ever_live (hard_regno
+ j
, true);
3866 else if ((x
= get_equiv_substitution (reg
)) != reg
)
3868 bool pseudo_p
= contains_reg_p (x
, false, false);
3870 /* After RTL transformation, we can not guarantee that
3871 pseudo in the substitution was not reloaded which might
3872 make equivalence invalid. For example, in reverse
3879 the memory address register was reloaded before the 2nd
3881 if ((! first_p
&& pseudo_p
)
3882 /* We don't use DF for compilation speed sake. So it
3883 is problematic to update live info when we use an
3884 equivalence containing pseudos in more than one
3886 || (pseudo_p
&& multi_block_pseudo_p (i
))
3887 /* If an init insn was deleted for some reason, cancel
3888 the equiv. We could update the equiv insns after
3889 transformations including an equiv insn deletion
3890 but it is not worthy as such cases are extremely
3892 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
3893 /* If it is not a reverse equivalence, we check that a
3894 pseudo in rhs of the init insn is not dying in the
3895 insn. Otherwise, the live info at the beginning of
3896 the corresponding BB might be wrong after we
3897 removed the insn. When the equiv can be a
3898 constant, the right hand side of the init insn can
3900 || (! reverse_equiv_p (i
)
3901 && (init_insn_rhs_dead_pseudo_p (i
)
3902 /* If we reloaded the pseudo in an equivalence
3903 init insn, we can not remove the equiv init
3904 insns and the init insns might write into
3905 const memory in this case. */
3906 || contains_reloaded_insn_p (i
)))
3907 /* Prevent access beyond equivalent memory for
3908 paradoxical subregs. */
3910 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
3911 > GET_MODE_SIZE (GET_MODE (x
)))))
3912 ira_reg_equiv
[i
].defined_p
= false;
3913 if (contains_reg_p (x
, false, true))
3914 ira_reg_equiv
[i
].profitable_p
= false;
3915 if (get_equiv_substitution (reg
) != reg
)
3916 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
3919 /* We should add all insns containing pseudos which should be
3920 substituted by their equivalences. */
3921 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
3922 lra_push_insn_by_uid (uid
);
3923 lra_eliminate (false);
3924 min_len
= lra_insn_stack_length ();
3928 while ((new_min_len
= lra_insn_stack_length ()) != 0)
3930 curr_insn
= lra_pop_insn ();
3932 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
3933 if (curr_bb
!= last_bb
)
3936 bb_reload_num
= lra_curr_reload_num
;
3938 if (min_len
> new_min_len
)
3940 min_len
= new_min_len
;
3943 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
3945 ("Max. number of generated reload insns per insn is achieved (%d)\n",
3946 MAX_RELOAD_INSNS_NUMBER
);
3948 if (DEBUG_INSN_P (curr_insn
))
3950 /* We need to check equivalence in debug insn and change
3951 pseudo to the equivalent value if necessary. */
3952 curr_id
= lra_get_insn_recog_data (curr_insn
);
3953 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
3955 rtx old
= *curr_id
->operand_loc
[0];
3956 *curr_id
->operand_loc
[0]
3957 = simplify_replace_fn_rtx (old
, NULL_RTX
,
3958 loc_equivalence_callback
, NULL
);
3959 if (old
!= *curr_id
->operand_loc
[0])
3961 lra_update_insn_regno_info (curr_insn
);
3966 else if (INSN_P (curr_insn
))
3968 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
3970 dest_reg
= SET_DEST (set
);
3971 /* The equivalence pseudo could be set up as SUBREG in a
3972 case when it is a call restore insn in a mode
3973 different from the pseudo mode. */
3974 if (GET_CODE (dest_reg
) == SUBREG
)
3975 dest_reg
= SUBREG_REG (dest_reg
);
3976 if ((REG_P (dest_reg
)
3977 && (x
= get_equiv_substitution (dest_reg
)) != dest_reg
3978 /* Remove insns which set up a pseudo whose value
3979 can not be changed. Such insns might be not in
3980 init_insns because we don't update equiv data
3981 during insn transformations.
3983 As an example, let suppose that a pseudo got
3984 hard register and on the 1st pass was not
3985 changed to equivalent constant. We generate an
3986 additional insn setting up the pseudo because of
3987 secondary memory movement. Then the pseudo is
3988 spilled and we use the equiv constant. In this
3989 case we should remove the additional insn and
3990 this insn is not init_insns list. */
3991 && (! MEM_P (x
) || MEM_READONLY_P (x
)
3992 /* Check that this is actually an insn setting
3993 up the equivalence. */
3994 || in_list_p (curr_insn
,
3996 [REGNO (dest_reg
)].init_insns
)))
3997 || (((x
= get_equiv_substitution (SET_SRC (set
)))
3999 && in_list_p (curr_insn
,
4001 [REGNO (SET_SRC (set
))].init_insns
)))
4003 /* This is equiv init insn of pseudo which did not get a
4004 hard register -- remove the insn. */
4005 if (lra_dump_file
!= NULL
)
4007 fprintf (lra_dump_file
,
4008 " Removing equiv init insn %i (freq=%d)\n",
4009 INSN_UID (curr_insn
),
4010 BLOCK_FOR_INSN (curr_insn
)->frequency
);
4011 dump_insn_slim (lra_dump_file
, curr_insn
);
4013 if (contains_reg_p (x
, true, false))
4014 lra_risky_transformations_p
= true;
4015 lra_set_insn_deleted (curr_insn
);
4019 curr_id
= lra_get_insn_recog_data (curr_insn
);
4020 curr_static_id
= curr_id
->insn_static_data
;
4021 init_curr_insn_input_reloads ();
4022 init_curr_operand_mode ();
4023 if (curr_insn_transform ())
4025 /* Check non-transformed insns too for equiv change as USE
4026 or CLOBBER don't need reloads but can contain pseudos
4027 being changed on their equivalences. */
4028 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
4029 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
4031 lra_update_insn_regno_info (curr_insn
);
4036 bitmap_clear (&equiv_insn_bitmap
);
4037 /* If we used a new hard regno, changed_p should be true because the
4038 hard reg is assigned to a new pseudo. */
4039 #ifdef ENABLE_CHECKING
4042 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
4043 if (lra_reg_info
[i
].nrefs
!= 0
4044 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
4046 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
4048 for (j
= 0; j
< nregs
; j
++)
4049 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
4056 /* Initiate the LRA constraint pass. It is done once per
4059 lra_constraints_init (void)
4063 /* Finalize the LRA constraint pass. It is done once per
4066 lra_constraints_finish (void)
4072 /* This page contains code to do inheritance/split
4075 /* Number of reloads passed so far in current EBB. */
4076 static int reloads_num
;
4078 /* Number of calls passed so far in current EBB. */
4079 static int calls_num
;
4081 /* Current reload pseudo check for validity of elements in
4083 static int curr_usage_insns_check
;
4085 /* Info about last usage of registers in EBB to do inheritance/split
4086 transformation. Inheritance transformation is done from a spilled
4087 pseudo and split transformations from a hard register or a pseudo
4088 assigned to a hard register. */
4091 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
4092 value INSNS is valid. The insns is chain of optional debug insns
4093 and a finishing non-debug insn using the corresponding reg. The
4094 value is also used to mark the registers which are set up in the
4095 current insn. The negated insn uid is used for this. */
4097 /* Value of global reloads_num at the last insn in INSNS. */
4099 /* Value of global reloads_nums at the last insn in INSNS. */
4101 /* It can be true only for splitting. And it means that the restore
4102 insn should be put after insn given by the following member. */
4104 /* Next insns in the current EBB which use the original reg and the
4105 original reg value is not changed between the current insn and
4106 the next insns. In order words, e.g. for inheritance, if we need
4107 to use the original reg value again in the next insns we can try
4108 to use the value in a hard register from a reload insn of the
4113 /* Map: regno -> corresponding pseudo usage insns. */
4114 static struct usage_insns
*usage_insns
;
4117 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
4119 usage_insns
[regno
].check
= curr_usage_insns_check
;
4120 usage_insns
[regno
].insns
= insn
;
4121 usage_insns
[regno
].reloads_num
= reloads_num
;
4122 usage_insns
[regno
].calls_num
= calls_num
;
4123 usage_insns
[regno
].after_p
= after_p
;
4126 /* The function is used to form list REGNO usages which consists of
4127 optional debug insns finished by a non-debug insn using REGNO.
4128 RELOADS_NUM is current number of reload insns processed so far. */
4130 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
4132 rtx next_usage_insns
;
4134 if (usage_insns
[regno
].check
== curr_usage_insns_check
4135 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
4136 && DEBUG_INSN_P (insn
))
4138 /* Check that we did not add the debug insn yet. */
4139 if (next_usage_insns
!= insn
4140 && (GET_CODE (next_usage_insns
) != INSN_LIST
4141 || XEXP (next_usage_insns
, 0) != insn
))
4142 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
4145 else if (NONDEBUG_INSN_P (insn
))
4146 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
4148 usage_insns
[regno
].check
= 0;
4151 /* Replace all references to register OLD_REGNO in *LOC with pseudo
4152 register NEW_REG. Return true if any change was made. */
4154 substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
)
4157 bool result
= false;
4165 code
= GET_CODE (x
);
4166 if (code
== REG
&& (int) REGNO (x
) == old_regno
)
4168 enum machine_mode mode
= GET_MODE (*loc
);
4169 enum machine_mode inner_mode
= GET_MODE (new_reg
);
4171 if (mode
!= inner_mode
)
4173 if (GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (inner_mode
)
4174 || ! SCALAR_INT_MODE_P (inner_mode
))
4175 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, 0);
4177 new_reg
= gen_lowpart_SUBREG (mode
, new_reg
);
4183 /* Scan all the operand sub-expressions. */
4184 fmt
= GET_RTX_FORMAT (code
);
4185 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
4189 if (substitute_pseudo (&XEXP (x
, i
), old_regno
, new_reg
))
4192 else if (fmt
[i
] == 'E')
4194 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
4195 if (substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
, new_reg
))
4202 /* Return first non-debug insn in list USAGE_INSNS. */
4204 skip_usage_debug_insns (rtx usage_insns
)
4208 /* Skip debug insns. */
4209 for (insn
= usage_insns
;
4210 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
4211 insn
= XEXP (insn
, 1))
4216 /* Return true if we need secondary memory moves for insn in
4217 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
4220 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
4221 rtx usage_insns ATTRIBUTE_UNUSED
)
4223 #ifndef SECONDARY_MEMORY_NEEDED
4226 rtx insn
, set
, dest
;
4229 if (inher_cl
== ALL_REGS
4230 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
4232 lra_assert (INSN_P (insn
));
4233 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
4235 dest
= SET_DEST (set
);
4238 lra_assert (inher_cl
!= NO_REGS
);
4239 cl
= get_reg_class (REGNO (dest
));
4240 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
4241 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
4245 /* Registers involved in inheritance/split in the current EBB
4246 (inheritance/split pseudos and original registers). */
4247 static bitmap_head check_only_regs
;
4249 /* Do inheritance transformations for insn INSN, which defines (if
4250 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
4251 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
4252 form as the "insns" field of usage_insns. Return true if we
4253 succeed in such transformation.
4255 The transformations look like:
4258 ... p <- i (new insn)
4260 <- ... p ... <- ... i ...
4262 ... i <- p (new insn)
4263 <- ... p ... <- ... i ...
4265 <- ... p ... <- ... i ...
4266 where p is a spilled original pseudo and i is a new inheritance pseudo.
4269 The inheritance pseudo has the smallest class of two classes CL and
4270 class of ORIGINAL REGNO. */
4272 inherit_reload_reg (bool def_p
, int original_regno
,
4273 enum reg_class cl
, rtx insn
, rtx next_usage_insns
)
4275 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
4276 rtx original_reg
= regno_reg_rtx
[original_regno
];
4277 rtx new_reg
, new_insns
, usage_insn
;
4279 lra_assert (! usage_insns
[original_regno
].after_p
);
4280 if (lra_dump_file
!= NULL
)
4281 fprintf (lra_dump_file
,
4282 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
4283 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
4285 if (lra_dump_file
!= NULL
)
4287 fprintf (lra_dump_file
,
4288 " Rejecting inheritance for %d "
4289 "because of disjoint classes %s and %s\n",
4290 original_regno
, reg_class_names
[cl
],
4291 reg_class_names
[rclass
]);
4292 fprintf (lra_dump_file
,
4293 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4297 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
4298 /* We don't use a subset of two classes because it can be
4299 NO_REGS. This transformation is still profitable in most
4300 cases even if the classes are not intersected as register
4301 move is probably cheaper than a memory load. */
4302 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
4304 if (lra_dump_file
!= NULL
)
4305 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
4306 reg_class_names
[cl
], reg_class_names
[rclass
]);
4310 if (check_secondary_memory_needed_p (rclass
, next_usage_insns
))
4312 /* Reject inheritance resulting in secondary memory moves.
4313 Otherwise, there is a danger in LRA cycling. Also such
4314 transformation will be unprofitable. */
4315 if (lra_dump_file
!= NULL
)
4317 rtx insn
= skip_usage_debug_insns (next_usage_insns
);
4318 rtx set
= single_set (insn
);
4320 lra_assert (set
!= NULL_RTX
);
4322 rtx dest
= SET_DEST (set
);
4324 lra_assert (REG_P (dest
));
4325 fprintf (lra_dump_file
,
4326 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
4327 "as secondary mem is needed\n",
4328 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
4329 original_regno
, reg_class_names
[rclass
]);
4330 fprintf (lra_dump_file
,
4331 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4335 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4336 rclass
, "inheritance");
4339 emit_move_insn (original_reg
, new_reg
);
4341 emit_move_insn (new_reg
, original_reg
);
4342 new_insns
= get_insns ();
4344 if (NEXT_INSN (new_insns
) != NULL_RTX
)
4346 if (lra_dump_file
!= NULL
)
4348 fprintf (lra_dump_file
,
4349 " Rejecting inheritance %d->%d "
4350 "as it results in 2 or more insns:\n",
4351 original_regno
, REGNO (new_reg
));
4352 dump_rtl_slim (lra_dump_file
, new_insns
, NULL_RTX
, -1, 0);
4353 fprintf (lra_dump_file
,
4354 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4358 substitute_pseudo (&insn
, original_regno
, new_reg
);
4359 lra_update_insn_regno_info (insn
);
4361 /* We now have a new usage insn for original regno. */
4362 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
4363 if (lra_dump_file
!= NULL
)
4364 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
4365 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
4366 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4367 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4368 bitmap_set_bit (&check_only_regs
, original_regno
);
4369 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
4371 lra_process_new_insns (insn
, NULL_RTX
, new_insns
,
4372 "Add original<-inheritance");
4374 lra_process_new_insns (insn
, new_insns
, NULL_RTX
,
4375 "Add inheritance<-original");
4376 while (next_usage_insns
!= NULL_RTX
)
4378 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4380 usage_insn
= next_usage_insns
;
4381 lra_assert (NONDEBUG_INSN_P (usage_insn
));
4382 next_usage_insns
= NULL
;
4386 usage_insn
= XEXP (next_usage_insns
, 0);
4387 lra_assert (DEBUG_INSN_P (usage_insn
));
4388 next_usage_insns
= XEXP (next_usage_insns
, 1);
4390 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4391 lra_update_insn_regno_info (usage_insn
);
4392 if (lra_dump_file
!= NULL
)
4394 fprintf (lra_dump_file
,
4395 " Inheritance reuse change %d->%d (bb%d):\n",
4396 original_regno
, REGNO (new_reg
),
4397 BLOCK_FOR_INSN (usage_insn
)->index
);
4398 dump_insn_slim (lra_dump_file
, usage_insn
);
4401 if (lra_dump_file
!= NULL
)
4402 fprintf (lra_dump_file
,
4403 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
4407 /* Return true if we need a caller save/restore for pseudo REGNO which
4408 was assigned to a hard register. */
4410 need_for_call_save_p (int regno
)
4412 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
4413 return (usage_insns
[regno
].calls_num
< calls_num
4414 && (overlaps_hard_reg_set_p
4416 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])
4417 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber
[regno
],
4418 PSEUDO_REGNO_MODE (regno
))));
4421 /* Global registers occurring in the current EBB. */
4422 static bitmap_head ebb_global_regs
;
4424 /* Return true if we need a split for hard register REGNO or pseudo
4425 REGNO which was assigned to a hard register.
4426 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
4427 used for reloads since the EBB end. It is an approximation of the
4428 used hard registers in the split range. The exact value would
4429 require expensive calculations. If we were aggressive with
4430 splitting because of the approximation, the split pseudo will save
4431 the same hard register assignment and will be removed in the undo
4432 pass. We still need the approximation because too aggressive
4433 splitting would result in too inaccurate cost calculation in the
4434 assignment pass because of too many generated moves which will be
4435 probably removed in the undo pass. */
4437 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
4439 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
4441 lra_assert (hard_regno
>= 0);
4442 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
4443 /* Don't split eliminable hard registers, otherwise we can
4444 split hard registers like hard frame pointer, which
4445 lives on BB start/end according to DF-infrastructure,
4446 when there is a pseudo assigned to the register and
4447 living in the same BB. */
4448 && (regno
>= FIRST_PSEUDO_REGISTER
4449 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
4450 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
4451 /* Don't split call clobbered hard regs living through
4452 calls, otherwise we might have a check problem in the
4453 assign sub-pass as in the most cases (exception is a
4454 situation when lra_risky_transformations_p value is
4455 true) the assign pass assumes that all pseudos living
4456 through calls are assigned to call saved hard regs. */
4457 && (regno
>= FIRST_PSEUDO_REGISTER
4458 || ! TEST_HARD_REG_BIT (call_used_reg_set
, regno
)
4459 || usage_insns
[regno
].calls_num
== calls_num
)
4460 /* We need at least 2 reloads to make pseudo splitting
4461 profitable. We should provide hard regno splitting in
4462 any case to solve 1st insn scheduling problem when
4463 moving hard register definition up might result in
4464 impossibility to find hard register for reload pseudo of
4465 small register class. */
4466 && (usage_insns
[regno
].reloads_num
4467 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 2) < reloads_num
)
4468 && (regno
< FIRST_PSEUDO_REGISTER
4469 /* For short living pseudos, spilling + inheritance can
4470 be considered a substitution for splitting.
4471 Therefore we do not splitting for local pseudos. It
4472 decreases also aggressiveness of splitting. The
4473 minimal number of references is chosen taking into
4474 account that for 2 references splitting has no sense
4475 as we can just spill the pseudo. */
4476 || (regno
>= FIRST_PSEUDO_REGISTER
4477 && lra_reg_info
[regno
].nrefs
> 3
4478 && bitmap_bit_p (&ebb_global_regs
, regno
))))
4479 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
4482 /* Return class for the split pseudo created from original pseudo with
4483 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
4484 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
4485 results in no secondary memory movements. */
4486 static enum reg_class
4487 choose_split_class (enum reg_class allocno_class
,
4488 int hard_regno ATTRIBUTE_UNUSED
,
4489 enum machine_mode mode ATTRIBUTE_UNUSED
)
4491 #ifndef SECONDARY_MEMORY_NEEDED
4492 return allocno_class
;
4495 enum reg_class cl
, best_cl
= NO_REGS
;
4496 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
4497 = REGNO_REG_CLASS (hard_regno
);
4499 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
4500 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
4501 return allocno_class
;
4503 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
4505 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
4506 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
4507 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
4508 && (best_cl
== NO_REGS
4509 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
4515 /* Do split transformations for insn INSN, which defines or uses
4516 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
4517 the EBB next uses ORIGINAL_REGNO; it has the same form as the
4518 "insns" field of usage_insns.
4520 The transformations look like:
4523 ... s <- p (new insn -- save)
4525 ... p <- s (new insn -- restore)
4526 <- ... p ... <- ... p ...
4528 <- ... p ... <- ... p ...
4529 ... s <- p (new insn -- save)
4531 ... p <- s (new insn -- restore)
4532 <- ... p ... <- ... p ...
4534 where p is an original pseudo got a hard register or a hard
4535 register and s is a new split pseudo. The save is put before INSN
4536 if BEFORE_P is true. Return true if we succeed in such
4539 split_reg (bool before_p
, int original_regno
, rtx insn
, rtx next_usage_insns
)
4541 enum reg_class rclass
;
4543 int hard_regno
, nregs
;
4544 rtx new_reg
, save
, restore
, usage_insn
;
4548 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4550 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4551 hard_regno
= original_regno
;
4552 call_save_p
= false;
4557 hard_regno
= reg_renumber
[original_regno
];
4558 nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (original_regno
)];
4559 rclass
= lra_get_allocno_class (original_regno
);
4560 original_reg
= regno_reg_rtx
[original_regno
];
4561 call_save_p
= need_for_call_save_p (original_regno
);
4563 original_reg
= regno_reg_rtx
[original_regno
];
4564 lra_assert (hard_regno
>= 0);
4565 if (lra_dump_file
!= NULL
)
4566 fprintf (lra_dump_file
,
4567 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4570 enum machine_mode mode
= GET_MODE (original_reg
);
4572 mode
= HARD_REGNO_CALLER_SAVE_MODE (hard_regno
,
4573 hard_regno_nregs
[hard_regno
][mode
],
4575 new_reg
= lra_create_new_reg (mode
, NULL_RTX
, NO_REGS
, "save");
4579 rclass
= choose_split_class (rclass
, hard_regno
,
4580 GET_MODE (original_reg
));
4581 if (rclass
== NO_REGS
)
4583 if (lra_dump_file
!= NULL
)
4585 fprintf (lra_dump_file
,
4586 " Rejecting split of %d(%s): "
4587 "no good reg class for %d(%s)\n",
4589 reg_class_names
[lra_get_allocno_class (original_regno
)],
4591 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4594 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4598 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4600 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4602 save
= emit_spill_move (true, new_reg
, original_reg
);
4603 if (NEXT_INSN (save
) != NULL_RTX
)
4605 lra_assert (! call_save_p
);
4606 if (lra_dump_file
!= NULL
)
4610 " Rejecting split %d->%d resulting in > 2 %s save insns:\n",
4611 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4612 dump_rtl_slim (lra_dump_file
, save
, NULL_RTX
, -1, 0);
4613 fprintf (lra_dump_file
,
4614 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4618 restore
= emit_spill_move (false, new_reg
, original_reg
);
4619 if (NEXT_INSN (restore
) != NULL_RTX
)
4621 lra_assert (! call_save_p
);
4622 if (lra_dump_file
!= NULL
)
4624 fprintf (lra_dump_file
,
4625 " Rejecting split %d->%d "
4626 "resulting in > 2 %s restore insns:\n",
4627 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4628 dump_rtl_slim (lra_dump_file
, restore
, NULL_RTX
, -1, 0);
4629 fprintf (lra_dump_file
,
4630 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4634 after_p
= usage_insns
[original_regno
].after_p
;
4635 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4636 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4637 bitmap_set_bit (&check_only_regs
, original_regno
);
4638 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4641 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4643 usage_insn
= next_usage_insns
;
4646 usage_insn
= XEXP (next_usage_insns
, 0);
4647 lra_assert (DEBUG_INSN_P (usage_insn
));
4648 next_usage_insns
= XEXP (next_usage_insns
, 1);
4649 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4650 lra_update_insn_regno_info (usage_insn
);
4651 if (lra_dump_file
!= NULL
)
4653 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4654 original_regno
, REGNO (new_reg
));
4655 dump_insn_slim (lra_dump_file
, usage_insn
);
4658 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4659 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4660 lra_process_new_insns (usage_insn
, after_p
? NULL_RTX
: restore
,
4661 after_p
? restore
: NULL_RTX
,
4663 ? "Add reg<-save" : "Add reg<-split");
4664 lra_process_new_insns (insn
, before_p
? save
: NULL_RTX
,
4665 before_p
? NULL_RTX
: save
,
4667 ? "Add save<-reg" : "Add split<-reg");
4669 /* If we are trying to split multi-register. We should check
4670 conflicts on the next assignment sub-pass. IRA can allocate on
4671 sub-register levels, LRA do this on pseudos level right now and
4672 this discrepancy may create allocation conflicts after
4674 lra_risky_transformations_p
= true;
4675 if (lra_dump_file
!= NULL
)
4676 fprintf (lra_dump_file
,
4677 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4681 /* Recognize that we need a split transformation for insn INSN, which
4682 defines or uses REGNO in its insn biggest MODE (we use it only if
4683 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
4684 hard registers which might be used for reloads since the EBB end.
4685 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
4686 uid before starting INSN processing. Return true if we succeed in
4687 such transformation. */
4689 split_if_necessary (int regno
, enum machine_mode mode
,
4690 HARD_REG_SET potential_reload_hard_regs
,
4691 bool before_p
, rtx insn
, int max_uid
)
4695 rtx next_usage_insns
;
4697 if (regno
< FIRST_PSEUDO_REGISTER
)
4698 nregs
= hard_regno_nregs
[regno
][mode
];
4699 for (i
= 0; i
< nregs
; i
++)
4700 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
4701 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
4702 /* To avoid processing the register twice or more. */
4703 && ((GET_CODE (next_usage_insns
) != INSN_LIST
4704 && INSN_UID (next_usage_insns
) < max_uid
)
4705 || (GET_CODE (next_usage_insns
) == INSN_LIST
4706 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
4707 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
4708 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
4713 /* Check only registers living at the current program point in the
4715 static bitmap_head live_regs
;
4717 /* Update live info in EBB given by its HEAD and TAIL insns after
4718 inheritance/split transformation. The function removes dead moves
4721 update_ebb_live_info (rtx head
, rtx tail
)
4728 basic_block last_bb
, prev_bb
, curr_bb
;
4730 struct lra_insn_reg
*reg
;
4734 last_bb
= BLOCK_FOR_INSN (tail
);
4736 for (curr_insn
= tail
;
4737 curr_insn
!= PREV_INSN (head
);
4738 curr_insn
= prev_insn
)
4740 prev_insn
= PREV_INSN (curr_insn
);
4741 /* We need to process empty blocks too. They contain
4742 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
4743 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
4745 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4746 if (curr_bb
!= prev_bb
)
4748 if (prev_bb
!= NULL
)
4750 /* Update df_get_live_in (prev_bb): */
4751 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4752 if (bitmap_bit_p (&live_regs
, j
))
4753 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
4755 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
4757 if (curr_bb
!= last_bb
)
4759 /* Update df_get_live_out (curr_bb): */
4760 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4762 live_p
= bitmap_bit_p (&live_regs
, j
);
4764 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
4765 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
4771 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
4773 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
4777 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
4779 if (! NONDEBUG_INSN_P (curr_insn
))
4781 curr_id
= lra_get_insn_recog_data (curr_insn
);
4783 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
4784 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
4785 && bitmap_bit_p (&check_only_regs
, regno
)
4786 && ! bitmap_bit_p (&live_regs
, regno
))
4788 /* See which defined values die here. */
4789 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4790 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4791 bitmap_clear_bit (&live_regs
, reg
->regno
);
4792 /* Mark each used value as live. */
4793 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4794 if (reg
->type
!= OP_OUT
4795 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
4796 bitmap_set_bit (&live_regs
, reg
->regno
);
4797 /* It is quite important to remove dead move insns because it
4798 means removing dead store. We don't need to process them for
4802 if (lra_dump_file
!= NULL
)
4804 fprintf (lra_dump_file
, " Removing dead insn:\n ");
4805 dump_insn_slim (lra_dump_file
, curr_insn
);
4807 lra_set_insn_deleted (curr_insn
);
4812 /* The structure describes info to do an inheritance for the current
4813 insn. We need to collect such info first before doing the
4814 transformations because the transformations change the insn
4815 internal representation. */
4818 /* Original regno. */
4820 /* Subsequent insns which can inherit original reg value. */
4824 /* Array containing all info for doing inheritance from the current
4826 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
4828 /* Number elements in the previous array. */
4829 static int to_inherit_num
;
4831 /* Add inheritance info REGNO and INSNS. Their meaning is described in
4832 structure to_inherit. */
4834 add_to_inherit (int regno
, rtx insns
)
4838 for (i
= 0; i
< to_inherit_num
; i
++)
4839 if (to_inherit
[i
].regno
== regno
)
4841 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
4842 to_inherit
[to_inherit_num
].regno
= regno
;
4843 to_inherit
[to_inherit_num
++].insns
= insns
;
4846 /* Return the last non-debug insn in basic block BB, or the block begin
4849 get_last_insertion_point (basic_block bb
)
4853 FOR_BB_INSNS_REVERSE (bb
, insn
)
4854 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
4859 /* Set up RES by registers living on edges FROM except the edge (FROM,
4860 TO) or by registers set up in a jump insn in BB FROM. */
4862 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
4865 struct lra_insn_reg
*reg
;
4869 lra_assert (to
!= NULL
);
4871 FOR_EACH_EDGE (e
, ei
, from
->succs
)
4873 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
4874 last
= get_last_insertion_point (from
);
4875 if (! JUMP_P (last
))
4877 curr_id
= lra_get_insn_recog_data (last
);
4878 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4879 if (reg
->type
!= OP_IN
)
4880 bitmap_set_bit (res
, reg
->regno
);
4883 /* Used as a temporary results of some bitmap calculations. */
4884 static bitmap_head temp_bitmap
;
4886 /* Do inheritance/split transformations in EBB starting with HEAD and
4887 finishing on TAIL. We process EBB insns in the reverse order.
4888 Return true if we did any inheritance/split transformation in the
4891 We should avoid excessive splitting which results in worse code
4892 because of inaccurate cost calculations for spilling new split
4893 pseudos in such case. To achieve this we do splitting only if
4894 register pressure is high in given basic block and there are reload
4895 pseudos requiring hard registers. We could do more register
4896 pressure calculations at any given program point to avoid necessary
4897 splitting even more but it is to expensive and the current approach
4898 works well enough. */
4900 inherit_in_ebb (rtx head
, rtx tail
)
4902 int i
, src_regno
, dst_regno
, nregs
;
4903 bool change_p
, succ_p
;
4904 rtx prev_insn
, next_usage_insns
, set
, last_insn
;
4906 struct lra_insn_reg
*reg
;
4907 basic_block last_processed_bb
, curr_bb
= NULL
;
4908 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
4912 bool head_p
, after_p
;
4915 curr_usage_insns_check
++;
4916 reloads_num
= calls_num
= 0;
4917 bitmap_clear (&check_only_regs
);
4918 last_processed_bb
= NULL
;
4919 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
4920 CLEAR_HARD_REG_SET (live_hard_regs
);
4921 /* We don't process new insns generated in the loop. */
4922 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
4924 prev_insn
= PREV_INSN (curr_insn
);
4925 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
4926 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4927 if (last_processed_bb
!= curr_bb
)
4929 /* We are at the end of BB. Add qualified living
4930 pseudos for potential splitting. */
4931 to_process
= df_get_live_out (curr_bb
);
4932 if (last_processed_bb
!= NULL
)
4934 /* We are somewhere in the middle of EBB. */
4935 get_live_on_other_edges (curr_bb
, last_processed_bb
,
4937 to_process
= &temp_bitmap
;
4939 last_processed_bb
= curr_bb
;
4940 last_insn
= get_last_insertion_point (curr_bb
);
4941 after_p
= (! JUMP_P (last_insn
)
4942 && (! CALL_P (last_insn
)
4943 || (find_reg_note (last_insn
,
4944 REG_NORETURN
, NULL_RTX
) == NULL_RTX
4945 && ! SIBLING_CALL_P (last_insn
))));
4946 REG_SET_TO_HARD_REG_SET (live_hard_regs
, df_get_live_out (curr_bb
));
4947 IOR_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
4948 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
4949 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
4950 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
4952 if ((int) j
>= lra_constraint_new_regno_start
)
4954 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
4956 if (j
< FIRST_PSEUDO_REGISTER
)
4957 SET_HARD_REG_BIT (live_hard_regs
, j
);
4959 add_to_hard_reg_set (&live_hard_regs
,
4960 PSEUDO_REGNO_MODE (j
),
4962 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
4966 src_regno
= dst_regno
= -1;
4967 if (NONDEBUG_INSN_P (curr_insn
)
4968 && (set
= single_set (curr_insn
)) != NULL_RTX
4969 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
4971 src_regno
= REGNO (SET_SRC (set
));
4972 dst_regno
= REGNO (SET_DEST (set
));
4974 if (src_regno
< lra_constraint_new_regno_start
4975 && src_regno
>= FIRST_PSEUDO_REGISTER
4976 && reg_renumber
[src_regno
] < 0
4977 && dst_regno
>= lra_constraint_new_regno_start
4978 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
4980 /* 'reload_pseudo <- original_pseudo'. */
4983 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
4984 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
4985 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
4986 curr_insn
, next_usage_insns
);
4990 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
4991 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
4992 IOR_HARD_REG_SET (potential_reload_hard_regs
,
4993 reg_class_contents
[cl
]);
4995 else if (src_regno
>= lra_constraint_new_regno_start
4996 && dst_regno
< lra_constraint_new_regno_start
4997 && dst_regno
>= FIRST_PSEUDO_REGISTER
4998 && reg_renumber
[dst_regno
] < 0
4999 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
5000 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5001 && (next_usage_insns
5002 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5005 /* 'original_pseudo <- reload_pseudo'. */
5006 if (! JUMP_P (curr_insn
)
5007 && inherit_reload_reg (true, dst_regno
, cl
,
5008 curr_insn
, next_usage_insns
))
5011 usage_insns
[dst_regno
].check
= 0;
5012 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
5013 IOR_HARD_REG_SET (potential_reload_hard_regs
,
5014 reg_class_contents
[cl
]);
5016 else if (INSN_P (curr_insn
))
5019 int max_uid
= get_max_uid ();
5021 curr_id
= lra_get_insn_recog_data (curr_insn
);
5022 curr_static_id
= curr_id
->insn_static_data
;
5024 /* Process insn definitions. */
5025 for (iter
= 0; iter
< 2; iter
++)
5026 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5029 if (reg
->type
!= OP_IN
5030 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5032 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
5033 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
5034 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
5035 && (next_usage_insns
5036 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
5038 struct lra_insn_reg
*r
;
5040 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
5041 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
5043 /* Don't do inheritance if the pseudo is also
5044 used in the insn. */
5046 /* We can not do inheritance right now
5047 because the current insn reg info (chain
5048 regs) can change after that. */
5049 add_to_inherit (dst_regno
, next_usage_insns
);
5051 /* We can not process one reg twice here because of
5052 usage_insns invalidation. */
5053 if ((dst_regno
< FIRST_PSEUDO_REGISTER
5054 || reg_renumber
[dst_regno
] >= 0)
5055 && ! reg
->subreg_p
&& reg
->type
!= OP_IN
)
5059 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
5060 potential_reload_hard_regs
,
5061 false, curr_insn
, max_uid
))
5063 CLEAR_HARD_REG_SET (s
);
5064 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
5065 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
5067 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
5068 reg_renumber
[dst_regno
]);
5069 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
5071 /* We should invalidate potential inheritance or
5072 splitting for the current insn usages to the next
5073 usage insns (see code below) as the output pseudo
5075 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
5076 && reg_renumber
[dst_regno
] < 0)
5077 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
5078 && (dst_regno
< FIRST_PSEUDO_REGISTER
5079 || reg_renumber
[dst_regno
] >= 0)))
5081 /* Invalidate and mark definitions. */
5082 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
5083 usage_insns
[dst_regno
].check
= -(int) INSN_UID (curr_insn
);
5086 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
5087 for (i
= 0; i
< nregs
; i
++)
5088 usage_insns
[dst_regno
+ i
].check
5089 = -(int) INSN_UID (curr_insn
);
5093 if (! JUMP_P (curr_insn
))
5094 for (i
= 0; i
< to_inherit_num
; i
++)
5095 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
5096 ALL_REGS
, curr_insn
,
5097 to_inherit
[i
].insns
))
5099 if (CALL_P (curr_insn
))
5101 rtx cheap
, pat
, dest
, restore
;
5102 int regno
, hard_regno
;
5105 if ((cheap
= find_reg_note (curr_insn
,
5106 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
5107 && ((cheap
= XEXP (cheap
, 0)), true)
5108 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
5109 && (hard_regno
= reg_renumber
[regno
]) >= 0
5110 /* If there are pending saves/restores, the
5111 optimization is not worth. */
5112 && usage_insns
[regno
].calls_num
== calls_num
- 1
5113 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
5115 /* Restore the pseudo from the call result as
5116 REG_RETURNED note says that the pseudo value is
5117 in the call result and the pseudo is an argument
5119 pat
= PATTERN (curr_insn
);
5120 if (GET_CODE (pat
) == PARALLEL
)
5121 pat
= XVECEXP (pat
, 0, 0);
5122 dest
= SET_DEST (pat
);
5124 emit_move_insn (cheap
, copy_rtx (dest
));
5125 restore
= get_insns ();
5127 lra_process_new_insns (curr_insn
, NULL
, restore
,
5128 "Inserting call parameter restore");
5129 /* We don't need to save/restore of the pseudo from
5131 usage_insns
[regno
].calls_num
= calls_num
;
5132 bitmap_set_bit (&check_only_regs
, regno
);
5136 /* Process insn usages. */
5137 for (iter
= 0; iter
< 2; iter
++)
5138 for (reg
= iter
== 0 ? curr_id
->regs
: curr_static_id
->hard_regs
;
5141 if ((reg
->type
!= OP_OUT
5142 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
5143 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
5145 if (src_regno
>= FIRST_PSEUDO_REGISTER
5146 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
5148 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
5149 && (next_usage_insns
5150 = usage_insns
[src_regno
].insns
) != NULL_RTX
5151 && NONDEBUG_INSN_P (curr_insn
))
5152 add_to_inherit (src_regno
, next_usage_insns
);
5153 else if (usage_insns
[src_regno
].check
5154 != -(int) INSN_UID (curr_insn
))
5155 /* Add usages but only if the reg is not set up
5156 in the same insn. */
5157 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
5159 else if (src_regno
< FIRST_PSEUDO_REGISTER
5160 || reg_renumber
[src_regno
] >= 0)
5163 rtx use_insn
= curr_insn
;
5165 before_p
= (JUMP_P (curr_insn
)
5166 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
5167 if (NONDEBUG_INSN_P (curr_insn
)
5168 && split_if_necessary (src_regno
, reg
->biggest_mode
,
5169 potential_reload_hard_regs
,
5170 before_p
, curr_insn
, max_uid
))
5173 lra_risky_transformations_p
= true;
5176 usage_insns
[src_regno
].check
= 0;
5178 use_insn
= PREV_INSN (curr_insn
);
5180 if (NONDEBUG_INSN_P (curr_insn
))
5182 if (src_regno
< FIRST_PSEUDO_REGISTER
)
5183 add_to_hard_reg_set (&live_hard_regs
,
5184 reg
->biggest_mode
, src_regno
);
5186 add_to_hard_reg_set (&live_hard_regs
,
5187 PSEUDO_REGNO_MODE (src_regno
),
5188 reg_renumber
[src_regno
]);
5190 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
5193 for (i
= 0; i
< to_inherit_num
; i
++)
5195 src_regno
= to_inherit
[i
].regno
;
5196 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
5197 curr_insn
, to_inherit
[i
].insns
))
5200 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
5203 /* We reached the start of the current basic block. */
5204 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
5205 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
5207 /* We reached the beginning of the current block -- do
5208 rest of spliting in the current BB. */
5209 to_process
= df_get_live_in (curr_bb
);
5210 if (BLOCK_FOR_INSN (head
) != curr_bb
)
5212 /* We are somewhere in the middle of EBB. */
5213 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
5214 curr_bb
, &temp_bitmap
);
5215 to_process
= &temp_bitmap
;
5218 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
5220 if ((int) j
>= lra_constraint_new_regno_start
)
5222 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
5223 && usage_insns
[j
].check
== curr_usage_insns_check
5224 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
5226 if (need_for_split_p (potential_reload_hard_regs
, j
))
5228 if (lra_dump_file
!= NULL
&& head_p
)
5230 fprintf (lra_dump_file
,
5231 " ----------------------------------\n");
5234 if (split_reg (false, j
, bb_note (curr_bb
),
5238 usage_insns
[j
].check
= 0;
5246 /* This value affects EBB forming. If probability of edge from EBB to
5247 a BB is not greater than the following value, we don't add the BB
5249 #define EBB_PROBABILITY_CUTOFF ((REG_BR_PROB_BASE * 50) / 100)
5251 /* Current number of inheritance/split iteration. */
5252 int lra_inheritance_iter
;
5254 /* Entry function for inheritance/split pass. */
5256 lra_inheritance (void)
5259 basic_block bb
, start_bb
;
5262 lra_inheritance_iter
++;
5263 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5265 timevar_push (TV_LRA_INHERITANCE
);
5266 if (lra_dump_file
!= NULL
)
5267 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
5268 lra_inheritance_iter
);
5269 curr_usage_insns_check
= 0;
5270 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
5271 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
5272 usage_insns
[i
].check
= 0;
5273 bitmap_initialize (&check_only_regs
, ®_obstack
);
5274 bitmap_initialize (&live_regs
, ®_obstack
);
5275 bitmap_initialize (&temp_bitmap
, ®_obstack
);
5276 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
5280 if (lra_dump_file
!= NULL
)
5281 fprintf (lra_dump_file
, "EBB");
5282 /* Form a EBB starting with BB. */
5283 bitmap_clear (&ebb_global_regs
);
5284 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
5287 if (lra_dump_file
!= NULL
)
5288 fprintf (lra_dump_file
, " %d", bb
->index
);
5289 if (bb
->next_bb
== EXIT_BLOCK_PTR
|| LABEL_P (BB_HEAD (bb
->next_bb
)))
5291 e
= find_fallthru_edge (bb
->succs
);
5294 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
5298 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
5299 if (lra_dump_file
!= NULL
)
5300 fprintf (lra_dump_file
, "\n");
5301 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
5302 /* Remember that the EBB head and tail can change in
5304 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
5306 bitmap_clear (&ebb_global_regs
);
5307 bitmap_clear (&temp_bitmap
);
5308 bitmap_clear (&live_regs
);
5309 bitmap_clear (&check_only_regs
);
5312 timevar_pop (TV_LRA_INHERITANCE
);
5317 /* This page contains code to undo failed inheritance/split
5320 /* Current number of iteration undoing inheritance/split. */
5321 int lra_undo_inheritance_iter
;
5323 /* Fix BB live info LIVE after removing pseudos created on pass doing
5324 inheritance/split which are REMOVED_PSEUDOS. */
5326 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
5331 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
5332 if (bitmap_clear_bit (live
, regno
))
5333 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
5336 /* Return regno of the (subreg of) REG. Otherwise, return a negative
5341 if (GET_CODE (reg
) == SUBREG
)
5342 reg
= SUBREG_REG (reg
);
5348 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
5349 return true if we did any change. The undo transformations for
5350 inheritance looks like
5354 p <- i, i <- p, and i <- i3
5355 where p is original pseudo from which inheritance pseudo i was
5356 created, i and i3 are removed inheritance pseudos, i2 is another
5357 not removed inheritance pseudo. All split pseudos or other
5358 occurrences of removed inheritance pseudos are changed on the
5359 corresponding original pseudos.
5361 The function also schedules insns changed and created during
5362 inheritance/split pass for processing by the subsequent constraint
5365 remove_inheritance_pseudos (bitmap remove_pseudos
)
5368 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
5369 rtx set
, prev_set
, prev_insn
;
5370 bool change_p
, done_p
;
5372 change_p
= ! bitmap_empty_p (remove_pseudos
);
5373 /* We can not finish the function right away if CHANGE_P is true
5374 because we need to marks insns affected by previous
5375 inheritance/split pass for processing by the subsequent
5379 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
5380 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
5381 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
5383 if (! INSN_P (curr_insn
))
5386 sregno
= dregno
= -1;
5387 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
5388 && (set
= single_set (curr_insn
)) != NULL_RTX
)
5390 dregno
= get_regno (SET_DEST (set
));
5391 sregno
= get_regno (SET_SRC (set
));
5394 if (sregno
>= 0 && dregno
>= 0)
5396 if ((bitmap_bit_p (remove_pseudos
, sregno
)
5397 && (lra_reg_info
[sregno
].restore_regno
== dregno
5398 || (bitmap_bit_p (remove_pseudos
, dregno
)
5399 && (lra_reg_info
[sregno
].restore_regno
5400 == lra_reg_info
[dregno
].restore_regno
))))
5401 || (bitmap_bit_p (remove_pseudos
, dregno
)
5402 && lra_reg_info
[dregno
].restore_regno
== sregno
))
5403 /* One of the following cases:
5404 original <- removed inheritance pseudo
5405 removed inherit pseudo <- another removed inherit pseudo
5406 removed inherit pseudo <- original pseudo
5408 removed_split_pseudo <- original_reg
5409 original_reg <- removed_split_pseudo */
5411 if (lra_dump_file
!= NULL
)
5413 fprintf (lra_dump_file
, " Removing %s:\n",
5414 bitmap_bit_p (&lra_split_regs
, sregno
)
5415 || bitmap_bit_p (&lra_split_regs
, dregno
)
5416 ? "split" : "inheritance");
5417 dump_insn_slim (lra_dump_file
, curr_insn
);
5419 lra_set_insn_deleted (curr_insn
);
5422 else if (bitmap_bit_p (remove_pseudos
, sregno
)
5423 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
5425 /* Search the following pattern:
5426 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
5427 original_pseudo <- inherit_or_split_pseudo1
5428 where the 2nd insn is the current insn and
5429 inherit_or_split_pseudo2 is not removed. If it is found,
5430 change the current insn onto:
5431 original_pseudo <- inherit_or_split_pseudo2. */
5432 for (prev_insn
= PREV_INSN (curr_insn
);
5433 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
5434 prev_insn
= PREV_INSN (prev_insn
))
5436 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
5437 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
5438 /* There should be no subregs in insn we are
5439 searching because only the original reg might
5440 be in subreg when we changed the mode of
5441 load/store for splitting. */
5442 && REG_P (SET_DEST (prev_set
))
5443 && REG_P (SET_SRC (prev_set
))
5444 && (int) REGNO (SET_DEST (prev_set
)) == sregno
5445 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
5446 >= FIRST_PSEUDO_REGISTER
)
5447 /* As we consider chain of inheritance or
5448 splitting described in above comment we should
5449 check that sregno and prev_sregno were
5450 inheritance/split pseudos created from the
5451 same original regno. */
5452 && (lra_reg_info
[sregno
].restore_regno
5453 == lra_reg_info
[prev_sregno
].restore_regno
)
5454 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
5456 lra_assert (GET_MODE (SET_SRC (prev_set
))
5457 == GET_MODE (regno_reg_rtx
[sregno
]));
5458 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
5459 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
5461 SET_SRC (set
) = SET_SRC (prev_set
);
5462 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5463 lra_set_used_insn_alternative_by_uid
5464 (INSN_UID (curr_insn
), -1);
5466 if (lra_dump_file
!= NULL
)
5468 fprintf (lra_dump_file
, " Change reload insn:\n");
5469 dump_insn_slim (lra_dump_file
, curr_insn
);
5476 struct lra_insn_reg
*reg
;
5477 bool restored_regs_p
= false;
5478 bool kept_regs_p
= false;
5480 curr_id
= lra_get_insn_recog_data (curr_insn
);
5481 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
5484 restore_regno
= lra_reg_info
[regno
].restore_regno
;
5485 if (restore_regno
>= 0)
5487 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
5489 substitute_pseudo (&curr_insn
, regno
,
5490 regno_reg_rtx
[restore_regno
]);
5491 restored_regs_p
= true;
5497 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
5499 /* The instruction has changed since the previous
5500 constraints pass. */
5501 lra_push_insn_and_update_insn_regno_info (curr_insn
);
5502 lra_set_used_insn_alternative_by_uid
5503 (INSN_UID (curr_insn
), -1);
5505 else if (restored_regs_p
)
5506 /* The instruction has been restored to the form that
5507 it had during the previous constraints pass. */
5508 lra_update_insn_regno_info (curr_insn
);
5509 if (restored_regs_p
&& lra_dump_file
!= NULL
)
5511 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
5512 dump_insn_slim (lra_dump_file
, curr_insn
);
5520 /* If optional reload pseudos failed to get a hard register or was not
5521 inherited, it is better to remove optional reloads. We do this
5522 transformation after undoing inheritance to figure out necessity to
5523 remove optional reloads easier. Return true if we do any
5526 undo_optional_reloads (void)
5528 bool change_p
, keep_p
;
5529 unsigned int regno
, uid
;
5530 bitmap_iterator bi
, bi2
;
5531 rtx insn
, set
, src
, dest
;
5532 bitmap_head removed_optional_reload_pseudos
, insn_bitmap
;
5534 bitmap_initialize (&removed_optional_reload_pseudos
, ®_obstack
);
5535 bitmap_copy (&removed_optional_reload_pseudos
, &lra_optional_reload_pseudos
);
5536 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5539 /* Keep optional reloads from previous subpasses. */
5540 if (lra_reg_info
[regno
].restore_regno
< 0
5541 /* If the original pseudo changed its allocation, just
5542 removing the optional pseudo is dangerous as the original
5543 pseudo will have longer live range. */
5544 || reg_renumber
[lra_reg_info
[regno
].restore_regno
] >= 0)
5546 else if (reg_renumber
[regno
] >= 0)
5547 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi2
)
5549 insn
= lra_insn_recog_data
[uid
]->insn
;
5550 if ((set
= single_set (insn
)) == NULL_RTX
)
5552 src
= SET_SRC (set
);
5553 dest
= SET_DEST (set
);
5554 if (! REG_P (src
) || ! REG_P (dest
))
5556 if (REGNO (dest
) == regno
5557 /* Ignore insn for optional reloads itself. */
5558 && lra_reg_info
[regno
].restore_regno
!= (int) REGNO (src
)
5559 /* Check only inheritance on last inheritance pass. */
5560 && (int) REGNO (src
) >= new_regno_start
5561 /* Check that the optional reload was inherited. */
5562 && bitmap_bit_p (&lra_inheritance_pseudos
, REGNO (src
)))
5570 bitmap_clear_bit (&removed_optional_reload_pseudos
, regno
);
5571 if (lra_dump_file
!= NULL
)
5572 fprintf (lra_dump_file
, "Keep optional reload reg %d\n", regno
);
5575 change_p
= ! bitmap_empty_p (&removed_optional_reload_pseudos
);
5576 bitmap_initialize (&insn_bitmap
, ®_obstack
);
5577 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos
, 0, regno
, bi
)
5579 if (lra_dump_file
!= NULL
)
5580 fprintf (lra_dump_file
, "Remove optional reload reg %d\n", regno
);
5581 bitmap_copy (&insn_bitmap
, &lra_reg_info
[regno
].insn_bitmap
);
5582 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap
, 0, uid
, bi2
)
5584 insn
= lra_insn_recog_data
[uid
]->insn
;
5585 if ((set
= single_set (insn
)) != NULL_RTX
)
5587 src
= SET_SRC (set
);
5588 dest
= SET_DEST (set
);
5589 if (REG_P (src
) && REG_P (dest
)
5590 && ((REGNO (src
) == regno
5591 && (lra_reg_info
[regno
].restore_regno
5592 == (int) REGNO (dest
)))
5593 || (REGNO (dest
) == regno
5594 && (lra_reg_info
[regno
].restore_regno
5595 == (int) REGNO (src
)))))
5597 if (lra_dump_file
!= NULL
)
5599 fprintf (lra_dump_file
, " Deleting move %u\n",
5601 dump_insn_slim (lra_dump_file
, insn
);
5603 lra_set_insn_deleted (insn
);
5606 /* We should not worry about generation memory-memory
5607 moves here as if the corresponding inheritance did
5608 not work (inheritance pseudo did not get a hard reg),
5609 we remove the inheritance pseudo and the optional
5612 substitute_pseudo (&insn
, regno
,
5613 regno_reg_rtx
[lra_reg_info
[regno
].restore_regno
]);
5614 lra_update_insn_regno_info (insn
);
5615 if (lra_dump_file
!= NULL
)
5617 fprintf (lra_dump_file
,
5618 " Restoring original insn:\n");
5619 dump_insn_slim (lra_dump_file
, insn
);
5623 /* Clear restore_regnos. */
5624 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos
, 0, regno
, bi
)
5625 lra_reg_info
[regno
].restore_regno
= -1;
5626 bitmap_clear (&insn_bitmap
);
5627 bitmap_clear (&removed_optional_reload_pseudos
);
5631 /* Entry function for undoing inheritance/split transformation. Return true
5632 if we did any RTL change in this pass. */
5634 lra_undo_inheritance (void)
5637 int restore_regno
, hard_regno
;
5638 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
5639 bitmap_head remove_pseudos
;
5643 lra_undo_inheritance_iter
++;
5644 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
5646 if (lra_dump_file
!= NULL
)
5647 fprintf (lra_dump_file
,
5648 "\n********** Undoing inheritance #%d: **********\n\n",
5649 lra_undo_inheritance_iter
);
5650 bitmap_initialize (&remove_pseudos
, ®_obstack
);
5651 n_inherit
= n_all_inherit
= 0;
5652 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5653 if (lra_reg_info
[regno
].restore_regno
>= 0)
5656 if (reg_renumber
[regno
] < 0
5657 /* If the original pseudo changed its allocation, just
5658 removing inheritance is dangerous as for changing
5659 allocation we used shorter live-ranges. */
5660 && reg_renumber
[lra_reg_info
[regno
].restore_regno
] < 0)
5661 bitmap_set_bit (&remove_pseudos
, regno
);
5665 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
5666 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
5667 n_inherit
, n_all_inherit
,
5668 (double) n_inherit
/ n_all_inherit
* 100);
5669 n_split
= n_all_split
= 0;
5670 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5671 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
5674 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
5675 ? reg_renumber
[restore_regno
] : restore_regno
);
5676 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
5677 bitmap_set_bit (&remove_pseudos
, regno
);
5681 if (lra_dump_file
!= NULL
)
5682 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
5683 regno
, restore_regno
);
5686 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
5687 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
5688 n_split
, n_all_split
,
5689 (double) n_split
/ n_all_split
* 100);
5690 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
5691 bitmap_clear (&remove_pseudos
);
5692 /* Clear restore_regnos. */
5693 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5694 lra_reg_info
[regno
].restore_regno
= -1;
5695 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5696 lra_reg_info
[regno
].restore_regno
= -1;
5697 change_p
= undo_optional_reloads () || change_p
;