2014-07-12 Paul Thomas <pault@gcc.gnu.org>
[official-gcc.git] / gcc / sel-sched.c
blob416e91725e84846504c3f8223124bf92e62c5cdb
1 /* Instruction scheduling pass. Selective scheduler and pipeliner.
2 Copyright (C) 2006-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "tm.h"
24 #include "rtl-error.h"
25 #include "tm_p.h"
26 #include "hard-reg-set.h"
27 #include "regs.h"
28 #include "function.h"
29 #include "flags.h"
30 #include "insn-config.h"
31 #include "insn-attr.h"
32 #include "except.h"
33 #include "recog.h"
34 #include "params.h"
35 #include "target.h"
36 #include "output.h"
37 #include "sched-int.h"
38 #include "ggc.h"
39 #include "tree.h"
40 #include "vec.h"
41 #include "langhooks.h"
42 #include "rtlhooks-def.h"
43 #include "emit-rtl.h"
44 #include "ira.h"
46 #ifdef INSN_SCHEDULING
47 #include "sel-sched-ir.h"
48 #include "sel-sched-dump.h"
49 #include "sel-sched.h"
50 #include "dbgcnt.h"
52 /* Implementation of selective scheduling approach.
53 The below implementation follows the original approach with the following
54 changes:
56 o the scheduler works after register allocation (but can be also tuned
57 to work before RA);
58 o some instructions are not copied or register renamed;
59 o conditional jumps are not moved with code duplication;
60 o several jumps in one parallel group are not supported;
61 o when pipelining outer loops, code motion through inner loops
62 is not supported;
63 o control and data speculation are supported;
64 o some improvements for better compile time/performance were made.
66 Terminology
67 ===========
69 A vinsn, or virtual insn, is an insn with additional data characterizing
70 insn pattern, such as LHS, RHS, register sets used/set/clobbered, etc.
71 Vinsns also act as smart pointers to save memory by reusing them in
72 different expressions. A vinsn is described by vinsn_t type.
74 An expression is a vinsn with additional data characterizing its properties
75 at some point in the control flow graph. The data may be its usefulness,
76 priority, speculative status, whether it was renamed/subsituted, etc.
77 An expression is described by expr_t type.
79 Availability set (av_set) is a set of expressions at a given control flow
80 point. It is represented as av_set_t. The expressions in av sets are kept
81 sorted in the terms of expr_greater_p function. It allows to truncate
82 the set while leaving the best expressions.
84 A fence is a point through which code motion is prohibited. On each step,
85 we gather a parallel group of insns at a fence. It is possible to have
86 multiple fences. A fence is represented via fence_t.
88 A boundary is the border between the fence group and the rest of the code.
89 Currently, we never have more than one boundary per fence, as we finalize
90 the fence group when a jump is scheduled. A boundary is represented
91 via bnd_t.
93 High-level overview
94 ===================
96 The scheduler finds regions to schedule, schedules each one, and finalizes.
97 The regions are formed starting from innermost loops, so that when the inner
98 loop is pipelined, its prologue can be scheduled together with yet unprocessed
99 outer loop. The rest of acyclic regions are found using extend_rgns:
100 the blocks that are not yet allocated to any regions are traversed in top-down
101 order, and a block is added to a region to which all its predecessors belong;
102 otherwise, the block starts its own region.
104 The main scheduling loop (sel_sched_region_2) consists of just
105 scheduling on each fence and updating fences. For each fence,
106 we fill a parallel group of insns (fill_insns) until some insns can be added.
107 First, we compute available exprs (av-set) at the boundary of the current
108 group. Second, we choose the best expression from it. If the stall is
109 required to schedule any of the expressions, we advance the current cycle
110 appropriately. So, the final group does not exactly correspond to a VLIW
111 word. Third, we move the chosen expression to the boundary (move_op)
112 and update the intermediate av sets and liveness sets. We quit fill_insns
113 when either no insns left for scheduling or we have scheduled enough insns
114 so we feel like advancing a scheduling point.
116 Computing available expressions
117 ===============================
119 The computation (compute_av_set) is a bottom-up traversal. At each insn,
120 we're moving the union of its successors' sets through it via
121 moveup_expr_set. The dependent expressions are removed. Local
122 transformations (substitution, speculation) are applied to move more
123 exprs. Then the expr corresponding to the current insn is added.
124 The result is saved on each basic block header.
126 When traversing the CFG, we're moving down for no more than max_ws insns.
127 Also, we do not move down to ineligible successors (is_ineligible_successor),
128 which include moving along a back-edge, moving to already scheduled code,
129 and moving to another fence. The first two restrictions are lifted during
130 pipelining, which allows us to move insns along a back-edge. We always have
131 an acyclic region for scheduling because we forbid motion through fences.
133 Choosing the best expression
134 ============================
136 We sort the final availability set via sel_rank_for_schedule, then we remove
137 expressions which are not yet ready (tick_check_p) or which dest registers
138 cannot be used. For some of them, we choose another register via
139 find_best_reg. To do this, we run find_used_regs to calculate the set of
140 registers which cannot be used. The find_used_regs function performs
141 a traversal of code motion paths for an expr. We consider for renaming
142 only registers which are from the same regclass as the original one and
143 using which does not interfere with any live ranges. Finally, we convert
144 the resulting set to the ready list format and use max_issue and reorder*
145 hooks similarly to the Haifa scheduler.
147 Scheduling the best expression
148 ==============================
150 We run the move_op routine to perform the same type of code motion paths
151 traversal as in find_used_regs. (These are working via the same driver,
152 code_motion_path_driver.) When moving down the CFG, we look for original
153 instruction that gave birth to a chosen expression. We undo
154 the transformations performed on an expression via the history saved in it.
155 When found, we remove the instruction or leave a reg-reg copy/speculation
156 check if needed. On a way up, we insert bookkeeping copies at each join
157 point. If a copy is not needed, it will be removed later during this
158 traversal. We update the saved av sets and liveness sets on the way up, too.
160 Finalizing the schedule
161 =======================
163 When pipelining, we reschedule the blocks from which insns were pipelined
164 to get a tighter schedule. On Itanium, we also perform bundling via
165 the same routine from ia64.c.
167 Dependence analysis changes
168 ===========================
170 We augmented the sched-deps.c with hooks that get called when a particular
171 dependence is found in a particular part of an insn. Using these hooks, we
172 can do several actions such as: determine whether an insn can be moved through
173 another (has_dependence_p, moveup_expr); find out whether an insn can be
174 scheduled on the current cycle (tick_check_p); find out registers that
175 are set/used/clobbered by an insn and find out all the strange stuff that
176 restrict its movement, like SCHED_GROUP_P or CANT_MOVE (done in
177 init_global_and_expr_for_insn).
179 Initialization changes
180 ======================
182 There are parts of haifa-sched.c, sched-deps.c, and sched-rgn.c that are
183 reused in all of the schedulers. We have split up the initialization of data
184 of such parts into different functions prefixed with scheduler type and
185 postfixed with the type of data initialized: {,sel_,haifa_}sched_{init,finish},
186 sched_rgn_init/finish, sched_deps_init/finish, sched_init_{luids/bbs}, etc.
187 The same splitting is done with current_sched_info structure:
188 dependence-related parts are in sched_deps_info, common part is in
189 common_sched_info, and haifa/sel/etc part is in current_sched_info.
191 Target contexts
192 ===============
194 As we now have multiple-point scheduling, this would not work with backends
195 which save some of the scheduler state to use it in the target hooks.
196 For this purpose, we introduce a concept of target contexts, which
197 encapsulate such information. The backend should implement simple routines
198 of allocating/freeing/setting such a context. The scheduler calls these
199 as target hooks and handles the target context as an opaque pointer (similar
200 to the DFA state type, state_t).
202 Various speedups
203 ================
205 As the correct data dependence graph is not supported during scheduling (which
206 is to be changed in mid-term), we cache as much of the dependence analysis
207 results as possible to avoid reanalyzing. This includes: bitmap caches on
208 each insn in stream of the region saying yes/no for a query with a pair of
209 UIDs; hashtables with the previously done transformations on each insn in
210 stream; a vector keeping a history of transformations on each expr.
212 Also, we try to minimize the dependence context used on each fence to check
213 whether the given expression is ready for scheduling by removing from it
214 insns that are definitely completed the execution. The results of
215 tick_check_p checks are also cached in a vector on each fence.
217 We keep a valid liveness set on each insn in a region to avoid the high
218 cost of recomputation on large basic blocks.
220 Finally, we try to minimize the number of needed updates to the availability
221 sets. The updates happen in two cases: when fill_insns terminates,
222 we advance all fences and increase the stage number to show that the region
223 has changed and the sets are to be recomputed; and when the next iteration
224 of a loop in fill_insns happens (but this one reuses the saved av sets
225 on bb headers.) Thus, we try to break the fill_insns loop only when
226 "significant" number of insns from the current scheduling window was
227 scheduled. This should be made a target param.
230 TODO: correctly support the data dependence graph at all stages and get rid
231 of all caches. This should speed up the scheduler.
232 TODO: implement moving cond jumps with bookkeeping copies on both targets.
233 TODO: tune the scheduler before RA so it does not create too much pseudos.
236 References:
237 S.-M. Moon and K. Ebcioglu. Parallelizing nonnumerical code with
238 selective scheduling and software pipelining.
239 ACM TOPLAS, Vol 19, No. 6, pages 853--898, Nov. 1997.
241 Andrey Belevantsev, Maxim Kuvyrkov, Vladimir Makarov, Dmitry Melnik,
242 and Dmitry Zhurikhin. An interblock VLIW-targeted instruction scheduler
243 for GCC. In Proceedings of GCC Developers' Summit 2006.
245 Arutyun Avetisyan, Andrey Belevantsev, and Dmitry Melnik. GCC Instruction
246 Scheduler and Software Pipeliner on the Itanium Platform. EPIC-7 Workshop.
247 http://rogue.colorado.edu/EPIC7/.
251 /* True when pipelining is enabled. */
252 bool pipelining_p;
254 /* True if bookkeeping is enabled. */
255 bool bookkeeping_p;
257 /* Maximum number of insns that are eligible for renaming. */
258 int max_insns_to_rename;
261 /* Definitions of local types and macros. */
263 /* Represents possible outcomes of moving an expression through an insn. */
264 enum MOVEUP_EXPR_CODE
266 /* The expression is not changed. */
267 MOVEUP_EXPR_SAME,
269 /* Not changed, but requires a new destination register. */
270 MOVEUP_EXPR_AS_RHS,
272 /* Cannot be moved. */
273 MOVEUP_EXPR_NULL,
275 /* Changed (substituted or speculated). */
276 MOVEUP_EXPR_CHANGED
279 /* The container to be passed into rtx search & replace functions. */
280 struct rtx_search_arg
282 /* What we are searching for. */
283 rtx x;
285 /* The occurrence counter. */
286 int n;
289 typedef struct rtx_search_arg *rtx_search_arg_p;
291 /* This struct contains precomputed hard reg sets that are needed when
292 computing registers available for renaming. */
293 struct hard_regs_data
295 /* For every mode, this stores registers available for use with
296 that mode. */
297 HARD_REG_SET regs_for_mode[NUM_MACHINE_MODES];
299 /* True when regs_for_mode[mode] is initialized. */
300 bool regs_for_mode_ok[NUM_MACHINE_MODES];
302 /* For every register, it has regs that are ok to rename into it.
303 The register in question is always set. If not, this means
304 that the whole set is not computed yet. */
305 HARD_REG_SET regs_for_rename[FIRST_PSEUDO_REGISTER];
307 /* For every mode, this stores registers not available due to
308 call clobbering. */
309 HARD_REG_SET regs_for_call_clobbered[NUM_MACHINE_MODES];
311 /* All registers that are used or call used. */
312 HARD_REG_SET regs_ever_used;
314 #ifdef STACK_REGS
315 /* Stack registers. */
316 HARD_REG_SET stack_regs;
317 #endif
320 /* Holds the results of computation of available for renaming and
321 unavailable hard registers. */
322 struct reg_rename
324 /* These are unavailable due to calls crossing, globalness, etc. */
325 HARD_REG_SET unavailable_hard_regs;
327 /* These are *available* for renaming. */
328 HARD_REG_SET available_for_renaming;
330 /* Whether this code motion path crosses a call. */
331 bool crosses_call;
334 /* A global structure that contains the needed information about harg
335 regs. */
336 static struct hard_regs_data sel_hrd;
339 /* This structure holds local data used in code_motion_path_driver hooks on
340 the same or adjacent levels of recursion. Here we keep those parameters
341 that are not used in code_motion_path_driver routine itself, but only in
342 its hooks. Moreover, all parameters that can be modified in hooks are
343 in this structure, so all other parameters passed explicitly to hooks are
344 read-only. */
345 struct cmpd_local_params
347 /* Local params used in move_op_* functions. */
349 /* Edges for bookkeeping generation. */
350 edge e1, e2;
352 /* C_EXPR merged from all successors and locally allocated temporary C_EXPR. */
353 expr_t c_expr_merged, c_expr_local;
355 /* Local params used in fur_* functions. */
356 /* Copy of the ORIGINAL_INSN list, stores the original insns already
357 found before entering the current level of code_motion_path_driver. */
358 def_list_t old_original_insns;
360 /* Local params used in move_op_* functions. */
361 /* True when we have removed last insn in the block which was
362 also a boundary. Do not update anything or create bookkeeping copies. */
363 BOOL_BITFIELD removed_last_insn : 1;
366 /* Stores the static parameters for move_op_* calls. */
367 struct moveop_static_params
369 /* Destination register. */
370 rtx dest;
372 /* Current C_EXPR. */
373 expr_t c_expr;
375 /* An UID of expr_vliw which is to be moved up. If we find other exprs,
376 they are to be removed. */
377 int uid;
379 #ifdef ENABLE_CHECKING
380 /* This is initialized to the insn on which the driver stopped its traversal. */
381 insn_t failed_insn;
382 #endif
384 /* True if we scheduled an insn with different register. */
385 bool was_renamed;
388 /* Stores the static parameters for fur_* calls. */
389 struct fur_static_params
391 /* Set of registers unavailable on the code motion path. */
392 regset used_regs;
394 /* Pointer to the list of original insns definitions. */
395 def_list_t *original_insns;
397 /* True if a code motion path contains a CALL insn. */
398 bool crosses_call;
401 typedef struct fur_static_params *fur_static_params_p;
402 typedef struct cmpd_local_params *cmpd_local_params_p;
403 typedef struct moveop_static_params *moveop_static_params_p;
405 /* Set of hooks and parameters that determine behaviour specific to
406 move_op or find_used_regs functions. */
407 struct code_motion_path_driver_info_def
409 /* Called on enter to the basic block. */
410 int (*on_enter) (insn_t, cmpd_local_params_p, void *, bool);
412 /* Called when original expr is found. */
413 void (*orig_expr_found) (insn_t, expr_t, cmpd_local_params_p, void *);
415 /* Called while descending current basic block if current insn is not
416 the original EXPR we're searching for. */
417 bool (*orig_expr_not_found) (insn_t, av_set_t, void *);
419 /* Function to merge C_EXPRes from different successors. */
420 void (*merge_succs) (insn_t, insn_t, int, cmpd_local_params_p, void *);
422 /* Function to finalize merge from different successors and possibly
423 deallocate temporary data structures used for merging. */
424 void (*after_merge_succs) (cmpd_local_params_p, void *);
426 /* Called on the backward stage of recursion to do moveup_expr.
427 Used only with move_op_*. */
428 void (*ascend) (insn_t, void *);
430 /* Called on the ascending pass, before returning from the current basic
431 block or from the whole traversal. */
432 void (*at_first_insn) (insn_t, cmpd_local_params_p, void *);
434 /* When processing successors in move_op we need only descend into
435 SUCCS_NORMAL successors, while in find_used_regs we need SUCCS_ALL. */
436 int succ_flags;
438 /* The routine name to print in dumps ("move_op" of "find_used_regs"). */
439 const char *routine_name;
442 /* Global pointer to current hooks, either points to MOVE_OP_HOOKS or
443 FUR_HOOKS. */
444 struct code_motion_path_driver_info_def *code_motion_path_driver_info;
446 /* Set of hooks for performing move_op and find_used_regs routines with
447 code_motion_path_driver. */
448 extern struct code_motion_path_driver_info_def move_op_hooks, fur_hooks;
450 /* True if/when we want to emulate Haifa scheduler in the common code.
451 This is used in sched_rgn_local_init and in various places in
452 sched-deps.c. */
453 int sched_emulate_haifa_p;
455 /* GLOBAL_LEVEL is used to discard information stored in basic block headers
456 av_sets. Av_set of bb header is valid if its (bb header's) level is equal
457 to GLOBAL_LEVEL. And invalid if lesser. This is primarily used to advance
458 scheduling window. */
459 int global_level;
461 /* Current fences. */
462 flist_t fences;
464 /* True when separable insns should be scheduled as RHSes. */
465 static bool enable_schedule_as_rhs_p;
467 /* Used in verify_target_availability to assert that target reg is reported
468 unavailabile by both TARGET_UNAVAILABLE and find_used_regs only if
469 we haven't scheduled anything on the previous fence.
470 if scheduled_something_on_previous_fence is true, TARGET_UNAVAILABLE can
471 have more conservative value than the one returned by the
472 find_used_regs, thus we shouldn't assert that these values are equal. */
473 static bool scheduled_something_on_previous_fence;
475 /* All newly emitted insns will have their uids greater than this value. */
476 static int first_emitted_uid;
478 /* Set of basic blocks that are forced to start new ebbs. This is a subset
479 of all the ebb heads. */
480 static bitmap_head _forced_ebb_heads;
481 bitmap_head *forced_ebb_heads = &_forced_ebb_heads;
483 /* Blocks that need to be rescheduled after pipelining. */
484 bitmap blocks_to_reschedule = NULL;
486 /* True when the first lv set should be ignored when updating liveness. */
487 static bool ignore_first = false;
489 /* Number of insns max_issue has initialized data structures for. */
490 static int max_issue_size = 0;
492 /* Whether we can issue more instructions. */
493 static int can_issue_more;
495 /* Maximum software lookahead window size, reduced when rescheduling after
496 pipelining. */
497 static int max_ws;
499 /* Number of insns scheduled in current region. */
500 static int num_insns_scheduled;
502 /* A vector of expressions is used to be able to sort them. */
503 static vec<expr_t> vec_av_set = vNULL;
505 /* A vector of vinsns is used to hold temporary lists of vinsns. */
506 typedef vec<vinsn_t> vinsn_vec_t;
508 /* This vector has the exprs which may still present in av_sets, but actually
509 can't be moved up due to bookkeeping created during code motion to another
510 fence. See comment near the call to update_and_record_unavailable_insns
511 for the detailed explanations. */
512 static vinsn_vec_t vec_bookkeeping_blocked_vinsns = vinsn_vec_t ();
514 /* This vector has vinsns which are scheduled with renaming on the first fence
515 and then seen on the second. For expressions with such vinsns, target
516 availability information may be wrong. */
517 static vinsn_vec_t vec_target_unavailable_vinsns = vinsn_vec_t ();
519 /* Vector to store temporary nops inserted in move_op to prevent removal
520 of empty bbs. */
521 static vec<insn_t> vec_temp_moveop_nops = vNULL;
523 /* These bitmaps record original instructions scheduled on the current
524 iteration and bookkeeping copies created by them. */
525 static bitmap current_originators = NULL;
526 static bitmap current_copies = NULL;
528 /* This bitmap marks the blocks visited by code_motion_path_driver so we don't
529 visit them afterwards. */
530 static bitmap code_motion_visited_blocks = NULL;
532 /* Variables to accumulate different statistics. */
534 /* The number of bookkeeping copies created. */
535 static int stat_bookkeeping_copies;
537 /* The number of insns that required bookkeeiping for their scheduling. */
538 static int stat_insns_needed_bookkeeping;
540 /* The number of insns that got renamed. */
541 static int stat_renamed_scheduled;
543 /* The number of substitutions made during scheduling. */
544 static int stat_substitutions_total;
547 /* Forward declarations of static functions. */
548 static bool rtx_ok_for_substitution_p (rtx, rtx);
549 static int sel_rank_for_schedule (const void *, const void *);
550 static av_set_t find_sequential_best_exprs (bnd_t, expr_t, bool);
551 static basic_block find_block_for_bookkeeping (edge e1, edge e2, bool lax);
553 static rtx get_dest_from_orig_ops (av_set_t);
554 static basic_block generate_bookkeeping_insn (expr_t, edge, edge);
555 static bool find_used_regs (insn_t, av_set_t, regset, struct reg_rename *,
556 def_list_t *);
557 static bool move_op (insn_t, av_set_t, expr_t, rtx, expr_t, bool*);
558 static int code_motion_path_driver (insn_t, av_set_t, ilist_t,
559 cmpd_local_params_p, void *);
560 static void sel_sched_region_1 (void);
561 static void sel_sched_region_2 (int);
562 static av_set_t compute_av_set_inside_bb (insn_t, ilist_t, int, bool);
564 static void debug_state (state_t);
567 /* Functions that work with fences. */
569 /* Advance one cycle on FENCE. */
570 static void
571 advance_one_cycle (fence_t fence)
573 unsigned i;
574 int cycle;
575 rtx insn;
577 advance_state (FENCE_STATE (fence));
578 cycle = ++FENCE_CYCLE (fence);
579 FENCE_ISSUED_INSNS (fence) = 0;
580 FENCE_STARTS_CYCLE_P (fence) = 1;
581 can_issue_more = issue_rate;
582 FENCE_ISSUE_MORE (fence) = can_issue_more;
584 for (i = 0; vec_safe_iterate (FENCE_EXECUTING_INSNS (fence), i, &insn); )
586 if (INSN_READY_CYCLE (insn) < cycle)
588 remove_from_deps (FENCE_DC (fence), insn);
589 FENCE_EXECUTING_INSNS (fence)->unordered_remove (i);
590 continue;
592 i++;
594 if (sched_verbose >= 2)
596 sel_print ("Finished a cycle. Current cycle = %d\n", FENCE_CYCLE (fence));
597 debug_state (FENCE_STATE (fence));
601 /* Returns true when SUCC in a fallthru bb of INSN, possibly
602 skipping empty basic blocks. */
603 static bool
604 in_fallthru_bb_p (rtx insn, rtx succ)
606 basic_block bb = BLOCK_FOR_INSN (insn);
607 edge e;
609 if (bb == BLOCK_FOR_INSN (succ))
610 return true;
612 e = find_fallthru_edge_from (bb);
613 if (e)
614 bb = e->dest;
615 else
616 return false;
618 while (sel_bb_empty_p (bb))
619 bb = bb->next_bb;
621 return bb == BLOCK_FOR_INSN (succ);
624 /* Construct successor fences from OLD_FENCEs and put them in NEW_FENCES.
625 When a successor will continue a ebb, transfer all parameters of a fence
626 to the new fence. ORIG_MAX_SEQNO is the maximal seqno before this round
627 of scheduling helping to distinguish between the old and the new code. */
628 static void
629 extract_new_fences_from (flist_t old_fences, flist_tail_t new_fences,
630 int orig_max_seqno)
632 bool was_here_p = false;
633 insn_t insn = NULL_RTX;
634 insn_t succ;
635 succ_iterator si;
636 ilist_iterator ii;
637 fence_t fence = FLIST_FENCE (old_fences);
638 basic_block bb;
640 /* Get the only element of FENCE_BNDS (fence). */
641 FOR_EACH_INSN (insn, ii, FENCE_BNDS (fence))
643 gcc_assert (!was_here_p);
644 was_here_p = true;
646 gcc_assert (was_here_p && insn != NULL_RTX);
648 /* When in the "middle" of the block, just move this fence
649 to the new list. */
650 bb = BLOCK_FOR_INSN (insn);
651 if (! sel_bb_end_p (insn)
652 || (single_succ_p (bb)
653 && single_pred_p (single_succ (bb))))
655 insn_t succ;
657 succ = (sel_bb_end_p (insn)
658 ? sel_bb_head (single_succ (bb))
659 : NEXT_INSN (insn));
661 if (INSN_SEQNO (succ) > 0
662 && INSN_SEQNO (succ) <= orig_max_seqno
663 && INSN_SCHED_TIMES (succ) <= 0)
665 FENCE_INSN (fence) = succ;
666 move_fence_to_fences (old_fences, new_fences);
668 if (sched_verbose >= 1)
669 sel_print ("Fence %d continues as %d[%d] (state continue)\n",
670 INSN_UID (insn), INSN_UID (succ), BLOCK_NUM (succ));
672 return;
675 /* Otherwise copy fence's structures to (possibly) multiple successors. */
676 FOR_EACH_SUCC_1 (succ, si, insn, SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
678 int seqno = INSN_SEQNO (succ);
680 if (0 < seqno && seqno <= orig_max_seqno
681 && (pipelining_p || INSN_SCHED_TIMES (succ) <= 0))
683 bool b = (in_same_ebb_p (insn, succ)
684 || in_fallthru_bb_p (insn, succ));
686 if (sched_verbose >= 1)
687 sel_print ("Fence %d continues as %d[%d] (state %s)\n",
688 INSN_UID (insn), INSN_UID (succ),
689 BLOCK_NUM (succ), b ? "continue" : "reset");
691 if (b)
692 add_dirty_fence_to_fences (new_fences, succ, fence);
693 else
695 /* Mark block of the SUCC as head of the new ebb. */
696 bitmap_set_bit (forced_ebb_heads, BLOCK_NUM (succ));
697 add_clean_fence_to_fences (new_fences, succ, fence);
704 /* Functions to support substitution. */
706 /* Returns whether INSN with dependence status DS is eligible for
707 substitution, i.e. it's a copy operation x := y, and RHS that is
708 moved up through this insn should be substituted. */
709 static bool
710 can_substitute_through_p (insn_t insn, ds_t ds)
712 /* We can substitute only true dependencies. */
713 if ((ds & DEP_OUTPUT)
714 || (ds & DEP_ANTI)
715 || ! INSN_RHS (insn)
716 || ! INSN_LHS (insn))
717 return false;
719 /* Now we just need to make sure the INSN_RHS consists of only one
720 simple REG rtx. */
721 if (REG_P (INSN_LHS (insn))
722 && REG_P (INSN_RHS (insn)))
723 return true;
724 return false;
727 /* Substitute all occurrences of INSN's destination in EXPR' vinsn with INSN's
728 source (if INSN is eligible for substitution). Returns TRUE if
729 substitution was actually performed, FALSE otherwise. Substitution might
730 be not performed because it's either EXPR' vinsn doesn't contain INSN's
731 destination or the resulting insn is invalid for the target machine.
732 When UNDO is true, perform unsubstitution instead (the difference is in
733 the part of rtx on which validate_replace_rtx is called). */
734 static bool
735 substitute_reg_in_expr (expr_t expr, insn_t insn, bool undo)
737 rtx *where;
738 bool new_insn_valid;
739 vinsn_t *vi = &EXPR_VINSN (expr);
740 bool has_rhs = VINSN_RHS (*vi) != NULL;
741 rtx old, new_rtx;
743 /* Do not try to replace in SET_DEST. Although we'll choose new
744 register for the RHS, we don't want to change RHS' original reg.
745 If the insn is not SET, we may still be able to substitute something
746 in it, and if we're here (don't have deps), it doesn't write INSN's
747 dest. */
748 where = (has_rhs
749 ? &VINSN_RHS (*vi)
750 : &PATTERN (VINSN_INSN_RTX (*vi)));
751 old = undo ? INSN_RHS (insn) : INSN_LHS (insn);
753 /* Substitute if INSN has a form of x:=y and LHS(INSN) occurs in *VI. */
754 if (rtx_ok_for_substitution_p (old, *where))
756 rtx new_insn;
757 rtx *where_replace;
759 /* We should copy these rtxes before substitution. */
760 new_rtx = copy_rtx (undo ? INSN_LHS (insn) : INSN_RHS (insn));
761 new_insn = create_copy_of_insn_rtx (VINSN_INSN_RTX (*vi));
763 /* Where we'll replace.
764 WHERE_REPLACE should point inside NEW_INSN, so INSN_RHS couldn't be
765 used instead of SET_SRC. */
766 where_replace = (has_rhs
767 ? &SET_SRC (PATTERN (new_insn))
768 : &PATTERN (new_insn));
770 new_insn_valid
771 = validate_replace_rtx_part_nosimplify (old, new_rtx, where_replace,
772 new_insn);
774 /* ??? Actually, constrain_operands result depends upon choice of
775 destination register. E.g. if we allow single register to be an rhs,
776 and if we try to move dx=ax(as rhs) through ax=dx, we'll result
777 in invalid insn dx=dx, so we'll loose this rhs here.
778 Just can't come up with significant testcase for this, so just
779 leaving it for now. */
780 if (new_insn_valid)
782 change_vinsn_in_expr (expr,
783 create_vinsn_from_insn_rtx (new_insn, false));
785 /* Do not allow clobbering the address register of speculative
786 insns. */
787 if ((EXPR_SPEC_DONE_DS (expr) & SPECULATIVE)
788 && register_unavailable_p (VINSN_REG_USES (EXPR_VINSN (expr)),
789 expr_dest_reg (expr)))
790 EXPR_TARGET_AVAILABLE (expr) = false;
792 return true;
794 else
795 return false;
797 else
798 return false;
801 /* Helper function for count_occurences_equiv. */
802 static int
803 count_occurrences_1 (rtx *cur_rtx, void *arg)
805 rtx_search_arg_p p = (rtx_search_arg_p) arg;
807 if (REG_P (*cur_rtx) && REGNO (*cur_rtx) == REGNO (p->x))
809 /* Bail out if mode is different or more than one register is used. */
810 if (GET_MODE (*cur_rtx) != GET_MODE (p->x)
811 || (HARD_REGISTER_P (*cur_rtx)
812 && hard_regno_nregs[REGNO (*cur_rtx)][GET_MODE (*cur_rtx)] > 1))
814 p->n = 0;
815 return 1;
818 p->n++;
820 /* Do not traverse subexprs. */
821 return -1;
824 if (GET_CODE (*cur_rtx) == SUBREG
825 && (!REG_P (SUBREG_REG (*cur_rtx))
826 || REGNO (SUBREG_REG (*cur_rtx)) == REGNO (p->x)))
828 /* ??? Do not support substituting regs inside subregs. In that case,
829 simplify_subreg will be called by validate_replace_rtx, and
830 unsubstitution will fail later. */
831 p->n = 0;
832 return 1;
835 /* Continue search. */
836 return 0;
839 /* Return the number of places WHAT appears within WHERE.
840 Bail out when we found a reference occupying several hard registers. */
841 static int
842 count_occurrences_equiv (rtx what, rtx where)
844 struct rtx_search_arg arg;
846 gcc_assert (REG_P (what));
847 arg.x = what;
848 arg.n = 0;
850 for_each_rtx (&where, &count_occurrences_1, (void *) &arg);
852 return arg.n;
855 /* Returns TRUE if WHAT is found in WHERE rtx tree. */
856 static bool
857 rtx_ok_for_substitution_p (rtx what, rtx where)
859 return (count_occurrences_equiv (what, where) > 0);
863 /* Functions to support register renaming. */
865 /* Substitute VI's set source with REGNO. Returns newly created pattern
866 that has REGNO as its source. */
867 static rtx
868 create_insn_rtx_with_rhs (vinsn_t vi, rtx rhs_rtx)
870 rtx lhs_rtx;
871 rtx pattern;
872 rtx insn_rtx;
874 lhs_rtx = copy_rtx (VINSN_LHS (vi));
876 pattern = gen_rtx_SET (VOIDmode, lhs_rtx, rhs_rtx);
877 insn_rtx = create_insn_rtx_from_pattern (pattern, NULL_RTX);
879 return insn_rtx;
882 /* Returns whether INSN's src can be replaced with register number
883 NEW_SRC_REG. E.g. the following insn is valid for i386:
885 (insn:HI 2205 6585 2207 727 ../../gcc/libiberty/regex.c:3337
886 (set (mem/s:QI (plus:SI (plus:SI (reg/f:SI 7 sp)
887 (reg:SI 0 ax [orig:770 c1 ] [770]))
888 (const_int 288 [0x120])) [0 str S1 A8])
889 (const_int 0 [0x0])) 43 {*movqi_1} (nil)
890 (nil))
892 But if we change (const_int 0 [0x0]) to (reg:QI 4 si), it will be invalid
893 because of operand constraints:
895 (define_insn "*movqi_1"
896 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
897 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn")
900 So do constrain_operands here, before choosing NEW_SRC_REG as best
901 reg for rhs. */
903 static bool
904 replace_src_with_reg_ok_p (insn_t insn, rtx new_src_reg)
906 vinsn_t vi = INSN_VINSN (insn);
907 enum machine_mode mode;
908 rtx dst_loc;
909 bool res;
911 gcc_assert (VINSN_SEPARABLE_P (vi));
913 get_dest_and_mode (insn, &dst_loc, &mode);
914 gcc_assert (mode == GET_MODE (new_src_reg));
916 if (REG_P (dst_loc) && REGNO (new_src_reg) == REGNO (dst_loc))
917 return true;
919 /* See whether SET_SRC can be replaced with this register. */
920 validate_change (insn, &SET_SRC (PATTERN (insn)), new_src_reg, 1);
921 res = verify_changes (0);
922 cancel_changes (0);
924 return res;
927 /* Returns whether INSN still be valid after replacing it's DEST with
928 register NEW_REG. */
929 static bool
930 replace_dest_with_reg_ok_p (insn_t insn, rtx new_reg)
932 vinsn_t vi = INSN_VINSN (insn);
933 bool res;
935 /* We should deal here only with separable insns. */
936 gcc_assert (VINSN_SEPARABLE_P (vi));
937 gcc_assert (GET_MODE (VINSN_LHS (vi)) == GET_MODE (new_reg));
939 /* See whether SET_DEST can be replaced with this register. */
940 validate_change (insn, &SET_DEST (PATTERN (insn)), new_reg, 1);
941 res = verify_changes (0);
942 cancel_changes (0);
944 return res;
947 /* Create a pattern with rhs of VI and lhs of LHS_RTX. */
948 static rtx
949 create_insn_rtx_with_lhs (vinsn_t vi, rtx lhs_rtx)
951 rtx rhs_rtx;
952 rtx pattern;
953 rtx insn_rtx;
955 rhs_rtx = copy_rtx (VINSN_RHS (vi));
957 pattern = gen_rtx_SET (VOIDmode, lhs_rtx, rhs_rtx);
958 insn_rtx = create_insn_rtx_from_pattern (pattern, NULL_RTX);
960 return insn_rtx;
963 /* Substitute lhs in the given expression EXPR for the register with number
964 NEW_REGNO. SET_DEST may be arbitrary rtx, not only register. */
965 static void
966 replace_dest_with_reg_in_expr (expr_t expr, rtx new_reg)
968 rtx insn_rtx;
969 vinsn_t vinsn;
971 insn_rtx = create_insn_rtx_with_lhs (EXPR_VINSN (expr), new_reg);
972 vinsn = create_vinsn_from_insn_rtx (insn_rtx, false);
974 change_vinsn_in_expr (expr, vinsn);
975 EXPR_WAS_RENAMED (expr) = 1;
976 EXPR_TARGET_AVAILABLE (expr) = 1;
979 /* Returns whether VI writes either one of the USED_REGS registers or,
980 if a register is a hard one, one of the UNAVAILABLE_HARD_REGS registers. */
981 static bool
982 vinsn_writes_one_of_regs_p (vinsn_t vi, regset used_regs,
983 HARD_REG_SET unavailable_hard_regs)
985 unsigned regno;
986 reg_set_iterator rsi;
988 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_SETS (vi), 0, regno, rsi)
990 if (REGNO_REG_SET_P (used_regs, regno))
991 return true;
992 if (HARD_REGISTER_NUM_P (regno)
993 && TEST_HARD_REG_BIT (unavailable_hard_regs, regno))
994 return true;
997 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_CLOBBERS (vi), 0, regno, rsi)
999 if (REGNO_REG_SET_P (used_regs, regno))
1000 return true;
1001 if (HARD_REGISTER_NUM_P (regno)
1002 && TEST_HARD_REG_BIT (unavailable_hard_regs, regno))
1003 return true;
1006 return false;
1009 /* Returns register class of the output register in INSN.
1010 Returns NO_REGS for call insns because some targets have constraints on
1011 destination register of a call insn.
1013 Code adopted from regrename.c::build_def_use. */
1014 static enum reg_class
1015 get_reg_class (rtx insn)
1017 int i, n_ops;
1019 extract_insn (insn);
1020 if (! constrain_operands (1))
1021 fatal_insn_not_found (insn);
1022 preprocess_constraints (insn);
1023 n_ops = recog_data.n_operands;
1025 const operand_alternative *op_alt = which_op_alt ();
1026 if (asm_noperands (PATTERN (insn)) > 0)
1028 for (i = 0; i < n_ops; i++)
1029 if (recog_data.operand_type[i] == OP_OUT)
1031 rtx *loc = recog_data.operand_loc[i];
1032 rtx op = *loc;
1033 enum reg_class cl = alternative_class (op_alt, i);
1035 if (REG_P (op)
1036 && REGNO (op) == ORIGINAL_REGNO (op))
1037 continue;
1039 return cl;
1042 else if (!CALL_P (insn))
1044 for (i = 0; i < n_ops + recog_data.n_dups; i++)
1046 int opn = i < n_ops ? i : recog_data.dup_num[i - n_ops];
1047 enum reg_class cl = alternative_class (op_alt, opn);
1049 if (recog_data.operand_type[opn] == OP_OUT ||
1050 recog_data.operand_type[opn] == OP_INOUT)
1051 return cl;
1055 /* Insns like
1056 (insn (set (reg:CCZ 17 flags) (compare:CCZ ...)))
1057 may result in returning NO_REGS, cause flags is written implicitly through
1058 CMP insn, which has no OP_OUT | OP_INOUT operands. */
1059 return NO_REGS;
1062 #ifdef HARD_REGNO_RENAME_OK
1063 /* Calculate HARD_REGNO_RENAME_OK data for REGNO. */
1064 static void
1065 init_hard_regno_rename (int regno)
1067 int cur_reg;
1069 SET_HARD_REG_BIT (sel_hrd.regs_for_rename[regno], regno);
1071 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1073 /* We are not interested in renaming in other regs. */
1074 if (!TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg))
1075 continue;
1077 if (HARD_REGNO_RENAME_OK (regno, cur_reg))
1078 SET_HARD_REG_BIT (sel_hrd.regs_for_rename[regno], cur_reg);
1081 #endif
1083 /* A wrapper around HARD_REGNO_RENAME_OK that will look into the hard regs
1084 data first. */
1085 static inline bool
1086 sel_hard_regno_rename_ok (int from ATTRIBUTE_UNUSED, int to ATTRIBUTE_UNUSED)
1088 #ifdef HARD_REGNO_RENAME_OK
1089 /* Check whether this is all calculated. */
1090 if (TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], from))
1091 return TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], to);
1093 init_hard_regno_rename (from);
1095 return TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], to);
1096 #else
1097 return true;
1098 #endif
1101 /* Calculate set of registers that are capable of holding MODE. */
1102 static void
1103 init_regs_for_mode (enum machine_mode mode)
1105 int cur_reg;
1107 CLEAR_HARD_REG_SET (sel_hrd.regs_for_mode[mode]);
1108 CLEAR_HARD_REG_SET (sel_hrd.regs_for_call_clobbered[mode]);
1110 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1112 int nregs;
1113 int i;
1115 /* See whether it accepts all modes that occur in
1116 original insns. */
1117 if (! HARD_REGNO_MODE_OK (cur_reg, mode))
1118 continue;
1120 nregs = hard_regno_nregs[cur_reg][mode];
1122 for (i = nregs - 1; i >= 0; --i)
1123 if (fixed_regs[cur_reg + i]
1124 || global_regs[cur_reg + i]
1125 /* Can't use regs which aren't saved by
1126 the prologue. */
1127 || !TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg + i)
1128 /* Can't use regs with non-null REG_BASE_VALUE, because adjusting
1129 it affects aliasing globally and invalidates all AV sets. */
1130 || get_reg_base_value (cur_reg + i)
1131 #ifdef LEAF_REGISTERS
1132 /* We can't use a non-leaf register if we're in a
1133 leaf function. */
1134 || (crtl->is_leaf
1135 && !LEAF_REGISTERS[cur_reg + i])
1136 #endif
1138 break;
1140 if (i >= 0)
1141 continue;
1143 if (HARD_REGNO_CALL_PART_CLOBBERED (cur_reg, mode))
1144 SET_HARD_REG_BIT (sel_hrd.regs_for_call_clobbered[mode],
1145 cur_reg);
1147 /* If the CUR_REG passed all the checks above,
1148 then it's ok. */
1149 SET_HARD_REG_BIT (sel_hrd.regs_for_mode[mode], cur_reg);
1152 sel_hrd.regs_for_mode_ok[mode] = true;
1155 /* Init all register sets gathered in HRD. */
1156 static void
1157 init_hard_regs_data (void)
1159 int cur_reg = 0;
1160 int cur_mode = 0;
1162 CLEAR_HARD_REG_SET (sel_hrd.regs_ever_used);
1163 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1164 if (df_regs_ever_live_p (cur_reg) || call_used_regs[cur_reg])
1165 SET_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg);
1167 /* Initialize registers that are valid based on mode when this is
1168 really needed. */
1169 for (cur_mode = 0; cur_mode < NUM_MACHINE_MODES; cur_mode++)
1170 sel_hrd.regs_for_mode_ok[cur_mode] = false;
1172 /* Mark that all HARD_REGNO_RENAME_OK is not calculated. */
1173 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1174 CLEAR_HARD_REG_SET (sel_hrd.regs_for_rename[cur_reg]);
1176 #ifdef STACK_REGS
1177 CLEAR_HARD_REG_SET (sel_hrd.stack_regs);
1179 for (cur_reg = FIRST_STACK_REG; cur_reg <= LAST_STACK_REG; cur_reg++)
1180 SET_HARD_REG_BIT (sel_hrd.stack_regs, cur_reg);
1181 #endif
1184 /* Mark hardware regs in REG_RENAME_P that are not suitable
1185 for renaming rhs in INSN due to hardware restrictions (register class,
1186 modes compatibility etc). This doesn't affect original insn's dest reg,
1187 if it isn't in USED_REGS. DEF is a definition insn of rhs for which the
1188 destination register is sought. LHS (DEF->ORIG_INSN) may be REG or MEM.
1189 Registers that are in used_regs are always marked in
1190 unavailable_hard_regs as well. */
1192 static void
1193 mark_unavailable_hard_regs (def_t def, struct reg_rename *reg_rename_p,
1194 regset used_regs ATTRIBUTE_UNUSED)
1196 enum machine_mode mode;
1197 enum reg_class cl = NO_REGS;
1198 rtx orig_dest;
1199 unsigned cur_reg, regno;
1200 hard_reg_set_iterator hrsi;
1202 gcc_assert (GET_CODE (PATTERN (def->orig_insn)) == SET);
1203 gcc_assert (reg_rename_p);
1205 orig_dest = SET_DEST (PATTERN (def->orig_insn));
1207 /* We have decided not to rename 'mem = something;' insns, as 'something'
1208 is usually a register. */
1209 if (!REG_P (orig_dest))
1210 return;
1212 regno = REGNO (orig_dest);
1214 /* If before reload, don't try to work with pseudos. */
1215 if (!reload_completed && !HARD_REGISTER_NUM_P (regno))
1216 return;
1218 if (reload_completed)
1219 cl = get_reg_class (def->orig_insn);
1221 /* Stop if the original register is one of the fixed_regs, global_regs or
1222 frame pointer, or we could not discover its class. */
1223 if (fixed_regs[regno]
1224 || global_regs[regno]
1225 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1226 || (frame_pointer_needed && regno == HARD_FRAME_POINTER_REGNUM)
1227 #else
1228 || (frame_pointer_needed && regno == FRAME_POINTER_REGNUM)
1229 #endif
1230 || (reload_completed && cl == NO_REGS))
1232 SET_HARD_REG_SET (reg_rename_p->unavailable_hard_regs);
1234 /* Give a chance for original register, if it isn't in used_regs. */
1235 if (!def->crosses_call)
1236 CLEAR_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs, regno);
1238 return;
1241 /* If something allocated on stack in this function, mark frame pointer
1242 register unavailable, considering also modes.
1243 FIXME: it is enough to do this once per all original defs. */
1244 if (frame_pointer_needed)
1246 add_to_hard_reg_set (&reg_rename_p->unavailable_hard_regs,
1247 Pmode, FRAME_POINTER_REGNUM);
1249 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER)
1250 add_to_hard_reg_set (&reg_rename_p->unavailable_hard_regs,
1251 Pmode, HARD_FRAME_POINTER_REGNUM);
1254 #ifdef STACK_REGS
1255 /* For the stack registers the presence of FIRST_STACK_REG in USED_REGS
1256 is equivalent to as if all stack regs were in this set.
1257 I.e. no stack register can be renamed, and even if it's an original
1258 register here we make sure it won't be lifted over it's previous def
1259 (it's previous def will appear as if it's a FIRST_STACK_REG def.
1260 The HARD_REGNO_RENAME_OK covers other cases in condition below. */
1261 if (IN_RANGE (REGNO (orig_dest), FIRST_STACK_REG, LAST_STACK_REG)
1262 && REGNO_REG_SET_P (used_regs, FIRST_STACK_REG))
1263 IOR_HARD_REG_SET (reg_rename_p->unavailable_hard_regs,
1264 sel_hrd.stack_regs);
1265 #endif
1267 /* If there's a call on this path, make regs from call_used_reg_set
1268 unavailable. */
1269 if (def->crosses_call)
1270 IOR_HARD_REG_SET (reg_rename_p->unavailable_hard_regs,
1271 call_used_reg_set);
1273 /* Stop here before reload: we need FRAME_REGS, STACK_REGS, and crosses_call,
1274 but not register classes. */
1275 if (!reload_completed)
1276 return;
1278 /* Leave regs as 'available' only from the current
1279 register class. */
1280 COPY_HARD_REG_SET (reg_rename_p->available_for_renaming,
1281 reg_class_contents[cl]);
1283 mode = GET_MODE (orig_dest);
1285 /* Leave only registers available for this mode. */
1286 if (!sel_hrd.regs_for_mode_ok[mode])
1287 init_regs_for_mode (mode);
1288 AND_HARD_REG_SET (reg_rename_p->available_for_renaming,
1289 sel_hrd.regs_for_mode[mode]);
1291 /* Exclude registers that are partially call clobbered. */
1292 if (def->crosses_call
1293 && ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))
1294 AND_COMPL_HARD_REG_SET (reg_rename_p->available_for_renaming,
1295 sel_hrd.regs_for_call_clobbered[mode]);
1297 /* Leave only those that are ok to rename. */
1298 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p->available_for_renaming,
1299 0, cur_reg, hrsi)
1301 int nregs;
1302 int i;
1304 nregs = hard_regno_nregs[cur_reg][mode];
1305 gcc_assert (nregs > 0);
1307 for (i = nregs - 1; i >= 0; --i)
1308 if (! sel_hard_regno_rename_ok (regno + i, cur_reg + i))
1309 break;
1311 if (i >= 0)
1312 CLEAR_HARD_REG_BIT (reg_rename_p->available_for_renaming,
1313 cur_reg);
1316 AND_COMPL_HARD_REG_SET (reg_rename_p->available_for_renaming,
1317 reg_rename_p->unavailable_hard_regs);
1319 /* Regno is always ok from the renaming part of view, but it really
1320 could be in *unavailable_hard_regs already, so set it here instead
1321 of there. */
1322 SET_HARD_REG_BIT (reg_rename_p->available_for_renaming, regno);
1325 /* reg_rename_tick[REG1] > reg_rename_tick[REG2] if REG1 was chosen as the
1326 best register more recently than REG2. */
1327 static int reg_rename_tick[FIRST_PSEUDO_REGISTER];
1329 /* Indicates the number of times renaming happened before the current one. */
1330 static int reg_rename_this_tick;
1332 /* Choose the register among free, that is suitable for storing
1333 the rhs value.
1335 ORIGINAL_INSNS is the list of insns where the operation (rhs)
1336 originally appears. There could be multiple original operations
1337 for single rhs since we moving it up and merging along different
1338 paths.
1340 Some code is adapted from regrename.c (regrename_optimize).
1341 If original register is available, function returns it.
1342 Otherwise it performs the checks, so the new register should
1343 comply with the following:
1344 - it should not violate any live ranges (such registers are in
1345 REG_RENAME_P->available_for_renaming set);
1346 - it should not be in the HARD_REGS_USED regset;
1347 - it should be in the class compatible with original uses;
1348 - it should not be clobbered through reference with different mode;
1349 - if we're in the leaf function, then the new register should
1350 not be in the LEAF_REGISTERS;
1351 - etc.
1353 If several registers meet the conditions, the register with smallest
1354 tick is returned to achieve more even register allocation.
1356 If original register seems to be ok, we set *IS_ORIG_REG_P_PTR to true.
1358 If no register satisfies the above conditions, NULL_RTX is returned. */
1359 static rtx
1360 choose_best_reg_1 (HARD_REG_SET hard_regs_used,
1361 struct reg_rename *reg_rename_p,
1362 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1364 int best_new_reg;
1365 unsigned cur_reg;
1366 enum machine_mode mode = VOIDmode;
1367 unsigned regno, i, n;
1368 hard_reg_set_iterator hrsi;
1369 def_list_iterator di;
1370 def_t def;
1372 /* If original register is available, return it. */
1373 *is_orig_reg_p_ptr = true;
1375 FOR_EACH_DEF (def, di, original_insns)
1377 rtx orig_dest = SET_DEST (PATTERN (def->orig_insn));
1379 gcc_assert (REG_P (orig_dest));
1381 /* Check that all original operations have the same mode.
1382 This is done for the next loop; if we'd return from this
1383 loop, we'd check only part of them, but in this case
1384 it doesn't matter. */
1385 if (mode == VOIDmode)
1386 mode = GET_MODE (orig_dest);
1387 gcc_assert (mode == GET_MODE (orig_dest));
1389 regno = REGNO (orig_dest);
1390 for (i = 0, n = hard_regno_nregs[regno][mode]; i < n; i++)
1391 if (TEST_HARD_REG_BIT (hard_regs_used, regno + i))
1392 break;
1394 /* All hard registers are available. */
1395 if (i == n)
1397 gcc_assert (mode != VOIDmode);
1399 /* Hard registers should not be shared. */
1400 return gen_rtx_REG (mode, regno);
1404 *is_orig_reg_p_ptr = false;
1405 best_new_reg = -1;
1407 /* Among all available regs choose the register that was
1408 allocated earliest. */
1409 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p->available_for_renaming,
1410 0, cur_reg, hrsi)
1411 if (! TEST_HARD_REG_BIT (hard_regs_used, cur_reg))
1413 /* Check that all hard regs for mode are available. */
1414 for (i = 1, n = hard_regno_nregs[cur_reg][mode]; i < n; i++)
1415 if (TEST_HARD_REG_BIT (hard_regs_used, cur_reg + i)
1416 || !TEST_HARD_REG_BIT (reg_rename_p->available_for_renaming,
1417 cur_reg + i))
1418 break;
1420 if (i < n)
1421 continue;
1423 /* All hard registers are available. */
1424 if (best_new_reg < 0
1425 || reg_rename_tick[cur_reg] < reg_rename_tick[best_new_reg])
1427 best_new_reg = cur_reg;
1429 /* Return immediately when we know there's no better reg. */
1430 if (! reg_rename_tick[best_new_reg])
1431 break;
1435 if (best_new_reg >= 0)
1437 /* Use the check from the above loop. */
1438 gcc_assert (mode != VOIDmode);
1439 return gen_rtx_REG (mode, best_new_reg);
1442 return NULL_RTX;
1445 /* A wrapper around choose_best_reg_1 () to verify that we make correct
1446 assumptions about available registers in the function. */
1447 static rtx
1448 choose_best_reg (HARD_REG_SET hard_regs_used, struct reg_rename *reg_rename_p,
1449 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1451 rtx best_reg = choose_best_reg_1 (hard_regs_used, reg_rename_p,
1452 original_insns, is_orig_reg_p_ptr);
1454 /* FIXME loop over hard_regno_nregs here. */
1455 gcc_assert (best_reg == NULL_RTX
1456 || TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, REGNO (best_reg)));
1458 return best_reg;
1461 /* Choose the pseudo register for storing rhs value. As this is supposed
1462 to work before reload, we return either the original register or make
1463 the new one. The parameters are the same that in choose_nest_reg_1
1464 functions, except that USED_REGS may contain pseudos.
1465 If we work with hard regs, check also REG_RENAME_P->UNAVAILABLE_HARD_REGS.
1467 TODO: take into account register pressure while doing this. Up to this
1468 moment, this function would never return NULL for pseudos, but we should
1469 not rely on this. */
1470 static rtx
1471 choose_best_pseudo_reg (regset used_regs,
1472 struct reg_rename *reg_rename_p,
1473 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1475 def_list_iterator i;
1476 def_t def;
1477 enum machine_mode mode = VOIDmode;
1478 bool bad_hard_regs = false;
1480 /* We should not use this after reload. */
1481 gcc_assert (!reload_completed);
1483 /* If original register is available, return it. */
1484 *is_orig_reg_p_ptr = true;
1486 FOR_EACH_DEF (def, i, original_insns)
1488 rtx dest = SET_DEST (PATTERN (def->orig_insn));
1489 int orig_regno;
1491 gcc_assert (REG_P (dest));
1493 /* Check that all original operations have the same mode. */
1494 if (mode == VOIDmode)
1495 mode = GET_MODE (dest);
1496 else
1497 gcc_assert (mode == GET_MODE (dest));
1498 orig_regno = REGNO (dest);
1500 if (!REGNO_REG_SET_P (used_regs, orig_regno))
1502 if (orig_regno < FIRST_PSEUDO_REGISTER)
1504 gcc_assert (df_regs_ever_live_p (orig_regno));
1506 /* For hard registers, we have to check hardware imposed
1507 limitations (frame/stack registers, calls crossed). */
1508 if (!TEST_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs,
1509 orig_regno))
1511 /* Don't let register cross a call if it doesn't already
1512 cross one. This condition is written in accordance with
1513 that in sched-deps.c sched_analyze_reg(). */
1514 if (!reg_rename_p->crosses_call
1515 || REG_N_CALLS_CROSSED (orig_regno) > 0)
1516 return gen_rtx_REG (mode, orig_regno);
1519 bad_hard_regs = true;
1521 else
1522 return dest;
1526 *is_orig_reg_p_ptr = false;
1528 /* We had some original hard registers that couldn't be used.
1529 Those were likely special. Don't try to create a pseudo. */
1530 if (bad_hard_regs)
1531 return NULL_RTX;
1533 /* We haven't found a register from original operations. Get a new one.
1534 FIXME: control register pressure somehow. */
1536 rtx new_reg = gen_reg_rtx (mode);
1538 gcc_assert (mode != VOIDmode);
1540 max_regno = max_reg_num ();
1541 maybe_extend_reg_info_p ();
1542 REG_N_CALLS_CROSSED (REGNO (new_reg)) = reg_rename_p->crosses_call ? 1 : 0;
1544 return new_reg;
1548 /* True when target of EXPR is available due to EXPR_TARGET_AVAILABLE,
1549 USED_REGS and REG_RENAME_P->UNAVAILABLE_HARD_REGS. */
1550 static void
1551 verify_target_availability (expr_t expr, regset used_regs,
1552 struct reg_rename *reg_rename_p)
1554 unsigned n, i, regno;
1555 enum machine_mode mode;
1556 bool target_available, live_available, hard_available;
1558 if (!REG_P (EXPR_LHS (expr)) || EXPR_TARGET_AVAILABLE (expr) < 0)
1559 return;
1561 regno = expr_dest_regno (expr);
1562 mode = GET_MODE (EXPR_LHS (expr));
1563 target_available = EXPR_TARGET_AVAILABLE (expr) == 1;
1564 n = HARD_REGISTER_NUM_P (regno) ? hard_regno_nregs[regno][mode] : 1;
1566 live_available = hard_available = true;
1567 for (i = 0; i < n; i++)
1569 if (bitmap_bit_p (used_regs, regno + i))
1570 live_available = false;
1571 if (TEST_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs, regno + i))
1572 hard_available = false;
1575 /* When target is not available, it may be due to hard register
1576 restrictions, e.g. crosses calls, so we check hard_available too. */
1577 if (target_available)
1578 gcc_assert (live_available);
1579 else
1580 /* Check only if we haven't scheduled something on the previous fence,
1581 cause due to MAX_SOFTWARE_LOOKAHEAD_WINDOW_SIZE issues
1582 and having more than one fence, we may end having targ_un in a block
1583 in which successors target register is actually available.
1585 The last condition handles the case when a dependence from a call insn
1586 was created in sched-deps.c for insns with destination registers that
1587 never crossed a call before, but do cross one after our code motion.
1589 FIXME: in the latter case, we just uselessly called find_used_regs,
1590 because we can't move this expression with any other register
1591 as well. */
1592 gcc_assert (scheduled_something_on_previous_fence || !live_available
1593 || !hard_available
1594 || (!reload_completed && reg_rename_p->crosses_call
1595 && REG_N_CALLS_CROSSED (regno) == 0));
1598 /* Collect unavailable registers due to liveness for EXPR from BNDS
1599 into USED_REGS. Save additional information about available
1600 registers and unavailable due to hardware restriction registers
1601 into REG_RENAME_P structure. Save original insns into ORIGINAL_INSNS
1602 list. */
1603 static void
1604 collect_unavailable_regs_from_bnds (expr_t expr, blist_t bnds, regset used_regs,
1605 struct reg_rename *reg_rename_p,
1606 def_list_t *original_insns)
1608 for (; bnds; bnds = BLIST_NEXT (bnds))
1610 bool res;
1611 av_set_t orig_ops = NULL;
1612 bnd_t bnd = BLIST_BND (bnds);
1614 /* If the chosen best expr doesn't belong to current boundary,
1615 skip it. */
1616 if (!av_set_is_in_p (BND_AV1 (bnd), EXPR_VINSN (expr)))
1617 continue;
1619 /* Put in ORIG_OPS all exprs from this boundary that became
1620 RES on top. */
1621 orig_ops = find_sequential_best_exprs (bnd, expr, false);
1623 /* Compute used regs and OR it into the USED_REGS. */
1624 res = find_used_regs (BND_TO (bnd), orig_ops, used_regs,
1625 reg_rename_p, original_insns);
1627 /* FIXME: the assert is true until we'd have several boundaries. */
1628 gcc_assert (res);
1629 av_set_clear (&orig_ops);
1633 /* Return TRUE if it is possible to replace LHSes of ORIG_INSNS with BEST_REG.
1634 If BEST_REG is valid, replace LHS of EXPR with it. */
1635 static bool
1636 try_replace_dest_reg (ilist_t orig_insns, rtx best_reg, expr_t expr)
1638 /* Try whether we'll be able to generate the insn
1639 'dest := best_reg' at the place of the original operation. */
1640 for (; orig_insns; orig_insns = ILIST_NEXT (orig_insns))
1642 insn_t orig_insn = DEF_LIST_DEF (orig_insns)->orig_insn;
1644 gcc_assert (EXPR_SEPARABLE_P (INSN_EXPR (orig_insn)));
1646 if (REGNO (best_reg) != REGNO (INSN_LHS (orig_insn))
1647 && (! replace_src_with_reg_ok_p (orig_insn, best_reg)
1648 || ! replace_dest_with_reg_ok_p (orig_insn, best_reg)))
1649 return false;
1652 /* Make sure that EXPR has the right destination
1653 register. */
1654 if (expr_dest_regno (expr) != REGNO (best_reg))
1655 replace_dest_with_reg_in_expr (expr, best_reg);
1656 else
1657 EXPR_TARGET_AVAILABLE (expr) = 1;
1659 return true;
1662 /* Select and assign best register to EXPR searching from BNDS.
1663 Set *IS_ORIG_REG_P to TRUE if original register was selected.
1664 Return FALSE if no register can be chosen, which could happen when:
1665 * EXPR_SEPARABLE_P is true but we were unable to find suitable register;
1666 * EXPR_SEPARABLE_P is false but the insn sets/clobbers one of the registers
1667 that are used on the moving path. */
1668 static bool
1669 find_best_reg_for_expr (expr_t expr, blist_t bnds, bool *is_orig_reg_p)
1671 static struct reg_rename reg_rename_data;
1673 regset used_regs;
1674 def_list_t original_insns = NULL;
1675 bool reg_ok;
1677 *is_orig_reg_p = false;
1679 /* Don't bother to do anything if this insn doesn't set any registers. */
1680 if (bitmap_empty_p (VINSN_REG_SETS (EXPR_VINSN (expr)))
1681 && bitmap_empty_p (VINSN_REG_CLOBBERS (EXPR_VINSN (expr))))
1682 return true;
1684 used_regs = get_clear_regset_from_pool ();
1685 CLEAR_HARD_REG_SET (reg_rename_data.unavailable_hard_regs);
1687 collect_unavailable_regs_from_bnds (expr, bnds, used_regs, &reg_rename_data,
1688 &original_insns);
1690 #ifdef ENABLE_CHECKING
1691 /* If after reload, make sure we're working with hard regs here. */
1692 if (reload_completed)
1694 reg_set_iterator rsi;
1695 unsigned i;
1697 EXECUTE_IF_SET_IN_REG_SET (used_regs, FIRST_PSEUDO_REGISTER, i, rsi)
1698 gcc_unreachable ();
1700 #endif
1702 if (EXPR_SEPARABLE_P (expr))
1704 rtx best_reg = NULL_RTX;
1705 /* Check that we have computed availability of a target register
1706 correctly. */
1707 verify_target_availability (expr, used_regs, &reg_rename_data);
1709 /* Turn everything in hard regs after reload. */
1710 if (reload_completed)
1712 HARD_REG_SET hard_regs_used;
1713 REG_SET_TO_HARD_REG_SET (hard_regs_used, used_regs);
1715 /* Join hard registers unavailable due to register class
1716 restrictions and live range intersection. */
1717 IOR_HARD_REG_SET (hard_regs_used,
1718 reg_rename_data.unavailable_hard_regs);
1720 best_reg = choose_best_reg (hard_regs_used, &reg_rename_data,
1721 original_insns, is_orig_reg_p);
1723 else
1724 best_reg = choose_best_pseudo_reg (used_regs, &reg_rename_data,
1725 original_insns, is_orig_reg_p);
1727 if (!best_reg)
1728 reg_ok = false;
1729 else if (*is_orig_reg_p)
1731 /* In case of unification BEST_REG may be different from EXPR's LHS
1732 when EXPR's LHS is unavailable, and there is another LHS among
1733 ORIGINAL_INSNS. */
1734 reg_ok = try_replace_dest_reg (original_insns, best_reg, expr);
1736 else
1738 /* Forbid renaming of low-cost insns. */
1739 if (sel_vinsn_cost (EXPR_VINSN (expr)) < 2)
1740 reg_ok = false;
1741 else
1742 reg_ok = try_replace_dest_reg (original_insns, best_reg, expr);
1745 else
1747 /* If !EXPR_SCHEDULE_AS_RHS (EXPR), just make sure INSN doesn't set
1748 any of the HARD_REGS_USED set. */
1749 if (vinsn_writes_one_of_regs_p (EXPR_VINSN (expr), used_regs,
1750 reg_rename_data.unavailable_hard_regs))
1752 reg_ok = false;
1753 gcc_assert (EXPR_TARGET_AVAILABLE (expr) <= 0);
1755 else
1757 reg_ok = true;
1758 gcc_assert (EXPR_TARGET_AVAILABLE (expr) != 0);
1762 ilist_clear (&original_insns);
1763 return_regset_to_pool (used_regs);
1765 return reg_ok;
1769 /* Return true if dependence described by DS can be overcomed. */
1770 static bool
1771 can_speculate_dep_p (ds_t ds)
1773 if (spec_info == NULL)
1774 return false;
1776 /* Leave only speculative data. */
1777 ds &= SPECULATIVE;
1779 if (ds == 0)
1780 return false;
1783 /* FIXME: make sched-deps.c produce only those non-hard dependencies,
1784 that we can overcome. */
1785 ds_t spec_mask = spec_info->mask;
1787 if ((ds & spec_mask) != ds)
1788 return false;
1791 if (ds_weak (ds) < spec_info->data_weakness_cutoff)
1792 return false;
1794 return true;
1797 /* Get a speculation check instruction.
1798 C_EXPR is a speculative expression,
1799 CHECK_DS describes speculations that should be checked,
1800 ORIG_INSN is the original non-speculative insn in the stream. */
1801 static insn_t
1802 create_speculation_check (expr_t c_expr, ds_t check_ds, insn_t orig_insn)
1804 rtx check_pattern;
1805 rtx insn_rtx;
1806 insn_t insn;
1807 basic_block recovery_block;
1808 rtx label;
1810 /* Create a recovery block if target is going to emit branchy check, or if
1811 ORIG_INSN was speculative already. */
1812 if (targetm.sched.needs_block_p (check_ds)
1813 || EXPR_SPEC_DONE_DS (INSN_EXPR (orig_insn)) != 0)
1815 recovery_block = sel_create_recovery_block (orig_insn);
1816 label = BB_HEAD (recovery_block);
1818 else
1820 recovery_block = NULL;
1821 label = NULL_RTX;
1824 /* Get pattern of the check. */
1825 check_pattern = targetm.sched.gen_spec_check (EXPR_INSN_RTX (c_expr), label,
1826 check_ds);
1828 gcc_assert (check_pattern != NULL);
1830 /* Emit check. */
1831 insn_rtx = create_insn_rtx_from_pattern (check_pattern, label);
1833 insn = sel_gen_insn_from_rtx_after (insn_rtx, INSN_EXPR (orig_insn),
1834 INSN_SEQNO (orig_insn), orig_insn);
1836 /* Make check to be non-speculative. */
1837 EXPR_SPEC_DONE_DS (INSN_EXPR (insn)) = 0;
1838 INSN_SPEC_CHECKED_DS (insn) = check_ds;
1840 /* Decrease priority of check by difference of load/check instruction
1841 latencies. */
1842 EXPR_PRIORITY (INSN_EXPR (insn)) -= (sel_vinsn_cost (INSN_VINSN (orig_insn))
1843 - sel_vinsn_cost (INSN_VINSN (insn)));
1845 /* Emit copy of original insn (though with replaced target register,
1846 if needed) to the recovery block. */
1847 if (recovery_block != NULL)
1849 rtx twin_rtx;
1851 twin_rtx = copy_rtx (PATTERN (EXPR_INSN_RTX (c_expr)));
1852 twin_rtx = create_insn_rtx_from_pattern (twin_rtx, NULL_RTX);
1853 sel_gen_recovery_insn_from_rtx_after (twin_rtx,
1854 INSN_EXPR (orig_insn),
1855 INSN_SEQNO (insn),
1856 bb_note (recovery_block));
1859 /* If we've generated a data speculation check, make sure
1860 that all the bookkeeping instruction we'll create during
1861 this move_op () will allocate an ALAT entry so that the
1862 check won't fail.
1863 In case of control speculation we must convert C_EXPR to control
1864 speculative mode, because failing to do so will bring us an exception
1865 thrown by the non-control-speculative load. */
1866 check_ds = ds_get_max_dep_weak (check_ds);
1867 speculate_expr (c_expr, check_ds);
1869 return insn;
1872 /* True when INSN is a "regN = regN" copy. */
1873 static bool
1874 identical_copy_p (rtx insn)
1876 rtx lhs, rhs, pat;
1878 pat = PATTERN (insn);
1880 if (GET_CODE (pat) != SET)
1881 return false;
1883 lhs = SET_DEST (pat);
1884 if (!REG_P (lhs))
1885 return false;
1887 rhs = SET_SRC (pat);
1888 if (!REG_P (rhs))
1889 return false;
1891 return REGNO (lhs) == REGNO (rhs);
1894 /* Undo all transformations on *AV_PTR that were done when
1895 moving through INSN. */
1896 static void
1897 undo_transformations (av_set_t *av_ptr, rtx insn)
1899 av_set_iterator av_iter;
1900 expr_t expr;
1901 av_set_t new_set = NULL;
1903 /* First, kill any EXPR that uses registers set by an insn. This is
1904 required for correctness. */
1905 FOR_EACH_EXPR_1 (expr, av_iter, av_ptr)
1906 if (!sched_insns_conditions_mutex_p (insn, EXPR_INSN_RTX (expr))
1907 && bitmap_intersect_p (INSN_REG_SETS (insn),
1908 VINSN_REG_USES (EXPR_VINSN (expr)))
1909 /* When an insn looks like 'r1 = r1', we could substitute through
1910 it, but the above condition will still hold. This happened with
1911 gcc.c-torture/execute/961125-1.c. */
1912 && !identical_copy_p (insn))
1914 if (sched_verbose >= 6)
1915 sel_print ("Expr %d removed due to use/set conflict\n",
1916 INSN_UID (EXPR_INSN_RTX (expr)));
1917 av_set_iter_remove (&av_iter);
1920 /* Undo transformations looking at the history vector. */
1921 FOR_EACH_EXPR (expr, av_iter, *av_ptr)
1923 int index = find_in_history_vect (EXPR_HISTORY_OF_CHANGES (expr),
1924 insn, EXPR_VINSN (expr), true);
1926 if (index >= 0)
1928 expr_history_def *phist;
1930 phist = &EXPR_HISTORY_OF_CHANGES (expr)[index];
1932 switch (phist->type)
1934 case TRANS_SPECULATION:
1936 ds_t old_ds, new_ds;
1938 /* Compute the difference between old and new speculative
1939 statuses: that's what we need to check.
1940 Earlier we used to assert that the status will really
1941 change. This no longer works because only the probability
1942 bits in the status may have changed during compute_av_set,
1943 and in the case of merging different probabilities of the
1944 same speculative status along different paths we do not
1945 record this in the history vector. */
1946 old_ds = phist->spec_ds;
1947 new_ds = EXPR_SPEC_DONE_DS (expr);
1949 old_ds &= SPECULATIVE;
1950 new_ds &= SPECULATIVE;
1951 new_ds &= ~old_ds;
1953 EXPR_SPEC_TO_CHECK_DS (expr) |= new_ds;
1954 break;
1956 case TRANS_SUBSTITUTION:
1958 expr_def _tmp_expr, *tmp_expr = &_tmp_expr;
1959 vinsn_t new_vi;
1960 bool add = true;
1962 new_vi = phist->old_expr_vinsn;
1964 gcc_assert (VINSN_SEPARABLE_P (new_vi)
1965 == EXPR_SEPARABLE_P (expr));
1966 copy_expr (tmp_expr, expr);
1968 if (vinsn_equal_p (phist->new_expr_vinsn,
1969 EXPR_VINSN (tmp_expr)))
1970 change_vinsn_in_expr (tmp_expr, new_vi);
1971 else
1972 /* This happens when we're unsubstituting on a bookkeeping
1973 copy, which was in turn substituted. The history is wrong
1974 in this case. Do it the hard way. */
1975 add = substitute_reg_in_expr (tmp_expr, insn, true);
1976 if (add)
1977 av_set_add (&new_set, tmp_expr);
1978 clear_expr (tmp_expr);
1979 break;
1981 default:
1982 gcc_unreachable ();
1988 av_set_union_and_clear (av_ptr, &new_set, NULL);
1992 /* Moveup_* helpers for code motion and computing av sets. */
1994 /* Propagates EXPR inside an insn group through THROUGH_INSN.
1995 The difference from the below function is that only substitution is
1996 performed. */
1997 static enum MOVEUP_EXPR_CODE
1998 moveup_expr_inside_insn_group (expr_t expr, insn_t through_insn)
2000 vinsn_t vi = EXPR_VINSN (expr);
2001 ds_t *has_dep_p;
2002 ds_t full_ds;
2004 /* Do this only inside insn group. */
2005 gcc_assert (INSN_SCHED_CYCLE (through_insn) > 0);
2007 full_ds = has_dependence_p (expr, through_insn, &has_dep_p);
2008 if (full_ds == 0)
2009 return MOVEUP_EXPR_SAME;
2011 /* Substitution is the possible choice in this case. */
2012 if (has_dep_p[DEPS_IN_RHS])
2014 /* Can't substitute UNIQUE VINSNs. */
2015 gcc_assert (!VINSN_UNIQUE_P (vi));
2017 if (can_substitute_through_p (through_insn,
2018 has_dep_p[DEPS_IN_RHS])
2019 && substitute_reg_in_expr (expr, through_insn, false))
2021 EXPR_WAS_SUBSTITUTED (expr) = true;
2022 return MOVEUP_EXPR_CHANGED;
2025 /* Don't care about this, as even true dependencies may be allowed
2026 in an insn group. */
2027 return MOVEUP_EXPR_SAME;
2030 /* This can catch output dependencies in COND_EXECs. */
2031 if (has_dep_p[DEPS_IN_INSN])
2032 return MOVEUP_EXPR_NULL;
2034 /* This is either an output or an anti dependence, which usually have
2035 a zero latency. Allow this here, if we'd be wrong, tick_check_p
2036 will fix this. */
2037 gcc_assert (has_dep_p[DEPS_IN_LHS]);
2038 return MOVEUP_EXPR_AS_RHS;
2041 /* True when a trapping EXPR cannot be moved through THROUGH_INSN. */
2042 #define CANT_MOVE_TRAPPING(expr, through_insn) \
2043 (VINSN_MAY_TRAP_P (EXPR_VINSN (expr)) \
2044 && !sel_insn_has_single_succ_p ((through_insn), SUCCS_ALL) \
2045 && !sel_insn_is_speculation_check (through_insn))
2047 /* True when a conflict on a target register was found during moveup_expr. */
2048 static bool was_target_conflict = false;
2050 /* Return true when moving a debug INSN across THROUGH_INSN will
2051 create a bookkeeping block. We don't want to create such blocks,
2052 for they would cause codegen differences between compilations with
2053 and without debug info. */
2055 static bool
2056 moving_insn_creates_bookkeeping_block_p (insn_t insn,
2057 insn_t through_insn)
2059 basic_block bbi, bbt;
2060 edge e1, e2;
2061 edge_iterator ei1, ei2;
2063 if (!bookkeeping_can_be_created_if_moved_through_p (through_insn))
2065 if (sched_verbose >= 9)
2066 sel_print ("no bookkeeping required: ");
2067 return FALSE;
2070 bbi = BLOCK_FOR_INSN (insn);
2072 if (EDGE_COUNT (bbi->preds) == 1)
2074 if (sched_verbose >= 9)
2075 sel_print ("only one pred edge: ");
2076 return TRUE;
2079 bbt = BLOCK_FOR_INSN (through_insn);
2081 FOR_EACH_EDGE (e1, ei1, bbt->succs)
2083 FOR_EACH_EDGE (e2, ei2, bbi->preds)
2085 if (find_block_for_bookkeeping (e1, e2, TRUE))
2087 if (sched_verbose >= 9)
2088 sel_print ("found existing block: ");
2089 return FALSE;
2094 if (sched_verbose >= 9)
2095 sel_print ("would create bookkeeping block: ");
2097 return TRUE;
2100 /* Return true when the conflict with newly created implicit clobbers
2101 between EXPR and THROUGH_INSN is found because of renaming. */
2102 static bool
2103 implicit_clobber_conflict_p (insn_t through_insn, expr_t expr)
2105 HARD_REG_SET temp;
2106 rtx insn, reg, rhs, pat;
2107 hard_reg_set_iterator hrsi;
2108 unsigned regno;
2109 bool valid;
2111 /* Make a new pseudo register. */
2112 reg = gen_reg_rtx (GET_MODE (EXPR_LHS (expr)));
2113 max_regno = max_reg_num ();
2114 maybe_extend_reg_info_p ();
2116 /* Validate a change and bail out early. */
2117 insn = EXPR_INSN_RTX (expr);
2118 validate_change (insn, &SET_DEST (PATTERN (insn)), reg, true);
2119 valid = verify_changes (0);
2120 cancel_changes (0);
2121 if (!valid)
2123 if (sched_verbose >= 6)
2124 sel_print ("implicit clobbers failed validation, ");
2125 return true;
2128 /* Make a new insn with it. */
2129 rhs = copy_rtx (VINSN_RHS (EXPR_VINSN (expr)));
2130 pat = gen_rtx_SET (VOIDmode, reg, rhs);
2131 start_sequence ();
2132 insn = emit_insn (pat);
2133 end_sequence ();
2135 /* Calculate implicit clobbers. */
2136 extract_insn (insn);
2137 preprocess_constraints (insn);
2138 ira_implicitly_set_insn_hard_regs (&temp);
2139 AND_COMPL_HARD_REG_SET (temp, ira_no_alloc_regs);
2141 /* If any implicit clobber registers intersect with regular ones in
2142 through_insn, we have a dependency and thus bail out. */
2143 EXECUTE_IF_SET_IN_HARD_REG_SET (temp, 0, regno, hrsi)
2145 vinsn_t vi = INSN_VINSN (through_insn);
2146 if (bitmap_bit_p (VINSN_REG_SETS (vi), regno)
2147 || bitmap_bit_p (VINSN_REG_CLOBBERS (vi), regno)
2148 || bitmap_bit_p (VINSN_REG_USES (vi), regno))
2149 return true;
2152 return false;
2155 /* Modifies EXPR so it can be moved through the THROUGH_INSN,
2156 performing necessary transformations. Record the type of transformation
2157 made in PTRANS_TYPE, when it is not NULL. When INSIDE_INSN_GROUP,
2158 permit all dependencies except true ones, and try to remove those
2159 too via forward substitution. All cases when a non-eliminable
2160 non-zero cost dependency exists inside an insn group will be fixed
2161 in tick_check_p instead. */
2162 static enum MOVEUP_EXPR_CODE
2163 moveup_expr (expr_t expr, insn_t through_insn, bool inside_insn_group,
2164 enum local_trans_type *ptrans_type)
2166 vinsn_t vi = EXPR_VINSN (expr);
2167 insn_t insn = VINSN_INSN_RTX (vi);
2168 bool was_changed = false;
2169 bool as_rhs = false;
2170 ds_t *has_dep_p;
2171 ds_t full_ds;
2173 /* ??? We use dependencies of non-debug insns on debug insns to
2174 indicate that the debug insns need to be reset if the non-debug
2175 insn is pulled ahead of it. It's hard to figure out how to
2176 introduce such a notion in sel-sched, but it already fails to
2177 support debug insns in other ways, so we just go ahead and
2178 let the deug insns go corrupt for now. */
2179 if (DEBUG_INSN_P (through_insn) && !DEBUG_INSN_P (insn))
2180 return MOVEUP_EXPR_SAME;
2182 /* When inside_insn_group, delegate to the helper. */
2183 if (inside_insn_group)
2184 return moveup_expr_inside_insn_group (expr, through_insn);
2186 /* Deal with unique insns and control dependencies. */
2187 if (VINSN_UNIQUE_P (vi))
2189 /* We can move jumps without side-effects or jumps that are
2190 mutually exclusive with instruction THROUGH_INSN (all in cases
2191 dependencies allow to do so and jump is not speculative). */
2192 if (control_flow_insn_p (insn))
2194 basic_block fallthru_bb;
2196 /* Do not move checks and do not move jumps through other
2197 jumps. */
2198 if (control_flow_insn_p (through_insn)
2199 || sel_insn_is_speculation_check (insn))
2200 return MOVEUP_EXPR_NULL;
2202 /* Don't move jumps through CFG joins. */
2203 if (bookkeeping_can_be_created_if_moved_through_p (through_insn))
2204 return MOVEUP_EXPR_NULL;
2206 /* The jump should have a clear fallthru block, and
2207 this block should be in the current region. */
2208 if ((fallthru_bb = fallthru_bb_of_jump (insn)) == NULL
2209 || ! in_current_region_p (fallthru_bb))
2210 return MOVEUP_EXPR_NULL;
2212 /* And it should be mutually exclusive with through_insn. */
2213 if (! sched_insns_conditions_mutex_p (insn, through_insn)
2214 && ! DEBUG_INSN_P (through_insn))
2215 return MOVEUP_EXPR_NULL;
2218 /* Don't move what we can't move. */
2219 if (EXPR_CANT_MOVE (expr)
2220 && BLOCK_FOR_INSN (through_insn) != BLOCK_FOR_INSN (insn))
2221 return MOVEUP_EXPR_NULL;
2223 /* Don't move SCHED_GROUP instruction through anything.
2224 If we don't force this, then it will be possible to start
2225 scheduling a sched_group before all its dependencies are
2226 resolved.
2227 ??? Haifa deals with this issue by delaying the SCHED_GROUP
2228 as late as possible through rank_for_schedule. */
2229 if (SCHED_GROUP_P (insn))
2230 return MOVEUP_EXPR_NULL;
2232 else
2233 gcc_assert (!control_flow_insn_p (insn));
2235 /* Don't move debug insns if this would require bookkeeping. */
2236 if (DEBUG_INSN_P (insn)
2237 && BLOCK_FOR_INSN (through_insn) != BLOCK_FOR_INSN (insn)
2238 && moving_insn_creates_bookkeeping_block_p (insn, through_insn))
2239 return MOVEUP_EXPR_NULL;
2241 /* Deal with data dependencies. */
2242 was_target_conflict = false;
2243 full_ds = has_dependence_p (expr, through_insn, &has_dep_p);
2244 if (full_ds == 0)
2246 if (!CANT_MOVE_TRAPPING (expr, through_insn))
2247 return MOVEUP_EXPR_SAME;
2249 else
2251 /* We can move UNIQUE insn up only as a whole and unchanged,
2252 so it shouldn't have any dependencies. */
2253 if (VINSN_UNIQUE_P (vi))
2254 return MOVEUP_EXPR_NULL;
2257 if (full_ds != 0 && can_speculate_dep_p (full_ds))
2259 int res;
2261 res = speculate_expr (expr, full_ds);
2262 if (res >= 0)
2264 /* Speculation was successful. */
2265 full_ds = 0;
2266 was_changed = (res > 0);
2267 if (res == 2)
2268 was_target_conflict = true;
2269 if (ptrans_type)
2270 *ptrans_type = TRANS_SPECULATION;
2271 sel_clear_has_dependence ();
2275 if (has_dep_p[DEPS_IN_INSN])
2276 /* We have some dependency that cannot be discarded. */
2277 return MOVEUP_EXPR_NULL;
2279 if (has_dep_p[DEPS_IN_LHS])
2281 /* Only separable insns can be moved up with the new register.
2282 Anyways, we should mark that the original register is
2283 unavailable. */
2284 if (!enable_schedule_as_rhs_p || !EXPR_SEPARABLE_P (expr))
2285 return MOVEUP_EXPR_NULL;
2287 /* When renaming a hard register to a pseudo before reload, extra
2288 dependencies can occur from the implicit clobbers of the insn.
2289 Filter out such cases here. */
2290 if (!reload_completed && REG_P (EXPR_LHS (expr))
2291 && HARD_REGISTER_P (EXPR_LHS (expr))
2292 && implicit_clobber_conflict_p (through_insn, expr))
2294 if (sched_verbose >= 6)
2295 sel_print ("implicit clobbers conflict detected, ");
2296 return MOVEUP_EXPR_NULL;
2298 EXPR_TARGET_AVAILABLE (expr) = false;
2299 was_target_conflict = true;
2300 as_rhs = true;
2303 /* At this point we have either separable insns, that will be lifted
2304 up only as RHSes, or non-separable insns with no dependency in lhs.
2305 If dependency is in RHS, then try to perform substitution and move up
2306 substituted RHS:
2308 Ex. 1: Ex.2
2309 y = x; y = x;
2310 z = y*2; y = y*2;
2312 In Ex.1 y*2 can be substituted for x*2 and the whole operation can be
2313 moved above y=x assignment as z=x*2.
2315 In Ex.2 y*2 also can be substituted for x*2, but only the right hand
2316 side can be moved because of the output dependency. The operation was
2317 cropped to its rhs above. */
2318 if (has_dep_p[DEPS_IN_RHS])
2320 ds_t *rhs_dsp = &has_dep_p[DEPS_IN_RHS];
2322 /* Can't substitute UNIQUE VINSNs. */
2323 gcc_assert (!VINSN_UNIQUE_P (vi));
2325 if (can_speculate_dep_p (*rhs_dsp))
2327 int res;
2329 res = speculate_expr (expr, *rhs_dsp);
2330 if (res >= 0)
2332 /* Speculation was successful. */
2333 *rhs_dsp = 0;
2334 was_changed = (res > 0);
2335 if (res == 2)
2336 was_target_conflict = true;
2337 if (ptrans_type)
2338 *ptrans_type = TRANS_SPECULATION;
2340 else
2341 return MOVEUP_EXPR_NULL;
2343 else if (can_substitute_through_p (through_insn,
2344 *rhs_dsp)
2345 && substitute_reg_in_expr (expr, through_insn, false))
2347 /* ??? We cannot perform substitution AND speculation on the same
2348 insn. */
2349 gcc_assert (!was_changed);
2350 was_changed = true;
2351 if (ptrans_type)
2352 *ptrans_type = TRANS_SUBSTITUTION;
2353 EXPR_WAS_SUBSTITUTED (expr) = true;
2355 else
2356 return MOVEUP_EXPR_NULL;
2359 /* Don't move trapping insns through jumps.
2360 This check should be at the end to give a chance to control speculation
2361 to perform its duties. */
2362 if (CANT_MOVE_TRAPPING (expr, through_insn))
2363 return MOVEUP_EXPR_NULL;
2365 return (was_changed
2366 ? MOVEUP_EXPR_CHANGED
2367 : (as_rhs
2368 ? MOVEUP_EXPR_AS_RHS
2369 : MOVEUP_EXPR_SAME));
2372 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2373 if successful. When INSIDE_INSN_GROUP, also try ignore dependencies
2374 that can exist within a parallel group. Write to RES the resulting
2375 code for moveup_expr. */
2376 static bool
2377 try_bitmap_cache (expr_t expr, insn_t insn,
2378 bool inside_insn_group,
2379 enum MOVEUP_EXPR_CODE *res)
2381 int expr_uid = INSN_UID (EXPR_INSN_RTX (expr));
2383 /* First check whether we've analyzed this situation already. */
2384 if (bitmap_bit_p (INSN_ANALYZED_DEPS (insn), expr_uid))
2386 if (bitmap_bit_p (INSN_FOUND_DEPS (insn), expr_uid))
2388 if (sched_verbose >= 6)
2389 sel_print ("removed (cached)\n");
2390 *res = MOVEUP_EXPR_NULL;
2391 return true;
2393 else
2395 if (sched_verbose >= 6)
2396 sel_print ("unchanged (cached)\n");
2397 *res = MOVEUP_EXPR_SAME;
2398 return true;
2401 else if (bitmap_bit_p (INSN_FOUND_DEPS (insn), expr_uid))
2403 if (inside_insn_group)
2405 if (sched_verbose >= 6)
2406 sel_print ("unchanged (as RHS, cached, inside insn group)\n");
2407 *res = MOVEUP_EXPR_SAME;
2408 return true;
2411 else
2412 EXPR_TARGET_AVAILABLE (expr) = false;
2414 /* This is the only case when propagation result can change over time,
2415 as we can dynamically switch off scheduling as RHS. In this case,
2416 just check the flag to reach the correct decision. */
2417 if (enable_schedule_as_rhs_p)
2419 if (sched_verbose >= 6)
2420 sel_print ("unchanged (as RHS, cached)\n");
2421 *res = MOVEUP_EXPR_AS_RHS;
2422 return true;
2424 else
2426 if (sched_verbose >= 6)
2427 sel_print ("removed (cached as RHS, but renaming"
2428 " is now disabled)\n");
2429 *res = MOVEUP_EXPR_NULL;
2430 return true;
2434 return false;
2437 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2438 if successful. Write to RES the resulting code for moveup_expr. */
2439 static bool
2440 try_transformation_cache (expr_t expr, insn_t insn,
2441 enum MOVEUP_EXPR_CODE *res)
2443 struct transformed_insns *pti
2444 = (struct transformed_insns *)
2445 htab_find_with_hash (INSN_TRANSFORMED_INSNS (insn),
2446 &EXPR_VINSN (expr),
2447 VINSN_HASH_RTX (EXPR_VINSN (expr)));
2448 if (pti)
2450 /* This EXPR was already moved through this insn and was
2451 changed as a result. Fetch the proper data from
2452 the hashtable. */
2453 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr),
2454 INSN_UID (insn), pti->type,
2455 pti->vinsn_old, pti->vinsn_new,
2456 EXPR_SPEC_DONE_DS (expr));
2458 if (INSN_IN_STREAM_P (VINSN_INSN_RTX (pti->vinsn_new)))
2459 pti->vinsn_new = vinsn_copy (pti->vinsn_new, true);
2460 change_vinsn_in_expr (expr, pti->vinsn_new);
2461 if (pti->was_target_conflict)
2462 EXPR_TARGET_AVAILABLE (expr) = false;
2463 if (pti->type == TRANS_SPECULATION)
2465 EXPR_SPEC_DONE_DS (expr) = pti->ds;
2466 EXPR_NEEDS_SPEC_CHECK_P (expr) |= pti->needs_check;
2469 if (sched_verbose >= 6)
2471 sel_print ("changed (cached): ");
2472 dump_expr (expr);
2473 sel_print ("\n");
2476 *res = MOVEUP_EXPR_CHANGED;
2477 return true;
2480 return false;
2483 /* Update bitmap caches on INSN with result RES of propagating EXPR. */
2484 static void
2485 update_bitmap_cache (expr_t expr, insn_t insn, bool inside_insn_group,
2486 enum MOVEUP_EXPR_CODE res)
2488 int expr_uid = INSN_UID (EXPR_INSN_RTX (expr));
2490 /* Do not cache result of propagating jumps through an insn group,
2491 as it is always true, which is not useful outside the group. */
2492 if (inside_insn_group)
2493 return;
2495 if (res == MOVEUP_EXPR_NULL)
2497 bitmap_set_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2498 bitmap_set_bit (INSN_FOUND_DEPS (insn), expr_uid);
2500 else if (res == MOVEUP_EXPR_SAME)
2502 bitmap_set_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2503 bitmap_clear_bit (INSN_FOUND_DEPS (insn), expr_uid);
2505 else if (res == MOVEUP_EXPR_AS_RHS)
2507 bitmap_clear_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2508 bitmap_set_bit (INSN_FOUND_DEPS (insn), expr_uid);
2510 else
2511 gcc_unreachable ();
2514 /* Update hashtable on INSN with changed EXPR, old EXPR_OLD_VINSN
2515 and transformation type TRANS_TYPE. */
2516 static void
2517 update_transformation_cache (expr_t expr, insn_t insn,
2518 bool inside_insn_group,
2519 enum local_trans_type trans_type,
2520 vinsn_t expr_old_vinsn)
2522 struct transformed_insns *pti;
2524 if (inside_insn_group)
2525 return;
2527 pti = XNEW (struct transformed_insns);
2528 pti->vinsn_old = expr_old_vinsn;
2529 pti->vinsn_new = EXPR_VINSN (expr);
2530 pti->type = trans_type;
2531 pti->was_target_conflict = was_target_conflict;
2532 pti->ds = EXPR_SPEC_DONE_DS (expr);
2533 pti->needs_check = EXPR_NEEDS_SPEC_CHECK_P (expr);
2534 vinsn_attach (pti->vinsn_old);
2535 vinsn_attach (pti->vinsn_new);
2536 *((struct transformed_insns **)
2537 htab_find_slot_with_hash (INSN_TRANSFORMED_INSNS (insn),
2538 pti, VINSN_HASH_RTX (expr_old_vinsn),
2539 INSERT)) = pti;
2542 /* Same as moveup_expr, but first looks up the result of
2543 transformation in caches. */
2544 static enum MOVEUP_EXPR_CODE
2545 moveup_expr_cached (expr_t expr, insn_t insn, bool inside_insn_group)
2547 enum MOVEUP_EXPR_CODE res;
2548 bool got_answer = false;
2550 if (sched_verbose >= 6)
2552 sel_print ("Moving ");
2553 dump_expr (expr);
2554 sel_print (" through %d: ", INSN_UID (insn));
2557 if (DEBUG_INSN_P (EXPR_INSN_RTX (expr))
2558 && (sel_bb_head (BLOCK_FOR_INSN (EXPR_INSN_RTX (expr)))
2559 == EXPR_INSN_RTX (expr)))
2560 /* Don't use cached information for debug insns that are heads of
2561 basic blocks. */;
2562 else if (try_bitmap_cache (expr, insn, inside_insn_group, &res))
2563 /* When inside insn group, we do not want remove stores conflicting
2564 with previosly issued loads. */
2565 got_answer = ! inside_insn_group || res != MOVEUP_EXPR_NULL;
2566 else if (try_transformation_cache (expr, insn, &res))
2567 got_answer = true;
2569 if (! got_answer)
2571 /* Invoke moveup_expr and record the results. */
2572 vinsn_t expr_old_vinsn = EXPR_VINSN (expr);
2573 ds_t expr_old_spec_ds = EXPR_SPEC_DONE_DS (expr);
2574 int expr_uid = INSN_UID (VINSN_INSN_RTX (expr_old_vinsn));
2575 bool unique_p = VINSN_UNIQUE_P (expr_old_vinsn);
2576 enum local_trans_type trans_type = TRANS_SUBSTITUTION;
2578 /* ??? Invent something better than this. We can't allow old_vinsn
2579 to go, we need it for the history vector. */
2580 vinsn_attach (expr_old_vinsn);
2582 res = moveup_expr (expr, insn, inside_insn_group,
2583 &trans_type);
2584 switch (res)
2586 case MOVEUP_EXPR_NULL:
2587 update_bitmap_cache (expr, insn, inside_insn_group, res);
2588 if (sched_verbose >= 6)
2589 sel_print ("removed\n");
2590 break;
2592 case MOVEUP_EXPR_SAME:
2593 update_bitmap_cache (expr, insn, inside_insn_group, res);
2594 if (sched_verbose >= 6)
2595 sel_print ("unchanged\n");
2596 break;
2598 case MOVEUP_EXPR_AS_RHS:
2599 gcc_assert (!unique_p || inside_insn_group);
2600 update_bitmap_cache (expr, insn, inside_insn_group, res);
2601 if (sched_verbose >= 6)
2602 sel_print ("unchanged (as RHS)\n");
2603 break;
2605 case MOVEUP_EXPR_CHANGED:
2606 gcc_assert (INSN_UID (EXPR_INSN_RTX (expr)) != expr_uid
2607 || EXPR_SPEC_DONE_DS (expr) != expr_old_spec_ds);
2608 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr),
2609 INSN_UID (insn), trans_type,
2610 expr_old_vinsn, EXPR_VINSN (expr),
2611 expr_old_spec_ds);
2612 update_transformation_cache (expr, insn, inside_insn_group,
2613 trans_type, expr_old_vinsn);
2614 if (sched_verbose >= 6)
2616 sel_print ("changed: ");
2617 dump_expr (expr);
2618 sel_print ("\n");
2620 break;
2621 default:
2622 gcc_unreachable ();
2625 vinsn_detach (expr_old_vinsn);
2628 return res;
2631 /* Moves an av set AVP up through INSN, performing necessary
2632 transformations. */
2633 static void
2634 moveup_set_expr (av_set_t *avp, insn_t insn, bool inside_insn_group)
2636 av_set_iterator i;
2637 expr_t expr;
2639 FOR_EACH_EXPR_1 (expr, i, avp)
2642 switch (moveup_expr_cached (expr, insn, inside_insn_group))
2644 case MOVEUP_EXPR_SAME:
2645 case MOVEUP_EXPR_AS_RHS:
2646 break;
2648 case MOVEUP_EXPR_NULL:
2649 av_set_iter_remove (&i);
2650 break;
2652 case MOVEUP_EXPR_CHANGED:
2653 expr = merge_with_other_exprs (avp, &i, expr);
2654 break;
2656 default:
2657 gcc_unreachable ();
2662 /* Moves AVP set along PATH. */
2663 static void
2664 moveup_set_inside_insn_group (av_set_t *avp, ilist_t path)
2666 int last_cycle;
2668 if (sched_verbose >= 6)
2669 sel_print ("Moving expressions up in the insn group...\n");
2670 if (! path)
2671 return;
2672 last_cycle = INSN_SCHED_CYCLE (ILIST_INSN (path));
2673 while (path
2674 && INSN_SCHED_CYCLE (ILIST_INSN (path)) == last_cycle)
2676 moveup_set_expr (avp, ILIST_INSN (path), true);
2677 path = ILIST_NEXT (path);
2681 /* Returns true if after moving EXPR along PATH it equals to EXPR_VLIW. */
2682 static bool
2683 equal_after_moveup_path_p (expr_t expr, ilist_t path, expr_t expr_vliw)
2685 expr_def _tmp, *tmp = &_tmp;
2686 int last_cycle;
2687 bool res = true;
2689 copy_expr_onside (tmp, expr);
2690 last_cycle = path ? INSN_SCHED_CYCLE (ILIST_INSN (path)) : 0;
2691 while (path
2692 && res
2693 && INSN_SCHED_CYCLE (ILIST_INSN (path)) == last_cycle)
2695 res = (moveup_expr_cached (tmp, ILIST_INSN (path), true)
2696 != MOVEUP_EXPR_NULL);
2697 path = ILIST_NEXT (path);
2700 if (res)
2702 vinsn_t tmp_vinsn = EXPR_VINSN (tmp);
2703 vinsn_t expr_vliw_vinsn = EXPR_VINSN (expr_vliw);
2705 if (tmp_vinsn != expr_vliw_vinsn)
2706 res = vinsn_equal_p (tmp_vinsn, expr_vliw_vinsn);
2709 clear_expr (tmp);
2710 return res;
2714 /* Functions that compute av and lv sets. */
2716 /* Returns true if INSN is not a downward continuation of the given path P in
2717 the current stage. */
2718 static bool
2719 is_ineligible_successor (insn_t insn, ilist_t p)
2721 insn_t prev_insn;
2723 /* Check if insn is not deleted. */
2724 if (PREV_INSN (insn) && NEXT_INSN (PREV_INSN (insn)) != insn)
2725 gcc_unreachable ();
2726 else if (NEXT_INSN (insn) && PREV_INSN (NEXT_INSN (insn)) != insn)
2727 gcc_unreachable ();
2729 /* If it's the first insn visited, then the successor is ok. */
2730 if (!p)
2731 return false;
2733 prev_insn = ILIST_INSN (p);
2735 if (/* a backward edge. */
2736 INSN_SEQNO (insn) < INSN_SEQNO (prev_insn)
2737 /* is already visited. */
2738 || (INSN_SEQNO (insn) == INSN_SEQNO (prev_insn)
2739 && (ilist_is_in_p (p, insn)
2740 /* We can reach another fence here and still seqno of insn
2741 would be equal to seqno of prev_insn. This is possible
2742 when prev_insn is a previously created bookkeeping copy.
2743 In that case it'd get a seqno of insn. Thus, check here
2744 whether insn is in current fence too. */
2745 || IN_CURRENT_FENCE_P (insn)))
2746 /* Was already scheduled on this round. */
2747 || (INSN_SEQNO (insn) > INSN_SEQNO (prev_insn)
2748 && IN_CURRENT_FENCE_P (insn))
2749 /* An insn from another fence could also be
2750 scheduled earlier even if this insn is not in
2751 a fence list right now. Check INSN_SCHED_CYCLE instead. */
2752 || (!pipelining_p
2753 && INSN_SCHED_TIMES (insn) > 0))
2754 return true;
2755 else
2756 return false;
2759 /* Computes the av_set below the last bb insn INSN, doing all the 'dirty work'
2760 of handling multiple successors and properly merging its av_sets. P is
2761 the current path traversed. WS is the size of lookahead window.
2762 Return the av set computed. */
2763 static av_set_t
2764 compute_av_set_at_bb_end (insn_t insn, ilist_t p, int ws)
2766 struct succs_info *sinfo;
2767 av_set_t expr_in_all_succ_branches = NULL;
2768 int is;
2769 insn_t succ, zero_succ = NULL;
2770 av_set_t av1 = NULL;
2772 gcc_assert (sel_bb_end_p (insn));
2774 /* Find different kind of successors needed for correct computing of
2775 SPEC and TARGET_AVAILABLE attributes. */
2776 sinfo = compute_succs_info (insn, SUCCS_NORMAL);
2778 /* Debug output. */
2779 if (sched_verbose >= 6)
2781 sel_print ("successors of bb end (%d): ", INSN_UID (insn));
2782 dump_insn_vector (sinfo->succs_ok);
2783 sel_print ("\n");
2784 if (sinfo->succs_ok_n != sinfo->all_succs_n)
2785 sel_print ("real successors num: %d\n", sinfo->all_succs_n);
2788 /* Add insn to the tail of current path. */
2789 ilist_add (&p, insn);
2791 FOR_EACH_VEC_ELT (sinfo->succs_ok, is, succ)
2793 av_set_t succ_set;
2795 /* We will edit SUCC_SET and EXPR_SPEC field of its elements. */
2796 succ_set = compute_av_set_inside_bb (succ, p, ws, true);
2798 av_set_split_usefulness (succ_set,
2799 sinfo->probs_ok[is],
2800 sinfo->all_prob);
2802 if (sinfo->all_succs_n > 1)
2804 /* Find EXPR'es that came from *all* successors and save them
2805 into expr_in_all_succ_branches. This set will be used later
2806 for calculating speculation attributes of EXPR'es. */
2807 if (is == 0)
2809 expr_in_all_succ_branches = av_set_copy (succ_set);
2811 /* Remember the first successor for later. */
2812 zero_succ = succ;
2814 else
2816 av_set_iterator i;
2817 expr_t expr;
2819 FOR_EACH_EXPR_1 (expr, i, &expr_in_all_succ_branches)
2820 if (!av_set_is_in_p (succ_set, EXPR_VINSN (expr)))
2821 av_set_iter_remove (&i);
2825 /* Union the av_sets. Check liveness restrictions on target registers
2826 in special case of two successors. */
2827 if (sinfo->succs_ok_n == 2 && is == 1)
2829 basic_block bb0 = BLOCK_FOR_INSN (zero_succ);
2830 basic_block bb1 = BLOCK_FOR_INSN (succ);
2832 gcc_assert (BB_LV_SET_VALID_P (bb0) && BB_LV_SET_VALID_P (bb1));
2833 av_set_union_and_live (&av1, &succ_set,
2834 BB_LV_SET (bb0),
2835 BB_LV_SET (bb1),
2836 insn);
2838 else
2839 av_set_union_and_clear (&av1, &succ_set, insn);
2842 /* Check liveness restrictions via hard way when there are more than
2843 two successors. */
2844 if (sinfo->succs_ok_n > 2)
2845 FOR_EACH_VEC_ELT (sinfo->succs_ok, is, succ)
2847 basic_block succ_bb = BLOCK_FOR_INSN (succ);
2849 gcc_assert (BB_LV_SET_VALID_P (succ_bb));
2850 mark_unavailable_targets (av1, BB_AV_SET (succ_bb),
2851 BB_LV_SET (succ_bb));
2854 /* Finally, check liveness restrictions on paths leaving the region. */
2855 if (sinfo->all_succs_n > sinfo->succs_ok_n)
2856 FOR_EACH_VEC_ELT (sinfo->succs_other, is, succ)
2857 mark_unavailable_targets
2858 (av1, NULL, BB_LV_SET (BLOCK_FOR_INSN (succ)));
2860 if (sinfo->all_succs_n > 1)
2862 av_set_iterator i;
2863 expr_t expr;
2865 /* Increase the spec attribute of all EXPR'es that didn't come
2866 from all successors. */
2867 FOR_EACH_EXPR (expr, i, av1)
2868 if (!av_set_is_in_p (expr_in_all_succ_branches, EXPR_VINSN (expr)))
2869 EXPR_SPEC (expr)++;
2871 av_set_clear (&expr_in_all_succ_branches);
2873 /* Do not move conditional branches through other
2874 conditional branches. So, remove all conditional
2875 branches from av_set if current operator is a conditional
2876 branch. */
2877 av_set_substract_cond_branches (&av1);
2880 ilist_remove (&p);
2881 free_succs_info (sinfo);
2883 if (sched_verbose >= 6)
2885 sel_print ("av_succs (%d): ", INSN_UID (insn));
2886 dump_av_set (av1);
2887 sel_print ("\n");
2890 return av1;
2893 /* This function computes av_set for the FIRST_INSN by dragging valid
2894 av_set through all basic block insns either from the end of basic block
2895 (computed using compute_av_set_at_bb_end) or from the insn on which
2896 MAX_WS was exceeded. It uses compute_av_set_at_bb_end to compute av_set
2897 below the basic block and handling conditional branches.
2898 FIRST_INSN - the basic block head, P - path consisting of the insns
2899 traversed on the way to the FIRST_INSN (the path is sparse, only bb heads
2900 and bb ends are added to the path), WS - current window size,
2901 NEED_COPY_P - true if we'll make a copy of av_set before returning it. */
2902 static av_set_t
2903 compute_av_set_inside_bb (insn_t first_insn, ilist_t p, int ws,
2904 bool need_copy_p)
2906 insn_t cur_insn;
2907 int end_ws = ws;
2908 insn_t bb_end = sel_bb_end (BLOCK_FOR_INSN (first_insn));
2909 insn_t after_bb_end = NEXT_INSN (bb_end);
2910 insn_t last_insn;
2911 av_set_t av = NULL;
2912 basic_block cur_bb = BLOCK_FOR_INSN (first_insn);
2914 /* Return NULL if insn is not on the legitimate downward path. */
2915 if (is_ineligible_successor (first_insn, p))
2917 if (sched_verbose >= 6)
2918 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (first_insn));
2920 return NULL;
2923 /* If insn already has valid av(insn) computed, just return it. */
2924 if (AV_SET_VALID_P (first_insn))
2926 av_set_t av_set;
2928 if (sel_bb_head_p (first_insn))
2929 av_set = BB_AV_SET (BLOCK_FOR_INSN (first_insn));
2930 else
2931 av_set = NULL;
2933 if (sched_verbose >= 6)
2935 sel_print ("Insn %d has a valid av set: ", INSN_UID (first_insn));
2936 dump_av_set (av_set);
2937 sel_print ("\n");
2940 return need_copy_p ? av_set_copy (av_set) : av_set;
2943 ilist_add (&p, first_insn);
2945 /* As the result after this loop have completed, in LAST_INSN we'll
2946 have the insn which has valid av_set to start backward computation
2947 from: it either will be NULL because on it the window size was exceeded
2948 or other valid av_set as returned by compute_av_set for the last insn
2949 of the basic block. */
2950 for (last_insn = first_insn; last_insn != after_bb_end;
2951 last_insn = NEXT_INSN (last_insn))
2953 /* We may encounter valid av_set not only on bb_head, but also on
2954 those insns on which previously MAX_WS was exceeded. */
2955 if (AV_SET_VALID_P (last_insn))
2957 if (sched_verbose >= 6)
2958 sel_print ("Insn %d has a valid empty av set\n", INSN_UID (last_insn));
2959 break;
2962 /* The special case: the last insn of the BB may be an
2963 ineligible_successor due to its SEQ_NO that was set on
2964 it as a bookkeeping. */
2965 if (last_insn != first_insn
2966 && is_ineligible_successor (last_insn, p))
2968 if (sched_verbose >= 6)
2969 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (last_insn));
2970 break;
2973 if (DEBUG_INSN_P (last_insn))
2974 continue;
2976 if (end_ws > max_ws)
2978 /* We can reach max lookahead size at bb_header, so clean av_set
2979 first. */
2980 INSN_WS_LEVEL (last_insn) = global_level;
2982 if (sched_verbose >= 6)
2983 sel_print ("Insn %d is beyond the software lookahead window size\n",
2984 INSN_UID (last_insn));
2985 break;
2988 end_ws++;
2991 /* Get the valid av_set into AV above the LAST_INSN to start backward
2992 computation from. It either will be empty av_set or av_set computed from
2993 the successors on the last insn of the current bb. */
2994 if (last_insn != after_bb_end)
2996 av = NULL;
2998 /* This is needed only to obtain av_sets that are identical to
2999 those computed by the old compute_av_set version. */
3000 if (last_insn == first_insn && !INSN_NOP_P (last_insn))
3001 av_set_add (&av, INSN_EXPR (last_insn));
3003 else
3004 /* END_WS is always already increased by 1 if LAST_INSN == AFTER_BB_END. */
3005 av = compute_av_set_at_bb_end (bb_end, p, end_ws);
3007 /* Compute av_set in AV starting from below the LAST_INSN up to
3008 location above the FIRST_INSN. */
3009 for (cur_insn = PREV_INSN (last_insn); cur_insn != PREV_INSN (first_insn);
3010 cur_insn = PREV_INSN (cur_insn))
3011 if (!INSN_NOP_P (cur_insn))
3013 expr_t expr;
3015 moveup_set_expr (&av, cur_insn, false);
3017 /* If the expression for CUR_INSN is already in the set,
3018 replace it by the new one. */
3019 expr = av_set_lookup (av, INSN_VINSN (cur_insn));
3020 if (expr != NULL)
3022 clear_expr (expr);
3023 copy_expr (expr, INSN_EXPR (cur_insn));
3025 else
3026 av_set_add (&av, INSN_EXPR (cur_insn));
3029 /* Clear stale bb_av_set. */
3030 if (sel_bb_head_p (first_insn))
3032 av_set_clear (&BB_AV_SET (cur_bb));
3033 BB_AV_SET (cur_bb) = need_copy_p ? av_set_copy (av) : av;
3034 BB_AV_LEVEL (cur_bb) = global_level;
3037 if (sched_verbose >= 6)
3039 sel_print ("Computed av set for insn %d: ", INSN_UID (first_insn));
3040 dump_av_set (av);
3041 sel_print ("\n");
3044 ilist_remove (&p);
3045 return av;
3048 /* Compute av set before INSN.
3049 INSN - the current operation (actual rtx INSN)
3050 P - the current path, which is list of insns visited so far
3051 WS - software lookahead window size.
3052 UNIQUE_P - TRUE, if returned av_set will be changed, hence
3053 if we want to save computed av_set in s_i_d, we should make a copy of it.
3055 In the resulting set we will have only expressions that don't have delay
3056 stalls and nonsubstitutable dependences. */
3057 static av_set_t
3058 compute_av_set (insn_t insn, ilist_t p, int ws, bool unique_p)
3060 return compute_av_set_inside_bb (insn, p, ws, unique_p);
3063 /* Propagate a liveness set LV through INSN. */
3064 static void
3065 propagate_lv_set (regset lv, insn_t insn)
3067 gcc_assert (INSN_P (insn));
3069 if (INSN_NOP_P (insn))
3070 return;
3072 df_simulate_one_insn_backwards (BLOCK_FOR_INSN (insn), insn, lv);
3075 /* Return livness set at the end of BB. */
3076 static regset
3077 compute_live_after_bb (basic_block bb)
3079 edge e;
3080 edge_iterator ei;
3081 regset lv = get_clear_regset_from_pool ();
3083 gcc_assert (!ignore_first);
3085 FOR_EACH_EDGE (e, ei, bb->succs)
3086 if (sel_bb_empty_p (e->dest))
3088 if (! BB_LV_SET_VALID_P (e->dest))
3090 gcc_unreachable ();
3091 gcc_assert (BB_LV_SET (e->dest) == NULL);
3092 BB_LV_SET (e->dest) = compute_live_after_bb (e->dest);
3093 BB_LV_SET_VALID_P (e->dest) = true;
3095 IOR_REG_SET (lv, BB_LV_SET (e->dest));
3097 else
3098 IOR_REG_SET (lv, compute_live (sel_bb_head (e->dest)));
3100 return lv;
3103 /* Compute the set of all live registers at the point before INSN and save
3104 it at INSN if INSN is bb header. */
3105 regset
3106 compute_live (insn_t insn)
3108 basic_block bb = BLOCK_FOR_INSN (insn);
3109 insn_t final, temp;
3110 regset lv;
3112 /* Return the valid set if we're already on it. */
3113 if (!ignore_first)
3115 regset src = NULL;
3117 if (sel_bb_head_p (insn) && BB_LV_SET_VALID_P (bb))
3118 src = BB_LV_SET (bb);
3119 else
3121 gcc_assert (in_current_region_p (bb));
3122 if (INSN_LIVE_VALID_P (insn))
3123 src = INSN_LIVE (insn);
3126 if (src)
3128 lv = get_regset_from_pool ();
3129 COPY_REG_SET (lv, src);
3131 if (sel_bb_head_p (insn) && ! BB_LV_SET_VALID_P (bb))
3133 COPY_REG_SET (BB_LV_SET (bb), lv);
3134 BB_LV_SET_VALID_P (bb) = true;
3137 return_regset_to_pool (lv);
3138 return lv;
3142 /* We've skipped the wrong lv_set. Don't skip the right one. */
3143 ignore_first = false;
3144 gcc_assert (in_current_region_p (bb));
3146 /* Find a valid LV set in this block or below, if needed.
3147 Start searching from the next insn: either ignore_first is true, or
3148 INSN doesn't have a correct live set. */
3149 temp = NEXT_INSN (insn);
3150 final = NEXT_INSN (BB_END (bb));
3151 while (temp != final && ! INSN_LIVE_VALID_P (temp))
3152 temp = NEXT_INSN (temp);
3153 if (temp == final)
3155 lv = compute_live_after_bb (bb);
3156 temp = PREV_INSN (temp);
3158 else
3160 lv = get_regset_from_pool ();
3161 COPY_REG_SET (lv, INSN_LIVE (temp));
3164 /* Put correct lv sets on the insns which have bad sets. */
3165 final = PREV_INSN (insn);
3166 while (temp != final)
3168 propagate_lv_set (lv, temp);
3169 COPY_REG_SET (INSN_LIVE (temp), lv);
3170 INSN_LIVE_VALID_P (temp) = true;
3171 temp = PREV_INSN (temp);
3174 /* Also put it in a BB. */
3175 if (sel_bb_head_p (insn))
3177 basic_block bb = BLOCK_FOR_INSN (insn);
3179 COPY_REG_SET (BB_LV_SET (bb), lv);
3180 BB_LV_SET_VALID_P (bb) = true;
3183 /* We return LV to the pool, but will not clear it there. Thus we can
3184 legimatelly use LV till the next use of regset_pool_get (). */
3185 return_regset_to_pool (lv);
3186 return lv;
3189 /* Update liveness sets for INSN. */
3190 static inline void
3191 update_liveness_on_insn (rtx insn)
3193 ignore_first = true;
3194 compute_live (insn);
3197 /* Compute liveness below INSN and write it into REGS. */
3198 static inline void
3199 compute_live_below_insn (rtx insn, regset regs)
3201 rtx succ;
3202 succ_iterator si;
3204 FOR_EACH_SUCC_1 (succ, si, insn, SUCCS_ALL)
3205 IOR_REG_SET (regs, compute_live (succ));
3208 /* Update the data gathered in av and lv sets starting from INSN. */
3209 static void
3210 update_data_sets (rtx insn)
3212 update_liveness_on_insn (insn);
3213 if (sel_bb_head_p (insn))
3215 gcc_assert (AV_LEVEL (insn) != 0);
3216 BB_AV_LEVEL (BLOCK_FOR_INSN (insn)) = -1;
3217 compute_av_set (insn, NULL, 0, 0);
3222 /* Helper for move_op () and find_used_regs ().
3223 Return speculation type for which a check should be created on the place
3224 of INSN. EXPR is one of the original ops we are searching for. */
3225 static ds_t
3226 get_spec_check_type_for_insn (insn_t insn, expr_t expr)
3228 ds_t to_check_ds;
3229 ds_t already_checked_ds = EXPR_SPEC_DONE_DS (INSN_EXPR (insn));
3231 to_check_ds = EXPR_SPEC_TO_CHECK_DS (expr);
3233 if (targetm.sched.get_insn_checked_ds)
3234 already_checked_ds |= targetm.sched.get_insn_checked_ds (insn);
3236 if (spec_info != NULL
3237 && (spec_info->flags & SEL_SCHED_SPEC_DONT_CHECK_CONTROL))
3238 already_checked_ds |= BEGIN_CONTROL;
3240 already_checked_ds = ds_get_speculation_types (already_checked_ds);
3242 to_check_ds &= ~already_checked_ds;
3244 return to_check_ds;
3247 /* Find the set of registers that are unavailable for storing expres
3248 while moving ORIG_OPS up on the path starting from INSN due to
3249 liveness (USED_REGS) or hardware restrictions (REG_RENAME_P).
3251 All the original operations found during the traversal are saved in the
3252 ORIGINAL_INSNS list.
3254 REG_RENAME_P denotes the set of hardware registers that
3255 can not be used with renaming due to the register class restrictions,
3256 mode restrictions and other (the register we'll choose should be
3257 compatible class with the original uses, shouldn't be in call_used_regs,
3258 should be HARD_REGNO_RENAME_OK etc).
3260 Returns TRUE if we've found all original insns, FALSE otherwise.
3262 This function utilizes code_motion_path_driver (formerly find_used_regs_1)
3263 to traverse the code motion paths. This helper function finds registers
3264 that are not available for storing expres while moving ORIG_OPS up on the
3265 path starting from INSN. A register considered as used on the moving path,
3266 if one of the following conditions is not satisfied:
3268 (1) a register not set or read on any path from xi to an instance of
3269 the original operation,
3270 (2) not among the live registers of the point immediately following the
3271 first original operation on a given downward path, except for the
3272 original target register of the operation,
3273 (3) not live on the other path of any conditional branch that is passed
3274 by the operation, in case original operations are not present on
3275 both paths of the conditional branch.
3277 All the original operations found during the traversal are saved in the
3278 ORIGINAL_INSNS list.
3280 REG_RENAME_P->CROSSES_CALL is true, if there is a call insn on the path
3281 from INSN to original insn. In this case CALL_USED_REG_SET will be added
3282 to unavailable hard regs at the point original operation is found. */
3284 static bool
3285 find_used_regs (insn_t insn, av_set_t orig_ops, regset used_regs,
3286 struct reg_rename *reg_rename_p, def_list_t *original_insns)
3288 def_list_iterator i;
3289 def_t def;
3290 int res;
3291 bool needs_spec_check_p = false;
3292 expr_t expr;
3293 av_set_iterator expr_iter;
3294 struct fur_static_params sparams;
3295 struct cmpd_local_params lparams;
3297 /* We haven't visited any blocks yet. */
3298 bitmap_clear (code_motion_visited_blocks);
3300 /* Init parameters for code_motion_path_driver. */
3301 sparams.crosses_call = false;
3302 sparams.original_insns = original_insns;
3303 sparams.used_regs = used_regs;
3305 /* Set the appropriate hooks and data. */
3306 code_motion_path_driver_info = &fur_hooks;
3308 res = code_motion_path_driver (insn, orig_ops, NULL, &lparams, &sparams);
3310 reg_rename_p->crosses_call |= sparams.crosses_call;
3312 gcc_assert (res == 1);
3313 gcc_assert (original_insns && *original_insns);
3315 /* ??? We calculate whether an expression needs a check when computing
3316 av sets. This information is not as precise as it could be due to
3317 merging this bit in merge_expr. We can do better in find_used_regs,
3318 but we want to avoid multiple traversals of the same code motion
3319 paths. */
3320 FOR_EACH_EXPR (expr, expr_iter, orig_ops)
3321 needs_spec_check_p |= EXPR_NEEDS_SPEC_CHECK_P (expr);
3323 /* Mark hardware regs in REG_RENAME_P that are not suitable
3324 for renaming expr in INSN due to hardware restrictions (register class,
3325 modes compatibility etc). */
3326 FOR_EACH_DEF (def, i, *original_insns)
3328 vinsn_t vinsn = INSN_VINSN (def->orig_insn);
3330 if (VINSN_SEPARABLE_P (vinsn))
3331 mark_unavailable_hard_regs (def, reg_rename_p, used_regs);
3333 /* Do not allow clobbering of ld.[sa] address in case some of the
3334 original operations need a check. */
3335 if (needs_spec_check_p)
3336 IOR_REG_SET (used_regs, VINSN_REG_USES (vinsn));
3339 return true;
3343 /* Functions to choose the best insn from available ones. */
3345 /* Adjusts the priority for EXPR using the backend *_adjust_priority hook. */
3346 static int
3347 sel_target_adjust_priority (expr_t expr)
3349 int priority = EXPR_PRIORITY (expr);
3350 int new_priority;
3352 if (targetm.sched.adjust_priority)
3353 new_priority = targetm.sched.adjust_priority (EXPR_INSN_RTX (expr), priority);
3354 else
3355 new_priority = priority;
3357 /* If the priority has changed, adjust EXPR_PRIORITY_ADJ accordingly. */
3358 EXPR_PRIORITY_ADJ (expr) = new_priority - EXPR_PRIORITY (expr);
3360 gcc_assert (EXPR_PRIORITY_ADJ (expr) >= 0);
3362 if (sched_verbose >= 4)
3363 sel_print ("sel_target_adjust_priority: insn %d, %d+%d = %d.\n",
3364 INSN_UID (EXPR_INSN_RTX (expr)), EXPR_PRIORITY (expr),
3365 EXPR_PRIORITY_ADJ (expr), new_priority);
3367 return new_priority;
3370 /* Rank two available exprs for schedule. Never return 0 here. */
3371 static int
3372 sel_rank_for_schedule (const void *x, const void *y)
3374 expr_t tmp = *(const expr_t *) y;
3375 expr_t tmp2 = *(const expr_t *) x;
3376 insn_t tmp_insn, tmp2_insn;
3377 vinsn_t tmp_vinsn, tmp2_vinsn;
3378 int val;
3380 tmp_vinsn = EXPR_VINSN (tmp);
3381 tmp2_vinsn = EXPR_VINSN (tmp2);
3382 tmp_insn = EXPR_INSN_RTX (tmp);
3383 tmp2_insn = EXPR_INSN_RTX (tmp2);
3385 /* Schedule debug insns as early as possible. */
3386 if (DEBUG_INSN_P (tmp_insn) && !DEBUG_INSN_P (tmp2_insn))
3387 return -1;
3388 else if (DEBUG_INSN_P (tmp2_insn))
3389 return 1;
3391 /* Prefer SCHED_GROUP_P insns to any others. */
3392 if (SCHED_GROUP_P (tmp_insn) != SCHED_GROUP_P (tmp2_insn))
3394 if (VINSN_UNIQUE_P (tmp_vinsn) && VINSN_UNIQUE_P (tmp2_vinsn))
3395 return SCHED_GROUP_P (tmp2_insn) ? 1 : -1;
3397 /* Now uniqueness means SCHED_GROUP_P is set, because schedule groups
3398 cannot be cloned. */
3399 if (VINSN_UNIQUE_P (tmp2_vinsn))
3400 return 1;
3401 return -1;
3404 /* Discourage scheduling of speculative checks. */
3405 val = (sel_insn_is_speculation_check (tmp_insn)
3406 - sel_insn_is_speculation_check (tmp2_insn));
3407 if (val)
3408 return val;
3410 /* Prefer not scheduled insn over scheduled one. */
3411 if (EXPR_SCHED_TIMES (tmp) > 0 || EXPR_SCHED_TIMES (tmp2) > 0)
3413 val = EXPR_SCHED_TIMES (tmp) - EXPR_SCHED_TIMES (tmp2);
3414 if (val)
3415 return val;
3418 /* Prefer jump over non-jump instruction. */
3419 if (control_flow_insn_p (tmp_insn) && !control_flow_insn_p (tmp2_insn))
3420 return -1;
3421 else if (control_flow_insn_p (tmp2_insn) && !control_flow_insn_p (tmp_insn))
3422 return 1;
3424 /* Prefer an expr with greater priority. */
3425 if (EXPR_USEFULNESS (tmp) != 0 && EXPR_USEFULNESS (tmp2) != 0)
3427 int p2 = EXPR_PRIORITY (tmp2) + EXPR_PRIORITY_ADJ (tmp2),
3428 p1 = EXPR_PRIORITY (tmp) + EXPR_PRIORITY_ADJ (tmp);
3430 val = p2 * EXPR_USEFULNESS (tmp2) - p1 * EXPR_USEFULNESS (tmp);
3432 else
3433 val = EXPR_PRIORITY (tmp2) - EXPR_PRIORITY (tmp)
3434 + EXPR_PRIORITY_ADJ (tmp2) - EXPR_PRIORITY_ADJ (tmp);
3435 if (val)
3436 return val;
3438 if (spec_info != NULL && spec_info->mask != 0)
3439 /* This code was taken from haifa-sched.c: rank_for_schedule (). */
3441 ds_t ds1, ds2;
3442 dw_t dw1, dw2;
3443 int dw;
3445 ds1 = EXPR_SPEC_DONE_DS (tmp);
3446 if (ds1)
3447 dw1 = ds_weak (ds1);
3448 else
3449 dw1 = NO_DEP_WEAK;
3451 ds2 = EXPR_SPEC_DONE_DS (tmp2);
3452 if (ds2)
3453 dw2 = ds_weak (ds2);
3454 else
3455 dw2 = NO_DEP_WEAK;
3457 dw = dw2 - dw1;
3458 if (dw > (NO_DEP_WEAK / 8) || dw < -(NO_DEP_WEAK / 8))
3459 return dw;
3462 /* Prefer an old insn to a bookkeeping insn. */
3463 if (INSN_UID (tmp_insn) < first_emitted_uid
3464 && INSN_UID (tmp2_insn) >= first_emitted_uid)
3465 return -1;
3466 if (INSN_UID (tmp_insn) >= first_emitted_uid
3467 && INSN_UID (tmp2_insn) < first_emitted_uid)
3468 return 1;
3470 /* Prefer an insn with smaller UID, as a last resort.
3471 We can't safely use INSN_LUID as it is defined only for those insns
3472 that are in the stream. */
3473 return INSN_UID (tmp_insn) - INSN_UID (tmp2_insn);
3476 /* Filter out expressions from av set pointed to by AV_PTR
3477 that are pipelined too many times. */
3478 static void
3479 process_pipelined_exprs (av_set_t *av_ptr)
3481 expr_t expr;
3482 av_set_iterator si;
3484 /* Don't pipeline already pipelined code as that would increase
3485 number of unnecessary register moves. */
3486 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3488 if (EXPR_SCHED_TIMES (expr)
3489 >= PARAM_VALUE (PARAM_SELSCHED_MAX_SCHED_TIMES))
3490 av_set_iter_remove (&si);
3494 /* Filter speculative insns from AV_PTR if we don't want them. */
3495 static void
3496 process_spec_exprs (av_set_t *av_ptr)
3498 expr_t expr;
3499 av_set_iterator si;
3501 if (spec_info == NULL)
3502 return;
3504 /* Scan *AV_PTR to find out if we want to consider speculative
3505 instructions for scheduling. */
3506 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3508 ds_t ds;
3510 ds = EXPR_SPEC_DONE_DS (expr);
3512 /* The probability of a success is too low - don't speculate. */
3513 if ((ds & SPECULATIVE)
3514 && (ds_weak (ds) < spec_info->data_weakness_cutoff
3515 || EXPR_USEFULNESS (expr) < spec_info->control_weakness_cutoff
3516 || (pipelining_p && false
3517 && (ds & DATA_SPEC)
3518 && (ds & CONTROL_SPEC))))
3520 av_set_iter_remove (&si);
3521 continue;
3526 /* Search for any use-like insns in AV_PTR and decide on scheduling
3527 them. Return one when found, and NULL otherwise.
3528 Note that we check here whether a USE could be scheduled to avoid
3529 an infinite loop later. */
3530 static expr_t
3531 process_use_exprs (av_set_t *av_ptr)
3533 expr_t expr;
3534 av_set_iterator si;
3535 bool uses_present_p = false;
3536 bool try_uses_p = true;
3538 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3540 /* This will also initialize INSN_CODE for later use. */
3541 if (recog_memoized (EXPR_INSN_RTX (expr)) < 0)
3543 /* If we have a USE in *AV_PTR that was not scheduled yet,
3544 do so because it will do good only. */
3545 if (EXPR_SCHED_TIMES (expr) <= 0)
3547 if (EXPR_TARGET_AVAILABLE (expr) == 1)
3548 return expr;
3550 av_set_iter_remove (&si);
3552 else
3554 gcc_assert (pipelining_p);
3556 uses_present_p = true;
3559 else
3560 try_uses_p = false;
3563 if (uses_present_p)
3565 /* If we don't want to schedule any USEs right now and we have some
3566 in *AV_PTR, remove them, else just return the first one found. */
3567 if (!try_uses_p)
3569 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3570 if (INSN_CODE (EXPR_INSN_RTX (expr)) < 0)
3571 av_set_iter_remove (&si);
3573 else
3575 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3577 gcc_assert (INSN_CODE (EXPR_INSN_RTX (expr)) < 0);
3579 if (EXPR_TARGET_AVAILABLE (expr) == 1)
3580 return expr;
3582 av_set_iter_remove (&si);
3587 return NULL;
3590 /* Lookup EXPR in VINSN_VEC and return TRUE if found. Also check patterns from
3591 EXPR's history of changes. */
3592 static bool
3593 vinsn_vec_has_expr_p (vinsn_vec_t vinsn_vec, expr_t expr)
3595 vinsn_t vinsn, expr_vinsn;
3596 int n;
3597 unsigned i;
3599 /* Start with checking expr itself and then proceed with all the old forms
3600 of expr taken from its history vector. */
3601 for (i = 0, expr_vinsn = EXPR_VINSN (expr);
3602 expr_vinsn;
3603 expr_vinsn = (i < EXPR_HISTORY_OF_CHANGES (expr).length ()
3604 ? EXPR_HISTORY_OF_CHANGES (expr)[i++].old_expr_vinsn
3605 : NULL))
3606 FOR_EACH_VEC_ELT (vinsn_vec, n, vinsn)
3607 if (VINSN_SEPARABLE_P (vinsn))
3609 if (vinsn_equal_p (vinsn, expr_vinsn))
3610 return true;
3612 else
3614 /* For non-separable instructions, the blocking insn can have
3615 another pattern due to substitution, and we can't choose
3616 different register as in the above case. Check all registers
3617 being written instead. */
3618 if (bitmap_intersect_p (VINSN_REG_SETS (vinsn),
3619 VINSN_REG_SETS (expr_vinsn)))
3620 return true;
3623 return false;
3626 #ifdef ENABLE_CHECKING
3627 /* Return true if either of expressions from ORIG_OPS can be blocked
3628 by previously created bookkeeping code. STATIC_PARAMS points to static
3629 parameters of move_op. */
3630 static bool
3631 av_set_could_be_blocked_by_bookkeeping_p (av_set_t orig_ops, void *static_params)
3633 expr_t expr;
3634 av_set_iterator iter;
3635 moveop_static_params_p sparams;
3637 /* This checks that expressions in ORIG_OPS are not blocked by bookkeeping
3638 created while scheduling on another fence. */
3639 FOR_EACH_EXPR (expr, iter, orig_ops)
3640 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns, expr))
3641 return true;
3643 gcc_assert (code_motion_path_driver_info == &move_op_hooks);
3644 sparams = (moveop_static_params_p) static_params;
3646 /* Expressions can be also blocked by bookkeeping created during current
3647 move_op. */
3648 if (bitmap_bit_p (current_copies, INSN_UID (sparams->failed_insn)))
3649 FOR_EACH_EXPR (expr, iter, orig_ops)
3650 if (moveup_expr_cached (expr, sparams->failed_insn, false) != MOVEUP_EXPR_NULL)
3651 return true;
3653 /* Expressions in ORIG_OPS may have wrong destination register due to
3654 renaming. Check with the right register instead. */
3655 if (sparams->dest && REG_P (sparams->dest))
3657 rtx reg = sparams->dest;
3658 vinsn_t failed_vinsn = INSN_VINSN (sparams->failed_insn);
3660 if (register_unavailable_p (VINSN_REG_SETS (failed_vinsn), reg)
3661 || register_unavailable_p (VINSN_REG_USES (failed_vinsn), reg)
3662 || register_unavailable_p (VINSN_REG_CLOBBERS (failed_vinsn), reg))
3663 return true;
3666 return false;
3668 #endif
3670 /* Clear VINSN_VEC and detach vinsns. */
3671 static void
3672 vinsn_vec_clear (vinsn_vec_t *vinsn_vec)
3674 unsigned len = vinsn_vec->length ();
3675 if (len > 0)
3677 vinsn_t vinsn;
3678 int n;
3680 FOR_EACH_VEC_ELT (*vinsn_vec, n, vinsn)
3681 vinsn_detach (vinsn);
3682 vinsn_vec->block_remove (0, len);
3686 /* Add the vinsn of EXPR to the VINSN_VEC. */
3687 static void
3688 vinsn_vec_add (vinsn_vec_t *vinsn_vec, expr_t expr)
3690 vinsn_attach (EXPR_VINSN (expr));
3691 vinsn_vec->safe_push (EXPR_VINSN (expr));
3694 /* Free the vector representing blocked expressions. */
3695 static void
3696 vinsn_vec_free (vinsn_vec_t &vinsn_vec)
3698 vinsn_vec.release ();
3701 /* Increase EXPR_PRIORITY_ADJ for INSN by AMOUNT. */
3703 void sel_add_to_insn_priority (rtx insn, int amount)
3705 EXPR_PRIORITY_ADJ (INSN_EXPR (insn)) += amount;
3707 if (sched_verbose >= 2)
3708 sel_print ("sel_add_to_insn_priority: insn %d, by %d (now %d+%d).\n",
3709 INSN_UID (insn), amount, EXPR_PRIORITY (INSN_EXPR (insn)),
3710 EXPR_PRIORITY_ADJ (INSN_EXPR (insn)));
3713 /* Turn AV into a vector, filter inappropriate insns and sort it. Return
3714 true if there is something to schedule. BNDS and FENCE are current
3715 boundaries and fence, respectively. If we need to stall for some cycles
3716 before an expr from AV would become available, write this number to
3717 *PNEED_STALL. */
3718 static bool
3719 fill_vec_av_set (av_set_t av, blist_t bnds, fence_t fence,
3720 int *pneed_stall)
3722 av_set_iterator si;
3723 expr_t expr;
3724 int sched_next_worked = 0, stalled, n;
3725 static int av_max_prio, est_ticks_till_branch;
3726 int min_need_stall = -1;
3727 deps_t dc = BND_DC (BLIST_BND (bnds));
3729 /* Bail out early when the ready list contained only USEs/CLOBBERs that are
3730 already scheduled. */
3731 if (av == NULL)
3732 return false;
3734 /* Empty vector from the previous stuff. */
3735 if (vec_av_set.length () > 0)
3736 vec_av_set.block_remove (0, vec_av_set.length ());
3738 /* Turn the set into a vector for sorting and call sel_target_adjust_priority
3739 for each insn. */
3740 gcc_assert (vec_av_set.is_empty ());
3741 FOR_EACH_EXPR (expr, si, av)
3743 vec_av_set.safe_push (expr);
3745 gcc_assert (EXPR_PRIORITY_ADJ (expr) == 0 || *pneed_stall);
3747 /* Adjust priority using target backend hook. */
3748 sel_target_adjust_priority (expr);
3751 /* Sort the vector. */
3752 vec_av_set.qsort (sel_rank_for_schedule);
3754 /* We record maximal priority of insns in av set for current instruction
3755 group. */
3756 if (FENCE_STARTS_CYCLE_P (fence))
3757 av_max_prio = est_ticks_till_branch = INT_MIN;
3759 /* Filter out inappropriate expressions. Loop's direction is reversed to
3760 visit "best" instructions first. We assume that vec::unordered_remove
3761 moves last element in place of one being deleted. */
3762 for (n = vec_av_set.length () - 1, stalled = 0; n >= 0; n--)
3764 expr_t expr = vec_av_set[n];
3765 insn_t insn = EXPR_INSN_RTX (expr);
3766 signed char target_available;
3767 bool is_orig_reg_p = true;
3768 int need_cycles, new_prio;
3769 bool fence_insn_p = INSN_UID (insn) == INSN_UID (FENCE_INSN (fence));
3771 /* Don't allow any insns other than from SCHED_GROUP if we have one. */
3772 if (FENCE_SCHED_NEXT (fence) && insn != FENCE_SCHED_NEXT (fence))
3774 vec_av_set.unordered_remove (n);
3775 continue;
3778 /* Set number of sched_next insns (just in case there
3779 could be several). */
3780 if (FENCE_SCHED_NEXT (fence))
3781 sched_next_worked++;
3783 /* Check all liveness requirements and try renaming.
3784 FIXME: try to minimize calls to this. */
3785 target_available = EXPR_TARGET_AVAILABLE (expr);
3787 /* If insn was already scheduled on the current fence,
3788 set TARGET_AVAILABLE to -1 no matter what expr's attribute says. */
3789 if (vinsn_vec_has_expr_p (vec_target_unavailable_vinsns, expr)
3790 && !fence_insn_p)
3791 target_available = -1;
3793 /* If the availability of the EXPR is invalidated by the insertion of
3794 bookkeeping earlier, make sure that we won't choose this expr for
3795 scheduling if it's not separable, and if it is separable, then
3796 we have to recompute the set of available registers for it. */
3797 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns, expr))
3799 vec_av_set.unordered_remove (n);
3800 if (sched_verbose >= 4)
3801 sel_print ("Expr %d is blocked by bookkeeping inserted earlier\n",
3802 INSN_UID (insn));
3803 continue;
3806 if (target_available == true)
3808 /* Do nothing -- we can use an existing register. */
3809 is_orig_reg_p = EXPR_SEPARABLE_P (expr);
3811 else if (/* Non-separable instruction will never
3812 get another register. */
3813 (target_available == false
3814 && !EXPR_SEPARABLE_P (expr))
3815 /* Don't try to find a register for low-priority expression. */
3816 || (int) vec_av_set.length () - 1 - n >= max_insns_to_rename
3817 /* ??? FIXME: Don't try to rename data speculation. */
3818 || (EXPR_SPEC_DONE_DS (expr) & BEGIN_DATA)
3819 || ! find_best_reg_for_expr (expr, bnds, &is_orig_reg_p))
3821 vec_av_set.unordered_remove (n);
3822 if (sched_verbose >= 4)
3823 sel_print ("Expr %d has no suitable target register\n",
3824 INSN_UID (insn));
3826 /* A fence insn should not get here. */
3827 gcc_assert (!fence_insn_p);
3828 continue;
3831 /* At this point a fence insn should always be available. */
3832 gcc_assert (!fence_insn_p
3833 || INSN_UID (FENCE_INSN (fence)) == INSN_UID (EXPR_INSN_RTX (expr)));
3835 /* Filter expressions that need to be renamed or speculated when
3836 pipelining, because compensating register copies or speculation
3837 checks are likely to be placed near the beginning of the loop,
3838 causing a stall. */
3839 if (pipelining_p && EXPR_ORIG_SCHED_CYCLE (expr) > 0
3840 && (!is_orig_reg_p || EXPR_SPEC_DONE_DS (expr) != 0))
3842 /* Estimation of number of cycles until loop branch for
3843 renaming/speculation to be successful. */
3844 int need_n_ticks_till_branch = sel_vinsn_cost (EXPR_VINSN (expr));
3846 if ((int) current_loop_nest->ninsns < 9)
3848 vec_av_set.unordered_remove (n);
3849 if (sched_verbose >= 4)
3850 sel_print ("Pipelining expr %d will likely cause stall\n",
3851 INSN_UID (insn));
3852 continue;
3855 if ((int) current_loop_nest->ninsns - num_insns_scheduled
3856 < need_n_ticks_till_branch * issue_rate / 2
3857 && est_ticks_till_branch < need_n_ticks_till_branch)
3859 vec_av_set.unordered_remove (n);
3860 if (sched_verbose >= 4)
3861 sel_print ("Pipelining expr %d will likely cause stall\n",
3862 INSN_UID (insn));
3863 continue;
3867 /* We want to schedule speculation checks as late as possible. Discard
3868 them from av set if there are instructions with higher priority. */
3869 if (sel_insn_is_speculation_check (insn)
3870 && EXPR_PRIORITY (expr) < av_max_prio)
3872 stalled++;
3873 min_need_stall = min_need_stall < 0 ? 1 : MIN (min_need_stall, 1);
3874 vec_av_set.unordered_remove (n);
3875 if (sched_verbose >= 4)
3876 sel_print ("Delaying speculation check %d until its first use\n",
3877 INSN_UID (insn));
3878 continue;
3881 /* Ignore EXPRs available from pipelining to update AV_MAX_PRIO. */
3882 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3883 av_max_prio = MAX (av_max_prio, EXPR_PRIORITY (expr));
3885 /* Don't allow any insns whose data is not yet ready.
3886 Check first whether we've already tried them and failed. */
3887 if (INSN_UID (insn) < FENCE_READY_TICKS_SIZE (fence))
3889 need_cycles = (FENCE_READY_TICKS (fence)[INSN_UID (insn)]
3890 - FENCE_CYCLE (fence));
3891 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3892 est_ticks_till_branch = MAX (est_ticks_till_branch,
3893 EXPR_PRIORITY (expr) + need_cycles);
3895 if (need_cycles > 0)
3897 stalled++;
3898 min_need_stall = (min_need_stall < 0
3899 ? need_cycles
3900 : MIN (min_need_stall, need_cycles));
3901 vec_av_set.unordered_remove (n);
3903 if (sched_verbose >= 4)
3904 sel_print ("Expr %d is not ready until cycle %d (cached)\n",
3905 INSN_UID (insn),
3906 FENCE_READY_TICKS (fence)[INSN_UID (insn)]);
3907 continue;
3911 /* Now resort to dependence analysis to find whether EXPR might be
3912 stalled due to dependencies from FENCE's context. */
3913 need_cycles = tick_check_p (expr, dc, fence);
3914 new_prio = EXPR_PRIORITY (expr) + EXPR_PRIORITY_ADJ (expr) + need_cycles;
3916 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3917 est_ticks_till_branch = MAX (est_ticks_till_branch,
3918 new_prio);
3920 if (need_cycles > 0)
3922 if (INSN_UID (insn) >= FENCE_READY_TICKS_SIZE (fence))
3924 int new_size = INSN_UID (insn) * 3 / 2;
3926 FENCE_READY_TICKS (fence)
3927 = (int *) xrecalloc (FENCE_READY_TICKS (fence),
3928 new_size, FENCE_READY_TICKS_SIZE (fence),
3929 sizeof (int));
3931 FENCE_READY_TICKS (fence)[INSN_UID (insn)]
3932 = FENCE_CYCLE (fence) + need_cycles;
3934 stalled++;
3935 min_need_stall = (min_need_stall < 0
3936 ? need_cycles
3937 : MIN (min_need_stall, need_cycles));
3939 vec_av_set.unordered_remove (n);
3941 if (sched_verbose >= 4)
3942 sel_print ("Expr %d is not ready yet until cycle %d\n",
3943 INSN_UID (insn),
3944 FENCE_READY_TICKS (fence)[INSN_UID (insn)]);
3945 continue;
3948 if (sched_verbose >= 4)
3949 sel_print ("Expr %d is ok\n", INSN_UID (insn));
3950 min_need_stall = 0;
3953 /* Clear SCHED_NEXT. */
3954 if (FENCE_SCHED_NEXT (fence))
3956 gcc_assert (sched_next_worked == 1);
3957 FENCE_SCHED_NEXT (fence) = NULL_RTX;
3960 /* No need to stall if this variable was not initialized. */
3961 if (min_need_stall < 0)
3962 min_need_stall = 0;
3964 if (vec_av_set.is_empty ())
3966 /* We need to set *pneed_stall here, because later we skip this code
3967 when ready list is empty. */
3968 *pneed_stall = min_need_stall;
3969 return false;
3971 else
3972 gcc_assert (min_need_stall == 0);
3974 /* Sort the vector. */
3975 vec_av_set.qsort (sel_rank_for_schedule);
3977 if (sched_verbose >= 4)
3979 sel_print ("Total ready exprs: %d, stalled: %d\n",
3980 vec_av_set.length (), stalled);
3981 sel_print ("Sorted av set (%d): ", vec_av_set.length ());
3982 FOR_EACH_VEC_ELT (vec_av_set, n, expr)
3983 dump_expr (expr);
3984 sel_print ("\n");
3987 *pneed_stall = 0;
3988 return true;
3991 /* Convert a vectored and sorted av set to the ready list that
3992 the rest of the backend wants to see. */
3993 static void
3994 convert_vec_av_set_to_ready (void)
3996 int n;
3997 expr_t expr;
3999 /* Allocate and fill the ready list from the sorted vector. */
4000 ready.n_ready = vec_av_set.length ();
4001 ready.first = ready.n_ready - 1;
4003 gcc_assert (ready.n_ready > 0);
4005 if (ready.n_ready > max_issue_size)
4007 max_issue_size = ready.n_ready;
4008 sched_extend_ready_list (ready.n_ready);
4011 FOR_EACH_VEC_ELT (vec_av_set, n, expr)
4013 vinsn_t vi = EXPR_VINSN (expr);
4014 insn_t insn = VINSN_INSN_RTX (vi);
4016 ready_try[n] = 0;
4017 ready.vec[n] = insn;
4021 /* Initialize ready list from *AV_PTR for the max_issue () call.
4022 If any unrecognizable insn found in *AV_PTR, return it (and skip
4023 max_issue). BND and FENCE are current boundary and fence,
4024 respectively. If we need to stall for some cycles before an expr
4025 from *AV_PTR would become available, write this number to *PNEED_STALL. */
4026 static expr_t
4027 fill_ready_list (av_set_t *av_ptr, blist_t bnds, fence_t fence,
4028 int *pneed_stall)
4030 expr_t expr;
4032 /* We do not support multiple boundaries per fence. */
4033 gcc_assert (BLIST_NEXT (bnds) == NULL);
4035 /* Process expressions required special handling, i.e. pipelined,
4036 speculative and recog() < 0 expressions first. */
4037 process_pipelined_exprs (av_ptr);
4038 process_spec_exprs (av_ptr);
4040 /* A USE could be scheduled immediately. */
4041 expr = process_use_exprs (av_ptr);
4042 if (expr)
4044 *pneed_stall = 0;
4045 return expr;
4048 /* Turn the av set to a vector for sorting. */
4049 if (! fill_vec_av_set (*av_ptr, bnds, fence, pneed_stall))
4051 ready.n_ready = 0;
4052 return NULL;
4055 /* Build the final ready list. */
4056 convert_vec_av_set_to_ready ();
4057 return NULL;
4060 /* Wrapper for dfa_new_cycle (). Returns TRUE if cycle was advanced. */
4061 static bool
4062 sel_dfa_new_cycle (insn_t insn, fence_t fence)
4064 int last_scheduled_cycle = FENCE_LAST_SCHEDULED_INSN (fence)
4065 ? INSN_SCHED_CYCLE (FENCE_LAST_SCHEDULED_INSN (fence))
4066 : FENCE_CYCLE (fence) - 1;
4067 bool res = false;
4068 int sort_p = 0;
4070 if (!targetm.sched.dfa_new_cycle)
4071 return false;
4073 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
4075 while (!sort_p && targetm.sched.dfa_new_cycle (sched_dump, sched_verbose,
4076 insn, last_scheduled_cycle,
4077 FENCE_CYCLE (fence), &sort_p))
4079 memcpy (FENCE_STATE (fence), curr_state, dfa_state_size);
4080 advance_one_cycle (fence);
4081 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
4082 res = true;
4085 return res;
4088 /* Invoke reorder* target hooks on the ready list. Return the number of insns
4089 we can issue. FENCE is the current fence. */
4090 static int
4091 invoke_reorder_hooks (fence_t fence)
4093 int issue_more;
4094 bool ran_hook = false;
4096 /* Call the reorder hook at the beginning of the cycle, and call
4097 the reorder2 hook in the middle of the cycle. */
4098 if (FENCE_ISSUED_INSNS (fence) == 0)
4100 if (targetm.sched.reorder
4101 && !SCHED_GROUP_P (ready_element (&ready, 0))
4102 && ready.n_ready > 1)
4104 /* Don't give reorder the most prioritized insn as it can break
4105 pipelining. */
4106 if (pipelining_p)
4107 --ready.n_ready;
4109 issue_more
4110 = targetm.sched.reorder (sched_dump, sched_verbose,
4111 ready_lastpos (&ready),
4112 &ready.n_ready, FENCE_CYCLE (fence));
4114 if (pipelining_p)
4115 ++ready.n_ready;
4117 ran_hook = true;
4119 else
4120 /* Initialize can_issue_more for variable_issue. */
4121 issue_more = issue_rate;
4123 else if (targetm.sched.reorder2
4124 && !SCHED_GROUP_P (ready_element (&ready, 0)))
4126 if (ready.n_ready == 1)
4127 issue_more =
4128 targetm.sched.reorder2 (sched_dump, sched_verbose,
4129 ready_lastpos (&ready),
4130 &ready.n_ready, FENCE_CYCLE (fence));
4131 else
4133 if (pipelining_p)
4134 --ready.n_ready;
4136 issue_more =
4137 targetm.sched.reorder2 (sched_dump, sched_verbose,
4138 ready.n_ready
4139 ? ready_lastpos (&ready) : NULL,
4140 &ready.n_ready, FENCE_CYCLE (fence));
4142 if (pipelining_p)
4143 ++ready.n_ready;
4146 ran_hook = true;
4148 else
4149 issue_more = FENCE_ISSUE_MORE (fence);
4151 /* Ensure that ready list and vec_av_set are in line with each other,
4152 i.e. vec_av_set[i] == ready_element (&ready, i). */
4153 if (issue_more && ran_hook)
4155 int i, j, n;
4156 rtx *arr = ready.vec;
4157 expr_t *vec = vec_av_set.address ();
4159 for (i = 0, n = ready.n_ready; i < n; i++)
4160 if (EXPR_INSN_RTX (vec[i]) != arr[i])
4162 expr_t tmp;
4164 for (j = i; j < n; j++)
4165 if (EXPR_INSN_RTX (vec[j]) == arr[i])
4166 break;
4167 gcc_assert (j < n);
4169 tmp = vec[i];
4170 vec[i] = vec[j];
4171 vec[j] = tmp;
4175 return issue_more;
4178 /* Return an EXPR corresponding to INDEX element of ready list, if
4179 FOLLOW_READY_ELEMENT is true (i.e., an expr of
4180 ready_element (&ready, INDEX) will be returned), and to INDEX element of
4181 ready.vec otherwise. */
4182 static inline expr_t
4183 find_expr_for_ready (int index, bool follow_ready_element)
4185 expr_t expr;
4186 int real_index;
4188 real_index = follow_ready_element ? ready.first - index : index;
4190 expr = vec_av_set[real_index];
4191 gcc_assert (ready.vec[real_index] == EXPR_INSN_RTX (expr));
4193 return expr;
4196 /* Calculate insns worth trying via lookahead_guard hook. Return a number
4197 of such insns found. */
4198 static int
4199 invoke_dfa_lookahead_guard (void)
4201 int i, n;
4202 bool have_hook
4203 = targetm.sched.first_cycle_multipass_dfa_lookahead_guard != NULL;
4205 if (sched_verbose >= 2)
4206 sel_print ("ready after reorder: ");
4208 for (i = 0, n = 0; i < ready.n_ready; i++)
4210 expr_t expr;
4211 insn_t insn;
4212 int r;
4214 /* In this loop insn is Ith element of the ready list given by
4215 ready_element, not Ith element of ready.vec. */
4216 insn = ready_element (&ready, i);
4218 if (! have_hook || i == 0)
4219 r = 0;
4220 else
4221 r = targetm.sched.first_cycle_multipass_dfa_lookahead_guard (insn, i);
4223 gcc_assert (INSN_CODE (insn) >= 0);
4225 /* Only insns with ready_try = 0 can get here
4226 from fill_ready_list. */
4227 gcc_assert (ready_try [i] == 0);
4228 ready_try[i] = r;
4229 if (!r)
4230 n++;
4232 expr = find_expr_for_ready (i, true);
4234 if (sched_verbose >= 2)
4236 dump_vinsn (EXPR_VINSN (expr));
4237 sel_print (":%d; ", ready_try[i]);
4241 if (sched_verbose >= 2)
4242 sel_print ("\n");
4243 return n;
4246 /* Calculate the number of privileged insns and return it. */
4247 static int
4248 calculate_privileged_insns (void)
4250 expr_t cur_expr, min_spec_expr = NULL;
4251 int privileged_n = 0, i;
4253 for (i = 0; i < ready.n_ready; i++)
4255 if (ready_try[i])
4256 continue;
4258 if (! min_spec_expr)
4259 min_spec_expr = find_expr_for_ready (i, true);
4261 cur_expr = find_expr_for_ready (i, true);
4263 if (EXPR_SPEC (cur_expr) > EXPR_SPEC (min_spec_expr))
4264 break;
4266 ++privileged_n;
4269 if (i == ready.n_ready)
4270 privileged_n = 0;
4272 if (sched_verbose >= 2)
4273 sel_print ("privileged_n: %d insns with SPEC %d\n",
4274 privileged_n, privileged_n ? EXPR_SPEC (min_spec_expr) : -1);
4275 return privileged_n;
4278 /* Call the rest of the hooks after the choice was made. Return
4279 the number of insns that still can be issued given that the current
4280 number is ISSUE_MORE. FENCE and BEST_INSN are the current fence
4281 and the insn chosen for scheduling, respectively. */
4282 static int
4283 invoke_aftermath_hooks (fence_t fence, rtx best_insn, int issue_more)
4285 gcc_assert (INSN_P (best_insn));
4287 /* First, call dfa_new_cycle, and then variable_issue, if available. */
4288 sel_dfa_new_cycle (best_insn, fence);
4290 if (targetm.sched.variable_issue)
4292 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
4293 issue_more =
4294 targetm.sched.variable_issue (sched_dump, sched_verbose, best_insn,
4295 issue_more);
4296 memcpy (FENCE_STATE (fence), curr_state, dfa_state_size);
4298 else if (GET_CODE (PATTERN (best_insn)) != USE
4299 && GET_CODE (PATTERN (best_insn)) != CLOBBER)
4300 issue_more--;
4302 return issue_more;
4305 /* Estimate the cost of issuing INSN on DFA state STATE. */
4306 static int
4307 estimate_insn_cost (rtx insn, state_t state)
4309 static state_t temp = NULL;
4310 int cost;
4312 if (!temp)
4313 temp = xmalloc (dfa_state_size);
4315 memcpy (temp, state, dfa_state_size);
4316 cost = state_transition (temp, insn);
4318 if (cost < 0)
4319 return 0;
4320 else if (cost == 0)
4321 return 1;
4322 return cost;
4325 /* Return the cost of issuing EXPR on the FENCE as estimated by DFA.
4326 This function properly handles ASMs, USEs etc. */
4327 static int
4328 get_expr_cost (expr_t expr, fence_t fence)
4330 rtx insn = EXPR_INSN_RTX (expr);
4332 if (recog_memoized (insn) < 0)
4334 if (!FENCE_STARTS_CYCLE_P (fence)
4335 && INSN_ASM_P (insn))
4336 /* This is asm insn which is tryed to be issued on the
4337 cycle not first. Issue it on the next cycle. */
4338 return 1;
4339 else
4340 /* A USE insn, or something else we don't need to
4341 understand. We can't pass these directly to
4342 state_transition because it will trigger a
4343 fatal error for unrecognizable insns. */
4344 return 0;
4346 else
4347 return estimate_insn_cost (insn, FENCE_STATE (fence));
4350 /* Find the best insn for scheduling, either via max_issue or just take
4351 the most prioritized available. */
4352 static int
4353 choose_best_insn (fence_t fence, int privileged_n, int *index)
4355 int can_issue = 0;
4357 if (dfa_lookahead > 0)
4359 cycle_issued_insns = FENCE_ISSUED_INSNS (fence);
4360 /* TODO: pass equivalent of first_cycle_insn_p to max_issue (). */
4361 can_issue = max_issue (&ready, privileged_n,
4362 FENCE_STATE (fence), true, index);
4363 if (sched_verbose >= 2)
4364 sel_print ("max_issue: we can issue %d insns, already did %d insns\n",
4365 can_issue, FENCE_ISSUED_INSNS (fence));
4367 else
4369 /* We can't use max_issue; just return the first available element. */
4370 int i;
4372 for (i = 0; i < ready.n_ready; i++)
4374 expr_t expr = find_expr_for_ready (i, true);
4376 if (get_expr_cost (expr, fence) < 1)
4378 can_issue = can_issue_more;
4379 *index = i;
4381 if (sched_verbose >= 2)
4382 sel_print ("using %dth insn from the ready list\n", i + 1);
4384 break;
4388 if (i == ready.n_ready)
4390 can_issue = 0;
4391 *index = -1;
4395 return can_issue;
4398 /* Choose the best expr from *AV_VLIW_PTR and a suitable register for it.
4399 BNDS and FENCE are current boundaries and scheduling fence respectively.
4400 Return the expr found and NULL if nothing can be issued atm.
4401 Write to PNEED_STALL the number of cycles to stall if no expr was found. */
4402 static expr_t
4403 find_best_expr (av_set_t *av_vliw_ptr, blist_t bnds, fence_t fence,
4404 int *pneed_stall)
4406 expr_t best;
4408 /* Choose the best insn for scheduling via:
4409 1) sorting the ready list based on priority;
4410 2) calling the reorder hook;
4411 3) calling max_issue. */
4412 best = fill_ready_list (av_vliw_ptr, bnds, fence, pneed_stall);
4413 if (best == NULL && ready.n_ready > 0)
4415 int privileged_n, index;
4417 can_issue_more = invoke_reorder_hooks (fence);
4418 if (can_issue_more > 0)
4420 /* Try choosing the best insn until we find one that is could be
4421 scheduled due to liveness restrictions on its destination register.
4422 In the future, we'd like to choose once and then just probe insns
4423 in the order of their priority. */
4424 invoke_dfa_lookahead_guard ();
4425 privileged_n = calculate_privileged_insns ();
4426 can_issue_more = choose_best_insn (fence, privileged_n, &index);
4427 if (can_issue_more)
4428 best = find_expr_for_ready (index, true);
4430 /* We had some available insns, so if we can't issue them,
4431 we have a stall. */
4432 if (can_issue_more == 0)
4434 best = NULL;
4435 *pneed_stall = 1;
4439 if (best != NULL)
4441 can_issue_more = invoke_aftermath_hooks (fence, EXPR_INSN_RTX (best),
4442 can_issue_more);
4443 if (targetm.sched.variable_issue
4444 && can_issue_more == 0)
4445 *pneed_stall = 1;
4448 if (sched_verbose >= 2)
4450 if (best != NULL)
4452 sel_print ("Best expression (vliw form): ");
4453 dump_expr (best);
4454 sel_print ("; cycle %d\n", FENCE_CYCLE (fence));
4456 else
4457 sel_print ("No best expr found!\n");
4460 return best;
4464 /* Functions that implement the core of the scheduler. */
4467 /* Emit an instruction from EXPR with SEQNO and VINSN after
4468 PLACE_TO_INSERT. */
4469 static insn_t
4470 emit_insn_from_expr_after (expr_t expr, vinsn_t vinsn, int seqno,
4471 insn_t place_to_insert)
4473 /* This assert fails when we have identical instructions
4474 one of which dominates the other. In this case move_op ()
4475 finds the first instruction and doesn't search for second one.
4476 The solution would be to compute av_set after the first found
4477 insn and, if insn present in that set, continue searching.
4478 For now we workaround this issue in move_op. */
4479 gcc_assert (!INSN_IN_STREAM_P (EXPR_INSN_RTX (expr)));
4481 if (EXPR_WAS_RENAMED (expr))
4483 unsigned regno = expr_dest_regno (expr);
4485 if (HARD_REGISTER_NUM_P (regno))
4487 df_set_regs_ever_live (regno, true);
4488 reg_rename_tick[regno] = ++reg_rename_this_tick;
4492 return sel_gen_insn_from_expr_after (expr, vinsn, seqno,
4493 place_to_insert);
4496 /* Return TRUE if BB can hold bookkeeping code. */
4497 static bool
4498 block_valid_for_bookkeeping_p (basic_block bb)
4500 insn_t bb_end = BB_END (bb);
4502 if (!in_current_region_p (bb) || EDGE_COUNT (bb->succs) > 1)
4503 return false;
4505 if (INSN_P (bb_end))
4507 if (INSN_SCHED_TIMES (bb_end) > 0)
4508 return false;
4510 else
4511 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (bb_end));
4513 return true;
4516 /* Attempt to find a block that can hold bookkeeping code for path(s) incoming
4517 into E2->dest, except from E1->src (there may be a sequence of empty basic
4518 blocks between E1->src and E2->dest). Return found block, or NULL if new
4519 one must be created. If LAX holds, don't assume there is a simple path
4520 from E1->src to E2->dest. */
4521 static basic_block
4522 find_block_for_bookkeeping (edge e1, edge e2, bool lax)
4524 basic_block candidate_block = NULL;
4525 edge e;
4527 /* Loop over edges from E1 to E2, inclusive. */
4528 for (e = e1; !lax || e->dest != EXIT_BLOCK_PTR_FOR_FN (cfun); e =
4529 EDGE_SUCC (e->dest, 0))
4531 if (EDGE_COUNT (e->dest->preds) == 2)
4533 if (candidate_block == NULL)
4534 candidate_block = (EDGE_PRED (e->dest, 0) == e
4535 ? EDGE_PRED (e->dest, 1)->src
4536 : EDGE_PRED (e->dest, 0)->src);
4537 else
4538 /* Found additional edge leading to path from e1 to e2
4539 from aside. */
4540 return NULL;
4542 else if (EDGE_COUNT (e->dest->preds) > 2)
4543 /* Several edges leading to path from e1 to e2 from aside. */
4544 return NULL;
4546 if (e == e2)
4547 return ((!lax || candidate_block)
4548 && block_valid_for_bookkeeping_p (candidate_block)
4549 ? candidate_block
4550 : NULL);
4552 if (lax && EDGE_COUNT (e->dest->succs) != 1)
4553 return NULL;
4556 if (lax)
4557 return NULL;
4559 gcc_unreachable ();
4562 /* Create new basic block for bookkeeping code for path(s) incoming into
4563 E2->dest, except from E1->src. Return created block. */
4564 static basic_block
4565 create_block_for_bookkeeping (edge e1, edge e2)
4567 basic_block new_bb, bb = e2->dest;
4569 /* Check that we don't spoil the loop structure. */
4570 if (current_loop_nest)
4572 basic_block latch = current_loop_nest->latch;
4574 /* We do not split header. */
4575 gcc_assert (e2->dest != current_loop_nest->header);
4577 /* We do not redirect the only edge to the latch block. */
4578 gcc_assert (e1->dest != latch
4579 || !single_pred_p (latch)
4580 || e1 != single_pred_edge (latch));
4583 /* Split BB to insert BOOK_INSN there. */
4584 new_bb = sched_split_block (bb, NULL);
4586 /* Move note_list from the upper bb. */
4587 gcc_assert (BB_NOTE_LIST (new_bb) == NULL_RTX);
4588 BB_NOTE_LIST (new_bb) = BB_NOTE_LIST (bb);
4589 BB_NOTE_LIST (bb) = NULL_RTX;
4591 gcc_assert (e2->dest == bb);
4593 /* Skip block for bookkeeping copy when leaving E1->src. */
4594 if (e1->flags & EDGE_FALLTHRU)
4595 sel_redirect_edge_and_branch_force (e1, new_bb);
4596 else
4597 sel_redirect_edge_and_branch (e1, new_bb);
4599 gcc_assert (e1->dest == new_bb);
4600 gcc_assert (sel_bb_empty_p (bb));
4602 /* To keep basic block numbers in sync between debug and non-debug
4603 compilations, we have to rotate blocks here. Consider that we
4604 started from (a,b)->d, (c,d)->e, and d contained only debug
4605 insns. It would have been removed before if the debug insns
4606 weren't there, so we'd have split e rather than d. So what we do
4607 now is to swap the block numbers of new_bb and
4608 single_succ(new_bb) == e, so that the insns that were in e before
4609 get the new block number. */
4611 if (MAY_HAVE_DEBUG_INSNS)
4613 basic_block succ;
4614 insn_t insn = sel_bb_head (new_bb);
4615 insn_t last;
4617 if (DEBUG_INSN_P (insn)
4618 && single_succ_p (new_bb)
4619 && (succ = single_succ (new_bb))
4620 && succ != EXIT_BLOCK_PTR_FOR_FN (cfun)
4621 && DEBUG_INSN_P ((last = sel_bb_end (new_bb))))
4623 while (insn != last && (DEBUG_INSN_P (insn) || NOTE_P (insn)))
4624 insn = NEXT_INSN (insn);
4626 if (insn == last)
4628 sel_global_bb_info_def gbi;
4629 sel_region_bb_info_def rbi;
4630 int i;
4632 if (sched_verbose >= 2)
4633 sel_print ("Swapping block ids %i and %i\n",
4634 new_bb->index, succ->index);
4636 i = new_bb->index;
4637 new_bb->index = succ->index;
4638 succ->index = i;
4640 SET_BASIC_BLOCK_FOR_FN (cfun, new_bb->index, new_bb);
4641 SET_BASIC_BLOCK_FOR_FN (cfun, succ->index, succ);
4643 memcpy (&gbi, SEL_GLOBAL_BB_INFO (new_bb), sizeof (gbi));
4644 memcpy (SEL_GLOBAL_BB_INFO (new_bb), SEL_GLOBAL_BB_INFO (succ),
4645 sizeof (gbi));
4646 memcpy (SEL_GLOBAL_BB_INFO (succ), &gbi, sizeof (gbi));
4648 memcpy (&rbi, SEL_REGION_BB_INFO (new_bb), sizeof (rbi));
4649 memcpy (SEL_REGION_BB_INFO (new_bb), SEL_REGION_BB_INFO (succ),
4650 sizeof (rbi));
4651 memcpy (SEL_REGION_BB_INFO (succ), &rbi, sizeof (rbi));
4653 i = BLOCK_TO_BB (new_bb->index);
4654 BLOCK_TO_BB (new_bb->index) = BLOCK_TO_BB (succ->index);
4655 BLOCK_TO_BB (succ->index) = i;
4657 i = CONTAINING_RGN (new_bb->index);
4658 CONTAINING_RGN (new_bb->index) = CONTAINING_RGN (succ->index);
4659 CONTAINING_RGN (succ->index) = i;
4661 for (i = 0; i < current_nr_blocks; i++)
4662 if (BB_TO_BLOCK (i) == succ->index)
4663 BB_TO_BLOCK (i) = new_bb->index;
4664 else if (BB_TO_BLOCK (i) == new_bb->index)
4665 BB_TO_BLOCK (i) = succ->index;
4667 FOR_BB_INSNS (new_bb, insn)
4668 if (INSN_P (insn))
4669 EXPR_ORIG_BB_INDEX (INSN_EXPR (insn)) = new_bb->index;
4671 FOR_BB_INSNS (succ, insn)
4672 if (INSN_P (insn))
4673 EXPR_ORIG_BB_INDEX (INSN_EXPR (insn)) = succ->index;
4675 if (bitmap_clear_bit (code_motion_visited_blocks, new_bb->index))
4676 bitmap_set_bit (code_motion_visited_blocks, succ->index);
4678 gcc_assert (LABEL_P (BB_HEAD (new_bb))
4679 && LABEL_P (BB_HEAD (succ)));
4681 if (sched_verbose >= 4)
4682 sel_print ("Swapping code labels %i and %i\n",
4683 CODE_LABEL_NUMBER (BB_HEAD (new_bb)),
4684 CODE_LABEL_NUMBER (BB_HEAD (succ)));
4686 i = CODE_LABEL_NUMBER (BB_HEAD (new_bb));
4687 CODE_LABEL_NUMBER (BB_HEAD (new_bb))
4688 = CODE_LABEL_NUMBER (BB_HEAD (succ));
4689 CODE_LABEL_NUMBER (BB_HEAD (succ)) = i;
4694 return bb;
4697 /* Return insn after which we must insert bookkeeping code for path(s) incoming
4698 into E2->dest, except from E1->src. If the returned insn immediately
4699 precedes a fence, assign that fence to *FENCE_TO_REWIND. */
4700 static insn_t
4701 find_place_for_bookkeeping (edge e1, edge e2, fence_t *fence_to_rewind)
4703 insn_t place_to_insert;
4704 /* Find a basic block that can hold bookkeeping. If it can be found, do not
4705 create new basic block, but insert bookkeeping there. */
4706 basic_block book_block = find_block_for_bookkeeping (e1, e2, FALSE);
4708 if (book_block)
4710 place_to_insert = BB_END (book_block);
4712 /* Don't use a block containing only debug insns for
4713 bookkeeping, this causes scheduling differences between debug
4714 and non-debug compilations, for the block would have been
4715 removed already. */
4716 if (DEBUG_INSN_P (place_to_insert))
4718 rtx insn = sel_bb_head (book_block);
4720 while (insn != place_to_insert &&
4721 (DEBUG_INSN_P (insn) || NOTE_P (insn)))
4722 insn = NEXT_INSN (insn);
4724 if (insn == place_to_insert)
4725 book_block = NULL;
4729 if (!book_block)
4731 book_block = create_block_for_bookkeeping (e1, e2);
4732 place_to_insert = BB_END (book_block);
4733 if (sched_verbose >= 9)
4734 sel_print ("New block is %i, split from bookkeeping block %i\n",
4735 EDGE_SUCC (book_block, 0)->dest->index, book_block->index);
4737 else
4739 if (sched_verbose >= 9)
4740 sel_print ("Pre-existing bookkeeping block is %i\n", book_block->index);
4743 *fence_to_rewind = NULL;
4744 /* If basic block ends with a jump, insert bookkeeping code right before it.
4745 Notice if we are crossing a fence when taking PREV_INSN. */
4746 if (INSN_P (place_to_insert) && control_flow_insn_p (place_to_insert))
4748 *fence_to_rewind = flist_lookup (fences, place_to_insert);
4749 place_to_insert = PREV_INSN (place_to_insert);
4752 return place_to_insert;
4755 /* Find a proper seqno for bookkeeing insn inserted at PLACE_TO_INSERT
4756 for JOIN_POINT. */
4757 static int
4758 find_seqno_for_bookkeeping (insn_t place_to_insert, insn_t join_point)
4760 int seqno;
4761 rtx next;
4763 /* Check if we are about to insert bookkeeping copy before a jump, and use
4764 jump's seqno for the copy; otherwise, use JOIN_POINT's seqno. */
4765 next = NEXT_INSN (place_to_insert);
4766 if (INSN_P (next)
4767 && JUMP_P (next)
4768 && BLOCK_FOR_INSN (next) == BLOCK_FOR_INSN (place_to_insert))
4770 gcc_assert (INSN_SCHED_TIMES (next) == 0);
4771 seqno = INSN_SEQNO (next);
4773 else if (INSN_SEQNO (join_point) > 0)
4774 seqno = INSN_SEQNO (join_point);
4775 else
4777 seqno = get_seqno_by_preds (place_to_insert);
4779 /* Sometimes the fences can move in such a way that there will be
4780 no instructions with positive seqno around this bookkeeping.
4781 This means that there will be no way to get to it by a regular
4782 fence movement. Never mind because we pick up such pieces for
4783 rescheduling anyways, so any positive value will do for now. */
4784 if (seqno < 0)
4786 gcc_assert (pipelining_p);
4787 seqno = 1;
4791 gcc_assert (seqno > 0);
4792 return seqno;
4795 /* Insert bookkeeping copy of C_EXPS's insn after PLACE_TO_INSERT, assigning
4796 NEW_SEQNO to it. Return created insn. */
4797 static insn_t
4798 emit_bookkeeping_insn (insn_t place_to_insert, expr_t c_expr, int new_seqno)
4800 rtx new_insn_rtx = create_copy_of_insn_rtx (EXPR_INSN_RTX (c_expr));
4802 vinsn_t new_vinsn
4803 = create_vinsn_from_insn_rtx (new_insn_rtx,
4804 VINSN_UNIQUE_P (EXPR_VINSN (c_expr)));
4806 insn_t new_insn = emit_insn_from_expr_after (c_expr, new_vinsn, new_seqno,
4807 place_to_insert);
4809 INSN_SCHED_TIMES (new_insn) = 0;
4810 bitmap_set_bit (current_copies, INSN_UID (new_insn));
4812 return new_insn;
4815 /* Generate a bookkeeping copy of C_EXPR's insn for path(s) incoming into to
4816 E2->dest, except from E1->src (there may be a sequence of empty blocks
4817 between E1->src and E2->dest). Return block containing the copy.
4818 All scheduler data is initialized for the newly created insn. */
4819 static basic_block
4820 generate_bookkeeping_insn (expr_t c_expr, edge e1, edge e2)
4822 insn_t join_point, place_to_insert, new_insn;
4823 int new_seqno;
4824 bool need_to_exchange_data_sets;
4825 fence_t fence_to_rewind;
4827 if (sched_verbose >= 4)
4828 sel_print ("Generating bookkeeping insn (%d->%d)\n", e1->src->index,
4829 e2->dest->index);
4831 join_point = sel_bb_head (e2->dest);
4832 place_to_insert = find_place_for_bookkeeping (e1, e2, &fence_to_rewind);
4833 new_seqno = find_seqno_for_bookkeeping (place_to_insert, join_point);
4834 need_to_exchange_data_sets
4835 = sel_bb_empty_p (BLOCK_FOR_INSN (place_to_insert));
4837 new_insn = emit_bookkeeping_insn (place_to_insert, c_expr, new_seqno);
4839 if (fence_to_rewind)
4840 FENCE_INSN (fence_to_rewind) = new_insn;
4842 /* When inserting bookkeeping insn in new block, av sets should be
4843 following: old basic block (that now holds bookkeeping) data sets are
4844 the same as was before generation of bookkeeping, and new basic block
4845 (that now hold all other insns of old basic block) data sets are
4846 invalid. So exchange data sets for these basic blocks as sel_split_block
4847 mistakenly exchanges them in this case. Cannot do it earlier because
4848 when single instruction is added to new basic block it should hold NULL
4849 lv_set. */
4850 if (need_to_exchange_data_sets)
4851 exchange_data_sets (BLOCK_FOR_INSN (new_insn),
4852 BLOCK_FOR_INSN (join_point));
4854 stat_bookkeeping_copies++;
4855 return BLOCK_FOR_INSN (new_insn);
4858 /* Remove from AV_PTR all insns that may need bookkeeping when scheduling
4859 on FENCE, but we are unable to copy them. */
4860 static void
4861 remove_insns_that_need_bookkeeping (fence_t fence, av_set_t *av_ptr)
4863 expr_t expr;
4864 av_set_iterator i;
4866 /* An expression does not need bookkeeping if it is available on all paths
4867 from current block to original block and current block dominates
4868 original block. We check availability on all paths by examining
4869 EXPR_SPEC; this is not equivalent, because it may be positive even
4870 if expr is available on all paths (but if expr is not available on
4871 any path, EXPR_SPEC will be positive). */
4873 FOR_EACH_EXPR_1 (expr, i, av_ptr)
4875 if (!control_flow_insn_p (EXPR_INSN_RTX (expr))
4876 && (!bookkeeping_p || VINSN_UNIQUE_P (EXPR_VINSN (expr)))
4877 && (EXPR_SPEC (expr)
4878 || !EXPR_ORIG_BB_INDEX (expr)
4879 || !dominated_by_p (CDI_DOMINATORS,
4880 BASIC_BLOCK_FOR_FN (cfun,
4881 EXPR_ORIG_BB_INDEX (expr)),
4882 BLOCK_FOR_INSN (FENCE_INSN (fence)))))
4884 if (sched_verbose >= 4)
4885 sel_print ("Expr %d removed because it would need bookkeeping, which "
4886 "cannot be created\n", INSN_UID (EXPR_INSN_RTX (expr)));
4887 av_set_iter_remove (&i);
4892 /* Moving conditional jump through some instructions.
4894 Consider example:
4896 ... <- current scheduling point
4897 NOTE BASIC BLOCK: <- bb header
4898 (p8) add r14=r14+0x9;;
4899 (p8) mov [r14]=r23
4900 (!p8) jump L1;;
4901 NOTE BASIC BLOCK:
4904 We can schedule jump one cycle earlier, than mov, because they cannot be
4905 executed together as their predicates are mutually exclusive.
4907 This is done in this way: first, new fallthrough basic block is created
4908 after jump (it is always can be done, because there already should be a
4909 fallthrough block, where control flow goes in case of predicate being true -
4910 in our example; otherwise there should be a dependence between those
4911 instructions and jump and we cannot schedule jump right now);
4912 next, all instructions between jump and current scheduling point are moved
4913 to this new block. And the result is this:
4915 NOTE BASIC BLOCK:
4916 (!p8) jump L1 <- current scheduling point
4917 NOTE BASIC BLOCK: <- bb header
4918 (p8) add r14=r14+0x9;;
4919 (p8) mov [r14]=r23
4920 NOTE BASIC BLOCK:
4923 static void
4924 move_cond_jump (rtx insn, bnd_t bnd)
4926 edge ft_edge;
4927 basic_block block_from, block_next, block_new, block_bnd, bb;
4928 rtx next, prev, link, head;
4930 block_from = BLOCK_FOR_INSN (insn);
4931 block_bnd = BLOCK_FOR_INSN (BND_TO (bnd));
4932 prev = BND_TO (bnd);
4934 #ifdef ENABLE_CHECKING
4935 /* Moving of jump should not cross any other jumps or beginnings of new
4936 basic blocks. The only exception is when we move a jump through
4937 mutually exclusive insns along fallthru edges. */
4938 if (block_from != block_bnd)
4940 bb = block_from;
4941 for (link = PREV_INSN (insn); link != PREV_INSN (prev);
4942 link = PREV_INSN (link))
4944 if (INSN_P (link))
4945 gcc_assert (sched_insns_conditions_mutex_p (insn, link));
4946 if (BLOCK_FOR_INSN (link) && BLOCK_FOR_INSN (link) != bb)
4948 gcc_assert (single_pred (bb) == BLOCK_FOR_INSN (link));
4949 bb = BLOCK_FOR_INSN (link);
4953 #endif
4955 /* Jump is moved to the boundary. */
4956 next = PREV_INSN (insn);
4957 BND_TO (bnd) = insn;
4959 ft_edge = find_fallthru_edge_from (block_from);
4960 block_next = ft_edge->dest;
4961 /* There must be a fallthrough block (or where should go
4962 control flow in case of false jump predicate otherwise?). */
4963 gcc_assert (block_next);
4965 /* Create new empty basic block after source block. */
4966 block_new = sel_split_edge (ft_edge);
4967 gcc_assert (block_new->next_bb == block_next
4968 && block_from->next_bb == block_new);
4970 /* Move all instructions except INSN to BLOCK_NEW. */
4971 bb = block_bnd;
4972 head = BB_HEAD (block_new);
4973 while (bb != block_from->next_bb)
4975 rtx from, to;
4976 from = bb == block_bnd ? prev : sel_bb_head (bb);
4977 to = bb == block_from ? next : sel_bb_end (bb);
4979 /* The jump being moved can be the first insn in the block.
4980 In this case we don't have to move anything in this block. */
4981 if (NEXT_INSN (to) != from)
4983 reorder_insns (from, to, head);
4985 for (link = to; link != head; link = PREV_INSN (link))
4986 EXPR_ORIG_BB_INDEX (INSN_EXPR (link)) = block_new->index;
4987 head = to;
4990 /* Cleanup possibly empty blocks left. */
4991 block_next = bb->next_bb;
4992 if (bb != block_from)
4993 tidy_control_flow (bb, false);
4994 bb = block_next;
4997 /* Assert there is no jump to BLOCK_NEW, only fallthrough edge. */
4998 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (BB_HEAD (block_new)));
5000 gcc_assert (!sel_bb_empty_p (block_from)
5001 && !sel_bb_empty_p (block_new));
5003 /* Update data sets for BLOCK_NEW to represent that INSN and
5004 instructions from the other branch of INSN is no longer
5005 available at BLOCK_NEW. */
5006 BB_AV_LEVEL (block_new) = global_level;
5007 gcc_assert (BB_LV_SET (block_new) == NULL);
5008 BB_LV_SET (block_new) = get_clear_regset_from_pool ();
5009 update_data_sets (sel_bb_head (block_new));
5011 /* INSN is a new basic block header - so prepare its data
5012 structures and update availability and liveness sets. */
5013 update_data_sets (insn);
5015 if (sched_verbose >= 4)
5016 sel_print ("Moving jump %d\n", INSN_UID (insn));
5019 /* Remove nops generated during move_op for preventing removal of empty
5020 basic blocks. */
5021 static void
5022 remove_temp_moveop_nops (bool full_tidying)
5024 int i;
5025 insn_t insn;
5027 FOR_EACH_VEC_ELT (vec_temp_moveop_nops, i, insn)
5029 gcc_assert (INSN_NOP_P (insn));
5030 return_nop_to_pool (insn, full_tidying);
5033 /* Empty the vector. */
5034 if (vec_temp_moveop_nops.length () > 0)
5035 vec_temp_moveop_nops.block_remove (0, vec_temp_moveop_nops.length ());
5038 /* Records the maximal UID before moving up an instruction. Used for
5039 distinguishing between bookkeeping copies and original insns. */
5040 static int max_uid_before_move_op = 0;
5042 /* Remove from AV_VLIW_P all instructions but next when debug counter
5043 tells us so. Next instruction is fetched from BNDS. */
5044 static void
5045 remove_insns_for_debug (blist_t bnds, av_set_t *av_vliw_p)
5047 if (! dbg_cnt (sel_sched_insn_cnt))
5048 /* Leave only the next insn in av_vliw. */
5050 av_set_iterator av_it;
5051 expr_t expr;
5052 bnd_t bnd = BLIST_BND (bnds);
5053 insn_t next = BND_TO (bnd);
5055 gcc_assert (BLIST_NEXT (bnds) == NULL);
5057 FOR_EACH_EXPR_1 (expr, av_it, av_vliw_p)
5058 if (EXPR_INSN_RTX (expr) != next)
5059 av_set_iter_remove (&av_it);
5063 /* Compute available instructions on BNDS. FENCE is the current fence. Write
5064 the computed set to *AV_VLIW_P. */
5065 static void
5066 compute_av_set_on_boundaries (fence_t fence, blist_t bnds, av_set_t *av_vliw_p)
5068 if (sched_verbose >= 2)
5070 sel_print ("Boundaries: ");
5071 dump_blist (bnds);
5072 sel_print ("\n");
5075 for (; bnds; bnds = BLIST_NEXT (bnds))
5077 bnd_t bnd = BLIST_BND (bnds);
5078 av_set_t av1_copy;
5079 insn_t bnd_to = BND_TO (bnd);
5081 /* Rewind BND->TO to the basic block header in case some bookkeeping
5082 instructions were inserted before BND->TO and it needs to be
5083 adjusted. */
5084 if (sel_bb_head_p (bnd_to))
5085 gcc_assert (INSN_SCHED_TIMES (bnd_to) == 0);
5086 else
5087 while (INSN_SCHED_TIMES (PREV_INSN (bnd_to)) == 0)
5089 bnd_to = PREV_INSN (bnd_to);
5090 if (sel_bb_head_p (bnd_to))
5091 break;
5094 if (BND_TO (bnd) != bnd_to)
5096 gcc_assert (FENCE_INSN (fence) == BND_TO (bnd));
5097 FENCE_INSN (fence) = bnd_to;
5098 BND_TO (bnd) = bnd_to;
5101 av_set_clear (&BND_AV (bnd));
5102 BND_AV (bnd) = compute_av_set (BND_TO (bnd), NULL, 0, true);
5104 av_set_clear (&BND_AV1 (bnd));
5105 BND_AV1 (bnd) = av_set_copy (BND_AV (bnd));
5107 moveup_set_inside_insn_group (&BND_AV1 (bnd), NULL);
5109 av1_copy = av_set_copy (BND_AV1 (bnd));
5110 av_set_union_and_clear (av_vliw_p, &av1_copy, NULL);
5113 if (sched_verbose >= 2)
5115 sel_print ("Available exprs (vliw form): ");
5116 dump_av_set (*av_vliw_p);
5117 sel_print ("\n");
5121 /* Calculate the sequential av set on BND corresponding to the EXPR_VLIW
5122 expression. When FOR_MOVEOP is true, also replace the register of
5123 expressions found with the register from EXPR_VLIW. */
5124 static av_set_t
5125 find_sequential_best_exprs (bnd_t bnd, expr_t expr_vliw, bool for_moveop)
5127 av_set_t expr_seq = NULL;
5128 expr_t expr;
5129 av_set_iterator i;
5131 FOR_EACH_EXPR (expr, i, BND_AV (bnd))
5133 if (equal_after_moveup_path_p (expr, NULL, expr_vliw))
5135 if (for_moveop)
5137 /* The sequential expression has the right form to pass
5138 to move_op except when renaming happened. Put the
5139 correct register in EXPR then. */
5140 if (EXPR_SEPARABLE_P (expr) && REG_P (EXPR_LHS (expr)))
5142 if (expr_dest_regno (expr) != expr_dest_regno (expr_vliw))
5144 replace_dest_with_reg_in_expr (expr, EXPR_LHS (expr_vliw));
5145 stat_renamed_scheduled++;
5147 /* Also put the correct TARGET_AVAILABLE bit on the expr.
5148 This is needed when renaming came up with original
5149 register. */
5150 else if (EXPR_TARGET_AVAILABLE (expr)
5151 != EXPR_TARGET_AVAILABLE (expr_vliw))
5153 gcc_assert (EXPR_TARGET_AVAILABLE (expr_vliw) == 1);
5154 EXPR_TARGET_AVAILABLE (expr) = 1;
5157 if (EXPR_WAS_SUBSTITUTED (expr))
5158 stat_substitutions_total++;
5161 av_set_add (&expr_seq, expr);
5163 /* With substitution inside insn group, it is possible
5164 that more than one expression in expr_seq will correspond
5165 to expr_vliw. In this case, choose one as the attempt to
5166 move both leads to miscompiles. */
5167 break;
5171 if (for_moveop && sched_verbose >= 2)
5173 sel_print ("Best expression(s) (sequential form): ");
5174 dump_av_set (expr_seq);
5175 sel_print ("\n");
5178 return expr_seq;
5182 /* Move nop to previous block. */
5183 static void ATTRIBUTE_UNUSED
5184 move_nop_to_previous_block (insn_t nop, basic_block prev_bb)
5186 insn_t prev_insn, next_insn, note;
5188 gcc_assert (sel_bb_head_p (nop)
5189 && prev_bb == BLOCK_FOR_INSN (nop)->prev_bb);
5190 note = bb_note (BLOCK_FOR_INSN (nop));
5191 prev_insn = sel_bb_end (prev_bb);
5192 next_insn = NEXT_INSN (nop);
5193 gcc_assert (prev_insn != NULL_RTX
5194 && PREV_INSN (note) == prev_insn);
5196 NEXT_INSN (prev_insn) = nop;
5197 PREV_INSN (nop) = prev_insn;
5199 PREV_INSN (note) = nop;
5200 NEXT_INSN (note) = next_insn;
5202 NEXT_INSN (nop) = note;
5203 PREV_INSN (next_insn) = note;
5205 BB_END (prev_bb) = nop;
5206 BLOCK_FOR_INSN (nop) = prev_bb;
5209 /* Prepare a place to insert the chosen expression on BND. */
5210 static insn_t
5211 prepare_place_to_insert (bnd_t bnd)
5213 insn_t place_to_insert;
5215 /* Init place_to_insert before calling move_op, as the later
5216 can possibly remove BND_TO (bnd). */
5217 if (/* If this is not the first insn scheduled. */
5218 BND_PTR (bnd))
5220 /* Add it after last scheduled. */
5221 place_to_insert = ILIST_INSN (BND_PTR (bnd));
5222 if (DEBUG_INSN_P (place_to_insert))
5224 ilist_t l = BND_PTR (bnd);
5225 while ((l = ILIST_NEXT (l)) &&
5226 DEBUG_INSN_P (ILIST_INSN (l)))
5228 if (!l)
5229 place_to_insert = NULL;
5232 else
5233 place_to_insert = NULL;
5235 if (!place_to_insert)
5237 /* Add it before BND_TO. The difference is in the
5238 basic block, where INSN will be added. */
5239 place_to_insert = get_nop_from_pool (BND_TO (bnd));
5240 gcc_assert (BLOCK_FOR_INSN (place_to_insert)
5241 == BLOCK_FOR_INSN (BND_TO (bnd)));
5244 return place_to_insert;
5247 /* Find original instructions for EXPR_SEQ and move it to BND boundary.
5248 Return the expression to emit in C_EXPR. */
5249 static bool
5250 move_exprs_to_boundary (bnd_t bnd, expr_t expr_vliw,
5251 av_set_t expr_seq, expr_t c_expr)
5253 bool b, should_move;
5254 unsigned book_uid;
5255 bitmap_iterator bi;
5256 int n_bookkeeping_copies_before_moveop;
5258 /* Make a move. This call will remove the original operation,
5259 insert all necessary bookkeeping instructions and update the
5260 data sets. After that all we have to do is add the operation
5261 at before BND_TO (BND). */
5262 n_bookkeeping_copies_before_moveop = stat_bookkeeping_copies;
5263 max_uid_before_move_op = get_max_uid ();
5264 bitmap_clear (current_copies);
5265 bitmap_clear (current_originators);
5267 b = move_op (BND_TO (bnd), expr_seq, expr_vliw,
5268 get_dest_from_orig_ops (expr_seq), c_expr, &should_move);
5270 /* We should be able to find the expression we've chosen for
5271 scheduling. */
5272 gcc_assert (b);
5274 if (stat_bookkeeping_copies > n_bookkeeping_copies_before_moveop)
5275 stat_insns_needed_bookkeeping++;
5277 EXECUTE_IF_SET_IN_BITMAP (current_copies, 0, book_uid, bi)
5279 unsigned uid;
5280 bitmap_iterator bi;
5282 /* We allocate these bitmaps lazily. */
5283 if (! INSN_ORIGINATORS_BY_UID (book_uid))
5284 INSN_ORIGINATORS_BY_UID (book_uid) = BITMAP_ALLOC (NULL);
5286 bitmap_copy (INSN_ORIGINATORS_BY_UID (book_uid),
5287 current_originators);
5289 /* Transitively add all originators' originators. */
5290 EXECUTE_IF_SET_IN_BITMAP (current_originators, 0, uid, bi)
5291 if (INSN_ORIGINATORS_BY_UID (uid))
5292 bitmap_ior_into (INSN_ORIGINATORS_BY_UID (book_uid),
5293 INSN_ORIGINATORS_BY_UID (uid));
5296 return should_move;
5300 /* Debug a DFA state as an array of bytes. */
5301 static void
5302 debug_state (state_t state)
5304 unsigned char *p;
5305 unsigned int i, size = dfa_state_size;
5307 sel_print ("state (%u):", size);
5308 for (i = 0, p = (unsigned char *) state; i < size; i++)
5309 sel_print (" %d", p[i]);
5310 sel_print ("\n");
5313 /* Advance state on FENCE with INSN. Return true if INSN is
5314 an ASM, and we should advance state once more. */
5315 static bool
5316 advance_state_on_fence (fence_t fence, insn_t insn)
5318 bool asm_p;
5320 if (recog_memoized (insn) >= 0)
5322 int res;
5323 state_t temp_state = alloca (dfa_state_size);
5325 gcc_assert (!INSN_ASM_P (insn));
5326 asm_p = false;
5328 memcpy (temp_state, FENCE_STATE (fence), dfa_state_size);
5329 res = state_transition (FENCE_STATE (fence), insn);
5330 gcc_assert (res < 0);
5332 if (memcmp (temp_state, FENCE_STATE (fence), dfa_state_size))
5334 FENCE_ISSUED_INSNS (fence)++;
5336 /* We should never issue more than issue_rate insns. */
5337 if (FENCE_ISSUED_INSNS (fence) > issue_rate)
5338 gcc_unreachable ();
5341 else
5343 /* This could be an ASM insn which we'd like to schedule
5344 on the next cycle. */
5345 asm_p = INSN_ASM_P (insn);
5346 if (!FENCE_STARTS_CYCLE_P (fence) && asm_p)
5347 advance_one_cycle (fence);
5350 if (sched_verbose >= 2)
5351 debug_state (FENCE_STATE (fence));
5352 if (!DEBUG_INSN_P (insn))
5353 FENCE_STARTS_CYCLE_P (fence) = 0;
5354 FENCE_ISSUE_MORE (fence) = can_issue_more;
5355 return asm_p;
5358 /* Update FENCE on which INSN was scheduled and this INSN, too. NEED_STALL
5359 is nonzero if we need to stall after issuing INSN. */
5360 static void
5361 update_fence_and_insn (fence_t fence, insn_t insn, int need_stall)
5363 bool asm_p;
5365 /* First, reflect that something is scheduled on this fence. */
5366 asm_p = advance_state_on_fence (fence, insn);
5367 FENCE_LAST_SCHEDULED_INSN (fence) = insn;
5368 vec_safe_push (FENCE_EXECUTING_INSNS (fence), insn);
5369 if (SCHED_GROUP_P (insn))
5371 FENCE_SCHED_NEXT (fence) = INSN_SCHED_NEXT (insn);
5372 SCHED_GROUP_P (insn) = 0;
5374 else
5375 FENCE_SCHED_NEXT (fence) = NULL_RTX;
5376 if (INSN_UID (insn) < FENCE_READY_TICKS_SIZE (fence))
5377 FENCE_READY_TICKS (fence) [INSN_UID (insn)] = 0;
5379 /* Set instruction scheduling info. This will be used in bundling,
5380 pipelining, tick computations etc. */
5381 ++INSN_SCHED_TIMES (insn);
5382 EXPR_TARGET_AVAILABLE (INSN_EXPR (insn)) = true;
5383 EXPR_ORIG_SCHED_CYCLE (INSN_EXPR (insn)) = FENCE_CYCLE (fence);
5384 INSN_AFTER_STALL_P (insn) = FENCE_AFTER_STALL_P (fence);
5385 INSN_SCHED_CYCLE (insn) = FENCE_CYCLE (fence);
5387 /* This does not account for adjust_cost hooks, just add the biggest
5388 constant the hook may add to the latency. TODO: make this
5389 a target dependent constant. */
5390 INSN_READY_CYCLE (insn)
5391 = INSN_SCHED_CYCLE (insn) + (INSN_CODE (insn) < 0
5393 : maximal_insn_latency (insn) + 1);
5395 /* Change these fields last, as they're used above. */
5396 FENCE_AFTER_STALL_P (fence) = 0;
5397 if (asm_p || need_stall)
5398 advance_one_cycle (fence);
5400 /* Indicate that we've scheduled something on this fence. */
5401 FENCE_SCHEDULED_P (fence) = true;
5402 scheduled_something_on_previous_fence = true;
5404 /* Print debug information when insn's fields are updated. */
5405 if (sched_verbose >= 2)
5407 sel_print ("Scheduling insn: ");
5408 dump_insn_1 (insn, 1);
5409 sel_print ("\n");
5413 /* Update boundary BND (and, if needed, FENCE) with INSN, remove the
5414 old boundary from BNDSP, add new boundaries to BNDS_TAIL_P and
5415 return it. */
5416 static blist_t *
5417 update_boundaries (fence_t fence, bnd_t bnd, insn_t insn, blist_t *bndsp,
5418 blist_t *bnds_tailp)
5420 succ_iterator si;
5421 insn_t succ;
5423 advance_deps_context (BND_DC (bnd), insn);
5424 FOR_EACH_SUCC_1 (succ, si, insn,
5425 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
5427 ilist_t ptr = ilist_copy (BND_PTR (bnd));
5429 ilist_add (&ptr, insn);
5431 if (DEBUG_INSN_P (insn) && sel_bb_end_p (insn)
5432 && is_ineligible_successor (succ, ptr))
5434 ilist_clear (&ptr);
5435 continue;
5438 if (FENCE_INSN (fence) == insn && !sel_bb_end_p (insn))
5440 if (sched_verbose >= 9)
5441 sel_print ("Updating fence insn from %i to %i\n",
5442 INSN_UID (insn), INSN_UID (succ));
5443 FENCE_INSN (fence) = succ;
5445 blist_add (bnds_tailp, succ, ptr, BND_DC (bnd));
5446 bnds_tailp = &BLIST_NEXT (*bnds_tailp);
5449 blist_remove (bndsp);
5450 return bnds_tailp;
5453 /* Schedule EXPR_VLIW on BND. Return the insn emitted. */
5454 static insn_t
5455 schedule_expr_on_boundary (bnd_t bnd, expr_t expr_vliw, int seqno)
5457 av_set_t expr_seq;
5458 expr_t c_expr = XALLOCA (expr_def);
5459 insn_t place_to_insert;
5460 insn_t insn;
5461 bool should_move;
5463 expr_seq = find_sequential_best_exprs (bnd, expr_vliw, true);
5465 /* In case of scheduling a jump skipping some other instructions,
5466 prepare CFG. After this, jump is at the boundary and can be
5467 scheduled as usual insn by MOVE_OP. */
5468 if (vinsn_cond_branch_p (EXPR_VINSN (expr_vliw)))
5470 insn = EXPR_INSN_RTX (expr_vliw);
5472 /* Speculative jumps are not handled. */
5473 if (insn != BND_TO (bnd)
5474 && !sel_insn_is_speculation_check (insn))
5475 move_cond_jump (insn, bnd);
5478 /* Find a place for C_EXPR to schedule. */
5479 place_to_insert = prepare_place_to_insert (bnd);
5480 should_move = move_exprs_to_boundary (bnd, expr_vliw, expr_seq, c_expr);
5481 clear_expr (c_expr);
5483 /* Add the instruction. The corner case to care about is when
5484 the expr_seq set has more than one expr, and we chose the one that
5485 is not equal to expr_vliw. Then expr_vliw may be insn in stream, and
5486 we can't use it. Generate the new vinsn. */
5487 if (INSN_IN_STREAM_P (EXPR_INSN_RTX (expr_vliw)))
5489 vinsn_t vinsn_new;
5491 vinsn_new = vinsn_copy (EXPR_VINSN (expr_vliw), false);
5492 change_vinsn_in_expr (expr_vliw, vinsn_new);
5493 should_move = false;
5495 if (should_move)
5496 insn = sel_move_insn (expr_vliw, seqno, place_to_insert);
5497 else
5498 insn = emit_insn_from_expr_after (expr_vliw, NULL, seqno,
5499 place_to_insert);
5501 /* Return the nops generated for preserving of data sets back
5502 into pool. */
5503 if (INSN_NOP_P (place_to_insert))
5504 return_nop_to_pool (place_to_insert, !DEBUG_INSN_P (insn));
5505 remove_temp_moveop_nops (!DEBUG_INSN_P (insn));
5507 av_set_clear (&expr_seq);
5509 /* Save the expression scheduled so to reset target availability if we'll
5510 meet it later on the same fence. */
5511 if (EXPR_WAS_RENAMED (expr_vliw))
5512 vinsn_vec_add (&vec_target_unavailable_vinsns, INSN_EXPR (insn));
5514 /* Check that the recent movement didn't destroyed loop
5515 structure. */
5516 gcc_assert (!pipelining_p
5517 || current_loop_nest == NULL
5518 || loop_latch_edge (current_loop_nest));
5519 return insn;
5522 /* Stall for N cycles on FENCE. */
5523 static void
5524 stall_for_cycles (fence_t fence, int n)
5526 int could_more;
5528 could_more = n > 1 || FENCE_ISSUED_INSNS (fence) < issue_rate;
5529 while (n--)
5530 advance_one_cycle (fence);
5531 if (could_more)
5532 FENCE_AFTER_STALL_P (fence) = 1;
5535 /* Gather a parallel group of insns at FENCE and assign their seqno
5536 to SEQNO. All scheduled insns are gathered in SCHEDULED_INSNS_TAILPP
5537 list for later recalculation of seqnos. */
5538 static void
5539 fill_insns (fence_t fence, int seqno, ilist_t **scheduled_insns_tailpp)
5541 blist_t bnds = NULL, *bnds_tailp;
5542 av_set_t av_vliw = NULL;
5543 insn_t insn = FENCE_INSN (fence);
5545 if (sched_verbose >= 2)
5546 sel_print ("Starting fill_insns for insn %d, cycle %d\n",
5547 INSN_UID (insn), FENCE_CYCLE (fence));
5549 blist_add (&bnds, insn, NULL, FENCE_DC (fence));
5550 bnds_tailp = &BLIST_NEXT (bnds);
5551 set_target_context (FENCE_TC (fence));
5552 can_issue_more = FENCE_ISSUE_MORE (fence);
5553 target_bb = INSN_BB (insn);
5555 /* Do while we can add any operation to the current group. */
5558 blist_t *bnds_tailp1, *bndsp;
5559 expr_t expr_vliw;
5560 int need_stall = false;
5561 int was_stall = 0, scheduled_insns = 0;
5562 int max_insns = pipelining_p ? issue_rate : 2 * issue_rate;
5563 int max_stall = pipelining_p ? 1 : 3;
5564 bool last_insn_was_debug = false;
5565 bool was_debug_bb_end_p = false;
5567 compute_av_set_on_boundaries (fence, bnds, &av_vliw);
5568 remove_insns_that_need_bookkeeping (fence, &av_vliw);
5569 remove_insns_for_debug (bnds, &av_vliw);
5571 /* Return early if we have nothing to schedule. */
5572 if (av_vliw == NULL)
5573 break;
5575 /* Choose the best expression and, if needed, destination register
5576 for it. */
5579 expr_vliw = find_best_expr (&av_vliw, bnds, fence, &need_stall);
5580 if (! expr_vliw && need_stall)
5582 /* All expressions required a stall. Do not recompute av sets
5583 as we'll get the same answer (modulo the insns between
5584 the fence and its boundary, which will not be available for
5585 pipelining).
5586 If we are going to stall for too long, break to recompute av
5587 sets and bring more insns for pipelining. */
5588 was_stall++;
5589 if (need_stall <= 3)
5590 stall_for_cycles (fence, need_stall);
5591 else
5593 stall_for_cycles (fence, 1);
5594 break;
5598 while (! expr_vliw && need_stall);
5600 /* Now either we've selected expr_vliw or we have nothing to schedule. */
5601 if (!expr_vliw)
5603 av_set_clear (&av_vliw);
5604 break;
5607 bndsp = &bnds;
5608 bnds_tailp1 = bnds_tailp;
5611 /* This code will be executed only once until we'd have several
5612 boundaries per fence. */
5614 bnd_t bnd = BLIST_BND (*bndsp);
5616 if (!av_set_is_in_p (BND_AV1 (bnd), EXPR_VINSN (expr_vliw)))
5618 bndsp = &BLIST_NEXT (*bndsp);
5619 continue;
5622 insn = schedule_expr_on_boundary (bnd, expr_vliw, seqno);
5623 last_insn_was_debug = DEBUG_INSN_P (insn);
5624 if (last_insn_was_debug)
5625 was_debug_bb_end_p = (insn == BND_TO (bnd) && sel_bb_end_p (insn));
5626 update_fence_and_insn (fence, insn, need_stall);
5627 bnds_tailp = update_boundaries (fence, bnd, insn, bndsp, bnds_tailp);
5629 /* Add insn to the list of scheduled on this cycle instructions. */
5630 ilist_add (*scheduled_insns_tailpp, insn);
5631 *scheduled_insns_tailpp = &ILIST_NEXT (**scheduled_insns_tailpp);
5633 while (*bndsp != *bnds_tailp1);
5635 av_set_clear (&av_vliw);
5636 if (!last_insn_was_debug)
5637 scheduled_insns++;
5639 /* We currently support information about candidate blocks only for
5640 one 'target_bb' block. Hence we can't schedule after jump insn,
5641 as this will bring two boundaries and, hence, necessity to handle
5642 information for two or more blocks concurrently. */
5643 if ((last_insn_was_debug ? was_debug_bb_end_p : sel_bb_end_p (insn))
5644 || (was_stall
5645 && (was_stall >= max_stall
5646 || scheduled_insns >= max_insns)))
5647 break;
5649 while (bnds);
5651 gcc_assert (!FENCE_BNDS (fence));
5653 /* Update boundaries of the FENCE. */
5654 while (bnds)
5656 ilist_t ptr = BND_PTR (BLIST_BND (bnds));
5658 if (ptr)
5660 insn = ILIST_INSN (ptr);
5662 if (!ilist_is_in_p (FENCE_BNDS (fence), insn))
5663 ilist_add (&FENCE_BNDS (fence), insn);
5666 blist_remove (&bnds);
5669 /* Update target context on the fence. */
5670 reset_target_context (FENCE_TC (fence), false);
5673 /* All exprs in ORIG_OPS must have the same destination register or memory.
5674 Return that destination. */
5675 static rtx
5676 get_dest_from_orig_ops (av_set_t orig_ops)
5678 rtx dest = NULL_RTX;
5679 av_set_iterator av_it;
5680 expr_t expr;
5681 bool first_p = true;
5683 FOR_EACH_EXPR (expr, av_it, orig_ops)
5685 rtx x = EXPR_LHS (expr);
5687 if (first_p)
5689 first_p = false;
5690 dest = x;
5692 else
5693 gcc_assert (dest == x
5694 || (dest != NULL_RTX && x != NULL_RTX
5695 && rtx_equal_p (dest, x)));
5698 return dest;
5701 /* Update data sets for the bookkeeping block and record those expressions
5702 which become no longer available after inserting this bookkeeping. */
5703 static void
5704 update_and_record_unavailable_insns (basic_block book_block)
5706 av_set_iterator i;
5707 av_set_t old_av_set = NULL;
5708 expr_t cur_expr;
5709 rtx bb_end = sel_bb_end (book_block);
5711 /* First, get correct liveness in the bookkeeping block. The problem is
5712 the range between the bookeeping insn and the end of block. */
5713 update_liveness_on_insn (bb_end);
5714 if (control_flow_insn_p (bb_end))
5715 update_liveness_on_insn (PREV_INSN (bb_end));
5717 /* If there's valid av_set on BOOK_BLOCK, then there might exist another
5718 fence above, where we may choose to schedule an insn which is
5719 actually blocked from moving up with the bookkeeping we create here. */
5720 if (AV_SET_VALID_P (sel_bb_head (book_block)))
5722 old_av_set = av_set_copy (BB_AV_SET (book_block));
5723 update_data_sets (sel_bb_head (book_block));
5725 /* Traverse all the expressions in the old av_set and check whether
5726 CUR_EXPR is in new AV_SET. */
5727 FOR_EACH_EXPR (cur_expr, i, old_av_set)
5729 expr_t new_expr = av_set_lookup (BB_AV_SET (book_block),
5730 EXPR_VINSN (cur_expr));
5732 if (! new_expr
5733 /* In this case, we can just turn off the E_T_A bit, but we can't
5734 represent this information with the current vector. */
5735 || EXPR_TARGET_AVAILABLE (new_expr)
5736 != EXPR_TARGET_AVAILABLE (cur_expr))
5737 /* Unfortunately, the below code could be also fired up on
5738 separable insns, e.g. when moving insns through the new
5739 speculation check as in PR 53701. */
5740 vinsn_vec_add (&vec_bookkeeping_blocked_vinsns, cur_expr);
5743 av_set_clear (&old_av_set);
5747 /* The main effect of this function is that sparams->c_expr is merged
5748 with (or copied to) lparams->c_expr_merged. If there's only one successor,
5749 we avoid merging anything by copying sparams->c_expr to lparams->c_expr_merged.
5750 lparams->c_expr_merged is copied back to sparams->c_expr after all
5751 successors has been traversed. lparams->c_expr_local is an expr allocated
5752 on stack in the caller function, and is used if there is more than one
5753 successor.
5755 SUCC is one of the SUCCS_NORMAL successors of INSN,
5756 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ,
5757 LPARAMS and STATIC_PARAMS contain the parameters described above. */
5758 static void
5759 move_op_merge_succs (insn_t insn ATTRIBUTE_UNUSED,
5760 insn_t succ ATTRIBUTE_UNUSED,
5761 int moveop_drv_call_res,
5762 cmpd_local_params_p lparams, void *static_params)
5764 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
5766 /* Nothing to do, if original expr wasn't found below. */
5767 if (moveop_drv_call_res != 1)
5768 return;
5770 /* If this is a first successor. */
5771 if (!lparams->c_expr_merged)
5773 lparams->c_expr_merged = sparams->c_expr;
5774 sparams->c_expr = lparams->c_expr_local;
5776 else
5778 /* We must merge all found expressions to get reasonable
5779 EXPR_SPEC_DONE_DS for the resulting insn. If we don't
5780 do so then we can first find the expr with epsilon
5781 speculation success probability and only then with the
5782 good probability. As a result the insn will get epsilon
5783 probability and will never be scheduled because of
5784 weakness_cutoff in find_best_expr.
5786 We call merge_expr_data here instead of merge_expr
5787 because due to speculation C_EXPR and X may have the
5788 same insns with different speculation types. And as of
5789 now such insns are considered non-equal.
5791 However, EXPR_SCHED_TIMES is different -- we must get
5792 SCHED_TIMES from a real insn, not a bookkeeping copy.
5793 We force this here. Instead, we may consider merging
5794 SCHED_TIMES to the maximum instead of minimum in the
5795 below function. */
5796 int old_times = EXPR_SCHED_TIMES (lparams->c_expr_merged);
5798 merge_expr_data (lparams->c_expr_merged, sparams->c_expr, NULL);
5799 if (EXPR_SCHED_TIMES (sparams->c_expr) == 0)
5800 EXPR_SCHED_TIMES (lparams->c_expr_merged) = old_times;
5802 clear_expr (sparams->c_expr);
5806 /* Add used regs for the successor SUCC into SPARAMS->USED_REGS.
5808 SUCC is one of the SUCCS_NORMAL successors of INSN,
5809 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ or 0,
5810 if SUCC is one of SUCCS_BACK or SUCCS_OUT.
5811 STATIC_PARAMS contain USED_REGS set. */
5812 static void
5813 fur_merge_succs (insn_t insn ATTRIBUTE_UNUSED, insn_t succ,
5814 int moveop_drv_call_res,
5815 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
5816 void *static_params)
5818 regset succ_live;
5819 fur_static_params_p sparams = (fur_static_params_p) static_params;
5821 /* Here we compute live regsets only for branches that do not lie
5822 on the code motion paths. These branches correspond to value
5823 MOVEOP_DRV_CALL_RES==0 and include SUCCS_BACK and SUCCS_OUT, though
5824 for such branches code_motion_path_driver is not called. */
5825 if (moveop_drv_call_res != 0)
5826 return;
5828 /* Mark all registers that do not meet the following condition:
5829 (3) not live on the other path of any conditional branch
5830 that is passed by the operation, in case original
5831 operations are not present on both paths of the
5832 conditional branch. */
5833 succ_live = compute_live (succ);
5834 IOR_REG_SET (sparams->used_regs, succ_live);
5837 /* This function is called after the last successor. Copies LP->C_EXPR_MERGED
5838 into SP->CEXPR. */
5839 static void
5840 move_op_after_merge_succs (cmpd_local_params_p lp, void *sparams)
5842 moveop_static_params_p sp = (moveop_static_params_p) sparams;
5844 sp->c_expr = lp->c_expr_merged;
5847 /* Track bookkeeping copies created, insns scheduled, and blocks for
5848 rescheduling when INSN is found by move_op. */
5849 static void
5850 track_scheduled_insns_and_blocks (rtx insn)
5852 /* Even if this insn can be a copy that will be removed during current move_op,
5853 we still need to count it as an originator. */
5854 bitmap_set_bit (current_originators, INSN_UID (insn));
5856 if (!bitmap_clear_bit (current_copies, INSN_UID (insn)))
5858 /* Note that original block needs to be rescheduled, as we pulled an
5859 instruction out of it. */
5860 if (INSN_SCHED_TIMES (insn) > 0)
5861 bitmap_set_bit (blocks_to_reschedule, BLOCK_FOR_INSN (insn)->index);
5862 else if (INSN_UID (insn) < first_emitted_uid && !DEBUG_INSN_P (insn))
5863 num_insns_scheduled++;
5866 /* For instructions we must immediately remove insn from the
5867 stream, so subsequent update_data_sets () won't include this
5868 insn into av_set.
5869 For expr we must make insn look like "INSN_REG (insn) := c_expr". */
5870 if (INSN_UID (insn) > max_uid_before_move_op)
5871 stat_bookkeeping_copies--;
5874 /* Emit a register-register copy for INSN if needed. Return true if
5875 emitted one. PARAMS is the move_op static parameters. */
5876 static bool
5877 maybe_emit_renaming_copy (rtx insn,
5878 moveop_static_params_p params)
5880 bool insn_emitted = false;
5881 rtx cur_reg;
5883 /* Bail out early when expression can not be renamed at all. */
5884 if (!EXPR_SEPARABLE_P (params->c_expr))
5885 return false;
5887 cur_reg = expr_dest_reg (params->c_expr);
5888 gcc_assert (cur_reg && params->dest && REG_P (params->dest));
5890 /* If original operation has expr and the register chosen for
5891 that expr is not original operation's dest reg, substitute
5892 operation's right hand side with the register chosen. */
5893 if (REGNO (params->dest) != REGNO (cur_reg))
5895 insn_t reg_move_insn, reg_move_insn_rtx;
5897 reg_move_insn_rtx = create_insn_rtx_with_rhs (INSN_VINSN (insn),
5898 params->dest);
5899 reg_move_insn = sel_gen_insn_from_rtx_after (reg_move_insn_rtx,
5900 INSN_EXPR (insn),
5901 INSN_SEQNO (insn),
5902 insn);
5903 EXPR_SPEC_DONE_DS (INSN_EXPR (reg_move_insn)) = 0;
5904 replace_dest_with_reg_in_expr (params->c_expr, params->dest);
5906 insn_emitted = true;
5907 params->was_renamed = true;
5910 return insn_emitted;
5913 /* Emit a speculative check for INSN speculated as EXPR if needed.
5914 Return true if we've emitted one. PARAMS is the move_op static
5915 parameters. */
5916 static bool
5917 maybe_emit_speculative_check (rtx insn, expr_t expr,
5918 moveop_static_params_p params)
5920 bool insn_emitted = false;
5921 insn_t x;
5922 ds_t check_ds;
5924 check_ds = get_spec_check_type_for_insn (insn, expr);
5925 if (check_ds != 0)
5927 /* A speculation check should be inserted. */
5928 x = create_speculation_check (params->c_expr, check_ds, insn);
5929 insn_emitted = true;
5931 else
5933 EXPR_SPEC_DONE_DS (INSN_EXPR (insn)) = 0;
5934 x = insn;
5937 gcc_assert (EXPR_SPEC_DONE_DS (INSN_EXPR (x)) == 0
5938 && EXPR_SPEC_TO_CHECK_DS (INSN_EXPR (x)) == 0);
5939 return insn_emitted;
5942 /* Handle transformations that leave an insn in place of original
5943 insn such as renaming/speculation. Return true if one of such
5944 transformations actually happened, and we have emitted this insn. */
5945 static bool
5946 handle_emitting_transformations (rtx insn, expr_t expr,
5947 moveop_static_params_p params)
5949 bool insn_emitted = false;
5951 insn_emitted = maybe_emit_renaming_copy (insn, params);
5952 insn_emitted |= maybe_emit_speculative_check (insn, expr, params);
5954 return insn_emitted;
5957 /* If INSN is the only insn in the basic block (not counting JUMP,
5958 which may be a jump to next insn, and DEBUG_INSNs), we want to
5959 leave a NOP there till the return to fill_insns. */
5961 static bool
5962 need_nop_to_preserve_insn_bb (rtx insn)
5964 insn_t bb_head, bb_end, bb_next, in_next;
5965 basic_block bb = BLOCK_FOR_INSN (insn);
5967 bb_head = sel_bb_head (bb);
5968 bb_end = sel_bb_end (bb);
5970 if (bb_head == bb_end)
5971 return true;
5973 while (bb_head != bb_end && DEBUG_INSN_P (bb_head))
5974 bb_head = NEXT_INSN (bb_head);
5976 if (bb_head == bb_end)
5977 return true;
5979 while (bb_head != bb_end && DEBUG_INSN_P (bb_end))
5980 bb_end = PREV_INSN (bb_end);
5982 if (bb_head == bb_end)
5983 return true;
5985 bb_next = NEXT_INSN (bb_head);
5986 while (bb_next != bb_end && DEBUG_INSN_P (bb_next))
5987 bb_next = NEXT_INSN (bb_next);
5989 if (bb_next == bb_end && JUMP_P (bb_end))
5990 return true;
5992 in_next = NEXT_INSN (insn);
5993 while (DEBUG_INSN_P (in_next))
5994 in_next = NEXT_INSN (in_next);
5996 if (IN_CURRENT_FENCE_P (in_next))
5997 return true;
5999 return false;
6002 /* Remove INSN from stream. When ONLY_DISCONNECT is true, its data
6003 is not removed but reused when INSN is re-emitted. */
6004 static void
6005 remove_insn_from_stream (rtx insn, bool only_disconnect)
6007 /* If there's only one insn in the BB, make sure that a nop is
6008 inserted into it, so the basic block won't disappear when we'll
6009 delete INSN below with sel_remove_insn. It should also survive
6010 till the return to fill_insns. */
6011 if (need_nop_to_preserve_insn_bb (insn))
6013 insn_t nop = get_nop_from_pool (insn);
6014 gcc_assert (INSN_NOP_P (nop));
6015 vec_temp_moveop_nops.safe_push (nop);
6018 sel_remove_insn (insn, only_disconnect, false);
6021 /* This function is called when original expr is found.
6022 INSN - current insn traversed, EXPR - the corresponding expr found.
6023 LPARAMS is the local parameters of code modion driver, STATIC_PARAMS
6024 is static parameters of move_op. */
6025 static void
6026 move_op_orig_expr_found (insn_t insn, expr_t expr,
6027 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
6028 void *static_params)
6030 bool only_disconnect;
6031 moveop_static_params_p params = (moveop_static_params_p) static_params;
6033 copy_expr_onside (params->c_expr, INSN_EXPR (insn));
6034 track_scheduled_insns_and_blocks (insn);
6035 handle_emitting_transformations (insn, expr, params);
6036 only_disconnect = params->uid == INSN_UID (insn);
6038 /* Mark that we've disconnected an insn. */
6039 if (only_disconnect)
6040 params->uid = -1;
6041 remove_insn_from_stream (insn, only_disconnect);
6044 /* The function is called when original expr is found.
6045 INSN - current insn traversed, EXPR - the corresponding expr found,
6046 crosses_call and original_insns in STATIC_PARAMS are updated. */
6047 static void
6048 fur_orig_expr_found (insn_t insn, expr_t expr ATTRIBUTE_UNUSED,
6049 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
6050 void *static_params)
6052 fur_static_params_p params = (fur_static_params_p) static_params;
6053 regset tmp;
6055 if (CALL_P (insn))
6056 params->crosses_call = true;
6058 def_list_add (params->original_insns, insn, params->crosses_call);
6060 /* Mark the registers that do not meet the following condition:
6061 (2) not among the live registers of the point
6062 immediately following the first original operation on
6063 a given downward path, except for the original target
6064 register of the operation. */
6065 tmp = get_clear_regset_from_pool ();
6066 compute_live_below_insn (insn, tmp);
6067 AND_COMPL_REG_SET (tmp, INSN_REG_SETS (insn));
6068 AND_COMPL_REG_SET (tmp, INSN_REG_CLOBBERS (insn));
6069 IOR_REG_SET (params->used_regs, tmp);
6070 return_regset_to_pool (tmp);
6072 /* (*1) We need to add to USED_REGS registers that are read by
6073 INSN's lhs. This may lead to choosing wrong src register.
6074 E.g. (scheduling const expr enabled):
6076 429: ax=0x0 <- Can't use AX for this expr (0x0)
6077 433: dx=[bp-0x18]
6078 427: [ax+dx+0x1]=ax
6079 REG_DEAD: ax
6080 168: di=dx
6081 REG_DEAD: dx
6083 /* FIXME: see comment above and enable MEM_P
6084 in vinsn_separable_p. */
6085 gcc_assert (!VINSN_SEPARABLE_P (INSN_VINSN (insn))
6086 || !MEM_P (INSN_LHS (insn)));
6089 /* This function is called on the ascending pass, before returning from
6090 current basic block. */
6091 static void
6092 move_op_at_first_insn (insn_t insn, cmpd_local_params_p lparams,
6093 void *static_params)
6095 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
6096 basic_block book_block = NULL;
6098 /* When we have removed the boundary insn for scheduling, which also
6099 happened to be the end insn in its bb, we don't need to update sets. */
6100 if (!lparams->removed_last_insn
6101 && lparams->e1
6102 && sel_bb_head_p (insn))
6104 /* We should generate bookkeeping code only if we are not at the
6105 top level of the move_op. */
6106 if (sel_num_cfg_preds_gt_1 (insn))
6107 book_block = generate_bookkeeping_insn (sparams->c_expr,
6108 lparams->e1, lparams->e2);
6109 /* Update data sets for the current insn. */
6110 update_data_sets (insn);
6113 /* If bookkeeping code was inserted, we need to update av sets of basic
6114 block that received bookkeeping. After generation of bookkeeping insn,
6115 bookkeeping block does not contain valid av set because we are not following
6116 the original algorithm in every detail with regards to e.g. renaming
6117 simple reg-reg copies. Consider example:
6119 bookkeeping block scheduling fence
6121 \ join /
6122 ----------
6124 ----------
6127 r1 := r2 r1 := r3
6129 We try to schedule insn "r1 := r3" on the current
6130 scheduling fence. Also, note that av set of bookkeeping block
6131 contain both insns "r1 := r2" and "r1 := r3". When the insn has
6132 been scheduled, the CFG is as follows:
6134 r1 := r3 r1 := r3
6135 bookkeeping block scheduling fence
6137 \ join /
6138 ----------
6140 ----------
6143 r1 := r2
6145 Here, insn "r1 := r3" was scheduled at the current scheduling point
6146 and bookkeeping code was generated at the bookeeping block. This
6147 way insn "r1 := r2" is no longer available as a whole instruction
6148 (but only as expr) ahead of insn "r1 := r3" in bookkeeping block.
6149 This situation is handled by calling update_data_sets.
6151 Since update_data_sets is called only on the bookkeeping block, and
6152 it also may have predecessors with av_sets, containing instructions that
6153 are no longer available, we save all such expressions that become
6154 unavailable during data sets update on the bookkeeping block in
6155 VEC_BOOKKEEPING_BLOCKED_VINSNS. Later we avoid selecting such
6156 expressions for scheduling. This allows us to avoid recomputation of
6157 av_sets outside the code motion path. */
6159 if (book_block)
6160 update_and_record_unavailable_insns (book_block);
6162 /* If INSN was previously marked for deletion, it's time to do it. */
6163 if (lparams->removed_last_insn)
6164 insn = PREV_INSN (insn);
6166 /* Do not tidy control flow at the topmost moveop, as we can erroneously
6167 kill a block with a single nop in which the insn should be emitted. */
6168 if (lparams->e1)
6169 tidy_control_flow (BLOCK_FOR_INSN (insn), true);
6172 /* This function is called on the ascending pass, before returning from the
6173 current basic block. */
6174 static void
6175 fur_at_first_insn (insn_t insn,
6176 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
6177 void *static_params ATTRIBUTE_UNUSED)
6179 gcc_assert (!sel_bb_head_p (insn) || AV_SET_VALID_P (insn)
6180 || AV_LEVEL (insn) == -1);
6183 /* Called on the backward stage of recursion to call moveup_expr for insn
6184 and sparams->c_expr. */
6185 static void
6186 move_op_ascend (insn_t insn, void *static_params)
6188 enum MOVEUP_EXPR_CODE res;
6189 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
6191 if (! INSN_NOP_P (insn))
6193 res = moveup_expr_cached (sparams->c_expr, insn, false);
6194 gcc_assert (res != MOVEUP_EXPR_NULL);
6197 /* Update liveness for this insn as it was invalidated. */
6198 update_liveness_on_insn (insn);
6201 /* This function is called on enter to the basic block.
6202 Returns TRUE if this block already have been visited and
6203 code_motion_path_driver should return 1, FALSE otherwise. */
6204 static int
6205 fur_on_enter (insn_t insn ATTRIBUTE_UNUSED, cmpd_local_params_p local_params,
6206 void *static_params, bool visited_p)
6208 fur_static_params_p sparams = (fur_static_params_p) static_params;
6210 if (visited_p)
6212 /* If we have found something below this block, there should be at
6213 least one insn in ORIGINAL_INSNS. */
6214 gcc_assert (*sparams->original_insns);
6216 /* Adjust CROSSES_CALL, since we may have come to this block along
6217 different path. */
6218 DEF_LIST_DEF (*sparams->original_insns)->crosses_call
6219 |= sparams->crosses_call;
6221 else
6222 local_params->old_original_insns = *sparams->original_insns;
6224 return 1;
6227 /* Same as above but for move_op. */
6228 static int
6229 move_op_on_enter (insn_t insn ATTRIBUTE_UNUSED,
6230 cmpd_local_params_p local_params ATTRIBUTE_UNUSED,
6231 void *static_params ATTRIBUTE_UNUSED, bool visited_p)
6233 if (visited_p)
6234 return -1;
6235 return 1;
6238 /* This function is called while descending current basic block if current
6239 insn is not the original EXPR we're searching for.
6241 Return value: FALSE, if code_motion_path_driver should perform a local
6242 cleanup and return 0 itself;
6243 TRUE, if code_motion_path_driver should continue. */
6244 static bool
6245 move_op_orig_expr_not_found (insn_t insn, av_set_t orig_ops ATTRIBUTE_UNUSED,
6246 void *static_params)
6248 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
6250 #ifdef ENABLE_CHECKING
6251 sparams->failed_insn = insn;
6252 #endif
6254 /* If we're scheduling separate expr, in order to generate correct code
6255 we need to stop the search at bookkeeping code generated with the
6256 same destination register or memory. */
6257 if (lhs_of_insn_equals_to_dest_p (insn, sparams->dest))
6258 return false;
6259 return true;
6262 /* This function is called while descending current basic block if current
6263 insn is not the original EXPR we're searching for.
6265 Return value: TRUE (code_motion_path_driver should continue). */
6266 static bool
6267 fur_orig_expr_not_found (insn_t insn, av_set_t orig_ops, void *static_params)
6269 bool mutexed;
6270 expr_t r;
6271 av_set_iterator avi;
6272 fur_static_params_p sparams = (fur_static_params_p) static_params;
6274 if (CALL_P (insn))
6275 sparams->crosses_call = true;
6276 else if (DEBUG_INSN_P (insn))
6277 return true;
6279 /* If current insn we are looking at cannot be executed together
6280 with original insn, then we can skip it safely.
6282 Example: ORIG_OPS = { (p6) r14 = sign_extend (r15); }
6283 INSN = (!p6) r14 = r14 + 1;
6285 Here we can schedule ORIG_OP with lhs = r14, though only
6286 looking at the set of used and set registers of INSN we must
6287 forbid it. So, add set/used in INSN registers to the
6288 untouchable set only if there is an insn in ORIG_OPS that can
6289 affect INSN. */
6290 mutexed = true;
6291 FOR_EACH_EXPR (r, avi, orig_ops)
6292 if (!sched_insns_conditions_mutex_p (insn, EXPR_INSN_RTX (r)))
6294 mutexed = false;
6295 break;
6298 /* Mark all registers that do not meet the following condition:
6299 (1) Not set or read on any path from xi to an instance of the
6300 original operation. */
6301 if (!mutexed)
6303 IOR_REG_SET (sparams->used_regs, INSN_REG_SETS (insn));
6304 IOR_REG_SET (sparams->used_regs, INSN_REG_USES (insn));
6305 IOR_REG_SET (sparams->used_regs, INSN_REG_CLOBBERS (insn));
6308 return true;
6311 /* Hooks and data to perform move_op operations with code_motion_path_driver. */
6312 struct code_motion_path_driver_info_def move_op_hooks = {
6313 move_op_on_enter,
6314 move_op_orig_expr_found,
6315 move_op_orig_expr_not_found,
6316 move_op_merge_succs,
6317 move_op_after_merge_succs,
6318 move_op_ascend,
6319 move_op_at_first_insn,
6320 SUCCS_NORMAL,
6321 "move_op"
6324 /* Hooks and data to perform find_used_regs operations
6325 with code_motion_path_driver. */
6326 struct code_motion_path_driver_info_def fur_hooks = {
6327 fur_on_enter,
6328 fur_orig_expr_found,
6329 fur_orig_expr_not_found,
6330 fur_merge_succs,
6331 NULL, /* fur_after_merge_succs */
6332 NULL, /* fur_ascend */
6333 fur_at_first_insn,
6334 SUCCS_ALL,
6335 "find_used_regs"
6338 /* Traverse all successors of INSN. For each successor that is SUCCS_NORMAL
6339 code_motion_path_driver is called recursively. Original operation
6340 was found at least on one path that is starting with one of INSN's
6341 successors (this fact is asserted). ORIG_OPS is expressions we're looking
6342 for, PATH is the path we've traversed, STATIC_PARAMS is the parameters
6343 of either move_op or find_used_regs depending on the caller.
6345 Return 0 if we haven't found expression, 1 if we found it, -1 if we don't
6346 know for sure at this point. */
6347 static int
6348 code_motion_process_successors (insn_t insn, av_set_t orig_ops,
6349 ilist_t path, void *static_params)
6351 int res = 0;
6352 succ_iterator succ_i;
6353 rtx succ;
6354 basic_block bb;
6355 int old_index;
6356 unsigned old_succs;
6358 struct cmpd_local_params lparams;
6359 expr_def _x;
6361 lparams.c_expr_local = &_x;
6362 lparams.c_expr_merged = NULL;
6364 /* We need to process only NORMAL succs for move_op, and collect live
6365 registers from ALL branches (including those leading out of the
6366 region) for find_used_regs.
6368 In move_op, there can be a case when insn's bb number has changed
6369 due to created bookkeeping. This happens very rare, as we need to
6370 move expression from the beginning to the end of the same block.
6371 Rescan successors in this case. */
6373 rescan:
6374 bb = BLOCK_FOR_INSN (insn);
6375 old_index = bb->index;
6376 old_succs = EDGE_COUNT (bb->succs);
6378 FOR_EACH_SUCC_1 (succ, succ_i, insn, code_motion_path_driver_info->succ_flags)
6380 int b;
6382 lparams.e1 = succ_i.e1;
6383 lparams.e2 = succ_i.e2;
6385 /* Go deep into recursion only for NORMAL edges (non-backedges within the
6386 current region). */
6387 if (succ_i.current_flags == SUCCS_NORMAL)
6388 b = code_motion_path_driver (succ, orig_ops, path, &lparams,
6389 static_params);
6390 else
6391 b = 0;
6393 /* Merge c_expres found or unify live register sets from different
6394 successors. */
6395 code_motion_path_driver_info->merge_succs (insn, succ, b, &lparams,
6396 static_params);
6397 if (b == 1)
6398 res = b;
6399 else if (b == -1 && res != 1)
6400 res = b;
6402 /* We have simplified the control flow below this point. In this case,
6403 the iterator becomes invalid. We need to try again.
6404 If we have removed the insn itself, it could be only an
6405 unconditional jump. Thus, do not rescan but break immediately --
6406 we have already visited the only successor block. */
6407 if (!BLOCK_FOR_INSN (insn))
6409 if (sched_verbose >= 6)
6410 sel_print ("Not doing rescan: already visited the only successor"
6411 " of block %d\n", old_index);
6412 break;
6414 if (BLOCK_FOR_INSN (insn)->index != old_index
6415 || EDGE_COUNT (bb->succs) != old_succs)
6417 if (sched_verbose >= 6)
6418 sel_print ("Rescan: CFG was simplified below insn %d, block %d\n",
6419 INSN_UID (insn), BLOCK_FOR_INSN (insn)->index);
6420 insn = sel_bb_end (BLOCK_FOR_INSN (insn));
6421 goto rescan;
6425 #ifdef ENABLE_CHECKING
6426 /* Here, RES==1 if original expr was found at least for one of the
6427 successors. After the loop, RES may happen to have zero value
6428 only if at some point the expr searched is present in av_set, but is
6429 not found below. In most cases, this situation is an error.
6430 The exception is when the original operation is blocked by
6431 bookkeeping generated for another fence or for another path in current
6432 move_op. */
6433 gcc_assert (res == 1
6434 || (res == 0
6435 && av_set_could_be_blocked_by_bookkeeping_p (orig_ops,
6436 static_params))
6437 || res == -1);
6438 #endif
6440 /* Merge data, clean up, etc. */
6441 if (res != -1 && code_motion_path_driver_info->after_merge_succs)
6442 code_motion_path_driver_info->after_merge_succs (&lparams, static_params);
6444 return res;
6448 /* Perform a cleanup when the driver is about to terminate. ORIG_OPS_P
6449 is the pointer to the av set with expressions we were looking for,
6450 PATH_P is the pointer to the traversed path. */
6451 static inline void
6452 code_motion_path_driver_cleanup (av_set_t *orig_ops_p, ilist_t *path_p)
6454 ilist_remove (path_p);
6455 av_set_clear (orig_ops_p);
6458 /* The driver function that implements move_op or find_used_regs
6459 functionality dependent whether code_motion_path_driver_INFO is set to
6460 &MOVE_OP_HOOKS or &FUR_HOOKS. This function implements the common parts
6461 of code (CFG traversal etc) that are shared among both functions. INSN
6462 is the insn we're starting the search from, ORIG_OPS are the expressions
6463 we're searching for, PATH is traversed path, LOCAL_PARAMS_IN are local
6464 parameters of the driver, and STATIC_PARAMS are static parameters of
6465 the caller.
6467 Returns whether original instructions were found. Note that top-level
6468 code_motion_path_driver always returns true. */
6469 static int
6470 code_motion_path_driver (insn_t insn, av_set_t orig_ops, ilist_t path,
6471 cmpd_local_params_p local_params_in,
6472 void *static_params)
6474 expr_t expr = NULL;
6475 basic_block bb = BLOCK_FOR_INSN (insn);
6476 insn_t first_insn, bb_tail, before_first;
6477 bool removed_last_insn = false;
6479 if (sched_verbose >= 6)
6481 sel_print ("%s (", code_motion_path_driver_info->routine_name);
6482 dump_insn (insn);
6483 sel_print (",");
6484 dump_av_set (orig_ops);
6485 sel_print (")\n");
6488 gcc_assert (orig_ops);
6490 /* If no original operations exist below this insn, return immediately. */
6491 if (is_ineligible_successor (insn, path))
6493 if (sched_verbose >= 6)
6494 sel_print ("Insn %d is ineligible successor\n", INSN_UID (insn));
6495 return false;
6498 /* The block can have invalid av set, in which case it was created earlier
6499 during move_op. Return immediately. */
6500 if (sel_bb_head_p (insn))
6502 if (! AV_SET_VALID_P (insn))
6504 if (sched_verbose >= 6)
6505 sel_print ("Returned from block %d as it had invalid av set\n",
6506 bb->index);
6507 return false;
6510 if (bitmap_bit_p (code_motion_visited_blocks, bb->index))
6512 /* We have already found an original operation on this branch, do not
6513 go any further and just return TRUE here. If we don't stop here,
6514 function can have exponential behaviour even on the small code
6515 with many different paths (e.g. with data speculation and
6516 recovery blocks). */
6517 if (sched_verbose >= 6)
6518 sel_print ("Block %d already visited in this traversal\n", bb->index);
6519 if (code_motion_path_driver_info->on_enter)
6520 return code_motion_path_driver_info->on_enter (insn,
6521 local_params_in,
6522 static_params,
6523 true);
6527 if (code_motion_path_driver_info->on_enter)
6528 code_motion_path_driver_info->on_enter (insn, local_params_in,
6529 static_params, false);
6530 orig_ops = av_set_copy (orig_ops);
6532 /* Filter the orig_ops set. */
6533 if (AV_SET_VALID_P (insn))
6534 av_set_code_motion_filter (&orig_ops, AV_SET (insn));
6536 /* If no more original ops, return immediately. */
6537 if (!orig_ops)
6539 if (sched_verbose >= 6)
6540 sel_print ("No intersection with av set of block %d\n", bb->index);
6541 return false;
6544 /* For non-speculative insns we have to leave only one form of the
6545 original operation, because if we don't, we may end up with
6546 different C_EXPRes and, consequently, with bookkeepings for different
6547 expression forms along the same code motion path. That may lead to
6548 generation of incorrect code. So for each code motion we stick to
6549 the single form of the instruction, except for speculative insns
6550 which we need to keep in different forms with all speculation
6551 types. */
6552 av_set_leave_one_nonspec (&orig_ops);
6554 /* It is not possible that all ORIG_OPS are filtered out. */
6555 gcc_assert (orig_ops);
6557 /* It is enough to place only heads and tails of visited basic blocks into
6558 the PATH. */
6559 ilist_add (&path, insn);
6560 first_insn = insn;
6561 bb_tail = sel_bb_end (bb);
6563 /* Descend the basic block in search of the original expr; this part
6564 corresponds to the part of the original move_op procedure executed
6565 before the recursive call. */
6566 for (;;)
6568 /* Look at the insn and decide if it could be an ancestor of currently
6569 scheduling operation. If it is so, then the insn "dest = op" could
6570 either be replaced with "dest = reg", because REG now holds the result
6571 of OP, or just removed, if we've scheduled the insn as a whole.
6573 If this insn doesn't contain currently scheduling OP, then proceed
6574 with searching and look at its successors. Operations we're searching
6575 for could have changed when moving up through this insn via
6576 substituting. In this case, perform unsubstitution on them first.
6578 When traversing the DAG below this insn is finished, insert
6579 bookkeeping code, if the insn is a joint point, and remove
6580 leftovers. */
6582 expr = av_set_lookup (orig_ops, INSN_VINSN (insn));
6583 if (expr)
6585 insn_t last_insn = PREV_INSN (insn);
6587 /* We have found the original operation. */
6588 if (sched_verbose >= 6)
6589 sel_print ("Found original operation at insn %d\n", INSN_UID (insn));
6591 code_motion_path_driver_info->orig_expr_found
6592 (insn, expr, local_params_in, static_params);
6594 /* Step back, so on the way back we'll start traversing from the
6595 previous insn (or we'll see that it's bb_note and skip that
6596 loop). */
6597 if (insn == first_insn)
6599 first_insn = NEXT_INSN (last_insn);
6600 removed_last_insn = sel_bb_end_p (last_insn);
6602 insn = last_insn;
6603 break;
6605 else
6607 /* We haven't found the original expr, continue descending the basic
6608 block. */
6609 if (code_motion_path_driver_info->orig_expr_not_found
6610 (insn, orig_ops, static_params))
6612 /* Av set ops could have been changed when moving through this
6613 insn. To find them below it, we have to un-substitute them. */
6614 undo_transformations (&orig_ops, insn);
6616 else
6618 /* Clean up and return, if the hook tells us to do so. It may
6619 happen if we've encountered the previously created
6620 bookkeeping. */
6621 code_motion_path_driver_cleanup (&orig_ops, &path);
6622 return -1;
6625 gcc_assert (orig_ops);
6628 /* Stop at insn if we got to the end of BB. */
6629 if (insn == bb_tail)
6630 break;
6632 insn = NEXT_INSN (insn);
6635 /* Here INSN either points to the insn before the original insn (may be
6636 bb_note, if original insn was a bb_head) or to the bb_end. */
6637 if (!expr)
6639 int res;
6640 rtx last_insn = PREV_INSN (insn);
6641 bool added_to_path;
6643 gcc_assert (insn == sel_bb_end (bb));
6645 /* Add bb tail to PATH (but it doesn't make any sense if it's a bb_head -
6646 it's already in PATH then). */
6647 if (insn != first_insn)
6649 ilist_add (&path, insn);
6650 added_to_path = true;
6652 else
6653 added_to_path = false;
6655 /* Process_successors should be able to find at least one
6656 successor for which code_motion_path_driver returns TRUE. */
6657 res = code_motion_process_successors (insn, orig_ops,
6658 path, static_params);
6660 /* Jump in the end of basic block could have been removed or replaced
6661 during code_motion_process_successors, so recompute insn as the
6662 last insn in bb. */
6663 if (NEXT_INSN (last_insn) != insn)
6665 insn = sel_bb_end (bb);
6666 first_insn = sel_bb_head (bb);
6669 /* Remove bb tail from path. */
6670 if (added_to_path)
6671 ilist_remove (&path);
6673 if (res != 1)
6675 /* This is the case when one of the original expr is no longer available
6676 due to bookkeeping created on this branch with the same register.
6677 In the original algorithm, which doesn't have update_data_sets call
6678 on a bookkeeping block, it would simply result in returning
6679 FALSE when we've encountered a previously generated bookkeeping
6680 insn in moveop_orig_expr_not_found. */
6681 code_motion_path_driver_cleanup (&orig_ops, &path);
6682 return res;
6686 /* Don't need it any more. */
6687 av_set_clear (&orig_ops);
6689 /* Backward pass: now, when we have C_EXPR computed, we'll drag it to
6690 the beginning of the basic block. */
6691 before_first = PREV_INSN (first_insn);
6692 while (insn != before_first)
6694 if (code_motion_path_driver_info->ascend)
6695 code_motion_path_driver_info->ascend (insn, static_params);
6697 insn = PREV_INSN (insn);
6700 /* Now we're at the bb head. */
6701 insn = first_insn;
6702 ilist_remove (&path);
6703 local_params_in->removed_last_insn = removed_last_insn;
6704 code_motion_path_driver_info->at_first_insn (insn, local_params_in, static_params);
6706 /* This should be the very last operation as at bb head we could change
6707 the numbering by creating bookkeeping blocks. */
6708 if (removed_last_insn)
6709 insn = PREV_INSN (insn);
6711 /* If we have simplified the control flow and removed the first jump insn,
6712 there's no point in marking this block in the visited blocks bitmap. */
6713 if (BLOCK_FOR_INSN (insn))
6714 bitmap_set_bit (code_motion_visited_blocks, BLOCK_FOR_INSN (insn)->index);
6715 return true;
6718 /* Move up the operations from ORIG_OPS set traversing the dag starting
6719 from INSN. PATH represents the edges traversed so far.
6720 DEST is the register chosen for scheduling the current expr. Insert
6721 bookkeeping code in the join points. EXPR_VLIW is the chosen expression,
6722 C_EXPR is how it looks like at the given cfg point.
6723 Set *SHOULD_MOVE to indicate whether we have only disconnected
6724 one of the insns found.
6726 Returns whether original instructions were found, which is asserted
6727 to be true in the caller. */
6728 static bool
6729 move_op (insn_t insn, av_set_t orig_ops, expr_t expr_vliw,
6730 rtx dest, expr_t c_expr, bool *should_move)
6732 struct moveop_static_params sparams;
6733 struct cmpd_local_params lparams;
6734 int res;
6736 /* Init params for code_motion_path_driver. */
6737 sparams.dest = dest;
6738 sparams.c_expr = c_expr;
6739 sparams.uid = INSN_UID (EXPR_INSN_RTX (expr_vliw));
6740 #ifdef ENABLE_CHECKING
6741 sparams.failed_insn = NULL;
6742 #endif
6743 sparams.was_renamed = false;
6744 lparams.e1 = NULL;
6746 /* We haven't visited any blocks yet. */
6747 bitmap_clear (code_motion_visited_blocks);
6749 /* Set appropriate hooks and data. */
6750 code_motion_path_driver_info = &move_op_hooks;
6751 res = code_motion_path_driver (insn, orig_ops, NULL, &lparams, &sparams);
6753 gcc_assert (res != -1);
6755 if (sparams.was_renamed)
6756 EXPR_WAS_RENAMED (expr_vliw) = true;
6758 *should_move = (sparams.uid == -1);
6760 return res;
6764 /* Functions that work with regions. */
6766 /* Current number of seqno used in init_seqno and init_seqno_1. */
6767 static int cur_seqno;
6769 /* A helper for init_seqno. Traverse the region starting from BB and
6770 compute seqnos for visited insns, marking visited bbs in VISITED_BBS.
6771 Clear visited blocks from BLOCKS_TO_RESCHEDULE. */
6772 static void
6773 init_seqno_1 (basic_block bb, sbitmap visited_bbs, bitmap blocks_to_reschedule)
6775 int bbi = BLOCK_TO_BB (bb->index);
6776 insn_t insn, note = bb_note (bb);
6777 insn_t succ_insn;
6778 succ_iterator si;
6780 bitmap_set_bit (visited_bbs, bbi);
6781 if (blocks_to_reschedule)
6782 bitmap_clear_bit (blocks_to_reschedule, bb->index);
6784 FOR_EACH_SUCC_1 (succ_insn, si, BB_END (bb),
6785 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
6787 basic_block succ = BLOCK_FOR_INSN (succ_insn);
6788 int succ_bbi = BLOCK_TO_BB (succ->index);
6790 gcc_assert (in_current_region_p (succ));
6792 if (!bitmap_bit_p (visited_bbs, succ_bbi))
6794 gcc_assert (succ_bbi > bbi);
6796 init_seqno_1 (succ, visited_bbs, blocks_to_reschedule);
6798 else if (blocks_to_reschedule)
6799 bitmap_set_bit (forced_ebb_heads, succ->index);
6802 for (insn = BB_END (bb); insn != note; insn = PREV_INSN (insn))
6803 INSN_SEQNO (insn) = cur_seqno--;
6806 /* Initialize seqnos for the current region. BLOCKS_TO_RESCHEDULE contains
6807 blocks on which we're rescheduling when pipelining, FROM is the block where
6808 traversing region begins (it may not be the head of the region when
6809 pipelining, but the head of the loop instead).
6811 Returns the maximal seqno found. */
6812 static int
6813 init_seqno (bitmap blocks_to_reschedule, basic_block from)
6815 sbitmap visited_bbs;
6816 bitmap_iterator bi;
6817 unsigned bbi;
6819 visited_bbs = sbitmap_alloc (current_nr_blocks);
6821 if (blocks_to_reschedule)
6823 bitmap_ones (visited_bbs);
6824 EXECUTE_IF_SET_IN_BITMAP (blocks_to_reschedule, 0, bbi, bi)
6826 gcc_assert (BLOCK_TO_BB (bbi) < current_nr_blocks);
6827 bitmap_clear_bit (visited_bbs, BLOCK_TO_BB (bbi));
6830 else
6832 bitmap_clear (visited_bbs);
6833 from = EBB_FIRST_BB (0);
6836 cur_seqno = sched_max_luid - 1;
6837 init_seqno_1 (from, visited_bbs, blocks_to_reschedule);
6839 /* cur_seqno may be positive if the number of instructions is less than
6840 sched_max_luid - 1 (when rescheduling or if some instructions have been
6841 removed by the call to purge_empty_blocks in sel_sched_region_1). */
6842 gcc_assert (cur_seqno >= 0);
6844 sbitmap_free (visited_bbs);
6845 return sched_max_luid - 1;
6848 /* Initialize scheduling parameters for current region. */
6849 static void
6850 sel_setup_region_sched_flags (void)
6852 enable_schedule_as_rhs_p = 1;
6853 bookkeeping_p = 1;
6854 pipelining_p = (bookkeeping_p
6855 && (flag_sel_sched_pipelining != 0)
6856 && current_loop_nest != NULL
6857 && loop_has_exit_edges (current_loop_nest));
6858 max_insns_to_rename = PARAM_VALUE (PARAM_SELSCHED_INSNS_TO_RENAME);
6859 max_ws = MAX_WS;
6862 /* Return true if all basic blocks of current region are empty. */
6863 static bool
6864 current_region_empty_p (void)
6866 int i;
6867 for (i = 0; i < current_nr_blocks; i++)
6868 if (! sel_bb_empty_p (BASIC_BLOCK_FOR_FN (cfun, BB_TO_BLOCK (i))))
6869 return false;
6871 return true;
6874 /* Prepare and verify loop nest for pipelining. */
6875 static void
6876 setup_current_loop_nest (int rgn, bb_vec_t *bbs)
6878 current_loop_nest = get_loop_nest_for_rgn (rgn);
6880 if (!current_loop_nest)
6881 return;
6883 /* If this loop has any saved loop preheaders from nested loops,
6884 add these basic blocks to the current region. */
6885 sel_add_loop_preheaders (bbs);
6887 /* Check that we're starting with a valid information. */
6888 gcc_assert (loop_latch_edge (current_loop_nest));
6889 gcc_assert (LOOP_MARKED_FOR_PIPELINING_P (current_loop_nest));
6892 /* Compute instruction priorities for current region. */
6893 static void
6894 sel_compute_priorities (int rgn)
6896 sched_rgn_compute_dependencies (rgn);
6898 /* Compute insn priorities in haifa style. Then free haifa style
6899 dependencies that we've calculated for this. */
6900 compute_priorities ();
6902 if (sched_verbose >= 5)
6903 debug_rgn_dependencies (0);
6905 free_rgn_deps ();
6908 /* Init scheduling data for RGN. Returns true when this region should not
6909 be scheduled. */
6910 static bool
6911 sel_region_init (int rgn)
6913 int i;
6914 bb_vec_t bbs;
6916 rgn_setup_region (rgn);
6918 /* Even if sched_is_disabled_for_current_region_p() is true, we still
6919 do region initialization here so the region can be bundled correctly,
6920 but we'll skip the scheduling in sel_sched_region (). */
6921 if (current_region_empty_p ())
6922 return true;
6924 bbs.create (current_nr_blocks);
6926 for (i = 0; i < current_nr_blocks; i++)
6927 bbs.quick_push (BASIC_BLOCK_FOR_FN (cfun, BB_TO_BLOCK (i)));
6929 sel_init_bbs (bbs);
6931 if (flag_sel_sched_pipelining)
6932 setup_current_loop_nest (rgn, &bbs);
6934 sel_setup_region_sched_flags ();
6936 /* Initialize luids and dependence analysis which both sel-sched and haifa
6937 need. */
6938 sched_init_luids (bbs);
6939 sched_deps_init (false);
6941 /* Initialize haifa data. */
6942 rgn_setup_sched_infos ();
6943 sel_set_sched_flags ();
6944 haifa_init_h_i_d (bbs);
6946 sel_compute_priorities (rgn);
6947 init_deps_global ();
6949 /* Main initialization. */
6950 sel_setup_sched_infos ();
6951 sel_init_global_and_expr (bbs);
6953 bbs.release ();
6955 blocks_to_reschedule = BITMAP_ALLOC (NULL);
6957 /* Init correct liveness sets on each instruction of a single-block loop.
6958 This is the only situation when we can't update liveness when calling
6959 compute_live for the first insn of the loop. */
6960 if (current_loop_nest)
6962 int header =
6963 (sel_is_loop_preheader_p (BASIC_BLOCK_FOR_FN (cfun, BB_TO_BLOCK (0)))
6965 : 0);
6967 if (current_nr_blocks == header + 1)
6968 update_liveness_on_insn
6969 (sel_bb_head (BASIC_BLOCK_FOR_FN (cfun, BB_TO_BLOCK (header))));
6972 /* Set hooks so that no newly generated insn will go out unnoticed. */
6973 sel_register_cfg_hooks ();
6975 /* !!! We call target.sched.init () for the whole region, but we invoke
6976 targetm.sched.finish () for every ebb. */
6977 if (targetm.sched.init)
6978 /* None of the arguments are actually used in any target. */
6979 targetm.sched.init (sched_dump, sched_verbose, -1);
6981 first_emitted_uid = get_max_uid () + 1;
6982 preheader_removed = false;
6984 /* Reset register allocation ticks array. */
6985 memset (reg_rename_tick, 0, sizeof reg_rename_tick);
6986 reg_rename_this_tick = 0;
6988 bitmap_initialize (forced_ebb_heads, 0);
6989 bitmap_clear (forced_ebb_heads);
6991 setup_nop_vinsn ();
6992 current_copies = BITMAP_ALLOC (NULL);
6993 current_originators = BITMAP_ALLOC (NULL);
6994 code_motion_visited_blocks = BITMAP_ALLOC (NULL);
6996 return false;
6999 /* Simplify insns after the scheduling. */
7000 static void
7001 simplify_changed_insns (void)
7003 int i;
7005 for (i = 0; i < current_nr_blocks; i++)
7007 basic_block bb = BASIC_BLOCK_FOR_FN (cfun, BB_TO_BLOCK (i));
7008 rtx insn;
7010 FOR_BB_INSNS (bb, insn)
7011 if (INSN_P (insn))
7013 expr_t expr = INSN_EXPR (insn);
7015 if (EXPR_WAS_SUBSTITUTED (expr))
7016 validate_simplify_insn (insn);
7021 /* Find boundaries of the EBB starting from basic block BB, marking blocks of
7022 this EBB in SCHEDULED_BLOCKS and appropriately filling in HEAD, TAIL,
7023 PREV_HEAD, and NEXT_TAIL fields of CURRENT_SCHED_INFO structure. */
7024 static void
7025 find_ebb_boundaries (basic_block bb, bitmap scheduled_blocks)
7027 insn_t head, tail;
7028 basic_block bb1 = bb;
7029 if (sched_verbose >= 2)
7030 sel_print ("Finishing schedule in bbs: ");
7034 bitmap_set_bit (scheduled_blocks, BLOCK_TO_BB (bb1->index));
7036 if (sched_verbose >= 2)
7037 sel_print ("%d; ", bb1->index);
7039 while (!bb_ends_ebb_p (bb1) && (bb1 = bb_next_bb (bb1)));
7041 if (sched_verbose >= 2)
7042 sel_print ("\n");
7044 get_ebb_head_tail (bb, bb1, &head, &tail);
7046 current_sched_info->head = head;
7047 current_sched_info->tail = tail;
7048 current_sched_info->prev_head = PREV_INSN (head);
7049 current_sched_info->next_tail = NEXT_INSN (tail);
7052 /* Regenerate INSN_SCHED_CYCLEs for insns of current EBB. */
7053 static void
7054 reset_sched_cycles_in_current_ebb (void)
7056 int last_clock = 0;
7057 int haifa_last_clock = -1;
7058 int haifa_clock = 0;
7059 int issued_insns = 0;
7060 insn_t insn;
7062 if (targetm.sched.init)
7064 /* None of the arguments are actually used in any target.
7065 NB: We should have md_reset () hook for cases like this. */
7066 targetm.sched.init (sched_dump, sched_verbose, -1);
7069 state_reset (curr_state);
7070 advance_state (curr_state);
7072 for (insn = current_sched_info->head;
7073 insn != current_sched_info->next_tail;
7074 insn = NEXT_INSN (insn))
7076 int cost, haifa_cost;
7077 int sort_p;
7078 bool asm_p, real_insn, after_stall, all_issued;
7079 int clock;
7081 if (!INSN_P (insn))
7082 continue;
7084 asm_p = false;
7085 real_insn = recog_memoized (insn) >= 0;
7086 clock = INSN_SCHED_CYCLE (insn);
7088 cost = clock - last_clock;
7090 /* Initialize HAIFA_COST. */
7091 if (! real_insn)
7093 asm_p = INSN_ASM_P (insn);
7095 if (asm_p)
7096 /* This is asm insn which *had* to be scheduled first
7097 on the cycle. */
7098 haifa_cost = 1;
7099 else
7100 /* This is a use/clobber insn. It should not change
7101 cost. */
7102 haifa_cost = 0;
7104 else
7105 haifa_cost = estimate_insn_cost (insn, curr_state);
7107 /* Stall for whatever cycles we've stalled before. */
7108 after_stall = 0;
7109 if (INSN_AFTER_STALL_P (insn) && cost > haifa_cost)
7111 haifa_cost = cost;
7112 after_stall = 1;
7114 all_issued = issued_insns == issue_rate;
7115 if (haifa_cost == 0 && all_issued)
7116 haifa_cost = 1;
7117 if (haifa_cost > 0)
7119 int i = 0;
7121 while (haifa_cost--)
7123 advance_state (curr_state);
7124 issued_insns = 0;
7125 i++;
7127 if (sched_verbose >= 2)
7129 sel_print ("advance_state (state_transition)\n");
7130 debug_state (curr_state);
7133 /* The DFA may report that e.g. insn requires 2 cycles to be
7134 issued, but on the next cycle it says that insn is ready
7135 to go. Check this here. */
7136 if (!after_stall
7137 && real_insn
7138 && haifa_cost > 0
7139 && estimate_insn_cost (insn, curr_state) == 0)
7140 break;
7142 /* When the data dependency stall is longer than the DFA stall,
7143 and when we have issued exactly issue_rate insns and stalled,
7144 it could be that after this longer stall the insn will again
7145 become unavailable to the DFA restrictions. Looks strange
7146 but happens e.g. on x86-64. So recheck DFA on the last
7147 iteration. */
7148 if ((after_stall || all_issued)
7149 && real_insn
7150 && haifa_cost == 0)
7151 haifa_cost = estimate_insn_cost (insn, curr_state);
7154 haifa_clock += i;
7155 if (sched_verbose >= 2)
7156 sel_print ("haifa clock: %d\n", haifa_clock);
7158 else
7159 gcc_assert (haifa_cost == 0);
7161 if (sched_verbose >= 2)
7162 sel_print ("Haifa cost for insn %d: %d\n", INSN_UID (insn), haifa_cost);
7164 if (targetm.sched.dfa_new_cycle)
7165 while (targetm.sched.dfa_new_cycle (sched_dump, sched_verbose, insn,
7166 haifa_last_clock, haifa_clock,
7167 &sort_p))
7169 advance_state (curr_state);
7170 issued_insns = 0;
7171 haifa_clock++;
7172 if (sched_verbose >= 2)
7174 sel_print ("advance_state (dfa_new_cycle)\n");
7175 debug_state (curr_state);
7176 sel_print ("haifa clock: %d\n", haifa_clock + 1);
7180 if (real_insn)
7182 static state_t temp = NULL;
7184 if (!temp)
7185 temp = xmalloc (dfa_state_size);
7186 memcpy (temp, curr_state, dfa_state_size);
7188 cost = state_transition (curr_state, insn);
7189 if (memcmp (temp, curr_state, dfa_state_size))
7190 issued_insns++;
7192 if (sched_verbose >= 2)
7194 sel_print ("scheduled insn %d, clock %d\n", INSN_UID (insn),
7195 haifa_clock + 1);
7196 debug_state (curr_state);
7198 gcc_assert (cost < 0);
7201 if (targetm.sched.variable_issue)
7202 targetm.sched.variable_issue (sched_dump, sched_verbose, insn, 0);
7204 INSN_SCHED_CYCLE (insn) = haifa_clock;
7206 last_clock = clock;
7207 haifa_last_clock = haifa_clock;
7211 /* Put TImode markers on insns starting a new issue group. */
7212 static void
7213 put_TImodes (void)
7215 int last_clock = -1;
7216 insn_t insn;
7218 for (insn = current_sched_info->head; insn != current_sched_info->next_tail;
7219 insn = NEXT_INSN (insn))
7221 int cost, clock;
7223 if (!INSN_P (insn))
7224 continue;
7226 clock = INSN_SCHED_CYCLE (insn);
7227 cost = (last_clock == -1) ? 1 : clock - last_clock;
7229 gcc_assert (cost >= 0);
7231 if (issue_rate > 1
7232 && GET_CODE (PATTERN (insn)) != USE
7233 && GET_CODE (PATTERN (insn)) != CLOBBER)
7235 if (reload_completed && cost > 0)
7236 PUT_MODE (insn, TImode);
7238 last_clock = clock;
7241 if (sched_verbose >= 2)
7242 sel_print ("Cost for insn %d is %d\n", INSN_UID (insn), cost);
7246 /* Perform MD_FINISH on EBBs comprising current region. When
7247 RESET_SCHED_CYCLES_P is true, run a pass emulating the scheduler
7248 to produce correct sched cycles on insns. */
7249 static void
7250 sel_region_target_finish (bool reset_sched_cycles_p)
7252 int i;
7253 bitmap scheduled_blocks = BITMAP_ALLOC (NULL);
7255 for (i = 0; i < current_nr_blocks; i++)
7257 if (bitmap_bit_p (scheduled_blocks, i))
7258 continue;
7260 /* While pipelining outer loops, skip bundling for loop
7261 preheaders. Those will be rescheduled in the outer loop. */
7262 if (sel_is_loop_preheader_p (EBB_FIRST_BB (i)))
7263 continue;
7265 find_ebb_boundaries (EBB_FIRST_BB (i), scheduled_blocks);
7267 if (no_real_insns_p (current_sched_info->head, current_sched_info->tail))
7268 continue;
7270 if (reset_sched_cycles_p)
7271 reset_sched_cycles_in_current_ebb ();
7273 if (targetm.sched.init)
7274 targetm.sched.init (sched_dump, sched_verbose, -1);
7276 put_TImodes ();
7278 if (targetm.sched.finish)
7280 targetm.sched.finish (sched_dump, sched_verbose);
7282 /* Extend luids so that insns generated by the target will
7283 get zero luid. */
7284 sched_extend_luids ();
7288 BITMAP_FREE (scheduled_blocks);
7291 /* Free the scheduling data for the current region. When RESET_SCHED_CYCLES_P
7292 is true, make an additional pass emulating scheduler to get correct insn
7293 cycles for md_finish calls. */
7294 static void
7295 sel_region_finish (bool reset_sched_cycles_p)
7297 simplify_changed_insns ();
7298 sched_finish_ready_list ();
7299 free_nop_pool ();
7301 /* Free the vectors. */
7302 vec_av_set.release ();
7303 BITMAP_FREE (current_copies);
7304 BITMAP_FREE (current_originators);
7305 BITMAP_FREE (code_motion_visited_blocks);
7306 vinsn_vec_free (vec_bookkeeping_blocked_vinsns);
7307 vinsn_vec_free (vec_target_unavailable_vinsns);
7309 /* If LV_SET of the region head should be updated, do it now because
7310 there will be no other chance. */
7312 succ_iterator si;
7313 insn_t insn;
7315 FOR_EACH_SUCC_1 (insn, si, bb_note (EBB_FIRST_BB (0)),
7316 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
7318 basic_block bb = BLOCK_FOR_INSN (insn);
7320 if (!BB_LV_SET_VALID_P (bb))
7321 compute_live (insn);
7325 /* Emulate the Haifa scheduler for bundling. */
7326 if (reload_completed)
7327 sel_region_target_finish (reset_sched_cycles_p);
7329 sel_finish_global_and_expr ();
7331 bitmap_clear (forced_ebb_heads);
7333 free_nop_vinsn ();
7335 finish_deps_global ();
7336 sched_finish_luids ();
7337 h_d_i_d.release ();
7339 sel_finish_bbs ();
7340 BITMAP_FREE (blocks_to_reschedule);
7342 sel_unregister_cfg_hooks ();
7344 max_issue_size = 0;
7348 /* Functions that implement the scheduler driver. */
7350 /* Schedule a parallel instruction group on each of FENCES. MAX_SEQNO
7351 is the current maximum seqno. SCHEDULED_INSNS_TAILPP is the list
7352 of insns scheduled -- these would be postprocessed later. */
7353 static void
7354 schedule_on_fences (flist_t fences, int max_seqno,
7355 ilist_t **scheduled_insns_tailpp)
7357 flist_t old_fences = fences;
7359 if (sched_verbose >= 1)
7361 sel_print ("\nScheduling on fences: ");
7362 dump_flist (fences);
7363 sel_print ("\n");
7366 scheduled_something_on_previous_fence = false;
7367 for (; fences; fences = FLIST_NEXT (fences))
7369 fence_t fence = NULL;
7370 int seqno = 0;
7371 flist_t fences2;
7372 bool first_p = true;
7374 /* Choose the next fence group to schedule.
7375 The fact that insn can be scheduled only once
7376 on the cycle is guaranteed by two properties:
7377 1. seqnos of parallel groups decrease with each iteration.
7378 2. If is_ineligible_successor () sees the larger seqno, it
7379 checks if candidate insn is_in_current_fence_p (). */
7380 for (fences2 = old_fences; fences2; fences2 = FLIST_NEXT (fences2))
7382 fence_t f = FLIST_FENCE (fences2);
7384 if (!FENCE_PROCESSED_P (f))
7386 int i = INSN_SEQNO (FENCE_INSN (f));
7388 if (first_p || i > seqno)
7390 seqno = i;
7391 fence = f;
7392 first_p = false;
7394 else
7395 /* ??? Seqnos of different groups should be different. */
7396 gcc_assert (1 || i != seqno);
7400 gcc_assert (fence);
7402 /* As FENCE is nonnull, SEQNO is initialized. */
7403 seqno -= max_seqno + 1;
7404 fill_insns (fence, seqno, scheduled_insns_tailpp);
7405 FENCE_PROCESSED_P (fence) = true;
7408 /* All av_sets are invalidated by GLOBAL_LEVEL increase, thus we
7409 don't need to keep bookkeeping-invalidated and target-unavailable
7410 vinsns any more. */
7411 vinsn_vec_clear (&vec_bookkeeping_blocked_vinsns);
7412 vinsn_vec_clear (&vec_target_unavailable_vinsns);
7415 /* Calculate MIN_SEQNO and MAX_SEQNO. */
7416 static void
7417 find_min_max_seqno (flist_t fences, int *min_seqno, int *max_seqno)
7419 *min_seqno = *max_seqno = INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences)));
7421 /* The first element is already processed. */
7422 while ((fences = FLIST_NEXT (fences)))
7424 int seqno = INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences)));
7426 if (*min_seqno > seqno)
7427 *min_seqno = seqno;
7428 else if (*max_seqno < seqno)
7429 *max_seqno = seqno;
7433 /* Calculate new fences from FENCES. Write the current time to PTIME. */
7434 static flist_t
7435 calculate_new_fences (flist_t fences, int orig_max_seqno, int *ptime)
7437 flist_t old_fences = fences;
7438 struct flist_tail_def _new_fences, *new_fences = &_new_fences;
7439 int max_time = 0;
7441 flist_tail_init (new_fences);
7442 for (; fences; fences = FLIST_NEXT (fences))
7444 fence_t fence = FLIST_FENCE (fences);
7445 insn_t insn;
7447 if (!FENCE_BNDS (fence))
7449 /* This fence doesn't have any successors. */
7450 if (!FENCE_SCHEDULED_P (fence))
7452 /* Nothing was scheduled on this fence. */
7453 int seqno;
7455 insn = FENCE_INSN (fence);
7456 seqno = INSN_SEQNO (insn);
7457 gcc_assert (seqno > 0 && seqno <= orig_max_seqno);
7459 if (sched_verbose >= 1)
7460 sel_print ("Fence %d[%d] has not changed\n",
7461 INSN_UID (insn),
7462 BLOCK_NUM (insn));
7463 move_fence_to_fences (fences, new_fences);
7466 else
7467 extract_new_fences_from (fences, new_fences, orig_max_seqno);
7468 max_time = MAX (max_time, FENCE_CYCLE (fence));
7471 flist_clear (&old_fences);
7472 *ptime = max_time;
7473 return FLIST_TAIL_HEAD (new_fences);
7476 /* Update seqnos of insns given by PSCHEDULED_INSNS. MIN_SEQNO and MAX_SEQNO
7477 are the miminum and maximum seqnos of the group, HIGHEST_SEQNO_IN_USE is
7478 the highest seqno used in a region. Return the updated highest seqno. */
7479 static int
7480 update_seqnos_and_stage (int min_seqno, int max_seqno,
7481 int highest_seqno_in_use,
7482 ilist_t *pscheduled_insns)
7484 int new_hs;
7485 ilist_iterator ii;
7486 insn_t insn;
7488 /* Actually, new_hs is the seqno of the instruction, that was
7489 scheduled first (i.e. it is the first one in SCHEDULED_INSNS). */
7490 if (*pscheduled_insns)
7492 new_hs = (INSN_SEQNO (ILIST_INSN (*pscheduled_insns))
7493 + highest_seqno_in_use + max_seqno - min_seqno + 2);
7494 gcc_assert (new_hs > highest_seqno_in_use);
7496 else
7497 new_hs = highest_seqno_in_use;
7499 FOR_EACH_INSN (insn, ii, *pscheduled_insns)
7501 gcc_assert (INSN_SEQNO (insn) < 0);
7502 INSN_SEQNO (insn) += highest_seqno_in_use + max_seqno - min_seqno + 2;
7503 gcc_assert (INSN_SEQNO (insn) <= new_hs);
7505 /* When not pipelining, purge unneeded insn info on the scheduled insns.
7506 For example, having reg_last array of INSN_DEPS_CONTEXT in memory may
7507 require > 1GB of memory e.g. on limit-fnargs.c. */
7508 if (! pipelining_p)
7509 free_data_for_scheduled_insn (insn);
7512 ilist_clear (pscheduled_insns);
7513 global_level++;
7515 return new_hs;
7518 /* The main driver for scheduling a region. This function is responsible
7519 for correct propagation of fences (i.e. scheduling points) and creating
7520 a group of parallel insns at each of them. It also supports
7521 pipelining. ORIG_MAX_SEQNO is the maximal seqno before this pass
7522 of scheduling. */
7523 static void
7524 sel_sched_region_2 (int orig_max_seqno)
7526 int highest_seqno_in_use = orig_max_seqno;
7527 int max_time = 0;
7529 stat_bookkeeping_copies = 0;
7530 stat_insns_needed_bookkeeping = 0;
7531 stat_renamed_scheduled = 0;
7532 stat_substitutions_total = 0;
7533 num_insns_scheduled = 0;
7535 while (fences)
7537 int min_seqno, max_seqno;
7538 ilist_t scheduled_insns = NULL;
7539 ilist_t *scheduled_insns_tailp = &scheduled_insns;
7541 find_min_max_seqno (fences, &min_seqno, &max_seqno);
7542 schedule_on_fences (fences, max_seqno, &scheduled_insns_tailp);
7543 fences = calculate_new_fences (fences, orig_max_seqno, &max_time);
7544 highest_seqno_in_use = update_seqnos_and_stage (min_seqno, max_seqno,
7545 highest_seqno_in_use,
7546 &scheduled_insns);
7549 if (sched_verbose >= 1)
7551 sel_print ("Total scheduling time: %d cycles\n", max_time);
7552 sel_print ("Scheduled %d bookkeeping copies, %d insns needed "
7553 "bookkeeping, %d insns renamed, %d insns substituted\n",
7554 stat_bookkeeping_copies,
7555 stat_insns_needed_bookkeeping,
7556 stat_renamed_scheduled,
7557 stat_substitutions_total);
7561 /* Schedule a region. When pipelining, search for possibly never scheduled
7562 bookkeeping code and schedule it. Reschedule pipelined code without
7563 pipelining after. */
7564 static void
7565 sel_sched_region_1 (void)
7567 int orig_max_seqno;
7569 /* Remove empty blocks that might be in the region from the beginning. */
7570 purge_empty_blocks ();
7572 orig_max_seqno = init_seqno (NULL, NULL);
7573 gcc_assert (orig_max_seqno >= 1);
7575 /* When pipelining outer loops, create fences on the loop header,
7576 not preheader. */
7577 fences = NULL;
7578 if (current_loop_nest)
7579 init_fences (BB_END (EBB_FIRST_BB (0)));
7580 else
7581 init_fences (bb_note (EBB_FIRST_BB (0)));
7582 global_level = 1;
7584 sel_sched_region_2 (orig_max_seqno);
7586 gcc_assert (fences == NULL);
7588 if (pipelining_p)
7590 int i;
7591 basic_block bb;
7592 struct flist_tail_def _new_fences;
7593 flist_tail_t new_fences = &_new_fences;
7594 bool do_p = true;
7596 pipelining_p = false;
7597 max_ws = MIN (max_ws, issue_rate * 3 / 2);
7598 bookkeeping_p = false;
7599 enable_schedule_as_rhs_p = false;
7601 /* Schedule newly created code, that has not been scheduled yet. */
7602 do_p = true;
7604 while (do_p)
7606 do_p = false;
7608 for (i = 0; i < current_nr_blocks; i++)
7610 basic_block bb = EBB_FIRST_BB (i);
7612 if (bitmap_bit_p (blocks_to_reschedule, bb->index))
7614 if (! bb_ends_ebb_p (bb))
7615 bitmap_set_bit (blocks_to_reschedule, bb_next_bb (bb)->index);
7616 if (sel_bb_empty_p (bb))
7618 bitmap_clear_bit (blocks_to_reschedule, bb->index);
7619 continue;
7621 clear_outdated_rtx_info (bb);
7622 if (sel_insn_is_speculation_check (BB_END (bb))
7623 && JUMP_P (BB_END (bb)))
7624 bitmap_set_bit (blocks_to_reschedule,
7625 BRANCH_EDGE (bb)->dest->index);
7627 else if (! sel_bb_empty_p (bb)
7628 && INSN_SCHED_TIMES (sel_bb_head (bb)) <= 0)
7629 bitmap_set_bit (blocks_to_reschedule, bb->index);
7632 for (i = 0; i < current_nr_blocks; i++)
7634 bb = EBB_FIRST_BB (i);
7636 /* While pipelining outer loops, skip bundling for loop
7637 preheaders. Those will be rescheduled in the outer
7638 loop. */
7639 if (sel_is_loop_preheader_p (bb))
7641 clear_outdated_rtx_info (bb);
7642 continue;
7645 if (bitmap_bit_p (blocks_to_reschedule, bb->index))
7647 flist_tail_init (new_fences);
7649 orig_max_seqno = init_seqno (blocks_to_reschedule, bb);
7651 /* Mark BB as head of the new ebb. */
7652 bitmap_set_bit (forced_ebb_heads, bb->index);
7654 gcc_assert (fences == NULL);
7656 init_fences (bb_note (bb));
7658 sel_sched_region_2 (orig_max_seqno);
7660 do_p = true;
7661 break;
7668 /* Schedule the RGN region. */
7669 void
7670 sel_sched_region (int rgn)
7672 bool schedule_p;
7673 bool reset_sched_cycles_p;
7675 if (sel_region_init (rgn))
7676 return;
7678 if (sched_verbose >= 1)
7679 sel_print ("Scheduling region %d\n", rgn);
7681 schedule_p = (!sched_is_disabled_for_current_region_p ()
7682 && dbg_cnt (sel_sched_region_cnt));
7683 reset_sched_cycles_p = pipelining_p;
7684 if (schedule_p)
7685 sel_sched_region_1 ();
7686 else
7687 /* Force initialization of INSN_SCHED_CYCLEs for correct bundling. */
7688 reset_sched_cycles_p = true;
7690 sel_region_finish (reset_sched_cycles_p);
7693 /* Perform global init for the scheduler. */
7694 static void
7695 sel_global_init (void)
7697 calculate_dominance_info (CDI_DOMINATORS);
7698 alloc_sched_pools ();
7700 /* Setup the infos for sched_init. */
7701 sel_setup_sched_infos ();
7702 setup_sched_dump ();
7704 sched_rgn_init (false);
7705 sched_init ();
7707 sched_init_bbs ();
7708 /* Reset AFTER_RECOVERY if it has been set by the 1st scheduler pass. */
7709 after_recovery = 0;
7710 can_issue_more = issue_rate;
7712 sched_extend_target ();
7713 sched_deps_init (true);
7714 setup_nop_and_exit_insns ();
7715 sel_extend_global_bb_info ();
7716 init_lv_sets ();
7717 init_hard_regs_data ();
7720 /* Free the global data of the scheduler. */
7721 static void
7722 sel_global_finish (void)
7724 free_bb_note_pool ();
7725 free_lv_sets ();
7726 sel_finish_global_bb_info ();
7728 free_regset_pool ();
7729 free_nop_and_exit_insns ();
7731 sched_rgn_finish ();
7732 sched_deps_finish ();
7733 sched_finish ();
7735 if (current_loops)
7736 sel_finish_pipelining ();
7738 free_sched_pools ();
7739 free_dominance_info (CDI_DOMINATORS);
7742 /* Return true when we need to skip selective scheduling. Used for debugging. */
7743 bool
7744 maybe_skip_selective_scheduling (void)
7746 return ! dbg_cnt (sel_sched_cnt);
7749 /* The entry point. */
7750 void
7751 run_selective_scheduling (void)
7753 int rgn;
7755 if (n_basic_blocks_for_fn (cfun) == NUM_FIXED_BLOCKS)
7756 return;
7758 sel_global_init ();
7760 for (rgn = 0; rgn < nr_regions; rgn++)
7761 sel_sched_region (rgn);
7763 sel_global_finish ();
7766 #endif