1 /* Output routines for Motorola MCore processor
2 Copyright (C) 1993-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published
8 by the Free Software Foundation; either version 3, or (at your
9 option) any later version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
30 #include "stringpool.h"
33 #include "diagnostic-core.h"
34 #include "stor-layout.h"
45 /* This file should be included last. */
46 #include "target-def.h"
48 /* For dumping information about frame sizes. */
49 char * mcore_current_function_name
= 0;
50 long mcore_current_compilation_timestamp
= 0;
52 /* Global variables for machine-dependent things. */
54 /* Provides the class number of the smallest class containing
56 const enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
] =
58 GENERAL_REGS
, ONLYR1_REGS
, LRW_REGS
, LRW_REGS
,
59 LRW_REGS
, LRW_REGS
, LRW_REGS
, LRW_REGS
,
60 LRW_REGS
, LRW_REGS
, LRW_REGS
, LRW_REGS
,
61 LRW_REGS
, LRW_REGS
, LRW_REGS
, GENERAL_REGS
,
62 GENERAL_REGS
, C_REGS
, NO_REGS
, NO_REGS
,
67 int arg_size
; /* Stdarg spills (bytes). */
68 int reg_size
; /* Non-volatile reg saves (bytes). */
69 int reg_mask
; /* Non-volatile reg saves. */
70 int local_size
; /* Locals. */
71 int outbound_size
; /* Arg overflow on calls out. */
75 /* Describe the steps we'll use to grow it. */
76 #define MAX_STACK_GROWS 4 /* Gives us some spare space. */
77 int growth
[MAX_STACK_GROWS
];
95 static void output_stack_adjust (int, int);
96 static int calc_live_regs (int *);
97 static int try_constant_tricks (HOST_WIDE_INT
, HOST_WIDE_INT
*, HOST_WIDE_INT
*);
98 static const char * output_inline_const (machine_mode
, rtx
*);
99 static void layout_mcore_frame (struct mcore_frame
*);
100 static void mcore_setup_incoming_varargs (cumulative_args_t
, machine_mode
, tree
, int *, int);
101 static cond_type
is_cond_candidate (rtx
);
102 static rtx_insn
*emit_new_cond_insn (rtx_insn
*, int);
103 static rtx_insn
*conditionalize_block (rtx_insn
*);
104 static void conditionalize_optimization (void);
105 static void mcore_reorg (void);
106 static rtx
handle_structs_in_regs (machine_mode
, const_tree
, int);
107 static void mcore_mark_dllexport (tree
);
108 static void mcore_mark_dllimport (tree
);
109 static int mcore_dllexport_p (tree
);
110 static int mcore_dllimport_p (tree
);
111 static tree
mcore_handle_naked_attribute (tree
*, tree
, tree
, int, bool *);
112 #ifdef OBJECT_FORMAT_ELF
113 static void mcore_asm_named_section (const char *,
116 static void mcore_print_operand (FILE *, rtx
, int);
117 static void mcore_print_operand_address (FILE *, machine_mode
, rtx
);
118 static bool mcore_print_operand_punct_valid_p (unsigned char code
);
119 static void mcore_unique_section (tree
, int);
120 static void mcore_encode_section_info (tree
, rtx
, int);
121 static const char *mcore_strip_name_encoding (const char *);
122 static int mcore_const_costs (rtx
, RTX_CODE
);
123 static int mcore_and_cost (rtx
);
124 static int mcore_ior_cost (rtx
);
125 static bool mcore_rtx_costs (rtx
, machine_mode
, int, int,
127 static void mcore_external_libcall (rtx
);
128 static bool mcore_return_in_memory (const_tree
, const_tree
);
129 static int mcore_arg_partial_bytes (cumulative_args_t
,
132 static rtx
mcore_function_arg (cumulative_args_t
,
135 static void mcore_function_arg_advance (cumulative_args_t
,
138 static unsigned int mcore_function_arg_boundary (machine_mode
,
140 static void mcore_asm_trampoline_template (FILE *);
141 static void mcore_trampoline_init (rtx
, tree
, rtx
);
142 static bool mcore_warn_func_return (tree
);
143 static void mcore_option_override (void);
144 static bool mcore_legitimate_constant_p (machine_mode
, rtx
);
145 static bool mcore_legitimate_address_p (machine_mode
, rtx
, bool,
147 static bool mcore_hard_regno_mode_ok (unsigned int, machine_mode
);
148 static bool mcore_modes_tieable_p (machine_mode
, machine_mode
);
150 /* MCore specific attributes. */
152 static const struct attribute_spec mcore_attribute_table
[] =
154 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
155 affects_type_identity } */
156 { "dllexport", 0, 0, true, false, false, NULL
, false },
157 { "dllimport", 0, 0, true, false, false, NULL
, false },
158 { "naked", 0, 0, true, false, false, mcore_handle_naked_attribute
,
160 { NULL
, 0, 0, false, false, false, NULL
, false }
163 /* Initialize the GCC target structure. */
164 #undef TARGET_ASM_EXTERNAL_LIBCALL
165 #define TARGET_ASM_EXTERNAL_LIBCALL mcore_external_libcall
167 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
168 #undef TARGET_MERGE_DECL_ATTRIBUTES
169 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
172 #ifdef OBJECT_FORMAT_ELF
173 #undef TARGET_ASM_UNALIGNED_HI_OP
174 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
175 #undef TARGET_ASM_UNALIGNED_SI_OP
176 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
179 #undef TARGET_PRINT_OPERAND
180 #define TARGET_PRINT_OPERAND mcore_print_operand
181 #undef TARGET_PRINT_OPERAND_ADDRESS
182 #define TARGET_PRINT_OPERAND_ADDRESS mcore_print_operand_address
183 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
184 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P mcore_print_operand_punct_valid_p
186 #undef TARGET_ATTRIBUTE_TABLE
187 #define TARGET_ATTRIBUTE_TABLE mcore_attribute_table
188 #undef TARGET_ASM_UNIQUE_SECTION
189 #define TARGET_ASM_UNIQUE_SECTION mcore_unique_section
190 #undef TARGET_ASM_FUNCTION_RODATA_SECTION
191 #define TARGET_ASM_FUNCTION_RODATA_SECTION default_no_function_rodata_section
192 #undef TARGET_ENCODE_SECTION_INFO
193 #define TARGET_ENCODE_SECTION_INFO mcore_encode_section_info
194 #undef TARGET_STRIP_NAME_ENCODING
195 #define TARGET_STRIP_NAME_ENCODING mcore_strip_name_encoding
196 #undef TARGET_RTX_COSTS
197 #define TARGET_RTX_COSTS mcore_rtx_costs
198 #undef TARGET_ADDRESS_COST
199 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0
200 #undef TARGET_MACHINE_DEPENDENT_REORG
201 #define TARGET_MACHINE_DEPENDENT_REORG mcore_reorg
203 #undef TARGET_PROMOTE_FUNCTION_MODE
204 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
205 #undef TARGET_PROMOTE_PROTOTYPES
206 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
208 #undef TARGET_RETURN_IN_MEMORY
209 #define TARGET_RETURN_IN_MEMORY mcore_return_in_memory
210 #undef TARGET_MUST_PASS_IN_STACK
211 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
212 #undef TARGET_PASS_BY_REFERENCE
213 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
214 #undef TARGET_ARG_PARTIAL_BYTES
215 #define TARGET_ARG_PARTIAL_BYTES mcore_arg_partial_bytes
216 #undef TARGET_FUNCTION_ARG
217 #define TARGET_FUNCTION_ARG mcore_function_arg
218 #undef TARGET_FUNCTION_ARG_ADVANCE
219 #define TARGET_FUNCTION_ARG_ADVANCE mcore_function_arg_advance
220 #undef TARGET_FUNCTION_ARG_BOUNDARY
221 #define TARGET_FUNCTION_ARG_BOUNDARY mcore_function_arg_boundary
223 #undef TARGET_SETUP_INCOMING_VARARGS
224 #define TARGET_SETUP_INCOMING_VARARGS mcore_setup_incoming_varargs
226 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
227 #define TARGET_ASM_TRAMPOLINE_TEMPLATE mcore_asm_trampoline_template
228 #undef TARGET_TRAMPOLINE_INIT
229 #define TARGET_TRAMPOLINE_INIT mcore_trampoline_init
231 #undef TARGET_OPTION_OVERRIDE
232 #define TARGET_OPTION_OVERRIDE mcore_option_override
234 #undef TARGET_LEGITIMATE_CONSTANT_P
235 #define TARGET_LEGITIMATE_CONSTANT_P mcore_legitimate_constant_p
236 #undef TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P
237 #define TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P mcore_legitimate_address_p
240 #define TARGET_LRA_P hook_bool_void_false
242 #undef TARGET_WARN_FUNC_RETURN
243 #define TARGET_WARN_FUNC_RETURN mcore_warn_func_return
245 #undef TARGET_HARD_REGNO_MODE_OK
246 #define TARGET_HARD_REGNO_MODE_OK mcore_hard_regno_mode_ok
248 #undef TARGET_MODES_TIEABLE_P
249 #define TARGET_MODES_TIEABLE_P mcore_modes_tieable_p
251 #undef TARGET_CONSTANT_ALIGNMENT
252 #define TARGET_CONSTANT_ALIGNMENT constant_alignment_word_strings
254 struct gcc_target targetm
= TARGET_INITIALIZER
;
256 /* Adjust the stack and return the number of bytes taken to do it. */
258 output_stack_adjust (int direction
, int size
)
260 /* If extending stack a lot, we do it incrementally. */
261 if (direction
< 0 && size
> mcore_stack_increment
&& mcore_stack_increment
> 0)
263 rtx tmp
= gen_rtx_REG (SImode
, 1);
266 emit_insn (gen_movsi (tmp
, GEN_INT (mcore_stack_increment
)));
269 emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, tmp
));
270 memref
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
271 MEM_VOLATILE_P (memref
) = 1;
272 emit_insn (gen_movsi (memref
, stack_pointer_rtx
));
273 size
-= mcore_stack_increment
;
275 while (size
> mcore_stack_increment
);
277 /* SIZE is now the residual for the last adjustment,
278 which doesn't require a probe. */
284 rtx val
= GEN_INT (size
);
288 rtx nval
= gen_rtx_REG (SImode
, 1);
289 emit_insn (gen_movsi (nval
, val
));
294 insn
= gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, val
);
296 insn
= gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
, val
);
302 /* Work out the registers which need to be saved,
303 both as a mask and a count. */
306 calc_live_regs (int * count
)
309 int live_regs_mask
= 0;
313 for (reg
= 0; reg
< FIRST_PSEUDO_REGISTER
; reg
++)
315 if (df_regs_ever_live_p (reg
) && !call_used_regs
[reg
])
318 live_regs_mask
|= (1 << reg
);
322 return live_regs_mask
;
325 /* Print the operand address in x to the stream. */
328 mcore_print_operand_address (FILE * stream
, machine_mode
/*mode*/, rtx x
)
330 switch (GET_CODE (x
))
333 fprintf (stream
, "(%s)", reg_names
[REGNO (x
)]);
338 rtx base
= XEXP (x
, 0);
339 rtx index
= XEXP (x
, 1);
341 if (GET_CODE (base
) != REG
)
343 /* Ensure that BASE is a register (one of them must be). */
349 switch (GET_CODE (index
))
352 fprintf (stream
, "(%s," HOST_WIDE_INT_PRINT_DEC
")",
353 reg_names
[REGNO(base
)], INTVAL (index
));
364 output_addr_const (stream
, x
);
370 mcore_print_operand_punct_valid_p (unsigned char code
)
372 return (code
== '.' || code
== '#' || code
== '*' || code
== '^'
376 /* Print operand x (an rtx) in assembler syntax to file stream
377 according to modifier code.
379 'R' print the next register or memory location along, i.e. the lsw in
381 'O' print a constant without the #
382 'M' print a constant as its negative
383 'P' print log2 of a power of two
384 'Q' print log2 of an inverse of a power of two
385 'U' print register for ldm/stm instruction
386 'X' print byte number for xtrbN instruction. */
389 mcore_print_operand (FILE * stream
, rtx x
, int code
)
395 fprintf (asm_out_file
, "32");
397 fprintf (asm_out_file
, "%d", exact_log2 (INTVAL (x
) + 1));
400 fprintf (asm_out_file
, "%d", exact_log2 (INTVAL (x
) & 0xffffffff));
403 fprintf (asm_out_file
, "%d", exact_log2 (~INTVAL (x
)));
406 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, INTVAL (x
));
409 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, - INTVAL (x
));
412 /* Next location along in memory or register. */
413 switch (GET_CODE (x
))
416 fputs (reg_names
[REGNO (x
) + 1], (stream
));
419 mcore_print_operand_address
420 (stream
, GET_MODE (x
), XEXP (adjust_address (x
, SImode
, 4), 0));
427 fprintf (asm_out_file
, "%s-%s", reg_names
[REGNO (x
)],
428 reg_names
[REGNO (x
) + 3]);
431 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
434 fprintf (asm_out_file
, HOST_WIDE_INT_PRINT_DEC
, 3 - INTVAL (x
) / 8);
438 switch (GET_CODE (x
))
441 fputs (reg_names
[REGNO (x
)], (stream
));
444 output_address (GET_MODE (x
), XEXP (x
, 0));
447 output_addr_const (stream
, x
);
454 /* What does a constant cost ? */
457 mcore_const_costs (rtx exp
, enum rtx_code code
)
459 HOST_WIDE_INT val
= INTVAL (exp
);
461 /* Easy constants. */
462 if ( CONST_OK_FOR_I (val
)
463 || CONST_OK_FOR_M (val
)
464 || CONST_OK_FOR_N (val
)
465 || (code
== PLUS
&& CONST_OK_FOR_L (val
)))
468 && ( CONST_OK_FOR_M (~val
)
469 || CONST_OK_FOR_N (~val
)))
471 else if (code
== PLUS
472 && ( CONST_OK_FOR_I (-val
)
473 || CONST_OK_FOR_M (-val
)
474 || CONST_OK_FOR_N (-val
)))
480 /* What does an and instruction cost - we do this b/c immediates may
481 have been relaxed. We want to ensure that cse will cse relaxed immeds
482 out. Otherwise we'll get bad code (multiple reloads of the same const). */
485 mcore_and_cost (rtx x
)
489 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
492 val
= INTVAL (XEXP (x
, 1));
494 /* Do it directly. */
495 if (CONST_OK_FOR_K (val
) || CONST_OK_FOR_M (~val
))
497 /* Takes one instruction to load. */
498 else if (const_ok_for_mcore (val
))
500 /* Takes two instructions to load. */
501 else if (TARGET_HARDLIT
&& mcore_const_ok_for_inline (val
))
504 /* Takes a lrw to load. */
508 /* What does an or cost - see and_cost(). */
511 mcore_ior_cost (rtx x
)
515 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
518 val
= INTVAL (XEXP (x
, 1));
520 /* Do it directly with bclri. */
521 if (CONST_OK_FOR_M (val
))
523 /* Takes one instruction to load. */
524 else if (const_ok_for_mcore (val
))
526 /* Takes two instructions to load. */
527 else if (TARGET_HARDLIT
&& mcore_const_ok_for_inline (val
))
530 /* Takes a lrw to load. */
535 mcore_rtx_costs (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
, int outer_code
,
536 int opno ATTRIBUTE_UNUSED
,
537 int * total
, bool speed ATTRIBUTE_UNUSED
)
539 int code
= GET_CODE (x
);
544 *total
= mcore_const_costs (x
, (enum rtx_code
) outer_code
);
556 *total
= COSTS_N_INSNS (mcore_and_cost (x
));
560 *total
= COSTS_N_INSNS (mcore_ior_cost (x
));
569 *total
= COSTS_N_INSNS (100);
577 /* Prepare the operands for a comparison. Return whether the branch/setcc
578 should reverse the operands. */
581 mcore_gen_compare (enum rtx_code code
, rtx op0
, rtx op1
)
583 rtx cc_reg
= gen_rtx_REG (CCmode
, CC_REG
);
586 if (GET_CODE (op1
) == CONST_INT
)
588 HOST_WIDE_INT val
= INTVAL (op1
);
593 /* Unsigned > 0 is the same as != 0; everything else is converted
594 below to LEU (reversed cmphs). */
599 /* Check whether (LE A imm) can become (LT A imm + 1),
600 or (GT A imm) can become (GE A imm + 1). */
603 if (CONST_OK_FOR_J (val
+ 1))
605 op1
= GEN_INT (val
+ 1);
606 code
= code
== LE
? LT
: GE
;
615 if (CONSTANT_P (op1
) && GET_CODE (op1
) != CONST_INT
)
616 op1
= force_reg (SImode
, op1
);
618 /* cmpnei: 0-31 (K immediate)
619 cmplti: 1-32 (J immediate, 0 using btsti x,31). */
623 case EQ
: /* Use inverted condition, cmpne. */
628 case NE
: /* Use normal condition, cmpne. */
629 if (GET_CODE (op1
) == CONST_INT
&& ! CONST_OK_FOR_K (INTVAL (op1
)))
630 op1
= force_reg (SImode
, op1
);
633 case LE
: /* Use inverted condition, reversed cmplt. */
638 case GT
: /* Use normal condition, reversed cmplt. */
639 if (GET_CODE (op1
) == CONST_INT
)
640 op1
= force_reg (SImode
, op1
);
643 case GE
: /* Use inverted condition, cmplt. */
648 case LT
: /* Use normal condition, cmplt. */
649 if (GET_CODE (op1
) == CONST_INT
&&
650 /* covered by btsti x,31. */
652 ! CONST_OK_FOR_J (INTVAL (op1
)))
653 op1
= force_reg (SImode
, op1
);
656 case GTU
: /* Use inverted condition, cmple. */
657 /* We coped with unsigned > 0 above. */
658 gcc_assert (GET_CODE (op1
) != CONST_INT
|| INTVAL (op1
) != 0);
663 case LEU
: /* Use normal condition, reversed cmphs. */
664 if (GET_CODE (op1
) == CONST_INT
&& INTVAL (op1
) != 0)
665 op1
= force_reg (SImode
, op1
);
668 case LTU
: /* Use inverted condition, cmphs. */
673 case GEU
: /* Use normal condition, cmphs. */
674 if (GET_CODE (op1
) == CONST_INT
&& INTVAL (op1
) != 0)
675 op1
= force_reg (SImode
, op1
);
682 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_fmt_ee (code
, CCmode
, op0
, op1
)));
687 mcore_symbolic_address_p (rtx x
)
689 switch (GET_CODE (x
))
696 return ( (GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
697 || GET_CODE (XEXP (x
, 0)) == LABEL_REF
)
698 && GET_CODE (XEXP (x
, 1)) == CONST_INT
);
704 /* Functions to output assembly code for a function call. */
707 mcore_output_call (rtx operands
[], int index
)
709 static char buffer
[20];
710 rtx addr
= operands
[index
];
716 gcc_assert (mcore_current_function_name
);
718 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
,
722 sprintf (buffer
, "jsr\t%%%d", index
);
728 gcc_assert (mcore_current_function_name
);
729 gcc_assert (GET_CODE (addr
) == SYMBOL_REF
);
731 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
,
735 sprintf (buffer
, "jbsr\t%%%d", index
);
741 /* Can we load a constant with a single instruction ? */
744 const_ok_for_mcore (HOST_WIDE_INT value
)
746 if (value
>= 0 && value
<= 127)
749 /* Try exact power of two. */
750 if (CONST_OK_FOR_M (value
))
753 /* Try exact power of two - 1. */
754 if (CONST_OK_FOR_N (value
) && value
!= -1)
760 /* Can we load a constant inline with up to 2 instructions ? */
763 mcore_const_ok_for_inline (HOST_WIDE_INT value
)
767 return try_constant_tricks (value
, & x
, & y
) > 0;
770 /* Are we loading the constant using a not ? */
773 mcore_const_trick_uses_not (HOST_WIDE_INT value
)
777 return try_constant_tricks (value
, & x
, & y
) == 2;
780 /* Try tricks to load a constant inline and return the trick number if
781 success (0 is non-inlinable).
784 1: single instruction (do the usual thing)
785 2: single insn followed by a 'not'
786 3: single insn followed by a subi
787 4: single insn followed by an addi
788 5: single insn followed by rsubi
789 6: single insn followed by bseti
790 7: single insn followed by bclri
791 8: single insn followed by rotli
792 9: single insn followed by lsli
793 10: single insn followed by ixh
794 11: single insn followed by ixw. */
797 try_constant_tricks (HOST_WIDE_INT value
, HOST_WIDE_INT
* x
, HOST_WIDE_INT
* y
)
800 unsigned HOST_WIDE_INT bit
, shf
, rot
;
802 if (const_ok_for_mcore (value
))
803 return 1; /* Do the usual thing. */
805 if (! TARGET_HARDLIT
)
808 if (const_ok_for_mcore (~value
))
814 for (i
= 1; i
<= 32; i
++)
816 if (const_ok_for_mcore (value
- i
))
824 if (const_ok_for_mcore (value
+ i
))
835 for (i
= 0; i
<= 31; i
++)
837 if (const_ok_for_mcore (i
- value
))
845 if (const_ok_for_mcore (value
& ~bit
))
852 if (const_ok_for_mcore (value
| bit
))
866 for (i
= 1; i
< 31; i
++)
870 /* MCore has rotate left. */
874 rot
|= c
; /* Simulate rotate. */
876 if (const_ok_for_mcore (rot
))
885 shf
= 0; /* Can't use logical shift, low order bit is one. */
889 if (shf
!= 0 && const_ok_for_mcore (shf
))
898 if ((value
% 3) == 0 && const_ok_for_mcore (value
/ 3))
905 if ((value
% 5) == 0 && const_ok_for_mcore (value
/ 5))
915 /* Check whether reg is dead at first. This is done by searching ahead
916 for either the next use (i.e., reg is live), a death note, or a set of
917 reg. Don't just use dead_or_set_p() since reload does not always mark
918 deaths (especially if PRESERVE_DEATH_NOTES_REGNO_P is not defined). We
919 can ignore subregs by extracting the actual register. BRC */
922 mcore_is_dead (rtx_insn
*first
, rtx reg
)
926 /* For mcore, subregs can't live independently of their parent regs. */
927 if (GET_CODE (reg
) == SUBREG
)
928 reg
= SUBREG_REG (reg
);
930 /* Dies immediately. */
931 if (dead_or_set_p (first
, reg
))
934 /* Look for conclusive evidence of live/death, otherwise we have
935 to assume that it is live. */
936 for (insn
= NEXT_INSN (first
); insn
; insn
= NEXT_INSN (insn
))
939 return 0; /* We lose track, assume it is alive. */
941 else if (CALL_P (insn
))
943 /* Call's might use it for target or register parms. */
944 if (reg_referenced_p (reg
, PATTERN (insn
))
945 || find_reg_fusage (insn
, USE
, reg
))
947 else if (dead_or_set_p (insn
, reg
))
950 else if (NONJUMP_INSN_P (insn
))
952 if (reg_referenced_p (reg
, PATTERN (insn
)))
954 else if (dead_or_set_p (insn
, reg
))
959 /* No conclusive evidence either way, we cannot take the chance
960 that control flow hid the use from us -- "I'm not dead yet". */
964 /* Count the number of ones in mask. */
967 mcore_num_ones (HOST_WIDE_INT mask
)
969 /* A trick to count set bits recently posted on comp.compilers. */
970 mask
= (mask
>> 1 & 0x55555555) + (mask
& 0x55555555);
971 mask
= ((mask
>> 2) & 0x33333333) + (mask
& 0x33333333);
972 mask
= ((mask
>> 4) + mask
) & 0x0f0f0f0f;
973 mask
= ((mask
>> 8) + mask
);
975 return (mask
+ (mask
>> 16)) & 0xff;
978 /* Count the number of zeros in mask. */
981 mcore_num_zeros (HOST_WIDE_INT mask
)
983 return 32 - mcore_num_ones (mask
);
986 /* Determine byte being masked. */
989 mcore_byte_offset (unsigned int mask
)
991 if (mask
== 0x00ffffffL
)
993 else if (mask
== 0xff00ffffL
)
995 else if (mask
== 0xffff00ffL
)
997 else if (mask
== 0xffffff00L
)
1003 /* Determine halfword being masked. */
1006 mcore_halfword_offset (unsigned int mask
)
1008 if (mask
== 0x0000ffffL
)
1010 else if (mask
== 0xffff0000L
)
1016 /* Output a series of bseti's corresponding to mask. */
1019 mcore_output_bseti (rtx dst
, int mask
)
1021 rtx out_operands
[2];
1024 out_operands
[0] = dst
;
1026 for (bit
= 0; bit
< 32; bit
++)
1028 if ((mask
& 0x1) == 0x1)
1030 out_operands
[1] = GEN_INT (bit
);
1032 output_asm_insn ("bseti\t%0,%1", out_operands
);
1040 /* Output a series of bclri's corresponding to mask. */
1043 mcore_output_bclri (rtx dst
, int mask
)
1045 rtx out_operands
[2];
1048 out_operands
[0] = dst
;
1050 for (bit
= 0; bit
< 32; bit
++)
1052 if ((mask
& 0x1) == 0x0)
1054 out_operands
[1] = GEN_INT (bit
);
1056 output_asm_insn ("bclri\t%0,%1", out_operands
);
1065 /* Output a conditional move of two constants that are +/- 1 within each
1066 other. See the "movtK" patterns in mcore.md. I'm not sure this is
1067 really worth the effort. */
1070 mcore_output_cmov (rtx operands
[], int cmp_t
, const char * test
)
1072 HOST_WIDE_INT load_value
;
1073 HOST_WIDE_INT adjust_value
;
1074 rtx out_operands
[4];
1076 out_operands
[0] = operands
[0];
1078 /* Check to see which constant is loadable. */
1079 if (const_ok_for_mcore (INTVAL (operands
[1])))
1081 out_operands
[1] = operands
[1];
1082 out_operands
[2] = operands
[2];
1084 else if (const_ok_for_mcore (INTVAL (operands
[2])))
1086 out_operands
[1] = operands
[2];
1087 out_operands
[2] = operands
[1];
1089 /* Complement test since constants are swapped. */
1090 cmp_t
= (cmp_t
== 0);
1092 load_value
= INTVAL (out_operands
[1]);
1093 adjust_value
= INTVAL (out_operands
[2]);
1095 /* First output the test if folded into the pattern. */
1098 output_asm_insn (test
, operands
);
1100 /* Load the constant - for now, only support constants that can be
1101 generated with a single instruction. maybe add general inlinable
1102 constants later (this will increase the # of patterns since the
1103 instruction sequence has a different length attribute). */
1104 if (load_value
>= 0 && load_value
<= 127)
1105 output_asm_insn ("movi\t%0,%1", out_operands
);
1106 else if (CONST_OK_FOR_M (load_value
))
1107 output_asm_insn ("bgeni\t%0,%P1", out_operands
);
1108 else if (CONST_OK_FOR_N (load_value
))
1109 output_asm_insn ("bmaski\t%0,%N1", out_operands
);
1111 /* Output the constant adjustment. */
1112 if (load_value
> adjust_value
)
1115 output_asm_insn ("decf\t%0", out_operands
);
1117 output_asm_insn ("dect\t%0", out_operands
);
1122 output_asm_insn ("incf\t%0", out_operands
);
1124 output_asm_insn ("inct\t%0", out_operands
);
1130 /* Outputs the peephole for moving a constant that gets not'ed followed
1131 by an and (i.e. combine the not and the and into andn). BRC */
1134 mcore_output_andn (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[])
1137 rtx out_operands
[3];
1138 const char * load_op
;
1142 trick_no
= try_constant_tricks (INTVAL (operands
[1]), &x
, &y
);
1143 gcc_assert (trick_no
== 2);
1145 out_operands
[0] = operands
[0];
1146 out_operands
[1] = GEN_INT (x
);
1147 out_operands
[2] = operands
[2];
1149 if (x
>= 0 && x
<= 127)
1150 load_op
= "movi\t%0,%1";
1152 /* Try exact power of two. */
1153 else if (CONST_OK_FOR_M (x
))
1154 load_op
= "bgeni\t%0,%P1";
1156 /* Try exact power of two - 1. */
1157 else if (CONST_OK_FOR_N (x
))
1158 load_op
= "bmaski\t%0,%N1";
1162 load_op
= "BADMOVI-andn\t%0, %1";
1166 sprintf (buf
, "%s\n\tandn\t%%2,%%0", load_op
);
1167 output_asm_insn (buf
, out_operands
);
1172 /* Output an inline constant. */
1175 output_inline_const (machine_mode mode
, rtx operands
[])
1177 HOST_WIDE_INT x
= 0, y
= 0;
1179 rtx out_operands
[3];
1182 const char *dst_fmt
;
1183 HOST_WIDE_INT value
;
1185 value
= INTVAL (operands
[1]);
1187 trick_no
= try_constant_tricks (value
, &x
, &y
);
1188 /* lrw's are handled separately: Large inlinable constants never get
1189 turned into lrw's. Our caller uses try_constant_tricks to back
1190 off to an lrw rather than calling this routine. */
1191 gcc_assert (trick_no
!= 0);
1196 /* operands: 0 = dst, 1 = load immed., 2 = immed. adjustment. */
1197 out_operands
[0] = operands
[0];
1198 out_operands
[1] = GEN_INT (x
);
1201 out_operands
[2] = GEN_INT (y
);
1203 /* Select dst format based on mode. */
1204 if (mode
== DImode
&& (! TARGET_LITTLE_END
))
1209 if (x
>= 0 && x
<= 127)
1210 sprintf (load_op
, "movi\t%s,%%1", dst_fmt
);
1212 /* Try exact power of two. */
1213 else if (CONST_OK_FOR_M (x
))
1214 sprintf (load_op
, "bgeni\t%s,%%P1", dst_fmt
);
1216 /* Try exact power of two - 1. */
1217 else if (CONST_OK_FOR_N (x
))
1218 sprintf (load_op
, "bmaski\t%s,%%N1", dst_fmt
);
1222 sprintf (load_op
, "BADMOVI-inline_const %s, %%1", dst_fmt
);
1229 strcpy (buf
, load_op
);
1232 sprintf (buf
, "%s\n\tnot\t%s\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1235 sprintf (buf
, "%s\n\taddi\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1238 sprintf (buf
, "%s\n\tsubi\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1241 /* Never happens unless -mrsubi, see try_constant_tricks(). */
1242 sprintf (buf
, "%s\n\trsubi\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1245 sprintf (buf
, "%s\n\tbseti\t%s,%%P2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1248 sprintf (buf
, "%s\n\tbclri\t%s,%%Q2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1251 sprintf (buf
, "%s\n\trotli\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1254 sprintf (buf
, "%s\n\tlsli\t%s,%%2\t// %ld 0x%lx", load_op
, dst_fmt
, value
, value
);
1257 sprintf (buf
, "%s\n\tixh\t%s,%s\t// %ld 0x%lx", load_op
, dst_fmt
, dst_fmt
, value
, value
);
1260 sprintf (buf
, "%s\n\tixw\t%s,%s\t// %ld 0x%lx", load_op
, dst_fmt
, dst_fmt
, value
, value
);
1266 output_asm_insn (buf
, out_operands
);
1271 /* Output a move of a word or less value. */
1274 mcore_output_move (rtx insn ATTRIBUTE_UNUSED
, rtx operands
[],
1275 machine_mode mode ATTRIBUTE_UNUSED
)
1277 rtx dst
= operands
[0];
1278 rtx src
= operands
[1];
1280 if (GET_CODE (dst
) == REG
)
1282 if (GET_CODE (src
) == REG
)
1284 if (REGNO (src
) == CC_REG
) /* r-c */
1287 return "mov\t%0,%1"; /* r-r*/
1289 else if (GET_CODE (src
) == MEM
)
1291 if (GET_CODE (XEXP (src
, 0)) == LABEL_REF
)
1292 return "lrw\t%0,[%1]"; /* a-R */
1294 switch (GET_MODE (src
)) /* r-m */
1297 return "ldw\t%0,%1";
1299 return "ld.h\t%0,%1";
1301 return "ld.b\t%0,%1";
1306 else if (GET_CODE (src
) == CONST_INT
)
1310 if (CONST_OK_FOR_I (INTVAL (src
))) /* r-I */
1311 return "movi\t%0,%1";
1312 else if (CONST_OK_FOR_M (INTVAL (src
))) /* r-M */
1313 return "bgeni\t%0,%P1\t// %1 %x1";
1314 else if (CONST_OK_FOR_N (INTVAL (src
))) /* r-N */
1315 return "bmaski\t%0,%N1\t// %1 %x1";
1316 else if (try_constant_tricks (INTVAL (src
), &x
, &y
)) /* R-P */
1317 return output_inline_const (SImode
, operands
); /* 1-2 insns */
1319 return "lrw\t%0,%x1\t// %1"; /* Get it from literal pool. */
1322 return "lrw\t%0, %1"; /* Into the literal pool. */
1324 else if (GET_CODE (dst
) == MEM
) /* m-r */
1325 switch (GET_MODE (dst
))
1328 return "stw\t%1,%0";
1330 return "st.h\t%1,%0";
1332 return "st.b\t%1,%0";
1340 /* Return a sequence of instructions to perform DI or DF move.
1341 Since the MCORE cannot move a DI or DF in one instruction, we have
1342 to take care when we see overlapping source and dest registers. */
1345 mcore_output_movedouble (rtx operands
[], machine_mode mode ATTRIBUTE_UNUSED
)
1347 rtx dst
= operands
[0];
1348 rtx src
= operands
[1];
1350 if (GET_CODE (dst
) == REG
)
1352 if (GET_CODE (src
) == REG
)
1354 int dstreg
= REGNO (dst
);
1355 int srcreg
= REGNO (src
);
1357 /* Ensure the second source not overwritten. */
1358 if (srcreg
+ 1 == dstreg
)
1359 return "mov %R0,%R1\n\tmov %0,%1";
1361 return "mov %0,%1\n\tmov %R0,%R1";
1363 else if (GET_CODE (src
) == MEM
)
1365 rtx memexp
= XEXP (src
, 0);
1366 int dstreg
= REGNO (dst
);
1369 if (GET_CODE (memexp
) == LABEL_REF
)
1370 return "lrw\t%0,[%1]\n\tlrw\t%R0,[%R1]";
1371 else if (GET_CODE (memexp
) == REG
)
1372 basereg
= REGNO (memexp
);
1373 else if (GET_CODE (memexp
) == PLUS
)
1375 if (GET_CODE (XEXP (memexp
, 0)) == REG
)
1376 basereg
= REGNO (XEXP (memexp
, 0));
1377 else if (GET_CODE (XEXP (memexp
, 1)) == REG
)
1378 basereg
= REGNO (XEXP (memexp
, 1));
1385 /* ??? length attribute is wrong here. */
1386 if (dstreg
== basereg
)
1388 /* Just load them in reverse order. */
1389 return "ldw\t%R0,%R1\n\tldw\t%0,%1";
1391 /* XXX: alternative: move basereg to basereg+1
1392 and then fall through. */
1395 return "ldw\t%0,%1\n\tldw\t%R0,%R1";
1397 else if (GET_CODE (src
) == CONST_INT
)
1399 if (TARGET_LITTLE_END
)
1401 if (CONST_OK_FOR_I (INTVAL (src
)))
1402 output_asm_insn ("movi %0,%1", operands
);
1403 else if (CONST_OK_FOR_M (INTVAL (src
)))
1404 output_asm_insn ("bgeni %0,%P1", operands
);
1405 else if (CONST_OK_FOR_N (INTVAL (src
)))
1406 output_asm_insn ("bmaski %0,%N1", operands
);
1410 if (INTVAL (src
) < 0)
1411 return "bmaski %R0,32";
1413 return "movi %R0,0";
1417 if (CONST_OK_FOR_I (INTVAL (src
)))
1418 output_asm_insn ("movi %R0,%1", operands
);
1419 else if (CONST_OK_FOR_M (INTVAL (src
)))
1420 output_asm_insn ("bgeni %R0,%P1", operands
);
1421 else if (CONST_OK_FOR_N (INTVAL (src
)))
1422 output_asm_insn ("bmaski %R0,%N1", operands
);
1426 if (INTVAL (src
) < 0)
1427 return "bmaski %0,32";
1435 else if (GET_CODE (dst
) == MEM
&& GET_CODE (src
) == REG
)
1436 return "stw\t%1,%0\n\tstw\t%R1,%R0";
1441 /* Predicates used by the templates. */
1444 mcore_arith_S_operand (rtx op
)
1446 if (GET_CODE (op
) == CONST_INT
&& CONST_OK_FOR_M (~INTVAL (op
)))
1452 /* Expand insert bit field. BRC */
1455 mcore_expand_insv (rtx operands
[])
1457 int width
= INTVAL (operands
[1]);
1458 int posn
= INTVAL (operands
[2]);
1460 rtx mreg
, sreg
, ereg
;
1462 /* To get width 1 insv, the test in store_bit_field() (expmed.c, line 191)
1463 for width==1 must be removed. Look around line 368. This is something
1464 we really want the md part to do. */
1465 if (width
== 1 && GET_CODE (operands
[3]) == CONST_INT
)
1467 /* Do directly with bseti or bclri. */
1468 /* RBE: 2/97 consider only low bit of constant. */
1469 if ((INTVAL (operands
[3]) & 1) == 0)
1471 mask
= ~(1 << posn
);
1472 emit_insn (gen_rtx_SET (operands
[0],
1473 gen_rtx_AND (SImode
, operands
[0],
1479 emit_insn (gen_rtx_SET (operands
[0],
1480 gen_rtx_IOR (SImode
, operands
[0],
1487 /* Look at some bit-field placements that we aren't interested
1488 in handling ourselves, unless specifically directed to do so. */
1489 if (! TARGET_W_FIELD
)
1490 return 0; /* Generally, give up about now. */
1492 if (width
== 8 && posn
% 8 == 0)
1493 /* Byte sized and aligned; let caller break it up. */
1496 if (width
== 16 && posn
% 16 == 0)
1497 /* Short sized and aligned; let caller break it up. */
1500 /* The general case - we can do this a little bit better than what the
1501 machine independent part tries. This will get rid of all the subregs
1502 that mess up constant folding in combine when working with relaxed
1505 /* If setting the entire field, do it directly. */
1506 if (GET_CODE (operands
[3]) == CONST_INT
1507 && INTVAL (operands
[3]) == ((1 << width
) - 1))
1509 mreg
= force_reg (SImode
, GEN_INT (INTVAL (operands
[3]) << posn
));
1510 emit_insn (gen_rtx_SET (operands
[0],
1511 gen_rtx_IOR (SImode
, operands
[0], mreg
)));
1515 /* Generate the clear mask. */
1516 mreg
= force_reg (SImode
, GEN_INT (~(((1 << width
) - 1) << posn
)));
1518 /* Clear the field, to overlay it later with the source. */
1519 emit_insn (gen_rtx_SET (operands
[0],
1520 gen_rtx_AND (SImode
, operands
[0], mreg
)));
1522 /* If the source is constant 0, we've nothing to add back. */
1523 if (GET_CODE (operands
[3]) == CONST_INT
&& INTVAL (operands
[3]) == 0)
1526 /* XXX: Should we worry about more games with constant values?
1527 We've covered the high profile: set/clear single-bit and many-bit
1528 fields. How often do we see "arbitrary bit pattern" constants? */
1529 sreg
= copy_to_mode_reg (SImode
, operands
[3]);
1531 /* Extract src as same width as dst (needed for signed values). We
1532 always have to do this since we widen everything to SImode.
1533 We don't have to mask if we're shifting this up against the
1534 MSB of the register (e.g., the shift will push out any hi-order
1536 if (width
+ posn
!= (int) GET_MODE_SIZE (SImode
))
1538 ereg
= force_reg (SImode
, GEN_INT ((1 << width
) - 1));
1539 emit_insn (gen_rtx_SET (sreg
, gen_rtx_AND (SImode
, sreg
, ereg
)));
1542 /* Insert source value in dest. */
1544 emit_insn (gen_rtx_SET (sreg
, gen_rtx_ASHIFT (SImode
, sreg
,
1547 emit_insn (gen_rtx_SET (operands
[0],
1548 gen_rtx_IOR (SImode
, operands
[0], sreg
)));
1553 /* ??? Block move stuff stolen from m88k. This code has not been
1554 verified for correctness. */
1556 /* Emit code to perform a block move. Choose the best method.
1558 OPERANDS[0] is the destination.
1559 OPERANDS[1] is the source.
1560 OPERANDS[2] is the size.
1561 OPERANDS[3] is the alignment safe to use. */
1563 /* Emit code to perform a block move with an offset sequence of ldw/st
1564 instructions (..., ldw 0, stw 1, ldw 1, stw 0, ...). SIZE and ALIGN are
1565 known constants. DEST and SRC are registers. OFFSET is the known
1566 starting point for the output pattern. */
1568 static const machine_mode mode_from_align
[] =
1570 VOIDmode
, QImode
, HImode
, VOIDmode
, SImode
,
1574 block_move_sequence (rtx dst_mem
, rtx src_mem
, int size
, int align
)
1577 machine_mode mode
[2];
1586 x
= XEXP (dst_mem
, 0);
1589 x
= force_reg (Pmode
, x
);
1590 dst_mem
= replace_equiv_address (dst_mem
, x
);
1593 x
= XEXP (src_mem
, 0);
1596 x
= force_reg (Pmode
, x
);
1597 src_mem
= replace_equiv_address (src_mem
, x
);
1600 active
[0] = active
[1] = false;
1611 next_amount
= (size
>= 4 ? 4 : (size
>= 2 ? 2 : 1));
1612 next_amount
= MIN (next_amount
, align
);
1614 amount
[next
] = next_amount
;
1615 mode
[next
] = mode_from_align
[next_amount
];
1616 temp
[next
] = gen_reg_rtx (mode
[next
]);
1618 x
= adjust_address (src_mem
, mode
[next
], offset_ld
);
1619 emit_insn (gen_rtx_SET (temp
[next
], x
));
1621 offset_ld
+= next_amount
;
1622 size
-= next_amount
;
1623 active
[next
] = true;
1628 active
[phase
] = false;
1630 x
= adjust_address (dst_mem
, mode
[phase
], offset_st
);
1631 emit_insn (gen_rtx_SET (x
, temp
[phase
]));
1633 offset_st
+= amount
[phase
];
1636 while (active
[next
]);
1640 mcore_expand_block_move (rtx
*operands
)
1642 HOST_WIDE_INT align
, bytes
, max
;
1644 if (GET_CODE (operands
[2]) != CONST_INT
)
1647 bytes
= INTVAL (operands
[2]);
1648 align
= INTVAL (operands
[3]);
1677 block_move_sequence (operands
[0], operands
[1], bytes
, align
);
1685 /* Code to generate prologue and epilogue sequences. */
1686 static int number_of_regs_before_varargs
;
1688 /* Set by TARGET_SETUP_INCOMING_VARARGS to indicate to prolog that this is
1689 for a varargs function. */
1690 static int current_function_anonymous_args
;
1692 #define STACK_BYTES (STACK_BOUNDARY/BITS_PER_UNIT)
1693 #define STORE_REACH (64) /* Maximum displace of word store + 4. */
1694 #define ADDI_REACH (32) /* Maximum addi operand. */
1697 layout_mcore_frame (struct mcore_frame
* infp
)
1705 unsigned int growths
;
1708 /* Might have to spill bytes to re-assemble a big argument that
1709 was passed partially in registers and partially on the stack. */
1710 nbytes
= crtl
->args
.pretend_args_size
;
1712 /* Determine how much space for spilled anonymous args (e.g., stdarg). */
1713 if (current_function_anonymous_args
)
1714 nbytes
+= (NPARM_REGS
- number_of_regs_before_varargs
) * UNITS_PER_WORD
;
1716 infp
->arg_size
= nbytes
;
1718 /* How much space to save non-volatile registers we stomp. */
1719 infp
->reg_mask
= calc_live_regs (& n
);
1720 infp
->reg_size
= n
* 4;
1722 /* And the rest of it... locals and space for overflowed outbounds. */
1723 infp
->local_size
= get_frame_size ();
1724 infp
->outbound_size
= crtl
->outgoing_args_size
;
1726 /* Make sure we have a whole number of words for the locals. */
1727 if (infp
->local_size
% STACK_BYTES
)
1728 infp
->local_size
= (infp
->local_size
+ STACK_BYTES
- 1) & ~ (STACK_BYTES
-1);
1730 /* Only thing we know we have to pad is the outbound space, since
1731 we've aligned our locals assuming that base of locals is aligned. */
1732 infp
->pad_local
= 0;
1734 infp
->pad_outbound
= 0;
1735 if (infp
->outbound_size
% STACK_BYTES
)
1736 infp
->pad_outbound
= STACK_BYTES
- (infp
->outbound_size
% STACK_BYTES
);
1738 /* Now we see how we want to stage the prologue so that it does
1739 the most appropriate stack growth and register saves to either:
1741 (2) reduce instruction space, or
1742 (3) reduce stack space. */
1743 for (i
= 0; i
< ARRAY_SIZE (infp
->growth
); i
++)
1744 infp
->growth
[i
] = 0;
1746 regarg
= infp
->reg_size
+ infp
->arg_size
;
1747 localregarg
= infp
->local_size
+ regarg
;
1748 outbounds
= infp
->outbound_size
+ infp
->pad_outbound
;
1751 /* XXX: Consider one where we consider localregarg + outbound too! */
1753 /* Frame of <= 32 bytes and using stm would get <= 2 registers.
1754 use stw's with offsets and buy the frame in one shot. */
1755 if (localregarg
<= ADDI_REACH
1756 && (infp
->reg_size
<= 8 || (infp
->reg_mask
& 0xc000) != 0xc000))
1758 /* Make sure we'll be aligned. */
1759 if (localregarg
% STACK_BYTES
)
1760 infp
->pad_reg
= STACK_BYTES
- (localregarg
% STACK_BYTES
);
1762 step
= localregarg
+ infp
->pad_reg
;
1763 infp
->reg_offset
= infp
->local_size
;
1765 if (outbounds
+ step
<= ADDI_REACH
&& !frame_pointer_needed
)
1768 infp
->reg_offset
+= outbounds
;
1772 infp
->arg_offset
= step
- 4;
1773 infp
->growth
[growths
++] = step
;
1774 infp
->reg_growth
= growths
;
1775 infp
->local_growth
= growths
;
1777 /* If we haven't already folded it in. */
1779 infp
->growth
[growths
++] = outbounds
;
1784 /* Frame can't be done with a single subi, but can be done with 2
1785 insns. If the 'stm' is getting <= 2 registers, we use stw's and
1786 shift some of the stack purchase into the first subi, so both are
1787 single instructions. */
1788 if (localregarg
<= STORE_REACH
1789 && (infp
->local_size
> ADDI_REACH
)
1790 && (infp
->reg_size
<= 8 || (infp
->reg_mask
& 0xc000) != 0xc000))
1794 /* Make sure we'll be aligned; use either pad_reg or pad_local. */
1795 if (localregarg
% STACK_BYTES
)
1796 infp
->pad_reg
= STACK_BYTES
- (localregarg
% STACK_BYTES
);
1798 all
= localregarg
+ infp
->pad_reg
+ infp
->pad_local
;
1799 step
= ADDI_REACH
; /* As much up front as we can. */
1803 /* XXX: Consider whether step will still be aligned; we believe so. */
1804 infp
->arg_offset
= step
- 4;
1805 infp
->growth
[growths
++] = step
;
1806 infp
->reg_growth
= growths
;
1807 infp
->reg_offset
= step
- infp
->pad_reg
- infp
->reg_size
;
1810 /* Can we fold in any space required for outbounds? */
1811 if (outbounds
+ all
<= ADDI_REACH
&& !frame_pointer_needed
)
1817 /* Get the rest of the locals in place. */
1819 infp
->growth
[growths
++] = step
;
1820 infp
->local_growth
= growths
;
1823 gcc_assert (all
== 0);
1825 /* Finish off if we need to do so. */
1827 infp
->growth
[growths
++] = outbounds
;
1832 /* Registers + args is nicely aligned, so we'll buy that in one shot.
1833 Then we buy the rest of the frame in 1 or 2 steps depending on
1834 whether we need a frame pointer. */
1835 if ((regarg
% STACK_BYTES
) == 0)
1837 infp
->growth
[growths
++] = regarg
;
1838 infp
->reg_growth
= growths
;
1839 infp
->arg_offset
= regarg
- 4;
1840 infp
->reg_offset
= 0;
1842 if (infp
->local_size
% STACK_BYTES
)
1843 infp
->pad_local
= STACK_BYTES
- (infp
->local_size
% STACK_BYTES
);
1845 step
= infp
->local_size
+ infp
->pad_local
;
1847 if (!frame_pointer_needed
)
1853 infp
->growth
[growths
++] = step
;
1854 infp
->local_growth
= growths
;
1856 /* If there's any left to be done. */
1858 infp
->growth
[growths
++] = outbounds
;
1863 /* XXX: optimizations that we'll want to play with....
1864 -- regarg is not aligned, but it's a small number of registers;
1865 use some of localsize so that regarg is aligned and then
1866 save the registers. */
1868 /* Simple encoding; plods down the stack buying the pieces as it goes.
1869 -- does not optimize space consumption.
1870 -- does not attempt to optimize instruction counts.
1871 -- but it is safe for all alignments. */
1872 if (regarg
% STACK_BYTES
!= 0)
1873 infp
->pad_reg
= STACK_BYTES
- (regarg
% STACK_BYTES
);
1875 infp
->growth
[growths
++] = infp
->arg_size
+ infp
->reg_size
+ infp
->pad_reg
;
1876 infp
->reg_growth
= growths
;
1877 infp
->arg_offset
= infp
->growth
[0] - 4;
1878 infp
->reg_offset
= 0;
1880 if (frame_pointer_needed
)
1882 if (infp
->local_size
% STACK_BYTES
!= 0)
1883 infp
->pad_local
= STACK_BYTES
- (infp
->local_size
% STACK_BYTES
);
1885 infp
->growth
[growths
++] = infp
->local_size
+ infp
->pad_local
;
1886 infp
->local_growth
= growths
;
1888 infp
->growth
[growths
++] = outbounds
;
1892 if ((infp
->local_size
+ outbounds
) % STACK_BYTES
!= 0)
1893 infp
->pad_local
= STACK_BYTES
- ((infp
->local_size
+ outbounds
) % STACK_BYTES
);
1895 infp
->growth
[growths
++] = infp
->local_size
+ infp
->pad_local
+ outbounds
;
1896 infp
->local_growth
= growths
;
1899 /* Anything else that we've forgotten?, plus a few consistency checks. */
1901 gcc_assert (infp
->reg_offset
>= 0);
1902 gcc_assert (growths
<= MAX_STACK_GROWS
);
1904 for (i
= 0; i
< growths
; i
++)
1905 gcc_assert (!(infp
->growth
[i
] % STACK_BYTES
));
1908 /* Define the offset between two registers, one to be eliminated, and
1909 the other its replacement, at the start of a routine. */
1912 mcore_initial_elimination_offset (int from
, int to
)
1916 struct mcore_frame fi
;
1918 layout_mcore_frame (& fi
);
1921 above_frame
= fi
.local_size
+ fi
.pad_local
+ fi
.reg_size
+ fi
.pad_reg
;
1923 below_frame
= fi
.outbound_size
+ fi
.pad_outbound
;
1925 if (from
== ARG_POINTER_REGNUM
&& to
== FRAME_POINTER_REGNUM
)
1928 if (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
1929 return above_frame
+ below_frame
;
1931 if (from
== FRAME_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
)
1937 /* Keep track of some information about varargs for the prolog. */
1940 mcore_setup_incoming_varargs (cumulative_args_t args_so_far_v
,
1941 machine_mode mode
, tree type
,
1942 int * ptr_pretend_size ATTRIBUTE_UNUSED
,
1943 int second_time ATTRIBUTE_UNUSED
)
1945 CUMULATIVE_ARGS
*args_so_far
= get_cumulative_args (args_so_far_v
);
1947 current_function_anonymous_args
= 1;
1949 /* We need to know how many argument registers are used before
1950 the varargs start, so that we can push the remaining argument
1951 registers during the prologue. */
1952 number_of_regs_before_varargs
= *args_so_far
+ mcore_num_arg_regs (mode
, type
);
1954 /* There is a bug somewhere in the arg handling code.
1955 Until I can find it this workaround always pushes the
1956 last named argument onto the stack. */
1957 number_of_regs_before_varargs
= *args_so_far
;
1959 /* The last named argument may be split between argument registers
1960 and the stack. Allow for this here. */
1961 if (number_of_regs_before_varargs
> NPARM_REGS
)
1962 number_of_regs_before_varargs
= NPARM_REGS
;
1966 mcore_expand_prolog (void)
1968 struct mcore_frame fi
;
1969 int space_allocated
= 0;
1972 /* Find out what we're doing. */
1973 layout_mcore_frame (&fi
);
1975 space_allocated
= fi
.arg_size
+ fi
.reg_size
+ fi
.local_size
+
1976 fi
.outbound_size
+ fi
.pad_outbound
+ fi
.pad_local
+ fi
.pad_reg
;
1980 /* Emit a symbol for this routine's frame size. */
1983 x
= DECL_RTL (current_function_decl
);
1985 gcc_assert (GET_CODE (x
) == MEM
);
1989 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
1991 free (mcore_current_function_name
);
1993 mcore_current_function_name
= xstrdup (XSTR (x
, 0));
1995 ASM_OUTPUT_CG_NODE (asm_out_file
, mcore_current_function_name
, space_allocated
);
1997 if (cfun
->calls_alloca
)
1998 ASM_OUTPUT_CG_EDGE (asm_out_file
, mcore_current_function_name
, "alloca", 1);
2001 We're looking at how the 8byte alignment affects stack layout
2002 and where we had to pad things. This emits information we can
2003 extract which tells us about frame sizes and the like. */
2004 fprintf (asm_out_file
,
2005 "\t.equ\t__$frame$info$_%s_$_%d_%d_x%x_%d_%d_%d,0\n",
2006 mcore_current_function_name
,
2007 fi
.arg_size
, fi
.reg_size
, fi
.reg_mask
,
2008 fi
.local_size
, fi
.outbound_size
,
2009 frame_pointer_needed
);
2012 if (mcore_naked_function_p ())
2015 /* Handle stdarg+regsaves in one shot: can't be more than 64 bytes. */
2016 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2018 /* If we have a parameter passed partially in regs and partially in memory,
2019 the registers will have been stored to memory already in function.c. So
2020 we only need to do something here for varargs functions. */
2021 if (fi
.arg_size
!= 0 && crtl
->args
.pretend_args_size
== 0)
2024 int rn
= FIRST_PARM_REG
+ NPARM_REGS
- 1;
2025 int remaining
= fi
.arg_size
;
2027 for (offset
= fi
.arg_offset
; remaining
>= 4; offset
-= 4, rn
--, remaining
-= 4)
2029 emit_insn (gen_movsi
2030 (gen_rtx_MEM (SImode
,
2031 plus_constant (Pmode
, stack_pointer_rtx
,
2033 gen_rtx_REG (SImode
, rn
)));
2037 /* Do we need another stack adjustment before we do the register saves? */
2038 if (growth
< fi
.reg_growth
)
2039 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2041 if (fi
.reg_size
!= 0)
2044 int offs
= fi
.reg_offset
;
2046 for (i
= 15; i
>= 0; i
--)
2048 if (offs
== 0 && i
== 15 && ((fi
.reg_mask
& 0xc000) == 0xc000))
2052 while (fi
.reg_mask
& (1 << first_reg
))
2056 emit_insn (gen_store_multiple (gen_rtx_MEM (SImode
, stack_pointer_rtx
),
2057 gen_rtx_REG (SImode
, first_reg
),
2058 GEN_INT (16 - first_reg
)));
2060 i
-= (15 - first_reg
);
2061 offs
+= (16 - first_reg
) * 4;
2063 else if (fi
.reg_mask
& (1 << i
))
2065 emit_insn (gen_movsi
2066 (gen_rtx_MEM (SImode
,
2067 plus_constant (Pmode
, stack_pointer_rtx
,
2069 gen_rtx_REG (SImode
, i
)));
2075 /* Figure the locals + outbounds. */
2076 if (frame_pointer_needed
)
2078 /* If we haven't already purchased to 'fp'. */
2079 if (growth
< fi
.local_growth
)
2080 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2082 emit_insn (gen_movsi (frame_pointer_rtx
, stack_pointer_rtx
));
2084 /* ... and then go any remaining distance for outbounds, etc. */
2085 if (fi
.growth
[growth
])
2086 output_stack_adjust (-1, fi
.growth
[growth
++]);
2090 if (growth
< fi
.local_growth
)
2091 output_stack_adjust (-1, fi
.growth
[growth
++]); /* Grows it. */
2092 if (fi
.growth
[growth
])
2093 output_stack_adjust (-1, fi
.growth
[growth
++]);
2098 mcore_expand_epilog (void)
2100 struct mcore_frame fi
;
2103 int growth
= MAX_STACK_GROWS
- 1 ;
2106 /* Find out what we're doing. */
2107 layout_mcore_frame(&fi
);
2109 if (mcore_naked_function_p ())
2112 /* If we had a frame pointer, restore the sp from that. */
2113 if (frame_pointer_needed
)
2115 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
2116 growth
= fi
.local_growth
- 1;
2120 /* XXX: while loop should accumulate and do a single sell. */
2121 while (growth
>= fi
.local_growth
)
2123 if (fi
.growth
[growth
] != 0)
2124 output_stack_adjust (1, fi
.growth
[growth
]);
2129 /* Make sure we've shrunk stack back to the point where the registers
2130 were laid down. This is typically 0/1 iterations. Then pull the
2131 register save information back off the stack. */
2132 while (growth
>= fi
.reg_growth
)
2133 output_stack_adjust ( 1, fi
.growth
[growth
--]);
2135 offs
= fi
.reg_offset
;
2137 for (i
= 15; i
>= 0; i
--)
2139 if (offs
== 0 && i
== 15 && ((fi
.reg_mask
& 0xc000) == 0xc000))
2143 /* Find the starting register. */
2146 while (fi
.reg_mask
& (1 << first_reg
))
2151 emit_insn (gen_load_multiple (gen_rtx_REG (SImode
, first_reg
),
2152 gen_rtx_MEM (SImode
, stack_pointer_rtx
),
2153 GEN_INT (16 - first_reg
)));
2155 i
-= (15 - first_reg
);
2156 offs
+= (16 - first_reg
) * 4;
2158 else if (fi
.reg_mask
& (1 << i
))
2160 emit_insn (gen_movsi
2161 (gen_rtx_REG (SImode
, i
),
2162 gen_rtx_MEM (SImode
,
2163 plus_constant (Pmode
, stack_pointer_rtx
,
2169 /* Give back anything else. */
2170 /* XXX: Should accumulate total and then give it back. */
2172 output_stack_adjust ( 1, fi
.growth
[growth
--]);
2175 /* This code is borrowed from the SH port. */
2177 /* The MCORE cannot load a large constant into a register, constants have to
2178 come from a pc relative load. The reference of a pc relative load
2179 instruction must be less than 1k in front of the instruction. This
2180 means that we often have to dump a constant inside a function, and
2181 generate code to branch around it.
2183 It is important to minimize this, since the branches will slow things
2184 down and make things bigger.
2186 Worst case code looks like:
2202 We fix this by performing a scan before scheduling, which notices which
2203 instructions need to have their operands fetched from the constant table
2204 and builds the table.
2208 scan, find an instruction which needs a pcrel move. Look forward, find the
2209 last barrier which is within MAX_COUNT bytes of the requirement.
2210 If there isn't one, make one. Process all the instructions between
2211 the find and the barrier.
2213 In the above example, we can tell that L3 is within 1k of L1, so
2214 the first move can be shrunk from the 2 insn+constant sequence into
2215 just 1 insn, and the constant moved to L3 to make:
2225 Then the second move becomes the target for the shortening process. */
2229 rtx value
; /* Value in table. */
2230 rtx label
; /* Label of value. */
2233 /* The maximum number of constants that can fit into one pool, since
2234 the pc relative range is 0...1020 bytes and constants are at least 4
2235 bytes long. We subtract 4 from the range to allow for the case where
2236 we need to add a branch/align before the constant pool. */
2238 #define MAX_COUNT 1016
2239 #define MAX_POOL_SIZE (MAX_COUNT/4)
2240 static pool_node pool_vector
[MAX_POOL_SIZE
];
2241 static int pool_size
;
2243 /* Dump out any constants accumulated in the final pass. These
2244 will only be labels. */
2247 mcore_output_jump_label_table (void)
2253 fprintf (asm_out_file
, "\t.align 2\n");
2255 for (i
= 0; i
< pool_size
; i
++)
2257 pool_node
* p
= pool_vector
+ i
;
2259 (*targetm
.asm_out
.internal_label
) (asm_out_file
, "L", CODE_LABEL_NUMBER (p
->label
));
2261 output_asm_insn (".long %0", &p
->value
);
2270 /* Check whether insn is a candidate for a conditional. */
2273 is_cond_candidate (rtx insn
)
2275 /* The only things we conditionalize are those that can be directly
2276 changed into a conditional. Only bother with SImode items. If
2277 we wanted to be a little more aggressive, we could also do other
2278 modes such as DImode with reg-reg move or load 0. */
2279 if (NONJUMP_INSN_P (insn
))
2281 rtx pat
= PATTERN (insn
);
2284 if (GET_CODE (pat
) != SET
)
2287 dst
= XEXP (pat
, 0);
2289 if ((GET_CODE (dst
) != REG
&&
2290 GET_CODE (dst
) != SUBREG
) ||
2291 GET_MODE (dst
) != SImode
)
2294 src
= XEXP (pat
, 1);
2296 if ((GET_CODE (src
) == REG
||
2297 (GET_CODE (src
) == SUBREG
&&
2298 GET_CODE (SUBREG_REG (src
)) == REG
)) &&
2299 GET_MODE (src
) == SImode
)
2300 return COND_MOV_INSN
;
2301 else if (GET_CODE (src
) == CONST_INT
&&
2303 return COND_CLR_INSN
;
2304 else if (GET_CODE (src
) == PLUS
&&
2305 (GET_CODE (XEXP (src
, 0)) == REG
||
2306 (GET_CODE (XEXP (src
, 0)) == SUBREG
&&
2307 GET_CODE (SUBREG_REG (XEXP (src
, 0))) == REG
)) &&
2308 GET_MODE (XEXP (src
, 0)) == SImode
&&
2309 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2310 INTVAL (XEXP (src
, 1)) == 1)
2311 return COND_INC_INSN
;
2312 else if (((GET_CODE (src
) == MINUS
&&
2313 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2314 INTVAL( XEXP (src
, 1)) == 1) ||
2315 (GET_CODE (src
) == PLUS
&&
2316 GET_CODE (XEXP (src
, 1)) == CONST_INT
&&
2317 INTVAL (XEXP (src
, 1)) == -1)) &&
2318 (GET_CODE (XEXP (src
, 0)) == REG
||
2319 (GET_CODE (XEXP (src
, 0)) == SUBREG
&&
2320 GET_CODE (SUBREG_REG (XEXP (src
, 0))) == REG
)) &&
2321 GET_MODE (XEXP (src
, 0)) == SImode
)
2322 return COND_DEC_INSN
;
2324 /* Some insns that we don't bother with:
2325 (set (rx:DI) (ry:DI))
2326 (set (rx:DI) (const_int 0))
2330 else if (JUMP_P (insn
)
2331 && GET_CODE (PATTERN (insn
)) == SET
2332 && GET_CODE (XEXP (PATTERN (insn
), 1)) == LABEL_REF
)
2333 return COND_BRANCH_INSN
;
2338 /* Emit a conditional version of insn and replace the old insn with the
2339 new one. Return the new insn if emitted. */
2342 emit_new_cond_insn (rtx_insn
*insn
, int cond
)
2348 if ((num
= is_cond_candidate (insn
)) == COND_NO
)
2351 pat
= PATTERN (insn
);
2353 if (NONJUMP_INSN_P (insn
))
2355 dst
= SET_DEST (pat
);
2356 src
= SET_SRC (pat
);
2360 dst
= JUMP_LABEL (insn
);
2369 c_insn
= gen_movt0 (dst
, src
, dst
);
2371 c_insn
= gen_movt0 (dst
, dst
, src
);
2376 c_insn
= gen_incscc (dst
, dst
);
2378 c_insn
= gen_incscc_false (dst
, dst
);
2383 c_insn
= gen_decscc (dst
, dst
);
2385 c_insn
= gen_decscc_false (dst
, dst
);
2388 case COND_BRANCH_INSN
:
2390 c_insn
= gen_branch_true (dst
);
2392 c_insn
= gen_branch_false (dst
);
2399 /* Only copy the notes if they exist. */
2400 if (rtx_length
[GET_CODE (c_insn
)] >= 7 && rtx_length
[GET_CODE (insn
)] >= 7)
2402 /* We really don't need to bother with the notes and links at this
2403 point, but go ahead and save the notes. This will help is_dead()
2404 when applying peepholes (links don't matter since they are not
2405 used any more beyond this point for the mcore). */
2406 REG_NOTES (c_insn
) = REG_NOTES (insn
);
2409 if (num
== COND_BRANCH_INSN
)
2411 /* For jumps, we need to be a little bit careful and emit the new jump
2412 before the old one and to update the use count for the target label.
2413 This way, the barrier following the old (uncond) jump will get
2414 deleted, but the label won't. */
2415 c_insn
= emit_jump_insn_before (c_insn
, insn
);
2417 ++ LABEL_NUSES (dst
);
2419 JUMP_LABEL (c_insn
) = dst
;
2422 c_insn
= emit_insn_after (c_insn
, insn
);
2426 return as_a
<rtx_insn
*> (c_insn
);
2429 /* Attempt to change a basic block into a series of conditional insns. This
2430 works by taking the branch at the end of the 1st block and scanning for the
2431 end of the 2nd block. If all instructions in the 2nd block have cond.
2432 versions and the label at the start of block 3 is the same as the target
2433 from the branch at block 1, then conditionalize all insn in block 2 using
2434 the inverse condition of the branch at block 1. (Note I'm bending the
2435 definition of basic block here.)
2439 bt L2 <-- end of block 1 (delete)
2442 br L3 <-- end of block 2
2444 L2: ... <-- start of block 3 (NUSES==1)
2455 we can delete the L2 label if NUSES==1 and re-apply the optimization
2456 starting at the last instruction of block 2. This may allow an entire
2457 if-then-else statement to be conditionalized. BRC */
2459 conditionalize_block (rtx_insn
*first
)
2463 rtx_insn
*end_blk_1_br
= 0;
2464 rtx_insn
*end_blk_2_insn
= 0;
2465 rtx_insn
*start_blk_3_lab
= 0;
2471 /* Check that the first insn is a candidate conditional jump. This is
2472 the one that we'll eliminate. If not, advance to the next insn to
2474 if (! JUMP_P (first
)
2475 || GET_CODE (PATTERN (first
)) != SET
2476 || GET_CODE (XEXP (PATTERN (first
), 1)) != IF_THEN_ELSE
)
2477 return NEXT_INSN (first
);
2479 /* Extract some information we need. */
2480 end_blk_1_br
= first
;
2481 br_pat
= PATTERN (end_blk_1_br
);
2483 /* Complement the condition since we use the reverse cond. for the insns. */
2484 cond
= (GET_CODE (XEXP (XEXP (br_pat
, 1), 0)) == EQ
);
2486 /* Determine what kind of branch we have. */
2487 if (GET_CODE (XEXP (XEXP (br_pat
, 1), 1)) == LABEL_REF
)
2489 /* A normal branch, so extract label out of first arm. */
2490 br_lab_num
= CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat
, 1), 1), 0));
2494 /* An inverse branch, so extract the label out of the 2nd arm
2495 and complement the condition. */
2497 br_lab_num
= CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat
, 1), 2), 0));
2500 /* Scan forward for the start of block 2: it must start with a
2501 label and that label must be the same as the branch target
2502 label from block 1. We don't care about whether block 2 actually
2503 ends with a branch or a label (an uncond. branch is
2504 conditionalizable). */
2505 for (insn
= NEXT_INSN (first
); insn
; insn
= NEXT_INSN (insn
))
2509 code
= GET_CODE (insn
);
2511 /* Look for the label at the start of block 3. */
2512 if (code
== CODE_LABEL
&& CODE_LABEL_NUMBER (insn
) == br_lab_num
)
2515 /* Skip barriers, notes, and conditionalizable insns. If the
2516 insn is not conditionalizable or makes this optimization fail,
2517 just return the next insn so we can start over from that point. */
2518 if (code
!= BARRIER
&& code
!= NOTE
&& !is_cond_candidate (insn
))
2519 return NEXT_INSN (insn
);
2521 /* Remember the last real insn before the label (i.e. end of block 2). */
2522 if (code
== JUMP_INSN
|| code
== INSN
)
2525 end_blk_2_insn
= insn
;
2532 /* It is possible for this optimization to slow performance if the blocks
2533 are long. This really depends upon whether the branch is likely taken
2534 or not. If the branch is taken, we slow performance in many cases. But,
2535 if the branch is not taken, we always help performance (for a single
2536 block, but for a double block (i.e. when the optimization is re-applied)
2537 this is not true since the 'right thing' depends on the overall length of
2538 the collapsed block). As a compromise, don't apply this optimization on
2539 blocks larger than size 2 (unlikely for the mcore) when speed is important.
2540 the best threshold depends on the latencies of the instructions (i.e.,
2541 the branch penalty). */
2542 if (optimize
> 1 && blk_size
> 2)
2545 /* At this point, we've found the start of block 3 and we know that
2546 it is the destination of the branch from block 1. Also, all
2547 instructions in the block 2 are conditionalizable. So, apply the
2548 conditionalization and delete the branch. */
2549 start_blk_3_lab
= insn
;
2551 for (insn
= NEXT_INSN (end_blk_1_br
); insn
!= start_blk_3_lab
;
2552 insn
= NEXT_INSN (insn
))
2556 if (insn
->deleted ())
2559 /* Try to form a conditional variant of the instruction and emit it. */
2560 if ((newinsn
= emit_new_cond_insn (insn
, cond
)))
2562 if (end_blk_2_insn
== insn
)
2563 end_blk_2_insn
= newinsn
;
2569 /* Note whether we will delete the label starting blk 3 when the jump
2570 gets deleted. If so, we want to re-apply this optimization at the
2571 last real instruction right before the label. */
2572 if (LABEL_NUSES (start_blk_3_lab
) == 1)
2574 start_blk_3_lab
= 0;
2577 /* ??? we probably should redistribute the death notes for this insn, esp.
2578 the death of cc, but it doesn't really matter this late in the game.
2579 The peepholes all use is_dead() which will find the correct death
2580 regardless of whether there is a note. */
2581 delete_insn (end_blk_1_br
);
2583 if (! start_blk_3_lab
)
2584 return end_blk_2_insn
;
2586 /* Return the insn right after the label at the start of block 3. */
2587 return NEXT_INSN (start_blk_3_lab
);
2590 /* Apply the conditionalization of blocks optimization. This is the
2591 outer loop that traverses through the insns scanning for a branch
2592 that signifies an opportunity to apply the optimization. Note that
2593 this optimization is applied late. If we could apply it earlier,
2594 say before cse 2, it may expose more optimization opportunities.
2595 but, the pay back probably isn't really worth the effort (we'd have
2596 to update all reg/flow/notes/links/etc to make it work - and stick it
2597 in before cse 2). */
2600 conditionalize_optimization (void)
2604 for (insn
= get_insns (); insn
; insn
= conditionalize_block (insn
))
2608 /* This is to handle loads from the constant pool. */
2613 /* Reset this variable. */
2614 current_function_anonymous_args
= 0;
2619 /* Conditionalize blocks where we can. */
2620 conditionalize_optimization ();
2622 /* Literal pool generation is now pushed off until the assembler. */
2626 /* Return true if X is something that can be moved directly into r15. */
2629 mcore_r15_operand_p (rtx x
)
2631 switch (GET_CODE (x
))
2634 return mcore_const_ok_for_inline (INTVAL (x
));
2646 /* Implement SECONDARY_RELOAD_CLASS. If RCLASS contains r15, and we can't
2647 directly move X into it, use r1-r14 as a temporary. */
2650 mcore_secondary_reload_class (enum reg_class rclass
,
2651 machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2653 if (TEST_HARD_REG_BIT (reg_class_contents
[rclass
], 15)
2654 && !mcore_r15_operand_p (x
))
2659 /* Return the reg_class to use when reloading the rtx X into the class
2660 RCLASS. If X is too complex to move directly into r15, prefer to
2661 use LRW_REGS instead. */
2664 mcore_reload_class (rtx x
, enum reg_class rclass
)
2666 if (reg_class_subset_p (LRW_REGS
, rclass
) && !mcore_r15_operand_p (x
))
2672 /* Tell me if a pair of reg/subreg rtx's actually refer to the same
2673 register. Note that the current version doesn't worry about whether
2674 they are the same mode or note (e.g., a QImode in r2 matches an HImode
2675 in r2 matches an SImode in r2. Might think in the future about whether
2676 we want to be able to say something about modes. */
2679 mcore_is_same_reg (rtx x
, rtx y
)
2681 /* Strip any and all of the subreg wrappers. */
2682 while (GET_CODE (x
) == SUBREG
)
2685 while (GET_CODE (y
) == SUBREG
)
2688 if (GET_CODE(x
) == REG
&& GET_CODE(y
) == REG
&& REGNO(x
) == REGNO(y
))
2695 mcore_option_override (void)
2697 /* Only the m340 supports little endian code. */
2698 if (TARGET_LITTLE_END
&& ! TARGET_M340
)
2699 target_flags
|= MASK_M340
;
2703 /* Compute the number of word sized registers needed to
2704 hold a function argument of mode MODE and type TYPE. */
2707 mcore_num_arg_regs (machine_mode mode
, const_tree type
)
2711 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
2714 if (type
&& mode
== BLKmode
)
2715 size
= int_size_in_bytes (type
);
2717 size
= GET_MODE_SIZE (mode
);
2719 return ROUND_ADVANCE (size
);
2723 handle_structs_in_regs (machine_mode mode
, const_tree type
, int reg
)
2727 /* The MCore ABI defines that a structure whose size is not a whole multiple
2728 of bytes is passed packed into registers (or spilled onto the stack if
2729 not enough registers are available) with the last few bytes of the
2730 structure being packed, left-justified, into the last register/stack slot.
2731 GCC handles this correctly if the last word is in a stack slot, but we
2732 have to generate a special, PARALLEL RTX if the last word is in an
2733 argument register. */
2735 && TYPE_MODE (type
) == BLKmode
2736 && TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
2737 && (size
= int_size_in_bytes (type
)) > UNITS_PER_WORD
2738 && (size
% UNITS_PER_WORD
!= 0)
2739 && (reg
+ mcore_num_arg_regs (mode
, type
) <= (FIRST_PARM_REG
+ NPARM_REGS
)))
2741 rtx arg_regs
[NPARM_REGS
];
2746 for (nregs
= 0; size
> 0; size
-= UNITS_PER_WORD
)
2749 gen_rtx_EXPR_LIST (SImode
, gen_rtx_REG (SImode
, reg
++),
2750 GEN_INT (nregs
* UNITS_PER_WORD
));
2754 /* We assume here that NPARM_REGS == 6. The assert checks this. */
2755 gcc_assert (ARRAY_SIZE (arg_regs
) == 6);
2756 rtvec
= gen_rtvec (nregs
, arg_regs
[0], arg_regs
[1], arg_regs
[2],
2757 arg_regs
[3], arg_regs
[4], arg_regs
[5]);
2759 result
= gen_rtx_PARALLEL (mode
, rtvec
);
2763 return gen_rtx_REG (mode
, reg
);
2767 mcore_function_value (const_tree valtype
, const_tree func
)
2772 mode
= TYPE_MODE (valtype
);
2774 /* Since we promote return types, we must promote the mode here too. */
2775 mode
= promote_function_mode (valtype
, mode
, &unsigned_p
, func
, 1);
2777 return handle_structs_in_regs (mode
, valtype
, FIRST_RET_REG
);
2780 /* Define where to put the arguments to a function.
2781 Value is zero to push the argument on the stack,
2782 or a hard register in which to store the argument.
2784 MODE is the argument's machine mode.
2785 TYPE is the data type of the argument (as a tree).
2786 This is null for libcalls where that information may
2788 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2789 the preceding args and about the function being called.
2790 NAMED is nonzero if this argument is a named parameter
2791 (otherwise it is an extra parameter matching an ellipsis).
2793 On MCore the first args are normally in registers
2794 and the rest are pushed. Any arg that starts within the first
2795 NPARM_REGS words is at least partially passed in a register unless
2796 its data type forbids. */
2799 mcore_function_arg (cumulative_args_t cum
, machine_mode mode
,
2800 const_tree type
, bool named
)
2804 if (! named
|| mode
== VOIDmode
)
2807 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
2810 arg_reg
= ROUND_REG (*get_cumulative_args (cum
), mode
);
2812 if (arg_reg
< NPARM_REGS
)
2813 return handle_structs_in_regs (mode
, type
, FIRST_PARM_REG
+ arg_reg
);
2819 mcore_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
2820 const_tree type
, bool named ATTRIBUTE_UNUSED
)
2822 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2824 *cum
= (ROUND_REG (*cum
, mode
)
2825 + (int)named
* mcore_num_arg_regs (mode
, type
));
2829 mcore_function_arg_boundary (machine_mode mode
,
2830 const_tree type ATTRIBUTE_UNUSED
)
2832 /* Doubles must be aligned to an 8 byte boundary. */
2833 return (mode
!= BLKmode
&& GET_MODE_SIZE (mode
) == 8
2838 /* Returns the number of bytes of argument registers required to hold *part*
2839 of a parameter of machine mode MODE and type TYPE (which may be NULL if
2840 the type is not known). If the argument fits entirely in the argument
2841 registers, or entirely on the stack, then 0 is returned. CUM is the
2842 number of argument registers already used by earlier parameters to
2846 mcore_arg_partial_bytes (cumulative_args_t cum
, machine_mode mode
,
2847 tree type
, bool named
)
2849 int reg
= ROUND_REG (*get_cumulative_args (cum
), mode
);
2854 if (targetm
.calls
.must_pass_in_stack (mode
, type
))
2857 /* REG is not the *hardware* register number of the register that holds
2858 the argument, it is the *argument* register number. So for example,
2859 the first argument to a function goes in argument register 0, which
2860 translates (for the MCore) into hardware register 2. The second
2861 argument goes into argument register 1, which translates into hardware
2862 register 3, and so on. NPARM_REGS is the number of argument registers
2863 supported by the target, not the maximum hardware register number of
2865 if (reg
>= NPARM_REGS
)
2868 /* If the argument fits entirely in registers, return 0. */
2869 if (reg
+ mcore_num_arg_regs (mode
, type
) <= NPARM_REGS
)
2872 /* The argument overflows the number of available argument registers.
2873 Compute how many argument registers have not yet been assigned to
2874 hold an argument. */
2875 reg
= NPARM_REGS
- reg
;
2877 /* Return partially in registers and partially on the stack. */
2878 return reg
* UNITS_PER_WORD
;
2881 /* Return nonzero if SYMBOL is marked as being dllexport'd. */
2884 mcore_dllexport_name_p (const char * symbol
)
2886 return symbol
[0] == '@' && symbol
[1] == 'e' && symbol
[2] == '.';
2889 /* Return nonzero if SYMBOL is marked as being dllimport'd. */
2892 mcore_dllimport_name_p (const char * symbol
)
2894 return symbol
[0] == '@' && symbol
[1] == 'i' && symbol
[2] == '.';
2897 /* Mark a DECL as being dllexport'd. */
2900 mcore_mark_dllexport (tree decl
)
2902 const char * oldname
;
2907 rtlname
= XEXP (DECL_RTL (decl
), 0);
2909 if (GET_CODE (rtlname
) == MEM
)
2910 rtlname
= XEXP (rtlname
, 0);
2911 gcc_assert (GET_CODE (rtlname
) == SYMBOL_REF
);
2912 oldname
= XSTR (rtlname
, 0);
2914 if (mcore_dllexport_name_p (oldname
))
2915 return; /* Already done. */
2917 newname
= XALLOCAVEC (char, strlen (oldname
) + 4);
2918 sprintf (newname
, "@e.%s", oldname
);
2920 /* We pass newname through get_identifier to ensure it has a unique
2921 address. RTL processing can sometimes peek inside the symbol ref
2922 and compare the string's addresses to see if two symbols are
2924 /* ??? At least I think that's why we do this. */
2925 idp
= get_identifier (newname
);
2927 XEXP (DECL_RTL (decl
), 0) =
2928 gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (idp
));
2931 /* Mark a DECL as being dllimport'd. */
2934 mcore_mark_dllimport (tree decl
)
2936 const char * oldname
;
2942 rtlname
= XEXP (DECL_RTL (decl
), 0);
2944 if (GET_CODE (rtlname
) == MEM
)
2945 rtlname
= XEXP (rtlname
, 0);
2946 gcc_assert (GET_CODE (rtlname
) == SYMBOL_REF
);
2947 oldname
= XSTR (rtlname
, 0);
2949 gcc_assert (!mcore_dllexport_name_p (oldname
));
2950 if (mcore_dllimport_name_p (oldname
))
2951 return; /* Already done. */
2953 /* ??? One can well ask why we're making these checks here,
2954 and that would be a good question. */
2956 /* Imported variables can't be initialized. */
2957 if (TREE_CODE (decl
) == VAR_DECL
2958 && !DECL_VIRTUAL_P (decl
)
2959 && DECL_INITIAL (decl
))
2961 error ("initialized variable %q+D is marked dllimport", decl
);
2965 /* `extern' needn't be specified with dllimport.
2966 Specify `extern' now and hope for the best. Sigh. */
2967 if (TREE_CODE (decl
) == VAR_DECL
2968 /* ??? Is this test for vtables needed? */
2969 && !DECL_VIRTUAL_P (decl
))
2971 DECL_EXTERNAL (decl
) = 1;
2972 TREE_PUBLIC (decl
) = 1;
2975 newname
= XALLOCAVEC (char, strlen (oldname
) + 11);
2976 sprintf (newname
, "@i.__imp_%s", oldname
);
2978 /* We pass newname through get_identifier to ensure it has a unique
2979 address. RTL processing can sometimes peek inside the symbol ref
2980 and compare the string's addresses to see if two symbols are
2982 /* ??? At least I think that's why we do this. */
2983 idp
= get_identifier (newname
);
2985 newrtl
= gen_rtx_MEM (Pmode
,
2986 gen_rtx_SYMBOL_REF (Pmode
,
2987 IDENTIFIER_POINTER (idp
)));
2988 XEXP (DECL_RTL (decl
), 0) = newrtl
;
2992 mcore_dllexport_p (tree decl
)
2994 if ( TREE_CODE (decl
) != VAR_DECL
2995 && TREE_CODE (decl
) != FUNCTION_DECL
)
2998 return lookup_attribute ("dllexport", DECL_ATTRIBUTES (decl
)) != 0;
3002 mcore_dllimport_p (tree decl
)
3004 if ( TREE_CODE (decl
) != VAR_DECL
3005 && TREE_CODE (decl
) != FUNCTION_DECL
)
3008 return lookup_attribute ("dllimport", DECL_ATTRIBUTES (decl
)) != 0;
3011 /* We must mark dll symbols specially. Definitions of dllexport'd objects
3012 install some info in the .drective (PE) or .exports (ELF) sections. */
3015 mcore_encode_section_info (tree decl
, rtx rtl ATTRIBUTE_UNUSED
, int first ATTRIBUTE_UNUSED
)
3017 /* Mark the decl so we can tell from the rtl whether the object is
3018 dllexport'd or dllimport'd. */
3019 if (mcore_dllexport_p (decl
))
3020 mcore_mark_dllexport (decl
);
3021 else if (mcore_dllimport_p (decl
))
3022 mcore_mark_dllimport (decl
);
3024 /* It might be that DECL has already been marked as dllimport, but
3025 a subsequent definition nullified that. The attribute is gone
3026 but DECL_RTL still has @i.__imp_foo. We need to remove that. */
3027 else if ((TREE_CODE (decl
) == FUNCTION_DECL
3028 || TREE_CODE (decl
) == VAR_DECL
)
3029 && DECL_RTL (decl
) != NULL_RTX
3030 && GET_CODE (DECL_RTL (decl
)) == MEM
3031 && GET_CODE (XEXP (DECL_RTL (decl
), 0)) == MEM
3032 && GET_CODE (XEXP (XEXP (DECL_RTL (decl
), 0), 0)) == SYMBOL_REF
3033 && mcore_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl
), 0), 0), 0)))
3035 const char * oldname
= XSTR (XEXP (XEXP (DECL_RTL (decl
), 0), 0), 0);
3036 tree idp
= get_identifier (oldname
+ 9);
3037 rtx newrtl
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (idp
));
3039 XEXP (DECL_RTL (decl
), 0) = newrtl
;
3041 /* We previously set TREE_PUBLIC and DECL_EXTERNAL.
3042 ??? We leave these alone for now. */
3046 /* Undo the effects of the above. */
3049 mcore_strip_name_encoding (const char * str
)
3051 return str
+ (str
[0] == '@' ? 3 : 0);
3054 /* MCore specific attribute support.
3055 dllexport - for exporting a function/variable that will live in a dll
3056 dllimport - for importing a function/variable from a dll
3057 naked - do not create a function prologue/epilogue. */
3059 /* Handle a "naked" attribute; arguments as in
3060 struct attribute_spec.handler. */
3063 mcore_handle_naked_attribute (tree
* node
, tree name
, tree args ATTRIBUTE_UNUSED
,
3064 int flags ATTRIBUTE_UNUSED
, bool * no_add_attrs
)
3066 if (TREE_CODE (*node
) != FUNCTION_DECL
)
3068 warning (OPT_Wattributes
, "%qE attribute only applies to functions",
3070 *no_add_attrs
= true;
3076 /* ??? It looks like this is PE specific? Oh well, this is what the
3077 old code did as well. */
3080 mcore_unique_section (tree decl
, int reloc ATTRIBUTE_UNUSED
)
3085 const char * prefix
;
3087 name
= IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl
));
3089 /* Strip off any encoding in name. */
3090 name
= (* targetm
.strip_name_encoding
) (name
);
3092 /* The object is put in, for example, section .text$foo.
3093 The linker will then ultimately place them in .text
3094 (everything from the $ on is stripped). */
3095 if (TREE_CODE (decl
) == FUNCTION_DECL
)
3097 /* For compatibility with EPOC, we ignore the fact that the
3098 section might have relocs against it. */
3099 else if (decl_readonly_section (decl
, 0))
3104 len
= strlen (name
) + strlen (prefix
);
3105 string
= XALLOCAVEC (char, len
+ 1);
3107 sprintf (string
, "%s%s", prefix
, name
);
3109 set_decl_section_name (decl
, string
);
3113 mcore_naked_function_p (void)
3115 return lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl
)) != NULL_TREE
;
3119 mcore_warn_func_return (tree decl
)
3121 /* Naked functions are implemented entirely in assembly, including the
3122 return sequence, so suppress warnings about this. */
3123 return lookup_attribute ("naked", DECL_ATTRIBUTES (decl
)) == NULL_TREE
;
3126 #ifdef OBJECT_FORMAT_ELF
3128 mcore_asm_named_section (const char *name
,
3129 unsigned int flags ATTRIBUTE_UNUSED
,
3130 tree decl ATTRIBUTE_UNUSED
)
3132 fprintf (asm_out_file
, "\t.section %s\n", name
);
3134 #endif /* OBJECT_FORMAT_ELF */
3136 /* Worker function for TARGET_ASM_EXTERNAL_LIBCALL. */
3139 mcore_external_libcall (rtx fun
)
3141 fprintf (asm_out_file
, "\t.import\t");
3142 assemble_name (asm_out_file
, XSTR (fun
, 0));
3143 fprintf (asm_out_file
, "\n");
3146 /* Worker function for TARGET_RETURN_IN_MEMORY. */
3149 mcore_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
3151 const HOST_WIDE_INT size
= int_size_in_bytes (type
);
3152 return (size
== -1 || size
> 2 * UNITS_PER_WORD
);
3155 /* Worker function for TARGET_ASM_TRAMPOLINE_TEMPLATE.
3156 Output assembler code for a block containing the constant parts
3157 of a trampoline, leaving space for the variable parts.
3159 On the MCore, the trampoline looks like:
3167 mcore_asm_trampoline_template (FILE *f
)
3169 fprintf (f
, "\t.short 0x7102\n");
3170 fprintf (f
, "\t.short 0x7d02\n");
3171 fprintf (f
, "\t.short 0x00cd\n");
3172 fprintf (f
, "\t.short 0x1e00\n");
3173 fprintf (f
, "\t.long 0\n");
3174 fprintf (f
, "\t.long 0\n");
3177 /* Worker function for TARGET_TRAMPOLINE_INIT. */
3180 mcore_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
3182 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
3185 emit_block_move (m_tramp
, assemble_trampoline_template (),
3186 GEN_INT (2*UNITS_PER_WORD
), BLOCK_OP_NORMAL
);
3188 mem
= adjust_address (m_tramp
, SImode
, 8);
3189 emit_move_insn (mem
, chain_value
);
3190 mem
= adjust_address (m_tramp
, SImode
, 12);
3191 emit_move_insn (mem
, fnaddr
);
3194 /* Implement TARGET_LEGITIMATE_CONSTANT_P
3196 On the MCore, allow anything but a double. */
3199 mcore_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
3201 return GET_CODE (x
) != CONST_DOUBLE
;
3204 /* Helper function for `mcore_legitimate_address_p'. */
3207 mcore_reg_ok_for_base_p (const_rtx reg
, bool strict_p
)
3210 return REGNO_OK_FOR_BASE_P (REGNO (reg
));
3212 return (REGNO (reg
) <= 16 || !HARD_REGISTER_P (reg
));
3216 mcore_base_register_rtx_p (const_rtx x
, bool strict_p
)
3218 return REG_P(x
) && mcore_reg_ok_for_base_p (x
, strict_p
);
3221 /* A legitimate index for a QI is 0..15, for HI is 0..30, for SI is 0..60,
3222 and for DI is 0..56 because we use two SI loads, etc. */
3225 mcore_legitimate_index_p (machine_mode mode
, const_rtx op
)
3227 if (CONST_INT_P (op
))
3229 if (GET_MODE_SIZE (mode
) >= 4
3230 && (((unsigned HOST_WIDE_INT
) INTVAL (op
)) % 4) == 0
3231 && ((unsigned HOST_WIDE_INT
) INTVAL (op
))
3232 <= (unsigned HOST_WIDE_INT
) 64 - GET_MODE_SIZE (mode
))
3234 if (GET_MODE_SIZE (mode
) == 2
3235 && (((unsigned HOST_WIDE_INT
) INTVAL (op
)) % 2) == 0
3236 && ((unsigned HOST_WIDE_INT
) INTVAL (op
)) <= 30)
3238 if (GET_MODE_SIZE (mode
) == 1
3239 && ((unsigned HOST_WIDE_INT
) INTVAL (op
)) <= 15)
3246 /* Worker function for TARGET_ADDR_SPACE_LEGITIMATE_ADDRESS_P.
3252 mcore_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
,
3255 gcc_assert (ADDR_SPACE_GENERIC_P (as
));
3257 if (mcore_base_register_rtx_p (x
, strict_p
))
3259 else if (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == LO_SUM
)
3261 rtx xop0
= XEXP (x
, 0);
3262 rtx xop1
= XEXP (x
, 1);
3263 if (mcore_base_register_rtx_p (xop0
, strict_p
)
3264 && mcore_legitimate_index_p (mode
, xop1
))
3266 if (mcore_base_register_rtx_p (xop1
, strict_p
)
3267 && mcore_legitimate_index_p (mode
, xop0
))
3274 /* Implement TARGET_HARD_REGNO_MODE_OK. We may keep double values in
3278 mcore_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
3280 if (TARGET_8ALIGN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3281 return (regno
& 1) == 0;
3286 /* Implement TARGET_MODES_TIEABLE_P. */
3289 mcore_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
3291 return mode1
== mode2
|| GET_MODE_CLASS (mode1
) == GET_MODE_CLASS (mode2
);