2017-12-01 Richard Biener <rguenther@suse.de>
[official-gcc.git] / gcc / config / m68k / m68k.c
blobcd2e15e2f6c8cc5cf05ae00ca4d88ee5c2e1cdef
1 /* Subroutines for insn-output.c for Motorola 68000 family.
2 Copyright (C) 1987-2017 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "backend.h"
24 #include "cfghooks.h"
25 #include "tree.h"
26 #include "stringpool.h"
27 #include "attribs.h"
28 #include "rtl.h"
29 #include "df.h"
30 #include "alias.h"
31 #include "fold-const.h"
32 #include "calls.h"
33 #include "stor-layout.h"
34 #include "varasm.h"
35 #include "regs.h"
36 #include "insn-config.h"
37 #include "conditions.h"
38 #include "output.h"
39 #include "insn-attr.h"
40 #include "recog.h"
41 #include "diagnostic-core.h"
42 #include "flags.h"
43 #include "expmed.h"
44 #include "dojump.h"
45 #include "explow.h"
46 #include "memmodel.h"
47 #include "emit-rtl.h"
48 #include "stmt.h"
49 #include "expr.h"
50 #include "reload.h"
51 #include "tm_p.h"
52 #include "target.h"
53 #include "debug.h"
54 #include "cfgrtl.h"
55 #include "cfganal.h"
56 #include "lcm.h"
57 #include "cfgbuild.h"
58 #include "cfgcleanup.h"
59 /* ??? Need to add a dependency between m68k.o and sched-int.h. */
60 #include "sched-int.h"
61 #include "insn-codes.h"
62 #include "opts.h"
63 #include "optabs.h"
64 #include "builtins.h"
65 #include "rtl-iter.h"
67 /* This file should be included last. */
68 #include "target-def.h"
70 enum reg_class regno_reg_class[] =
72 DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS,
73 DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS,
74 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
75 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS,
76 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
77 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
78 ADDR_REGS
82 /* The minimum number of integer registers that we want to save with the
83 movem instruction. Using two movel instructions instead of a single
84 moveml is about 15% faster for the 68020 and 68030 at no expense in
85 code size. */
86 #define MIN_MOVEM_REGS 3
88 /* The minimum number of floating point registers that we want to save
89 with the fmovem instruction. */
90 #define MIN_FMOVEM_REGS 1
92 /* Structure describing stack frame layout. */
93 struct m68k_frame
95 /* Stack pointer to frame pointer offset. */
96 HOST_WIDE_INT offset;
98 /* Offset of FPU registers. */
99 HOST_WIDE_INT foffset;
101 /* Frame size in bytes (rounded up). */
102 HOST_WIDE_INT size;
104 /* Data and address register. */
105 int reg_no;
106 unsigned int reg_mask;
108 /* FPU registers. */
109 int fpu_no;
110 unsigned int fpu_mask;
112 /* Offsets relative to ARG_POINTER. */
113 HOST_WIDE_INT frame_pointer_offset;
114 HOST_WIDE_INT stack_pointer_offset;
116 /* Function which the above information refers to. */
117 int funcdef_no;
120 /* Current frame information calculated by m68k_compute_frame_layout(). */
121 static struct m68k_frame current_frame;
123 /* Structure describing an m68k address.
125 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET,
126 with null fields evaluating to 0. Here:
128 - BASE satisfies m68k_legitimate_base_reg_p
129 - INDEX satisfies m68k_legitimate_index_reg_p
130 - OFFSET satisfies m68k_legitimate_constant_address_p
132 INDEX is either HImode or SImode. The other fields are SImode.
134 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC,
135 the address is (BASE)+. */
136 struct m68k_address {
137 enum rtx_code code;
138 rtx base;
139 rtx index;
140 rtx offset;
141 int scale;
144 static int m68k_sched_adjust_cost (rtx_insn *, int, rtx_insn *, int,
145 unsigned int);
146 static int m68k_sched_issue_rate (void);
147 static int m68k_sched_variable_issue (FILE *, int, rtx_insn *, int);
148 static void m68k_sched_md_init_global (FILE *, int, int);
149 static void m68k_sched_md_finish_global (FILE *, int);
150 static void m68k_sched_md_init (FILE *, int, int);
151 static void m68k_sched_dfa_pre_advance_cycle (void);
152 static void m68k_sched_dfa_post_advance_cycle (void);
153 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void);
155 static bool m68k_can_eliminate (const int, const int);
156 static void m68k_conditional_register_usage (void);
157 static bool m68k_legitimate_address_p (machine_mode, rtx, bool);
158 static void m68k_option_override (void);
159 static void m68k_override_options_after_change (void);
160 static rtx find_addr_reg (rtx);
161 static const char *singlemove_string (rtx *);
162 static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
163 HOST_WIDE_INT, tree);
164 static rtx m68k_struct_value_rtx (tree, int);
165 static tree m68k_handle_fndecl_attribute (tree *node, tree name,
166 tree args, int flags,
167 bool *no_add_attrs);
168 static void m68k_compute_frame_layout (void);
169 static bool m68k_save_reg (unsigned int regno, bool interrupt_handler);
170 static bool m68k_ok_for_sibcall_p (tree, tree);
171 static bool m68k_tls_symbol_p (rtx);
172 static rtx m68k_legitimize_address (rtx, rtx, machine_mode);
173 static bool m68k_rtx_costs (rtx, machine_mode, int, int, int *, bool);
174 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
175 static bool m68k_return_in_memory (const_tree, const_tree);
176 #endif
177 static void m68k_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
178 static void m68k_trampoline_init (rtx, tree, rtx);
179 static int m68k_return_pops_args (tree, tree, int);
180 static rtx m68k_delegitimize_address (rtx);
181 static void m68k_function_arg_advance (cumulative_args_t, machine_mode,
182 const_tree, bool);
183 static rtx m68k_function_arg (cumulative_args_t, machine_mode,
184 const_tree, bool);
185 static bool m68k_cannot_force_const_mem (machine_mode mode, rtx x);
186 static bool m68k_output_addr_const_extra (FILE *, rtx);
187 static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED;
188 static enum flt_eval_method
189 m68k_excess_precision (enum excess_precision_type);
190 static unsigned int m68k_hard_regno_nregs (unsigned int, machine_mode);
191 static bool m68k_hard_regno_mode_ok (unsigned int, machine_mode);
192 static bool m68k_modes_tieable_p (machine_mode, machine_mode);
194 /* Initialize the GCC target structure. */
196 #if INT_OP_GROUP == INT_OP_DOT_WORD
197 #undef TARGET_ASM_ALIGNED_HI_OP
198 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
199 #endif
201 #if INT_OP_GROUP == INT_OP_NO_DOT
202 #undef TARGET_ASM_BYTE_OP
203 #define TARGET_ASM_BYTE_OP "\tbyte\t"
204 #undef TARGET_ASM_ALIGNED_HI_OP
205 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t"
206 #undef TARGET_ASM_ALIGNED_SI_OP
207 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t"
208 #endif
210 #if INT_OP_GROUP == INT_OP_DC
211 #undef TARGET_ASM_BYTE_OP
212 #define TARGET_ASM_BYTE_OP "\tdc.b\t"
213 #undef TARGET_ASM_ALIGNED_HI_OP
214 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t"
215 #undef TARGET_ASM_ALIGNED_SI_OP
216 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t"
217 #endif
219 #undef TARGET_ASM_UNALIGNED_HI_OP
220 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
221 #undef TARGET_ASM_UNALIGNED_SI_OP
222 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
224 #undef TARGET_ASM_OUTPUT_MI_THUNK
225 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk
226 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
227 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
229 #undef TARGET_ASM_FILE_START_APP_OFF
230 #define TARGET_ASM_FILE_START_APP_OFF true
232 #undef TARGET_LEGITIMIZE_ADDRESS
233 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address
235 #undef TARGET_SCHED_ADJUST_COST
236 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost
238 #undef TARGET_SCHED_ISSUE_RATE
239 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate
241 #undef TARGET_SCHED_VARIABLE_ISSUE
242 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue
244 #undef TARGET_SCHED_INIT_GLOBAL
245 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global
247 #undef TARGET_SCHED_FINISH_GLOBAL
248 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global
250 #undef TARGET_SCHED_INIT
251 #define TARGET_SCHED_INIT m68k_sched_md_init
253 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE
254 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle
256 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE
257 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle
259 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
260 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
261 m68k_sched_first_cycle_multipass_dfa_lookahead
263 #undef TARGET_OPTION_OVERRIDE
264 #define TARGET_OPTION_OVERRIDE m68k_option_override
266 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
267 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change
269 #undef TARGET_RTX_COSTS
270 #define TARGET_RTX_COSTS m68k_rtx_costs
272 #undef TARGET_ATTRIBUTE_TABLE
273 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table
275 #undef TARGET_PROMOTE_PROTOTYPES
276 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
278 #undef TARGET_STRUCT_VALUE_RTX
279 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx
281 #undef TARGET_CANNOT_FORCE_CONST_MEM
282 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem
284 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
285 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p
287 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
288 #undef TARGET_RETURN_IN_MEMORY
289 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory
290 #endif
292 #ifdef HAVE_AS_TLS
293 #undef TARGET_HAVE_TLS
294 #define TARGET_HAVE_TLS (true)
296 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
297 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel
298 #endif
300 #undef TARGET_LRA_P
301 #define TARGET_LRA_P hook_bool_void_false
303 #undef TARGET_LEGITIMATE_ADDRESS_P
304 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p
306 #undef TARGET_CAN_ELIMINATE
307 #define TARGET_CAN_ELIMINATE m68k_can_eliminate
309 #undef TARGET_CONDITIONAL_REGISTER_USAGE
310 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage
312 #undef TARGET_TRAMPOLINE_INIT
313 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init
315 #undef TARGET_RETURN_POPS_ARGS
316 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args
318 #undef TARGET_DELEGITIMIZE_ADDRESS
319 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address
321 #undef TARGET_FUNCTION_ARG
322 #define TARGET_FUNCTION_ARG m68k_function_arg
324 #undef TARGET_FUNCTION_ARG_ADVANCE
325 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance
327 #undef TARGET_LEGITIMATE_CONSTANT_P
328 #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p
330 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
331 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra
333 #undef TARGET_C_EXCESS_PRECISION
334 #define TARGET_C_EXCESS_PRECISION m68k_excess_precision
336 /* The value stored by TAS. */
337 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
338 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128
340 #undef TARGET_HARD_REGNO_NREGS
341 #define TARGET_HARD_REGNO_NREGS m68k_hard_regno_nregs
342 #undef TARGET_HARD_REGNO_MODE_OK
343 #define TARGET_HARD_REGNO_MODE_OK m68k_hard_regno_mode_ok
345 #undef TARGET_MODES_TIEABLE_P
346 #define TARGET_MODES_TIEABLE_P m68k_modes_tieable_p
348 static const struct attribute_spec m68k_attribute_table[] =
350 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
351 affects_type_identity } */
352 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute,
353 false },
354 { "interrupt_handler", 0, 0, true, false, false,
355 m68k_handle_fndecl_attribute, false },
356 { "interrupt_thread", 0, 0, true, false, false,
357 m68k_handle_fndecl_attribute, false },
358 { NULL, 0, 0, false, false, false, NULL, false }
361 struct gcc_target targetm = TARGET_INITIALIZER;
363 /* Base flags for 68k ISAs. */
364 #define FL_FOR_isa_00 FL_ISA_68000
365 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010)
366 /* FL_68881 controls the default setting of -m68881. gcc has traditionally
367 generated 68881 code for 68020 and 68030 targets unless explicitly told
368 not to. */
369 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \
370 | FL_BITFIELD | FL_68881 | FL_CAS)
371 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040)
372 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020)
374 /* Base flags for ColdFire ISAs. */
375 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A)
376 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP)
377 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */
378 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV)
379 /* ISA_C is not upwardly compatible with ISA_B. */
380 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP)
382 enum m68k_isa
384 /* Traditional 68000 instruction sets. */
385 isa_00,
386 isa_10,
387 isa_20,
388 isa_40,
389 isa_cpu32,
390 /* ColdFire instruction set variants. */
391 isa_a,
392 isa_aplus,
393 isa_b,
394 isa_c,
395 isa_max
398 /* Information about one of the -march, -mcpu or -mtune arguments. */
399 struct m68k_target_selection
401 /* The argument being described. */
402 const char *name;
404 /* For -mcpu, this is the device selected by the option.
405 For -mtune and -march, it is a representative device
406 for the microarchitecture or ISA respectively. */
407 enum target_device device;
409 /* The M68K_DEVICE fields associated with DEVICE. See the comment
410 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */
411 const char *family;
412 enum uarch_type microarch;
413 enum m68k_isa isa;
414 unsigned long flags;
417 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */
418 static const struct m68k_target_selection all_devices[] =
420 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \
421 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA },
422 #include "m68k-devices.def"
423 #undef M68K_DEVICE
424 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
427 /* A list of all ISAs, mapping each one to a representative device.
428 Used for -march selection. */
429 static const struct m68k_target_selection all_isas[] =
431 #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
432 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
433 #include "m68k-isas.def"
434 #undef M68K_ISA
435 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
438 /* A list of all microarchitectures, mapping each one to a representative
439 device. Used for -mtune selection. */
440 static const struct m68k_target_selection all_microarchs[] =
442 #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \
443 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS },
444 #include "m68k-microarchs.def"
445 #undef M68K_MICROARCH
446 { NULL, unk_device, NULL, unk_arch, isa_max, 0 }
449 /* The entries associated with the -mcpu, -march and -mtune settings,
450 or null for options that have not been used. */
451 const struct m68k_target_selection *m68k_cpu_entry;
452 const struct m68k_target_selection *m68k_arch_entry;
453 const struct m68k_target_selection *m68k_tune_entry;
455 /* Which CPU we are generating code for. */
456 enum target_device m68k_cpu;
458 /* Which microarchitecture to tune for. */
459 enum uarch_type m68k_tune;
461 /* Which FPU to use. */
462 enum fpu_type m68k_fpu;
464 /* The set of FL_* flags that apply to the target processor. */
465 unsigned int m68k_cpu_flags;
467 /* The set of FL_* flags that apply to the processor to be tuned for. */
468 unsigned int m68k_tune_flags;
470 /* Asm templates for calling or jumping to an arbitrary symbolic address,
471 or NULL if such calls or jumps are not supported. The address is held
472 in operand 0. */
473 const char *m68k_symbolic_call;
474 const char *m68k_symbolic_jump;
476 /* Enum variable that corresponds to m68k_symbolic_call values. */
477 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var;
480 /* Implement TARGET_OPTION_OVERRIDE. */
482 static void
483 m68k_option_override (void)
485 const struct m68k_target_selection *entry;
486 unsigned long target_mask;
488 if (global_options_set.x_m68k_arch_option)
489 m68k_arch_entry = &all_isas[m68k_arch_option];
491 if (global_options_set.x_m68k_cpu_option)
492 m68k_cpu_entry = &all_devices[(int) m68k_cpu_option];
494 if (global_options_set.x_m68k_tune_option)
495 m68k_tune_entry = &all_microarchs[(int) m68k_tune_option];
497 /* User can choose:
499 -mcpu=
500 -march=
501 -mtune=
503 -march=ARCH should generate code that runs any processor
504 implementing architecture ARCH. -mcpu=CPU should override -march
505 and should generate code that runs on processor CPU, making free
506 use of any instructions that CPU understands. -mtune=UARCH applies
507 on top of -mcpu or -march and optimizes the code for UARCH. It does
508 not change the target architecture. */
509 if (m68k_cpu_entry)
511 /* Complain if the -march setting is for a different microarchitecture,
512 or includes flags that the -mcpu setting doesn't. */
513 if (m68k_arch_entry
514 && (m68k_arch_entry->microarch != m68k_cpu_entry->microarch
515 || (m68k_arch_entry->flags & ~m68k_cpu_entry->flags) != 0))
516 warning (0, "-mcpu=%s conflicts with -march=%s",
517 m68k_cpu_entry->name, m68k_arch_entry->name);
519 entry = m68k_cpu_entry;
521 else
522 entry = m68k_arch_entry;
524 if (!entry)
525 entry = all_devices + TARGET_CPU_DEFAULT;
527 m68k_cpu_flags = entry->flags;
529 /* Use the architecture setting to derive default values for
530 certain flags. */
531 target_mask = 0;
533 /* ColdFire is lenient about alignment. */
534 if (!TARGET_COLDFIRE)
535 target_mask |= MASK_STRICT_ALIGNMENT;
537 if ((m68k_cpu_flags & FL_BITFIELD) != 0)
538 target_mask |= MASK_BITFIELD;
539 if ((m68k_cpu_flags & FL_CF_HWDIV) != 0)
540 target_mask |= MASK_CF_HWDIV;
541 if ((m68k_cpu_flags & (FL_68881 | FL_CF_FPU)) != 0)
542 target_mask |= MASK_HARD_FLOAT;
543 target_flags |= target_mask & ~target_flags_explicit;
545 /* Set the directly-usable versions of the -mcpu and -mtune settings. */
546 m68k_cpu = entry->device;
547 if (m68k_tune_entry)
549 m68k_tune = m68k_tune_entry->microarch;
550 m68k_tune_flags = m68k_tune_entry->flags;
552 #ifdef M68K_DEFAULT_TUNE
553 else if (!m68k_cpu_entry && !m68k_arch_entry)
555 enum target_device dev;
556 dev = all_microarchs[M68K_DEFAULT_TUNE].device;
557 m68k_tune_flags = all_devices[dev].flags;
559 #endif
560 else
562 m68k_tune = entry->microarch;
563 m68k_tune_flags = entry->flags;
566 /* Set the type of FPU. */
567 m68k_fpu = (!TARGET_HARD_FLOAT ? FPUTYPE_NONE
568 : (m68k_cpu_flags & FL_COLDFIRE) != 0 ? FPUTYPE_COLDFIRE
569 : FPUTYPE_68881);
571 /* Sanity check to ensure that msep-data and mid-sahred-library are not
572 * both specified together. Doing so simply doesn't make sense.
574 if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY)
575 error ("cannot specify both -msep-data and -mid-shared-library");
577 /* If we're generating code for a separate A5 relative data segment,
578 * we've got to enable -fPIC as well. This might be relaxable to
579 * -fpic but it hasn't been tested properly.
581 if (TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY)
582 flag_pic = 2;
584 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an
585 error if the target does not support them. */
586 if (TARGET_PCREL && !TARGET_68020 && flag_pic == 2)
587 error ("-mpcrel -fPIC is not currently supported on selected cpu");
589 /* ??? A historic way of turning on pic, or is this intended to
590 be an embedded thing that doesn't have the same name binding
591 significance that it does on hosted ELF systems? */
592 if (TARGET_PCREL && flag_pic == 0)
593 flag_pic = 1;
595 if (!flag_pic)
597 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_JSR;
599 m68k_symbolic_jump = "jra %a0";
601 else if (TARGET_ID_SHARED_LIBRARY)
602 /* All addresses must be loaded from the GOT. */
604 else if (TARGET_68020 || TARGET_ISAB || TARGET_ISAC)
606 if (TARGET_PCREL)
607 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_C;
608 else
609 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_P;
611 if (TARGET_ISAC)
612 /* No unconditional long branch */;
613 else if (TARGET_PCREL)
614 m68k_symbolic_jump = "bra%.l %c0";
615 else
616 m68k_symbolic_jump = "bra%.l %p0";
617 /* Turn off function cse if we are doing PIC. We always want
618 function call to be done as `bsr foo@PLTPC'. */
619 /* ??? It's traditional to do this for -mpcrel too, but it isn't
620 clear how intentional that is. */
621 flag_no_function_cse = 1;
624 switch (m68k_symbolic_call_var)
626 case M68K_SYMBOLIC_CALL_JSR:
627 m68k_symbolic_call = "jsr %a0";
628 break;
630 case M68K_SYMBOLIC_CALL_BSR_C:
631 m68k_symbolic_call = "bsr%.l %c0";
632 break;
634 case M68K_SYMBOLIC_CALL_BSR_P:
635 m68k_symbolic_call = "bsr%.l %p0";
636 break;
638 case M68K_SYMBOLIC_CALL_NONE:
639 gcc_assert (m68k_symbolic_call == NULL);
640 break;
642 default:
643 gcc_unreachable ();
646 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP
647 if (align_labels > 2)
649 warning (0, "-falign-labels=%d is not supported", align_labels);
650 align_labels = 0;
652 if (align_loops > 2)
654 warning (0, "-falign-loops=%d is not supported", align_loops);
655 align_loops = 0;
657 #endif
659 if ((opt_fstack_limit_symbol_arg != NULL || opt_fstack_limit_register_no >= 0)
660 && !TARGET_68020)
662 warning (0, "-fstack-limit- options are not supported on this cpu");
663 opt_fstack_limit_symbol_arg = NULL;
664 opt_fstack_limit_register_no = -1;
667 SUBTARGET_OVERRIDE_OPTIONS;
669 /* Setup scheduling options. */
670 if (TUNE_CFV1)
671 m68k_sched_cpu = CPU_CFV1;
672 else if (TUNE_CFV2)
673 m68k_sched_cpu = CPU_CFV2;
674 else if (TUNE_CFV3)
675 m68k_sched_cpu = CPU_CFV3;
676 else if (TUNE_CFV4)
677 m68k_sched_cpu = CPU_CFV4;
678 else
680 m68k_sched_cpu = CPU_UNKNOWN;
681 flag_schedule_insns = 0;
682 flag_schedule_insns_after_reload = 0;
683 flag_modulo_sched = 0;
684 flag_live_range_shrinkage = 0;
687 if (m68k_sched_cpu != CPU_UNKNOWN)
689 if ((m68k_cpu_flags & (FL_CF_EMAC | FL_CF_EMAC_B)) != 0)
690 m68k_sched_mac = MAC_CF_EMAC;
691 else if ((m68k_cpu_flags & FL_CF_MAC) != 0)
692 m68k_sched_mac = MAC_CF_MAC;
693 else
694 m68k_sched_mac = MAC_NO;
698 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */
700 static void
701 m68k_override_options_after_change (void)
703 if (m68k_sched_cpu == CPU_UNKNOWN)
705 flag_schedule_insns = 0;
706 flag_schedule_insns_after_reload = 0;
707 flag_modulo_sched = 0;
708 flag_live_range_shrinkage = 0;
712 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the
713 given argument and NAME is the argument passed to -mcpu. Return NULL
714 if -mcpu was not passed. */
716 const char *
717 m68k_cpp_cpu_ident (const char *prefix)
719 if (!m68k_cpu_entry)
720 return NULL;
721 return concat ("__m", prefix, "_cpu_", m68k_cpu_entry->name, NULL);
724 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the
725 given argument and NAME is the name of the representative device for
726 the -mcpu argument's family. Return NULL if -mcpu was not passed. */
728 const char *
729 m68k_cpp_cpu_family (const char *prefix)
731 if (!m68k_cpu_entry)
732 return NULL;
733 return concat ("__m", prefix, "_family_", m68k_cpu_entry->family, NULL);
736 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or
737 "interrupt_handler" attribute and interrupt_thread if FUNC has an
738 "interrupt_thread" attribute. Otherwise, return
739 m68k_fk_normal_function. */
741 enum m68k_function_kind
742 m68k_get_function_kind (tree func)
744 tree a;
746 gcc_assert (TREE_CODE (func) == FUNCTION_DECL);
748 a = lookup_attribute ("interrupt", DECL_ATTRIBUTES (func));
749 if (a != NULL_TREE)
750 return m68k_fk_interrupt_handler;
752 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func));
753 if (a != NULL_TREE)
754 return m68k_fk_interrupt_handler;
756 a = lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func));
757 if (a != NULL_TREE)
758 return m68k_fk_interrupt_thread;
760 return m68k_fk_normal_function;
763 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in
764 struct attribute_spec.handler. */
765 static tree
766 m68k_handle_fndecl_attribute (tree *node, tree name,
767 tree args ATTRIBUTE_UNUSED,
768 int flags ATTRIBUTE_UNUSED,
769 bool *no_add_attrs)
771 if (TREE_CODE (*node) != FUNCTION_DECL)
773 warning (OPT_Wattributes, "%qE attribute only applies to functions",
774 name);
775 *no_add_attrs = true;
778 if (m68k_get_function_kind (*node) != m68k_fk_normal_function)
780 error ("multiple interrupt attributes not allowed");
781 *no_add_attrs = true;
784 if (!TARGET_FIDOA
785 && !strcmp (IDENTIFIER_POINTER (name), "interrupt_thread"))
787 error ("interrupt_thread is available only on fido");
788 *no_add_attrs = true;
791 return NULL_TREE;
794 static void
795 m68k_compute_frame_layout (void)
797 int regno, saved;
798 unsigned int mask;
799 enum m68k_function_kind func_kind =
800 m68k_get_function_kind (current_function_decl);
801 bool interrupt_handler = func_kind == m68k_fk_interrupt_handler;
802 bool interrupt_thread = func_kind == m68k_fk_interrupt_thread;
804 /* Only compute the frame once per function.
805 Don't cache information until reload has been completed. */
806 if (current_frame.funcdef_no == current_function_funcdef_no
807 && reload_completed)
808 return;
810 current_frame.size = (get_frame_size () + 3) & -4;
812 mask = saved = 0;
814 /* Interrupt thread does not need to save any register. */
815 if (!interrupt_thread)
816 for (regno = 0; regno < 16; regno++)
817 if (m68k_save_reg (regno, interrupt_handler))
819 mask |= 1 << (regno - D0_REG);
820 saved++;
822 current_frame.offset = saved * 4;
823 current_frame.reg_no = saved;
824 current_frame.reg_mask = mask;
826 current_frame.foffset = 0;
827 mask = saved = 0;
828 if (TARGET_HARD_FLOAT)
830 /* Interrupt thread does not need to save any register. */
831 if (!interrupt_thread)
832 for (regno = 16; regno < 24; regno++)
833 if (m68k_save_reg (regno, interrupt_handler))
835 mask |= 1 << (regno - FP0_REG);
836 saved++;
838 current_frame.foffset = saved * TARGET_FP_REG_SIZE;
839 current_frame.offset += current_frame.foffset;
841 current_frame.fpu_no = saved;
842 current_frame.fpu_mask = mask;
844 /* Remember what function this frame refers to. */
845 current_frame.funcdef_no = current_function_funcdef_no;
848 /* Worker function for TARGET_CAN_ELIMINATE. */
850 bool
851 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to)
853 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true);
856 HOST_WIDE_INT
857 m68k_initial_elimination_offset (int from, int to)
859 int argptr_offset;
860 /* The arg pointer points 8 bytes before the start of the arguments,
861 as defined by FIRST_PARM_OFFSET. This makes it coincident with the
862 frame pointer in most frames. */
863 argptr_offset = frame_pointer_needed ? 0 : UNITS_PER_WORD;
864 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
865 return argptr_offset;
867 m68k_compute_frame_layout ();
869 gcc_assert (to == STACK_POINTER_REGNUM);
870 switch (from)
872 case ARG_POINTER_REGNUM:
873 return current_frame.offset + current_frame.size - argptr_offset;
874 case FRAME_POINTER_REGNUM:
875 return current_frame.offset + current_frame.size;
876 default:
877 gcc_unreachable ();
881 /* Refer to the array `regs_ever_live' to determine which registers
882 to save; `regs_ever_live[I]' is nonzero if register number I
883 is ever used in the function. This function is responsible for
884 knowing which registers should not be saved even if used.
885 Return true if we need to save REGNO. */
887 static bool
888 m68k_save_reg (unsigned int regno, bool interrupt_handler)
890 if (flag_pic && regno == PIC_REG)
892 if (crtl->saves_all_registers)
893 return true;
894 if (crtl->uses_pic_offset_table)
895 return true;
896 /* Reload may introduce constant pool references into a function
897 that thitherto didn't need a PIC register. Note that the test
898 above will not catch that case because we will only set
899 crtl->uses_pic_offset_table when emitting
900 the address reloads. */
901 if (crtl->uses_const_pool)
902 return true;
905 if (crtl->calls_eh_return)
907 unsigned int i;
908 for (i = 0; ; i++)
910 unsigned int test = EH_RETURN_DATA_REGNO (i);
911 if (test == INVALID_REGNUM)
912 break;
913 if (test == regno)
914 return true;
918 /* Fixed regs we never touch. */
919 if (fixed_regs[regno])
920 return false;
922 /* The frame pointer (if it is such) is handled specially. */
923 if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed)
924 return false;
926 /* Interrupt handlers must also save call_used_regs
927 if they are live or when calling nested functions. */
928 if (interrupt_handler)
930 if (df_regs_ever_live_p (regno))
931 return true;
933 if (!crtl->is_leaf && call_used_regs[regno])
934 return true;
937 /* Never need to save registers that aren't touched. */
938 if (!df_regs_ever_live_p (regno))
939 return false;
941 /* Otherwise save everything that isn't call-clobbered. */
942 return !call_used_regs[regno];
945 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents
946 the lowest memory address. COUNT is the number of registers to be
947 moved, with register REGNO + I being moved if bit I of MASK is set.
948 STORE_P specifies the direction of the move and ADJUST_STACK_P says
949 whether or not this is pre-decrement (if STORE_P) or post-increment
950 (if !STORE_P) operation. */
952 static rtx_insn *
953 m68k_emit_movem (rtx base, HOST_WIDE_INT offset,
954 unsigned int count, unsigned int regno,
955 unsigned int mask, bool store_p, bool adjust_stack_p)
957 int i;
958 rtx body, addr, src, operands[2];
959 machine_mode mode;
961 body = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (adjust_stack_p + count));
962 mode = reg_raw_mode[regno];
963 i = 0;
965 if (adjust_stack_p)
967 src = plus_constant (Pmode, base,
968 (count
969 * GET_MODE_SIZE (mode)
970 * (HOST_WIDE_INT) (store_p ? -1 : 1)));
971 XVECEXP (body, 0, i++) = gen_rtx_SET (base, src);
974 for (; mask != 0; mask >>= 1, regno++)
975 if (mask & 1)
977 addr = plus_constant (Pmode, base, offset);
978 operands[!store_p] = gen_frame_mem (mode, addr);
979 operands[store_p] = gen_rtx_REG (mode, regno);
980 XVECEXP (body, 0, i++)
981 = gen_rtx_SET (operands[0], operands[1]);
982 offset += GET_MODE_SIZE (mode);
984 gcc_assert (i == XVECLEN (body, 0));
986 return emit_insn (body);
989 /* Make INSN a frame-related instruction. */
991 static void
992 m68k_set_frame_related (rtx_insn *insn)
994 rtx body;
995 int i;
997 RTX_FRAME_RELATED_P (insn) = 1;
998 body = PATTERN (insn);
999 if (GET_CODE (body) == PARALLEL)
1000 for (i = 0; i < XVECLEN (body, 0); i++)
1001 RTX_FRAME_RELATED_P (XVECEXP (body, 0, i)) = 1;
1004 /* Emit RTL for the "prologue" define_expand. */
1006 void
1007 m68k_expand_prologue (void)
1009 HOST_WIDE_INT fsize_with_regs;
1010 rtx limit, src, dest;
1012 m68k_compute_frame_layout ();
1014 if (flag_stack_usage_info)
1015 current_function_static_stack_size
1016 = current_frame.size + current_frame.offset;
1018 /* If the stack limit is a symbol, we can check it here,
1019 before actually allocating the space. */
1020 if (crtl->limit_stack
1021 && GET_CODE (stack_limit_rtx) == SYMBOL_REF)
1023 limit = plus_constant (Pmode, stack_limit_rtx, current_frame.size + 4);
1024 if (!m68k_legitimate_constant_p (Pmode, limit))
1026 emit_move_insn (gen_rtx_REG (Pmode, D0_REG), limit);
1027 limit = gen_rtx_REG (Pmode, D0_REG);
1029 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode,
1030 stack_pointer_rtx, limit),
1031 stack_pointer_rtx, limit,
1032 const1_rtx));
1035 fsize_with_regs = current_frame.size;
1036 if (TARGET_COLDFIRE)
1038 /* ColdFire's move multiple instructions do not allow pre-decrement
1039 addressing. Add the size of movem saves to the initial stack
1040 allocation instead. */
1041 if (current_frame.reg_no >= MIN_MOVEM_REGS)
1042 fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode);
1043 if (current_frame.fpu_no >= MIN_FMOVEM_REGS)
1044 fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode);
1047 if (frame_pointer_needed)
1049 if (fsize_with_regs == 0 && TUNE_68040)
1051 /* On the 68040, two separate moves are faster than link.w 0. */
1052 dest = gen_frame_mem (Pmode,
1053 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
1054 m68k_set_frame_related (emit_move_insn (dest, frame_pointer_rtx));
1055 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx,
1056 stack_pointer_rtx));
1058 else if (fsize_with_regs < 0x8000 || TARGET_68020)
1059 m68k_set_frame_related
1060 (emit_insn (gen_link (frame_pointer_rtx,
1061 GEN_INT (-4 - fsize_with_regs))));
1062 else
1064 m68k_set_frame_related
1065 (emit_insn (gen_link (frame_pointer_rtx, GEN_INT (-4))));
1066 m68k_set_frame_related
1067 (emit_insn (gen_addsi3 (stack_pointer_rtx,
1068 stack_pointer_rtx,
1069 GEN_INT (-fsize_with_regs))));
1072 /* If the frame pointer is needed, emit a special barrier that
1073 will prevent the scheduler from moving stores to the frame
1074 before the stack adjustment. */
1075 emit_insn (gen_stack_tie (stack_pointer_rtx, frame_pointer_rtx));
1077 else if (fsize_with_regs != 0)
1078 m68k_set_frame_related
1079 (emit_insn (gen_addsi3 (stack_pointer_rtx,
1080 stack_pointer_rtx,
1081 GEN_INT (-fsize_with_regs))));
1083 if (current_frame.fpu_mask)
1085 gcc_assert (current_frame.fpu_no >= MIN_FMOVEM_REGS);
1086 if (TARGET_68881)
1087 m68k_set_frame_related
1088 (m68k_emit_movem (stack_pointer_rtx,
1089 current_frame.fpu_no * -GET_MODE_SIZE (XFmode),
1090 current_frame.fpu_no, FP0_REG,
1091 current_frame.fpu_mask, true, true));
1092 else
1094 int offset;
1096 /* If we're using moveml to save the integer registers,
1097 the stack pointer will point to the bottom of the moveml
1098 save area. Find the stack offset of the first FP register. */
1099 if (current_frame.reg_no < MIN_MOVEM_REGS)
1100 offset = 0;
1101 else
1102 offset = current_frame.reg_no * GET_MODE_SIZE (SImode);
1103 m68k_set_frame_related
1104 (m68k_emit_movem (stack_pointer_rtx, offset,
1105 current_frame.fpu_no, FP0_REG,
1106 current_frame.fpu_mask, true, false));
1110 /* If the stack limit is not a symbol, check it here.
1111 This has the disadvantage that it may be too late... */
1112 if (crtl->limit_stack)
1114 if (REG_P (stack_limit_rtx))
1115 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode, stack_pointer_rtx,
1116 stack_limit_rtx),
1117 stack_pointer_rtx, stack_limit_rtx,
1118 const1_rtx));
1120 else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF)
1121 warning (0, "stack limit expression is not supported");
1124 if (current_frame.reg_no < MIN_MOVEM_REGS)
1126 /* Store each register separately in the same order moveml does. */
1127 int i;
1129 for (i = 16; i-- > 0; )
1130 if (current_frame.reg_mask & (1 << i))
1132 src = gen_rtx_REG (SImode, D0_REG + i);
1133 dest = gen_frame_mem (SImode,
1134 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
1135 m68k_set_frame_related (emit_insn (gen_movsi (dest, src)));
1138 else
1140 if (TARGET_COLDFIRE)
1141 /* The required register save space has already been allocated.
1142 The first register should be stored at (%sp). */
1143 m68k_set_frame_related
1144 (m68k_emit_movem (stack_pointer_rtx, 0,
1145 current_frame.reg_no, D0_REG,
1146 current_frame.reg_mask, true, false));
1147 else
1148 m68k_set_frame_related
1149 (m68k_emit_movem (stack_pointer_rtx,
1150 current_frame.reg_no * -GET_MODE_SIZE (SImode),
1151 current_frame.reg_no, D0_REG,
1152 current_frame.reg_mask, true, true));
1155 if (!TARGET_SEP_DATA
1156 && crtl->uses_pic_offset_table)
1157 emit_insn (gen_load_got (pic_offset_table_rtx));
1160 /* Return true if a simple (return) instruction is sufficient for this
1161 instruction (i.e. if no epilogue is needed). */
1163 bool
1164 m68k_use_return_insn (void)
1166 if (!reload_completed || frame_pointer_needed || get_frame_size () != 0)
1167 return false;
1169 m68k_compute_frame_layout ();
1170 return current_frame.offset == 0;
1173 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand;
1174 SIBCALL_P says which.
1176 The function epilogue should not depend on the current stack pointer!
1177 It should use the frame pointer only, if there is a frame pointer.
1178 This is mandatory because of alloca; we also take advantage of it to
1179 omit stack adjustments before returning. */
1181 void
1182 m68k_expand_epilogue (bool sibcall_p)
1184 HOST_WIDE_INT fsize, fsize_with_regs;
1185 bool big, restore_from_sp;
1187 m68k_compute_frame_layout ();
1189 fsize = current_frame.size;
1190 big = false;
1191 restore_from_sp = false;
1193 /* FIXME : crtl->is_leaf below is too strong.
1194 What we really need to know there is if there could be pending
1195 stack adjustment needed at that point. */
1196 restore_from_sp = (!frame_pointer_needed
1197 || (!cfun->calls_alloca && crtl->is_leaf));
1199 /* fsize_with_regs is the size we need to adjust the sp when
1200 popping the frame. */
1201 fsize_with_regs = fsize;
1202 if (TARGET_COLDFIRE && restore_from_sp)
1204 /* ColdFire's move multiple instructions do not allow post-increment
1205 addressing. Add the size of movem loads to the final deallocation
1206 instead. */
1207 if (current_frame.reg_no >= MIN_MOVEM_REGS)
1208 fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode);
1209 if (current_frame.fpu_no >= MIN_FMOVEM_REGS)
1210 fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode);
1213 if (current_frame.offset + fsize >= 0x8000
1214 && !restore_from_sp
1215 && (current_frame.reg_mask || current_frame.fpu_mask))
1217 if (TARGET_COLDFIRE
1218 && (current_frame.reg_no >= MIN_MOVEM_REGS
1219 || current_frame.fpu_no >= MIN_FMOVEM_REGS))
1221 /* ColdFire's move multiple instructions do not support the
1222 (d8,Ax,Xi) addressing mode, so we're as well using a normal
1223 stack-based restore. */
1224 emit_move_insn (gen_rtx_REG (Pmode, A1_REG),
1225 GEN_INT (-(current_frame.offset + fsize)));
1226 emit_insn (gen_blockage ());
1227 emit_insn (gen_addsi3 (stack_pointer_rtx,
1228 gen_rtx_REG (Pmode, A1_REG),
1229 frame_pointer_rtx));
1230 restore_from_sp = true;
1232 else
1234 emit_move_insn (gen_rtx_REG (Pmode, A1_REG), GEN_INT (-fsize));
1235 fsize = 0;
1236 big = true;
1240 if (current_frame.reg_no < MIN_MOVEM_REGS)
1242 /* Restore each register separately in the same order moveml does. */
1243 int i;
1244 HOST_WIDE_INT offset;
1246 offset = current_frame.offset + fsize;
1247 for (i = 0; i < 16; i++)
1248 if (current_frame.reg_mask & (1 << i))
1250 rtx addr;
1252 if (big)
1254 /* Generate the address -OFFSET(%fp,%a1.l). */
1255 addr = gen_rtx_REG (Pmode, A1_REG);
1256 addr = gen_rtx_PLUS (Pmode, addr, frame_pointer_rtx);
1257 addr = plus_constant (Pmode, addr, -offset);
1259 else if (restore_from_sp)
1260 addr = gen_rtx_POST_INC (Pmode, stack_pointer_rtx);
1261 else
1262 addr = plus_constant (Pmode, frame_pointer_rtx, -offset);
1263 emit_move_insn (gen_rtx_REG (SImode, D0_REG + i),
1264 gen_frame_mem (SImode, addr));
1265 offset -= GET_MODE_SIZE (SImode);
1268 else if (current_frame.reg_mask)
1270 if (big)
1271 m68k_emit_movem (gen_rtx_PLUS (Pmode,
1272 gen_rtx_REG (Pmode, A1_REG),
1273 frame_pointer_rtx),
1274 -(current_frame.offset + fsize),
1275 current_frame.reg_no, D0_REG,
1276 current_frame.reg_mask, false, false);
1277 else if (restore_from_sp)
1278 m68k_emit_movem (stack_pointer_rtx, 0,
1279 current_frame.reg_no, D0_REG,
1280 current_frame.reg_mask, false,
1281 !TARGET_COLDFIRE);
1282 else
1283 m68k_emit_movem (frame_pointer_rtx,
1284 -(current_frame.offset + fsize),
1285 current_frame.reg_no, D0_REG,
1286 current_frame.reg_mask, false, false);
1289 if (current_frame.fpu_no > 0)
1291 if (big)
1292 m68k_emit_movem (gen_rtx_PLUS (Pmode,
1293 gen_rtx_REG (Pmode, A1_REG),
1294 frame_pointer_rtx),
1295 -(current_frame.foffset + fsize),
1296 current_frame.fpu_no, FP0_REG,
1297 current_frame.fpu_mask, false, false);
1298 else if (restore_from_sp)
1300 if (TARGET_COLDFIRE)
1302 int offset;
1304 /* If we used moveml to restore the integer registers, the
1305 stack pointer will still point to the bottom of the moveml
1306 save area. Find the stack offset of the first FP
1307 register. */
1308 if (current_frame.reg_no < MIN_MOVEM_REGS)
1309 offset = 0;
1310 else
1311 offset = current_frame.reg_no * GET_MODE_SIZE (SImode);
1312 m68k_emit_movem (stack_pointer_rtx, offset,
1313 current_frame.fpu_no, FP0_REG,
1314 current_frame.fpu_mask, false, false);
1316 else
1317 m68k_emit_movem (stack_pointer_rtx, 0,
1318 current_frame.fpu_no, FP0_REG,
1319 current_frame.fpu_mask, false, true);
1321 else
1322 m68k_emit_movem (frame_pointer_rtx,
1323 -(current_frame.foffset + fsize),
1324 current_frame.fpu_no, FP0_REG,
1325 current_frame.fpu_mask, false, false);
1328 emit_insn (gen_blockage ());
1329 if (frame_pointer_needed)
1330 emit_insn (gen_unlink (frame_pointer_rtx));
1331 else if (fsize_with_regs)
1332 emit_insn (gen_addsi3 (stack_pointer_rtx,
1333 stack_pointer_rtx,
1334 GEN_INT (fsize_with_regs)));
1336 if (crtl->calls_eh_return)
1337 emit_insn (gen_addsi3 (stack_pointer_rtx,
1338 stack_pointer_rtx,
1339 EH_RETURN_STACKADJ_RTX));
1341 if (!sibcall_p)
1342 emit_jump_insn (ret_rtx);
1345 /* Return true if X is a valid comparison operator for the dbcc
1346 instruction.
1348 Note it rejects floating point comparison operators.
1349 (In the future we could use Fdbcc).
1351 It also rejects some comparisons when CC_NO_OVERFLOW is set. */
1354 valid_dbcc_comparison_p_2 (rtx x, machine_mode mode ATTRIBUTE_UNUSED)
1356 switch (GET_CODE (x))
1358 case EQ: case NE: case GTU: case LTU:
1359 case GEU: case LEU:
1360 return 1;
1362 /* Reject some when CC_NO_OVERFLOW is set. This may be over
1363 conservative */
1364 case GT: case LT: case GE: case LE:
1365 return ! (cc_prev_status.flags & CC_NO_OVERFLOW);
1366 default:
1367 return 0;
1371 /* Return nonzero if flags are currently in the 68881 flag register. */
1373 flags_in_68881 (void)
1375 /* We could add support for these in the future */
1376 return cc_status.flags & CC_IN_68881;
1379 /* Return true if PARALLEL contains register REGNO. */
1380 static bool
1381 m68k_reg_present_p (const_rtx parallel, unsigned int regno)
1383 int i;
1385 if (REG_P (parallel) && REGNO (parallel) == regno)
1386 return true;
1388 if (GET_CODE (parallel) != PARALLEL)
1389 return false;
1391 for (i = 0; i < XVECLEN (parallel, 0); ++i)
1393 const_rtx x;
1395 x = XEXP (XVECEXP (parallel, 0, i), 0);
1396 if (REG_P (x) && REGNO (x) == regno)
1397 return true;
1400 return false;
1403 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */
1405 static bool
1406 m68k_ok_for_sibcall_p (tree decl, tree exp)
1408 enum m68k_function_kind kind;
1410 /* We cannot use sibcalls for nested functions because we use the
1411 static chain register for indirect calls. */
1412 if (CALL_EXPR_STATIC_CHAIN (exp))
1413 return false;
1415 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl))))
1417 /* Check that the return value locations are the same. For
1418 example that we aren't returning a value from the sibling in
1419 a D0 register but then need to transfer it to a A0 register. */
1420 rtx cfun_value;
1421 rtx call_value;
1423 cfun_value = FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun->decl)),
1424 cfun->decl);
1425 call_value = FUNCTION_VALUE (TREE_TYPE (exp), decl);
1427 /* Check that the values are equal or that the result the callee
1428 function returns is superset of what the current function returns. */
1429 if (!(rtx_equal_p (cfun_value, call_value)
1430 || (REG_P (cfun_value)
1431 && m68k_reg_present_p (call_value, REGNO (cfun_value)))))
1432 return false;
1435 kind = m68k_get_function_kind (current_function_decl);
1436 if (kind == m68k_fk_normal_function)
1437 /* We can always sibcall from a normal function, because it's
1438 undefined if it is calling an interrupt function. */
1439 return true;
1441 /* Otherwise we can only sibcall if the function kind is known to be
1442 the same. */
1443 if (decl && m68k_get_function_kind (decl) == kind)
1444 return true;
1446 return false;
1449 /* On the m68k all args are always pushed. */
1451 static rtx
1452 m68k_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED,
1453 machine_mode mode ATTRIBUTE_UNUSED,
1454 const_tree type ATTRIBUTE_UNUSED,
1455 bool named ATTRIBUTE_UNUSED)
1457 return NULL_RTX;
1460 static void
1461 m68k_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
1462 const_tree type, bool named ATTRIBUTE_UNUSED)
1464 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
1466 *cum += (mode != BLKmode
1467 ? (GET_MODE_SIZE (mode) + 3) & ~3
1468 : (int_size_in_bytes (type) + 3) & ~3);
1471 /* Convert X to a legitimate function call memory reference and return the
1472 result. */
1475 m68k_legitimize_call_address (rtx x)
1477 gcc_assert (MEM_P (x));
1478 if (call_operand (XEXP (x, 0), VOIDmode))
1479 return x;
1480 return replace_equiv_address (x, force_reg (Pmode, XEXP (x, 0)));
1483 /* Likewise for sibling calls. */
1486 m68k_legitimize_sibcall_address (rtx x)
1488 gcc_assert (MEM_P (x));
1489 if (sibcall_operand (XEXP (x, 0), VOIDmode))
1490 return x;
1492 emit_move_insn (gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM), XEXP (x, 0));
1493 return replace_equiv_address (x, gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM));
1496 /* Convert X to a legitimate address and return it if successful. Otherwise
1497 return X.
1499 For the 68000, we handle X+REG by loading X into a register R and
1500 using R+REG. R will go in an address reg and indexing will be used.
1501 However, if REG is a broken-out memory address or multiplication,
1502 nothing needs to be done because REG can certainly go in an address reg. */
1504 static rtx
1505 m68k_legitimize_address (rtx x, rtx oldx, machine_mode mode)
1507 if (m68k_tls_symbol_p (x))
1508 return m68k_legitimize_tls_address (x);
1510 if (GET_CODE (x) == PLUS)
1512 int ch = (x) != (oldx);
1513 int copied = 0;
1515 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1517 if (GET_CODE (XEXP (x, 0)) == MULT)
1519 COPY_ONCE (x);
1520 XEXP (x, 0) = force_operand (XEXP (x, 0), 0);
1522 if (GET_CODE (XEXP (x, 1)) == MULT)
1524 COPY_ONCE (x);
1525 XEXP (x, 1) = force_operand (XEXP (x, 1), 0);
1527 if (ch)
1529 if (GET_CODE (XEXP (x, 1)) == REG
1530 && GET_CODE (XEXP (x, 0)) == REG)
1532 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT)
1534 COPY_ONCE (x);
1535 x = force_operand (x, 0);
1537 return x;
1539 if (memory_address_p (mode, x))
1540 return x;
1542 if (GET_CODE (XEXP (x, 0)) == REG
1543 || (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
1544 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
1545 && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode))
1547 rtx temp = gen_reg_rtx (Pmode);
1548 rtx val = force_operand (XEXP (x, 1), 0);
1549 emit_move_insn (temp, val);
1550 COPY_ONCE (x);
1551 XEXP (x, 1) = temp;
1552 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT
1553 && GET_CODE (XEXP (x, 0)) == REG)
1554 x = force_operand (x, 0);
1556 else if (GET_CODE (XEXP (x, 1)) == REG
1557 || (GET_CODE (XEXP (x, 1)) == SIGN_EXTEND
1558 && GET_CODE (XEXP (XEXP (x, 1), 0)) == REG
1559 && GET_MODE (XEXP (XEXP (x, 1), 0)) == HImode))
1561 rtx temp = gen_reg_rtx (Pmode);
1562 rtx val = force_operand (XEXP (x, 0), 0);
1563 emit_move_insn (temp, val);
1564 COPY_ONCE (x);
1565 XEXP (x, 0) = temp;
1566 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT
1567 && GET_CODE (XEXP (x, 1)) == REG)
1568 x = force_operand (x, 0);
1572 return x;
1576 /* Output a dbCC; jCC sequence. Note we do not handle the
1577 floating point version of this sequence (Fdbcc). We also
1578 do not handle alternative conditions when CC_NO_OVERFLOW is
1579 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will
1580 kick those out before we get here. */
1582 void
1583 output_dbcc_and_branch (rtx *operands)
1585 switch (GET_CODE (operands[3]))
1587 case EQ:
1588 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands);
1589 break;
1591 case NE:
1592 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands);
1593 break;
1595 case GT:
1596 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands);
1597 break;
1599 case GTU:
1600 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands);
1601 break;
1603 case LT:
1604 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands);
1605 break;
1607 case LTU:
1608 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands);
1609 break;
1611 case GE:
1612 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands);
1613 break;
1615 case GEU:
1616 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands);
1617 break;
1619 case LE:
1620 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands);
1621 break;
1623 case LEU:
1624 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands);
1625 break;
1627 default:
1628 gcc_unreachable ();
1631 /* If the decrement is to be done in SImode, then we have
1632 to compensate for the fact that dbcc decrements in HImode. */
1633 switch (GET_MODE (operands[0]))
1635 case E_SImode:
1636 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands);
1637 break;
1639 case E_HImode:
1640 break;
1642 default:
1643 gcc_unreachable ();
1647 const char *
1648 output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest)
1650 rtx loperands[7];
1651 enum rtx_code op_code = GET_CODE (op);
1653 /* This does not produce a useful cc. */
1654 CC_STATUS_INIT;
1656 /* The m68k cmp.l instruction requires operand1 to be a reg as used
1657 below. Swap the operands and change the op if these requirements
1658 are not fulfilled. */
1659 if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG)
1661 rtx tmp = operand1;
1663 operand1 = operand2;
1664 operand2 = tmp;
1665 op_code = swap_condition (op_code);
1667 loperands[0] = operand1;
1668 if (GET_CODE (operand1) == REG)
1669 loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1);
1670 else
1671 loperands[1] = adjust_address (operand1, SImode, 4);
1672 if (operand2 != const0_rtx)
1674 loperands[2] = operand2;
1675 if (GET_CODE (operand2) == REG)
1676 loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1);
1677 else
1678 loperands[3] = adjust_address (operand2, SImode, 4);
1680 loperands[4] = gen_label_rtx ();
1681 if (operand2 != const0_rtx)
1682 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands);
1683 else
1685 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0]))
1686 output_asm_insn ("tst%.l %0", loperands);
1687 else
1688 output_asm_insn ("cmp%.w #0,%0", loperands);
1690 output_asm_insn ("jne %l4", loperands);
1692 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1]))
1693 output_asm_insn ("tst%.l %1", loperands);
1694 else
1695 output_asm_insn ("cmp%.w #0,%1", loperands);
1698 loperands[5] = dest;
1700 switch (op_code)
1702 case EQ:
1703 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1704 CODE_LABEL_NUMBER (loperands[4]));
1705 output_asm_insn ("seq %5", loperands);
1706 break;
1708 case NE:
1709 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1710 CODE_LABEL_NUMBER (loperands[4]));
1711 output_asm_insn ("sne %5", loperands);
1712 break;
1714 case GT:
1715 loperands[6] = gen_label_rtx ();
1716 output_asm_insn ("shi %5\n\tjra %l6", loperands);
1717 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1718 CODE_LABEL_NUMBER (loperands[4]));
1719 output_asm_insn ("sgt %5", loperands);
1720 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1721 CODE_LABEL_NUMBER (loperands[6]));
1722 break;
1724 case GTU:
1725 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1726 CODE_LABEL_NUMBER (loperands[4]));
1727 output_asm_insn ("shi %5", loperands);
1728 break;
1730 case LT:
1731 loperands[6] = gen_label_rtx ();
1732 output_asm_insn ("scs %5\n\tjra %l6", loperands);
1733 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1734 CODE_LABEL_NUMBER (loperands[4]));
1735 output_asm_insn ("slt %5", loperands);
1736 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1737 CODE_LABEL_NUMBER (loperands[6]));
1738 break;
1740 case LTU:
1741 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1742 CODE_LABEL_NUMBER (loperands[4]));
1743 output_asm_insn ("scs %5", loperands);
1744 break;
1746 case GE:
1747 loperands[6] = gen_label_rtx ();
1748 output_asm_insn ("scc %5\n\tjra %l6", loperands);
1749 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1750 CODE_LABEL_NUMBER (loperands[4]));
1751 output_asm_insn ("sge %5", loperands);
1752 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1753 CODE_LABEL_NUMBER (loperands[6]));
1754 break;
1756 case GEU:
1757 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1758 CODE_LABEL_NUMBER (loperands[4]));
1759 output_asm_insn ("scc %5", loperands);
1760 break;
1762 case LE:
1763 loperands[6] = gen_label_rtx ();
1764 output_asm_insn ("sls %5\n\tjra %l6", loperands);
1765 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1766 CODE_LABEL_NUMBER (loperands[4]));
1767 output_asm_insn ("sle %5", loperands);
1768 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1769 CODE_LABEL_NUMBER (loperands[6]));
1770 break;
1772 case LEU:
1773 (*targetm.asm_out.internal_label) (asm_out_file, "L",
1774 CODE_LABEL_NUMBER (loperands[4]));
1775 output_asm_insn ("sls %5", loperands);
1776 break;
1778 default:
1779 gcc_unreachable ();
1781 return "";
1784 const char *
1785 output_btst (rtx *operands, rtx countop, rtx dataop, rtx_insn *insn, int signpos)
1787 operands[0] = countop;
1788 operands[1] = dataop;
1790 if (GET_CODE (countop) == CONST_INT)
1792 register int count = INTVAL (countop);
1793 /* If COUNT is bigger than size of storage unit in use,
1794 advance to the containing unit of same size. */
1795 if (count > signpos)
1797 int offset = (count & ~signpos) / 8;
1798 count = count & signpos;
1799 operands[1] = dataop = adjust_address (dataop, QImode, offset);
1801 if (count == signpos)
1802 cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
1803 else
1804 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
1806 /* These three statements used to use next_insns_test_no...
1807 but it appears that this should do the same job. */
1808 if (count == 31
1809 && next_insn_tests_no_inequality (insn))
1810 return "tst%.l %1";
1811 if (count == 15
1812 && next_insn_tests_no_inequality (insn))
1813 return "tst%.w %1";
1814 if (count == 7
1815 && next_insn_tests_no_inequality (insn))
1816 return "tst%.b %1";
1817 /* Try to use `movew to ccr' followed by the appropriate branch insn.
1818 On some m68k variants unfortunately that's slower than btst.
1819 On 68000 and higher, that should also work for all HImode operands. */
1820 if (TUNE_CPU32 || TARGET_COLDFIRE || optimize_size)
1822 if (count == 3 && DATA_REG_P (operands[1])
1823 && next_insn_tests_no_inequality (insn))
1825 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N | CC_NO_OVERFLOW;
1826 return "move%.w %1,%%ccr";
1828 if (count == 2 && DATA_REG_P (operands[1])
1829 && next_insn_tests_no_inequality (insn))
1831 cc_status.flags = CC_NOT_NEGATIVE | CC_INVERTED | CC_NO_OVERFLOW;
1832 return "move%.w %1,%%ccr";
1834 /* count == 1 followed by bvc/bvs and
1835 count == 0 followed by bcc/bcs are also possible, but need
1836 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */
1839 cc_status.flags = CC_NOT_NEGATIVE;
1841 return "btst %0,%1";
1844 /* Return true if X is a legitimate base register. STRICT_P says
1845 whether we need strict checking. */
1847 bool
1848 m68k_legitimate_base_reg_p (rtx x, bool strict_p)
1850 /* Allow SUBREG everywhere we allow REG. This results in better code. */
1851 if (!strict_p && GET_CODE (x) == SUBREG)
1852 x = SUBREG_REG (x);
1854 return (REG_P (x)
1855 && (strict_p
1856 ? REGNO_OK_FOR_BASE_P (REGNO (x))
1857 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x))));
1860 /* Return true if X is a legitimate index register. STRICT_P says
1861 whether we need strict checking. */
1863 bool
1864 m68k_legitimate_index_reg_p (rtx x, bool strict_p)
1866 if (!strict_p && GET_CODE (x) == SUBREG)
1867 x = SUBREG_REG (x);
1869 return (REG_P (x)
1870 && (strict_p
1871 ? REGNO_OK_FOR_INDEX_P (REGNO (x))
1872 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x))));
1875 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or
1876 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of
1877 ADDRESS if so. STRICT_P says whether we need strict checking. */
1879 static bool
1880 m68k_decompose_index (rtx x, bool strict_p, struct m68k_address *address)
1882 int scale;
1884 /* Check for a scale factor. */
1885 scale = 1;
1886 if ((TARGET_68020 || TARGET_COLDFIRE)
1887 && GET_CODE (x) == MULT
1888 && GET_CODE (XEXP (x, 1)) == CONST_INT
1889 && (INTVAL (XEXP (x, 1)) == 2
1890 || INTVAL (XEXP (x, 1)) == 4
1891 || (INTVAL (XEXP (x, 1)) == 8
1892 && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE))))
1894 scale = INTVAL (XEXP (x, 1));
1895 x = XEXP (x, 0);
1898 /* Check for a word extension. */
1899 if (!TARGET_COLDFIRE
1900 && GET_CODE (x) == SIGN_EXTEND
1901 && GET_MODE (XEXP (x, 0)) == HImode)
1902 x = XEXP (x, 0);
1904 if (m68k_legitimate_index_reg_p (x, strict_p))
1906 address->scale = scale;
1907 address->index = x;
1908 return true;
1911 return false;
1914 /* Return true if X is an illegitimate symbolic constant. */
1916 bool
1917 m68k_illegitimate_symbolic_constant_p (rtx x)
1919 rtx base, offset;
1921 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
1923 split_const (x, &base, &offset);
1924 if (GET_CODE (base) == SYMBOL_REF
1925 && !offset_within_block_p (base, INTVAL (offset)))
1926 return true;
1928 return m68k_tls_reference_p (x, false);
1931 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1933 static bool
1934 m68k_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1936 return m68k_illegitimate_symbolic_constant_p (x);
1939 /* Return true if X is a legitimate constant address that can reach
1940 bytes in the range [X, X + REACH). STRICT_P says whether we need
1941 strict checking. */
1943 static bool
1944 m68k_legitimate_constant_address_p (rtx x, unsigned int reach, bool strict_p)
1946 rtx base, offset;
1948 if (!CONSTANT_ADDRESS_P (x))
1949 return false;
1951 if (flag_pic
1952 && !(strict_p && TARGET_PCREL)
1953 && symbolic_operand (x, VOIDmode))
1954 return false;
1956 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P && reach > 1)
1958 split_const (x, &base, &offset);
1959 if (GET_CODE (base) == SYMBOL_REF
1960 && !offset_within_block_p (base, INTVAL (offset) + reach - 1))
1961 return false;
1964 return !m68k_tls_reference_p (x, false);
1967 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced
1968 labels will become jump tables. */
1970 static bool
1971 m68k_jump_table_ref_p (rtx x)
1973 if (GET_CODE (x) != LABEL_REF)
1974 return false;
1976 rtx_insn *insn = as_a <rtx_insn *> (XEXP (x, 0));
1977 if (!NEXT_INSN (insn) && !PREV_INSN (insn))
1978 return true;
1980 insn = next_nonnote_insn (insn);
1981 return insn && JUMP_TABLE_DATA_P (insn);
1984 /* Return true if X is a legitimate address for values of mode MODE.
1985 STRICT_P says whether strict checking is needed. If the address
1986 is valid, describe its components in *ADDRESS. */
1988 static bool
1989 m68k_decompose_address (machine_mode mode, rtx x,
1990 bool strict_p, struct m68k_address *address)
1992 unsigned int reach;
1994 memset (address, 0, sizeof (*address));
1996 if (mode == BLKmode)
1997 reach = 1;
1998 else
1999 reach = GET_MODE_SIZE (mode);
2001 /* Check for (An) (mode 2). */
2002 if (m68k_legitimate_base_reg_p (x, strict_p))
2004 address->base = x;
2005 return true;
2008 /* Check for -(An) and (An)+ (modes 3 and 4). */
2009 if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC)
2010 && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p))
2012 address->code = GET_CODE (x);
2013 address->base = XEXP (x, 0);
2014 return true;
2017 /* Check for (d16,An) (mode 5). */
2018 if (GET_CODE (x) == PLUS
2019 && GET_CODE (XEXP (x, 1)) == CONST_INT
2020 && IN_RANGE (INTVAL (XEXP (x, 1)), -0x8000, 0x8000 - reach)
2021 && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p))
2023 address->base = XEXP (x, 0);
2024 address->offset = XEXP (x, 1);
2025 return true;
2028 /* Check for GOT loads. These are (bd,An,Xn) addresses if
2029 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An)
2030 addresses. */
2031 if (GET_CODE (x) == PLUS
2032 && XEXP (x, 0) == pic_offset_table_rtx)
2034 /* As we are processing a PLUS, do not unwrap RELOC32 symbols --
2035 they are invalid in this context. */
2036 if (m68k_unwrap_symbol (XEXP (x, 1), false) != XEXP (x, 1))
2038 address->base = XEXP (x, 0);
2039 address->offset = XEXP (x, 1);
2040 return true;
2044 /* The ColdFire FPU only accepts addressing modes 2-5. */
2045 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT)
2046 return false;
2048 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case,
2049 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register.
2050 All these modes are variations of mode 7. */
2051 if (m68k_legitimate_constant_address_p (x, reach, strict_p))
2053 address->offset = x;
2054 return true;
2057 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for
2058 tablejumps.
2060 ??? do_tablejump creates these addresses before placing the target
2061 label, so we have to assume that unplaced labels are jump table
2062 references. It seems unlikely that we would ever generate indexed
2063 accesses to unplaced labels in other cases. */
2064 if (GET_CODE (x) == PLUS
2065 && m68k_jump_table_ref_p (XEXP (x, 1))
2066 && m68k_decompose_index (XEXP (x, 0), strict_p, address))
2068 address->offset = XEXP (x, 1);
2069 return true;
2072 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or
2073 (bd,An,Xn.SIZE*SCALE) addresses. */
2075 if (TARGET_68020)
2077 /* Check for a nonzero base displacement. */
2078 if (GET_CODE (x) == PLUS
2079 && m68k_legitimate_constant_address_p (XEXP (x, 1), reach, strict_p))
2081 address->offset = XEXP (x, 1);
2082 x = XEXP (x, 0);
2085 /* Check for a suppressed index register. */
2086 if (m68k_legitimate_base_reg_p (x, strict_p))
2088 address->base = x;
2089 return true;
2092 /* Check for a suppressed base register. Do not allow this case
2093 for non-symbolic offsets as it effectively gives gcc freedom
2094 to treat data registers as base registers, which can generate
2095 worse code. */
2096 if (address->offset
2097 && symbolic_operand (address->offset, VOIDmode)
2098 && m68k_decompose_index (x, strict_p, address))
2099 return true;
2101 else
2103 /* Check for a nonzero base displacement. */
2104 if (GET_CODE (x) == PLUS
2105 && GET_CODE (XEXP (x, 1)) == CONST_INT
2106 && IN_RANGE (INTVAL (XEXP (x, 1)), -0x80, 0x80 - reach))
2108 address->offset = XEXP (x, 1);
2109 x = XEXP (x, 0);
2113 /* We now expect the sum of a base and an index. */
2114 if (GET_CODE (x) == PLUS)
2116 if (m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)
2117 && m68k_decompose_index (XEXP (x, 1), strict_p, address))
2119 address->base = XEXP (x, 0);
2120 return true;
2123 if (m68k_legitimate_base_reg_p (XEXP (x, 1), strict_p)
2124 && m68k_decompose_index (XEXP (x, 0), strict_p, address))
2126 address->base = XEXP (x, 1);
2127 return true;
2130 return false;
2133 /* Return true if X is a legitimate address for values of mode MODE.
2134 STRICT_P says whether strict checking is needed. */
2136 bool
2137 m68k_legitimate_address_p (machine_mode mode, rtx x, bool strict_p)
2139 struct m68k_address address;
2141 return m68k_decompose_address (mode, x, strict_p, &address);
2144 /* Return true if X is a memory, describing its address in ADDRESS if so.
2145 Apply strict checking if called during or after reload. */
2147 static bool
2148 m68k_legitimate_mem_p (rtx x, struct m68k_address *address)
2150 return (MEM_P (x)
2151 && m68k_decompose_address (GET_MODE (x), XEXP (x, 0),
2152 reload_in_progress || reload_completed,
2153 address));
2156 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
2158 bool
2159 m68k_legitimate_constant_p (machine_mode mode, rtx x)
2161 return mode != XFmode && !m68k_illegitimate_symbolic_constant_p (x);
2164 /* Return true if X matches the 'Q' constraint. It must be a memory
2165 with a base address and no constant offset or index. */
2167 bool
2168 m68k_matches_q_p (rtx x)
2170 struct m68k_address address;
2172 return (m68k_legitimate_mem_p (x, &address)
2173 && address.code == UNKNOWN
2174 && address.base
2175 && !address.offset
2176 && !address.index);
2179 /* Return true if X matches the 'U' constraint. It must be a base address
2180 with a constant offset and no index. */
2182 bool
2183 m68k_matches_u_p (rtx x)
2185 struct m68k_address address;
2187 return (m68k_legitimate_mem_p (x, &address)
2188 && address.code == UNKNOWN
2189 && address.base
2190 && address.offset
2191 && !address.index);
2194 /* Return GOT pointer. */
2196 static rtx
2197 m68k_get_gp (void)
2199 if (pic_offset_table_rtx == NULL_RTX)
2200 pic_offset_table_rtx = gen_rtx_REG (Pmode, PIC_REG);
2202 crtl->uses_pic_offset_table = 1;
2204 return pic_offset_table_rtx;
2207 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC
2208 wrappers. */
2209 enum m68k_reloc { RELOC_GOT, RELOC_TLSGD, RELOC_TLSLDM, RELOC_TLSLDO,
2210 RELOC_TLSIE, RELOC_TLSLE };
2212 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT)
2214 /* Wrap symbol X into unspec representing relocation RELOC.
2215 BASE_REG - register that should be added to the result.
2216 TEMP_REG - if non-null, temporary register. */
2218 static rtx
2219 m68k_wrap_symbol (rtx x, enum m68k_reloc reloc, rtx base_reg, rtx temp_reg)
2221 bool use_x_p;
2223 use_x_p = (base_reg == pic_offset_table_rtx) ? TARGET_XGOT : TARGET_XTLS;
2225 if (TARGET_COLDFIRE && use_x_p)
2226 /* When compiling with -mx{got, tls} switch the code will look like this:
2228 move.l <X>@<RELOC>,<TEMP_REG>
2229 add.l <BASE_REG>,<TEMP_REG> */
2231 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra
2232 to put @RELOC after reference. */
2233 x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (reloc)),
2234 UNSPEC_RELOC32);
2235 x = gen_rtx_CONST (Pmode, x);
2237 if (temp_reg == NULL)
2239 gcc_assert (can_create_pseudo_p ());
2240 temp_reg = gen_reg_rtx (Pmode);
2243 emit_move_insn (temp_reg, x);
2244 emit_insn (gen_addsi3 (temp_reg, temp_reg, base_reg));
2245 x = temp_reg;
2247 else
2249 x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (reloc)),
2250 UNSPEC_RELOC16);
2251 x = gen_rtx_CONST (Pmode, x);
2253 x = gen_rtx_PLUS (Pmode, base_reg, x);
2256 return x;
2259 /* Helper for m68k_unwrap_symbol.
2260 Also, if unwrapping was successful (that is if (ORIG != <return value>)),
2261 sets *RELOC_PTR to relocation type for the symbol. */
2263 static rtx
2264 m68k_unwrap_symbol_1 (rtx orig, bool unwrap_reloc32_p,
2265 enum m68k_reloc *reloc_ptr)
2267 if (GET_CODE (orig) == CONST)
2269 rtx x;
2270 enum m68k_reloc dummy;
2272 x = XEXP (orig, 0);
2274 if (reloc_ptr == NULL)
2275 reloc_ptr = &dummy;
2277 /* Handle an addend. */
2278 if ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS)
2279 && CONST_INT_P (XEXP (x, 1)))
2280 x = XEXP (x, 0);
2282 if (GET_CODE (x) == UNSPEC)
2284 switch (XINT (x, 1))
2286 case UNSPEC_RELOC16:
2287 orig = XVECEXP (x, 0, 0);
2288 *reloc_ptr = (enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1));
2289 break;
2291 case UNSPEC_RELOC32:
2292 if (unwrap_reloc32_p)
2294 orig = XVECEXP (x, 0, 0);
2295 *reloc_ptr = (enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1));
2297 break;
2299 default:
2300 break;
2305 return orig;
2308 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p,
2309 UNSPEC_RELOC32 wrappers. */
2312 m68k_unwrap_symbol (rtx orig, bool unwrap_reloc32_p)
2314 return m68k_unwrap_symbol_1 (orig, unwrap_reloc32_p, NULL);
2317 /* Prescan insn before outputing assembler for it. */
2319 void
2320 m68k_final_prescan_insn (rtx_insn *insn ATTRIBUTE_UNUSED,
2321 rtx *operands, int n_operands)
2323 int i;
2325 /* Combine and, possibly, other optimizations may do good job
2326 converting
2327 (const (unspec [(symbol)]))
2328 into
2329 (const (plus (unspec [(symbol)])
2330 (const_int N))).
2331 The problem with this is emitting @TLS or @GOT decorations.
2332 The decoration is emitted when processing (unspec), so the
2333 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE".
2335 It seems that the easiest solution to this is to convert such
2336 operands to
2337 (const (unspec [(plus (symbol)
2338 (const_int N))])).
2339 Note, that the top level of operand remains intact, so we don't have
2340 to patch up anything outside of the operand. */
2342 subrtx_var_iterator::array_type array;
2343 for (i = 0; i < n_operands; ++i)
2345 rtx op;
2347 op = operands[i];
2349 FOR_EACH_SUBRTX_VAR (iter, array, op, ALL)
2351 rtx x = *iter;
2352 if (m68k_unwrap_symbol (x, true) != x)
2354 rtx plus;
2356 gcc_assert (GET_CODE (x) == CONST);
2357 plus = XEXP (x, 0);
2359 if (GET_CODE (plus) == PLUS || GET_CODE (plus) == MINUS)
2361 rtx unspec;
2362 rtx addend;
2364 unspec = XEXP (plus, 0);
2365 gcc_assert (GET_CODE (unspec) == UNSPEC);
2366 addend = XEXP (plus, 1);
2367 gcc_assert (CONST_INT_P (addend));
2369 /* We now have all the pieces, rearrange them. */
2371 /* Move symbol to plus. */
2372 XEXP (plus, 0) = XVECEXP (unspec, 0, 0);
2374 /* Move plus inside unspec. */
2375 XVECEXP (unspec, 0, 0) = plus;
2377 /* Move unspec to top level of const. */
2378 XEXP (x, 0) = unspec;
2380 iter.skip_subrtxes ();
2386 /* Move X to a register and add REG_EQUAL note pointing to ORIG.
2387 If REG is non-null, use it; generate new pseudo otherwise. */
2389 static rtx
2390 m68k_move_to_reg (rtx x, rtx orig, rtx reg)
2392 rtx_insn *insn;
2394 if (reg == NULL_RTX)
2396 gcc_assert (can_create_pseudo_p ());
2397 reg = gen_reg_rtx (Pmode);
2400 insn = emit_move_insn (reg, x);
2401 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2402 by loop. */
2403 set_unique_reg_note (insn, REG_EQUAL, orig);
2405 return reg;
2408 /* Does the same as m68k_wrap_symbol, but returns a memory reference to
2409 GOT slot. */
2411 static rtx
2412 m68k_wrap_symbol_into_got_ref (rtx x, enum m68k_reloc reloc, rtx temp_reg)
2414 x = m68k_wrap_symbol (x, reloc, m68k_get_gp (), temp_reg);
2416 x = gen_rtx_MEM (Pmode, x);
2417 MEM_READONLY_P (x) = 1;
2419 return x;
2422 /* Legitimize PIC addresses. If the address is already
2423 position-independent, we return ORIG. Newly generated
2424 position-independent addresses go to REG. If we need more
2425 than one register, we lose.
2427 An address is legitimized by making an indirect reference
2428 through the Global Offset Table with the name of the symbol
2429 used as an offset.
2431 The assembler and linker are responsible for placing the
2432 address of the symbol in the GOT. The function prologue
2433 is responsible for initializing a5 to the starting address
2434 of the GOT.
2436 The assembler is also responsible for translating a symbol name
2437 into a constant displacement from the start of the GOT.
2439 A quick example may make things a little clearer:
2441 When not generating PIC code to store the value 12345 into _foo
2442 we would generate the following code:
2444 movel #12345, _foo
2446 When generating PIC two transformations are made. First, the compiler
2447 loads the address of foo into a register. So the first transformation makes:
2449 lea _foo, a0
2450 movel #12345, a0@
2452 The code in movsi will intercept the lea instruction and call this
2453 routine which will transform the instructions into:
2455 movel a5@(_foo:w), a0
2456 movel #12345, a0@
2459 That (in a nutshell) is how *all* symbol and label references are
2460 handled. */
2463 legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED,
2464 rtx reg)
2466 rtx pic_ref = orig;
2468 /* First handle a simple SYMBOL_REF or LABEL_REF */
2469 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
2471 gcc_assert (reg);
2473 pic_ref = m68k_wrap_symbol_into_got_ref (orig, RELOC_GOT, reg);
2474 pic_ref = m68k_move_to_reg (pic_ref, orig, reg);
2476 else if (GET_CODE (orig) == CONST)
2478 rtx base;
2480 /* Make sure this has not already been legitimized. */
2481 if (m68k_unwrap_symbol (orig, true) != orig)
2482 return orig;
2484 gcc_assert (reg);
2486 /* legitimize both operands of the PLUS */
2487 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
2489 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
2490 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
2491 base == reg ? 0 : reg);
2493 if (GET_CODE (orig) == CONST_INT)
2494 pic_ref = plus_constant (Pmode, base, INTVAL (orig));
2495 else
2496 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
2499 return pic_ref;
2502 /* The __tls_get_addr symbol. */
2503 static GTY(()) rtx m68k_tls_get_addr;
2505 /* Return SYMBOL_REF for __tls_get_addr. */
2507 static rtx
2508 m68k_get_tls_get_addr (void)
2510 if (m68k_tls_get_addr == NULL_RTX)
2511 m68k_tls_get_addr = init_one_libfunc ("__tls_get_addr");
2513 return m68k_tls_get_addr;
2516 /* Return libcall result in A0 instead of usual D0. */
2517 static bool m68k_libcall_value_in_a0_p = false;
2519 /* Emit instruction sequence that calls __tls_get_addr. X is
2520 the TLS symbol we are referencing and RELOC is the symbol type to use
2521 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence
2522 emitted. A pseudo register with result of __tls_get_addr call is
2523 returned. */
2525 static rtx
2526 m68k_call_tls_get_addr (rtx x, rtx eqv, enum m68k_reloc reloc)
2528 rtx a0;
2529 rtx_insn *insns;
2530 rtx dest;
2532 /* Emit the call sequence. */
2533 start_sequence ();
2535 /* FIXME: Unfortunately, emit_library_call_value does not
2536 consider (plus (%a5) (const (unspec))) to be a good enough
2537 operand for push, so it forces it into a register. The bad
2538 thing about this is that combiner, due to copy propagation and other
2539 optimizations, sometimes can not later fix this. As a consequence,
2540 additional register may be allocated resulting in a spill.
2541 For reference, see args processing loops in
2542 calls.c:emit_library_call_value_1.
2543 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */
2544 x = m68k_wrap_symbol (x, reloc, m68k_get_gp (), NULL_RTX);
2546 /* __tls_get_addr() is not a libcall, but emitting a libcall_value
2547 is the simpliest way of generating a call. The difference between
2548 __tls_get_addr() and libcall is that the result is returned in D0
2549 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2550 which temporarily switches returning the result to A0. */
2552 m68k_libcall_value_in_a0_p = true;
2553 a0 = emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX, LCT_PURE,
2554 Pmode, x, Pmode);
2555 m68k_libcall_value_in_a0_p = false;
2557 insns = get_insns ();
2558 end_sequence ();
2560 gcc_assert (can_create_pseudo_p ());
2561 dest = gen_reg_rtx (Pmode);
2562 emit_libcall_block (insns, dest, a0, eqv);
2564 return dest;
2567 /* The __tls_get_addr symbol. */
2568 static GTY(()) rtx m68k_read_tp;
2570 /* Return SYMBOL_REF for __m68k_read_tp. */
2572 static rtx
2573 m68k_get_m68k_read_tp (void)
2575 if (m68k_read_tp == NULL_RTX)
2576 m68k_read_tp = init_one_libfunc ("__m68k_read_tp");
2578 return m68k_read_tp;
2581 /* Emit instruction sequence that calls __m68k_read_tp.
2582 A pseudo register with result of __m68k_read_tp call is returned. */
2584 static rtx
2585 m68k_call_m68k_read_tp (void)
2587 rtx a0;
2588 rtx eqv;
2589 rtx_insn *insns;
2590 rtx dest;
2592 start_sequence ();
2594 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value
2595 is the simpliest way of generating a call. The difference between
2596 __m68k_read_tp() and libcall is that the result is returned in D0
2597 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p
2598 which temporarily switches returning the result to A0. */
2600 /* Emit the call sequence. */
2601 m68k_libcall_value_in_a0_p = true;
2602 a0 = emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX, LCT_PURE,
2603 Pmode);
2604 m68k_libcall_value_in_a0_p = false;
2605 insns = get_insns ();
2606 end_sequence ();
2608 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2609 share the m68k_read_tp result with other IE/LE model accesses. */
2610 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx), UNSPEC_RELOC32);
2612 gcc_assert (can_create_pseudo_p ());
2613 dest = gen_reg_rtx (Pmode);
2614 emit_libcall_block (insns, dest, a0, eqv);
2616 return dest;
2619 /* Return a legitimized address for accessing TLS SYMBOL_REF X.
2620 For explanations on instructions sequences see TLS/NPTL ABI for m68k and
2621 ColdFire. */
2624 m68k_legitimize_tls_address (rtx orig)
2626 switch (SYMBOL_REF_TLS_MODEL (orig))
2628 case TLS_MODEL_GLOBAL_DYNAMIC:
2629 orig = m68k_call_tls_get_addr (orig, orig, RELOC_TLSGD);
2630 break;
2632 case TLS_MODEL_LOCAL_DYNAMIC:
2634 rtx eqv;
2635 rtx a0;
2636 rtx x;
2638 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to
2639 share the LDM result with other LD model accesses. */
2640 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2641 UNSPEC_RELOC32);
2643 a0 = m68k_call_tls_get_addr (orig, eqv, RELOC_TLSLDM);
2645 x = m68k_wrap_symbol (orig, RELOC_TLSLDO, a0, NULL_RTX);
2647 if (can_create_pseudo_p ())
2648 x = m68k_move_to_reg (x, orig, NULL_RTX);
2650 orig = x;
2651 break;
2654 case TLS_MODEL_INITIAL_EXEC:
2656 rtx a0;
2657 rtx x;
2659 a0 = m68k_call_m68k_read_tp ();
2661 x = m68k_wrap_symbol_into_got_ref (orig, RELOC_TLSIE, NULL_RTX);
2662 x = gen_rtx_PLUS (Pmode, x, a0);
2664 if (can_create_pseudo_p ())
2665 x = m68k_move_to_reg (x, orig, NULL_RTX);
2667 orig = x;
2668 break;
2671 case TLS_MODEL_LOCAL_EXEC:
2673 rtx a0;
2674 rtx x;
2676 a0 = m68k_call_m68k_read_tp ();
2678 x = m68k_wrap_symbol (orig, RELOC_TLSLE, a0, NULL_RTX);
2680 if (can_create_pseudo_p ())
2681 x = m68k_move_to_reg (x, orig, NULL_RTX);
2683 orig = x;
2684 break;
2687 default:
2688 gcc_unreachable ();
2691 return orig;
2694 /* Return true if X is a TLS symbol. */
2696 static bool
2697 m68k_tls_symbol_p (rtx x)
2699 if (!TARGET_HAVE_TLS)
2700 return false;
2702 if (GET_CODE (x) != SYMBOL_REF)
2703 return false;
2705 return SYMBOL_REF_TLS_MODEL (x) != 0;
2708 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference,
2709 though illegitimate one.
2710 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */
2712 bool
2713 m68k_tls_reference_p (rtx x, bool legitimate_p)
2715 if (!TARGET_HAVE_TLS)
2716 return false;
2718 if (!legitimate_p)
2720 subrtx_var_iterator::array_type array;
2721 FOR_EACH_SUBRTX_VAR (iter, array, x, ALL)
2723 rtx x = *iter;
2725 /* Note: this is not the same as m68k_tls_symbol_p. */
2726 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0)
2727 return true;
2729 /* Don't recurse into legitimate TLS references. */
2730 if (m68k_tls_reference_p (x, true))
2731 iter.skip_subrtxes ();
2733 return false;
2735 else
2737 enum m68k_reloc reloc = RELOC_GOT;
2739 return (m68k_unwrap_symbol_1 (x, true, &reloc) != x
2740 && TLS_RELOC_P (reloc));
2746 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255)
2748 /* Return the type of move that should be used for integer I. */
2750 M68K_CONST_METHOD
2751 m68k_const_method (HOST_WIDE_INT i)
2753 unsigned u;
2755 if (USE_MOVQ (i))
2756 return MOVQ;
2758 /* The ColdFire doesn't have byte or word operations. */
2759 /* FIXME: This may not be useful for the m68060 either. */
2760 if (!TARGET_COLDFIRE)
2762 /* if -256 < N < 256 but N is not in range for a moveq
2763 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */
2764 if (USE_MOVQ (i ^ 0xff))
2765 return NOTB;
2766 /* Likewise, try with not.w */
2767 if (USE_MOVQ (i ^ 0xffff))
2768 return NOTW;
2769 /* This is the only value where neg.w is useful */
2770 if (i == -65408)
2771 return NEGW;
2774 /* Try also with swap. */
2775 u = i;
2776 if (USE_MOVQ ((u >> 16) | (u << 16)))
2777 return SWAP;
2779 if (TARGET_ISAB)
2781 /* Try using MVZ/MVS with an immediate value to load constants. */
2782 if (i >= 0 && i <= 65535)
2783 return MVZ;
2784 if (i >= -32768 && i <= 32767)
2785 return MVS;
2788 /* Otherwise, use move.l */
2789 return MOVL;
2792 /* Return the cost of moving constant I into a data register. */
2794 static int
2795 const_int_cost (HOST_WIDE_INT i)
2797 switch (m68k_const_method (i))
2799 case MOVQ:
2800 /* Constants between -128 and 127 are cheap due to moveq. */
2801 return 0;
2802 case MVZ:
2803 case MVS:
2804 case NOTB:
2805 case NOTW:
2806 case NEGW:
2807 case SWAP:
2808 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */
2809 return 1;
2810 case MOVL:
2811 return 2;
2812 default:
2813 gcc_unreachable ();
2817 static bool
2818 m68k_rtx_costs (rtx x, machine_mode mode, int outer_code,
2819 int opno ATTRIBUTE_UNUSED,
2820 int *total, bool speed ATTRIBUTE_UNUSED)
2822 int code = GET_CODE (x);
2824 switch (code)
2826 case CONST_INT:
2827 /* Constant zero is super cheap due to clr instruction. */
2828 if (x == const0_rtx)
2829 *total = 0;
2830 else
2831 *total = const_int_cost (INTVAL (x));
2832 return true;
2834 case CONST:
2835 case LABEL_REF:
2836 case SYMBOL_REF:
2837 *total = 3;
2838 return true;
2840 case CONST_DOUBLE:
2841 /* Make 0.0 cheaper than other floating constants to
2842 encourage creating tstsf and tstdf insns. */
2843 if (outer_code == COMPARE
2844 && (x == CONST0_RTX (SFmode) || x == CONST0_RTX (DFmode)))
2845 *total = 4;
2846 else
2847 *total = 5;
2848 return true;
2850 /* These are vaguely right for a 68020. */
2851 /* The costs for long multiply have been adjusted to work properly
2852 in synth_mult on the 68020, relative to an average of the time
2853 for add and the time for shift, taking away a little more because
2854 sometimes move insns are needed. */
2855 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS
2856 terms. */
2857 #define MULL_COST \
2858 (TUNE_68060 ? 2 \
2859 : TUNE_68040 ? 5 \
2860 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2861 : (TUNE_CFV2 && TUNE_MAC) ? 4 \
2862 : TUNE_CFV2 ? 8 \
2863 : TARGET_COLDFIRE ? 3 : 13)
2865 #define MULW_COST \
2866 (TUNE_68060 ? 2 \
2867 : TUNE_68040 ? 3 \
2868 : TUNE_68000_10 ? 5 \
2869 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \
2870 : (TUNE_CFV2 && TUNE_MAC) ? 2 \
2871 : TUNE_CFV2 ? 8 \
2872 : TARGET_COLDFIRE ? 2 : 8)
2874 #define DIVW_COST \
2875 (TARGET_CF_HWDIV ? 11 \
2876 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27)
2878 case PLUS:
2879 /* An lea costs about three times as much as a simple add. */
2880 if (mode == SImode
2881 && GET_CODE (XEXP (x, 1)) == REG
2882 && GET_CODE (XEXP (x, 0)) == MULT
2883 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2884 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2885 && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2
2886 || INTVAL (XEXP (XEXP (x, 0), 1)) == 4
2887 || INTVAL (XEXP (XEXP (x, 0), 1)) == 8))
2889 /* lea an@(dx:l:i),am */
2890 *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3);
2891 return true;
2893 return false;
2895 case ASHIFT:
2896 case ASHIFTRT:
2897 case LSHIFTRT:
2898 if (TUNE_68060)
2900 *total = COSTS_N_INSNS(1);
2901 return true;
2903 if (TUNE_68000_10)
2905 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
2907 if (INTVAL (XEXP (x, 1)) < 16)
2908 *total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2;
2909 else
2910 /* We're using clrw + swap for these cases. */
2911 *total = COSTS_N_INSNS (4) + (INTVAL (XEXP (x, 1)) - 16) / 2;
2913 else
2914 *total = COSTS_N_INSNS (10); /* Worst case. */
2915 return true;
2917 /* A shift by a big integer takes an extra instruction. */
2918 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2919 && (INTVAL (XEXP (x, 1)) == 16))
2921 *total = COSTS_N_INSNS (2); /* clrw;swap */
2922 return true;
2924 if (GET_CODE (XEXP (x, 1)) == CONST_INT
2925 && !(INTVAL (XEXP (x, 1)) > 0
2926 && INTVAL (XEXP (x, 1)) <= 8))
2928 *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3); /* lsr #i,dn */
2929 return true;
2931 return false;
2933 case MULT:
2934 if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
2935 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
2936 && mode == SImode)
2937 *total = COSTS_N_INSNS (MULW_COST);
2938 else if (mode == QImode || mode == HImode)
2939 *total = COSTS_N_INSNS (MULW_COST);
2940 else
2941 *total = COSTS_N_INSNS (MULL_COST);
2942 return true;
2944 case DIV:
2945 case UDIV:
2946 case MOD:
2947 case UMOD:
2948 if (mode == QImode || mode == HImode)
2949 *total = COSTS_N_INSNS (DIVW_COST); /* div.w */
2950 else if (TARGET_CF_HWDIV)
2951 *total = COSTS_N_INSNS (18);
2952 else
2953 *total = COSTS_N_INSNS (43); /* div.l */
2954 return true;
2956 case ZERO_EXTRACT:
2957 if (outer_code == COMPARE)
2958 *total = 0;
2959 return false;
2961 default:
2962 return false;
2966 /* Return an instruction to move CONST_INT OPERANDS[1] into data register
2967 OPERANDS[0]. */
2969 static const char *
2970 output_move_const_into_data_reg (rtx *operands)
2972 HOST_WIDE_INT i;
2974 i = INTVAL (operands[1]);
2975 switch (m68k_const_method (i))
2977 case MVZ:
2978 return "mvzw %1,%0";
2979 case MVS:
2980 return "mvsw %1,%0";
2981 case MOVQ:
2982 return "moveq %1,%0";
2983 case NOTB:
2984 CC_STATUS_INIT;
2985 operands[1] = GEN_INT (i ^ 0xff);
2986 return "moveq %1,%0\n\tnot%.b %0";
2987 case NOTW:
2988 CC_STATUS_INIT;
2989 operands[1] = GEN_INT (i ^ 0xffff);
2990 return "moveq %1,%0\n\tnot%.w %0";
2991 case NEGW:
2992 CC_STATUS_INIT;
2993 return "moveq #-128,%0\n\tneg%.w %0";
2994 case SWAP:
2996 unsigned u = i;
2998 operands[1] = GEN_INT ((u << 16) | (u >> 16));
2999 return "moveq %1,%0\n\tswap %0";
3001 case MOVL:
3002 return "move%.l %1,%0";
3003 default:
3004 gcc_unreachable ();
3008 /* Return true if I can be handled by ISA B's mov3q instruction. */
3010 bool
3011 valid_mov3q_const (HOST_WIDE_INT i)
3013 return TARGET_ISAB && (i == -1 || IN_RANGE (i, 1, 7));
3016 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0].
3017 I is the value of OPERANDS[1]. */
3019 static const char *
3020 output_move_simode_const (rtx *operands)
3022 rtx dest;
3023 HOST_WIDE_INT src;
3025 dest = operands[0];
3026 src = INTVAL (operands[1]);
3027 if (src == 0
3028 && (DATA_REG_P (dest) || MEM_P (dest))
3029 /* clr insns on 68000 read before writing. */
3030 && ((TARGET_68010 || TARGET_COLDFIRE)
3031 || !(MEM_P (dest) && MEM_VOLATILE_P (dest))))
3032 return "clr%.l %0";
3033 else if (GET_MODE (dest) == SImode && valid_mov3q_const (src))
3034 return "mov3q%.l %1,%0";
3035 else if (src == 0 && ADDRESS_REG_P (dest))
3036 return "sub%.l %0,%0";
3037 else if (DATA_REG_P (dest))
3038 return output_move_const_into_data_reg (operands);
3039 else if (ADDRESS_REG_P (dest) && IN_RANGE (src, -0x8000, 0x7fff))
3041 if (valid_mov3q_const (src))
3042 return "mov3q%.l %1,%0";
3043 return "move%.w %1,%0";
3045 else if (MEM_P (dest)
3046 && GET_CODE (XEXP (dest, 0)) == PRE_DEC
3047 && REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM
3048 && IN_RANGE (src, -0x8000, 0x7fff))
3050 if (valid_mov3q_const (src))
3051 return "mov3q%.l %1,%-";
3052 return "pea %a1";
3054 return "move%.l %1,%0";
3057 const char *
3058 output_move_simode (rtx *operands)
3060 if (GET_CODE (operands[1]) == CONST_INT)
3061 return output_move_simode_const (operands);
3062 else if ((GET_CODE (operands[1]) == SYMBOL_REF
3063 || GET_CODE (operands[1]) == CONST)
3064 && push_operand (operands[0], SImode))
3065 return "pea %a1";
3066 else if ((GET_CODE (operands[1]) == SYMBOL_REF
3067 || GET_CODE (operands[1]) == CONST)
3068 && ADDRESS_REG_P (operands[0]))
3069 return "lea %a1,%0";
3070 return "move%.l %1,%0";
3073 const char *
3074 output_move_himode (rtx *operands)
3076 if (GET_CODE (operands[1]) == CONST_INT)
3078 if (operands[1] == const0_rtx
3079 && (DATA_REG_P (operands[0])
3080 || GET_CODE (operands[0]) == MEM)
3081 /* clr insns on 68000 read before writing. */
3082 && ((TARGET_68010 || TARGET_COLDFIRE)
3083 || !(GET_CODE (operands[0]) == MEM
3084 && MEM_VOLATILE_P (operands[0]))))
3085 return "clr%.w %0";
3086 else if (operands[1] == const0_rtx
3087 && ADDRESS_REG_P (operands[0]))
3088 return "sub%.l %0,%0";
3089 else if (DATA_REG_P (operands[0])
3090 && INTVAL (operands[1]) < 128
3091 && INTVAL (operands[1]) >= -128)
3092 return "moveq %1,%0";
3093 else if (INTVAL (operands[1]) < 0x8000
3094 && INTVAL (operands[1]) >= -0x8000)
3095 return "move%.w %1,%0";
3097 else if (CONSTANT_P (operands[1]))
3098 return "move%.l %1,%0";
3099 return "move%.w %1,%0";
3102 const char *
3103 output_move_qimode (rtx *operands)
3105 /* 68k family always modifies the stack pointer by at least 2, even for
3106 byte pushes. The 5200 (ColdFire) does not do this. */
3108 /* This case is generated by pushqi1 pattern now. */
3109 gcc_assert (!(GET_CODE (operands[0]) == MEM
3110 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
3111 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
3112 && ! ADDRESS_REG_P (operands[1])
3113 && ! TARGET_COLDFIRE));
3115 /* clr and st insns on 68000 read before writing. */
3116 if (!ADDRESS_REG_P (operands[0])
3117 && ((TARGET_68010 || TARGET_COLDFIRE)
3118 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
3120 if (operands[1] == const0_rtx)
3121 return "clr%.b %0";
3122 if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0]))
3123 && GET_CODE (operands[1]) == CONST_INT
3124 && (INTVAL (operands[1]) & 255) == 255)
3126 CC_STATUS_INIT;
3127 return "st %0";
3130 if (GET_CODE (operands[1]) == CONST_INT
3131 && DATA_REG_P (operands[0])
3132 && INTVAL (operands[1]) < 128
3133 && INTVAL (operands[1]) >= -128)
3134 return "moveq %1,%0";
3135 if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0]))
3136 return "sub%.l %0,%0";
3137 if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
3138 return "move%.l %1,%0";
3139 /* 68k family (including the 5200 ColdFire) does not support byte moves to
3140 from address registers. */
3141 if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
3142 return "move%.w %1,%0";
3143 return "move%.b %1,%0";
3146 const char *
3147 output_move_stricthi (rtx *operands)
3149 if (operands[1] == const0_rtx
3150 /* clr insns on 68000 read before writing. */
3151 && ((TARGET_68010 || TARGET_COLDFIRE)
3152 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
3153 return "clr%.w %0";
3154 return "move%.w %1,%0";
3157 const char *
3158 output_move_strictqi (rtx *operands)
3160 if (operands[1] == const0_rtx
3161 /* clr insns on 68000 read before writing. */
3162 && ((TARGET_68010 || TARGET_COLDFIRE)
3163 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
3164 return "clr%.b %0";
3165 return "move%.b %1,%0";
3168 /* Return the best assembler insn template
3169 for moving operands[1] into operands[0] as a fullword. */
3171 static const char *
3172 singlemove_string (rtx *operands)
3174 if (GET_CODE (operands[1]) == CONST_INT)
3175 return output_move_simode_const (operands);
3176 return "move%.l %1,%0";
3180 /* Output assembler or rtl code to perform a doubleword move insn
3181 with operands OPERANDS.
3182 Pointers to 3 helper functions should be specified:
3183 HANDLE_REG_ADJUST to adjust a register by a small value,
3184 HANDLE_COMPADR to compute an address and
3185 HANDLE_MOVSI to move 4 bytes. */
3187 static void
3188 handle_move_double (rtx operands[2],
3189 void (*handle_reg_adjust) (rtx, int),
3190 void (*handle_compadr) (rtx [2]),
3191 void (*handle_movsi) (rtx [2]))
3193 enum
3195 REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP
3196 } optype0, optype1;
3197 rtx latehalf[2];
3198 rtx middlehalf[2];
3199 rtx xops[2];
3200 rtx addreg0 = 0, addreg1 = 0;
3201 int dest_overlapped_low = 0;
3202 int size = GET_MODE_SIZE (GET_MODE (operands[0]));
3204 middlehalf[0] = 0;
3205 middlehalf[1] = 0;
3207 /* First classify both operands. */
3209 if (REG_P (operands[0]))
3210 optype0 = REGOP;
3211 else if (offsettable_memref_p (operands[0]))
3212 optype0 = OFFSOP;
3213 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
3214 optype0 = POPOP;
3215 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
3216 optype0 = PUSHOP;
3217 else if (GET_CODE (operands[0]) == MEM)
3218 optype0 = MEMOP;
3219 else
3220 optype0 = RNDOP;
3222 if (REG_P (operands[1]))
3223 optype1 = REGOP;
3224 else if (CONSTANT_P (operands[1]))
3225 optype1 = CNSTOP;
3226 else if (offsettable_memref_p (operands[1]))
3227 optype1 = OFFSOP;
3228 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
3229 optype1 = POPOP;
3230 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
3231 optype1 = PUSHOP;
3232 else if (GET_CODE (operands[1]) == MEM)
3233 optype1 = MEMOP;
3234 else
3235 optype1 = RNDOP;
3237 /* Check for the cases that the operand constraints are not supposed
3238 to allow to happen. Generating code for these cases is
3239 painful. */
3240 gcc_assert (optype0 != RNDOP && optype1 != RNDOP);
3242 /* If one operand is decrementing and one is incrementing
3243 decrement the former register explicitly
3244 and change that operand into ordinary indexing. */
3246 if (optype0 == PUSHOP && optype1 == POPOP)
3248 operands[0] = XEXP (XEXP (operands[0], 0), 0);
3250 handle_reg_adjust (operands[0], -size);
3252 if (GET_MODE (operands[1]) == XFmode)
3253 operands[0] = gen_rtx_MEM (XFmode, operands[0]);
3254 else if (GET_MODE (operands[0]) == DFmode)
3255 operands[0] = gen_rtx_MEM (DFmode, operands[0]);
3256 else
3257 operands[0] = gen_rtx_MEM (DImode, operands[0]);
3258 optype0 = OFFSOP;
3260 if (optype0 == POPOP && optype1 == PUSHOP)
3262 operands[1] = XEXP (XEXP (operands[1], 0), 0);
3264 handle_reg_adjust (operands[1], -size);
3266 if (GET_MODE (operands[1]) == XFmode)
3267 operands[1] = gen_rtx_MEM (XFmode, operands[1]);
3268 else if (GET_MODE (operands[1]) == DFmode)
3269 operands[1] = gen_rtx_MEM (DFmode, operands[1]);
3270 else
3271 operands[1] = gen_rtx_MEM (DImode, operands[1]);
3272 optype1 = OFFSOP;
3275 /* If an operand is an unoffsettable memory ref, find a register
3276 we can increment temporarily to make it refer to the second word. */
3278 if (optype0 == MEMOP)
3279 addreg0 = find_addr_reg (XEXP (operands[0], 0));
3281 if (optype1 == MEMOP)
3282 addreg1 = find_addr_reg (XEXP (operands[1], 0));
3284 /* Ok, we can do one word at a time.
3285 Normally we do the low-numbered word first,
3286 but if either operand is autodecrementing then we
3287 do the high-numbered word first.
3289 In either case, set up in LATEHALF the operands to use
3290 for the high-numbered word and in some cases alter the
3291 operands in OPERANDS to be suitable for the low-numbered word. */
3293 if (size == 12)
3295 if (optype0 == REGOP)
3297 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2);
3298 middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3300 else if (optype0 == OFFSOP)
3302 middlehalf[0] = adjust_address (operands[0], SImode, 4);
3303 latehalf[0] = adjust_address (operands[0], SImode, size - 4);
3305 else
3307 middlehalf[0] = adjust_address (operands[0], SImode, 0);
3308 latehalf[0] = adjust_address (operands[0], SImode, 0);
3311 if (optype1 == REGOP)
3313 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
3314 middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
3316 else if (optype1 == OFFSOP)
3318 middlehalf[1] = adjust_address (operands[1], SImode, 4);
3319 latehalf[1] = adjust_address (operands[1], SImode, size - 4);
3321 else if (optype1 == CNSTOP)
3323 if (GET_CODE (operands[1]) == CONST_DOUBLE)
3325 long l[3];
3327 REAL_VALUE_TO_TARGET_LONG_DOUBLE
3328 (*CONST_DOUBLE_REAL_VALUE (operands[1]), l);
3329 operands[1] = GEN_INT (l[0]);
3330 middlehalf[1] = GEN_INT (l[1]);
3331 latehalf[1] = GEN_INT (l[2]);
3333 else
3335 /* No non-CONST_DOUBLE constant should ever appear
3336 here. */
3337 gcc_assert (!CONSTANT_P (operands[1]));
3340 else
3342 middlehalf[1] = adjust_address (operands[1], SImode, 0);
3343 latehalf[1] = adjust_address (operands[1], SImode, 0);
3346 else
3347 /* size is not 12: */
3349 if (optype0 == REGOP)
3350 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3351 else if (optype0 == OFFSOP)
3352 latehalf[0] = adjust_address (operands[0], SImode, size - 4);
3353 else
3354 latehalf[0] = adjust_address (operands[0], SImode, 0);
3356 if (optype1 == REGOP)
3357 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
3358 else if (optype1 == OFFSOP)
3359 latehalf[1] = adjust_address (operands[1], SImode, size - 4);
3360 else if (optype1 == CNSTOP)
3361 split_double (operands[1], &operands[1], &latehalf[1]);
3362 else
3363 latehalf[1] = adjust_address (operands[1], SImode, 0);
3366 /* If insn is effectively movd N(REG),-(REG) then we will do the high
3367 word first. We should use the adjusted operand 1 (which is N+4(REG))
3368 for the low word as well, to compensate for the first decrement of
3369 REG. */
3370 if (optype0 == PUSHOP
3371 && reg_overlap_mentioned_p (XEXP (XEXP (operands[0], 0), 0), operands[1]))
3372 operands[1] = middlehalf[1] = latehalf[1];
3374 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)),
3375 if the upper part of reg N does not appear in the MEM, arrange to
3376 emit the move late-half first. Otherwise, compute the MEM address
3377 into the upper part of N and use that as a pointer to the memory
3378 operand. */
3379 if (optype0 == REGOP
3380 && (optype1 == OFFSOP || optype1 == MEMOP))
3382 rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0]));
3384 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
3385 && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
3387 /* If both halves of dest are used in the src memory address,
3388 compute the address into latehalf of dest.
3389 Note that this can't happen if the dest is two data regs. */
3390 compadr:
3391 xops[0] = latehalf[0];
3392 xops[1] = XEXP (operands[1], 0);
3394 handle_compadr (xops);
3395 if (GET_MODE (operands[1]) == XFmode)
3397 operands[1] = gen_rtx_MEM (XFmode, latehalf[0]);
3398 middlehalf[1] = adjust_address (operands[1], DImode, size - 8);
3399 latehalf[1] = adjust_address (operands[1], DImode, size - 4);
3401 else
3403 operands[1] = gen_rtx_MEM (DImode, latehalf[0]);
3404 latehalf[1] = adjust_address (operands[1], DImode, size - 4);
3407 else if (size == 12
3408 && reg_overlap_mentioned_p (middlehalf[0],
3409 XEXP (operands[1], 0)))
3411 /* Check for two regs used by both source and dest.
3412 Note that this can't happen if the dest is all data regs.
3413 It can happen if the dest is d6, d7, a0.
3414 But in that case, latehalf is an addr reg, so
3415 the code at compadr does ok. */
3417 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))
3418 || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0)))
3419 goto compadr;
3421 /* JRV says this can't happen: */
3422 gcc_assert (!addreg0 && !addreg1);
3424 /* Only the middle reg conflicts; simply put it last. */
3425 handle_movsi (operands);
3426 handle_movsi (latehalf);
3427 handle_movsi (middlehalf);
3429 return;
3431 else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)))
3432 /* If the low half of dest is mentioned in the source memory
3433 address, the arrange to emit the move late half first. */
3434 dest_overlapped_low = 1;
3437 /* If one or both operands autodecrementing,
3438 do the two words, high-numbered first. */
3440 /* Likewise, the first move would clobber the source of the second one,
3441 do them in the other order. This happens only for registers;
3442 such overlap can't happen in memory unless the user explicitly
3443 sets it up, and that is an undefined circumstance. */
3445 if (optype0 == PUSHOP || optype1 == PUSHOP
3446 || (optype0 == REGOP && optype1 == REGOP
3447 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1]))
3448 || REGNO (operands[0]) == REGNO (latehalf[1])))
3449 || dest_overlapped_low)
3451 /* Make any unoffsettable addresses point at high-numbered word. */
3452 if (addreg0)
3453 handle_reg_adjust (addreg0, size - 4);
3454 if (addreg1)
3455 handle_reg_adjust (addreg1, size - 4);
3457 /* Do that word. */
3458 handle_movsi (latehalf);
3460 /* Undo the adds we just did. */
3461 if (addreg0)
3462 handle_reg_adjust (addreg0, -4);
3463 if (addreg1)
3464 handle_reg_adjust (addreg1, -4);
3466 if (size == 12)
3468 handle_movsi (middlehalf);
3470 if (addreg0)
3471 handle_reg_adjust (addreg0, -4);
3472 if (addreg1)
3473 handle_reg_adjust (addreg1, -4);
3476 /* Do low-numbered word. */
3478 handle_movsi (operands);
3479 return;
3482 /* Normal case: do the two words, low-numbered first. */
3484 m68k_final_prescan_insn (NULL, operands, 2);
3485 handle_movsi (operands);
3487 /* Do the middle one of the three words for long double */
3488 if (size == 12)
3490 if (addreg0)
3491 handle_reg_adjust (addreg0, 4);
3492 if (addreg1)
3493 handle_reg_adjust (addreg1, 4);
3495 m68k_final_prescan_insn (NULL, middlehalf, 2);
3496 handle_movsi (middlehalf);
3499 /* Make any unoffsettable addresses point at high-numbered word. */
3500 if (addreg0)
3501 handle_reg_adjust (addreg0, 4);
3502 if (addreg1)
3503 handle_reg_adjust (addreg1, 4);
3505 /* Do that word. */
3506 m68k_final_prescan_insn (NULL, latehalf, 2);
3507 handle_movsi (latehalf);
3509 /* Undo the adds we just did. */
3510 if (addreg0)
3511 handle_reg_adjust (addreg0, -(size - 4));
3512 if (addreg1)
3513 handle_reg_adjust (addreg1, -(size - 4));
3515 return;
3518 /* Output assembler code to adjust REG by N. */
3519 static void
3520 output_reg_adjust (rtx reg, int n)
3522 const char *s;
3524 gcc_assert (GET_MODE (reg) == SImode
3525 && -12 <= n && n != 0 && n <= 12);
3527 switch (n)
3529 case 12:
3530 s = "add%.l #12,%0";
3531 break;
3533 case 8:
3534 s = "addq%.l #8,%0";
3535 break;
3537 case 4:
3538 s = "addq%.l #4,%0";
3539 break;
3541 case -12:
3542 s = "sub%.l #12,%0";
3543 break;
3545 case -8:
3546 s = "subq%.l #8,%0";
3547 break;
3549 case -4:
3550 s = "subq%.l #4,%0";
3551 break;
3553 default:
3554 gcc_unreachable ();
3555 s = NULL;
3558 output_asm_insn (s, &reg);
3561 /* Emit rtl code to adjust REG by N. */
3562 static void
3563 emit_reg_adjust (rtx reg1, int n)
3565 rtx reg2;
3567 gcc_assert (GET_MODE (reg1) == SImode
3568 && -12 <= n && n != 0 && n <= 12);
3570 reg1 = copy_rtx (reg1);
3571 reg2 = copy_rtx (reg1);
3573 if (n < 0)
3574 emit_insn (gen_subsi3 (reg1, reg2, GEN_INT (-n)));
3575 else if (n > 0)
3576 emit_insn (gen_addsi3 (reg1, reg2, GEN_INT (n)));
3577 else
3578 gcc_unreachable ();
3581 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */
3582 static void
3583 output_compadr (rtx operands[2])
3585 output_asm_insn ("lea %a1,%0", operands);
3588 /* Output the best assembler insn for moving operands[1] into operands[0]
3589 as a fullword. */
3590 static void
3591 output_movsi (rtx operands[2])
3593 output_asm_insn (singlemove_string (operands), operands);
3596 /* Copy OP and change its mode to MODE. */
3597 static rtx
3598 copy_operand (rtx op, machine_mode mode)
3600 /* ??? This looks really ugly. There must be a better way
3601 to change a mode on the operand. */
3602 if (GET_MODE (op) != VOIDmode)
3604 if (REG_P (op))
3605 op = gen_rtx_REG (mode, REGNO (op));
3606 else
3608 op = copy_rtx (op);
3609 PUT_MODE (op, mode);
3613 return op;
3616 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */
3617 static void
3618 emit_movsi (rtx operands[2])
3620 operands[0] = copy_operand (operands[0], SImode);
3621 operands[1] = copy_operand (operands[1], SImode);
3623 emit_insn (gen_movsi (operands[0], operands[1]));
3626 /* Output assembler code to perform a doubleword move insn
3627 with operands OPERANDS. */
3628 const char *
3629 output_move_double (rtx *operands)
3631 handle_move_double (operands,
3632 output_reg_adjust, output_compadr, output_movsi);
3634 return "";
3637 /* Output rtl code to perform a doubleword move insn
3638 with operands OPERANDS. */
3639 void
3640 m68k_emit_move_double (rtx operands[2])
3642 handle_move_double (operands, emit_reg_adjust, emit_movsi, emit_movsi);
3645 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
3646 new rtx with the correct mode. */
3648 static rtx
3649 force_mode (machine_mode mode, rtx orig)
3651 if (mode == GET_MODE (orig))
3652 return orig;
3654 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
3655 abort ();
3657 return gen_rtx_REG (mode, REGNO (orig));
3660 static int
3661 fp_reg_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
3663 return reg_renumber && FP_REG_P (op);
3666 /* Emit insns to move operands[1] into operands[0].
3668 Return 1 if we have written out everything that needs to be done to
3669 do the move. Otherwise, return 0 and the caller will emit the move
3670 normally.
3672 Note SCRATCH_REG may not be in the proper mode depending on how it
3673 will be used. This routine is responsible for creating a new copy
3674 of SCRATCH_REG in the proper mode. */
3677 emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
3679 register rtx operand0 = operands[0];
3680 register rtx operand1 = operands[1];
3681 register rtx tem;
3683 if (scratch_reg
3684 && reload_in_progress && GET_CODE (operand0) == REG
3685 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
3686 operand0 = reg_equiv_mem (REGNO (operand0));
3687 else if (scratch_reg
3688 && reload_in_progress && GET_CODE (operand0) == SUBREG
3689 && GET_CODE (SUBREG_REG (operand0)) == REG
3690 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
3692 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3693 the code which tracks sets/uses for delete_output_reload. */
3694 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
3695 reg_equiv_mem (REGNO (SUBREG_REG (operand0))),
3696 SUBREG_BYTE (operand0));
3697 operand0 = alter_subreg (&temp, true);
3700 if (scratch_reg
3701 && reload_in_progress && GET_CODE (operand1) == REG
3702 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
3703 operand1 = reg_equiv_mem (REGNO (operand1));
3704 else if (scratch_reg
3705 && reload_in_progress && GET_CODE (operand1) == SUBREG
3706 && GET_CODE (SUBREG_REG (operand1)) == REG
3707 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
3709 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
3710 the code which tracks sets/uses for delete_output_reload. */
3711 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
3712 reg_equiv_mem (REGNO (SUBREG_REG (operand1))),
3713 SUBREG_BYTE (operand1));
3714 operand1 = alter_subreg (&temp, true);
3717 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
3718 && ((tem = find_replacement (&XEXP (operand0, 0)))
3719 != XEXP (operand0, 0)))
3720 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
3721 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
3722 && ((tem = find_replacement (&XEXP (operand1, 0)))
3723 != XEXP (operand1, 0)))
3724 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
3726 /* Handle secondary reloads for loads/stores of FP registers where
3727 the address is symbolic by using the scratch register */
3728 if (fp_reg_operand (operand0, mode)
3729 && ((GET_CODE (operand1) == MEM
3730 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
3731 || ((GET_CODE (operand1) == SUBREG
3732 && GET_CODE (XEXP (operand1, 0)) == MEM
3733 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
3734 && scratch_reg)
3736 if (GET_CODE (operand1) == SUBREG)
3737 operand1 = XEXP (operand1, 0);
3739 /* SCRATCH_REG will hold an address. We want
3740 it in SImode regardless of what mode it was originally given
3741 to us. */
3742 scratch_reg = force_mode (SImode, scratch_reg);
3744 /* D might not fit in 14 bits either; for such cases load D into
3745 scratch reg. */
3746 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
3748 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
3749 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
3750 Pmode,
3751 XEXP (XEXP (operand1, 0), 0),
3752 scratch_reg));
3754 else
3755 emit_move_insn (scratch_reg, XEXP (operand1, 0));
3756 emit_insn (gen_rtx_SET (operand0, gen_rtx_MEM (mode, scratch_reg)));
3757 return 1;
3759 else if (fp_reg_operand (operand1, mode)
3760 && ((GET_CODE (operand0) == MEM
3761 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
3762 || ((GET_CODE (operand0) == SUBREG)
3763 && GET_CODE (XEXP (operand0, 0)) == MEM
3764 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
3765 && scratch_reg)
3767 if (GET_CODE (operand0) == SUBREG)
3768 operand0 = XEXP (operand0, 0);
3770 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3771 it in SIMODE regardless of what mode it was originally given
3772 to us. */
3773 scratch_reg = force_mode (SImode, scratch_reg);
3775 /* D might not fit in 14 bits either; for such cases load D into
3776 scratch reg. */
3777 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
3779 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
3780 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
3781 0)),
3782 Pmode,
3783 XEXP (XEXP (operand0, 0),
3785 scratch_reg));
3787 else
3788 emit_move_insn (scratch_reg, XEXP (operand0, 0));
3789 emit_insn (gen_rtx_SET (gen_rtx_MEM (mode, scratch_reg), operand1));
3790 return 1;
3792 /* Handle secondary reloads for loads of FP registers from constant
3793 expressions by forcing the constant into memory.
3795 use scratch_reg to hold the address of the memory location.
3797 The proper fix is to change PREFERRED_RELOAD_CLASS to return
3798 NO_REGS when presented with a const_int and an register class
3799 containing only FP registers. Doing so unfortunately creates
3800 more problems than it solves. Fix this for 2.5. */
3801 else if (fp_reg_operand (operand0, mode)
3802 && CONSTANT_P (operand1)
3803 && scratch_reg)
3805 rtx xoperands[2];
3807 /* SCRATCH_REG will hold an address and maybe the actual data. We want
3808 it in SIMODE regardless of what mode it was originally given
3809 to us. */
3810 scratch_reg = force_mode (SImode, scratch_reg);
3812 /* Force the constant into memory and put the address of the
3813 memory location into scratch_reg. */
3814 xoperands[0] = scratch_reg;
3815 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
3816 emit_insn (gen_rtx_SET (scratch_reg, xoperands[1]));
3818 /* Now load the destination register. */
3819 emit_insn (gen_rtx_SET (operand0, gen_rtx_MEM (mode, scratch_reg)));
3820 return 1;
3823 /* Now have insn-emit do whatever it normally does. */
3824 return 0;
3827 /* Split one or more DImode RTL references into pairs of SImode
3828 references. The RTL can be REG, offsettable MEM, integer constant, or
3829 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to
3830 split and "num" is its length. lo_half and hi_half are output arrays
3831 that parallel "operands". */
3833 void
3834 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
3836 while (num--)
3838 rtx op = operands[num];
3840 /* simplify_subreg refuses to split volatile memory addresses,
3841 but we still have to handle it. */
3842 if (GET_CODE (op) == MEM)
3844 lo_half[num] = adjust_address (op, SImode, 4);
3845 hi_half[num] = adjust_address (op, SImode, 0);
3847 else
3849 lo_half[num] = simplify_gen_subreg (SImode, op,
3850 GET_MODE (op) == VOIDmode
3851 ? DImode : GET_MODE (op), 4);
3852 hi_half[num] = simplify_gen_subreg (SImode, op,
3853 GET_MODE (op) == VOIDmode
3854 ? DImode : GET_MODE (op), 0);
3859 /* Split X into a base and a constant offset, storing them in *BASE
3860 and *OFFSET respectively. */
3862 static void
3863 m68k_split_offset (rtx x, rtx *base, HOST_WIDE_INT *offset)
3865 *offset = 0;
3866 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
3868 *offset += INTVAL (XEXP (x, 1));
3869 x = XEXP (x, 0);
3871 *base = x;
3874 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem
3875 instruction. STORE_P says whether the move is a load or store.
3877 If the instruction uses post-increment or pre-decrement addressing,
3878 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total
3879 adjustment. This adjustment will be made by the first element of
3880 PARALLEL, with the loads or stores starting at element 1. If the
3881 instruction does not use post-increment or pre-decrement addressing,
3882 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores
3883 start at element 0. */
3885 bool
3886 m68k_movem_pattern_p (rtx pattern, rtx automod_base,
3887 HOST_WIDE_INT automod_offset, bool store_p)
3889 rtx base, mem_base, set, mem, reg, last_reg;
3890 HOST_WIDE_INT offset, mem_offset;
3891 int i, first, len;
3892 enum reg_class rclass;
3894 len = XVECLEN (pattern, 0);
3895 first = (automod_base != NULL);
3897 if (automod_base)
3899 /* Stores must be pre-decrement and loads must be post-increment. */
3900 if (store_p != (automod_offset < 0))
3901 return false;
3903 /* Work out the base and offset for lowest memory location. */
3904 base = automod_base;
3905 offset = (automod_offset < 0 ? automod_offset : 0);
3907 else
3909 /* Allow any valid base and offset in the first access. */
3910 base = NULL;
3911 offset = 0;
3914 last_reg = NULL;
3915 rclass = NO_REGS;
3916 for (i = first; i < len; i++)
3918 /* We need a plain SET. */
3919 set = XVECEXP (pattern, 0, i);
3920 if (GET_CODE (set) != SET)
3921 return false;
3923 /* Check that we have a memory location... */
3924 mem = XEXP (set, !store_p);
3925 if (!MEM_P (mem) || !memory_operand (mem, VOIDmode))
3926 return false;
3928 /* ...with the right address. */
3929 if (base == NULL)
3931 m68k_split_offset (XEXP (mem, 0), &base, &offset);
3932 /* The ColdFire instruction only allows (An) and (d16,An) modes.
3933 There are no mode restrictions for 680x0 besides the
3934 automodification rules enforced above. */
3935 if (TARGET_COLDFIRE
3936 && !m68k_legitimate_base_reg_p (base, reload_completed))
3937 return false;
3939 else
3941 m68k_split_offset (XEXP (mem, 0), &mem_base, &mem_offset);
3942 if (!rtx_equal_p (base, mem_base) || offset != mem_offset)
3943 return false;
3946 /* Check that we have a register of the required mode and class. */
3947 reg = XEXP (set, store_p);
3948 if (!REG_P (reg)
3949 || !HARD_REGISTER_P (reg)
3950 || GET_MODE (reg) != reg_raw_mode[REGNO (reg)])
3951 return false;
3953 if (last_reg)
3955 /* The register must belong to RCLASS and have a higher number
3956 than the register in the previous SET. */
3957 if (!TEST_HARD_REG_BIT (reg_class_contents[rclass], REGNO (reg))
3958 || REGNO (last_reg) >= REGNO (reg))
3959 return false;
3961 else
3963 /* Work out which register class we need. */
3964 if (INT_REGNO_P (REGNO (reg)))
3965 rclass = GENERAL_REGS;
3966 else if (FP_REGNO_P (REGNO (reg)))
3967 rclass = FP_REGS;
3968 else
3969 return false;
3972 last_reg = reg;
3973 offset += GET_MODE_SIZE (GET_MODE (reg));
3976 /* If we have an automodification, check whether the final offset is OK. */
3977 if (automod_base && offset != (automod_offset < 0 ? 0 : automod_offset))
3978 return false;
3980 /* Reject unprofitable cases. */
3981 if (len < first + (rclass == FP_REGS ? MIN_FMOVEM_REGS : MIN_MOVEM_REGS))
3982 return false;
3984 return true;
3987 /* Return the assembly code template for a movem or fmovem instruction
3988 whose pattern is given by PATTERN. Store the template's operands
3989 in OPERANDS.
3991 If the instruction uses post-increment or pre-decrement addressing,
3992 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P
3993 is true if this is a store instruction. */
3995 const char *
3996 m68k_output_movem (rtx *operands, rtx pattern,
3997 HOST_WIDE_INT automod_offset, bool store_p)
3999 unsigned int mask;
4000 int i, first;
4002 gcc_assert (GET_CODE (pattern) == PARALLEL);
4003 mask = 0;
4004 first = (automod_offset != 0);
4005 for (i = first; i < XVECLEN (pattern, 0); i++)
4007 /* When using movem with pre-decrement addressing, register X + D0_REG
4008 is controlled by bit 15 - X. For all other addressing modes,
4009 register X + D0_REG is controlled by bit X. Confusingly, the
4010 register mask for fmovem is in the opposite order to that for
4011 movem. */
4012 unsigned int regno;
4014 gcc_assert (MEM_P (XEXP (XVECEXP (pattern, 0, i), !store_p)));
4015 gcc_assert (REG_P (XEXP (XVECEXP (pattern, 0, i), store_p)));
4016 regno = REGNO (XEXP (XVECEXP (pattern, 0, i), store_p));
4017 if (automod_offset < 0)
4019 if (FP_REGNO_P (regno))
4020 mask |= 1 << (regno - FP0_REG);
4021 else
4022 mask |= 1 << (15 - (regno - D0_REG));
4024 else
4026 if (FP_REGNO_P (regno))
4027 mask |= 1 << (7 - (regno - FP0_REG));
4028 else
4029 mask |= 1 << (regno - D0_REG);
4032 CC_STATUS_INIT;
4034 if (automod_offset == 0)
4035 operands[0] = XEXP (XEXP (XVECEXP (pattern, 0, first), !store_p), 0);
4036 else if (automod_offset < 0)
4037 operands[0] = gen_rtx_PRE_DEC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0)));
4038 else
4039 operands[0] = gen_rtx_POST_INC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0)));
4040 operands[1] = GEN_INT (mask);
4041 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern, 0, first), store_p))))
4043 if (store_p)
4044 return "fmovem %1,%a0";
4045 else
4046 return "fmovem %a0,%1";
4048 else
4050 if (store_p)
4051 return "movem%.l %1,%a0";
4052 else
4053 return "movem%.l %a0,%1";
4057 /* Return a REG that occurs in ADDR with coefficient 1.
4058 ADDR can be effectively incremented by incrementing REG. */
4060 static rtx
4061 find_addr_reg (rtx addr)
4063 while (GET_CODE (addr) == PLUS)
4065 if (GET_CODE (XEXP (addr, 0)) == REG)
4066 addr = XEXP (addr, 0);
4067 else if (GET_CODE (XEXP (addr, 1)) == REG)
4068 addr = XEXP (addr, 1);
4069 else if (CONSTANT_P (XEXP (addr, 0)))
4070 addr = XEXP (addr, 1);
4071 else if (CONSTANT_P (XEXP (addr, 1)))
4072 addr = XEXP (addr, 0);
4073 else
4074 gcc_unreachable ();
4076 gcc_assert (GET_CODE (addr) == REG);
4077 return addr;
4080 /* Output assembler code to perform a 32-bit 3-operand add. */
4082 const char *
4083 output_addsi3 (rtx *operands)
4085 if (! operands_match_p (operands[0], operands[1]))
4087 if (!ADDRESS_REG_P (operands[1]))
4089 rtx tmp = operands[1];
4091 operands[1] = operands[2];
4092 operands[2] = tmp;
4095 /* These insns can result from reloads to access
4096 stack slots over 64k from the frame pointer. */
4097 if (GET_CODE (operands[2]) == CONST_INT
4098 && (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767))
4099 return "move%.l %2,%0\n\tadd%.l %1,%0";
4100 if (GET_CODE (operands[2]) == REG)
4101 return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
4102 return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
4104 if (GET_CODE (operands[2]) == CONST_INT)
4106 if (INTVAL (operands[2]) > 0
4107 && INTVAL (operands[2]) <= 8)
4108 return "addq%.l %2,%0";
4109 if (INTVAL (operands[2]) < 0
4110 && INTVAL (operands[2]) >= -8)
4112 operands[2] = GEN_INT (- INTVAL (operands[2]));
4113 return "subq%.l %2,%0";
4115 /* On the CPU32 it is faster to use two addql instructions to
4116 add a small integer (8 < N <= 16) to a register.
4117 Likewise for subql. */
4118 if (TUNE_CPU32 && REG_P (operands[0]))
4120 if (INTVAL (operands[2]) > 8
4121 && INTVAL (operands[2]) <= 16)
4123 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
4124 return "addq%.l #8,%0\n\taddq%.l %2,%0";
4126 if (INTVAL (operands[2]) < -8
4127 && INTVAL (operands[2]) >= -16)
4129 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8);
4130 return "subq%.l #8,%0\n\tsubq%.l %2,%0";
4133 if (ADDRESS_REG_P (operands[0])
4134 && INTVAL (operands[2]) >= -0x8000
4135 && INTVAL (operands[2]) < 0x8000)
4137 if (TUNE_68040)
4138 return "add%.w %2,%0";
4139 else
4140 return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0";
4143 return "add%.l %2,%0";
4146 /* Store in cc_status the expressions that the condition codes will
4147 describe after execution of an instruction whose pattern is EXP.
4148 Do not alter them if the instruction would not alter the cc's. */
4150 /* On the 68000, all the insns to store in an address register fail to
4151 set the cc's. However, in some cases these instructions can make it
4152 possibly invalid to use the saved cc's. In those cases we clear out
4153 some or all of the saved cc's so they won't be used. */
4155 void
4156 notice_update_cc (rtx exp, rtx insn)
4158 if (GET_CODE (exp) == SET)
4160 if (GET_CODE (SET_SRC (exp)) == CALL)
4161 CC_STATUS_INIT;
4162 else if (ADDRESS_REG_P (SET_DEST (exp)))
4164 if (cc_status.value1 && modified_in_p (cc_status.value1, insn))
4165 cc_status.value1 = 0;
4166 if (cc_status.value2 && modified_in_p (cc_status.value2, insn))
4167 cc_status.value2 = 0;
4169 /* fmoves to memory or data registers do not set the condition
4170 codes. Normal moves _do_ set the condition codes, but not in
4171 a way that is appropriate for comparison with 0, because -0.0
4172 would be treated as a negative nonzero number. Note that it
4173 isn't appropriate to conditionalize this restriction on
4174 HONOR_SIGNED_ZEROS because that macro merely indicates whether
4175 we care about the difference between -0.0 and +0.0. */
4176 else if (!FP_REG_P (SET_DEST (exp))
4177 && SET_DEST (exp) != cc0_rtx
4178 && (FP_REG_P (SET_SRC (exp))
4179 || GET_CODE (SET_SRC (exp)) == FIX
4180 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp)))))
4181 CC_STATUS_INIT;
4182 /* A pair of move insns doesn't produce a useful overall cc. */
4183 else if (!FP_REG_P (SET_DEST (exp))
4184 && !FP_REG_P (SET_SRC (exp))
4185 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
4186 && (GET_CODE (SET_SRC (exp)) == REG
4187 || GET_CODE (SET_SRC (exp)) == MEM
4188 || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE))
4189 CC_STATUS_INIT;
4190 else if (SET_DEST (exp) != pc_rtx)
4192 cc_status.flags = 0;
4193 cc_status.value1 = SET_DEST (exp);
4194 cc_status.value2 = SET_SRC (exp);
4197 else if (GET_CODE (exp) == PARALLEL
4198 && GET_CODE (XVECEXP (exp, 0, 0)) == SET)
4200 rtx dest = SET_DEST (XVECEXP (exp, 0, 0));
4201 rtx src = SET_SRC (XVECEXP (exp, 0, 0));
4203 if (ADDRESS_REG_P (dest))
4204 CC_STATUS_INIT;
4205 else if (dest != pc_rtx)
4207 cc_status.flags = 0;
4208 cc_status.value1 = dest;
4209 cc_status.value2 = src;
4212 else
4213 CC_STATUS_INIT;
4214 if (cc_status.value2 != 0
4215 && ADDRESS_REG_P (cc_status.value2)
4216 && GET_MODE (cc_status.value2) == QImode)
4217 CC_STATUS_INIT;
4218 if (cc_status.value2 != 0)
4219 switch (GET_CODE (cc_status.value2))
4221 case ASHIFT: case ASHIFTRT: case LSHIFTRT:
4222 case ROTATE: case ROTATERT:
4223 /* These instructions always clear the overflow bit, and set
4224 the carry to the bit shifted out. */
4225 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY;
4226 break;
4228 case PLUS: case MINUS: case MULT:
4229 case DIV: case UDIV: case MOD: case UMOD: case NEG:
4230 if (GET_MODE (cc_status.value2) != VOIDmode)
4231 cc_status.flags |= CC_NO_OVERFLOW;
4232 break;
4233 case ZERO_EXTEND:
4234 /* (SET r1 (ZERO_EXTEND r2)) on this machine
4235 ends with a move insn moving r2 in r2's mode.
4236 Thus, the cc's are set for r2.
4237 This can set N bit spuriously. */
4238 cc_status.flags |= CC_NOT_NEGATIVE;
4240 default:
4241 break;
4243 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
4244 && cc_status.value2
4245 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
4246 cc_status.value2 = 0;
4247 /* Check for PRE_DEC in dest modifying a register used in src. */
4248 if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM
4249 && GET_CODE (XEXP (cc_status.value1, 0)) == PRE_DEC
4250 && cc_status.value2
4251 && reg_overlap_mentioned_p (XEXP (XEXP (cc_status.value1, 0), 0),
4252 cc_status.value2))
4253 cc_status.value2 = 0;
4254 if (((cc_status.value1 && FP_REG_P (cc_status.value1))
4255 || (cc_status.value2 && FP_REG_P (cc_status.value2))))
4256 cc_status.flags = CC_IN_68881;
4257 if (cc_status.value2 && GET_CODE (cc_status.value2) == COMPARE
4258 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status.value2, 0))) == MODE_FLOAT)
4260 cc_status.flags = CC_IN_68881;
4261 if (!FP_REG_P (XEXP (cc_status.value2, 0))
4262 && FP_REG_P (XEXP (cc_status.value2, 1)))
4263 cc_status.flags |= CC_REVERSED;
4267 const char *
4268 output_move_const_double (rtx *operands)
4270 int code = standard_68881_constant_p (operands[1]);
4272 if (code != 0)
4274 static char buf[40];
4276 sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff);
4277 return buf;
4279 return "fmove%.d %1,%0";
4282 const char *
4283 output_move_const_single (rtx *operands)
4285 int code = standard_68881_constant_p (operands[1]);
4287 if (code != 0)
4289 static char buf[40];
4291 sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff);
4292 return buf;
4294 return "fmove%.s %f1,%0";
4297 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
4298 from the "fmovecr" instruction.
4299 The value, anded with 0xff, gives the code to use in fmovecr
4300 to get the desired constant. */
4302 /* This code has been fixed for cross-compilation. */
4304 static int inited_68881_table = 0;
4306 static const char *const strings_68881[7] = {
4307 "0.0",
4308 "1.0",
4309 "10.0",
4310 "100.0",
4311 "10000.0",
4312 "1e8",
4313 "1e16"
4316 static const int codes_68881[7] = {
4317 0x0f,
4318 0x32,
4319 0x33,
4320 0x34,
4321 0x35,
4322 0x36,
4323 0x37
4326 REAL_VALUE_TYPE values_68881[7];
4328 /* Set up values_68881 array by converting the decimal values
4329 strings_68881 to binary. */
4331 void
4332 init_68881_table (void)
4334 int i;
4335 REAL_VALUE_TYPE r;
4336 machine_mode mode;
4338 mode = SFmode;
4339 for (i = 0; i < 7; i++)
4341 if (i == 6)
4342 mode = DFmode;
4343 r = REAL_VALUE_ATOF (strings_68881[i], mode);
4344 values_68881[i] = r;
4346 inited_68881_table = 1;
4350 standard_68881_constant_p (rtx x)
4352 const REAL_VALUE_TYPE *r;
4353 int i;
4355 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be
4356 used at all on those chips. */
4357 if (TUNE_68040_60)
4358 return 0;
4360 if (! inited_68881_table)
4361 init_68881_table ();
4363 r = CONST_DOUBLE_REAL_VALUE (x);
4365 /* Use real_identical instead of real_equal so that -0.0 is rejected. */
4366 for (i = 0; i < 6; i++)
4368 if (real_identical (r, &values_68881[i]))
4369 return (codes_68881[i]);
4372 if (GET_MODE (x) == SFmode)
4373 return 0;
4375 if (real_equal (r, &values_68881[6]))
4376 return (codes_68881[6]);
4378 /* larger powers of ten in the constants ram are not used
4379 because they are not equal to a `double' C constant. */
4380 return 0;
4383 /* If X is a floating-point constant, return the logarithm of X base 2,
4384 or 0 if X is not a power of 2. */
4387 floating_exact_log2 (rtx x)
4389 const REAL_VALUE_TYPE *r;
4390 REAL_VALUE_TYPE r1;
4391 int exp;
4393 r = CONST_DOUBLE_REAL_VALUE (x);
4395 if (real_less (r, &dconst1))
4396 return 0;
4398 exp = real_exponent (r);
4399 real_2expN (&r1, exp, DFmode);
4400 if (real_equal (&r1, r))
4401 return exp;
4403 return 0;
4406 /* A C compound statement to output to stdio stream STREAM the
4407 assembler syntax for an instruction operand X. X is an RTL
4408 expression.
4410 CODE is a value that can be used to specify one of several ways
4411 of printing the operand. It is used when identical operands
4412 must be printed differently depending on the context. CODE
4413 comes from the `%' specification that was used to request
4414 printing of the operand. If the specification was just `%DIGIT'
4415 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4416 is the ASCII code for LTR.
4418 If X is a register, this macro should print the register's name.
4419 The names can be found in an array `reg_names' whose type is
4420 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4422 When the machine description has a specification `%PUNCT' (a `%'
4423 followed by a punctuation character), this macro is called with
4424 a null pointer for X and the punctuation character for CODE.
4426 The m68k specific codes are:
4428 '.' for dot needed in Motorola-style opcode names.
4429 '-' for an operand pushing on the stack:
4430 sp@-, -(sp) or -(%sp) depending on the style of syntax.
4431 '+' for an operand pushing on the stack:
4432 sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
4433 '@' for a reference to the top word on the stack:
4434 sp@, (sp) or (%sp) depending on the style of syntax.
4435 '#' for an immediate operand prefix (# in MIT and Motorola syntax
4436 but & in SGS syntax).
4437 '!' for the cc register (used in an `and to cc' insn).
4438 '$' for the letter `s' in an op code, but only on the 68040.
4439 '&' for the letter `d' in an op code, but only on the 68040.
4440 '/' for register prefix needed by longlong.h.
4441 '?' for m68k_library_id_string
4443 'b' for byte insn (no effect, on the Sun; this is for the ISI).
4444 'd' to force memory addressing to be absolute, not relative.
4445 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
4446 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
4447 or print pair of registers as rx:ry.
4448 'p' print an address with @PLTPC attached, but only if the operand
4449 is not locally-bound. */
4451 void
4452 print_operand (FILE *file, rtx op, int letter)
4454 if (letter == '.')
4456 if (MOTOROLA)
4457 fprintf (file, ".");
4459 else if (letter == '#')
4460 asm_fprintf (file, "%I");
4461 else if (letter == '-')
4462 asm_fprintf (file, MOTOROLA ? "-(%Rsp)" : "%Rsp@-");
4463 else if (letter == '+')
4464 asm_fprintf (file, MOTOROLA ? "(%Rsp)+" : "%Rsp@+");
4465 else if (letter == '@')
4466 asm_fprintf (file, MOTOROLA ? "(%Rsp)" : "%Rsp@");
4467 else if (letter == '!')
4468 asm_fprintf (file, "%Rfpcr");
4469 else if (letter == '$')
4471 if (TARGET_68040)
4472 fprintf (file, "s");
4474 else if (letter == '&')
4476 if (TARGET_68040)
4477 fprintf (file, "d");
4479 else if (letter == '/')
4480 asm_fprintf (file, "%R");
4481 else if (letter == '?')
4482 asm_fprintf (file, m68k_library_id_string);
4483 else if (letter == 'p')
4485 output_addr_const (file, op);
4486 if (!(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op)))
4487 fprintf (file, "@PLTPC");
4489 else if (GET_CODE (op) == REG)
4491 if (letter == 'R')
4492 /* Print out the second register name of a register pair.
4493 I.e., R (6) => 7. */
4494 fputs (M68K_REGNAME(REGNO (op) + 1), file);
4495 else
4496 fputs (M68K_REGNAME(REGNO (op)), file);
4498 else if (GET_CODE (op) == MEM)
4500 output_address (GET_MODE (op), XEXP (op, 0));
4501 if (letter == 'd' && ! TARGET_68020
4502 && CONSTANT_ADDRESS_P (XEXP (op, 0))
4503 && !(GET_CODE (XEXP (op, 0)) == CONST_INT
4504 && INTVAL (XEXP (op, 0)) < 0x8000
4505 && INTVAL (XEXP (op, 0)) >= -0x8000))
4506 fprintf (file, MOTOROLA ? ".l" : ":l");
4508 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode)
4510 long l;
4511 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), l);
4512 asm_fprintf (file, "%I0x%lx", l & 0xFFFFFFFF);
4514 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode)
4516 long l[3];
4517 REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
4518 asm_fprintf (file, "%I0x%lx%08lx%08lx", l[0] & 0xFFFFFFFF,
4519 l[1] & 0xFFFFFFFF, l[2] & 0xFFFFFFFF);
4521 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode)
4523 long l[2];
4524 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
4525 asm_fprintf (file, "%I0x%lx%08lx", l[0] & 0xFFFFFFFF, l[1] & 0xFFFFFFFF);
4527 else
4529 /* Use `print_operand_address' instead of `output_addr_const'
4530 to ensure that we print relevant PIC stuff. */
4531 asm_fprintf (file, "%I");
4532 if (TARGET_PCREL
4533 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST))
4534 print_operand_address (file, op);
4535 else
4536 output_addr_const (file, op);
4540 /* Return string for TLS relocation RELOC. */
4542 static const char *
4543 m68k_get_reloc_decoration (enum m68k_reloc reloc)
4545 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */
4546 gcc_assert (MOTOROLA || reloc == RELOC_GOT);
4548 switch (reloc)
4550 case RELOC_GOT:
4551 if (MOTOROLA)
4553 if (flag_pic == 1 && TARGET_68020)
4554 return "@GOT.w";
4555 else
4556 return "@GOT";
4558 else
4560 if (TARGET_68020)
4562 switch (flag_pic)
4564 case 1:
4565 return ":w";
4566 case 2:
4567 return ":l";
4568 default:
4569 return "";
4573 gcc_unreachable ();
4575 case RELOC_TLSGD:
4576 return "@TLSGD";
4578 case RELOC_TLSLDM:
4579 return "@TLSLDM";
4581 case RELOC_TLSLDO:
4582 return "@TLSLDO";
4584 case RELOC_TLSIE:
4585 return "@TLSIE";
4587 case RELOC_TLSLE:
4588 return "@TLSLE";
4590 default:
4591 gcc_unreachable ();
4595 /* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */
4597 static bool
4598 m68k_output_addr_const_extra (FILE *file, rtx x)
4600 if (GET_CODE (x) == UNSPEC)
4602 switch (XINT (x, 1))
4604 case UNSPEC_RELOC16:
4605 case UNSPEC_RELOC32:
4606 output_addr_const (file, XVECEXP (x, 0, 0));
4607 fputs (m68k_get_reloc_decoration
4608 ((enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1))), file);
4609 return true;
4611 default:
4612 break;
4616 return false;
4619 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */
4621 static void
4622 m68k_output_dwarf_dtprel (FILE *file, int size, rtx x)
4624 gcc_assert (size == 4);
4625 fputs ("\t.long\t", file);
4626 output_addr_const (file, x);
4627 fputs ("@TLSLDO+0x8000", file);
4630 /* In the name of slightly smaller debug output, and to cater to
4631 general assembler lossage, recognize various UNSPEC sequences
4632 and turn them back into a direct symbol reference. */
4634 static rtx
4635 m68k_delegitimize_address (rtx orig_x)
4637 rtx x;
4638 struct m68k_address addr;
4639 rtx unspec;
4641 orig_x = delegitimize_mem_from_attrs (orig_x);
4642 x = orig_x;
4643 if (MEM_P (x))
4644 x = XEXP (x, 0);
4646 if (GET_CODE (x) != PLUS || GET_MODE (x) != Pmode)
4647 return orig_x;
4649 if (!m68k_decompose_address (GET_MODE (x), x, false, &addr)
4650 || addr.offset == NULL_RTX
4651 || GET_CODE (addr.offset) != CONST)
4652 return orig_x;
4654 unspec = XEXP (addr.offset, 0);
4655 if (GET_CODE (unspec) == PLUS && CONST_INT_P (XEXP (unspec, 1)))
4656 unspec = XEXP (unspec, 0);
4657 if (GET_CODE (unspec) != UNSPEC
4658 || (XINT (unspec, 1) != UNSPEC_RELOC16
4659 && XINT (unspec, 1) != UNSPEC_RELOC32))
4660 return orig_x;
4661 x = XVECEXP (unspec, 0, 0);
4662 gcc_assert (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF);
4663 if (unspec != XEXP (addr.offset, 0))
4664 x = gen_rtx_PLUS (Pmode, x, XEXP (XEXP (addr.offset, 0), 1));
4665 if (addr.index)
4667 rtx idx = addr.index;
4668 if (addr.scale != 1)
4669 idx = gen_rtx_MULT (Pmode, idx, GEN_INT (addr.scale));
4670 x = gen_rtx_PLUS (Pmode, idx, x);
4672 if (addr.base)
4673 x = gen_rtx_PLUS (Pmode, addr.base, x);
4674 if (MEM_P (orig_x))
4675 x = replace_equiv_address_nv (orig_x, x);
4676 return x;
4680 /* A C compound statement to output to stdio stream STREAM the
4681 assembler syntax for an instruction operand that is a memory
4682 reference whose address is ADDR. ADDR is an RTL expression.
4684 Note that this contains a kludge that knows that the only reason
4685 we have an address (plus (label_ref...) (reg...)) when not generating
4686 PIC code is in the insn before a tablejump, and we know that m68k.md
4687 generates a label LInnn: on such an insn.
4689 It is possible for PIC to generate a (plus (label_ref...) (reg...))
4690 and we handle that just like we would a (plus (symbol_ref...) (reg...)).
4692 This routine is responsible for distinguishing between -fpic and -fPIC
4693 style relocations in an address. When generating -fpic code the
4694 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating
4695 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */
4697 void
4698 print_operand_address (FILE *file, rtx addr)
4700 struct m68k_address address;
4702 if (!m68k_decompose_address (QImode, addr, true, &address))
4703 gcc_unreachable ();
4705 if (address.code == PRE_DEC)
4706 fprintf (file, MOTOROLA ? "-(%s)" : "%s@-",
4707 M68K_REGNAME (REGNO (address.base)));
4708 else if (address.code == POST_INC)
4709 fprintf (file, MOTOROLA ? "(%s)+" : "%s@+",
4710 M68K_REGNAME (REGNO (address.base)));
4711 else if (!address.base && !address.index)
4713 /* A constant address. */
4714 gcc_assert (address.offset == addr);
4715 if (GET_CODE (addr) == CONST_INT)
4717 /* (xxx).w or (xxx).l. */
4718 if (IN_RANGE (INTVAL (addr), -0x8000, 0x7fff))
4719 fprintf (file, MOTOROLA ? "%d.w" : "%d:w", (int) INTVAL (addr));
4720 else
4721 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr));
4723 else if (TARGET_PCREL)
4725 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */
4726 fputc ('(', file);
4727 output_addr_const (file, addr);
4728 asm_fprintf (file, flag_pic == 1 ? ":w,%Rpc)" : ":l,%Rpc)");
4730 else
4732 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol
4733 name ends in `.<letter>', as the last 2 characters can be
4734 mistaken as a size suffix. Put the name in parentheses. */
4735 if (GET_CODE (addr) == SYMBOL_REF
4736 && strlen (XSTR (addr, 0)) > 2
4737 && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.')
4739 putc ('(', file);
4740 output_addr_const (file, addr);
4741 putc (')', file);
4743 else
4744 output_addr_const (file, addr);
4747 else
4749 int labelno;
4751 /* If ADDR is a (d8,pc,Xn) address, this is the number of the
4752 label being accessed, otherwise it is -1. */
4753 labelno = (address.offset
4754 && !address.base
4755 && GET_CODE (address.offset) == LABEL_REF
4756 ? CODE_LABEL_NUMBER (XEXP (address.offset, 0))
4757 : -1);
4758 if (MOTOROLA)
4760 /* Print the "offset(base" component. */
4761 if (labelno >= 0)
4762 asm_fprintf (file, "%LL%d(%Rpc,", labelno);
4763 else
4765 if (address.offset)
4766 output_addr_const (file, address.offset);
4768 putc ('(', file);
4769 if (address.base)
4770 fputs (M68K_REGNAME (REGNO (address.base)), file);
4772 /* Print the ",index" component, if any. */
4773 if (address.index)
4775 if (address.base)
4776 putc (',', file);
4777 fprintf (file, "%s.%c",
4778 M68K_REGNAME (REGNO (address.index)),
4779 GET_MODE (address.index) == HImode ? 'w' : 'l');
4780 if (address.scale != 1)
4781 fprintf (file, "*%d", address.scale);
4783 putc (')', file);
4785 else /* !MOTOROLA */
4787 if (!address.offset && !address.index)
4788 fprintf (file, "%s@", M68K_REGNAME (REGNO (address.base)));
4789 else
4791 /* Print the "base@(offset" component. */
4792 if (labelno >= 0)
4793 asm_fprintf (file, "%Rpc@(%LL%d", labelno);
4794 else
4796 if (address.base)
4797 fputs (M68K_REGNAME (REGNO (address.base)), file);
4798 fprintf (file, "@(");
4799 if (address.offset)
4800 output_addr_const (file, address.offset);
4802 /* Print the ",index" component, if any. */
4803 if (address.index)
4805 fprintf (file, ",%s:%c",
4806 M68K_REGNAME (REGNO (address.index)),
4807 GET_MODE (address.index) == HImode ? 'w' : 'l');
4808 if (address.scale != 1)
4809 fprintf (file, ":%d", address.scale);
4811 putc (')', file);
4817 /* Check for cases where a clr insns can be omitted from code using
4818 strict_low_part sets. For example, the second clrl here is not needed:
4819 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ...
4821 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear
4822 insn we are checking for redundancy. TARGET is the register set by the
4823 clear insn. */
4825 bool
4826 strict_low_part_peephole_ok (machine_mode mode, rtx_insn *first_insn,
4827 rtx target)
4829 rtx_insn *p = first_insn;
4831 while ((p = PREV_INSN (p)))
4833 if (NOTE_INSN_BASIC_BLOCK_P (p))
4834 return false;
4836 if (NOTE_P (p))
4837 continue;
4839 /* If it isn't an insn, then give up. */
4840 if (!INSN_P (p))
4841 return false;
4843 if (reg_set_p (target, p))
4845 rtx set = single_set (p);
4846 rtx dest;
4848 /* If it isn't an easy to recognize insn, then give up. */
4849 if (! set)
4850 return false;
4852 dest = SET_DEST (set);
4854 /* If this sets the entire target register to zero, then our
4855 first_insn is redundant. */
4856 if (rtx_equal_p (dest, target)
4857 && SET_SRC (set) == const0_rtx)
4858 return true;
4859 else if (GET_CODE (dest) == STRICT_LOW_PART
4860 && GET_CODE (XEXP (dest, 0)) == REG
4861 && REGNO (XEXP (dest, 0)) == REGNO (target)
4862 && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0)))
4863 <= GET_MODE_SIZE (mode)))
4864 /* This is a strict low part set which modifies less than
4865 we are using, so it is safe. */
4867 else
4868 return false;
4872 return false;
4875 /* Operand predicates for implementing asymmetric pc-relative addressing
4876 on m68k. The m68k supports pc-relative addressing (mode 7, register 2)
4877 when used as a source operand, but not as a destination operand.
4879 We model this by restricting the meaning of the basic predicates
4880 (general_operand, memory_operand, etc) to forbid the use of this
4881 addressing mode, and then define the following predicates that permit
4882 this addressing mode. These predicates can then be used for the
4883 source operands of the appropriate instructions.
4885 n.b. While it is theoretically possible to change all machine patterns
4886 to use this addressing more where permitted by the architecture,
4887 it has only been implemented for "common" cases: SImode, HImode, and
4888 QImode operands, and only for the principle operations that would
4889 require this addressing mode: data movement and simple integer operations.
4891 In parallel with these new predicates, two new constraint letters
4892 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'.
4893 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case.
4894 In the pcrel case 's' is only valid in combination with 'a' registers.
4895 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding
4896 of how these constraints are used.
4898 The use of these predicates is strictly optional, though patterns that
4899 don't will cause an extra reload register to be allocated where one
4900 was not necessary:
4902 lea (abc:w,%pc),%a0 ; need to reload address
4903 moveq &1,%d1 ; since write to pc-relative space
4904 movel %d1,%a0@ ; is not allowed
4906 lea (abc:w,%pc),%a1 ; no need to reload address here
4907 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok
4909 For more info, consult tiemann@cygnus.com.
4912 All of the ugliness with predicates and constraints is due to the
4913 simple fact that the m68k does not allow a pc-relative addressing
4914 mode as a destination. gcc does not distinguish between source and
4915 destination addresses. Hence, if we claim that pc-relative address
4916 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we
4917 end up with invalid code. To get around this problem, we left
4918 pc-relative modes as invalid addresses, and then added special
4919 predicates and constraints to accept them.
4921 A cleaner way to handle this is to modify gcc to distinguish
4922 between source and destination addresses. We can then say that
4923 pc-relative is a valid source address but not a valid destination
4924 address, and hopefully avoid a lot of the predicate and constraint
4925 hackery. Unfortunately, this would be a pretty big change. It would
4926 be a useful change for a number of ports, but there aren't any current
4927 plans to undertake this.
4929 ***************************************************************************/
4932 const char *
4933 output_andsi3 (rtx *operands)
4935 int logval;
4936 if (GET_CODE (operands[2]) == CONST_INT
4937 && (INTVAL (operands[2]) | 0xffff) == -1
4938 && (DATA_REG_P (operands[0])
4939 || offsettable_memref_p (operands[0]))
4940 && !TARGET_COLDFIRE)
4942 if (GET_CODE (operands[0]) != REG)
4943 operands[0] = adjust_address (operands[0], HImode, 2);
4944 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
4945 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4946 CC_STATUS_INIT;
4947 if (operands[2] == const0_rtx)
4948 return "clr%.w %0";
4949 return "and%.w %2,%0";
4951 if (GET_CODE (operands[2]) == CONST_INT
4952 && (logval = exact_log2 (~ INTVAL (operands[2]) & 0xffffffff)) >= 0
4953 && (DATA_REG_P (operands[0])
4954 || offsettable_memref_p (operands[0])))
4956 if (DATA_REG_P (operands[0]))
4957 operands[1] = GEN_INT (logval);
4958 else
4960 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
4961 operands[1] = GEN_INT (logval % 8);
4963 /* This does not set condition codes in a standard way. */
4964 CC_STATUS_INIT;
4965 return "bclr %1,%0";
4967 return "and%.l %2,%0";
4970 const char *
4971 output_iorsi3 (rtx *operands)
4973 register int logval;
4974 if (GET_CODE (operands[2]) == CONST_INT
4975 && INTVAL (operands[2]) >> 16 == 0
4976 && (DATA_REG_P (operands[0])
4977 || offsettable_memref_p (operands[0]))
4978 && !TARGET_COLDFIRE)
4980 if (GET_CODE (operands[0]) != REG)
4981 operands[0] = adjust_address (operands[0], HImode, 2);
4982 /* Do not delete a following tstl %0 insn; that would be incorrect. */
4983 CC_STATUS_INIT;
4984 if (INTVAL (operands[2]) == 0xffff)
4985 return "mov%.w %2,%0";
4986 return "or%.w %2,%0";
4988 if (GET_CODE (operands[2]) == CONST_INT
4989 && (logval = exact_log2 (INTVAL (operands[2]) & 0xffffffff)) >= 0
4990 && (DATA_REG_P (operands[0])
4991 || offsettable_memref_p (operands[0])))
4993 if (DATA_REG_P (operands[0]))
4994 operands[1] = GEN_INT (logval);
4995 else
4997 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
4998 operands[1] = GEN_INT (logval % 8);
5000 CC_STATUS_INIT;
5001 return "bset %1,%0";
5003 return "or%.l %2,%0";
5006 const char *
5007 output_xorsi3 (rtx *operands)
5009 register int logval;
5010 if (GET_CODE (operands[2]) == CONST_INT
5011 && INTVAL (operands[2]) >> 16 == 0
5012 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))
5013 && !TARGET_COLDFIRE)
5015 if (! DATA_REG_P (operands[0]))
5016 operands[0] = adjust_address (operands[0], HImode, 2);
5017 /* Do not delete a following tstl %0 insn; that would be incorrect. */
5018 CC_STATUS_INIT;
5019 if (INTVAL (operands[2]) == 0xffff)
5020 return "not%.w %0";
5021 return "eor%.w %2,%0";
5023 if (GET_CODE (operands[2]) == CONST_INT
5024 && (logval = exact_log2 (INTVAL (operands[2]) & 0xffffffff)) >= 0
5025 && (DATA_REG_P (operands[0])
5026 || offsettable_memref_p (operands[0])))
5028 if (DATA_REG_P (operands[0]))
5029 operands[1] = GEN_INT (logval);
5030 else
5032 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8));
5033 operands[1] = GEN_INT (logval % 8);
5035 CC_STATUS_INIT;
5036 return "bchg %1,%0";
5038 return "eor%.l %2,%0";
5041 /* Return the instruction that should be used for a call to address X,
5042 which is known to be in operand 0. */
5044 const char *
5045 output_call (rtx x)
5047 if (symbolic_operand (x, VOIDmode))
5048 return m68k_symbolic_call;
5049 else
5050 return "jsr %a0";
5053 /* Likewise sibling calls. */
5055 const char *
5056 output_sibcall (rtx x)
5058 if (symbolic_operand (x, VOIDmode))
5059 return m68k_symbolic_jump;
5060 else
5061 return "jmp %a0";
5064 static void
5065 m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
5066 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
5067 tree function)
5069 rtx this_slot, offset, addr, mem, tmp;
5070 rtx_insn *insn;
5072 /* Avoid clobbering the struct value reg by using the
5073 static chain reg as a temporary. */
5074 tmp = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
5076 /* Pretend to be a post-reload pass while generating rtl. */
5077 reload_completed = 1;
5079 /* The "this" pointer is stored at 4(%sp). */
5080 this_slot = gen_rtx_MEM (Pmode, plus_constant (Pmode,
5081 stack_pointer_rtx, 4));
5083 /* Add DELTA to THIS. */
5084 if (delta != 0)
5086 /* Make the offset a legitimate operand for memory addition. */
5087 offset = GEN_INT (delta);
5088 if ((delta < -8 || delta > 8)
5089 && (TARGET_COLDFIRE || USE_MOVQ (delta)))
5091 emit_move_insn (gen_rtx_REG (Pmode, D0_REG), offset);
5092 offset = gen_rtx_REG (Pmode, D0_REG);
5094 emit_insn (gen_add3_insn (copy_rtx (this_slot),
5095 copy_rtx (this_slot), offset));
5098 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */
5099 if (vcall_offset != 0)
5101 /* Set the static chain register to *THIS. */
5102 emit_move_insn (tmp, this_slot);
5103 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
5105 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */
5106 addr = plus_constant (Pmode, tmp, vcall_offset);
5107 if (!m68k_legitimate_address_p (Pmode, addr, true))
5109 emit_insn (gen_rtx_SET (tmp, addr));
5110 addr = tmp;
5113 /* Load the offset into %d0 and add it to THIS. */
5114 emit_move_insn (gen_rtx_REG (Pmode, D0_REG),
5115 gen_rtx_MEM (Pmode, addr));
5116 emit_insn (gen_add3_insn (copy_rtx (this_slot),
5117 copy_rtx (this_slot),
5118 gen_rtx_REG (Pmode, D0_REG)));
5121 /* Jump to the target function. Use a sibcall if direct jumps are
5122 allowed, otherwise load the address into a register first. */
5123 mem = DECL_RTL (function);
5124 if (!sibcall_operand (XEXP (mem, 0), VOIDmode))
5126 gcc_assert (flag_pic);
5128 if (!TARGET_SEP_DATA)
5130 /* Use the static chain register as a temporary (call-clobbered)
5131 GOT pointer for this function. We can use the static chain
5132 register because it isn't live on entry to the thunk. */
5133 SET_REGNO (pic_offset_table_rtx, STATIC_CHAIN_REGNUM);
5134 emit_insn (gen_load_got (pic_offset_table_rtx));
5136 legitimize_pic_address (XEXP (mem, 0), Pmode, tmp);
5137 mem = replace_equiv_address (mem, tmp);
5139 insn = emit_call_insn (gen_sibcall (mem, const0_rtx));
5140 SIBLING_CALL_P (insn) = 1;
5142 /* Run just enough of rest_of_compilation. */
5143 insn = get_insns ();
5144 split_all_insns_noflow ();
5145 final_start_function (insn, file, 1);
5146 final (insn, file, 1);
5147 final_end_function ();
5149 /* Clean up the vars set above. */
5150 reload_completed = 0;
5152 /* Restore the original PIC register. */
5153 if (flag_pic)
5154 SET_REGNO (pic_offset_table_rtx, PIC_REG);
5157 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
5159 static rtx
5160 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
5161 int incoming ATTRIBUTE_UNUSED)
5163 return gen_rtx_REG (Pmode, M68K_STRUCT_VALUE_REGNUM);
5166 /* Return nonzero if register old_reg can be renamed to register new_reg. */
5168 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
5169 unsigned int new_reg)
5172 /* Interrupt functions can only use registers that have already been
5173 saved by the prologue, even if they would normally be
5174 call-clobbered. */
5176 if ((m68k_get_function_kind (current_function_decl)
5177 == m68k_fk_interrupt_handler)
5178 && !df_regs_ever_live_p (new_reg))
5179 return 0;
5181 return 1;
5184 /* Implement TARGET_HARD_REGNO_NREGS.
5186 On the m68k, ordinary registers hold 32 bits worth;
5187 for the 68881 registers, a single register is always enough for
5188 anything that can be stored in them at all. */
5190 static unsigned int
5191 m68k_hard_regno_nregs (unsigned int regno, machine_mode mode)
5193 if (regno >= 16)
5194 return GET_MODE_NUNITS (mode);
5195 return CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD);
5198 /* Implement TARGET_HARD_REGNO_MODE_OK. On the 68000, we let the cpu
5199 registers can hold any mode, but restrict the 68881 registers to
5200 floating-point modes. */
5202 static bool
5203 m68k_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
5205 if (DATA_REGNO_P (regno))
5207 /* Data Registers, can hold aggregate if fits in. */
5208 if (regno + GET_MODE_SIZE (mode) / 4 <= 8)
5209 return true;
5211 else if (ADDRESS_REGNO_P (regno))
5213 if (regno + GET_MODE_SIZE (mode) / 4 <= 16)
5214 return true;
5216 else if (FP_REGNO_P (regno))
5218 /* FPU registers, hold float or complex float of long double or
5219 smaller. */
5220 if ((GET_MODE_CLASS (mode) == MODE_FLOAT
5221 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5222 && GET_MODE_UNIT_SIZE (mode) <= TARGET_FP_REG_SIZE)
5223 return true;
5225 return false;
5228 /* Implement TARGET_MODES_TIEABLE_P. */
5230 static bool
5231 m68k_modes_tieable_p (machine_mode mode1, machine_mode mode2)
5233 return (!TARGET_HARD_FLOAT
5234 || ((GET_MODE_CLASS (mode1) == MODE_FLOAT
5235 || GET_MODE_CLASS (mode1) == MODE_COMPLEX_FLOAT)
5236 == (GET_MODE_CLASS (mode2) == MODE_FLOAT
5237 || GET_MODE_CLASS (mode2) == MODE_COMPLEX_FLOAT)));
5240 /* Implement SECONDARY_RELOAD_CLASS. */
5242 enum reg_class
5243 m68k_secondary_reload_class (enum reg_class rclass,
5244 machine_mode mode, rtx x)
5246 int regno;
5248 regno = true_regnum (x);
5250 /* If one operand of a movqi is an address register, the other
5251 operand must be a general register or constant. Other types
5252 of operand must be reloaded through a data register. */
5253 if (GET_MODE_SIZE (mode) == 1
5254 && reg_classes_intersect_p (rclass, ADDR_REGS)
5255 && !(INT_REGNO_P (regno) || CONSTANT_P (x)))
5256 return DATA_REGS;
5258 /* PC-relative addresses must be loaded into an address register first. */
5259 if (TARGET_PCREL
5260 && !reg_class_subset_p (rclass, ADDR_REGS)
5261 && symbolic_operand (x, VOIDmode))
5262 return ADDR_REGS;
5264 return NO_REGS;
5267 /* Implement PREFERRED_RELOAD_CLASS. */
5269 enum reg_class
5270 m68k_preferred_reload_class (rtx x, enum reg_class rclass)
5272 enum reg_class secondary_class;
5274 /* If RCLASS might need a secondary reload, try restricting it to
5275 a class that doesn't. */
5276 secondary_class = m68k_secondary_reload_class (rclass, GET_MODE (x), x);
5277 if (secondary_class != NO_REGS
5278 && reg_class_subset_p (secondary_class, rclass))
5279 return secondary_class;
5281 /* Prefer to use moveq for in-range constants. */
5282 if (GET_CODE (x) == CONST_INT
5283 && reg_class_subset_p (DATA_REGS, rclass)
5284 && IN_RANGE (INTVAL (x), -0x80, 0x7f))
5285 return DATA_REGS;
5287 /* ??? Do we really need this now? */
5288 if (GET_CODE (x) == CONST_DOUBLE
5289 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
5291 if (TARGET_HARD_FLOAT && reg_class_subset_p (FP_REGS, rclass))
5292 return FP_REGS;
5294 return NO_REGS;
5297 return rclass;
5300 /* Return floating point values in a 68881 register. This makes 68881 code
5301 a little bit faster. It also makes -msoft-float code incompatible with
5302 hard-float code, so people have to be careful not to mix the two.
5303 For ColdFire it was decided the ABI incompatibility is undesirable.
5304 If there is need for a hard-float ABI it is probably worth doing it
5305 properly and also passing function arguments in FP registers. */
5307 m68k_libcall_value (machine_mode mode)
5309 switch (mode) {
5310 case E_SFmode:
5311 case E_DFmode:
5312 case E_XFmode:
5313 if (TARGET_68881)
5314 return gen_rtx_REG (mode, FP0_REG);
5315 break;
5316 default:
5317 break;
5320 return gen_rtx_REG (mode, m68k_libcall_value_in_a0_p ? A0_REG : D0_REG);
5323 /* Location in which function value is returned.
5324 NOTE: Due to differences in ABIs, don't call this function directly,
5325 use FUNCTION_VALUE instead. */
5327 m68k_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
5329 machine_mode mode;
5331 mode = TYPE_MODE (valtype);
5332 switch (mode) {
5333 case E_SFmode:
5334 case E_DFmode:
5335 case E_XFmode:
5336 if (TARGET_68881)
5337 return gen_rtx_REG (mode, FP0_REG);
5338 break;
5339 default:
5340 break;
5343 /* If the function returns a pointer, push that into %a0. */
5344 if (func && POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func))))
5345 /* For compatibility with the large body of existing code which
5346 does not always properly declare external functions returning
5347 pointer types, the m68k/SVR4 convention is to copy the value
5348 returned for pointer functions from a0 to d0 in the function
5349 epilogue, so that callers that have neglected to properly
5350 declare the callee can still find the correct return value in
5351 d0. */
5352 return gen_rtx_PARALLEL
5353 (mode,
5354 gen_rtvec (2,
5355 gen_rtx_EXPR_LIST (VOIDmode,
5356 gen_rtx_REG (mode, A0_REG),
5357 const0_rtx),
5358 gen_rtx_EXPR_LIST (VOIDmode,
5359 gen_rtx_REG (mode, D0_REG),
5360 const0_rtx)));
5361 else if (POINTER_TYPE_P (valtype))
5362 return gen_rtx_REG (mode, A0_REG);
5363 else
5364 return gen_rtx_REG (mode, D0_REG);
5367 /* Worker function for TARGET_RETURN_IN_MEMORY. */
5368 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT
5369 static bool
5370 m68k_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
5372 machine_mode mode = TYPE_MODE (type);
5374 if (mode == BLKmode)
5375 return true;
5377 /* If TYPE's known alignment is less than the alignment of MODE that
5378 would contain the structure, then return in memory. We need to
5379 do so to maintain the compatibility between code compiled with
5380 -mstrict-align and that compiled with -mno-strict-align. */
5381 if (AGGREGATE_TYPE_P (type)
5382 && TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (mode))
5383 return true;
5385 return false;
5387 #endif
5389 /* CPU to schedule the program for. */
5390 enum attr_cpu m68k_sched_cpu;
5392 /* MAC to schedule the program for. */
5393 enum attr_mac m68k_sched_mac;
5395 /* Operand type. */
5396 enum attr_op_type
5398 /* No operand. */
5399 OP_TYPE_NONE,
5401 /* Integer register. */
5402 OP_TYPE_RN,
5404 /* FP register. */
5405 OP_TYPE_FPN,
5407 /* Implicit mem reference (e.g. stack). */
5408 OP_TYPE_MEM1,
5410 /* Memory without offset or indexing. EA modes 2, 3 and 4. */
5411 OP_TYPE_MEM234,
5413 /* Memory with offset but without indexing. EA mode 5. */
5414 OP_TYPE_MEM5,
5416 /* Memory with indexing. EA mode 6. */
5417 OP_TYPE_MEM6,
5419 /* Memory referenced by absolute address. EA mode 7. */
5420 OP_TYPE_MEM7,
5422 /* Immediate operand that doesn't require extension word. */
5423 OP_TYPE_IMM_Q,
5425 /* Immediate 16 bit operand. */
5426 OP_TYPE_IMM_W,
5428 /* Immediate 32 bit operand. */
5429 OP_TYPE_IMM_L
5432 /* Return type of memory ADDR_RTX refers to. */
5433 static enum attr_op_type
5434 sched_address_type (machine_mode mode, rtx addr_rtx)
5436 struct m68k_address address;
5438 if (symbolic_operand (addr_rtx, VOIDmode))
5439 return OP_TYPE_MEM7;
5441 if (!m68k_decompose_address (mode, addr_rtx,
5442 reload_completed, &address))
5444 gcc_assert (!reload_completed);
5445 /* Reload will likely fix the address to be in the register. */
5446 return OP_TYPE_MEM234;
5449 if (address.scale != 0)
5450 return OP_TYPE_MEM6;
5452 if (address.base != NULL_RTX)
5454 if (address.offset == NULL_RTX)
5455 return OP_TYPE_MEM234;
5457 return OP_TYPE_MEM5;
5460 gcc_assert (address.offset != NULL_RTX);
5462 return OP_TYPE_MEM7;
5465 /* Return X or Y (depending on OPX_P) operand of INSN. */
5466 static rtx
5467 sched_get_operand (rtx_insn *insn, bool opx_p)
5469 int i;
5471 if (recog_memoized (insn) < 0)
5472 gcc_unreachable ();
5474 extract_constrain_insn_cached (insn);
5476 if (opx_p)
5477 i = get_attr_opx (insn);
5478 else
5479 i = get_attr_opy (insn);
5481 if (i >= recog_data.n_operands)
5482 return NULL;
5484 return recog_data.operand[i];
5487 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P).
5488 If ADDRESS_P is true, return type of memory location operand refers to. */
5489 static enum attr_op_type
5490 sched_attr_op_type (rtx_insn *insn, bool opx_p, bool address_p)
5492 rtx op;
5494 op = sched_get_operand (insn, opx_p);
5496 if (op == NULL)
5498 gcc_assert (!reload_completed);
5499 return OP_TYPE_RN;
5502 if (address_p)
5503 return sched_address_type (QImode, op);
5505 if (memory_operand (op, VOIDmode))
5506 return sched_address_type (GET_MODE (op), XEXP (op, 0));
5508 if (register_operand (op, VOIDmode))
5510 if ((!reload_completed && FLOAT_MODE_P (GET_MODE (op)))
5511 || (reload_completed && FP_REG_P (op)))
5512 return OP_TYPE_FPN;
5514 return OP_TYPE_RN;
5517 if (GET_CODE (op) == CONST_INT)
5519 int ival;
5521 ival = INTVAL (op);
5523 /* Check for quick constants. */
5524 switch (get_attr_type (insn))
5526 case TYPE_ALUQ_L:
5527 if (IN_RANGE (ival, 1, 8) || IN_RANGE (ival, -8, -1))
5528 return OP_TYPE_IMM_Q;
5530 gcc_assert (!reload_completed);
5531 break;
5533 case TYPE_MOVEQ_L:
5534 if (USE_MOVQ (ival))
5535 return OP_TYPE_IMM_Q;
5537 gcc_assert (!reload_completed);
5538 break;
5540 case TYPE_MOV3Q_L:
5541 if (valid_mov3q_const (ival))
5542 return OP_TYPE_IMM_Q;
5544 gcc_assert (!reload_completed);
5545 break;
5547 default:
5548 break;
5551 if (IN_RANGE (ival, -0x8000, 0x7fff))
5552 return OP_TYPE_IMM_W;
5554 return OP_TYPE_IMM_L;
5557 if (GET_CODE (op) == CONST_DOUBLE)
5559 switch (GET_MODE (op))
5561 case E_SFmode:
5562 return OP_TYPE_IMM_W;
5564 case E_VOIDmode:
5565 case E_DFmode:
5566 return OP_TYPE_IMM_L;
5568 default:
5569 gcc_unreachable ();
5573 if (GET_CODE (op) == CONST
5574 || symbolic_operand (op, VOIDmode)
5575 || LABEL_P (op))
5577 switch (GET_MODE (op))
5579 case E_QImode:
5580 return OP_TYPE_IMM_Q;
5582 case E_HImode:
5583 return OP_TYPE_IMM_W;
5585 case E_SImode:
5586 return OP_TYPE_IMM_L;
5588 default:
5589 if (symbolic_operand (m68k_unwrap_symbol (op, false), VOIDmode))
5590 /* Just a guess. */
5591 return OP_TYPE_IMM_W;
5593 return OP_TYPE_IMM_L;
5597 gcc_assert (!reload_completed);
5599 if (FLOAT_MODE_P (GET_MODE (op)))
5600 return OP_TYPE_FPN;
5602 return OP_TYPE_RN;
5605 /* Implement opx_type attribute.
5606 Return type of INSN's operand X.
5607 If ADDRESS_P is true, return type of memory location operand refers to. */
5608 enum attr_opx_type
5609 m68k_sched_attr_opx_type (rtx_insn *insn, int address_p)
5611 switch (sched_attr_op_type (insn, true, address_p != 0))
5613 case OP_TYPE_RN:
5614 return OPX_TYPE_RN;
5616 case OP_TYPE_FPN:
5617 return OPX_TYPE_FPN;
5619 case OP_TYPE_MEM1:
5620 return OPX_TYPE_MEM1;
5622 case OP_TYPE_MEM234:
5623 return OPX_TYPE_MEM234;
5625 case OP_TYPE_MEM5:
5626 return OPX_TYPE_MEM5;
5628 case OP_TYPE_MEM6:
5629 return OPX_TYPE_MEM6;
5631 case OP_TYPE_MEM7:
5632 return OPX_TYPE_MEM7;
5634 case OP_TYPE_IMM_Q:
5635 return OPX_TYPE_IMM_Q;
5637 case OP_TYPE_IMM_W:
5638 return OPX_TYPE_IMM_W;
5640 case OP_TYPE_IMM_L:
5641 return OPX_TYPE_IMM_L;
5643 default:
5644 gcc_unreachable ();
5648 /* Implement opy_type attribute.
5649 Return type of INSN's operand Y.
5650 If ADDRESS_P is true, return type of memory location operand refers to. */
5651 enum attr_opy_type
5652 m68k_sched_attr_opy_type (rtx_insn *insn, int address_p)
5654 switch (sched_attr_op_type (insn, false, address_p != 0))
5656 case OP_TYPE_RN:
5657 return OPY_TYPE_RN;
5659 case OP_TYPE_FPN:
5660 return OPY_TYPE_FPN;
5662 case OP_TYPE_MEM1:
5663 return OPY_TYPE_MEM1;
5665 case OP_TYPE_MEM234:
5666 return OPY_TYPE_MEM234;
5668 case OP_TYPE_MEM5:
5669 return OPY_TYPE_MEM5;
5671 case OP_TYPE_MEM6:
5672 return OPY_TYPE_MEM6;
5674 case OP_TYPE_MEM7:
5675 return OPY_TYPE_MEM7;
5677 case OP_TYPE_IMM_Q:
5678 return OPY_TYPE_IMM_Q;
5680 case OP_TYPE_IMM_W:
5681 return OPY_TYPE_IMM_W;
5683 case OP_TYPE_IMM_L:
5684 return OPY_TYPE_IMM_L;
5686 default:
5687 gcc_unreachable ();
5691 /* Return size of INSN as int. */
5692 static int
5693 sched_get_attr_size_int (rtx_insn *insn)
5695 int size;
5697 switch (get_attr_type (insn))
5699 case TYPE_IGNORE:
5700 /* There should be no references to m68k_sched_attr_size for 'ignore'
5701 instructions. */
5702 gcc_unreachable ();
5703 return 0;
5705 case TYPE_MUL_L:
5706 size = 2;
5707 break;
5709 default:
5710 size = 1;
5711 break;
5714 switch (get_attr_opx_type (insn))
5716 case OPX_TYPE_NONE:
5717 case OPX_TYPE_RN:
5718 case OPX_TYPE_FPN:
5719 case OPX_TYPE_MEM1:
5720 case OPX_TYPE_MEM234:
5721 case OPY_TYPE_IMM_Q:
5722 break;
5724 case OPX_TYPE_MEM5:
5725 case OPX_TYPE_MEM6:
5726 /* Here we assume that most absolute references are short. */
5727 case OPX_TYPE_MEM7:
5728 case OPY_TYPE_IMM_W:
5729 ++size;
5730 break;
5732 case OPY_TYPE_IMM_L:
5733 size += 2;
5734 break;
5736 default:
5737 gcc_unreachable ();
5740 switch (get_attr_opy_type (insn))
5742 case OPY_TYPE_NONE:
5743 case OPY_TYPE_RN:
5744 case OPY_TYPE_FPN:
5745 case OPY_TYPE_MEM1:
5746 case OPY_TYPE_MEM234:
5747 case OPY_TYPE_IMM_Q:
5748 break;
5750 case OPY_TYPE_MEM5:
5751 case OPY_TYPE_MEM6:
5752 /* Here we assume that most absolute references are short. */
5753 case OPY_TYPE_MEM7:
5754 case OPY_TYPE_IMM_W:
5755 ++size;
5756 break;
5758 case OPY_TYPE_IMM_L:
5759 size += 2;
5760 break;
5762 default:
5763 gcc_unreachable ();
5766 if (size > 3)
5768 gcc_assert (!reload_completed);
5770 size = 3;
5773 return size;
5776 /* Return size of INSN as attribute enum value. */
5777 enum attr_size
5778 m68k_sched_attr_size (rtx_insn *insn)
5780 switch (sched_get_attr_size_int (insn))
5782 case 1:
5783 return SIZE_1;
5785 case 2:
5786 return SIZE_2;
5788 case 3:
5789 return SIZE_3;
5791 default:
5792 gcc_unreachable ();
5796 /* Return operand X or Y (depending on OPX_P) of INSN,
5797 if it is a MEM, or NULL overwise. */
5798 static enum attr_op_type
5799 sched_get_opxy_mem_type (rtx_insn *insn, bool opx_p)
5801 if (opx_p)
5803 switch (get_attr_opx_type (insn))
5805 case OPX_TYPE_NONE:
5806 case OPX_TYPE_RN:
5807 case OPX_TYPE_FPN:
5808 case OPX_TYPE_IMM_Q:
5809 case OPX_TYPE_IMM_W:
5810 case OPX_TYPE_IMM_L:
5811 return OP_TYPE_RN;
5813 case OPX_TYPE_MEM1:
5814 case OPX_TYPE_MEM234:
5815 case OPX_TYPE_MEM5:
5816 case OPX_TYPE_MEM7:
5817 return OP_TYPE_MEM1;
5819 case OPX_TYPE_MEM6:
5820 return OP_TYPE_MEM6;
5822 default:
5823 gcc_unreachable ();
5826 else
5828 switch (get_attr_opy_type (insn))
5830 case OPY_TYPE_NONE:
5831 case OPY_TYPE_RN:
5832 case OPY_TYPE_FPN:
5833 case OPY_TYPE_IMM_Q:
5834 case OPY_TYPE_IMM_W:
5835 case OPY_TYPE_IMM_L:
5836 return OP_TYPE_RN;
5838 case OPY_TYPE_MEM1:
5839 case OPY_TYPE_MEM234:
5840 case OPY_TYPE_MEM5:
5841 case OPY_TYPE_MEM7:
5842 return OP_TYPE_MEM1;
5844 case OPY_TYPE_MEM6:
5845 return OP_TYPE_MEM6;
5847 default:
5848 gcc_unreachable ();
5853 /* Implement op_mem attribute. */
5854 enum attr_op_mem
5855 m68k_sched_attr_op_mem (rtx_insn *insn)
5857 enum attr_op_type opx;
5858 enum attr_op_type opy;
5860 opx = sched_get_opxy_mem_type (insn, true);
5861 opy = sched_get_opxy_mem_type (insn, false);
5863 if (opy == OP_TYPE_RN && opx == OP_TYPE_RN)
5864 return OP_MEM_00;
5866 if (opy == OP_TYPE_RN && opx == OP_TYPE_MEM1)
5868 switch (get_attr_opx_access (insn))
5870 case OPX_ACCESS_R:
5871 return OP_MEM_10;
5873 case OPX_ACCESS_W:
5874 return OP_MEM_01;
5876 case OPX_ACCESS_RW:
5877 return OP_MEM_11;
5879 default:
5880 gcc_unreachable ();
5884 if (opy == OP_TYPE_RN && opx == OP_TYPE_MEM6)
5886 switch (get_attr_opx_access (insn))
5888 case OPX_ACCESS_R:
5889 return OP_MEM_I0;
5891 case OPX_ACCESS_W:
5892 return OP_MEM_0I;
5894 case OPX_ACCESS_RW:
5895 return OP_MEM_I1;
5897 default:
5898 gcc_unreachable ();
5902 if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_RN)
5903 return OP_MEM_10;
5905 if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_MEM1)
5907 switch (get_attr_opx_access (insn))
5909 case OPX_ACCESS_W:
5910 return OP_MEM_11;
5912 default:
5913 gcc_assert (!reload_completed);
5914 return OP_MEM_11;
5918 if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_MEM6)
5920 switch (get_attr_opx_access (insn))
5922 case OPX_ACCESS_W:
5923 return OP_MEM_1I;
5925 default:
5926 gcc_assert (!reload_completed);
5927 return OP_MEM_1I;
5931 if (opy == OP_TYPE_MEM6 && opx == OP_TYPE_RN)
5932 return OP_MEM_I0;
5934 if (opy == OP_TYPE_MEM6 && opx == OP_TYPE_MEM1)
5936 switch (get_attr_opx_access (insn))
5938 case OPX_ACCESS_W:
5939 return OP_MEM_I1;
5941 default:
5942 gcc_assert (!reload_completed);
5943 return OP_MEM_I1;
5947 gcc_assert (opy == OP_TYPE_MEM6 && opx == OP_TYPE_MEM6);
5948 gcc_assert (!reload_completed);
5949 return OP_MEM_I1;
5952 /* Data for ColdFire V4 index bypass.
5953 Producer modifies register that is used as index in consumer with
5954 specified scale. */
5955 static struct
5957 /* Producer instruction. */
5958 rtx pro;
5960 /* Consumer instruction. */
5961 rtx con;
5963 /* Scale of indexed memory access within consumer.
5964 Or zero if bypass should not be effective at the moment. */
5965 int scale;
5966 } sched_cfv4_bypass_data;
5968 /* An empty state that is used in m68k_sched_adjust_cost. */
5969 static state_t sched_adjust_cost_state;
5971 /* Implement adjust_cost scheduler hook.
5972 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */
5973 static int
5974 m68k_sched_adjust_cost (rtx_insn *insn, int, rtx_insn *def_insn, int cost,
5975 unsigned int)
5977 int delay;
5979 if (recog_memoized (def_insn) < 0
5980 || recog_memoized (insn) < 0)
5981 return cost;
5983 if (sched_cfv4_bypass_data.scale == 1)
5984 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */
5986 /* haifa-sched.c: insn_cost () calls bypass_p () just before
5987 targetm.sched.adjust_cost (). Hence, we can be relatively sure
5988 that the data in sched_cfv4_bypass_data is up to date. */
5989 gcc_assert (sched_cfv4_bypass_data.pro == def_insn
5990 && sched_cfv4_bypass_data.con == insn);
5992 if (cost < 3)
5993 cost = 3;
5995 sched_cfv4_bypass_data.pro = NULL;
5996 sched_cfv4_bypass_data.con = NULL;
5997 sched_cfv4_bypass_data.scale = 0;
5999 else
6000 gcc_assert (sched_cfv4_bypass_data.pro == NULL
6001 && sched_cfv4_bypass_data.con == NULL
6002 && sched_cfv4_bypass_data.scale == 0);
6004 /* Don't try to issue INSN earlier than DFA permits.
6005 This is especially useful for instructions that write to memory,
6006 as their true dependence (default) latency is better to be set to 0
6007 to workaround alias analysis limitations.
6008 This is, in fact, a machine independent tweak, so, probably,
6009 it should be moved to haifa-sched.c: insn_cost (). */
6010 delay = min_insn_conflict_delay (sched_adjust_cost_state, def_insn, insn);
6011 if (delay > cost)
6012 cost = delay;
6014 return cost;
6017 /* Return maximal number of insns that can be scheduled on a single cycle. */
6018 static int
6019 m68k_sched_issue_rate (void)
6021 switch (m68k_sched_cpu)
6023 case CPU_CFV1:
6024 case CPU_CFV2:
6025 case CPU_CFV3:
6026 return 1;
6028 case CPU_CFV4:
6029 return 2;
6031 default:
6032 gcc_unreachable ();
6033 return 0;
6037 /* Maximal length of instruction for current CPU.
6038 E.g. it is 3 for any ColdFire core. */
6039 static int max_insn_size;
6041 /* Data to model instruction buffer of CPU. */
6042 struct _sched_ib
6044 /* True if instruction buffer model is modeled for current CPU. */
6045 bool enabled_p;
6047 /* Size of the instruction buffer in words. */
6048 int size;
6050 /* Number of filled words in the instruction buffer. */
6051 int filled;
6053 /* Additional information about instruction buffer for CPUs that have
6054 a buffer of instruction records, rather then a plain buffer
6055 of instruction words. */
6056 struct _sched_ib_records
6058 /* Size of buffer in records. */
6059 int n_insns;
6061 /* Array to hold data on adjustments made to the size of the buffer. */
6062 int *adjust;
6064 /* Index of the above array. */
6065 int adjust_index;
6066 } records;
6068 /* An insn that reserves (marks empty) one word in the instruction buffer. */
6069 rtx insn;
6072 static struct _sched_ib sched_ib;
6074 /* ID of memory unit. */
6075 static int sched_mem_unit_code;
6077 /* Implementation of the targetm.sched.variable_issue () hook.
6078 It is called after INSN was issued. It returns the number of insns
6079 that can possibly get scheduled on the current cycle.
6080 It is used here to determine the effect of INSN on the instruction
6081 buffer. */
6082 static int
6083 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED,
6084 int sched_verbose ATTRIBUTE_UNUSED,
6085 rtx_insn *insn, int can_issue_more)
6087 int insn_size;
6089 if (recog_memoized (insn) >= 0 && get_attr_type (insn) != TYPE_IGNORE)
6091 switch (m68k_sched_cpu)
6093 case CPU_CFV1:
6094 case CPU_CFV2:
6095 insn_size = sched_get_attr_size_int (insn);
6096 break;
6098 case CPU_CFV3:
6099 insn_size = sched_get_attr_size_int (insn);
6101 /* ColdFire V3 and V4 cores have instruction buffers that can
6102 accumulate up to 8 instructions regardless of instructions'
6103 sizes. So we should take care not to "prefetch" 24 one-word
6104 or 12 two-words instructions.
6105 To model this behavior we temporarily decrease size of the
6106 buffer by (max_insn_size - insn_size) for next 7 instructions. */
6108 int adjust;
6110 adjust = max_insn_size - insn_size;
6111 sched_ib.size -= adjust;
6113 if (sched_ib.filled > sched_ib.size)
6114 sched_ib.filled = sched_ib.size;
6116 sched_ib.records.adjust[sched_ib.records.adjust_index] = adjust;
6119 ++sched_ib.records.adjust_index;
6120 if (sched_ib.records.adjust_index == sched_ib.records.n_insns)
6121 sched_ib.records.adjust_index = 0;
6123 /* Undo adjustment we did 7 instructions ago. */
6124 sched_ib.size
6125 += sched_ib.records.adjust[sched_ib.records.adjust_index];
6127 break;
6129 case CPU_CFV4:
6130 gcc_assert (!sched_ib.enabled_p);
6131 insn_size = 0;
6132 break;
6134 default:
6135 gcc_unreachable ();
6138 if (insn_size > sched_ib.filled)
6139 /* Scheduling for register pressure does not always take DFA into
6140 account. Workaround instruction buffer not being filled enough. */
6142 gcc_assert (sched_pressure == SCHED_PRESSURE_WEIGHTED);
6143 insn_size = sched_ib.filled;
6146 --can_issue_more;
6148 else if (GET_CODE (PATTERN (insn)) == ASM_INPUT
6149 || asm_noperands (PATTERN (insn)) >= 0)
6150 insn_size = sched_ib.filled;
6151 else
6152 insn_size = 0;
6154 sched_ib.filled -= insn_size;
6156 return can_issue_more;
6159 /* Return how many instructions should scheduler lookahead to choose the
6160 best one. */
6161 static int
6162 m68k_sched_first_cycle_multipass_dfa_lookahead (void)
6164 return m68k_sched_issue_rate () - 1;
6167 /* Implementation of targetm.sched.init_global () hook.
6168 It is invoked once per scheduling pass and is used here
6169 to initialize scheduler constants. */
6170 static void
6171 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED,
6172 int sched_verbose ATTRIBUTE_UNUSED,
6173 int n_insns ATTRIBUTE_UNUSED)
6175 /* Check that all instructions have DFA reservations and
6176 that all instructions can be issued from a clean state. */
6177 if (flag_checking)
6179 rtx_insn *insn;
6180 state_t state;
6182 state = alloca (state_size ());
6184 for (insn = get_insns (); insn != NULL; insn = NEXT_INSN (insn))
6186 if (INSN_P (insn) && recog_memoized (insn) >= 0)
6188 gcc_assert (insn_has_dfa_reservation_p (insn));
6190 state_reset (state);
6191 if (state_transition (state, insn) >= 0)
6192 gcc_unreachable ();
6197 /* Setup target cpu. */
6199 /* ColdFire V4 has a set of features to keep its instruction buffer full
6200 (e.g., a separate memory bus for instructions) and, hence, we do not model
6201 buffer for this CPU. */
6202 sched_ib.enabled_p = (m68k_sched_cpu != CPU_CFV4);
6204 switch (m68k_sched_cpu)
6206 case CPU_CFV4:
6207 sched_ib.filled = 0;
6209 /* FALLTHRU */
6211 case CPU_CFV1:
6212 case CPU_CFV2:
6213 max_insn_size = 3;
6214 sched_ib.records.n_insns = 0;
6215 sched_ib.records.adjust = NULL;
6216 break;
6218 case CPU_CFV3:
6219 max_insn_size = 3;
6220 sched_ib.records.n_insns = 8;
6221 sched_ib.records.adjust = XNEWVEC (int, sched_ib.records.n_insns);
6222 break;
6224 default:
6225 gcc_unreachable ();
6228 sched_mem_unit_code = get_cpu_unit_code ("cf_mem1");
6230 sched_adjust_cost_state = xmalloc (state_size ());
6231 state_reset (sched_adjust_cost_state);
6233 start_sequence ();
6234 emit_insn (gen_ib ());
6235 sched_ib.insn = get_insns ();
6236 end_sequence ();
6239 /* Scheduling pass is now finished. Free/reset static variables. */
6240 static void
6241 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
6242 int verbose ATTRIBUTE_UNUSED)
6244 sched_ib.insn = NULL;
6246 free (sched_adjust_cost_state);
6247 sched_adjust_cost_state = NULL;
6249 sched_mem_unit_code = 0;
6251 free (sched_ib.records.adjust);
6252 sched_ib.records.adjust = NULL;
6253 sched_ib.records.n_insns = 0;
6254 max_insn_size = 0;
6257 /* Implementation of targetm.sched.init () hook.
6258 It is invoked each time scheduler starts on the new block (basic block or
6259 extended basic block). */
6260 static void
6261 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED,
6262 int sched_verbose ATTRIBUTE_UNUSED,
6263 int n_insns ATTRIBUTE_UNUSED)
6265 switch (m68k_sched_cpu)
6267 case CPU_CFV1:
6268 case CPU_CFV2:
6269 sched_ib.size = 6;
6270 break;
6272 case CPU_CFV3:
6273 sched_ib.size = sched_ib.records.n_insns * max_insn_size;
6275 memset (sched_ib.records.adjust, 0,
6276 sched_ib.records.n_insns * sizeof (*sched_ib.records.adjust));
6277 sched_ib.records.adjust_index = 0;
6278 break;
6280 case CPU_CFV4:
6281 gcc_assert (!sched_ib.enabled_p);
6282 sched_ib.size = 0;
6283 break;
6285 default:
6286 gcc_unreachable ();
6289 if (sched_ib.enabled_p)
6290 /* haifa-sched.c: schedule_block () calls advance_cycle () just before
6291 the first cycle. Workaround that. */
6292 sched_ib.filled = -2;
6295 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook.
6296 It is invoked just before current cycle finishes and is used here
6297 to track if instruction buffer got its two words this cycle. */
6298 static void
6299 m68k_sched_dfa_pre_advance_cycle (void)
6301 if (!sched_ib.enabled_p)
6302 return;
6304 if (!cpu_unit_reservation_p (curr_state, sched_mem_unit_code))
6306 sched_ib.filled += 2;
6308 if (sched_ib.filled > sched_ib.size)
6309 sched_ib.filled = sched_ib.size;
6313 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook.
6314 It is invoked just after new cycle begins and is used here
6315 to setup number of filled words in the instruction buffer so that
6316 instructions which won't have all their words prefetched would be
6317 stalled for a cycle. */
6318 static void
6319 m68k_sched_dfa_post_advance_cycle (void)
6321 int i;
6323 if (!sched_ib.enabled_p)
6324 return;
6326 /* Setup number of prefetched instruction words in the instruction
6327 buffer. */
6328 i = max_insn_size - sched_ib.filled;
6330 while (--i >= 0)
6332 if (state_transition (curr_state, sched_ib.insn) >= 0)
6333 /* Pick up scheduler state. */
6334 ++sched_ib.filled;
6338 /* Return X or Y (depending on OPX_P) operand of INSN,
6339 if it is an integer register, or NULL overwise. */
6340 static rtx
6341 sched_get_reg_operand (rtx_insn *insn, bool opx_p)
6343 rtx op = NULL;
6345 if (opx_p)
6347 if (get_attr_opx_type (insn) == OPX_TYPE_RN)
6349 op = sched_get_operand (insn, true);
6350 gcc_assert (op != NULL);
6352 if (!reload_completed && !REG_P (op))
6353 return NULL;
6356 else
6358 if (get_attr_opy_type (insn) == OPY_TYPE_RN)
6360 op = sched_get_operand (insn, false);
6361 gcc_assert (op != NULL);
6363 if (!reload_completed && !REG_P (op))
6364 return NULL;
6368 return op;
6371 /* Return true, if X or Y (depending on OPX_P) operand of INSN
6372 is a MEM. */
6373 static bool
6374 sched_mem_operand_p (rtx_insn *insn, bool opx_p)
6376 switch (sched_get_opxy_mem_type (insn, opx_p))
6378 case OP_TYPE_MEM1:
6379 case OP_TYPE_MEM6:
6380 return true;
6382 default:
6383 return false;
6387 /* Return X or Y (depending on OPX_P) operand of INSN,
6388 if it is a MEM, or NULL overwise. */
6389 static rtx
6390 sched_get_mem_operand (rtx_insn *insn, bool must_read_p, bool must_write_p)
6392 bool opx_p;
6393 bool opy_p;
6395 opx_p = false;
6396 opy_p = false;
6398 if (must_read_p)
6400 opx_p = true;
6401 opy_p = true;
6404 if (must_write_p)
6406 opx_p = true;
6407 opy_p = false;
6410 if (opy_p && sched_mem_operand_p (insn, false))
6411 return sched_get_operand (insn, false);
6413 if (opx_p && sched_mem_operand_p (insn, true))
6414 return sched_get_operand (insn, true);
6416 gcc_unreachable ();
6417 return NULL;
6420 /* Return non-zero if PRO modifies register used as part of
6421 address in CON. */
6423 m68k_sched_address_bypass_p (rtx_insn *pro, rtx_insn *con)
6425 rtx pro_x;
6426 rtx con_mem_read;
6428 pro_x = sched_get_reg_operand (pro, true);
6429 if (pro_x == NULL)
6430 return 0;
6432 con_mem_read = sched_get_mem_operand (con, true, false);
6433 gcc_assert (con_mem_read != NULL);
6435 if (reg_mentioned_p (pro_x, con_mem_read))
6436 return 1;
6438 return 0;
6441 /* Helper function for m68k_sched_indexed_address_bypass_p.
6442 if PRO modifies register used as index in CON,
6443 return scale of indexed memory access in CON. Return zero overwise. */
6444 static int
6445 sched_get_indexed_address_scale (rtx_insn *pro, rtx_insn *con)
6447 rtx reg;
6448 rtx mem;
6449 struct m68k_address address;
6451 reg = sched_get_reg_operand (pro, true);
6452 if (reg == NULL)
6453 return 0;
6455 mem = sched_get_mem_operand (con, true, false);
6456 gcc_assert (mem != NULL && MEM_P (mem));
6458 if (!m68k_decompose_address (GET_MODE (mem), XEXP (mem, 0), reload_completed,
6459 &address))
6460 gcc_unreachable ();
6462 if (REGNO (reg) == REGNO (address.index))
6464 gcc_assert (address.scale != 0);
6465 return address.scale;
6468 return 0;
6471 /* Return non-zero if PRO modifies register used
6472 as index with scale 2 or 4 in CON. */
6474 m68k_sched_indexed_address_bypass_p (rtx_insn *pro, rtx_insn *con)
6476 gcc_assert (sched_cfv4_bypass_data.pro == NULL
6477 && sched_cfv4_bypass_data.con == NULL
6478 && sched_cfv4_bypass_data.scale == 0);
6480 switch (sched_get_indexed_address_scale (pro, con))
6482 case 1:
6483 /* We can't have a variable latency bypass, so
6484 remember to adjust the insn cost in adjust_cost hook. */
6485 sched_cfv4_bypass_data.pro = pro;
6486 sched_cfv4_bypass_data.con = con;
6487 sched_cfv4_bypass_data.scale = 1;
6488 return 0;
6490 case 2:
6491 case 4:
6492 return 1;
6494 default:
6495 return 0;
6499 /* We generate a two-instructions program at M_TRAMP :
6500 movea.l &CHAIN_VALUE,%a0
6501 jmp FNADDR
6502 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */
6504 static void
6505 m68k_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
6507 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
6508 rtx mem;
6510 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM));
6512 mem = adjust_address (m_tramp, HImode, 0);
6513 emit_move_insn (mem, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM-8) << 9)));
6514 mem = adjust_address (m_tramp, SImode, 2);
6515 emit_move_insn (mem, chain_value);
6517 mem = adjust_address (m_tramp, HImode, 6);
6518 emit_move_insn (mem, GEN_INT(0x4EF9));
6519 mem = adjust_address (m_tramp, SImode, 8);
6520 emit_move_insn (mem, fnaddr);
6522 FINALIZE_TRAMPOLINE (XEXP (m_tramp, 0));
6525 /* On the 68000, the RTS insn cannot pop anything.
6526 On the 68010, the RTD insn may be used to pop them if the number
6527 of args is fixed, but if the number is variable then the caller
6528 must pop them all. RTD can't be used for library calls now
6529 because the library is compiled with the Unix compiler.
6530 Use of RTD is a selectable option, since it is incompatible with
6531 standard Unix calling sequences. If the option is not selected,
6532 the caller must always pop the args. */
6534 static int
6535 m68k_return_pops_args (tree fundecl, tree funtype, int size)
6537 return ((TARGET_RTD
6538 && (!fundecl
6539 || TREE_CODE (fundecl) != IDENTIFIER_NODE)
6540 && (!stdarg_p (funtype)))
6541 ? size : 0);
6544 /* Make sure everything's fine if we *don't* have a given processor.
6545 This assumes that putting a register in fixed_regs will keep the
6546 compiler's mitts completely off it. We don't bother to zero it out
6547 of register classes. */
6549 static void
6550 m68k_conditional_register_usage (void)
6552 int i;
6553 HARD_REG_SET x;
6554 if (!TARGET_HARD_FLOAT)
6556 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]);
6557 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
6558 if (TEST_HARD_REG_BIT (x, i))
6559 fixed_regs[i] = call_used_regs[i] = 1;
6561 if (flag_pic)
6562 fixed_regs[PIC_REG] = call_used_regs[PIC_REG] = 1;
6565 static void
6566 m68k_init_sync_libfuncs (void)
6568 init_sync_libfuncs (UNITS_PER_WORD);
6571 /* Implements EPILOGUE_USES. All registers are live on exit from an
6572 interrupt routine. */
6573 bool
6574 m68k_epilogue_uses (int regno ATTRIBUTE_UNUSED)
6576 return (reload_completed
6577 && (m68k_get_function_kind (current_function_decl)
6578 == m68k_fk_interrupt_handler));
6582 /* Implement TARGET_C_EXCESS_PRECISION.
6584 Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp
6585 instructions, we get proper intermediate rounding, otherwise we
6586 get extended precision results. */
6588 static enum flt_eval_method
6589 m68k_excess_precision (enum excess_precision_type type)
6591 switch (type)
6593 case EXCESS_PRECISION_TYPE_FAST:
6594 /* The fastest type to promote to will always be the native type,
6595 whether that occurs with implicit excess precision or
6596 otherwise. */
6597 return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT;
6598 case EXCESS_PRECISION_TYPE_STANDARD:
6599 case EXCESS_PRECISION_TYPE_IMPLICIT:
6600 /* Otherwise, the excess precision we want when we are
6601 in a standards compliant mode, and the implicit precision we
6602 provide can be identical. */
6603 if (TARGET_68040 || ! TARGET_68881)
6604 return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT;
6606 return FLT_EVAL_METHOD_PROMOTE_TO_LONG_DOUBLE;
6607 default:
6608 gcc_unreachable ();
6610 return FLT_EVAL_METHOD_UNPREDICTABLE;
6613 #include "gt-m68k.h"