gcc/config/aarch64/aarch64-simd-builtins.def

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2012-2017 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 /* In the list below, the BUILTIN_<ITERATOR> macros expand to create
  22    builtins for each of the modes described by <ITERATOR>.  When adding
  23    new builtins to this list, a helpful idiom to follow is to add
  24    a line for each pattern in the md file.  Thus, ADDP, which has one
  25    pattern defined for the VD_BHSI iterator, and one for DImode, has two
  26    entries below.
  27
  28    Parameter 1 is the 'type' of the intrinsic.  This is used to
  29    describe the type modifiers (for example; unsigned) applied to
  30    each of the parameters to the intrinsic function.
  31
  32    Parameter 2 is the name of the intrinsic.  This is appended
  33    to `__builtin_aarch64_<name><mode>` to give the intrinsic name
  34    as exported to the front-ends.
  35
  36    Parameter 3 describes how to map from the name to the CODE_FOR_
  37    macro holding the RTL pattern for the intrinsic.  This mapping is:
  38    0 - CODE_FOR_aarch64_<name><mode>
  39    1-9 - CODE_FOR_<name><mode><1-9>
  40    10 - CODE_FOR_<name><mode>.  */
  41
  42   BUILTIN_VDC (COMBINE, combine, 0)
  43   VAR1 (COMBINEP, combine, 0, di)
  44   BUILTIN_VB (BINOP, pmul, 0)
  45   BUILTIN_VHSDF_HSDF (BINOP, fmulx, 0)
  46   BUILTIN_VHSDF_DF (UNOP, sqrt, 2)
  47   BUILTIN_VD_BHSI (BINOP, addp, 0)
  48   VAR1 (UNOP, addp, 0, di)
  49   BUILTIN_VDQ_BHSI (UNOP, clrsb, 2)
  50   BUILTIN_VDQ_BHSI (UNOP, clz, 2)
  51   BUILTIN_VS (UNOP, ctz, 2)
  52   BUILTIN_VB (UNOP, popcount, 2)
  53
  54   /* Implemented by aarch64_<sur>q<r>shl<mode>.  */
  55   BUILTIN_VSDQ_I (BINOP, sqshl, 0)
  56   BUILTIN_VSDQ_I (BINOP_UUS, uqshl, 0)
  57   BUILTIN_VSDQ_I (BINOP, sqrshl, 0)
  58   BUILTIN_VSDQ_I (BINOP_UUS, uqrshl, 0)
  59   /* Implemented by aarch64_<su_optab><optab><mode>.  */
  60   BUILTIN_VSDQ_I (BINOP, sqadd, 0)
  61   BUILTIN_VSDQ_I (BINOPU, uqadd, 0)
  62   BUILTIN_VSDQ_I (BINOP, sqsub, 0)
  63   BUILTIN_VSDQ_I (BINOPU, uqsub, 0)
  64   /* Implemented by aarch64_<sur>qadd<mode>.  */
  65   BUILTIN_VSDQ_I (BINOP_SSU, suqadd, 0)
  66   BUILTIN_VSDQ_I (BINOP_UUS, usqadd, 0)
  67
  68   /* Implemented by aarch64_get_dreg<VSTRUCT:mode><VDC:mode>.  */
  69   BUILTIN_VDC (GETREG, get_dregoi, 0)
  70   BUILTIN_VDC (GETREG, get_dregci, 0)
  71   BUILTIN_VDC (GETREG, get_dregxi, 0)
  72   VAR1 (GETREGP, get_dregoi, 0, di)
  73   VAR1 (GETREGP, get_dregci, 0, di)
  74   VAR1 (GETREGP, get_dregxi, 0, di)
  75   /* Implemented by aarch64_get_qreg<VSTRUCT:mode><VQ:mode>.  */
  76   BUILTIN_VQ (GETREG, get_qregoi, 0)
  77   BUILTIN_VQ (GETREG, get_qregci, 0)
  78   BUILTIN_VQ (GETREG, get_qregxi, 0)
  79   VAR1 (GETREGP, get_qregoi, 0, v2di)
  80   VAR1 (GETREGP, get_qregci, 0, v2di)
  81   VAR1 (GETREGP, get_qregxi, 0, v2di)
  82   /* Implemented by aarch64_set_qreg<VSTRUCT:mode><VQ:mode>.  */
  83   BUILTIN_VQ (SETREG, set_qregoi, 0)
  84   BUILTIN_VQ (SETREG, set_qregci, 0)
  85   BUILTIN_VQ (SETREG, set_qregxi, 0)
  86   VAR1 (SETREGP, set_qregoi, 0, v2di)
  87   VAR1 (SETREGP, set_qregci, 0, v2di)
  88   VAR1 (SETREGP, set_qregxi, 0, v2di)
  89   /* Implemented by aarch64_ld<VSTRUCT:nregs><VDC:mode>.  */
  90   BUILTIN_VDC (LOADSTRUCT, ld2, 0)
  91   BUILTIN_VDC (LOADSTRUCT, ld3, 0)
  92   BUILTIN_VDC (LOADSTRUCT, ld4, 0)
  93   /* Implemented by aarch64_ld<VSTRUCT:nregs><VQ:mode>.  */
  94   BUILTIN_VQ (LOADSTRUCT, ld2, 0)
  95   BUILTIN_VQ (LOADSTRUCT, ld3, 0)
  96   BUILTIN_VQ (LOADSTRUCT, ld4, 0)
  97   /* Implemented by aarch64_ld<VSTRUCT:nregs>r<VALLDIF:mode>.  */
  98   BUILTIN_VALLDIF (LOADSTRUCT, ld2r, 0)
  99   BUILTIN_VALLDIF (LOADSTRUCT, ld3r, 0)
 100   BUILTIN_VALLDIF (LOADSTRUCT, ld4r, 0)
 101   /* Implemented by aarch64_ld<VSTRUCT:nregs>_lane<VQ:mode>.  */
 102   BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld2_lane, 0)
 103   BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld3_lane, 0)
 104   BUILTIN_VALLDIF (LOADSTRUCT_LANE, ld4_lane, 0)
 105   /* Implemented by aarch64_st<VSTRUCT:nregs><VDC:mode>.  */
 106   BUILTIN_VDC (STORESTRUCT, st2, 0)
 107   BUILTIN_VDC (STORESTRUCT, st3, 0)
 108   BUILTIN_VDC (STORESTRUCT, st4, 0)
 109   /* Implemented by aarch64_st<VSTRUCT:nregs><VQ:mode>.  */
 110   BUILTIN_VQ (STORESTRUCT, st2, 0)
 111   BUILTIN_VQ (STORESTRUCT, st3, 0)
 112   BUILTIN_VQ (STORESTRUCT, st4, 0)
 113
 114   BUILTIN_VALLDIF (STORESTRUCT_LANE, st2_lane, 0)
 115   BUILTIN_VALLDIF (STORESTRUCT_LANE, st3_lane, 0)
 116   BUILTIN_VALLDIF (STORESTRUCT_LANE, st4_lane, 0)
 117
 118   BUILTIN_VQW (BINOP, saddl2, 0)
 119   BUILTIN_VQW (BINOP, uaddl2, 0)
 120   BUILTIN_VQW (BINOP, ssubl2, 0)
 121   BUILTIN_VQW (BINOP, usubl2, 0)
 122   BUILTIN_VQW (BINOP, saddw2, 0)
 123   BUILTIN_VQW (BINOP, uaddw2, 0)
 124   BUILTIN_VQW (BINOP, ssubw2, 0)
 125   BUILTIN_VQW (BINOP, usubw2, 0)
 126   /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>l<mode>.  */
 127   BUILTIN_VD_BHSI (BINOP, saddl, 0)
 128   BUILTIN_VD_BHSI (BINOP, uaddl, 0)
 129   BUILTIN_VD_BHSI (BINOP, ssubl, 0)
 130   BUILTIN_VD_BHSI (BINOP, usubl, 0)
 131   /* Implemented by aarch64_<ANY_EXTEND:su><ADDSUB:optab>w<mode>.  */
 132   BUILTIN_VD_BHSI (BINOP, saddw, 0)
 133   BUILTIN_VD_BHSI (BINOP, uaddw, 0)
 134   BUILTIN_VD_BHSI (BINOP, ssubw, 0)
 135   BUILTIN_VD_BHSI (BINOP, usubw, 0)
 136   /* Implemented by aarch64_<sur>h<addsub><mode>.  */
 137   BUILTIN_VDQ_BHSI (BINOP, shadd, 0)
 138   BUILTIN_VDQ_BHSI (BINOP, shsub, 0)
 139   BUILTIN_VDQ_BHSI (BINOP, uhadd, 0)
 140   BUILTIN_VDQ_BHSI (BINOP, uhsub, 0)
 141   BUILTIN_VDQ_BHSI (BINOP, srhadd, 0)
 142   BUILTIN_VDQ_BHSI (BINOP, urhadd, 0)
 143   /* Implemented by aarch64_<sur><addsub>hn<mode>.  */
 144   BUILTIN_VQN (BINOP, addhn, 0)
 145   BUILTIN_VQN (BINOP, subhn, 0)
 146   BUILTIN_VQN (BINOP, raddhn, 0)
 147   BUILTIN_VQN (BINOP, rsubhn, 0)
 148   /* Implemented by aarch64_<sur><addsub>hn2<mode>.  */
 149   BUILTIN_VQN (TERNOP, addhn2, 0)
 150   BUILTIN_VQN (TERNOP, subhn2, 0)
 151   BUILTIN_VQN (TERNOP, raddhn2, 0)
 152   BUILTIN_VQN (TERNOP, rsubhn2, 0)
 153
 154   BUILTIN_VSQN_HSDI (UNOP, sqmovun, 0)
 155   /* Implemented by aarch64_<sur>qmovn<mode>.  */
 156   BUILTIN_VSQN_HSDI (UNOP, sqmovn, 0)
 157   BUILTIN_VSQN_HSDI (UNOP, uqmovn, 0)
 158   /* Implemented by aarch64_s<optab><mode>.  */
 159   BUILTIN_VSDQ_I (UNOP, sqabs, 0)
 160   BUILTIN_VSDQ_I (UNOP, sqneg, 0)
 161
 162   /* Implemented by aarch64_sqdml<SBINQOPS:as>l<mode>.  */
 163   BUILTIN_VSD_HSI (TERNOP, sqdmlal, 0)
 164   BUILTIN_VSD_HSI (TERNOP, sqdmlsl, 0)
 165   /* Implemented by aarch64_sqdml<SBINQOPS:as>l_lane<mode>.  */
 166   BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_lane, 0)
 167   BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_lane, 0)
 168   /* Implemented by aarch64_sqdml<SBINQOPS:as>l_laneq<mode>.  */
 169   BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlal_laneq, 0)
 170   BUILTIN_VSD_HSI (QUADOP_LANE, sqdmlsl_laneq, 0)
 171   /* Implemented by aarch64_sqdml<SBINQOPS:as>l_n<mode>.  */
 172   BUILTIN_VD_HSI (TERNOP, sqdmlal_n, 0)
 173   BUILTIN_VD_HSI (TERNOP, sqdmlsl_n, 0)
 174
 175   BUILTIN_VQ_HSI (TERNOP, sqdmlal2, 0)
 176   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2, 0)
 177   BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_lane, 0)
 178   BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_lane, 0)
 179   BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlal2_laneq, 0)
 180   BUILTIN_VQ_HSI (QUADOP_LANE, sqdmlsl2_laneq, 0)
 181   BUILTIN_VQ_HSI (TERNOP, sqdmlal2_n, 0)
 182   BUILTIN_VQ_HSI (TERNOP, sqdmlsl2_n, 0)
 183
 184   BUILTIN_VSD_HSI (BINOP, sqdmull, 0)
 185   BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_lane, 0)
 186   BUILTIN_VSD_HSI (TERNOP_LANE, sqdmull_laneq, 0)
 187   BUILTIN_VD_HSI (BINOP, sqdmull_n, 0)
 188   BUILTIN_VQ_HSI (BINOP, sqdmull2, 0)
 189   BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_lane, 0)
 190   BUILTIN_VQ_HSI (TERNOP_LANE, sqdmull2_laneq, 0)
 191   BUILTIN_VQ_HSI (BINOP, sqdmull2_n, 0)
 192   /* Implemented by aarch64_sq<r>dmulh<mode>.  */
 193   BUILTIN_VSDQ_HSI (BINOP, sqdmulh, 0)
 194   BUILTIN_VSDQ_HSI (BINOP, sqrdmulh, 0)
 195   /* Implemented by aarch64_sq<r>dmulh_lane<q><mode>.  */
 196   BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_lane, 0)
 197   BUILTIN_VSDQ_HSI (TERNOP_LANE, sqdmulh_laneq, 0)
 198   BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_lane, 0)
 199   BUILTIN_VSDQ_HSI (TERNOP_LANE, sqrdmulh_laneq, 0)
 200
 201   BUILTIN_VSDQ_I_DI (BINOP, ashl, 3)
 202   /* Implemented by aarch64_<sur>shl<mode>.  */
 203   BUILTIN_VSDQ_I_DI (BINOP, sshl, 0)
 204   BUILTIN_VSDQ_I_DI (BINOP_UUS, ushl, 0)
 205   BUILTIN_VSDQ_I_DI (BINOP, srshl, 0)
 206   BUILTIN_VSDQ_I_DI (BINOP_UUS, urshl, 0)
 207
 208   /* Implemented by aarch64_<sur><dotprod>{_lane}{q}<dot_mode>.  */
 209   BUILTIN_VB (TERNOP, sdot, 0)
 210   BUILTIN_VB (TERNOPU, udot, 0)
 211   BUILTIN_VB (QUADOP_LANE, sdot_lane, 0)
 212   BUILTIN_VB (QUADOPU_LANE, udot_lane, 0)
 213   BUILTIN_VB (QUADOP_LANE, sdot_laneq, 0)
 214   BUILTIN_VB (QUADOPU_LANE, udot_laneq, 0)
 215
 216   BUILTIN_VDQ_I (SHIFTIMM, ashr, 3)
 217   VAR1 (SHIFTIMM, ashr_simd, 0, di)
 218   BUILTIN_VDQ_I (SHIFTIMM, lshr, 3)
 219   VAR1 (USHIFTIMM, lshr_simd, 0, di)
 220   /* Implemented by aarch64_<sur>shr_n<mode>.  */
 221   BUILTIN_VSDQ_I_DI (SHIFTIMM, srshr_n, 0)
 222   BUILTIN_VSDQ_I_DI (USHIFTIMM, urshr_n, 0)
 223   /* Implemented by aarch64_<sur>sra_n<mode>.  */
 224   BUILTIN_VSDQ_I_DI (SHIFTACC, ssra_n, 0)
 225   BUILTIN_VSDQ_I_DI (USHIFTACC, usra_n, 0)
 226   BUILTIN_VSDQ_I_DI (SHIFTACC, srsra_n, 0)
 227   BUILTIN_VSDQ_I_DI (USHIFTACC, ursra_n, 0)
 228   /* Implemented by aarch64_<sur>shll_n<mode>.  */
 229   BUILTIN_VD_BHSI (SHIFTIMM, sshll_n, 0)
 230   BUILTIN_VD_BHSI (USHIFTIMM, ushll_n, 0)
 231   /* Implemented by aarch64_<sur>shll2_n<mode>.  */
 232   BUILTIN_VQW (SHIFTIMM, sshll2_n, 0)
 233   BUILTIN_VQW (SHIFTIMM, ushll2_n, 0)
 234   /* Implemented by aarch64_<sur>q<r>shr<u>n_n<mode>.  */
 235   BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrun_n, 0)
 236   BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrun_n, 0)
 237   BUILTIN_VSQN_HSDI (SHIFTIMM, sqshrn_n, 0)
 238   BUILTIN_VSQN_HSDI (USHIFTIMM, uqshrn_n, 0)
 239   BUILTIN_VSQN_HSDI (SHIFTIMM, sqrshrn_n, 0)
 240   BUILTIN_VSQN_HSDI (USHIFTIMM, uqrshrn_n, 0)
 241   /* Implemented by aarch64_<sur>s<lr>i_n<mode>.  */
 242   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssri_n, 0)
 243   BUILTIN_VSDQ_I_DI (USHIFTACC, usri_n, 0)
 244   BUILTIN_VSDQ_I_DI (SHIFTINSERT, ssli_n, 0)
 245   VAR2 (SHIFTINSERTP, ssli_n, 0, di, v2di)
 246   BUILTIN_VSDQ_I_DI (USHIFTACC, usli_n, 0)
 247   /* Implemented by aarch64_<sur>qshl<u>_n<mode>.  */
 248   BUILTIN_VSDQ_I (SHIFTIMM_USS, sqshlu_n, 0)
 249   BUILTIN_VSDQ_I (SHIFTIMM, sqshl_n, 0)
 250   BUILTIN_VSDQ_I (USHIFTIMM, uqshl_n, 0)
 251
 252   /* Implemented by aarch64_reduc_plus_<mode>.  */
 253   BUILTIN_VALL (UNOP, reduc_plus_scal_, 10)
 254
 255   /* Implemented by reduc_<maxmin_uns>_scal_<mode> (producing scalar).  */
 256   BUILTIN_VDQIF_F16 (UNOP, reduc_smax_scal_, 10)
 257   BUILTIN_VDQIF_F16 (UNOP, reduc_smin_scal_, 10)
 258   BUILTIN_VDQ_BHSI (UNOPU, reduc_umax_scal_, 10)
 259   BUILTIN_VDQ_BHSI (UNOPU, reduc_umin_scal_, 10)
 260   BUILTIN_VHSDF (UNOP, reduc_smax_nan_scal_, 10)
 261   BUILTIN_VHSDF (UNOP, reduc_smin_nan_scal_, 10)
 262
 263   /* Implemented by <maxmin_uns><mode>3.
 264      smax variants map to fmaxnm,
 265      smax_nan variants map to fmax.  */
 266   BUILTIN_VDQ_BHSI (BINOP, smax, 3)
 267   BUILTIN_VDQ_BHSI (BINOP, smin, 3)
 268   BUILTIN_VDQ_BHSI (BINOP, umax, 3)
 269   BUILTIN_VDQ_BHSI (BINOP, umin, 3)
 270   BUILTIN_VHSDF_DF (BINOP, smax_nan, 3)
 271   BUILTIN_VHSDF_DF (BINOP, smin_nan, 3)
 272
 273   /* Implemented by <maxmin_uns><mode>3.  */
 274   BUILTIN_VHSDF_HSDF (BINOP, fmax, 3)
 275   BUILTIN_VHSDF_HSDF (BINOP, fmin, 3)
 276
 277   /* Implemented by aarch64_<maxmin_uns>p<mode>.  */
 278   BUILTIN_VDQ_BHSI (BINOP, smaxp, 0)
 279   BUILTIN_VDQ_BHSI (BINOP, sminp, 0)
 280   BUILTIN_VDQ_BHSI (BINOP, umaxp, 0)
 281   BUILTIN_VDQ_BHSI (BINOP, uminp, 0)
 282   BUILTIN_VHSDF (BINOP, smaxp, 0)
 283   BUILTIN_VHSDF (BINOP, sminp, 0)
 284   BUILTIN_VHSDF (BINOP, smax_nanp, 0)
 285   BUILTIN_VHSDF (BINOP, smin_nanp, 0)
 286
 287   /* Implemented by <frint_pattern><mode>2.  */
 288   BUILTIN_VHSDF (UNOP, btrunc, 2)
 289   BUILTIN_VHSDF (UNOP, ceil, 2)
 290   BUILTIN_VHSDF (UNOP, floor, 2)
 291   BUILTIN_VHSDF (UNOP, nearbyint, 2)
 292   BUILTIN_VHSDF (UNOP, rint, 2)
 293   BUILTIN_VHSDF (UNOP, round, 2)
 294   BUILTIN_VHSDF_DF (UNOP, frintn, 2)
 295
 296   VAR1 (UNOP, btrunc, 2, hf)
 297   VAR1 (UNOP, ceil, 2, hf)
 298   VAR1 (UNOP, floor, 2, hf)
 299   VAR1 (UNOP, frintn, 2, hf)
 300   VAR1 (UNOP, nearbyint, 2, hf)
 301   VAR1 (UNOP, rint, 2, hf)
 302   VAR1 (UNOP, round, 2, hf)
 303
 304   /* Implemented by l<fcvt_pattern><su_optab><VQDF:mode><vcvt_target>2.  */
 305   VAR1 (UNOP, lbtruncv4hf, 2, v4hi)
 306   VAR1 (UNOP, lbtruncv8hf, 2, v8hi)
 307   VAR1 (UNOP, lbtruncv2sf, 2, v2si)
 308   VAR1 (UNOP, lbtruncv4sf, 2, v4si)
 309   VAR1 (UNOP, lbtruncv2df, 2, v2di)
 310
 311   VAR1 (UNOPUS, lbtruncuv4hf, 2, v4hi)
 312   VAR1 (UNOPUS, lbtruncuv8hf, 2, v8hi)
 313   VAR1 (UNOPUS, lbtruncuv2sf, 2, v2si)
 314   VAR1 (UNOPUS, lbtruncuv4sf, 2, v4si)
 315   VAR1 (UNOPUS, lbtruncuv2df, 2, v2di)
 316
 317   VAR1 (UNOP, lroundv4hf, 2, v4hi)
 318   VAR1 (UNOP, lroundv8hf, 2, v8hi)
 319   VAR1 (UNOP, lroundv2sf, 2, v2si)
 320   VAR1 (UNOP, lroundv4sf, 2, v4si)
 321   VAR1 (UNOP, lroundv2df, 2, v2di)
 322   /* Implemented by l<fcvt_pattern><su_optab><GPF_F16:mode><GPI:mode>2.  */
 323   BUILTIN_GPI_I16 (UNOP, lroundhf, 2)
 324   VAR1 (UNOP, lroundsf, 2, si)
 325   VAR1 (UNOP, lrounddf, 2, di)
 326
 327   VAR1 (UNOPUS, lrounduv4hf, 2, v4hi)
 328   VAR1 (UNOPUS, lrounduv8hf, 2, v8hi)
 329   VAR1 (UNOPUS, lrounduv2sf, 2, v2si)
 330   VAR1 (UNOPUS, lrounduv4sf, 2, v4si)
 331   VAR1 (UNOPUS, lrounduv2df, 2, v2di)
 332   BUILTIN_GPI_I16 (UNOPUS, lrounduhf, 2)
 333   VAR1 (UNOPUS, lroundusf, 2, si)
 334   VAR1 (UNOPUS, lroundudf, 2, di)
 335
 336   VAR1 (UNOP, lceilv4hf, 2, v4hi)
 337   VAR1 (UNOP, lceilv8hf, 2, v8hi)
 338   VAR1 (UNOP, lceilv2sf, 2, v2si)
 339   VAR1 (UNOP, lceilv4sf, 2, v4si)
 340   VAR1 (UNOP, lceilv2df, 2, v2di)
 341   BUILTIN_GPI_I16 (UNOP, lceilhf, 2)
 342
 343   VAR1 (UNOPUS, lceiluv4hf, 2, v4hi)
 344   VAR1 (UNOPUS, lceiluv8hf, 2, v8hi)
 345   VAR1 (UNOPUS, lceiluv2sf, 2, v2si)
 346   VAR1 (UNOPUS, lceiluv4sf, 2, v4si)
 347   VAR1 (UNOPUS, lceiluv2df, 2, v2di)
 348   BUILTIN_GPI_I16 (UNOPUS, lceiluhf, 2)
 349   VAR1 (UNOPUS, lceilusf, 2, si)
 350   VAR1 (UNOPUS, lceiludf, 2, di)
 351
 352   VAR1 (UNOP, lfloorv4hf, 2, v4hi)
 353   VAR1 (UNOP, lfloorv8hf, 2, v8hi)
 354   VAR1 (UNOP, lfloorv2sf, 2, v2si)
 355   VAR1 (UNOP, lfloorv4sf, 2, v4si)
 356   VAR1 (UNOP, lfloorv2df, 2, v2di)
 357   BUILTIN_GPI_I16 (UNOP, lfloorhf, 2)
 358
 359   VAR1 (UNOPUS, lflooruv4hf, 2, v4hi)
 360   VAR1 (UNOPUS, lflooruv8hf, 2, v8hi)
 361   VAR1 (UNOPUS, lflooruv2sf, 2, v2si)
 362   VAR1 (UNOPUS, lflooruv4sf, 2, v4si)
 363   VAR1 (UNOPUS, lflooruv2df, 2, v2di)
 364   BUILTIN_GPI_I16 (UNOPUS, lflooruhf, 2)
 365   VAR1 (UNOPUS, lfloorusf, 2, si)
 366   VAR1 (UNOPUS, lfloorudf, 2, di)
 367
 368   VAR1 (UNOP, lfrintnv4hf, 2, v4hi)
 369   VAR1 (UNOP, lfrintnv8hf, 2, v8hi)
 370   VAR1 (UNOP, lfrintnv2sf, 2, v2si)
 371   VAR1 (UNOP, lfrintnv4sf, 2, v4si)
 372   VAR1 (UNOP, lfrintnv2df, 2, v2di)
 373   BUILTIN_GPI_I16 (UNOP, lfrintnhf, 2)
 374   VAR1 (UNOP, lfrintnsf, 2, si)
 375   VAR1 (UNOP, lfrintndf, 2, di)
 376
 377   VAR1 (UNOPUS, lfrintnuv4hf, 2, v4hi)
 378   VAR1 (UNOPUS, lfrintnuv8hf, 2, v8hi)
 379   VAR1 (UNOPUS, lfrintnuv2sf, 2, v2si)
 380   VAR1 (UNOPUS, lfrintnuv4sf, 2, v4si)
 381   VAR1 (UNOPUS, lfrintnuv2df, 2, v2di)
 382   BUILTIN_GPI_I16 (UNOPUS, lfrintnuhf, 2)
 383   VAR1 (UNOPUS, lfrintnusf, 2, si)
 384   VAR1 (UNOPUS, lfrintnudf, 2, di)
 385
 386   /* Implemented by <optab><fcvt_target><VDQF:mode>2.  */
 387   VAR1 (UNOP, floatv4hi, 2, v4hf)
 388   VAR1 (UNOP, floatv8hi, 2, v8hf)
 389   VAR1 (UNOP, floatv2si, 2, v2sf)
 390   VAR1 (UNOP, floatv4si, 2, v4sf)
 391   VAR1 (UNOP, floatv2di, 2, v2df)
 392
 393   VAR1 (UNOP, floatunsv4hi, 2, v4hf)
 394   VAR1 (UNOP, floatunsv8hi, 2, v8hf)
 395   VAR1 (UNOP, floatunsv2si, 2, v2sf)
 396   VAR1 (UNOP, floatunsv4si, 2, v4sf)
 397   VAR1 (UNOP, floatunsv2di, 2, v2df)
 398
 399   VAR5 (UNOPU, bswap, 2, v4hi, v8hi, v2si, v4si, v2di)
 400
 401   BUILTIN_VB (UNOP, rbit, 0)
 402
 403   /* Implemented by
 404      aarch64_<PERMUTE:perm_insn><PERMUTE:perm_hilo><mode>.  */
 405   BUILTIN_VALL (BINOP, zip1, 0)
 406   BUILTIN_VALL (BINOP, zip2, 0)
 407   BUILTIN_VALL (BINOP, uzp1, 0)
 408   BUILTIN_VALL (BINOP, uzp2, 0)
 409   BUILTIN_VALL (BINOP, trn1, 0)
 410   BUILTIN_VALL (BINOP, trn2, 0)
 411
 412   /* Implemented by
 413      aarch64_frecp<FRECP:frecp_suffix><mode>.  */
 414   BUILTIN_GPF_F16 (UNOP, frecpe, 0)
 415   BUILTIN_GPF_F16 (UNOP, frecpx, 0)
 416
 417   BUILTIN_VDQ_SI (UNOP, urecpe, 0)
 418
 419   BUILTIN_VHSDF (UNOP, frecpe, 0)
 420   BUILTIN_VHSDF_HSDF (BINOP, frecps, 0)
 421
 422   /* Implemented by a mixture of abs2 patterns.  Note the DImode builtin is
 423      only ever used for the int64x1_t intrinsic, there is no scalar version.  */
 424   BUILTIN_VSDQ_I_DI (UNOP, abs, 0)
 425   BUILTIN_VHSDF (UNOP, abs, 2)
 426   VAR1 (UNOP, abs, 2, hf)
 427
 428   BUILTIN_VQ_HSF (UNOP, vec_unpacks_hi_, 10)
 429   VAR1 (BINOP, float_truncate_hi_, 0, v4sf)
 430   VAR1 (BINOP, float_truncate_hi_, 0, v8hf)
 431
 432   VAR1 (UNOP, float_extend_lo_, 0, v2df)
 433   VAR1 (UNOP, float_extend_lo_,  0, v4sf)
 434   BUILTIN_VDF (UNOP, float_truncate_lo_, 0)
 435
 436   /* Implemented by aarch64_ld1<VALL_F16:mode>.  */
 437   BUILTIN_VALL_F16 (LOAD1, ld1, 0)
 438   VAR1(STORE1P, ld1, 0, v2di)
 439
 440   /* Implemented by aarch64_st1<VALL_F16:mode>.  */
 441   BUILTIN_VALL_F16 (STORE1, st1, 0)
 442   VAR1(STORE1P, st1, 0, v2di)
 443
 444   /* Implemented by fma<mode>4.  */
 445   BUILTIN_VHSDF (TERNOP, fma, 4)
 446   VAR1 (TERNOP, fma, 4, hf)
 447   /* Implemented by fnma<mode>4.  */
 448   BUILTIN_VHSDF (TERNOP, fnma, 4)
 449   VAR1 (TERNOP, fnma, 4, hf)
 450
 451   /* Implemented by aarch64_simd_bsl<mode>.  */
 452   BUILTIN_VDQQH (BSL_P, simd_bsl, 0)
 453   VAR2 (BSL_P, simd_bsl,0, di, v2di)
 454   BUILTIN_VSDQ_I_DI (BSL_U, simd_bsl, 0)
 455   BUILTIN_VALLDIF (BSL_S, simd_bsl, 0)
 456
 457   /* Implemented by aarch64_crypto_aes<op><mode>.  */
 458   VAR1 (BINOPU, crypto_aese, 0, v16qi)
 459   VAR1 (BINOPU, crypto_aesd, 0, v16qi)
 460   VAR1 (UNOPU, crypto_aesmc, 0, v16qi)
 461   VAR1 (UNOPU, crypto_aesimc, 0, v16qi)
 462
 463   /* Implemented by aarch64_crypto_sha1<op><mode>.  */
 464   VAR1 (UNOPU, crypto_sha1h, 0, si)
 465   VAR1 (BINOPU, crypto_sha1su1, 0, v4si)
 466   VAR1 (TERNOPU, crypto_sha1c, 0, v4si)
 467   VAR1 (TERNOPU, crypto_sha1m, 0, v4si)
 468   VAR1 (TERNOPU, crypto_sha1p, 0, v4si)
 469   VAR1 (TERNOPU, crypto_sha1su0, 0, v4si)
 470
 471   /* Implemented by aarch64_crypto_sha256<op><mode>.  */
 472   VAR1 (TERNOPU, crypto_sha256h, 0, v4si)
 473   VAR1 (TERNOPU, crypto_sha256h2, 0, v4si)
 474   VAR1 (BINOPU, crypto_sha256su0, 0, v4si)
 475   VAR1 (TERNOPU, crypto_sha256su1, 0, v4si)
 476
 477   /* Implemented by aarch64_crypto_pmull<mode>.  */
 478   VAR1 (BINOPP, crypto_pmull, 0, di)
 479   VAR1 (BINOPP, crypto_pmull, 0, v2di)
 480
 481   /* Implemented by aarch64_tbl3<mode>.  */
 482   VAR1 (BINOP, tbl3, 0, v8qi)
 483   VAR1 (BINOP, tbl3, 0, v16qi)
 484
 485   /* Implemented by aarch64_qtbl3<mode>.  */
 486   VAR1 (BINOP, qtbl3, 0, v8qi)
 487   VAR1 (BINOP, qtbl3, 0, v16qi)
 488
 489   /* Implemented by aarch64_qtbl4<mode>.  */
 490   VAR1 (BINOP, qtbl4, 0, v8qi)
 491   VAR1 (BINOP, qtbl4, 0, v16qi)
 492
 493   /* Implemented by aarch64_tbx4<mode>.  */
 494   VAR1 (TERNOP, tbx4, 0, v8qi)
 495   VAR1 (TERNOP, tbx4, 0, v16qi)
 496
 497   /* Implemented by aarch64_qtbx3<mode>.  */
 498   VAR1 (TERNOP, qtbx3, 0, v8qi)
 499   VAR1 (TERNOP, qtbx3, 0, v16qi)
 500
 501   /* Implemented by aarch64_qtbx4<mode>.  */
 502   VAR1 (TERNOP, qtbx4, 0, v8qi)
 503   VAR1 (TERNOP, qtbx4, 0, v16qi)
 504
 505   /* Builtins for ARMv8.1-A Adv.SIMD instructions.  */
 506
 507   /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h<mode>.  */
 508   BUILTIN_VSDQ_HSI (TERNOP, sqrdmlah, 0)
 509   BUILTIN_VSDQ_HSI (TERNOP, sqrdmlsh, 0)
 510
 511   /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_lane<mode>.  */
 512   BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_lane, 0)
 513   BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_lane, 0)
 514
 515   /* Implemented by aarch64_sqrdml<SQRDMLH_AS:rdma_as>h_laneq<mode>.  */
 516   BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlah_laneq, 0)
 517   BUILTIN_VSDQ_HSI (QUADOP_LANE, sqrdmlsh_laneq, 0)
 518
 519   /* Implemented by <FCVT_F2FIXED/FIXED2F:fcvt_fixed_insn><*><*>3.  */
 520   BUILTIN_VSDQ_HSDI (SHIFTIMM, scvtf, 3)
 521   BUILTIN_VSDQ_HSDI (FCVTIMM_SUS, ucvtf, 3)
 522   BUILTIN_VHSDF_HSDF (SHIFTIMM, fcvtzs, 3)
 523   BUILTIN_VHSDF_HSDF (SHIFTIMM_USS, fcvtzu, 3)
 524   VAR1 (SHIFTIMM, scvtfsi, 3, hf)
 525   VAR1 (SHIFTIMM, scvtfdi, 3, hf)
 526   VAR1 (FCVTIMM_SUS, ucvtfsi, 3, hf)
 527   VAR1 (FCVTIMM_SUS, ucvtfdi, 3, hf)
 528   BUILTIN_GPI (SHIFTIMM, fcvtzshf, 3)
 529   BUILTIN_GPI (SHIFTIMM_USS, fcvtzuhf, 3)
 530
 531   /* Implemented by aarch64_rsqrte<mode>.  */
 532   BUILTIN_VHSDF_HSDF (UNOP, rsqrte, 0)
 533
 534   /* Implemented by aarch64_rsqrts<mode>.  */
 535   BUILTIN_VHSDF_HSDF (BINOP, rsqrts, 0)
 536
 537   /* Implemented by fabd<mode>3.  */
 538   BUILTIN_VHSDF_HSDF (BINOP, fabd, 3)
 539
 540   /* Implemented by aarch64_faddp<mode>.  */
 541   BUILTIN_VHSDF (BINOP, faddp, 0)
 542
 543   /* Implemented by aarch64_cm<optab><mode>.  */
 544   BUILTIN_VHSDF_HSDF (BINOP_USS, cmeq, 0)
 545   BUILTIN_VHSDF_HSDF (BINOP_USS, cmge, 0)
 546   BUILTIN_VHSDF_HSDF (BINOP_USS, cmgt, 0)
 547   BUILTIN_VHSDF_HSDF (BINOP_USS, cmle, 0)
 548   BUILTIN_VHSDF_HSDF (BINOP_USS, cmlt, 0)
 549
 550   /* Implemented by neg<mode>2.  */
 551   BUILTIN_VHSDF_HSDF (UNOP, neg, 2)
 552
 553   /* Implemented by aarch64_fac<optab><mode>.  */
 554   BUILTIN_VHSDF_HSDF (BINOP_USS, faclt, 0)
 555   BUILTIN_VHSDF_HSDF (BINOP_USS, facle, 0)
 556   BUILTIN_VHSDF_HSDF (BINOP_USS, facgt, 0)
 557   BUILTIN_VHSDF_HSDF (BINOP_USS, facge, 0)
 558
 559   /* Implemented by sqrt<mode>2.  */
 560   VAR1 (UNOP, sqrt, 2, hf)
 561
 562   /* Implemented by <optab><mode>hf2.  */
 563   VAR1 (UNOP, floatdi, 2, hf)
 564   VAR1 (UNOP, floatsi, 2, hf)
 565   VAR1 (UNOP, floathi, 2, hf)
 566   VAR1 (UNOPUS, floatunsdi, 2, hf)
 567   VAR1 (UNOPUS, floatunssi, 2, hf)
 568   VAR1 (UNOPUS, floatunshi, 2, hf)
 569   BUILTIN_GPI_I16 (UNOP, fix_trunchf, 2)
 570   BUILTIN_GPI (UNOP, fix_truncsf, 2)
 571   BUILTIN_GPI (UNOP, fix_truncdf, 2)
 572   BUILTIN_GPI_I16 (UNOPUS, fixuns_trunchf, 2)
 573   BUILTIN_GPI (UNOPUS, fixuns_truncsf, 2)
 574   BUILTIN_GPI (UNOPUS, fixuns_truncdf, 2)