| blob | 76ebf091fa41d7391560c440d97438ddca4724c1 |
1 2024-04-16 Andrew Pinski <quic_apinski@quicinc.com>
3 PR c/92880
4 * doc/extend.texi (Using Vector Instructions): Add that
5 the base_types could be a typedef of them.
7 2024-04-16 Richard Biener <rguenther@suse.de>
9 PR tree-optimization/114736
10 * tree-vect-slp.cc (vect_optimize_slp_pass::is_cfg_latch_edge):
11 Do not consider VEC_PERM_EXPRs as PHI use.
13 2024-04-16 Richard Biener <rguenther@suse.de>
15 PR tree-optimization/114733
16 * tree-vect-loop.cc (vectorizable_nonlinear_induction): Reject
17 neg induction vectorization of single element vectors.
19 2024-04-16 Jakub Jelinek <jakub@redhat.com>
21 * tree.cc (array_type_nelts): Ensure 2 spaces after . in comment
22 instead of just one.
23 (build_variant_type_copy): Likewise.
24 (tree_check_failed): Likewise.
25 (build_atomic_base): Likewise.
26 * ipa-free-lang-data.cc (fld_incomplete_type_of): Use an indefinite
27 article rather than a.
29 2024-04-16 Fei Gao <gaofei@eswincomputing.com>
31 * config/riscv/riscv.cc (riscv_expand_conditional_move):
32 replace or with add when expanding zicond if possible.
34 2024-04-16 Alexandre Oliva <oliva@adacore.com>
36 PR middle-end/112938
37 * ipa-strub.cc (pass_ipa_strub::execute): Drop volatility from
38 indirected parm.
39 (maybe_make_indirect): Restore volatility in dereferences.
41 2024-04-16 Lulu Cheng <chenglulu@loongson.cn>
43 * config/loongarch/loongarch.opt.urls: Regenerate.
44 * config/mn10300/mn10300.opt.urls: Likewise.
45 * config/msp430/msp430.opt.urls: Likewise.
46 * config/nds32/nds32-elf.opt.urls: Likewise.
47 * config/nds32/nds32-linux.opt.urls: Likewise.
48 * config/nds32/nds32.opt.urls: Likewise.
49 * config/pru/pru.opt.urls: Likewise.
50 * config/riscv/riscv.opt.urls: Likewise.
51 * config/rx/rx.opt.urls: Likewise.
52 * config/sh/sh.opt.urls: Likewise.
53 * config/sparc/sparc.opt.urls: Likewise.
54 * doc/invoke.texi: Add indexes for some compilation options.
56 2024-04-15 Georg-Johann Lay <avr@gjlay.de>
58 * config/avr/avr-mcus.def: Add: avr16du14, avr16du20, avr16du28,
59 avr16du32, avr32du14, avr32du20, avr32du28, avr32du32.
60 * doc/avr-mmcu.texi: Rebuild.
62 2024-04-15 Robin Dapp <rdapp@ventanamicro.com>
64 PR target/114668
65 * config/riscv/autovec.md: Add VLS.
67 2024-04-15 Richard Biener <rguenther@suse.de>
69 PR gcov-profile/114715
70 * gimplify.cc (gimplify_switch_expr): Set the location of the
71 GIMPLE switch.
73 2024-04-15 H.J. Lu <hjl.tools@gmail.com>
75 PR target/114696
76 * config/i386/i386.md (isa): Add apx_ndd_64.
77 (enabled): Likewise.
78 (*add<dwi>3_doubleword): Change rjO to r,ro,jO with 8-bit
79 signed integer constant and enable jO only for apx_ndd_64.
80 (*add<dwi>3_doubleword_cc_overflow_1): Likewise.
81 (*and<dwi>3_doubleword): Likewise.
82 (*<code><dwi>3_doubleword): Likewise.
84 2024-04-15 Tamar Christina <tamar.christina@arm.com>
86 PR tree-optimization/114403
87 * tree-vect-loop.cc (vect_transform_loop): Adjust upper bounds for when
88 peeling for gaps and early break.
90 2024-04-15 Jakub Jelinek <jakub@redhat.com>
92 PR c++/114634
93 * attribs.cc (diag_attr_exclusions): Set attrs[1] to NULL_TREE for
94 decls with NULL TREE_TYPE.
96 2024-04-12 Andrew Carlotti <andrew.carlotti@arm.com>
98 * config/aarch64/aarch64-option-extensions.def: Add RCPC to
99 RCPC3 dependencies.
100 * config/aarch64/aarch64.h (AARCH64_ISA_RCPC8_4): Add test for
101 RCPC3 bit
103 2024-04-12 Andrew Carlotti <andrew.carlotti@arm.com>
105 * config/aarch64/aarch64-arches.def: Add CSSC to V8_9A
106 dependencies.
108 2024-04-12 Will Schmidt <will_schmidt@linux.ibm.com>
109 Peter Bergner <bergner@linux.ibm.com>
111 PR target/101865
112 * config/rs6000/rs6000-builtin.cc (rs6000_builtin_is_supported): Use
113 TARGET_POWER8.
114 * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Use
115 OPTION_MASK_POWER8.
116 * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add OPTION_MASK_POWER8.
117 (ISA_2_7_MASKS_SERVER): Likewise.
118 * config/rs6000/rs6000.cc (rs6000_option_override_internal): Update
119 comment. Use OPTION_MASK_POWER8 and TARGET_POWER8.
120 * config/rs6000/rs6000.h (TARGET_SYNC_HI_QI): Use TARGET_POWER8.
121 * config/rs6000/rs6000.md (define_attr "isa"): Add p8.
122 (define_attr "enabled"): Handle it.
123 (define_insn "prefetch"): Use TARGET_POWER8.
124 * config/rs6000/rs6000.opt (mpower8-internal): New.
126 2024-04-12 Jason Merrill <jason@redhat.com>
127 Patrick Palka <ppalka@redhat.com>
129 PR c++/113141
130 * doc/invoke.texi: Document -Wcast-user-defined.
132 2024-04-12 Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
134 * config/riscv/riscv.opt.urls: Regenerated.
136 2024-04-12 Andrew Pinski <quic_apinski@quicinc.com>
138 PR tree-optimization/114666
139 * match.pd (`!a?b:c`): Reject signed types for the condition.
140 (`a?~t:t`): Likewise.
142 2024-04-12 Richard Sandiford <richard.sandiford@arm.com>
144 * config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Require
145 all tiles to have the same suffix.
147 2024-04-12 Pan Li <pan2.li@intel.com>
149 * config/riscv/riscv.cc (riscv_vector_float_type_p): Take int
150 as the return value instead of unsigned.
151 (riscv_vector_element_bitsize): Ditto.
152 (riscv_vector_required_min_vlen): Ditto.
153 (riscv_validate_vector_type): Take int type for local variable(s).
155 2024-04-12 Jakub Jelinek <jakub@redhat.com>
157 * tree-cfg.cc (gimple_verify_flow_info): Make the misplaced
158 returns_twice diagnostics translatable.
160 2024-04-12 Jakub Jelinek <jakub@redhat.com>
162 PR sanitizer/114687
163 * gimple-iterator.cc (gsi_safe_insert_before): Only use
164 edge_before_returns_twice_call if bb_has_abnormal_pred.
165 (gsi_safe_insert_seq_before): Likewise.
166 * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Only
167 push to m_returns_twice_calls if bb_has_abnormal_pred.
169 2024-04-12 Pan Li <pan2.li@intel.com>
171 PR target/114639
172 * config/riscv/riscv.cc (riscv_function_value_regno_p): Add
173 TARGET_VECTOR predicate for V_RETURN regno.
175 2024-04-11 David Faust <david.faust@oracle.com>
177 * btfout.cc (btf_asm_type_ref): Convert IDs to BTF internally and
178 fix potentially looking up wrong type for asm debug comment info.
179 Split into...
180 (btf_asm_datasec_type_ref): ... This. New.
181 (btf_asm_datasec_entry): Call it here, instead of btf_asm_type_ref.
182 (btf_asm_type, btf_asm_array, btf_asm_varent, btf_asm_sou_member)
183 (btf_asm_func_arg, btf_asm_func_type): Adapt btf_asm_type_ref call.
185 2024-04-11 David Faust <david.faust@oracle.com>
187 * btfout.cc (btf_asm_sou_member): Always emit non-representable
188 bitfield members as having 'void' type. Refactor slightly.
190 2024-04-11 Andrew Carlotti <andrew.carlotti@arm.com>
192 * config/aarch64/aarch64-option-extensions.def:
193 Remove "memtag", "memtag2", "ssbs", "ssbs2", "ls64", "ls64_v"
194 and "ls64_accdata" FMV features.
196 2024-04-11 Andrew Carlotti <andrew.carlotti@arm.com>
198 * config/aarch64/aarch64-option-extensions.def:
199 Remove "flagm2", "sha1", "pmull", "dit", "dpb", "dpb2", "jscvt",
200 "fcma", "rcpc2", "frintts", "dgh", "ebf16", "sve-bf16",
201 "sve-ebf16", "sve-i8mm", "sve2-pmull128", "memtag3", "bti" and
202 "wfxt" entries.
204 2024-04-11 Andrew Carlotti <andrew.carlotti@arm.com>
206 * config/aarch64/aarch64-option-extensions.def:
207 Fix "rmd"->"rdm", and add FMV to "rdma".
208 * config/aarch64/aarch64.cc (FEAT_RDMA): Define as FEAT_RDM.
210 2024-04-11 Andrew Carlotti <andrew.carlotti@arm.com>
212 * config/aarch64/aarch64.cc (compare_feature_masks):
213 Use ARRAY_SIZE and >=0 for iteration bounds.
214 (aarch64_mangle_decl_assembler_name): Use ARRAY_SIZE.
216 2024-04-11 Andrew Carlotti <andrew.carlotti@arm.com>
218 * config/aarch64/aarch64-option-extensions.def: Reorder FMV entries.
220 2024-04-11 Gaius Mulley <gaiusmod2@gmail.com>
222 * doc/standards.texi (Language Standards Supported by GCC):
223 Add Modula-2 language section.
225 2024-04-11 Jakub Jelinek <jakub@redhat.com>
227 PR middle-end/110027
228 * asan.cc (asan_emit_stack_protection): Assert offsets[0] is
229 zero if there is no stack protect guard, otherwise
230 -ASAN_RED_ZONE_SIZE. If alignb > ASAN_RED_ZONE_SIZE and there is
231 stack pointer guard, take the ASAN_RED_ZONE_SIZE bytes allocated at
232 the top of the stack into account when computing base_align_bias.
233 Recompute use_after_return_class from asan_frame_size + base_align_bias
234 and set to -1 if that would overflow to 11.
236 2024-04-11 Richard Biener <rguenther@suse.de>
238 PR tree-optimization/109596
239 * tree-ssa-loop-ch.cc (ch_base::copy_headers): Propagate
240 debug stmts to nonexit->dest rather than exit->dest.
242 2024-04-11 Richard Biener <rguenther@suse.de>
244 PR middle-end/114681
245 * tree-inline.cc (copy_bb): Key on the remapped stmt
246 to identify gconds to have condition coverage data remapped.
248 2024-04-11 Pan Li <pan2.li@intel.com>
250 PR target/114639
251 * config/riscv/riscv.cc (riscv_function_value_regno_p): New func
252 impl for hook TARGET_FUNCTION_VALUE_REGNO_P.
253 (riscv_get_raw_result_mode): New func imple for hook
254 TARGET_GET_RAW_RESULT_MODE.
255 (TARGET_FUNCTION_VALUE_REGNO_P): Impl the hook.
256 (TARGET_GET_RAW_RESULT_MODE): Ditto.
257 * config/riscv/riscv.h (V_RETURN): New macro for vector return.
258 (GP_RETURN_FIRST): New macro for the first GPR in return.
259 (GP_RETURN_LAST): New macro for the last GPR in return.
260 (FP_RETURN_FIRST): Diito but for FPR.
261 (FP_RETURN_LAST): Ditto.
262 (FUNCTION_VALUE_REGNO_P): Remove as deprecated and replace by
263 TARGET_FUNCTION_VALUE_REGNO_P.
265 2024-04-11 Indu Bhagat <indu.bhagat@oracle.com>
267 * btfout.cc (btf_asm_type): Do not skip emitting members of
268 unknown type.
270 2024-04-11 Indu Bhagat <indu.bhagat@oracle.com>
272 PR debug/112878
273 * dwarf2ctf.cc (gen_ctf_sou_type): Check for conditions before
274 call to ctf_add_slice. Use CTF_K_UNKNOWN type if fail.
276 2024-04-10 Marek Polacek <polacek@redhat.com>
278 PR target/114606
279 * config/i386/i386-options.cc (ix86_option_override_internal): Use
280 opts_set rather than checking == CF_NONE.
282 2024-04-10 David Malcolm <dmalcolm@redhat.com>
284 * doc/analyzer.texi: Various tweaks.
286 2024-04-10 Richard Biener <rguenther@suse.de>
288 PR tree-optimization/114672
289 * tree-ssa-math-opts.cc (convert_plusminus_to_widen): Only
290 allow mode-precision results.
292 2024-04-10 Andre Vieira <andre.simoesdiasvieira@arm.com>
294 * config/aarch64/aarch64.cc (TARGET_C_BITINT_TYPE_INFO): Declare MACRO.
295 (aarch64_bitint_type_info): New function.
296 (aarch64_return_in_memory_1): Return large _BitInt's in memory.
297 (aarch64_function_arg_alignment): Adapt to correctly return the ABI
298 mandated alignment of _BitInt(N) where N > 128 as the alignment of
299 TImode.
300 (aarch64_composite_type_p): Return true for _BitInt(N), where N > 128.
302 2024-04-10 Andre Vieira <andre.simoesdiasvieira@arm.com>
304 * config/aarch64/aarch64.cc (bitint_or_aggr_of_bitint_p): New function.
305 (aarch64_layout_arg): Don't emit diagnostics for types involving
306 _BitInt(N).
308 2024-04-10 Jakub Jelinek <jakub@redhat.com>
310 PR c++/114462
311 * tree-core.h (enum annot_expr_kind): Add
312 annot_expr_maybe_infinite_kind enumerator.
313 * gimplify.cc (gimple_boolify): Handle annot_expr_maybe_infinite_kind.
314 * tree-cfg.cc (replace_loop_annotate_in_block): Likewise.
315 (replace_loop_annotate): Likewise. Move loop->finite_p initialization
316 before the replace_loop_annotate_in_block calls.
317 * tree-pretty-print.cc (dump_generic_node): Handle
318 annot_expr_maybe_infinite_kind.
320 2024-04-10 Richard Biener <rguenther@suse.de>
322 Revert:
323 2024-03-27 Segher Boessenkool <segher@kernel.crashing.org>
325 PR rtl-optimization/101523
326 * combine.cc (try_combine): Don't do a 2-insn combination if
327 it does not in fact change I2.
329 2024-04-10 Peter Bergner <bergner@linux.ibm.com>
331 PR target/101865
332 * config/rs6000/rs6000.h (TARGET_DIRECT_MOVE): Define.
333 * config/rs6000/rs6000.cc (rs6000_option_override_internal): Replace
334 OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR. Delete redundant
335 OPTION_MASK_DIRECT_MOVE usage. Delete TARGET_DIRECT_MOVE dead code.
336 (rs6000_opt_masks): Neuter the "direct-move" option.
337 * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Replace
338 OPTION_MASK_DIRECT_MOVE with OPTION_MASK_P8_VECTOR. Delete useless
339 comment.
340 * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Delete
341 OPTION_MASK_DIRECT_MOVE.
342 (OTHER_VSX_VECTOR_MASKS): Likewise.
343 (POWERPC_MASKS): Likewise.
344 * config/rs6000/rs6000.opt (mdirect-move): Remove Mask and Var.
346 2024-04-10 Hongyu Wang <hongyu.wang@intel.com>
348 * config/i386/sse.md (sha1msg1): Use "ja" instead of "Bm" for
349 memory constraint.
350 (sha1msg2): Likewise.
351 (sha1nexte): Likewise.
352 (sha1rnds4): Likewise.
353 (sha256msg1): Likewise.
354 (sha256msg2): Likewise.
355 (sha256rnds2): Likewise.
356 (aes<aesklvariant>u8): Use "jm" instead of "m" for memory
357 constraint.
358 (*aes<aeswideklvariant>u8): Likewise.
359 (*encodekey128u32): Use "jr" instead of "r" for register
360 constraints.
361 (*encodekey256u32): Likewise.
363 2024-04-09 Juergen Christ <jchrist@linux.ibm.com>
365 * config/s390/s390.cc (expand_perm_as_replicate): Implement.
366 (vectorize_vec_perm_const_1): Call new function.
367 * config/s390/vx-builtins.md (vec_splat<mode>): Change to...
368 (@vec_splat<mode>): ...this.
370 2024-04-09 David Faust <david.faust@oracle.com>
372 PR debug/114608
373 * btfout.cc (btf_asm_datasec_entry): Only emit a symbol reference when
374 generating BTF for BPF CO-RE target.
376 2024-04-09 Richard Ball <richard.ball@arm.com>
378 * config/aarch64/aarch64-c.cc (aarch64_pragma_aarch64):
379 Add functions_nulls parameter to pragma_handlers.
380 * config/aarch64/aarch64-protos.h: Likewise.
381 * config/aarch64/aarch64-sve-builtins.h
382 (enum handle_pragma_index): Add enum to count
383 number of pragmas to be handled.
384 * config/aarch64/aarch64-sve-builtins.cc
385 (GTY): Add global variable for initial indexes
386 and change overload_names to an array.
387 (function_builder::function_builder):
388 Add pragma handler information.
389 (function_builder::add_function):
390 Add code for overwriting previous
391 registered_functions entries.
392 (add_unique_function):
393 Use an array to register overload_names
394 for both pragma handler modes.
395 (add_overloaded_function): Likewise.
396 (init_builtins):
397 Add functions_nulls parameter to pragma_handlers.
398 (handle_arm_sve_h):
399 Initialize pragma handler information.
400 (handle_arm_neon_sve_bridge_h): Likewise.
401 (handle_arm_sme_h): Likewise.
403 2024-04-09 Richard Biener <rguenther@suse.de>
405 PR lto/114655
406 * lto-wrapper.cc (merge_flto_options): Add force argument.
407 (merge_and_complain): Do not force here.
408 (run_gcc): But here to make the link-time -flto option override
409 any compile-time one.
411 2024-04-09 Sebastian Huber <sebastian.huber@embedded-brains.de>
413 * config/rs6000/rtems.h (OS_MISSING_POWERPC64): Define.
415 2024-04-09 Jørgen Kvalsvik <j@lambda.is>
417 PR gcov-profile/114601
418 * tree-profile.cc (condition_uid): Guard fn->cond_uids access.
420 2024-04-09 Jakub Jelinek <jakub@redhat.com>
422 PR target/114576
423 * config/i386/i386.md (isa): Remove aes, add vaes_avx512vl.
424 (enabled): Remove aes isa check, add vaes_avx512vl.
425 * config/i386/sse.md (aesenc, aesenclast, aesdec, aesdeclast): Use
426 jm instead of m for second alternative and emit {evex} prefix
427 for it if !TARGET_AES. Use noavx,avx,vaes_avx512vl isa attribute.
428 (vaesdec_<mode>, vaesdeclast_<mode>, vaesenc_<mode>,
429 vaesenclast_<mode>): Add second alternative with x instead of v
430 and jm instead of m.
432 2024-04-09 Gaius Mulley <gaiusmod2@gmail.com>
434 * doc/gm2.texi (Compiler options): Remove -fdebug-trace-quad.
435 Remove -fdebug-trace-api.
436 Add -fm2-debug-trace=.
438 2024-04-09 Yang Yujie <yangyujie@loongson.cn>
440 PR target/113233
441 * config/loongarch/loongarch.cc (loongarch_reg_init):
442 Reinitialize the loongarch_regno_mode_ok cache.
443 (loongarch_option_override): Same.
444 (loongarch_save_restore_target_globals): Restore target globals.
445 (loongarch_set_current_function): Restore the target contexts
446 for functions.
447 (TARGET_SET_CURRENT_FUNCTION): Define.
448 * config/loongarch/loongarch.h (SWITCHABLE_TARGET): Enable
449 switchable target context.
450 * config/loongarch/loongarch-builtins.cc (loongarch_init_builtins):
451 Initialize all builtin functions at startup.
452 (loongarch_expand_builtin): Turn assertion of builtin availability
453 into a test.
455 2024-04-09 Jørgen Kvalsvik <j@lambda.is>
457 PR middle-end/114627
458 * tree-profile.cc (instrument_decisions): Generate constant
459 at the start of loop.
461 2024-04-09 Jørgen Kvalsvik <j@lambda.is>
463 PR middle-end/114599
464 * tree-inline.cc (copy_bb): Copy cond_uids into callee.
465 (prepend_lexical_block): Remove outdated comment.
466 (add_local_variables): Remove bad cond_uids copy.
468 2024-04-09 Jakub Jelinek <jakub@redhat.com>
470 * expr.cc (convert_mode_scalar): Fix duplicated words in comment;
471 into into -> it into.
472 * function.h (function::cond_uids): Fix duplicated words in comment;
473 same same -> same.
474 * config/riscv/riscv-vector-costs.cc
475 (costs::adjust_vect_cost_per_loop): Fix duplicated words in comment;
476 model model -> model.
477 * config/riscv/riscv-vector-builtins-shapes.cc (build_base): Fix
478 duplicated words in comment; for for -> for.
479 * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Fix
480 duplicated words in comment; more more -> more.
481 * config/aarch64/driver-aarch64.cc (host_detect_local_cpu): Fix
482 duplicated words in comment; be be -> be.
483 * tree-profile.cc (masking_vectors): Fix duplicated words in comment;
484 has has -> has, the the -> the.
485 * value-range.cc (irange::set_range_from_bitmask): Fix duplicated
486 words in comment; the the -> the.
487 * gcov.cc (add_condition_counts): Fix duplicated words in comment;
488 to to -> to.
489 * vr-values.cc (get_scev_info): Fix duplicated words in comment;
490 the the -> to the.
491 * tree-vrp.cc (fully_replaceable): Fix duplicated words in comment;
492 by by -> by.
493 * mode-switching.cc (single_succ_confluence_n): Fix duplicated words
494 in comment; the the -> the.
495 * tree-ssa-phiopt.cc (value_replacement): Fix duplicated words in
496 comment; can can -> we can.
497 * gimple-range-phi.cc (phi_analyzer::process_phi): Fix duplicated words
498 in comment; it it -> it is.
499 * tree-ssa-sccvn.cc (visit_phi): Fix duplicated words in comment;
500 to to -> to.
501 * rtl-ssa/accesses.h (use_info::next_debug_insn_use): Fix duplicated
502 words in comment; if if -> if.
503 * doc/options.texi (InverseMask): Fix duplicated words; and and -> and.
504 Change take to takes.
505 * doc/invoke.texi (fanalyzer-undo-inlining): Fix duplicated words;
506 be be -> be.
507 (-minline-memops-threshold): Likewise.
509 2024-04-09 Jakub Jelinek <jakub@redhat.com>
511 PR middle-end/114628
512 * gimple-lower-bitint.cc (gimple_lower_bitint): Keep debug stmts
513 before returns_twice calls as is, don't push them into arg_stmts
514 vector/move to edges.
516 2024-04-09 Sergey Bugaev <bugaevc@gmail.com>
518 * config.gcc: Recognize aarch64*-*-gnu* targets.
519 * config/aarch64/aarch64-gnu.h: New file.
521 2024-04-09 Sergey Bugaev <bugaevc@gmail.com>
523 * config/i386/gnu.h: Move GNU/Hurd STARTFILE_SPEC from here...
524 * config/gnu.h: ...to here.
526 2024-04-09 Richard Biener <rguenther@suse.de>
528 PR middle-end/114604
529 * gimple-range.cc (enable_ranger): Initialize the global
530 bitmap obstack.
531 (disable_ranger): Release it.
533 2024-04-09 Sebastian Huber <sebastian.huber@embedded-brains.de>
535 * config.gcc (aarch64-*-rtems*): Add target makefile fragment
536 t-aarch64-rtems.
537 * config/aarch64/t-aarch64-rtems: New file.
539 2024-04-09 H.J. Lu <hjl.tools@gmail.com>
541 PR target/114587
542 * config/i386/i386-c.cc (ix86_target_macros_internal): Define
543 __APX_INLINE_ASM_USE_GPR32__ for -mapx-inline-asm-use-gpr32.
545 2024-04-09 Kewen Lin <linkw@linux.ibm.com>
546 Andrew Pinski <quic_apinski@quicinc.com>
548 PR target/88309
549 * config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_builtin): Fix
550 wrong align passed to function build_aligned_type.
551 * tree-ssa-loop-prefetch.cc (is_miss_rate_acceptable): Add an
552 assertion to ensure align_unit should be positive.
553 * tree.cc (build_qualified_type): Update function comments.
555 2024-04-08 Uros Bizjak <ubizjak@gmail.com>
557 PR rtl-optimization/112560
558 * combine.cc (try_combine): Replace cc_use_loc with the entire
559 new RTX only in case cc_use_loc satisfies COMPARISON_P predicate.
560 Otherwise scan the entire cc_use_loc RTX for CC reg to be updated
561 with a new mode.
562 * config/i386/i386.md (@pushf<mode>2): Allow all CC modes for
563 operand 1.
565 2024-04-08 Thomas Schwinge <tschwinge@baylibre.com>
567 * config/gcn/gcn.opt (--param=gcn-preferred-vectorization-factor):
568 New.
569 * config/gcn/gcn.cc (gcn_vectorize_preferred_simd_mode) Use it.
570 * doc/invoke.texi (Optimize Options): Document it.
572 2024-04-08 Thomas Schwinge <tschwinge@baylibre.com>
574 * doc/sourcebuild.texi (Effective-Target Keywords): Document
575 'asm_goto_with_outputs'. Add comment to 'lra'.
577 2024-04-08 Martin Jambor <mjambor@suse.cz>
579 PR ipa/113359
580 * ipa-icf-gimple.h (func_checker): New members
581 safe_for_total_scalarization_p, m_total_scalarization_limit_known_p
582 and m_total_scalarization_limit.
583 (func_checker::func_checker): Initialize new member variables.
584 * ipa-icf-gimple.cc: Include tree-sra.h.
585 (func_checker::func_checker): Initialize new member variables.
586 (func_checker::safe_for_total_scalarization_p): New function.
587 (func_checker::compare_operand): Use the new function.
588 * tree-sra.h (sra_get_max_scalarization_size): Declare.
589 (sra_total_scalarization_would_copy_same_data_p): Likewise.
590 * tree-sra.cc (prepare_iteration_over_array_elts): New function.
591 (class sra_padding_collecting): New.
592 (sra_padding_collecting::record_padding): Likewise.
593 (scalarizable_type_p): Rename to totally_scalarizable_type_p. Add
594 ability to record padding when requested.
595 (totally_scalarize_subtree): Split out gathering information necessary
596 to iterate over array elements to prepare_iteration_over_array_elts.
597 Fix errornous early exit.
598 (analyze_all_variable_accesses): Adjust the call to
599 totally_scalarizable_type_p. Move determining of total scalariation
600 size limit...
601 (sra_get_max_scalarization_size): ...here.
602 (check_ts_and_push_padding_to_vec): New function.
603 (sra_total_scalarization_would_copy_same_data_p): Likewise.
605 2024-04-08 Martin Jambor <mjambor@suse.cz>
607 PR ipa/113907
608 * ipa-prop.h (class ipa_vr): Declare new overload of a member function
609 equal_p.
610 (ipa_jump_functions_equivalent_p): Declare.
611 * ipa-prop.cc (ipa_vr::equal_p): New function.
612 (ipa_agg_pass_through_jf_equivalent_p): Likewise.
613 (ipa_agg_jump_functions_equivalent_p): Likewise.
614 (ipa_jump_functions_equivalent_p): Likewise.
615 * ipa-cp.h (values_equal_for_ipcp_p): Declare.
616 * ipa-cp.cc (values_equal_for_ipcp_p): Make function public.
617 * ipa-icf-gimple.cc: Include alloc-pool.h, symbol-summary.h, sreal.h,
618 ipa-cp.h and ipa-prop.h.
619 (func_checker::compare_gimple_call): Comapre jump functions.
621 2024-04-08 Richard Sandiford <richard.sandiford@arm.com>
623 PR target/114607
624 * config/aarch64/aarch64-sve-builtins-base.cc
625 (svusdot_impl::expand): Fix botched attempt to swap the operands
626 for svsudot.
628 2024-04-08 Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
630 * config/riscv/riscv.opt: Add -mtls-dialect to configure TLS flavor.
631 * config.gcc: Add --with-tls configuration option to change the
632 default TLS flavor.
633 * config/riscv/riscv.h: Add TARGET_TLSDESC determined from
634 -mtls-dialect and with_tls defaults.
635 * config/riscv/riscv-opts.h: Define enum riscv_tls_type for the
636 two TLS flavors.
637 * config/riscv/riscv-protos.h: Define SYMBOL_TLSDESC symbol type.
638 * config/riscv/riscv.md: Add instruction sequence for TLSDESC.
639 * config/riscv/riscv.cc (riscv_symbol_insns): Add instruction
640 sequence length data for TLSDESC.
641 (riscv_legitimize_tls_address): Add lowering of TLSDESC.
642 * doc/install.texi: Document --with-tls for RISC-V.
643 * doc/invoke.texi: Document -mtls-dialect for RISC-V.
645 2024-04-08 Jakub Jelinek <jakub@redhat.com>
647 PR target/114605
648 * config/s390/s390.cc (s390_const_int_pool_entry_p): Punt
649 if mem doesn't have MODE_INT mode, or pool constant doesn't
650 have MODE_INT mode, or if pool constant mode is smaller than
651 mem mode. If mem mode is different from pool constant mode,
652 try to simplify subreg. If that doesn't work, punt, if it
653 does, use the simplified constant instead of the constant pool
654 constant.
655 * config/s390/s390.md (movdi from const pool peephole): If
656 either low or high 32-bit part is zero, just emit move insn
657 instead of move + ior.
659 2024-04-08 Richard Biener <rguenther@suse.de>
661 PR tree-optimization/114624
662 * tree-scalar-evolution.cc (final_value_replacement_loop):
663 Get at the PHI arg location before releasing the PHI node.
665 2024-04-08 Pan Li <pan2.li@intel.com>
667 * config/riscv/riscv-vector-builtins-shapes.cc (build_one): Pass
668 required_ext arg when invoke add function.
669 (build_th_loadstore): Ditto.
670 (struct vcreate_def): Ditto.
671 (struct read_vl_def): Ditto.
672 (struct vlenb_def): Ditto.
673 * config/riscv/riscv-vector-builtins.cc (function_builder::add_function):
674 Introduce new arg required_ext to fill in the register func.
675 (function_builder::add_unique_function): Ditto.
676 (function_builder::add_overloaded_function): Ditto.
677 (expand_builtin): Leverage required_extensions_specified to
678 check if the required extension is provided.
679 * config/riscv/riscv-vector-builtins.h (reqired_ext_to_isa_name): New
680 func impl to convert the required_ext enum to the extension name.
681 (required_extensions_specified): New func impl to predicate if
682 the required extension is well feeded.
684 2024-04-08 Iain Sandoe <iain@sandoe.co.uk>
686 * config/darwin.h (LINK_COMMAND_SPEC_A): Update coverage
687 specs.
689 2024-04-08 demin.han <demin.han@starfivetech.com>
691 * config/riscv/riscv-vector-costs.cc: Use length()
693 2024-04-08 Pan Li <pan2.li@intel.com>
695 * config/riscv/riscv-c.cc (struct pragma_intrinsic_flags): New
696 struct to hold all intrinisc related flags.
697 (riscv_pragma_intrinsic_flags_pollute): New func to pollute
698 the intrinsic flags and backup original flags.
699 (riscv_pragma_intrinsic_flags_restore): New func to restore
700 the flags from the backup intrinsic flags.
701 (riscv_pragma_intrinsic): Pollute the flags and register all
702 possible builtin types and functions, then restore and reinit.
703 * config/riscv/riscv-protos.h (reinit_builtins): New func
704 decl to reinit after flags pollution.
705 (riscv_option_override): New extern func decl.
706 * config/riscv/riscv-vector-builtins.cc (register_builtin_types_on_null):
707 New func to register builtin types if null.
708 (DEF_RVV_TYPE): Ditto.
709 (DEF_RVV_TUPLE_TYPE): Ditto.
710 (reinit_builtins): New func impl to reinit after flags pollution.
711 (expand_builtin): Return
712 target rtx after error_at.
713 * config/riscv/riscv.cc (riscv_vector_int_type_p): New predicate
714 func to tell one tree type is integer or not.
715 (riscv_vector_float_type_p): New predicate func to tell one tree
716 type is float or not.
717 (riscv_vector_element_bitsize): New func to get the element bitsize
718 of a vector tree type.
719 (riscv_vector_required_min_vlen): New func to get the required min vlen
720 of a vector tree type.
721 (riscv_validate_vector_type): New func to validate the tree type
722 is valid on flags.
723 (riscv_return_value_is_vector_type_p): Leverage the func
724 riscv_validate_vector_type to do the tree type validation.
725 (riscv_arguments_is_vector_type_p): Ditto.
726 (riscv_override_options_internal): Ditto.
728 2024-04-08 Lulu Cheng <chenglulu@loongson.cn>
730 PR target/112919
731 * config/loongarch/loongarch-def.cc (la664_align): Newly defined
732 function that sets alignment rules under the LA664 microarchitecture.
733 * config/loongarch/loongarch-opts.cc
734 (loongarch_target_option_override): If not optimizing for size, set
735 the default alignment to what the target wants.
736 * config/loongarch/loongarch-tune.h (struct loongarch_align): Add
737 new member variables jump and loop.
739 2024-04-06 H.J. Lu <hjl.tools@gmail.com>
741 PR target/114590
742 * config/i386/i386.md (x86_64_shld): Use explicit shift count in
743 AT&T syntax.
744 (x86_64_shld_ndd): Likewise.
745 (x86_shld): Likewise.
746 (x86_shld_ndd): Likewise.
747 (x86_64_shrd): Likewise.
748 (x86_64_shrd_ndd): Likewise.
749 (x86_shrd): Likewise.
750 (x86_shrd_ndd): Likewise.
752 2024-04-06 Jørgen Kvalsvik <j@lambda.is>
754 PR middle-end/114599
755 * tree-inline.cc (add_local_variables): Copy cond_uids mappings.
757 2024-04-05 David Malcolm <dmalcolm@redhat.com>
759 PR analyzer/114588
760 * diagnostic-color.cc (color_dict): Add "valid" and "invalid" as
761 color capability names.
762 * doc/invoke.texi: Document them in description of GCC_COLORS.
763 * text-art/style.cc: Include "diagnostic-color.h".
764 (text_art::get_style_from_color_cap_name): New.
765 * text-art/types.h (get_style_from_color_cap_name): New decl.
767 2024-04-05 Alex Coplan <alex.coplan@arm.com>
769 * config/aarch64/aarch64-ldp-fusion.cc (struct alias_walker):
770 Fix double space after const qualifier on valid ().
772 2024-04-05 Martin Jambor <mjambor@suse.cz>
774 PR ipa/113964
775 * ipa-param-manipulation.cc (ipa_param_adjustments::modify_call):
776 Force values obtined through pass-through maps to the expected
777 split type.
779 2024-04-05 Mark Wielaard <mark@klomp.org>
781 * common.opt.urls: Regenerate.
783 2024-04-05 Richard Sandiford <richard.sandiford@arm.com>
785 PR target/114603
786 * config/aarch64/aarch64-sve.md (@aarch64_pred_cnot<mode>): Replace
787 with...
788 (@aarch64_ptrue_cnot<mode>): ...this, requiring operand 1 to be
789 a ptrue.
790 (*cnot<mode>): Require operand 1 to be a ptrue.
791 * config/aarch64/aarch64-sve-builtins-base.cc (svcnot_impl::expand):
792 Use aarch64_ptrue_cnot<mode> for _x operations that are predicated
793 with a ptrue. Represent other _x operations as fully-defined _m
794 operations.
796 2024-04-05 Jakub Jelinek <jakub@redhat.com>
798 PR tree-optimization/114566
799 * tree-vect-loop.cc (update_epilogue_loop_vinfo): Don't clear
800 base_misaligned.
802 2024-04-05 Richard Biener <rguenther@suse.de>
804 PR middle-end/114599
805 PR gcov-profile/114115
806 * symtab.cc (ifunc_ref_map): Do not use auto_bitmap.
807 (is_caller_ifunc_resolver): Optimize bitmap_bit_p/bitmap_set_bit
808 pair.
809 (symtab_node::check_ifunc_callee_symtab_nodes): Properly
810 allocate ifunc_ref_map here.
812 2024-04-04 Martin Jambor <mjambor@suse.cz>
814 PR ipa/111571
815 * ipa-param-manipulation.cc
816 (ipa_param_body_adjustments::common_initialization): Avoid creating
817 duplicate replacement entries.
819 2024-04-04 Vladimir N. Makarov <vmakarov@redhat.com>
821 PR rtl-optimization/114415
822 * sched-deps.cc (add_insn_mem_dependence): Add memory check for mem argument.
823 (sched_analyze_1): Treat stack pointer modification as memory read.
824 (sched_analyze_2, sched_analyze_insn): Add memory guard for processing pending_read_mems.
825 * sched-int.h (deps_desc): Add comment to pending_read_mems.
827 2024-04-04 Tobias Burnus <tburnus@baylibre.com>
829 * config/nvptx/mkoffload.cc (main): Call
830 gcc_init_libintl and diagnostic_color_init.
832 2024-04-04 H.J. Lu <hjl.tools@gmail.com>
834 PR target/114587
835 * config/i386/i386-c.cc (ix86_target_macros_internal): Define
836 __APX_F__ when APX is enabled.
838 2024-04-04 Jørgen Kvalsvik <j@lambda.is>
840 * builtins.cc (expand_builtin_fork_or_exec): Check
841 condition_coverage_flag.
842 * collect2.cc (main): Add -fno-condition-coverage to OBSTACK.
843 * common.opt: Add new options -fcondition-coverage and
844 -Wcoverage-too-many-conditions.
845 * doc/gcov.texi: Add --conditions documentation.
846 * doc/invoke.texi: Add -fcondition-coverage documentation.
847 * function.cc (free_after_compilation): Free cond_uids.
848 * function.h (struct function): Add cond_uids.
849 * gcc.cc: Link gcov on -fcondition-coverage.
850 * gcov-counter.def (GCOV_COUNTER_CONDS): New.
851 * gcov-dump.cc (tag_conditions): New.
852 * gcov-io.h (GCOV_TAG_CONDS): New.
853 (GCOV_TAG_CONDS_LENGTH): New.
854 (GCOV_TAG_CONDS_NUM): New.
855 * gcov.cc (class condition_info): New.
856 (condition_info::condition_info): New.
857 (condition_info::popcount): New.
858 (struct coverage_info): New.
859 (add_condition_counts): New.
860 (output_conditions): New.
861 (print_usage): Add -g, --conditions.
862 (process_args): Likewise.
863 (output_intermediate_json_line): Output conditions.
864 (read_graph_file): Read condition counters.
865 (read_count_file): Likewise.
866 (file_summary): Print conditions.
867 (accumulate_line_info): Accumulate conditions.
868 (output_line_details): Print conditions.
869 * gimplify.cc (next_cond_uid): New.
870 (reset_cond_uid): New.
871 (shortcut_cond_r): Set condition discriminator.
872 (tag_shortcut_cond): New.
873 (gimple_associate_condition_with_expr): New.
874 (shortcut_cond_expr): Set condition discriminator.
875 (gimplify_cond_expr): Likewise.
876 (gimplify_function_tree): Call reset_cond_uid.
877 * ipa-inline.cc (can_early_inline_edge_p): Check
878 condition_coverage_flag.
879 * ipa-split.cc (pass_split_functions::gate): Likewise.
880 * passes.cc (finish_optimization_passes): Likewise.
881 * profile.cc (struct condcov): New declaration.
882 (cov_length): Likewise.
883 (cov_blocks): Likewise.
884 (cov_masks): Likewise.
885 (cov_maps): Likewise.
886 (cov_free): Likewise.
887 (instrument_decisions): New.
888 (read_thunk_profile): Control output to file.
889 (branch_prob): Call find_conditions, instrument_decisions.
890 (init_branch_prob): Add total_num_conds.
891 (end_branch_prob): Likewise.
892 * tree-core.h (struct tree_exp): Add condition_uid.
893 * tree-profile.cc (struct conds_ctx): New.
894 (CONDITIONS_MAX_TERMS): New.
895 (EDGE_CONDITION): New.
896 (topological_cmp): New.
897 (index_of): New.
898 (single_p): New.
899 (single_edge): New.
900 (contract_edge_up): New.
901 (struct outcomes): New.
902 (conditional_succs): New.
903 (condition_index): New.
904 (condition_uid): New.
905 (masking_vectors): New.
906 (emit_assign): New.
907 (emit_bitwise_op): New.
908 (make_top_index_visit): New.
909 (make_top_index): New.
910 (paths_between): New.
911 (struct condcov): New.
912 (cov_length): New.
913 (cov_blocks): New.
914 (cov_masks): New.
915 (cov_maps): New.
916 (cov_free): New.
917 (find_conditions): New.
918 (struct counters): New.
919 (find_counters): New.
920 (resolve_counter): New.
921 (resolve_counters): New.
922 (instrument_decisions): New.
923 (tree_profiling): Check condition_coverage_flag.
924 (pass_ipa_tree_profile::gate): Likewise.
925 * tree.h (SET_EXPR_UID): New.
926 (EXPR_COND_UID): New.
928 2024-04-04 Richard Sandiford <richard.sandiford@arm.com>
930 PR target/114577
931 * config/aarch64/aarch64-sve-builtins.h (aarch64_sve::lookup_fndecl):
932 Declare.
933 * config/aarch64/aarch64-sve-builtins.cc (aarch64_sve::lookup_fndecl):
934 New function.
935 * config/aarch64/aarch64-sve-builtins-base.cc (is_undef): Likewise.
936 (svset_neonq_impl::expand): Optimise expansions whose first argument
937 is undefined.
939 2024-04-04 Richard Biener <rguenther@suse.de>
941 PR tree-optimization/114485
942 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
943 vect_step_op_neg isn't OK for partial vectors but only
944 for unknown niter.
946 2024-04-04 Jakub Jelinek <jakub@redhat.com>
948 PR c++/114537
949 * fold-const.cc (native_encode_initializer): Look through
950 NON_LVALUE_EXPR if val is INTEGER_CST.
952 2024-04-04 Jakub Jelinek <jakub@redhat.com>
954 PR tree-optimization/114555
955 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): For
956 m_bitfld_load and save_cast_conditional add any needed PHIs
957 and adjust t4 accordingly.
959 2024-04-04 Richard Biener <rguenther@suse.de>
961 PR tree-optimization/114551
962 * tree-ssa-loop-split.cc (split_loop): If the guard is
963 only conditionally evaluated rewrite computations with
964 possibly undefined overflow to unsigned arithmetic.
966 2024-04-04 Eugene Rozenfeld <erozen@microsoft.com>
968 PR gcov-profile/113765
969 * auto-profile.cc (afdo_annotate_cfg): Don't set full_profile to true
971 2024-04-03 Mark Wielaard <mark@klomp.org>
973 * config/i386/i386.opt.urls: Regenerate.
975 2024-04-03 H.J. Lu <hjl.tools@gmail.com>
977 PR tree-optimization/114115
978 * cgraph.h (symtab_node): Add check_ifunc_callee_symtab_nodes.
979 (cgraph_node): Add called_by_ifunc_resolver.
980 * cgraphunit.cc (symbol_table::compile): Call
981 symtab_node::check_ifunc_callee_symtab_nodes.
982 * symtab.cc (check_ifunc_resolver): New.
983 (ifunc_ref_map): Likewise.
984 (is_caller_ifunc_resolver): Likewise.
985 (symtab_node::check_ifunc_callee_symtab_nodes): Likewise.
986 * tree-profile.cc (gimple_gen_ic_func_profiler): Disable indirect
987 call profiling for IFUNC resolvers and their callees.
989 2024-04-03 Tobias Burnus <tburnus@baylibre.com>
991 * lto-wrapper.cc (compile_offload_image): Prefix 'offload_args'
992 suffix by the target name.
994 2024-04-03 Tobias Burnus <tburnus@baylibre.com>
996 * doc/install.texi (amdgcn-*-amdhsa): Update Newlib recommendation
997 and update wording for LLVM 18 release.
999 2024-04-03 Tobias Burnus <tburnus@baylibre.com>
1001 PR other/111966
1002 * config/gcn/mkoffload.cc (get_arch): New; moved -march= flag
1003 handling from ...
1004 (main): ... here; call it to handle --with-arch config option
1005 and -march= commandline.
1007 2024-04-03 Jakub Jelinek <jakub@redhat.com>
1009 PR middle-end/114552
1010 * expr.cc (emit_push_insn): Only use store_constructor for
1011 immediate_const_ctor_p if int_expr_size matches size.
1013 2024-04-03 Richard Biener <rguenther@suse.de>
1015 PR tree-optimization/114557
1016 PR tree-optimization/114480
1017 * tree-phinodes.cc (release_phi_node): Return PHIs from
1018 allocation buckets not covered by free_phinodes to GC.
1019 (remove_phi_node): Release the PHI LHS before freeing the
1020 PHI node.
1021 * tree-vect-loop.cc (vectorizable_live_operation): Get PHI lhs
1022 before releasing it.
1024 2024-04-03 Jiahao Xu <xujiahao@loongson.cn>
1026 * config/loongarch/lasx.md: Remove unused code.
1027 * config/loongarch/loongarch-protos.h
1028 (loongarch_split_lsx_copy_d): Remove.
1029 (loongarch_split_lsx_insert_d): Ditto.
1030 (loongarch_split_lsx_fill_d): Ditto.
1031 * config/loongarch/loongarch.cc
1032 (loongarch_split_lsx_copy_d): Ditto.
1033 (loongarch_split_lsx_insert_d): Ditto.
1034 (loongarch_split_lsx_fill_d): Ditto.
1035 * config/loongarch/lsx.md (lsx_vpickve2gr_du): Remove splitter.
1036 (lsx_vpickve2gr_<lsxfmt_f>): Ditto.
1037 (abs<mode>2): Remove expander.
1038 (vabs<mode>2): Rename 2 abs<mode>2.
1040 2024-04-02 Christophe Lyon <christophe.lyon@linaro.org>
1042 * config/aarch64/aarch64-option-extensions.def: Fix comment.
1044 2024-04-02 Tom Tromey <tromey@adacore.com>
1046 * dwarf2out.cc (print_dw_val) <dw_val_class_loc>: Don't
1047 print newline when not recursing.
1049 2024-04-02 Iain Sandoe <iain@sandoe.co.uk>
1051 * config/darwin.cc (darwin_override_options): Update the
1052 clang major version value in the dsymutil check.
1054 2024-04-02 Iain Sandoe <iain@sandoe.co.uk>
1056 * config/darwin.cc (darwin_override_options): Reduce the debug
1057 level to 2 if dsymutil cannot handle .macinfo sections.
1059 2024-04-02 Yang Yujie <yangyujie@loongson.cn>
1061 * config/loongarch/t-loongarch: Add loongarch-def-arrays.h
1062 to OPTION_H_EXTRA.
1064 2024-04-02 mengqinggang <mengqinggang@loongson.cn>
1065 Lulu Cheng <chenglulu@loongson.cn>
1066 Xi Ruoyao <xry111@xry111.site>
1068 * config.gcc: Add --with-tls option to change TLS flavor.
1069 * config/loongarch/genopts/loongarch.opt.in: Add -mtls-dialect to
1070 configure TLS flavor.
1071 * config/loongarch/loongarch-def.h (struct loongarch_target): Add
1072 tls_dialect.
1073 * config/loongarch/loongarch-driver.cc (la_driver_init): Add tls
1074 flavor.
1075 * config/loongarch/loongarch-opts.cc (loongarch_init_target): Add
1076 tls_dialect.
1077 (loongarch_config_target): Ditto.
1078 (loongarch_update_gcc_opt_status): Ditto.
1079 * config/loongarch/loongarch-opts.h (loongarch_init_target): Ditto.
1080 (TARGET_TLS_DESC): New define.
1081 * config/loongarch/loongarch.cc (loongarch_symbol_insns): Add TLS
1082 DESC instructions sequence length.
1083 (loongarch_legitimize_tls_address): New TLS DESC instruction sequence.
1084 (loongarch_option_override_internal): Add la_opt_tls_dialect.
1085 (loongarch_option_restore): Add la_target.tls_dialect.
1086 * config/loongarch/loongarch.md (@got_load_tls_desc<mode>): Normal
1087 code model for TLS DESC.
1088 (got_load_tls_desc_off64): Extreme cmode model for TLS DESC.
1089 * config/loongarch/loongarch.opt: Regenerate.
1090 * config/loongarch/loongarch.opt.urls: Ditto.
1091 * doc/invoke.texi: Add a description of the compilation option
1092 '-mtls-dialect={trad,desc}'.
1094 2024-04-02 Lulu Cheng <chenglulu@loongson.cn>
1096 * config/loongarch/loongarch.opt.urls: Regenerate.
1098 2024-04-01 Yang Yujie <yangyujie@loongson.cn>
1100 * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]recip as
1101 aliases to -mrecip={all,none}, respectively.
1102 * config/loongarch/loongarch.opt: Regenerate.
1103 * config/loongarch/loongarch-def.h (ABI_FPU_64): Rename to...
1104 (ABI_FPU64_P): ...this.
1105 (ABI_FPU_32): Rename to...
1106 (ABI_FPU32_P): ...this.
1107 (ABI_FPU_NONE): Rename to...
1108 (ABI_NOFPU_P): ...this.
1109 (ABI_LP64_P): Define.
1110 * config/loongarch/loongarch.cc (loongarch_init_print_operand_punct):
1111 Merged into loongarch_global_init.
1112 (loongarch_cpu_option_override): Renamed to
1113 loongarch_target_option_override.
1114 (loongarch_option_override_internal): Move the work after
1115 loongarch_config_target into loongarch_target_option_override.
1116 (loongarch_global_init): Define.
1117 (INIT_TARGET_FLAG): Move to loongarch-opts.cc.
1118 (loongarch_option_override): Call loongarch_global_init
1119 separately.
1120 * config/loongarch/loongarch-opts.cc (loongarch_parse_mrecip_scheme):
1121 Split the parsing of -mrecip=<string> from
1122 loongarch_option_override_internal.
1123 (loongarch_generate_mrecip_scheme): Define. Split from
1124 loongarch_option_override_internal.
1125 (loongarch_target_option_override): Define. Renamed from
1126 loongarch_cpu_option_override.
1127 (loongarch_init_misc_options): Define. Split from
1128 loongarch_option_override_internal.
1129 (INIT_TARGET_FLAG): Move from loongarch.cc.
1130 * config/loongarch/loongarch-opts.h (loongarch_target_option_override):
1131 New prototype.
1132 (loongarch_parse_mrecip_scheme): New prototype.
1133 (loongarch_init_misc_options): New prototype.
1134 (TARGET_ABI_LP64): Simplify with ABI_LP64_P.
1135 * config/loongarch/loongarch.h (TARGET_RECIP_DIV): Simplify.
1136 Do not reference specific CPU architecture (LA664).
1137 (TARGET_RECIP_SQRT): Same.
1138 (TARGET_RECIP_RSQRT): Same.
1139 (TARGET_RECIP_VEC_DIV): Same.
1140 (TARGET_RECIP_VEC_SQRT): Same.
1141 (TARGET_RECIP_VEC_RSQRT): Same.
1143 2024-04-01 Lulu Cheng <chenglulu@loongson.cn>
1145 * doc/invoke.texi: Add descriptions for the compilation
1146 options.
1148 2024-03-31 Jeff Law <jlaw@ventanamicro.com>
1150 * config/riscv/xiangshan.md (xiangshan_jump): Add branch, jalr, ret
1151 and sfb_alu.
1153 2024-03-31 Pan Li <pan2.li@intel.com>
1155 * config/riscv/riscv-vector-builtins.cc (expand_builtin): Take
1156 the term built-in over builtin.
1158 2024-03-31 Pan Li <pan2.li@intel.com>
1160 * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
1161 Remove unused var decl.
1163 2024-03-30 Xi Ruoyao <xry111@xry111.site>
1165 PR target/114175
1166 * config/mips/mips.cc (mips_setup_incoming_varargs): Only skip
1167 mips_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P
1168 functions if arg.type is NULL.
1170 2024-03-29 Andrew Pinski <quic_apinski@quicinc.com>
1172 * lto-compress.cc (lto_end_uncompression): Use
1173 fatal_error instead of internal_error when ZSTD
1174 is not enabled.
1176 2024-03-28 Jeff Law <jlaw@ventanamicro.com>
1178 * config/h8300/extensions.md (zero_extendqihi*): Add output
1179 template for reg->reg case where the regs don't match.
1181 2024-03-28 Gaius Mulley <(no_default)>
1183 PR modula2/114517
1184 * doc/gm2.texi: Mention gm2 treats a # in the first column
1185 as a preprocessor directive unless -fno-cpp is supplied.
1187 2024-03-28 Jakub Jelinek <jakub@redhat.com>
1189 * predict.cc (estimate_bb_frequencies): Fix comment typo,
1190 scalling -> scaling.
1192 2024-03-28 Jakub Jelinek <jakub@redhat.com>
1194 PR tree-optimization/112303
1195 * profile-count.h (profile_count::operator+): Perform
1196 addition in uint64_t variable and set m_val to MIN of that
1197 val and max_count.
1198 (profile_count::operator+=): Likewise.
1199 (profile_count::operator-=): Formatting fix.
1200 (profile_count::apply_probability): Use safe_scale_64bit
1201 even in the int overload.
1203 2024-03-28 Jan Hubicka <jh@suse.cz>
1205 PR middle-end/113907
1206 * ipa-icf.cc (sem_function::init): Hash PHI operands
1207 (sem_function::compare_phi_node): Add argument about preserving order
1209 2024-03-28 Richard Biener <rguenther@suse.de>
1211 PR middle-end/114480
1212 * cfganal.cc (compute_idf): Use simpler bitmap iteration,
1213 touch work_set only when phi_insertion_points changed.
1215 2024-03-28 Palmer Dabbelt <palmer@rivosinc.com>
1217 * config/riscv/riscv.h (REGISTER_NAMES): Add vxsat.
1219 2024-03-27 Segher Boessenkool <segher@kernel.crashing.org>
1221 PR rtl-optimization/101523
1222 * combine.cc (try_combine): Don't do a 2-insn combination if
1223 it does not in fact change I2.
1225 2024-03-27 Jakub Jelinek <jakub@redhat.com>
1227 * doc/invoke.texi (Spec Files): Use @var{S} instead of S,
1228 @var{X} instead of X etc. for other placeholders.
1230 2024-03-27 Richard Biener <rguenther@suse.de>
1232 PR tree-optimization/114057
1233 * tree-vect-slp.cc (vect_bb_slp_mark_live_stmts): Mark
1234 BB reduction remain defs as scalar uses.
1236 2024-03-27 Victor Do Nascimento <victor.donascimento@arm.com>
1238 * config/aarch64/aarch64-option-extensions.def (rcpc3):
1239 Fix FEATURE_STRING field to "lrcpc3".
1241 2024-03-27 Victor Do Nascimento <victor.donascimento@arm.com>
1243 * config/aarch64/aarch64-option-extensions.def: Add LSE128
1244 AARCH64_OPT_EXTENSION, adding it as a dependency for the D128
1245 feature.
1246 * doc/invoke.texi (AArch64 Options): Document +lse128.
1248 2024-03-26 Richard Sandiford <richard.sandiford@arm.com>
1250 * config/aarch64/aarch64-feature-deps.h: Use constexpr for
1251 out-of-line statics.
1253 2024-03-26 Cupertino Miranda <cupertino.miranda@oracle.com>
1255 PR target/114431
1256 * btfout.cc (get_name_for_datasec_entry): Add function.
1257 (btf_asm_datasec_entry): Print label when possible.
1259 2024-03-26 Richard Ball <richard.ball@arm.com>
1261 PR target/114272
1262 * config/aarch64/aarch64-cores.def (AARCH64_CORE):
1263 Change SCHEDULER_IDENT from cortexa55 to cortexa53
1264 for Cortex-A510 and Cortex-A520.
1266 2024-03-26 Jakub Jelinek <jakub@redhat.com>
1268 PR middle-end/111151
1269 * fold-const.cc (extract_muldiv_1) <case MAX_EXPR>: Punt for
1270 MULT_EXPR altogether, or for MAX_EXPR if c is -1.
1272 2024-03-26 Jakub Jelinek <jakub@redhat.com>
1274 PR sanitizer/111736
1275 * tsan.cc (instrument_expr): Punt on non-generic address space
1276 accesses.
1278 2024-03-26 Richard Biener <rguenther@suse.de>
1280 PR tree-optimization/114471
1281 * tree-vect-stmts.cc (vectorizable_operation): Verify operand
1282 types are compatible with the result type.
1284 2024-03-26 Richard Biener <rguenther@suse.de>
1286 PR tree-optimization/114464
1287 * tree-vect-loop.cc (vectorizable_recurr): Verify the latch
1288 vector type is compatible with what we chose for the recurrence.
1290 2024-03-26 Jakub Jelinek <jakub@redhat.com>
1292 * cfgloopmanip.cc (update_loop_exit_probability_scale_dom_bbs):
1293 Fix comment typo - multple -> multiple.
1294 * config/i386/x86-tune.def (X86_TUNE_ACCUMULATE_OUTGOING_ARGS):
1295 Likewise.
1297 2024-03-26 YunQiang Su <syq@gcc.gnu.org>
1299 * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Predefine
1300 __mips_strict_alignment if STRICT_ALIGNMENT.
1302 2024-03-25 Richard Biener <rguenther@suse.de>
1304 * config.gcc (amdgcn): Add gfx1036 entries.
1305 * config/gcn/gcn-hsa.h (NO_XNACK): Likewise.
1306 (gcn_local_sym_hash): Likewise.
1307 * config/gcn/gcn-opts.h (enum processor_type): Likewise.
1308 (TARGET_GFX1036): New macro.
1309 * config/gcn/gcn.cc (gcn_option_override): Handle gfx1036.
1310 (gcn_omp_device_kind_arch_isa): Likewise.
1311 (output_file_start): Likewise.
1312 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Add __gfx1036__.
1313 (TARGET_CPU_CPP_BUILTINS): Rename __gfx1030 to __gfx1030__.
1314 * config/gcn/gcn.opt: Add gfx1036.
1315 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1036): New.
1316 (main): Handle gfx1036.
1317 * config/gcn/t-omp-device: Add gfx1036 isa.
1318 * doc/install.texi (amdgcn): Add gfx1036.
1319 * doc/invoke.texi (-march): Likewise.
1321 2024-03-25 Pan Li <pan2.li@intel.com>
1323 * config/riscv/riscv-c.cc (riscv_pragma_intrinsic): Remove error
1324 when V is disabled and init the RVV types and intrinic APIs.
1325 * config/riscv/riscv-vector-builtins.cc (expand_builtin): Report
1326 error if V ext is disabled.
1327 * config/riscv/riscv.cc (riscv_return_value_is_vector_type_p):
1328 Ditto.
1329 (riscv_arguments_is_vector_type_p): Ditto.
1330 (riscv_vector_cc_function_p): Ditto.
1331 * config/riscv/riscv_vector.h: Remove error if V is disable.
1333 2024-03-23 John David Anglin <danglin@gcc.gnu.org>
1335 * config/pa/pa.cc (pa_output_global_address): Handle
1336 UNSPEC_DLTIND14R addresses.
1337 * config/pa/pa.h (PRINT_OPERAND_ADDRESS): Output "RT'" for
1338 UNSPEC_DLTIND14R address.
1340 2024-03-23 Jakub Jelinek <jakub@redhat.com>
1342 PR tree-optimization/114433
1343 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): For
1344 m_bitfld_load check save_first rather than m_first.
1346 2024-03-23 Jakub Jelinek <jakub@redhat.com>
1348 PR tree-optimization/114425
1349 * gimple-lower-bitint.cc (build_bitint_stmt_ssa_conflicts): Handle
1350 _Complex large/huge _BitInt types like the large/huge _BitInt types.
1352 2024-03-23 Jakub Jelinek <jakub@redhat.com>
1354 PR middle-end/111683
1355 * tree-predcom.cc (pcom_worker::suitable_component_p): If has_write
1356 and comp_step is RS_NONZERO, return false if any reference in the
1357 component doesn't have DR_STEP a multiple of access size.
1359 2024-03-23 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
1361 * config/xtensa/xtensa.md: Add new split pattern described above.
1363 2024-03-22 Georg-Johann Lay <avr@gjlay.de>
1365 * config/avr/avr.cc (avr_set_current_function): Adjust diagnostic
1366 for deprecated SIGNAL and INTERRUPT usage without respective header.
1368 2024-03-22 Andrew Stubbs <ams@baylibre.com>
1370 * config/gcn/gcn.md (*memory_barrier): Split into RDNA and !RDNA.
1371 (atomic_load<mode>): Adjust RDNA cache settings.
1372 (atomic_store<mode>): Likewise.
1373 (atomic_exchange<mode>): Likewise.
1375 2024-03-22 Andrew Stubbs <ams@baylibre.com>
1377 * config/gcn/gcn.cc (gcn_vectorize_preferred_simd_mode): Prefer V32 on
1378 RDNA devices.
1380 2024-03-22 Andrew Stubbs <ams@baylibre.com>
1382 * config.gcc (amdgcn): Add gfx1103 entries.
1383 * config/gcn/gcn-hsa.h (NO_XNACK): Likewise.
1384 (gcn_local_sym_hash): Likewise.
1385 * config/gcn/gcn-opts.h (enum processor_type): Likewise.
1386 (TARGET_GFX1103): New macro.
1387 * config/gcn/gcn.cc (gcn_option_override): Handle gfx1103.
1388 (gcn_omp_device_kind_arch_isa): Likewise.
1389 (output_file_start): Likewise.
1390 (gcn_hsa_declare_function_name): Use TARGET_RDNA3, not just gfx1100.
1391 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Add __gfx1103__.
1392 * config/gcn/gcn.opt: Add gfx1103.
1393 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1103): New.
1394 (main): Handle gfx1103.
1395 * config/gcn/t-omp-device: Add gfx1103 isa.
1396 * doc/install.texi (amdgcn): Add gfx1103.
1397 * doc/invoke.texi (-march): Likewise.
1399 2024-03-22 Andrew Stubbs <ams@baylibre.com>
1401 * dojump.cc (do_compare_rtx_and_jump): Clear excess bits in vector
1402 bitmasks.
1403 (do_compare_and_jump): Remove now-redundant similar code.
1404 * internal-fn.cc (expand_fn_using_insn): Clear excess bits in vector
1405 bitmasks.
1406 (add_mask_and_len_args): Likewise.
1408 2024-03-22 Pan Li <pan2.li@intel.com>
1410 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add pre-define
1411 macro __riscv_v_fixed_vlen when zvl.
1412 * config/riscv/riscv.cc (riscv_handle_rvv_vector_bits_attribute):
1413 New static func to take care of the RVV types decorated by
1414 the attributes.
1416 2024-03-22 Andrew Pinski <quic_apinski@quicinc.com>
1418 PR c/109619
1419 * builtins.cc (fold_builtin_1): Use error_operand_p
1420 instead of checking against ERROR_MARK.
1421 (fold_builtin_2): Likewise.
1422 (fold_builtin_3): Likewise.
1424 2024-03-22 Jakub Jelinek <jakub@redhat.com>
1426 PR sanitizer/111736
1427 * ubsan.cc (ubsan_expand_null_ifn, instrument_mem_ref): Avoid
1428 SANITIZE_NULL instrumentation for non-generic address spaces
1429 for which targetm.addr_space.zero_address_valid (as) is true.
1431 2024-03-22 Jakub Jelinek <jakub@redhat.com>
1433 PR tree-optimization/114405
1434 * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
1435 Set rprec to limb_prec rather than 0 if tprec is divisible by
1436 limb_prec. In the last bf_cur handling, set rprec to (tprec + bo_bit)
1437 % limb_prec rather than tprec % limb_prec and use just rprec instead
1438 of rprec + bo_bit. For build_bit_field_ref offset, divide
1439 (tprec + bo_bit) by limb_prec rather than just tprec.
1441 2024-03-22 Christoph Müllner <christoph.muellner@vrull.eu>
1443 PR target/114194
1444 * config/riscv/vector-iterators.md: Split VI into VI_FRAC and VI_NOFRAC.
1445 Only include VI_NOFRAC in V_VLS without TARGET_XTHEADVECTOR.
1447 2024-03-22 Jeff Law <jlaw@ventanamicro.com>
1449 * config/riscv/riscv.cc (riscv_expand_prologue): Add missing stack
1450 tie for scalable and final stack adjustment if needed.
1451 Co-authored-by: Raphael Zinsly <rzinsly@ventanamicro.com>
1453 2024-03-22 Pan Li <pan2.li@intel.com>
1455 PR target/114352
1456 * common/config/riscv/riscv-common.cc (struct riscv_func_target_info):
1457 New struct for func decl and target name.
1458 (struct riscv_func_target_hasher): New hasher for hash table mapping
1459 from the fn_decl to fn_target_name.
1460 (riscv_func_decl_hash): New func to compute the hash for fn_decl.
1461 (riscv_func_target_hasher::hash): New func to impl hash interface.
1462 (riscv_func_target_hasher::equal): New func to impl equal interface.
1463 (riscv_cmdline_subset_list): New static var for cmdline subset list.
1464 (riscv_func_target_table_lazy_init): New func to lazy init the func
1465 target hash table.
1466 (riscv_func_target_get): New func to get target name from hash table.
1467 (riscv_func_target_put): New func to put target name into hash table.
1468 (riscv_func_target_remove_and_destory): New func to remove target
1469 info from the hash table and destory it.
1470 (riscv_parse_arch_string): Set the static var cmdline_subset_list.
1471 * config/riscv/riscv-subset.h (riscv_cmdline_subset_list): New static
1472 var for cmdline subset list.
1473 (riscv_func_target_get): New func decl.
1474 (riscv_func_target_put): Ditto.
1475 (riscv_func_target_remove_and_destory): Ditto.
1476 * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
1477 Take cmdline_subset_list instead of current_subset_list when clone.
1478 (riscv_process_target_attr): Record the func target info to hash table.
1479 (riscv_option_valid_attribute_p): Add new arg tree fndel.
1480 * config/riscv/riscv.cc (riscv_declare_function_name): Consume the
1481 func target info and print the arch message.
1483 2024-03-22 Pan Li <pan2.li@intel.com>
1485 PR target/114352
1486 * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
1487 Replace implied, combine and check to func finalize.
1488 (riscv_subset_list::finalize): New func impl to take care of
1489 implied, combine ext and related checks.
1490 * config/riscv/riscv-subset.h: Add func decl for finalize.
1491 * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
1492 Finalize the ext before return succeed.
1493 * config/riscv/riscv.cc (riscv_set_current_function): Reinit the
1494 machine mode before when set cur function.
1496 2024-03-21 Andrew Stubbs <ams@baylibre.com>
1498 * config/gcn/gcn.cc (gcn_expand_builtin_1): Comment correction.
1500 2024-03-21 Andrew Stubbs <ams@baylibre.com>
1502 * config/gcn/gcn-hsa.h (ASM_SPEC): Pass -mattr=+cumode.
1504 2024-03-21 Andrew Stubbs <ams@baylibre.com>
1506 * config/gcn/gcn-run.cc (main): Add an hsa_memory_free calls for each
1507 device_malloc call.
1509 2024-03-21 liuhongt <hongtao.liu@intel.com>
1511 PR tree-optimization/114396
1512 * tree-vect-loop.cc (vect_peel_nonlinear_iv_init): Pass utype
1513 and true to wi::from_mpz.
1515 2024-03-21 Richard Biener <rguenther@suse.de>
1517 PR tree-optimization/111736
1518 * asan.cc (instrument_derefs): Do not instrument accesses
1519 to non-generic address-spaces.
1521 2024-03-21 Richard Biener <rguenther@suse.de>
1523 PR tree-optimization/113727
1524 * tree-sra.cc (analyze_access_subtree): Do not allow
1525 replacements in subtrees when grp_partial_lhs.
1527 2024-03-21 liuhongt <hongtao.liu@intel.com>
1529 PR middle-end/114347
1530 * doc/invoke.texi: Document -fexcess-precision=16.
1532 2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
1534 * config/bpf/core-builtins.cc (bpf_core_get_index): Check if
1535 field contains a DECL_NAME.
1537 2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
1539 * config/bpf/btfext-out.cc (cpf_core_reloc_add): Correct for new code.
1540 Add assert to validate the string is set.
1541 * config/bpf/core-builtins.cc (cr_final): Make string struct
1542 field as const.
1543 (process_enum_value): Correct for field type change.
1544 (process_type): Set access string to "0".
1546 2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
1548 * config/bpf/core-builtins.cc (core_field_info): Add
1549 support for POINTER_PLUS_EXPR in the root of the field expression.
1550 (bpf_core_get_index): Likewise.
1551 (pack_field_expr): Make the BTF type to point to the structure
1552 related node, instead of its pointer type.
1553 (make_core_safe_access_index): Correct to new code.
1555 2024-03-20 Xi Ruoyao <xry111@xry111.site>
1557 PR target/114407
1558 * config/loongarch/loongarch-opts.cc (loongarch_config_target):
1559 Fix typo in diagnostic message, enabing -> enabling.
1561 2024-03-20 Jakub Jelinek <jakub@redhat.com>
1563 PR target/114175
1564 * config/visium/visium.cc (visium_setup_incoming_varargs): Only skip
1565 TARGET_FUNCTION_ARG_ADVANCE for TYPE_NO_NAMED_ARGS_STDARG_P functions
1566 if arg.type is NULL.
1568 2024-03-20 Jakub Jelinek <jakub@redhat.com>
1570 PR target/114175
1571 * config/nios2/nios2.cc (nios2_setup_incoming_varargs): Only skip
1572 nios2_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
1573 if arg.type is NULL.
1575 2024-03-20 Jakub Jelinek <jakub@redhat.com>
1577 PR target/114175
1578 * config/nds32/nds32.cc (nds32_setup_incoming_varargs): Only skip
1579 function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
1580 if arg.type is NULL.
1582 2024-03-20 Jakub Jelinek <jakub@redhat.com>
1584 PR target/114175
1585 * config/m32r/m32r.cc (m32r_setup_incoming_varargs): Only skip
1586 function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
1587 if arg.type is NULL.
1589 2024-03-20 Jakub Jelinek <jakub@redhat.com>
1591 PR target/114175
1592 * config/ft32/ft32.cc (ft32_setup_incoming_varargs): Only skip
1593 function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
1594 if arg.type is NULL.
1596 2024-03-20 Jakub Jelinek <jakub@redhat.com>
1598 PR target/114175
1599 * config/epiphany/epiphany.cc (epiphany_setup_incoming_varargs): Only
1600 skip function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
1601 if arg.type is NULL.
1603 2024-03-20 Jakub Jelinek <jakub@redhat.com>
1605 PR target/114175
1606 * config/csky/csky.cc (csky_setup_incoming_varargs): Only skip
1607 csky_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
1608 if arg.type is NULL.
1610 2024-03-20 Yury Khrustalev <yury.khrustalev@arm.com>
1612 * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
1614 2024-03-20 Jakub Jelinek <jakub@redhat.com>
1616 PR tree-optimization/114365
1617 * gimple-lower-bitint.cc (bitint_large_huge::handle_load): When adding
1618 a PHI node, set iv2 to its result afterwards.
1620 2024-03-20 Jakub Jelinek <jakub@redhat.com>
1622 * tree-ssa-loop-ch.cc (update_profile_after_ch): Fix comment typo:
1623 probabbility -> probability.
1624 (ch_base::copy_headers): Fix comment typo: itrations -> iterations.
1626 2024-03-20 Jakub Jelinek <jakub@redhat.com>
1628 PR bootstrap/114369
1629 * system.h (vec_step): Define to vec_step_ when compiling
1630 with clang on PowerPC.
1632 2024-03-20 demin.han <demin.han@starfivetech.com>
1634 PR target/112651
1635 * config/riscv/riscv-opts.h (enum riscv_autovec_lmul_enum): Rename
1636 (enum rvv_max_lmul_enum): Ditto
1637 (TARGET_MAX_LMUL): Ditto
1638 * config/riscv/riscv-v.cc (preferred_simd_mode): Ditto
1639 * config/riscv/riscv-vector-costs.cc (costs::record_potential_unexpected_spills): Ditto
1640 (costs::better_main_loop_than_p): Ditto
1641 * config/riscv/riscv.opt: Replace -param=riscv-autovec-lmul with -mrvv-max-lmul
1643 2024-03-20 Richard Biener <rguenther@suse.de>
1645 PR middle-end/113396
1646 * tree-dfa.cc (get_ref_base_and_extent): Use index range
1647 bounds only if they fit within the address-range constraints
1648 of offset_int.
1650 2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
1652 * config/loongarch/loongarch.cc
1653 (loongarch_hard_regno_mode_ok_uncached): Combine UNITS_PER_FP_REG and
1654 UNITS_PER_FPREG macros.
1655 (loongarch_hard_regno_nregs): Ditto.
1656 (loongarch_class_max_nregs): Ditto.
1657 (loongarch_get_separate_components): Ditto.
1658 (loongarch_process_components): Ditto.
1659 * config/loongarch/loongarch.h (UNITS_PER_FPREG): Ditto.
1660 (UNITS_PER_HWFPVALUE): Ditto.
1661 (UNITS_PER_FPVALUE): Ditto.
1663 2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
1665 * config/loongarch/lasx.md (vec_cmp<mode><mode256_i>): Remove checking
1666 of loongarch_expand_vec_cmp()'s return value.
1667 (vec_cmpu<ILASX:mode><mode256_i>): Ditto.
1668 * config/loongarch/lsx.md (vec_cmp<mode><mode_i>): Ditto.
1669 (vec_cmpu<ILSX:mode><mode_i>): Ditto.
1670 * config/loongarch/loongarch-protos.h
1671 (loongarch_expand_vec_cmp): Change loongarch_expand_vec_cmp()'s return
1672 type from bool to void.
1673 * config/loongarch/loongarch.cc (loongarch_expand_vec_cmp): Ditto.
1675 2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
1677 * config/loongarch/loongarch-protos.h
1678 (loongarch_cfun_has_cprestore_slot_p): Delete.
1679 (loongarch_adjust_insn_length): Delete.
1680 (current_section_name): Delete.
1681 (loongarch_split_symbol_type): Delete.
1682 * config/loongarch/loongarch.cc
1683 (loongarch_case_values_threshold): Delete.
1684 (loongarch_spill_class): Delete.
1685 (TARGET_OPTAB_SUPPORTED_P): Delete.
1686 (TARGET_CASE_VALUES_THRESHOLD): Delete.
1687 (TARGET_SPILL_CLASS): Delete.
1689 2024-03-20 Lewis Hyatt <lhyatt@gmail.com>
1691 PR c++/111918
1692 * diagnostic-core.h (enum diagnostic_t): Add DK_ANY special flag.
1693 * diagnostic.cc (diagnostic_option_classifier::classify_diagnostic):
1694 Make use of DK_ANY to indicate a diagnostic was initially enabled.
1695 (diagnostic_context::diagnostic_enabled): Do not change the type of
1696 a diagnostic if the saved classification is type DK_ANY.
1698 2024-03-19 Martin Jambor <mjambor@suse.cz>
1700 PR ipa/108802
1701 PR ipa/114254
1702 * ipa-prop.cc (ipa_get_stmt_member_ptr_load_param): Fix case looking
1703 at COMPONENT_REFs directly from a PARM_DECL, also recognize loads from
1704 a pointer parameter.
1705 (ipa_analyze_indirect_call_uses): Also recognize loads from a pointer
1706 parameter, also recognize the case when pfn pointer is loaded in its
1707 own BB.
1709 2024-03-19 Vladimir N. Makarov <vmakarov@redhat.com>
1711 PR target/99829
1712 * lra-constraints.cc (lra_constraints): Prevent removing insn
1713 with reverse equivalence to memory if the memory was reloaded.
1715 2024-03-19 David Malcolm <dmalcolm@redhat.com>
1717 PR middle-end/114348
1718 * diagnostic-format-json.cc
1719 (json_stderr_output_format::machine_readable_stderr_p): New.
1720 (json_file_output_format::machine_readable_stderr_p): New.
1721 * diagnostic-format-sarif.cc
1722 (sarif_stream_output_format::machine_readable_stderr_p): New.
1723 (sarif_file_output_format::machine_readable_stderr_p): New.
1724 * diagnostic.cc (diagnostic_context::action_after_output): Move
1725 "fnotice" to before "finish" call, so that we still have the
1726 diagnostic_context.
1727 (fnotice): Bail out if the user requested one of the
1728 machine-readable diagnostic output formats on stderr.
1729 * diagnostic.h
1730 (diagnostic_output_format::machine_readable_stderr_p): New pure
1731 virtual function.
1732 (diagnostic_text_output_format::machine_readable_stderr_p): New.
1733 (diagnostic_context::get_output_format): New accessor.
1735 2024-03-19 Edwin Lu <ewlu@rivosinc.com>
1737 PR target/114175
1738 * config/riscv/riscv.cc (riscv_setup_incoming_varargs): Only skip
1739 riscv_funciton_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
1740 if arg.type is NULL
1742 2024-03-19 Jonathan Wakely <jwakely@redhat.com>
1744 * doc/install.texi (Prerequisites): Document use of autogen for
1745 libstdc++.
1747 2024-03-19 Richard Biener <rguenther@suse.de>
1749 PR tree-optimization/114151
1750 PR tree-optimization/114269
1751 PR tree-optimization/114322
1752 PR tree-optimization/114074
1753 * tree-chrec.cc (chrec_fold_multiply): Restrict the use of
1754 unsigned arithmetic when actual overflow on constant operands
1755 is observed.
1757 2024-03-19 Jakub Jelinek <jakub@redhat.com>
1759 PR target/114175
1760 * config/arc/arc.cc (arc_setup_incoming_varargs): Only skip
1761 arc_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
1762 if arg.type is NULL.
1764 2024-03-19 Xi Ruoyao <xry111@xry111.site>
1766 PR target/114175
1767 * config/loongarch/loongarch.cc
1768 (loongarch_setup_incoming_varargs): Only skip
1769 loongarch_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P
1770 functions if arg.type is NULL.
1772 2024-03-19 Christophe Lyon <christophe.lyon@linaro.org>
1774 PR target/114323
1775 * config/arm/arm-mve-builtins.cc
1776 (function_instance::reads_global_state_p): Take CP_READ_MEMORY
1777 into account.
1779 2024-03-19 Jakub Jelinek <jakub@redhat.com>
1781 PR target/114175
1782 * config/alpha/alpha.cc (alpha_setup_incoming_varargs): Only skip
1783 function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
1784 if arg.type is NULL.
1786 2024-03-19 Jakub Jelinek <jakub@redhat.com>
1788 PR target/114175
1789 * config/rs6000/rs6000-call.cc (setup_incoming_varargs): Only skip
1790 rs6000_function_arg_advance_1 for TYPE_NO_NAMED_ARGS_STDARG_P functions
1791 if arg.type is NULL.
1793 2024-03-19 Richard Biener <rguenther@suse.de>
1795 PR tree-optimization/114375
1796 * tree-vect-slp.cc (vect_build_slp_tree_2): Compute the
1797 load permutation for masked loads but reject it when any
1798 such is necessary.
1799 * tree-vect-stmts.cc (vectorizable_load): Reject masked
1800 VMAT_ELEMENTWISE and VMAT_STRIDED_SLP as those are not
1801 supported.
1803 2024-03-19 Mary Bennett <mary.bennett@embecosm.com>
1805 * common/config/riscv/riscv-common.cc: Create XCVbi extension
1806 support.
1807 * config/riscv/riscv.opt: Likewise.
1808 * config/riscv/corev.md: Implement cv_branch<mode> pattern
1809 for cv.beqimm and cv.bneimm.
1810 * config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
1811 branch instruction pattern.
1812 * config/riscv/constraints.md: Implement constraints
1813 cv_bi_s5 - signed 5-bit immediate.
1814 * config/riscv/predicates.md: Implement predicate
1815 const_int5s_operand - signed 5 bit immediate.
1816 * doc/sourcebuild.texi: Add XCVbi documentation.
1818 2024-03-19 Chen Jiawei <jiawei@iscas.ac.cn>
1820 * config/riscv/riscv-cores.def (RISCV_TUNE): New def.
1821 (RISCV_CORE): Ditto.
1822 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): New
1823 option.
1824 * config/riscv/riscv.cc: New def.
1825 * config/riscv/riscv.md: New include.
1826 * config/riscv/xiangshan.md: New file.
1828 2024-03-18 David Malcolm <dmalcolm@redhat.com>
1830 PR analyzer/110902
1831 PR analyzer/110928
1832 PR analyzer/111305
1833 PR analyzer/111441
1834 * selftest.h (ASSERT_NE_AT): New macro.
1836 2024-03-18 Uros Bizjak <ubizjak@gmail.com>
1838 PR target/111822
1839 * config/i386/i386-features.cc (smode_convert_cst): New function
1840 to handle SImode, DImode and TImode immediates, generalized from
1841 timode_convert_cst.
1842 (timode_convert_cst): Remove.
1843 (scalar_chain::convert_op): Unify from
1844 general_scalar_chain::convert_op and timode_scalar_chain::convert_op.
1845 (general_scalar_chain::convert_op): Remove.
1846 (timode_scalar_chain::convert_op): Remove.
1847 (timode_scalar_chain::convert_insn): Update the call to
1848 renamed timode_convert_cst.
1849 * config/i386/i386-features.h (class scalar_chain):
1850 Redeclare convert_op as protected class member.
1851 (class general_calar_chain): Remove convert_op.
1852 (class timode_scalar_chain): Ditto.
1854 2024-03-18 Jan Hubicka <jh@suse.cz>
1856 * config/i386/zn4zn5.md: Add file missed in the previous commit.
1858 2024-03-18 Jan Hubicka <jh@suse.cz>
1859 Karthiban Anbazhagan <Karthiban.Anbazhagan@amd.com>
1861 * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver5.
1862 * common/config/i386/i386-common.cc (processor_names): Add znver5.
1863 (processor_alias_table): Likewise.
1864 * common/config/i386/i386-cpuinfo.h (processor_types): Add new zen
1865 family.
1866 (processor_subtypes): Add znver5.
1867 * config.gcc (x86_64-*-* |...): Likewise.
1868 * config/i386/driver-i386.cc (host_detect_local_cpu): Let
1869 march=native detect znver5 cpu's.
1870 * config/i386/i386-c.cc (ix86_target_macros_internal): Add
1871 znver5.
1872 * config/i386/i386-options.cc (m_ZNVER5): New definition
1873 (processor_cost_table): Add znver5.
1874 * config/i386/i386.cc (ix86_reassociation_width): Likewise.
1875 * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER5
1876 (PTA_ZNVER5): New definition.
1877 * config/i386/i386.md (define_attr "cpu"): Add znver5.
1878 (Scheduling descriptions) Add znver5.md.
1879 * config/i386/x86-tune-costs.h (znver5_cost): New definition.
1880 * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver5.
1881 (ix86_adjust_cost): Likewise.
1882 * config/i386/x86-tune.def (avx512_move_by_pieces): Add m_ZNVER5.
1883 (avx512_store_by_pieces): Add m_ZNVER5.
1884 * doc/extend.texi: Add znver5.
1885 * doc/invoke.texi: Likewise.
1886 * config/i386/znver4.md: Rename to zn4zn5.md; combine znver4 and znver5 Scheduler.
1888 2024-03-18 Georg-Johann Lay <avr@gjlay.de>
1890 * config/avr/constraints.md (CX2, CX3, CX4): New constraints.
1891 * config/avr/avr-protos.h (avr_xor_noclobber_dconst): New proto.
1892 * config/avr/avr.cc (avr_xor_noclobber_dconst): New function.
1893 * config/avr/avr.md (xorhi3, *xorhi3): Add "d,0,CX2,X" alternative.
1894 (xorpsi3, *xorpsi3): Add "d,0,CX3,X" alternative.
1895 (xorsi3, *xorsi3): Add "d,0,CX4,X" alternative.
1897 2024-03-18 liuhongt <hongtao.liu@intel.com>
1899 PR target/114334
1900 * config/i386/i386.md (mode): Add new number V8BF,V16BF,V32BF.
1901 (MODEF248): New mode iterator.
1902 (ssevecmodesuffix): Hanlde BF and HF.
1903 * config/i386/sse.md (andnot<mode>3): Extend to HF/BF.
1904 (<code><mode>3): Ditto.
1906 2024-03-18 John David Anglin <danglin@gcc.gnu.org>
1908 PR rtl-optimization/112415
1909 * config/pa/pa.cc (pa_emit_move_sequence): Revise condition
1910 for symbolic memory operands.
1911 (pa_legitimate_address_p): Revise LO_SUM condition.
1912 * config/pa/pa.h (INT14_OK_STRICT): Revise define. Move
1913 comment about GNU linker to predicates.md.
1914 * config/pa/predicates.md (floating_point_store_memory_operand):
1915 Revise condition for symbolic memory operands. Update
1916 comment.
1918 2024-03-17 John David Anglin <danglin@gcc.gnu.org>
1920 * config/pa/pa.cc (pa_delegitimize_address): Delegitimize UNSPEC_TP.
1922 2024-03-16 Jakub Jelinek <jakub@redhat.com>
1924 PR target/114175
1925 * config/i386/i386.cc (ix86_setup_incoming_varargs): Only skip
1926 ix86_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
1927 if arg.type is NULL.
1929 2024-03-16 Jakub Jelinek <jakub@redhat.com>
1931 PR tree-optimization/114329
1932 * gimple-lower-bitint.cc (struct bitint_large_huge): Declare
1933 build_bit_field_ref method.
1934 (bitint_large_huge::build_bit_field_ref): New method.
1935 (bitint_large_huge::lower_mergeable_stmt): Use it.
1937 2024-03-15 YunQiang Su <syq@gcc.gnu.org>
1939 * config/riscv/riscv.opt.urls: Regenerated.
1940 * config/rs6000/sysv4.opt.urls: Likewise.
1941 * config/xtensa/xtensa.opt.urls: Likewise.
1943 2024-03-15 Jakub Jelinek <jakub@redhat.com>
1945 * lower-subreg.cc (resolve_simple_move): Fix comment typo,
1946 betwee -> between.
1947 * edit-context.cc (class line_event): Fix comment typo,
1948 betweeen -> between.
1950 2024-03-15 Jakub Jelinek <jakub@redhat.com>
1952 PR target/114339
1953 * config/i386/i386-expand.cc (ix86_expand_int_sse_cmp) <case LE>: Fix
1954 a pasto, compare code against LE rather than GE.
1956 2024-03-15 Joe Ramsay <Joe.Ramsay@arm.com>
1958 * match.pd: Fix truncation pattern for -fno-signed-zeroes
1960 2024-03-15 Jakub Jelinek <jakub@redhat.com>
1962 PR middle-end/114332
1963 * expr.cc (expand_expr_real_1): EXTEND_BITINT also CALL_EXPR results.
1965 2024-03-15 Jakub Jelinek <jakub@redhat.com>
1967 PR tree-optimization/113466
1968 * gimple-lower-bitint.cc (bitint_large_huge): Add m_returns_twice_calls
1969 member.
1970 (bitint_large_huge::bitint_large_huge): Initialize it.
1971 (bitint_large_huge::~bitint_large_huge): Release it.
1972 (bitint_large_huge::lower_call): Remember ECF_RETURNS_TWICE call stmts
1973 before which at least one statement has been inserted.
1974 (gimple_lower_bitint): Move argument loads before ECF_RETURNS_TWICE
1975 calls to a different block and add corresponding PHIs.
1977 2024-03-15 YunQiang Su <syq@gcc.gnu.org>
1979 * config/mips/mips.opt: Support -mstrict-align, and use
1980 TARGET_STRICT_ALIGN as the flag; keep -m(no-)unaligned-access
1981 as alias.
1982 * config/mips/mips.h: Use TARGET_STRICT_ALIGN.
1983 * config/mips/mips.opt.urls: Regenerate.
1984 * doc/invoke.texi: Document -m(no-)strict-algin for MIPSr6.
1986 2024-03-15 Tejas Belagod <tejas.belagod@arm.com>
1988 PR middle-end/114108
1989 * tree-vect-patterns.cc (vect_recog_abd_pattern): Call
1990 vect_convert_output with the correct vecitype.
1992 2024-03-15 Chenghui Pan <panchenghui@loongson.cn>
1994 * config/loongarch/lasx.md (lasx_xvpermi_q_<LASX:mode>):
1995 Remove masking of operand 3.
1997 2024-03-14 Jason Merrill <jason@redhat.com>
1999 * tree-core.h (enum clobber_kind): Clarify CLOBBER_OBJECT_*
2000 comments.
2002 2024-03-14 John David Anglin <danglin@gcc.gnu.org>
2004 PR target/114288
2005 * config/pa/pa.cc (pa_legitimate_address_p): Don't allow
2006 14-bit displacements before reload for modes that may use
2007 a floating-point load or store.
2009 2024-03-14 David Faust <david.faust@oracle.com>
2011 * config/bpf/bpf.h (INT8_TYPE): Change to signed char.
2013 2024-03-14 Max Filippov <jcmvbkbc@gmail.com>
2015 * config/xtensa/xtensa.md (movsi_internal): Move l32i and s32i
2016 patterns ahead of the l32i.n and s32i.n.
2018 2024-03-14 Jakub Jelinek <jakub@redhat.com>
2020 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): Fix comment typo.
2022 2024-03-14 Jakub Jelinek <jakub@redhat.com>
2024 PR middle-end/113907
2025 * ipa-icf.cc (sem_item_optimizer::merge_classes): Reset
2026 SSA_NAME_RANGE_INFO and SSA_NAME_PTR_INFO on successfully ICF merged
2027 functions.
2029 2024-03-14 Xi Ruoyao <xry111@xry111.site>
2031 * config/loongarch/loongarch.md (any_ge): Remove.
2032 (sge<u>_<X:mode><GPR:mode>): Remove.
2034 2024-03-14 Jakub Jelinek <jakub@redhat.com>
2036 PR target/114310
2037 * config/aarch64/aarch64.cc (aarch64_expand_compare_and_swap): For
2038 TImode force newval into a register.
2040 2024-03-14 Chung-Lin Tang <cltang@baylibre.com>
2042 * tree.h (OMP_CLAUSE_MAP_READONLY): New macro.
2043 (OMP_CLAUSE__CACHE__READONLY): New macro.
2044 * tree-core.h (struct GTY(()) tree_base): Adjust comments for new
2045 uses of readonly_flag bit in OMP_CLAUSE_MAP_READONLY and
2046 OMP_CLAUSE__CACHE__READONLY.
2047 * tree-pretty-print.cc (dump_omp_clause): Add support for printing
2048 OMP_CLAUSE_MAP_READONLY and OMP_CLAUSE__CACHE__READONLY.
2050 2024-03-14 Andreas Krebbel <krebbel@linux.ibm.com>
2052 * config/s390/s390.cc (s390_encode_section_info): Adjust the check
2053 for misaligned symbols.
2054 * config/s390/s390.opt: Improve documentation.
2056 2024-03-14 Jakub Jelinek <jakub@redhat.com>
2058 * gimple-iterator.cc (edge_before_returns_twice_call): Copy all
2059 flags and probability from ad_edge to e edge. If CDI_DOMINATORS
2060 are computed, recompute immediate dominator of other_edge->src
2061 and other_edge->dest.
2062 (gsi_safe_insert_before, gsi_safe_insert_seq_before): Update *iter
2063 for the returns_twice call case to the gsi_for_stmt (stmt) to deal
2064 with update it for bb splitting.
2066 2024-03-14 liuhongt <hongtao.liu@intel.com>
2068 * config/i386/i386-features.cc
2069 (general_scalar_chain::convert_op): Handle REG_EH_REGION note.
2070 (convert_scalars_to_vector): Ditto.
2071 * config/i386/i386-features.h (class scalar_chain): New
2072 memeber control_flow_insns.
2074 2024-03-13 Jakub Jelinek <jakub@redhat.com>
2076 PR middle-end/114319
2077 * gimple-ssa-store-merging.cc
2078 (imm_store_chain_info::try_coalesce_bswap): For 32-bit targets
2079 allow matching __builtin_bswap64 if there is bswapsi2 optab.
2081 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2083 * config/s390/s390.cc (s390_secondary_reload): Guard
2084 SYMBOL_FLAG_NOTALIGN2_P.
2086 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2088 * config/s390/s390-builtin-types.def: Update to reflect latest
2089 changes.
2090 * config/s390/s390-builtins.def: Streamline vector builtins with
2091 LLVM.
2093 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
2095 * config/s390/s390-builtins.def (vec_permi): Deprecate.
2096 (vec_ctd): Deprecate.
2097 (vec_ctd_s64): Deprecate.
2098 (vec_ctd_u64): Deprecate.
2099 (vec_ctsl): Deprecate.
2100 (vec_ctul): Deprecate.
2101 (vec_ld2f): Deprecate.
2102 (vec_st2f): Deprecate.
2103 (vec_insert): Deprecate overloads with bool vectors.
2105 2024-03-13 Jakub Jelinek <jakub@redhat.com>
2107 PR middle-end/114313
2108 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
2109 TYPE_SIZE of TREE_TYPE (var) rather than TYPE_SIZE of type.
2110 (bitint_large_huge::handle_load): Pass NULL_TREE rather than
2111 rhs_type to limb_access for the bitfield load cases.
2112 (bitint_large_huge::lower_mergeable_stmt): Pass NULL_TREE rather than
2113 lhs_type to limb_access if nlhs is non-NULL.
2115 2024-03-13 Jakub Jelinek <jakub@redhat.com>
2117 PR sanitizer/112709
2118 * asan.cc (maybe_create_ssa_name, maybe_cast_to_ptrmode,
2119 build_check_stmt, maybe_instrument_call, asan_expand_mark_ifn): Use
2120 gsi_safe_insert_before instead of gsi_insert_before.
2122 2024-03-13 Jakub Jelinek <jakub@redhat.com>
2124 PR sanitizer/112709
2125 * gimple-iterator.h (gsi_safe_insert_before,
2126 gsi_safe_insert_seq_before): Declare.
2127 * gimple-iterator.cc: Include gimplify.h.
2128 (edge_before_returns_twice_call, adjust_before_returns_twice_call,
2129 gsi_safe_insert_before, gsi_safe_insert_seq_before): New functions.
2130 * ubsan.cc (instrument_mem_ref, instrument_pointer_overflow,
2131 instrument_nonnull_arg, instrument_nonnull_return): Use
2132 gsi_safe_insert_before instead of gsi_insert_before.
2133 (maybe_instrument_pointer_overflow): Use force_gimple_operand,
2134 gimple_seq_add_seq_without_update and gsi_safe_insert_seq_before
2135 instead of force_gimple_operand_gsi.
2136 (instrument_object_size): Likewise. Use gsi_safe_insert_before
2137 instead of gsi_insert_before.
2139 2024-03-12 Richard Biener <rguenther@suse.de>
2141 PR tree-optimization/114121
2142 * tree-chrec.cc (chrec_fold_plus_1): Guard recursion with
2143 converted operand properly.
2144 (chrec_fold_multiply): Likewise. Handle missed recursion.
2146 2024-03-12 Jakub Jelinek <jakub@redhat.com>
2148 PR sanitizer/112709
2149 * asan.cc (has_stmt_been_instrumented_p): Don't instrument call
2150 stores on the caller side unless it is a call to a builtin or
2151 internal function or function doesn't return by hidden reference.
2152 (maybe_instrument_call): Likewise.
2153 (instrument_derefs): Instrument stores to RESULT_DECL if
2154 returning by hidden reference.
2156 2024-03-12 Jakub Jelinek <jakub@redhat.com>
2158 PR tree-optimization/114293
2159 * tree-ssa-strlen.cc (strlen_pass::handle_builtin_strlen): If
2160 max is smaller than min, set max to ~(size_t)0.
2162 2024-03-12 Pan Li <pan2.li@intel.com>
2164 * config/riscv/riscv-c.cc (riscv_ext_version_value): Fix
2165 code style greater than 80 chars.
2166 (riscv_cpu_cpp_builtins): Fix useless empty line, indent
2167 with 3 space(s) and argument unalignment.
2169 2024-03-12 Richard Biener <rguenther@suse.de>
2171 PR tree-optimization/114297
2172 * tree-vect-loop.cc (vectorizable_live_operation): Pass in the
2173 live stmts SLP node to vect_create_epilog_for_reduction.
2175 2024-03-12 Andrew Pinski <quic_apinski@quicinc.com>
2177 PR driver/114314
2178 * common.opt (fmultiflags): Add RejectNegative.
2180 2024-03-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
2182 * config/aarch64/aarch64.md: Rename aarch_ to aarch64_.
2183 * config/aarch64/aarch64.opt: Likewise.
2184 * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Likewise.
2185 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Likewise.
2186 (aarch64_expand_epilogue): Likewise.
2187 (aarch64_post_cfi_startproc): Likewise.
2188 (aarch64_handle_no_branch_protection): Copy and rename.
2189 (aarch64_handle_standard_branch_protection): Likewise.
2190 (aarch64_handle_pac_ret_protection): Likewise.
2191 (aarch64_handle_pac_ret_leaf): Likewise.
2192 (aarch64_handle_pac_ret_b_key): Likewise.
2193 (aarch64_handle_bti_protection): Likewise.
2194 (aarch64_override_options): Update branch protection validation.
2195 (aarch64_handle_attr_branch_protection): Likewise.
2196 * config/arm/aarch-common-protos.h (aarch_validate_mbranch_protection):
2197 Pass branch protection type description as argument.
2198 (struct aarch_branch_protect_type): Move from aarch-common.h.
2199 * config/arm/aarch-common.cc (aarch_handle_no_branch_protection):
2200 Remove.
2201 (aarch_handle_standard_branch_protection): Remove.
2202 (aarch_handle_pac_ret_protection): Remove.
2203 (aarch_handle_pac_ret_leaf): Remove.
2204 (aarch_handle_pac_ret_b_key): Remove.
2205 (aarch_handle_bti_protection): Remove.
2206 (aarch_validate_mbranch_protection): Pass branch protection type
2207 description as argument.
2208 * config/arm/aarch-common.h (enum aarch_key_type): Remove.
2209 (struct aarch_branch_protect_type): Remove.
2210 * config/arm/arm-c.cc (arm_cpu_builtins): Remove aarch_ra_sign_key.
2211 * config/arm/arm.cc (arm_handle_no_branch_protection): Copy and rename.
2212 (arm_handle_standard_branch_protection): Likewise.
2213 (arm_handle_pac_ret_protection): Likewise.
2214 (arm_handle_pac_ret_leaf): Likewise.
2215 (arm_handle_bti_protection): Likewise.
2216 (arm_configure_build_target): Update branch protection validation.
2217 * config/arm/arm.opt: Remove aarch_ra_sign_key.
2219 2024-03-11 Richard Biener <rguenther@suse.de>
2221 PR middle-end/114299
2222 * gimplify.cc (internal_get_tmp_var): When gimplification
2223 of VAL failed, return a decl.
2225 2024-03-11 Jakub Jelinek <jakub@redhat.com>
2227 PR tree-optimization/114278
2228 * tree-ssa.cc (maybe_optimize_var): If large/huge _BitInt vars are no
2229 longer addressable, set DECL_NOT_GIMPLE_REG_P on them.
2231 2024-03-11 Eric Botcazou <ebotcazou@adacore.com>
2233 PR debug/113519
2234 PR debug/113777
2235 * dwarf2out.cc (gen_enumeration_type_die): In the reverse case,
2236 generate the DIE with the same parent as in the regular case.
2238 2024-03-11 Andrew Pinski <quic_apinski@quicinc.com>
2240 PR middle-end/95351
2241 * fold-const.cc (merge_truthop_with_opposite_arm): Use
2242 the type of the operands of the comparison and not the type
2243 of the comparison.
2245 2024-03-10 jlaw <jeffreyalaw@gmail.com>
2247 PR tree-optimization/110199
2248 * tree-ssa-scopedtables.cc
2249 (avail_exprs_stack::simplify_binary_operation): Generalize handling
2250 of MIN_EXPR/MAX_EXPR to allow additional simplifications. Canonicalize
2251 comparison operands for other cases.
2253 2024-03-10 Pan Li <pan2.li@intel.com>
2255 * tree-vect-stmts.cc (vectorizable_store): Enable the assert
2256 during transform process.
2257 (vectorizable_load): Ditto.
2259 2024-03-10 jlaw <jeffreyalaw@gmail.com>
2261 PR target/102250
2262 * doc/install.texi: Document need for python when building
2263 RISC-V compilers.
2265 2024-03-10 jlaw <jeffreyalaw@gmail.com>
2267 PR target/111362
2268 * mode-switching.cc (optimize_mode_switching): Only process
2269 NONDEBUG insns.
2271 2024-03-09 Georg-Johann Lay <avr@gjlay.de>
2273 * config/avr/avr.md: Fix typos in comment, indentation glitches
2274 and some other nits.
2276 2024-03-09 Jakub Jelinek <jakub@redhat.com>
2278 PR target/114284
2279 * fwprop.cc (try_fwprop_subst_pattern): Don't propagate
2280 src containing MEMs unless prop.likely_profitable_p ().
2282 2024-03-09 Xi Ruoyao <xry111@xry111.site>
2284 * config/loongarch/loongarch.cc (loongarch_print_operand_reloc):
2285 Support 'Q' for R_LARCH_RELAX for TLS IE.
2286 (loongarch_output_move): Use 'Q' to print R_LARCH_RELAX for TLS
2287 IE.
2288 * config/loongarch/loongarch.md (ld_from_got<mode>): Likewise.
2290 2024-03-09 Georg-Johann Lay <avr@gjlay.de>
2292 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Determine cost for
2293 usum_widenqihi and add_zero_extend1.
2294 [MINUS]: Determine costs for udiff_widenqihi, sub+zero_extend,
2295 sub+sign_extend.
2296 * config/avr/avr.md (*addhi3.sign_extend1, *subhi3.sign_extend2):
2297 Compute exact insn lengths.
2298 (*usum_widenqihi3): Allow input operands to commute.
2300 2024-03-09 Jakub Jelinek <jakub@redhat.com>
2302 * config/i386/i386.opt.urls: Regenerate.
2304 2024-03-09 Lulu Cheng <chenglulu@loongson.cn>
2306 * config/loongarch/sync.md (atomic_cas_value_strong<mode>):
2307 In loongarch64, a sign extension operation is added when
2308 operands[2] is a register operand and the mode is SImode.
2310 2024-03-08 Martin Jambor <mjambor@suse.cz>
2312 PR ipa/113757
2313 * tree-inline.cc (redirect_all_calls): Remove code adding SSAs to
2314 id->killed_new_ssa_names.
2316 2024-03-08 Vladimir N. Makarov <vmakarov@redhat.com>
2318 PR target/113790
2319 * lra-assigns.cc (assign_by_spills): Set up all_spilled_pseudos
2320 for non-reload pseudo too.
2322 2024-03-08 David Faust <david.faust@oracle.com>
2324 * config/bpf/bpf.cc (bpf_expand_cpymem, bpf_expand_setmem): Do
2325 not attempt inline expansion if size is above threshold.
2326 * config/bpf/bpf.opt (-minline-memops-threshold): New option.
2327 * doc/invoke.texi (eBPF Options) <-minline-memops-threshold>:
2328 Document.
2330 2024-03-08 Richard Biener <rguenther@suse.de>
2332 PR tree-optimization/114269
2333 PR tree-optimization/114074
2334 * tree-chrec.cc (chrec_fold_plus_1): Handle sign-conversions
2335 in the third CASE_CONVERT case as well.
2336 (chrec_fold_multiply): Handle sign-conversions from unsigned
2337 by performing the operation in the unsigned type.
2339 2024-03-08 Georg-Johann Lay <avr@gjlay.de>
2341 * config/avr/avr.md (*addhi3_zero_extend.ashift1): New pattern.
2342 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Compute its cost.
2344 2024-03-08 Jakub Jelinek <jakub@redhat.com>
2346 * bb-reorder.cc (fix_up_fall_thru_edges): Fix up checking assert,
2347 asm_noperands < 0 means it is not asm goto too.
2349 2024-03-08 Jakub Jelinek <jakub@redhat.com>
2351 PR target/38534
2352 * config/i386/i386.opt (mnoreturn-no-callee-saved-registers): New
2353 option.
2354 * config/i386/i386-options.cc (ix86_set_func_type): Don't use
2355 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP unless
2356 ix86_noreturn_no_callee_saved_registers is enabled.
2357 * doc/invoke.texi (-mnoreturn-no-callee-saved-registers): Document.
2359 2024-03-08 Jakub Jelinek <jakub@redhat.com>
2361 PR debug/113918
2362 * dwarf2out.cc (gen_field_die): Emit DW_AT_export_symbols
2363 on anonymous unions or structs for -gdwarf-5 or -gno-strict-dwarf.
2365 2024-03-08 demin.han <demin.han@starfivetech.com>
2367 PR target/114264
2368 * config/riscv/riscv-vector-costs.cc: Fix ICE
2370 2024-03-08 Haochen Gui <guihaoc@gcc.gnu.org>
2372 * fwprop.cc (forward_propagate_into): Return false for volatile set
2373 source rtx.
2375 2024-03-07 Wilco Dijkstra <wilco.dijkstra@arm.com>
2377 PR target/113618
2378 * config/aarch64/aarch64.cc (aarch64_copy_one_block): Remove.
2379 (aarch64_expand_cpymem): Emit single load/store only.
2380 (aarch64_set_one_block): Emit single stores only.
2382 2024-03-07 Robin Dapp <rdapp@ventanamicro.com>
2384 PR middle-end/114196
2385 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p): Merge
2386 vectorization guards.
2388 2024-03-07 Jonathan Wakely <jwakely@redhat.com>
2390 * doc/cppopts.texi: Remove incorrect claim about -dD not
2391 outputting predefined macros.
2393 2024-03-07 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
2395 PR target/113950
2396 * config/rs6000/vsx.md (vsx_splat_<mode>): Correct assignment to operand1
2397 and simplify else if with else.
2399 2024-03-07 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
2401 * system.h: Include safe-ctype.h after C++ standard headers.
2403 2024-03-07 Jakub Jelinek <jakub@redhat.com>
2405 PR rtl-optimization/110079
2406 * bb-reorder.cc (fix_crossing_unconditional_branches): Don't adjust
2407 asm goto.
2409 2024-03-07 Jakub Jelinek <jakub@redhat.com>
2411 PR middle-end/105533
2412 * expmed.cc (choose_mult_variant): Only try the val - 1 variant
2413 if val is not HOST_WIDE_INT_MIN or if mode has exactly
2414 HOST_BITS_PER_WIDE_INT precision. Avoid triggering UB while computing
2415 val - 1.
2417 2024-03-07 Jakub Jelinek <jakub@redhat.com>
2419 PR middle-end/105533
2420 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference) <case ARRAY_REF>:
2421 Multiple op->off by BITS_PER_UNIT instead of shifting it left by
2422 LOG2_BITS_PER_UNIT.
2424 2024-03-07 Yang Yujie <yangyujie@loongson.cn>
2426 * config.gcc: Add a case for loongarch*-*-linux-musl*.
2427 * config/loongarch/linux.h: Disable the multilib-compatible
2428 treatment for *musl* targets.
2429 * config/loongarch/musl.h: New file.
2431 2024-03-07 Jakub Jelinek <jakub@redhat.com>
2433 PR tree-optimization/114009
2434 * genmatch.cc (decision_tree::gen): Emit ARG_UNUSED for captures
2435 argument even for GENERIC, not just for GIMPLE.
2436 * match.pd (a * !a -> 0): New simplifications.
2438 2024-03-07 demin.han <demin.han@starfivetech.com>
2440 * config/riscv/riscv-protos.h (expand_vec_cmp): Change proto
2441 * config/riscv/riscv-v.cc (expand_vec_cmp): Use default arguments
2442 (expand_vec_cmp_float): Adapt arguments
2444 2024-03-06 Uros Bizjak <ubizjak@gmail.com>
2446 PR target/114232
2447 * config/i386/mmx.md (negv2qi2): Enable for optimize_size instead
2448 of optimize_function_for_size_p. Explictily enable for TARGET_SSE2.
2449 (negv2qi SSE reg splitter): Enable for TARGET_SSE2 only.
2450 (<plusminus:insn>v2qi3): Enable for optimize_size instead
2451 of optimize_function_for_size_p. Explictily enable for TARGET_SSE2.
2452 (<plusminus:insn>v2qi SSE reg splitter): Enable for TARGET_SSE2 only.
2453 (<any_shift:insn>v2qi3): Enable for optimize_size instead
2454 of optimize_function_for_size_p.
2456 2024-03-06 Robin Dapp <rdapp@ventanamicro.com>
2458 PR target/114200
2459 PR target/114202
2460 * config/riscv/vector.md: Use vmv[1248]r.v instead of vmv.v.v.
2462 2024-03-06 Robin Dapp <rdapp@ventanamicro.com>
2464 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Move...
2465 (costs::adjust_stmt_cost): ... to here and add vec_load/vec_store
2466 offset handling.
2467 (costs::add_stmt_cost): Also adjust cost for statements without
2468 stmt_info.
2469 * config/riscv/riscv-vector-costs.h: Define zero constant.
2471 2024-03-06 Wilco Dijkstra <wilco.dijkstra@arm.com>
2473 PR target/113915
2474 * config/arm/arm.md (NOCOND): Improve comment.
2475 (arm_rev*) Add predicable.
2476 * config/arm/arm.cc (arm_final_prescan_insn): Add check for
2477 PREDICABLE_YES.
2479 2024-03-06 Jeff Law <jlaw@ventanamicro.com>
2481 PR target/113001
2482 PR target/112871
2483 * config/riscv/riscv.cc (expand_conditional_move): Do not swap
2484 operands when the comparison operand is the same as the false
2485 arm for a NE test.
2487 2024-03-06 Uros Bizjak <ubizjak@gmail.com>
2489 * config/i386/i386-expand.cc (ix86_expand_move) [TARGET_MACHO]:
2490 Eliminate common code and use generic code instead.
2492 2024-03-06 Georg-Johann Lay <avr@gjlay.de>
2494 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS+ZERO_EXTEND]: Adjust
2495 rtx cost.
2497 2024-03-06 Richard Biener <rguenther@suse.de>
2499 PR tree-optimization/114239
2500 * tree-vect-loop.cc (vect_get_vect_def): Remove.
2501 (vect_create_epilog_for_reduction): The passed in stmt_info
2502 should now be the live stmt that produces the scalar reduction
2503 result. Revert PR114192 fix. Base reduction info off
2504 info_for_reduction. Remove special handling of
2505 early-break/peeled, restore original vector def gathering.
2506 Make sure to pick the correct exit PHIs.
2507 (vectorizable_live_operation): Pass in the proper stmt_info
2508 for early break exits.
2510 2024-03-06 Richard Sandiford <richard.sandiford@arm.com>
2512 * config/aarch64/aarch64-feature-deps.h (feature_deps::info): Add
2513 out-of-class definitions of static constants.
2515 2024-03-06 Richard Biener <rguenther@suse.de>
2517 PR tree-optimization/114249
2518 * tree-vect-slp.cc (vect_build_slp_instance): Move making
2519 a BB reduction lane number even ...
2520 (vect_slp_check_for_roots): ... here to avoid leaking
2521 pattern defs.
2523 2024-03-06 Richard Biener <rguenther@suse.de>
2525 PR tree-optimization/114246
2526 * tree-ssa-dse.cc (increment_start_addr): Strip useless
2527 type conversions from the adjusted address.
2529 2024-03-06 Jakub Jelinek <jakub@redhat.com>
2531 PR rtl-optimization/114190
2532 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
2533 Call df_remove_problem for df_note before calling df_analyze.
2535 2024-03-05 Cupertino Miranda <cupertino.miranda@oracle.com>
2536 Indu Bhagat <indu.bhagat@oracle.com>
2538 PR debug/114186
2539 * dwarf2ctf.cc (gen_ctf_array_type): Invoke the ctf_add_array ()
2540 in the correct order of the dimensions.
2541 (gen_ctf_subrange_type): Refactor out handling of
2542 DW_TAG_subrange_type DIE to here.
2544 2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
2546 PR sanitizer/97696
2547 * asan.cc (asan_expand_mark_ifn): Allow the length to be a poly_int.
2549 2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
2551 * config/aarch64/aarch64.md (stride_type): Remove luti_consecutive
2552 and luti_strided.
2553 * config/aarch64/aarch64-sme.md
2554 (@aarch64_sme_lut<LUTI_BITS><mode>): Remove stride_type attribute.
2555 (@aarch64_sme_lut<LUTI_BITS><mode>_strided2): Delete.
2556 (@aarch64_sme_lut<LUTI_BITS><mode>_strided4): Likewise.
2557 * config/aarch64/aarch64-early-ra.cc (is_stride_candidate)
2558 (early_ra::maybe_convert_to_strided_access): Remove support for
2559 strided LUTI2 and LUTI4.
2561 2024-03-05 Richard Earnshaw <rearnsha@arm.com>
2563 PR target/113510
2564 * config/arm/thumb1.md (peephole2 to fuse mov imm/add SP): Use
2565 low_register_operand.
2567 2024-03-05 Georg-Johann Lay <avr@gjlay.de>
2569 * config/avr/avr.md: Add two RTL peepholes for PLUS, IOR and AND
2570 in HI, PSI, SI that swap operation order from "X = CST, X o= Y"
2571 to "X = Y, X o= CST".
2573 2024-03-05 Xi Ruoyao <xry111@xry111.site>
2575 * config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add
2576 s9 as an alias of r22.
2578 2024-03-05 Roger Sayle <roger@nextmovesoftware.com>
2580 * config/avr/avr-protos.h (avr_out_insv): New proto.
2581 * config/avr/avr.cc (avr_out_insv): New function.
2582 (avr_adjust_insn_length) [ADJUST_LEN_INSV]: Handle case.
2583 (avr_cbranch_cost) [ZERO_EXTRACT]: Adjust rtx costs.
2584 * config/avr/avr.md (define_attr "adjust_len") Add insv.
2585 (andhi3, *andhi3, andpsi3, *andpsi3, andsi3, *andsi3):
2586 Add constraint alternative where the 3rd operand is a power
2587 of 2, and the source register may differ from the destination.
2588 (*insv.any_shift.<mode>_split): Call avr_out_insv to output
2589 instructions. Set attr "length" to "insv".
2590 * config/avr/constraints.md (Cb2, Cb3, Cb4): New constraints.
2592 2024-03-05 Richard Biener <rguenther@suse.de>
2594 PR tree-optimization/114231
2595 * tree-vect-slp.cc (vect_analyze_slp): Lookup patterns when
2596 processing a BB SLP root.
2598 2024-03-05 Jakub Jelinek <jakub@redhat.com>
2600 PR rtl-optimization/114211
2601 * lower-subreg.cc (resolve_simple_move): For double-word
2602 rotates by BITS_PER_WORD if there is overlap between source
2603 and destination use a temporary.
2605 2024-03-05 Jakub Jelinek <jakub@redhat.com>
2607 PR middle-end/114157
2608 * gimple-lower-bitint.cc: Include stor-layout.h.
2609 (mergeable_op): Return true for BIT_FIELD_REF.
2610 (struct bitint_large_huge): Declare handle_bit_field_ref method.
2611 (bitint_large_huge::handle_bit_field_ref): New method.
2612 (bitint_large_huge::handle_stmt): Use it for BIT_FIELD_REF.
2614 2024-03-05 Jakub Jelinek <jakub@redhat.com>
2616 PR target/114116
2617 * config/i386/i386.h (enum call_saved_registers_type): Add
2618 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP enumerator.
2619 * config/i386/i386-options.cc (ix86_set_func_type): Remove
2620 has_no_callee_saved_registers variable, add no_callee_saved_registers
2621 instead, initialize it depending on whether it is
2622 no_callee_saved_registers function or not. Don't set it if
2623 no_caller_saved_registers attribute is present. Adjust users.
2624 * config/i386/i386.cc (ix86_function_ok_for_sibcall): Handle
2625 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP like
2626 TYPE_NO_CALLEE_SAVED_REGISTERS.
2627 (ix86_save_reg): Handle TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP.
2629 2024-03-05 Pan Li <pan2.li@intel.com>
2631 * config/riscv/riscv.cc (riscv_v_adjust_bytesize): Cleanup unused
2632 mode_size related code.
2634 2024-03-05 Patrick Palka <ppalka@redhat.com>
2636 * doc/invoke.texi (-Wno-global-module): Document.
2638 2024-03-04 David Faust <david.faust@oracle.com>
2640 * config/bpf/bpf-protos.h (bpf_expand_setmem): New prototype.
2641 * config/bpf/bpf.cc (bpf_expand_setmem): New.
2642 * config/bpf/bpf.md (setmemdi): New define_expand.
2644 2024-03-04 Jakub Jelinek <jakub@redhat.com>
2646 PR rtl-optimization/113010
2647 * combine.cc (simplify_comparison): Guard the
2648 WORD_REGISTER_OPERATIONS check on scalar_int_mode of SUBREG_REG
2649 and initialize inner_mode.
2651 2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
2653 * config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U,
2654 VMLALDAVAXQ_U cases.
2655 (VMLALDAVXQ): Remove iterator.
2656 (VMLALDAVXQ_P): Likewise.
2657 (VMLALDAVAXQ): Likewise.
2658 * config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of <MVE_VPRED>
2659 mode iterator attribute with V4BI mode.
2660 * config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U,
2661 VMLALDAVAXQ_U): Remove unused unspecs.
2663 2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
2665 * config/arm/arm.md (mve_safe_imp_xlane_pred): New attribute.
2666 * config/arm/iterators.md (mve_vmaxmin_safe_imp): New iterator
2667 attribute.
2668 * config/arm/mve.md (vaddvq_s, vaddvq_u, vaddlvq_s, vaddlvq_u,
2669 vaddvaq_s, vaddvaq_u, vmaxavq_s, vmaxvq_u, vmladavq_s, vmladavq_u,
2670 vmladavxq_s, vmlsdavq_s, vmlsdavxq_s, vaddlvaq_s, vaddlvaq_u,
2671 vmlaldavq_u, vmlaldavq_s, vmlaldavq_u, vmlaldavxq_s, vmlsldavq_s,
2672 vmlsldavxq_s, vrmlaldavhq_u, vrmlaldavhq_s, vrmlaldavhxq_s,
2673 vrmlsldavhq_s, vrmlsldavhxq_s, vrmlaldavhaq_s, vrmlaldavhaq_u,
2674 vrmlaldavhaxq_s, vrmlsldavhaq_s, vrmlsldavhaxq_s, vabavq_s, vabavq_u,
2675 vmladavaq_u, vmladavaq_s, vmladavaxq_s, vmlsdavaq_s, vmlsdavaxq_s,
2676 vmlaldavaq_s, vmlaldavaq_u, vmlaldavaxq_s, vmlsldavaq_s,
2677 vmlsldavaxq_s): Added mve_safe_imp_xlane_pred.
2679 2024-03-04 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2681 * config/arm/arm.md (mve_unpredicated_insn): New attribute.
2682 * config/arm/arm.h (MVE_VPT_PREDICATED_INSN_P): New define.
2683 (MVE_VPT_UNPREDICATED_INSN_P): Likewise.
2684 (MVE_VPT_PREDICABLE_INSN_P): Likewise.
2685 * config/arm/vec-common.md (mve_vshlq_<supf><mode>): Add attribute.
2686 * config/arm/mve.md (arm_vcx1q<a>_p_v16qi): Add attribute.
2687 (arm_vcx1q<a>v16qi): Likewise.
2688 (arm_vcx1qav16qi): Likewise.
2689 (arm_vcx1qv16qi): Likewise.
2690 (arm_vcx2q<a>_p_v16qi): Likewise.
2691 (arm_vcx2q<a>v16qi): Likewise.
2692 (arm_vcx2qav16qi): Likewise.
2693 (arm_vcx2qv16qi): Likewise.
2694 (arm_vcx3q<a>_p_v16qi): Likewise.
2695 (arm_vcx3q<a>v16qi): Likewise.
2696 (arm_vcx3qav16qi): Likewise.
2697 (arm_vcx3qv16qi): Likewise.
2698 (@mve_<mve_insn>q_<supf><mode>): Likewise.
2699 (@mve_<mve_insn>q_int_<supf><mode>): Likewise.
2700 (@mve_<mve_insn>q_<supf>v4si): Likewise.
2701 (@mve_<mve_insn>q_n_<supf><mode>): Likewise.
2702 (@mve_<mve_insn>q_r_<supf><mode>): Likewise.
2703 (@mve_<mve_insn>q_f<mode>): Likewise.
2704 (@mve_<mve_insn>q_m_<supf><mode>): Likewise.
2705 (@mve_<mve_insn>q_m_n_<supf><mode>): Likewise.
2706 (@mve_<mve_insn>q_m_r_<supf><mode>): Likewise.
2707 (@mve_<mve_insn>q_m_f<mode>): Likewise.
2708 (@mve_<mve_insn>q_int_m_<supf><mode>): Likewise.
2709 (@mve_<mve_insn>q_p_<supf>v4si): Likewise.
2710 (@mve_<mve_insn>q_p_<supf><mode>): Likewise.
2711 (@mve_<mve_insn>q<mve_rot>_<supf><mode>): Likewise.
2712 (@mve_<mve_insn>q<mve_rot>_f<mode>): Likewise.
2713 (@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): Likewise.
2714 (@mve_<mve_insn>q<mve_rot>_m_f<mode>): Likewise.
2715 (mve_v<absneg_str>q_f<mode>): Likewise.
2716 (mve_<mve_addsubmul>q<mode>): Likewise.
2717 (mve_<mve_addsubmul>q_f<mode>): Likewise.
2718 (mve_vadciq_<supf>v4si): Likewise.
2719 (mve_vadciq_m_<supf>v4si): Likewise.
2720 (mve_vadcq_<supf>v4si): Likewise.
2721 (mve_vadcq_m_<supf>v4si): Likewise.
2722 (mve_vandq_<supf><mode>): Likewise.
2723 (mve_vandq_f<mode>): Likewise.
2724 (mve_vandq_m_<supf><mode>): Likewise.
2725 (mve_vandq_m_f<mode>): Likewise.
2726 (mve_vandq_s<mode>): Likewise.
2727 (mve_vandq_u<mode>): Likewise.
2728 (mve_vbicq_<supf><mode>): Likewise.
2729 (mve_vbicq_f<mode>): Likewise.
2730 (mve_vbicq_m_<supf><mode>): Likewise.
2731 (mve_vbicq_m_f<mode>): Likewise.
2732 (mve_vbicq_m_n_<supf><mode>): Likewise.
2733 (mve_vbicq_n_<supf><mode>): Likewise.
2734 (mve_vbicq_s<mode>): Likewise.
2735 (mve_vbicq_u<mode>): Likewise.
2736 (@mve_vclzq_s<mode>): Likewise.
2737 (mve_vclzq_u<mode>): Likewise.
2738 (@mve_vcmp_<mve_cmp_op>q_<mode>): Likewise.
2739 (@mve_vcmp_<mve_cmp_op>q_n_<mode>): Likewise.
2740 (@mve_vcmp_<mve_cmp_op>q_f<mode>): Likewise.
2741 (@mve_vcmp_<mve_cmp_op>q_n_f<mode>): Likewise.
2742 (@mve_vcmp_<mve_cmp_op1>q_m_f<mode>): Likewise.
2743 (@mve_vcmp_<mve_cmp_op1>q_m_n_<supf><mode>): Likewise.
2744 (@mve_vcmp_<mve_cmp_op1>q_m_<supf><mode>): Likewise.
2745 (@mve_vcmp_<mve_cmp_op1>q_m_n_f<mode>): Likewise.
2746 (mve_vctp<MVE_vctp>q<MVE_vpred>): Likewise.
2747 (mve_vctp<MVE_vctp>q_m<MVE_vpred>): Likewise.
2748 (mve_vcvtaq_<supf><mode>): Likewise.
2749 (mve_vcvtaq_m_<supf><mode>): Likewise.
2750 (mve_vcvtbq_f16_f32v8hf): Likewise.
2751 (mve_vcvtbq_f32_f16v4sf): Likewise.
2752 (mve_vcvtbq_m_f16_f32v8hf): Likewise.
2753 (mve_vcvtbq_m_f32_f16v4sf): Likewise.
2754 (mve_vcvtmq_<supf><mode>): Likewise.
2755 (mve_vcvtmq_m_<supf><mode>): Likewise.
2756 (mve_vcvtnq_<supf><mode>): Likewise.
2757 (mve_vcvtnq_m_<supf><mode>): Likewise.
2758 (mve_vcvtpq_<supf><mode>): Likewise.
2759 (mve_vcvtpq_m_<supf><mode>): Likewise.
2760 (mve_vcvtq_from_f_<supf><mode>): Likewise.
2761 (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
2762 (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
2763 (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
2764 (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
2765 (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
2766 (mve_vcvtq_n_to_f_<supf><mode>): Likewise.
2767 (mve_vcvtq_to_f_<supf><mode>): Likewise.
2768 (mve_vcvttq_f16_f32v8hf): Likewise.
2769 (mve_vcvttq_f32_f16v4sf): Likewise.
2770 (mve_vcvttq_m_f16_f32v8hf): Likewise.
2771 (mve_vcvttq_m_f32_f16v4sf): Likewise.
2772 (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
2773 (mve_vdwdupq_wb_u<mode>_insn): Likewise.
2774 (mve_veorq_s><mode>): Likewise.
2775 (mve_veorq_u><mode>): Likewise.
2776 (mve_veorq_f<mode>): Likewise.
2777 (mve_vidupq_m_wb_u<mode>_insn): Likewise.
2778 (mve_vidupq_u<mode>_insn): Likewise.
2779 (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
2780 (mve_viwdupq_wb_u<mode>_insn): Likewise.
2781 (mve_vldrbq_<supf><mode>): Likewise.
2782 (mve_vldrbq_gather_offset_<supf><mode>): Likewise.
2783 (mve_vldrbq_gather_offset_z_<supf><mode>): Likewise.
2784 (mve_vldrbq_z_<supf><mode>): Likewise.
2785 (mve_vldrdq_gather_base_<supf>v2di): Likewise.
2786 (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
2787 (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
2788 (mve_vldrdq_gather_base_z_<supf>v2di): Likewise.
2789 (mve_vldrdq_gather_offset_<supf>v2di): Likewise.
2790 (mve_vldrdq_gather_offset_z_<supf>v2di): Likewise.
2791 (mve_vldrdq_gather_shifted_offset_<supf>v2di): Likewise.
2792 (mve_vldrdq_gather_shifted_offset_z_<supf>v2di): Likewise.
2793 (mve_vldrhq_<supf><mode>): Likewise.
2794 (mve_vldrhq_fv8hf): Likewise.
2795 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
2796 (mve_vldrhq_gather_offset_fv8hf): Likewise.
2797 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
2798 (mve_vldrhq_gather_offset_z_fv8hf): Likewise.
2799 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
2800 (mve_vldrhq_gather_shifted_offset_fv8hf): Likewise.
2801 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
2802 (mve_vldrhq_gather_shifted_offset_z_fv8hf): Likewise.
2803 (mve_vldrhq_z_<supf><mode>): Likewise.
2804 (mve_vldrhq_z_fv8hf): Likewise.
2805 (mve_vldrwq_<supf>v4si): Likewise.
2806 (mve_vldrwq_fv4sf): Likewise.
2807 (mve_vldrwq_gather_base_<supf>v4si): Likewise.
2808 (mve_vldrwq_gather_base_fv4sf): Likewise.
2809 (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
2810 (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
2811 (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
2812 (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
2813 (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
2814 (mve_vldrwq_gather_base_z_fv4sf): Likewise.
2815 (mve_vldrwq_gather_offset_<supf>v4si): Likewise.
2816 (mve_vldrwq_gather_offset_fv4sf): Likewise.
2817 (mve_vldrwq_gather_offset_z_<supf>v4si): Likewise.
2818 (mve_vldrwq_gather_offset_z_fv4sf): Likewise.
2819 (mve_vldrwq_gather_shifted_offset_<supf>v4si): Likewise.
2820 (mve_vldrwq_gather_shifted_offset_fv4sf): Likewise.
2821 (mve_vldrwq_gather_shifted_offset_z_<supf>v4si): Likewise.
2822 (mve_vldrwq_gather_shifted_offset_z_fv4sf): Likewise.
2823 (mve_vldrwq_z_<supf>v4si): Likewise.
2824 (mve_vldrwq_z_fv4sf): Likewise.
2825 (mve_vmvnq_s<mode>): Likewise.
2826 (mve_vmvnq_u<mode>): Likewise.
2827 (mve_vornq_<supf><mode>): Likewise.
2828 (mve_vornq_f<mode>): Likewise.
2829 (mve_vornq_m_<supf><mode>): Likewise.
2830 (mve_vornq_m_f<mode>): Likewise.
2831 (mve_vornq_s<mode>): Likewise.
2832 (mve_vornq_u<mode>): Likewise.
2833 (mve_vorrq_<supf><mode>): Likewise.
2834 (mve_vorrq_f<mode>): Likewise.
2835 (mve_vorrq_m_<supf><mode>): Likewise.
2836 (mve_vorrq_m_f<mode>): Likewise.
2837 (mve_vorrq_m_n_<supf><mode>): Likewise.
2838 (mve_vorrq_n_<supf><mode>): Likewise.
2839 (mve_vorrq_s<mode>): Likewise.
2840 (mve_vorrq_s<mode>): Likewise.
2841 (mve_vsbciq_<supf>v4si): Likewise.
2842 (mve_vsbciq_m_<supf>v4si): Likewise.
2843 (mve_vsbcq_<supf>v4si): Likewise.
2844 (mve_vsbcq_m_<supf>v4si): Likewise.
2845 (mve_vshlcq_<supf><mode>): Likewise.
2846 (mve_vshlcq_m_<supf><mode>): Likewise.
2847 (mve_vshrq_m_n_<supf><mode>): Likewise.
2848 (mve_vshrq_n_<supf><mode>): Likewise.
2849 (mve_vstrbq_<supf><mode>): Likewise.
2850 (mve_vstrbq_p_<supf><mode>): Likewise.
2851 (mve_vstrbq_scatter_offset_<supf><mode>_insn): Likewise.
2852 (mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
2853 (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
2854 (mve_vstrdq_scatter_base_p_<supf>v2di): Likewise.
2855 (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
2856 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
2857 (mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
2858 (mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
2859 (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
2860 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
2861 (mve_vstrhq_<supf><mode>): Likewise.
2862 (mve_vstrhq_fv8hf): Likewise.
2863 (mve_vstrhq_p_<supf><mode>): Likewise.
2864 (mve_vstrhq_p_fv8hf): Likewise.
2865 (mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
2866 (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
2867 (mve_vstrhq_scatter_offset_p_<supf><mode>_insn): Likewise.
2868 (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
2869 (mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
2870 (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
2871 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
2872 (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
2873 (mve_vstrwq_<supf>v4si): Likewise.
2874 (mve_vstrwq_fv4sf): Likewise.
2875 (mve_vstrwq_p_<supf>v4si): Likewise.
2876 (mve_vstrwq_p_fv4sf): Likewise.
2877 (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
2878 (mve_vstrwq_scatter_base_fv4sf): Likewise.
2879 (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
2880 (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
2881 (mve_vstrwq_scatter_base_wb_<supf>v4si): Likewise.
2882 (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
2883 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
2884 (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
2885 (mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
2886 (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
2887 (mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
2888 (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
2889 (mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.
2890 (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
2891 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
2892 (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.
2894 2024-03-04 Marek Polacek <polacek@redhat.com>
2896 * doc/extend.texi: Update [[gnu::no_dangling]].
2898 2024-03-04 Andrew Stubbs <ams@baylibre.com>
2900 * dojump.cc (do_compare_and_jump): Use full-width integers for shifts.
2901 * expr.cc (store_constructor): Likewise.
2902 (do_store_flag): Likewise.
2904 2024-03-04 Mark Wielaard <mark@klomp.org>
2906 * common.opt.urls: Regenerate.
2907 * config/avr/avr.opt.urls: Likewise.
2908 * config/i386/i386.opt.urls: Likewise.
2909 * config/pru/pru.opt.urls: Likewise.
2910 * config/riscv/riscv.opt.urls: Likewise.
2911 * config/rs6000/rs6000.opt.urls: Likewise.
2913 2024-03-04 Richard Biener <rguenther@suse.de>
2915 PR tree-optimization/114197
2916 * tree-if-conv.cc (bitfields_to_lower_p): Do not lower if
2917 there are volatile bitfield accesses.
2918 (pass_if_conversion::execute): Throw away result if the
2919 if-converted and original loops are not nested as expected.
2921 2024-03-04 Richard Biener <rguenther@suse.de>
2923 PR tree-optimization/114164
2924 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Fail if
2925 the code generated for mask argument setup is not supported.
2927 2024-03-04 Richard Biener <rguenther@suse.de>
2929 PR tree-optimization/114203
2930 * tree-ssa-loop-niter.cc (build_cltz_expr): Apply CTZ->CLZ
2931 adjustment before making the result defined at zero.
2933 2024-03-04 Richard Biener <rguenther@suse.de>
2935 PR tree-optimization/114192
2936 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Use the
2937 appropriate def for the live out stmt in case of an alternate
2938 exit.
2940 2024-03-04 Jakub Jelinek <jakub@redhat.com>
2942 PR middle-end/114209
2943 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Call
2944 unshare_expr when creating a MEM_REF from MEM_REF.
2945 (bitint_large_huge::lower_stmt): Call unshare_expr.
2947 2024-03-04 Jakub Jelinek <jakub@redhat.com>
2949 PR target/114184
2950 * config/i386/i386-expand.cc (ix86_expand_move): If XFmode op1
2951 is SUBREG of CONSTANT_P, force the SUBREG_REG into memory or
2952 register.
2954 2024-03-04 Roger Sayle <roger@nextmovesoftware.com>
2956 PR target/114187
2957 * simplify-rtx.cc (simplify_context::simplify_subreg): Call
2958 lowpart_subreg to perform type conversion, to avoid confusion
2959 over the offset to use in the call to simplify_reg_subreg.
2961 2024-03-03 Greg McGary <gkm@rivosinc.com>
2963 PR rtl-optimization/113010
2964 * combine.cc (simplify_comparison): Simplify a SUBREG on
2965 WORD_REGISTER_OPERATIONS targets only if it is a zero-extending
2966 MEM load.
2968 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
2970 * config/avr/avr.cc: Resolve ATTRIBUTE_UNUSED.
2971 Use bool in place of int for boolean logic (if possible).
2972 Move declarations to definitions (if possible).
2973 * config/avr/avr.md: Use C++ comments. Fix some indentation glitches.
2974 * config/avr/avr-dimode.md: Same.
2975 * config/avr/constraints.md: Same.
2976 * config/avr/predicates.md: Same.
2978 2024-03-03 Uros Bizjak <ubizjak@gmail.com>
2980 PR target/113720
2981 * config/alpha/alpha.md (umuldi3_highpart): Remove expander.
2982 (*umuldi3_highpart_reg): Rename to umuldi3_highpart and
2983 simplify insn RTX using UMUL_HIGHPART rtx_code.
2984 (*umuldi3_highpart_const): Remove.
2986 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
2988 PR target/114100
2989 * config/avr/avr-protos.h (_reg_unused_after): Remove proto.
2990 * config/avr/avr.cc (_reg_unused_after): Make static. And
2991 add 3rd argument to skip the current insn.
2992 (reg_unused_after): Adjust call of reg_unused_after.
2993 (avr_out_plus_1) [AVR_TINY && -mfuse-add >= 2]: Don't output
2994 unneeded frame pointer adjustments.
2996 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
2998 PR target/92729
2999 * config/avr/avr.md (define_attr "cc"): Remove.
3000 * config/avr/avr-protos.h (avr_out_plus): Remove pcc argument
3001 from prototype.
3002 * config/avr/avr.cc (avr_out_plus_1): Remove pcc argument and
3003 its uses. Add insn argument.
3004 (avr_out_plus_symbol): Remove pcc argument and its uses.
3005 (avr_out_plus): Remove pcc argument and its uses.
3006 Adjust calls of avr_out_plus_symbol and avr_out_plus_1.
3007 (avr_out_round): Adjust call of avr_out_plus.
3009 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
3011 * config/avr/avr.cc (avr_init_cumulative_args): Fix a typo
3012 from r14-9273.
3014 2024-03-03 Oleg Endo <olegendo@gcc.gnu.org>
3016 PR target/101737
3017 * config/sh/sh.cc (sh_is_nott_insn): Handle case where the input
3018 is not an insn, but e.g. a code label.
3020 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
3022 * config/avr/avr.md (REG_0, ... REG_36): New define_constants.
3023 * config/avr/avr.cc: Use them instead of magic numbers when it
3024 means a register number.
3026 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
3028 * config/avr/avr.cc: Adjust some comments.
3030 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
3032 PR target/114100
3033 * config/avr/avr.cc (avr_out_plus_1) [-mtiny-stack]: Only adjust
3034 the low part of the frame pointer with 8-bit stack pointer.
3036 2024-03-01 Patrick Palka <ppalka@redhat.com>
3038 PR c++/104919
3039 PR c++/106009
3040 * tree-inline.cc (remap_decl): Handle copy_decl returning the
3041 original decl.
3042 (remap_decls): Handle remap_decl returning the original decl.
3043 (copy_fn): Adjust copy_decl callback to skip TYPE_DECL and
3044 CONST_DECL.
3046 2024-03-01 Jeff Law <jlaw@ventanamicro.com>
3048 * config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2_internal): Fix
3049 type attribute.
3050 (extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise.
3051 (movdi_32bit, movdi_64bit, movsi_internal): Likewise.
3052 (movhi_internal, movqi_internal): Likewise.
3053 (movsf_softfloat, movsf_hardfloat): Likewise.
3054 (movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise.
3055 (movdf_softfloat): Likewise.
3057 2024-03-01 Marek Polacek <polacek@redhat.com>
3059 PR c++/110358
3060 PR c++/109642
3061 * doc/extend.texi: Document gnu::no_dangling.
3062 * doc/invoke.texi: Mention that gnu::no_dangling disables
3063 -Wdangling-reference.
3065 2024-03-01 Georg-Johann Lay <avr@gjlay.de>
3067 * config/avr/avr.opt: Overhaul help screen.
3069 2024-03-01 Jakub Jelinek <jakub@redhat.com>
3070 Tobias Burnus <tburnus@baylibre.com>
3072 PR c++/110347
3073 * gimplify.cc (omp_notice_variable): Fix 'shared' arg to
3074 lang_hooks.decls.omp_disregard_value_expr for
3075 (first)private in target regions.
3077 2024-03-01 Jakub Jelinek <jakub@redhat.com>
3079 PR middle-end/114136
3080 * calls.cc (expand_call): For TYPE_NO_NAMED_ARGS_STDARG_P set
3081 n_named_args initially before INIT_CUMULATIVE_ARGS to
3082 structure_value_addr_parm rather than 0, after it don't modify
3083 it if strict_argument_naming and clear only if
3084 !pretend_outgoing_varargs_named.
3086 2024-03-01 Jakub Jelinek <jakub@redhat.com>
3088 PR debug/114015
3089 * dwarf2out.cc (should_move_die_to_comdat): Return false for
3090 aggregates without DW_AT_byte_size attribute or with non-constant
3091 DW_AT_byte_size.
3093 2024-03-01 Georg-Johann Lay <avr@gjlay.de>
3095 * doc/invoke.texi (AVR Options) <-mfuse-add=level>: Document
3096 valid values for level.
3098 2024-03-01 Richard Biener <rguenther@suse.de>
3100 PR middle-end/114070
3101 * match.pd ((c ? a : b) op d --> c ? (a op d) : (b op d)):
3102 Allow the folding if before lowering and the current IL
3103 isn't supported with vcond_mask.
3105 2024-03-01 xuli <xuli1@eswincomputing.com>
3107 * config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc
3108 attribute to riscv_attribute_table.
3109 (riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function.
3110 (riscv_fntype_abi): Add riscv_vector_cc attribute check.
3111 * doc/extend.texi: Add riscv_vector_cc attribute description.
3113 2024-03-01 Pan Li <pan2.li@intel.com>
3115 PR target/112817
3116 * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace
3117 RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL.
3118 * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove.
3119 (enum rvv_vector_bits_enum): New enum for different RVV vector bits.
3120 * config/riscv/riscv-selftests.cc (riscv_run_selftests): Update
3121 comments for option replacement.
3122 * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of
3123 riscv_autovec_preference to rvv_vector_bits.
3124 (vls_mode_valid_p): Ditto.
3125 (estimated_poly_value): Ditto.
3126 * config/riscv/riscv.cc (riscv_convert_vector_chunks): Rename to
3127 vector chunks and honor new option mrvv-vector-bits.
3128 (riscv_override_options_internal): Update comments and rename the
3129 vector chunks.
3130 * config/riscv/riscv.opt: Add option mrvv-vector-bits and remove
3131 internal option param=riscv-autovec-preference.
3133 2024-03-01 Jakub Jelinek <jakub@redhat.com>
3135 * function.cc (assign_parms): Only call assign_parms_setup_varargs
3136 early for TYPE_NO_NAMED_ARGS_STDARG_P functions if fnargs is empty.
3138 2024-03-01 Jakub Jelinek <jakub@redhat.com>
3140 PR middle-end/114156
3141 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Allow
3142 rhs1 of a VCE to have no underlying variable if it is a load and
3143 handle that case.
3145 2024-02-29 David Malcolm <dmalcolm@redhat.com>
3147 PR analyzer/114159
3148 * function.cc (function_name): Make param const.
3149 * function.h (function_name): Likewise.
3151 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
3153 PR target/114100
3154 * doc/invoke.texi (AVR Options) <-mfuse-add>: Document.
3155 * config/avr/avr.opt (-mfuse-add=): New target option.
3156 * common/config/avr/avr-common.cc (avr_option_optimization_table)
3157 [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1.
3158 [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2.
3159 * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass.
3160 * config/avr/avr-protos.h (avr_split_tiny_move)
3161 (make_avr_pass_fuse_add): New protos.
3162 * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses
3163 avr_split_tiny_move to split indirect memory accesses.
3164 (gen_move_clobbercc): New define_expand helper.
3165 * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data.
3166 (avr_pass_fuse_add): New class from rtl_opt_pass.
3167 (make_avr_pass_fuse_add, avr_split_tiny_move): New functions.
3168 (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions.
3169 (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets
3170 of PLUS addressing for AVR_TINY.
3171 (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X.
3172 (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y.
3173 (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS.
3175 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
3177 PR target/114132
3178 * config/avr/avr.h (CUMULATIVE_ARGS) <has_stack_args>: New field.
3179 * config/avr/avr.cc (avr_init_cumulative_args): Initialize it.
3180 (avr_function_arg): Set it.
3181 (avr_frame_pointer_required_p): Use it instead of .nregs.
3183 2024-02-29 Andrew Pinski <quic_apinski@quicinc.com>
3185 PR target/108174
3186 * config/aarch64/aarch64-builtins.cc (aarch64_memtag_builtin_data): Make
3187 static and mark with GTY.
3189 2024-02-29 Xi Ruoyao <xry111@xry111.site>
3191 * config/loongarch/loongarch.md
3192 (loongarch_<crc>_w_<size>_w_extended): New define_insn.
3194 2024-02-29 Xi Ruoyao <xry111@xry111.site>
3196 * config/loongarch/loongarch.md (CRC): New define_int_iterator.
3197 (crc): New define_int_attr.
3198 (loongarch_crc_w_<size>_w, loongarch_crcc_w_<size>_w): Unify
3199 into ...
3200 (loongarch_<crc>_w_<size>_w): ... here.
3202 2024-02-29 Kito Cheng <kito.cheng@sifive.com>
3204 PR target/114130
3205 * config/riscv/sync.md (atomic_compare_and_swap<mode>): Sign
3206 extend the expected value if needed.
3208 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
3210 * config.gcc (target_gtfiles): Change coreout to btfext-out.
3211 (extra_objs): Change coreout to btfext-out.
3212 * config/bpf/coreout.cc: Rename to btfext-out.cc.
3213 * config/bpf/btfext-out.cc: Add.
3214 * config/bpf/coreout.h: Rename to btfext-out.h.
3215 * config/bpf/btfext-out.h: Add.
3216 * config/bpf/core-builtins.cc: Change include.
3217 * config/bpf/core-builtins.h: Change include.
3218 * config/bpf/t-bpf: Accomodate renamed files.
3220 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
3222 PR target/113453
3223 * config/bpf/bpf.cc (bpf_function_prologue): Define target
3224 hook.
3225 * config/bpf/coreout.cc (brf_ext_info_section)
3226 (btf_ext_info): Move from coreout.h
3227 (btf_ext_funcinfo, btf_ext_lineinfo): Add struct.
3228 (bpf_core_reloc): Rename to btf_ext_core_reloc.
3229 (btf_ext): Add static variable.
3230 (btfext_info_sec_find_or_add, SEARCH_NODE_AND_RETURN)
3231 (bpf_create_or_find_funcinfo, bpt_create_core_reloc)
3232 (btf_ext_add_string, btf_funcinfo_type_callback)
3233 (btf_add_func_info_for, btf_validate_funcinfo)
3234 (btf_ext_info_len, output_btfext_func_info): Add function.
3235 (output_btfext_header, bpf_core_reloc_add)
3236 (output_btfext_core_relocs, btf_ext_init, btf_ext_output):
3237 Change to support new structs.
3238 * config/bpf/coreout.h (btf_ext_funcinfo, btf_ext_lineinfo):
3239 Move and change in coreout.cc.
3240 (btf_add_func_info_for, btf_ext_add_string): Add prototypes.
3242 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
3244 * config/bpf/bpf.cc (bpf_option_override): Make .BTF.ext
3245 enabled by default for BPF.
3246 (bpf_file_end): Call BTF deallocation.
3247 (bpf_asm_init_sections): Correct condition.
3248 * dwarf2ctf.cc (ctf_debug_finalize): Conditionally execute BTF
3249 deallocation.
3250 (ctf_debuf_finish): Correct condition for calling
3251 ctf_debug_finalize.
3253 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
3255 * btfout.cc (output_btf_func_types): Use FOR_EACH_VEC_ELT.
3256 (traverse_btf_func_types): Define function.
3257 * ctfc.h (funcs_traverse_callback): Typedef for function
3258 prototype.
3259 (traverse_btf_func_types): Add prototype.
3261 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
3263 * btfout.cc (btf_collect_dataset): Corrects BTF type id.
3265 2024-02-28 Richard Biener <rguenther@suse.de>
3267 PR tree-optimization/113831
3268 PR tree-optimization/108355
3269 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Revert
3270 PR113831 fix.
3272 2024-02-28 Richard Biener <rguenther@suse.de>
3274 PR tree-optimization/114121
3275 * tree-ssa-sccvn.h (vn_reference_s::offset,
3276 vn_reference_s::max_size): New fields.
3277 (vn_reference_insert_pieces): Adjust prototype.
3278 * tree-ssa-pre.cc (phi_translate_1): Preserve offset/max_size.
3279 * tree-ssa-sccvn.cc (vn_reference_eq): Compare offset and
3280 size, allow using "don't know" state.
3281 (vn_walk_cb_data::finish): Pass along offset/max_size.
3282 (vn_reference_lookup_or_insert_for_pieces): Take offset and
3283 max_size as argument and use it.
3284 (vn_reference_lookup_3): Properly adjust offset and max_size
3285 according to the adjusted ao_ref.
3286 (vn_reference_lookup_pieces): Initialize offset and max_size.
3287 (vn_reference_lookup): Likewise.
3288 (vn_reference_lookup_call): Likewise.
3289 (vn_reference_insert): Likewise.
3290 (visit_reference_op_call): Likewise.
3291 (vn_reference_insert_pieces): Take offset and max_size
3292 as argument and use it.
3294 2024-02-28 Juergen Christ <jchrist@linux.ibm.com>
3296 PR tree-optimization/114075
3297 * tree-vect-stmts.cc (vectorizable_operation): Don't emulate floating
3298 point vectors
3300 2024-02-28 Jakub Jelinek <jakub@redhat.com>
3302 PR tree-optimization/114041
3303 * graphite-sese-to-poly.cc (add_conditions_to_domain): Check for
3304 INTEGRAL_TYPE_P check rather than INTEGER_TYPE.
3306 2024-02-28 Jakub Jelinek <jakub@redhat.com>
3308 PR tree-optimization/113988
3309 * stor-layout.h (bitwise_mode_for_size): Declare.
3310 * stor-layout.cc (bitwise_mode_for_size): New function.
3311 * gimple-fold.cc (gimple_fold_builtin_memory_op): Use it.
3312 Use bitwise_type_for_mode instead of build_nonstandard_integer_type.
3313 Use BITS_PER_UNIT instead of 8.
3315 2024-02-27 Uros Bizjak <ubizjak@gmail.com>
3317 PR target/113871
3318 * config/i386/mmx.md (V248FI): Add V2BF mode.
3319 (V24FI_32): Ditto.
3321 2024-02-27 Eric Botcazou <ebotcazou@adacore.com>
3323 * tree-ssa-dse.cc (compute_trims): Fix description. Return early
3324 if either ref->offset is not byte aligned or ref->size is not known
3325 to be equal to ref->max_size.
3326 (maybe_trim_complex_store): Fix description.
3327 (maybe_trim_constructor_store): Likewise.
3328 (maybe_trim_partially_dead_store): Likewise.
3330 2024-02-27 Richard Earnshaw <rearnsha@arm.com>
3332 * config/arm/mmintrin.h: Warn if this header is included without
3333 defining __ENABLE_DEPRECATED_IWMMXT.
3335 2024-02-27 Richard Biener <rguenther@suse.de>
3337 PR tree-optimization/114074
3338 * tree-chrec.h (chrec_convert_rhs): Default at_stmt arg to NULL.
3339 * tree-chrec.cc (chrec_fold_multiply): Canonicalize inputs.
3340 Handle poly vs. non-poly multiplication correctly with respect
3341 to undefined behavior on overflow.
3343 2024-02-27 Jakub Jelinek <jakub@redhat.com>
3345 PR rtl-optimization/114044
3346 * internal-fn.def (CLRSB, CLZ, CTZ, FFS, PARITY): Use
3347 DEF_INTERNAL_INT_EXT_FN macro rather than DEF_INTERNAL_INT_FN.
3348 * internal-fn.h (expand_CLRSB, expand_CLZ, expand_CTZ, expand_FFS,
3349 expand_PARITY): Declare.
3350 * internal-fn.cc (expand_bitquery, expand_CLRSB, expand_CLZ,
3351 expand_CTZ, expand_FFS, expand_PARITY): New functions.
3352 (expand_POPCOUNT): Use expand_bitquery.
3354 2024-02-27 Richard Biener <rguenther@suse.de>
3356 PR tree-optimization/114081
3357 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3358 Perform manual dominator update for prologue peeling.
3359 (vect_do_peeling): Properly update dominators after adding the
3360 prologue-around guard.
3362 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
3364 * config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args)
3365 (mstrict-X): Tag as "Optimization".
3367 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
3369 * config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in
3370 an "if avr_adiw_reg_p()" block that's dead for AVR_TINY.
3372 2024-02-26 Jakub Jelinek <jakub@redhat.com>
3373 H.J. Lu <hjl.tools@gmail.com>
3375 PR rtl-optimization/113617
3376 * varasm.cc (default_elf_select_rtx_section): For
3377 references to private symbols in comdat sections
3378 use .data.relro.local.pool.<comdat>, .data.relro.pool.<comdat>
3379 or .rodata.<comdat> comdat sections.
3381 2024-02-26 Richard Biener <rguenther@suse.de>
3383 PR tree-optimization/114099
3384 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
3385 Create and fill in a needed virtual LC PHI for the alternate
3386 exits. Remove code dealing with that missing.
3388 2024-02-26 Richard Biener <rguenther@suse.de>
3390 PR tree-optimization/114068
3391 * tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge):
3392 New function.
3393 (slpeel_tree_duplicate_loop_to_edge_cfg): Add a virtual LC PHI
3394 on the main exit if needed. Remove band-aid for the case
3395 it was missing.
3397 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
3399 PR target/114097
3400 * config/i386/i386-options.cc (ix86_set_func_type): Check
3401 interrupt instead of noreturn attribute.
3403 2024-02-26 Jakub Jelinek <jakub@redhat.com>
3405 * config/i386/i386.cc (ix86_bitint_type_info): Add support for
3406 !TARGET_64BIT.
3408 2024-02-26 Jakub Jelinek <jakub@redhat.com>
3410 PR tree-optimization/114090
3411 * match.pd ((x >= 0 ? x : 0) + (x <= 0 ? -x : 0) -> abs x):
3412 Restrict pattern to ANY_INTEGRAL_TYPE_P and TYPE_OVERFLOW_UNDEFINED
3413 types.
3414 ((x <= 0 ? -x : 0) -> max(-x, 0)): Likewise.
3416 2024-02-26 Jakub Jelinek <jakub@redhat.com>
3418 PR middle-end/114084
3419 * fold-const.cc (fold_binary_loc): Avoid the final associate_trees
3420 if all subtrees of var0 come from one of the op0 or op1 operands
3421 and all subtrees of con0 come from the other one. Don't clear
3422 variables which are never used afterwards.
3424 2024-02-26 Richard Biener <rguenther@suse.de>
3426 PR middle-end/114070
3427 * genmatch.cc (parser::parse_c_expr): Do not record operand
3428 lists but only mark operators used.
3429 * match.pd ((c ? a : b) op (c ? d : e) --> c ? (a op d) : (b op e)):
3430 Properly guard the case of tcc_comparison changing the VEC_COND
3431 value operand type.
3433 2024-02-26 Jakub Jelinek <jakub@redhat.com>
3435 PR target/114094
3436 * config/i386/i386.cc (x86_function_profiler): Add missing new-line
3437 to printed instruction.
3439 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
3441 PR target/114098
3442 * config/i386/amxtileintrin.h (_tile_loadconfig): Use
3443 __builtin_ia32_ldtilecfg.
3444 (_tile_storeconfig): Use __builtin_ia32_sttilecfg.
3445 * config/i386/i386-builtin.def (BDESC): Add
3446 __builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg.
3447 * config/i386/i386-expand.cc (ix86_expand_builtin): Handle
3448 IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG.
3449 * config/i386/i386.md (ldtilecfg): New pattern.
3450 (sttilecfg): Likewise.
3452 2024-02-24 Richard Sandiford <richard.sandiford@arm.com>
3454 PR tree-optimization/113205
3455 * tree-vect-slp.cc (vect_optimize_slp_pass::forward_cost): Reject
3456 the proposed layout if it does not allow a source partition with
3457 layout 2 to keep that layout.
3459 2024-02-24 Jakub Jelinek <jakub@redhat.com>
3461 * builtins.cc (fold_builtin_isascii): Use HOST_WIDE_INT_UC macro.
3462 * combine.cc (make_field_assignment): Use HOST_WIDE_INT_1U macro.
3463 * double-int.cc (double_int::mask): Use HOST_WIDE_INT_UC macros.
3464 * genattrtab.cc (attr_alt_complement): Use HOST_WIDE_INT_1 macro.
3465 (mk_attr_alt): Use HOST_WIDE_INT_0 macro.
3466 * genautomata.cc (bitmap_set_bit, CLEAR_BIT): Use HOST_WIDE_INT_1
3467 macros.
3468 * ipa-strub.cc (can_strub_internally_p): Use HOST_WIDE_INT_1 macro.
3469 * loop-iv.cc (implies_p): Use HOST_WIDE_INT_1U macro.
3470 * pretty-print.cc (test_pp_format): Use HOST_WIDE_INT_C and
3471 HOST_WIDE_INT_UC macros.
3472 * rtlanal.cc (nonzero_bits1): Use HOST_WIDE_INT_UC macro.
3473 * tree.cc (build_replicated_int_cst): Use HOST_WIDE_INT_1U macro.
3474 * tree.h (DECL_OFFSET_ALIGN): Use HOST_WIDE_INT_1U macro.
3475 * tree-ssa-structalias.cc (dump_varinfo): Use ~HOST_WIDE_INT_0U
3476 macros.
3477 * wide-int.cc (divmod_internal_2): Use HOST_WIDE_INT_1U macro.
3478 * config/i386/constraints.md (define_constraint "L"): Use
3479 HOST_WIDE_INT_C macro.
3480 * config/i386/i386.md (movabsq split peephole2): Use HOST_WIDE_INT_C
3481 macro.
3482 (movl + movb peephole2): Likewise.
3483 * config/i386/predicates.md (x86_64_zext_immediate_operand): Likewise.
3484 (const_32bit_mask): Likewise.
3486 2024-02-24 Jakub Jelinek <jakub@redhat.com>
3488 PR middle-end/114073
3489 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle
3490 VIEW_CONVERT_EXPRs between large/huge _BitInt and non-integer/pointer
3491 types like vector or complex types.
3492 (gimple_lower_bitint): Don't merge VIEW_CONVERT_EXPRs to non-integral
3493 types. Fix up VIEW_CONVERT_EXPR handling. Allow merging
3494 VIEW_CONVERT_EXPR from non-integral/pointer types with a store.
3496 2024-02-23 Robin Dapp <rdapp@ventanamicro.com>
3498 PR target/114028
3499 * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p):
3500 Return false if inner mode is already Pmode.
3501 (rvv_builder::is_all_same_sequence): New function.
3502 (expand_vec_init): Emit broadcast if sequence is all same.
3504 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
3506 PR target/113613
3507 * config/aarch64/aarch64-early-ra.cc
3508 (early_ra::m_current_region): New member variable.
3509 (early_ra::m_fpr_recency): Likewise.
3510 (early_ra::start_new_region): Bump m_current_region.
3511 (early_ra::allocate_colors): Prefer less recently used registers
3512 in the event of a tie. Add a comment to explain why we prefer(ed)
3513 higher-numbered registers.
3514 (early_ra::find_oldest_color): Prefer less recently used registers
3515 here too.
3516 (early_ra::finalize_allocation): Update recency information for
3517 allocated registers.
3518 (early_ra::process_blocks): Initialize m_current_region and
3519 m_fpr_recency.
3521 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
3523 PR target/113295
3524 * config/aarch64/aarch64-early-ra.cc
3525 (early_ra::test_strictness): New enum.
3526 (early_ra::is_chain_candidate): Add a strictness parameter to
3527 control whether only correctness matters, or whether both correctness
3528 and heuristics should be used. Handle multiple levels of equivalence.
3529 (early_ra::find_related_start): Update call accordingly.
3530 (early_ra::strided_polarity_pref): Likewise.
3531 (early_ra::form_chains): Likewise.
3532 (early_ra::try_to_chain_allocnos): Use is_chain_candidate in
3533 correctness mode rather than trying to inline the test.
3535 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
3537 PR target/113295
3538 * config/aarch64/aarch64-early-ra.cc
3539 (early_ra::find_related_start): Account for definitions by shared
3540 registers when testing for a single register definition.
3541 (early_ra::accumulate_defs): New function.
3542 (early_ra::record_copy): If A shares B's register, fold A's
3543 definition information into B's. Fold A's use information into B's.
3545 2024-02-23 H.J. Lu <hjl.tools@gmail.com>
3547 * configure.ac (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF): Defined as 1
3548 if R_X86_64_CODE_6_GOTTPOFF is supported.
3549 * config.in: Regenerated.
3550 * configure: Likewise.
3551 * config/i386/predicates.md (apx_ndd_add_memory_operand): Allow
3552 UNSPEC_GOTNTPOFF if R_X86_64_CODE_6_GOTTPOFF is supported.
3554 2024-02-23 Richard Earnshaw <rearnsha@arm.com>
3556 PR target/108120
3557 * config/arm/neon.md (div<VCVTF:mode>3): Rename from div<mode>3.
3558 Gate with ARM_HAVE_NEON_<MODE>_ARITH.
3560 2024-02-23 Jakub Jelinek <jakub@redhat.com>
3562 PR rtl-optimization/114054
3563 * expr.cc (expand_expr_real_2) <case MULT_EXPR>: Use
3564 temp variable instead of target parameter for result.
3566 2024-02-23 Jakub Jelinek <jakub@redhat.com>
3568 PR tree-optimization/114040
3569 * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
3570 Use EQ_EXPR rather than LT_EXPR for g2 condition and change its
3571 probability from likely to unlikely. When handling the true true
3572 store, first cast to limb_access_type and then to l's type.
3574 2024-02-23 Richard Biener <rguenther@suse.de>
3576 PR target/90785
3577 * config.gcc: Add ia64*-*-* to the list of obsoleted targets.
3579 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
3581 PR other/109668
3582 * config/riscv/arch-canonicalize: Move to python3
3583 * config/riscv/multilib-generator: Likewise
3585 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
3587 * doc/invoke.texi: Document -mcpu.
3589 2024-02-23 Lulu Cheng <chenglulu@loongson.cn>
3591 * configure: Regenerate.
3592 * configure.ac: Add parameter "--fatal-warnings" to assemble
3593 when checking whether the assemble support conditional branch
3594 relaxation.
3596 2024-02-22 Jakub Jelinek <jakub@redhat.com>
3598 PR c/114007
3599 * doc/extend.texi: (__extension__): Remove comments about scope
3600 tokens vs. two colons.
3602 2024-02-22 Andrew Pinski <quic_apinski@quicinc.com>
3604 PR tree-optimization/109804
3605 * gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle
3606 DEMANGLE_COMPONENT_UNNAMED_TYPE.
3608 2024-02-22 Richard Biener <rguenther@suse.de>
3610 PR tree-optimization/114048
3611 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): MEM_REF
3612 can also produce -1 off.
3614 2024-02-22 Richard Biener <rguenther@suse.de>
3616 PR tree-optimization/114027
3617 * tree-vect-loop.cc (vecctorizable_reduction): Use optimized
3618 condition reduction classification only for single-element
3619 chains.
3621 2024-02-22 Jakub Jelinek <jakub@redhat.com>
3623 PR ipa/111960
3624 * profile-count.h (profile_count::dump): Remove overload with
3625 char * first argument.
3626 * profile-count.cc (profile_count::dump): Change overload with char *
3627 first argument which uses sprintf into the overfload with FILE *
3628 first argument and use fprintf instead. Remove overload which wrapped
3629 it.
3631 2024-02-22 Jakub Jelinek <jakub@redhat.com>
3633 PR tree-optimization/113993
3634 * tree-call-cdce.cc (get_no_error_domain): Handle
3635 BUILT_IN_{COSH,SINH,EXP{,M1,2}}{F32X,F64X}. Handle
3636 BUILT_IN_{COSH,SINH,EXP{,M1,2}}L for
3637 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
3638 the as the F128 suffixed cases, otherwise as non-suffixed ones.
3639 Handle BUILT_IN_{EXP,POW}10L for
3640 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
3641 as (-inf, 4932).
3643 2024-02-22 Jakub Jelinek <jakub@redhat.com>
3645 PR tree-optimization/114038
3646 * gimple-lower-bitint.cc (bitint_large_huge::lower_mul_overflow): Fix
3647 loop exit condition if end is divisible by limb_prec.
3649 2024-02-22 YunQiang Su <syq@gcc.gnu.org>
3651 * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix
3652 problem of mabi=, mno-flush-func, mexplicit-relocs;
3653 add missing leading - of mbranch-cost option.
3654 * config/mips/mips.opt.urls: Regenerate.
3656 2024-02-22 Kewen Lin <linkw@linux.ibm.com>
3658 PR target/109987
3659 * config/rs6000/constraints.md (we): Update internal doc without
3660 referring to option -mpower9-vector.
3661 * config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector
3662 special handlings.
3663 * config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS,
3664 OTHER_P8_VECTOR_MASKS): Merge to ...
3665 (OTHER_VSX_VECTOR_MASKS): ... here.
3666 * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove
3667 some error message handlings and explicit option mask adjustments on
3668 explicit option power{8,9}-vector conflicting with other options.
3669 (rs6000_print_isa_options): Update comments.
3670 (rs6000_disable_incompatible_switches): Remove power{8,9}-vector
3671 related array items and handlings.
3672 * config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector
3673 special handlings.
3674 * config/rs6000/rs6000.opt: Make option power{8,9}-vector as
3675 WarnRemoved.
3676 * doc/extend.texi: Remove documentation referring to option
3677 -mpower8-vector.
3678 * doc/invoke.texi: Remove documentation for option
3679 -mpower{8,9}-vector and adjust some documentation referring to them.
3680 * doc/md.texi: Update documentation for constraint we.
3681 * doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok.
3683 2024-02-22 Pan Li <pan2.li@intel.com>
3685 PR target/114017
3686 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade
3687 the version to 0.12.
3689 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
3691 * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert
3693 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
3694 Robin Dapp <rdapp.gcc@gmail.com>
3696 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
3697 (generic_ooo_vec_load): Ditto
3698 (generic_ooo_vec_store): Ditto
3699 (generic_ooo_vec_loadstore_seg): Ditto
3700 (generic_ooo_vec_alu): Ditto
3701 (generic_ooo_vec_fcmp): Ditto
3702 (generic_ooo_vec_imul): Ditto
3703 (generic_ooo_vec_fadd): Ditto
3704 (generic_ooo_vec_fmul): Ditto
3705 (generic_ooo_crypto): Ditto
3706 (generic_ooo_perm): Ditto
3707 (generic_ooo_vec_reduction): Ditto
3708 (generic_ooo_vec_ordered_reduction): Ditto
3709 (generic_ooo_vec_idiv): Ditto
3710 (generic_ooo_vec_float_divsqrt): Ditto
3711 (generic_ooo_vec_mask): Ditto
3712 (generic_ooo_vec_vesetvl): Ditto
3713 (generic_ooo_vec_setrm): Ditto
3714 (generic_ooo_vec_readlen): Ditto
3715 * config/riscv/riscv.md: Include generic-vector-ooo
3716 * config/riscv/generic-vector-ooo.md: New file. To here
3718 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
3720 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
3721 (generic_ooo_branch): Ditto
3722 * config/riscv/generic.md (generic_sfb_alu): Ditto
3723 (generic_fmul_half): Ditto
3724 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
3725 * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
3726 (sifive_7_popcount): Ditto
3727 * config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto
3728 * config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto
3729 * config/riscv/vector.md: Change rdfrm to fmove
3730 * config/riscv/zc.md: Change pushpop to load/store
3732 2024-02-21 Jonathan Wakely <jwakely@redhat.com>
3734 * doc/invoke.texi (Warning Options): Fix typos.
3736 2024-02-21 David Faust <david.faust@oracle.com>
3738 * config/bpf/bpf-protos.h (bpf_expand_cpymem): New.
3739 * config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New.
3740 * config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands.
3742 2024-02-21 Martin Jambor <mjambor@suse.cz>
3744 PR ipa/113476
3745 * ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust
3746 initializers in the contructor.
3747 (ipa_node_params::~ipa_node_params): Release lattices as a vector.
3748 * ipa-cp.h: New file.
3749 * ipa-cp.cc: Include sreal.h and ipa-cp.h.
3750 (ipcp_value_source): Move to ipa-cp.h.
3751 (ipcp_value_base): Likewise.
3752 (ipcp_value): Likewise.
3753 (ipcp_lattice): Likewise.
3754 (ipcp_agg_lattice): Likewise.
3755 (ipcp_bits_lattice): Likewise.
3756 (ipcp_vr_lattice): Likewise.
3757 (ipcp_param_lattices): Likewise.
3758 (ipa_get_parm_lattices): Remove assert latticess is non-NULL.
3759 (ipa_value_from_jfunc): Adjust a check for empty lattices.
3760 (ipa_context_from_jfunc): Likewise.
3761 (ipa_agg_value_from_jfunc): Likewise.
3762 (merge_agg_lats_step): Do not memset new aggregate lattices to zero.
3763 (ipcp_propagate_stage): Allocate lattices in a vector as opposed to
3764 just in contiguous memory.
3765 (ipcp_store_vr_results): Adjust a check for empty lattices.
3766 * auto-profile.cc: Include sreal.h and ipa-cp.h.
3767 * cgraph.cc: Likewise.
3768 * cgraphclones.cc: Likewise.
3769 * cgraphunit.cc: Likewise.
3770 * config/aarch64/aarch64.cc: Likewise.
3771 * config/i386/i386-builtins.cc: Likewise.
3772 * config/i386/i386-expand.cc: Likewise.
3773 * config/i386/i386-features.cc: Likewise.
3774 * config/i386/i386-options.cc: Likewise.
3775 * config/i386/i386.cc: Likewise.
3776 * config/rs6000/rs6000.cc: Likewise.
3777 * config/s390/s390.cc: Likewise.
3778 * gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the
3779 files to be included in gtype-desc.cc.
3780 * gimple-range-fold.cc: Include sreal.h and ipa-cp.h.
3781 * ipa-devirt.cc: Likewise.
3782 * ipa-fnsummary.cc: Likewise.
3783 * ipa-icf.cc: Likewise.
3784 * ipa-inline-analysis.cc: Likewise.
3785 * ipa-inline-transform.cc: Likewise.
3786 * ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher.
3787 * ipa-modref.cc: Include sreal.h and ipa-cp.h.
3788 * ipa-param-manipulation.cc: Likewise.
3789 * ipa-predicate.cc: Likewise.
3790 * ipa-profile.cc: Likewise.
3791 * ipa-prop.cc: Likewise.
3792 (ipa_node_params_t::duplicate): Assert new lattices remain empty
3793 instead of setting them to NULL.
3794 * ipa-pure-const.cc: Include sreal.h and ipa-cp.h.
3795 * ipa-split.cc: Likewise.
3796 * ipa-sra.cc: Likewise.
3797 * ipa-strub.cc: Likewise.
3798 * ipa-utils.cc: Likewise.
3799 * ipa.cc: Likewise.
3800 * toplev.cc: Likewise.
3801 * tree-ssa-ccp.cc: Likewise.
3802 * tree-ssa-sccvn.cc: Likewise.
3803 * tree-vrp.cc: Likewise.
3805 2024-02-21 Tamar Christina <tamar.christina@arm.com>
3807 * config/aarch64/aarch64-arches.def (AARCH64_ARCH): Remove LS64 from
3808 Armv8.7-a.
3810 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
3812 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
3813 Use aarch64_gen_compare_zero_and_branch rather than emitting
3814 a CBZ directly.
3816 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
3818 * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
3819 Remove duplicated call.
3821 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
3823 * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall):
3824 Check that each individual piece of state is shared in the same
3825 way, rather than using an aggregate check for PSTATE.ZA.
3827 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
3829 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
3830 In the code that commits a lazy save, only zero ZA if the function
3831 has ZA state. Similarly zero ZT0 if the function has ZT0 state.
3833 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
3835 * config/aarch64/aarch64-sme.md (aarch64_commit_lazy_save): Remove,
3836 directly inserting the associated sequence
3837 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
3838 ...here instead.
3840 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
3842 PR target/113995
3843 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Don't
3844 fold the SVE allocation into the initial allocation if the
3845 initial allocation includes a VG save.
3847 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
3849 PR target/113220
3850 * cfgrtl.cc (commit_one_edge_insertion): Handle sequences that
3851 contain jumps even if called after initial RTL expansion.
3852 * mode-switching.cc: Include cfgbuild.h.
3853 (optimize_mode_switching): Allow the sequence returned by the
3854 emit hook to contain internal jumps. Record which blocks
3855 contain such jumps and split the blocks at the end.
3856 * config/aarch64/aarch64.cc (aarch64_mode_emit): Check for
3857 non-debug insns when scanning the sequence.
3859 2024-02-21 Tobias Burnus <tburnus@baylibre.com>
3861 * config/nvptx/gen-omp-device-properties.sh: Add 'nvptx64' to arch.
3862 * config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Likewise.
3864 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
3866 * doc/invoke.texi (-mmcu): Add information about MCU specs.
3868 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
3870 * doc/invoke.texi (-minrt): Clarify that main
3871 must take no arguments.
3873 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
3875 * config/avr/builtins.def: Use function prototypes of given size
3876 and signedness.
3877 * config/avr/avr.cc (avr_init_builtins): Adjust types required
3878 by builtins.def.
3879 * doc/extend.texi (AVR Built-in Functions): Adjust accordingly.
3881 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
3883 * doc/extend.texi (AVR Built-in Functions): Use @defbuiltin
3884 instead of @table.
3886 2024-02-20 Will Hawkins <hawkinsw@obs.cr>
3888 * config/bpf/bpf.opt: Add help information for -mcpu.
3890 2024-02-20 Richard Sandiford <richard.sandiford@arm.com>
3892 PR target/113805
3893 * config/aarch64/aarch64-passes.def (pass_late_track_speculation):
3894 New pass.
3895 * config/aarch64/aarch64-protos.h (make_pass_late_track_speculation):
3896 Declare.
3897 * config/aarch64/aarch64.md (is_call): New attribute.
3898 (*and<mode>3nr_compare0): Rename to...
3899 (@aarch64_and<mode>3nr_compare0): ...this.
3900 * config/aarch64/aarch64-sme.md (aarch64_get_sme_state)
3901 (aarch64_tpidr2_save, aarch64_tpidr2_restore): Add is_call attributes.
3902 * config/aarch64/aarch64-speculation.cc: Update file comment to
3903 describe the new late pass.
3904 (aarch64_do_track_speculation): Handle is_call insns like other calls.
3905 (pass_track_speculation): Add an is_late member variable.
3906 (pass_track_speculation::gate): Run the late pass for streaming-
3907 compatible functions and the early pass for other functions.
3908 (make_pass_track_speculation): Update accordingly.
3909 (make_pass_late_track_speculation): New function.
3910 * config/aarch64/aarch64.cc (aarch64_gen_test_and_branch): New
3911 function.
3912 (aarch64_guard_switch_pstate_sm): Use it.
3914 2024-02-19 Iain Sandoe <iain@sandoe.co.uk>
3916 * config/aarch64/aarch64-builtins.cc (aarch64_init_rng_builtins):
3917 Register these builtins with a pointer to uint64_t rather than unsigned
3918 DI mode.
3920 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
3922 PR target/113615
3923 * config/gcn/gcn-valu.md (define_expand "reduc_<fexpander>_scal_<mode>"):
3924 Conditionalize on '!TARGET_RDNA2_PLUS'.
3925 * config/gcn/gcn.cc (gcn_expand_dpp_shr_insn)
3926 (gcn_expand_reduc_scalar):
3927 'gcc_checking_assert (!TARGET_RDNA2_PLUS);'.
3929 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
3931 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Restore lost
3932 '__gfx90a__' target CPU definition. Add some safeguards for the future.
3934 2024-02-19 Richard Biener <rguenther@suse.de>
3936 PR rtl-optimization/54052
3937 * rtl-ssa/blocks.cc (function_info::place_phis): Filter
3938 local defs by LR_OUT.
3940 2024-02-19 Jakub Jelinek <jakub@redhat.com>
3942 PR tree-optimization/113967
3943 * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..): Require
3944 in condition that @rpos is multiple of vector element size.
3946 2024-02-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3948 PR target/113696
3949 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
3950 Suppress vsetvl fusion.
3952 2024-02-18 H.J. Lu <hjl.tools@gmail.com>
3954 PR target/113912
3955 * config/i386/i386.cc (ix86_can_use_push2pop2): New.
3956 (ix86_pro_and_epilogue_can_use_push2pop2): Use it.
3957 (ix86_emit_save_regs): Don't generate push2 if
3958 ix86_can_use_push2pop2 return false.
3959 (ix86_expand_epilogue): Don't generate pop2 if
3960 ix86_can_use_push2pop2 return false.
3962 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
3964 * doc/invoke.texi (AVR Options) <-mmcu>: Remove "Atmel".
3965 Note on complete device support.
3967 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
3969 * doc/extend.texi (AVR Function Attributes): Fuse description
3970 of "signal" and "interrupt" attribute. Link pseudo instruction.
3972 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
3974 * config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant
3975 symbol type conversions.
3976 (__cacop_d): Likewise.
3977 (__cpucfg): Likewise.
3978 (__asrtle_d): Likewise.
3979 (__asrtgt_d): Likewise.
3980 (__lddir_d): Likewise.
3981 (__ldpte_d): Likewise.
3982 (__crc_w_b_w): Likewise.
3983 (__crc_w_h_w): Likewise.
3984 (__crc_w_w_w): Likewise.
3985 (__crc_w_d_w): Likewise.
3986 (__crcc_w_b_w): Likewise.
3987 (__crcc_w_h_w): Likewise.
3988 (__crcc_w_w_w): Likewise.
3989 (__crcc_w_d_w): Likewise.
3990 (__csrrd_w): Likewise.
3991 (__csrwr_w): Likewise.
3992 (__csrxchg_w): Likewise.
3993 (__csrrd_d): Likewise.
3994 (__csrwr_d): Likewise.
3995 (__csrxchg_d): Likewise.
3996 (__iocsrrd_b): Likewise.
3997 (__iocsrrd_h): Likewise.
3998 (__iocsrrd_w): Likewise.
3999 (__iocsrrd_d): Likewise.
4000 (__iocsrwr_b): Likewise.
4001 (__iocsrwr_h): Likewise.
4002 (__iocsrwr_w): Likewise.
4003 (__iocsrwr_d): Likewise.
4004 (__frecipe_s): Likewise.
4005 (__frecipe_d): Likewise.
4006 (__frsqrte_s): Likewise.
4007 (__frsqrte_d): Likewise.
4009 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
4011 * config/loongarch/larchintrin.h (__iocsrrd_h): Modify the
4012 function return value type to unsigned short.
4014 2024-02-16 Edwin Lu <ewlu@rivosinc.com>
4016 * doc/sourcebuild.texi: add scan-assembler-bound
4018 2024-02-16 Jason Merrill <jason@redhat.com>
4020 * gdbhooks.py: Fix regex syntax.
4022 2024-02-16 Richard Biener <rguenther@suse.de>
4024 PR tree-optimization/113895
4025 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Disable
4026 consistency checking when there are out-of-bound array
4027 accesses. Allow -1 off when from an array reference with
4028 constant index.
4030 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
4032 PR target/106543
4033 * config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm
4034 pattern.
4036 2024-02-16 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
4038 * doc/sourcebuild.texi (Effective-Target Keywords, Other
4039 attribugs): Document linker_plugin.
4040 (Require Support): Document dg-require-linker-plugin.
4042 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
4044 PR target/109349
4045 * common/config/riscv/riscv-common.cc (riscv_arch_help): New.
4046 * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New.
4047 (RISCV_MINOR_VERSION_BASE): Ditto.
4048 (RISCV_REVISION_VERSION_BASE): Ditto.
4049 * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum
4050 rather than magic number.
4051 * config/riscv/riscv.h (riscv_arch_help): New.
4052 (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help.
4053 (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and
4054 --print-supported-extensions.
4055 * config/riscv/riscv.opt (march=help): New.
4056 (print-supported-extensions): New.
4057 (-print-supported-extensions): New.
4058 * doc/invoke.texi (RISC-V Options): Document -march=help.
4060 2024-02-16 Tejas Belagod <tejas.belagod@arm.com>
4062 PR target/113780
4063 * config/arm/arm.cc (arm_function_ok_for_sibcall): Don't allow tailcalls
4064 for indirect calls with 4 or more arguments in pac-enabled functions.
4066 2024-02-15 David Faust <david.faust@oracle.com>
4068 * config/bpf/bpf.md (zero_extendqidi2): Correct asm template to
4069 use ldxb instead of ldxh.
4071 2024-02-15 Jakub Jelinek <jakub@redhat.com>
4073 PR middle-end/113921
4074 * cfgrtl.h (prepend_insn_to_edge): New declaration.
4075 * cfgrtl.cc (insert_insn_on_edge): Clarify behavior in function
4076 comment.
4077 (prepend_insn_to_edge): New function.
4078 * cfgexpand.cc (expand_asm_stmt): Use prepend_insn_to_edge instead of
4079 insert_insn_on_edge.
4081 2024-02-15 Richard Biener <rguenther@suse.de>
4083 PR tree-optimization/111156
4084 * tree-vect-loop.cc (vect_dissolve_slp_only_groups): Look
4085 at the pattern stmt if any.
4087 2024-02-15 Georg-Johann Lay <avr@gjlay.de>
4089 PR target/113927
4090 * config/avr/avr.h (AVR_HAVE_ADIW): New macro.
4091 * config/avr/avr-protos.h (avr_adiw_reg_p): New proto.
4092 * config/avr/avr.cc (avr_adiw_reg_p): New function.
4093 (avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS.
4094 Replace test_hard_reg_class (ADDW_REGS, ...) with calls to
4095 * config/avr/avr.md: Same.
4096 (attr "isa") <tiny, no_tiny>: Remove.
4097 <adiw, no_adiw>: Add.
4098 (define_insn, define_insn_and_split): When an alternative has
4099 constraint "w", then set attribute "isa" to "adiw".
4100 * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]:
4101 Built-in define __AVR_HAVE_ADIW__.
4102 * doc/invoke.texi (AVR Options): Document it.
4104 2024-02-15 Andrew Stubbs <ams@baylibre.com>
4106 * config/gcn/gcn-valu.md
4107 (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): Add conditions for RDNA.
4108 * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Check permutation
4109 details are supported on RDNA devices.
4111 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
4113 PR middle-end/113508
4114 * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
4115 usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
4116 smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
4117 Add sentence about what the mode m is.
4119 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
4121 * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
4122 smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
4123 var.
4125 2024-02-15 Richard Biener <rguenther@suse.de>
4127 * tree-ssa-tail-merge.cc (same_succ_hash): Skip debug
4128 stmts.
4130 2024-02-15 Jakub Jelinek <jakub@redhat.com>
4132 PR tree-optimization/113567
4133 * gimple-lower-bitint.cc (gimple_lower_bitint): For large/huge
4134 _BitInt multiplication, division or modulo with
4135 SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs and at least one of rhs1 and rhs2
4136 force the affected inputs into a new SSA_NAME.
4138 2024-02-14 Uros Bizjak <ubizjak@gmail.com>
4140 PR target/113871
4141 * config/i386/mmx.md (V248FI): New mode iterator.
4142 (V24FI_32): DItto.
4143 (vec_shl_<V248FI:mode>): New expander.
4144 (vec_shl_<V24FI_32:mode>): Ditto.
4145 (vec_shr_<V248FI:mode>): Ditto.
4146 (vec_shr_<V24FI_32:mode>): Ditto.
4147 * config/i386/sse.md (vec_shl_<V_128:mode>): Simplify expander.
4148 (vec_shr_<V248FI:mode>): Ditto.
4150 2024-02-14 Jan Hubicka <jh@suse.cz>
4152 PR tree-optimization/111054
4153 * tree-ssa-loop-split.cc (split_loop): Check for profile being present.
4155 2024-02-14 Tamar Christina <tamar.christina@arm.com>
4157 * tree-cfg.cc (replace_loop_annotate): Inspect loop edges for annotations.
4159 2024-02-14 Richard Biener <rguenther@suse.de>
4161 PR tree-optimization/113910
4162 * bitmap.cc (bitmap_hash): Mix the full element "hash" to
4163 the hashval_t hash.
4165 2024-02-14 Jakub Jelinek <jakub@redhat.com>
4167 * pretty-print.cc (PTRDIFF_MAX): Define if not yet defined.
4168 (pp_integer_with_precision): For unsigned ptrdiff_t printing
4169 with u, o or x print ptrdiff_t argument converted to
4170 unsigned long long and masked with 2ULL * PTRDIFF_MAX + 1.
4172 2024-02-14 Richard Biener <rguenther@suse.de>
4174 PR middle-end/113576
4175 * expr.cc (do_store_flag): For vector bool compares of vectors
4176 with padding zero that.
4177 * dojump.cc (do_compare_and_jump): Likewise.
4179 2024-02-14 Gerald Pfeifer <gerald@pfeifer.com>
4181 * doc/install.texi (Prerequisites): Update gettext link.
4183 2024-02-13 H.J. Lu <hjl.tools@gmail.com>
4185 PR target/113876
4186 * config/i386/i386.cc (ix86_pro_and_epilogue_can_use_push2pop2):
4187 Return false if the incoming stack isn't 16-byte aligned.
4189 2024-02-13 Tobias Burnus <tburnus@baylibre.com>
4191 PR middle-end/113904
4192 * omp-general.cc (struct omp_ts_info): Update for splitting of
4193 OMP_TRAIT_PROPERTY_EXPR into OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
4194 * omp-selectors.h (enum omp_tp_type): Replace
4195 OMP_TRAIT_PROPERTY_EXPR by OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
4197 2024-02-13 Monk Chiang <monk.chiang@sifive.com>
4199 PR target/113742
4200 * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
4201 recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
4203 2024-02-13 Richard Biener <rguenther@suse.de>
4205 PR tree-optimization/113895
4206 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Track
4207 offset to discover constant array indices in bits, handle
4208 COMPONENT_REF to bitfields.
4210 2024-02-13 Richard Biener <rguenther@suse.de>
4212 PR tree-optimization/113831
4213 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Fix
4214 typo in comment.
4216 2024-02-13 Richard Biener <rguenther@suse.de>
4218 PR tree-optimization/113902
4219 * tree-vect-loop.cc (move_early_exit_stmts): Track
4220 last_seen_vuse for VUSE updating.
4222 2024-02-13 Tamar Christina <tamar.christina@arm.com>
4224 PR tree-optimization/113734
4225 * tree-vect-loop.cc (vect_transform_loop): Treat the final iteration of
4226 an early break loop as partial.
4228 2024-02-13 Richard Biener <rguenther@suse.de>
4230 PR tree-optimization/113898
4231 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Add
4232 missing accumulated off adjustment.
4234 2024-02-13 Jakub Jelinek <jakub@redhat.com>
4236 * hwint.h (GCC_PRISZ, fmt_size_t): Fix preprocessor conditions,
4237 instead of comparing SIZE_MAX against INT_MAX and LONG_MAX compare
4238 it against UINT_MAX and ULONG_MAX.
4240 2024-02-13 David Malcolm <dmalcolm@redhat.com>
4242 * diagnostic-core.h (emit_diagnostic_valist): Rename overload
4243 to...
4244 (emit_diagnostic_valist_meta): ...this.
4245 * diagnostic.cc (emit_diagnostic_valist): Likewise, to...
4246 (emit_diagnostic_valist_meta): ...this.
4248 2024-02-12 Jakub Jelinek <jakub@redhat.com>
4250 PR tree-optimization/113849
4251 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't use
4252 fast path for widening casts where !m_upwards_2limb and lhs_type
4253 has precision which is a multiple of limb_prec.
4255 2024-02-12 Jakub Jelinek <jakub@redhat.com>
4257 PR c++/113674
4258 * attribs.cc (extract_attribute_substring): Remove.
4259 (lookup_scoped_attribute_spec): Don't call it.
4261 2024-02-12 Jakub Jelinek <jakub@redhat.com>
4263 * gengtype.cc (adjust_field_rtx_def): Use HOST_SIZE_T_PRINT_UNSIGNED
4264 and cast to fmt_size_t instead of %lu and cast to unsigned long.
4266 2024-02-12 Christophe Lyon <christophe.lyon@linaro.org>
4268 * Makefile.in: Add no-info dependency.
4269 * configure.ac: Set BUILD_INFO=no-info if makeinfo is not
4270 available.
4271 * configure: Regenerate.
4273 2024-02-12 Iain Sandoe <iain@sandoe.co.uk>
4275 PR target/113855
4276 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): Moved to be
4277 available to all sub-targets.
4278 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): Delete.
4279 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): Delete.
4281 2024-02-12 Richard Biener <rguenther@suse.de>
4283 PR tree-optimization/113831
4284 PR tree-optimization/108355
4285 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): When
4286 we see variable array indices and get_ref_base_and_extent
4287 can resolve those to constants fix up the ops to constants
4288 as well.
4289 (ao_ref_init_from_vn_reference): Use 'off' member for
4290 ARRAY_REF and ARRAY_RANGE_REF instead of recomputing it.
4291 (valueize_refs_1): Also fixup 'off' of ARRAY_RANGE_REF.
4293 2024-02-12 Pan Li <pan2.li@intel.com>
4295 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin):
4296 Replace args to arguments for misspelled term.
4298 2024-02-12 Georg-Johann Lay <avr@gjlay.de>
4300 PR target/112944
4301 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) [have_flmap]:
4302 <*link_rodata_in_ram>: Spec undefs symbol __do_flmap_init
4303 when not linked with -mrodata-in-ram.
4305 2024-02-12 Richard Biener <rguenther@suse.de>
4307 PR tree-optimization/113863
4308 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
4309 Record crossed virtual PHIs.
4310 * tree-vect-loop.cc (move_early_exit_stmts): Elide crossed
4311 virtual PHIs.
4313 2024-02-10 Marek Polacek <polacek@redhat.com>
4315 DR 2237
4316 PR c++/107126
4317 PR c++/97202
4318 * doc/invoke.texi: Document -Wtemplate-id-cdtor.
4320 2024-02-10 Jakub Jelinek <jakub@redhat.com>
4322 * gimple-lower-bitint.cc (itint_large_huge::lower_addsub_overflow): Fix
4323 computation of idx for i == 4 of bitint_prec_huge.
4325 2024-02-10 Jakub Jelinek <jakub@redhat.com>
4327 PR middle-end/110754
4328 * gimple-low.cc (assumption_copy_decl): For TREE_THIS_VOLATILE
4329 decls create PARM_DECL with pointer to original type, set
4330 TREE_READONLY and keep TREE_THIS_VOLATILE, TREE_ADDRESSABLE,
4331 DECL_NOT_GIMPLE_REG_P and DECL_BY_REFERENCE cleared.
4332 (adjust_assumption_stmt_op): For remapped TREE_THIS_VOLATILE decls
4333 wrap PARM_DECL into a simple TREE_THIS_NO_TRAP MEM_REF.
4334 (lower_assumption): For TREE_THIS_VOLATILE vars pass ADDR_EXPR
4335 of the var as argument.
4337 2024-02-10 Jakub Jelinek <jakub@redhat.com>
4339 * pretty-print.cc (pp_integer_with_precision): Handle precision 3 for
4340 size_t and precision 4 for ptrdiff_t. Formatting fix.
4341 (pp_format): Document %{t,z}{d,i,u,o,x}. Implement t and z modifiers.
4342 Formatting fixes.
4343 (test_pp_format): Test t and z modifiers.
4344 * gcc.cc (read_specs): Use %td instead of %ld and casts to long.
4346 2024-02-10 Jakub Jelinek <jakub@redhat.com>
4348 * ipa-icf.cc (sem_item_optimizer::process_cong_reduction,
4349 sem_item_optimizer::dump_cong_classes): Use HOST_SIZE_T_PRINT_UNSIGNED
4350 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
4351 * tree.cc (print_debug_expr_statistics): Use HOST_SIZE_T_PRINT_DEC
4352 and casts to fmt_size_t instead of "%ld" and casts to long.
4353 (print_value_expr_statistics, print_type_hash_statistics): Likewise.
4354 * dwarf2out.cc (output_macinfo_op): Use HOST_WIDE_INT_PRINT_UNSIGNED
4355 instead of "%lu" and casts to unsigned long.
4356 * gcov-dump.cc (dump_gcov_file): Use %u instead of %lu and casts to
4357 unsigned long.
4358 * tree-ssa-dom.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
4359 and casts to fmt_size_t instead of "%ld" and casts to long.
4360 * cfgexpand.cc (dump_stack_var_partition): Use
4361 HOST_SIZE_T_PRINT_UNSIGNED and casts to fmt_size_t instead of "%lu"
4362 and casts to unsigned long.
4363 * gengtype.cc (adjust_field_rtx_def): Likewise.
4364 * tree-into-ssa.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
4365 and casts to fmt_size_t instead of "%ld" and casts to long.
4366 * postreload-gcse.cc (dump_hash_table): Likewise.
4367 * ggc-page.cc (alloc_page): Use HOST_SIZE_T_PRINT_UNSIGNED
4368 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
4369 (ggc_internal_alloc, ggc_free): Likewise.
4370 * genpreds.cc (write_lookup_constraint_1): Likewise.
4371 (write_insn_constraint_len): Likewise.
4372 * tree-dfa.cc (dump_dfa_stats): Use HOST_SIZE_T_PRINT_DEC
4373 and casts to fmt_size_t instead of "%ld" and casts to long.
4374 * varasm.cc (output_constant_pool_contents): Use
4375 HOST_WIDE_INT_PRINT_DEC instead of "%ld" and casts to long.
4376 * var-tracking.cc (dump_var): Likewise.
4378 2024-02-09 Jakub Jelinek <jakub@redhat.com>
4380 PR tree-optimization/113783
4381 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Look
4382 through VIEW_CONVERT_EXPR for final cast checks. Handle
4383 VIEW_CONVERT_EXPRs from large/huge _BitInt to > MAX_FIXED_MODE_SIZE
4384 INTEGER_TYPEs.
4385 (gimple_lower_bitint): Don't merge mergeable operations or other
4386 casts with VIEW_CONVERT_EXPRs to > MAX_FIXED_MODE_SIZE INTEGER_TYPEs.
4387 * expr.cc (expand_expr_real_1): Don't use convert_modes if either
4388 mode is BLKmode.
4390 2024-02-09 Jakub Jelinek <jakub@redhat.com>
4392 * hwint.h (GCC_PRISZ, fmt_size_t, HOST_SIZE_T_PRINT_DEC,
4393 HOST_SIZE_T_PRINT_UNSIGNED, HOST_SIZE_T_PRINT_HEX,
4394 HOST_SIZE_T_PRINT_HEX_PURE): Define.
4395 * ira-conflicts.cc (build_conflict_bit_table): Use it. Formatting
4396 fixes.
4398 2024-02-09 Jakub Jelinek <jakub@redhat.com>
4400 PR middle-end/113415
4401 * cfgexpand.cc (expand_asm_stmt): For asm goto, use
4402 duplicate_insn_chain to duplicate after_rtl_seq sequence instead
4403 of hand written loop with emit_insn of copy_insn and emit original
4404 after_rtl_seq on the last edge.
4406 2024-02-09 Jakub Jelinek <jakub@redhat.com>
4408 PR tree-optimization/113818
4409 * gimple-lower-bitint.cc (add_eh_edge): New function.
4410 (bitint_large_huge::handle_load,
4411 bitint_large_huge::lower_mergeable_stmt,
4412 bitint_large_huge::lower_muldiv_stmt): Use it.
4414 2024-02-09 Jakub Jelinek <jakub@redhat.com>
4416 PR tree-optimization/113774
4417 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't
4418 emit any comparison if m_first and low + 1 is equal to
4419 m_upwards_2limb, simplify condition for that. If not
4420 single_comparison, not m_first and we can prove that the idx <= low
4421 comparison will be always true, emit instead of idx <= low
4422 comparison low <= low such that cfg cleanup will optimize it at
4423 the end of the pass.
4425 2024-02-08 Aldy Hernandez <aldyh@redhat.com>
4427 PR tree-optimization/113735
4428 * value-relation.cc (equiv_oracle::add_equiv_to_block): Call
4429 limit_check().
4431 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
4433 * config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New.
4434 (main, print_mcu, diagnose_mrodata_in_ram): Pass it down.
4436 2024-02-08 H.J. Lu <hjl.tools@gmail.com>
4438 PR target/113711
4439 PR target/113733
4440 * config/i386/constraints.md: List all constraints with j prefix.
4441 (j>): Change auto-dec to auto-inc in documentation.
4442 (je): Changed to a memory constraint with APX NDD TLS operand
4443 check.
4444 (jM): New memory constraint for APX NDD instructions.
4445 (jO): Likewise.
4446 * config/i386/i386-protos.h (x86_poff_operand_p): Removed.
4447 * config/i386/i386.cc (x86_poff_operand_p): Likewise.
4448 * config/i386/i386.md (*add<dwi>3_doubleword): Use rjO.
4449 (*add<mode>_1[SWI48]): Use je and jM.
4450 (addsi_1_zext): Use jM.
4451 (*addv<dwi>4_doubleword_1[DWI]): Likewise.
4452 (*sub<mode>_1[SWI]): Use jM.
4453 (@add<mode>3_cc_overflow_1[SWI]): Likewise.
4454 (*add<dwi>3_doubleword_cc_overflow_1): Use rjO.
4455 (*and<dwi>3_doubleword): Likewise.
4456 (*anddi_1): Use jM.
4457 (*andsi_1_zext): Likewise.
4458 (*and<mode>_1[SWI24]): Likewise.
4459 (*<code><dwi>3_doubleword[any_or]): Use rjO
4460 (*code<mode>_1[any_or SWI248]): Use jM.
4461 (*<code>si_1_zext[zero_extend + any_or]): Likewise.
4462 * config/i386/predicates.md (apx_ndd_memory_operand): New.
4463 (apx_ndd_add_memory_operand): Likewise.
4465 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
4467 PR target/113824
4468 * config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4.
4469 * doc/avr-mmcu.texi: Rebuild.
4471 2024-02-08 Tamar Christina <tamar.christina@arm.com>
4473 PR tree-optimization/113808
4474 * tree-vect-loop.cc (vectorizable_live_operation): Don't cache the
4475 value cross iterations.
4477 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
4479 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always
4480 defines __AVR_PM_BASE_ADDRESS__ if the core has it.
4482 2024-02-08 Richard Biener <rguenther@suse.de>
4484 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
4485 Revert last change to dr_may_alias_p.
4487 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
4489 * config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to
4490 cc1_rodata_in_ram. Rename spec link_misc to link_rodata_in_ram.
4491 Remove spec asm_misc.
4492 * config/avr/specs.h: Same.
4494 2024-02-08 Pan Li <pan2.li@intel.com>
4496 PR target/113766
4497 * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
4498 sure the c.arg_num is >= 2 before checking.
4499 (struct build_frm_base): Ditto.
4500 (struct narrow_alu_def): Ditto.
4502 2024-02-07 Richard Biener <rguenther@suse.de>
4504 PR tree-optimization/113796
4505 * tree-if-conv.cc (combine_blocks): Wipe range-info before
4506 replacing PHIs and inserting predicates.
4508 2024-02-07 Roger Sayle <roger@nextmovesoftware.com>
4509 Uros Bizjak <ubizjak@gmail.com>
4511 PR target/113690
4512 * config/i386/i386-features.cc (timode_convert_cst): New helper
4513 function to convert a TImode CONST_SCALAR_INT_P to a V1TImode
4514 CONST_VECTOR.
4515 (timode_scalar_chain::convert_op): Use timode_convert_cst.
4516 (timode_scalar_chain::convert_insn): Delete REG_EQUAL notes.
4517 Use timode_convert_cst.
4519 2024-02-07 Victor Do Nascimento <victor.donascimento@arm.com>
4521 * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
4522 * config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
4523 (AARCH64_FL_DEBUGv8p9): Likewise.
4524 (AARCH64_FL_FGT2): Likewise.Likewise.
4525 (AARCH64_FL_ITE): Likewise.
4526 (AARCH64_FL_PFAR): Likewise.
4527 (AARCH64_FL_PMUv3_ICNTR): Likewise.
4528 (AARCH64_FL_PMUv3_SS): Likewise.
4529 (AARCH64_FL_PMUv3p9): Likewise.
4530 (AARCH64_FL_RASv2): Likewise.
4531 (AARCH64_FL_S1PIE): Likewise.
4532 (AARCH64_FL_S1POE): Likewise.
4533 (AARCH64_FL_S2PIE): Likewise.
4534 (AARCH64_FL_S2POE): Likewise.
4535 (AARCH64_FL_SCTLR2): Likewise.
4536 (AARCH64_FL_SEBEP): Likewise.
4537 (AARCH64_FL_SPE_FDS): Likewise.
4538 (AARCH64_FL_TCR2): Likewise.
4540 2024-02-07 Richard Biener <rguenther@suse.de>
4542 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
4543 Only check whether reads are in-bound in places that are not safe.
4544 Fix dependence check. Add missing newline. Clarify comments.
4546 2024-02-07 Tamar Christina <tamar.christina@arm.com>
4548 PR tree-optimization/113750
4549 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check
4550 for single predecessor when doing early break vect.
4551 * tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but
4552 after labels.
4554 2024-02-07 Tamar Christina <tamar.christina@arm.com>
4556 PR tree-optimization/113731
4557 * gimple-iterator.cc (gsi_move_before): Take new parameter for update
4558 method.
4559 * gimple-iterator.h (gsi_move_before): Default new param to
4560 GSI_SAME_STMT.
4561 * tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with
4562 GSI_NEW_STMT.
4564 2024-02-07 Jakub Jelinek <jakub@redhat.com>
4566 PR tree-optimization/113756
4567 * range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS,
4568 use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from
4569 of lh_bits value and mask.
4571 2024-02-07 Jakub Jelinek <jakub@redhat.com>
4573 PR tree-optimization/113753
4574 * wide-int.cc (wi::mul_internal): Unpack op1val and op2val with
4575 UNSIGNED rather than SIGNED. If high or needs_overflow and prec is
4576 not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec
4577 so that they start with r[half_blocks_needed] lowest bit. Fix up
4578 computation of top mask for SIGNED.
4580 2024-02-07 Pan Li <pan2.li@intel.com>
4582 PR target/113766
4583 * config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust
4584 the signature of func.
4585 * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto.
4586 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make
4587 overloaded func with empty args error.
4589 2024-02-06 H.J. Lu <hjl.tools@gmail.com>
4591 PR target/113689
4592 * config/i386/i386.cc (x86_64_select_profile_regnum): Return
4593 R10_REG after sorry.
4595 2024-02-06 Andrew Carlotti <andrew.carlotti@arm.com>
4597 * config/aarch64/aarch64.cc (aarch64_mangle_decl_assembler_name):
4598 Move before new caller, and add ".default" suffix.
4599 (get_suffixed_assembler_name): New.
4600 (make_resolver_func): Use get_suffixed_assembler_name.
4601 (aarch64_generate_version_dispatcher_body): Redo name mangling.
4603 2024-02-06 Jakub Jelinek <jakub@redhat.com>
4605 PR target/113763
4606 * config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Change tiles
4607 element from std::pair<unsigned int, char> to an unnamed struct.
4608 Adjust uses of tile range variable.
4610 2024-02-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4612 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation.
4613 (pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
4615 2024-02-06 Jakub Jelinek <jakub@redhat.com>
4617 PR sanitizer/110676
4618 * gimple-fold.cc (gimple_fold_builtin_strlen): For -fsanitize=address
4619 reset maxlen to sizetype maximum.
4621 2024-02-06 Jakub Jelinek <jakub@redhat.com>
4623 PR tree-optimization/113736
4624 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
4625 var's address space for MEM_REF or VIEW_CONVERT_EXPRs.
4627 2024-02-06 Jakub Jelinek <jakub@redhat.com>
4629 PR tree-optimization/113759
4630 * tree-ssa-math-opts.cc (convert_mult_to_widen): If actual_precision
4631 or from_unsignedN differs from properties of typeN, update typeN
4632 to build_nonstandard_integer_type. If TREE_TYPE (rhsN) is not
4633 uselessly convertible to typeN, convert it using fold_convert or
4634 build_and_insert_cast depending on if rhsN is INTEGER_CST or not.
4635 (convert_plusminus_to_widen): Likewise.
4637 2024-02-06 Tejas Belagod <tejas.belagod@arm.com>
4639 PR target/112577
4640 * config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
4641 vector structure modes correctly.
4643 2024-02-05 Christoph Müllner <christoph.muellner@vrull.eu>
4645 * config/riscv/thead.cc (th_print_operand_address): Fix compiler
4646 warning.
4648 2024-02-05 H.J. Lu <hjl.tools@gmail.com>
4650 PR target/113689
4651 * config/i386/i386.cc (x86_64_select_profile_regnum): New.
4652 (x86_function_profiler): Call x86_64_select_profile_regnum to
4653 get a scratch register for large model profiling.
4655 2024-02-05 Richard Ball <richard.ball@arm.com>
4657 * config/arm/arm.cc (arm_output_mi_thunk): Emit
4658 insn for bti_c when bti is enabled.
4660 2024-02-05 Xi Ruoyao <xry111@xry111.site>
4662 * config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
4663 neg.
4665 2024-02-05 Xi Ruoyao <xry111@xry111.site>
4667 * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
4668 (neg<mode>2): Change the mode iterator from MSA to IMSA because
4669 in FP arithmetic we cannot use (0 - x) for -x.
4670 (neg<mode>2): New define_insn to implement FP vector negation,
4671 using a bnegi instruction to negate the sign bit.
4673 2024-02-05 Richard Biener <rguenther@suse.de>
4675 PR tree-optimization/113707
4676 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After
4677 checking the avail set treat out-of-region defines as
4678 available.
4680 2024-02-05 Richard Biener <rguenther@suse.de>
4682 * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use
4683 the default mode when building a pointer.
4685 2024-02-05 Jakub Jelinek <jakub@redhat.com>
4687 PR tree-optimization/113737
4688 * gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH
4689 has just a single label, remove it and make single successor edge
4690 EDGE_FALLTHRU.
4692 2024-02-05 Jakub Jelinek <jakub@redhat.com>
4694 PR target/113059
4695 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
4696 Remove REG_DEAD/REG_UNUSED notes at the end of the pass before
4697 df_analyze call.
4699 2024-02-05 Richard Biener <rguenther@suse.de>
4701 PR target/113255
4702 * config/i386/i386-expand.cc
4703 (expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves):
4704 Use a new pseudo for the skipped number of bytes.
4706 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
4708 * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
4709 * doc/invoke.texi (RISC-V Options): Add sifive-p450,
4710 sifive-p670.
4712 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
4714 * config/riscv/riscv.md: Include sifive-p400.md.
4715 * config/riscv/sifive-p400.md: New file.
4716 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
4717 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
4718 Add sifive_p400.
4719 * config/riscv/riscv.cc (sifive_p400_tune_info): New.
4720 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
4721 * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
4723 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
4725 * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
4726 Add missing ":SI" to the match_operator.
4728 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
4730 * config/xtensa/xtensa.md (SHI): New mode iterator.
4731 (2 split patterns related to constsynth):
4732 Change to also accept HImode operands.
4734 2024-02-04 Jeff Law <jlaw@ventanamicro.com>
4736 * config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
4737 similarly.
4739 2024-02-04 Xi Ruoyao <xry111@xry111.site>
4741 * config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
4742 incorrect expand.
4743 * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
4744 (elmsgnbit): Likewise.
4745 (neg<mode:FVEC>2): New define_insn.
4746 * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
4747 are now instantiated in simd.md.
4749 2024-02-04 Xi Ruoyao <xry111@xry111.site>
4751 * config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
4752 use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
4753 MAX_MACHINE_MODE.
4755 2024-02-04 Li Wei <liwei@loongson.cn>
4757 * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
4758 (loongarch_expand_vselect_vconcat): Ditto.
4759 (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
4760 all 128-bit constant permutation situations.
4761 (loongarch_expand_lsx_shuffle): Adjust and rename function name.
4762 (loongarch_is_imm_set_shuffle): Renamed function name.
4763 (loongarch_expand_vec_perm_even_odd): Function forward declaration.
4764 (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
4765 extract-even and extract-odd permutations.
4766 (loongarch_is_odd_extraction): Delete.
4767 (loongarch_is_even_extraction): Ditto.
4768 (loongarch_expand_vec_perm_const): Adjust.
4770 2024-02-03 Jakub Jelinek <jakub@redhat.com>
4772 PR middle-end/113722
4773 * wide-int.cc (wi::bswap_large): Rename third argument from
4774 len to xlen and adjust use in safe_uhwi. Add len variable, set
4775 it to BLOCKS_NEEDED (precision) and use it for clearing of val
4776 and as canonize argument. Clear val using memset instead of
4777 a loop.
4779 2024-02-03 Jakub Jelinek <jakub@redhat.com>
4781 * ggc-common.cc (gt_pch_save): Allow addr to be equal to
4782 mmi.preferred_base + mmi.size - sizeof (void *).
4784 2024-02-03 Xi Ruoyao <xry111@xry111.site>
4786 * config/loongarch/loongarch-def.h (abi_minimal_isa): Declare.
4787 * config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove
4788 the ODR-violating locale declaration.
4790 2024-02-02 Tamar Christina <tamar.christina@arm.com>
4792 PR tree-optimization/113588
4793 PR tree-optimization/113467
4794 * tree-vect-data-refs.cc
4795 (vect_analyze_data_ref_dependence): Choose correct dest and fix checks.
4796 (vect_analyze_early_break_dependences): Update comments.
4798 2024-02-02 John David Anglin <danglin@gcc.gnu.org>
4800 PR target/59778
4801 * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
4802 and PA_BUILTIN_SET_FPSR builtins.
4803 * (pa_builtins_icode): Declare.
4804 * (def_builtin, pa_fpu_init_builtins): New.
4805 * (pa_init_builtins): Initialize FPU builtins.
4806 * (pa_builtin_decl, pa_expand_builtin_1): New.
4807 * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
4808 PA_BUILTIN_SET_FPSR builtins.
4809 * (pa_atomic_assign_expand_fenv): New.
4810 * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
4811 UNSPECV constants.
4812 (get_fpsr, put_fpsr): New expanders.
4813 (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
4814 insn patterns.
4816 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4818 PR target/113697
4819 * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.
4821 2024-02-02 Jonathan Wakely <jwakely@redhat.com>
4823 * doc/extend.texi (Common Type Attributes): Fix typo in
4824 description of hardbool.
4826 2024-02-02 Jakub Jelinek <jakub@redhat.com>
4828 PR tree-optimization/113692
4829 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
4830 from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
4831 final_cast_p.
4833 2024-02-02 Jakub Jelinek <jakub@redhat.com>
4835 PR middle-end/113699
4836 * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
4837 uninitialized large/huge _BitInt SSA_NAME inputs.
4839 2024-02-02 Jakub Jelinek <jakub@redhat.com>
4841 PR middle-end/113705
4842 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
4843 around wi::to_wide in order to compare value in prec precision.
4845 2024-02-02 Lehua Ding <lehua.ding@rivai.ai>
4847 Revert:
4848 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4850 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
4852 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4854 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
4856 2024-02-02 Pan Li <pan2.li@intel.com>
4858 * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
4859 (riscv_pass_by_reference): Ditto.
4860 (riscv_fntype_abi): Ditto.
4862 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4864 * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
4865 (pre_vsetvl::cleaup): Remove vsetvl_pre.
4866 (pre_vsetvl::remove_vsetvl_pre_insns): New function.
4868 2024-02-02 Jiahao Xu <xujiahao@loongson.cn>
4870 * config/loongarch/larchintrin.h
4871 (__frecipe_s): Update function return type.
4872 (__frecipe_d): Ditto.
4873 (__frsqrte_s): Ditto.
4874 (__frsqrte_d): Ditto.
4876 2024-02-02 Li Wei <liwei@loongson.cn>
4878 * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
4879 (loongarch_vector_costs::add_stmt_cost): Adjust.
4881 2024-02-02 Xi Ruoyao <xry111@xry111.site>
4883 * config/loongarch/loongarch.md (unspec): Add
4884 UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
4885 (la_pcrel64_two_parts): New define_insn.
4886 * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
4887 typo in the comment.
4888 (loongarch_call_tls_get_addr): If -mcmodel=extreme
4889 -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
4890 addressing the TLS symbol and __tls_get_addr. Emit an REG_EQUAL
4891 note to allow CSE addressing __tls_get_addr.
4892 (loongarch_legitimize_tls_address): If -mcmodel=extreme
4893 -mexplicit-relocs={always,auto}, address TLS IE symbols with
4894 la_pcrel64_two_parts.
4895 (loongarch_split_symbol): If -mcmodel=extreme
4896 -mexplicit-relocs={always,auto}, address symbols with
4897 la_pcrel64_two_parts.
4898 (loongarch_output_mi_thunk): Clean up unreachable code. If
4899 -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
4900 thunks with la_pcrel64_two_parts.
4902 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
4904 * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
4905 Add support for call36.
4907 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
4909 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
4910 When the code model of the symbol is extreme and -mexplicit-relocs=auto,
4911 the macro instruction loading symbol address is not applicable.
4912 (loongarch_call_tls_get_addr): Adjust code.
4913 (loongarch_legitimize_tls_address): Likewise.
4915 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
4917 * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
4918 Add function declaration.
4919 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
4920 For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
4921 is not allowed
4922 (loongarch_load_tls): Added macro support in extreme mode.
4923 (loongarch_call_tls_get_addr): Likewise.
4924 (loongarch_legitimize_tls_address): Likewise.
4925 (loongarch_force_address): Likewise.
4926 (loongarch_legitimize_move): Likewise.
4927 (loongarch_output_mi_thunk): Likewise.
4928 (loongarch_option_override_internal): Remove the code that detects
4929 explicit relocs status.
4930 (loongarch_handle_model_attribute): Likewise.
4931 * config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
4932 * config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
4933 (symbolic_off64_or_reg_operand): Likewise.
4935 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
4937 * config/loongarch/loongarch.cc (loongarch_load_tls):
4938 Load all types of tls symbols through one function.
4939 (loongarch_got_load_tls_gd): Delete.
4940 (loongarch_got_load_tls_ld): Delete.
4941 (loongarch_got_load_tls_ie): Delete.
4942 (loongarch_got_load_tls_le): Delete.
4943 (loongarch_call_tls_get_addr): Modify the called function name.
4944 (loongarch_legitimize_tls_address): Likewise.
4945 * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
4946 (@load_tls<mode>): New template.
4947 (@got_load_tls_ld<mode>): Delete.
4948 (@got_load_tls_le<mode>): Delete.
4949 (@got_load_tls_ie<mode>): Delete.
4951 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
4953 * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
4954 (loongarch_legitimize_address): Add logical transformation code.
4956 2024-02-01 Marek Polacek <polacek@redhat.com>
4958 * doc/invoke.texi: Update -Wdangling-reference documentation.
4960 2024-02-01 Uros Bizjak <ubizjak@gmail.com>
4962 PR target/113701
4963 * config/i386/i386.md (*cmp<dwi>_doubleword):
4964 Do not force SUBREG pieces to pseudos.
4966 2024-02-01 John David Anglin <danglin@gcc.gnu.org>
4968 * config/pa/pa.md (atomic_storedi_1): Fix bug in
4969 alternative 1.
4971 2024-02-01 Georg-Johann Lay <avr@gjlay.de>
4973 * config/avr/avr.cc: Tabify.
4975 2024-02-01 Richard Ball <richard.ball@arm.com>
4977 PR tree-optimization/111268
4978 * tree-vect-slp.cc (vectorizable_slp_permutation_1):
4979 Add variable-length check for vector input arguments
4980 to a function.
4982 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
4984 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
4985 hard-code number of SGPR/VGPR/AVGPR registers.
4986 * config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
4987 SGPR/VGPR/AVGPR registers.
4989 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
4991 * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
4992 attribute, and include sifive-p600.md.
4993 * config/riscv/generic-ooo.md: Update type attribute.
4994 * config/riscv/generic.md: Update type attribute.
4995 * config/riscv/sifive-7.md: Update type attribute.
4996 * config/riscv/sifive-p600.md: New file.
4997 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
4998 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
4999 Add sifive_p600.
5000 * config/riscv/riscv.cc (sifive_p600_tune_info): New.
5001 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
5002 * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
5004 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
5006 * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
5007 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
5008 * config/riscv/riscv.opt: New macro for 7 new unprivileged
5009 extensions.
5010 * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
5011 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
5013 2024-02-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
5015 * config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
5016 -static-libasan. Add missing whitespace.
5018 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
5020 * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
5021 (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
5022 Don't 'define_constants'.
5024 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
5026 * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.
5028 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
5030 * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
5031 [TARGET_RDNA3]: Adjust.
5033 2024-02-01 Richard Biener <rguenther@suse.de>
5035 PR tree-optimization/113693
5036 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
5037 data when available.
5039 2024-02-01 Jakub Jelinek <jakub@redhat.com>
5040 Jason Merrill <jason@redhat.com>
5042 PR c++/113531
5043 * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
5044 on variables which were promoted to TREE_STATIC.
5046 2024-02-01 Roger Sayle <roger@nextmovesoftware.com>
5047 Richard Biener <rguenther@suse.de>
5049 PR target/113560
5050 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
5051 information via tree_non_zero_bits to check if this operand
5052 is suitably extended for a widening (or highpart) multiplication.
5053 (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
5054 isn't already of the claimed type.
5056 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
5058 Revert:
5059 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
5061 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
5062 (generic_ooo_branch): ditto
5063 * config/riscv/generic.md (generic_sfb_alu): ditto
5064 (generic_fmul_half): ditto
5065 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
5066 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
5067 (sifive_7_popcount): ditto
5068 * config/riscv/vector.md: change rdfrm to fmove
5069 * config/riscv/zc.md: change pushpop to load/store
5071 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
5073 Revert:
5074 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
5075 Robin Dapp <rdapp.gcc@gmail.com>
5077 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
5078 (generic_ooo_vec_load): ditto
5079 (generic_ooo_vec_store): ditto
5080 (generic_ooo_vec_loadstore_seg): ditto
5081 (generic_ooo_vec_alu): ditto
5082 (generic_ooo_vec_fcmp): ditto
5083 (generic_ooo_vec_imul): ditto
5084 (generic_ooo_vec_fadd): ditto
5085 (generic_ooo_vec_fmul): ditto
5086 (generic_ooo_crypto): ditto
5087 (generic_ooo_perm): ditto
5088 (generic_ooo_vec_reduction): ditto
5089 (generic_ooo_vec_ordered_reduction): ditto
5090 (generic_ooo_vec_idiv): ditto
5091 (generic_ooo_vec_float_divsqrt): ditto
5092 (generic_ooo_vec_mask): ditto
5093 (generic_ooo_vec_vesetvl): ditto
5094 (generic_ooo_vec_setrm): ditto
5095 (generic_ooo_vec_readlen): ditto
5096 * config/riscv/riscv.md: include generic-vector-ooo
5097 * config/riscv/generic-vector-ooo.md: New file. to here
5099 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
5101 Revert:
5102 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
5104 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
5106 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
5108 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
5110 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
5111 Robin Dapp <rdapp.gcc@gmail.com>
5113 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
5114 (generic_ooo_vec_load): ditto
5115 (generic_ooo_vec_store): ditto
5116 (generic_ooo_vec_loadstore_seg): ditto
5117 (generic_ooo_vec_alu): ditto
5118 (generic_ooo_vec_fcmp): ditto
5119 (generic_ooo_vec_imul): ditto
5120 (generic_ooo_vec_fadd): ditto
5121 (generic_ooo_vec_fmul): ditto
5122 (generic_ooo_crypto): ditto
5123 (generic_ooo_perm): ditto
5124 (generic_ooo_vec_reduction): ditto
5125 (generic_ooo_vec_ordered_reduction): ditto
5126 (generic_ooo_vec_idiv): ditto
5127 (generic_ooo_vec_float_divsqrt): ditto
5128 (generic_ooo_vec_mask): ditto
5129 (generic_ooo_vec_vesetvl): ditto
5130 (generic_ooo_vec_setrm): ditto
5131 (generic_ooo_vec_readlen): ditto
5132 * config/riscv/riscv.md: include generic-vector-ooo
5133 * config/riscv/generic-vector-ooo.md: New file. to here
5135 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
5137 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
5138 (generic_ooo_branch): ditto
5139 * config/riscv/generic.md (generic_sfb_alu): ditto
5140 (generic_fmul_half): ditto
5141 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
5142 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
5143 (sifive_7_popcount): ditto
5144 * config/riscv/vector.md: change rdfrm to fmove
5145 * config/riscv/zc.md: change pushpop to load/store
5147 2024-02-01 Andrew Pinski <quic_apinski@quicinc.com>
5149 PR target/113657
5150 * config/aarch64/aarch64-simd.md (split for movv8di):
5151 For strict aligned mode, use DImode instead of TImode.
5153 2024-01-31 Robin Dapp <rdapp@ventanamicro.com>
5155 PR middle-end/113607
5156 * match.pd: Make sure else values match when folding a
5157 vec_cond into a conditional operation.
5159 2024-01-31 Marek Polacek <polacek@redhat.com>
5161 * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
5163 2024-01-31 Tamar Christina <tamar.christina@arm.com>
5164 Matthew Malcomson <matthew.malcomson@arm.com>
5166 PR sanitizer/112644
5167 * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
5168 memcmp.
5169 * builtins.cc (expand_builtin): Include HWASAN when checking for
5170 builtin inlining.
5172 2024-01-31 Richard Biener <rguenther@suse.de>
5174 PR middle-end/110176
5175 * match.pd (zext (bool) <= (int) 4294967295u): Make sure
5176 to match INTEGER_CST only without outstanding conversion.
5178 2024-01-31 Alex Coplan <alex.coplan@arm.com>
5180 PR target/111677
5181 * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
5182 V16QImode for the full 16-byte FPR saves in the vector PCS case.
5184 2024-01-31 Richard Biener <rguenther@suse.de>
5186 PR tree-optimization/111444
5187 * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
5188 vn_reference_lookup_2 when optimistically skipping may-defs.
5190 2024-01-31 Richard Biener <rguenther@suse.de>
5192 PR tree-optimization/113630
5193 * tree-ssa-pre.cc (compute_avail): Avoid registering a
5194 reference with a representation with not matching base
5195 access size.
5197 2024-01-31 Jakub Jelinek <jakub@redhat.com>
5199 PR rtl-optimization/113656
5200 * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
5201 <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.
5203 2024-01-31 Jakub Jelinek <jakub@redhat.com>
5205 PR debug/113637
5206 * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
5207 with BLKmode are larger than DWARF2_ADDR_SIZE.
5209 2024-01-31 Jakub Jelinek <jakub@redhat.com>
5211 PR tree-optimization/113639
5212 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
5213 For VIEW_CONVERT_EXPR set rhs1 to its operand.
5215 2024-01-31 Richard Biener <rguenther@suse.de>
5217 PR tree-optimization/113670
5218 * tree-vect-data-refs.cc (vect_check_gather_scatter):
5219 Make sure we can take the address of the reference base.
5221 2024-01-31 Georg-Johann Lay <avr@gjlay.de>
5223 * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
5224 ATA5835, ATtiny64AUTO, ATA5700M322.
5225 * doc/avr-mmcu.texi: Rebuild.
5227 2024-01-31 Alexandre Oliva <oliva@adacore.com>
5229 PR debug/113394
5230 * ipa-strub.cc (build_ref_type_for): Drop nonaliased. Adjust
5231 caller.
5233 2024-01-31 Alexandre Oliva <oliva@adacore.com>
5235 PR middle-end/112917
5236 PR middle-end/113100
5237 * builtins.cc (expand_builtin_stack_address): Use
5238 STACK_ADDRESS_OFFSET.
5239 * doc/extend.texi (__builtin_stack_address): Adjust.
5240 * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
5241 * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
5242 * doc/tm.texi: Rebuilt.
5244 2024-01-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5246 PR target/113495
5247 * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
5248 (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
5249 (pre_vsetvl::compute_transparent): New function.
5250 (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
5252 2024-01-30 Fangrui Song <maskray@google.com>
5254 PR target/105576
5255 * config/i386/constraints.md: Define constraint "Ws".
5256 * doc/md.texi: Document it.
5258 2024-01-30 Marek Polacek <polacek@redhat.com>
5260 PR c++/110358
5261 PR c++/109640
5262 * doc/invoke.texi: Update -Wdangling-reference description.
5264 2024-01-30 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
5266 * config/xtensa/constraints.md (R, T, U):
5267 Change define_constraint to define_memory_constraint.
5268 * config/xtensa/predicates.md (move_operand): Don't check that a
5269 constant pool operand size is a multiple of UNITS_PER_WORD.
5270 * config/xtensa/xtensa.cc
5271 (xtensa_lra_p, TARGET_LRA_P): Remove.
5272 (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
5273 clause as it can no longer be true.
5274 (fixup_subreg_mem): Drop function.
5275 (xtensa_output_integer_literal_parts): Consider 16-bit wide
5276 constants.
5277 (xtensa_legitimate_constant_p): Add short-circuit path for
5278 integer load instructions. Don't check that mode size is
5279 at least UNITS_PER_WORD.
5280 * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
5281 rather reload_in_progress and reload_completed.
5282 (doloop_end): Drop operand 2.
5283 (movhi_internal): Add alternative loading constant from a
5284 literal pool.
5285 (define_split for DI register_operand): Don't limit to
5286 !TARGET_AUTO_LITPOOLS.
5287 * config/xtensa/xtensa.opt (mlra): Change to no effect.
5289 2024-01-30 Pan Li <pan2.li@intel.com>
5291 * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
5292 calculate the gpr count required by vls mode.
5293 (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
5294 (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
5295 for vls mode.
5296 (riscv_get_arg_info): Add vls mode handling.
5297 (riscv_pass_by_reference): Return false if arg info has no zero gpr count.
5299 2024-01-30 Richard Biener <rguenther@suse.de>
5301 PR tree-optimization/113659
5302 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5303 Handle main exit without virtual use.
5305 2024-01-30 Christoph Müllner <christoph.muellner@vrull.eu>
5307 * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
5309 2024-01-30 Iain Sandoe <iain@sandoe.co.uk>
5311 PR libgcc/113403
5312 * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
5313 (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
5314 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
5315 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
5316 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
5317 * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.
5319 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
5321 PR target/113623
5322 * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
5323 Mark all registers that occur in addresses as needing a GPR.
5325 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
5327 PR target/113636
5328 * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
5329 the containing insn as an extra parameter. Reset debug instructions
5330 if they reference a register that is no longer used by real insns.
5331 (early_ra::apply_allocation): Update calls accordingly.
5333 2024-01-30 Jakub Jelinek <jakub@redhat.com>
5335 PR tree-optimization/113603
5336 * tree-ssa-strlen.cc (strlen_pass::handle_store): After
5337 count_nonzero_bytes call refetch si using get_strinfo in case it
5338 has been unshared in the meantime.
5340 2024-01-30 Jakub Jelinek <jakub@redhat.com>
5342 PR middle-end/101195
5343 * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
5344 fit into unsigned HOST_WIDE_INT, return constm1_rtx.
5346 2024-01-30 Jin Ma <jinma@linux.alibaba.com>
5348 * config/riscv/thead.cc (th_print_operand_address): Change %ld
5349 to %lld.
5351 2024-01-29 Manos Anagnostakis <manos.anagnostakis@vrull.eu>
5352 Manolis Tsamis <manolis.tsamis@vrull.eu>
5353 Philipp Tomsich <philipp.tomsich@vrull.eu>
5355 * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
5356 * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
5357 Likewise.
5358 * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
5359 Call on framework moved later.
5361 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com>
5363 * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
5364 instruction in naked function epilogues.
5366 2024-01-29 YunQiang Su <syq@gcc.gnu.org>
5368 PR target/113655
5369 * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
5370 gcc_cv_as_mips_explicit_relocs.
5371 * configure: Regnerated.
5373 2024-01-29 Matthieu Longo <matthieu.longo@arm.com>
5375 PR target/108933
5376 * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
5377 Correct generated RTL.
5378 (arm_rev16si2_alt1): Correctly handle conditional execution.
5379 (arm_rev16si2_alt2): Likewise.
5381 2024-01-29 Richard Biener <rguenther@suse.de>
5383 PR middle-end/113622
5384 * expr.cc (expand_assignment): Spill hard registers if
5385 we index them with a variable offset.
5387 2024-01-29 Richard Biener <rguenther@suse.de>
5389 PR middle-end/113622
5390 * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
5391 Also allow DECL_HARD_REGISTER variables.
5393 2024-01-29 Alex Coplan <alex.coplan@arm.com>
5395 PR target/113616
5396 * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
5397 Use iterate_safely when iterating over debug uses.
5398 (fixup_debug_uses): Likewise.
5399 (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
5400 over nondebug insns instead of manually maintaining the next insn.
5401 * iterator-utils.h (class safe_iterator): New.
5402 (iterate_safely): New.
5404 2024-01-29 H.J. Lu <hjl.tools@gmail.com>
5406 PR target/38534
5407 * config/i386/i386-options.cc (ix86_set_func_type): Save
5408 callee-saved registers in noreturn functions for -O0/-Og.
5410 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
5412 PR target/113615
5413 * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
5414 define for !TARGET_RDNA2_PLUS.
5416 2024-01-29 Richard Sandiford <richard.sandiford@arm.com>
5418 PR target/113281
5419 * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
5420 workaround for right shifts.
5421 (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
5422 (vect_determine_precisions_from_range): Be more selective about
5423 which codes can be narrowed based on their input and output ranges.
5424 For shifts, require at least one more bit of precision than the
5425 maximum shift amount.
5427 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
5429 * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.
5431 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
5433 * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
5434 but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
5435 LLVM 13.0.1+.
5437 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
5439 PR other/111966
5440 * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
5441 (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
5442 (SET_SRAM_ECC_UNSET): ... this.
5443 (copy_early_debug_info): Remove gfx900 special case, now handled as
5444 part of the generic handling.
5445 (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.
5447 2024-01-29 Jakub Jelinek <jakub@redhat.com>
5449 PR tree-optimization/110603
5450 * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
5451 setting of pdata->maxlen to vr.upper_bound (which is unconditionally
5452 overwritten anyway). Avoid creating invalid range with minlen
5453 larger than maxlen. Formatting fix.
5455 2024-01-29 Richard Biener <rguenther@suse.de>
5457 PR debug/103047
5458 * tree-inline.cc (initialize_inlined_parameters): Reverse
5459 the decl chain of inlined parameters.
5461 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
5463 * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
5464 alignment of CFString constants by setting DECL_USER_ALIGN.
5466 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
5467 Jakub Jelinek <jakub@redhat.com>
5469 PR libgcc/113402
5470 * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
5471 and BUILT_IN_GCC_NESTED_PTR_DELETED.
5472 * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
5473 BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
5474 rename the library fallbacks to __gcc_nested_func_ptr_created and
5475 __gcc_nested_func_ptr_deleted.
5476 * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
5477 and __gcc_nested_func_ptr_deleted.
5478 * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
5479 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
5480 * tree.cc (build_common_builtin_nodes): Build the
5481 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
5482 builtins only for non-explicit.
5484 2024-01-28 YunQiang Su <syq@gcc.gnu.org>
5486 * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
5488 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
5490 PR target/38534
5491 * config/i386/i386-options.cc (ix86_set_func_type): Don't
5492 save and restore callee saved registers for a noreturn function
5493 with nothrow or compiled with -fno-exceptions.
5495 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
5497 PR target/103503
5498 PR target/113312
5499 * config/i386/i386-expand.cc (ix86_expand_call): Replace
5500 no_caller_saved_registers check with call_saved_registers check.
5501 Clobber all registers that are not used by the callee with
5502 no_callee_saved_registers attribute.
5503 * config/i386/i386-options.cc (ix86_set_func_type): Set
5504 call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
5505 noreturn function. Disallow no_callee_saved_registers with
5506 interrupt or no_caller_saved_registers attributes together.
5507 (ix86_set_current_function): Replace no_caller_saved_registers
5508 check with call_saved_registers check.
5509 (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
5510 (ix86_handle_call_saved_registers_attribute): This.
5511 (ix86_gnu_attributes): Add
5512 ix86_handle_call_saved_registers_attribute.
5513 * config/i386/i386.cc (ix86_conditional_register_usage): Replace
5514 no_caller_saved_registers check with call_saved_registers check.
5515 (ix86_function_ok_for_sibcall): Don't allow callee with
5516 no_callee_saved_registers attribute when the calling function
5517 has callee-saved registers.
5518 (ix86_comp_type_attributes): Also check
5519 no_callee_saved_registers.
5520 (ix86_epilogue_uses): Replace no_caller_saved_registers check
5521 with call_saved_registers check.
5522 (ix86_hard_regno_scratch_ok): Likewise.
5523 (ix86_save_reg): Replace no_caller_saved_registers check with
5524 call_saved_registers check. Don't save any registers for
5525 TYPE_NO_CALLEE_SAVED_REGISTERS. Save all registers with
5526 TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
5527 no_callee_saved_registers attribute is called.
5528 (find_drap_reg): Replace no_caller_saved_registers check with
5529 call_saved_registers check.
5530 * config/i386/i386.h (call_saved_registers_type): New enum.
5531 (machine_function): Replace no_caller_saved_registers with
5532 call_saved_registers.
5533 * doc/extend.texi: Document no_callee_saved_registers attribute.
5535 2024-01-27 Jakub Jelinek <jakub@redhat.com>
5537 PR tree-optimization/113614
5538 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
5539 widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
5540 TRUNC_MOD_EXPR or FLOAT_EXPR uses.
5542 2024-01-27 Jakub Jelinek <jakub@redhat.com>
5544 PR tree-optimization/113568
5545 * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
5546 For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
5547 in the widening extension checks.
5549 2024-01-27 Jakub Jelinek <jakub@redhat.com>
5551 * gimple-lower-bitint.cc (gimple_lower_bitint): For
5552 TDF_DETAILS dump mapping of SSA_NAMEs to decls.
5554 2024-01-26 Hans-Peter Nilsson <hp@axis.com>
5556 * cgraphunit.cc (process_function_and_variable_attributes): Tweak
5557 the warning for an attribute-always_inline without inline declaration.
5559 2024-01-26 Robin Dapp <rdapp@ventanamicro.com>
5561 PR other/113575
5562 * genopinit.cc (main): Split init_all_optabs into functions
5563 of 1000 patterns each.
5565 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
5567 * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
5568 TM_MULTILIB_CONFIG.
5569 * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
5570 * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
5571 -march/-mtune.
5573 2024-01-26 Andrew Stubbs <ams@baylibre.com>
5575 * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
5576 * config/gcn/gcn-valu.md (all_convert): New iterator.
5577 (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
5578 define_expand, and rename the old one to ...
5579 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
5580 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
5581 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
5582 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
5583 * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
5584 (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
5585 * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
5586 (<u>mulqihi3_scalar): Likewise.
5588 2024-01-26 Richard Biener <rguenther@suse.de>
5590 PR tree-optimization/113602
5591 * tree-data-ref.cc (dr_analyze_innermost): Fail when
5592 the base object isn't addressable.
5594 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
5596 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
5597 "--amdhsa-code-object-version=" argument.
5598 (ASM_SPEC): Use it; replace previous version of it.
5600 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5602 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
5603 (pre_vsetvl::emit_vsetvl): Ditto.
5605 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
5607 * config/loongarch/lasx.md (vec_extract<mode>_0):
5608 New define_insn_and_split patten.
5610 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
5612 * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
5614 2024-01-26 Li Wei <liwei@loongson.cn>
5616 * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.
5618 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5620 PR target/113469
5621 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.
5623 2024-01-26 Andrew Pinski <quic_apinski@quicinc.com>
5625 PR target/100212
5626 * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
5627 undefined shift after the call to exact_log2.
5629 2024-01-25 Andrew Pinski <quic_apinski@quicinc.com>
5631 PR target/100204
5632 * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
5633 before taking the negative of it.
5635 2024-01-25 Vladimir N. Makarov <vmakarov@redhat.com>
5637 PR target/113526
5638 * lra-constraints.cc (curr_insn_transform): Change class even for
5639 spilled pseudo successfully matched with with NO_REGS.
5641 2024-01-25 Georg-Johann Lay <avr@gjlay.de>
5643 PR target/113601
5644 * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.
5646 2024-01-25 Szabolcs Nagy <szabolcs.nagy@arm.com>
5648 PR target/112987
5649 * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
5650 (aarch64_expand_epilogue): Use the new function.
5651 (aarch64_split_compare_and_swap): Likewise.
5652 (aarch64_split_atomic_op): Likewise.
5654 2024-01-25 Robin Dapp <rdapp.gcc@gmail.com>
5656 PR middle-end/112971
5657 * fold-const.cc (simplify_const_binop): New function for binop
5658 simplification of two constant vectors when element-wise
5659 handling is not necessary.
5660 (const_binop): Call new function.
5662 2024-01-25 Mary Bennett <mary.bennett@embecosm.com>
5664 * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
5665 * config/riscv/constraints.md: Likewise.
5666 * config/riscv/corev.def: Likewise.
5667 * config/riscv/corev.md: Likewise.
5668 * config/riscv/predicates.md: Likewise.
5669 * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
5670 * config/riscv/riscv-ftypes.def: Likewise.
5671 * config/riscv/riscv.opt: Likewise.
5672 * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
5673 * doc/extend.texi: Add XCVbitmanip builtin documentation.
5674 * doc/sourcebuild.texi: Likewise.
5676 2024-01-25 Tobias Burnus <tburnus@baylibre.com>
5678 * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.
5680 2024-01-25 Yanzhang Wang <yanzhang.wang@intel.com>
5682 PR target/113538
5683 * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
5684 (riscv_fntype_abi): Ditto.
5685 * config/riscv/riscv.opt: Ditto.
5687 2024-01-25 Jakub Jelinek <jakub@redhat.com>
5689 PR middle-end/113574
5690 * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
5691 count against TYPE_PRECISION rather than TYPE_SIZE.
5693 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
5695 PR target/113572
5696 * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
5697 Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT
5699 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
5701 PR target/113550
5702 * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
5703 whether each split instruction is a load that clobbers the source
5704 address. Emit that instruction last if so.
5706 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
5708 PR target/113485
5709 * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
5710 pattern.
5711 (<optab><Vnarrowq><mode>2): Use it instead of generating a
5712 paradoxical subreg for the input.
5714 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5716 * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
5717 (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
5718 predecessors dump information.
5720 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5722 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
5723 redundant full available computation.
5724 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
5726 2024-01-25 Jakub Jelinek <jakub@redhat.com>
5728 * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
5729 * doc/rtl.texi (CONST_VECTOR): Likewise.
5731 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5733 * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
5734 * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
5735 (pass_vsetvl::execute): Ditto.
5736 * config/riscv/riscv.opt: Ditto.
5738 2024-01-25 Jiahao Xu <xujiahao@loongson.cn>
5740 * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
5741 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
5743 2024-01-25 Richard Biener <rguenther@suse.de>
5745 PR tree-optimization/113576
5746 * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
5747 exits with may_be_zero niters when its the last one.
5749 2024-01-25 Lulu Cheng <chenglulu@loongson.cn>
5751 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
5752 For symbols of type tls, non-zero Offset is not generated.
5754 2024-01-25 Haochen Gui <guihaoc@gcc.gnu.org>
5756 * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
5757 P9 with m32 and mpowerpc64.
5759 2024-01-25 liuhongt <hongtao.liu@intel.com>
5761 * config/i386/i386-options.cc (ix86_option_override_internal):
5762 Enable -mlam=u57 by default when compiled with
5763 -fsanitize=hwaddress.
5765 2024-01-25 Palmer Dabbelt <palmer@rivosinc.com>
5767 * common/config/riscv/riscv-common.cc (riscv_implied_info):
5768 Remove {"ztso", "a"}.
5770 2024-01-24 Martin Jambor <mjambor@suse.cz>
5772 PR ipa/108007
5773 PR ipa/112616
5774 * cgraph.h (cgraph_edge): Add a parameter to
5775 redirect_call_stmt_to_callee.
5776 * ipa-param-manipulation.h (ipa_param_adjustments): Add a
5777 parameter to modify_call.
5778 (ipa_release_ssas_in_hash): Declare.
5779 * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
5780 parameter killed_ssas, pass it to padjs->modify_call.
5781 * ipa-param-manipulation.cc (purge_all_uses): New function.
5782 (ipa_param_adjustments::modify_call): New parameter killed_ssas.
5783 Instead of substituting uses, invoke purge_all_uses. If
5784 hash of killed SSAs has not been provided, create a temporary one
5785 and release SSAs that have been added to it.
5786 (compare_ssa_versions): New function.
5787 (ipa_release_ssas_in_hash): Likewise.
5788 * tree-inline.cc (redirect_all_calls): Create
5789 id->killed_new_ssa_names earlier, pass it to edge redirection,
5790 adjust a comment.
5791 (copy_body): Release SSAs in id->killed_new_ssa_names.
5793 2024-01-24 Andrew Pinski <quic_apinski@quicinc.com>
5795 PR target/113486
5796 * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
5797 TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
5799 2024-01-24 Monk Chiang <monk.chiang@sifive.com>
5801 PR target/113095
5802 * config/riscv/sfb.md: New splitters to rewrite single bit
5803 sign extension as the condition to SFB instructions.
5805 2024-01-24 Jan Hubicka <jh@suse.cz>
5807 PR middle-end/88345
5808 * common.opt: (flimit-function-alignment): Reorder alphabeticaly
5809 (fmin-function-alignment): New parameter.
5810 * doc/invoke.texi: (-fmin-function-alignment): Document.
5811 (-falign-functions,-falign-loops,-falign-labels): Mention that
5812 aglinments are ignored in cold code.
5813 * varasm.cc (assemble_start_function): Handle min-function-alignment.
5815 2024-01-24 Tamar Christina <tamar.christina@arm.com>
5817 PR target/109636
5818 * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
5819 mulv2di3): Remove.
5820 * config/aarch64/iterators.md (VQDIV): Remove.
5821 (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
5822 SVE_I_SIMD_DI): New.
5823 (VPRED, sve_lane_con): Add V4SI and V2DI.
5824 * config/aarch64/aarch64-sve.md (<optab><mode>3,
5825 @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
5826 (mul<mode>3): New, split from <optab><mode>3.
5827 (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
5828 * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
5829 *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
5830 SVE_FULL_HSDI_SIMD_DI.
5832 2024-01-24 Tamar Christina <tamar.christina@arm.com>
5834 PR tree-optimization/113552
5835 * config/aarch64/aarch64.cc
5836 (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
5838 2024-01-24 Martin Jambor <mjambor@suse.cz>
5840 PR ipa/113490
5841 * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
5842 count is equal or greater than the limit. Use the limit from the
5843 callee.
5845 2024-01-24 YunQiang Su <syq@gcc.gnu.org>
5847 * configure.ac: Detect the explicit relocs support for
5848 mips, and define C macro MIPS_EXPLICIT_RELOCS.
5849 * config.in: Regenerated.
5850 * configure: Regenerated.
5851 * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
5852 * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
5853 * config/mips/mips.cc(mips_set_compression_mode): Sorry if
5854 !TARGET_EXPLICIT_RELOCS instead of just set it.
5855 * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
5856 TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
5857 * config/mips/mips.opt: Introduce -mexplicit-relocs= option
5858 and define -m(no-)explicit-relocs as aliases.
5860 2024-01-24 Alex Coplan <alex.coplan@arm.com>
5862 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
5863 to 1.
5864 (-mlate-ldp-fusion): Likewise.
5866 2024-01-24 Tamar Christina <tamar.christina@arm.com>
5868 * tree-vect-loop.cc (vect_get_vect_def,
5869 vect_create_epilog_for_reduction): Rename main_exit_p to
5870 last_val_reduc_p.
5872 2024-01-24 Tamar Christina <tamar.christina@arm.com>
5874 PR tree-optimization/113364
5875 * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
5876 early exits then we must reduce from the first offset for all of them.
5878 2024-01-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5880 PR target/113495
5881 * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
5882 (get_regno): Ditto.
5883 (get_bb_index): Ditto.
5884 (pre_vsetvl::compute_avl_def_data): Ditto.
5885 (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
5886 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
5888 2024-01-23 Andrew Pinski <quic_apinski@quicinc.com>
5889 Richard Sandiford <richard.sandiford@arm.com>
5891 PR target/100942
5892 * ccmp.cc (ccmp_candidate_p): Add outer argument.
5893 Allow if the outer is true and the lhs is used more
5894 than once.
5895 (expand_ccmp_expr): Update call to ccmp_candidate_p.
5896 * expr.h (expand_expr_real_gassign): Declare.
5897 * expr.cc (expand_expr_real_gassign): New function, split out from...
5898 (expand_expr_real_1): ...here.
5899 * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
5901 2024-01-23 Alex Coplan <alex.coplan@arm.com>
5903 PR target/113089
5904 * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
5905 (fixup_debug_use): New.
5906 (fixup_debug_uses_trailing_add): New.
5907 (fixup_debug_uses): New. Use it ...
5908 (ldp_bb_info::fuse_pair): ... here.
5909 (try_promote_writeback): Call fixup_debug_uses_trailing_add to
5910 fix up debug uses of the base register that are affected by
5911 folding in the trailing add insn.
5913 2024-01-23 Alex Coplan <alex.coplan@arm.com>
5915 PR target/113089
5916 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
5917 Update trailing nondebug uses of the base register in the case
5918 of cancelling writeback.
5920 2024-01-23 Alex Coplan <alex.coplan@arm.com>
5922 PR target/113089
5923 * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
5924 (debug_insn_use_iterator): New.
5925 (set_info::first_debug_insn_use): New.
5926 (set_info::debug_insn_uses): New.
5927 * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
5928 (set_info::first_debug_insn_use): New.
5929 (set_info::debug_insn_uses): New.
5931 2024-01-23 Alex Coplan <alex.coplan@arm.com>
5933 PR target/113356
5934 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
5935 Don't record hazards against the opposite insn in the pair.
5937 2024-01-23 Alex Coplan <alex.coplan@arm.com>
5939 PR target/113070
5940 * config/aarch64/aarch64-ldp-fusion.cc
5941 (struct stp_change_builder): New.
5942 (decide_stp_strategy): Reanme to ...
5943 (try_repurpose_store): ... this.
5944 (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
5945 construct stp changes. Fix up uses when inserting new stp insns.
5947 2024-01-23 Alex Coplan <alex.coplan@arm.com>
5949 PR target/113070
5950 * rtl-ssa.h: Include hash-set.h.
5951 * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
5952 new_sets parameter and use it to keep track of new user-created sets.
5953 (function_info::apply_changes_to_insn): Also call add_def on new sets.
5954 (function_info::change_insns): Add hash_set to keep track of new
5955 user-created defs. Plumb it through.
5956 * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
5957 apply_changes_to_insn.
5959 2024-01-23 Alex Coplan <alex.coplan@arm.com>
5961 PR target/113070
5962 * rtl-ssa/accesses.cc (function_info::create_use): New.
5963 * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
5964 Ensure new uses end up referring to permanent defs.
5965 * rtl-ssa/functions.h (function_info::create_use): Declare.
5967 2024-01-23 Alex Coplan <alex.coplan@arm.com>
5969 PR target/113070
5970 * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
5971 to finalize_new_accesses from the backwards placement loop, run it
5972 forwards in a separate loop.
5974 2024-01-23 Richard Biener <rguenther@suse.de>
5976 PR tree-optimization/113552
5977 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
5978 floor_log2 instead of exact_log2 on the number of calls.
5980 2024-01-23 Jeff Law <jlaw@ventanamicro.com>
5981 Jakub Jelinek <jakub@redhat.com>
5983 * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
5984 decl.
5986 2024-01-23 Richard Biener <rguenther@suse.de>
5988 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5989 Separate single and multi-exit case when creating PHIs between
5990 the main and epilogue.
5992 2024-01-23 Richard Sandiford <richard.sandiford@arm.com>
5994 PR target/112989
5995 * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
5996 MODE_single variants of functions that don't take tuple arguments.
5998 2024-01-23 Alex Coplan <alex.coplan@arm.com>
6000 PR target/113114
6001 * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
6002 Don't assert recog success, just punt if the writeback pair
6003 isn't recognized.
6005 2024-01-23 Jakub Jelinek <jakub@redhat.com>
6007 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
6008 ATTRIBUTE_UNUSED to decl.
6010 2024-01-23 Richard Biener <rguenther@suse.de>
6012 PR debug/107058
6013 * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
6014 handle unexpected but bogus DIE contexts when not checking
6015 enabled.
6017 2024-01-23 Jakub Jelinek <jakub@redhat.com>
6019 PR tree-optimization/113462
6020 * fold-const.cc (native_interpret_int): Don't punt if total_bytes
6021 is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
6022 (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
6023 sizes between 129 and 8192 bytes.
6025 2024-01-23 Xi Ruoyao <xry111@xry111.site>
6027 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
6028 If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
6029 for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
6030 (loongarch_call_tls_get_addr): Do not split symbols of
6031 SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
6032 EXPLICIT_RELOCS_AUTO.
6034 2024-01-23 Richard Biener <rguenther@suse.de>
6036 * alias.cc (known_base_value_p): Remove.
6037 (find_base_value): Remove PLUS/MINUS handling
6038 when both operands are not CONST_INT_P.
6040 2024-01-23 Richard Biener <rguenther@suse.de>
6042 PR rtl-optimization/113255
6043 * alias.cc (find_base_term): Remove PLUS/MINUS handling
6044 when both operands are not CONST_INT_P.
6046 2024-01-23 Richard Biener <rguenther@suse.de>
6048 PR debug/112718
6049 * dwarf2out.cc (dwarf2out_finish): Reset all type units
6050 for the fat part of an LTO compile.
6052 2024-01-23 chenxiaolong <chenxiaolong@loongson.cn>
6054 * doc/sourcebuild.texi: Add attributes for keywords.
6056 2024-01-23 Sandra Loosemore <sandra@codesourcery.com>
6058 PR c++/90463
6059 * doc/invoke.texi (Warning Options): Correct lists of options
6060 enabled by -Wall and -Wextra by checking against common.opt
6061 and c-family/c.opt.
6063 2024-01-22 Andrew Pinski <quic_apinski@quicinc.com>
6065 PR target/113030
6066 * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
6067 instead of cpu_optaliases.
6068 (check_arch): Use arch_opt_alias instead of arch_optaliases.
6070 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6072 * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
6073 * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
6074 * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
6076 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6078 PR target/109092
6079 * config/riscv/riscv.md: Use reg instead of subreg.
6081 2024-01-22 Tobias Burnus <tburnus@baylibre.com>
6083 PR other/111966
6084 * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
6085 to match the compiler default.
6086 (simple_object_copy_lto_debug_sections): Never unlink the outfile
6087 on error as the caller does so.
6088 (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
6089 (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
6091 2024-01-22 Richard Biener <rguenther@suse.de>
6093 PR tree-optimization/113373
6094 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
6095 Create LC PHIs in the exit blocks where necessary.
6096 * tree-vect-loop.cc (vectorizable_live_operation): Do not try
6097 to handle missing LC PHIs.
6098 (find_connected_edge): Remove.
6099 (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
6101 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6103 * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
6105 2024-01-22 xuli <xuli1@eswincomputing.com>
6107 PR target/113420
6108 * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
6109 (registered_function::overloaded_hash):refactor.
6110 (resolve_overloaded_builtin):avoid internal ICE.
6112 2024-01-21 Mikael Pettersson <mikpelinux@gmail.com>
6114 PR target/82420
6115 PR target/111279
6116 * calls.cc (emit_library_call_value_1): Pass valid TYPE
6117 to emit_push_insn.
6118 * expr.cc (emit_push_insn): Likewise.
6120 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
6122 * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
6123 correcction version of last change.
6125 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
6127 * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
6128 fix bugs in signature.
6130 2024-01-21 Roger Sayle <roger@nextmovesoftware.com>
6131 Richard Biener <rguenther@suse.de>
6133 PR rtl-optimization/111267
6134 * fwprop.cc (fwprop_propagation::profitabe_p): Rename
6135 profitable_p method to likely_profitable_p.
6136 (try_fwprop_subst_node): Update call to likely_profitable_p.
6137 Only bail-out early when !prop.likely_profitable_p for instructions
6138 that are not single sets. When comparing costs, bail-out if the
6139 cost is unchanged and !prop.likely_profitable_p.
6141 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
6143 PR c++/90464
6144 * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
6145 isn't enabled by -Wunused unless -Wextra is provided, and that
6146 -Wunused does enable -Wunused-const-variable=1 for C. Clarify that
6147 -Wunused doesn't enable -Wunused-* options documented as behaving
6148 otherwise, and list them explicitly.
6150 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
6152 PR c/109708
6153 * doc/invoke.texi (Warning Options): Fix broken example and
6154 clean up/reorganize the others. Also describe what the short-form
6155 options mean.
6157 2024-01-20 Sandra Loosemore <sandra@codesourcery.com>
6159 PR c/102998
6160 * doc/invoke.texi (Option Summary): Add -Warray-parameter.
6161 (Warning Options): Correct/edit discussion of -Warray-parameter
6162 to make the first example less confusing, and fill in missing info.
6164 2024-01-20 Jakub Jelinek <jakub@redhat.com>
6166 PR tree-optimization/113462
6167 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
6168 Handle rhs1 INTEGER_CST like SSA_NAME.
6170 2024-01-20 Jakub Jelinek <jakub@redhat.com>
6172 PR tree-optimization/113491
6173 * tree-switch-conversion.cc (switch_conversion::build_constructors):
6174 If elt.index has precision higher than sizetype, fold_convert it to
6175 sizetype.
6176 (switch_conversion::array_value_type): Return type if type is
6177 BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
6178 (switch_conversion::build_arrays): Use unsigned_type_for rather than
6179 lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
6180 above MAX_FIXED_MODE_SIZE or with BLKmode. If utype has precision
6181 higher than sizetype, use sizetype as tidx type and fold_convert the
6182 subtraction to sizetype.
6184 2024-01-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6186 * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
6187 (riscv_vector_mode_supported_any_target_p): Ditto.
6189 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
6191 PR target/110934
6192 * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
6193 (TARGET_ZERO_CALL_USED_REGS): Define.
6195 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
6197 PR target/108640
6198 * config/m68k/m68k.cc (output_andsi3): Use QImode for
6199 address adjusted for 1-byte RMW access.
6200 (output_iorsi3): Likewise.
6201 (output_xorsi3): Likewise.
6203 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
6205 * doc/invoke.texi (RISC-V Options): Add list of supported
6206 extensions.
6208 2024-01-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6210 PR target/113495
6211 * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
6212 (RVV_VUNDEF): Ditto.
6213 * config/riscv/riscv-vsetvl.cc: Add timevar.
6215 2024-01-19 Richard Biener <rguenther@suse.de>
6217 PR debug/113488
6218 * lto-streamer-in.cc (lto_read_tree_1): When there isn't
6219 an early DIE but there should be, do not pretend there is.
6221 2024-01-19 Richard Biener <rguenther@suse.de>
6223 PR tree-optimization/113494
6224 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
6225 Handle endless loop on exit. Handle re-allocated PHI.
6227 2024-01-19 Jakub Jelinek <jakub@redhat.com>
6229 PR tree-optimization/113464
6230 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
6231 optimize loads into GIMPLE_ASM stmts.
6233 2024-01-19 Jakub Jelinek <jakub@redhat.com>
6235 PR tree-optimization/113463
6236 * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
6237 Only look through NOP_EXPRs if rhs1 doesn't have wider type than
6238 lhs.
6240 2024-01-19 Jakub Jelinek <jakub@redhat.com>
6242 PR tree-optimization/113459
6243 * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
6244 TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
6245 of SCALAR_INT_TYPE_MODE if type has BLKmode.
6246 (vn_reference_lookup_3): Likewise. Formatting fix.
6248 2024-01-19 Jakub Jelinek <jakub@redhat.com>
6249 Richard Biener <rguenther@suse.de>
6251 * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
6252 VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
6253 * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
6254 but adjust_address also for BLKmode mode and MEM op0.
6256 2024-01-19 Palmer Dabbelt <palmer@rivosinc.com>
6258 * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
6259 extensions.
6261 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
6263 * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
6265 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
6267 * common/config/riscv/riscv-common.cc
6268 (riscv_subset_list::parse_std_ext): Remove.
6269 (riscv_subset_list::parse_multiletter_ext): Remove.
6270 * config/riscv/riscv-subset.h
6271 (riscv_subset_list::parse_std_ext): Remove.
6272 (riscv_subset_list::parse_multiletter_ext): Remove.
6274 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
6276 * common/config/riscv/riscv-common.cc
6277 (riscv_subset_list::parse_single_std_ext): New parameter.
6278 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
6279 (riscv_subset_list::parse_single_ext): Ditto.
6280 (riscv_subset_list::parse): Relax the order for the input of ISA
6281 string.
6282 * config/riscv/riscv-subset.h
6283 (riscv_subset_list::parse_single_std_ext): New parameter.
6284 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
6285 (riscv_subset_list::parse_single_ext): Ditto.
6287 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
6289 * common/config/riscv/riscv-common.cc
6290 (riscv_subset_list::parse_base_ext): New.
6291 (riscv_subset_list::parse): Extract part of logic into
6292 riscv_subset_list::parse_base_ext.
6293 * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
6294 New.
6296 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
6298 * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
6299 sorry message.
6301 2024-01-19 Kuan-Lin Chen <rufus@andestech.com>
6303 * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
6304 UNSPEC_CLMUL_VC.
6306 2024-01-19 Sandra Loosemore <sandra@codesourcery.com>
6308 PR c/110029
6309 * doc/extend.texi (Common Variable Attributes): Explain what
6310 happens when multiple variables with cleanups are in the same scope.
6312 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
6314 PR ipa/108470
6315 * doc/extend.texi (Common Function Attributes): Document that
6316 noinline also disables some interprocedural optimizations and
6317 improve flow to the part about using inline asm instead to
6318 disable calls from being optimized away completely. Remove the
6319 sentence that says noipa is mainly for internal compiler testing.
6321 2024-01-18 John David Anglin <danglin@gcc.gnu.org>
6323 PR tree-optimization/69807
6324 * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
6326 2024-01-18 Brian Inglis <Brian.Inglis@Shaw.ca>
6328 PR target/108521
6329 * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
6330 from x86 Windows Options.
6332 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
6334 PR c/107942
6335 * doc/extend.texi (C Extensions): Add new section to menu.
6336 (Function Attributes): Move dangling index entries to....
6337 (Const and Volatile Functions): New section.
6339 2024-01-18 David Malcolm <dmalcolm@redhat.com>
6341 PR middle-end/112684
6342 * toplev.cc (toplev::main): Don't ICE in
6343 -fdiagnostics-generate-patch when exiting after options,
6344 since no edit context will have been created.
6346 2024-01-18 Richard Biener <rguenther@suse.de>
6348 * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
6349 operands vector.
6351 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
6353 * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
6354 when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
6356 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
6357 Jin Ma <jinma@linux.alibaba.com>
6358 Xianmiao Qu <cooper.qu@linux.alibaba.com>
6359 Christoph Müllner <christoph.muellner@vrull.eu>
6361 * config/riscv/thead.cc
6362 (th_asm_output_opcode): Rewrite some instructions.
6364 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
6365 Jin Ma <jinma@linux.alibaba.com>
6366 Xianmiao Qu <cooper.qu@linux.alibaba.com>
6367 Christoph Müllner <christoph.muellner@vrull.eu>
6369 * config/riscv/riscv.md (none,thv,rvv): New attribute.
6370 (no,yes): Add an attribute to disable alternative
6371 for xtheadvector or RVV1.0.
6372 * config/riscv/vector.md:
6373 Disable alternatives that destination register overlaps
6374 source register group for xtheadvector.
6376 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
6377 Jin Ma <jinma@linux.alibaba.com>
6378 Xianmiao Qu <cooper.qu@linux.alibaba.com>
6379 Christoph Müllner <christoph.muellner@vrull.eu>
6381 * config/riscv/riscv-vector-builtins-bases.cc
6382 (class th_loadstore_width): Define new builtin bases.
6383 (class th_extract): Define new builtin bases.
6384 (BASE): Define new builtin bases.
6385 * config/riscv/riscv-vector-builtins-bases.h:
6386 Define new builtin class.
6387 * config/riscv/riscv-vector-builtins-shapes.cc
6388 (struct th_loadstore_width_def): Define new builtin shapes.
6389 (struct th_indexed_loadstore_width_def):
6390 Define new builtin shapes.
6391 (struct th_extract_def): Define new builtin shapes.
6392 (SHAPE): Define new builtin shapes.
6393 * config/riscv/riscv-vector-builtins-shapes.h:
6394 Define new builtin shapes.
6395 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
6396 Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
6397 * config/riscv/riscv-vector-builtins.h
6398 (enum required_ext): Add new XTheadVector member.
6399 (struct function_group_info): Likewise.
6400 * config/riscv/t-riscv:
6401 Add thead-vector-builtins-functions.def
6402 * config/riscv/thead-vector.md
6403 (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
6404 (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
6405 (@pred_store_width<vlmem_op_attr><mode>): Likewise.
6406 (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
6407 (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
6408 (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
6409 (@pred_th_extract<mode>): Likewise.
6410 (*pred_th_extract<mode>): Likewise.
6411 * config/riscv/thead-vector-builtins-functions.def: New file.
6413 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
6414 Jin Ma <jinma@linux.alibaba.com>
6415 Xianmiao Qu <cooper.qu@linux.alibaba.com>
6416 Christoph Müllner <christoph.muellner@vrull.eu>
6418 * config.gcc: Add files for XTheadVector intrinsics.
6419 * config/riscv/autovec.md: Guard XTheadVector.
6420 * config/riscv/predicates.md: Disable immediate vl
6421 for XTheadVector.
6422 * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
6423 Add pragma for XTheadVector.
6424 * config/riscv/riscv-string.cc (riscv_expand_block_move):
6425 Guard XTheadVector.
6426 * config/riscv/riscv-v.cc (vls_mode_valid_p):
6427 Avoid autovec.
6428 * config/riscv/riscv-vector-builtins-bases.cc:
6429 Do not normalize vsetvl instructions for XTheadVector.
6430 * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
6431 New check type function.
6432 (build_one): Adjust for XTheadVector.
6433 * config/riscv/riscv-vector-switch.def (ENTRY):
6434 Disable fractional mode for the XTheadVector extension.
6435 (TUPLE_ENTRY): Likewise.
6436 * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
6437 Guard XTheadVector.
6438 (riscv_preferred_simd_mode): Likewsie.
6439 (riscv_autovectorize_vector_modes): Likewise.
6440 (riscv_vector_mode_supported_any_target_p): Likewise.
6441 (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
6442 * config/riscv/thead.cc (th_asm_output_opcode):
6443 Rewrite vsetvl instructions.
6444 * config/riscv/vector.md:
6445 Include thead-vector.md and change fractional LMUL
6446 into 1 for vbool.
6447 * config/riscv/riscv_th_vector.h: New file.
6448 * config/riscv/thead-vector.md: New file.
6450 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
6451 Jin Ma <jinma@linux.alibaba.com>
6452 Xianmiao Qu <cooper.qu@linux.alibaba.com>
6453 Christoph Müllner <christoph.muellner@vrull.eu>
6455 * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
6456 Add new function to add assembler insn code prefix/suffix.
6457 (th_asm_output_opcode):
6458 Add Thead function to add assembler insn code prefix/suffix.
6459 * config/riscv/riscv.cc (riscv_asm_output_opcode):
6460 Implement function to add assembler insn code prefix/suffix.
6461 * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
6462 Add new function to add assembler insn code prefix/suffix.
6463 * config/riscv/thead.cc (th_asm_output_opcode):
6464 Implement Thead function to add assembler insn code
6465 prefix/suffix.
6467 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
6468 Jin Ma <jinma@linux.alibaba.com>
6469 Xianmiao Qu <cooper.qu@linux.alibaba.com>
6470 Christoph Müllner <christoph.muellner@vrull.eu>
6472 * common/config/riscv/riscv-common.cc
6473 (riscv_subset_list::parse): Add new vendor extension.
6474 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
6475 Add test marco.
6476 * config/riscv/riscv.opt: Add new mask.
6478 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
6480 * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
6481 to be conditional on macosx-version-min.
6483 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
6485 * config/darwin.cc (darwin_objc1_section): Use the correct
6486 meta-data version for constant strings.
6487 (machopic_select_section): Assert if we fail to handle CFString
6488 sections as Obejctive-C meta-data or drectly.
6490 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
6492 * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
6493 OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
6494 OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
6495 versions when the object format is Mach-O.
6497 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
6499 PR target/105522
6500 * config/darwin.cc (machopic_select_section): Handle C and C++
6501 CFStrings.
6502 (darwin_rename_builtins): Move this out of the CFString code.
6503 (darwin_libc_has_function): Likewise.
6504 (darwin_build_constant_cfstring): Create an anonymous var to
6505 hold each CFString.
6506 * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
6507 CFstrings.
6509 2024-01-18 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
6511 PR bootstrap/113445
6512 * haifa-sched.cc (dep_list_size): Make global.
6513 * sched-deps.cc (find_inc): Use instead of sd_lists_size().
6514 * sched-int.h (dep_list_size): Declare.
6516 2024-01-18 Martin Jambor <mjambor@suse.cz>
6518 PR tree-optimization/110422
6519 * tree-sra.cc (scan_function): Disqualify bases of operands of asm
6520 gotos.
6522 2024-01-18 Richard Biener <rguenther@suse.de>
6524 PR tree-optimization/113475
6525 * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
6526 * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
6527 (phi_analyzer::~phi_analyzer): Deallocate and free collected
6528 phi_grous.
6529 (phi_analyzer::process_phi): Record allocated phi_groups.
6531 2024-01-18 Richard Biener <rguenther@suse.de>
6533 * tree-vect-stmts.cc (vectorizable_store): Do not allocate
6534 storage for gvec_oprnds elements.
6536 2024-01-18 Richard Biener <rguenther@suse.de>
6538 * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
6539 prefer all later exits we can handle.
6540 (vect_analyze_loop_form): Free the allocated loop body.
6541 Adjust comments.
6543 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
6545 * config/avr/avr-log.cc: Tabify.
6547 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6549 * config/riscv/autovec.md: Support vi variant.
6551 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
6553 * config/avr/avr-devices.cc: Tabify.
6555 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
6557 * config/avr/avr-c.cc: Tabify.
6559 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
6561 * config/avr/driver-avr.cc: Tabify.
6563 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
6565 * config/avr/gen-avr-mmcu-texi.cc: Tabify.
6567 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
6569 * config/avr/gen-avr-mmcu-specs.cc: Tabify.
6571 2024-01-18 Jakub Jelinek <jakub@redhat.com>
6573 * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
6574 minline-strcmp, minline-strncmp, minline-strlen,
6575 -param=riscv-vector-abi): Remove Bool keywords.
6577 2024-01-18 Jakub Jelinek <jakub@redhat.com>
6579 PR target/113122
6580 * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
6581 support. Add missing space after , in emitted assembly in some
6582 cases. Formatting fixes.
6584 2024-01-18 Xi Ruoyao <xry111@xry111.site>
6586 * config/loongarch/loongarch.md (movsi_internal): Remove
6587 constraint z.
6589 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
6591 * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
6592 in the diagnostic, and capitalize the device name.
6593 (print_mcu): Generate specs such that:
6594 <*check_rodata_in_ram>: New.
6595 <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
6596 <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
6597 <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
6599 2024-01-18 Jakub Jelinek <jakub@redhat.com>
6601 PR other/113399
6602 * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
6603 Common and Optimization.
6605 2024-01-18 Richard Biener <rguenther@suse.de>
6607 PR tree-optimization/113431
6608 * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
6609 When there is an invariant load we might not preserve
6610 scalar order.
6612 2024-01-18 Richard Biener <rguenther@suse.de>
6614 PR tree-optimization/113374
6615 * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
6616 * tree-vect-loop.cc (move_early_exit_stmts): Update
6617 virtual LC PHIs.
6618 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
6619 Refactor. Preserve virtual LC PHIs on all exits.
6621 2024-01-18 Lulu Cheng <chenglulu@loongson.cn>
6623 * config/loongarch/loongarch.cc (loongarch_split_symbol):
6624 Assign the '/u' attribute to the mem.
6626 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
6628 PR middle-end/110847
6629 * doc/invoke.texi (Option Summary): Document negative forms of
6630 -Wtsan and -Wxor-used-as-pow.
6631 (Warning Options): Likewise.
6633 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6635 PR target/113429
6636 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
6638 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
6640 * doc/extend.texi (Common Function Attributes): Re-alphabetize
6641 the table.
6642 (Common Variable Attributes): Likewise.
6643 (Common Type Attributes): Likewise.
6645 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
6647 PR middle-end/111659
6648 * doc/extend.texi (Common Variable Attributes): Fix long lines
6649 in documentation of strict_flex_array + other minor copy-editing.
6650 Add a cross-reference to -Wstrict-flex-arrays.
6651 * doc/invoke.texi (Option Summary): Fix whitespace in tables
6652 before -fstrict-flex-arrays and -Wstrict-flex-arrays.
6653 (C Dialect Options): Combine the docs for the two
6654 -fstrict-flex-arrays forms into a single entry. Note this option
6655 is for C/C++ only. Add a cross-reference to -Wstrict-flex-arrays.
6656 (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
6657 Minor copy-editing. Add cross references to the strict_flex_array
6658 attribute and -fstrict-flex-arrays option. Add note that this
6659 option depends on -ftree-vrp.
6661 2024-01-17 Andrew Pinski <quic_apinski@quicinc.com>
6663 PR target/113221
6664 * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
6665 only allow REG operands instead of allowing all.
6667 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
6669 * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
6670 Remove redundant checks in else condition for readablity.
6671 (earliest_fuse_vsetvl_info) Print iteration count in debug
6672 prints.
6673 (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
6674 dump details in certain cases.
6676 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
6678 * config/riscv/riscv.opt: New -param=vsetvl-strategy.
6679 * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
6680 * config/riscv/riscv-vsetvl.cc
6681 (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
6682 (pass_vsetvl::execute): Use vsetvl_strategy.
6684 2024-01-17 Jan Hubicka <jh@suse.cz>
6686 * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
6687 accidental hack reseting offset.
6689 2024-01-17 Jan Hubicka <jh@suse.cz>
6691 * config/i386/i386-options.cc (ix86_option_override_internal): Fix
6692 handling of X86_TUNE_AVOID_512FMA_CHAINS.
6694 2024-01-17 Jan Hubicka <jh@suse.cz>
6695 Jakub Jelinek <jakub@redhat.com>
6697 PR tree-optimization/110852
6698 * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
6699 binary operations
6700 (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
6701 PRED_COMBINED_VALUE_PREDICTIONS_PHI
6702 * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
6703 (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
6705 2024-01-17 Jakub Jelinek <jakub@redhat.com>
6707 PR tree-optimization/113421
6708 * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
6709 comment.
6710 (bitint_dom_walker::before_dom_children): Add g temporary to simplify
6711 formatting. Start at vop rather than cvop even if stmt is a store
6712 and needs_operand_addr.
6714 2024-01-17 Jakub Jelinek <jakub@redhat.com>
6716 PR middle-end/113410
6717 * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
6718 If access_nelts is integral with larger precision than sizetype,
6719 fold_convert it to sizetype.
6721 2024-01-17 Jakub Jelinek <jakub@redhat.com>
6723 PR tree-optimization/113408
6724 * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
6725 VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
6726 to handle_cast.
6728 2024-01-17 Jakub Jelinek <jakub@redhat.com>
6730 PR middle-end/113406
6731 * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
6732 regardless of whether is_gimple_reg_type (restype) or not.
6734 2024-01-17 Jakub Jelinek <jakub@redhat.com>
6736 * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
6737 funcions -> functions, and use were instead of was.
6738 * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
6739 and guaranteee -> guarantee.
6740 * attribs.h (struct attr_access): Fix comment typo funcion -> function.
6742 2024-01-17 Jakub Jelinek <jakub@redhat.com>
6744 PR middle-end/113409
6745 * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
6746 INTEGER_TYPE.
6747 (omp_extract_for_data): Use build_bitint_type rather than
6748 build_nonstandard_integer_type if either iter_type or loop->v type
6749 is BITINT_TYPE.
6750 * omp-expand.cc (expand_omp_for_generic,
6751 expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
6752 BITINT_TYPE like INTEGER_TYPE.
6754 2024-01-17 Richard Biener <rguenther@suse.de>
6756 PR tree-optimization/113371
6757 * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
6758 Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
6759 * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
6760 not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
6762 2024-01-17 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
6764 PR rtl-optimization/96388
6765 PR rtl-optimization/111554
6766 * sched-deps.cc (find_inc): Avoid exponential behavior.
6768 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
6770 PR c/111693
6771 * doc/invoke.texi (Option Summary): Move -Wuseless-cast
6772 from C++ Language Options to Warning Options. Add entry for
6773 -Wuse-after-free.
6774 (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
6775 from here....
6776 (Warning Options): ...to here. Minor copy-editing to fix typo
6777 and grammar.
6779 2024-01-17 YunQiang Su <syq@gcc.gnu.org>
6781 * config/mips/mips.cc (mips_compute_frame_info): If another
6782 register is used as global_pointer, mark $GP live false.
6784 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
6786 PR target/112973
6787 * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
6788 give the section a light copy-editing pass.
6790 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
6792 * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
6793 * config/aarch64/aarch64-tune.md: Regenerated.
6794 * doc/invoke.texi (-mcpu): Add cobalt-100 core.
6796 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
6798 PR target/112573
6799 * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
6800 badly formed CONST expressions.
6802 2024-01-16 Daniel Cederman <cederman@gaisler.com>
6804 * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
6806 2024-01-16 Daniel Cederman <cederman@gaisler.com>
6808 * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
6809 * config/sparc/sync.md (membar_storeload): Turn into named insn
6810 and add GR712RC errata workaround.
6811 (membar_v8): Add GR712RC errata workaround.
6813 2024-01-16 Andreas Larsson <andreas@gaisler.com>
6815 * config/sparc/sync.md (*membar_storeload_leon3): Remove
6816 (*membar_storeload): Enable for LEON
6818 2024-01-16 Jakub Jelinek <jakub@redhat.com>
6820 PR tree-optimization/113372
6821 PR middle-end/90348
6822 PR middle-end/110115
6823 PR middle-end/111422
6824 * cfgexpand.cc (add_scope_conflicts_2): New function.
6825 (add_scope_conflicts_1): Use it.
6827 2024-01-16 Georg-Johann Lay <avr@gjlay.de>
6829 * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
6830 (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
6831 * doc/avr-mmcu.texi: Regenerate.
6833 2024-01-16 Feng Xue <fxue@os.amperecomputing.com>
6835 PR tree-optimization/113091
6836 * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
6837 (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
6838 scalar use with new function.
6839 (vect_bb_slp_mark_live_stmts): New function as entry to existing
6840 overriden functions with same name.
6841 (vect_slp_analyze_operations): Call new entry function to mark
6842 live statements.
6844 2024-01-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6846 PR target/113404
6847 * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
6848 for RVV in big-endian mode.
6850 2024-01-16 Yanzhang Wang <yanzhang.wang@intel.com>
6852 * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
6853 (riscv_pass_in_vector_p): Delete.
6854 (riscv_init_cumulative_args): Delete the checking.
6855 (riscv_get_arg_info): Delete the checking.
6856 (riscv_function_value): Delete the checking.
6857 * config/riscv/riscv.h: Delete the member for checking.
6859 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
6861 * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
6863 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
6865 * config.gcc: Include riscv_bitmanip.h.
6866 * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
6867 * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
6868 * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
6869 (RISCV_BUILTIN_NO_PREFIX): New helper macro.
6870 * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
6871 * config/riscv/riscv-ftypes.def (2): New ftypes.
6872 * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
6873 (RISCV_BUILTIN_NO_PREFIX): Likewise.
6874 * config/riscv/riscv_bitmanip.h: New file.
6876 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
6878 * config.gcc: Include riscv_crypto.h.
6879 * config/riscv/riscv_crypto.h: New file.
6881 2024-01-15 Vladimir N. Makarov <vmakarov@redhat.com>
6883 PR middle-end/113354
6884 * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
6885 in the insn if the corresponding operand does not require hard
6886 register anymore.
6888 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
6890 PR target/107201
6891 * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
6892 * config/avr/driver-avr.cc (avr_no_devlib): New function.
6893 (avr_devicespecs_file): Use it to remove -nodevicelib from the
6894 options for cores only.
6895 * config/avr/avr-arch.h (avr_get_parch): New prototype.
6896 * config/avr/avr-devices.cc (avr_get_parch): New function.
6898 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6900 PR target/113247
6901 * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
6902 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
6903 * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
6905 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6907 PR target/113281
6908 * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
6909 (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
6910 * config/riscv/riscv-vector-costs.h: New function.
6912 2024-01-15 Richard Biener <rguenther@suse.de>
6914 PR tree-optimization/113385
6915 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
6916 First redirect, then split the exit edge.
6918 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6920 * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
6921 Remove m_num_vector_iterations.
6922 * config/riscv/riscv-vector-costs.h: Ditto.
6924 2024-01-15 Andrew Pinski <quic_apinski@quicinc.com>
6926 PR target/113156
6927 * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
6928 (-mbranch-cost): Set "Optimization" flag.
6930 2024-01-15 Jakub Jelinek <jakub@redhat.com>
6932 PR tree-optimization/113370
6933 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
6934 set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
6935 set it to just prec % limb_prec.
6937 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6939 PR target/113393
6940 * config/riscv/vector.md: Fix ternary attributes.
6942 2024-01-14 Georg-Johann Lay <avr@gjlay.de>
6944 PR target/112944
6945 * configure.ac [target=avr]: Check availability of emulations
6946 avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
6947 HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
6948 * configure: Regenerate.
6949 * config.in: Regenerate.
6950 * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
6951 __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
6952 * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
6953 * config/avr/avr-arch.h (enum avr_device_specific_features):
6954 Add AVR_ISA_FLMAP.
6955 * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
6956 AVR_ISA_FLMAP.
6957 * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
6958 (avr_set_core_architecture): Set avr_arch_index.
6959 (have_avrxmega2_flmap, have_avrxmega4_flmap)
6960 (have_avrxmega3_rodata_in_flash): Set new static const bool according
6961 to configure results.
6962 (avr_rodata_in_flash_p): New function using them.
6963 (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
6964 track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
6965 (avr_asm_named_section): Track avr_has_rodata_p.
6966 (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
6967 and not avr_rodata_in_flash_p ().
6968 * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
6969 (LINK_SPEC): Add %(link_rodata_in_ram).
6970 (LINK_ARCH_SPEC): Remove.
6971 * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
6972 (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
6973 const bool according to configure results.
6974 (diagnose_mrodata_in_ram): New function.
6975 (print_mcu): Generate specs with the following changes:
6976 <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
6977 need to extend avr/specs.h each time we add a new bell or whistle.
6978 <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
6979 -m[no-]rodata-in-ram.
6980 <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
6981 <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
6982 <*cpp>: Add %(cpp_rodata_in_ram).
6983 <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
6984 requested.
6985 <*self_spec>: Add -mflmap or %<mflmap as needed.
6987 2024-01-14 Jeff Law <jlaw@ventanamicro.com>
6989 * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
6990 not the GPR iterator. Adjust pattern name and mode attribute
6991 accordingly.
6993 2024-01-13 Jakub Jelinek <jakub@redhat.com>
6995 PR tree-optimization/113361
6996 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
6997 Fix up determination of the type for > limb_prec constants.
6999 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
7001 * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
7002 Add web-link to the avr-gcc wiki.
7004 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
7006 * doc/extend.texi (AVR Variable Attributes) [address]: Remove
7007 documentation for a version without argument, which is not supported.
7009 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
7011 * config/arm/arm_neon.h
7012 (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
7013 (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
7014 (vld1_f16_x4, vld1_f32_x4): New.
7015 (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
7016 (vld1_bf16_x4): New.
7017 (vld1q_types_x4): Updated to use vld1q_x4
7018 from arm_neon_builtins.def
7019 * config/arm/arm_neon_builtins.def
7020 (vld1_x4): Updated entries.
7021 (vld1q_x4): New entries, but comes from the old vld1_x4
7022 * config/arm/neon.md
7023 (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
7025 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
7027 * config/arm/arm_neon.h
7028 (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
7029 (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
7030 (vld1_f16_x3, vld1_f32_x3): New.
7031 (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
7032 (vld1_bf16_x3): New.
7033 (vld1q_types_x3): Updated to use vld1q_x3 from
7034 arm_neon_builtins.def
7035 * config/arm/arm_neon_builtins.def
7036 (vld1_x3): Updated entries.
7037 (vld1q_x3): New entries, but comes from the old vld1_x2
7038 * config/arm/neon.md
7039 (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
7041 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
7043 * config/arm/arm_neon.h
7044 (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
7045 (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
7046 (vld1_f16_x2, vld1_f32_x2): New.
7047 (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
7048 (vld1_bf16_x2): New.
7049 (vld1q_types_x2): Updated to use vld1q_x2 from
7050 arm_neon_builtins.def
7051 * config/arm/arm_neon_builtins.def
7052 (vld1_x2): Updated entries.
7053 (vld1q_x2): New entries, but comes from the old vld1_x2
7054 * config/arm/neon.md
7055 (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
7056 neon_vld1_x2<mode>.
7058 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
7060 * config/arm/arm_neon.h
7061 (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
7062 (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
7063 (vst1q_f16_x4, vst1q_f32_x4): New.
7064 (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
7065 (vst1q_bf16_x4): New.
7066 * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
7067 * config/arm/neon.md
7068 (neon_vst1q_x4<mode>): New.
7069 (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
7070 * config/arm/unspecs.md
7071 (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
7073 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
7075 * config/arm/arm_neon.h
7076 (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
7077 (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
7078 (vst1q_f16_x3, vst1q_f32_x3): New.
7079 (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
7080 (vst1q_bf16_x3): New.
7081 * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
7082 * config/arm/neon.md
7083 (neon_vst1q_x3<mode>): New.
7084 (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
7085 * config/arm/unspecs.md
7086 (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
7088 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
7090 * config/arm/arm_neon.h
7091 (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
7092 (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
7093 (vst1q_f16_x2, vst1q_f32_x2): New.
7094 (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
7095 (vst1q_bf16_x2): New.
7096 * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
7097 * config/arm/neon.md
7098 (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
7099 neon_vst1_x2<mode>.
7100 * config/arm/iterators.md
7101 (VMEMX2): New mode iterator.
7102 (VMEMX2_q): New mode attribute.
7104 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
7106 * config/arm/arm_neon.h
7107 (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
7108 (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
7109 (vst1_f16_x4, vst1_f32_x4): New.
7110 (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
7111 (vst1_bf16_x4): New.
7112 * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
7113 * config/arm/neon.md (vst1_x4<mode>): New.
7115 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
7117 * config/arm/arm_neon.h
7118 (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
7119 (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
7120 (vst1_f16_x3, vst1_f32_x3): New.
7121 (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
7122 (vst1_bf16_x3): New.
7123 * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
7124 * config/arm/neon.md (vst1_x3<mode>): New.
7126 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
7128 * config/arm/arm_neon.h
7129 (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
7130 (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
7131 (vst1_f16_x2, vst1_f32_x2): New.
7132 (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
7133 (vst1_bf16_x2): New.
7134 * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
7135 * config/arm/neon.md (vst1_x2<mode>): New.
7137 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
7139 * config/arm/arm_neon.h
7140 (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
7141 (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
7142 (vld1q_f16_x4, vld1q_f32_x4): New.
7143 (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
7144 (vld1q_bf16_x4): New.
7145 * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
7146 * config/arm/neon.md
7147 (neon_vld1_x4<mode>): New.
7148 (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
7149 * config/arm/unspecs.md
7150 (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
7152 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
7154 * config/arm/arm_neon.h
7155 (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
7156 (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
7157 (vld1q_f16_x3, vld1q_f32_x3): New.
7158 (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
7159 (vld1q_bf16_x3): New.
7160 * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
7161 * config/arm/neon.md
7162 (neon_vld1_x3<mode>): New.
7163 (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
7164 * config/arm/unspecs.md
7165 (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
7167 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
7169 * config/arm/arm_neon.h
7170 (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
7171 (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
7172 (vld1q_f16_x2, vld1q_f32_x2): New.
7173 (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
7174 (vld1q_bf16_x2): New.
7175 * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
7176 * config/arm/neon.md (vld1_x2<mode>): New.
7178 2024-01-12 Tamar Christina <tamar.christina@arm.com>
7180 PR tree-optimization/113287
7181 * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
7183 2024-01-12 Tamar Christina <tamar.christina@arm.com>
7185 * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
7186 * tree-vect-loop.cc (vect_transform_loop): Likewise.
7188 2024-01-12 Tamar Christina <tamar.christina@arm.com>
7190 PR tree-optimization/113178
7191 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
7192 alternate exits.
7194 2024-01-12 Tamar Christina <tamar.christina@arm.com>
7196 PR tree-optimization/113237
7197 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
7198 existing LCSSA variable for exit when all exits are early break.
7200 2024-01-12 Tamar Christina <tamar.christina@arm.com>
7202 PR tree-optimization/113137
7203 PR tree-optimization/113136
7204 PR tree-optimization/113172
7205 PR tree-optimization/113178
7206 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
7207 Maintain PHIs on inverted loops.
7208 (vect_do_peeling): Maintain virtual PHIs on inverted loops.
7209 * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
7210 latch.
7211 (vect_create_loop_vinfo): Record all conds instead of only alt ones.
7213 2024-01-12 Tamar Christina <tamar.christina@arm.com>
7215 PR tree-optimization/113135
7216 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
7217 dependency analysis.
7219 2024-01-12 Iain Sandoe <iain@sandoe.co.uk>
7221 * config/rs6000/host-darwin.cc (segv_handler): Use the revised
7222 diagnostics class member name for abort of error.
7224 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
7226 * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
7227 format string to %s argument.
7229 2024-01-12 John David Anglin <danglin@gcc.gnu.org>
7230 Jakub Jelinek <jakub@redhat.com>
7232 PR middle-end/113182
7233 * varasm.cc (process_pending_assemble_externals,
7234 assemble_external_libcall): Use targetm.strip_name_encoding
7235 before calling get_identifier.
7237 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
7239 PR target/113196
7240 * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
7241 New member variable.
7242 * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
7243 Declare.
7244 * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
7245 * config/aarch64/aarch64-simd.md
7246 (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
7247 (vec_unpack<su>_hi_<mode>): ...this. Move the generation of
7248 zip2 for zero-extends to...
7249 (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
7250 instruction. Fix big-endian handling.
7251 (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
7252 (vec_unpack<su>_lo_<mode>): ...this. Move the generation of
7253 zip1 for zero-extends to...
7254 (<optab><Vnarrowq><mode>2): ...a split of this instruction.
7255 Fix big-endian handling.
7256 (*aarch64_zip1_uxtl): New pattern.
7257 (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
7258 (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
7259 * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
7260 (aarch64_gen_shareable_zero): Use it.
7261 (aarch64_split_simd_shift_p): New function.
7263 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
7265 * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
7266 (function_beg_insn): New macro.
7267 * function.cc (expand_function_start): Initialize function_beg_insn.
7269 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
7271 PR target/112989
7272 * config/aarch64/aarch64-sve-builtins.h
7273 (function_builder::m_overload_names): Replace with...
7274 * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
7275 new global.
7276 (add_overloaded_function): Update accordingly, using get_identifier
7277 to get a GGC-friendly record of the name.
7279 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
7281 PR target/112989
7282 * config/aarch64/aarch64-sve-builtins.def: Don't include
7283 aarch64-sve-builtins-sme.def.
7284 (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
7285 * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
7286 (DEF_SME_FUNCTION): New macro. Use it and DEF_SME_FUNCTION_GS
7287 instead of DEF_SVE_*. Add AARCH64_FL_SME to anything that
7288 requires AARCH64_FL_SME2.
7289 * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
7290 AARCH64_FL_SME adjustment here.
7291 * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
7292 include SME intrinsics.
7293 (sme_function_groups): New array.
7294 (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
7295 (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
7297 2024-01-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7299 PR target/113281
7300 * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
7301 (struct cpu_vector_cost): Add regmove struct.
7302 (get_vector_costs): Export as global.
7303 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
7304 (costs::add_stmt_cost): Ditto.
7305 * config/riscv/riscv.cc (get_common_costs): Export global function.
7307 2024-01-12 Jakub Jelinek <jakub@redhat.com>
7309 PR tree-optimization/113334
7310 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
7311 wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
7312 to determine if number should be extended by all ones rather than zero
7313 extended.
7315 2024-01-12 Jakub Jelinek <jakub@redhat.com>
7317 PR tree-optimization/113330
7318 * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
7319 too large size.
7321 2024-01-12 Jakub Jelinek <jakub@redhat.com>
7323 PR tree-optimization/113323
7324 * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
7325 check for lhs being large/huge _BitInt not in m_names.
7327 2024-01-12 Jakub Jelinek <jakub@redhat.com>
7329 PR tree-optimization/113316
7330 * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
7331 uninitialized large/huge _BitInt arguments to calls.
7333 2024-01-12 Jakub Jelinek <jakub@redhat.com>
7335 * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
7336 TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
7337 CEIL (TYPE_PRECISION (t), limb_prec).
7338 (bitint_large_huge::handle_cast): Likewise.
7340 2024-01-12 Ilya Leoshkevich <iii@linux.ibm.com>
7342 PR sanitizer/113284
7343 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
7344 Use assemble_function_label_final () for Power ELF V1 ABI.
7345 * output.h (assemble_function_label_final): New function.
7346 * varasm.cc (assemble_function_label_raw): Use
7347 assemble_function_label_final ().
7348 (assemble_function_label_final): New function.
7350 2024-01-12 Richard Biener <rguenther@suse.de>
7352 PR middle-end/113344
7353 * match.pd ((double)float CMP (double)float -> float CMP float):
7354 Perform result type check only for vectors.
7355 * fold-const.cc (fold_binary_loc): Likewise.
7357 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
7359 * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
7360 (usdot_prod<mode>): Ditto.
7361 (sdot_prod<mode>): Ditto.
7362 (udot_prod<mode>): Ditto.
7364 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
7366 PR target/113288
7367 * config/i386/i386-c.cc (ix86_target_macros_internal):
7368 Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
7370 2024-01-12 Richard Biener <rguenther@suse.de>
7372 PR target/112280
7373 * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
7374 Do not generate code when d.testing_p.
7376 2024-01-12 liuhongt <hongtao.liu@intel.com>
7378 PR target/113039
7379 * doc/invoke.texi (fcf-protection=): Update documents.
7381 2024-01-12 Pan Li <pan2.li@intel.com>
7383 * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
7384 comments of predicate func riscv_v_ext_mode_p.
7386 2024-01-12 Feng Wang <wangfeng@eswincomputing.com>
7388 * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
7389 Modify ABI-name length of vfloat16m8_t
7391 2024-01-12 Li Wei <liwei@loongson.cn>
7393 * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
7394 Adjust.
7396 2024-01-12 Li Wei <liwei@loongson.cn>
7398 * config/loongarch/loongarch.md (add<mode>3): Removed.
7399 (*addsi3): New.
7400 (addsi3): Ditto.
7401 (adddi3): Ditto.
7402 (*addsi3_extended): Removed.
7403 (addsi3_extended): New.
7405 2024-01-11 Jin Ma <jinma@linux.alibaba.com>
7407 * config/riscv/thead.md: Add limits for splits.
7409 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
7411 PR middle-end/113322
7412 * expr.cc (do_store_flag): Don't try single bit tests with
7413 comparison on vector types.
7415 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
7417 PR tree-optimization/113301
7418 * match.pd (`1/x`): Delay signed case until late.
7420 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
7422 * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
7423 and -msp8 to...
7424 (AVR Internal Options): ...this new @subsubsection.
7426 2024-01-11 Vladimir N. Makarov <vmakarov@redhat.com>
7428 PR rtl-optimization/112918
7429 * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
7430 (in_class_p): Restrict condition for narrowing class in case of
7431 allow_all_reload_class_changes_p.
7432 (process_alt_operands): Try to match operand without and with
7433 narrowing reg class. Discourage narrowing the class. Finish insn
7434 matching only if there is no class narrowing.
7435 (curr_insn_transform): Pass true to in_class_p for reg operand win.
7437 2024-01-11 Richard Biener <rguenther@suse.de>
7439 PR tree-optimization/112505
7440 * tree-vect-loop.cc (vectorizable_induction): Reject
7441 bit-precision induction.
7443 2024-01-11 Richard Biener <rguenther@suse.de>
7445 PR tree-optimization/113126
7446 * match.pd ((double)float CMP (double)float -> float CMP float):
7447 Make sure the boolean type is the same.
7448 * fold-const.cc (fold_binary_loc): Likewise.
7450 2024-01-11 Richard Biener <rguenther@suse.de>
7452 PR tree-optimization/112636
7453 * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
7454 estimate_numbers_of_iterations before querying
7455 get_max_loop_iterations_int.
7456 (pass_ch::execute): Initialize SCEV and loops appropriately.
7458 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
7460 * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
7461 Reduced Tiny.
7462 * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
7463 * doc/extend.texi (AVR Variable Attributes): Improve documentation
7464 of io, io_low and address attributes.
7465 * doc/invoke.texi (AVR Options): Add some anchors for external refs.
7466 * doc/avr-mmcu.texi: Rebuild.
7468 2024-01-11 Yang Yujie <yangyujie@loongson.cn>
7470 PR target/113233
7471 * config/loongarch/genopts/loongarch.opt.in: Mark options with
7472 the "Save" property.
7473 * config/loongarch/loongarch.opt: Same.
7474 * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
7475 according to la_target.
7476 * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
7477 RESTORE} for the la_target structure; Rename option conditions
7478 to have the same "la_" prefix.
7479 * config/loongarch/loongarch.h: Same.
7481 2024-01-11 Pan Li <pan2.li@intel.com>
7483 * loop-unroll.cc (insert_var_expansion_initialization): Leverage
7484 MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
7486 2024-01-11 Alex Coplan <alex.coplan@arm.com>
7488 PR target/113077
7489 * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
7490 fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
7491 (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
7492 synthesize these if needed. Update caller ...
7493 (ldp_bb_info::fuse_pair): ... here.
7494 (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
7495 and either insn is frame-related.
7496 (find_trailing_add): Punt on frame-related insns.
7497 * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
7498 REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
7500 2024-01-11 YunQiang Su <syq@gcc.gnu.org>
7502 * config/mips/mips.cc (mips_start_function_definition):
7503 Add ATTRIBUTE_UNUSED.
7505 2024-01-11 Richard Biener <rguenther@suse.de>
7507 PR middle-end/112740
7508 * expr.cc (store_constructor): Check the integer vector
7509 mask has a single bit per element before using sign-extension
7510 to expand an uniform vector.
7512 2024-01-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7514 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
7515 preempt VLS on unknown NITERS loop.
7517 2024-01-11 Haochen Jiang <haochen.jiang@intel.com>
7519 * doc/invoke.texi: Add -mevex512.
7521 2024-01-11 Lulu Cheng <chenglulu@loongson.cn>
7523 * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
7524 (*nor<mode>3): Likewise.
7525 (nor<mode>3): Likewise.
7526 (*negsi2_extended): New template.
7527 (*<optab>si3_internal): Likewise.
7528 (*one_cmplsi2_internal): Likewise.
7529 (*norsi3_internal): Likewise.
7530 (*<optab>nsi_internal): Likewise.
7531 (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
7532 modified bit operation to make the optimization work.
7534 2024-01-11 liuhongt <hongtao.liu@intel.com>
7536 PR target/104401
7537 * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
7539 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7541 * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
7542 (get_vector_costs): Ditto.
7543 (riscv_builtin_vectorization_cost): Ditto.
7545 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7547 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
7549 2024-01-10 Antoni Boucher <bouanto@zoho.com>
7551 PR jit/111396
7552 * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
7553 ipa_free_size_summary.
7554 * ipa-icf.cc (ipa_icf_cc_finalize): New function.
7555 * ipa-profile.cc (ipa_profile_cc_finalize): New function.
7556 * ipa-prop.cc (ipa_prop_cc_finalize): New function.
7557 * ipa-prop.h (ipa_prop_cc_finalize): New function.
7558 * ipa-sra.cc (ipa_sra_cc_finalize): New function.
7559 * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
7560 ipa_sra_cc_finalize): New functions.
7561 * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
7562 ipa_prop_cc_finalize, ipa_profile_cc_finalize and
7563 ipa_sra_cc_finalize
7564 Include ipa-utils.h.
7566 2024-01-10 Jin Ma <jinma@linux.alibaba.com>
7568 * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
7569 (th_int_get_save_adjustment): Likewise.
7570 (th_int_adjust_cfi_prologue): Likewise.
7571 * config/riscv/riscv.cc (BITSET_P): Moved away from here.
7572 (TH_INT_INTERRUPT): New macro.
7573 (riscv_expand_prologue): Add the processing of XTheadInt.
7574 (riscv_expand_epilogue): Likewise.
7575 * config/riscv/riscv.h (BITSET_P): Moved to here.
7576 * config/riscv/riscv.md: New unspec.
7577 * config/riscv/thead.cc (th_int_get_mask): New function.
7578 (th_int_get_save_adjustment): Likewise.
7579 (th_int_adjust_cfi_prologue): Likewise.
7580 * config/riscv/thead.md (th_int_push): New pattern.
7581 (th_int_pop): new pattern.
7583 2024-01-10 Tamar Christina <tamar.christina@arm.com>
7585 PR tree-optimization/112468
7586 * doc/sourcebuild.texi: Document ifn_copysign.
7587 * match.pd: Only apply transformation if target supports the IFN.
7589 2024-01-10 Andrew Pinski <quic_apinski@quicinc.com>
7591 PR tree-optimization/112581
7592 * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
7593 mark_ssa_maybe_undefs.
7594 * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
7595 variables can not be reassociated.
7596 (init_range_entry): Check for uninitialized variables too.
7597 (init_reassoc): Call mark_ssa_maybe_undefs.
7599 2024-01-10 Maciej W. Rozycki <macro@embecosm.com>
7601 * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
7602 Also handle sign extension.
7604 2024-01-10 Alex Coplan <alex.coplan@arm.com>
7606 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
7607 to 0.
7608 (-mlate-ldp-fusion): Likewise.
7610 2024-01-10 Tamar Christina <tamar.christina@arm.com>
7612 PR tree-optimization/113287
7613 * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
7614 instead of using BRANCH_EDGE to determine true edge.
7616 2024-01-10 Richard Biener <rguenther@suse.de>
7618 PR tree-optimization/113078
7619 * tree-vect-loop.cc (check_reduction_path): Canonicalize
7620 .COND_SUB to .COND_ADD.
7622 2024-01-10 David Malcolm <dmalcolm@redhat.com>
7624 * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
7625 Handle prefix mappings before calling find_opt.
7626 (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
7627 "-fno-"-prefixed command-line option.
7628 * opts-common.cc (get_option_prefix_remapping): New.
7629 * opts.h (get_option_prefix_remapping): New decl.
7631 2024-01-10 David Malcolm <dmalcolm@redhat.com>
7633 * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
7634 m_urlifier to pp_output_formatted_text.
7635 * pretty-print.cc: Add #define of INCLUDE_VECTOR.
7636 (obstack_append_string): New overload, taking a length.
7637 (urlify_quoted_string): Pass in an obstack ptr, rather than using
7638 that of the pp's buffer. Generalize to handle trailing text in
7639 the buffer beyond the run of quoted text.
7640 (class quoting_info): New.
7641 (on_begin_quote): New.
7642 (on_end_quote): New.
7643 (pp_format): Refactor phase 1 and phase 2 quoting support, moving
7644 it to calls to on_begin_quote and on_end_quote.
7645 (struct auto_obstack): New.
7646 (quoting_info::handle_phase_3): New.
7647 (pp_output_formatted_text): Add urlifier param. Use it if there
7648 is deferred urlification. Delete m_quotes.
7649 (selftest::pp_printf_with_urlifier): Pass urlifier to
7650 pp_output_formatted_text.
7651 (selftest::test_urlification): Update results for the existing
7652 case of quoted text stradding chunks; add more such test cases.
7653 * pretty-print.h (class quoting_info): New forward decl.
7654 (chunk_info::m_quotes): New field.
7655 (pp_output_formatted_text): Add optional urlifier param.
7657 2024-01-10 David Malcolm <dmalcolm@redhat.com>
7659 * pretty-print.cc (selftest::test_pp_format): Add selftest
7660 coverage for numbered args.
7662 2024-01-10 Tamar Christina <tamar.christina@arm.com>
7664 PR tree-optimization/113144
7665 PR tree-optimization/113145
7666 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
7667 Update all BB that the original exits dominated.
7669 2024-01-10 Eric Botcazou <ebotcazou@adacore.com>
7671 * dwarf2out.cc (modified_type_die): Extend the support of reverse
7672 storage order to enumeration types if -gstrict-dwarf is not passed.
7673 (gen_enumeration_type_die): Add REVERSE parameter and generate the
7674 DIE immediately after the existing one if it is true.
7675 (gen_tagged_type_die): Add REVERSE parameter and pass it in the
7676 call to gen_enumeration_type_die.
7677 (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
7678 first recursive call as well as the call to gen_tagged_type_die.
7679 (gen_type_die): Add REVERSE parameter and pass it in the call to
7680 gen_type_die_with_usage.
7682 2024-01-10 Jakub Jelinek <jakub@redhat.com>
7684 PR tree-optimization/113120
7685 * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
7686 with root->size TYPE_PRECISION don't build anything new.
7687 Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
7688 rather than build_nonstandard_integer_type.
7690 2024-01-10 Hongyu Wang <hongyu.wang@intel.com>
7692 * config/i386/i386.opt: Adjust document.
7693 * doc/invoke.texi: Add description for
7694 -mapx-inline-asm-use-gpr32.
7696 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7698 * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
7699 (avg<v_double_trunc>3_floor): New pattern.
7700 (<u>avg<v_double_trunc>3_ceil): Remove.
7701 (avg<v_double_trunc>3_ceil): New pattern.
7702 (uavg<mode>3_floor): Ditto.
7703 (uavg<mode>3_ceil): Ditto.
7704 * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
7705 (enum insn_type): Ditto.
7706 * config/riscv/riscv-v.cc: Ditto.
7707 * config/riscv/vector-iterators.md (ashiftrt): Remove.
7708 (ASHIFTRT): Ditto.
7709 * config/riscv/vector.md: Add VLS modes.
7711 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
7713 PR target/111480
7714 * config/rs6000/vsx.md (VCZLSBB): New int iterator.
7715 (vczlsbb_char): New int attribute.
7716 (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
7717 (vc<vczlsbb_char>zlsbb_<mode>): ... this.
7718 (*vctzlsbb_zext_<mode>): Rename to ...
7719 (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
7720 cover vclzlsbb.
7722 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
7724 PR target/112606
7725 * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
7726 of the last argument from altivec_register_operand to any_operand. If
7727 operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
7728 otherwise if it doesn't satisfy altivec_register_operand, force it to
7729 REG using copy_to_mode_reg.
7731 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
7733 PR middle-end/113100
7734 * builtins.cc (expand_builtin_stack_address): Guard stack point
7735 adjustment with SPARC_STACK_BOUNDARY_HACK.
7737 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
7739 * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
7740 argument string definitions.
7741 * config/loongarch/loongarch-str.h: Same.
7742 * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
7743 as aliases to -mexplicit-relocs={always,none}
7744 * config/loongarch/loongarch.opt: Regenerate.
7745 * config/loongarch/loongarch.cc: Same.
7747 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
7749 * config/loongarch/loongarch-def.h: Define constants with
7750 enums instead of Macros.
7752 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
7754 * config/loongarch/genopts/loongarch-strings: Rename.
7755 * config/loongarch/genopts/loongarch.opt.in: Same.
7756 * config/loongarch/loongarch-cpu.cc: Same.
7757 * config/loongarch/loongarch-def.cc: Same.
7758 * config/loongarch/loongarch-def.h: Same.
7759 * config/loongarch/loongarch-opts.cc: Same.
7760 * config/loongarch/loongarch-opts.h: Same.
7761 * config/loongarch/loongarch-str.h: Same.
7762 * config/loongarch/loongarch.opt: Same.
7764 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
7766 * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
7767 variable with the common la_ prefix.
7768 * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
7769 flags as saved using TargetVariable.
7770 * config/loongarch/loongarch.opt: Same.
7771 * config/loongarch/loongarch-def.h: Define evolution_set to
7772 mark changes to the -march default.
7773 * config/loongarch/loongarch-driver.cc: Same.
7774 * config/loongarch/loongarch-opts.cc: Same.
7775 * config/loongarch/loongarch-opts.h: Define and use ISA evolution
7776 conditions around the la_target structure.
7777 * config/loongarch/loongarch.cc: Same.
7778 * config/loongarch/loongarch.md: Same.
7779 * config/loongarch/loongarch-builtins.cc: Same.
7780 * config/loongarch/loongarch-c.cc: Same.
7781 * config/loongarch/lasx.md: Same.
7782 * config/loongarch/lsx.md: Same.
7783 * config/loongarch/sync.md: Same.
7785 2024-01-09 Jeff Law <jlaw@ventanamicro.com>
7787 * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
7788 no less.
7790 2024-01-09 Richard Sandiford <richard.sandiford@arm.com>
7792 * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
7794 2024-01-09 Tamar Christina <tamar.christina@arm.com>
7796 * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
7797 restart_loop.
7798 (vectorizable_live_operation): Likewise.
7800 2024-01-09 Tamar Christina <tamar.christina@arm.com>
7802 PR tree-optimization/113199
7803 * tree-vect-loop.cc (vectorizable_live_operation_1): Use
7804 BIT_FIELD_REF.
7806 2024-01-09 Jakub Jelinek <jakub@redhat.com>
7808 PR target/113270
7809 * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
7810 * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
7811 GTY(()) declaration before the definition, drop GTY(()) drom the
7812 definition.
7814 2024-01-09 Richard Biener <rguenther@suse.de>
7816 PR tree-optimization/113026
7817 * tree-vect-loop-manip.cc (vect_do_peeling): Remove
7818 redundant and wrong niter bound setting. Move niter
7819 bound adjustment down.
7821 2024-01-09 Tamar Christina <tamar.christina@arm.com>
7823 PR middle-end/113163
7824 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
7825 Reject non-linear inductions that aren't supported.
7827 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
7829 * config/arc/arc.cc (arc_shift_alg): New enumerated type for
7830 left shift implementation strategies.
7831 (arc_shift_info): Type for each entry of the shift strategy table.
7832 (arc_shift_context_idx): Return a integer value for each code
7833 generation context, used as an index
7834 (arc_ashl_alg): Table indexed by context and shifted bit count.
7835 (arc_split_ashl): Use the arc_ashl_alg table to select SImode
7836 left shift implementation.
7837 (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
7838 provide accurate costs, when optimizing for speed or size.
7840 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7842 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
7844 2024-01-09 Julian Brown <julian@codesourcery.com>
7846 * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
7847 processed out before gimplification.
7848 * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
7849 * tree.def (OMP_ARRAY_SECTION): New tree code.
7851 2024-01-09 Jakub Jelinek <jakub@redhat.com>
7853 PR tree-optimization/113210
7854 * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
7855 value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
7856 INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
7857 minus 1.
7859 2024-01-09 Eric Botcazou <ebotcazou@adacore.com>
7861 PR rtl-optimization/113140
7862 * reorg.cc (fill_slots_from_thread): If we are to branch after the
7863 last instruction of the function, create an end label.
7865 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
7866 Hongtao Liu <hongtao.liu@intel.com>
7868 PR target/112992
7869 * config/i386/i386-expand.cc
7870 (ix86_convert_const_wide_int_to_broadcast): Allow call to
7871 ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
7872 (ix86_broadcast_from_constant): Revert recent change; Return a
7873 suitable MEMREF independently of mode/target combinations.
7874 (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
7875 to decide whether expansion is possible/preferrable. Only try
7876 forcing DImode constants to memory (and trying again) if calling
7877 ix86_expand_vector_init_duplicate fails with an DImode immediate
7878 constant.
7879 (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
7880 V4SImode for suitable immediate constants.
7881 <case E_V4DImode>: Try using V8SImode for suitable constants.
7882 <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
7883 <case E_V2HImode>: Likewise.
7884 <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
7885 <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
7886 <label widen>: Handle CONT_INTs via simplify_binary_operation.
7887 Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
7888 <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
7889 <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
7890 (ix86_expand_vector_init): Move try using a broadcast for all_same
7891 with ix86_expand_vector_init_duplicate before using constant pool.
7893 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
7895 * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
7897 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
7899 * config/arm/arm-cpus.in (cortex-m52): New cpu.
7900 * config/arm/arm-tables.opt: Regenerate.
7901 * config/arm/arm-tune.md: Regenerate.
7903 2024-01-09 Jiahao Xu <xujiahao@loongson.cn>
7905 * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
7906 (vec_init<mode><lasxhalf>): .. this, and extend to mode.
7907 (@vec_concatz<mode>): New insn pattern.
7908 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
7909 Handle VALS containing two vectors.
7911 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7913 * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
7914 (vundefined): Ditto.
7916 2024-01-09 Feng Wang <wangfeng@eswincomputing.com>
7918 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
7919 Add new function_base for crypto vector.
7920 (class bitmanip): Ditto.
7921 (class b_reverse):Ditto.
7922 (class vwsll): Ditto.
7923 (class clmul): Ditto.
7924 (class vg_nhab): Ditto.
7925 (class crypto_vv):Ditto.
7926 (class crypto_vi):Ditto.
7927 (class vaeskf2_vsm3c):Ditto.
7928 (class vsm3me): Ditto.
7929 (BASE): Add BASE declaration for crypto vector.
7930 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
7931 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
7932 Add crypto vector intrinsic definition.
7933 (vbrev): Ditto.
7934 (vclz): Ditto.
7935 (vctz): Ditto.
7936 (vwsll): Ditto.
7937 (vandn): Ditto.
7938 (vbrev8): Ditto.
7939 (vrev8): Ditto.
7940 (vrol): Ditto.
7941 (vror): Ditto.
7942 (vclmul): Ditto.
7943 (vclmulh): Ditto.
7944 (vghsh): Ditto.
7945 (vgmul): Ditto.
7946 (vaesef): Ditto.
7947 (vaesem): Ditto.
7948 (vaesdf): Ditto.
7949 (vaesdm): Ditto.
7950 (vaesz): Ditto.
7951 (vaeskf1): Ditto.
7952 (vaeskf2): Ditto.
7953 (vsha2ms): Ditto.
7954 (vsha2ch): Ditto.
7955 (vsha2cl): Ditto.
7956 (vsm4k): Ditto.
7957 (vsm4r): Ditto.
7958 (vsm3me): Ditto.
7959 (vsm3c): Ditto.
7960 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
7961 Add new function_shape for crypto vector.
7962 (struct crypto_vi_def): Ditto.
7963 (struct crypto_vv_no_op_type_def): Ditto.
7964 (SHAPE): Add SHAPE declaration of crypto vector.
7965 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
7966 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
7967 Add new data type for crypto vector.
7968 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7969 (vuint32mf2_t): Ditto.
7970 (vuint32m1_t): Ditto.
7971 (vuint32m2_t): Ditto.
7972 (vuint32m4_t): Ditto.
7973 (vuint32m8_t): Ditto.
7974 (vuint64m1_t): Ditto.
7975 (vuint64m2_t): Ditto.
7976 (vuint64m4_t): Ditto.
7977 (vuint64m8_t): Ditto.
7978 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
7979 Add new data struct for crypto vector.
7980 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7981 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
7982 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
7984 2024-01-08 Ilya Leoshkevich <iii@linux.ibm.com>
7986 PR sanitizer/113251
7987 * varasm.cc (assemble_function_label_raw): Do not call
7988 asan_function_start () without the current function.
7990 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
7992 PR target/113225
7993 * btfout.cc (btf_collect_datasec): Skip creating BTF info for
7994 extern and kernel_helper attributed function decls.
7996 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
7998 * btfout.cc (output_btf_strs): Changed.
8000 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
8002 * config/gcn/mkoffload.cc (main): Handle gfx1100
8003 when setting the default XNACK.
8005 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
8007 * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
8008 * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
8009 (ASM_SPEC): Handle gfx1100.
8010 * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
8011 (enum gcn_isa): Add ISA_RDNA3.
8012 (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
8013 * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
8014 * config/gcn/gcn.cc (gcn_option_override,
8015 gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
8016 (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
8017 TARGET_RDNA2 to TARGET_RDNA2_PLUS.
8018 (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
8019 with gfx1100.
8020 * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
8021 (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
8022 __gfx1100__.
8023 * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
8024 * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
8025 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
8026 (isa_has_combined_avgprs, main): Handle gfx1100.
8027 * config/gcn/t-omp-device (isa): Add gfx1100.
8029 2024-01-08 Richard Biener <rguenther@suse.de>
8031 * doc/invoke.texi (-mmovbe): Clarify.
8033 2024-01-08 Richard Biener <rguenther@suse.de>
8035 PR tree-optimization/113026
8036 * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
8037 Avoid an epilog in more cases.
8038 * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
8039 epilogues niter upper bounds and estimates.
8041 2024-01-08 Jakub Jelinek <jakub@redhat.com>
8043 PR tree-optimization/113228
8044 * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
8046 2024-01-08 Jakub Jelinek <jakub@redhat.com>
8048 PR tree-optimization/113120
8049 * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
8050 large _BitInt zero INTEGER_CST PHI argument.
8052 2024-01-08 Jakub Jelinek <jakub@redhat.com>
8054 PR tree-optimization/113119
8055 * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
8056 both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
8057 is before REALPART_EXPR.
8059 2024-01-08 Georg-Johann Lay <avr@gjlay.de>
8061 PR target/112952
8062 * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
8063 range when diagnosing attribute "io" and "io_low" are out of range.
8064 (avr_eval_addr_attrib): Don't ICE on empty address at that place.
8065 (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
8066 in contexts other than static storage.
8067 (avr_asm_output_aligned_decl_common): Move output of decls with
8068 attribute "address", "io", and "io_low" to...
8069 (avr_output_addr_attrib): ...this new function.
8070 (avr_asm_asm_output_aligned_bss): Remove output for decls with
8071 attribute "address", "io", and "io_low".
8072 (avr_encode_section_info): Rectify handling of decls with attribute
8073 "address", "io", and "io_low".
8075 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
8077 * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
8078 (elf_flags): Remove XNACK from the default value.
8079 (main): Set a default XNACK according to the arch.
8081 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
8083 * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
8084 (process_asm): Don't count avgprs.
8086 2024-01-08 Hongyu Wang <hongyu.wang@intel.com>
8088 * config/i386/i386.opt: Add supported sub-features.
8089 * doc/extend.texi: Add description for target attribute.
8091 2024-01-08 Feng Wang <wangfeng@eswincomputing.com>
8093 * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
8095 2024-01-07 Roger Sayle <roger@nextmovesoftware.com>
8096 Uros Bizjak <ubizjak@gmail.com>
8098 PR target/113231
8099 * config/i386/i386-features.cc (compute_convert_gain): Include
8100 the overhead of explicit load and store (movd) instructions when
8101 converting non-store scalar operations with memory destinations.
8102 Various indentation whitespace fixes.
8104 2024-01-07 Tamar Christina <tamar.christina@arm.com>
8106 * config/arm/neon.md (cbranch<mode>4): New.
8108 2024-01-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
8110 * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
8112 2024-01-06 Jiahao Xu <xujiahao@loongson.cn>
8114 * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
8116 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
8118 PR target/113248
8119 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
8120 Update the MAX_SEW.
8122 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
8124 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
8125 (variable_vectorized_p): Teach loop invariant.
8126 (has_unexpected_spills_p): Ditto.
8128 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
8130 * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
8131 * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
8132 * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
8134 2024-01-05 Richard Sandiford <richard.sandiford@arm.com>
8136 PR target/113104
8137 * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
8138 (aarch64-vect-compare-costs): ...this.
8139 * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
8140 Replace with...
8141 (-param=aarch64-vect-compare-costs=): ...this new param.
8142 * config/aarch64/aarch64.cc (aarch64_override_options_internal):
8143 Don't disable it when vectorizing for Advanced SIMD only.
8144 (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
8145 whenever aarch64_vect_compare_costs is true.
8147 2024-01-05 Lulu Cheng <chenglulu@loongson.cn>
8149 * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
8150 Modify the method of determining the memory offset of [x]vld/[x]vst.
8151 (lasx_mxst_<lasxfmt_f>): Likewise.
8152 * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
8153 (loongarch_address_insns): Likewise.
8154 * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
8155 (lsx_st_<lsxfmt_f>): Likewise.
8156 * config/loongarch/predicates.md (aq10b_operand): Likewise.
8157 (aq10h_operand): Likewise.
8158 (aq10w_operand): Likewise.
8159 (aq10d_operand): Likewise.
8161 2024-01-05 Alex Coplan <alex.coplan@arm.com>
8163 PR target/113217
8164 * config/aarch64/aarch64-ldp-fusion.cc
8165 (ldp_bb_info::try_fuse_pair): If the second access can throw,
8166 narrow the move range to exactly that insn.
8168 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
8170 * asan.cc (asan_function_start): Drop switch_to_section ().
8171 (asan_emit_stack_protection): Set .LASANPC alignment.
8172 * config/i386/i386.cc: Use assemble_function_label_raw ()
8173 instead of ASM_OUTPUT_LABEL ().
8174 * config/s390/s390.cc (s390_asm_output_function_label):
8175 Likewise.
8176 * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
8177 * final.cc (final_start_function_1): Drop
8178 asan_function_start ().
8179 * output.h (assemble_function_label_raw): New function.
8180 * varasm.cc (assemble_function_label_raw): Likewise.
8182 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
8184 * config/aarch64/aarch64.cc (aarch64_declare_function_name):
8185 Use ASM_OUTPUT_FUNCTION_LABEL ().
8186 * config/alpha/alpha.cc (alpha_start_function): Likewise.
8187 * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
8188 * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
8189 * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
8190 * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
8191 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
8192 * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
8193 * config/ia64/ia64.cc (ia64_start_function): Likewise.
8194 * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
8195 Likewise.
8196 * config/microblaze/microblaze.cc (microblaze_function_prologue):
8197 Likewise.
8198 * config/mips/mips.cc (mips_start_unique_function): Return the
8199 tree.
8200 (mips_start_function_definition): Use
8201 ASM_OUTPUT_FUNCTION_LABEL ().
8202 (mips_finish_stub): Pass the tree to
8203 mips_start_function_definition ().
8204 (mips16_build_function_stub): Likewise.
8205 (mips16_build_call_stub): Likewise.
8206 (mips_output_function_prologue): Likewise.
8207 * config/pa/pa.cc (pa_output_function_label): Use
8208 ASM_OUTPUT_FUNCTION_LABEL ().
8209 * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
8210 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
8211 Likewise.
8212 (rs6000_xcoff_declare_function_name): Likewise.
8214 2024-01-05 Jakub Jelinek <jakub@redhat.com>
8216 PR tree-optimization/113201
8217 * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
8218 replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
8220 2024-01-05 Jakub Jelinek <jakub@redhat.com>
8222 PR tree-optimization/90693
8223 * tree-ssa-math-opts.cc (match_single_bit_test): If
8224 tree_expr_nonzero_p (arg), remember it in the second argument to
8225 IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
8226 arg ^ (arg - 1) > arg - 1.
8227 * internal-fn.cc (expand_POPCOUNT): If second argument to
8228 IFN_POPCOUNT suggests arg is non-zero, try to expand it as
8229 arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
8231 2024-01-05 Kito Cheng <kito.cheng@sifive.com>
8233 * config/riscv/riscv-v.cc (expand_load_store):
8234 Remove `value`.
8235 (expand_cond_len_op): Ditto.
8236 (expand_gather_scatter): Ditto.
8237 (expand_lanes_load_store): Ditto.
8238 (expand_fold_extract_last): Ditto.
8240 2024-01-05 Pan Li <pan2.li@intel.com>
8242 Revert:
8243 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
8245 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
8246 Add new function_base for crypto vector.
8247 (class bitmanip): Ditto.
8248 (class b_reverse):Ditto.
8249 (class vwsll): Ditto.
8250 (class clmul): Ditto.
8251 (class vg_nhab): Ditto.
8252 (class crypto_vv):Ditto.
8253 (class crypto_vi):Ditto.
8254 (class vaeskf2_vsm3c):Ditto.
8255 (class vsm3me): Ditto.
8256 (BASE): Add BASE declaration for crypto vector.
8257 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
8258 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
8259 Add crypto vector intrinsic definition.
8260 (vbrev): Ditto.
8261 (vclz): Ditto.
8262 (vctz): Ditto.
8263 (vwsll): Ditto.
8264 (vandn): Ditto.
8265 (vbrev8): Ditto.
8266 (vrev8): Ditto.
8267 (vrol): Ditto.
8268 (vror): Ditto.
8269 (vclmul): Ditto.
8270 (vclmulh): Ditto.
8271 (vghsh): Ditto.
8272 (vgmul): Ditto.
8273 (vaesef): Ditto.
8274 (vaesem): Ditto.
8275 (vaesdf): Ditto.
8276 (vaesdm): Ditto.
8277 (vaesz): Ditto.
8278 (vaeskf1): Ditto.
8279 (vaeskf2): Ditto.
8280 (vsha2ms): Ditto.
8281 (vsha2ch): Ditto.
8282 (vsha2cl): Ditto.
8283 (vsm4k): Ditto.
8284 (vsm4r): Ditto.
8285 (vsm3me): Ditto.
8286 (vsm3c): Ditto.
8287 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
8288 Add new function_shape for crypto vector.
8289 (struct crypto_vi_def): Ditto.
8290 (struct crypto_vv_no_op_type_def): Ditto.
8291 (SHAPE): Add SHAPE declaration of crypto vector.
8292 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
8293 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
8294 Add new data type for crypto vector.
8295 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
8296 (vuint32mf2_t): Ditto.
8297 (vuint32m1_t): Ditto.
8298 (vuint32m2_t): Ditto.
8299 (vuint32m4_t): Ditto.
8300 (vuint32m8_t): Ditto.
8301 (vuint64m1_t): Ditto.
8302 (vuint64m2_t): Ditto.
8303 (vuint64m4_t): Ditto.
8304 (vuint64m8_t): Ditto.
8305 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
8306 Add new data struct for crypto vector.
8307 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
8308 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
8309 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
8311 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
8313 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
8314 Add new function_base for crypto vector.
8315 (class bitmanip): Ditto.
8316 (class b_reverse):Ditto.
8317 (class vwsll): Ditto.
8318 (class clmul): Ditto.
8319 (class vg_nhab): Ditto.
8320 (class crypto_vv):Ditto.
8321 (class crypto_vi):Ditto.
8322 (class vaeskf2_vsm3c):Ditto.
8323 (class vsm3me): Ditto.
8324 (BASE): Add BASE declaration for crypto vector.
8325 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
8326 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
8327 Add crypto vector intrinsic definition.
8328 (vbrev): Ditto.
8329 (vclz): Ditto.
8330 (vctz): Ditto.
8331 (vwsll): Ditto.
8332 (vandn): Ditto.
8333 (vbrev8): Ditto.
8334 (vrev8): Ditto.
8335 (vrol): Ditto.
8336 (vror): Ditto.
8337 (vclmul): Ditto.
8338 (vclmulh): Ditto.
8339 (vghsh): Ditto.
8340 (vgmul): Ditto.
8341 (vaesef): Ditto.
8342 (vaesem): Ditto.
8343 (vaesdf): Ditto.
8344 (vaesdm): Ditto.
8345 (vaesz): Ditto.
8346 (vaeskf1): Ditto.
8347 (vaeskf2): Ditto.
8348 (vsha2ms): Ditto.
8349 (vsha2ch): Ditto.
8350 (vsha2cl): Ditto.
8351 (vsm4k): Ditto.
8352 (vsm4r): Ditto.
8353 (vsm3me): Ditto.
8354 (vsm3c): Ditto.
8355 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
8356 Add new function_shape for crypto vector.
8357 (struct crypto_vi_def): Ditto.
8358 (struct crypto_vv_no_op_type_def): Ditto.
8359 (SHAPE): Add SHAPE declaration of crypto vector.
8360 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
8361 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
8362 Add new data type for crypto vector.
8363 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
8364 (vuint32mf2_t): Ditto.
8365 (vuint32m1_t): Ditto.
8366 (vuint32m2_t): Ditto.
8367 (vuint32m4_t): Ditto.
8368 (vuint32m8_t): Ditto.
8369 (vuint64m1_t): Ditto.
8370 (vuint64m2_t): Ditto.
8371 (vuint64m4_t): Ditto.
8372 (vuint64m8_t): Ditto.
8373 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
8374 Add new data struct for crypto vector.
8375 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
8376 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
8377 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
8379 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
8381 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
8383 2024-01-04 Andrew Pinski <quic_apinski@quicinc.com>
8385 PR tree-optimization/113186
8386 * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
8387 Match `^` with the `==` for 1bit integral types.
8388 * match.pd (maybe_cmp): Allow for bit_xor for 1bit
8389 integral types.
8391 2024-01-04 David Malcolm <dmalcolm@redhat.com>
8393 * toplev.cc (general_init): Pass lang_mask to urlifier.
8395 2024-01-04 David Malcolm <dmalcolm@redhat.com>
8397 * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
8398 param.
8399 (diagnostic_context::make_option_url): Update for lang_mask param.
8400 * gcc-urlifier.cc: Include "opts.h" and "options.h".
8401 (gcc_urlifier::gcc_urlifier): Add lang_mask param.
8402 (gcc_urlifier::m_lang_mask): New field.
8403 (doc_urls): Make static.
8404 (gcc_urlifier::get_url_for_quoted_text): Use label_text.
8405 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
8406 Look for an option by name before trying a binary search in
8407 doc_urls.
8408 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
8409 (gcc_urlifier::get_url_suffix_for_option): New.
8410 (make_gcc_urlifier): Add lang_mask param.
8411 (selftest::gcc_urlifier_cc_tests): Update for above changes.
8412 Verify that a URL is found for "-fpack-struct".
8413 * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
8414 * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
8415 * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
8416 to make_gcc_urlifier.
8417 * opts-diagnostic.h (get_option_url): Add lang_mask param.
8418 * opts.cc (get_option_html_page): Remove special-casing for
8419 analyzer and LTO.
8420 (get_option_url_suffix): New.
8421 (get_option_url): Reimplement.
8422 (selftest::test_get_option_html_page): Rename to...
8423 (selftest::test_get_option_url_suffix): ...this and update for
8424 above changes.
8425 (selftest::opts_cc_tests): Update for renaming.
8426 * opts.h: Include "rich-location.h".
8427 (get_option_url_suffix): New decl.
8429 2024-01-04 David Malcolm <dmalcolm@redhat.com>
8431 * Makefile.in (ALL_OPT_URL_FILES): New.
8432 (GCC_OBJS): Add options-urls.o.
8433 (OBJS): Likewise.
8434 (OBJS-libcommon): Likewise.
8435 (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
8436 inputs to opt-gather.awk.
8437 (options-urls.cc): New Makefile target.
8438 * opt-functions.awk (url_suffix): New function.
8439 (lang_url_suffix): New function.
8440 * options-urls-cc-gen.awk: New file.
8441 * opts.h (get_opt_url_suffix): New decl.
8443 2024-01-04 David Malcolm <dmalcolm@redhat.com>
8445 * params.opt.urls: New file, autogenerated by
8446 regenerate-opt-urls.py.
8448 2024-01-04 David Malcolm <dmalcolm@redhat.com>
8450 * common.opt.urls: New file, autogenerated by
8451 regenerate-opt-urls.py.
8452 * config/aarch64/aarch64.opt.urls: Likewise.
8453 * config/alpha/alpha.opt.urls: Likewise.
8454 * config/alpha/elf.opt.urls: Likewise.
8455 * config/arc/arc-tables.opt.urls: Likewise.
8456 * config/arc/arc.opt.urls: Likewise.
8457 * config/arm/arm-tables.opt.urls: Likewise.
8458 * config/arm/arm.opt.urls: Likewise.
8459 * config/arm/vxworks.opt.urls: Likewise.
8460 * config/avr/avr.opt.urls: Likewise.
8461 * config/bpf/bpf.opt.urls: Likewise.
8462 * config/c6x/c6x-tables.opt.urls: Likewise.
8463 * config/c6x/c6x.opt.urls: Likewise.
8464 * config/cris/cris.opt.urls: Likewise.
8465 * config/cris/elf.opt.urls: Likewise.
8466 * config/csky/csky.opt.urls: Likewise.
8467 * config/csky/csky_tables.opt.urls: Likewise.
8468 * config/darwin.opt.urls: Likewise.
8469 * config/dragonfly.opt.urls: Likewise.
8470 * config/epiphany/epiphany.opt.urls: Likewise.
8471 * config/fr30/fr30.opt.urls: Likewise.
8472 * config/freebsd.opt.urls: Likewise.
8473 * config/frv/frv.opt.urls: Likewise.
8474 * config/ft32/ft32.opt.urls: Likewise.
8475 * config/fused-madd.opt.urls: Likewise.
8476 * config/g.opt.urls: Likewise.
8477 * config/gcn/gcn.opt.urls: Likewise.
8478 * config/gnu-user.opt.urls: Likewise.
8479 * config/h8300/h8300.opt.urls: Likewise.
8480 * config/hpux11.opt.urls: Likewise.
8481 * config/i386/cygming.opt.urls: Likewise.
8482 * config/i386/cygwin.opt.urls: Likewise.
8483 * config/i386/djgpp.opt.urls: Likewise.
8484 * config/i386/i386.opt.urls: Likewise.
8485 * config/i386/mingw-w64.opt.urls: Likewise.
8486 * config/i386/mingw.opt.urls: Likewise.
8487 * config/i386/nto.opt.urls: Likewise.
8488 * config/ia64/ia64.opt.urls: Likewise.
8489 * config/ia64/ilp32.opt.urls: Likewise.
8490 * config/ia64/vms.opt.urls: Likewise.
8491 * config/iq2000/iq2000.opt.urls: Likewise.
8492 * config/linux-android.opt.urls: Likewise.
8493 * config/linux.opt.urls: Likewise.
8494 * config/lm32/lm32.opt.urls: Likewise.
8495 * config/loongarch/loongarch.opt.urls: Likewise.
8496 * config/lynx.opt.urls: Likewise.
8497 * config/m32c/m32c.opt.urls: Likewise.
8498 * config/m32r/m32r.opt.urls: Likewise.
8499 * config/m68k/ieee.opt.urls: Likewise.
8500 * config/m68k/m68k-tables.opt.urls: Likewise.
8501 * config/m68k/m68k.opt.urls: Likewise.
8502 * config/m68k/uclinux.opt.urls: Likewise.
8503 * config/mcore/mcore.opt.urls: Likewise.
8504 * config/microblaze/microblaze.opt.urls: Likewise.
8505 * config/mips/mips-tables.opt.urls: Likewise.
8506 * config/mips/mips.opt.urls: Likewise.
8507 * config/mips/sde.opt.urls: Likewise.
8508 * config/mmix/mmix.opt.urls: Likewise.
8509 * config/mn10300/mn10300.opt.urls: Likewise.
8510 * config/moxie/moxie.opt.urls: Likewise.
8511 * config/msp430/msp430.opt.urls: Likewise.
8512 * config/nds32/nds32-elf.opt.urls: Likewise.
8513 * config/nds32/nds32-linux.opt.urls: Likewise.
8514 * config/nds32/nds32.opt.urls: Likewise.
8515 * config/netbsd-elf.opt.urls: Likewise.
8516 * config/netbsd.opt.urls: Likewise.
8517 * config/nios2/elf.opt.urls: Likewise.
8518 * config/nios2/nios2.opt.urls: Likewise.
8519 * config/nvptx/nvptx-gen.opt.urls: Likewise.
8520 * config/nvptx/nvptx.opt.urls: Likewise.
8521 * config/openbsd.opt.urls: Likewise.
8522 * config/or1k/elf.opt.urls: Likewise.
8523 * config/or1k/or1k.opt.urls: Likewise.
8524 * config/pa/pa-hpux.opt.urls: Likewise.
8525 * config/pa/pa-hpux1010.opt.urls: Likewise.
8526 * config/pa/pa-hpux1111.opt.urls: Likewise.
8527 * config/pa/pa-hpux1131.opt.urls: Likewise.
8528 * config/pa/pa.opt.urls: Likewise.
8529 * config/pa/pa64-hpux.opt.urls: Likewise.
8530 * config/pdp11/pdp11.opt.urls: Likewise.
8531 * config/pru/pru.opt.urls: Likewise.
8532 * config/riscv/riscv.opt.urls: Likewise.
8533 * config/rl78/rl78.opt.urls: Likewise.
8534 * config/rpath.opt.urls: Likewise.
8535 * config/rs6000/476.opt.urls: Likewise.
8536 * config/rs6000/aix64.opt.urls: Likewise.
8537 * config/rs6000/darwin.opt.urls: Likewise.
8538 * config/rs6000/linux64.opt.urls: Likewise.
8539 * config/rs6000/rs6000-tables.opt.urls: Likewise.
8540 * config/rs6000/rs6000.opt.urls: Likewise.
8541 * config/rs6000/sysv4.opt.urls: Likewise.
8542 * config/rtems.opt.urls: Likewise.
8543 * config/rx/elf.opt.urls: Likewise.
8544 * config/rx/rx.opt.urls: Likewise.
8545 * config/s390/s390.opt.urls: Likewise.
8546 * config/s390/tpf.opt.urls: Likewise.
8547 * config/sh/sh.opt.urls: Likewise.
8548 * config/sh/superh.opt.urls: Likewise.
8549 * config/sol2.opt.urls: Likewise.
8550 * config/sparc/long-double-switch.opt.urls: Likewise.
8551 * config/sparc/sparc.opt.urls: Likewise.
8552 * config/stormy16/stormy16.opt.urls: Likewise.
8553 * config/v850/v850.opt.urls: Likewise.
8554 * config/vax/elf.opt.urls: Likewise.
8555 * config/vax/vax.opt.urls: Likewise.
8556 * config/visium/visium.opt.urls: Likewise.
8557 * config/vms/vms.opt.urls: Likewise.
8558 * config/vxworks-smp.opt.urls: Likewise.
8559 * config/vxworks.opt.urls: Likewise.
8560 * config/xtensa/elf.opt.urls: Likewise.
8561 * config/xtensa/uclinux.opt.urls: Likewise.
8562 * config/xtensa/xtensa.opt.urls: Likewise.
8563 * config/bfin/bfin.opt.urls: New file.
8565 2024-01-04 David Malcolm <dmalcolm@redhat.com>
8567 * Makefile.in (OPT_URLS_HTML_DEPS): New.
8568 (regenerate-opt-urls): New target.
8569 (regenerate-opt-urls-unit-test): New target.
8570 * doc/options.texi (Option properties): Add UrlSuffix and
8571 description of regenerate-opt-urls.py. Add LangUrlSuffix_*.
8572 * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
8573 reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
8574 and Makefile.in's OPT_URLS_HTML_DEPS.
8575 (Anatomy of a Target Back End): Add
8576 reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
8577 * regenerate-opt-urls.py: New file.
8579 2024-01-04 David Malcolm <dmalcolm@redhat.com>
8581 * diagnostic-format-sarif.cc
8582 (sarif_builder::make_logical_location_object): Convert to...
8583 (make_sarif_logical_location_object): ...this.
8584 (sarif_builder::set_any_logical_locs_arr): Update for above
8585 change.
8586 (sarif_builder::make_thread_flow_location_object): Call
8587 maybe_add_sarif_properties on each diagnostic_event.
8588 * diagnostic-format-sarif.h (class logical_location): New forward
8589 decl.
8590 (make_sarif_logical_location_object): New decl.
8591 * diagnostic-path.h (class sarif_object): New forward decl.
8592 (diagnostic_event::maybe_add_sarif_properties): New vfunc.
8594 2024-01-04 Kuan-Lin Chen <rufus@andestech.com>
8595 Patrick Lin <patrick@andestech.com>
8596 Rufus Chen <rufus@andestech.com>
8597 Monk Chiang <monk.chiang@sifive.com>
8599 * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
8600 with Nan-boxing value.
8601 * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
8603 2024-01-04 Roger Sayle <roger@nextmovesoftware.com>
8604 Jeff Law <jlaw@ventanamicro.com>
8606 PR rtl-optimization/104914
8607 * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
8608 a sign or zero extension is only required if the modified field
8609 overlaps the SUBREG's most significant bit. On MODE_REP_EXTENDED
8610 targets, don't refer to the temporarily incorrectly extended value
8611 using a SUBREG, but instead generate an explicit TRUNCATE rtx.
8613 2024-01-04 Pan Li <pan2.li@intel.com>
8615 Revert:
8616 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
8618 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
8620 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
8622 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
8624 2024-01-04 Kito Cheng <kito.cheng@sifive.com>
8626 * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
8627 offset of fcsr.
8629 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
8631 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
8632 (compute_nregs_for_mode): Refine LMUL.
8633 (max_number_of_live_regs): Ditto.
8634 (compute_estimated_lmul): Ditto.
8635 (has_unexpected_spills_p): Ditto.
8637 2024-01-04 Li Wei <liwei@loongson.cn>
8639 * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
8640 Remove useless forward declaration.
8641 (loongarch_is_even_extraction): Remove useless forward declaration.
8642 (loongarch_try_expand_lsx_vshuf_const): Removed.
8643 (loongarch_expand_vec_perm_const_1): Merged.
8644 (loongarch_is_double_duplicate): Removed.
8645 (loongarch_is_center_extraction): Ditto.
8646 (loongarch_is_reversing_permutation): Ditto.
8647 (loongarch_is_di_misalign_extract): Ditto.
8648 (loongarch_is_si_misalign_extract): Ditto.
8649 (loongarch_is_lasx_lowpart_extract): Ditto.
8650 (loongarch_is_op_reverse_perm): Ditto.
8651 (loongarch_is_single_op_perm): Ditto.
8652 (loongarch_is_divisible_perm): Ditto.
8653 (loongarch_is_triple_stride_extract): Ditto.
8654 (loongarch_expand_vec_perm_const_2): Merged.
8655 (loongarch_expand_vec_perm_const): New.
8656 (loongarch_vectorize_vec_perm_const): Adjust.
8658 2024-01-04 Sandra Loosemore <sandra@codesourcery.com>
8660 * omp-general.cc: Fix comment typos and misplaced/confusing
8661 comments. Delete redundant include of omp-general.h.
8663 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
8665 PR rtl-optimization/104914
8666 * config/mips/mips.md (insqisi_extended): New patterns.
8667 (inshisi_extended): Ditto.
8669 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
8671 * config/mips/mips.cc (mips_insn_cost): New function.
8673 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
8675 * config/mips/mips.md (perf_ratio): New attribute.
8677 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
8679 PR target/113206
8680 PR target/113209
8681 * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
8682 (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
8683 blocks belong to infinite loop.
8684 (pre_vsetvl::emit_vsetvl): Remove fake edges.
8685 * config/riscv/t-riscv: Add a new include file.
8687 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
8689 * config/riscv/vector.md: Fix indent.
8691 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
8693 * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
8694 OMP_CLAUSE__SIMDUID_.
8695 * tree.cc (omp_clause_num_ops): Update position of entry for
8696 OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
8697 (omp_clause_code_name): Likewise.
8699 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
8701 * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
8702 printing of FUNC_MAP/IND_FUNC_MAP labels.
8704 2024-01-03 Jakub Jelinek <jakub@redhat.com>
8706 * gcc.cc (process_command): Update copyright notice dates.
8707 * gcov-dump.cc (print_version): Ditto.
8708 * gcov.cc (print_version): Ditto.
8709 * gcov-tool.cc (print_version): Ditto.
8710 * gengtype.cc (create_file): Ditto.
8711 * doc/cpp.texi: Bump @copying's copyright year.
8712 * doc/cppinternals.texi: Ditto.
8713 * doc/gcc.texi: Ditto.
8714 * doc/gccint.texi: Ditto.
8715 * doc/gcov.texi: Ditto.
8716 * doc/install.texi: Ditto.
8717 * doc/invoke.texi: Ditto.
8719 2024-01-03 Xi Ruoyao <xry111@xry111.site>
8721 * config/loongarch/simd.md (fmax<mode>3): New define_insn.
8722 (fmin<mode>3): Likewise.
8723 (reduc_fmax_scal_<mode>3): New define_expand.
8724 (reduc_fmin_scal_<mode>3): Likewise.
8726 2024-01-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
8728 PR target/113112
8729 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
8730 (max_number_of_live_regs): Ditto.
8731 (has_unexpected_spills_p): Ditto.
8733 2024-01-02 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
8734 Jin Ma <jinma@linux.alibaba.com>
8735 Xianmiao Qu <cooper.qu@linux.alibaba.com>
8736 Christoph Müllner <christoph.muellner@vrull.eu>
8738 * config/riscv/vector.md:
8739 Use vector_length_operand for vsetvl patterns.
8741 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
8743 * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
8744 (expand_cond_len_op): Add simplification of dummy len and dummy mask.
8746 2024-01-02 Di Zhao <dizhao@os.amperecomputing.com>
8748 * config/aarch64/aarch64-tuning-flags.def
8749 (AARCH64_EXTRA_TUNING_OPTION): New tuning option
8750 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
8751 * config/aarch64/aarch64.cc
8752 (aarch64_override_options_internal): Set
8753 param_fully_pipelined_fma according to tuning option.
8754 * config/aarch64/tuning_models/ampere1.h: Add
8755 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
8756 * config/aarch64/tuning_models/ampere1a.h: Likewise.
8757 * config/aarch64/tuning_models/ampere1b.h: Likewise.
8759 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
8761 * config/riscv/vector-crypto.md: Modify copyright year.
8763 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
8765 * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
8767 2024-01-02 Lulu Cheng <chenglulu@loongson.cn>
8769 * config.in: Regenerate.
8770 * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
8771 * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
8772 Added TLS Le Relax support.
8773 (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
8774 * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
8775 * configure: Regenerate.
8776 * configure.ac: Check if binutils supports TLS le relax.
8778 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
8780 * config/riscv/iterators.md: Add rotate insn name.
8781 * config/riscv/riscv.md: Add new insns name for crypto vector.
8782 * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
8783 * config/riscv/vector.md: Add the corresponding attr for crypto vector.
8784 * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
8786 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
8788 PR target/113112
8789 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
8790 pointer type liveness count.
8791 \f
8792 Copyright (C) 2024 Free Software Foundation, Inc.
8794 Copying and distribution of this file, with or without modification,
8795 are permitted in any medium without royalty provided the copyright
8796 notice and this notice are preserved.