Daily bump.
[official-gcc.git] / gcc / config / sh / sh.c
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1 /* Output routines for GCC for Renesas / SuperH SH.
2 Copyright (C) 1993-2018 Free Software Foundation, Inc.
3 Contributed by Steve Chamberlain (sac@cygnus.com).
4 Improved by Jim Wilson (wilson@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
22 #include <sstream>
24 #define IN_TARGET_CODE 1
26 #include "config.h"
27 #define INCLUDE_VECTOR
28 #include "system.h"
29 #include "coretypes.h"
30 #include "backend.h"
31 #include "target.h"
32 #include "rtl.h"
33 #include "tree.h"
34 #include "gimple.h"
35 #include "cfghooks.h"
36 #include "df.h"
37 #include "memmodel.h"
38 #include "tm_p.h"
39 #include "stringpool.h"
40 #include "attribs.h"
41 #include "optabs.h"
42 #include "emit-rtl.h"
43 #include "recog.h"
44 #include "diagnostic-core.h"
45 #include "alias.h"
46 #include "fold-const.h"
47 #include "stor-layout.h"
48 #include "calls.h"
49 #include "varasm.h"
50 #include "flags.h"
51 #include "explow.h"
52 #include "expr.h"
53 #include "reload.h"
54 #include "output.h"
55 #include "insn-attr.h"
56 #include "dwarf2.h"
57 #include "langhooks.h"
58 #include "cfgrtl.h"
59 #include "intl.h"
60 #include "sched-int.h"
61 #include "gimplify.h"
62 #include "tm-constrs.h"
63 #include "opts.h"
64 #include "tree-pass.h"
65 #include "context.h"
66 #include "builtins.h"
67 #include "rtl-iter.h"
68 #include "regs.h"
70 /* This file should be included last. */
71 #include "target-def.h"
73 int code_for_indirect_jump_scratch = CODE_FOR_indirect_jump_scratch;
75 #define CONST_OK_FOR_ADD(size) CONST_OK_FOR_I08 (size)
76 #define GEN_MOV (*(gen_movsi))
77 #define GEN_ADD3 (*(gen_addsi3))
78 #define GEN_SUB3 (*(gen_subsi3))
80 /* Used to simplify the logic below. Find the attributes wherever
81 they may be. */
82 #define SH_ATTRIBUTES(decl) \
83 (TYPE_P (decl)) ? TYPE_ATTRIBUTES (decl) \
84 : DECL_ATTRIBUTES (decl) \
85 ? (DECL_ATTRIBUTES (decl)) \
86 : TYPE_ATTRIBUTES (TREE_TYPE (decl))
88 /* Set to true by expand_prologue() when the function is an
89 interrupt handler. */
90 bool current_function_interrupt;
92 tree sh_deferred_function_attributes;
93 tree *sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
95 /* Global variables for machine-dependent things. */
97 /* Which cpu are we scheduling for. */
98 enum processor_type sh_cpu;
100 /* Definitions used in ready queue reordering for first scheduling pass. */
102 /* Reg weights arrays for modes SFmode and SImode, indexed by insn LUID. */
103 static short *regmode_weight[2];
105 /* Total SFmode and SImode weights of scheduled insns. */
106 static int curr_regmode_pressure[2];
108 /* Number of r0 life regions. */
109 static int r0_life_regions;
111 /* If true, skip cycles for Q -> R movement. */
112 static int skip_cycles = 0;
114 /* Cached value of can_issue_more. This is cached in sh_variable_issue hook
115 and returned from sh_reorder2. */
116 static short cached_can_issue_more;
118 /* Unique number for UNSPEC_BBR pattern. */
119 static unsigned int unspec_bbr_uid = 1;
121 /* Provides the class number of the smallest class containing
122 reg number. */
123 enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER] =
125 R0_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
126 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
127 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
128 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
129 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
130 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
131 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
132 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
133 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
134 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
135 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
136 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
137 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
138 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
139 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
140 GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
141 FP0_REGS,FP_REGS, FP_REGS, FP_REGS,
142 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
143 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
144 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
145 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
146 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
147 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
148 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
149 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
150 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
151 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
152 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
153 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
154 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
155 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
156 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
157 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
158 TARGET_REGS, TARGET_REGS, TARGET_REGS, TARGET_REGS,
159 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
160 DF_REGS, DF_REGS, DF_REGS, DF_REGS,
161 NO_REGS, GENERAL_REGS, PR_REGS, T_REGS,
162 MAC_REGS, MAC_REGS, FPUL_REGS, FPSCR_REGS,
163 GENERAL_REGS, GENERAL_REGS,
166 char sh_register_names[FIRST_PSEUDO_REGISTER] \
167 [MAX_REGISTER_NAME_LENGTH + 1] = SH_REGISTER_NAMES_INITIALIZER;
169 char sh_additional_register_names[ADDREGNAMES_SIZE] \
170 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]
171 = SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER;
173 int assembler_dialect;
175 static void split_branches (rtx_insn *);
176 static int branch_dest (rtx);
177 static void print_slot (rtx_sequence *);
178 static rtx_code_label *add_constant (rtx, machine_mode, rtx);
179 static void dump_table (rtx_insn *, rtx_insn *);
180 static bool broken_move (rtx_insn *);
181 static bool mova_p (rtx_insn *);
182 static rtx_insn *find_barrier (int, rtx_insn *, rtx_insn *);
183 static bool noncall_uses_reg (rtx, rtx_insn *, rtx *);
184 static rtx_insn *gen_block_redirect (rtx_insn *, int, int);
185 static void sh_reorg (void);
186 static void sh_option_override (void);
187 static void sh_override_options_after_change (void);
188 static void output_stack_adjust (int, rtx, int, HARD_REG_SET *, bool);
189 static rtx_insn* emit_frame_insn (rtx);
190 static rtx push (int);
191 static void pop (int);
192 static void push_regs (HARD_REG_SET* mask, bool interrupt_handler);
193 static int calc_live_regs (HARD_REG_SET *);
194 static HOST_WIDE_INT rounded_frame_size (int);
195 static bool sh_frame_pointer_required (void);
196 static void sh_emit_mode_set (int, int, int, HARD_REG_SET);
197 static int sh_mode_needed (int, rtx_insn *);
198 static int sh_mode_after (int, int, rtx_insn *);
199 static int sh_mode_entry (int);
200 static int sh_mode_exit (int);
201 static int sh_mode_priority (int entity, int n);
203 static rtx mark_constant_pool_use (rtx);
204 static tree sh_handle_interrupt_handler_attribute (tree *, tree, tree,
205 int, bool *);
206 static tree sh_handle_resbank_handler_attribute (tree *, tree,
207 tree, int, bool *);
208 static tree sh2a_handle_function_vector_handler_attribute (tree *, tree,
209 tree, int, bool *);
210 static tree sh_handle_sp_switch_attribute (tree *, tree, tree, int, bool *);
211 static tree sh_handle_trap_exit_attribute (tree *, tree, tree, int, bool *);
212 static tree sh_handle_renesas_attribute (tree *, tree, tree, int, bool *);
213 static void sh_print_operand (FILE *, rtx, int);
214 static void sh_print_operand_address (FILE *, machine_mode, rtx);
215 static bool sh_print_operand_punct_valid_p (unsigned char code);
216 static bool sh_asm_output_addr_const_extra (FILE *file, rtx x);
217 static void sh_output_function_epilogue (FILE *);
218 static void sh_insert_attributes (tree, tree *);
219 static const char *sh_check_pch_target_flags (int);
220 static int sh_register_move_cost (machine_mode, reg_class_t, reg_class_t);
221 static int sh_adjust_cost (rtx_insn *, int, rtx_insn *, int, unsigned int);
222 static int sh_issue_rate (void);
223 static int sh_dfa_new_cycle (FILE *, int, rtx_insn *, int, int, int *sort_p);
224 static short find_set_regmode_weight (rtx, machine_mode);
225 static short find_insn_regmode_weight (rtx, machine_mode);
226 static void find_regmode_weight (basic_block, machine_mode);
227 static int find_r0_life_regions (basic_block);
228 static void sh_md_init_global (FILE *, int, int);
229 static void sh_md_finish_global (FILE *, int);
230 static int rank_for_reorder (const void *, const void *);
231 static void swap_reorder (rtx_insn **, int);
232 static void ready_reorder (rtx_insn **, int);
233 static bool high_pressure (machine_mode);
234 static int sh_reorder (FILE *, int, rtx_insn **, int *, int);
235 static int sh_reorder2 (FILE *, int, rtx_insn **, int *, int);
236 static void sh_md_init (FILE *, int, int);
237 static int sh_variable_issue (FILE *, int, rtx_insn *, int);
239 static bool sh_function_ok_for_sibcall (tree, tree);
241 static bool sh_can_follow_jump (const rtx_insn *, const rtx_insn *);
242 static bool sh_ms_bitfield_layout_p (const_tree);
244 static void sh_init_builtins (void);
245 static tree sh_builtin_decl (unsigned, bool);
246 static rtx sh_expand_builtin (tree, rtx, rtx, machine_mode, int);
247 static void sh_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
248 HOST_WIDE_INT, tree);
249 static void sh_file_start (void);
250 static bool sh_assemble_integer (rtx, unsigned int, int);
251 static bool flow_dependent_p (rtx, rtx);
252 static void flow_dependent_p_1 (rtx, const_rtx, void *);
253 static int shiftcosts (rtx);
254 static int and_xor_ior_costs (rtx, int);
255 static int addsubcosts (rtx);
256 static int multcosts (rtx);
257 static bool unspec_caller_rtx_p (rtx);
258 static bool sh_cannot_copy_insn_p (rtx_insn *);
259 static bool sh_cannot_force_const_mem_p (machine_mode, rtx);
260 static bool sh_rtx_costs (rtx, machine_mode, int, int, int *, bool);
261 static int sh_address_cost (rtx, machine_mode, addr_space_t, bool);
262 static int sh_pr_n_sets (void);
263 static rtx sh_allocate_initial_value (rtx);
264 static reg_class_t sh_preferred_reload_class (rtx, reg_class_t);
265 static reg_class_t sh_secondary_reload (bool, rtx, reg_class_t,
266 machine_mode,
267 struct secondary_reload_info *);
268 static bool sh_legitimate_address_p (machine_mode, rtx, bool);
269 static rtx sh_legitimize_address (rtx, rtx, machine_mode);
270 static rtx sh_delegitimize_address (rtx);
271 static bool sh_cannot_substitute_mem_equiv_p (rtx);
272 static bool sh_legitimize_address_displacement (rtx *, rtx *,
273 poly_int64, machine_mode);
274 static int scavenge_reg (HARD_REG_SET *s);
276 static rtx sh_struct_value_rtx (tree, int);
277 static rtx sh_function_value (const_tree, const_tree, bool);
278 static bool sh_function_value_regno_p (const unsigned int);
279 static rtx sh_libcall_value (machine_mode, const_rtx);
280 static bool sh_return_in_memory (const_tree, const_tree);
281 static rtx sh_builtin_saveregs (void);
282 static void sh_setup_incoming_varargs (cumulative_args_t, machine_mode,
283 tree, int *, int);
284 static bool sh_strict_argument_naming (cumulative_args_t);
285 static bool sh_pretend_outgoing_varargs_named (cumulative_args_t);
286 static void sh_atomic_assign_expand_fenv (tree *, tree *, tree *);
287 static tree sh_build_builtin_va_list (void);
288 static void sh_va_start (tree, rtx);
289 static tree sh_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
290 static bool sh_promote_prototypes (const_tree);
291 static machine_mode sh_promote_function_mode (const_tree type,
292 machine_mode,
293 int *punsignedp,
294 const_tree funtype,
295 int for_return);
296 static bool sh_pass_by_reference (cumulative_args_t, machine_mode,
297 const_tree, bool);
298 static bool sh_callee_copies (cumulative_args_t, machine_mode,
299 const_tree, bool);
300 static int sh_arg_partial_bytes (cumulative_args_t, machine_mode,
301 tree, bool);
302 static void sh_function_arg_advance (cumulative_args_t, machine_mode,
303 const_tree, bool);
304 static rtx sh_function_arg (cumulative_args_t, machine_mode,
305 const_tree, bool);
306 static int sh_dwarf_calling_convention (const_tree);
307 static void sh_encode_section_info (tree, rtx, int);
308 static bool sh2a_function_vector_p (tree);
309 static void sh_trampoline_init (rtx, tree, rtx);
310 static rtx sh_trampoline_adjust_address (rtx);
311 static void sh_conditional_register_usage (void);
312 static bool sh_legitimate_constant_p (machine_mode, rtx);
313 static int mov_insn_size (machine_mode, bool);
314 static int mov_insn_alignment_mask (machine_mode, bool);
315 static bool sh_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT,
316 unsigned int,
317 enum by_pieces_operation,
318 bool);
319 static bool sequence_insn_p (rtx_insn *);
320 static void sh_canonicalize_comparison (int *, rtx *, rtx *, bool);
321 static void sh_canonicalize_comparison (enum rtx_code&, rtx&, rtx&,
322 machine_mode, bool);
323 static bool sh_legitimate_combined_insn (rtx_insn* insn);
325 static bool sh_fixed_condition_code_regs (unsigned int* p1, unsigned int* p2);
327 static void sh_init_sync_libfuncs (void) ATTRIBUTE_UNUSED;
328 static unsigned int sh_hard_regno_nregs (unsigned int, machine_mode);
329 static bool sh_hard_regno_mode_ok (unsigned int, machine_mode);
330 static bool sh_modes_tieable_p (machine_mode, machine_mode);
331 static bool sh_can_change_mode_class (machine_mode, machine_mode, reg_class_t);
333 static const struct attribute_spec sh_attribute_table[] =
335 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
336 affects_type_identity, handler, exclude } */
337 { "interrupt_handler", 0, 0, true, false, false, false,
338 sh_handle_interrupt_handler_attribute, NULL },
339 { "sp_switch", 1, 1, true, false, false, false,
340 sh_handle_sp_switch_attribute, NULL },
341 { "trap_exit", 1, 1, true, false, false, false,
342 sh_handle_trap_exit_attribute, NULL },
343 { "renesas", 0, 0, false, true, false, false,
344 sh_handle_renesas_attribute, NULL },
345 { "trapa_handler", 0, 0, true, false, false, false,
346 sh_handle_interrupt_handler_attribute, NULL },
347 { "nosave_low_regs", 0, 0, true, false, false, false,
348 sh_handle_interrupt_handler_attribute, NULL },
349 { "resbank", 0, 0, true, false, false, false,
350 sh_handle_resbank_handler_attribute, NULL },
351 { "function_vector", 1, 1, true, false, false, false,
352 sh2a_handle_function_vector_handler_attribute, NULL },
353 { NULL, 0, 0, false, false, false, false, NULL, NULL }
356 /* Initialize the GCC target structure. */
357 #undef TARGET_ATTRIBUTE_TABLE
358 #define TARGET_ATTRIBUTE_TABLE sh_attribute_table
360 /* The next two are used for debug info when compiling with -gdwarf. */
361 #undef TARGET_ASM_UNALIGNED_HI_OP
362 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uaword\t"
363 #undef TARGET_ASM_UNALIGNED_SI_OP
364 #define TARGET_ASM_UNALIGNED_SI_OP "\t.ualong\t"
366 #undef TARGET_OPTION_OVERRIDE
367 #define TARGET_OPTION_OVERRIDE sh_option_override
369 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
370 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
371 sh_override_options_after_change
373 #undef TARGET_PRINT_OPERAND
374 #define TARGET_PRINT_OPERAND sh_print_operand
375 #undef TARGET_PRINT_OPERAND_ADDRESS
376 #define TARGET_PRINT_OPERAND_ADDRESS sh_print_operand_address
377 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
378 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sh_print_operand_punct_valid_p
379 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
380 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA sh_asm_output_addr_const_extra
382 #undef TARGET_ASM_FUNCTION_EPILOGUE
383 #define TARGET_ASM_FUNCTION_EPILOGUE sh_output_function_epilogue
385 #undef TARGET_ASM_OUTPUT_MI_THUNK
386 #define TARGET_ASM_OUTPUT_MI_THUNK sh_output_mi_thunk
388 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
389 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
390 hook_bool_const_tree_hwi_hwi_const_tree_true
392 #undef TARGET_ASM_FILE_START
393 #define TARGET_ASM_FILE_START sh_file_start
394 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
395 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
397 #undef TARGET_ASM_INTEGER
398 #define TARGET_ASM_INTEGER sh_assemble_integer
400 #undef TARGET_REGISTER_MOVE_COST
401 #define TARGET_REGISTER_MOVE_COST sh_register_move_cost
403 #undef TARGET_INSERT_ATTRIBUTES
404 #define TARGET_INSERT_ATTRIBUTES sh_insert_attributes
406 #undef TARGET_SCHED_ADJUST_COST
407 #define TARGET_SCHED_ADJUST_COST sh_adjust_cost
409 #undef TARGET_SCHED_ISSUE_RATE
410 #define TARGET_SCHED_ISSUE_RATE sh_issue_rate
412 /* The next 5 hooks have been implemented for reenabling sched1. With the
413 help of these macros we are limiting the movement of insns in sched1 to
414 reduce the register pressure. The overall idea is to keep count of SImode
415 and SFmode regs required by already scheduled insns. When these counts
416 cross some threshold values; give priority to insns that free registers.
417 The insn that frees registers is most likely to be the insn with lowest
418 LUID (original insn order); but such an insn might be there in the stalled
419 queue (Q) instead of the ready queue (R). To solve this, we skip cycles
420 up to a max of 8 cycles so that such insns may move from Q -> R.
422 The description of the hooks are as below:
424 TARGET_SCHED_INIT_GLOBAL: Added a new target hook in the generic
425 scheduler; it is called inside the sched_init function just after
426 find_insn_reg_weights function call. It is used to calculate the SImode
427 and SFmode weights of insns of basic blocks; much similar to what
428 find_insn_reg_weights does.
429 TARGET_SCHED_FINISH_GLOBAL: Corresponding cleanup hook.
431 TARGET_SCHED_DFA_NEW_CYCLE: Skip cycles if high register pressure is
432 indicated by TARGET_SCHED_REORDER2; doing this may move insns from
433 (Q)->(R).
435 TARGET_SCHED_REORDER: If the register pressure for SImode or SFmode is
436 high; reorder the ready queue so that the insn with lowest LUID will be
437 issued next.
439 TARGET_SCHED_REORDER2: If the register pressure is high, indicate to
440 TARGET_SCHED_DFA_NEW_CYCLE to skip cycles.
442 TARGET_SCHED_VARIABLE_ISSUE: Cache the value of can_issue_more so that it
443 can be returned from TARGET_SCHED_REORDER2.
445 TARGET_SCHED_INIT: Reset the register pressure counting variables. */
447 #undef TARGET_SCHED_DFA_NEW_CYCLE
448 #define TARGET_SCHED_DFA_NEW_CYCLE sh_dfa_new_cycle
450 #undef TARGET_SCHED_INIT_GLOBAL
451 #define TARGET_SCHED_INIT_GLOBAL sh_md_init_global
453 #undef TARGET_SCHED_FINISH_GLOBAL
454 #define TARGET_SCHED_FINISH_GLOBAL sh_md_finish_global
456 #undef TARGET_SCHED_VARIABLE_ISSUE
457 #define TARGET_SCHED_VARIABLE_ISSUE sh_variable_issue
459 #undef TARGET_SCHED_REORDER
460 #define TARGET_SCHED_REORDER sh_reorder
462 #undef TARGET_SCHED_REORDER2
463 #define TARGET_SCHED_REORDER2 sh_reorder2
465 #undef TARGET_SCHED_INIT
466 #define TARGET_SCHED_INIT sh_md_init
468 #undef TARGET_DELEGITIMIZE_ADDRESS
469 #define TARGET_DELEGITIMIZE_ADDRESS sh_delegitimize_address
471 #undef TARGET_LEGITIMIZE_ADDRESS
472 #define TARGET_LEGITIMIZE_ADDRESS sh_legitimize_address
474 #undef TARGET_CAN_FOLLOW_JUMP
475 #define TARGET_CAN_FOLLOW_JUMP sh_can_follow_jump
477 #undef TARGET_MS_BITFIELD_LAYOUT_P
478 #define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
480 #undef TARGET_INIT_BUILTINS
481 #define TARGET_INIT_BUILTINS sh_init_builtins
482 #undef TARGET_BUILTIN_DECL
483 #define TARGET_BUILTIN_DECL sh_builtin_decl
484 #undef TARGET_EXPAND_BUILTIN
485 #define TARGET_EXPAND_BUILTIN sh_expand_builtin
487 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
488 #define TARGET_FUNCTION_OK_FOR_SIBCALL sh_function_ok_for_sibcall
490 #undef TARGET_CANNOT_COPY_INSN_P
491 #define TARGET_CANNOT_COPY_INSN_P sh_cannot_copy_insn_p
492 #undef TARGET_RTX_COSTS
493 #define TARGET_RTX_COSTS sh_rtx_costs
494 #undef TARGET_ADDRESS_COST
495 #define TARGET_ADDRESS_COST sh_address_cost
496 #undef TARGET_ALLOCATE_INITIAL_VALUE
497 #define TARGET_ALLOCATE_INITIAL_VALUE sh_allocate_initial_value
499 #undef TARGET_MACHINE_DEPENDENT_REORG
500 #define TARGET_MACHINE_DEPENDENT_REORG sh_reorg
502 #undef TARGET_DWARF_REGISTER_SPAN
503 #define TARGET_DWARF_REGISTER_SPAN sh_dwarf_register_span
505 #ifdef HAVE_AS_TLS
506 #undef TARGET_HAVE_TLS
507 #define TARGET_HAVE_TLS true
508 #endif
510 #undef TARGET_PROMOTE_PROTOTYPES
511 #define TARGET_PROMOTE_PROTOTYPES sh_promote_prototypes
512 #undef TARGET_PROMOTE_FUNCTION_MODE
513 #define TARGET_PROMOTE_FUNCTION_MODE sh_promote_function_mode
515 #undef TARGET_FUNCTION_VALUE
516 #define TARGET_FUNCTION_VALUE sh_function_value
517 #undef TARGET_FUNCTION_VALUE_REGNO_P
518 #define TARGET_FUNCTION_VALUE_REGNO_P sh_function_value_regno_p
519 #undef TARGET_LIBCALL_VALUE
520 #define TARGET_LIBCALL_VALUE sh_libcall_value
521 #undef TARGET_STRUCT_VALUE_RTX
522 #define TARGET_STRUCT_VALUE_RTX sh_struct_value_rtx
523 #undef TARGET_RETURN_IN_MEMORY
524 #define TARGET_RETURN_IN_MEMORY sh_return_in_memory
526 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
527 #define TARGET_EXPAND_BUILTIN_SAVEREGS sh_builtin_saveregs
528 #undef TARGET_SETUP_INCOMING_VARARGS
529 #define TARGET_SETUP_INCOMING_VARARGS sh_setup_incoming_varargs
530 #undef TARGET_STRICT_ARGUMENT_NAMING
531 #define TARGET_STRICT_ARGUMENT_NAMING sh_strict_argument_naming
532 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
533 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED sh_pretend_outgoing_varargs_named
534 #undef TARGET_MUST_PASS_IN_STACK
535 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
536 #undef TARGET_PASS_BY_REFERENCE
537 #define TARGET_PASS_BY_REFERENCE sh_pass_by_reference
538 #undef TARGET_CALLEE_COPIES
539 #define TARGET_CALLEE_COPIES sh_callee_copies
540 #undef TARGET_ARG_PARTIAL_BYTES
541 #define TARGET_ARG_PARTIAL_BYTES sh_arg_partial_bytes
542 #undef TARGET_FUNCTION_ARG
543 #define TARGET_FUNCTION_ARG sh_function_arg
544 #undef TARGET_FUNCTION_ARG_ADVANCE
545 #define TARGET_FUNCTION_ARG_ADVANCE sh_function_arg_advance
547 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
548 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV sh_atomic_assign_expand_fenv
550 #undef TARGET_BUILD_BUILTIN_VA_LIST
551 #define TARGET_BUILD_BUILTIN_VA_LIST sh_build_builtin_va_list
552 #undef TARGET_EXPAND_BUILTIN_VA_START
553 #define TARGET_EXPAND_BUILTIN_VA_START sh_va_start
554 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
555 #define TARGET_GIMPLIFY_VA_ARG_EXPR sh_gimplify_va_arg_expr
557 #undef TARGET_VECTOR_MODE_SUPPORTED_P
558 #define TARGET_VECTOR_MODE_SUPPORTED_P sh_vector_mode_supported_p
560 #undef TARGET_CHECK_PCH_TARGET_FLAGS
561 #define TARGET_CHECK_PCH_TARGET_FLAGS sh_check_pch_target_flags
563 #undef TARGET_DWARF_CALLING_CONVENTION
564 #define TARGET_DWARF_CALLING_CONVENTION sh_dwarf_calling_convention
566 #undef TARGET_FRAME_POINTER_REQUIRED
567 #define TARGET_FRAME_POINTER_REQUIRED sh_frame_pointer_required
569 #undef TARGET_MODE_EMIT
570 #define TARGET_MODE_EMIT sh_emit_mode_set
572 #undef TARGET_MODE_NEEDED
573 #define TARGET_MODE_NEEDED sh_mode_needed
575 #undef TARGET_MODE_AFTER
576 #define TARGET_MODE_AFTER sh_mode_after
578 #undef TARGET_MODE_ENTRY
579 #define TARGET_MODE_ENTRY sh_mode_entry
581 #undef TARGET_MODE_EXIT
582 #define TARGET_MODE_EXIT sh_mode_exit
584 #undef TARGET_MODE_PRIORITY
585 #define TARGET_MODE_PRIORITY sh_mode_priority
587 /* Return regmode weight for insn. */
588 #define INSN_REGMODE_WEIGHT(INSN, MODE)\
589 regmode_weight[((MODE) == SImode) ? 0 : 1][INSN_UID (INSN)]
591 /* Return current register pressure for regmode. */
592 #define CURR_REGMODE_PRESSURE(MODE)\
593 curr_regmode_pressure[((MODE) == SImode) ? 0 : 1]
595 #undef TARGET_ENCODE_SECTION_INFO
596 #define TARGET_ENCODE_SECTION_INFO sh_encode_section_info
598 #undef TARGET_LRA_P
599 #define TARGET_LRA_P sh_lra_p
601 #undef TARGET_SECONDARY_RELOAD
602 #define TARGET_SECONDARY_RELOAD sh_secondary_reload
604 #undef TARGET_PREFERRED_RELOAD_CLASS
605 #define TARGET_PREFERRED_RELOAD_CLASS sh_preferred_reload_class
607 #undef TARGET_CONDITIONAL_REGISTER_USAGE
608 #define TARGET_CONDITIONAL_REGISTER_USAGE sh_conditional_register_usage
610 #undef TARGET_LEGITIMATE_ADDRESS_P
611 #define TARGET_LEGITIMATE_ADDRESS_P sh_legitimate_address_p
613 #undef TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P
614 #define TARGET_CANNOT_SUBSTITUTE_MEM_EQUIV_P sh_cannot_substitute_mem_equiv_p
616 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
617 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
618 sh_legitimize_address_displacement
620 #undef TARGET_TRAMPOLINE_INIT
621 #define TARGET_TRAMPOLINE_INIT sh_trampoline_init
622 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
623 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS sh_trampoline_adjust_address
625 #undef TARGET_LEGITIMATE_CONSTANT_P
626 #define TARGET_LEGITIMATE_CONSTANT_P sh_legitimate_constant_p
628 #undef TARGET_CANONICALIZE_COMPARISON
629 #define TARGET_CANONICALIZE_COMPARISON sh_canonicalize_comparison
631 #undef TARGET_LEGITIMATE_COMBINED_INSN
632 #define TARGET_LEGITIMATE_COMBINED_INSN sh_legitimate_combined_insn
634 #undef TARGET_FIXED_CONDITION_CODE_REGS
635 #define TARGET_FIXED_CONDITION_CODE_REGS sh_fixed_condition_code_regs
637 #undef TARGET_USE_BY_PIECES_INFRASTRUCTURE_P
638 #define TARGET_USE_BY_PIECES_INFRASTRUCTURE_P \
639 sh_use_by_pieces_infrastructure_p
641 /* Machine-specific symbol_ref flags. */
642 #define SYMBOL_FLAG_FUNCVEC_FUNCTION (SYMBOL_FLAG_MACH_DEP << 0)
644 /* The tas.b instruction sets the 7th bit in the byte, i.e. 0x80. This value
645 is used by optabs.c atomic op expansion code as well as in sync.md. */
646 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL
647 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0x80
649 #undef TARGET_CANNOT_FORCE_CONST_MEM
650 #define TARGET_CANNOT_FORCE_CONST_MEM sh_cannot_force_const_mem_p
652 #undef TARGET_HARD_REGNO_NREGS
653 #define TARGET_HARD_REGNO_NREGS sh_hard_regno_nregs
654 #undef TARGET_HARD_REGNO_MODE_OK
655 #define TARGET_HARD_REGNO_MODE_OK sh_hard_regno_mode_ok
657 #undef TARGET_MODES_TIEABLE_P
658 #define TARGET_MODES_TIEABLE_P sh_modes_tieable_p
660 #undef TARGET_CAN_CHANGE_MODE_CLASS
661 #define TARGET_CAN_CHANGE_MODE_CLASS sh_can_change_mode_class
663 #undef TARGET_CONSTANT_ALIGNMENT
664 #define TARGET_CONSTANT_ALIGNMENT constant_alignment_word_strings
666 struct gcc_target targetm = TARGET_INITIALIZER;
669 /* Information on the currently selected atomic model.
670 This is initialized in sh_option_override. */
671 static sh_atomic_model selected_atomic_model_;
673 const sh_atomic_model&
674 selected_atomic_model (void)
676 return selected_atomic_model_;
679 static sh_atomic_model
680 parse_validate_atomic_model_option (const char* str)
682 const char* model_names[sh_atomic_model::num_models];
683 model_names[sh_atomic_model::none] = "none";
684 model_names[sh_atomic_model::soft_gusa] = "soft-gusa";
685 model_names[sh_atomic_model::hard_llcs] = "hard-llcs";
686 model_names[sh_atomic_model::soft_tcb] = "soft-tcb";
687 model_names[sh_atomic_model::soft_imask] = "soft-imask";
689 const char* model_cdef_names[sh_atomic_model::num_models];
690 model_cdef_names[sh_atomic_model::none] = "NONE";
691 model_cdef_names[sh_atomic_model::soft_gusa] = "SOFT_GUSA";
692 model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS";
693 model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB";
694 model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK";
696 sh_atomic_model ret;
697 ret.type = sh_atomic_model::none;
698 ret.name = model_names[sh_atomic_model::none];
699 ret.cdef_name = model_cdef_names[sh_atomic_model::none];
700 ret.strict = false;
701 ret.tcb_gbr_offset = -1;
703 /* Handle empty string as 'none'. */
704 if (str == NULL || *str == '\0')
705 return ret;
707 #define err_ret(...) do { error (__VA_ARGS__); return ret; } while (0)
709 std::vector<std::string> tokens;
710 for (std::stringstream ss (str); ss.good (); )
712 tokens.push_back (std::string ());
713 std::getline (ss, tokens.back (), ',');
716 if (tokens.empty ())
717 err_ret ("invalid atomic model option");
719 /* The first token must be the atomic model name. */
721 for (size_t i = 0; i < sh_atomic_model::num_models; ++i)
722 if (tokens.front () == model_names[i])
724 ret.type = (sh_atomic_model::enum_type)i;
725 ret.name = model_names[i];
726 ret.cdef_name = model_cdef_names[i];
727 goto got_mode_name;
730 err_ret ("invalid atomic model name \"%s\"", tokens.front ().c_str ());
731 got_mode_name:;
734 /* Go through the remaining tokens. */
735 for (size_t i = 1; i < tokens.size (); ++i)
737 if (tokens[i] == "strict")
738 ret.strict = true;
739 else if (tokens[i].find ("gbr-offset=") == 0)
741 std::string offset_str = tokens[i].substr (strlen ("gbr-offset="));
742 ret.tcb_gbr_offset = integral_argument (offset_str.c_str ());
743 if (offset_str.empty () || ret.tcb_gbr_offset == -1)
744 err_ret ("could not parse gbr-offset value \"%s\" in atomic model "
745 "option", offset_str.c_str ());
747 else
748 err_ret ("unknown parameter \"%s\" in atomic model option",
749 tokens[i].c_str ());
752 /* Check that the selection makes sense. */
753 if (ret.type == sh_atomic_model::soft_gusa && !TARGET_SH3)
754 err_ret ("atomic model %s is only available on SH3 and SH4 targets",
755 ret.name);
757 if (ret.type == sh_atomic_model::hard_llcs && !TARGET_SH4A)
758 err_ret ("atomic model %s is only available on SH4A targets", ret.name);
760 if (ret.type == sh_atomic_model::soft_tcb && ret.tcb_gbr_offset == -1)
761 err_ret ("atomic model %s requires gbr-offset parameter", ret.name);
763 if (ret.type == sh_atomic_model::soft_tcb
764 && (ret.tcb_gbr_offset < 0 || ret.tcb_gbr_offset > 1020
765 || (ret.tcb_gbr_offset & 3) != 0))
766 err_ret ("invalid gbr-offset value \"%d\" for atomic model %s; it must be "
767 "a multiple of 4 in the range 0-1020", ret.tcb_gbr_offset,
768 ret.name);
770 if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE)
771 err_ret ("cannot use atomic model %s in user mode", ret.name);
773 return ret;
775 #undef err_ret
778 /* Register SH specific RTL passes. */
779 extern opt_pass* make_pass_sh_treg_combine (gcc::context* ctx, bool split_insns,
780 const char* name);
781 extern opt_pass* make_pass_sh_optimize_sett_clrt (gcc::context* ctx,
782 const char* name);
783 static void
784 register_sh_passes (void)
786 /* Running the sh_treg_combine pass after ce1 generates better code when
787 comparisons are combined and reg-reg moves are introduced, because
788 reg-reg moves will be eliminated afterwards. However, there are quite
789 some cases where combine will be unable to fold comparison related insns,
790 thus for now don't do it.
791 register_pass (make_pass_sh_treg_combine (g, false, "sh_treg_combine1"),
792 PASS_POS_INSERT_AFTER, "ce1", 1);
795 /* Run sh_treg_combine pass after combine but before register allocation. */
796 register_pass (make_pass_sh_treg_combine (g, true, "sh_treg_combine2"),
797 PASS_POS_INSERT_AFTER, "split1", 1);
799 /* Run sh_treg_combine pass after register allocation and basic block
800 reordering as this sometimes creates new opportunities. */
801 register_pass (make_pass_sh_treg_combine (g, true, "sh_treg_combine3"),
802 PASS_POS_INSERT_AFTER, "split4", 1);
804 /* Optimize sett and clrt insns, by e.g. removing them if the T bit value
805 is known after a conditional branch.
806 This must be done after basic blocks and branch conditions have
807 stabilized and won't be changed by further passes. */
808 register_pass (make_pass_sh_optimize_sett_clrt (g, "sh_optimize_sett_clrt"),
809 PASS_POS_INSERT_BEFORE, "sched2", 1);
812 /* Implement TARGET_OPTION_OVERRIDE macro. Validate and override
813 various options, and do some machine dependent initialization. */
814 static void
815 sh_option_override (void)
817 int regno;
819 SUBTARGET_OVERRIDE_OPTIONS;
821 sh_cpu = PROCESSOR_SH1;
822 assembler_dialect = 0;
823 if (TARGET_SH2)
824 sh_cpu = PROCESSOR_SH2;
825 if (TARGET_SH2E)
826 sh_cpu = PROCESSOR_SH2E;
827 if (TARGET_SH2A)
828 sh_cpu = PROCESSOR_SH2A;
829 if (TARGET_SH3)
830 sh_cpu = PROCESSOR_SH3;
831 if (TARGET_SH3E)
832 sh_cpu = PROCESSOR_SH3E;
833 if (TARGET_SH4)
835 assembler_dialect = 1;
836 sh_cpu = PROCESSOR_SH4;
838 if (TARGET_SH4A)
840 assembler_dialect = 1;
841 sh_cpu = PROCESSOR_SH4A;
844 /* User/priviledged mode is supported only on SH3* and SH4*.
845 Disable it for everything else. */
846 if (!TARGET_SH3 && TARGET_USERMODE)
847 TARGET_USERMODE = false;
849 if (! strcmp (sh_div_str, "call-div1"))
850 sh_div_strategy = SH_DIV_CALL_DIV1;
851 else if (! strcmp (sh_div_str, "call-fp") && TARGET_FPU_ANY)
852 sh_div_strategy = SH_DIV_CALL_FP;
853 else if (! strcmp (sh_div_str, "call-table") && TARGET_DYNSHIFT)
854 sh_div_strategy = SH_DIV_CALL_TABLE;
855 else
857 /* Pick one that makes most sense for the target in general.
858 It is not much good to use different functions depending on -Os,
859 since then we'll end up with two different functions when some of
860 the code is compiled for size, and some for speed. */
862 /* SH4 tends to emphasize speed. */
863 if (TARGET_HARD_SH4)
864 sh_div_strategy = SH_DIV_CALL_TABLE;
865 /* These have their own way of doing things. */
866 else if (TARGET_SH2A)
867 sh_div_strategy = SH_DIV_INTRINSIC;
868 /* SH1 .. SH3 cores often go into small-footprint systems, so
869 default to the smallest implementation available. */
870 else
871 sh_div_strategy = SH_DIV_CALL_DIV1;
874 if (sh_divsi3_libfunc[0])
875 ; /* User supplied - leave it alone. */
876 else if (TARGET_DIVIDE_CALL_FP)
877 sh_divsi3_libfunc = "__sdivsi3_i4";
878 else if (TARGET_DIVIDE_CALL_TABLE)
879 sh_divsi3_libfunc = "__sdivsi3_i4i";
880 else
881 sh_divsi3_libfunc = "__sdivsi3";
883 if (sh_branch_cost == -1)
885 /* The SH1 does not have delay slots, hence we get a pipeline stall
886 at every branch. The SH4 is superscalar, so the single delay slot
887 is not sufficient to keep both pipelines filled.
888 In any case, set the default branch cost to '2', as it results in
889 slightly overall smaller code and also enables some if conversions
890 that are required for matching special T bit related insns. */
891 sh_branch_cost = 2;
894 /* Set -mzdcbranch for SH4 / SH4A if not otherwise specified by the user. */
895 if (! global_options_set.x_TARGET_ZDCBRANCH && TARGET_HARD_SH4)
896 TARGET_ZDCBRANCH = 1;
898 /* FDPIC code is a special form of PIC, and the vast majority of code
899 generation constraints that apply to PIC also apply to FDPIC, so we
900 set flag_pic to avoid the need to check TARGET_FDPIC everywhere
901 flag_pic is checked. */
902 if (TARGET_FDPIC && !flag_pic)
903 flag_pic = 2;
905 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
906 if (! VALID_REGISTER_P (regno))
907 sh_register_names[regno][0] = '\0';
909 for (regno = 0; regno < ADDREGNAMES_SIZE; regno++)
910 if (! VALID_REGISTER_P (ADDREGNAMES_REGNO (regno)))
911 sh_additional_register_names[regno][0] = '\0';
913 if (flag_pic && ! TARGET_PREFERGOT)
914 flag_no_function_cse = 1;
916 if (targetm.small_register_classes_for_mode_p (VOIDmode))
918 /* Never run scheduling before reload, since that can
919 break global alloc, and generates slower code anyway due
920 to the pressure on R0. */
921 /* Enable sched1 for SH4 if the user explicitly requests.
922 When sched1 is enabled, the ready queue will be reordered by
923 the target hooks if pressure is high. We can not do this for
924 PIC, SH3 and lower as they give spill failures for R0. */
925 if (!TARGET_HARD_SH4 || flag_pic)
926 flag_schedule_insns = 0;
927 /* ??? Current exception handling places basic block boundaries
928 after call_insns. It causes the high pressure on R0 and gives
929 spill failures for R0 in reload. See PR 22553 and the thread
930 on gcc-patches
931 <http://gcc.gnu.org/ml/gcc-patches/2005-10/msg00816.html>. */
932 else if (flag_exceptions)
934 if (flag_schedule_insns && global_options_set.x_flag_schedule_insns)
935 warning (0, "ignoring -fschedule-insns because of exception "
936 "handling bug");
937 flag_schedule_insns = 0;
939 else if (flag_schedule_insns
940 && !global_options_set.x_flag_schedule_insns)
941 flag_schedule_insns = 0;
944 /* Unwind info is not correct around the CFG unless either a frame
945 pointer is present or M_A_O_A is set. Fixing this requires rewriting
946 unwind info generation to be aware of the CFG and propagating states
947 around edges. */
948 if ((flag_unwind_tables || flag_asynchronous_unwind_tables
949 || flag_exceptions || flag_non_call_exceptions)
950 && flag_omit_frame_pointer && !TARGET_ACCUMULATE_OUTGOING_ARGS)
952 warning (0, "unwind tables currently require either a frame pointer "
953 "or -maccumulate-outgoing-args for correctness");
954 TARGET_ACCUMULATE_OUTGOING_ARGS = 1;
957 if (flag_unsafe_math_optimizations)
959 /* Enable fsca insn for SH4A if not otherwise specified by the user. */
960 if (global_options_set.x_TARGET_FSCA == 0 && TARGET_SH4A_FP)
961 TARGET_FSCA = 1;
963 /* Enable fsrra insn for SH4A if not otherwise specified by the user. */
964 if (global_options_set.x_TARGET_FSRRA == 0 && TARGET_SH4A_FP)
965 TARGET_FSRRA = 1;
968 /* Allow fsrra insn only if -funsafe-math-optimizations and
969 -ffinite-math-only is enabled. */
970 TARGET_FSRRA = TARGET_FSRRA
971 && flag_unsafe_math_optimizations
972 && flag_finite_math_only;
974 /* If the -mieee option was not explicitly set by the user, turn it on
975 unless -ffinite-math-only was specified. See also PR 33135. */
976 if (! global_options_set.x_TARGET_IEEE)
977 TARGET_IEEE = ! flag_finite_math_only;
979 if (sh_fixed_range_str)
980 sh_fix_range (sh_fixed_range_str);
982 /* This target defaults to strict volatile bitfields. */
983 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2))
984 flag_strict_volatile_bitfields = 1;
986 sh_override_options_after_change ();
988 /* Parse atomic model option and make sure it is valid for the current
989 target CPU. */
990 selected_atomic_model_
991 = parse_validate_atomic_model_option (sh_atomic_model_str);
993 register_sh_passes ();
996 /* Implement targetm.override_options_after_change. */
998 static void
999 sh_override_options_after_change (void)
1001 /* Adjust loop, jump and function alignment values (in bytes), if those
1002 were not specified by the user using -falign-loops, -falign-jumps
1003 and -falign-functions options.
1004 32 bit alignment is better for speed, because instructions can be
1005 fetched as a pair from a longword boundary. For size use 16 bit
1006 alignment to get more compact code.
1007 Aligning all jumps increases the code size, even if it might
1008 result in slightly faster code. Thus, it is set to the smallest
1009 alignment possible if not specified by the user. */
1010 if (align_loops == 0)
1011 align_loops = optimize_size ? 2 : 4;
1013 if (align_jumps == 0)
1014 align_jumps = 2;
1015 else if (align_jumps < 2)
1016 align_jumps = 2;
1018 if (align_functions == 0)
1019 align_functions = optimize_size ? 2 : 4;
1021 /* The linker relaxation code breaks when a function contains
1022 alignments that are larger than that at the start of a
1023 compilation unit. */
1024 if (TARGET_RELAX)
1026 int min_align = align_loops > align_jumps ? align_loops : align_jumps;
1028 /* Also take possible .long constants / mova tables into account. */
1029 if (min_align < 4)
1030 min_align = 4;
1031 if (align_functions < min_align)
1032 align_functions = min_align;
1036 /* Print the operand address in x to the stream. */
1037 static void
1038 sh_print_operand_address (FILE *stream, machine_mode /*mode*/, rtx x)
1040 switch (GET_CODE (x))
1042 case REG:
1043 case SUBREG:
1044 fprintf (stream, "@%s", reg_names[true_regnum (x)]);
1045 break;
1047 case PLUS:
1049 rtx base = XEXP (x, 0);
1050 rtx index = XEXP (x, 1);
1052 switch (GET_CODE (index))
1054 case CONST_INT:
1055 fprintf (stream, "@(%d,%s)", (int) INTVAL (index),
1056 reg_names[true_regnum (base)]);
1057 break;
1059 case REG:
1060 case SUBREG:
1062 int base_num = true_regnum (base);
1063 int index_num = true_regnum (index);
1065 /* If base or index is R0, make sure that it comes first.
1066 Usually one of them will be R0, but the order might be wrong.
1067 If neither base nor index are R0 it's an error and we just
1068 pass it on to the assembler. This avoids silent wrong code
1069 bugs. */
1070 if (base_num == 0 && index_num != 0)
1071 std::swap (base_num, index_num);
1073 fprintf (stream, "@(%s,%s)", reg_names[index_num],
1074 reg_names[base_num]);
1075 break;
1078 default:
1079 gcc_unreachable ();
1082 break;
1084 case PRE_DEC:
1085 fprintf (stream, "@-%s", reg_names[true_regnum (XEXP (x, 0))]);
1086 break;
1088 case POST_INC:
1089 fprintf (stream, "@%s+", reg_names[true_regnum (XEXP (x, 0))]);
1090 break;
1092 default:
1093 x = mark_constant_pool_use (x);
1094 output_addr_const (stream, x);
1095 break;
1099 /* Print operand x (an rtx) in assembler syntax to file stream
1100 according to modifier code.
1102 '.' print a .s if insn needs delay slot
1103 ',' print LOCAL_LABEL_PREFIX
1104 '@' print trap, rte or rts depending upon pragma interruptness
1105 '#' output a nop if there is nothing to put in the delay slot
1106 ''' print likelihood suffix (/u for unlikely).
1107 '>' print branch target if -fverbose-asm
1108 'O' print a constant without the #
1109 'R' print the LSW of a dp value - changes if in little endian
1110 'S' print the MSW of a dp value - changes if in little endian
1111 'T' print the next word of a dp value - same as 'R' in big endian mode.
1112 'M' print .b / .w / .l / .s / .d suffix if operand is a MEM.
1113 'N' print 'r63' if the operand is (const_int 0).
1114 'd' print a V2SF reg as dN instead of fpN.
1115 'm' print a pair `base,offset' or `base,index', for LD and ST.
1116 'U' Likewise for {LD,ST}{HI,LO}.
1117 'V' print the position of a single bit set.
1118 'W' print the position of a single bit cleared.
1119 't' print a memory address which is a register.
1120 'u' prints the lowest 16 bits of CONST_INT, as an unsigned value.
1121 'o' output an operator. */
1122 static void
1123 sh_print_operand (FILE *stream, rtx x, int code)
1125 int regno;
1126 machine_mode mode;
1128 switch (code)
1130 tree trapa_attr;
1132 case '.':
1133 if (final_sequence
1134 && ! INSN_ANNULLED_BRANCH_P (final_sequence->insn (0))
1135 && get_attr_length (final_sequence->insn (1)))
1136 fprintf (stream, ASSEMBLER_DIALECT ? "/s" : ".s");
1137 break;
1138 case ',':
1139 fprintf (stream, "%s", LOCAL_LABEL_PREFIX);
1140 break;
1141 case '@':
1142 trapa_attr = lookup_attribute ("trap_exit",
1143 DECL_ATTRIBUTES (current_function_decl));
1144 if (trapa_attr)
1145 fprintf (stream, "trapa #%ld",
1146 (long) TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (trapa_attr))));
1147 else if (sh_cfun_interrupt_handler_p ())
1149 if (sh_cfun_resbank_handler_p ())
1150 fprintf (stream, "resbank\n");
1151 fprintf (stream, "rte");
1153 else
1154 fprintf (stream, "rts");
1155 break;
1156 case '#':
1157 /* Output a nop if there's nothing in the delay slot. */
1158 if (dbr_sequence_length () == 0)
1159 fprintf (stream, "\n\tnop");
1160 break;
1161 case '\'':
1163 rtx note = find_reg_note (current_output_insn, REG_BR_PROB, 0);
1165 if (note
1166 && profile_probability::from_reg_br_prob_note (XINT (note, 0))
1167 < profile_probability::even ())
1168 fputs ("/u", stream);
1169 break;
1171 case '>':
1172 if (flag_verbose_asm && JUMP_LABEL (current_output_insn))
1174 fputs ("\t! target: ", stream);
1175 output_addr_const (stream, JUMP_LABEL (current_output_insn));
1177 break;
1178 case 'O':
1179 x = mark_constant_pool_use (x);
1180 output_addr_const (stream, x);
1181 break;
1182 /* N.B.: %R / %S / %T adjust memory addresses by four.
1183 While they can be used to access 64 bit parts of a larger value
1184 held in general purpose registers, that won't work with memory -
1185 neither for fp registers, since the frxx names are used. */
1186 case 'R':
1187 if (REG_P (x) || GET_CODE (x) == SUBREG)
1189 regno = true_regnum (x);
1190 regno += FP_REGISTER_P (regno) ? 1 : SH_REG_LSW_OFFSET;
1191 fputs (reg_names[regno], (stream));
1193 else if (MEM_P (x))
1195 x = adjust_address (x, SImode, 4 * SH_REG_LSW_OFFSET);
1196 sh_print_operand_address (stream, GET_MODE (x), XEXP (x, 0));
1198 else
1200 rtx sub = NULL_RTX;
1202 mode = GET_MODE (x);
1203 if (mode == VOIDmode)
1204 mode = DImode;
1205 if (GET_MODE_SIZE (mode) >= 8)
1206 sub = simplify_subreg (SImode, x, mode, 4 * SH_REG_LSW_OFFSET);
1207 if (sub)
1208 sh_print_operand (stream, sub, 0);
1209 else
1210 output_operand_lossage ("invalid operand to %%R");
1212 break;
1213 case 'S':
1214 if (REG_P (x) || GET_CODE (x) == SUBREG)
1216 regno = true_regnum (x);
1217 regno += FP_REGISTER_P (regno) ? 0 : SH_REG_MSW_OFFSET;
1218 fputs (reg_names[regno], (stream));
1220 else if (MEM_P (x))
1222 x = adjust_address (x, SImode, 4 * SH_REG_MSW_OFFSET);
1223 sh_print_operand_address (stream, GET_MODE (x), XEXP (x, 0));
1225 else
1227 rtx sub = NULL_RTX;
1229 mode = GET_MODE (x);
1230 if (mode == VOIDmode)
1231 mode = DImode;
1232 if (GET_MODE_SIZE (mode) >= 8)
1233 sub = simplify_subreg (SImode, x, mode, 4 * SH_REG_MSW_OFFSET);
1234 if (sub)
1235 sh_print_operand (stream, sub, 0);
1236 else
1237 output_operand_lossage ("invalid operand to %%S");
1239 break;
1240 case 'T':
1241 /* Next word of a double. */
1242 switch (GET_CODE (x))
1244 case REG:
1245 fputs (reg_names[REGNO (x) + 1], (stream));
1246 break;
1247 case MEM:
1249 machine_mode mode = GET_MODE (x);
1250 if (GET_CODE (XEXP (x, 0)) != PRE_DEC
1251 && GET_CODE (XEXP (x, 0)) != POST_INC)
1252 x = adjust_address (x, SImode, 4);
1253 sh_print_operand_address (stream, mode, XEXP (x, 0));
1255 break;
1256 default:
1257 break;
1259 break;
1261 case 't':
1262 gcc_assert (MEM_P (x));
1263 x = XEXP (x, 0);
1264 switch (GET_CODE (x))
1266 case REG:
1267 case SUBREG:
1268 sh_print_operand (stream, x, 0);
1269 break;
1270 default:
1271 break;
1273 break;
1275 case 'o':
1276 switch (GET_CODE (x))
1278 case PLUS: fputs ("add", stream); break;
1279 case MINUS: fputs ("sub", stream); break;
1280 case MULT: fputs ("mul", stream); break;
1281 case DIV: fputs ("div", stream); break;
1282 case EQ: fputs ("eq", stream); break;
1283 case NE: fputs ("ne", stream); break;
1284 case GT: case LT: fputs ("gt", stream); break;
1285 case GE: case LE: fputs ("ge", stream); break;
1286 case GTU: case LTU: fputs ("gtu", stream); break;
1287 case GEU: case LEU: fputs ("geu", stream); break;
1288 default:
1289 break;
1291 break;
1292 case 'M':
1293 if (MEM_P (x))
1295 switch (GET_MODE (x))
1297 case E_QImode: fputs (".b", stream); break;
1298 case E_HImode: fputs (".w", stream); break;
1299 case E_SImode: fputs (".l", stream); break;
1300 case E_SFmode: fputs (".s", stream); break;
1301 case E_DFmode: fputs (".d", stream); break;
1302 default: gcc_unreachable ();
1305 break;
1307 case 'm':
1308 gcc_assert (MEM_P (x));
1309 x = XEXP (x, 0);
1310 /* Fall through. */
1311 case 'U':
1312 switch (GET_CODE (x))
1314 case REG:
1315 case SUBREG:
1316 sh_print_operand (stream, x, 0);
1317 fputs (", 0", stream);
1318 break;
1320 case PLUS:
1321 sh_print_operand (stream, XEXP (x, 0), 0);
1322 fputs (", ", stream);
1323 sh_print_operand (stream, XEXP (x, 1), 0);
1324 break;
1326 default:
1327 gcc_unreachable ();
1329 break;
1331 case 'V':
1333 int num = exact_log2 (INTVAL (x));
1334 gcc_assert (num >= 0);
1335 fprintf (stream, "#%d", num);
1337 break;
1339 case 'W':
1341 int num = exact_log2 (~INTVAL (x));
1342 gcc_assert (num >= 0);
1343 fprintf (stream, "#%d", num);
1345 break;
1347 case 'd':
1348 gcc_assert (REG_P (x) && GET_MODE (x) == V2SFmode);
1350 fprintf ((stream), "d%s", reg_names[REGNO (x)] + 1);
1351 break;
1353 case 'N':
1354 if (x == CONST0_RTX (GET_MODE (x)))
1356 fprintf ((stream), "r63");
1357 break;
1359 goto default_output;
1360 case 'u':
1361 if (CONST_INT_P (x))
1363 fprintf ((stream), "%u", (unsigned) INTVAL (x) & (0x10000 - 1));
1364 break;
1366 /* Fall through. */
1368 default_output:
1369 default:
1370 regno = 0;
1371 mode = GET_MODE (x);
1373 switch (GET_CODE (x))
1375 case TRUNCATE:
1377 rtx inner = XEXP (x, 0);
1378 int offset = 0;
1379 machine_mode inner_mode;
1381 /* We might see SUBREGs with vector mode registers inside. */
1382 if (GET_CODE (inner) == SUBREG
1383 && (GET_MODE_SIZE (GET_MODE (inner))
1384 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1385 && subreg_lowpart_p (inner))
1386 inner = SUBREG_REG (inner);
1387 if (CONST_INT_P (inner))
1389 x = GEN_INT (trunc_int_for_mode (INTVAL (inner), GET_MODE (x)));
1390 goto default_output;
1392 inner_mode = GET_MODE (inner);
1393 if (GET_CODE (inner) == SUBREG
1394 && (GET_MODE_SIZE (GET_MODE (inner))
1395 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
1396 && REG_P (SUBREG_REG (inner)))
1398 offset = subreg_regno_offset (REGNO (SUBREG_REG (inner)),
1399 GET_MODE (SUBREG_REG (inner)),
1400 SUBREG_BYTE (inner),
1401 GET_MODE (inner));
1402 inner = SUBREG_REG (inner);
1404 if (!REG_P (inner) || GET_MODE_SIZE (inner_mode) > 8)
1405 abort ();
1406 /* Floating point register pairs are always big endian;
1407 general purpose registers are 64 bit wide. */
1408 regno = REGNO (inner);
1409 regno = (hard_regno_nregs (regno, inner_mode)
1410 - hard_regno_nregs (regno, mode))
1411 + offset;
1412 x = inner;
1413 goto reg;
1415 case SIGN_EXTEND:
1416 x = XEXP (x, 0);
1417 goto reg;
1418 case SUBREG:
1419 gcc_assert (SUBREG_BYTE (x) == 0
1420 && REG_P (SUBREG_REG (x)));
1422 x = SUBREG_REG (x);
1423 /* Fall through. */
1425 reg:
1426 case REG:
1427 regno += REGNO (x);
1428 if (FP_REGISTER_P (regno)
1429 && mode == V16SFmode)
1430 fprintf ((stream), "mtrx%s", reg_names[regno] + 2);
1431 else if (FP_REGISTER_P (REGNO (x))
1432 && mode == V4SFmode)
1433 fprintf ((stream), "fv%s", reg_names[regno] + 2);
1434 else if (REG_P (x)
1435 && mode == V2SFmode)
1436 fprintf ((stream), "fp%s", reg_names[regno] + 2);
1437 else if (FP_REGISTER_P (REGNO (x))
1438 && GET_MODE_SIZE (mode) > 4)
1439 fprintf ((stream), "d%s", reg_names[regno] + 1);
1440 else
1441 fputs (reg_names[regno], (stream));
1442 break;
1444 case MEM:
1445 output_address (GET_MODE (x), XEXP (x, 0));
1446 break;
1448 default:
1449 fputc ('#', stream);
1450 output_addr_const (stream, x);
1451 break;
1453 break;
1457 static bool
1458 sh_print_operand_punct_valid_p (unsigned char code)
1460 return (code == '.' || code == '#' || code == '@' || code == ','
1461 || code == '$' || code == '\'' || code == '>');
1464 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
1465 static bool
1466 sh_asm_output_addr_const_extra (FILE *file, rtx x)
1468 if (GET_CODE (x) == UNSPEC)
1470 switch (XINT (x, 1))
1472 case UNSPEC_PIC:
1473 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */
1474 output_addr_const (file, XVECEXP (x, 0, 0));
1475 break;
1476 case UNSPEC_GOT:
1477 output_addr_const (file, XVECEXP (x, 0, 0));
1478 fputs ("@GOT", file);
1479 break;
1480 case UNSPEC_GOTOFF:
1481 output_addr_const (file, XVECEXP (x, 0, 0));
1482 fputs ("@GOTOFF", file);
1483 break;
1484 case UNSPEC_PLT:
1485 output_addr_const (file, XVECEXP (x, 0, 0));
1486 fputs ("@PLT", file);
1487 break;
1488 case UNSPEC_GOTPLT:
1489 output_addr_const (file, XVECEXP (x, 0, 0));
1490 fputs ("@GOTPLT", file);
1491 break;
1492 case UNSPEC_PCREL:
1493 output_addr_const (file, XVECEXP (x, 0, 0));
1494 fputs ("@PCREL", file);
1495 break;
1496 case UNSPEC_DTPOFF:
1497 output_addr_const (file, XVECEXP (x, 0, 0));
1498 fputs ("@DTPOFF", file);
1499 break;
1500 case UNSPEC_GOTTPOFF:
1501 output_addr_const (file, XVECEXP (x, 0, 0));
1502 fputs ("@GOTTPOFF", file);
1503 break;
1504 case UNSPEC_TPOFF:
1505 output_addr_const (file, XVECEXP (x, 0, 0));
1506 fputs ("@TPOFF", file);
1507 break;
1508 case UNSPEC_CALLER:
1510 char name[32];
1511 /* LPCS stands for Label for PIC Call Site. */
1512 targetm.asm_out.generate_internal_label (name, "LPCS",
1513 INTVAL (XVECEXP (x, 0, 0)));
1514 assemble_name (file, name);
1516 break;
1517 case UNSPEC_SYMOFF:
1518 output_addr_const (file, XVECEXP (x, 0, 0));
1519 fputc ('-', file);
1520 if (GET_CODE (XVECEXP (x, 0, 1)) == CONST)
1522 fputc ('(', file);
1523 output_addr_const (file, XVECEXP (x, 0, 1));
1524 fputc (')', file);
1526 else
1527 output_addr_const (file, XVECEXP (x, 0, 1));
1528 break;
1529 case UNSPEC_PCREL_SYMOFF:
1530 output_addr_const (file, XVECEXP (x, 0, 0));
1531 fputs ("-(", file);
1532 output_addr_const (file, XVECEXP (x, 0, 1));
1533 fputs ("-.)", file);
1534 break;
1535 case UNSPEC_GOTFUNCDESC:
1536 output_addr_const (file, XVECEXP (x, 0, 0));
1537 fputs ("@GOTFUNCDESC", file);
1538 break;
1539 case UNSPEC_GOTOFFFUNCDESC:
1540 output_addr_const (file, XVECEXP (x, 0, 0));
1541 fputs ("@GOTOFFFUNCDESC", file);
1542 break;
1543 default:
1544 return false;
1546 return true;
1548 else
1549 return false;
1552 /* Encode symbol attributes of a SYMBOL_REF into its
1553 SYMBOL_REF_FLAGS. */
1554 static void
1555 sh_encode_section_info (tree decl, rtx rtl, int first)
1557 default_encode_section_info (decl, rtl, first);
1559 if (TREE_CODE (decl) == FUNCTION_DECL
1560 && sh2a_function_vector_p (decl) && TARGET_SH2A)
1561 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FUNCVEC_FUNCTION;
1564 /* Prepare operands for a move define_expand; specifically, one of the
1565 operands must be in a register. */
1566 void
1567 prepare_move_operands (rtx operands[], machine_mode mode)
1569 if ((mode == SImode || mode == DImode)
1570 && flag_pic
1571 && ! ((mode == Pmode || mode == ptr_mode)
1572 && tls_symbolic_operand (operands[1], Pmode) != TLS_MODEL_NONE))
1574 rtx temp;
1575 if (SYMBOLIC_CONST_P (operands[1]))
1577 if (MEM_P (operands[0]))
1578 operands[1] = force_reg (Pmode, operands[1]);
1579 else
1581 temp = (!can_create_pseudo_p ()
1582 ? operands[0]
1583 : gen_reg_rtx (Pmode));
1584 operands[1] = legitimize_pic_address (operands[1], mode, temp);
1587 else if (GET_CODE (operands[1]) == CONST
1588 && GET_CODE (XEXP (operands[1], 0)) == PLUS
1589 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0)))
1591 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
1592 temp = legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0),
1593 mode, temp);
1594 operands[1] = expand_binop (mode, add_optab, temp,
1595 XEXP (XEXP (operands[1], 0), 1),
1596 (!can_create_pseudo_p ()
1597 ? temp
1598 : gen_reg_rtx (Pmode)),
1599 0, OPTAB_LIB_WIDEN);
1603 if (! reload_in_progress && ! reload_completed)
1605 /* Copy the source to a register if both operands aren't registers. */
1606 if (! register_operand (operands[0], mode)
1607 && ! register_operand (operands[1], mode))
1608 operands[1] = copy_to_mode_reg (mode, operands[1]);
1610 if (MEM_P (operands[0]) && ! memory_operand (operands[0], mode))
1612 /* This is like change_address_1 (operands[0], mode, 0, 1) ,
1613 except that we can't use that function because it is static. */
1614 rtx new_rtx = change_address (operands[0], mode, 0);
1615 MEM_COPY_ATTRIBUTES (new_rtx, operands[0]);
1616 operands[0] = new_rtx;
1619 /* This case can happen while generating code to move the result
1620 of a library call to the target. Reject `st r0,@(rX,rY)' because
1621 reload will fail to find a spill register for rX, since r0 is already
1622 being used for the source. */
1623 else if (refers_to_regno_p (R0_REG, operands[1])
1624 && MEM_P (operands[0])
1625 && GET_CODE (XEXP (operands[0], 0)) == PLUS
1626 && REG_P (XEXP (XEXP (operands[0], 0), 1)))
1627 operands[1] = copy_to_mode_reg (mode, operands[1]);
1629 /* When the displacement addressing is used, RA will assign r0 to
1630 the pseudo register operand for the QI/HImode load/store.
1631 This tends to make a long live range for R0 and might cause
1632 anomalous register spills in some case with LRA. See PR
1633 target/55212.
1634 We split possible load/store to two move insns via r0 so as to
1635 shorten R0 live range. It will make some codes worse but will
1636 win on average for LRA.
1637 Also when base+index addressing is used and the index term is
1638 a subreg, LRA assumes that more hard registers can be available
1639 in some situation. It isn't the case for SH in the problematic
1640 case. We can pre-allocate R0 for that index term to avoid
1641 the issue. See PR target/66591. */
1642 else if (sh_lra_p ()
1643 && ! TARGET_SH2A
1644 && ((REG_P (operands[0]) && MEM_P (operands[1]))
1645 || (REG_P (operands[1]) && MEM_P (operands[0]))))
1647 bool load_p = REG_P (operands[0]);
1648 rtx reg = operands[load_p ? 0 : 1];
1649 rtx adr = XEXP (operands[load_p ? 1 : 0], 0);
1651 if ((mode == QImode || mode == HImode)
1652 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
1653 && GET_CODE (adr) == PLUS
1654 && REG_P (XEXP (adr, 0))
1655 && (REGNO (XEXP (adr, 0)) >= FIRST_PSEUDO_REGISTER)
1656 && CONST_INT_P (XEXP (adr, 1))
1657 && INTVAL (XEXP (adr, 1)) != 0
1658 && sh_legitimate_index_p (mode, XEXP (adr, 1), false, true))
1660 rtx r0_rtx = gen_rtx_REG (mode, R0_REG);
1661 emit_move_insn (r0_rtx, operands[1]);
1662 operands[1] = r0_rtx;
1664 if (REGNO (reg) >= FIRST_PSEUDO_REGISTER
1665 && GET_CODE (adr) == PLUS
1666 && REG_P (XEXP (adr, 0))
1667 && (REGNO (XEXP (adr, 0)) >= FIRST_PSEUDO_REGISTER)
1668 && SUBREG_P (XEXP (adr, 1))
1669 && REG_P (SUBREG_REG (XEXP (adr, 1))))
1671 rtx r0_rtx = gen_rtx_REG (GET_MODE (XEXP (adr, 1)), R0_REG);
1672 emit_move_insn (r0_rtx, XEXP (adr, 1));
1673 XEXP (adr, 1) = r0_rtx;
1678 if (mode == Pmode || mode == ptr_mode)
1680 rtx op0 = operands[0];
1681 rtx op1 = operands[1];
1682 rtx opc;
1683 if (GET_CODE (op1) == CONST
1684 && GET_CODE (XEXP (op1, 0)) == PLUS
1685 && (tls_symbolic_operand (XEXP (XEXP (op1, 0), 0), Pmode)
1686 != TLS_MODEL_NONE))
1688 opc = XEXP (XEXP (op1, 0), 1);
1689 op1 = XEXP (XEXP (op1, 0), 0);
1691 else
1692 opc = NULL_RTX;
1694 enum tls_model tls_kind;
1696 if (! reload_in_progress && ! reload_completed
1697 && (tls_kind = tls_symbolic_operand (op1, Pmode)) != TLS_MODEL_NONE)
1699 rtx tga_op1, tga_ret, tmp, tmp2;
1701 if (! flag_pic
1702 && (tls_kind == TLS_MODEL_GLOBAL_DYNAMIC
1703 || tls_kind == TLS_MODEL_LOCAL_DYNAMIC
1704 || tls_kind == TLS_MODEL_INITIAL_EXEC))
1706 static int got_labelno;
1707 /* Don't schedule insns for getting GOT address when
1708 the first scheduling is enabled, to avoid spill
1709 failures for R0. */
1710 if (flag_schedule_insns)
1711 emit_insn (gen_blockage ());
1712 emit_insn (gen_GOTaddr2picreg (GEN_INT (++got_labelno)));
1713 emit_use (gen_rtx_REG (SImode, PIC_REG));
1714 if (flag_schedule_insns)
1715 emit_insn (gen_blockage ());
1718 switch (tls_kind)
1720 case TLS_MODEL_GLOBAL_DYNAMIC:
1721 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1722 if (TARGET_FDPIC)
1723 emit_move_insn (gen_rtx_REG (Pmode, PIC_REG),
1724 sh_get_fdpic_reg_initial_val ());
1725 emit_call_insn (gen_tls_global_dynamic (tga_ret, op1));
1726 tmp = gen_reg_rtx (Pmode);
1727 emit_move_insn (tmp, tga_ret);
1728 op1 = tmp;
1729 break;
1731 case TLS_MODEL_LOCAL_DYNAMIC:
1732 tga_ret = gen_rtx_REG (Pmode, R0_REG);
1733 if (TARGET_FDPIC)
1734 emit_move_insn (gen_rtx_REG (Pmode, PIC_REG),
1735 sh_get_fdpic_reg_initial_val ());
1736 emit_call_insn (gen_tls_local_dynamic (tga_ret, op1));
1738 tmp = gen_reg_rtx (Pmode);
1739 emit_move_insn (tmp, tga_ret);
1741 if (register_operand (op0, Pmode))
1742 tmp2 = op0;
1743 else
1744 tmp2 = gen_reg_rtx (Pmode);
1746 emit_insn (gen_symDTPOFF2reg (tmp2, op1, tmp));
1747 op1 = tmp2;
1748 break;
1750 case TLS_MODEL_INITIAL_EXEC:
1751 tga_op1 = !can_create_pseudo_p () ? op0 : gen_reg_rtx (Pmode);
1752 tmp = gen_sym2GOTTPOFF (op1);
1753 if (TARGET_FDPIC)
1754 emit_move_insn (gen_rtx_REG (Pmode, PIC_REG),
1755 sh_get_fdpic_reg_initial_val ());
1756 emit_insn (gen_tls_initial_exec (tga_op1, tmp));
1757 op1 = tga_op1;
1758 break;
1760 case TLS_MODEL_LOCAL_EXEC:
1761 tmp2 = gen_reg_rtx (Pmode);
1762 emit_insn (gen_store_gbr (tmp2));
1763 tmp = gen_reg_rtx (Pmode);
1764 emit_insn (gen_symTPOFF2reg (tmp, op1));
1766 if (register_operand (op0, Pmode))
1767 op1 = op0;
1768 else
1769 op1 = gen_reg_rtx (Pmode);
1771 emit_insn (gen_addsi3 (op1, tmp, tmp2));
1772 break;
1774 default:
1775 gcc_unreachable ();
1777 if (opc)
1778 emit_insn (gen_addsi3 (op1, op1, force_reg (SImode, opc)));
1779 operands[1] = op1;
1783 if (SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
1785 rtx base, offset;
1786 split_const (operands[1], &base, &offset);
1788 if (GET_CODE (base) == SYMBOL_REF
1789 && !offset_within_block_p (base, INTVAL (offset)))
1791 rtx tmp = can_create_pseudo_p () ? gen_reg_rtx (mode) : operands[0];
1792 emit_move_insn (tmp, base);
1793 if (!arith_operand (offset, mode))
1794 offset = force_reg (mode, offset);
1795 emit_insn (gen_add3_insn (operands[0], tmp, offset));
1800 /* Implement the canonicalize_comparison target hook for the combine
1801 pass. For the target hook this function is invoked via
1802 sh_canonicalize_comparison. This function is also re-used to
1803 canonicalize comparisons in cbranch pattern expanders. */
1804 static void
1805 sh_canonicalize_comparison (enum rtx_code& cmp, rtx& op0, rtx& op1,
1806 machine_mode mode,
1807 bool op0_preserve_value)
1809 /* When invoked from within the combine pass the mode is not specified,
1810 so try to get it from one of the operands. */
1811 if (mode == VOIDmode)
1812 mode = GET_MODE (op0);
1813 if (mode == VOIDmode)
1814 mode = GET_MODE (op1);
1816 // We need to have a mode to do something useful here.
1817 if (mode == VOIDmode)
1818 return;
1820 // Currently, we don't deal with floats here.
1821 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
1822 return;
1824 // Make sure that the constant operand is the second operand.
1825 if (CONST_INT_P (op0) && !CONST_INT_P (op1))
1827 if (op0_preserve_value)
1828 return;
1830 std::swap (op0, op1);
1831 cmp = swap_condition (cmp);
1834 if (CONST_INT_P (op1))
1836 /* Try to adjust the constant operand in such a way that available
1837 comparison insns can be utilized better and the constant can be
1838 loaded with a 'mov #imm,Rm' insn. This avoids a load from the
1839 constant pool. */
1840 const HOST_WIDE_INT val = INTVAL (op1);
1842 /* x > -1 --> x >= 0
1843 x > 0xFFFFFF7F --> x >= 0xFFFFFF80
1844 x <= -1 --> x < 0
1845 x <= 0xFFFFFF7F --> x < 0xFFFFFF80 */
1846 if ((val == -1 || val == -0x81) && (cmp == GT || cmp == LE))
1848 cmp = cmp == GT ? GE : LT;
1849 op1 = gen_int_mode (val + 1, mode);
1852 /* x >= 1 --> x > 0
1853 x >= 0x80 --> x > 0x7F
1854 x < 1 --> x <= 0
1855 x < 0x80 --> x <= 0x7F */
1856 else if ((val == 1 || val == 0x80) && (cmp == GE || cmp == LT))
1858 cmp = cmp == GE ? GT : LE;
1859 op1 = gen_int_mode (val - 1, mode);
1862 /* unsigned x >= 1 --> x != 0
1863 unsigned x < 1 --> x == 0 */
1864 else if (val == 1 && (cmp == GEU || cmp == LTU))
1866 cmp = cmp == GEU ? NE : EQ;
1867 op1 = CONST0_RTX (mode);
1870 /* unsigned x >= 0x80 --> unsigned x > 0x7F
1871 unsigned x < 0x80 --> unsigned x < 0x7F */
1872 else if (val == 0x80 && (cmp == GEU || cmp == LTU))
1874 cmp = cmp == GEU ? GTU : LEU;
1875 op1 = gen_int_mode (val - 1, mode);
1878 /* unsigned x > 0 --> x != 0
1879 unsigned x <= 0 --> x == 0 */
1880 else if (val == 0 && (cmp == GTU || cmp == LEU))
1881 cmp = cmp == GTU ? NE : EQ;
1883 /* unsigned x > 0x7FFFFFFF --> signed x < 0
1884 unsigned x <= 0x7FFFFFFF --> signed x >= 0 */
1885 else if (mode == SImode && (cmp == GTU || cmp == LEU)
1886 && val == 0x7FFFFFFF)
1888 cmp = cmp == GTU ? LT : GE;
1889 op1 = const0_rtx;
1892 /* unsigned x >= 0x80000000 --> signed x < 0
1893 unsigned x < 0x80000000 --> signed x >= 0 */
1894 else if (mode == SImode && (cmp == GEU || cmp == LTU)
1895 && (unsigned HOST_WIDE_INT)val
1896 == ((unsigned HOST_WIDE_INT)0x7FFFFFFF + 1))
1898 cmp = cmp == GEU ? LT : GE;
1899 op1 = const0_rtx;
1904 /* This function implements the canonicalize_comparison target hook.
1905 This wrapper around the internally used sh_canonicalize_comparison
1906 function is needed to do the enum rtx_code <-> int conversion.
1907 Target hooks cannot use enum rtx_code in its definition. */
1908 static void
1909 sh_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
1910 bool op0_preserve_value)
1912 enum rtx_code tmp_code = (enum rtx_code)*code;
1913 sh_canonicalize_comparison (tmp_code, *op0, *op1,
1914 VOIDmode, op0_preserve_value);
1915 *code = (int)tmp_code;
1918 /* This function implements the legitimate_combined_insn target hook,
1919 which the combine pass uses to early reject combined insns, before
1920 it tries to recog the insn and determine its cost. */
1921 static bool
1922 sh_legitimate_combined_insn (rtx_insn* insn)
1924 /* Reject combinations of memory loads and zero extensions, as these
1925 interfere with other combine patterns such as zero extracts and bit
1926 tests. The SH2A movu.{b|w} insns are formed later in the
1927 'sh_optimize_extu_exts' pass after combine/split1. */
1928 rtx p = PATTERN (insn);
1929 if (GET_CODE (p) == SET
1930 && REG_P (XEXP (p, 0)) && GET_MODE (XEXP (p, 0)) == SImode
1931 && GET_CODE (XEXP (p, 1)) == ZERO_EXTEND
1932 && MEM_P (XEXP (XEXP (p, 1), 0)))
1933 return false;
1935 return true;
1938 bool
1939 sh_fixed_condition_code_regs (unsigned int* p1, unsigned int* p2)
1941 *p1 = T_REG;
1942 *p2 = INVALID_REGNUM;
1943 return true;
1946 /* Try to calculate the branch distance of a conditional branch in bytes.
1948 FIXME: Because of PR 59189 we can't use the CFG here. Instead just
1949 walk from this insn into the next (fall-through) basic block and see if
1950 we hit the label. */
1951 unsigned int
1952 sh_cbranch_distance (rtx_insn* _cbranch_insn, unsigned int max_dist)
1954 rtx_jump_insn* cbranch_insn = safe_as_a<rtx_jump_insn*> (_cbranch_insn);
1956 if (dump_file)
1958 fprintf (dump_file, "sh_cbranch_distance insn = \n");
1959 print_rtl_single (dump_file, cbranch_insn);
1962 unsigned int dist = 0;
1964 for (rtx_insn* i = next_nonnote_insn (cbranch_insn);
1965 i != NULL && dist < max_dist; i = next_nonnote_insn (i))
1967 const unsigned int i_len = get_attr_length (i);
1968 dist += i_len;
1970 if (dump_file)
1971 fprintf (dump_file, " insn %d length = %u dist = %u\n",
1972 INSN_UID (i), i_len, dist);
1974 if (rtx_code_label* l = dyn_cast<rtx_code_label*> (i))
1976 if (l == cbranch_insn->jump_target ())
1978 if (dump_file)
1979 fprintf (dump_file, " cbranch dist = %u\n", dist);
1980 return dist;
1982 break;
1986 if (dump_file)
1987 fprintf (dump_file, " cbranch dist = unknown\n");
1989 return unknown_cbranch_distance;
1992 enum rtx_code
1993 prepare_cbranch_operands (rtx *operands, machine_mode mode,
1994 enum rtx_code comparison)
1996 gcc_assert (can_create_pseudo_p ());
1998 if (comparison == LAST_AND_UNUSED_RTX_CODE)
1999 comparison = GET_CODE (operands[0]);
2001 sh_canonicalize_comparison (comparison, operands[1], operands[2],
2002 mode, false);
2004 rtx op1 = operands[1];
2005 operands[1] = force_reg (mode, op1);
2007 /* When we are handling DImode comparisons, we want to keep constants so
2008 that we can optimize the component comparisons; however, memory loads
2009 are better issued as a whole so that they can be scheduled well.
2010 SImode equality comparisons allow I08 constants, but only when they
2011 compare r0. Hence, if operands[1] has to be loaded from somewhere else
2012 into a register, that register might as well be r0, and we allow the
2013 constant. If it is already in a register, this is likely to be
2014 allocated to a different hard register, thus we load the constant into
2015 a register unless it is zero. */
2016 if (!REG_P (operands[2])
2017 && (!CONST_INT_P (operands[2])
2018 || (mode == SImode && operands[2] != CONST0_RTX (SImode)
2019 && ((comparison != EQ && comparison != NE)
2020 || (REG_P (op1) && REGNO (op1) != R0_REG)
2021 || !satisfies_constraint_I08 (operands[2])))))
2022 operands[2] = force_reg (mode, operands[2]);
2024 return comparison;
2027 static void
2028 expand_cbranchsi4 (rtx *operands, enum rtx_code comparison,
2029 profile_probability probability)
2031 rtx (*branch_expander) (rtx) = gen_branch_true;
2032 comparison = prepare_cbranch_operands (operands, SImode, comparison);
2033 switch (comparison)
2035 case NE: case LT: case LE: case LTU: case LEU:
2036 comparison = reverse_condition (comparison);
2037 branch_expander = gen_branch_false;
2038 default: ;
2040 emit_insn (gen_rtx_SET (get_t_reg_rtx (),
2041 gen_rtx_fmt_ee (comparison, SImode,
2042 operands[1], operands[2])));
2043 rtx_insn *jump = emit_jump_insn (branch_expander (operands[3]));
2044 if (probability.initialized_p ())
2045 add_reg_br_prob_note (jump, probability);
2048 void
2049 expand_cbranchsi4 (rtx *operands, enum rtx_code comparison)
2051 expand_cbranchsi4 (operands, comparison,
2052 profile_probability::uninitialized ());
2055 /* ??? How should we distribute probabilities when more than one branch
2056 is generated. So far we only have some ad-hoc observations:
2057 - If the operands are random, they are likely to differ in both parts.
2058 - If comparing items in a hash chain, the operands are random or equal;
2059 operation should be EQ or NE.
2060 - If items are searched in an ordered tree from the root, we can expect
2061 the highpart to be unequal about half of the time; operation should be
2062 an inequality comparison, operands non-constant, and overall probability
2063 about 50%. Likewise for quicksort.
2064 - Range checks will be often made against constants. Even if we assume for
2065 simplicity an even distribution of the non-constant operand over a
2066 sub-range here, the same probability could be generated with differently
2067 wide sub-ranges - as long as the ratio of the part of the subrange that
2068 is before the threshold to the part that comes after the threshold stays
2069 the same. Thus, we can't really tell anything here;
2070 assuming random distribution is at least simple.
2072 bool
2073 expand_cbranchdi4 (rtx *operands, enum rtx_code comparison)
2075 enum rtx_code msw_taken, msw_skip, lsw_taken;
2076 rtx_code_label *skip_label = NULL;
2077 rtx op1h, op1l, op2h, op2l;
2078 int num_branches;
2079 profile_probability prob, rev_prob;
2080 profile_probability msw_taken_prob = profile_probability::uninitialized (),
2081 msw_skip_prob = profile_probability::uninitialized (),
2082 lsw_taken_prob = profile_probability::uninitialized ();
2084 comparison = prepare_cbranch_operands (operands, DImode, comparison);
2085 op1h = gen_highpart_mode (SImode, DImode, operands[1]);
2086 op2h = gen_highpart_mode (SImode, DImode, operands[2]);
2087 op1l = gen_lowpart (SImode, operands[1]);
2088 op2l = gen_lowpart (SImode, operands[2]);
2089 msw_taken = msw_skip = lsw_taken = LAST_AND_UNUSED_RTX_CODE;
2090 prob = split_branch_probability;
2091 rev_prob = prob.invert ();
2092 switch (comparison)
2094 case EQ:
2095 msw_skip = NE;
2096 lsw_taken = EQ;
2097 if (prob.initialized_p ())
2099 /* FIXME: This is not optimal. We do not really know the probablity
2100 that values differ by MCW only, but we should probably distribute
2101 probabilities more evenly. */
2102 msw_skip_prob = rev_prob;
2103 lsw_taken_prob = prob > profile_probability::never ()
2104 ? profile_probability::guessed_always ()
2105 : profile_probability::guessed_never ();
2107 break;
2108 case NE:
2109 msw_taken = NE;
2110 msw_taken_prob = prob;
2111 lsw_taken = NE;
2112 lsw_taken_prob = profile_probability::guessed_never ();
2113 break;
2114 case GTU: case GT:
2115 msw_taken = comparison;
2116 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
2117 break;
2118 if (comparison != GTU || op2h != CONST0_RTX (SImode))
2119 msw_skip = swap_condition (msw_taken);
2120 lsw_taken = GTU;
2121 break;
2122 case GEU: case GE:
2123 if (op2l == CONST0_RTX (SImode))
2124 msw_taken = comparison;
2125 else
2127 msw_taken = comparison == GE ? GT : GTU;
2128 msw_skip = swap_condition (msw_taken);
2129 lsw_taken = GEU;
2131 break;
2132 case LTU: case LT:
2133 msw_taken = comparison;
2134 if (op2l == CONST0_RTX (SImode))
2135 break;
2136 msw_skip = swap_condition (msw_taken);
2137 lsw_taken = LTU;
2138 break;
2139 case LEU: case LE:
2140 if (CONST_INT_P (op2l) && INTVAL (op2l) == -1)
2141 msw_taken = comparison;
2142 else
2144 lsw_taken = LEU;
2145 if (comparison == LE)
2146 msw_taken = LT;
2147 else if (op2h != CONST0_RTX (SImode))
2148 msw_taken = LTU;
2149 else
2151 msw_skip = swap_condition (LTU);
2152 break;
2154 msw_skip = swap_condition (msw_taken);
2156 break;
2157 default: return false;
2159 num_branches = ((msw_taken != LAST_AND_UNUSED_RTX_CODE)
2160 + (msw_skip != LAST_AND_UNUSED_RTX_CODE)
2161 + (lsw_taken != LAST_AND_UNUSED_RTX_CODE));
2162 if (comparison != EQ && comparison != NE && num_branches > 1)
2164 if (!CONSTANT_P (operands[2])
2165 && prob.initialized_p ()
2166 && prob.to_reg_br_prob_base () >= (int) (REG_BR_PROB_BASE * 3 / 8U)
2167 && prob.to_reg_br_prob_base () <= (int) (REG_BR_PROB_BASE * 5 / 8U))
2169 msw_taken_prob = prob.apply_scale (1, 2);
2170 msw_skip_prob = rev_prob.apply_scale (REG_BR_PROB_BASE,
2171 rev_prob.to_reg_br_prob_base ()
2172 + REG_BR_PROB_BASE);
2173 lsw_taken_prob = prob;
2175 else
2177 msw_taken_prob = prob;
2178 msw_skip_prob = profile_probability::guessed_always ();
2179 /* ??? If we have a constant op2h, should we use that when
2180 calculating lsw_taken_prob? */
2181 lsw_taken_prob = prob;
2184 operands[1] = op1h;
2185 operands[2] = op2h;
2187 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
2188 expand_cbranchsi4 (operands, msw_taken, msw_taken_prob);
2189 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
2191 rtx taken_label = operands[3];
2193 /* Operands were possibly modified, but msw_skip doesn't expect this.
2194 Always use the original ones. */
2195 if (msw_taken != LAST_AND_UNUSED_RTX_CODE)
2197 operands[1] = op1h;
2198 operands[2] = op2h;
2201 operands[3] = skip_label = gen_label_rtx ();
2202 expand_cbranchsi4 (operands, msw_skip, msw_skip_prob);
2203 operands[3] = taken_label;
2205 operands[1] = op1l;
2206 operands[2] = op2l;
2207 if (lsw_taken != LAST_AND_UNUSED_RTX_CODE)
2208 expand_cbranchsi4 (operands, lsw_taken, lsw_taken_prob);
2209 if (msw_skip != LAST_AND_UNUSED_RTX_CODE)
2210 emit_label (skip_label);
2211 return true;
2214 /* Given an operand, return 1 if the evaluated operand plugged into an
2215 if_then_else will result in a branch_true, 0 if branch_false, or
2216 -1 if neither nor applies. The truth table goes like this:
2218 op | cmpval | code | result
2219 ---------+--------+---------+--------------------
2220 T (0) | 0 | EQ (1) | 0 = 0 ^ (0 == 1)
2221 T (0) | 1 | EQ (1) | 1 = 0 ^ (1 == 1)
2222 T (0) | 0 | NE (0) | 1 = 0 ^ (0 == 0)
2223 T (0) | 1 | NE (0) | 0 = 0 ^ (1 == 0)
2224 !T (1) | 0 | EQ (1) | 1 = 1 ^ (0 == 1)
2225 !T (1) | 1 | EQ (1) | 0 = 1 ^ (1 == 1)
2226 !T (1) | 0 | NE (0) | 0 = 1 ^ (0 == 0)
2227 !T (1) | 1 | NE (0) | 1 = 1 ^ (1 == 0) */
2229 sh_eval_treg_value (rtx op)
2231 if (t_reg_operand (op, GET_MODE (op)))
2232 return 1;
2233 if (negt_reg_operand (op, GET_MODE (op)))
2234 return 0;
2236 rtx_code code = GET_CODE (op);
2237 if ((code != EQ && code != NE) || !CONST_INT_P (XEXP (op, 1)))
2238 return -1;
2240 int cmpop = code == EQ ? 1 : 0;
2241 int cmpval = INTVAL (XEXP (op, 1));
2242 if (cmpval != 0 && cmpval != 1)
2243 return -1;
2245 int t;
2246 if (t_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0))))
2247 t = 0;
2248 else if (negt_reg_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0))))
2249 t = 1;
2250 else
2251 return -1;
2253 return t ^ (cmpval == cmpop);
2256 /* Emit INSN, possibly in a PARALLEL with an USE/CLOBBER of FPSCR bits in case
2257 of floating-point comparisons. */
2258 static void
2259 sh_emit_set_t_insn (rtx insn, machine_mode mode)
2261 if (TARGET_FPU_ANY && GET_MODE_CLASS (mode) == MODE_FLOAT
2262 && GET_CODE (insn) != PARALLEL)
2264 insn = gen_rtx_PARALLEL (VOIDmode,
2265 gen_rtvec (3, insn,
2266 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, FPSCR_STAT_REG)),
2267 gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, FPSCR_MODES_REG))));
2269 emit_insn (insn);
2272 /* Prepare the operands for an scc instruction; make sure that the
2273 compare has been done and the result is in T_REG. */
2274 void
2275 sh_emit_scc_to_t (enum rtx_code code, rtx op0, rtx op1)
2277 rtx t_reg = get_t_reg_rtx ();
2278 enum rtx_code oldcode = code;
2280 /* First need a compare insn. */
2281 switch (code)
2283 case NE:
2284 /* It isn't possible to handle this case. */
2285 gcc_unreachable ();
2286 case LT:
2287 code = GT;
2288 break;
2289 case LE:
2290 code = GE;
2291 break;
2292 case LTU:
2293 code = GTU;
2294 break;
2295 case LEU:
2296 code = GEU;
2297 break;
2298 default:
2299 break;
2301 if (code != oldcode)
2302 std::swap (op0, op1);
2304 machine_mode mode = GET_MODE (op0);
2305 if (mode == VOIDmode)
2306 mode = GET_MODE (op1);
2308 op0 = force_reg (mode, op0);
2309 if ((code != EQ && code != NE
2310 && (op1 != const0_rtx
2311 || code == GTU || code == GEU || code == LTU || code == LEU))
2312 || (mode == DImode && op1 != const0_rtx)
2313 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2314 op1 = force_reg (mode, op1);
2316 sh_emit_set_t_insn (gen_rtx_SET (t_reg,
2317 gen_rtx_fmt_ee (code, SImode, op0, op1)),
2318 mode);
2321 /* Called from the md file, set up the operands of a compare instruction. */
2322 void
2323 sh_emit_compare_and_branch (rtx *operands, machine_mode mode)
2325 enum rtx_code code = GET_CODE (operands[0]);
2326 enum rtx_code branch_code;
2327 rtx op0 = operands[1];
2328 rtx op1 = operands[2];
2329 rtx insn;
2330 bool need_ccmpeq = false;
2332 if (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT)
2334 op0 = force_reg (mode, op0);
2335 op1 = force_reg (mode, op1);
2337 else
2339 if (code != EQ || mode == DImode)
2341 /* Force args into regs, since we can't use constants here. */
2342 op0 = force_reg (mode, op0);
2343 if (op1 != const0_rtx || code == GTU || code == GEU)
2344 op1 = force_reg (mode, op1);
2348 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2350 if (code == LT
2351 || (code == LE && TARGET_IEEE && TARGET_SH2E)
2352 || (code == GE && !(TARGET_IEEE && TARGET_SH2E)))
2354 std::swap (op0, op1);
2355 code = swap_condition (code);
2358 /* GE becomes fcmp/gt+fcmp/eq, for SH2E and TARGET_IEEE only. */
2359 if (code == GE)
2361 gcc_assert (TARGET_IEEE && TARGET_SH2E);
2362 need_ccmpeq = true;
2363 code = GT;
2366 /* Now we can have EQ, NE, GT, LE. NE and LE are then transformed
2367 to EQ/GT respectively. */
2368 gcc_assert (code == EQ || code == GT || code == NE || code == LE);
2371 switch (code)
2373 case EQ:
2374 case GT:
2375 case GE:
2376 case GTU:
2377 case GEU:
2378 branch_code = code;
2379 break;
2380 case NE:
2381 case LT:
2382 case LE:
2383 case LTU:
2384 case LEU:
2385 branch_code = reverse_condition (code);
2386 break;
2387 default:
2388 gcc_unreachable ();
2391 insn = gen_rtx_SET (get_t_reg_rtx (),
2392 gen_rtx_fmt_ee (branch_code, SImode, op0, op1));
2394 sh_emit_set_t_insn (insn, mode);
2395 if (need_ccmpeq)
2396 sh_emit_set_t_insn (gen_ieee_ccmpeqsf_t (op0, op1), mode);
2398 if (branch_code == code)
2399 emit_jump_insn (gen_branch_true (operands[3]));
2400 else
2401 emit_jump_insn (gen_branch_false (operands[3]));
2404 void
2405 sh_emit_compare_and_set (rtx *operands, machine_mode mode)
2407 enum rtx_code code = GET_CODE (operands[1]);
2408 rtx op0 = operands[2];
2409 rtx op1 = operands[3];
2410 rtx_code_label *lab = NULL;
2411 bool invert = false;
2413 op0 = force_reg (mode, op0);
2414 if ((code != EQ && code != NE
2415 && (op1 != const0_rtx
2416 || code == GTU || code == GEU || code == LTU || code == LEU))
2417 || (mode == DImode && op1 != const0_rtx)
2418 || (TARGET_SH2E && GET_MODE_CLASS (mode) == MODE_FLOAT))
2419 op1 = force_reg (mode, op1);
2421 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
2423 if (code == LT || code == LE)
2425 std::swap (op0, op1);
2426 code = swap_condition (code);
2428 if (code == GE)
2430 if (TARGET_IEEE)
2432 lab = gen_label_rtx ();
2433 sh_emit_scc_to_t (EQ, op0, op1);
2434 emit_jump_insn (gen_branch_true (lab));
2435 code = GT;
2437 else
2439 code = LT;
2440 invert = true;
2445 if (code == NE)
2447 code = EQ;
2448 invert = true;
2451 sh_emit_scc_to_t (code, op0, op1);
2452 if (lab)
2453 emit_label (lab);
2454 if (invert)
2455 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
2456 else
2457 emit_move_insn (operands[0], get_t_reg_rtx ());
2460 /* Functions to output assembly code. */
2462 /* Return a sequence of instructions to perform DI or DF move.
2464 Since the SH cannot move a DI or DF in one instruction, we have
2465 to take care when we see overlapping source and dest registers. */
2466 const char *
2467 output_movedouble (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
2468 machine_mode mode)
2470 rtx dst = operands[0];
2471 rtx src = operands[1];
2473 if (MEM_P (dst)
2474 && GET_CODE (XEXP (dst, 0)) == PRE_DEC)
2475 return "mov.l %T1,%0" "\n"
2476 " mov.l %1,%0";
2478 if (register_operand (dst, mode)
2479 && register_operand (src, mode))
2481 if (REGNO (src) == MACH_REG)
2482 return "sts mach,%S0" "\n"
2483 " sts macl,%R0";
2485 /* When mov.d r1,r2 do r2->r3 then r1->r2;
2486 when mov.d r1,r0 do r1->r0 then r2->r1. */
2487 if (REGNO (src) + 1 == REGNO (dst))
2488 return "mov %T1,%T0" "\n"
2489 " mov %1,%0";
2490 else
2491 return "mov %1,%0" "\n"
2492 " mov %T1,%T0";
2494 else if (CONST_INT_P (src))
2496 if (INTVAL (src) < 0)
2497 output_asm_insn ("mov #-1,%S0", operands);
2498 else
2499 output_asm_insn ("mov #0,%S0", operands);
2501 return "mov %1,%R0";
2503 else if (MEM_P (src))
2505 int ptrreg = -1;
2506 int dreg = REGNO (dst);
2507 rtx inside = XEXP (src, 0);
2509 switch (GET_CODE (inside))
2511 case REG:
2512 ptrreg = REGNO (inside);
2513 break;
2515 case SUBREG:
2516 ptrreg = subreg_regno (inside);
2517 break;
2519 case PLUS:
2520 ptrreg = REGNO (XEXP (inside, 0));
2521 /* ??? A r0+REG address shouldn't be possible here, because it isn't
2522 an offsettable address. Unfortunately, offsettable addresses use
2523 QImode to check the offset, and a QImode offsettable address
2524 requires r0 for the other operand, which is not currently
2525 supported, so we can't use the 'o' constraint.
2526 Thus we must check for and handle r0+REG addresses here.
2527 We punt for now, since this is likely very rare. */
2528 gcc_assert (!REG_P (XEXP (inside, 1)));
2529 break;
2531 case LABEL_REF:
2532 return "mov.l %1,%0" "\n"
2533 " mov.l %1+4,%T0";
2534 case POST_INC:
2535 return "mov.l %1,%0" "\n"
2536 " mov.l %1,%T0";
2537 default:
2538 gcc_unreachable ();
2541 /* Work out the safe way to copy. Copy into the second half first. */
2542 if (dreg == ptrreg)
2543 return "mov.l %T1,%T0" "\n"
2544 " mov.l %1,%0";
2547 return "mov.l %1,%0" "\n"
2548 " mov.l %T1,%T0";
2551 /* Print an instruction which would have gone into a delay slot after
2552 another instruction, but couldn't because the other instruction expanded
2553 into a sequence where putting the slot insn at the end wouldn't work. */
2554 static void
2555 print_slot (rtx_sequence *seq)
2557 final_scan_insn (seq->insn (1), asm_out_file, optimize, 1, NULL);
2559 seq->insn (1)->set_deleted ();
2562 const char *
2563 output_far_jump (rtx_insn *insn, rtx op)
2565 struct { rtx lab, reg, op; } this_jmp;
2566 rtx_code_label *braf_base_lab = NULL;
2567 const char *jump;
2568 int far;
2569 int offset = branch_dest (insn) - INSN_ADDRESSES (INSN_UID (insn));
2570 rtx_insn *prev;
2572 this_jmp.lab = gen_label_rtx ();
2574 if (TARGET_SH2
2575 && offset >= -32764
2576 && offset - get_attr_length (insn) <= 32766
2577 && ! CROSSING_JUMP_P (insn))
2579 far = 0;
2580 jump = "mov.w %O0,%1" "\n"
2581 " braf %1";
2583 else
2585 far = 1;
2586 if (flag_pic)
2588 if (TARGET_SH2)
2589 jump = "mov.l %O0,%1" "\n"
2590 " braf %1";
2591 else
2592 jump = "mov.l r0,@-r15" "\n"
2593 " mova %O0,r0" "\n"
2594 " mov.l @r0,%1" "\n"
2595 " add r0,%1" "\n"
2596 " mov.l @r15+,r0" "\n"
2597 " jmp @%1";
2599 else
2600 jump = "mov.l %O0,%1" "\n"
2601 " jmp @%1";
2603 /* If we have a scratch register available, use it. */
2604 if (NONJUMP_INSN_P ((prev = prev_nonnote_insn (insn)))
2605 && INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
2607 this_jmp.reg = SET_DEST (XVECEXP (PATTERN (prev), 0, 0));
2608 if (REGNO (this_jmp.reg) == R0_REG && flag_pic && ! TARGET_SH2)
2609 jump = "mov.l r1,@-r15" "\n"
2610 " mova %O0,r0" "\n"
2611 " mov.l @r0,r1" "\n"
2612 " add r1,r0" "\n"
2613 " mov.l @r15+,r1" "\n"
2614 " jmp @%1";
2615 output_asm_insn (jump, &this_jmp.lab);
2616 if (dbr_sequence_length ())
2617 print_slot (final_sequence);
2618 else
2619 output_asm_insn ("nop", 0);
2621 else
2623 /* Output the delay slot insn first if any. */
2624 if (dbr_sequence_length ())
2625 print_slot (final_sequence);
2627 this_jmp.reg = gen_rtx_REG (SImode, 13);
2628 output_asm_insn ("mov.l r13,@-r15", 0);
2629 output_asm_insn (jump, &this_jmp.lab);
2630 output_asm_insn ("mov.l @r15+,r13", 0);
2632 if (far && flag_pic && TARGET_SH2)
2634 braf_base_lab = gen_label_rtx ();
2635 (*targetm.asm_out.internal_label) (asm_out_file, "L",
2636 CODE_LABEL_NUMBER (braf_base_lab));
2638 if (far)
2639 output_asm_insn (".align 2", 0);
2640 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (this_jmp.lab));
2641 this_jmp.op = op;
2642 if (far && flag_pic)
2644 if (TARGET_SH2)
2645 this_jmp.lab = braf_base_lab;
2646 output_asm_insn (".long %O2-%O0", &this_jmp.lab);
2648 else
2649 output_asm_insn (far ? ".long %O2" : ".word %O2-%O0", &this_jmp.lab);
2650 return "";
2653 /* Local label counter, used for constants in the pool and inside
2654 pattern branches. */
2655 static int lf = 100;
2657 /* Output code for ordinary branches. */
2658 const char *
2659 output_branch (int logic, rtx_insn *insn, rtx *operands)
2661 switch (get_attr_length (insn))
2663 case 6:
2664 /* This can happen if filling the delay slot has caused a forward
2665 branch to exceed its range (we could reverse it, but only
2666 when we know we won't overextend other branches; this should
2667 best be handled by relaxation).
2668 It can also happen when other condbranches hoist delay slot insn
2669 from their destination, thus leading to code size increase.
2670 But the branch will still be in the range -4092..+4098 bytes. */
2671 if (! TARGET_RELAX)
2673 int label = lf++;
2674 /* The call to print_slot will clobber the operands. */
2675 rtx op0 = operands[0];
2677 /* If the instruction in the delay slot is annulled (true), then
2678 there is no delay slot where we can put it now. The only safe
2679 place for it is after the label. final will do that by default. */
2681 if (final_sequence
2682 && ! INSN_ANNULLED_BRANCH_P (final_sequence->insn (0))
2683 && get_attr_length (final_sequence->insn (1)))
2685 asm_fprintf (asm_out_file, "\tb%s%ss\t%LLF%d\n", logic ? "f" : "t",
2686 ASSEMBLER_DIALECT ? "/" : ".", label);
2687 print_slot (final_sequence);
2689 else
2690 asm_fprintf (asm_out_file, "\tb%s\t%LLF%d\n", logic ? "f" : "t", label);
2692 output_asm_insn ("bra\t%l0", &op0);
2693 fprintf (asm_out_file, "\tnop\n");
2694 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2696 return "";
2698 /* FALLTHRU */
2699 /* When relaxing, handle this like a short branch. The linker
2700 will fix it up if it still doesn't fit after relaxation. */
2701 case 2:
2702 return logic ? "bt%.\t%l0" : "bf%.\t%l0";
2704 /* These are for SH2e, in which we have to account for the
2705 extra nop because of the hardware bug in annulled branches. */
2706 case 8:
2707 if (! TARGET_RELAX)
2709 int label = lf++;
2711 gcc_assert (!final_sequence
2712 || !(INSN_ANNULLED_BRANCH_P
2713 (XVECEXP (final_sequence, 0, 0))));
2714 asm_fprintf (asm_out_file, "b%s%ss\t%LLF%d\n",
2715 logic ? "f" : "t",
2716 ASSEMBLER_DIALECT ? "/" : ".", label);
2717 fprintf (asm_out_file, "\tnop\n");
2718 output_asm_insn ("bra\t%l0", operands);
2719 fprintf (asm_out_file, "\tnop\n");
2720 (*targetm.asm_out.internal_label) (asm_out_file, "LF", label);
2722 return "";
2724 /* FALLTHRU */
2725 case 4:
2727 char buffer[10];
2729 sprintf (buffer, "b%s%ss\t%%l0",
2730 logic ? "t" : "f",
2731 ASSEMBLER_DIALECT ? "/" : ".");
2732 output_asm_insn (buffer, &operands[0]);
2733 return "nop";
2736 default:
2737 /* There should be no longer branches now - that would
2738 indicate that something has destroyed the branches set
2739 up in machine_dependent_reorg. */
2740 gcc_unreachable ();
2744 /* Output a code sequence for INSN using TEMPL with OPERANDS; but before,
2745 fill in operands 9 as a label to the successor insn.
2746 We try to use jump threading where possible.
2747 IF CODE matches the comparison in the IF_THEN_ELSE of a following jump,
2748 we assume the jump is taken. I.e. EQ means follow jmp and bf, NE means
2749 follow jmp and bt, if the address is in range. */
2750 const char *
2751 output_branchy_insn (enum rtx_code code, const char *templ,
2752 rtx_insn *insn, rtx *operands)
2754 rtx_insn *next_insn = NEXT_INSN (insn);
2756 if (next_insn && JUMP_P (next_insn) && condjump_p (next_insn))
2758 rtx src = SET_SRC (PATTERN (next_insn));
2759 if (GET_CODE (src) == IF_THEN_ELSE && GET_CODE (XEXP (src, 0)) != code)
2761 /* Following branch not taken */
2762 rtx_code_label *lab = gen_label_rtx ();
2763 emit_label_after (lab, next_insn);
2764 INSN_ADDRESSES_NEW (lab,
2765 INSN_ADDRESSES (INSN_UID (next_insn))
2766 + get_attr_length (next_insn));
2767 operands[9] = lab;
2768 return templ;
2770 else
2772 int offset = (branch_dest (next_insn)
2773 - INSN_ADDRESSES (INSN_UID (next_insn)) + 4);
2774 if (offset >= -252 && offset <= 258)
2776 if (GET_CODE (src) == IF_THEN_ELSE)
2777 /* branch_true */
2778 src = XEXP (src, 1);
2779 operands[9] = src;
2780 return templ;
2784 rtx_code_label *lab = gen_label_rtx ();
2785 emit_label_after (lab, insn);
2786 INSN_ADDRESSES_NEW (lab,
2787 INSN_ADDRESSES (INSN_UID (insn))
2788 + get_attr_length (insn));
2789 operands[9] = lab;
2790 return templ;
2793 const char *
2794 output_ieee_ccmpeq (rtx_insn *insn, rtx *operands)
2796 return output_branchy_insn (NE, "bt %l9" "\n"
2797 " fcmp/eq %1,%0",
2798 insn, operands);
2801 /* Output the start of the assembler file. */
2802 static void
2803 sh_file_start (void)
2805 default_file_start ();
2807 if (TARGET_ELF)
2808 /* We need to show the text section with the proper
2809 attributes as in TEXT_SECTION_ASM_OP, before dwarf2out
2810 emits it without attributes in TEXT_SECTION_ASM_OP, else GAS
2811 will complain. We can teach GAS specifically about the
2812 default attributes for our choice of text section, but
2813 then we would have to change GAS again if/when we change
2814 the text section name. */
2815 fprintf (asm_out_file, "%s\n", TEXT_SECTION_ASM_OP);
2816 else
2817 /* Switch to the data section so that the coffsem symbol
2818 isn't in the text section. */
2819 switch_to_section (data_section);
2821 if (TARGET_LITTLE_ENDIAN)
2822 fputs ("\t.little\n", asm_out_file);
2825 /* Implementation of TARGET_ASM_INTEGER for SH. Pointers to functions
2826 need to be output as pointers to function descriptors for
2827 FDPIC. */
2829 static bool
2830 sh_assemble_integer (rtx value, unsigned int size, int aligned_p)
2832 if (TARGET_FDPIC && size == UNITS_PER_WORD
2833 && GET_CODE (value) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (value))
2835 fputs ("\t.long\t", asm_out_file);
2836 output_addr_const (asm_out_file, value);
2837 fputs ("@FUNCDESC\n", asm_out_file);
2838 return true;
2840 return default_assemble_integer (value, size, aligned_p);
2843 /* Check if PAT includes UNSPEC_CALLER unspec pattern. */
2844 static bool
2845 unspec_caller_rtx_p (rtx pat)
2847 rtx base, offset;
2848 split_const (pat, &base, &offset);
2850 if (GET_CODE (base) == UNSPEC)
2852 if (XINT (base, 1) == UNSPEC_CALLER)
2853 return true;
2854 for (int i = 0; i < XVECLEN (base, 0); i++)
2855 if (unspec_caller_rtx_p (XVECEXP (base, 0, i)))
2856 return true;
2858 return false;
2861 /* Indicate that INSN cannot be duplicated. This is true for insn
2862 that generates a unique label. */
2863 static bool
2864 sh_cannot_copy_insn_p (rtx_insn *insn)
2866 if (!reload_completed || !flag_pic)
2867 return false;
2869 if (!NONJUMP_INSN_P (insn))
2870 return false;
2871 if (asm_noperands (insn) >= 0)
2872 return false;
2874 rtx pat = PATTERN (insn);
2876 if (GET_CODE (pat) == CLOBBER || GET_CODE (pat) == USE)
2877 return false;
2879 if (TARGET_FDPIC && GET_CODE (pat) == PARALLEL)
2881 rtx t = XVECEXP (pat, 0, XVECLEN (pat, 0) - 1);
2882 if (GET_CODE (t) == USE && unspec_caller_rtx_p (XEXP (t, 0)))
2883 return true;
2886 if (GET_CODE (pat) != SET)
2887 return false;
2888 pat = SET_SRC (pat);
2890 if (unspec_caller_rtx_p (pat))
2891 return true;
2893 return false;
2896 /* Number of instructions used to make an arithmetic right shift by N. */
2897 static const char ashiftrt_insns[] =
2898 { 0,1,2,3,4,5,8,8,8,8,8,8,8,8,8,8,2,3,4,5,8,8,8,8,8,8,8,8,8,8,8,2};
2900 /* Description of a logical left or right shift, when expanded to a sequence
2901 of 1/2/8/16 shifts.
2902 Notice that one bit right shifts clobber the T bit. One bit left shifts
2903 are done with an 'add Rn,Rm' insn and thus do not clobber the T bit. */
2904 enum
2906 ASHL_CLOBBERS_T = 1 << 0,
2907 LSHR_CLOBBERS_T = 1 << 1
2910 struct ashl_lshr_sequence
2912 char insn_count;
2913 signed char amount[6];
2914 char clobbers_t;
2917 static const struct ashl_lshr_sequence ashl_lshr_seq[32] =
2919 { 0, { 0 }, 0 }, // 0
2920 { 1, { 1 }, LSHR_CLOBBERS_T },
2921 { 1, { 2 }, 0 },
2922 { 2, { 2, 1 }, LSHR_CLOBBERS_T },
2923 { 2, { 2, 2 }, 0 }, // 4
2924 { 3, { 2, 1, 2 }, LSHR_CLOBBERS_T },
2925 { 3, { 2, 2, 2 }, 0 },
2926 { 4, { 2, 2, 1, 2 }, LSHR_CLOBBERS_T },
2927 { 1, { 8 }, 0 }, // 8
2928 { 2, { 8, 1 }, LSHR_CLOBBERS_T },
2929 { 2, { 8, 2 }, 0 },
2930 { 3, { 8, 1, 2 }, LSHR_CLOBBERS_T },
2931 { 3, { 8, 2, 2 }, 0 }, // 12
2932 { 4, { 8, 2, 1, 2 }, LSHR_CLOBBERS_T },
2933 { 3, { 8, -2, 8 }, 0 },
2934 { 3, { 8, -1, 8 }, ASHL_CLOBBERS_T },
2935 { 1, { 16 }, 0 }, // 16
2936 { 2, { 16, 1 }, LSHR_CLOBBERS_T },
2937 { 2, { 16, 2 }, 0 },
2938 { 3, { 16, 1, 2 }, LSHR_CLOBBERS_T },
2939 { 3, { 16, 2, 2 }, 0 }, // 20
2940 { 4, { 16, 2, 1, 2 }, LSHR_CLOBBERS_T },
2941 { 3, { 16, -2, 8 }, 0 },
2942 { 3, { 16, -1, 8 }, ASHL_CLOBBERS_T },
2943 { 2, { 16, 8 }, 0 }, // 24
2944 { 3, { 16, 1, 8 }, LSHR_CLOBBERS_T },
2945 { 3, { 16, 8, 2 }, 0 },
2946 { 4, { 16, 8, 1, 2 }, LSHR_CLOBBERS_T },
2947 { 4, { 16, 8, 2, 2 }, 0 }, // 28
2948 { 4, { 16, -1, -2, 16 }, ASHL_CLOBBERS_T },
2949 { 3, { 16, -2, 16 }, 0 },
2951 /* For a right shift by 31 a 2 insn shll-movt sequence can be used.
2952 For a left shift by 31 a 2 insn and-rotl sequences can be used.
2953 However, the shift-and combiner code needs this entry here to be in
2954 terms of real shift insns. */
2955 { 3, { 16, -1, 16 }, ASHL_CLOBBERS_T }
2958 /* Individual shift amounts for shift amounts < 16, up to three highmost
2959 bits might be clobbered. This is typically used when combined with some
2960 kind of sign or zero extension. */
2961 static const struct ashl_lshr_sequence ext_ashl_lshr_seq[32] =
2963 { 0, { 0 }, 0 }, // 0
2964 { 1, { 1 }, LSHR_CLOBBERS_T },
2965 { 1, { 2 }, 0 },
2966 { 2, { 2, 1 }, LSHR_CLOBBERS_T },
2967 { 2, { 2, 2 }, 0 }, // 4
2968 { 3, { 2, 1, 2 }, LSHR_CLOBBERS_T },
2969 { 2, { 8, -2 }, 0 },
2970 { 2, { 8, -1 }, ASHL_CLOBBERS_T },
2971 { 1, { 8 }, 0 }, // 8
2972 { 2, { 8, 1 }, LSHR_CLOBBERS_T },
2973 { 2, { 8, 2 }, 0 },
2974 { 3, { 8, 1, 2 }, LSHR_CLOBBERS_T },
2975 { 3, { 8, 2, 2 }, 0 }, // 12
2976 { 3, { 16, -2, -1 }, ASHL_CLOBBERS_T },
2977 { 2, { 16, -2 }, 0 },
2978 { 2, { 16, -1 }, ASHL_CLOBBERS_T },
2979 { 1, { 16 }, 0 }, // 16
2980 { 2, { 16, 1 }, LSHR_CLOBBERS_T },
2981 { 2, { 16, 2 }, 0 },
2982 { 3, { 16, 1, 2 }, LSHR_CLOBBERS_T },
2983 { 3, { 16, 2, 2 }, 0 }, // 20
2984 { 4, { 16, 2, 1, 2 }, LSHR_CLOBBERS_T },
2985 { 3, { 16, -2, 8 }, 0 },
2986 { 3, { 16, -1, 8 }, ASHL_CLOBBERS_T },
2987 { 2, { 16, 8 }, 0 }, // 24
2988 { 3, { 16, 1, 8 }, LSHR_CLOBBERS_T },
2989 { 3, { 16, 8, 2 }, 0 },
2990 { 4, { 16, 8, 1, 2 }, LSHR_CLOBBERS_T },
2991 { 4, { 16, 8, 2, 2 }, 0 }, // 28
2992 { 4, { 16, -1, -2, 16 }, ASHL_CLOBBERS_T },
2993 { 3, { 16, -2, 16 }, 0 },
2994 { 3, { 16, -1, 16 }, ASHL_CLOBBERS_T }
2997 /* Return true if a shift left consisting of 1/2/8/16 shift instructions
2998 will clobber the T bit. */
2999 bool
3000 sh_ashlsi_clobbers_t_reg_p (rtx shift_amount)
3002 gcc_assert (CONST_INT_P (shift_amount));
3004 const int shift_amount_i = INTVAL (shift_amount) & 31;
3006 /* Special case for shift count of 31: use and-rotl sequence. */
3007 if (shift_amount_i == 31)
3008 return true;
3010 return (ashl_lshr_seq[shift_amount_i].clobbers_t
3011 & ASHL_CLOBBERS_T) != 0;
3014 /* Return true if a logical right shift consisting of 1/2/8/16 shift
3015 instructions will clobber the T bit. */
3016 bool
3017 sh_lshrsi_clobbers_t_reg_p (rtx shift_amount)
3019 gcc_assert (CONST_INT_P (shift_amount));
3021 /* For right shifts the constant might be negative. */
3022 const int shift_amount_i = std::abs (INTVAL (shift_amount)) & 31;
3024 /* Special case for shift count of 31: use shll-movt sequence. */
3025 if (shift_amount_i == 31)
3026 return true;
3028 return (ashl_lshr_seq[shift_amount_i].clobbers_t
3029 & LSHR_CLOBBERS_T) != 0;
3032 /* Return true if it is potentially beneficial to use a dynamic shift
3033 instruction (shad / shar) instead of a combination of 1/2/8/16
3034 shift instructions for the specified shift count.
3035 If dynamic shifts are not available, always return false. */
3036 bool
3037 sh_dynamicalize_shift_p (rtx count)
3039 gcc_assert (CONST_INT_P (count));
3041 /* For right shifts the constant might be negative. */
3042 const int shift_amount_i = std::abs (INTVAL (count)) & 31;
3043 int insn_count;
3045 /* For left and right shifts, there are shorter 2 insn sequences for
3046 shift amounts of 31. */
3047 if (shift_amount_i == 31)
3048 insn_count = 2;
3049 else
3050 insn_count = ashl_lshr_seq[shift_amount_i].insn_count;
3052 return TARGET_DYNSHIFT && (insn_count > 1 + SH_DYNAMIC_SHIFT_COST);
3055 /* Assuming we have a value that has been sign-extended by at least one bit,
3056 can we use the ext_shift_amounts with the last shift turned to an
3057 arithmetic shift to shift it by N without data loss, and quicker than by
3058 other means? */
3059 #define EXT_SHIFT_SIGNED(n) (((n) | 8) == 15)
3061 /* Return the cost of a shift. */
3062 static inline int
3063 shiftcosts (rtx x)
3065 if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
3067 if (GET_MODE (x) == DImode
3068 && CONST_INT_P (XEXP (x, 1))
3069 && INTVAL (XEXP (x, 1)) == 1)
3070 return 2;
3072 /* Everything else is invalid, because there is no pattern for it. */
3073 return -1;
3075 /* If shift by a non constant, then this will be expensive. */
3076 if (!CONST_INT_P (XEXP (x, 1)))
3077 return SH_DYNAMIC_SHIFT_COST;
3079 /* Otherwise, return the true cost in instructions. Cope with out of range
3080 shift counts more or less arbitrarily. */
3081 int value = INTVAL (XEXP (x, 1)) & 31;
3083 if (GET_CODE (x) == ASHIFTRT)
3085 int cost = ashiftrt_insns[value];
3086 /* If dynamic shifts are available and profitable in this case, then we
3087 put the constant in a reg and use shad. */
3088 if (cost > 1 + SH_DYNAMIC_SHIFT_COST)
3089 cost = 1 + SH_DYNAMIC_SHIFT_COST;
3090 return cost;
3092 else
3093 return ashl_lshr_seq[value].insn_count;
3096 /* Return the cost of an AND/XOR/IOR operation. */
3097 static inline int
3098 and_xor_ior_costs (rtx x, int code)
3100 /* On SH1-4 we have only max. SImode operations.
3101 Double the cost for modes > SImode. */
3102 const int cost_scale = GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD ? 2 : 1;
3104 /* A logical operation with two registers is a single cycle
3105 instruction. */
3106 if (!CONST_INT_P (XEXP (x, 1)))
3107 return 1 * cost_scale;
3109 int i = INTVAL (XEXP (x, 1));
3111 /* These constants are single cycle extu.[bw] instructions. */
3112 if ((i == 0xff || i == 0xffff) && code == AND)
3113 return 1 * cost_scale;
3114 /* Constants that can be used in an instruction as an immediate are
3115 a single cycle, but this requires r0, so make it a little more
3116 expensive. */
3117 if (CONST_OK_FOR_K08 (i))
3118 return 2 * cost_scale;
3119 /* Constants that can be loaded with a mov immediate need one more cycle.
3120 This case is probably unnecessary. */
3121 if (CONST_OK_FOR_I08 (i))
3122 return 2 * cost_scale;
3123 /* Any other constant requires an additional 2 cycle pc-relative load.
3124 This case is probably unnecessary. */
3125 return 3 * cost_scale;
3128 /* Return the cost of an addition or a subtraction. */
3129 static inline int
3130 addsubcosts (rtx x)
3132 if (GET_MODE (x) == SImode)
3134 /* The addc or subc patterns will eventually become one or two
3135 instructions. Below are some costs for some of the patterns
3136 which combine would reject because the costs of the individual
3137 insns in the patterns are lower.
3139 FIXME: It would be much easier if we had something like insn cost
3140 attributes and the cost calculation machinery used those attributes
3141 in the first place. This would eliminate redundant recog-like C
3142 code to calculate costs of complex patterns. */
3143 rtx op0 = XEXP (x, 0);
3144 rtx op1 = XEXP (x, 1);
3146 if (GET_CODE (x) == PLUS)
3148 if (GET_CODE (op0) == AND
3149 && XEXP (op0, 1) == const1_rtx
3150 && (GET_CODE (op1) == PLUS
3151 || (GET_CODE (op1) == MULT && XEXP (op1, 1) == const2_rtx)))
3152 return 1;
3154 if (GET_CODE (op0) == MULT && XEXP (op0, 1) == const2_rtx
3155 && GET_CODE (op1) == LSHIFTRT
3156 && CONST_INT_P (XEXP (op1, 1)) && INTVAL (XEXP (op1, 1)) == 31)
3157 return 1;
3159 /* Let's assume that adding the result of an insns that stores into
3160 the T bit is cheap. */
3161 if (treg_set_expr (op1, SImode))
3162 return 1;
3163 if (treg_set_expr (op0, SImode))
3164 return 1;
3167 /* On SH1-4 we have only max. SImode operations.
3168 Double the cost for modes > SImode. */
3169 const int cost_scale = GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD ? 2 : 1;
3171 /* Adding a register is a single cycle insn. */
3172 if (REG_P (XEXP (x, 1))
3173 || GET_CODE (XEXP (x, 1)) == SUBREG)
3174 return 1 * cost_scale;
3176 /* Likewise for small constants. */
3177 if (CONST_INT_P (XEXP (x, 1))
3178 && CONST_OK_FOR_ADD (INTVAL (XEXP (x, 1))))
3179 return 1 * cost_scale;
3181 /* Any other constant requires a 2 cycle pc-relative load plus an
3182 addition. */
3183 return 3 * cost_scale;
3186 /* Return the cost of a multiply. */
3187 static inline int
3188 multcosts (rtx x ATTRIBUTE_UNUSED)
3190 if (sh_multcost >= 0)
3191 return sh_multcost;
3193 if (TARGET_SH2)
3195 /* We have a mul insn, so we can never take more than the mul and the
3196 read of the mac reg, but count more because of the latency and extra
3197 reg usage. */
3198 if (optimize_size)
3199 return 2;
3200 return 3;
3203 /* If we're aiming at small code, then just count the number of
3204 insns in a multiply call sequence. */
3205 if (optimize_size)
3206 return 5;
3208 /* Otherwise count all the insns in the routine we'd be calling too. */
3209 return 20;
3212 /* Compute a (partial) cost for rtx X. Return true if the complete
3213 cost has been computed, and false if subexpressions should be
3214 scanned. In either case, *TOTAL contains the cost result. */
3215 static bool
3216 sh_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code,
3217 int opno ATTRIBUTE_UNUSED,
3218 int *total, bool speed ATTRIBUTE_UNUSED)
3220 int code = GET_CODE (x);
3222 switch (code)
3224 /* The lower-subreg pass decides whether to split multi-word regs
3225 into individual regs by looking at the cost for a SET of certain
3226 modes with the following patterns:
3227 (set (reg) (reg))
3228 (set (reg) (const_int 0))
3229 On machines that support vector-move operations a multi-word move
3230 is the same cost as individual reg move. On SH there is no
3231 vector-move, so we have to provide the correct cost in the number
3232 of move insns to load/store the reg of the mode in question. */
3233 case SET:
3234 if (sh_movt_set_dest (x) != NULL || sh_movrt_set_dest (x) != NULL)
3236 *total = COSTS_N_INSNS (1);
3237 return true;
3240 if (register_operand (SET_DEST (x), VOIDmode)
3241 && (register_operand (SET_SRC (x), VOIDmode)
3242 || satisfies_constraint_Z (SET_SRC (x))))
3244 const machine_mode mode = GET_MODE (SET_DEST (x));
3245 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode)
3246 / mov_insn_size (mode, TARGET_SH2A));
3247 return true;
3249 return false;
3251 /* The cost of a mem access is mainly the cost of the address mode. */
3252 case MEM:
3253 *total = sh_address_cost (XEXP (x, 0), GET_MODE (x), MEM_ADDR_SPACE (x),
3254 true);
3255 return true;
3257 case IF_THEN_ELSE:
3258 /* This case is required for the if_then_else negc pattern. */
3259 if (treg_set_expr (XEXP (x, 0), SImode))
3261 *total = COSTS_N_INSNS (1);
3262 return true;
3264 else
3265 return false;
3267 /* Zero extracts of single bits are usually combine patterns for the
3268 tst insns. */
3269 case ZERO_EXTRACT:
3270 if (GET_CODE (XEXP (x, 0)) == XOR
3271 && arith_reg_operand (XEXP (XEXP (x, 0), 0), VOIDmode)
3272 && XEXP (x, 1) == const1_rtx
3273 && CONST_INT_P (XEXP (x, 2))
3274 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
3275 /* Check that the xor constaint overlaps with the extracted bit. */
3276 && (INTVAL (XEXP (XEXP (x, 0), 1)) & (1LL << INTVAL (XEXP (x, 2)))))
3278 *total = 1; //COSTS_N_INSNS (1);
3279 return true;
3282 /* div0s variant. */
3283 if (GET_CODE (XEXP (x, 0)) == XOR
3284 && GET_CODE (XEXP (XEXP (x, 0), 0)) == XOR
3285 && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
3287 *total = 1;
3288 return true;
3290 return false;
3292 /* The cost of a sign or zero extend depends on whether the source is a
3293 reg or a mem. In case of a mem take the address into account. */
3294 case SIGN_EXTEND:
3295 if (arith_reg_operand (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
3297 *total = COSTS_N_INSNS (1);
3298 return true;
3300 if (MEM_P (XEXP (x, 0)))
3302 *total = sh_address_cost (XEXP (XEXP (x, 0), 0),
3303 GET_MODE (XEXP (x, 0)),
3304 MEM_ADDR_SPACE (XEXP (x, 0)), true);
3305 return true;
3307 return false;
3309 case ZERO_EXTEND:
3310 if (arith_reg_operand (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
3312 *total = COSTS_N_INSNS (1);
3313 return true;
3315 else if (TARGET_SH2A && MEM_P (XEXP (x, 0))
3316 && (GET_MODE (XEXP (x, 0)) == QImode
3317 || GET_MODE (XEXP (x, 0)) == HImode))
3319 /* Handle SH2A's movu.b and movu.w insn. */
3320 *total = sh_address_cost (XEXP (XEXP (x, 0), 0),
3321 GET_MODE (XEXP (x, 0)),
3322 MEM_ADDR_SPACE (XEXP (x, 0)), true);
3323 return true;
3325 return false;
3327 /* mems for SFmode and DFmode can be inside a parallel due to
3328 the way the fpscr is handled. */
3329 case PARALLEL:
3330 for (int i = 0; i < XVECLEN (x, 0); i++)
3332 rtx xx = XVECEXP (x, 0, i);
3333 if (GET_CODE (xx) == SET && MEM_P (XEXP (xx, 0)))
3335 *total = sh_address_cost (XEXP (XEXP (xx, 0), 0),
3336 GET_MODE (XEXP (xx, 0)),
3337 MEM_ADDR_SPACE (XEXP (xx, 0)), true);
3338 return true;
3340 if (GET_CODE (xx) == SET && MEM_P (XEXP (xx, 1)))
3342 *total = sh_address_cost (XEXP (XEXP (xx, 1), 0),
3343 GET_MODE (XEXP (xx, 1)),
3344 MEM_ADDR_SPACE (XEXP (xx, 1)), true);
3345 return true;
3349 if (sh_1el_vec (x, VOIDmode))
3350 *total = outer_code != SET;
3351 else if (sh_rep_vec (x, VOIDmode))
3352 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
3353 + (outer_code != SET));
3354 else
3355 *total = COSTS_N_INSNS (3) + (outer_code != SET);
3356 return true;
3358 case CONST_INT:
3359 if (CONST_OK_FOR_I08 (INTVAL (x)))
3360 *total = 0;
3361 else if ((outer_code == AND || outer_code == IOR || outer_code == XOR)
3362 && CONST_OK_FOR_K08 (INTVAL (x)))
3363 *total = 1;
3364 /* prepare_cmp_insn will force costly constants int registers before
3365 the cbranch[sd]i4 patterns can see them, so preserve potentially
3366 interesting ones not covered by I08 above. */
3367 else if (outer_code == COMPARE
3368 && ((unsigned HOST_WIDE_INT) INTVAL (x)
3369 == (unsigned HOST_WIDE_INT) 0x7fffffff + 1
3370 || INTVAL (x) == 0x7fffffff
3371 || INTVAL (x) == 0x80 || INTVAL (x) == -0x81))
3372 *total = 1;
3373 else
3374 *total = 8;
3375 return true;
3377 case EQ:
3378 /* An and with a constant compared against zero is
3379 most likely going to be a TST #imm, R0 instruction. */
3380 if (XEXP (x, 1) == const0_rtx
3381 && ((GET_CODE (XEXP (x, 0)) == AND
3382 || (SUBREG_P (XEXP (x, 0))
3383 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == AND))
3384 || GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT))
3386 *total = 1;
3387 return true;
3390 else if (XEXP (x, 1) == const0_rtx
3391 && GET_CODE (XEXP (x, 0)) == AND
3392 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
3393 && GET_CODE (XEXP (XEXP (x, 0), 0)) == ASHIFT
3394 && arith_reg_operand (XEXP (XEXP (XEXP (x, 0), 0), 0), SImode)
3395 && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1)))
3397 *total = 1;
3398 return true;
3400 else
3401 return false;
3403 case SMIN:
3404 case SMAX:
3405 /* This is most likely a clips.b or clips.w insn that is being made up
3406 by combine. */
3407 if (TARGET_SH2A
3408 && (GET_CODE (XEXP (x, 0)) == SMAX || GET_CODE (XEXP (x, 0)) == SMIN)
3409 && CONST_INT_P (XEXP (XEXP (x, 0), 1))
3410 && REG_P (XEXP (XEXP (x, 0), 0))
3411 && CONST_INT_P (XEXP (x, 1)))
3413 *total = COSTS_N_INSNS (1);
3414 return true;
3416 else
3417 return false;
3419 case CONST:
3420 case LABEL_REF:
3421 case SYMBOL_REF:
3422 *total = 5;
3423 return true;
3425 case CONST_DOUBLE:
3426 /* prepare_cmp_insn will force costly constants int registers before
3427 the cbranchdi4 pattern can see them, so preserve potentially
3428 interesting ones. */
3429 if (outer_code == COMPARE && GET_MODE (x) == DImode)
3430 *total = 1;
3431 else
3432 *total = 10;
3433 return true;
3435 case CONST_VECTOR:
3436 /* FIXME: This looks broken. Only the last statement has any effect.
3437 Probably this could be folded with the PARALLEL case? */
3438 if (x == CONST0_RTX (GET_MODE (x)))
3439 *total = 0;
3440 else if (sh_1el_vec (x, VOIDmode))
3441 *total = outer_code != SET;
3442 if (sh_rep_vec (x, VOIDmode))
3443 *total = ((GET_MODE_UNIT_SIZE (GET_MODE (x)) + 3) / 4
3444 + (outer_code != SET));
3445 *total = COSTS_N_INSNS (3) + (outer_code != SET);
3446 return true;
3448 case PLUS:
3449 case MINUS:
3450 *total = COSTS_N_INSNS (addsubcosts (x));
3451 return true;
3453 case AND:
3454 /* Check for (and (not (reg)) (const_int 1)) which is a tst insn. */
3455 if (GET_CODE (XEXP (x, 0)) == NOT && XEXP (x, 1) == const1_rtx)
3457 *total = COSTS_N_INSNS (1);
3458 return true;
3460 /* Fall through. */
3462 case XOR:
3463 case IOR:
3464 *total = COSTS_N_INSNS (and_xor_ior_costs (x, code));
3465 return true;
3467 case MULT:
3468 *total = COSTS_N_INSNS (multcosts (x));
3469 return true;
3471 case LT:
3472 case GE:
3473 /* div0s sign comparison. */
3474 if (GET_CODE (XEXP (x, 0)) == XOR
3475 && REG_P ((XEXP (XEXP (x, 0), 0)))
3476 && REG_P ((XEXP (XEXP (x, 0), 1)))
3477 && satisfies_constraint_Z (XEXP (x, 1)))
3479 *total = COSTS_N_INSNS (1);
3480 return true;
3482 else
3483 return false;
3485 case LSHIFTRT:
3486 /* div0s sign comparison. */
3487 if (GET_CODE (XEXP (x, 0)) == XOR
3488 && REG_P ((XEXP (XEXP (x, 0), 0)))
3489 && REG_P ((XEXP (XEXP (x, 0), 1)))
3490 && CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) == 31)
3492 *total = COSTS_N_INSNS (1);
3493 return true;
3495 /* FALLTHRU */
3496 case ASHIFT:
3497 case ASHIFTRT:
3499 int cost = shiftcosts (x);
3500 if (cost < 0)
3501 return false;
3502 *total = COSTS_N_INSNS (cost);
3503 return true;
3506 case DIV:
3507 case UDIV:
3508 case MOD:
3509 case UMOD:
3510 *total = COSTS_N_INSNS (20);
3511 return true;
3513 case FLOAT:
3514 case FIX:
3515 *total = 100;
3516 return true;
3518 default:
3519 return false;
3523 /* Determine the size of the fundamental move insn that will be used
3524 for the specified mode. */
3525 static inline int
3526 mov_insn_size (machine_mode mode, bool consider_sh2a)
3528 const int mode_sz = GET_MODE_SIZE (mode);
3530 if ((consider_sh2a && TARGET_SH2A_DOUBLE && mode == DFmode)
3531 || (TARGET_FMOVD && mode == DFmode))
3532 return mode_sz;
3533 else
3535 /* The max. available mode for actual move insns is SImode.
3536 Larger accesses will be split into multiple loads/stores. */
3537 const int max_mov_sz = GET_MODE_SIZE (SImode);
3538 return mode_sz >= max_mov_sz ? max_mov_sz : mode_sz;
3542 /* Determine the maximum possible displacement for a move insn for the
3543 specified mode. */
3545 sh_max_mov_insn_displacement (machine_mode mode, bool consider_sh2a)
3547 /* The 4 byte displacement move insns are the same as the 2 byte
3548 versions but take a 12 bit displacement. All we need to do is to
3549 scale the max. displacement value accordingly. */
3550 const int disp_scale = consider_sh2a ? (4095 / 15) : 1;
3552 /* SH2A supports FPU move insns with 12 bit displacements.
3553 Other variants to do not support any kind of displacements for
3554 FPU move insns. */
3555 if (! consider_sh2a && TARGET_FPU_ANY && GET_MODE_CLASS (mode) == MODE_FLOAT)
3556 return 0;
3557 else
3559 const int mov_insn_sz = mov_insn_size (mode, consider_sh2a);
3560 const int mode_sz = GET_MODE_SIZE (mode);
3561 int r = 15 * mov_insn_sz * disp_scale;
3563 /* If the mov insn will be split into multiple loads/stores, the
3564 maximum possible displacement is a bit smaller. */
3565 if (mode_sz > mov_insn_sz)
3566 r -= mode_sz - mov_insn_sz;
3567 return r;
3571 /* Determine the alignment mask for a move insn of the
3572 specified mode. */
3573 static inline int
3574 mov_insn_alignment_mask (machine_mode mode, bool consider_sh2a)
3576 const int mov_insn_sz = mov_insn_size (mode, consider_sh2a);
3577 return mov_insn_sz > 0 ? (mov_insn_sz - 1) : 0;
3580 /* Return the displacement value of a displacement address. */
3581 HOST_WIDE_INT
3582 sh_disp_addr_displacement (rtx x)
3584 gcc_assert (satisfies_constraint_Sdd (x));
3585 return INTVAL (XEXP (XEXP (x, 0), 1));
3588 /* Compute the cost of an address. */
3589 static int
3590 sh_address_cost (rtx x, machine_mode mode,
3591 addr_space_t as ATTRIBUTE_UNUSED, bool speed ATTRIBUTE_UNUSED)
3593 /* 'GBR + 0'. Account one more because of R0 restriction. */
3594 if (REG_P (x) && REGNO (x) == GBR_REG)
3595 return 2;
3597 /* Simple reg, post-inc, pre-dec addressing. */
3598 if (REG_P (x) || GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
3599 return 1;
3601 /* 'reg + disp' addressing. */
3602 if (GET_CODE (x) == PLUS
3603 && REG_P (XEXP (x, 0)) && CONST_INT_P (XEXP (x, 1)))
3605 /* 'GBR + disp'. Account one more because of R0 restriction. */
3606 if (REGNO (XEXP (x, 0)) == GBR_REG
3607 && gbr_displacement (XEXP (x, 1), mode))
3608 return 2;
3610 const HOST_WIDE_INT offset = INTVAL (XEXP (x, 1));
3612 if (offset == 0)
3613 return 1;
3615 /* The displacement would fit into a 2 byte move insn.
3616 HImode and QImode loads/stores with displacement put pressure on
3617 R0 which will most likely require another reg copy. Thus account
3618 a higher cost for that. */
3619 if (offset > 0 && offset <= sh_max_mov_insn_displacement (mode, false))
3620 return (mode == HImode || mode == QImode) ? 2 : 1;
3622 /* The displacement would fit into a 4 byte move insn (SH2A). */
3623 if (TARGET_SH2A
3624 && offset > 0 && offset <= sh_max_mov_insn_displacement (mode, true))
3625 return 2;
3627 /* The displacement is probably out of range and will require extra
3628 calculations. */
3629 return 3;
3632 /* 'reg + reg' addressing. Account a slightly higher cost because of
3633 increased pressure on R0. */
3634 if (GET_CODE (x) == PLUS && ! CONSTANT_P (XEXP (x, 1)))
3635 return 3;
3637 /* Not sure what it is - probably expensive. */
3638 return 10;
3641 /* Code to expand a shift. */
3642 static void
3643 gen_ashift (int type, int n, rtx reg)
3645 rtx n_rtx;
3647 /* Negative values here come from the shift_amounts array. */
3648 if (n < 0)
3650 if (type == ASHIFT)
3651 type = LSHIFTRT;
3652 else
3653 type = ASHIFT;
3654 n = -n;
3657 n_rtx = GEN_INT (n);
3658 gcc_assert (satisfies_constraint_P27 (n_rtx));
3660 switch (type)
3662 case ASHIFTRT:
3663 emit_insn (gen_ashrsi3_k (reg, reg, n_rtx));
3664 break;
3665 case LSHIFTRT:
3666 if (n == 1)
3667 emit_insn (gen_shlr (reg, reg));
3668 else
3669 emit_insn (gen_lshrsi3_k (reg, reg, n_rtx));
3670 break;
3671 case ASHIFT:
3672 emit_insn (gen_ashlsi3_k (reg, reg, n_rtx));
3673 break;
3674 default:
3675 gcc_unreachable ();
3679 /* Code to expand a HImode shift. */
3680 static void
3681 gen_ashift_hi (int type, int n, rtx reg)
3683 /* Negative values here come from the shift_amounts array. */
3684 if (n < 0)
3686 if (type == ASHIFT)
3687 type = LSHIFTRT;
3688 else
3689 type = ASHIFT;
3690 n = -n;
3693 switch (type)
3695 case ASHIFTRT:
3696 case LSHIFTRT:
3697 /* We don't have HImode right shift operations because using the
3698 ordinary 32 bit shift instructions for that doesn't generate proper
3699 zero/sign extension.
3700 gen_ashift_hi is only called in contexts where we know that the
3701 sign extension works out correctly. */
3703 int offset = 0;
3704 if (GET_CODE (reg) == SUBREG)
3706 offset = SUBREG_BYTE (reg);
3707 reg = SUBREG_REG (reg);
3709 gen_ashift (type, n, gen_rtx_SUBREG (SImode, reg, offset));
3710 break;
3712 case ASHIFT:
3713 emit_insn (gen_ashlhi3_k (reg, reg, GEN_INT (n)));
3714 break;
3718 /* Output RTL to split a constant shift into its component SH constant
3719 shift instructions. */
3720 void
3721 gen_shifty_op (int code, rtx *operands)
3723 int value = INTVAL (operands[2]);
3724 int max, i;
3726 /* Truncate the shift count in case it is out of bounds. */
3727 value = value & 31;
3729 if (value == 31)
3731 if (code == LSHIFTRT)
3733 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
3734 emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
3735 return;
3737 else if (code == ASHIFT)
3739 /* There is a two instruction sequence for 31 bit left shifts,
3740 but it requires r0. */
3741 if (REG_P (operands[0]) && REGNO (operands[0]) == 0)
3743 emit_insn (gen_andsi3 (operands[0], operands[0], const1_rtx));
3744 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
3745 return;
3749 else if (value == 0)
3751 /* This can happen even when optimizing, if there were subregs before
3752 reload. Don't output a nop here, as this is never optimized away;
3753 use a no-op move instead. */
3754 emit_insn (gen_rtx_SET (operands[0], operands[0]));
3755 return;
3758 max = ashl_lshr_seq[value].insn_count;
3759 for (i = 0; i < max; i++)
3760 gen_ashift (code, ashl_lshr_seq[value].amount[i], operands[0]);
3763 /* Same as gen_shifty_op, but optimized for values where the topmost bits
3764 don't matter. */
3765 void
3766 gen_shifty_hi_op (int code, rtx *operands)
3768 int value = INTVAL (operands[2]);
3769 int max, i;
3770 void (*gen_fun) (int, int, rtx);
3772 /* This operation is used by and_shl for SImode values with a few
3773 high bits known to be cleared. */
3774 value &= 31;
3775 if (value == 0)
3777 emit_insn (gen_nop ());
3778 return;
3781 gen_fun = GET_MODE (operands[0]) == HImode ? gen_ashift_hi : gen_ashift;
3782 if (code == ASHIFT)
3784 max = ext_ashl_lshr_seq[value].insn_count;
3785 for (i = 0; i < max; i++)
3786 gen_fun (code, ext_ashl_lshr_seq[value].amount[i], operands[0]);
3788 else
3789 /* When shifting right, emit the shifts in reverse order, so that
3790 solitary negative values come first. */
3791 for (i = ext_ashl_lshr_seq[value].insn_count - 1; i >= 0; i--)
3792 gen_fun (code, ext_ashl_lshr_seq[value].amount[i], operands[0]);
3795 /* Output RTL for an arithmetic right shift.
3796 ??? Rewrite to use super-optimizer sequences. */
3797 bool
3798 expand_ashiftrt (rtx *operands)
3800 rtx wrk;
3801 char func[18];
3802 int value;
3804 if (TARGET_DYNSHIFT)
3806 if (!CONST_INT_P (operands[2]))
3808 rtx count = copy_to_mode_reg (SImode, operands[2]);
3809 emit_insn (gen_negsi2 (count, count));
3810 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3811 return true;
3813 else if (ashiftrt_insns[INTVAL (operands[2]) & 31]
3814 > 1 + SH_DYNAMIC_SHIFT_COST)
3816 rtx count
3817 = force_reg (SImode, GEN_INT (- (INTVAL (operands[2]) & 31)));
3818 emit_insn (gen_ashrsi3_d (operands[0], operands[1], count));
3819 return true;
3822 if (!CONST_INT_P (operands[2]))
3823 return false;
3825 value = INTVAL (operands[2]) & 31;
3827 if (value == 31)
3829 /* If we are called from abs expansion, arrange things so that we
3830 we can use a single MT instruction that doesn't clobber the source,
3831 if LICM can hoist out the load of the constant zero. */
3832 if (currently_expanding_to_rtl)
3834 emit_insn (gen_cmpgtsi_t (force_reg (SImode, CONST0_RTX (SImode)),
3835 operands[1]));
3836 emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ()));
3837 return true;
3839 emit_insn (gen_ashrsi2_31 (operands[0], operands[1]));
3840 return true;
3842 else if (value >= 16 && value <= 19)
3844 wrk = gen_reg_rtx (SImode);
3845 emit_insn (gen_ashrsi2_16 (wrk, operands[1]));
3846 value -= 16;
3847 while (value--)
3848 gen_ashift (ASHIFTRT, 1, wrk);
3849 emit_move_insn (operands[0], wrk);
3850 return true;
3852 /* Expand a short sequence inline, longer call a magic routine. */
3853 else if (value <= 5)
3855 wrk = gen_reg_rtx (SImode);
3856 emit_move_insn (wrk, operands[1]);
3857 while (value--)
3858 gen_ashift (ASHIFTRT, 1, wrk);
3859 emit_move_insn (operands[0], wrk);
3860 return true;
3863 wrk = gen_reg_rtx (Pmode);
3865 /* Load the value into an arg reg and call a helper. */
3866 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
3867 sprintf (func, "__ashiftrt_r4_%d", value);
3868 rtx lab = function_symbol (wrk, func, SFUNC_STATIC).lab;
3869 emit_insn (gen_ashrsi3_n (GEN_INT (value), wrk, lab));
3870 emit_move_insn (operands[0], gen_rtx_REG (SImode, 4));
3871 return true;
3874 /* Try to find a good way to implement the combiner pattern
3875 [(set (match_operand:SI 0 "register_operand" "r")
3876 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
3877 (match_operand:SI 2 "const_int_operand" "n"))
3878 (match_operand:SI 3 "const_int_operand" "n"))) .
3879 LEFT_RTX is operand 2 in the above pattern, and MASK_RTX is operand 3.
3880 return 0 for simple right / left or left/right shift combination.
3881 return 1 for a combination of shifts with zero_extend.
3882 return 2 for a combination of shifts with an AND that needs r0.
3883 return 3 for a combination of shifts with an AND that needs an extra
3884 scratch register, when the three highmost bits of the AND mask are clear.
3885 return 4 for a combination of shifts with an AND that needs an extra
3886 scratch register, when any of the three highmost bits of the AND mask
3887 is set.
3888 If ATTRP is set, store an initial right shift width in ATTRP[0],
3889 and the instruction length in ATTRP[1] . These values are not valid
3890 when returning 0.
3891 When ATTRP is set and returning 1, ATTRP[2] gets set to the index into
3892 shift_amounts for the last shift value that is to be used before the
3893 sign extend. */
3895 shl_and_kind (rtx left_rtx, rtx mask_rtx, int *attrp)
3897 unsigned HOST_WIDE_INT mask, lsb, mask2, lsb2;
3898 int left = INTVAL (left_rtx), right;
3899 int best = 0;
3900 int cost, best_cost = 10000;
3901 int best_right = 0, best_len = 0;
3902 int i;
3903 int can_ext;
3905 if (left < 0 || left > 31)
3906 return 0;
3907 if (CONST_INT_P (mask_rtx))
3908 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> left;
3909 else
3910 mask = (unsigned HOST_WIDE_INT) GET_MODE_MASK (SImode) >> left;
3911 /* Can this be expressed as a right shift / left shift pair? */
3912 lsb = ((mask ^ (mask - 1)) >> 1) + 1;
3913 right = exact_log2 (lsb);
3914 mask2 = ~(mask + lsb - 1);
3915 lsb2 = ((mask2 ^ (mask2 - 1)) >> 1) + 1;
3916 /* mask has no zeroes but trailing zeroes <==> ! mask2 */
3917 if (! mask2)
3918 best_cost = ashl_lshr_seq[right].insn_count
3919 + ashl_lshr_seq[right + left].insn_count;
3920 /* mask has no trailing zeroes <==> ! right */
3921 else if (! right && mask2 == ~(lsb2 - 1))
3923 int late_right = exact_log2 (lsb2);
3924 best_cost = ashl_lshr_seq[left + late_right].insn_count
3925 + ashl_lshr_seq[late_right].insn_count;
3927 /* Try to use zero extend. */
3928 if (mask2 == ~(lsb2 - 1))
3930 int width, first;
3932 for (width = 8; width <= 16; width += 8)
3934 /* Can we zero-extend right away? */
3935 if (lsb2 == (unsigned HOST_WIDE_INT) 1 << width)
3937 cost = 1 + ext_ashl_lshr_seq[right].insn_count
3938 + ext_ashl_lshr_seq[left + right].insn_count;
3939 if (cost < best_cost)
3941 best = 1;
3942 best_cost = cost;
3943 best_right = right;
3944 best_len = cost;
3945 if (attrp)
3946 attrp[2] = -1;
3948 continue;
3950 /* ??? Could try to put zero extend into initial right shift,
3951 or even shift a bit left before the right shift. */
3952 /* Determine value of first part of left shift, to get to the
3953 zero extend cut-off point. */
3954 first = width - exact_log2 (lsb2) + right;
3955 if (first >= 0 && right + left - first >= 0)
3957 cost = ext_ashl_lshr_seq[right].insn_count
3958 + ext_ashl_lshr_seq[first].insn_count + 1
3959 + ext_ashl_lshr_seq[right + left - first].insn_count;
3961 if (cost < best_cost)
3963 best = 1;
3964 best_cost = cost;
3965 best_right = right;
3966 best_len = cost;
3967 if (attrp)
3968 attrp[2] = first;
3973 /* Try to use r0 AND pattern */
3974 for (i = 0; i <= 2; i++)
3976 if (i > right)
3977 break;
3978 if (! CONST_OK_FOR_K08 (mask >> i))
3979 continue;
3980 cost = (i != 0) + 2 + ext_ashl_lshr_seq[left + i].insn_count;
3981 if (cost < best_cost)
3983 best = 2;
3984 best_cost = cost;
3985 best_right = i;
3986 best_len = cost - 1;
3989 /* Try to use a scratch register to hold the AND operand. */
3990 can_ext = ((mask << left) & ((unsigned HOST_WIDE_INT) 3 << 30)) == 0;
3991 for (i = 0; i <= 2; i++)
3993 if (i > right)
3994 break;
3995 cost = (i != 0) + (CONST_OK_FOR_I08 (mask >> i) ? 2 : 3)
3996 + (can_ext
3997 ? ext_ashl_lshr_seq
3998 : ashl_lshr_seq)[left + i].insn_count;
3999 if (cost < best_cost)
4001 best = 4 - can_ext;
4002 best_cost = cost;
4003 best_right = i;
4004 best_len = cost - 1 - ! CONST_OK_FOR_I08 (mask >> i);
4008 if (attrp)
4010 attrp[0] = best_right;
4011 attrp[1] = best_len;
4013 return best;
4016 /* This is used in length attributes of the unnamed instructions
4017 corresponding to shl_and_kind return values of 1 and 2. */
4019 shl_and_length (rtx insn)
4021 rtx set_src, left_rtx, mask_rtx;
4022 int attributes[3];
4024 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
4025 left_rtx = XEXP (XEXP (set_src, 0), 1);
4026 mask_rtx = XEXP (set_src, 1);
4027 shl_and_kind (left_rtx, mask_rtx, attributes);
4028 return attributes[1];
4031 /* This is used in length attribute of the and_shl_scratch instruction. */
4033 shl_and_scr_length (rtx insn)
4035 rtx set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
4036 int len = ashl_lshr_seq[INTVAL (XEXP (set_src, 1)) & 31].insn_count;
4037 rtx op = XEXP (set_src, 0);
4038 len += ashl_lshr_seq[INTVAL (XEXP (op, 1)) & 31].insn_count + 1;
4039 op = XEXP (XEXP (op, 0), 0);
4040 return len + ashl_lshr_seq[INTVAL (XEXP (op, 1)) & 31].insn_count;
4043 /* Generate rtl for instructions for which shl_and_kind advised a particular
4044 method of generating them, i.e. returned zero. */
4045 bool
4046 gen_shl_and (rtx dest, rtx left_rtx, rtx mask_rtx, rtx source)
4048 int attributes[3];
4049 unsigned HOST_WIDE_INT mask;
4050 int kind = shl_and_kind (left_rtx, mask_rtx, attributes);
4051 int right, total_shift;
4052 void (*shift_gen_fun) (int, rtx *) = gen_shifty_hi_op;
4054 right = attributes[0];
4055 total_shift = INTVAL (left_rtx) + right;
4056 mask = (unsigned HOST_WIDE_INT) INTVAL (mask_rtx) >> total_shift;
4057 switch (kind)
4059 default:
4060 return true;
4061 case 1:
4063 int first = attributes[2];
4064 rtx operands[3];
4066 if (first < 0)
4068 emit_insn ((mask << right) <= 0xff
4069 ? gen_zero_extendqisi2 (dest,
4070 gen_lowpart (QImode, source))
4071 : gen_zero_extendhisi2 (dest,
4072 gen_lowpart (HImode, source)));
4073 source = dest;
4075 if (source != dest)
4076 emit_insn (gen_movsi (dest, source));
4077 operands[0] = dest;
4078 if (right)
4080 operands[2] = GEN_INT (right);
4081 gen_shifty_hi_op (LSHIFTRT, operands);
4083 if (first > 0)
4085 operands[2] = GEN_INT (first);
4086 gen_shifty_hi_op (ASHIFT, operands);
4087 total_shift -= first;
4088 mask <<= first;
4090 if (first >= 0)
4091 emit_insn (mask <= 0xff
4092 ? gen_zero_extendqisi2 (dest, gen_lowpart (QImode, dest))
4093 : gen_zero_extendhisi2 (dest, gen_lowpart (HImode, dest)));
4094 if (total_shift > 0)
4096 operands[2] = GEN_INT (total_shift);
4097 gen_shifty_hi_op (ASHIFT, operands);
4099 break;
4101 case 4:
4102 shift_gen_fun = gen_shifty_op;
4103 /* FALLTHRU */
4104 case 3:
4105 /* If the topmost bit that matters is set, set the topmost bits
4106 that don't matter. This way, we might be able to get a shorter
4107 signed constant. */
4108 if (mask & ((HOST_WIDE_INT) 1 << (31 - total_shift)))
4109 mask |= (HOST_WIDE_INT) ((HOST_WIDE_INT_M1U) << (31 - total_shift));
4110 /* FALLTHRU */
4111 case 2:
4112 /* Don't expand fine-grained when combining, because that will
4113 make the pattern fail. */
4114 if (currently_expanding_to_rtl
4115 || reload_in_progress || reload_completed)
4117 rtx operands[3];
4119 /* Cases 3 and 4 should be handled by this split
4120 only while combining */
4121 gcc_assert (kind <= 2);
4122 if (right)
4124 emit_insn (gen_lshrsi3 (dest, source, GEN_INT (right)));
4125 source = dest;
4127 emit_insn (gen_andsi3 (dest, source, GEN_INT (mask)));
4128 if (total_shift)
4130 operands[0] = dest;
4131 operands[1] = dest;
4132 operands[2] = GEN_INT (total_shift);
4133 shift_gen_fun (ASHIFT, operands);
4135 break;
4137 else
4139 int neg = 0;
4140 if (kind != 4 && total_shift < 16)
4142 neg = -ext_ashl_lshr_seq[total_shift].amount[1];
4143 if (neg > 0)
4144 neg -= ext_ashl_lshr_seq[total_shift].amount[2];
4145 else
4146 neg = 0;
4148 emit_insn (gen_and_shl_scratch (dest, source,
4149 GEN_INT (right),
4150 GEN_INT (mask),
4151 GEN_INT (total_shift + neg),
4152 GEN_INT (neg)));
4153 emit_insn (gen_movsi (dest, dest));
4154 break;
4157 return false;
4160 /* Try to find a good way to implement the combiner pattern
4161 [(set (match_operand:SI 0 "register_operand" "=r")
4162 (sign_extract:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
4163 (match_operand:SI 2 "const_int_operand" "n")
4164 (match_operand:SI 3 "const_int_operand" "n")
4165 (const_int 0)))
4166 (clobber (reg:SI T_REG))]
4167 LEFT_RTX is operand 2 in the above pattern, and SIZE_RTX is operand 3.
4168 return 0 for simple left / right shift combination.
4169 return 1 for left shift / 8 bit sign extend / left shift.
4170 return 2 for left shift / 16 bit sign extend / left shift.
4171 return 3 for left shift / 8 bit sign extend / shift / sign extend.
4172 return 4 for left shift / 16 bit sign extend / shift / sign extend.
4173 return 5 for left shift / 16 bit sign extend / right shift
4174 return 6 for < 8 bit sign extend / left shift.
4175 return 7 for < 8 bit sign extend / left shift / single right shift.
4176 If COSTP is nonzero, assign the calculated cost to *COSTP. */
4178 shl_sext_kind (rtx left_rtx, rtx size_rtx, int *costp)
4180 int left, size, insize, ext;
4181 int cost = 0, best_cost;
4182 int kind;
4184 left = INTVAL (left_rtx);
4185 size = INTVAL (size_rtx);
4186 insize = size - left;
4187 gcc_assert (insize > 0);
4188 /* Default to left / right shift. */
4189 kind = 0;
4190 best_cost = ashl_lshr_seq[32 - insize].insn_count
4191 + ashl_lshr_seq[32 - size].insn_count;
4192 if (size <= 16)
4194 /* 16 bit shift / sign extend / 16 bit shift */
4195 cost = ashl_lshr_seq[16 - insize].insn_count + 1
4196 + ashl_lshr_seq[16 - size].insn_count;
4197 /* If ashiftrt_insns[16 - size] is 8, this choice will be overridden
4198 below, by alternative 3 or something even better. */
4199 if (cost < best_cost)
4201 kind = 5;
4202 best_cost = cost;
4205 /* Try a plain sign extend between two shifts. */
4206 for (ext = 16; ext >= insize; ext -= 8)
4208 if (ext <= size)
4210 cost = ext_ashl_lshr_seq[ext - insize].insn_count + 1
4211 + ashl_lshr_seq[size - ext].insn_count;
4212 if (cost < best_cost)
4214 kind = ext / (unsigned) 8;
4215 best_cost = cost;
4218 /* Check if we can do a sloppy shift with a final signed shift
4219 restoring the sign. */
4220 if (EXT_SHIFT_SIGNED (size - ext))
4221 cost = ext_ashl_lshr_seq[ext - insize].insn_count
4222 + ext_ashl_lshr_seq[size - ext].insn_count + 1;
4223 /* If not, maybe it's still cheaper to do the second shift sloppy,
4224 and do a final sign extend? */
4225 else if (size <= 16)
4226 cost = ext_ashl_lshr_seq[ext - insize].insn_count + 1
4227 + ext_ashl_lshr_seq[size > ext ? size - ext : ext - size].insn_count
4228 + 1;
4229 else
4230 continue;
4231 if (cost < best_cost)
4233 kind = ext / (unsigned) 8 + 2;
4234 best_cost = cost;
4237 /* Check if we can sign extend in r0 */
4238 if (insize < 8)
4240 cost = 3 + ashl_lshr_seq[left].insn_count;
4241 if (cost < best_cost)
4243 kind = 6;
4244 best_cost = cost;
4246 /* Try the same with a final signed shift. */
4247 if (left < 31)
4249 cost = 3 + ext_ashl_lshr_seq[left + 1].insn_count + 1;
4250 if (cost < best_cost)
4252 kind = 7;
4253 best_cost = cost;
4257 if (TARGET_DYNSHIFT)
4259 /* Try to use a dynamic shift. */
4260 cost = ashl_lshr_seq[32 - insize].insn_count + 1 + SH_DYNAMIC_SHIFT_COST;
4261 if (cost < best_cost)
4263 kind = 0;
4264 best_cost = cost;
4267 if (costp)
4268 *costp = cost;
4269 return kind;
4272 /* Function to be used in the length attribute of the instructions
4273 implementing this pattern. */
4275 shl_sext_length (rtx insn)
4277 rtx set_src, left_rtx, size_rtx;
4278 int cost;
4280 set_src = SET_SRC (XVECEXP (PATTERN (insn), 0, 0));
4281 left_rtx = XEXP (XEXP (set_src, 0), 1);
4282 size_rtx = XEXP (set_src, 1);
4283 shl_sext_kind (left_rtx, size_rtx, &cost);
4284 return cost;
4287 /* Generate rtl for this pattern */
4288 bool
4289 gen_shl_sext (rtx dest, rtx left_rtx, rtx size_rtx, rtx source)
4291 int kind;
4292 int left, size, insize, cost;
4293 rtx operands[3];
4295 kind = shl_sext_kind (left_rtx, size_rtx, &cost);
4296 left = INTVAL (left_rtx);
4297 size = INTVAL (size_rtx);
4298 insize = size - left;
4299 switch (kind)
4301 case 1:
4302 case 2:
4303 case 3:
4304 case 4:
4306 int ext = kind & 1 ? 8 : 16;
4307 int shift2 = size - ext;
4309 /* Don't expand fine-grained when combining, because that will
4310 make the pattern fail. */
4311 if (! currently_expanding_to_rtl
4312 && ! reload_in_progress && ! reload_completed)
4314 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
4315 emit_insn (gen_movsi (dest, source));
4316 break;
4318 if (dest != source)
4319 emit_insn (gen_movsi (dest, source));
4320 operands[0] = dest;
4321 if (ext - insize)
4323 operands[2] = GEN_INT (ext - insize);
4324 gen_shifty_hi_op (ASHIFT, operands);
4326 emit_insn (kind & 1
4327 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
4328 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
4329 if (kind <= 2)
4331 if (shift2)
4333 operands[2] = GEN_INT (shift2);
4334 gen_shifty_op (ASHIFT, operands);
4337 else
4339 if (shift2 > 0)
4341 if (EXT_SHIFT_SIGNED (shift2))
4343 operands[2] = GEN_INT (shift2 + 1);
4344 gen_shifty_op (ASHIFT, operands);
4345 operands[2] = const1_rtx;
4346 gen_shifty_op (ASHIFTRT, operands);
4347 break;
4349 operands[2] = GEN_INT (shift2);
4350 gen_shifty_hi_op (ASHIFT, operands);
4352 else if (shift2)
4354 operands[2] = GEN_INT (-shift2);
4355 gen_shifty_hi_op (LSHIFTRT, operands);
4357 emit_insn (size <= 8
4358 ? gen_extendqisi2 (dest, gen_lowpart (QImode, dest))
4359 : gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
4361 break;
4363 case 5:
4365 int i = 16 - size;
4366 if (! currently_expanding_to_rtl
4367 && ! reload_in_progress && ! reload_completed)
4368 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
4369 else
4371 operands[0] = dest;
4372 operands[2] = GEN_INT (16 - insize);
4373 gen_shifty_hi_op (ASHIFT, operands);
4374 emit_insn (gen_extendhisi2 (dest, gen_lowpart (HImode, dest)));
4376 /* Don't use gen_ashrsi3 because it generates new pseudos. */
4377 while (--i >= 0)
4378 gen_ashift (ASHIFTRT, 1, dest);
4379 break;
4381 case 6:
4382 case 7:
4383 /* Don't expand fine-grained when combining, because that will
4384 make the pattern fail. */
4385 if (! currently_expanding_to_rtl
4386 && ! reload_in_progress && ! reload_completed)
4388 emit_insn (gen_shl_sext_ext (dest, source, left_rtx, size_rtx));
4389 emit_insn (gen_movsi (dest, source));
4390 break;
4392 emit_insn (gen_andsi3 (dest, source, GEN_INT ((1 << insize) - 1)));
4393 emit_insn (gen_xorsi3 (dest, dest, GEN_INT (1 << (insize - 1))));
4394 emit_insn (gen_addsi3 (dest, dest, GEN_INT (HOST_WIDE_INT_M1U << (insize - 1))));
4395 operands[0] = dest;
4396 operands[2] = kind == 7 ? GEN_INT (left + 1) : left_rtx;
4397 gen_shifty_op (ASHIFT, operands);
4398 if (kind == 7)
4399 emit_insn (gen_ashrsi3_k (dest, dest, const1_rtx));
4400 break;
4401 default:
4402 return true;
4404 return false;
4407 typedef struct label_ref_list_d
4409 rtx_code_label *label;
4410 struct label_ref_list_d *next;
4411 } *label_ref_list_t;
4413 static object_allocator<label_ref_list_d> label_ref_list_d_pool
4414 ("label references list");
4416 /* The SH cannot load a large constant into a register, constants have to
4417 come from a pc relative load. The reference of a pc relative load
4418 instruction must be less than 1k in front of the instruction. This
4419 means that we often have to dump a constant inside a function, and
4420 generate code to branch around it.
4422 It is important to minimize this, since the branches will slow things
4423 down and make things bigger.
4425 Worst case code looks like:
4427 mov.l L1,rn
4428 bra L2
4430 align
4431 L1: .long value
4435 mov.l L3,rn
4436 bra L4
4438 align
4439 L3: .long value
4443 We fix this by performing a scan before scheduling, which notices which
4444 instructions need to have their operands fetched from the constant table
4445 and builds the table.
4447 The algorithm is:
4449 scan, find an instruction which needs a pcrel move. Look forward, find the
4450 last barrier which is within MAX_COUNT bytes of the requirement.
4451 If there isn't one, make one. Process all the instructions between
4452 the find and the barrier.
4454 In the above example, we can tell that L3 is within 1k of L1, so
4455 the first move can be shrunk from the 3 insn+constant sequence into
4456 just 1 insn, and the constant moved to L3 to make:
4458 mov.l L1,rn
4460 mov.l L3,rn
4461 bra L4
4463 align
4464 L3:.long value
4465 L4:.long value
4467 Then the second move becomes the target for the shortening process. */
4469 typedef struct
4471 rtx value; /* Value in table. */
4472 rtx_code_label *label; /* Label of value. */
4473 label_ref_list_t wend; /* End of window. */
4474 machine_mode mode; /* Mode of value. */
4476 /* True if this constant is accessed as part of a post-increment
4477 sequence. Note that HImode constants are never accessed in this way. */
4478 bool part_of_sequence_p;
4479 } pool_node;
4481 /* The maximum number of constants that can fit into one pool, since
4482 constants in the range 0..510 are at least 2 bytes long, and in the
4483 range from there to 1018 at least 4 bytes. */
4485 #define MAX_POOL_SIZE 372
4486 static pool_node pool_vector[MAX_POOL_SIZE];
4487 static int pool_size;
4488 static rtx_code_label *pool_window_label;
4489 static int pool_window_last;
4491 static int max_labelno_before_reorg;
4493 /* ??? If we need a constant in HImode which is the truncated value of a
4494 constant we need in SImode, we could combine the two entries thus saving
4495 two bytes. Is this common enough to be worth the effort of implementing
4496 it? */
4498 /* ??? This stuff should be done at the same time that we shorten branches.
4499 As it is now, we must assume that all branches are the maximum size, and
4500 this causes us to almost always output constant pools sooner than
4501 necessary. */
4503 /* Add a constant to the pool and return its label. */
4504 static rtx_code_label *
4505 add_constant (rtx x, machine_mode mode, rtx last_value)
4507 rtx_code_label *lab, *new_rtx;
4508 label_ref_list_t ref, newref;
4510 /* First see if we've already got it. */
4511 for (int i = 0; i < pool_size; i++)
4513 if (x->code == pool_vector[i].value->code
4514 && mode == pool_vector[i].mode)
4516 if (x->code == CODE_LABEL)
4518 if (XINT (x, 3) != XINT (pool_vector[i].value, 3))
4519 continue;
4521 if (rtx_equal_p (x, pool_vector[i].value))
4523 lab = new_rtx = 0;
4524 if (! last_value
4525 || ! i
4526 || ! rtx_equal_p (last_value, pool_vector[i-1].value))
4528 new_rtx = gen_label_rtx ();
4529 LABEL_REFS (new_rtx) = pool_vector[i].label;
4530 pool_vector[i].label = lab = new_rtx;
4532 if (lab && pool_window_label)
4534 newref = label_ref_list_d_pool.allocate ();
4535 newref->label = pool_window_label;
4536 ref = pool_vector[pool_window_last].wend;
4537 newref->next = ref;
4538 pool_vector[pool_window_last].wend = newref;
4540 if (new_rtx)
4541 pool_window_label = new_rtx;
4542 pool_window_last = i;
4543 return lab;
4548 /* Need a new one. */
4549 pool_vector[pool_size].value = x;
4550 if (last_value && rtx_equal_p (last_value, pool_vector[pool_size - 1].value))
4552 lab = 0;
4553 pool_vector[pool_size - 1].part_of_sequence_p = true;
4555 else
4556 lab = gen_label_rtx ();
4557 pool_vector[pool_size].mode = mode;
4558 pool_vector[pool_size].label = lab;
4559 pool_vector[pool_size].wend = NULL;
4560 pool_vector[pool_size].part_of_sequence_p = (lab == 0);
4561 if (lab && pool_window_label)
4563 newref = label_ref_list_d_pool.allocate ();
4564 newref->label = pool_window_label;
4565 ref = pool_vector[pool_window_last].wend;
4566 newref->next = ref;
4567 pool_vector[pool_window_last].wend = newref;
4569 if (lab)
4570 pool_window_label = lab;
4571 pool_window_last = pool_size;
4572 pool_size++;
4573 return lab;
4576 /* Output the literal table. START, if nonzero, is the first instruction
4577 this table is needed for, and also indicates that there is at least one
4578 casesi_worker_2 instruction; We have to emit the operand3 labels from
4579 these insns at a 4-byte aligned position. BARRIER is the barrier
4580 after which we are to place the table. */
4581 static void
4582 dump_table (rtx_insn *start, rtx_insn *barrier)
4584 rtx_insn *scan = barrier;
4585 bool need_align = true;
4586 rtx lab;
4587 label_ref_list_t ref;
4588 bool have_df = false;
4590 /* Do two passes, first time dump out the HI sized constants. */
4592 for (int i = 0; i < pool_size; i++)
4594 pool_node *p = &pool_vector[i];
4596 if (p->mode == HImode)
4598 if (need_align)
4600 scan = emit_insn_after (gen_align_2 (), scan);
4601 need_align = false;
4603 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4604 scan = emit_label_after (lab, scan);
4605 scan = emit_insn_after (gen_consttable_2 (p->value, const0_rtx),
4606 scan);
4607 for (ref = p->wend; ref; ref = ref->next)
4609 lab = ref->label;
4610 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4613 else if (p->mode == DFmode)
4614 have_df = true;
4617 need_align = true;
4619 if (start)
4621 scan = emit_insn_after (gen_align_4 (), scan);
4622 need_align = false;
4623 for (; start != barrier; start = NEXT_INSN (start))
4624 if (NONJUMP_INSN_P (start)
4625 && recog_memoized (start) == CODE_FOR_casesi_worker_2)
4627 rtx src = SET_SRC (XVECEXP (PATTERN (start), 0, 0));
4628 rtx lab = XEXP (XVECEXP (src, 0, 3), 0);
4630 scan = emit_label_after (lab, scan);
4633 if (TARGET_FMOVD && TARGET_ALIGN_DOUBLE && have_df)
4635 rtx_insn *align_insn = NULL;
4637 scan = emit_label_after (gen_label_rtx (), scan);
4638 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4639 need_align = false;
4641 for (int i = 0; i < pool_size; i++)
4643 pool_node *p = &pool_vector[i];
4645 switch (p->mode)
4647 case E_HImode:
4648 break;
4649 case E_SImode:
4650 case E_SFmode:
4651 if (align_insn && !p->part_of_sequence_p)
4653 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4654 emit_label_before (lab, align_insn);
4655 emit_insn_before (gen_consttable_4 (p->value, const0_rtx),
4656 align_insn);
4657 for (ref = p->wend; ref; ref = ref->next)
4659 lab = ref->label;
4660 emit_insn_before (gen_consttable_window_end (lab),
4661 align_insn);
4663 delete_insn (align_insn);
4664 align_insn = NULL;
4665 continue;
4667 else
4669 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4670 scan = emit_label_after (lab, scan);
4671 scan = emit_insn_after (gen_consttable_4 (p->value,
4672 const0_rtx), scan);
4673 need_align = ! need_align;
4675 break;
4676 case E_DFmode:
4677 if (need_align)
4679 scan = emit_insn_after (gen_align_log (GEN_INT (3)), scan);
4680 align_insn = scan;
4681 need_align = false;
4683 /* FALLTHRU */
4684 case E_DImode:
4685 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4686 scan = emit_label_after (lab, scan);
4687 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4688 scan);
4689 break;
4690 default:
4691 gcc_unreachable ();
4694 if (p->mode != HImode)
4696 for (ref = p->wend; ref; ref = ref->next)
4698 lab = ref->label;
4699 scan = emit_insn_after (gen_consttable_window_end (lab),
4700 scan);
4705 pool_size = 0;
4708 for (int i = 0; i < pool_size; i++)
4710 pool_node *p = &pool_vector[i];
4712 switch (p->mode)
4714 case E_HImode:
4715 break;
4716 case E_SImode:
4717 case E_SFmode:
4718 if (need_align)
4720 need_align = false;
4721 scan = emit_label_after (gen_label_rtx (), scan);
4722 scan = emit_insn_after (gen_align_4 (), scan);
4724 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4725 scan = emit_label_after (lab, scan);
4726 scan = emit_insn_after (gen_consttable_4 (p->value, const0_rtx),
4727 scan);
4728 break;
4729 case E_DFmode:
4730 case E_DImode:
4731 if (need_align)
4733 need_align = false;
4734 scan = emit_label_after (gen_label_rtx (), scan);
4735 scan = emit_insn_after (gen_align_4 (), scan);
4737 for (lab = p->label; lab; lab = LABEL_REFS (lab))
4738 scan = emit_label_after (lab, scan);
4739 scan = emit_insn_after (gen_consttable_8 (p->value, const0_rtx),
4740 scan);
4741 break;
4742 default:
4743 gcc_unreachable ();
4746 if (p->mode != HImode)
4748 for (ref = p->wend; ref; ref = ref->next)
4750 lab = ref->label;
4751 scan = emit_insn_after (gen_consttable_window_end (lab), scan);
4756 scan = emit_insn_after (gen_consttable_end (), scan);
4757 scan = emit_barrier_after (scan);
4758 pool_size = 0;
4759 pool_window_label = NULL;
4760 pool_window_last = 0;
4763 #define MOVA_LABELREF(mova) XVECEXP (SET_SRC (PATTERN (mova)), 0, 0)
4765 /* Nonzero if the insn is a move instruction which needs to be fixed. */
4767 /* ??? For a DImode/DFmode moves, we don't need to fix it if each half of the
4768 CONST_DOUBLE input value is CONST_OK_FOR_I08. For a SFmode move, we don't
4769 need to fix it if the input value is CONST_OK_FOR_I08. */
4770 static bool
4771 broken_move (rtx_insn *insn)
4773 if (NONJUMP_INSN_P (insn))
4775 rtx pat = PATTERN (insn);
4776 if (GET_CODE (pat) == PARALLEL)
4777 pat = XVECEXP (pat, 0, 0);
4778 if (GET_CODE (pat) == SET
4779 /* We can load any 8-bit value if we don't care what the high
4780 order bits end up as. */
4781 && GET_MODE (SET_DEST (pat)) != QImode
4782 && (CONSTANT_P (SET_SRC (pat))
4783 || (GET_CODE (SET_SRC (pat)) == UNSPEC_VOLATILE
4784 && XINT (SET_SRC (pat), 1) == UNSPECV_SP_SWITCH_B)
4785 /* Match mova_const. */
4786 || (GET_CODE (SET_SRC (pat)) == UNSPEC
4787 && XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
4788 && GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
4789 && ! (TARGET_SH2E
4790 && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
4791 && (fp_zero_operand (SET_SRC (pat))
4792 || fp_one_operand (SET_SRC (pat)))
4793 /* In general we don't know the current setting of fpscr, so
4794 disable fldi.
4795 There is an exception if this was a register-register move
4796 before reload - and hence it was ascertained that we have
4797 single precision setting - and in a post-reload optimization
4798 we changed this to do a constant load. In that case
4799 we don't have an r0 clobber, hence we must use fldi. */
4800 && (TARGET_FMOVD
4801 || (GET_CODE (XEXP (XVECEXP (PATTERN (insn), 0, 2), 0))
4802 == SCRATCH))
4803 && REG_P (SET_DEST (pat))
4804 && FP_REGISTER_P (REGNO (SET_DEST (pat))))
4805 && ! (TARGET_SH2A
4806 && GET_MODE (SET_DEST (pat)) == SImode
4807 && (satisfies_constraint_I20 (SET_SRC (pat))
4808 || satisfies_constraint_I28 (SET_SRC (pat))))
4809 && ! satisfies_constraint_I08 (SET_SRC (pat)))
4810 return true;
4813 return false;
4816 /* Return true if the specified insn is a mova insn. */
4817 static bool
4818 mova_p (rtx_insn *insn)
4820 return (NONJUMP_INSN_P (insn)
4821 && GET_CODE (PATTERN (insn)) == SET
4822 && GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
4823 && XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
4824 /* Don't match mova_const. */
4825 && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
4828 /* Fix up a mova from a switch that went out of range. */
4829 static void
4830 fixup_mova (rtx_insn *mova)
4832 PUT_MODE (XEXP (MOVA_LABELREF (mova), 0), QImode);
4833 if (! flag_pic)
4835 SET_SRC (PATTERN (mova)) = MOVA_LABELREF (mova);
4836 INSN_CODE (mova) = -1;
4838 else
4840 rtx_insn *worker = mova;
4841 rtx_code_label *lab = gen_label_rtx ();
4842 rtx wpat, wpat0, wpat1, wsrc, target, base, diff;
4846 worker = NEXT_INSN (worker);
4847 gcc_assert (worker
4848 && !LABEL_P (worker)
4849 && !JUMP_P (worker));
4850 } while (NOTE_P (worker)
4851 || recog_memoized (worker) != CODE_FOR_casesi_worker_1);
4852 wpat = PATTERN (worker);
4853 wpat0 = XVECEXP (wpat, 0, 0);
4854 wpat1 = XVECEXP (wpat, 0, 1);
4855 wsrc = SET_SRC (wpat0);
4856 PATTERN (worker) = (gen_casesi_worker_2
4857 (SET_DEST (wpat0), XVECEXP (wsrc, 0, 1),
4858 XEXP (XVECEXP (wsrc, 0, 2), 0), lab,
4859 XEXP (wpat1, 0)));
4860 INSN_CODE (worker) = -1;
4861 target = XVECEXP (SET_SRC (PATTERN (mova)), 0, 0);
4862 base = gen_rtx_LABEL_REF (Pmode, lab);
4863 diff = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, target, base), UNSPEC_SYMOFF);
4864 SET_SRC (PATTERN (mova)) = gen_rtx_CONST (Pmode, diff);
4865 INSN_CODE (mova) = -1;
4869 /* NEW_MOVA is a mova we've just encountered while scanning forward. Update
4870 *num_mova, and check if the new mova is not nested within the first one.
4871 return 0 if *first_mova was replaced, 1 if new_mova was replaced,
4872 2 if new_mova has been assigned to *first_mova, -1 otherwise.. */
4873 static int
4874 untangle_mova (int *num_mova, rtx_insn **first_mova, rtx_insn *new_mova)
4876 int n_addr = 0; /* Initialization to shut up spurious warning. */
4877 int f_target, n_target = 0; /* Likewise. */
4879 if (optimize)
4881 /* If NEW_MOVA has no address yet, it will be handled later. */
4882 if (INSN_ADDRESSES_SIZE() <= (unsigned) INSN_UID (new_mova))
4883 return -1;
4885 n_addr = INSN_ADDRESSES (INSN_UID (new_mova));
4886 n_target = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (new_mova), 0)));
4887 if (n_addr > n_target || n_addr + 1022 < n_target)
4889 /* Change the mova into a load.
4890 broken_move will then return true for it. */
4891 fixup_mova (new_mova);
4892 return 1;
4895 if (!(*num_mova)++)
4897 *first_mova = new_mova;
4898 return 2;
4900 if (!optimize
4901 || ((f_target
4902 = INSN_ADDRESSES (INSN_UID (XEXP (MOVA_LABELREF (*first_mova), 0))))
4903 >= n_target))
4904 return -1;
4906 (*num_mova)--;
4907 if (f_target - INSN_ADDRESSES (INSN_UID (*first_mova))
4908 > n_target - n_addr)
4910 fixup_mova (*first_mova);
4911 return 0;
4913 else
4915 fixup_mova (new_mova);
4916 return 1;
4920 /* Find the last barrier from insn FROM which is close enough to hold the
4921 constant pool. If we can't find one, then create one near the end of
4922 the range. */
4923 static rtx_insn *
4924 find_barrier (int num_mova, rtx_insn *mova, rtx_insn *from)
4926 int count_si = 0;
4927 int count_hi = 0;
4928 int found_hi = 0;
4929 int found_si = 0;
4930 int hi_align = 2;
4931 int si_align = 2;
4932 int leading_mova = num_mova;
4933 rtx_insn *barrier_before_mova = NULL;
4934 rtx_insn *found_barrier = NULL;
4935 rtx_insn *good_barrier = NULL;
4936 int si_limit;
4937 int hi_limit;
4938 rtx_insn *orig = from;
4939 rtx_insn *last_got = NULL;
4940 rtx_insn *last_symoff = NULL;
4942 /* For HImode: range is 510, add 4 because pc counts from address of
4943 second instruction after this one, subtract 2 for the jump instruction
4944 that we may need to emit before the table, subtract 2 for the instruction
4945 that fills the jump delay slot (in very rare cases, reorg will take an
4946 instruction from after the constant pool or will leave the delay slot
4947 empty). This gives 510.
4948 For SImode: range is 1020, add 4 because pc counts from address of
4949 second instruction after this one, subtract 2 in case pc is 2 byte
4950 aligned, subtract 2 for the jump instruction that we may need to emit
4951 before the table, subtract 2 for the instruction that fills the jump
4952 delay slot. This gives 1018. */
4954 /* The branch will always be shortened now that the reference address for
4955 forward branches is the successor address, thus we need no longer make
4956 adjustments to the [sh]i_limit for -O0. */
4958 si_limit = 1018;
4959 hi_limit = 510;
4961 while (from && count_si < si_limit && count_hi < hi_limit)
4963 int inc = get_attr_length (from);
4964 int new_align = 1;
4966 /* If this is a label that existed at the time of the compute_alignments
4967 call, determine the alignment. N.B. When find_barrier recurses for
4968 an out-of-reach mova, we might see labels at the start of previously
4969 inserted constant tables. */
4970 if (LABEL_P (from)
4971 && CODE_LABEL_NUMBER (from) <= max_labelno_before_reorg)
4973 if (optimize)
4974 new_align = 1 << label_to_alignment (from);
4975 else if (BARRIER_P (prev_nonnote_insn (from)))
4976 new_align = 1 << barrier_align (from);
4977 else
4978 new_align = 1;
4979 inc = 0;
4981 /* In case we are scanning a constant table because of recursion, check
4982 for explicit alignments. If the table is long, we might be forced
4983 to emit the new table in front of it; the length of the alignment
4984 might be the last straw. */
4985 else if (NONJUMP_INSN_P (from)
4986 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4987 && XINT (PATTERN (from), 1) == UNSPECV_ALIGN)
4988 new_align = INTVAL (XVECEXP (PATTERN (from), 0, 0));
4989 /* When we find the end of a constant table, paste the new constant
4990 at the end. That is better than putting it in front because
4991 this way, we don't need extra alignment for adding a 4-byte-aligned
4992 mov(a) label to a 2/4 or 8/4 byte aligned table. */
4993 else if (NONJUMP_INSN_P (from)
4994 && GET_CODE (PATTERN (from)) == UNSPEC_VOLATILE
4995 && XINT (PATTERN (from), 1) == UNSPECV_CONST_END)
4996 return from;
4998 if (BARRIER_P (from))
5000 rtx_insn *next;
5002 found_barrier = from;
5004 /* If we are at the end of the function, or in front of an alignment
5005 instruction, we need not insert an extra alignment. We prefer
5006 this kind of barrier. */
5007 if (barrier_align (from) > 2)
5008 good_barrier = from;
5010 /* If we are at the end of a hot/cold block, dump the constants
5011 here. */
5012 next = NEXT_INSN (from);
5013 if (next
5014 && NOTE_P (next)
5015 && NOTE_KIND (next) == NOTE_INSN_SWITCH_TEXT_SECTIONS)
5016 break;
5019 if (broken_move (from))
5021 rtx pat, src, dst;
5022 machine_mode mode;
5024 pat = PATTERN (from);
5025 if (GET_CODE (pat) == PARALLEL)
5026 pat = XVECEXP (pat, 0, 0);
5027 src = SET_SRC (pat);
5028 dst = SET_DEST (pat);
5029 mode = GET_MODE (dst);
5031 /* GOT pcrelat setting comes in pair of
5032 mova .L8,r0
5033 mov.l .L8,r12
5034 instructions. (plus add r0,r12).
5035 Remember if we see one without the other. */
5036 if (GET_CODE (src) == UNSPEC && PIC_ADDR_P (XVECEXP (src, 0, 0)))
5037 last_got = last_got ? NULL : from;
5038 else if (PIC_ADDR_P (src))
5039 last_got = last_got ? NULL : from;
5041 /* We must explicitly check the mode, because sometimes the
5042 front end will generate code to load unsigned constants into
5043 HImode targets without properly sign extending them. */
5044 if (mode == HImode
5045 || (mode == SImode && satisfies_constraint_I16 (src)
5046 && REGNO (dst) != FPUL_REG))
5048 found_hi += 2;
5049 /* We put the short constants before the long constants, so
5050 we must count the length of short constants in the range
5051 for the long constants. */
5052 /* ??? This isn't optimal, but is easy to do. */
5053 si_limit -= 2;
5055 else
5057 /* We dump DF/DI constants before SF/SI ones, because
5058 the limit is the same, but the alignment requirements
5059 are higher. We may waste up to 4 additional bytes
5060 for alignment, and the DF/DI constant may have
5061 another SF/SI constant placed before it. */
5062 while (si_align > 2 && found_si + si_align - 2 > count_si)
5063 si_align >>= 1;
5064 if (found_si > count_si)
5065 count_si = found_si;
5066 found_si += GET_MODE_SIZE (mode);
5067 if (num_mova)
5068 si_limit -= GET_MODE_SIZE (mode);
5072 if (mova_p (from))
5074 switch (untangle_mova (&num_mova, &mova, from))
5076 case 1:
5077 if (flag_pic)
5079 rtx src = SET_SRC (PATTERN (from));
5080 if (GET_CODE (src) == CONST
5081 && GET_CODE (XEXP (src, 0)) == UNSPEC
5082 && XINT (XEXP (src, 0), 1) == UNSPEC_SYMOFF)
5083 last_symoff = from;
5085 break;
5086 case 0: return find_barrier (0, 0, mova);
5087 case 2:
5089 leading_mova = 0;
5090 barrier_before_mova
5091 = good_barrier ? good_barrier : found_barrier;
5093 default: break;
5095 if (found_si > count_si)
5096 count_si = found_si;
5098 else if (JUMP_TABLE_DATA_P (from)
5099 && GET_CODE (PATTERN (from)) == ADDR_DIFF_VEC)
5101 if ((num_mova > 1 && GET_MODE (prev_nonnote_insn (from)) == VOIDmode)
5102 || (num_mova
5103 && (prev_nonnote_insn (from)
5104 == XEXP (MOVA_LABELREF (mova), 0))))
5105 num_mova--;
5106 if (barrier_align (next_real_insn (from)) == align_jumps_log)
5108 /* We have just passed the barrier in front of the
5109 ADDR_DIFF_VEC, which is stored in found_barrier. Since
5110 the ADDR_DIFF_VEC is accessed as data, just like our pool
5111 constants, this is a good opportunity to accommodate what
5112 we have gathered so far.
5113 If we waited any longer, we could end up at a barrier in
5114 front of code, which gives worse cache usage for separated
5115 instruction / data caches. */
5116 good_barrier = found_barrier;
5117 break;
5119 else
5121 rtx body = PATTERN (from);
5122 inc = XVECLEN (body, 1) * GET_MODE_SIZE (GET_MODE (body));
5125 /* For the SH1, we generate alignments even after jumps-around-jumps. */
5126 else if (JUMP_P (from)
5127 && ! TARGET_SH2
5128 && ! optimize_size)
5129 new_align = 4;
5131 /* There is a possibility that a bf is transformed into a bf/s by the
5132 delay slot scheduler. */
5133 if (JUMP_P (from)
5134 && get_attr_type (from) == TYPE_CBRANCH
5135 && ! sequence_insn_p (from))
5136 inc += 2;
5138 if (found_si)
5140 count_si += inc;
5141 if (new_align > si_align)
5143 si_limit -= (count_si - 1) & (new_align - si_align);
5144 si_align = new_align;
5146 count_si = (count_si + new_align - 1) & -new_align;
5148 if (found_hi)
5150 count_hi += inc;
5151 if (new_align > hi_align)
5153 hi_limit -= (count_hi - 1) & (new_align - hi_align);
5154 hi_align = new_align;
5156 count_hi = (count_hi + new_align - 1) & -new_align;
5158 from = NEXT_INSN (from);
5161 if (num_mova)
5163 if (leading_mova)
5165 /* Try as we might, the leading mova is out of range. Change
5166 it into a load (which will become a pcload) and retry. */
5167 fixup_mova (mova);
5168 return find_barrier (0, 0, mova);
5170 else
5172 /* Insert the constant pool table before the mova instruction,
5173 to prevent the mova label reference from going out of range. */
5174 from = mova;
5175 good_barrier = found_barrier = barrier_before_mova;
5179 if (found_barrier)
5181 if (good_barrier && next_real_insn (found_barrier))
5182 found_barrier = good_barrier;
5184 else
5186 /* We didn't find a barrier in time to dump our stuff,
5187 so we'll make one. */
5188 rtx_code_label *label = gen_label_rtx ();
5190 /* Don't emit a constant table in the middle of insns for
5191 casesi_worker_2. This is a bit overkill but is enough
5192 because casesi_worker_2 wouldn't appear so frequently. */
5193 if (last_symoff)
5194 from = last_symoff;
5196 /* If we exceeded the range, then we must back up over the last
5197 instruction we looked at. Otherwise, we just need to undo the
5198 NEXT_INSN at the end of the loop. */
5199 if (PREV_INSN (from) != orig
5200 && (count_hi > hi_limit || count_si > si_limit))
5201 from = PREV_INSN (PREV_INSN (from));
5202 else
5203 from = PREV_INSN (from);
5205 /* Don't emit a constant table int the middle of global pointer setting,
5206 since that that would move the addressing base GOT into another table.
5207 We need the first mov instruction before the _GLOBAL_OFFSET_TABLE_
5208 in the pool anyway, so just move up the whole constant pool.
5210 However, avoid doing so when the last single GOT mov is the starting
5211 insn itself. Going past above the start insn would create a negative
5212 offset, causing errors. */
5213 if (last_got && last_got != orig)
5214 from = PREV_INSN (last_got);
5216 /* Don't insert the constant pool table at the position which
5217 may be the landing pad. */
5218 if (flag_exceptions
5219 && CALL_P (from)
5220 && find_reg_note (from, REG_EH_REGION, NULL_RTX))
5221 from = PREV_INSN (from);
5223 /* Walk back to be just before any jump or label.
5224 Putting it before a label reduces the number of times the branch
5225 around the constant pool table will be hit. Putting it before
5226 a jump makes it more likely that the bra delay slot will be
5227 filled. */
5228 while (NOTE_P (from) || JUMP_P (from)
5229 || LABEL_P (from))
5230 from = PREV_INSN (from);
5232 /* Make sure we do not split between a call and its corresponding
5233 CALL_ARG_LOCATION note. */
5234 if (CALL_P (from))
5236 rtx_insn *next = NEXT_INSN (from);
5237 if (next && NOTE_P (next)
5238 && NOTE_KIND (next) == NOTE_INSN_CALL_ARG_LOCATION)
5239 from = next;
5242 from = emit_jump_insn_after (gen_jump (label), from);
5243 JUMP_LABEL (from) = label;
5244 LABEL_NUSES (label) = 1;
5245 found_barrier = emit_barrier_after (from);
5246 emit_label_after (label, found_barrier);
5249 return found_barrier;
5252 /* If the instruction INSN is implemented by a special function, and we can
5253 positively find the register that is used to call the sfunc, and this
5254 register is not used anywhere else in this instruction - except as the
5255 destination of a set, return this register; else, return 0. */
5257 sfunc_uses_reg (rtx_insn *insn)
5259 int i;
5260 rtx pattern, part, reg_part, reg;
5262 if (!NONJUMP_INSN_P (insn))
5263 return NULL_RTX;
5264 pattern = PATTERN (insn);
5265 if (GET_CODE (pattern) != PARALLEL || get_attr_type (insn) != TYPE_SFUNC)
5266 return NULL_RTX;
5268 for (reg_part = NULL_RTX, i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
5270 part = XVECEXP (pattern, 0, i);
5271 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == SImode)
5272 reg_part = part;
5274 if (! reg_part)
5275 return NULL_RTX;
5276 reg = XEXP (reg_part, 0);
5277 for (int i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
5279 part = XVECEXP (pattern, 0, i);
5280 if (part == reg_part || GET_CODE (part) == CLOBBER)
5281 continue;
5282 if (reg_mentioned_p (reg, ((GET_CODE (part) == SET
5283 && REG_P (SET_DEST (part)))
5284 ? SET_SRC (part) : part)))
5285 return NULL_RTX;
5287 return reg;
5290 /* See if the only way in which INSN uses REG is by calling it, or by
5291 setting it while calling it. Set *SET to a SET rtx if the register
5292 is set by INSN. */
5293 static bool
5294 noncall_uses_reg (rtx reg, rtx_insn *insn, rtx *set)
5296 *set = NULL_RTX;
5298 rtx reg2 = sfunc_uses_reg (insn);
5299 if (reg2 && REGNO (reg2) == REGNO (reg))
5301 rtx pattern = single_set (insn);
5302 if (pattern
5303 && REG_P (SET_DEST (pattern))
5304 && REGNO (reg) == REGNO (SET_DEST (pattern)))
5305 *set = pattern;
5306 return false;
5308 if (!CALL_P (insn))
5310 /* We don't use rtx_equal_p because we don't care if the mode is
5311 different. */
5312 rtx pattern = single_set (insn);
5313 if (pattern
5314 && REG_P (SET_DEST (pattern))
5315 && REGNO (reg) == REGNO (SET_DEST (pattern)))
5317 rtx par, part;
5318 int i;
5320 *set = pattern;
5321 par = PATTERN (insn);
5322 if (GET_CODE (par) == PARALLEL)
5323 for (i = XVECLEN (par, 0) - 1; i >= 0; i--)
5325 part = XVECEXP (par, 0, i);
5326 if (GET_CODE (part) != SET && reg_mentioned_p (reg, part))
5327 return true;
5329 return reg_mentioned_p (reg, SET_SRC (pattern));
5332 return true;
5335 rtx pattern = PATTERN (insn);
5337 if (GET_CODE (pattern) == PARALLEL)
5339 for (int i = XVECLEN (pattern, 0) - 1; i >= 1; i--)
5340 if (reg_mentioned_p (reg, XVECEXP (pattern, 0, i)))
5341 return true;
5342 pattern = XVECEXP (pattern, 0, 0);
5345 if (GET_CODE (pattern) == SET)
5347 if (reg_mentioned_p (reg, SET_DEST (pattern)))
5349 /* We don't use rtx_equal_p, because we don't care if the
5350 mode is different. */
5351 if (!REG_P (SET_DEST (pattern))
5352 || REGNO (reg) != REGNO (SET_DEST (pattern)))
5353 return true;
5355 *set = pattern;
5358 pattern = SET_SRC (pattern);
5361 if (GET_CODE (pattern) != CALL
5362 || !MEM_P (XEXP (pattern, 0))
5363 || ! rtx_equal_p (reg, XEXP (XEXP (pattern, 0), 0)))
5364 return true;
5366 return false;
5369 /* Given a X, a pattern of an insn or a part of it, return a mask of used
5370 general registers. Bits 0..15 mean that the respective registers
5371 are used as inputs in the instruction. Bits 16..31 mean that the
5372 registers 0..15, respectively, are used as outputs, or are clobbered.
5373 IS_DEST should be set to 16 if X is the destination of a SET, else to 0. */
5375 regs_used (rtx x, int is_dest)
5377 enum rtx_code code;
5378 const char *fmt;
5379 int used = 0;
5381 if (! x)
5382 return used;
5383 code = GET_CODE (x);
5384 switch (code)
5386 case REG:
5387 if (REGNO (x) < 16)
5388 return (((1 << hard_regno_nregs (0, GET_MODE (x))) - 1)
5389 << (REGNO (x) + is_dest));
5390 return 0;
5391 case SUBREG:
5393 rtx y = SUBREG_REG (x);
5395 if (!REG_P (y))
5396 break;
5397 if (REGNO (y) < 16)
5398 return (((1 << hard_regno_nregs (0, GET_MODE (x))) - 1)
5399 << (REGNO (y) +
5400 subreg_regno_offset (REGNO (y),
5401 GET_MODE (y),
5402 SUBREG_BYTE (x),
5403 GET_MODE (x)) + is_dest));
5404 return 0;
5406 case SET:
5407 return regs_used (SET_SRC (x), 0) | regs_used (SET_DEST (x), 16);
5408 case RETURN:
5409 /* If there was a return value, it must have been indicated with USE. */
5410 return 0x00ffff00;
5411 case CLOBBER:
5412 is_dest = 1;
5413 break;
5414 case MEM:
5415 is_dest = 0;
5416 break;
5417 case CALL:
5418 used |= 0x00ff00f0;
5419 break;
5420 default:
5421 break;
5424 fmt = GET_RTX_FORMAT (code);
5426 for (int i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5428 if (fmt[i] == 'E')
5430 for (int j = XVECLEN (x, i) - 1; j >= 0; j--)
5431 used |= regs_used (XVECEXP (x, i, j), is_dest);
5433 else if (fmt[i] == 'e')
5434 used |= regs_used (XEXP (x, i), is_dest);
5436 return used;
5439 /* Create an instruction that prevents redirection of a conditional branch
5440 to the destination of the JUMP with address ADDR.
5441 If the branch needs to be implemented as an indirect jump, try to find
5442 a scratch register for it.
5443 If NEED_BLOCK is 0, don't do anything unless we need a scratch register.
5444 If any preceding insn that doesn't fit into a delay slot is good enough,
5445 pass 1. Pass 2 if a definite blocking insn is needed.
5446 -1 is used internally to avoid deep recursion.
5447 If a blocking instruction is made or recognized, return it. */
5448 static rtx_insn *
5449 gen_block_redirect (rtx_insn *jump, int addr, int need_block)
5451 int dead = 0;
5452 rtx_insn *prev = prev_nonnote_insn (jump);
5454 /* First, check if we already have an instruction that satisfies our need. */
5455 if (prev && NONJUMP_INSN_P (prev) && ! prev->deleted ())
5457 if (INSN_CODE (prev) == CODE_FOR_indirect_jump_scratch)
5458 return prev;
5459 if (GET_CODE (PATTERN (prev)) == USE
5460 || GET_CODE (PATTERN (prev)) == CLOBBER
5461 || get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
5462 prev = jump;
5463 else if ((need_block &= ~1) < 0)
5464 return prev;
5465 else if (recog_memoized (prev) == CODE_FOR_block_branch_redirect)
5466 need_block = 0;
5468 if (GET_CODE (PATTERN (jump)) == RETURN)
5470 if (! need_block)
5471 return prev;
5472 /* Reorg even does nasty things with return insns that cause branches
5473 to go out of range - see find_end_label and callers. */
5474 return emit_insn_before (gen_block_branch_redirect (const0_rtx) , jump);
5476 /* We can't use JUMP_LABEL here because it might be undefined
5477 when not optimizing. */
5478 rtx dest = XEXP (SET_SRC (PATTERN (jump)), 0);
5479 /* If the branch is out of range, try to find a scratch register for it. */
5480 if (optimize
5481 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
5482 > 4092 + 4098))
5484 rtx_insn *scan;
5485 /* Don't look for the stack pointer as a scratch register,
5486 it would cause trouble if an interrupt occurred. */
5487 unsigned attempt = 0x7fff, used;
5488 int jump_left = flag_expensive_optimizations + 1;
5490 /* It is likely that the most recent eligible instruction is wanted for
5491 the delay slot. Therefore, find out which registers it uses, and
5492 try to avoid using them. */
5494 for (scan = jump; (scan = PREV_INSN (scan)); )
5496 if (scan->deleted ())
5497 continue;
5498 rtx_code code = GET_CODE (scan);
5499 if (code == CODE_LABEL || code == JUMP_INSN)
5500 break;
5501 if (code == INSN
5502 && GET_CODE (PATTERN (scan)) != USE
5503 && GET_CODE (PATTERN (scan)) != CLOBBER
5504 && get_attr_in_delay_slot (scan) == IN_DELAY_SLOT_YES)
5506 attempt &= ~regs_used (PATTERN (scan), 0);
5507 break;
5510 for (used = dead = 0, scan = JUMP_LABEL_AS_INSN (jump);
5511 (scan = NEXT_INSN (scan)); )
5513 if (scan->deleted ())
5514 continue;
5515 rtx_code code = GET_CODE (scan);
5516 if (INSN_P (scan))
5518 used |= regs_used (PATTERN (scan), 0);
5519 if (code == CALL_INSN)
5520 used |= regs_used (CALL_INSN_FUNCTION_USAGE (scan), 0);
5521 dead |= (used >> 16) & ~used;
5522 if (dead & attempt)
5524 dead &= attempt;
5525 break;
5527 if (code == JUMP_INSN)
5529 if (jump_left-- && simplejump_p (scan))
5530 scan = JUMP_LABEL_AS_INSN (scan);
5531 else
5532 break;
5536 /* Mask out the stack pointer again, in case it was
5537 the only 'free' register we have found. */
5538 dead &= 0x7fff;
5540 /* If the immediate destination is still in range, check for possible
5541 threading with a jump beyond the delay slot insn.
5542 Don't check if we are called recursively; the jump has been or will be
5543 checked in a different invocation then. */
5545 else if (optimize && need_block >= 0)
5547 rtx_insn *next = next_active_insn (as_a<rtx_insn *> (dest));
5548 next = next_active_insn (next);
5549 if (next && JUMP_P (next)
5550 && GET_CODE (PATTERN (next)) == SET
5551 && recog_memoized (next) == CODE_FOR_jump_compact)
5553 dest = JUMP_LABEL (next);
5554 if (dest
5555 && (INSN_ADDRESSES (INSN_UID (dest)) - addr + (unsigned) 4092
5556 > 4092 + 4098))
5557 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), -1);
5561 if (dead)
5563 rtx reg = gen_rtx_REG (SImode, exact_log2 (dead & -dead));
5565 /* It would be nice if we could convert the jump into an indirect
5566 jump / far branch right now, and thus exposing all constituent
5567 instructions to further optimization. However, reorg uses
5568 simplejump_p to determine if there is an unconditional jump where
5569 it should try to schedule instructions from the target of the
5570 branch; simplejump_p fails for indirect jumps even if they have
5571 a JUMP_LABEL. */
5572 rtx_insn *insn = emit_insn_before (gen_indirect_jump_scratch
5573 (reg, GEN_INT (unspec_bbr_uid++)),
5574 jump);
5575 /* ??? We would like this to have the scope of the jump, but that
5576 scope will change when a delay slot insn of an inner scope is added.
5577 Hence, after delay slot scheduling, we'll have to expect
5578 NOTE_INSN_BLOCK_END notes between the indirect_jump_scratch and
5579 the jump. */
5581 INSN_LOCATION (insn) = INSN_LOCATION (jump);
5582 INSN_CODE (insn) = CODE_FOR_indirect_jump_scratch;
5583 return insn;
5585 else if (need_block)
5586 /* We can't use JUMP_LABEL here because it might be undefined
5587 when not optimizing. */
5588 return emit_insn_before (gen_block_branch_redirect
5589 (GEN_INT (unspec_bbr_uid++)),
5590 jump);
5591 return prev;
5594 #define CONDJUMP_MIN -252
5595 #define CONDJUMP_MAX 262
5596 struct far_branch
5598 /* A label (to be placed) in front of the jump
5599 that jumps to our ultimate destination. */
5600 rtx_insn *near_label;
5601 /* Where we are going to insert it if we cannot move the jump any farther,
5602 or the jump itself if we have picked up an existing jump. */
5603 rtx_insn *insert_place;
5604 /* The ultimate destination. */
5605 rtx_insn *far_label;
5606 struct far_branch *prev;
5607 /* If the branch has already been created, its address;
5608 else the address of its first prospective user. */
5609 int address;
5612 enum mdep_reorg_phase_e mdep_reorg_phase;
5614 static void
5615 gen_far_branch (struct far_branch *bp)
5617 rtx_insn *insn = bp->insert_place;
5618 rtx_jump_insn *jump;
5619 rtx_code_label *label = gen_label_rtx ();
5621 emit_label_after (label, insn);
5622 if (bp->far_label)
5624 jump = emit_jump_insn_after (gen_jump (bp->far_label), insn);
5625 LABEL_NUSES (bp->far_label)++;
5627 else
5628 jump = emit_jump_insn_after (gen_return (), insn);
5630 /* Emit a barrier so that reorg knows that any following instructions
5631 are not reachable via a fall-through path.
5632 But don't do this when not optimizing, since we wouldn't suppress the
5633 alignment for the barrier then, and could end up with out-of-range
5634 pc-relative loads. */
5635 if (optimize)
5636 emit_barrier_after (jump);
5637 emit_label_after (bp->near_label, insn);
5639 if (bp->far_label)
5640 JUMP_LABEL (jump) = bp->far_label;
5641 else
5643 rtx pat = PATTERN (jump);
5644 gcc_assert (ANY_RETURN_P (pat));
5645 JUMP_LABEL (jump) = pat;
5648 bool ok = invert_jump (as_a <rtx_jump_insn *> (insn), label, 1);
5649 gcc_assert (ok);
5651 /* If we are branching around a jump (rather than a return), prevent
5652 reorg from using an insn from the jump target as the delay slot insn -
5653 when reorg did this, it pessimized code (we rather hide the delay slot)
5654 and it could cause branches to go out of range. */
5655 if (bp->far_label)
5656 (emit_insn_after
5657 (gen_stuff_delay_slot
5658 (GEN_INT (unspec_bbr_uid++),
5659 GEN_INT (recog_memoized (insn) == CODE_FOR_branch_false)),
5660 insn));
5661 /* Prevent reorg from undoing our splits. */
5662 gen_block_redirect (jump, bp->address += 2, 2);
5665 /* Fix up ADDR_DIFF_VECs. */
5666 void
5667 fixup_addr_diff_vecs (rtx_insn *first)
5669 rtx_insn *insn;
5671 for (insn = first; insn; insn = NEXT_INSN (insn))
5673 rtx vec_lab, pat, prevpat, x, braf_label;
5674 rtx_insn *prev;
5676 if (! JUMP_TABLE_DATA_P (insn)
5677 || GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC)
5678 continue;
5679 pat = PATTERN (insn);
5680 vec_lab = XEXP (XEXP (pat, 0), 0);
5682 /* Search the matching casesi_jump_2. */
5683 for (prev = as_a <rtx_insn *> (vec_lab); ; prev = PREV_INSN (prev))
5685 if (!JUMP_P (prev))
5686 continue;
5687 prevpat = PATTERN (prev);
5688 if (GET_CODE (prevpat) != PARALLEL || XVECLEN (prevpat, 0) != 2)
5689 continue;
5690 x = XVECEXP (prevpat, 0, 1);
5691 if (GET_CODE (x) != USE)
5692 continue;
5693 x = XEXP (x, 0);
5694 if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
5695 break;
5697 /* FIXME: This is a bug in the optimizer, but it seems harmless
5698 to just avoid panicing. */
5699 if (!prev)
5700 continue;
5702 /* Emit the reference label of the braf where it belongs, right after
5703 the casesi_jump_2 (i.e. braf). */
5704 braf_label = XEXP (XEXP (SET_SRC (XVECEXP (prevpat, 0, 0)), 1), 0);
5705 emit_label_after (braf_label, prev);
5707 /* Fix up the ADDR_DIF_VEC to be relative
5708 to the reference address of the braf. */
5709 XEXP (XEXP (pat, 0), 0) = braf_label;
5713 /* BARRIER_OR_LABEL is either a BARRIER or a CODE_LABEL immediately following
5714 a barrier. Return the base 2 logarithm of the desired alignment. */
5716 barrier_align (rtx_insn *barrier_or_label)
5718 if (! barrier_or_label)
5719 return 0;
5721 if (LABEL_P (barrier_or_label)
5722 && NEXT_INSN (barrier_or_label)
5723 && JUMP_TABLE_DATA_P (NEXT_INSN (barrier_or_label)))
5724 return 2;
5726 if (BARRIER_P (barrier_or_label)
5727 && PREV_INSN (barrier_or_label)
5728 && JUMP_TABLE_DATA_P (PREV_INSN (barrier_or_label)))
5730 rtx pat = PATTERN (PREV_INSN (barrier_or_label));
5731 /* If this is a very small table, we want to keep the alignment after
5732 the table to the minimum for proper code alignment. */
5733 return ((optimize_size
5734 || ((unsigned) XVECLEN (pat, 1) * GET_MODE_SIZE (GET_MODE (pat))
5735 <= (unsigned) 1 << (CACHE_LOG - 2)))
5736 ? 1 : align_jumps_log);
5739 rtx_insn *next = next_active_insn (barrier_or_label);
5741 if (! next)
5742 return 0;
5744 rtx pat = PATTERN (next);
5746 if (GET_CODE (pat) == UNSPEC_VOLATILE && XINT (pat, 1) == UNSPECV_ALIGN)
5747 /* This is a barrier in front of a constant table. */
5748 return 0;
5750 if (optimize_size)
5751 return 0;
5753 if (! TARGET_SH2 || ! optimize)
5754 return align_jumps_log;
5756 /* When fixing up pcloads, a constant table might be inserted just before
5757 the basic block that ends with the barrier. Thus, we can't trust the
5758 instruction lengths before that. */
5759 if (mdep_reorg_phase > SH_FIXUP_PCLOAD)
5761 /* Check if there is an immediately preceding branch to the insn beyond
5762 the barrier. We must weight the cost of discarding useful information
5763 from the current cache line when executing this branch and there is
5764 an alignment, against that of fetching unneeded insn in front of the
5765 branch target when there is no alignment. */
5767 /* There are two delay_slot cases to consider. One is the simple case
5768 where the preceding branch is to the insn beyond the barrier (simple
5769 delay slot filling), and the other is where the preceding branch has
5770 a delay slot that is a duplicate of the insn after the barrier
5771 (fill_eager_delay_slots) and the branch is to the insn after the insn
5772 after the barrier. */
5774 int slot, credit;
5775 bool jump_to_next = false;
5777 /* Skip to the insn before the JUMP_INSN before the barrier under
5778 investigation. */
5779 rtx_insn *prev = prev_real_insn (prev_active_insn (barrier_or_label));
5781 for (slot = 2, credit = (1 << (CACHE_LOG - 2)) + 2;
5782 credit >= 0 && prev && NONJUMP_INSN_P (prev);
5783 prev = prev_real_insn (prev))
5785 jump_to_next = false;
5786 if (GET_CODE (PATTERN (prev)) == USE
5787 || GET_CODE (PATTERN (prev)) == CLOBBER)
5788 continue;
5789 if (rtx_sequence *prev_seq = dyn_cast <rtx_sequence *> (PATTERN (prev)))
5791 prev = prev_seq->insn (1);
5792 if (INSN_UID (prev) == INSN_UID (next))
5794 /* Delay slot was filled with insn at jump target. */
5795 jump_to_next = true;
5796 continue;
5800 if (slot &&
5801 get_attr_in_delay_slot (prev) == IN_DELAY_SLOT_YES)
5802 slot = 0;
5803 credit -= get_attr_length (prev);
5805 if (prev && jump_to_label_p (prev))
5807 rtx_insn *x;
5808 if (jump_to_next
5809 || next_real_insn (JUMP_LABEL (prev)) == next
5810 /* If relax_delay_slots() decides NEXT was redundant
5811 with some previous instruction, it will have
5812 redirected PREV's jump to the following insn. */
5813 || JUMP_LABEL (prev) == next_nonnote_insn (next)
5814 /* There is no upper bound on redundant instructions
5815 that might have been skipped, but we must not put an
5816 alignment where none had been before. */
5817 || (x = (NEXT_INSN (NEXT_INSN (PREV_INSN (prev)))),
5818 (INSN_P (x)
5819 && (INSN_CODE (x) == CODE_FOR_block_branch_redirect
5820 || INSN_CODE (x) == CODE_FOR_indirect_jump_scratch
5821 || INSN_CODE (x) == CODE_FOR_stuff_delay_slot))))
5823 rtx pat = PATTERN (prev);
5824 if (GET_CODE (pat) == PARALLEL)
5825 pat = XVECEXP (pat, 0, 0);
5826 if (credit - slot >= (GET_CODE (SET_SRC (pat)) == PC ? 2 : 0))
5827 return 0;
5832 return align_jumps_log;
5835 /* If we are inside a phony loop, almost any kind of label can turn up as the
5836 first one in the loop. Aligning a braf label causes incorrect switch
5837 destination addresses; we can detect braf labels because they are
5838 followed by a BARRIER.
5839 Applying loop alignment to small constant or switch tables is a waste
5840 of space, so we suppress this too. */
5842 sh_loop_align (rtx_insn *label)
5844 rtx_insn *next = label;
5846 if (! optimize || optimize_size)
5847 return 0;
5850 next = next_nonnote_insn (next);
5851 while (next && LABEL_P (next));
5853 if (! next
5854 || ! INSN_P (next)
5855 || recog_memoized (next) == CODE_FOR_consttable_2)
5856 return 0;
5858 return align_loops_log;
5861 /* Do a final pass over the function, just before delayed branch
5862 scheduling. */
5863 static void
5864 sh_reorg (void)
5866 rtx_insn *first, *insn, *mova = NULL;
5867 int num_mova;
5868 rtx r0_rtx = gen_rtx_REG (Pmode, 0);
5869 rtx r0_inc_rtx = gen_rtx_POST_INC (Pmode, r0_rtx);
5871 first = get_insns ();
5872 max_labelno_before_reorg = max_label_num ();
5874 /* We must split call insns before introducing `mova's. If we're
5875 optimizing, they'll have already been split. Otherwise, make
5876 sure we don't split them too late. */
5877 if (! optimize)
5878 split_all_insns_noflow ();
5880 /* If relaxing, generate pseudo-ops to associate function calls with
5881 the symbols they call. It does no harm to not generate these
5882 pseudo-ops. However, when we can generate them, it enables the
5883 linker to potentially relax the jsr to a bsr, and eliminate the
5884 register load and, possibly, the constant pool entry. */
5886 mdep_reorg_phase = SH_INSERT_USES_LABELS;
5887 if (TARGET_RELAX)
5889 /* Remove all REG_LABEL_OPERAND notes. We want to use them for our
5890 own purposes. This works because none of the remaining passes
5891 need to look at them.
5893 ??? But it may break in the future. We should use a machine
5894 dependent REG_NOTE, or some other approach entirely. */
5895 for (insn = first; insn; insn = NEXT_INSN (insn))
5897 if (INSN_P (insn))
5899 rtx note;
5901 while ((note = find_reg_note (insn, REG_LABEL_OPERAND,
5902 NULL_RTX)) != 0)
5903 remove_note (insn, note);
5907 for (insn = first; insn; insn = NEXT_INSN (insn))
5909 rtx pattern, reg, set, dies;
5910 rtx_code_label *label;
5911 rtx_insn *link, *scan;
5912 int rescan = 0, foundinsn = 0;
5914 if (CALL_P (insn))
5916 pattern = PATTERN (insn);
5918 if (GET_CODE (pattern) == PARALLEL)
5919 pattern = XVECEXP (pattern, 0, 0);
5920 if (GET_CODE (pattern) == SET)
5921 pattern = SET_SRC (pattern);
5923 if (GET_CODE (pattern) != CALL
5924 || !MEM_P (XEXP (pattern, 0)))
5925 continue;
5927 reg = XEXP (XEXP (pattern, 0), 0);
5929 else
5931 reg = sfunc_uses_reg (insn);
5932 if (! reg)
5933 continue;
5936 if (!REG_P (reg))
5937 continue;
5939 /* Try scanning backward to find where the register is set. */
5940 link = NULL;
5941 for (scan = PREV_INSN (insn);
5942 scan && !LABEL_P (scan);
5943 scan = PREV_INSN (scan))
5945 if (! INSN_P (scan))
5946 continue;
5948 if (! reg_mentioned_p (reg, scan))
5949 continue;
5951 if (noncall_uses_reg (reg, scan, &set))
5952 break;
5954 if (set)
5956 link = scan;
5957 break;
5961 if (! link)
5962 continue;
5964 /* The register is set at LINK. */
5966 /* We can only optimize the function call if the register is
5967 being set to a symbol. In theory, we could sometimes
5968 optimize calls to a constant location, but the assembler
5969 and linker do not support that at present. */
5970 if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
5971 && GET_CODE (SET_SRC (set)) != LABEL_REF)
5972 continue;
5974 /* Scan forward from LINK to the place where REG dies, and
5975 make sure that the only insns which use REG are
5976 themselves function calls. */
5978 /* ??? This doesn't work for call targets that were allocated
5979 by reload, since there may not be a REG_DEAD note for the
5980 register. */
5982 dies = NULL_RTX;
5983 for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
5985 rtx scanset;
5987 /* Don't try to trace forward past a CODE_LABEL if we haven't
5988 seen INSN yet. Ordinarily, we will only find the setting insn
5989 if it is in the same basic block. However,
5990 cross-jumping can insert code labels in between the load and
5991 the call, and can result in situations where a single call
5992 insn may have two targets depending on where we came from. */
5994 if (LABEL_P (scan) && ! foundinsn)
5995 break;
5997 if (! INSN_P (scan))
5998 continue;
6000 /* Don't try to trace forward past a JUMP. To optimize
6001 safely, we would have to check that all the
6002 instructions at the jump destination did not use REG. */
6004 if (JUMP_P (scan))
6005 break;
6007 if (! reg_mentioned_p (reg, scan))
6008 continue;
6010 if (noncall_uses_reg (reg, scan, &scanset))
6011 break;
6013 if (scan == insn)
6014 foundinsn = 1;
6016 if (scan != insn
6017 && (CALL_P (scan) || sfunc_uses_reg (scan)))
6019 /* There is a function call to this register other
6020 than the one we are checking. If we optimize
6021 this call, we need to rescan again below. */
6022 rescan = 1;
6025 /* ??? We shouldn't have to worry about SCANSET here.
6026 We should just be able to check for a REG_DEAD note
6027 on a function call. However, the REG_DEAD notes are
6028 apparently not dependable around libcalls; c-torture
6029 execute/920501-2 is a test case. If SCANSET is set,
6030 then this insn sets the register, so it must have
6031 died earlier. Unfortunately, this will only handle
6032 the cases in which the register is, in fact, set in a
6033 later insn. */
6035 /* ??? We shouldn't have to use FOUNDINSN here.
6036 This dates back to when we used LOG_LINKS to find
6037 the most recent insn which sets the register. */
6039 if (foundinsn
6040 && (scanset
6041 || find_reg_note (scan, REG_DEAD, reg)))
6043 dies = scan;
6044 break;
6048 if (! dies)
6050 /* Either there was a branch, or some insn used REG
6051 other than as a function call address. */
6052 continue;
6055 /* Create a code label, and put it in a REG_LABEL_OPERAND note
6056 on the insn which sets the register, and on each call insn
6057 which uses the register. In final_prescan_insn we look for
6058 the REG_LABEL_OPERAND notes, and output the appropriate label
6059 or pseudo-op. */
6061 label = gen_label_rtx ();
6062 add_reg_note (link, REG_LABEL_OPERAND, label);
6063 add_reg_note (insn, REG_LABEL_OPERAND, label);
6064 if (rescan)
6066 scan = link;
6069 rtx reg2;
6071 scan = NEXT_INSN (scan);
6072 if (scan != insn
6073 && ((CALL_P (scan)
6074 && reg_mentioned_p (reg, scan))
6075 || ((reg2 = sfunc_uses_reg (scan))
6076 && REGNO (reg2) == REGNO (reg))))
6077 add_reg_note (scan, REG_LABEL_OPERAND, label);
6079 while (scan != dies);
6084 if (TARGET_SH2)
6085 fixup_addr_diff_vecs (first);
6087 if (optimize)
6089 mdep_reorg_phase = SH_SHORTEN_BRANCHES0;
6090 shorten_branches (first);
6093 /* Scan the function looking for move instructions which have to be
6094 changed to pc-relative loads and insert the literal tables. */
6095 mdep_reorg_phase = SH_FIXUP_PCLOAD;
6096 for (insn = first, num_mova = 0; insn; insn = NEXT_INSN (insn))
6098 if (mova_p (insn))
6100 /* ??? basic block reordering can move a switch table dispatch
6101 below the switch table. Check if that has happened.
6102 We only have the addresses available when optimizing; but then,
6103 this check shouldn't be needed when not optimizing. */
6104 if (!untangle_mova (&num_mova, &mova, insn))
6106 insn = mova;
6107 num_mova = 0;
6110 else if (JUMP_TABLE_DATA_P (insn)
6111 && GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
6112 && num_mova
6113 /* ??? loop invariant motion can also move a mova out of a
6114 loop. Since loop does this code motion anyway, maybe we
6115 should wrap UNSPEC_MOVA into a CONST, so that reload can
6116 move it back. */
6117 && ((num_mova > 1
6118 && GET_MODE (prev_nonnote_insn (insn)) == VOIDmode)
6119 || (prev_nonnote_insn (insn)
6120 == XEXP (MOVA_LABELREF (mova), 0))))
6122 rtx_insn *scan;
6123 int total;
6125 num_mova--;
6127 /* Some code might have been inserted between the mova and
6128 its ADDR_DIFF_VEC. Check if the mova is still in range. */
6129 for (scan = mova, total = 0; scan != insn; scan = NEXT_INSN (scan))
6130 total += get_attr_length (scan);
6132 /* range of mova is 1020, add 4 because pc counts from address of
6133 second instruction after this one, subtract 2 in case pc is 2
6134 byte aligned. Possible alignment needed for the ADDR_DIFF_VEC
6135 cancels out with alignment effects of the mova itself. */
6136 if (total > 1022)
6138 /* Change the mova into a load, and restart scanning
6139 there. broken_move will then return true for mova. */
6140 fixup_mova (mova);
6141 insn = mova;
6144 if (broken_move (insn)
6145 || (NONJUMP_INSN_P (insn)
6146 && recog_memoized (insn) == CODE_FOR_casesi_worker_2))
6148 rtx_insn *scan;
6149 /* Scan ahead looking for a barrier to stick the constant table
6150 behind. */
6151 rtx_insn *barrier = find_barrier (num_mova, mova, insn);
6152 rtx_insn *last_float_move = NULL;
6153 rtx last_float = 0, *last_float_addr = NULL;
6154 int need_aligned_label = 0;
6156 if (num_mova && ! mova_p (mova))
6158 /* find_barrier had to change the first mova into a
6159 pcload; thus, we have to start with this new pcload. */
6160 insn = mova;
6161 num_mova = 0;
6163 /* Now find all the moves between the points and modify them. */
6164 for (scan = insn; scan != barrier; scan = NEXT_INSN (scan))
6166 if (LABEL_P (scan))
6167 last_float = 0;
6168 if (NONJUMP_INSN_P (scan)
6169 && recog_memoized (scan) == CODE_FOR_casesi_worker_2)
6170 need_aligned_label = 1;
6171 if (broken_move (scan))
6173 rtx *patp = &PATTERN (scan), pat = *patp;
6174 rtx src, dst;
6175 rtx lab;
6176 rtx newsrc;
6177 machine_mode mode;
6179 if (GET_CODE (pat) == PARALLEL)
6180 patp = &XVECEXP (pat, 0, 0), pat = *patp;
6181 src = SET_SRC (pat);
6182 dst = SET_DEST (pat);
6183 mode = GET_MODE (dst);
6185 if (mode == SImode && satisfies_constraint_I16 (src)
6186 && REGNO (dst) != FPUL_REG)
6188 int offset = 0;
6190 mode = HImode;
6191 while (GET_CODE (dst) == SUBREG)
6193 offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
6194 GET_MODE (SUBREG_REG (dst)),
6195 SUBREG_BYTE (dst),
6196 GET_MODE (dst));
6197 dst = SUBREG_REG (dst);
6199 dst = gen_rtx_REG (HImode, REGNO (dst) + offset);
6201 if (REG_P (dst) && FP_ANY_REGISTER_P (REGNO (dst)))
6203 /* This must be an insn that clobbers r0. */
6204 rtx *clobberp = &XVECEXP (PATTERN (scan), 0,
6205 XVECLEN (PATTERN (scan), 0)
6206 - 1);
6207 rtx clobber = *clobberp;
6209 gcc_assert (GET_CODE (clobber) == CLOBBER
6210 && rtx_equal_p (XEXP (clobber, 0), r0_rtx));
6212 if (last_float
6213 && reg_set_between_p (r0_rtx, last_float_move, scan))
6214 last_float = 0;
6215 lab = add_constant (src, mode, last_float);
6216 if (lab)
6217 emit_insn_before (gen_mova (lab), scan);
6218 else
6220 /* There will be a REG_UNUSED note for r0 on
6221 LAST_FLOAT_MOVE; we have to change it to REG_INC,
6222 lest reorg:mark_target_live_regs will not
6223 consider r0 to be used, and we end up with delay
6224 slot insn in front of SCAN that clobbers r0. */
6225 rtx note
6226 = find_regno_note (last_float_move, REG_UNUSED, 0);
6228 /* If we are not optimizing, then there may not be
6229 a note. */
6230 if (note)
6231 PUT_REG_NOTE_KIND (note, REG_INC);
6233 *last_float_addr = r0_inc_rtx;
6235 last_float_move = scan;
6236 last_float = src;
6237 newsrc = gen_const_mem (mode,
6238 (((TARGET_SH4 && ! TARGET_FMOVD)
6239 || REGNO (dst) == FPUL_REG)
6240 ? r0_inc_rtx
6241 : r0_rtx));
6242 last_float_addr = &XEXP (newsrc, 0);
6244 /* Remove the clobber of r0. */
6245 *clobberp = gen_rtx_CLOBBER (GET_MODE (clobber),
6246 gen_rtx_SCRATCH (Pmode));
6248 /* This is a mova needing a label. Create it. */
6249 else if (GET_CODE (src) == UNSPEC
6250 && XINT (src, 1) == UNSPEC_MOVA
6251 && GET_CODE (XVECEXP (src, 0, 0)) == CONST)
6253 lab = add_constant (XVECEXP (src, 0, 0), mode, 0);
6254 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
6255 newsrc = gen_rtx_UNSPEC (SImode,
6256 gen_rtvec (1, newsrc),
6257 UNSPEC_MOVA);
6259 else if (GET_CODE (src) == UNSPEC_VOLATILE
6260 && XINT (src, 1) == UNSPECV_SP_SWITCH_B)
6262 newsrc = XVECEXP (src, 0, 0);
6263 XVECEXP (src, 0, 0) = gen_const_mem (mode, newsrc);
6264 INSN_CODE (scan) = -1;
6265 continue;
6267 else
6269 lab = add_constant (src, mode, 0);
6270 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
6271 newsrc = gen_const_mem (mode, newsrc);
6273 *patp = gen_rtx_SET (dst, newsrc);
6274 INSN_CODE (scan) = -1;
6277 dump_table (need_aligned_label ? insn : 0, barrier);
6278 insn = barrier;
6281 label_ref_list_d_pool.release ();
6282 for (insn = first; insn; insn = NEXT_INSN (insn))
6283 PUT_MODE (insn, VOIDmode);
6285 mdep_reorg_phase = SH_SHORTEN_BRANCHES1;
6286 INSN_ADDRESSES_FREE ();
6287 split_branches (first);
6289 /* The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
6290 also has an effect on the register that holds the address of the sfunc.
6291 Insert an extra dummy insn in front of each sfunc that pretends to
6292 use this register. */
6293 if (flag_delayed_branch)
6295 for (insn = first; insn; insn = NEXT_INSN (insn))
6297 rtx reg = sfunc_uses_reg (insn);
6299 if (! reg)
6300 continue;
6301 emit_insn_before (gen_use_sfunc_addr (reg), insn);
6304 mdep_reorg_phase = SH_AFTER_MDEP_REORG;
6307 /* Return the UID of the insn that follows the specified label. */
6309 get_dest_uid (rtx label, int max_uid)
6311 rtx_insn *dest = next_real_insn (label);
6313 if (! dest)
6314 /* This can happen for an undefined label. */
6315 return 0;
6316 int dest_uid = INSN_UID (dest);
6317 /* If this is a newly created branch redirection blocking instruction,
6318 we cannot index the branch_uid or insn_addresses arrays with its
6319 uid. But then, we won't need to, because the actual destination is
6320 the following branch. */
6321 while (dest_uid >= max_uid)
6323 dest = NEXT_INSN (dest);
6324 dest_uid = INSN_UID (dest);
6326 if (JUMP_P (dest) && GET_CODE (PATTERN (dest)) == RETURN)
6327 return 0;
6328 return dest_uid;
6331 /* Split condbranches that are out of range. Also add clobbers for
6332 scratch registers that are needed in far jumps.
6333 We do this before delay slot scheduling, so that it can take our
6334 newly created instructions into account. It also allows us to
6335 find branches with common targets more easily. */
6336 static void
6337 split_branches (rtx_insn *first)
6339 rtx_insn *insn;
6340 struct far_branch **uid_branch, *far_branch_list = 0;
6341 int max_uid = get_max_uid ();
6342 int ok;
6344 /* Find out which branches are out of range. */
6345 shorten_branches (first);
6347 uid_branch = (struct far_branch **) alloca (max_uid * sizeof *uid_branch);
6348 memset ((char *) uid_branch, 0, max_uid * sizeof *uid_branch);
6350 for (insn = first; insn; insn = NEXT_INSN (insn))
6351 if (! INSN_P (insn))
6352 continue;
6353 else if (insn->deleted ())
6355 /* Shorten_branches would split this instruction again,
6356 so transform it into a note. */
6357 SET_INSN_DELETED (insn);
6359 else if (JUMP_P (insn))
6361 enum attr_type type = get_attr_type (insn);
6362 if (type == TYPE_CBRANCH)
6364 rtx_insn *next, *beyond;
6366 if (get_attr_length (insn) > 4)
6368 rtx src = SET_SRC (PATTERN (insn));
6369 rtx olabel = XEXP (XEXP (src, 1), 0);
6370 int addr = INSN_ADDRESSES (INSN_UID (insn));
6371 rtx_insn *label = 0;
6372 int dest_uid = get_dest_uid (olabel, max_uid);
6373 struct far_branch *bp = uid_branch[dest_uid];
6375 /* redirect_jump needs a valid JUMP_LABEL, and it might delete
6376 the label if the LABEL_NUSES count drops to zero. There is
6377 always a jump_optimize pass that sets these values, but it
6378 proceeds to delete unreferenced code, and then if not
6379 optimizing, to un-delete the deleted instructions, thus
6380 leaving labels with too low uses counts. */
6381 if (! optimize)
6383 JUMP_LABEL (insn) = olabel;
6384 LABEL_NUSES (olabel)++;
6386 if (! bp)
6388 bp = (struct far_branch *) alloca (sizeof *bp);
6389 uid_branch[dest_uid] = bp;
6390 bp->prev = far_branch_list;
6391 far_branch_list = bp;
6392 bp->far_label = as_a <rtx_insn *> (
6393 XEXP (XEXP (SET_SRC (PATTERN (insn)), 1),
6394 0));
6395 LABEL_NUSES (bp->far_label)++;
6397 else
6399 label = bp->near_label;
6400 if (! label && bp->address - addr >= CONDJUMP_MIN)
6402 rtx_insn *block = bp->insert_place;
6404 if (GET_CODE (PATTERN (block)) == RETURN)
6405 block = PREV_INSN (block);
6406 else
6407 block = gen_block_redirect (block,
6408 bp->address, 2);
6409 label = emit_label_after (gen_label_rtx (),
6410 PREV_INSN (block));
6411 bp->near_label = label;
6413 else if (label && ! NEXT_INSN (label))
6415 if (addr + 2 - bp->address <= CONDJUMP_MAX)
6416 bp->insert_place = insn;
6417 else
6418 gen_far_branch (bp);
6421 if (! label
6422 || (NEXT_INSN (label) && bp->address - addr < CONDJUMP_MIN))
6424 bp->near_label = label = gen_label_rtx ();
6425 bp->insert_place = insn;
6426 bp->address = addr;
6428 ok = redirect_jump (as_a <rtx_jump_insn *> (insn), label, 0);
6429 gcc_assert (ok);
6431 else
6433 /* get_attr_length (insn) == 2 */
6434 /* Check if we have a pattern where reorg wants to redirect
6435 the branch to a label from an unconditional branch that
6436 is too far away. */
6437 /* We can't use JUMP_LABEL here because it might be undefined
6438 when not optimizing. */
6439 /* A syntax error might cause beyond to be NULL_RTX. */
6440 rtx temp = XEXP (XEXP (SET_SRC (PATTERN (insn)), 1), 0);
6441 beyond = next_active_insn (as_a<rtx_insn *> (temp));
6443 if (beyond
6444 && (JUMP_P (beyond)
6445 || ((beyond = next_active_insn (beyond))
6446 && JUMP_P (beyond)))
6447 && GET_CODE (PATTERN (beyond)) == SET
6448 && recog_memoized (beyond) == CODE_FOR_jump_compact
6449 && ((INSN_ADDRESSES
6450 (INSN_UID (XEXP (SET_SRC (PATTERN (beyond)), 0)))
6451 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
6452 > 252 + 258 + 2))
6453 gen_block_redirect (beyond,
6454 INSN_ADDRESSES (INSN_UID (beyond)), 1);
6457 next = next_active_insn (insn);
6459 if (next
6460 && (JUMP_P (next)
6461 || ((next = next_active_insn (next))
6462 && JUMP_P (next)))
6463 && GET_CODE (PATTERN (next)) == SET
6464 && recog_memoized (next) == CODE_FOR_jump_compact
6465 && ((INSN_ADDRESSES
6466 (INSN_UID (XEXP (SET_SRC (PATTERN (next)), 0)))
6467 - INSN_ADDRESSES (INSN_UID (insn)) + (unsigned) 252)
6468 > 252 + 258 + 2))
6469 gen_block_redirect (next, INSN_ADDRESSES (INSN_UID (next)), 1);
6471 else if (type == TYPE_JUMP || type == TYPE_RETURN)
6473 int addr = INSN_ADDRESSES (INSN_UID (insn));
6474 rtx_insn *far_label = 0;
6475 int dest_uid = 0;
6476 struct far_branch *bp;
6478 if (type == TYPE_JUMP)
6480 if (CROSSING_JUMP_P (insn))
6482 emit_insn_before (gen_block_branch_redirect (const0_rtx),
6483 insn);
6484 continue;
6487 far_label = as_a <rtx_insn *> (
6488 XEXP (SET_SRC (PATTERN (insn)), 0));
6489 dest_uid = get_dest_uid (far_label, max_uid);
6490 if (! dest_uid)
6492 /* Parse errors can lead to labels outside
6493 the insn stream. */
6494 if (! NEXT_INSN (far_label))
6495 continue;
6497 if (! optimize)
6499 JUMP_LABEL (insn) = far_label;
6500 LABEL_NUSES (far_label)++;
6502 redirect_jump (as_a <rtx_jump_insn *> (insn), ret_rtx, 1);
6503 far_label = 0;
6506 bp = uid_branch[dest_uid];
6507 if (! bp)
6509 bp = (struct far_branch *) alloca (sizeof *bp);
6510 uid_branch[dest_uid] = bp;
6511 bp->prev = far_branch_list;
6512 far_branch_list = bp;
6513 bp->near_label = 0;
6514 bp->far_label = far_label;
6515 if (far_label)
6516 LABEL_NUSES (far_label)++;
6518 else if (bp->near_label && ! NEXT_INSN (bp->near_label))
6519 if (addr - bp->address <= CONDJUMP_MAX)
6520 emit_label_after (bp->near_label, PREV_INSN (insn));
6521 else
6523 gen_far_branch (bp);
6524 bp->near_label = 0;
6526 else
6527 bp->near_label = 0;
6528 bp->address = addr;
6529 bp->insert_place = insn;
6530 if (! far_label)
6531 emit_insn_before (gen_block_branch_redirect (const0_rtx), insn);
6532 else
6533 gen_block_redirect (insn, addr, bp->near_label ? 2 : 0);
6536 /* Generate all pending far branches,
6537 and free our references to the far labels. */
6538 while (far_branch_list)
6540 if (far_branch_list->near_label
6541 && ! NEXT_INSN (far_branch_list->near_label))
6542 gen_far_branch (far_branch_list);
6543 if (optimize
6544 && far_branch_list->far_label
6545 && ! --LABEL_NUSES (far_branch_list->far_label))
6546 delete_insn (far_branch_list->far_label);
6547 far_branch_list = far_branch_list->prev;
6550 /* Instruction length information is no longer valid due to the new
6551 instructions that have been generated. */
6552 init_insn_lengths ();
6555 /* Dump out instruction addresses, which is useful for debugging the
6556 constant pool table stuff.
6558 If relaxing, output the label and pseudo-ops used to link together
6559 calls and the instruction which set the registers.
6561 ??? The addresses printed by this routine for insns are nonsense for
6562 insns which are inside of a sequence where none of the inner insns have
6563 variable length. This is because the second pass of shorten_branches
6564 does not bother to update them. */
6565 void
6566 final_prescan_insn (rtx_insn *insn, rtx *opvec ATTRIBUTE_UNUSED,
6567 int noperands ATTRIBUTE_UNUSED)
6569 if (TARGET_DUMPISIZE)
6570 fprintf (asm_out_file, "\n! at %04x\n", INSN_ADDRESSES (INSN_UID (insn)));
6572 if (TARGET_RELAX)
6574 if (rtx note = find_reg_note (insn, REG_LABEL_OPERAND, NULL_RTX))
6576 rtx pattern = PATTERN (insn);
6577 if (GET_CODE (pattern) == PARALLEL)
6578 pattern = XVECEXP (pattern, 0, 0);
6579 switch (GET_CODE (pattern))
6581 case SET:
6582 if (GET_CODE (SET_SRC (pattern)) != CALL
6583 && get_attr_type (insn) != TYPE_SFUNC)
6585 targetm.asm_out.internal_label
6586 (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (note, 0)));
6587 break;
6589 /* FALLTHROUGH */
6590 case CALL:
6591 asm_fprintf (asm_out_file, "\t.uses %LL%d\n",
6592 CODE_LABEL_NUMBER (XEXP (note, 0)));
6593 break;
6595 default:
6596 gcc_unreachable ();
6602 /* Dump out any constants accumulated in the final pass. These will
6603 only be labels. */
6604 const char *
6605 output_jump_label_table (void)
6607 if (pool_size)
6609 fprintf (asm_out_file, "\t.align 2\n");
6610 for (int i = 0; i < pool_size; i++)
6612 pool_node *p = &pool_vector[i];
6614 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6615 CODE_LABEL_NUMBER (p->label));
6616 output_asm_insn (".long %O0", &p->value);
6618 pool_size = 0;
6621 return "";
6624 /* A full frame looks like:
6626 arg-5
6627 arg-4
6628 [ if current_function_anonymous_args
6629 arg-3
6630 arg-2
6631 arg-1
6632 arg-0 ]
6633 saved-fp
6634 saved-r10
6635 saved-r11
6636 saved-r12
6637 saved-pr
6638 local-n
6640 local-1
6641 local-0 <- fp points here.
6643 Number of bytes pushed for anonymous args, used to pass information
6644 between expand_prologue and expand_epilogue.
6646 Adjust the stack by SIZE bytes. REG holds the rtl of the register to be
6647 adjusted. If epilogue_p is zero, this is for a prologue; otherwise, it's
6648 for an epilogue and a negative value means that it's for a sibcall
6649 epilogue. If LIVE_REGS_MASK is nonzero, it points to a HARD_REG_SET of
6650 all the registers that are about to be restored, and hence dead. */
6651 static void
6652 output_stack_adjust (int size, rtx reg, int epilogue_p,
6653 HARD_REG_SET *live_regs_mask, bool frame_p)
6655 rtx_insn *(*emit_fn) (rtx) = frame_p ? &emit_frame_insn : &emit_insn;
6656 if (size)
6658 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
6660 /* This test is bogus, as output_stack_adjust is used to re-align the
6661 stack. */
6662 #if 0
6663 gcc_assert (!(size % align));
6664 #endif
6666 if (CONST_OK_FOR_ADD (size))
6667 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size)));
6668 /* Try to do it with two partial adjustments; however, we must make
6669 sure that the stack is properly aligned at all times, in case
6670 an interrupt occurs between the two partial adjustments. */
6671 else if (CONST_OK_FOR_ADD (size / 2 & -align)
6672 && CONST_OK_FOR_ADD (size - (size / 2 & -align)))
6674 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size / 2 & -align)));
6675 emit_fn (GEN_ADD3 (reg, reg, GEN_INT (size - (size / 2 & -align))));
6677 else
6679 rtx const_reg;
6680 rtx insn;
6681 int temp = epilogue_p ? 7 : 1;
6682 int i;
6684 /* If TEMP is invalid, we could temporarily save a general
6685 register to MACL. However, there is currently no need
6686 to handle this case, so just die when we see it. */
6687 if (epilogue_p < 0
6688 || current_function_interrupt
6689 || ! call_really_used_regs[temp] || fixed_regs[temp])
6690 temp = -1;
6691 if (temp < 0 && ! current_function_interrupt && epilogue_p >= 0)
6693 HARD_REG_SET temps;
6694 COPY_HARD_REG_SET (temps, call_used_reg_set);
6695 AND_COMPL_HARD_REG_SET (temps, call_fixed_reg_set);
6696 if (epilogue_p > 0)
6698 int nreg = 0;
6699 if (crtl->return_rtx)
6701 machine_mode mode;
6702 mode = GET_MODE (crtl->return_rtx);
6703 if (BASE_RETURN_VALUE_REG (mode) == FIRST_RET_REG)
6704 nreg = hard_regno_nregs (FIRST_RET_REG, mode);
6706 for (i = 0; i < nreg; i++)
6707 CLEAR_HARD_REG_BIT (temps, FIRST_RET_REG + i);
6708 if (crtl->calls_eh_return)
6710 CLEAR_HARD_REG_BIT (temps, EH_RETURN_STACKADJ_REGNO);
6711 for (i = 0; i <= 3; i++)
6712 CLEAR_HARD_REG_BIT (temps, EH_RETURN_DATA_REGNO (i));
6715 if (epilogue_p <= 0)
6717 for (i = FIRST_PARM_REG;
6718 i < FIRST_PARM_REG + NPARM_REGS (SImode); i++)
6719 CLEAR_HARD_REG_BIT (temps, i);
6720 if (cfun->static_chain_decl != NULL)
6721 CLEAR_HARD_REG_BIT (temps, STATIC_CHAIN_REGNUM);
6723 temp = scavenge_reg (&temps);
6725 if (temp < 0 && live_regs_mask)
6727 HARD_REG_SET temps;
6729 COPY_HARD_REG_SET (temps, *live_regs_mask);
6730 CLEAR_HARD_REG_BIT (temps, REGNO (reg));
6731 temp = scavenge_reg (&temps);
6733 if (temp < 0)
6735 rtx adj_reg, tmp_reg, mem;
6737 /* If we reached here, the most likely case is the (sibcall)
6738 epilogue. Put a special push/pop sequence for such case as
6739 the last resort. This looks lengthy but would not be problem
6740 because it seems to be very rare. */
6741 gcc_assert (epilogue_p);
6743 /* ??? There is still the slight possibility that r4 or
6744 r5 have been reserved as fixed registers or assigned
6745 as global registers, and they change during an
6746 interrupt. There are possible ways to handle this:
6748 - If we are adjusting the frame pointer (r14), we can do
6749 with a single temp register and an ordinary push / pop
6750 on the stack.
6751 - Grab any call-used or call-saved registers (i.e. not
6752 fixed or globals) for the temps we need. We might
6753 also grab r14 if we are adjusting the stack pointer.
6754 If we can't find enough available registers, issue
6755 a diagnostic and die - the user must have reserved
6756 way too many registers.
6757 But since all this is rather unlikely to happen and
6758 would require extra testing, we just die if r4 / r5
6759 are not available. */
6760 gcc_assert (!fixed_regs[4] && !fixed_regs[5]
6761 && !global_regs[4] && !global_regs[5]);
6763 adj_reg = gen_rtx_REG (GET_MODE (reg), 4);
6764 tmp_reg = gen_rtx_REG (GET_MODE (reg), 5);
6765 emit_move_insn (gen_tmp_stack_mem (Pmode, reg), adj_reg);
6766 emit_insn (GEN_MOV (adj_reg, GEN_INT (size)));
6767 emit_insn (GEN_ADD3 (adj_reg, adj_reg, reg));
6768 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6769 emit_move_insn (mem, tmp_reg);
6770 emit_move_insn (tmp_reg, gen_tmp_stack_mem (Pmode, reg));
6771 mem = gen_tmp_stack_mem (Pmode, gen_rtx_PRE_DEC (Pmode, adj_reg));
6772 emit_move_insn (mem, tmp_reg);
6773 emit_move_insn (reg, adj_reg);
6774 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6775 emit_move_insn (adj_reg, mem);
6776 mem = gen_tmp_stack_mem (Pmode, gen_rtx_POST_INC (Pmode, reg));
6777 emit_move_insn (tmp_reg, mem);
6778 /* Tell flow the insns that pop r4/r5 aren't dead. */
6779 emit_use (tmp_reg);
6780 emit_use (adj_reg);
6781 return;
6783 const_reg = gen_rtx_REG (GET_MODE (reg), temp);
6785 /* If SIZE is negative, subtract the positive value.
6786 This sometimes allows a constant pool entry to be shared
6787 between prologue and epilogue code. */
6788 if (size < 0)
6790 emit_insn (GEN_MOV (const_reg, GEN_INT (-size)));
6791 insn = emit_fn (GEN_SUB3 (reg, reg, const_reg));
6793 else
6795 emit_insn (GEN_MOV (const_reg, GEN_INT (size)));
6796 insn = emit_fn (GEN_ADD3 (reg, reg, const_reg));
6798 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
6799 gen_rtx_SET (reg, gen_rtx_PLUS (SImode, reg,
6800 GEN_INT (size))));
6805 /* Emit the specified insn and mark it as frame related. */
6806 static rtx_insn *
6807 emit_frame_insn (rtx x)
6809 rtx_insn *insn = emit_insn (x);
6810 RTX_FRAME_RELATED_P (insn) = 1;
6811 return insn;
6814 /* Output RTL to push register RN onto the stack. */
6815 static rtx
6816 push (int rn)
6818 rtx x;
6819 if (rn == FPUL_REG)
6820 x = gen_push_fpul ();
6821 else if (rn == FPSCR_REG)
6822 x = gen_push_fpscr ();
6823 else if (TARGET_FPU_DOUBLE && TARGET_FMOVD
6824 && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P (rn))
6826 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6827 return NULL_RTX;
6828 x = gen_push_4 (gen_rtx_REG (DFmode, rn));
6830 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6831 x = gen_push_e (gen_rtx_REG (SFmode, rn));
6832 else
6833 x = gen_push (gen_rtx_REG (SImode, rn));
6835 x = emit_frame_insn (x);
6836 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6837 return x;
6840 /* Output RTL to pop register RN from the stack. */
6841 static void
6842 pop (int rn)
6844 rtx x, sp_reg, reg;
6845 if (rn == FPUL_REG)
6846 x = gen_pop_fpul ();
6847 else if (rn == FPSCR_REG)
6848 x = gen_pop_fpscr ();
6849 else if (TARGET_FPU_DOUBLE && TARGET_FMOVD
6850 && ! TARGET_FPU_SINGLE && FP_OR_XD_REGISTER_P (rn))
6852 if (FP_REGISTER_P (rn) && (rn - FIRST_FP_REG) & 1)
6853 return;
6854 x = gen_pop_4 (gen_rtx_REG (DFmode, rn));
6856 else if (TARGET_SH2E && FP_REGISTER_P (rn))
6857 x = gen_pop_e (gen_rtx_REG (SFmode, rn));
6858 else
6859 x = gen_pop (gen_rtx_REG (SImode, rn));
6861 x = emit_insn (x);
6863 sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM);
6864 reg = copy_rtx (GET_CODE (PATTERN (x)) == PARALLEL
6865 ? SET_DEST (XVECEXP (PATTERN (x), 0, 0))
6866 : SET_DEST (PATTERN (x)));
6867 add_reg_note (x, REG_CFA_RESTORE, reg);
6868 add_reg_note (x, REG_CFA_ADJUST_CFA,
6869 gen_rtx_SET (sp_reg,
6870 plus_constant (SImode, sp_reg,
6871 GET_MODE_SIZE (GET_MODE (reg)))));
6872 add_reg_note (x, REG_INC, gen_rtx_REG (SImode, STACK_POINTER_REGNUM));
6873 RTX_FRAME_RELATED_P (x) = 1;
6876 /* Generate code to push the regs specified in the mask. */
6877 static void
6878 push_regs (HARD_REG_SET *mask, bool interrupt_handler)
6880 bool skip_fpscr = false;
6882 /* Push PR last; this gives better latencies after the prologue, and
6883 candidates for the return delay slot when there are no general
6884 registers pushed. */
6885 for (int i = interrupt_handler ? LAST_BANKED_REG + 1 : 0;
6886 i < FIRST_PSEUDO_REGISTER; i++)
6888 /* If this is an interrupt handler, and the SZ bit varies,
6889 and we have to push any floating point register, we need
6890 to switch to the correct precision first. */
6891 if (i == FIRST_FP_REG && interrupt_handler && TARGET_FMOVD
6892 && hard_reg_set_intersect_p (*mask, reg_class_contents[DF_REGS]))
6894 HARD_REG_SET unsaved;
6896 push (FPSCR_REG);
6897 COMPL_HARD_REG_SET (unsaved, *mask);
6898 fpscr_set_from_mem (NORMAL_MODE (FP_MODE), unsaved);
6899 skip_fpscr = true;
6901 if (i != PR_REG
6902 && (i != FPSCR_REG || ! skip_fpscr)
6903 && TEST_HARD_REG_BIT (*mask, i))
6905 /* If the ISR has RESBANK attribute assigned, don't push any of
6906 the following registers - R0-R14, MACH, MACL and GBR. */
6907 if (! (sh_cfun_resbank_handler_p ()
6908 && ((i >= FIRST_GENERAL_REG && i < LAST_GENERAL_REG)
6909 || i == MACH_REG
6910 || i == MACL_REG
6911 || i == GBR_REG)))
6912 push (i);
6916 /* Push banked registers last to improve delay slot opportunities. */
6917 if (interrupt_handler)
6919 bool use_movml = false;
6921 if (TARGET_SH2A)
6923 unsigned int count = 0;
6925 for (int i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6926 if (TEST_HARD_REG_BIT (*mask, i))
6927 count++;
6928 else
6929 break;
6931 /* Use movml when all banked registers are pushed. */
6932 if (count == LAST_BANKED_REG - FIRST_BANKED_REG + 1)
6933 use_movml = true;
6936 if (sh_cfun_resbank_handler_p ())
6937 ; /* Do nothing. */
6938 else if (use_movml)
6940 rtx x, mem, reg, set;
6941 rtx sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM);
6943 /* We must avoid scheduling multiple store insn with another
6944 insns. */
6945 emit_insn (gen_blockage ());
6946 x = gen_movml_push_banked (sp_reg);
6947 x = emit_frame_insn (x);
6948 for (int i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6950 mem = gen_rtx_MEM (SImode, plus_constant (Pmode, sp_reg, i * 4));
6951 reg = gen_rtx_REG (SImode, i);
6952 add_reg_note (x, REG_CFA_OFFSET, gen_rtx_SET (mem, reg));
6955 set = gen_rtx_SET (sp_reg, plus_constant (Pmode, sp_reg, - 32));
6956 add_reg_note (x, REG_CFA_ADJUST_CFA, set);
6957 emit_insn (gen_blockage ());
6959 else
6960 for (int i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
6961 if (TEST_HARD_REG_BIT (*mask, i))
6962 push (i);
6965 /* Don't push PR register for an ISR with RESBANK attribute assigned. */
6966 if (TEST_HARD_REG_BIT (*mask, PR_REG) && !sh_cfun_resbank_handler_p ())
6967 push (PR_REG);
6970 /* Work out the registers which need to be saved, both as a mask and a
6971 count of saved words. Return the count.
6973 If doing a pragma interrupt function, then push all regs used by the
6974 function, and if we call another function (we can tell by looking at PR),
6975 make sure that all the regs it clobbers are safe too. */
6976 static int
6977 calc_live_regs (HARD_REG_SET *live_regs_mask)
6979 unsigned int reg;
6980 tree attrs;
6981 bool interrupt_or_trapa_handler, trapa_handler, interrupt_handler;
6982 bool nosave_low_regs;
6984 attrs = DECL_ATTRIBUTES (current_function_decl);
6985 interrupt_or_trapa_handler = sh_cfun_interrupt_handler_p ();
6986 trapa_handler = lookup_attribute ("trapa_handler", attrs) != NULL_TREE;
6987 interrupt_handler = interrupt_or_trapa_handler && ! trapa_handler;
6988 nosave_low_regs = lookup_attribute ("nosave_low_regs", attrs) != NULL_TREE;
6990 CLEAR_HARD_REG_SET (*live_regs_mask);
6991 if (TARGET_FPU_DOUBLE && TARGET_FMOVD && interrupt_handler
6992 && df_regs_ever_live_p (FPSCR_REG))
6993 target_flags &= ~MASK_FPU_SINGLE;
6994 /* If we can save a lot of saves by switching to double mode, do that. */
6995 else if (TARGET_FPU_DOUBLE && TARGET_FMOVD && TARGET_FPU_SINGLE)
6996 for (int count = 0, reg = FIRST_FP_REG; reg <= LAST_FP_REG; reg += 2)
6997 if (df_regs_ever_live_p (reg) && df_regs_ever_live_p (reg+1)
6998 && (! call_really_used_regs[reg]
6999 || interrupt_handler)
7000 && ++count > 2)
7002 target_flags &= ~MASK_FPU_SINGLE;
7003 break;
7007 rtx pr_initial = has_hard_reg_initial_val (Pmode, PR_REG);
7008 bool pr_live = (pr_initial
7009 ? (!REG_P (pr_initial)
7010 || REGNO (pr_initial) != (PR_REG))
7011 : df_regs_ever_live_p (PR_REG));
7012 /* For Shcompact, if not optimizing, we end up with a memory reference
7013 using the return address pointer for __builtin_return_address even
7014 though there is no actual need to put the PR register on the stack. */
7015 pr_live |= df_regs_ever_live_p (RETURN_ADDRESS_POINTER_REGNUM);
7017 /* Force PR to be live if the prologue has to call the SHmedia
7018 argument decoder or register saver. */
7019 bool has_call = pr_live;
7021 int count;
7022 for (count = 0, reg = FIRST_PSEUDO_REGISTER; reg-- != 0; )
7024 if (reg == PR_REG
7025 ? pr_live
7026 : interrupt_handler
7027 ? (/* Need to save all the regs ever live. */
7028 (df_regs_ever_live_p (reg)
7029 || (call_really_used_regs[reg]
7030 && (! fixed_regs[reg] || reg == MACH_REG || reg == MACL_REG
7031 || reg == PIC_OFFSET_TABLE_REGNUM)
7032 && has_call))
7033 && reg != STACK_POINTER_REGNUM && reg != ARG_POINTER_REGNUM
7034 && reg != RETURN_ADDRESS_POINTER_REGNUM
7035 && reg != T_REG && reg != GBR_REG
7036 && reg != FPSCR_MODES_REG && reg != FPSCR_STAT_REG
7037 /* Push fpscr only on targets which have FPU */
7038 && (reg != FPSCR_REG || TARGET_FPU_ANY))
7039 : (/* Only push those regs which are used and need to be saved. */
7040 (false)
7041 || (df_regs_ever_live_p (reg)
7042 && ((!call_really_used_regs[reg]
7043 && !(reg != PIC_OFFSET_TABLE_REGNUM
7044 && fixed_regs[reg] && call_used_regs[reg]))
7045 || (trapa_handler && reg == FPSCR_REG && TARGET_FPU_ANY)))
7046 || (crtl->calls_eh_return
7047 && (reg == EH_RETURN_DATA_REGNO (0)
7048 || reg == EH_RETURN_DATA_REGNO (1)
7049 || reg == EH_RETURN_DATA_REGNO (2)
7050 || reg == EH_RETURN_DATA_REGNO (3)))
7051 || ((reg == MACL_REG || reg == MACH_REG)
7052 && df_regs_ever_live_p (reg)
7053 && sh_cfun_attr_renesas_p ())
7056 SET_HARD_REG_BIT (*live_regs_mask, reg);
7057 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
7059 if (TARGET_FPU_DOUBLE && TARGET_FMOVD
7060 && GET_MODE_CLASS (REGISTER_NATURAL_MODE (reg)) == MODE_FLOAT)
7062 if (FP_REGISTER_P (reg))
7064 if (! TARGET_FPU_SINGLE && ! df_regs_ever_live_p (reg ^ 1))
7066 SET_HARD_REG_BIT (*live_regs_mask, (reg ^ 1));
7067 count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg ^ 1));
7070 else if (XD_REGISTER_P (reg))
7072 /* Must switch to double mode to access these registers. */
7073 target_flags &= ~MASK_FPU_SINGLE;
7077 if (nosave_low_regs && reg == R8_REG)
7078 break;
7081 return count;
7084 /* Code to generate prologue and epilogue sequences */
7086 /* PUSHED is the number of bytes that are being pushed on the
7087 stack for register saves. Return the frame size, padded
7088 appropriately so that the stack stays properly aligned. */
7089 static HOST_WIDE_INT
7090 rounded_frame_size (int pushed)
7092 HOST_WIDE_INT size = get_frame_size ();
7093 HOST_WIDE_INT align = STACK_BOUNDARY / BITS_PER_UNIT;
7095 if (ACCUMULATE_OUTGOING_ARGS)
7096 size += crtl->outgoing_args_size;
7098 return ((size + pushed + align - 1) & -align) - pushed;
7101 /* Expand code for the function prologue. */
7102 void
7103 sh_expand_prologue (void)
7105 int save_flags = target_flags;
7106 tree sp_switch_attr
7107 = lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl));
7109 current_function_interrupt = sh_cfun_interrupt_handler_p ();
7111 /* We have pretend args if we had an object sent partially in registers
7112 and partially on the stack, e.g. a large structure. */
7113 int pretend_args = crtl->args.pretend_args_size;
7114 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl)
7115 && (NPARM_REGS(SImode)
7116 > crtl->args.info.arg_count[(int) SH_ARG_INT]))
7117 pretend_args = 0;
7119 output_stack_adjust (-pretend_args, stack_pointer_rtx, 0, NULL, true);
7120 int stack_usage = pretend_args;
7122 /* Emit the code for SETUP_VARARGS. */
7123 if (cfun->stdarg)
7125 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
7127 /* Push arg regs as if they'd been provided by caller in stack. */
7128 for (int i = 0; i < NPARM_REGS(SImode); i++)
7130 int rn = NPARM_REGS(SImode) + FIRST_PARM_REG - i - 1;
7132 if (i >= (NPARM_REGS(SImode)
7133 - crtl->args.info.arg_count[(int) SH_ARG_INT]
7135 break;
7136 push (rn);
7137 stack_usage += GET_MODE_SIZE (SImode);
7142 /* If we're supposed to switch stacks at function entry, do so now. */
7143 if (sp_switch_attr)
7145 rtx lab, newsrc;
7146 /* The argument specifies a variable holding the address of the
7147 stack the interrupt function should switch to/from at entry/exit. */
7148 tree arg = TREE_VALUE ( TREE_VALUE (sp_switch_attr));
7149 const char* s = ggc_strdup (TREE_STRING_POINTER (arg));
7150 rtx sp_switch = gen_rtx_SYMBOL_REF (Pmode, s);
7152 lab = add_constant (sp_switch, SImode, 0);
7153 newsrc = gen_rtx_LABEL_REF (VOIDmode, lab);
7155 emit_insn (gen_sp_switch_1 (newsrc));
7158 HARD_REG_SET live_regs_mask;
7159 int d = calc_live_regs (&live_regs_mask);
7160 /* ??? Maybe we could save some switching if we can move a mode switch
7161 that already happens to be at the function start into the prologue. */
7162 if (target_flags != save_flags && ! current_function_interrupt)
7163 emit_insn (gen_toggle_sz ());
7165 push_regs (&live_regs_mask, current_function_interrupt);
7166 stack_usage += d;
7168 if (flag_pic && !TARGET_FDPIC
7169 && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
7170 emit_insn (gen_GOTaddr2picreg (const0_rtx));
7172 if (target_flags != save_flags && ! current_function_interrupt)
7173 emit_insn (gen_toggle_sz ());
7175 target_flags = save_flags;
7177 output_stack_adjust (-rounded_frame_size (d),
7178 stack_pointer_rtx, 0, NULL, true);
7179 stack_usage += rounded_frame_size (d);
7181 if (frame_pointer_needed)
7182 emit_frame_insn (GEN_MOV (hard_frame_pointer_rtx, stack_pointer_rtx));
7184 /* If we are profiling, make sure no instructions are scheduled before
7185 the call to mcount. Similarly if some call instructions are swapped
7186 before frame related insns, it'll confuse the unwinder because
7187 currently SH has no unwind info for function epilogues. */
7188 if (crtl->profile || flag_exceptions || flag_unwind_tables)
7189 emit_insn (gen_blockage ());
7191 if (flag_stack_usage_info)
7192 current_function_static_stack_size = stack_usage;
7195 /* Expand code for the function epilogue. */
7196 void
7197 sh_expand_epilogue (bool sibcall_p)
7199 int save_flags = target_flags;
7200 bool fpscr_deferred = false;
7201 int e = sibcall_p ? -1 : 1;
7203 HARD_REG_SET live_regs_mask;
7204 int d = calc_live_regs (&live_regs_mask);
7206 int save_size = d;
7207 int frame_size = rounded_frame_size (d);
7209 if (frame_pointer_needed)
7211 /* We must avoid scheduling the epilogue with previous basic blocks.
7212 See PR/18032 and PR/40313. */
7213 emit_insn (gen_blockage ());
7214 output_stack_adjust (frame_size, hard_frame_pointer_rtx, e,
7215 &live_regs_mask, true);
7217 /* We must avoid moving the stack pointer adjustment past code
7218 which reads from the local frame, else an interrupt could
7219 occur after the SP adjustment and clobber data in the local
7220 frame. */
7221 emit_insn (gen_blockage ());
7222 emit_frame_insn (GEN_MOV (stack_pointer_rtx, hard_frame_pointer_rtx));
7224 else if (frame_size)
7226 /* We must avoid moving the stack pointer adjustment past code
7227 which reads from the local frame, else an interrupt could
7228 occur after the SP adjustment and clobber data in the local
7229 frame. */
7230 emit_insn (gen_blockage ());
7231 output_stack_adjust (frame_size, stack_pointer_rtx, e,
7232 &live_regs_mask, true);
7235 /* Pop all the registers. */
7237 if (target_flags != save_flags && ! current_function_interrupt)
7238 emit_insn (gen_toggle_sz ());
7241 int last_reg;
7243 save_size = 0;
7244 /* For an ISR with RESBANK attribute assigned, don't pop PR
7245 register. */
7246 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG)
7247 && !sh_cfun_resbank_handler_p ())
7249 if (!frame_pointer_needed)
7250 emit_insn (gen_blockage ());
7251 pop (PR_REG);
7254 /* Banked registers are popped first to avoid being scheduled in the
7255 delay slot. RTE switches banks before the ds instruction. */
7256 if (current_function_interrupt)
7258 bool use_movml = false;
7260 if (TARGET_SH2A)
7262 unsigned int count = 0;
7264 for (int i = FIRST_BANKED_REG; i <= LAST_BANKED_REG; i++)
7265 if (TEST_HARD_REG_BIT (live_regs_mask, i))
7266 count++;
7267 else
7268 break;
7270 /* Use movml when all banked register are poped. */
7271 if (count == LAST_BANKED_REG - FIRST_BANKED_REG + 1)
7272 use_movml = true;
7275 if (sh_cfun_resbank_handler_p ())
7276 ; /* Do nothing. */
7277 else if (use_movml)
7279 rtx sp_reg = gen_rtx_REG (SImode, STACK_POINTER_REGNUM);
7281 /* We must avoid scheduling multiple load insn with another
7282 insns. */
7283 emit_insn (gen_blockage ());
7284 emit_insn (gen_movml_pop_banked (sp_reg));
7285 emit_insn (gen_blockage ());
7287 else
7288 for (int i = LAST_BANKED_REG; i >= FIRST_BANKED_REG; i--)
7289 if (TEST_HARD_REG_BIT (live_regs_mask, i))
7290 pop (i);
7292 last_reg = FIRST_PSEUDO_REGISTER - LAST_BANKED_REG - 1;
7294 else
7295 last_reg = FIRST_PSEUDO_REGISTER;
7297 for (int i = 0; i < last_reg; i++)
7299 int j = (FIRST_PSEUDO_REGISTER - 1) - i;
7301 if (j == FPSCR_REG && current_function_interrupt && TARGET_FMOVD
7302 && hard_reg_set_intersect_p (live_regs_mask,
7303 reg_class_contents[DF_REGS]))
7304 fpscr_deferred = true;
7305 /* For an ISR with RESBANK attribute assigned, don't pop
7306 following registers, R0-R14, MACH, MACL and GBR. */
7307 else if (j != PR_REG && TEST_HARD_REG_BIT (live_regs_mask, j)
7308 && ! (sh_cfun_resbank_handler_p ()
7309 && ((j >= FIRST_GENERAL_REG
7310 && j < LAST_GENERAL_REG)
7311 || j == MACH_REG
7312 || j == MACL_REG
7313 || j == GBR_REG)))
7314 pop (j);
7316 if (j == FIRST_FP_REG && fpscr_deferred)
7317 pop (FPSCR_REG);
7320 if (target_flags != save_flags && ! current_function_interrupt)
7321 emit_insn (gen_toggle_sz ());
7322 target_flags = save_flags;
7324 output_stack_adjust (crtl->args.pretend_args_size + save_size,
7325 stack_pointer_rtx, e, NULL, true);
7327 if (crtl->calls_eh_return)
7328 emit_insn (GEN_ADD3 (stack_pointer_rtx, stack_pointer_rtx,
7329 EH_RETURN_STACKADJ_RTX));
7331 /* Switch back to the normal stack if necessary. */
7332 if (lookup_attribute ("sp_switch", DECL_ATTRIBUTES (current_function_decl)))
7333 emit_insn (gen_sp_switch_2 ());
7335 /* Tell flow the insn that pops PR isn't dead. */
7336 if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
7337 emit_use (gen_rtx_REG (SImode, PR_REG));
7340 /* Emit code to change the current function's return address to RA.
7341 TEMP is available as a scratch register, if needed. */
7342 void
7343 sh_set_return_address (rtx ra, rtx tmp)
7345 HARD_REG_SET live_regs_mask;
7346 int d = calc_live_regs (&live_regs_mask);
7348 /* If pr_reg isn't life, we can set it directly. */
7349 if (! TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
7351 rtx rr = gen_rtx_REG (SImode, PR_REG);
7352 emit_insn (GEN_MOV (rr, ra));
7353 /* Tell flow the register for return isn't dead. */
7354 emit_use (rr);
7355 return;
7358 int pr_offset = rounded_frame_size (d);
7360 emit_insn (GEN_MOV (tmp, GEN_INT (pr_offset)));
7362 if (frame_pointer_needed)
7363 emit_insn (GEN_ADD3 (tmp, tmp, hard_frame_pointer_rtx));
7364 else
7365 emit_insn (GEN_ADD3 (tmp, tmp, stack_pointer_rtx));
7367 tmp = gen_frame_mem (Pmode, tmp);
7368 emit_insn (GEN_MOV (tmp, ra));
7369 /* Tell this store isn't dead. */
7370 emit_use (tmp);
7373 /* Clear variables at function end. */
7374 static void
7375 sh_output_function_epilogue (FILE *)
7379 static rtx
7380 sh_builtin_saveregs (void)
7382 /* First unnamed integer register. */
7383 int first_intreg = crtl->args.info.arg_count[(int) SH_ARG_INT];
7384 /* Number of integer registers we need to save. */
7385 int n_intregs = MAX (0, NPARM_REGS (SImode) - first_intreg);
7386 /* First unnamed SFmode float reg */
7387 int first_floatreg = crtl->args.info.arg_count[(int) SH_ARG_FLOAT];
7388 /* Number of SFmode float regs to save. */
7389 int n_floatregs = MAX (0, NPARM_REGS (SFmode) - first_floatreg);
7390 rtx regbuf, fpregs;
7391 int bufsize, regno;
7392 alias_set_type alias_set;
7394 if (!TARGET_FPU_ANY)
7396 error ("__builtin_saveregs not supported by this subtarget");
7397 return const0_rtx;
7400 /* Allocate block of memory for the regs. */
7401 /* ??? If n_intregs + n_floatregs == 0, should we allocate at least 1 byte?
7402 Or can assign_stack_local accept a 0 SIZE argument? */
7403 bufsize = (n_intregs * UNITS_PER_WORD) + (n_floatregs * UNITS_PER_WORD);
7405 if (n_floatregs & 1)
7407 rtx addr;
7409 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7410 addr = copy_to_mode_reg (Pmode, XEXP (regbuf, 0));
7411 emit_insn (gen_iorsi3 (addr, addr, GEN_INT (UNITS_PER_WORD)));
7412 regbuf = change_address (regbuf, BLKmode, addr);
7414 else if (STACK_BOUNDARY < 64 && TARGET_FPU_DOUBLE && n_floatregs)
7416 rtx addr, mask;
7418 regbuf = assign_stack_local (BLKmode, bufsize + UNITS_PER_WORD, 0);
7419 addr = copy_to_mode_reg (Pmode, plus_constant (Pmode,
7420 XEXP (regbuf, 0), 4));
7421 mask = copy_to_mode_reg (Pmode, GEN_INT (-8));
7422 emit_insn (gen_andsi3 (addr, addr, mask));
7423 regbuf = change_address (regbuf, BLKmode, addr);
7425 else
7426 regbuf = assign_stack_local (BLKmode, bufsize, TARGET_FPU_DOUBLE ? 64 : 0);
7427 alias_set = get_varargs_alias_set ();
7428 set_mem_alias_set (regbuf, alias_set);
7430 /* Save int args.
7431 This is optimized to only save the regs that are necessary. Explicitly
7432 named args need not be saved. */
7433 if (n_intregs > 0)
7434 move_block_from_reg (BASE_ARG_REG (SImode) + first_intreg,
7435 adjust_address (regbuf, BLKmode,
7436 n_floatregs * UNITS_PER_WORD),
7437 n_intregs);
7439 /* Save float args.
7440 This is optimized to only save the regs that are necessary. Explicitly
7441 named args need not be saved.
7442 We explicitly build a pointer to the buffer because it halves the insn
7443 count when not optimizing (otherwise the pointer is built for each reg
7444 saved).
7445 We emit the moves in reverse order so that we can use predecrement. */
7447 fpregs = copy_to_mode_reg (Pmode,
7448 plus_constant (Pmode, XEXP (regbuf, 0),
7449 n_floatregs * UNITS_PER_WORD));
7450 if (TARGET_FPU_DOUBLE)
7452 rtx mem;
7453 for (regno = NPARM_REGS (DFmode) - 2; regno >= first_floatreg; regno -= 2)
7455 emit_insn (gen_addsi3 (fpregs, fpregs,
7456 GEN_INT (-2 * UNITS_PER_WORD)));
7457 mem = change_address (regbuf, DFmode, fpregs);
7458 emit_move_insn (mem,
7459 gen_rtx_REG (DFmode, BASE_ARG_REG (DFmode) + regno));
7461 regno = first_floatreg;
7462 if (regno & 1)
7464 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7465 mem = change_address (regbuf, SFmode, fpregs);
7466 emit_move_insn (mem,
7467 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode)
7468 + regno - SH_REG_MSW_OFFSET));
7471 else
7472 for (regno = NPARM_REGS (SFmode) - 1; regno >= first_floatreg; regno--)
7474 rtx mem;
7476 emit_insn (gen_addsi3 (fpregs, fpregs, GEN_INT (-UNITS_PER_WORD)));
7477 mem = change_address (regbuf, SFmode, fpregs);
7478 emit_move_insn (mem,
7479 gen_rtx_REG (SFmode, BASE_ARG_REG (SFmode) + regno));
7482 /* Return the address of the regbuf. */
7483 return XEXP (regbuf, 0);
7486 /* Define the `__builtin_va_list' type for the ABI. */
7487 static tree
7488 sh_build_builtin_va_list (void)
7490 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7491 tree record, type_decl;
7493 if ((! TARGET_SH2E && ! TARGET_SH4)
7494 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7495 return ptr_type_node;
7497 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
7498 type_decl = build_decl (BUILTINS_LOCATION,
7499 TYPE_DECL, get_identifier ("__va_list_tag"), record);
7501 f_next_o = build_decl (BUILTINS_LOCATION,
7502 FIELD_DECL, get_identifier ("__va_next_o"),
7503 ptr_type_node);
7504 f_next_o_limit = build_decl (BUILTINS_LOCATION,
7505 FIELD_DECL,
7506 get_identifier ("__va_next_o_limit"),
7507 ptr_type_node);
7508 f_next_fp = build_decl (BUILTINS_LOCATION,
7509 FIELD_DECL, get_identifier ("__va_next_fp"),
7510 ptr_type_node);
7511 f_next_fp_limit = build_decl (BUILTINS_LOCATION,
7512 FIELD_DECL,
7513 get_identifier ("__va_next_fp_limit"),
7514 ptr_type_node);
7515 f_next_stack = build_decl (BUILTINS_LOCATION,
7516 FIELD_DECL, get_identifier ("__va_next_stack"),
7517 ptr_type_node);
7519 DECL_FIELD_CONTEXT (f_next_o) = record;
7520 DECL_FIELD_CONTEXT (f_next_o_limit) = record;
7521 DECL_FIELD_CONTEXT (f_next_fp) = record;
7522 DECL_FIELD_CONTEXT (f_next_fp_limit) = record;
7523 DECL_FIELD_CONTEXT (f_next_stack) = record;
7525 TYPE_STUB_DECL (record) = type_decl;
7526 TYPE_NAME (record) = type_decl;
7527 TYPE_FIELDS (record) = f_next_o;
7528 DECL_CHAIN (f_next_o) = f_next_o_limit;
7529 DECL_CHAIN (f_next_o_limit) = f_next_fp;
7530 DECL_CHAIN (f_next_fp) = f_next_fp_limit;
7531 DECL_CHAIN (f_next_fp_limit) = f_next_stack;
7533 layout_type (record);
7535 return record;
7538 /* Implement `va_start' for varargs and stdarg. */
7539 static void
7540 sh_va_start (tree valist, rtx nextarg)
7542 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7543 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7544 tree t, u;
7545 int nfp, nint;
7547 if ((! TARGET_SH2E && ! TARGET_SH4)
7548 || TARGET_HITACHI || sh_cfun_attr_renesas_p ())
7550 std_expand_builtin_va_start (valist, nextarg);
7551 return;
7554 f_next_o = TYPE_FIELDS (va_list_type_node);
7555 f_next_o_limit = DECL_CHAIN (f_next_o);
7556 f_next_fp = DECL_CHAIN (f_next_o_limit);
7557 f_next_fp_limit = DECL_CHAIN (f_next_fp);
7558 f_next_stack = DECL_CHAIN (f_next_fp_limit);
7560 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7561 NULL_TREE);
7562 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7563 valist, f_next_o_limit, NULL_TREE);
7564 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp), valist, f_next_fp,
7565 NULL_TREE);
7566 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7567 valist, f_next_fp_limit, NULL_TREE);
7568 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7569 valist, f_next_stack, NULL_TREE);
7571 /* Call __builtin_saveregs. */
7572 u = make_tree (sizetype, expand_builtin_saveregs ());
7573 u = fold_convert (ptr_type_node, u);
7574 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp, u);
7575 TREE_SIDE_EFFECTS (t) = 1;
7576 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7578 nfp = crtl->args.info.arg_count[SH_ARG_FLOAT];
7579 if (nfp < 8)
7580 nfp = 8 - nfp;
7581 else
7582 nfp = 0;
7583 u = fold_build_pointer_plus_hwi (u, UNITS_PER_WORD * nfp);
7584 t = build2 (MODIFY_EXPR, ptr_type_node, next_fp_limit, u);
7585 TREE_SIDE_EFFECTS (t) = 1;
7586 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7588 t = build2 (MODIFY_EXPR, ptr_type_node, next_o, u);
7589 TREE_SIDE_EFFECTS (t) = 1;
7590 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7592 nint = crtl->args.info.arg_count[SH_ARG_INT];
7593 if (nint < 4)
7594 nint = 4 - nint;
7595 else
7596 nint = 0;
7597 u = fold_build_pointer_plus_hwi (u, UNITS_PER_WORD * nint);
7598 t = build2 (MODIFY_EXPR, ptr_type_node, next_o_limit, u);
7599 TREE_SIDE_EFFECTS (t) = 1;
7600 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7602 u = make_tree (ptr_type_node, nextarg);
7603 t = build2 (MODIFY_EXPR, ptr_type_node, next_stack, u);
7604 TREE_SIDE_EFFECTS (t) = 1;
7605 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
7608 /* TYPE is a RECORD_TYPE. If there is only a single nonzero-sized
7609 member, return it. */
7610 static tree
7611 find_sole_member (tree type)
7613 tree field, member = NULL_TREE;
7615 for (field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field))
7617 if (TREE_CODE (field) != FIELD_DECL)
7618 continue;
7619 if (!DECL_SIZE (field))
7620 return NULL_TREE;
7621 if (integer_zerop (DECL_SIZE (field)))
7622 continue;
7623 if (member)
7624 return NULL_TREE;
7625 member = field;
7627 return member;
7630 /* Implement `va_arg'. */
7631 static tree
7632 sh_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
7633 gimple_seq *post_p ATTRIBUTE_UNUSED)
7635 tree tmp;
7636 tree addr, lab_over = NULL, result = NULL;
7637 tree eff_type;
7639 const bool pass_by_ref =
7640 !VOID_TYPE_P (type)
7641 && targetm.calls.must_pass_in_stack (TYPE_MODE (type), type);
7643 if (pass_by_ref)
7644 type = build_pointer_type (type);
7646 HOST_WIDE_INT size = int_size_in_bytes (type);
7647 HOST_WIDE_INT rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
7648 tree pptr_type_node = build_pointer_type (ptr_type_node);
7650 if ((TARGET_SH2E || TARGET_SH4)
7651 && ! (TARGET_HITACHI || sh_cfun_attr_renesas_p ()))
7653 tree f_next_o, f_next_o_limit, f_next_fp, f_next_fp_limit, f_next_stack;
7654 tree next_o, next_o_limit, next_fp, next_fp_limit, next_stack;
7655 tree lab_false;
7656 tree member;
7658 f_next_o = TYPE_FIELDS (va_list_type_node);
7659 f_next_o_limit = DECL_CHAIN (f_next_o);
7660 f_next_fp = DECL_CHAIN (f_next_o_limit);
7661 f_next_fp_limit = DECL_CHAIN (f_next_fp);
7662 f_next_stack = DECL_CHAIN (f_next_fp_limit);
7664 next_o = build3 (COMPONENT_REF, TREE_TYPE (f_next_o), valist, f_next_o,
7665 NULL_TREE);
7666 next_o_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_o_limit),
7667 valist, f_next_o_limit, NULL_TREE);
7668 next_fp = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp),
7669 valist, f_next_fp, NULL_TREE);
7670 next_fp_limit = build3 (COMPONENT_REF, TREE_TYPE (f_next_fp_limit),
7671 valist, f_next_fp_limit, NULL_TREE);
7672 next_stack = build3 (COMPONENT_REF, TREE_TYPE (f_next_stack),
7673 valist, f_next_stack, NULL_TREE);
7675 /* Structures with a single member with a distinct mode are passed
7676 like their member. This is relevant if the latter has a REAL_TYPE
7677 or COMPLEX_TYPE type. */
7678 eff_type = type;
7679 while (TREE_CODE (eff_type) == RECORD_TYPE
7680 && (member = find_sole_member (eff_type))
7681 && (TREE_CODE (TREE_TYPE (member)) == REAL_TYPE
7682 || TREE_CODE (TREE_TYPE (member)) == COMPLEX_TYPE
7683 || TREE_CODE (TREE_TYPE (member)) == RECORD_TYPE))
7685 tree field_type = TREE_TYPE (member);
7687 if (TYPE_MODE (eff_type) == TYPE_MODE (field_type))
7688 eff_type = field_type;
7689 else
7691 gcc_assert ((TYPE_ALIGN (eff_type)
7692 < GET_MODE_ALIGNMENT (TYPE_MODE (field_type)))
7693 || (TYPE_ALIGN (eff_type)
7694 > GET_MODE_BITSIZE (TYPE_MODE (field_type))));
7695 break;
7699 bool pass_as_float;
7700 if (TARGET_FPU_DOUBLE)
7702 pass_as_float = ((TREE_CODE (eff_type) == REAL_TYPE && size <= 8)
7703 || (TREE_CODE (eff_type) == COMPLEX_TYPE
7704 && TREE_CODE (TREE_TYPE (eff_type)) == REAL_TYPE
7705 && size <= 16));
7707 else
7709 pass_as_float = (TREE_CODE (eff_type) == REAL_TYPE && size == 4);
7712 addr = create_tmp_var (pptr_type_node);
7713 lab_false = create_artificial_label (UNKNOWN_LOCATION);
7714 lab_over = create_artificial_label (UNKNOWN_LOCATION);
7716 valist = build_simple_mem_ref (addr);
7718 if (pass_as_float)
7720 tree next_fp_tmp = create_tmp_var (TREE_TYPE (f_next_fp));
7721 tree cmp;
7722 bool is_double = size == 8 && TREE_CODE (eff_type) == REAL_TYPE;
7724 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_fp));
7725 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7727 gimplify_assign (unshare_expr (next_fp_tmp), valist, pre_p);
7728 tmp = next_fp_limit;
7729 if (size > 4 && !is_double)
7730 tmp = fold_build_pointer_plus_hwi (unshare_expr (tmp), 4 - size);
7731 tmp = build2 (GE_EXPR, boolean_type_node,
7732 unshare_expr (next_fp_tmp), unshare_expr (tmp));
7733 cmp = build3 (COND_EXPR, void_type_node, tmp,
7734 build1 (GOTO_EXPR, void_type_node,
7735 unshare_expr (lab_false)), NULL_TREE);
7736 if (!is_double)
7737 gimplify_and_add (cmp, pre_p);
7739 if (TYPE_ALIGN (eff_type) > BITS_PER_WORD
7740 || (is_double || size == 16))
7742 tmp = fold_convert (sizetype, next_fp_tmp);
7743 tmp = build2 (BIT_AND_EXPR, sizetype, tmp,
7744 size_int (UNITS_PER_WORD));
7745 tmp = fold_build_pointer_plus (unshare_expr (next_fp_tmp), tmp);
7746 gimplify_assign (unshare_expr (next_fp_tmp), tmp, pre_p);
7748 if (is_double)
7749 gimplify_and_add (cmp, pre_p);
7751 #ifdef FUNCTION_ARG_SCmode_WART
7752 if (TYPE_MODE (eff_type) == SCmode
7753 && TARGET_SH4 && TARGET_LITTLE_ENDIAN)
7755 tree subtype = TREE_TYPE (eff_type);
7756 tree real, imag;
7758 imag
7759 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7760 imag = get_initialized_tmp_var (imag, pre_p, NULL);
7762 real
7763 = std_gimplify_va_arg_expr (next_fp_tmp, subtype, pre_p, NULL);
7764 real = get_initialized_tmp_var (real, pre_p, NULL);
7766 result = build2 (COMPLEX_EXPR, eff_type, real, imag);
7767 if (type != eff_type)
7768 result = build1 (VIEW_CONVERT_EXPR, type, result);
7769 result = get_initialized_tmp_var (result, pre_p, NULL);
7771 #endif /* FUNCTION_ARG_SCmode_WART */
7773 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7774 gimplify_and_add (tmp, pre_p);
7776 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7777 gimplify_and_add (tmp, pre_p);
7779 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7780 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7781 gimplify_assign (unshare_expr (next_fp_tmp),
7782 unshare_expr (valist), pre_p);
7784 gimplify_assign (unshare_expr (valist),
7785 unshare_expr (next_fp_tmp), post_p);
7786 valist = next_fp_tmp;
7788 else
7790 tmp = fold_build_pointer_plus_hwi (unshare_expr (next_o), rsize);
7791 tmp = build2 (GT_EXPR, boolean_type_node, tmp,
7792 unshare_expr (next_o_limit));
7793 tmp = build3 (COND_EXPR, void_type_node, tmp,
7794 build1 (GOTO_EXPR, void_type_node,
7795 unshare_expr (lab_false)),
7796 NULL_TREE);
7797 gimplify_and_add (tmp, pre_p);
7799 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_o));
7800 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7802 tmp = build1 (GOTO_EXPR, void_type_node, unshare_expr (lab_over));
7803 gimplify_and_add (tmp, pre_p);
7805 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_false));
7806 gimplify_and_add (tmp, pre_p);
7808 if (size > 4 && ! (TARGET_SH4 || TARGET_SH2A))
7809 gimplify_assign (unshare_expr (next_o),
7810 unshare_expr (next_o_limit), pre_p);
7812 tmp = build1 (ADDR_EXPR, pptr_type_node, unshare_expr (next_stack));
7813 gimplify_assign (unshare_expr (addr), tmp, pre_p);
7816 if (!result)
7818 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7819 gimplify_and_add (tmp, pre_p);
7823 /* ??? In va-sh.h, there had been code to make values larger than
7824 size 8 indirect. This does not match the FUNCTION_ARG macros. */
7826 tmp = std_gimplify_va_arg_expr (valist, type, pre_p, NULL);
7827 if (result)
7829 gimplify_assign (result, tmp, pre_p);
7830 result = build1 (NOP_EXPR, TREE_TYPE (result), result);
7831 tmp = build1 (LABEL_EXPR, void_type_node, unshare_expr (lab_over));
7832 gimplify_and_add (tmp, pre_p);
7834 else
7835 result = tmp;
7837 if (pass_by_ref)
7838 result = build_va_arg_indirect_ref (result);
7840 return result;
7843 /* 64 bit floating points memory transfers are paired single precision loads
7844 or store. So DWARF information needs fixing in little endian (unless
7845 PR=SZ=1 in FPSCR). */
7847 sh_dwarf_register_span (rtx reg)
7849 unsigned regno = REGNO (reg);
7851 if (WORDS_BIG_ENDIAN || GET_MODE (reg) != DFmode)
7852 return NULL_RTX;
7854 return
7855 gen_rtx_PARALLEL (VOIDmode,
7856 gen_rtvec (2,
7857 gen_rtx_REG (SFmode, regno + 1),
7858 gen_rtx_REG (SFmode, regno)));
7861 static machine_mode
7862 sh_promote_function_mode (const_tree type, machine_mode mode,
7863 int *punsignedp, const_tree funtype,
7864 int for_return)
7866 if (sh_promote_prototypes (funtype))
7867 return promote_mode (type, mode, punsignedp);
7868 else
7869 return default_promote_function_mode (type, mode, punsignedp, funtype,
7870 for_return);
7873 static bool
7874 sh_promote_prototypes (const_tree type)
7876 if (TARGET_HITACHI)
7877 return false;
7878 if (! type)
7879 return true;
7880 return ! sh_attr_renesas_p (type);
7883 static bool
7884 sh_pass_by_reference (cumulative_args_t cum_v, machine_mode mode,
7885 const_tree type, bool named ATTRIBUTE_UNUSED)
7887 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
7889 if (targetm.calls.must_pass_in_stack (mode, type))
7890 return true;
7892 /* ??? std_gimplify_va_arg_expr passes NULL for cum. That function
7893 wants to know about pass-by-reference semantics for incoming
7894 arguments. */
7895 if (! cum)
7896 return false;
7898 return false;
7901 static bool
7902 sh_callee_copies (cumulative_args_t cum, machine_mode mode,
7903 const_tree type, bool named ATTRIBUTE_UNUSED)
7905 /* ??? How can it possibly be correct to return true only on the
7906 caller side of the equation? Is there someplace else in the
7907 sh backend that's magically producing the copies? */
7908 return (get_cumulative_args (cum)->outgoing
7909 && ((mode == BLKmode ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
7910 % SH_MIN_ALIGN_FOR_CALLEE_COPY == 0));
7913 static sh_arg_class
7914 get_sh_arg_class (machine_mode mode)
7916 if (TARGET_FPU_ANY && mode == SFmode)
7917 return SH_ARG_FLOAT;
7919 if (TARGET_FPU_DOUBLE
7920 && (GET_MODE_CLASS (mode) == MODE_FLOAT
7921 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT))
7922 return SH_ARG_FLOAT;
7924 return SH_ARG_INT;
7927 /* Round a register number up to a proper boundary for an arg of mode
7928 MODE.
7929 The SH doesn't care about double alignment, so we only
7930 round doubles to even regs when asked to explicitly. */
7931 static int
7932 sh_round_reg (const CUMULATIVE_ARGS& cum, machine_mode mode)
7934 /* FIXME: This used to be a macro and has been copy pasted into this
7935 function as is. Make this more readable. */
7936 return
7937 (((TARGET_ALIGN_DOUBLE
7938 || (TARGET_FPU_DOUBLE
7939 && (mode == DFmode || mode == DCmode)
7940 && cum.arg_count[(int) SH_ARG_FLOAT] < NPARM_REGS (mode)))
7941 && GET_MODE_UNIT_SIZE (mode) > UNITS_PER_WORD)
7942 ? (cum.arg_count[(int) get_sh_arg_class (mode)]
7943 + (cum.arg_count[(int) get_sh_arg_class (mode)] & 1))
7944 : cum.arg_count[(int) get_sh_arg_class (mode)]);
7947 /* Return true if arg of the specified mode should be passed in a register
7948 or false otherwise. */
7949 static bool
7950 sh_pass_in_reg_p (const CUMULATIVE_ARGS& cum, machine_mode mode,
7951 const_tree type)
7953 /* FIXME: This used to be a macro and has been copy pasted into this
7954 function as is. Make this more readable. */
7955 return
7956 ((type == 0
7957 || (! TREE_ADDRESSABLE (type)
7958 && (! (TARGET_HITACHI || cum.renesas_abi)
7959 || ! (AGGREGATE_TYPE_P (type)
7960 || (!TARGET_FPU_ANY
7961 && (GET_MODE_CLASS (mode) == MODE_FLOAT
7962 && GET_MODE_SIZE (mode) > GET_MODE_SIZE (SFmode)))))))
7963 && ! cum.force_mem
7964 && (TARGET_SH2E
7965 ? ((mode) == BLKmode
7966 ? ((cum.arg_count[(int) SH_ARG_INT] * UNITS_PER_WORD
7967 + int_size_in_bytes (type))
7968 <= NPARM_REGS (SImode) * UNITS_PER_WORD)
7969 : ((sh_round_reg (cum, mode)
7970 + sh_hard_regno_nregs (BASE_ARG_REG (mode), mode))
7971 <= NPARM_REGS (mode)))
7972 : sh_round_reg (cum, mode) < NPARM_REGS (mode)));
7975 static int
7976 sh_arg_partial_bytes (cumulative_args_t cum_v, machine_mode mode,
7977 tree type, bool named ATTRIBUTE_UNUSED)
7979 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
7980 int words = 0;
7982 if (sh_pass_in_reg_p (*cum, mode, type)
7983 && !TARGET_FPU_DOUBLE
7984 && (sh_round_reg (*cum, mode)
7985 + (mode != BLKmode
7986 ? CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD)
7987 : CEIL (int_size_in_bytes (type), UNITS_PER_WORD))
7988 > NPARM_REGS (mode)))
7989 words = NPARM_REGS (mode) - sh_round_reg (*cum, mode);
7991 return words * UNITS_PER_WORD;
7995 /* Define where to put the arguments to a function.
7996 Value is zero to push the argument on the stack,
7997 or a hard register in which to store the argument.
7999 MODE is the argument's machine mode.
8000 TYPE is the data type of the argument (as a tree).
8001 This is null for libcalls where that information may
8002 not be available.
8003 CUM is a variable of type CUMULATIVE_ARGS which gives info about
8004 the preceding args and about the function being called.
8005 NAMED is nonzero if this argument is a named parameter
8006 (otherwise it is an extra parameter matching an ellipsis).
8008 On SH the first args are normally in registers
8009 and the rest are pushed. Any arg that starts within the first
8010 NPARM_REGS words is at least partially passed in a register unless
8011 its data type forbids. */
8012 static rtx
8013 sh_function_arg (cumulative_args_t ca_v, machine_mode mode,
8014 const_tree type, bool named)
8016 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
8018 if (mode == VOIDmode)
8019 return ca->renesas_abi ? const1_rtx : const0_rtx;
8021 if (sh_pass_in_reg_p (*ca, mode, type)
8022 && (named || ! (TARGET_HITACHI || ca->renesas_abi)))
8024 int regno;
8026 if (mode == SCmode && TARGET_SH4 && TARGET_LITTLE_ENDIAN
8027 && (! FUNCTION_ARG_SCmode_WART || (sh_round_reg (*ca, mode) & 1)))
8029 rtx r1 = gen_rtx_EXPR_LIST (VOIDmode,
8030 gen_rtx_REG (SFmode,
8031 BASE_ARG_REG (mode)
8032 + (sh_round_reg (*ca, mode) ^ 1)),
8033 const0_rtx);
8034 rtx r2 = gen_rtx_EXPR_LIST (VOIDmode,
8035 gen_rtx_REG (SFmode,
8036 BASE_ARG_REG (mode)
8037 + ((sh_round_reg (*ca, mode) + 1) ^ 1)),
8038 GEN_INT (4));
8039 return gen_rtx_PARALLEL(SCmode, gen_rtvec(2, r1, r2));
8042 /* If the alignment of a DF value causes an SF register to be
8043 skipped, we will use that skipped register for the next SF
8044 value. */
8045 if ((TARGET_HITACHI || ca->renesas_abi)
8046 && ca->free_single_fp_reg
8047 && mode == SFmode)
8048 return gen_rtx_REG (mode, ca->free_single_fp_reg);
8050 regno = (BASE_ARG_REG (mode) + sh_round_reg (*ca, mode))
8051 ^ (mode == SFmode && TARGET_SH4
8052 && TARGET_LITTLE_ENDIAN
8053 && ! TARGET_HITACHI && ! ca->renesas_abi);
8054 return gen_rtx_REG (mode, regno);
8058 return NULL_RTX;
8061 /* Update the data in CUM to advance over an argument
8062 of mode MODE and data type TYPE.
8063 (TYPE is null for libcalls where that information may not be
8064 available.) */
8065 static void
8066 sh_function_arg_advance (cumulative_args_t ca_v, machine_mode mode,
8067 const_tree type, bool named ATTRIBUTE_UNUSED)
8069 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
8071 if (ca->force_mem)
8072 ca->force_mem = false;
8074 if ((TARGET_HITACHI || ca->renesas_abi) && TARGET_FPU_DOUBLE)
8076 /* Note that we've used the skipped register. */
8077 if (mode == SFmode && ca->free_single_fp_reg)
8079 ca->free_single_fp_reg = 0;
8080 return;
8082 /* When we have a DF after an SF, there's an SF register that get
8083 skipped in order to align the DF value. We note this skipped
8084 register, because the next SF value will use it, and not the
8085 SF that follows the DF. */
8086 if (mode == DFmode
8087 && sh_round_reg (*ca, DFmode) != sh_round_reg (*ca, SFmode))
8089 ca->free_single_fp_reg = (sh_round_reg (*ca, SFmode)
8090 + BASE_ARG_REG (mode));
8094 if (! ((TARGET_SH4 || TARGET_SH2A) || ca->renesas_abi)
8095 || sh_pass_in_reg_p (*ca, mode, type))
8096 (ca->arg_count[(int) get_sh_arg_class (mode)]
8097 = (sh_round_reg (*ca, mode)
8098 + (mode == BLKmode
8099 ? CEIL (int_size_in_bytes (type), UNITS_PER_WORD)
8100 : CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD))));
8103 /* The Renesas calling convention doesn't quite fit into this scheme since
8104 the address is passed like an invisible argument, but one that is always
8105 passed in memory. */
8106 static rtx
8107 sh_struct_value_rtx (tree fndecl, int incoming ATTRIBUTE_UNUSED)
8109 if (TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8110 return NULL_RTX;
8111 return gen_rtx_REG (Pmode, 2);
8114 /* Worker function for TARGET_FUNCTION_VALUE.
8116 For the SH, this is like LIBCALL_VALUE, except that we must change the
8117 mode like PROMOTE_MODE does.
8118 ??? PROMOTE_MODE is ignored for non-scalar types. The set of types
8119 tested here has to be kept in sync with the one in
8120 explow.c:promote_mode. */
8121 static rtx
8122 sh_function_value (const_tree valtype,
8123 const_tree fn_decl_or_type,
8124 bool outgoing ATTRIBUTE_UNUSED)
8126 if (fn_decl_or_type
8127 && !DECL_P (fn_decl_or_type))
8128 fn_decl_or_type = NULL;
8130 return gen_rtx_REG (
8131 ((GET_MODE_CLASS (TYPE_MODE (valtype)) == MODE_INT
8132 && GET_MODE_SIZE (TYPE_MODE (valtype)) < 4
8133 && (TREE_CODE (valtype) == INTEGER_TYPE
8134 || TREE_CODE (valtype) == ENUMERAL_TYPE
8135 || TREE_CODE (valtype) == BOOLEAN_TYPE
8136 || TREE_CODE (valtype) == REAL_TYPE
8137 || TREE_CODE (valtype) == OFFSET_TYPE))
8138 && sh_promote_prototypes (fn_decl_or_type)
8139 ? SImode : TYPE_MODE (valtype)),
8140 BASE_RETURN_VALUE_REG (TYPE_MODE (valtype)));
8143 /* Worker function for TARGET_LIBCALL_VALUE. */
8144 static rtx
8145 sh_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED)
8147 return gen_rtx_REG (mode, BASE_RETURN_VALUE_REG (mode));
8150 /* Return true if N is a possible register number of function value. */
8151 static bool
8152 sh_function_value_regno_p (const unsigned int regno)
8154 return regno == FIRST_RET_REG || (TARGET_SH2E && regno == FIRST_FP_RET_REG);
8157 /* Worker function for TARGET_RETURN_IN_MEMORY. */
8158 static bool
8159 sh_return_in_memory (const_tree type, const_tree fndecl)
8161 return TYPE_MODE (type) == BLKmode
8162 || ((TARGET_HITACHI || sh_attr_renesas_p (fndecl))
8163 && TREE_CODE (type) == RECORD_TYPE);
8166 /* We actually emit the code in sh_expand_prologue. We used to use
8167 a static variable to flag that we need to emit this code, but that
8168 doesn't when inlining, when functions are deferred and then emitted
8169 later. Fortunately, we already have two flags that are part of struct
8170 function that tell if a function uses varargs or stdarg. */
8171 static void
8172 sh_setup_incoming_varargs (cumulative_args_t ca,
8173 machine_mode mode,
8174 tree type,
8175 int *pretend_arg_size,
8176 int second_time ATTRIBUTE_UNUSED)
8178 gcc_assert (cfun->stdarg);
8179 if (TARGET_VARARGS_PRETEND_ARGS (current_function_decl))
8181 int named_parm_regs, anon_parm_regs;
8183 named_parm_regs = (sh_round_reg (*get_cumulative_args (ca), mode)
8184 + (mode == BLKmode
8185 ? CEIL (int_size_in_bytes (type), UNITS_PER_WORD)
8186 : CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD)));
8187 anon_parm_regs = NPARM_REGS (SImode) - named_parm_regs;
8188 if (anon_parm_regs > 0)
8189 *pretend_arg_size = anon_parm_regs * 4;
8193 static bool
8194 sh_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED)
8196 return false;
8199 static bool
8200 sh_pretend_outgoing_varargs_named (cumulative_args_t ca_v)
8202 CUMULATIVE_ARGS *ca = get_cumulative_args (ca_v);
8204 return ! (TARGET_HITACHI || ca->renesas_abi);
8208 /* Define the offset between two registers, one to be eliminated, and
8209 the other its replacement, at the start of a routine. */
8211 initial_elimination_offset (int from, int to)
8213 const int regs_saved_rounding = 0;
8214 int save_flags = target_flags;
8215 HARD_REG_SET live_regs_mask;
8217 int regs_saved = calc_live_regs (&live_regs_mask);
8219 int total_auto_space = rounded_frame_size (regs_saved) - regs_saved_rounding;
8220 target_flags = save_flags;
8222 int total_saved_regs_space = regs_saved + regs_saved_rounding;
8224 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8225 return total_saved_regs_space + total_auto_space;
8227 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8228 return total_saved_regs_space + total_auto_space;
8230 /* Initial gap between fp and sp is 0. */
8231 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8232 return 0;
8234 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
8235 return rounded_frame_size (0);
8237 if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
8238 return rounded_frame_size (0);
8240 gcc_assert (from == RETURN_ADDRESS_POINTER_REGNUM
8241 && (to == HARD_FRAME_POINTER_REGNUM
8242 || to == STACK_POINTER_REGNUM));
8243 return total_auto_space;
8246 /* Parse the -mfixed-range= option string. */
8247 void
8248 sh_fix_range (const char *const_str)
8250 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
8251 REG2 are either register names or register numbers. The effect
8252 of this option is to mark the registers in the range from REG1 to
8253 REG2 as ``fixed'' so they won't be used by the compiler. */
8255 char* str = strcpy ((char*)alloca (strlen (const_str) + 1), const_str);
8257 while (1)
8259 char* dash = strchr (str, '-');
8260 if (!dash)
8262 warning (0, "value of -mfixed-range must have form REG1-REG2");
8263 return;
8265 *dash = '\0';
8266 char* comma = strchr (dash + 1, ',');
8267 if (comma)
8268 *comma = '\0';
8270 int first = decode_reg_name (str);
8271 if (first < 0)
8273 warning (0, "unknown register name: %s", str);
8274 return;
8277 int last = decode_reg_name (dash + 1);
8278 if (last < 0)
8280 warning (0, "unknown register name: %s", dash + 1);
8281 return;
8284 *dash = '-';
8286 if (first > last)
8288 warning (0, "%s-%s is an empty range", str, dash + 1);
8289 return;
8292 for (int i = first; i <= last; ++i)
8293 fixed_regs[i] = call_used_regs[i] = 1;
8295 if (!comma)
8296 break;
8298 *comma = ',';
8299 str = comma + 1;
8303 /* Insert any deferred function attributes from earlier pragmas. */
8304 static void
8305 sh_insert_attributes (tree node, tree *attributes)
8307 if (TREE_CODE (node) != FUNCTION_DECL)
8308 return;
8310 /* We are only interested in fields. */
8311 if (!DECL_P (node))
8312 return;
8314 /* Append the attributes to the deferred attributes. */
8315 *sh_deferred_function_attributes_tail = *attributes;
8316 tree attrs = sh_deferred_function_attributes;
8317 if (!attrs)
8318 return;
8320 /* Some attributes imply or require the interrupt attribute. */
8321 if (!lookup_attribute ("interrupt_handler", attrs)
8322 && !lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (node)))
8324 /* If we have a trapa_handler, but no interrupt_handler attribute,
8325 insert an interrupt_handler attribute. */
8326 if (lookup_attribute ("trapa_handler", attrs) != NULL_TREE)
8327 /* We can't use sh_pr_interrupt here because that's not in the
8328 java frontend. */
8329 attrs
8330 = tree_cons (get_identifier("interrupt_handler"), NULL_TREE, attrs);
8331 /* However, for sp_switch, trap_exit, nosave_low_regs and resbank,
8332 if the interrupt attribute is missing, we ignore the attribute
8333 and warn. */
8334 else if (lookup_attribute ("sp_switch", attrs)
8335 || lookup_attribute ("trap_exit", attrs)
8336 || lookup_attribute ("nosave_low_regs", attrs)
8337 || lookup_attribute ("resbank", attrs))
8339 tree *tail;
8341 for (tail = attributes; attrs; attrs = TREE_CHAIN (attrs))
8343 if (is_attribute_p ("sp_switch", TREE_PURPOSE (attrs))
8344 || is_attribute_p ("trap_exit", TREE_PURPOSE (attrs))
8345 || is_attribute_p ("nosave_low_regs", TREE_PURPOSE (attrs))
8346 || is_attribute_p ("resbank", TREE_PURPOSE (attrs)))
8347 warning (OPT_Wattributes,
8348 "%qE attribute only applies to interrupt functions",
8349 TREE_PURPOSE (attrs));
8350 else
8352 *tail = tree_cons (TREE_PURPOSE (attrs), NULL_TREE,
8353 NULL_TREE);
8354 tail = &TREE_CHAIN (*tail);
8357 attrs = *attributes;
8361 /* Install the processed list. */
8362 *attributes = attrs;
8364 /* Clear deferred attributes. */
8365 sh_deferred_function_attributes = NULL_TREE;
8366 sh_deferred_function_attributes_tail = &sh_deferred_function_attributes;
8368 return;
8371 /*------------------------------------------------------------------------------
8372 Target specific attributes
8373 Supported attributes are:
8375 * interrupt_handler
8376 Specifies this function is an interrupt handler.
8378 * trapa_handler
8379 Like interrupt_handler, but don't save all registers.
8381 * sp_switch
8382 Specifies an alternate stack for an interrupt handler to run on.
8384 * trap_exit
8385 Use a trapa to exit an interrupt function instead of rte.
8387 * nosave_low_regs
8388 Don't save r0..r7 in an interrupt handler function.
8389 This is useful on SH3* and SH4*, which have a separate set of low
8390 regs for user and privileged modes.
8391 This is mainly to be used for non-reentrant interrupt handlers (i.e.
8392 those that run with interrupts disabled and thus can't be
8393 interrupted thenselves).
8395 * renesas
8396 Use Renesas calling/layout conventions (functions and structures).
8398 * resbank
8399 In case of an interrupt handler function, use a register bank to
8400 save registers R0-R14, MACH, MACL, GBR and PR.
8401 This is available only on SH2A targets.
8403 * function_vector
8404 Declares a function to be called using the TBR relative addressing
8405 mode. Takes an argument that specifies the slot number in the table
8406 where this function can be looked up by the JSR/N @@(disp8,TBR) insn.
8409 /* Handle a 'resbank' attribute. */
8410 static tree
8411 sh_handle_resbank_handler_attribute (tree * node, tree name,
8412 tree args ATTRIBUTE_UNUSED,
8413 int flags ATTRIBUTE_UNUSED,
8414 bool * no_add_attrs)
8416 if (!TARGET_SH2A)
8418 warning (OPT_Wattributes, "%qE attribute is supported only for SH2A",
8419 name);
8420 *no_add_attrs = true;
8422 if (TREE_CODE (*node) != FUNCTION_DECL)
8424 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8425 name);
8426 *no_add_attrs = true;
8429 return NULL_TREE;
8432 /* Handle an "interrupt_handler" attribute; arguments as in
8433 struct attribute_spec.handler. */
8434 static tree
8435 sh_handle_interrupt_handler_attribute (tree *node, tree name,
8436 tree args ATTRIBUTE_UNUSED,
8437 int flags ATTRIBUTE_UNUSED,
8438 bool *no_add_attrs)
8440 if (TREE_CODE (*node) != FUNCTION_DECL)
8442 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8443 name);
8444 *no_add_attrs = true;
8447 return NULL_TREE;
8450 /* Handle an 'function_vector' attribute; arguments as in
8451 struct attribute_spec.handler. */
8452 static tree
8453 sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
8454 tree args ATTRIBUTE_UNUSED,
8455 int flags ATTRIBUTE_UNUSED,
8456 bool * no_add_attrs)
8458 if (!TARGET_SH2A)
8460 warning (OPT_Wattributes, "%qE attribute only applies to SH2A",
8461 name);
8462 *no_add_attrs = true;
8464 else if (TREE_CODE (*node) != FUNCTION_DECL)
8466 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8467 name);
8468 *no_add_attrs = true;
8470 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8472 /* The argument must be a constant integer. */
8473 warning (OPT_Wattributes,
8474 "%qE attribute argument not an integer constant",
8475 name);
8476 *no_add_attrs = true;
8478 else if (TREE_INT_CST_LOW (TREE_VALUE (args)) > 255)
8480 /* The argument value must be between 0 to 255. */
8481 warning (OPT_Wattributes,
8482 "%qE attribute argument should be between 0 to 255",
8483 name);
8484 *no_add_attrs = true;
8486 return NULL_TREE;
8489 /* Returns true if current function has been assigned the attribute
8490 'function_vector'. */
8491 bool
8492 sh2a_is_function_vector_call (rtx x)
8494 if (GET_CODE (x) == SYMBOL_REF
8495 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8497 tree tr = SYMBOL_REF_DECL (x);
8499 if (sh2a_function_vector_p (tr))
8500 return true;
8503 return false;
8506 /* Returns the function vector number, if the attribute
8507 'function_vector' is assigned, otherwise returns zero. */
8509 sh2a_get_function_vector_number (rtx x)
8511 if ((GET_CODE (x) == SYMBOL_REF)
8512 && (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
8514 tree t = SYMBOL_REF_DECL (x);
8516 if (TREE_CODE (t) != FUNCTION_DECL)
8517 return 0;
8519 for (tree list = SH_ATTRIBUTES (t); list; list = TREE_CHAIN (list))
8520 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8521 return TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (list)));
8523 return 0;
8525 else
8526 return 0;
8529 /* Handle an "sp_switch" attribute; arguments as in
8530 struct attribute_spec.handler. */
8531 static tree
8532 sh_handle_sp_switch_attribute (tree *node, tree name, tree args,
8533 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8535 if (TREE_CODE (*node) != FUNCTION_DECL)
8537 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8538 name);
8539 *no_add_attrs = true;
8541 else if (TREE_CODE (TREE_VALUE (args)) != STRING_CST)
8543 /* The argument must be a constant string. */
8544 warning (OPT_Wattributes, "%qE attribute argument not a string constant",
8545 name);
8546 *no_add_attrs = true;
8549 return NULL_TREE;
8552 /* Handle an "trap_exit" attribute; arguments as in
8553 struct attribute_spec.handler. */
8554 static tree
8555 sh_handle_trap_exit_attribute (tree *node, tree name, tree args,
8556 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
8558 if (TREE_CODE (*node) != FUNCTION_DECL)
8560 warning (OPT_Wattributes, "%qE attribute only applies to functions",
8561 name);
8562 *no_add_attrs = true;
8564 /* The argument specifies a trap number to be used in a trapa instruction
8565 at function exit (instead of an rte instruction). */
8566 else if (TREE_CODE (TREE_VALUE (args)) != INTEGER_CST)
8568 /* The argument must be a constant integer. */
8569 warning (OPT_Wattributes, "%qE attribute argument not an "
8570 "integer constant", name);
8571 *no_add_attrs = true;
8574 return NULL_TREE;
8577 static tree
8578 sh_handle_renesas_attribute (tree *node ATTRIBUTE_UNUSED,
8579 tree name ATTRIBUTE_UNUSED,
8580 tree args ATTRIBUTE_UNUSED,
8581 int flags ATTRIBUTE_UNUSED,
8582 bool *no_add_attrs ATTRIBUTE_UNUSED)
8584 return NULL_TREE;
8587 /* True if __attribute__((renesas)) or -mrenesas. */
8588 bool
8589 sh_attr_renesas_p (const_tree td)
8591 if (TARGET_HITACHI)
8592 return true;
8593 if (td == NULL_TREE)
8594 return false;
8595 if (DECL_P (td))
8596 td = TREE_TYPE (td);
8597 if (td == error_mark_node)
8598 return false;
8599 return lookup_attribute ("renesas", TYPE_ATTRIBUTES (td)) != NULL_TREE;
8602 /* True if __attribute__((renesas)) or -mrenesas, for the current
8603 function. */
8604 bool
8605 sh_cfun_attr_renesas_p (void)
8607 return sh_attr_renesas_p (current_function_decl);
8610 /* Returns true if the current function has the "interrupt_handler"
8611 attribute set. */
8612 bool
8613 sh_cfun_interrupt_handler_p (void)
8615 return (lookup_attribute ("interrupt_handler",
8616 DECL_ATTRIBUTES (current_function_decl))
8617 != NULL_TREE);
8620 /* Returns true if FUNC has been assigned the attribute
8621 "function_vector". */
8622 bool
8623 sh2a_function_vector_p (tree func)
8625 if (TREE_CODE (func) != FUNCTION_DECL)
8626 return false;
8628 for (tree list = SH_ATTRIBUTES (func); list; list = TREE_CHAIN (list))
8629 if (is_attribute_p ("function_vector", TREE_PURPOSE (list)))
8630 return true;
8632 return false;
8635 /* Returns true if given tree has the "resbank" attribute set. */
8636 bool
8637 sh_cfun_resbank_handler_p (void)
8639 return ((lookup_attribute ("resbank",
8640 DECL_ATTRIBUTES (current_function_decl))
8641 != NULL_TREE)
8642 && (lookup_attribute ("interrupt_handler",
8643 DECL_ATTRIBUTES (current_function_decl))
8644 != NULL_TREE) && TARGET_SH2A);
8647 /* Returns true if the current function has a "trap_exit" attribute set. */
8648 bool
8649 sh_cfun_trap_exit_p (void)
8651 return lookup_attribute ("trap_exit", DECL_ATTRIBUTES (current_function_decl))
8652 != NULL_TREE;
8655 /* Implement TARGET_CHECK_PCH_TARGET_FLAGS. */
8656 static const char *
8657 sh_check_pch_target_flags (int old_flags)
8659 if ((old_flags ^ target_flags) & (MASK_SH1 | MASK_SH2 | MASK_SH3
8660 | MASK_SH_E | MASK_HARD_SH4
8661 | MASK_FPU_SINGLE | MASK_SH4))
8662 return _("created and used with different architectures / ABIs");
8663 if ((old_flags ^ target_flags) & MASK_HITACHI)
8664 return _("created and used with different ABIs");
8665 if ((old_flags ^ target_flags) & MASK_LITTLE_ENDIAN)
8666 return _("created and used with different endianness");
8667 return NULL;
8670 /* Predicates used by the templates. */
8672 /* Returns true if OP is MACL, MACH or PR. The input must be a REG rtx.
8673 Used only in general_movsrc_operand. */
8674 bool
8675 system_reg_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
8677 switch (REGNO (op))
8679 case PR_REG:
8680 case MACL_REG:
8681 case MACH_REG:
8682 return true;
8684 return false;
8687 /* Returns true if OP is a floating point value with value 0.0. */
8688 bool
8689 fp_zero_operand (rtx op)
8691 if (GET_MODE (op) != SFmode)
8692 return false;
8694 const REAL_VALUE_TYPE* r = CONST_DOUBLE_REAL_VALUE (op);
8695 return real_equal (r, &dconst0) && ! REAL_VALUE_MINUS_ZERO (*r);
8698 /* Returns true if OP is a floating point value with value 1.0. */
8699 bool
8700 fp_one_operand (rtx op)
8702 if (GET_MODE (op) != SFmode)
8703 return false;
8705 return real_equal (CONST_DOUBLE_REAL_VALUE (op), &dconst1);
8708 /* Return the TLS type for TLS symbols. */
8709 enum tls_model
8710 tls_symbolic_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
8712 if (GET_CODE (op) != SYMBOL_REF)
8713 return TLS_MODEL_NONE;
8714 return SYMBOL_REF_TLS_MODEL (op);
8717 /* Return the destination address of a branch. */
8718 static int
8719 branch_dest (rtx branch)
8721 rtx dest = SET_SRC (PATTERN (branch));
8723 if (GET_CODE (dest) == IF_THEN_ELSE)
8724 dest = XEXP (dest, 1);
8726 return INSN_ADDRESSES (INSN_UID (XEXP (dest, 0)));
8729 /* Return nonzero if REG is not used after INSN.
8730 We assume REG is a reload reg, and therefore does
8731 not live past labels. It may live past calls or jumps though. */
8732 bool
8733 reg_unused_after (rtx reg, rtx_insn *insn)
8735 /* If the reg is set by this instruction, then it is safe for our
8736 case. Disregard the case where this is a store to memory, since
8737 we are checking a register used in the store address. */
8738 rtx set = single_set (insn);
8739 if (set && !MEM_P (SET_DEST (set))
8740 && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8741 return true;
8743 while ((insn = NEXT_INSN (insn)))
8745 if (!INSN_P (insn))
8746 continue;
8748 rtx_code code = GET_CODE (insn);
8750 #if 0
8751 /* If this is a label that existed before reload, then the register
8752 is dead here. However, if this is a label added by reorg, then
8753 the register may still be live here. We can't tell the difference,
8754 so we just ignore labels completely. */
8755 if (code == CODE_LABEL)
8756 return 1;
8757 /* else */
8758 #endif
8760 if (code == JUMP_INSN)
8761 return false;
8763 /* If this is a sequence, we must handle them all at once.
8764 We could have for instance a call that sets the target register,
8765 and an insn in a delay slot that uses the register. In this case,
8766 we must return 0. */
8767 else if (code == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
8769 rtx_sequence *seq = as_a <rtx_sequence *> (PATTERN (insn));
8770 bool retval = false;
8772 for (int i = 0; i < seq->len (); i++)
8774 rtx_insn *this_insn = seq->insn (i);
8775 rtx set = single_set (this_insn);
8777 if (CALL_P (this_insn))
8778 code = CALL_INSN;
8779 else if (JUMP_P (this_insn))
8781 if (INSN_ANNULLED_BRANCH_P (this_insn))
8782 return false;
8783 code = JUMP_INSN;
8786 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8787 return false;
8788 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8790 if (!MEM_P (SET_DEST (set)))
8791 retval = true;
8792 else
8793 return false;
8795 if (set == NULL_RTX
8796 && reg_overlap_mentioned_p (reg, PATTERN (this_insn)))
8797 return false;
8799 if (retval)
8800 return true;
8801 else if (code == JUMP_INSN)
8802 return false;
8805 rtx set = single_set (insn);
8806 if (set && reg_overlap_mentioned_p (reg, SET_SRC (set)))
8807 return false;
8808 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
8809 return !MEM_P (SET_DEST (set));
8810 if (set == NULL && reg_overlap_mentioned_p (reg, PATTERN (insn)))
8811 return false;
8813 if (code == CALL_INSN && call_really_used_regs[REGNO (reg)])
8814 return true;
8816 return true;
8820 static GTY(()) rtx t_reg_rtx;
8822 get_t_reg_rtx (void)
8824 if (! t_reg_rtx)
8825 t_reg_rtx = gen_rtx_REG (SImode, T_REG);
8826 return t_reg_rtx;
8829 static GTY(()) tree fpscr_values;
8831 static void
8832 emit_fpu_switch (rtx scratch, int index)
8834 if (fpscr_values == NULL)
8836 tree t = build_index_type (integer_one_node);
8837 t = build_array_type (integer_type_node, t);
8838 t = build_decl (BUILTINS_LOCATION,
8839 VAR_DECL, get_identifier ("__fpscr_values"), t);
8840 DECL_ARTIFICIAL (t) = 1;
8841 DECL_IGNORED_P (t) = 1;
8842 DECL_EXTERNAL (t) = 1;
8843 TREE_STATIC (t) = 1;
8844 TREE_PUBLIC (t) = 1;
8845 TREE_USED (t) = 1;
8847 fpscr_values = t;
8850 rtx src = DECL_RTL (fpscr_values);
8851 if (!can_create_pseudo_p ())
8853 emit_move_insn (scratch, XEXP (src, 0));
8854 if (index != 0)
8855 emit_insn (gen_addsi3 (scratch, scratch, GEN_INT (index * 4)));
8856 src = adjust_automodify_address (src, SImode, scratch, index * 4);
8858 else
8859 src = adjust_address (src, SImode, index * 4);
8861 emit_insn (gen_lds_fpscr (src));
8864 static rtx get_free_reg (HARD_REG_SET);
8866 /* This function returns a register to use to load the address to load
8867 the fpscr from. Currently it always returns r1 or r7, but when we are
8868 able to use pseudo registers after combine, or have a better mechanism
8869 for choosing a register, it should be done here. */
8870 /* REGS_LIVE is the liveness information for the point for which we
8871 need this allocation. In some bare-bones exit blocks, r1 is live at the
8872 start. We can even have all of r0..r3 being live:
8873 __complex__ long long f (double d) { if (d == 0) return 2; else return 3; }
8874 INSN before which new insns are placed with will clobber the register
8875 we return. If a basic block consists only of setting the return value
8876 register to a pseudo and using that register, the return value is not
8877 live before or after this block, yet we we'll insert our insns right in
8878 the middle. */
8879 static rtx
8880 get_free_reg (HARD_REG_SET regs_live)
8882 if (! TEST_HARD_REG_BIT (regs_live, 1))
8883 return gen_rtx_REG (Pmode, 1);
8885 /* Hard reg 1 is live; since this is a small register classes target,
8886 there shouldn't be anything but a jump before the function end. */
8887 gcc_assert (!TEST_HARD_REG_BIT (regs_live, 7));
8888 return gen_rtx_REG (Pmode, 7);
8891 /* This function will set the fpscr from memory.
8892 MODE is the mode we are setting it to. */
8893 void
8894 fpscr_set_from_mem (int mode, HARD_REG_SET regs_live)
8896 enum attr_fp_mode fp_mode = (enum attr_fp_mode) mode;
8897 enum attr_fp_mode norm_mode = ACTUAL_NORMAL_MODE (FP_MODE);
8899 rtx addr_reg = !can_create_pseudo_p () ? get_free_reg (regs_live) : NULL_RTX;
8900 emit_fpu_switch (addr_reg, fp_mode == norm_mode);
8903 /* Is the given character a logical line separator for the assembler? */
8904 #ifndef IS_ASM_LOGICAL_LINE_SEPARATOR
8905 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == ';')
8906 #endif
8908 static bool
8909 sequence_insn_p (rtx_insn *insn)
8911 rtx_insn* prev = PREV_INSN (insn);
8912 if (prev == NULL)
8913 return false;
8915 rtx_insn* next = NEXT_INSN (prev);
8916 if (next == NULL)
8917 return false;
8919 return INSN_P (next) && GET_CODE (PATTERN (next)) == SEQUENCE;
8923 sh_insn_length_adjustment (rtx_insn *insn)
8925 /* Instructions with unfilled delay slots take up an extra two bytes for
8926 the nop in the delay slot. */
8927 if (((NONJUMP_INSN_P (insn)
8928 && GET_CODE (PATTERN (insn)) != USE
8929 && GET_CODE (PATTERN (insn)) != CLOBBER)
8930 || CALL_P (insn) || JUMP_P (insn))
8931 && ! sequence_insn_p (insn)
8932 && get_attr_needs_delay_slot (insn) == NEEDS_DELAY_SLOT_YES)
8933 return 2;
8935 /* Increase the insn length of a cbranch without a delay slot insn to
8936 force a delay slot which will be stuffed with a nop. */
8937 if (TARGET_CBRANCH_FORCE_DELAY_SLOT && TARGET_SH2
8938 && JUMP_P (insn) && get_attr_type (insn) == TYPE_CBRANCH
8939 && ! sequence_insn_p (insn))
8940 return 2;
8942 /* sh-dsp parallel processing insn take four bytes instead of two. */
8944 if (NONJUMP_INSN_P (insn))
8946 int sum = 0;
8947 rtx body = PATTERN (insn);
8948 const char *templ;
8949 char c;
8950 bool maybe_label = true;
8952 if (GET_CODE (body) == ASM_INPUT)
8953 templ = XSTR (body, 0);
8954 else if (asm_noperands (body) >= 0)
8955 templ
8956 = decode_asm_operands (body, NULL, NULL, NULL, NULL, NULL);
8957 else
8958 return 0;
8961 int ppi_adjust = 0;
8964 c = *templ++;
8965 while (c == ' ' || c == '\t');
8966 /* all sh-dsp parallel-processing insns start with p.
8967 The only non-ppi sh insn starting with p is pref.
8968 The only ppi starting with pr is prnd. */
8969 if ((c == 'p' || c == 'P') && strncasecmp ("re", templ, 2))
8970 ppi_adjust = 2;
8971 /* The repeat pseudo-insn expands two three insns, a total of
8972 six bytes in size. */
8973 else if ((c == 'r' || c == 'R')
8974 && ! strncasecmp ("epeat", templ, 5))
8975 ppi_adjust = 4;
8976 while (c && c != '\n'
8977 && ! IS_ASM_LOGICAL_LINE_SEPARATOR (c, templ))
8979 /* If this is a label, it is obviously not a ppi insn. */
8980 if (c == ':' && maybe_label)
8982 ppi_adjust = 0;
8983 break;
8985 else if (c == '\'' || c == '"')
8986 maybe_label = false;
8987 c = *templ++;
8989 sum += ppi_adjust;
8990 maybe_label = c != ':';
8992 while (c);
8993 return sum;
8995 return 0;
8998 /* Return TRUE for a valid displacement for the REG+disp addressing
8999 with MODE. */
9000 bool
9001 sh_legitimate_index_p (machine_mode mode, rtx op, bool consider_sh2a,
9002 bool allow_zero)
9004 if (! CONST_INT_P (op))
9005 return false;
9008 const HOST_WIDE_INT offset = INTVAL (op);
9009 const int max_disp = sh_max_mov_insn_displacement (mode, consider_sh2a);
9010 const int align_mask = mov_insn_alignment_mask (mode, consider_sh2a);
9012 /* If the mode does not support any displacement always return false.
9013 Even though an index of '0' is actually always valid, it will cause
9014 troubles when e.g. a DFmode move is split into two SFmode moves,
9015 where one SFmode move will have index '0' and the other move will
9016 have index '4'. */
9017 if (!allow_zero && max_disp < 1)
9018 return false;
9020 return offset >= 0 && offset <= max_disp && (offset & align_mask) == 0;
9024 /* Recognize an RTL expression that is a valid memory address for
9025 an instruction.
9026 The MODE argument is the machine mode for the MEM expression
9027 that wants to use this address.
9028 Allow REG
9029 REG+disp
9030 REG+r0
9031 REG++
9032 --REG
9034 GBR+disp */
9035 static bool
9036 sh_legitimate_address_p (machine_mode mode, rtx x, bool strict)
9038 if (REG_P (x) && REGNO (x) == GBR_REG)
9039 return true;
9041 if (MAYBE_BASE_REGISTER_RTX_P (x, strict))
9042 return true;
9043 else if ((GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC)
9044 && MAYBE_BASE_REGISTER_RTX_P (XEXP (x, 0), strict))
9045 return true;
9046 else if (GET_CODE (x) == PLUS)
9048 rtx xop0 = XEXP (x, 0);
9049 rtx xop1 = XEXP (x, 1);
9051 if (REG_P (xop0) && REGNO (xop0) == GBR_REG)
9052 return gbr_displacement (xop1, mode);
9054 if (GET_MODE_SIZE (mode) <= 8
9055 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict)
9056 && sh_legitimate_index_p (mode, xop1, TARGET_SH2A, false))
9057 return true;
9059 if (GET_MODE_SIZE (mode) <= 4
9060 || (TARGET_FPU_DOUBLE && TARGET_FMOVD && mode == DFmode))
9062 if (MAYBE_BASE_REGISTER_RTX_P (xop1, strict)
9063 && MAYBE_INDEX_REGISTER_RTX_P (xop0, strict))
9064 return true;
9065 if (MAYBE_INDEX_REGISTER_RTX_P (xop1, strict)
9066 && MAYBE_BASE_REGISTER_RTX_P (xop0, strict))
9067 return true;
9071 return false;
9074 /* Return TRUE if X references a SYMBOL_REF or LABEL_REF whose symbol
9075 isn't protected by a PIC unspec. */
9076 bool
9077 nonpic_symbol_mentioned_p (rtx x)
9079 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
9080 || GET_CODE (x) == PC)
9081 return true;
9083 /* We don't want to look into the possible MEM location of a
9084 CONST_DOUBLE, since we're not going to use it, in general. */
9085 if (GET_CODE (x) == CONST_DOUBLE)
9086 return false;
9088 if (GET_CODE (x) == UNSPEC
9089 && (XINT (x, 1) == UNSPEC_PIC
9090 || XINT (x, 1) == UNSPEC_GOT
9091 || XINT (x, 1) == UNSPEC_GOTOFF
9092 || XINT (x, 1) == UNSPEC_GOTPLT
9093 || XINT (x, 1) == UNSPEC_GOTTPOFF
9094 || XINT (x, 1) == UNSPEC_DTPOFF
9095 || XINT (x, 1) == UNSPEC_TPOFF
9096 || XINT (x, 1) == UNSPEC_PLT
9097 || XINT (x, 1) == UNSPEC_PCREL
9098 || XINT (x, 1) == UNSPEC_SYMOFF
9099 || XINT (x, 1) == UNSPEC_PCREL_SYMOFF
9100 || XINT (x, 1) == UNSPEC_GOTFUNCDESC
9101 || XINT (x, 1) == UNSPEC_GOTOFFFUNCDESC))
9102 return false;
9104 const char* fmt = GET_RTX_FORMAT (GET_CODE (x));
9105 for (int i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
9107 if (fmt[i] == 'E')
9109 for (int j = XVECLEN (x, i) - 1; j >= 0; j--)
9110 if (nonpic_symbol_mentioned_p (XVECEXP (x, i, j)))
9111 return true;
9113 else if (fmt[i] == 'e' && nonpic_symbol_mentioned_p (XEXP (x, i)))
9114 return true;
9117 return false;
9120 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
9121 @GOTOFF in `reg'. */
9123 legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED, rtx reg)
9125 if (tls_symbolic_operand (orig, Pmode) != TLS_MODEL_NONE)
9126 return orig;
9128 if (GET_CODE (orig) == LABEL_REF
9129 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
9131 if (reg == NULL_RTX)
9132 reg = gen_reg_rtx (Pmode);
9134 if (TARGET_FDPIC
9135 && GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (orig))
9137 /* Weak functions may be NULL which doesn't work with
9138 GOTOFFFUNCDESC because the runtime offset is not known. */
9139 if (SYMBOL_REF_WEAK (orig))
9140 emit_insn (gen_symGOTFUNCDESC2reg (reg, orig));
9141 else
9142 emit_insn (gen_symGOTOFFFUNCDESC2reg (reg, orig));
9144 else if (TARGET_FDPIC
9145 && (GET_CODE (orig) == LABEL_REF
9146 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_DECL (orig)
9147 && (TREE_READONLY (SYMBOL_REF_DECL (orig))
9148 || SYMBOL_REF_EXTERNAL_P (orig)
9149 || DECL_SECTION_NAME(SYMBOL_REF_DECL (orig))))))
9150 /* In FDPIC, GOTOFF can only be used for writable data. */
9151 emit_insn (gen_symGOT2reg (reg, orig));
9152 else
9153 emit_insn (gen_symGOTOFF2reg (reg, orig));
9154 return reg;
9156 else if (GET_CODE (orig) == SYMBOL_REF)
9158 if (reg == NULL_RTX)
9159 reg = gen_reg_rtx (Pmode);
9161 if (TARGET_FDPIC && SYMBOL_REF_FUNCTION_P (orig))
9162 emit_insn (gen_symGOTFUNCDESC2reg (reg, orig));
9163 else
9164 emit_insn (gen_symGOT2reg (reg, orig));
9165 return reg;
9167 return orig;
9170 /* Given a (logical) mode size and an offset in bytes, try to find a the
9171 appropriate displacement value for a mov insn. On SH the displacements
9172 are limited to max. 60 bytes for SImode, max. 30 bytes in HImode and max.
9173 15 bytes in QImode. To compensate this we create a new base address by
9174 adding an adjustment value to it.
9176 If the originally requested offset is greater than 127 we prefer using
9177 values 124..127 over 128..131 to increase opportunities to use the
9178 add #imm, Rn insn.
9180 In some cases it is possible that a requested offset might seem unaligned
9181 or inappropriate for the mode size, like offset = 2 and mode size = 4.
9182 This is compensated by adjusting the base address so that the effective
9183 address of the displacement move insn will be aligned.
9185 This is not the best possible way of rebasing the base address, as it
9186 does not look at other present displacement addressings around it.
9187 In some cases this can create more base address adjustments than would
9188 actually be necessary. */
9189 struct disp_adjust
9191 rtx offset_adjust;
9192 rtx mov_disp;
9195 static struct disp_adjust
9196 sh_find_mov_disp_adjust (machine_mode mode, HOST_WIDE_INT offset)
9198 struct disp_adjust res = { NULL_RTX, NULL_RTX };
9200 /* Do not try to use SH2A's large displacements here, because this would
9201 effectively disable the small displacement insns. */
9202 const int mode_sz = GET_MODE_SIZE (mode);
9203 const int mov_insn_sz = mov_insn_size (mode, false);
9204 const int max_disp = sh_max_mov_insn_displacement (mode, false);
9205 const int max_disp_next = max_disp + mov_insn_sz;
9206 HOST_WIDE_INT align_modifier = offset > 127 ? mov_insn_sz : 0;
9207 HOST_WIDE_INT offset_adjust;
9209 /* In some cases this actually does happen and we must check for it. */
9210 if (mode_sz < 1 || mode_sz > 8 || max_disp < 1)
9211 return res;
9213 /* Keeps the previous behavior for QImode displacement addressing.
9214 This just decides how the offset is re-based. Removing this special
9215 case will result in slightly bigger code on average, but it's not that
9216 bad actually. */
9217 if (mov_insn_sz == 1)
9218 align_modifier = 0;
9220 offset_adjust = ((offset + align_modifier) & ~max_disp) - align_modifier;
9222 if (mode_sz + offset - offset_adjust <= max_disp_next)
9224 res.offset_adjust = GEN_INT (offset_adjust);
9225 res.mov_disp = GEN_INT (offset - offset_adjust);
9228 return res;
9231 /* Try to modify an illegitimate address and make it legitimate.
9232 If we find one, return the new, valid address.
9233 Otherwise, return the original address. */
9234 static rtx
9235 sh_legitimize_address (rtx x, rtx oldx, machine_mode mode)
9237 if (flag_pic)
9238 x = legitimize_pic_address (oldx, mode, NULL_RTX);
9240 if ((TARGET_FPU_DOUBLE && mode == DFmode)
9241 || (TARGET_SH2E && mode == SFmode))
9242 return x;
9244 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1))
9245 && BASE_REGISTER_RTX_P (XEXP (x, 0)))
9247 struct disp_adjust adj = sh_find_mov_disp_adjust (mode,
9248 INTVAL (XEXP (x, 1)));
9250 if (adj.offset_adjust != NULL_RTX && adj.mov_disp != NULL_RTX)
9252 rtx sum = expand_binop (Pmode, add_optab, XEXP (x, 0),
9253 adj.offset_adjust, NULL_RTX, 0,
9254 OPTAB_LIB_WIDEN);
9255 return gen_rtx_PLUS (Pmode, sum, adj.mov_disp);
9258 return x;
9261 /* Attempt to replace *p, which is an address that needs reloading, with
9262 a valid memory address for an operand of mode MODE.
9263 Like for sh_legitimize_address, for the SH we try to get a normal form
9264 of the address. That will allow inheritance of the address reloads. */
9265 bool
9266 sh_legitimize_reload_address (rtx *p, machine_mode mode, int opnum,
9267 int itype)
9269 enum reload_type type = (enum reload_type) itype;
9270 const int mode_sz = GET_MODE_SIZE (mode);
9272 if (sh_lra_p ())
9273 return false;
9275 if (GET_CODE (*p) == PLUS && CONST_INT_P (XEXP (*p, 1))
9276 && MAYBE_BASE_REGISTER_RTX_P (XEXP (*p, 0), true))
9278 const HOST_WIDE_INT offset = INTVAL (XEXP (*p, 1));
9279 struct disp_adjust adj = sh_find_mov_disp_adjust (mode, offset);
9281 if (TARGET_SH2A && mode == DFmode && (offset & 0x7))
9283 push_reload (*p, NULL_RTX, p, NULL,
9284 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9285 return true;
9288 if (TARGET_SH2E && mode == SFmode)
9290 *p = copy_rtx (*p);
9291 push_reload (*p, NULL_RTX, p, NULL,
9292 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9293 return true;
9296 /* FIXME: Do not allow to legitimize QImode and HImode displacement
9297 moves because then reload has a problem figuring the constraint
9298 that the move insn target/source reg must be R0.
9299 Or maybe some handling is wrong in sh_secondary_reload for this
9300 to work properly? */
9301 if ((mode_sz == 4 || mode_sz == 8)
9302 && ! (TARGET_SH4 && mode == DFmode)
9303 && adj.offset_adjust != NULL_RTX && adj.mov_disp != NULL_RTX)
9305 rtx sum = gen_rtx_PLUS (Pmode, XEXP (*p, 0), adj.offset_adjust);
9306 *p = gen_rtx_PLUS (Pmode, sum, adj.mov_disp);
9307 push_reload (sum, NULL_RTX, &XEXP (*p, 0), NULL,
9308 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9309 return true;
9313 /* We must re-recognize what we created before. */
9314 if (GET_CODE (*p) == PLUS
9315 && (mode_sz == 4 || mode_sz == 8)
9316 && GET_CODE (XEXP (*p, 0)) == PLUS
9317 && CONST_INT_P (XEXP (XEXP (*p, 0), 1))
9318 && MAYBE_BASE_REGISTER_RTX_P (XEXP (XEXP (*p, 0), 0), true)
9319 && CONST_INT_P (XEXP (*p, 1))
9320 && ! (TARGET_SH2E && mode == SFmode))
9322 /* Because this address is so complex, we know it must have
9323 been created by LEGITIMIZE_RELOAD_ADDRESS before; thus,
9324 it is already unshared, and needs no further unsharing. */
9325 push_reload (XEXP (*p, 0), NULL_RTX, &XEXP (*p, 0), NULL,
9326 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, opnum, type);
9327 return true;
9330 return false;
9333 /* In the name of slightly smaller debug output, and to cater to
9334 general assembler lossage, recognize various UNSPEC sequences
9335 and turn them back into a direct symbol reference. */
9336 static rtx
9337 sh_delegitimize_address (rtx orig_x)
9339 orig_x = delegitimize_mem_from_attrs (orig_x);
9341 rtx x = orig_x;
9342 if (MEM_P (x))
9343 x = XEXP (x, 0);
9344 if (GET_CODE (x) == CONST)
9346 rtx y = XEXP (x, 0);
9347 if (GET_CODE (y) == UNSPEC)
9349 if (XINT (y, 1) == UNSPEC_GOT
9350 || XINT (y, 1) == UNSPEC_GOTOFF
9351 || XINT (y, 1) == UNSPEC_SYMOFF)
9352 return XVECEXP (y, 0, 0);
9353 else if (XINT (y, 1) == UNSPEC_PCREL_SYMOFF)
9355 if (GET_CODE (XVECEXP (y, 0, 0)) == CONST)
9357 rtx symplt = XEXP (XVECEXP (y, 0, 0), 0);
9359 if (GET_CODE (symplt) == UNSPEC
9360 && (XINT (symplt, 1) == UNSPEC_PLT
9361 || XINT (symplt, 1) == UNSPEC_PCREL))
9362 return XVECEXP (symplt, 0, 0);
9368 return orig_x;
9371 /* Mark the use of a constant in the literal table. If the constant
9372 has multiple labels, make it unique. */
9373 static rtx
9374 mark_constant_pool_use (rtx x)
9376 if (x == NULL_RTX)
9377 return x;
9379 switch (GET_CODE (x))
9381 case LABEL_REF:
9382 x = XEXP (x, 0);
9383 case CODE_LABEL:
9384 break;
9385 default:
9386 return x;
9389 /* Get the first label in the list of labels for the same constant
9390 and delete another labels in the list. */
9391 rtx_insn* lab = as_a <rtx_insn*> (x);
9392 for (rtx_insn* insn = PREV_INSN (lab); insn; insn = PREV_INSN (insn))
9394 if (!LABEL_P (insn)
9395 || LABEL_REFS (insn) != NEXT_INSN (insn))
9396 break;
9397 lab = insn;
9400 for (rtx insn = LABEL_REFS (lab); insn; insn = LABEL_REFS (insn))
9401 as_a<rtx_insn *> (insn)->set_deleted ();
9403 /* Mark constants in a window. */
9404 for (rtx_insn* insn = NEXT_INSN (as_a <rtx_insn *> (x)); insn;
9405 insn = NEXT_INSN (insn))
9407 if (!NONJUMP_INSN_P (insn))
9408 continue;
9410 rtx pattern = PATTERN (insn);
9411 if (GET_CODE (pattern) != UNSPEC_VOLATILE)
9412 continue;
9414 switch (XINT (pattern, 1))
9416 case UNSPECV_CONST2:
9417 case UNSPECV_CONST4:
9418 case UNSPECV_CONST8:
9419 XVECEXP (pattern, 0, 1) = const1_rtx;
9420 break;
9421 case UNSPECV_WINDOW_END:
9422 if (XVECEXP (pattern, 0, 0) == x)
9423 return lab;
9424 break;
9425 case UNSPECV_CONST_END:
9426 return lab;
9427 default:
9428 break;
9432 return lab;
9435 /* Return true if it's possible to redirect BRANCH1 to the destination
9436 of an unconditional jump BRANCH2. We only want to do this if the
9437 resulting branch will have a short displacement. */
9438 static bool
9439 sh_can_follow_jump (const rtx_insn *branch1, const rtx_insn *branch2)
9441 /* Don't follow if BRANCH2 is possible to be a jump crossing between
9442 hot and cold partitions. */
9443 if (flag_reorder_blocks_and_partition
9444 && simplejump_p (branch2)
9445 && CROSSING_JUMP_P (branch2))
9446 return false;
9448 if (flag_expensive_optimizations && simplejump_p (branch2))
9450 rtx dest = XEXP (SET_SRC (single_set (branch2)), 0);
9451 rtx_insn *insn;
9452 int distance;
9454 for (distance = 0, insn = NEXT_INSN (branch1);
9455 insn && distance < 256;
9456 insn = PREV_INSN (insn))
9458 if (insn == dest)
9459 return true;
9460 else
9461 distance += get_attr_length (insn);
9463 for (distance = 0, insn = NEXT_INSN (branch1);
9464 insn && distance < 256;
9465 insn = NEXT_INSN (insn))
9467 if (insn == dest)
9468 return true;
9469 else
9470 distance += get_attr_length (insn);
9473 return false;
9476 /* Return nonzero if register old_reg can be renamed to register new_reg. */
9477 bool
9478 sh_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
9479 unsigned int new_reg)
9481 /* Interrupt functions can only use registers that have already been
9482 saved by the prologue, even if they would normally be
9483 call-clobbered. */
9484 if (sh_cfun_interrupt_handler_p () && !df_regs_ever_live_p (new_reg))
9485 return false;
9487 return true;
9490 /* Function to update the integer COST
9491 based on the relationship between INSN that is dependent on
9492 DEP_INSN through the dependence LINK. The default is to make no
9493 adjustment to COST. This can be used for example to specify to
9494 the scheduler that an output- or anti-dependence does not incur
9495 the same cost as a data-dependence. The return value should be
9496 the new value for COST. */
9497 static int
9498 sh_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,
9499 unsigned int)
9501 rtx reg, use_pat;
9503 if (dep_type == 0)
9505 if (recog_memoized (insn) < 0
9506 || recog_memoized (dep_insn) < 0)
9507 return cost;
9509 rtx dep_set = single_set (dep_insn);
9511 /* The latency that we specify in the scheduling description refers
9512 to the actual output, not to an auto-increment register; for that,
9513 the latency is one. */
9514 if (dep_set && MEM_P (SET_SRC (dep_set)) && cost > 1)
9516 rtx set = single_set (insn);
9518 if (set
9519 && !reg_mentioned_p (SET_DEST (dep_set), SET_SRC (set))
9520 && (!MEM_P (SET_DEST (set))
9521 || !reg_mentioned_p (SET_DEST (dep_set),
9522 XEXP (SET_DEST (set), 0))))
9523 cost = 1;
9525 /* The only input for a call that is timing-critical is the
9526 function's address. */
9527 if (CALL_P (insn))
9529 rtx call = get_call_rtx_from (insn);
9530 if (call
9531 /* sibcalli_thunk uses a symbol_ref in an unspec. */
9532 && (GET_CODE (XEXP (XEXP (call, 0), 0)) == UNSPEC
9533 || ! reg_set_p (XEXP (XEXP (call, 0), 0), dep_insn)))
9534 cost -= TARGET_SH4_300 ? 3 : 6;
9536 /* Likewise, the most timing critical input for an sfuncs call
9537 is the function address. However, sfuncs typically start
9538 using their arguments pretty quickly.
9539 Assume a four cycle delay for SH4 before they are needed.
9540 Cached ST40-300 calls are quicker, so assume only a one
9541 cycle delay there.
9542 ??? Maybe we should encode the delays till input registers
9543 are needed by sfuncs into the sfunc call insn. */
9544 /* All sfunc calls are parallels with at least four components.
9545 Exploit this to avoid unnecessary calls to sfunc_uses_reg. */
9546 else if (GET_CODE (PATTERN (insn)) == PARALLEL
9547 && XVECLEN (PATTERN (insn), 0) >= 4
9548 && (reg = sfunc_uses_reg (insn)))
9550 if (! reg_set_p (reg, dep_insn))
9551 cost -= TARGET_SH4_300 ? 1 : 4;
9553 if (TARGET_HARD_SH4 && !TARGET_SH4_300)
9555 attr_type dep_type = get_attr_type (dep_insn);
9556 attr_type type;
9557 if (dep_type == TYPE_FLOAD || dep_type == TYPE_PCFLOAD)
9558 cost--;
9559 else if ((dep_type == TYPE_LOAD_SI || dep_type == TYPE_PCLOAD_SI)
9560 && (type = get_attr_type (insn)) != TYPE_CALL
9561 && type != TYPE_SFUNC)
9562 cost--;
9563 /* When the preceding instruction loads the shift amount of
9564 the following SHAD/SHLD, the latency of the load is increased
9565 by 1 cycle. */
9566 if (get_attr_type (insn) == TYPE_DYN_SHIFT
9567 && get_attr_any_int_load (dep_insn) == ANY_INT_LOAD_YES
9568 && reg_overlap_mentioned_p (SET_DEST (dep_set),
9569 XEXP (SET_SRC (single_set (insn)),
9570 1)))
9571 cost++;
9572 /* When an LS group instruction with a latency of less than
9573 3 cycles is followed by a double-precision floating-point
9574 instruction, FIPR, or FTRV, the latency of the first
9575 instruction is increased to 3 cycles. */
9576 else if (cost < 3
9577 && get_attr_insn_class (dep_insn) == INSN_CLASS_LS_GROUP
9578 && get_attr_dfp_comp (insn) == DFP_COMP_YES)
9579 cost = 3;
9580 /* The lsw register of a double-precision computation is ready one
9581 cycle earlier. */
9582 else if (reload_completed
9583 && get_attr_dfp_comp (dep_insn) == DFP_COMP_YES
9584 && (use_pat = single_set (insn))
9585 && ! regno_use_in (REGNO (SET_DEST (single_set (dep_insn))),
9586 SET_SRC (use_pat)))
9587 cost -= 1;
9589 if (get_attr_any_fp_comp (dep_insn) == ANY_FP_COMP_YES
9590 && get_attr_late_fp_use (insn) == LATE_FP_USE_YES)
9591 cost -= 1;
9593 else if (TARGET_SH4_300)
9595 /* Stores need their input register two cycles later. */
9596 attr_type type;
9597 if (dep_set && cost >= 1
9598 && ((type = get_attr_type (insn)) == TYPE_STORE
9599 || type == TYPE_PSTORE
9600 || type == TYPE_FSTORE || type == TYPE_MAC_MEM))
9602 rtx set = single_set (insn);
9604 if (!reg_mentioned_p (SET_SRC (set), XEXP (SET_DEST (set), 0))
9605 && rtx_equal_p (SET_SRC (set), SET_DEST (dep_set)))
9607 cost -= 2;
9608 /* But don't reduce the cost below 1 if the address depends
9609 on a side effect of dep_insn. */
9610 if (cost < 1
9611 && modified_in_p (XEXP (SET_DEST (set), 0), dep_insn))
9612 cost = 1;
9617 /* An anti-dependence penalty of two applies if the first insn is a double
9618 precision fadd / fsub / fmul. */
9619 else if (!TARGET_SH4_300
9620 && dep_type == REG_DEP_ANTI
9621 && recog_memoized (dep_insn) >= 0
9622 && (get_attr_type (dep_insn) == TYPE_DFP_ARITH
9623 || get_attr_type (dep_insn) == TYPE_DFP_MUL)
9624 /* A lot of alleged anti-flow dependences are fake,
9625 so check this one is real. */
9626 && flow_dependent_p (dep_insn, insn))
9627 cost = 2;
9629 return cost;
9632 /* Check if INSN is flow-dependent on DEP_INSN. Can also be used to check
9633 if DEP_INSN is anti-flow dependent on INSN. */
9634 static bool
9635 flow_dependent_p (rtx insn, rtx dep_insn)
9637 rtx tmp = PATTERN (insn);
9639 note_stores (PATTERN (dep_insn), flow_dependent_p_1, &tmp);
9640 return tmp == NULL_RTX;
9643 /* A helper function for flow_dependent_p called through note_stores. */
9644 static void
9645 flow_dependent_p_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
9647 rtx * pinsn = (rtx *) data;
9649 if (*pinsn && reg_referenced_p (x, *pinsn))
9650 *pinsn = NULL_RTX;
9653 /* For use by sh_allocate_initial_value. Note that sh.md contains some
9654 'special function' patterns (type sfunc) that clobber pr, but that
9655 do not look like function calls to leaf_function_p. Hence we must
9656 do this extra check. */
9657 static int
9658 sh_pr_n_sets (void)
9660 return DF_REG_DEF_COUNT (PR_REG);
9663 /* Return where to allocate pseudo for a given hard register initial
9664 value. */
9665 static rtx
9666 sh_allocate_initial_value (rtx hard_reg)
9668 if (REGNO (hard_reg) == PR_REG)
9670 if (crtl->is_leaf && ! sh_pr_n_sets ())
9671 return hard_reg;
9672 else
9673 return gen_frame_mem (Pmode, return_address_pointer_rtx);
9676 return NULL_RTX;
9679 /* This function returns "2" to indicate dual issue for the SH4
9680 processor. To be used by the DFA pipeline description. */
9681 static int
9682 sh_issue_rate (void)
9684 if (TARGET_SUPERSCALAR)
9685 return 2;
9686 else
9687 return 1;
9690 /* Functions for ready queue reordering for sched1. */
9692 /* Get weight for mode for a set x. */
9693 static short
9694 find_set_regmode_weight (rtx x, machine_mode mode)
9696 if (GET_CODE (x) == CLOBBER && register_operand (SET_DEST (x), mode))
9697 return 1;
9698 if (GET_CODE (x) == SET && register_operand (SET_DEST (x), mode))
9700 if (REG_P (SET_DEST (x)))
9702 if (!reg_mentioned_p (SET_DEST (x), SET_SRC (x)))
9703 return 1;
9704 else
9705 return 0;
9707 return 1;
9709 return 0;
9712 /* Get regmode weight for insn. */
9713 static short
9714 find_insn_regmode_weight (rtx insn, machine_mode mode)
9716 /* Increment weight for each register born here. */
9717 rtx x = PATTERN (insn);
9718 short reg_weight = find_set_regmode_weight (x, mode);
9719 if (GET_CODE (x) == PARALLEL)
9721 int j;
9722 for (j = XVECLEN (x, 0) - 1; j >= 0; j--)
9724 x = XVECEXP (PATTERN (insn), 0, j);
9725 reg_weight += find_set_regmode_weight (x, mode);
9728 /* Decrement weight for each register that dies here. */
9729 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
9731 if (REG_NOTE_KIND (x) == REG_DEAD || REG_NOTE_KIND (x) == REG_UNUSED)
9733 rtx note = XEXP (x, 0);
9734 if (REG_P (note) && GET_MODE (note) == mode)
9735 reg_weight--;
9738 return reg_weight;
9741 /* Calculate regmode weights for all insns of a basic block. */
9742 static void
9743 find_regmode_weight (basic_block b, machine_mode mode)
9745 rtx_insn *insn, *next_tail, *head, *tail;
9747 get_ebb_head_tail (b, b, &head, &tail);
9748 next_tail = NEXT_INSN (tail);
9750 for (insn = head; insn != next_tail; insn = NEXT_INSN (insn))
9752 /* Handle register life information. */
9753 if (!INSN_P (insn))
9754 continue;
9756 if (mode == SFmode)
9757 INSN_REGMODE_WEIGHT (insn, mode) =
9758 find_insn_regmode_weight (insn, mode)
9759 + 2 * find_insn_regmode_weight (insn, DFmode);
9760 else if (mode == SImode)
9761 INSN_REGMODE_WEIGHT (insn, mode) =
9762 find_insn_regmode_weight (insn, mode)
9763 + 2 * find_insn_regmode_weight (insn, DImode);
9767 /* Comparison function for ready queue sorting. */
9768 static int
9769 rank_for_reorder (const void *x, const void *y)
9771 rtx_insn *tmp = *(rtx_insn * const *) y;
9772 rtx_insn *tmp2 = *(rtx_insn * const *) x;
9774 /* The insn in a schedule group should be issued the first. */
9775 if (SCHED_GROUP_P (tmp) != SCHED_GROUP_P (tmp2))
9776 return SCHED_GROUP_P (tmp2) ? 1 : -1;
9778 /* If insns are equally good, sort by INSN_LUID (original insn order), This
9779 minimizes instruction movement, thus minimizing sched's effect on
9780 register pressure. */
9781 return INSN_LUID (tmp) - INSN_LUID (tmp2);
9784 /* Resort the array A in which only element at index N may be out of order. */
9785 static void
9786 swap_reorder (rtx_insn **a, int n)
9788 rtx_insn *insn = a[n - 1];
9789 int i = n - 2;
9791 while (i >= 0 && rank_for_reorder (a + i, &insn) >= 0)
9793 a[i + 1] = a[i];
9794 i -= 1;
9796 a[i + 1] = insn;
9799 /* Sort the ready list by ascending priority. */
9800 static void
9801 ready_reorder (rtx_insn **ready, int nready)
9803 if (nready == 2)
9804 swap_reorder (ready, nready);
9805 else if (nready > 2)
9806 qsort (ready, nready, sizeof (rtx_insn *), rank_for_reorder);
9809 /* Count life regions of r0 for a block. */
9810 static int
9811 find_r0_life_regions (basic_block b)
9813 bool live;
9814 int set;
9815 int death = 0;
9817 if (REGNO_REG_SET_P (df_get_live_in (b), R0_REG))
9819 set = 1;
9820 live = true;
9822 else
9824 set = 0;
9825 live = false;
9828 rtx_insn* insn = BB_HEAD (b);
9829 rtx_insn* end = BB_END (b);
9830 rtx r0_reg = gen_rtx_REG (SImode, R0_REG);
9831 while (1)
9833 if (INSN_P (insn))
9835 if (find_regno_note (insn, REG_DEAD, R0_REG))
9837 death++;
9838 live = false;
9841 rtx pset;
9842 if (!live
9843 && (pset = single_set (insn))
9844 && reg_overlap_mentioned_p (r0_reg, SET_DEST (pset))
9845 && !find_regno_note (insn, REG_UNUSED, R0_REG))
9847 set++;
9848 live = true;
9851 if (insn == end)
9852 break;
9853 insn = NEXT_INSN (insn);
9855 return set - death;
9858 /* Calculate regmode weights for all insns of all basic block. */
9859 static void
9860 sh_md_init_global (FILE *dump ATTRIBUTE_UNUSED,
9861 int verbose ATTRIBUTE_UNUSED,
9862 int old_max_uid)
9864 basic_block b;
9866 regmode_weight[0] = (short *) xcalloc (old_max_uid, sizeof (short));
9867 regmode_weight[1] = (short *) xcalloc (old_max_uid, sizeof (short));
9868 r0_life_regions = 0;
9870 FOR_EACH_BB_REVERSE_FN (b, cfun)
9872 find_regmode_weight (b, SImode);
9873 find_regmode_weight (b, SFmode);
9874 if (!reload_completed)
9875 r0_life_regions += find_r0_life_regions (b);
9878 CURR_REGMODE_PRESSURE (SImode) = 0;
9879 CURR_REGMODE_PRESSURE (SFmode) = 0;
9882 /* Cleanup. */
9883 static void
9884 sh_md_finish_global (FILE *dump ATTRIBUTE_UNUSED,
9885 int verbose ATTRIBUTE_UNUSED)
9887 if (regmode_weight[0])
9889 free (regmode_weight[0]);
9890 regmode_weight[0] = NULL;
9892 if (regmode_weight[1])
9894 free (regmode_weight[1]);
9895 regmode_weight[1] = NULL;
9899 /* Cache the can_issue_more so that we can return it from reorder2. Also,
9900 keep count of register pressures on SImode and SFmode. */
9901 static int
9902 sh_variable_issue (FILE *dump ATTRIBUTE_UNUSED,
9903 int sched_verbose ATTRIBUTE_UNUSED,
9904 rtx_insn *insn,
9905 int can_issue_more)
9907 if (GET_CODE (PATTERN (insn)) != USE
9908 && GET_CODE (PATTERN (insn)) != CLOBBER)
9909 cached_can_issue_more = can_issue_more - 1;
9910 else
9911 cached_can_issue_more = can_issue_more;
9913 if (reload_completed)
9914 return cached_can_issue_more;
9916 CURR_REGMODE_PRESSURE (SImode) += INSN_REGMODE_WEIGHT (insn, SImode);
9917 CURR_REGMODE_PRESSURE (SFmode) += INSN_REGMODE_WEIGHT (insn, SFmode);
9919 return cached_can_issue_more;
9922 static void
9923 sh_md_init (FILE *dump ATTRIBUTE_UNUSED,
9924 int verbose ATTRIBUTE_UNUSED,
9925 int veclen ATTRIBUTE_UNUSED)
9927 CURR_REGMODE_PRESSURE (SImode) = 0;
9928 CURR_REGMODE_PRESSURE (SFmode) = 0;
9931 /* Some magic numbers. */
9932 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
9933 functions that already have high pressure on r0. */
9934 #define R0_MAX_LIFE_REGIONS 2
9935 /* Register Pressure thresholds for SImode and SFmode registers. */
9936 #define SIMODE_MAX_WEIGHT 5
9937 #define SFMODE_MAX_WEIGHT 10
9939 /* Return true if the pressure is high for MODE. */
9940 static bool
9941 high_pressure (machine_mode mode)
9943 /* Pressure on register r0 can lead to spill failures. so avoid sched1 for
9944 functions that already have high pressure on r0. */
9945 if (r0_life_regions >= R0_MAX_LIFE_REGIONS)
9946 return true;
9948 if (mode == SFmode)
9949 return (CURR_REGMODE_PRESSURE (SFmode) > SFMODE_MAX_WEIGHT);
9950 else
9951 return (CURR_REGMODE_PRESSURE (SImode) > SIMODE_MAX_WEIGHT);
9954 /* Reorder ready queue if register pressure is high. */
9955 static int
9956 sh_reorder (FILE *dump ATTRIBUTE_UNUSED,
9957 int sched_verbose ATTRIBUTE_UNUSED,
9958 rtx_insn **ready,
9959 int *n_readyp,
9960 int clock_var ATTRIBUTE_UNUSED)
9962 if (reload_completed)
9963 return sh_issue_rate ();
9965 if (high_pressure (SFmode) || high_pressure (SImode))
9967 ready_reorder (ready, *n_readyp);
9970 return sh_issue_rate ();
9973 /* Skip cycles if the current register pressure is high. */
9974 static int
9975 sh_reorder2 (FILE *dump ATTRIBUTE_UNUSED,
9976 int sched_verbose ATTRIBUTE_UNUSED,
9977 rtx_insn **ready ATTRIBUTE_UNUSED,
9978 int *n_readyp ATTRIBUTE_UNUSED,
9979 int clock_var ATTRIBUTE_UNUSED)
9981 if (reload_completed)
9982 return cached_can_issue_more;
9984 if (high_pressure(SFmode) || high_pressure (SImode))
9985 skip_cycles = 1;
9987 return cached_can_issue_more;
9990 /* Skip cycles without sorting the ready queue. This will move insn from
9991 Q->R. If this is the last cycle we are skipping; allow sorting of ready
9992 queue by sh_reorder. */
9994 /* Generally, skipping these many cycles are sufficient for all insns to move
9995 from Q -> R. */
9996 #define MAX_SKIPS 8
9998 static int
9999 sh_dfa_new_cycle (FILE *sched_dump ATTRIBUTE_UNUSED,
10000 int sched_verbose ATTRIBUTE_UNUSED,
10001 rtx_insn *insn ATTRIBUTE_UNUSED,
10002 int last_clock_var,
10003 int clock_var,
10004 int *sort_p)
10006 if (reload_completed)
10007 return 0;
10009 if (skip_cycles)
10011 if ((clock_var - last_clock_var) < MAX_SKIPS)
10013 *sort_p = 0;
10014 return 1;
10016 /* If this is the last cycle we are skipping, allow reordering of R. */
10017 if ((clock_var - last_clock_var) == MAX_SKIPS)
10019 *sort_p = 1;
10020 return 1;
10024 skip_cycles = 0;
10026 return 0;
10029 static bool
10030 sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
10032 return TARGET_HITACHI || sh_attr_renesas_p (record_type);
10036 On the SH1..SH4, the trampoline looks like
10037 2 0002 D202 mov.l l2,r2
10038 1 0000 D301 mov.l l1,r3
10039 3 0004 422B jmp @r2
10040 4 0006 0009 nop
10041 5 0008 00000000 l1: .long area
10042 6 000c 00000000 l2: .long function
10044 FDPIC needs a form that includes a function descriptor and
10045 code to load the GOT register:
10046 0 0000 00000000 .long l0
10047 1 0004 00000000 .long gotval
10048 2 0008 D302 l0: mov.l l1,r3
10049 3 000a D203 mov.l l2,r2
10050 4 000c 6122 mov.l @r2,r1
10051 5 000e 5C21 mov.l @(4,r2),r12
10052 6 0010 412B jmp @r1
10053 7 0012 0009 nop
10054 8 0014 00000000 l1: .long area
10055 9 0018 00000000 l2: .long function
10057 SH5 (compact) uses r1 instead of r3 for the static chain. */
10059 /* Emit insns to store a value at memory address + offset. */
10060 static void
10061 sh_emit_storesi (rtx addr, HOST_WIDE_INT offset, rtx value)
10063 gcc_assert ((offset & 3) == 0);
10064 emit_move_insn (offset == 0
10065 ? change_address (addr, SImode, NULL_RTX)
10066 : adjust_address (addr, SImode, offset), value);
10069 /* Emit insns to store w0 at addr + offset and w1 at addr + offset + 2. */
10070 static void
10071 sh_emit_storehi (rtx addr, HOST_WIDE_INT offset, uint16_t w0, uint16_t w1)
10073 sh_emit_storesi (addr, offset, gen_int_mode (TARGET_LITTLE_ENDIAN
10074 ? (w0 | (w1 << 16))
10075 : (w1 | (w0 << 16)), SImode));
10078 /* Emit RTL insns to initialize the variable parts of a trampoline.
10079 FNADDR is an RTX for the address of the function's pure code.
10080 CXT is an RTX for the static chain value for the function. */
10081 static void
10082 sh_trampoline_init (rtx tramp_mem, tree fndecl, rtx cxt)
10084 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
10085 rtx tramp = force_reg (Pmode, XEXP (tramp_mem, 0));
10087 if (TARGET_FDPIC)
10089 rtx a = force_reg (Pmode, plus_constant (Pmode, XEXP (tramp_mem, 0), 8));
10091 sh_emit_storesi (tramp_mem, 0, a);
10092 sh_emit_storesi (tramp_mem, 4, sh_get_fdpic_reg_initial_val ());
10094 sh_emit_storehi (tramp_mem, 8, 0xd302, 0xd203);
10095 sh_emit_storehi (tramp_mem, 12, 0x6122, 0x5c21);
10096 sh_emit_storehi (tramp_mem, 16, 0x412b, 0x0009);
10098 sh_emit_storesi (tramp_mem, 20, cxt);
10099 sh_emit_storesi (tramp_mem, 24, fnaddr);
10101 else
10103 sh_emit_storehi (tramp_mem, 0, 0xd202, 0xd301);
10104 sh_emit_storehi (tramp_mem, 4, 0x422b, 0x0009);
10106 sh_emit_storesi (tramp_mem, 8, cxt);
10107 sh_emit_storesi (tramp_mem, 12, fnaddr);
10109 if (TARGET_HARD_SH4)
10111 if (!TARGET_INLINE_IC_INVALIDATE
10112 || (!(TARGET_SH4A || TARGET_SH4_300) && TARGET_USERMODE))
10113 emit_library_call (function_symbol (NULL, "__ic_invalidate",
10114 FUNCTION_ORDINARY).sym,
10115 LCT_NORMAL, VOIDmode, tramp, SImode);
10116 else
10117 emit_insn (gen_ic_invalidate_line (tramp));
10121 /* On SH5, trampolines are SHmedia code, so add 1 to the address. */
10122 static rtx
10123 sh_trampoline_adjust_address (rtx tramp)
10125 return tramp;
10128 /* If PIC, we cannot make sibling calls to global functions
10129 because the PLT requires r12 to be live. */
10130 static bool
10131 sh_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
10133 return (1
10134 && ! sh_cfun_interrupt_handler_p ()
10135 && (! flag_pic || TARGET_FDPIC
10136 || (decl && ! (TREE_PUBLIC (decl) || DECL_WEAK (decl)))
10137 || (decl && DECL_VISIBILITY (decl) != VISIBILITY_DEFAULT)));
10140 /* Expand to appropriate sym*_label2reg for SYM and SIBCALL_P. */
10141 void
10142 sh_expand_sym_label2reg (rtx reg, rtx sym, rtx lab, bool sibcall_p)
10144 const_tree decl = SYMBOL_REF_DECL (sym);
10145 bool is_weak = (decl && DECL_P (decl) && DECL_WEAK (decl));
10147 if (!is_weak && SYMBOL_REF_LOCAL_P (sym))
10148 emit_insn (gen_sym_label2reg (reg, sym, lab));
10149 else if (sibcall_p && SYMBOL_REF_LOCAL_P (sym))
10150 emit_insn (gen_symPCREL_label2reg (reg, sym, lab));
10151 else
10152 emit_insn (gen_symPLT_label2reg (reg, sym, lab));
10155 /* Machine specific built-in functions. */
10157 struct builtin_description
10159 bool (* const is_enabled) (void);
10160 const enum insn_code icode;
10161 const char *const name;
10162 int signature;
10163 tree fndecl;
10166 /* This function can be used if there are any built-ins that are not for
10167 SHmedia. It's commented out to avoid the defined-but-unused warning. */
10168 static bool
10169 sh1_builtin_p (void)
10171 return TARGET_SH1;
10174 /* describe number and signedness of arguments; arg[0] == result
10175 (1: unsigned, 2: signed, 4: don't care, 8: pointer 0: no argument */
10176 /* 9: 64-bit pointer, 10: 32-bit pointer */
10177 static const char signature_args[][4] =
10179 #define SH_BLTIN_V2SI2 0
10180 { 4, 4 },
10181 #define SH_BLTIN_V4HI2 1
10182 { 4, 4 },
10183 #define SH_BLTIN_V2SI3 2
10184 { 4, 4, 4 },
10185 #define SH_BLTIN_V4HI3 3
10186 { 4, 4, 4 },
10187 #define SH_BLTIN_V8QI3 4
10188 { 4, 4, 4 },
10189 #define SH_BLTIN_MAC_HISI 5
10190 { 1, 4, 4, 1 },
10191 #define SH_BLTIN_SH_HI 6
10192 { 4, 4, 1 },
10193 #define SH_BLTIN_SH_SI 7
10194 { 4, 4, 1 },
10195 #define SH_BLTIN_V4HI2V2SI 8
10196 { 4, 4, 4 },
10197 #define SH_BLTIN_V4HI2V8QI 9
10198 { 4, 4, 4 },
10199 #define SH_BLTIN_SISF 10
10200 { 4, 2 },
10201 #define SH_BLTIN_LDUA_L 11
10202 { 2, 10 },
10203 #define SH_BLTIN_LDUA_Q 12
10204 { 1, 10 },
10205 #define SH_BLTIN_STUA_L 13
10206 { 0, 10, 2 },
10207 #define SH_BLTIN_STUA_Q 14
10208 { 0, 10, 1 },
10209 #define SH_BLTIN_LDUA_L64 15
10210 { 2, 9 },
10211 #define SH_BLTIN_LDUA_Q64 16
10212 { 1, 9 },
10213 #define SH_BLTIN_STUA_L64 17
10214 { 0, 9, 2 },
10215 #define SH_BLTIN_STUA_Q64 18
10216 { 0, 9, 1 },
10217 #define SH_BLTIN_NUM_SHARED_SIGNATURES 19
10218 #define SH_BLTIN_2 19
10219 #define SH_BLTIN_SU 19
10220 { 1, 2 },
10221 #define SH_BLTIN_3 20
10222 #define SH_BLTIN_SUS 20
10223 { 2, 2, 1 },
10224 #define SH_BLTIN_PSSV 21
10225 { 0, 8, 2, 2 },
10226 #define SH_BLTIN_XXUU 22
10227 #define SH_BLTIN_UUUU 22
10228 { 1, 1, 1, 1 },
10229 #define SH_BLTIN_PV 23
10230 { 0, 8 },
10231 #define SH_BLTIN_VP 24
10232 { 8, 0 },
10233 #define SH_BLTIN_UV 25
10234 { 1, 0 },
10235 #define SH_BLTIN_VU 26
10236 { 0, 1 },
10238 /* mcmv: operands considered unsigned. */
10239 /* mmulsum_wq, msad_ubq: result considered unsigned long long. */
10240 /* mperm: control value considered unsigned int. */
10241 /* mshalds, mshard, mshards, mshlld, mshlrd: shift count is unsigned int. */
10242 /* mshards_q: returns signed short. */
10243 /* nsb: takes long long arg, returns unsigned char. */
10244 static struct builtin_description bdesc[] =
10246 { sh1_builtin_p,
10247 CODE_FOR_sts_fpscr, "__builtin_sh_get_fpscr", SH_BLTIN_UV, 0 },
10248 { sh1_builtin_p,
10249 CODE_FOR_set_fpscr, "__builtin_sh_set_fpscr", SH_BLTIN_VU, 0 },
10252 static tree sh_builtin_get_fpscr;
10253 static tree sh_builtin_set_fpscr;
10255 static void
10256 sh_init_builtins (void)
10258 tree shared[SH_BLTIN_NUM_SHARED_SIGNATURES];
10259 memset (shared, 0, sizeof shared);
10261 for (unsigned int di = 0; di < ARRAY_SIZE (bdesc); ++di)
10263 builtin_description* d = &bdesc[di];
10265 if (!d->is_enabled ())
10266 continue;
10268 tree type, arg_type = NULL_TREE;
10269 int signature = d->signature;
10271 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES && shared[signature])
10272 type = shared[signature];
10273 else
10275 int has_result = signature_args[signature][0] != 0;
10276 tree args[3];
10278 if (! TARGET_FPU_ANY
10279 && FLOAT_MODE_P (insn_data[d->icode].operand[0].mode))
10280 continue;
10281 for (unsigned int i = 0; i < ARRAY_SIZE (args); i++)
10282 args[i] = NULL_TREE;
10283 for (int i = 3; ; i--)
10285 int arg = signature_args[signature][i];
10286 int opno = i - 1 + has_result;
10288 if (arg & 8)
10289 arg_type = ptr_type_node;
10290 else if (arg)
10291 arg_type = (*lang_hooks.types.type_for_mode)
10292 (insn_data[d->icode].operand[opno].mode, (arg & 1));
10293 else if (i)
10294 continue;
10295 else
10296 arg_type = void_type_node;
10297 if (i == 0)
10298 break;
10299 args[i-1] = arg_type;
10301 type = build_function_type_list (arg_type, args[0], args[1],
10302 args[2], NULL_TREE);
10303 if (signature < SH_BLTIN_NUM_SHARED_SIGNATURES)
10304 shared[signature] = type;
10306 d->fndecl =
10307 add_builtin_function (d->name, type, d - bdesc, BUILT_IN_MD,
10308 NULL, NULL_TREE);
10309 /* Recode {sts,set}_fpscr decls for sh_atomic_assign_expand_fenv. */
10310 if (d->icode == CODE_FOR_sts_fpscr)
10311 sh_builtin_get_fpscr = d->fndecl;
10312 else if (d->icode == CODE_FOR_set_fpscr)
10313 sh_builtin_set_fpscr = d->fndecl;
10317 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
10319 static void
10320 sh_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update)
10322 const unsigned SH_FE_INVALID = 64;
10323 const unsigned SH_FE_DIVBYZERO = 32;
10324 const unsigned SH_FE_OVERFLOW = 16;
10325 const unsigned SH_FE_UNDERFLOW = 8;
10326 const unsigned SH_FE_INEXACT = 4;
10327 const unsigned HOST_WIDE_INT SH_FE_ALL_EXCEPT = (SH_FE_INVALID
10328 | SH_FE_DIVBYZERO
10329 | SH_FE_OVERFLOW
10330 | SH_FE_UNDERFLOW
10331 | SH_FE_INEXACT);
10332 const unsigned HOST_WIDE_INT SH_FE_EXCEPT_SHIFT = 5;
10333 tree fenv_var, mask, ld_fenv, masked_fenv;
10334 tree new_fenv_var, reload_fenv, restore_fnenv;
10335 tree update_call, atomic_feraiseexcept, hold_fnclex;
10337 if (! TARGET_FPU_ANY)
10338 return;
10340 /* Generate the equivalent of :
10341 unsigned int fenv_var;
10342 fenv_var = __builtin_sh_get_fpscr ();
10344 unsigned int masked_fenv;
10345 masked_fenv = fenv_var & mask;
10347 __builtin_sh_set_fpscr (masked_fenv); */
10349 fenv_var = create_tmp_var_raw (unsigned_type_node);
10350 mask = build_int_cst (unsigned_type_node,
10351 ~((SH_FE_ALL_EXCEPT << SH_FE_EXCEPT_SHIFT)
10352 | SH_FE_ALL_EXCEPT));
10353 ld_fenv = build2 (MODIFY_EXPR, unsigned_type_node,
10354 fenv_var, build_call_expr (sh_builtin_get_fpscr, 0));
10355 masked_fenv = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_var, mask);
10356 hold_fnclex = build_call_expr (sh_builtin_set_fpscr, 1, masked_fenv);
10357 fenv_var = build4 (TARGET_EXPR, unsigned_type_node, fenv_var,
10358 build2 (COMPOUND_EXPR, void_type_node, masked_fenv,
10359 ld_fenv),
10360 NULL_TREE, NULL_TREE);
10361 *hold = build2 (COMPOUND_EXPR, void_type_node, fenv_var, hold_fnclex);
10363 /* Store the value of masked_fenv to clear the exceptions:
10364 __builtin_sh_set_fpscr (masked_fenv); */
10366 *clear = build_call_expr (sh_builtin_set_fpscr, 1, masked_fenv);
10368 /* Generate the equivalent of :
10369 unsigned int new_fenv_var;
10370 new_fenv_var = __builtin_sh_get_fpscr ();
10372 __builtin_sh_set_fpscr (fenv_var);
10374 __atomic_feraiseexcept (new_fenv_var); */
10376 new_fenv_var = create_tmp_var_raw (unsigned_type_node);
10377 reload_fenv = build2 (MODIFY_EXPR, unsigned_type_node, new_fenv_var,
10378 build_call_expr (sh_builtin_get_fpscr, 0));
10379 restore_fnenv = build_call_expr (sh_builtin_set_fpscr, 1, fenv_var);
10380 atomic_feraiseexcept = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT);
10381 update_call = build_call_expr (atomic_feraiseexcept, 1,
10382 fold_convert (integer_type_node,
10383 new_fenv_var));
10384 *update = build2 (COMPOUND_EXPR, void_type_node,
10385 build2 (COMPOUND_EXPR, void_type_node,
10386 reload_fenv, restore_fnenv), update_call);
10389 /* Implements target hook vector_mode_supported_p. */
10390 bool
10391 sh_vector_mode_supported_p (machine_mode mode ATTRIBUTE_UNUSED)
10393 return false;
10396 bool
10397 sh_frame_pointer_required (void)
10399 /* If needed override this in other tm.h files to cope with various OS
10400 lossage requiring a frame pointer. */
10401 if (SUBTARGET_FRAME_POINTER_REQUIRED)
10402 return true;
10404 if (crtl->profile)
10405 return true;
10407 return false;
10410 /* Implements target hook dwarf_calling_convention. Return an enum
10411 of dwarf_calling_convention. */
10413 sh_dwarf_calling_convention (const_tree func)
10415 if (sh_attr_renesas_p (func))
10416 return DW_CC_GNU_renesas_sh;
10418 return DW_CC_normal;
10421 /* Returns the sh builtin decl for CODE. */
10422 static tree
10423 sh_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED)
10425 if (code >= ARRAY_SIZE (bdesc))
10426 return error_mark_node;
10428 if (!bdesc[code].is_enabled ())
10429 return error_mark_node;
10431 return bdesc[code].fndecl;
10434 /* Expand an expression EXP that calls a built-in function,
10435 with result going to TARGET if that's convenient
10436 (and in mode MODE if that's convenient).
10437 SUBTARGET may be used as the target for computing one of EXP's operands.
10438 IGNORE is nonzero if the value is to be ignored. */
10439 static rtx
10440 sh_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
10441 machine_mode mode ATTRIBUTE_UNUSED, int ignore)
10443 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
10444 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
10445 const struct builtin_description *d = &bdesc[fcode];
10446 enum insn_code icode = d->icode;
10447 int signature = d->signature;
10448 int nop = 0;
10449 rtx op[4];
10451 if (signature_args[signature][0])
10453 if (ignore)
10454 return NULL_RTX;
10456 machine_mode tmode = insn_data[icode].operand[0].mode;
10457 if (! target || GET_MODE (target) != tmode
10458 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
10459 target = gen_reg_rtx (tmode);
10460 op[nop++] = target;
10462 else
10463 target = NULL_RTX;
10465 for (int i = 1; i <= 3; i++, nop++)
10467 if (! signature_args[signature][i])
10468 break;
10469 tree arg = CALL_EXPR_ARG (exp, i - 1);
10470 if (arg == error_mark_node)
10471 return const0_rtx;
10473 machine_mode opmode;
10474 tree optype;
10475 if (signature_args[signature][i] & 8)
10477 opmode = ptr_mode;
10478 optype = ptr_type_node;
10480 else
10482 opmode = insn_data[icode].operand[nop].mode;
10483 optype = (*lang_hooks.types.type_for_mode) (opmode, 0);
10486 machine_mode argmode = TYPE_MODE (TREE_TYPE (arg));
10487 if (argmode != opmode)
10488 arg = build1 (NOP_EXPR, optype, arg);
10489 op[nop] = expand_expr (arg, NULL_RTX, opmode, EXPAND_NORMAL);
10490 if (! (*insn_data[icode].operand[nop].predicate) (op[nop], opmode))
10491 op[nop] = copy_to_mode_reg (opmode, op[nop]);
10494 rtx pat = NULL_RTX;
10496 switch (nop)
10498 case 1:
10499 pat = (*insn_data[d->icode].genfun) (op[0]);
10500 break;
10501 case 2:
10502 pat = (*insn_data[d->icode].genfun) (op[0], op[1]);
10503 break;
10504 case 3:
10505 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2]);
10506 break;
10507 case 4:
10508 pat = (*insn_data[d->icode].genfun) (op[0], op[1], op[2], op[3]);
10509 break;
10510 default:
10511 gcc_unreachable ();
10513 if (! pat)
10514 return NULL_RTX;
10515 emit_insn (pat);
10516 return target;
10519 /* Implement TARGET_HARD_REGNO_NREGS. On the SH all but the XD regs are
10520 UNITS_PER_WORD bits wide. */
10522 static unsigned int
10523 sh_hard_regno_nregs (unsigned int regno, machine_mode mode)
10525 if (XD_REGISTER_P (regno))
10526 return CEIL (GET_MODE_SIZE (mode), 2 * UNITS_PER_WORD);
10527 return CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD);
10530 /* Implement TARGET_HARD_REGNO_MODE_OK.
10532 We can allow any mode in any general register. The special registers
10533 only allow SImode. Don't allow any mode in the PR.
10535 We cannot hold DCmode values in the XD registers because alter_reg
10536 handles subregs of them incorrectly. We could work around this by
10537 spacing the XD registers like the DR registers, but this would require
10538 additional memory in every compilation to hold larger register vectors.
10539 We could hold SFmode / SCmode values in XD registers, but that
10540 would require a tertiary reload when reloading from / to memory,
10541 and a secondary reload to reload from / to general regs; that
10542 seems to be a losing proposition.
10544 We want to allow TImode FP regs so that when V4SFmode is loaded as TImode,
10545 it won't be ferried through GP registers first. */
10546 static bool
10547 sh_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
10549 if (SPECIAL_REGISTER_P (regno))
10550 return mode == SImode;
10552 if (regno == FPUL_REG)
10553 return (mode == SImode || mode == SFmode);
10555 if (FP_REGISTER_P (regno) && mode == SFmode)
10556 return true;
10558 if (mode == V2SFmode)
10560 if (((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 2 == 0)
10561 || GENERAL_REGISTER_P (regno)))
10562 return true;
10563 else
10564 return false;
10567 if (mode == V4SFmode)
10569 if ((FP_REGISTER_P (regno) && (regno - FIRST_FP_REG) % 4 == 0)
10570 || GENERAL_REGISTER_P (regno))
10571 return true;
10572 else
10573 return false;
10576 if (mode == V16SFmode)
10577 return regno == FIRST_XD_REG;
10579 if (FP_REGISTER_P (regno))
10581 if (mode == SFmode
10582 || mode == SImode
10583 || ((TARGET_SH2E) && mode == SCmode)
10584 || (((TARGET_FPU_DOUBLE && mode == DFmode) || mode == DCmode)
10585 && ((regno - FIRST_FP_REG) & 1) == 0)
10586 || (TARGET_SH4 && mode == TImode
10587 && ((regno - FIRST_FP_REG) & 3) == 0))
10588 return true;
10589 else
10590 return false;
10593 if (XD_REGISTER_P (regno))
10594 return mode == DFmode;
10596 if (regno == PR_REG)
10597 return mode == SImode;
10599 if (regno == FPSCR_REG)
10600 return mode == SImode;
10602 return true;
10605 /* Implement TARGET_MODES_TIEABLE_P.
10607 If TARGET_HARD_REGNO_MODE_OK could produce different values for MODE1
10608 and MODE2, for any hard reg, then this must be false for correct output.
10609 That's the case for xd registers: we don't hold SFmode values in
10610 them, so we can't tie an SFmode pseudos with one in another
10611 floating-point mode. */
10613 static bool
10614 sh_modes_tieable_p (machine_mode mode1, machine_mode mode2)
10616 return (mode1 == mode2
10617 || (GET_MODE_CLASS (mode1) == GET_MODE_CLASS (mode2)
10618 && (mode1 != SFmode && mode2 != SFmode)));
10621 /* Specify the modes required to caller save a given hard regno.
10622 choose_hard_reg_mode chooses mode based on TARGET_HARD_REGNO_MODE_OK
10623 and returns ?Imode for float regs when sh_hard_regno_mode_ok
10624 permits integer modes on them. That makes LRA's split process
10625 unhappy. See PR55212.
10627 machine_mode
10628 sh_hard_regno_caller_save_mode (unsigned int regno, unsigned int nregs,
10629 machine_mode mode)
10631 if (FP_REGISTER_P (regno)
10632 && (mode == SFmode
10633 || mode == SCmode
10634 || ((mode == DFmode || mode == DCmode)
10635 && ((regno - FIRST_FP_REG) & 1) == 0)))
10636 return mode;
10638 return choose_hard_reg_mode (regno, nregs, false);
10641 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
10642 static bool
10643 sh_can_change_mode_class (machine_mode from, machine_mode to,
10644 reg_class_t rclass)
10646 /* We want to enable the use of SUBREGs as a means to
10647 VEC_SELECT a single element of a vector. */
10649 /* This effectively disallows using GENERAL_REGS for SFmode vector subregs.
10650 This can be problematic when SFmode vector subregs need to be accessed
10651 on the stack with displacement addressing, as it happens with -O0.
10652 Thus we disallow the mode change for -O0. */
10653 if (to == SFmode && VECTOR_MODE_P (from) && GET_MODE_INNER (from) == SFmode)
10654 return optimize ? !reg_classes_intersect_p (GENERAL_REGS, rclass) : true;
10656 if (GET_MODE_SIZE (from) != GET_MODE_SIZE (to))
10658 if (TARGET_LITTLE_ENDIAN)
10660 if (GET_MODE_SIZE (to) < 8 || GET_MODE_SIZE (from) < 8)
10661 return !reg_classes_intersect_p (DF_REGS, rclass);
10663 else
10665 if (GET_MODE_SIZE (from) < 8)
10666 return !reg_classes_intersect_p (DF_REGS, rclass);
10669 return true;
10672 /* Return true if registers in machine mode MODE will likely be
10673 allocated to registers in small register classes. */
10674 bool
10675 sh_small_register_classes_for_mode_p (machine_mode mode ATTRIBUTE_UNUSED)
10677 return true;
10680 /* If ADDRESS refers to a CODE_LABEL, add NUSES to the number of times
10681 that label is used. */
10682 void
10683 sh_mark_label (rtx address, int nuses)
10685 if (GOTOFF_P (address))
10687 /* Extract the label or symbol. */
10688 address = XEXP (address, 0);
10689 if (GET_CODE (address) == PLUS)
10690 address = XEXP (address, 0);
10691 address = XVECEXP (address, 0, 0);
10693 if (GET_CODE (address) == LABEL_REF
10694 && LABEL_P (XEXP (address, 0)))
10695 LABEL_NUSES (XEXP (address, 0)) += nuses;
10698 /* Compute extra cost of moving data between one register class
10699 and another.
10701 If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass
10702 uses this information. Hence, the general register <-> floating point
10703 register information here is not used for SFmode. */
10704 static int
10705 sh_register_move_cost (machine_mode mode,
10706 reg_class_t srcclass, reg_class_t dstclass)
10708 if (dstclass == T_REGS || dstclass == PR_REGS)
10709 return 10;
10711 if (dstclass == MAC_REGS && srcclass == MAC_REGS)
10712 return 4;
10714 if (mode == SImode && TARGET_FMOVD
10715 && REGCLASS_HAS_FP_REG (srcclass)
10716 && REGCLASS_HAS_FP_REG (dstclass))
10717 return 4;
10719 if (REGCLASS_HAS_FP_REG (dstclass) && srcclass == T_REGS)
10720 return ((TARGET_HARD_SH4 && !optimize_size) ? 10 : 7);
10722 if ((REGCLASS_HAS_FP_REG (dstclass) && srcclass == MAC_REGS)
10723 || (dstclass == MAC_REGS && REGCLASS_HAS_FP_REG (srcclass)))
10724 return 9;
10726 if ((REGCLASS_HAS_FP_REG (dstclass)
10727 && REGCLASS_HAS_GENERAL_REG (srcclass))
10728 || (REGCLASS_HAS_GENERAL_REG (dstclass)
10729 && REGCLASS_HAS_FP_REG (srcclass)))
10731 /* Discourage trying to use fp regs for a pointer. This also
10732 discourages fp regs with SImode because Pmode is an alias
10733 of SImode on this target. See PR target/48596. */
10734 int addend = (mode == Pmode) ? 40 : 0;
10736 return ((TARGET_FMOVD ? 8 : 12) + addend)
10737 * ((GET_MODE_SIZE (mode) + 7) / 8U);
10740 if ((dstclass == FPUL_REGS
10741 && REGCLASS_HAS_GENERAL_REG (srcclass))
10742 || (srcclass == FPUL_REGS
10743 && REGCLASS_HAS_GENERAL_REG (dstclass)))
10744 return 5;
10746 if ((dstclass == FPUL_REGS
10747 && (srcclass == PR_REGS || srcclass == MAC_REGS || srcclass == T_REGS))
10748 || (srcclass == FPUL_REGS
10749 && (dstclass == PR_REGS || dstclass == MAC_REGS)))
10750 return 7;
10752 if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
10753 || (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
10754 return 4;
10756 if (TARGET_FMOVD
10757 && ! REGCLASS_HAS_GENERAL_REG (srcclass)
10758 && ! REGCLASS_HAS_GENERAL_REG (dstclass))
10759 return 2 * ((GET_MODE_SIZE (mode) + 7) / 8U);
10761 return 2 * ((GET_MODE_SIZE (mode) + 3) / 4U);
10764 static rtx
10765 emit_load_ptr (rtx reg, rtx addr)
10767 rtx mem = gen_const_mem (ptr_mode, addr);
10769 if (Pmode != ptr_mode)
10770 mem = gen_rtx_SIGN_EXTEND (Pmode, mem);
10771 return emit_move_insn (reg, mem);
10774 static void
10775 sh_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
10776 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
10777 tree function)
10779 CUMULATIVE_ARGS cum;
10780 int structure_value_byref = 0;
10781 rtx this_rtx, this_value, sibcall, funexp;
10782 rtx_insn *insns;
10783 tree funtype = TREE_TYPE (function);
10784 int simple_add = CONST_OK_FOR_ADD (delta);
10785 int did_load = 0;
10786 rtx scratch0, scratch1, scratch2;
10788 reload_completed = 1;
10789 epilogue_completed = 1;
10790 crtl->uses_only_leaf_regs = 1;
10792 emit_note (NOTE_INSN_PROLOGUE_END);
10794 /* Find the "this" pointer. We have such a wide range of ABIs for the
10795 SH that it's best to do this completely machine independently.
10796 "this" is passed as first argument, unless a structure return pointer
10797 comes first, in which case "this" comes second. */
10798 INIT_CUMULATIVE_ARGS (cum, funtype, NULL_RTX, 0, 1);
10799 #ifndef PCC_STATIC_STRUCT_RETURN
10800 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
10801 structure_value_byref = 1;
10802 #endif /* not PCC_STATIC_STRUCT_RETURN */
10803 if (structure_value_byref && sh_struct_value_rtx (function, 0) == 0)
10805 tree ptype = build_pointer_type (TREE_TYPE (funtype));
10807 sh_function_arg_advance (pack_cumulative_args (&cum), Pmode, ptype, true);
10809 this_rtx
10810 = sh_function_arg (pack_cumulative_args (&cum), Pmode, ptr_type_node, true);
10812 /* For SHcompact, we only have r0 for a scratch register: r1 is the
10813 static chain pointer (even if you can't have nested virtual functions
10814 right now, someone might implement them sometime), and the rest of the
10815 registers are used for argument passing, are callee-saved, or reserved. */
10816 /* We need to check call_used_regs / fixed_regs in case -fcall_saved-reg /
10817 -ffixed-reg has been used. */
10818 if (! call_used_regs[0] || fixed_regs[0])
10819 error ("r0 needs to be available as a call-clobbered register");
10820 scratch0 = scratch1 = scratch2 = gen_rtx_REG (Pmode, 0);
10823 if (call_used_regs[1] && ! fixed_regs[1])
10824 scratch1 = gen_rtx_REG (ptr_mode, 1);
10825 /* N.B., if not TARGET_HITACHI, register 2 is used to pass the pointer
10826 pointing where to return struct values. */
10827 if (call_used_regs[3] && ! fixed_regs[3])
10828 scratch2 = gen_rtx_REG (Pmode, 3);
10831 this_value = plus_constant (Pmode, this_rtx, delta);
10832 if (vcall_offset
10833 && (simple_add || scratch0 != scratch1)
10834 && strict_memory_address_p (ptr_mode, this_value))
10836 emit_load_ptr (scratch0, this_value);
10837 did_load = 1;
10840 if (!delta)
10841 ; /* Do nothing. */
10842 else if (simple_add)
10843 emit_move_insn (this_rtx, this_value);
10844 else
10846 emit_move_insn (scratch1, GEN_INT (delta));
10847 emit_insn (gen_add2_insn (this_rtx, scratch1));
10850 if (vcall_offset)
10852 rtx offset_addr;
10854 if (!did_load)
10855 emit_load_ptr (scratch0, this_rtx);
10857 offset_addr = plus_constant (Pmode, scratch0, vcall_offset);
10858 if (strict_memory_address_p (ptr_mode, offset_addr))
10859 ; /* Do nothing. */
10860 else if (scratch0 != scratch1)
10862 /* scratch0 != scratch1, and we have indexed loads. Get better
10863 schedule by loading the offset into r1 and using an indexed
10864 load - then the load of r1 can issue before the load from
10865 (this_rtx + delta) finishes. */
10866 emit_move_insn (scratch1, GEN_INT (vcall_offset));
10867 offset_addr = gen_rtx_PLUS (Pmode, scratch0, scratch1);
10869 else if (CONST_OK_FOR_ADD (vcall_offset))
10871 emit_insn (gen_add2_insn (scratch0, GEN_INT (vcall_offset)));
10872 offset_addr = scratch0;
10874 else if (scratch0 != scratch1)
10876 emit_move_insn (scratch1, GEN_INT (vcall_offset));
10877 emit_insn (gen_add2_insn (scratch0, scratch1));
10878 offset_addr = scratch0;
10880 else
10881 gcc_unreachable (); /* FIXME */
10882 emit_load_ptr (scratch0, offset_addr);
10884 if (Pmode != ptr_mode)
10885 scratch0 = gen_rtx_TRUNCATE (ptr_mode, scratch0);
10886 emit_insn (gen_add2_insn (this_rtx, scratch0));
10889 /* Generate a tail call to the target function. */
10890 if (! TREE_USED (function))
10892 assemble_external (function);
10893 TREE_USED (function) = 1;
10895 funexp = XEXP (DECL_RTL (function), 0);
10896 /* If the function is overridden, so is the thunk, hence we don't
10897 need GOT addressing even if this is a public symbol. */
10898 #if 0
10899 if (TARGET_SH1 && ! flag_weak)
10900 sibcall = gen_sibcalli_thunk (funexp, const0_rtx);
10901 else
10902 #endif
10903 if (TARGET_SH2 && flag_pic)
10905 if (TARGET_FDPIC)
10907 sibcall = gen_sibcall_pcrel_fdpic (funexp, const0_rtx);
10908 XEXP (XVECEXP (sibcall, 0, 3), 0) = scratch2;
10910 else
10912 sibcall = gen_sibcall_pcrel (funexp, const0_rtx);
10913 XEXP (XVECEXP (sibcall, 0, 2), 0) = scratch2;
10916 else
10918 emit_move_insn (scratch2, funexp);
10919 funexp = gen_rtx_MEM (FUNCTION_MODE, scratch2);
10920 sibcall = gen_sibcall (funexp, const0_rtx, NULL_RTX);
10922 sibcall = emit_call_insn (sibcall);
10923 SIBLING_CALL_P (sibcall) = 1;
10924 use_reg (&CALL_INSN_FUNCTION_USAGE (sibcall), this_rtx);
10925 emit_barrier ();
10927 /* Run just enough of rest_of_compilation to do scheduling and get
10928 the insns emitted. Note that use_thunk calls
10929 assemble_start_function and assemble_end_function. */
10931 insns = get_insns ();
10933 if (optimize > 0)
10935 if (! cfun->cfg)
10936 init_flow (cfun);
10937 split_all_insns_noflow ();
10940 sh_reorg ();
10941 shorten_branches (insns);
10942 final_start_function (insns, file, 1);
10943 final (insns, file, 1);
10944 final_end_function ();
10946 reload_completed = 0;
10947 epilogue_completed = 0;
10950 /* Return an RTX pair for the address and call site label of a function
10951 NAME of kind KIND, placing the result in TARGET if not NULL. For
10952 SFUNC_STATIC, if FDPIC, the LAB member of result will be set to
10953 (const_int 0) if jsr should be used, or a label_ref if bsrf should
10954 be used. For FDPIC, both SFUNC_GOT and SFUNC_STATIC will return the
10955 address of the function itself, not a function descriptor, so they
10956 can only be used with functions not using the FDPIC register that
10957 are known to be called directory without a PLT entry. */
10959 function_symbol_result
10960 function_symbol (rtx target, const char *name, sh_function_kind kind)
10962 /* If this is not an ordinary function, the name usually comes from a
10963 string literal or an sprintf buffer. Make sure we use the same
10964 string consistently, so that cse will be able to unify address loads. */
10965 if (kind != FUNCTION_ORDINARY)
10966 name = IDENTIFIER_POINTER (get_identifier (name));
10967 rtx sym = gen_rtx_SYMBOL_REF (Pmode, name);
10968 rtx lab = const0_rtx;
10969 SYMBOL_REF_FLAGS (sym) = SYMBOL_FLAG_FUNCTION;
10970 if (flag_pic)
10971 switch (kind)
10973 case FUNCTION_ORDINARY:
10974 break;
10975 case SFUNC_GOT:
10977 rtx reg = target ? target : gen_reg_rtx (Pmode);
10979 emit_insn (gen_symGOT2reg (reg, sym));
10980 sym = reg;
10981 break;
10983 case SFUNC_STATIC:
10985 rtx reg = target ? target : gen_reg_rtx (Pmode);
10987 if (TARGET_FDPIC)
10989 /* We use PC-relative calls, since GOTOFF can only refer
10990 to writable data. This works along with sh_sfunc_call. */
10991 lab = PATTERN (gen_call_site ());
10992 emit_insn (gen_sym_label2reg (reg, sym, lab));
10994 else
10996 /* ??? To allow cse to work, we use GOTOFF relocations.
10997 we could add combiner patterns to transform this into
10998 straight pc-relative calls with sym2PIC / bsrf when
10999 label load and function call are still 1:1 and in the
11000 same basic block during combine. */
11001 emit_insn (gen_symGOTOFF2reg (reg, sym));
11004 sym = reg;
11005 break;
11008 if (target && sym != target)
11010 emit_move_insn (target, sym);
11011 return function_symbol_result (target, lab);
11013 return function_symbol_result (sym, lab);
11016 /* Find the number of the first general purpose register in S that
11017 is not set. */
11018 static int
11019 scavenge_reg (HARD_REG_SET *s)
11021 for (int r = FIRST_GENERAL_REG; r <= LAST_GENERAL_REG; r++)
11022 if (TEST_HARD_REG_BIT (*s, r))
11023 return r;
11024 return -1;
11028 sh_get_pr_initial_val (void)
11030 /* If we haven't finished rtl generation, there might be a nonlocal label
11031 that we haven't seen yet.
11032 ??? get_hard_reg_initial_val fails if it is called after register
11033 allocation has started, unless it has been called before for the
11034 same register. And even then, we end in trouble if we didn't use
11035 the register in the same basic block before. So call
11036 get_hard_reg_initial_val now and wrap it in an unspec if we might
11037 need to replace it. */
11038 /* ??? We also must do this for TARGET_SH1 in general, because otherwise
11039 combine can put the pseudo returned by get_hard_reg_initial_val into
11040 instructions that need a general purpose registers, which will fail to
11041 be recognized when the pseudo becomes allocated to PR. */
11042 rtx val = get_hard_reg_initial_val (Pmode, PR_REG);
11043 return gen_rtx_UNSPEC (SImode, gen_rtvec (1, val), UNSPEC_RA);
11046 bool
11047 sh_expand_t_scc (rtx operands[])
11049 enum rtx_code code = GET_CODE (operands[1]);
11050 rtx target = operands[0];
11051 rtx op0 = operands[2];
11052 rtx op1 = operands[3];
11053 rtx result = target;
11055 if (!REG_P (op0) || REGNO (op0) != T_REG
11056 || !CONST_INT_P (op1))
11057 return false;
11058 if (!REG_P (result))
11059 result = gen_reg_rtx (SImode);
11060 HOST_WIDE_INT val = INTVAL (op1);
11061 if ((code == EQ && val == 1) || (code == NE && val == 0))
11062 emit_insn (gen_movt (result, get_t_reg_rtx ()));
11063 else if ((code == EQ && val == 0) || (code == NE && val == 1))
11064 emit_insn (gen_movnegt (result, get_t_reg_rtx ()));
11065 else if (code == EQ || code == NE)
11066 emit_insn (gen_move_insn (result, GEN_INT (code == NE)));
11067 else
11068 return false;
11069 if (result != target)
11070 emit_move_insn (target, result);
11071 return true;
11074 /* INSN is an sfunc; return the rtx that describes the address used. */
11075 static rtx
11076 extract_sfunc_addr (rtx insn)
11078 rtx pattern = PATTERN (insn);
11079 const int len = XVECLEN (pattern, 0);
11080 for (int i = 0; i < len; i++)
11082 rtx part = XVECEXP (pattern, 0, i);
11083 if (GET_CODE (part) == USE && GET_MODE (XEXP (part, 0)) == Pmode
11084 && GENERAL_REGISTER_P (true_regnum (XEXP (part, 0))))
11085 return XEXP (part, 0);
11087 gcc_assert (GET_CODE (XVECEXP (pattern, 0, 0)) == UNSPEC_VOLATILE);
11088 return XVECEXP (XVECEXP (pattern, 0, 0), 0, 1);
11091 /* Verify that the register in use_sfunc_addr still agrees with the address
11092 used in the sfunc. This prevents fill_slots_from_thread from changing
11093 use_sfunc_addr.
11094 INSN is the use_sfunc_addr instruction, and REG is the register it
11095 guards. */
11096 bool
11097 check_use_sfunc_addr (rtx_insn *insn, rtx reg)
11099 /* Search for the sfunc. It should really come right after INSN. */
11100 while ((insn = NEXT_INSN (insn)))
11102 if (LABEL_P (insn) || JUMP_P (insn))
11103 break;
11104 if (! INSN_P (insn))
11105 continue;
11107 if (rtx_sequence *seq = dyn_cast<rtx_sequence *> (PATTERN (insn)))
11108 insn = seq->insn (0);
11109 if (GET_CODE (PATTERN (insn)) != PARALLEL
11110 || get_attr_type (insn) != TYPE_SFUNC)
11111 continue;
11112 return rtx_equal_p (extract_sfunc_addr (insn), reg);
11114 gcc_unreachable ();
11117 /* This function returns a constant rtx that represents 2**15 / pi in
11118 SFmode. It's used to scale a fixed-point signed 16.16-bit fraction
11119 of a full circle back to an SFmode value, i.e. 0x10000 maps to 2*pi. */
11120 static GTY(()) rtx sh_fsca_sf2int_rtx;
11123 sh_fsca_sf2int (void)
11125 if (! sh_fsca_sf2int_rtx)
11127 REAL_VALUE_TYPE rv;
11129 real_from_string (&rv, "10430.378350470453");
11130 sh_fsca_sf2int_rtx = const_double_from_real_value (rv, SFmode);
11133 return sh_fsca_sf2int_rtx;
11136 /* This function returns a constant rtx that represents pi / 2**15 in
11137 SFmode. It's used to scale SFmode angles, in radians, to a
11138 fixed-point signed 16.16-bit fraction of a full circle, i.e. 2*pi
11139 maps to 0x10000. */
11140 static GTY(()) rtx sh_fsca_int2sf_rtx;
11143 sh_fsca_int2sf (void)
11145 if (! sh_fsca_int2sf_rtx)
11147 REAL_VALUE_TYPE rv;
11149 real_from_string (&rv, "9.587379924285257e-5");
11150 sh_fsca_int2sf_rtx = const_double_from_real_value (rv, SFmode);
11153 return sh_fsca_int2sf_rtx;
11156 /* Initialize the CUMULATIVE_ARGS structure. */
11157 void
11158 sh_init_cumulative_args (CUMULATIVE_ARGS * pcum,
11159 tree fntype,
11160 rtx libname ATTRIBUTE_UNUSED,
11161 tree fndecl,
11162 signed int n_named_args,
11163 machine_mode mode)
11165 pcum->arg_count [(int) SH_ARG_FLOAT] = 0;
11166 pcum->free_single_fp_reg = 0;
11167 pcum->outgoing = n_named_args != -1;
11169 /* FIXME: Should we check TARGET_HITACHI here ??? */
11170 pcum->renesas_abi = sh_attr_renesas_p (fntype);
11172 if (fntype)
11174 pcum->force_mem = ((TARGET_HITACHI || pcum->renesas_abi)
11175 && aggregate_value_p (TREE_TYPE (fntype), fndecl));
11176 pcum->prototype_p = prototype_p (fntype);
11177 pcum->arg_count [(int) SH_ARG_INT] = false;
11179 else
11181 pcum->arg_count [(int) SH_ARG_INT] = 0;
11182 pcum->prototype_p = false;
11183 if (mode != VOIDmode)
11185 /* If the default ABI is the Renesas ABI then all library
11186 calls must assume that the library will be using the
11187 Renesas ABI. So if the function would return its result
11188 in memory then we must force the address of this memory
11189 block onto the stack. Ideally we would like to call
11190 targetm.calls.return_in_memory() here but we do not have
11191 the TYPE or the FNDECL available so we synthesize the
11192 contents of that function as best we can. */
11193 pcum->force_mem =
11194 (TARGET_DEFAULT & MASK_HITACHI)
11195 && (mode == BLKmode
11196 || (GET_MODE_SIZE (mode) > 4
11197 && !(mode == DFmode
11198 && TARGET_FPU_DOUBLE)));
11200 else
11201 pcum->force_mem = false;
11206 sh_gen_truncate (machine_mode mode, rtx x, int need_sign_ext)
11208 enum rtx_code code = TRUNCATE;
11210 if (GET_CODE (x) == ZERO_EXTEND || GET_CODE (x) == SIGN_EXTEND)
11212 rtx inner = XEXP (x, 0);
11213 machine_mode inner_mode = GET_MODE (inner);
11215 if (inner_mode == mode)
11216 return inner;
11217 else if (GET_MODE_SIZE (inner_mode) >= GET_MODE_SIZE (mode))
11218 x = inner;
11219 else if (GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (mode)
11220 && (! need_sign_ext || GET_CODE (x) == SIGN_EXTEND))
11222 code = GET_CODE (x);
11223 x = inner;
11226 return gen_rtx_fmt_e (code, mode, x);
11229 /* Load and store depend on the highpart of the address. However,
11230 set_attr_alternative does not give well-defined results before reload,
11231 so we must look at the rtl ourselves to see if any of the feeding
11232 registers is used in a memref.
11234 Return true iff INSN contains a MEM. */
11235 bool
11236 sh_contains_memref_p (rtx insn)
11238 subrtx_iterator::array_type array;
11239 FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST)
11240 if (MEM_P (*iter))
11241 return true;
11242 return false;
11245 /* Return true iff INSN loads a banked register. */
11246 bool
11247 sh_loads_bankedreg_p (rtx insn)
11249 if (GET_CODE (PATTERN (insn)) == SET)
11251 rtx op = SET_DEST (PATTERN(insn));
11252 if (REG_P (op) && BANKED_REGISTER_P (REGNO (op)))
11253 return true;
11256 return false;
11259 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
11260 static reg_class_t
11261 sh_preferred_reload_class (rtx x ATTRIBUTE_UNUSED, reg_class_t rclass)
11263 return rclass;
11266 /* Implement TARGET_SECONDARY_RELOAD. */
11267 static reg_class_t
11268 sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
11269 machine_mode mode, secondary_reload_info *sri)
11271 enum reg_class rclass = (enum reg_class) rclass_i;
11273 if (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS
11274 && REG_P (XEXP (XEXP (x, 0), 0))
11275 && REGNO (XEXP (XEXP (x, 0), 0)) == GBR_REG)
11276 return rclass == R0_REGS ? NO_REGS : R0_REGS;
11278 if (MEM_P (x) && REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) == GBR_REG)
11279 return rclass == R0_REGS ? NO_REGS : R0_REGS;
11281 if (REG_P (x) && REGNO (x) == GBR_REG)
11282 return NO_REGS;
11284 if (in_p)
11286 if (REGCLASS_HAS_FP_REG (rclass)
11287 && immediate_operand ((x), mode)
11288 && ! ((fp_zero_operand (x) || fp_one_operand (x)) && mode == SFmode))
11289 switch (mode)
11291 case E_SFmode:
11292 sri->icode = CODE_FOR_reload_insf__frn;
11293 return NO_REGS;
11294 case E_DFmode:
11295 sri->icode = CODE_FOR_reload_indf__frn;
11296 return NO_REGS;
11297 case E_SImode:
11298 /* ??? If we knew that we are in the appropriate mode -
11299 single precision - we could use a reload pattern directly. */
11300 return FPUL_REGS;
11301 default:
11302 abort ();
11304 if (rclass == FPUL_REGS
11305 && ((REG_P (x) && (REGNO (x) == MACL_REG || REGNO (x) == MACH_REG
11306 || REGNO (x) == T_REG))
11307 || GET_CODE (x) == PLUS))
11308 return GENERAL_REGS;
11309 if (rclass == FPUL_REGS && immediate_operand (x, mode))
11311 if (satisfies_constraint_I08 (x) || fp_zero_operand (x))
11312 return GENERAL_REGS;
11313 else if (mode == SFmode)
11314 return FP_REGS;
11315 sri->icode = CODE_FOR_reload_insi__i_fpul;
11316 return NO_REGS;
11318 if (rclass == FPSCR_REGS
11319 && ((REG_P (x) && REGNO (x) >= FIRST_PSEUDO_REGISTER)
11320 || (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PLUS)))
11321 return GENERAL_REGS;
11322 } /* end of input-only processing. */
11324 if (((REGCLASS_HAS_FP_REG (rclass)
11325 && (REG_P (x)
11326 && (GENERAL_OR_AP_REGISTER_P (REGNO (x))
11327 || (FP_REGISTER_P (REGNO (x)) && mode == SImode
11328 && TARGET_FMOVD))))
11329 || (REGCLASS_HAS_GENERAL_REG (rclass)
11330 && REG_P (x)
11331 && FP_REGISTER_P (REGNO (x))))
11332 && (mode == SFmode || mode == SImode))
11333 return FPUL_REGS;
11334 if ((rclass == FPUL_REGS
11335 || (REGCLASS_HAS_FP_REG (rclass) && mode == SImode))
11336 && (MEM_P (x)
11337 || (REG_P (x)
11338 && (REGNO (x) >= FIRST_PSEUDO_REGISTER
11339 || REGNO (x) == T_REG
11340 || system_reg_operand (x, VOIDmode)))))
11342 if (rclass == FPUL_REGS)
11343 return GENERAL_REGS;
11344 return NO_REGS; // LRA wants NO_REGS here, it used to be FPUL_REGS;
11347 if ((rclass == MAC_REGS || rclass == PR_REGS)
11348 && REG_P (x) && ! GENERAL_REGISTER_P (REGNO (x))
11349 && rclass != REGNO_REG_CLASS (REGNO (x)))
11350 return GENERAL_REGS;
11352 /* If here fall back to loading FPUL register through general registers.
11353 This case can happen when movsi_ie insn is picked initially to
11354 load/store the FPUL register from/to another register, and then the
11355 other register is allocated on the stack. */
11356 if (rclass == FPUL_REGS && true_regnum (x) == -1)
11357 return GENERAL_REGS;
11359 /* Force mov.b / mov.w displacement addressing insn to use R0 as
11360 the other operand.
11361 On SH2A could also just leave it alone here, which would result in a
11362 4 byte move insn being generated instead. However, for this to work
11363 the insns must have the appropriate alternatives. */
11364 if ((mode == QImode || mode == HImode) && rclass != R0_REGS
11365 && satisfies_constraint_Sdd (x)
11366 && sh_disp_addr_displacement (x)
11367 <= sh_max_mov_insn_displacement (mode, false))
11368 return R0_REGS;
11370 /* When reload is trying to address a QImode or HImode subreg on the stack,
11371 force any subreg byte into R0_REGS, as this is going to become a
11372 displacement address.
11373 We could restrict this to SUBREG_BYTE (x) > 0, but if the actual reg
11374 is on the stack, the memref to it might already require a displacement
11375 and that has to be added to the final address. At this point we don't
11376 know the cumulative displacement so we assume the worst case. */
11377 if ((mode == QImode || mode == HImode) && rclass != R0_REGS
11378 && GET_CODE (x) == SUBREG && true_regnum (x) == -1)
11379 return R0_REGS;
11381 return NO_REGS;
11384 /* Return true if SUBST can't safely replace its equivalent during RA. */
11385 static bool
11386 sh_cannot_substitute_mem_equiv_p (rtx)
11388 /* If SUBST is mem[base+index] or QI/HImode mem[base+disp], the insn
11389 uses R0 and may cause spill failure when R0 is already used.
11390 We have to return true for that case at least.
11391 Moreover SH has strong R0 parity and also have not enough numbers of
11392 the hard registers to make the equiv substitution win in the size
11393 and the speed on average working sets. The pseudos produced to
11394 hold the equiv values can't get good hard registers for bad cases
11395 and end up memory save/restore insns which make the code worse. */
11396 return true;
11399 /* Implement TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT. */
11400 static bool
11401 sh_legitimize_address_displacement (rtx *offset1, rtx *offset2,
11402 poly_int64 orig_offset,
11403 machine_mode mode)
11405 if ((TARGET_FPU_DOUBLE && mode == DFmode)
11406 || (TARGET_SH2E && mode == SFmode))
11407 return false;
11409 struct disp_adjust adj = sh_find_mov_disp_adjust (mode, orig_offset);
11410 if (adj.offset_adjust != NULL_RTX && adj.mov_disp != NULL_RTX)
11412 *offset1 = adj.offset_adjust;
11413 *offset2 = adj.mov_disp;
11414 return true;
11417 return false;
11420 /* Return true if movsf insn should be splited with an additional
11421 register. */
11422 bool
11423 sh_movsf_ie_ra_split_p (rtx op0, rtx op1, rtx op2)
11425 /* op0 == op1 */
11426 if (rtx_equal_p (op0, op1))
11427 return true;
11428 /* fy, FQ, reg */
11429 if (GET_CODE (op1) == CONST_DOUBLE
11430 && ! satisfies_constraint_G (op1)
11431 && ! satisfies_constraint_H (op1)
11432 && REG_P (op0)
11433 && REG_P (op2))
11434 return true;
11435 /* f, r, y */
11436 if (REG_P (op0) && FP_REGISTER_P (REGNO (op0))
11437 && REG_P (op1) && GENERAL_REGISTER_P (REGNO (op1))
11438 && REG_P (op2) && (REGNO (op2) == FPUL_REG))
11439 return true;
11440 /* r, f, y */
11441 if (REG_P (op1) && FP_REGISTER_P (REGNO (op1))
11442 && REG_P (op0) && GENERAL_REGISTER_P (REGNO (op0))
11443 && REG_P (op2) && (REGNO (op2) == FPUL_REG))
11444 return true;
11446 return false;
11449 static void
11450 sh_conditional_register_usage (void)
11452 for (int regno = 0; regno < FIRST_PSEUDO_REGISTER; regno ++)
11453 if (! VALID_REGISTER_P (regno))
11454 fixed_regs[regno] = call_used_regs[regno] = 1;
11455 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. */
11456 if (flag_pic)
11458 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
11459 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
11461 if (TARGET_FDPIC)
11463 fixed_regs[PIC_REG] = 1;
11464 call_used_regs[PIC_REG] = 1;
11465 call_really_used_regs[PIC_REG] = 1;
11467 /* Renesas saves and restores mac registers on call. */
11468 if (TARGET_HITACHI && ! TARGET_NOMACSAVE)
11470 call_really_used_regs[MACH_REG] = 0;
11471 call_really_used_regs[MACL_REG] = 0;
11474 for (int regno = FIRST_GENERAL_REG; regno <= LAST_GENERAL_REG; regno++)
11475 if (! fixed_regs[regno] && call_really_used_regs[regno])
11476 SET_HARD_REG_BIT (reg_class_contents[SIBCALL_REGS], regno);
11478 call_really_used_regs[FPSCR_MODES_REG] = 0;
11479 call_really_used_regs[FPSCR_STAT_REG] = 0;
11482 /* Implement TARGET_LEGITIMATE_CONSTANT_P
11484 can_store_by_pieces constructs VOIDmode CONST_DOUBLEs. */
11485 static bool
11486 sh_legitimate_constant_p (machine_mode mode, rtx x)
11488 if (SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
11490 rtx base, offset;
11491 split_const (x, &base, &offset);
11493 if (GET_CODE (base) == SYMBOL_REF
11494 && !offset_within_block_p (base, INTVAL (offset)))
11495 return false;
11498 if (TARGET_FDPIC
11499 && (SYMBOLIC_CONST_P (x)
11500 || (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
11501 && SYMBOLIC_CONST_P (XEXP (XEXP (x, 0), 0)))))
11502 return false;
11504 return GET_CODE (x) != CONST_DOUBLE
11505 || mode == DFmode || mode == SFmode
11506 || mode == DImode || GET_MODE (x) == VOIDmode;
11509 enum sh_divide_strategy_e sh_div_strategy = SH_DIV_STRATEGY_DEFAULT;
11511 static void
11512 sh_init_sync_libfuncs (void)
11514 init_sync_libfuncs (UNITS_PER_WORD);
11517 /* Return true if it is appropriate to emit `ret' instructions in the
11518 body of a function. */
11519 bool
11520 sh_can_use_simple_return_p (void)
11522 if (! reload_completed || frame_pointer_needed)
11523 return false;
11525 /* Moving prologue around does't reduce the size. */
11526 if (optimize_function_for_size_p (cfun))
11527 return false;
11529 /* Finally, allow for pr save. */
11530 HARD_REG_SET live_regs_mask;
11531 int d = calc_live_regs (&live_regs_mask);
11533 if (rounded_frame_size (d) > 4)
11534 return false;
11536 return true;
11539 /*------------------------------------------------------------------------------
11540 Address mode optimization support code
11543 typedef HOST_WIDE_INT disp_t;
11544 static const disp_t MIN_DISP = HOST_WIDE_INT_MIN;
11545 static const disp_t MAX_DISP = HOST_WIDE_INT_MAX;
11546 static const disp_t INVALID_DISP = MAX_DISP;
11548 /* A memory reference which is described by a base register and a
11549 displacement. */
11550 class base_reg_disp
11552 public:
11553 base_reg_disp (rtx br, disp_t d);
11555 bool is_reg (void) const;
11556 bool is_disp (void) const;
11557 rtx reg (void) const;
11558 disp_t disp (void) const;
11560 private:
11561 rtx reg_;
11562 disp_t disp_;
11565 inline
11566 base_reg_disp::base_reg_disp (rtx br, disp_t d)
11567 : reg_ (br), disp_ (d)
11571 inline bool
11572 base_reg_disp::is_reg (void) const
11574 return reg_ != NULL_RTX && disp_ != INVALID_DISP;
11577 inline bool
11578 base_reg_disp::is_disp (void) const
11580 return reg_ == NULL_RTX && disp_ != INVALID_DISP;
11583 inline rtx
11584 base_reg_disp::reg (void) const
11586 return reg_;
11589 inline disp_t
11590 base_reg_disp::disp (void) const
11592 return disp_;
11595 /* Find the base register and calculate the displacement for a given
11596 address rtx 'x'. */
11597 static base_reg_disp
11598 sh_find_base_reg_disp (rtx_insn* insn, rtx x, disp_t disp = 0,
11599 rtx base_reg = NULL)
11601 if (REG_P (x))
11603 if (REGNO (x) == GBR_REG)
11604 return base_reg_disp (x, disp);
11606 /* We've reached a hard-reg. This is probably the point where
11607 function args are copied to pseudos. Do not go any further and
11608 stick to the pseudo. If the original mem addr was in a hard reg
11609 from the beginning, it will become the base reg. */
11610 if (REGNO (x) < FIRST_PSEUDO_REGISTER)
11611 return base_reg_disp (base_reg != NULL ? base_reg : x, disp);
11613 /* Find the def of the reg and trace it. If there are more than one
11614 defs and they are not the same, assume it's not safe to proceed. */
11615 rtx_insn* last_i = NULL;
11616 rtx last_set = NULL;
11617 for (df_ref d = DF_REG_DEF_CHAIN (REGNO (x)); d != NULL;
11618 d = DF_REF_NEXT_REG (d))
11620 rtx set = const_cast<rtx> (set_of (x, DF_REF_INSN (d)));
11622 /* Accept multiple defs, as long as they are equal. */
11623 if (last_set == NULL || rtx_equal_p (last_set, set))
11625 last_i = DF_REF_INSN (d);
11626 last_set = set;
11628 else
11630 last_i = NULL;
11631 last_set = NULL;
11632 break;
11636 if (last_set != NULL && last_i != NULL)
11637 return sh_find_base_reg_disp (last_i, XEXP (last_set, 1), disp,
11638 XEXP (last_set, 0));
11640 /* When here, no previous insn was found that sets the reg.
11641 The input reg is already the base reg. */
11642 return base_reg_disp (x, disp);
11645 else if (GET_CODE (x) == PLUS)
11647 base_reg_disp left_val = sh_find_base_reg_disp (insn, XEXP (x, 0));
11648 base_reg_disp right_val = sh_find_base_reg_disp (insn, XEXP (x, 1));
11650 /* Either left or right val must be a reg.
11651 We don't handle the case of 'reg + reg' here. */
11652 if (left_val.is_reg () && right_val.is_disp ())
11653 return base_reg_disp (left_val.reg (), left_val.disp ()
11654 + right_val.disp () + disp);
11655 else if (right_val.is_reg () && left_val.is_disp ())
11656 return base_reg_disp (right_val.reg (), right_val.disp ()
11657 + left_val.disp () + disp);
11658 else
11659 return base_reg_disp (base_reg, disp);
11662 else if (CONST_INT_P (x))
11663 return base_reg_disp (NULL, disp + INTVAL (x));
11665 /* Didn't find anything useful. */
11666 return base_reg_disp (base_reg, disp);
11669 /* Given an insn and a memory operand, try to find an equivalent GBR
11670 based memory address and return the corresponding new memory address.
11671 Return NULL_RTX if not found. */
11673 sh_find_equiv_gbr_addr (rtx_insn* insn, rtx mem)
11675 if (!MEM_P (mem) || gbr_address_mem (mem, GET_MODE (mem)))
11676 return NULL_RTX;
11678 /* Leave post/pre inc/dec or any other side effect addresses alone. */
11679 if (side_effects_p (XEXP (mem, 0)))
11680 return NULL_RTX;
11682 /* When not optimizing there might be no dataflow available. */
11683 if (df == NULL)
11684 return NULL_RTX;
11686 base_reg_disp gbr_disp = sh_find_base_reg_disp (insn, XEXP (mem, 0));
11688 if (gbr_disp.is_reg () && REGNO (gbr_disp.reg ()) == GBR_REG)
11690 /* If GBR is marked as call clobbered we bail out if we see a call.
11691 FIXME: Actually should check if this mem refers to the gbr value
11692 before or after the call. If there is a store_gbr preceeding this
11693 mem, it's safe to use GBR for this mem.
11695 If GBR is not marked as call clobbered, but there is some other
11696 def than a call, it's probably a load_gbr upon which we also
11697 bail out to be on the safe side.
11698 FIXME: Should check if we have a use-after-def case, such as
11699 the call case above. */
11700 for (df_ref d = DF_REG_DEF_CHAIN (GBR_REG); d != NULL;
11701 d = DF_REF_NEXT_REG (d))
11703 if (CALL_P (DF_REF_INSN (d)))
11705 if (REGNO_REG_SET_P (regs_invalidated_by_call_regset, GBR_REG))
11706 return NULL_RTX;
11707 else
11708 continue;
11710 else
11711 return NULL_RTX;
11714 rtx disp = GEN_INT (gbr_disp.disp ());
11715 if (gbr_displacement (disp, GET_MODE (mem)))
11716 return gen_rtx_PLUS (SImode, gen_rtx_REG (SImode, GBR_REG), disp);
11719 return NULL_RTX;
11722 /*------------------------------------------------------------------------------
11723 Manual insn combine support code.
11726 /* Return true if the specified insn contains any UNSPECs or
11727 UNSPEC_VOLATILEs. */
11728 static bool
11729 sh_unspec_insn_p (rtx x)
11731 subrtx_iterator::array_type array;
11732 FOR_EACH_SUBRTX (i, array, x, ALL)
11733 if (*i != NULL
11734 && (GET_CODE (*i) == UNSPEC || GET_CODE (*i) == UNSPEC_VOLATILE))
11735 return true;
11737 return false;
11740 /* Return true if the register operands of the specified insn are modified
11741 between the specified from and to insns (exclusive of those two). */
11742 bool
11743 sh_insn_operands_modified_between_p (rtx_insn* operands_insn,
11744 const rtx_insn* from,
11745 const rtx_insn* to)
11747 /* FIXME: Return true for multiple sets for now. */
11748 rtx s = single_set (operands_insn);
11749 if (s == NULL_RTX)
11750 return true;
11752 subrtx_iterator::array_type array;
11753 FOR_EACH_SUBRTX (i, array, SET_SRC (s), ALL)
11754 if (*i != NULL &&
11755 ((REG_P (*i) || SUBREG_P (*i)) && reg_set_between_p (*i, from, to)))
11756 return true;
11758 return false;
11761 /* Given an insn, determine whether it's a 'nott' insn, i.e. an insn that
11762 negates the T bit and stores the result in the T bit. */
11763 bool
11764 sh_is_nott_insn (const rtx_insn* i)
11766 return i != NULL && GET_CODE (PATTERN (i)) == SET
11767 && t_reg_operand (XEXP (PATTERN (i), 0), VOIDmode)
11768 && negt_reg_operand (XEXP (PATTERN (i), 1), VOIDmode);
11772 sh_movt_set_dest (const rtx_insn* i)
11774 return i == NULL ? NULL : sh_movt_set_dest (PATTERN (i));
11778 sh_movt_set_dest (const_rtx pat)
11780 return GET_CODE (pat) == SET
11781 && arith_reg_dest (XEXP (pat, 0), SImode)
11782 && t_reg_operand (XEXP (pat, 1), VOIDmode) ? XEXP (pat, 0) : NULL;
11785 /* Given an insn, check whether it's a 'movrt' kind of insn, i.e. an insn
11786 that stores the negated T bit in a register, and return the destination
11787 register rtx, or null. */
11789 sh_movrt_set_dest (const rtx_insn* i)
11791 return i == NULL ? NULL : sh_movrt_set_dest (PATTERN (i));
11795 sh_movrt_set_dest (const_rtx pat)
11797 /* The negc movrt replacement is inside a parallel. */
11798 if (GET_CODE (pat) == PARALLEL)
11799 pat = XVECEXP (pat, 0, 0);
11801 return GET_CODE (pat) == SET
11802 && arith_reg_dest (XEXP (pat, 0), SImode)
11803 && negt_reg_operand (XEXP (pat, 1), VOIDmode) ? XEXP (pat, 0) : NULL;
11807 /* Given an insn and a reg number, tell whether the reg dies or is unused
11808 after the insn. */
11809 bool
11810 sh_reg_dead_or_unused_after_insn (const rtx_insn* i, int regno)
11812 return find_regno_note (i, REG_DEAD, regno) != NULL
11813 || find_regno_note (i, REG_UNUSED, regno) != NULL;
11816 /* Given an insn and a reg number, remove reg dead or reg unused notes to
11817 mark it as being used after the insn. */
11818 void
11819 sh_remove_reg_dead_or_unused_notes (rtx_insn* i, int regno)
11821 if (rtx n = find_regno_note (i, REG_DEAD, regno))
11822 remove_note (i, n);
11823 if (rtx n = find_regno_note (i, REG_UNUSED, regno))
11824 remove_note (i, n);
11827 /* Given an insn check if it contains any post/pre inc/dec mem operands and
11828 add the REG_INC notes accordingly.
11829 FIXME: This function is very similar to lra.c (add_auto_inc_notes).
11830 FIXME: This function is currently used by peephole2 patterns because
11831 the peephole2 pass does not preserve REG_INC notes. If the notes
11832 are dropped the following passes will do wrong things. */
11833 rtx_insn*
11834 sh_check_add_incdec_notes (rtx_insn* i)
11836 struct for_each_inc_dec_clb
11838 static int func (rtx mem ATTRIBUTE_UNUSED, rtx op ATTRIBUTE_UNUSED,
11839 rtx dest, rtx src ATTRIBUTE_UNUSED,
11840 rtx srcoff ATTRIBUTE_UNUSED, void* arg)
11842 gcc_assert (REG_P (dest));
11844 rtx_insn* i = (rtx_insn*)arg;
11845 if (find_regno_note (i, REG_INC, REGNO (dest)) == NULL)
11846 add_reg_note (i, REG_INC, dest);
11848 return 0;
11852 for_each_inc_dec (PATTERN (i), for_each_inc_dec_clb::func, i);
11853 return i;
11856 /* Given a move insn destiation and a source, make sure that the move source
11857 operand is not a post-inc mem load with the same address reg as the
11858 destination. Returns the modified source operand with the post-inc removed
11859 if necessary. */
11861 sh_remove_overlapping_post_inc (rtx dst, rtx src)
11863 if (!MEM_P (src))
11864 return src;
11866 rtx addr = XEXP (src, 0);
11868 if (GET_CODE (addr) == POST_INC
11869 && reg_overlap_mentioned_p (XEXP (addr, 0), dst))
11870 return replace_equiv_address (src, XEXP (addr, 0));
11872 gcc_assert (GET_CODE (addr) != POST_MODIFY);
11873 return src;
11876 /* Emit a move insn that is safe to be used in peephole patterns. */
11877 rtx_insn*
11878 sh_peephole_emit_move_insn (rtx dst, rtx src)
11880 return sh_check_add_incdec_notes (
11881 emit_move_insn (dst, sh_remove_overlapping_post_inc (dst, src)));
11884 /* Given an op rtx and an insn, try to find out whether the result of the
11885 specified op consists only of logical operations on T bit stores. */
11886 bool
11887 sh_is_logical_t_store_expr (rtx op, rtx_insn* insn)
11889 if (!logical_operator (op, SImode))
11890 return false;
11892 rtx ops[2] = { XEXP (op, 0), XEXP (op, 1) };
11893 int op_is_t_count = 0;
11895 for (int i = 0; i < 2; ++i)
11897 if (t_reg_operand (ops[i], VOIDmode)
11898 || negt_reg_operand (ops[i], VOIDmode))
11899 op_is_t_count++;
11901 else
11903 set_of_reg op_set = sh_find_set_of_reg
11904 (ops[i], insn, prev_nonnote_nondebug_insn_bb);
11905 if (op_set.set_src == NULL_RTX)
11906 continue;
11908 if (t_reg_operand (op_set.set_src, VOIDmode)
11909 || negt_reg_operand (op_set.set_src, VOIDmode)
11910 || sh_is_logical_t_store_expr (op_set.set_src, op_set.insn))
11911 op_is_t_count++;
11915 return op_is_t_count == 2;
11918 /* Given the operand that is extended in a sign/zero extend insn, and the
11919 insn, try to figure out whether the sign/zero extension can be replaced
11920 by a simple reg-reg copy. If so, the replacement reg rtx is returned,
11921 NULL_RTX otherwise. */
11923 sh_try_omit_signzero_extend (rtx extended_op, rtx_insn* insn)
11925 if (REG_P (extended_op))
11926 extended_op = extended_op;
11927 else if (GET_CODE (extended_op) == SUBREG && REG_P (SUBREG_REG (extended_op)))
11928 extended_op = SUBREG_REG (extended_op);
11929 else
11930 return NULL_RTX;
11932 /* Reg moves must be of the same mode. */
11933 if (GET_MODE (extended_op) != SImode)
11934 return NULL_RTX;
11936 set_of_reg s = sh_find_set_of_reg (extended_op, insn,
11937 prev_nonnote_nondebug_insn_bb);
11938 if (s.set_src == NULL_RTX)
11939 return NULL_RTX;
11941 if (t_reg_operand (s.set_src, VOIDmode)
11942 || negt_reg_operand (s.set_src, VOIDmode))
11943 return extended_op;
11945 /* If the zero extended reg was formed by a logical operation, check the
11946 operands of the logical operation. If both originated from T bit
11947 stores the zero extension can be eliminated. */
11948 else if (sh_is_logical_t_store_expr (s.set_src, s.insn))
11949 return extended_op;
11951 return NULL_RTX;
11954 /* Given the current insn, which is assumed to be a movrt_negc insn, try to
11955 figure out whether it should be converted into a movt-xor sequence in
11956 the movrt_negc splitter.
11957 Returns true if insns have been modified and the splitter has succeeded. */
11958 bool
11959 sh_split_movrt_negc_to_movt_xor (rtx_insn* curr_insn, rtx operands[])
11961 /* In cases such as
11962 tst r4,r4
11963 mov #-1,r1
11964 negc r1,r1
11965 tst r4,r4
11966 we can replace the T bit clobbering negc with a movt-xor sequence and
11967 eliminate the redundant comparison.
11968 Because the xor insn depends on register allocation results, allow this
11969 only before reload. */
11970 if (!can_create_pseudo_p ())
11971 return false;
11973 set_of_reg t_before_negc = sh_find_set_of_reg
11974 (get_t_reg_rtx (), curr_insn, prev_nonnote_nondebug_insn_bb);
11975 set_of_reg t_after_negc = sh_find_set_of_reg
11976 (get_t_reg_rtx (), curr_insn, next_nonnote_nondebug_insn_bb);
11978 if (t_before_negc.set_rtx != NULL_RTX && t_after_negc.set_rtx != NULL_RTX
11979 && rtx_equal_p (t_before_negc.set_rtx, t_after_negc.set_rtx)
11980 && !reg_used_between_p (get_t_reg_rtx (), curr_insn, t_after_negc.insn)
11981 && !sh_insn_operands_modified_between_p (t_before_negc.insn,
11982 t_before_negc.insn,
11983 t_after_negc.insn)
11984 && !modified_between_p (get_t_reg_rtx (), curr_insn, t_after_negc.insn)
11985 && !sh_unspec_insn_p (t_after_negc.insn)
11986 && !volatile_insn_p (PATTERN (t_after_negc.insn))
11987 && !side_effects_p (PATTERN (t_after_negc.insn))
11988 && !may_trap_or_fault_p (PATTERN (t_after_negc.insn)))
11990 emit_insn (gen_movrt_xor (operands[0], get_t_reg_rtx ()));
11991 set_insn_deleted (t_after_negc.insn);
11992 return true;
11994 else
11995 return false;
11998 /* Given a reg and the current insn, see if the value of the reg originated
11999 from a sign or zero extension and return the discovered information. */
12000 sh_extending_set_of_reg
12001 sh_find_extending_set_of_reg (rtx reg, rtx_insn* curr_insn)
12003 if (reg == NULL)
12004 return sh_extending_set_of_reg (curr_insn);
12006 if (SUBREG_P (reg))
12007 reg = SUBREG_REG (reg);
12009 if (!REG_P (reg))
12010 return sh_extending_set_of_reg (curr_insn);
12012 /* FIXME: Also search the predecessor basic blocks. It seems that checking
12013 only the adjacent predecessor blocks would cover most of the cases.
12014 Also try to look through the first extension that we hit. There are some
12015 cases, where a zero_extend is followed an (implicit) sign_extend, and it
12016 fails to see the sign_extend. */
12017 sh_extending_set_of_reg result = sh_find_set_of_reg
12018 (reg, curr_insn, prev_nonnote_nondebug_insn_bb, true);
12020 if (result.set_src != NULL)
12022 if (GET_CODE (result.set_src) == SIGN_EXTEND
12023 || GET_CODE (result.set_src) == ZERO_EXTEND)
12025 if (dump_file)
12026 fprintf (dump_file, "sh_find_extending_set_of_reg: reg %d is "
12027 "explicitly sign/zero extended in insn %d\n",
12028 REGNO (reg), INSN_UID (result.insn));
12029 result.from_mode = GET_MODE (XEXP (result.set_src, 0));
12030 result.ext_code = GET_CODE (result.set_src);
12032 else if (MEM_P (result.set_src)
12033 && (GET_MODE (result.set_src) == QImode
12034 || GET_MODE (result.set_src) == HImode)
12035 && !sh_unspec_insn_p (result.insn))
12037 /* On SH QIHImode memory loads always sign extend. However, in
12038 some cases where it seems that the higher bits are not
12039 interesting, the loads will not be expanded as sign extending
12040 insns, but as QIHImode loads into QIHImode regs. We report that
12041 the reg has been sign extended by the mem load. When it is used
12042 as such, we must convert the mem load into a sign extending insn,
12043 see also sh_extending_set_of_reg::use_as_extended_reg. */
12044 if (dump_file)
12045 fprintf (dump_file, "sh_find_extending_set_of_reg: reg %d is "
12046 "implicitly sign extended in insn %d\n",
12047 REGNO (reg), INSN_UID (result.insn));
12048 result.from_mode = GET_MODE (result.set_src);
12049 result.ext_code = SIGN_EXTEND;
12053 return result;
12056 /* Given a reg that is known to be sign or zero extended at some insn,
12057 take the appropriate measures so that the extended value can be used as
12058 a reg at the specified insn and return the resulting reg rtx. */
12060 sh_extending_set_of_reg::use_as_extended_reg (rtx_insn* use_at_insn) const
12062 gcc_assert (insn != NULL && set_src != NULL && set_rtx != NULL);
12063 gcc_assert (ext_code == SIGN_EXTEND || ext_code == ZERO_EXTEND);
12064 gcc_assert (from_mode == QImode || from_mode == HImode);
12066 if (MEM_P (set_src) && ext_code == SIGN_EXTEND)
12068 if (dump_file)
12069 fprintf (dump_file,
12070 "use_as_extended_reg: converting non-extending mem load in "
12071 "insn %d into sign-extending load\n", INSN_UID (insn));
12073 rtx r = gen_reg_rtx (SImode);
12074 rtx_insn* i0;
12075 if (from_mode == QImode)
12076 i0 = emit_insn_after (gen_extendqisi2 (r, set_src), insn);
12077 else if (from_mode == HImode)
12078 i0 = emit_insn_after (gen_extendhisi2 (r, set_src), insn);
12079 else
12080 gcc_unreachable ();
12082 emit_insn_after (
12083 gen_move_insn (XEXP (set_rtx, 0),
12084 gen_lowpart (GET_MODE (set_src), r)), i0);
12085 set_insn_deleted (insn);
12086 return r;
12088 else
12090 rtx extension_dst = XEXP (set_rtx, 0);
12091 if (GET_MODE (extension_dst) != SImode)
12092 extension_dst = simplify_gen_subreg (SImode, extension_dst,
12093 GET_MODE (extension_dst), 0);
12094 if (modified_between_p (extension_dst, insn, use_at_insn))
12096 if (dump_file)
12097 fprintf (dump_file,
12098 "use_as_extended_reg: dest reg %d of extending insn %d is "
12099 "modified, inserting a reg-reg copy\n",
12100 REGNO (extension_dst), INSN_UID (insn));
12102 rtx r = gen_reg_rtx (SImode);
12103 emit_insn_after (gen_move_insn (r, extension_dst), insn);
12104 return r;
12106 else
12108 sh_remove_reg_dead_or_unused_notes (insn, REGNO (extension_dst));
12109 return extension_dst;
12114 bool
12115 sh_extending_set_of_reg::can_use_as_unextended_reg (void) const
12117 if ((ext_code == SIGN_EXTEND || ext_code == ZERO_EXTEND)
12118 && (from_mode == QImode || from_mode == HImode)
12119 && set_src != NULL)
12120 return arith_reg_operand (XEXP (set_src, 0), from_mode);
12121 else
12122 return false;
12126 sh_extending_set_of_reg::use_as_unextended_reg (rtx_insn* use_at_insn) const
12128 gcc_assert (can_use_as_unextended_reg ());
12130 rtx r = XEXP (set_src, 0);
12131 rtx r0 = simplify_gen_subreg (SImode, r, from_mode, 0);
12133 if (modified_between_p (r, insn, use_at_insn))
12135 rtx r1 = gen_reg_rtx (SImode);
12136 emit_insn_after (gen_move_insn (r1, r0), insn);
12137 return r1;
12139 else
12141 sh_remove_reg_dead_or_unused_notes (insn, SUBREG_P (r)
12142 ? REGNO (SUBREG_REG (r))
12143 : REGNO (r));
12144 return r0;
12148 /* Given the current insn, which is assumed to be the *tst<mode>_t_subregs insn,
12149 perform the necessary checks on the operands and split it accordingly. */
12150 void
12151 sh_split_tst_subregs (rtx_insn* curr_insn, machine_mode subreg_mode,
12152 int subreg_offset, rtx operands[])
12154 gcc_assert (subreg_mode == QImode || subreg_mode == HImode);
12156 sh_extending_set_of_reg eop0 = sh_find_extending_set_of_reg (operands[0],
12157 curr_insn);
12158 sh_extending_set_of_reg eop1 = sh_find_extending_set_of_reg (operands[1],
12159 curr_insn);
12161 /* If one of the operands is known to be zero extended, that's already
12162 sufficient to mask out the unwanted high bits. */
12163 if (eop0.ext_code == ZERO_EXTEND && eop0.from_mode == subreg_mode)
12165 emit_insn (gen_tstsi_t (eop0.use_as_extended_reg (curr_insn),
12166 operands[1]));
12167 return;
12169 if (eop1.ext_code == ZERO_EXTEND && eop1.from_mode == subreg_mode)
12171 emit_insn (gen_tstsi_t (operands[0],
12172 eop1.use_as_extended_reg (curr_insn)));
12173 return;
12176 /* None of the operands seem to be zero extended.
12177 If both are sign extended it's OK, too. */
12178 if (eop0.ext_code == SIGN_EXTEND && eop1.ext_code == SIGN_EXTEND
12179 && eop0.from_mode == subreg_mode && eop1.from_mode == subreg_mode)
12181 emit_insn (gen_tstsi_t (eop0.use_as_extended_reg (curr_insn),
12182 eop1.use_as_extended_reg (curr_insn)));
12183 return;
12186 /* Otherwise we have to insert a zero extension on one of the operands to
12187 mask out the unwanted high bits.
12188 Prefer the operand that has no known extension. */
12189 if (eop0.ext_code != UNKNOWN && eop1.ext_code == UNKNOWN)
12190 std::swap (operands[0], operands[1]);
12192 rtx tmp0 = gen_reg_rtx (SImode);
12193 rtx tmp1 = simplify_gen_subreg (subreg_mode, operands[0],
12194 GET_MODE (operands[0]), subreg_offset);
12195 emit_insn (subreg_mode == QImode
12196 ? gen_zero_extendqisi2 (tmp0, tmp1)
12197 : gen_zero_extendhisi2 (tmp0, tmp1));
12198 emit_insn (gen_tstsi_t (tmp0, operands[1]));
12201 /* A helper class to increment/decrement a counter variable each time a
12202 function is entered/left. */
12203 class scope_counter
12205 public:
12206 scope_counter (int& counter) : m_counter (counter) { ++m_counter; }
12208 ~scope_counter (void)
12210 --m_counter;
12211 gcc_assert (m_counter >= 0);
12214 int count (void) const { return m_counter; }
12216 private:
12217 int& m_counter;
12220 /* Given an rtx x, determine whether the expression can be used to create
12221 an insn that calulates x and stores the result in the T bit.
12222 This is used by the 'treg_set_expr' predicate to construct insns sequences
12223 where T bit results are fed into other insns, such as addc, subc, negc
12224 insns.
12226 FIXME: The patterns that expand 'treg_set_expr' operands tend to
12227 distinguish between 'positive' and 'negative' forms. For now this has to
12228 be done in the preparation code. We could also introduce
12229 'pos_treg_set_expr' and 'neg_treg_set_expr' predicates for that and write
12230 two different patterns for the 'postive' and 'negative' forms. However,
12231 the total amount of lines of code seems to be about the same and the
12232 '{pos|neg}_treg_set_expr' predicates would be more expensive, because the
12233 recog function would need to look inside the expression by temporarily
12234 splitting it. */
12235 static int sh_recog_treg_set_expr_reent_count = 0;
12237 bool
12238 sh_recog_treg_set_expr (rtx op, machine_mode mode)
12240 scope_counter recursion (sh_recog_treg_set_expr_reent_count);
12242 /* Limit the recursion count to avoid nested expressions which we can't
12243 resolve to a single treg set insn. */
12244 if (recursion.count () > 1)
12245 return false;
12247 /* Early accept known possible operands before doing recog. */
12248 if (op == const0_rtx || op == const1_rtx || t_reg_operand (op, mode)
12249 || negt_reg_operand (op, mode))
12250 return true;
12252 /* Early reject impossible operands before doing recog.
12253 There are some (set ((t) (subreg ...))) patterns, but we must be careful
12254 not to allow any invalid reg-reg or mem-reg moves, or else other passes
12255 such as lower-subreg will bail out. Some insns such as SH4A movua are
12256 done with UNSPEC, so must reject those, too, or else it would result
12257 in an invalid reg -> treg move. */
12258 if (CONST_INT_P (op) || register_operand (op, mode)
12259 || memory_operand (op, mode) || sh_unspec_insn_p (op))
12260 return false;
12262 if (!can_create_pseudo_p ())
12263 return false;
12265 /* expand_debug_locations may call this to compute rtx costs at
12266 very early stage. In that case, don't make new insns here to
12267 avoid codegen differences with -g. */
12268 if (currently_expanding_to_rtl)
12269 return false;
12271 /* We are going to invoke recog in a re-entrant way and thus
12272 have to capture its current state and restore it afterwards. */
12273 recog_data_d prev_recog_data = recog_data;
12275 rtx_insn* i = make_insn_raw (gen_rtx_SET (get_t_reg_rtx (), op));
12276 SET_PREV_INSN (i) = NULL;
12277 SET_NEXT_INSN (i) = NULL;
12279 /* If the comparison op doesn't have a result mode, set it to SImode. */
12280 machine_mode prev_op_mode = GET_MODE (op);
12281 if (COMPARISON_P (op) && prev_op_mode == VOIDmode)
12282 PUT_MODE (op, SImode);
12284 int result = recog (PATTERN (i), i, 0);
12286 /* It seems there is no insn like that. Create a negated version and
12287 try again. If we hit a negated form, we'll allow that and append a
12288 nott sequence when splitting out the insns. Insns that do the split
12289 can then remove the trailing nott if they know how to deal with it. */
12290 if (result < 0 && COMPARISON_P (op))
12292 machine_mode cmp_mode = GET_MODE (XEXP (op, 0));
12293 if (cmp_mode == VOIDmode)
12294 cmp_mode = GET_MODE (XEXP (op, 1));
12296 rtx_code prev_code = GET_CODE (op);
12297 PUT_CODE (op, reverse_condition (GET_CODE (op)));
12298 result = recog (PATTERN (i), i, 0);
12299 PUT_CODE (op, prev_code);
12302 PUT_MODE (op, prev_op_mode);
12303 recog_data = prev_recog_data;
12304 return result >= 0;
12307 /* Returns true when recog of a 'treg_set_expr' is currently in progress.
12308 This can be used as a condition for insn/split patterns to allow certain
12309 T bit setting patters only to be matched as sub expressions of other
12310 patterns. */
12311 bool
12312 sh_in_recog_treg_set_expr (void)
12314 return sh_recog_treg_set_expr_reent_count > 0;
12317 /* Given an rtx x, which is assumed to be some expression that has been
12318 matched by the 'treg_set_expr' predicate before, split and emit the
12319 insns that are necessary to calculate the expression and store the result
12320 in the T bit.
12321 The splitting is done recursively similar to 'try_split' in emit-rt.c.
12322 Unfortunately we can't use 'try_split' here directly, as it tries to invoke
12323 'delete_insn' which then causes the DF parts to bail out, because we
12324 currently are inside another gen_split* function and would invoke
12325 'try_split' in a reentrant way. */
12326 static std::pair<rtx_insn*, rtx_insn*>
12327 sh_try_split_insn_simple (rtx_insn* i, rtx_insn* curr_insn, int n = 0)
12329 if (dump_file)
12331 fprintf (dump_file, "sh_try_split_insn_simple n = %d i = \n", n);
12332 print_rtl_single (dump_file, i);
12333 fprintf (dump_file, "\n");
12336 rtx_insn* seq = split_insns (PATTERN (i), curr_insn);
12338 if (seq == NULL)
12339 return std::make_pair (i, i);
12341 /* Avoid infinite splitter loops if any insn of the result matches
12342 the original pattern. */
12343 for (rtx_insn* s = seq; s != NULL; s = NEXT_INSN (s))
12344 if (INSN_P (s) && rtx_equal_p (PATTERN (s), PATTERN (i)))
12345 return std::make_pair (i, i);
12347 unshare_all_rtl_in_chain (seq);
12349 /* 'seq' is now a replacement for 'i'. Assuming that 'i' is an insn in
12350 a linked list, replace the single insn with the new insns. */
12351 rtx_insn* seqlast = seq;
12352 while (NEXT_INSN (seqlast) != NULL)
12353 seqlast = NEXT_INSN (seqlast);
12355 if (rtx_insn* iprev = PREV_INSN (i))
12356 SET_NEXT_INSN (iprev) = seq;
12357 if (rtx_insn* inext = NEXT_INSN (i))
12358 SET_PREV_INSN (inext) = seqlast;
12360 SET_PREV_INSN (seq) = PREV_INSN (i);
12361 SET_NEXT_INSN (seqlast) = NEXT_INSN (i);
12363 SET_PREV_INSN (i) = NULL;
12364 SET_NEXT_INSN (i) = NULL;
12366 /* Recursively split all insns. */
12367 for (i = seq; ; i = NEXT_INSN (i))
12369 std::pair<rtx_insn*, rtx_insn*> ii =
12370 sh_try_split_insn_simple (i, curr_insn, n + 1);
12371 if (i == seq)
12372 seq = ii.first;
12373 if (i == seqlast)
12375 seqlast = ii.second;
12376 break;
12378 i = ii.first;
12381 return std::make_pair (seq, seqlast);
12384 sh_treg_insns
12385 sh_split_treg_set_expr (rtx x, rtx_insn* curr_insn)
12387 if (t_reg_operand (x, VOIDmode))
12388 return sh_treg_insns ();
12390 scope_counter in_treg_set_expr (sh_recog_treg_set_expr_reent_count);
12392 rtx_insn* i = make_insn_raw (gen_rtx_SET (get_t_reg_rtx (), x));
12393 SET_PREV_INSN (i) = NULL;
12394 SET_NEXT_INSN (i) = NULL;
12396 if (dump_file)
12398 fprintf (dump_file, "split_treg_set_expr insn:\n");
12399 print_rtl (dump_file, i);
12400 fprintf (dump_file, "\n");
12403 /* If the insn is not found, we will try a negated form and append
12404 a nott. */
12405 bool append_nott = false;
12407 /* We are going to invoke recog/split_insns in a re-entrant way and thus
12408 have to capture its current state and restore it afterwards. */
12409 recog_data_d prev_recog_data = recog_data;
12411 if (negt_reg_operand (x, GET_MODE (x)))
12413 /* This is a normal movt followed by a nott. It will be converted
12414 into a movrt after initial expansion. */
12415 XEXP (PATTERN (i), 1) = get_t_reg_rtx ();
12416 append_nott = true;
12418 else
12420 /* If the comparison op doesn't have a mode set, set it to SImode. */
12421 if (COMPARISON_P (x) && GET_MODE (x) == VOIDmode)
12422 PUT_MODE (x, SImode);
12424 int insn_code = recog (PATTERN (i), i, 0);
12426 if (insn_code < 0 && COMPARISON_P (x))
12428 machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
12429 if (cmp_mode == VOIDmode)
12430 cmp_mode = GET_MODE (XEXP (x, 1));
12432 PUT_CODE (x, reverse_condition (GET_CODE (x)));
12433 insn_code = recog (PATTERN (i), i, 0);
12434 append_nott = true;
12437 gcc_assert (insn_code >= 0);
12440 /* Try to recursively split the insn. Some insns might refuse to split
12441 any further while we are in the treg_set_expr splitting phase. They
12442 will be emitted as part of the outer insn and then split again. */
12443 std::pair<rtx_insn*, rtx_insn*> insnlist =
12444 sh_try_split_insn_simple (i, curr_insn);
12446 /* Restore recog state. */
12447 recog_data = prev_recog_data;
12449 rtx_insn* nott_insn = sh_is_nott_insn (insnlist.second)
12450 ? insnlist.second
12451 : NULL;
12452 if (dump_file)
12454 fprintf (dump_file, "split_treg_set_expr insnlist:\n");
12455 print_rtl (dump_file, insnlist.first);
12456 fprintf (dump_file, "\n");
12458 if (nott_insn != NULL)
12459 fprintf (dump_file, "trailing nott insn %d\n", INSN_UID (nott_insn));
12462 emit_insn (insnlist.first);
12464 if (nott_insn != NULL && append_nott)
12466 if (dump_file)
12467 fprintf (dump_file, "removing trailing nott\n");
12468 remove_insn (nott_insn);
12469 nott_insn = NULL;
12470 append_nott = false;
12473 if (append_nott)
12474 nott_insn = emit_insn (gen_nott (get_t_reg_rtx ()));
12476 rtx_insn* first_insn = get_insns ();
12478 if (dump_file)
12480 fprintf (dump_file, "resulting insns:\n");
12481 print_rtl (dump_file, first_insn);
12482 fprintf (dump_file, "\n");
12485 return sh_treg_insns (first_insn, nott_insn);
12488 /*------------------------------------------------------------------------------
12489 Mode switching support code.
12492 static void
12493 sh_emit_mode_set (int entity ATTRIBUTE_UNUSED, int mode,
12494 int prev_mode, HARD_REG_SET regs_live ATTRIBUTE_UNUSED)
12496 if ((TARGET_SH4A_FP || TARGET_SH4_300)
12497 && prev_mode != FP_MODE_NONE && prev_mode != mode)
12499 emit_insn (gen_toggle_pr ());
12500 if (TARGET_FMOVD)
12501 emit_insn (gen_toggle_sz ());
12503 else if (mode != FP_MODE_NONE)
12505 rtx tmp = gen_reg_rtx (SImode);
12506 emit_insn (gen_sts_fpscr (tmp));
12507 rtx i = NULL;
12509 const unsigned HOST_WIDE_INT fpbits =
12510 TARGET_FMOVD ? (FPSCR_PR | FPSCR_SZ) : FPSCR_PR;
12512 if (prev_mode != FP_MODE_NONE && prev_mode != mode)
12513 i = gen_xorsi3 (tmp, tmp, force_reg (SImode, GEN_INT (fpbits)));
12514 else if (mode == FP_MODE_SINGLE)
12515 i = gen_andsi3 (tmp, tmp, force_reg (SImode, GEN_INT (~fpbits)));
12516 else if (mode == FP_MODE_DOUBLE)
12517 i = gen_iorsi3 (tmp, tmp, force_reg (SImode, GEN_INT (fpbits)));
12518 else
12519 gcc_unreachable ();
12521 emit_insn (i);
12522 emit_insn (gen_lds_fpscr (tmp));
12526 static int
12527 sh_mode_needed (int entity ATTRIBUTE_UNUSED, rtx_insn *insn)
12529 return recog_memoized (insn) >= 0 ? get_attr_fp_mode (insn) : FP_MODE_NONE;
12532 static int
12533 sh_mode_after (int entity ATTRIBUTE_UNUSED, int mode, rtx_insn *insn)
12535 if (TARGET_HITACHI && recog_memoized (insn) >= 0 &&
12536 get_attr_fp_set (insn) != FP_SET_NONE)
12537 return (int) get_attr_fp_set (insn);
12538 else
12539 return mode;
12542 static int
12543 sh_mode_entry (int entity ATTRIBUTE_UNUSED)
12545 return NORMAL_MODE (entity);
12548 static int
12549 sh_mode_exit (int entity ATTRIBUTE_UNUSED)
12551 return sh_cfun_attr_renesas_p () ? FP_MODE_NONE : NORMAL_MODE (entity);
12554 static int
12555 sh_mode_priority (int entity ATTRIBUTE_UNUSED, int n)
12557 return ((TARGET_FPU_SINGLE != 0) ^ (n) ? FP_MODE_SINGLE : FP_MODE_DOUBLE);
12560 /*------------------------------------------------------------------------------
12561 Misc
12564 /* Return true if we use LRA instead of reload pass. */
12565 bool
12566 sh_lra_p (void)
12568 return sh_lra_flag;
12571 /* Implement TARGET_USE_BY_PIECES_INFRASTRUCTURE_P. */
12573 static bool
12574 sh_use_by_pieces_infrastructure_p (unsigned HOST_WIDE_INT size,
12575 unsigned int align,
12576 enum by_pieces_operation op,
12577 bool speed_p)
12579 switch (op)
12581 case MOVE_BY_PIECES:
12582 return by_pieces_ninsns (size, align, MOVE_MAX_PIECES + 1, op)
12583 < (!speed_p ? 2 : (align >= 32) ? 16 : 2);
12584 case STORE_BY_PIECES:
12585 case SET_BY_PIECES:
12586 return by_pieces_ninsns (size, align, STORE_MAX_PIECES + 1, op)
12587 < (!speed_p ? 2 : (align >= 32) ? 16 : 2);
12588 default:
12589 return default_use_by_pieces_infrastructure_p (size, align,
12590 op, speed_p);
12594 bool
12595 sh_cannot_force_const_mem_p (machine_mode mode ATTRIBUTE_UNUSED,
12596 rtx x ATTRIBUTE_UNUSED)
12598 return TARGET_FDPIC;
12601 /* Emit insns to load the function address from FUNCDESC (an FDPIC
12602 function descriptor) into r1 and the GOT address into r12,
12603 returning an rtx for r1. */
12606 sh_load_function_descriptor (rtx funcdesc)
12608 rtx r1 = gen_rtx_REG (Pmode, R1_REG);
12609 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
12610 rtx fnaddr = gen_rtx_MEM (Pmode, funcdesc);
12611 rtx gotaddr = gen_rtx_MEM (Pmode, plus_constant (Pmode, funcdesc, 4));
12613 emit_move_insn (r1, fnaddr);
12614 /* The ABI requires the entry point address to be loaded first, so
12615 prevent the load from being moved after that of the GOT
12616 address. */
12617 emit_insn (gen_blockage ());
12618 emit_move_insn (pic_reg, gotaddr);
12619 return r1;
12622 /* Return an rtx holding the initial value of the FDPIC register (the
12623 FDPIC pointer passed in from the caller). */
12626 sh_get_fdpic_reg_initial_val (void)
12628 return get_hard_reg_initial_val (Pmode, PIC_REG);
12631 #include "gt-sh.h"