gcc/config/aarch64/predicates.md

   1 ;; Machine description for AArch64 architecture.
   2 ;; Copyright (C) 2009-2018 Free Software Foundation, Inc.
   3 ;; Contributed by ARM Ltd.
   4 ;;
   5 ;; This file is part of GCC.
   6 ;;
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published by
   9 ;; the Free Software Foundation; either version 3, or (at your option)
  10 ;; any later version.
  11 ;;
  12 ;; GCC is distributed in the hope that it will be useful, but
  13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 ;; General Public License for more details.
  16 ;;
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING3.  If not see
  19 ;; <http://www.gnu.org/licenses/>.
  20
  21 (define_special_predicate "cc_register"
  22   (and (match_code "reg")
  23        (and (match_test "REGNO (op) == CC_REGNUM")
  24             (ior (match_test "mode == GET_MODE (op)")
  25                  (match_test "mode == VOIDmode
  26                               && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC"))))
  27 )
  28
  29 (define_predicate "aarch64_call_insn_operand"
  30   (ior (match_code "symbol_ref")
  31        (match_operand 0 "register_operand")))
  32
  33 ;; Return true if OP a (const_int 0) operand.
  34 (define_predicate "const0_operand"
  35   (and (match_code "const_int")
  36        (match_test "op == CONST0_RTX (mode)")))
  37
  38 (define_special_predicate "subreg_lowpart_operator"
  39   (and (match_code "subreg")
  40        (match_test "subreg_lowpart_p (op)")))
  41
  42 (define_predicate "aarch64_ccmp_immediate"
  43   (and (match_code "const_int")
  44        (match_test "IN_RANGE (INTVAL (op), -31, 31)")))
  45
  46 (define_predicate "aarch64_ccmp_operand"
  47   (ior (match_operand 0 "register_operand")
  48        (match_operand 0 "aarch64_ccmp_immediate")))
  49
  50 (define_predicate "aarch64_simd_register"
  51   (and (match_code "reg")
  52        (ior (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_LO_REGS")
  53             (match_test "REGNO_REG_CLASS (REGNO (op)) == FP_REGS"))))
  54
  55 (define_predicate "aarch64_reg_or_zero"
  56   (and (match_code "reg,subreg,const_int")
  57        (ior (match_operand 0 "register_operand")
  58             (match_test "op == const0_rtx"))))
  59
  60 (define_predicate "aarch64_reg_or_fp_zero"
  61   (ior (match_operand 0 "register_operand")
  62         (and (match_code "const_double")
  63              (match_test "aarch64_float_const_zero_rtx_p (op)"))))
  64
  65 (define_predicate "aarch64_reg_zero_or_m1_or_1"
  66   (and (match_code "reg,subreg,const_int")
  67        (ior (match_operand 0 "register_operand")
  68             (ior (match_test "op == const0_rtx")
  69                  (ior (match_test "op == constm1_rtx")
  70                       (match_test "op == const1_rtx"))))))
  71
  72 (define_predicate "aarch64_reg_or_orr_imm"
  73    (ior (match_operand 0 "register_operand")
  74         (and (match_code "const_vector")
  75              (match_test "aarch64_simd_valid_immediate (op, NULL,
  76                                                         AARCH64_CHECK_ORR)"))))
  77
  78 (define_predicate "aarch64_reg_or_bic_imm"
  79    (ior (match_operand 0 "register_operand")
  80         (and (match_code "const_vector")
  81              (match_test "aarch64_simd_valid_immediate (op, NULL,
  82                                                         AARCH64_CHECK_BIC)"))))
  83
  84 (define_predicate "aarch64_fp_compare_operand"
  85   (ior (match_operand 0 "register_operand")
  86        (and (match_code "const_double")
  87             (match_test "aarch64_float_const_zero_rtx_p (op)"))))
  88
  89 (define_predicate "aarch64_fp_pow2"
  90   (and (match_code "const_double")
  91         (match_test "aarch64_fpconst_pow_of_2 (op) > 0")))
  92
  93 (define_predicate "aarch64_fp_vec_pow2"
  94   (match_test "aarch64_vec_fpconst_pow_of_2 (op) > 0"))
  95
  96 (define_predicate "aarch64_sve_cnt_immediate"
  97   (and (match_code "const_poly_int")
  98        (match_test "aarch64_sve_cnt_immediate_p (op)")))
  99
 100 (define_predicate "aarch64_sub_immediate"
 101   (and (match_code "const_int")
 102        (match_test "aarch64_uimm12_shift (-INTVAL (op))")))
 103
 104 (define_predicate "aarch64_plus_immediate"
 105   (and (match_code "const_int")
 106        (ior (match_test "aarch64_uimm12_shift (INTVAL (op))")
 107             (match_test "aarch64_uimm12_shift (-INTVAL (op))"))))
 108
 109 (define_predicate "aarch64_plus_operand"
 110   (ior (match_operand 0 "register_operand")
 111        (match_operand 0 "aarch64_plus_immediate")))
 112
 113 (define_predicate "aarch64_pluslong_immediate"
 114   (and (match_code "const_int")
 115        (match_test "(INTVAL (op) < 0xffffff && INTVAL (op) > -0xffffff)")))
 116
 117 (define_predicate "aarch64_pluslong_strict_immedate"
 118   (and (match_operand 0 "aarch64_pluslong_immediate")
 119        (not (match_operand 0 "aarch64_plus_immediate"))))
 120
 121 (define_predicate "aarch64_sve_addvl_addpl_immediate"
 122   (and (match_code "const_poly_int")
 123        (match_test "aarch64_sve_addvl_addpl_immediate_p (op)")))
 124
 125 (define_predicate "aarch64_split_add_offset_immediate"
 126   (and (match_code "const_poly_int")
 127        (match_test "aarch64_add_offset_temporaries (op) == 1")))
 128
 129 (define_predicate "aarch64_pluslong_operand"
 130   (ior (match_operand 0 "register_operand")
 131        (match_operand 0 "aarch64_pluslong_immediate")
 132        (match_operand 0 "aarch64_sve_addvl_addpl_immediate")))
 133
 134 (define_predicate "aarch64_pluslong_or_poly_operand"
 135   (ior (match_operand 0 "aarch64_pluslong_operand")
 136        (match_operand 0 "aarch64_split_add_offset_immediate")))
 137
 138 (define_predicate "aarch64_logical_immediate"
 139   (and (match_code "const_int")
 140        (match_test "aarch64_bitmask_imm (INTVAL (op), mode)")))
 141
 142 (define_predicate "aarch64_logical_operand"
 143   (ior (match_operand 0 "register_operand")
 144        (match_operand 0 "aarch64_logical_immediate")))
 145
 146 (define_predicate "aarch64_mov_imm_operand"
 147   (and (match_code "const_int")
 148        (match_test "aarch64_move_imm (INTVAL (op), mode)")))
 149
 150 (define_predicate "aarch64_logical_and_immediate"
 151   (and (match_code "const_int")
 152        (match_test "aarch64_and_bitmask_imm (INTVAL (op), mode)")))
 153
 154 (define_predicate "aarch64_shift_imm_si"
 155   (and (match_code "const_int")
 156        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 32")))
 157
 158 (define_predicate "aarch64_shift_imm_di"
 159   (and (match_code "const_int")
 160        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) < 64")))
 161
 162 (define_predicate "aarch64_shift_imm64_di"
 163   (and (match_code "const_int")
 164        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 64")))
 165
 166 (define_predicate "aarch64_reg_or_shift_imm_si"
 167   (ior (match_operand 0 "register_operand")
 168        (match_operand 0 "aarch64_shift_imm_si")))
 169
 170 (define_predicate "aarch64_reg_or_shift_imm_di"
 171   (ior (match_operand 0 "register_operand")
 172        (match_operand 0 "aarch64_shift_imm_di")))
 173
 174 ;; The imm3 field is a 3-bit field that only accepts immediates in the
 175 ;; range 0..4.
 176 (define_predicate "aarch64_imm3"
 177   (and (match_code "const_int")
 178        (match_test "(unsigned HOST_WIDE_INT) INTVAL (op) <= 4")))
 179
 180 ;; The imm2 field is a 2-bit field that only accepts immediates in the
 181 ;; range 0..3.
 182 (define_predicate "aarch64_imm2"
 183   (and (match_code "const_int")
 184        (match_test "UINTVAL (op) <= 3")))
 185
 186 ;; The imm3 field is a 3-bit field that only accepts immediates in the
 187 ;; range 0..7.
 188 (define_predicate "aarch64_lane_imm3"
 189   (and (match_code "const_int")
 190        (match_test "UINTVAL (op) <= 7")))
 191
 192 ;; An immediate that fits into 24 bits.
 193 (define_predicate "aarch64_imm24"
 194   (and (match_code "const_int")
 195        (match_test "IN_RANGE (UINTVAL (op), 0, 0xffffff)")))
 196
 197 (define_predicate "aarch64_pwr_imm3"
 198   (and (match_code "const_int")
 199        (match_test "INTVAL (op) != 0
 200                     && (unsigned) exact_log2 (INTVAL (op)) <= 4")))
 201
 202 (define_predicate "aarch64_pwr_2_si"
 203   (and (match_code "const_int")
 204        (match_test "INTVAL (op) != 0
 205                     && (unsigned) exact_log2 (INTVAL (op)) < 32")))
 206
 207 (define_predicate "aarch64_pwr_2_di"
 208   (and (match_code "const_int")
 209        (match_test "INTVAL (op) != 0
 210                     && (unsigned) exact_log2 (INTVAL (op)) < 64")))
 211
 212 (define_predicate "aarch64_mem_pair_offset"
 213   (and (match_code "const_int")
 214        (match_test "aarch64_offset_7bit_signed_scaled_p (mode, INTVAL (op))")))
 215
 216 (define_predicate "aarch64_mem_pair_operand"
 217   (and (match_code "mem")
 218        (match_test "aarch64_legitimate_address_p (mode, XEXP (op, 0), false,
 219                                                   ADDR_QUERY_LDP_STP)")))
 220
 221 ;; Used for storing two 64-bit values in an AdvSIMD register using an STP
 222 ;; as a 128-bit vec_concat.
 223 (define_predicate "aarch64_mem_pair_lanes_operand"
 224   (and (match_code "mem")
 225        (match_test "aarch64_legitimate_address_p (DFmode, XEXP (op, 0), 1,
 226                                                   ADDR_QUERY_LDP_STP)")))
 227
 228 (define_predicate "aarch64_prefetch_operand"
 229   (match_test "aarch64_address_valid_for_prefetch_p (op, false)"))
 230
 231 (define_predicate "aarch64_valid_symref"
 232   (match_code "const, symbol_ref, label_ref")
 233 {
 234   return (aarch64_classify_symbolic_expression (op)
 235           != SYMBOL_FORCE_TO_MEM);
 236 })
 237
 238 (define_predicate "aarch64_tls_ie_symref"
 239   (match_code "const, symbol_ref, label_ref")
 240 {
 241   switch (GET_CODE (op))
 242     {
 243     case CONST:
 244       op = XEXP (op, 0);
 245       if (GET_CODE (op) != PLUS
 246           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
 247           || GET_CODE (XEXP (op, 1)) != CONST_INT)
 248         return false;
 249       op = XEXP (op, 0);
 250       /* FALLTHRU */
 251
 252     case SYMBOL_REF:
 253       return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_INITIAL_EXEC;
 254
 255     default:
 256       gcc_unreachable ();
 257     }
 258 })
 259
 260 (define_predicate "aarch64_tls_le_symref"
 261   (match_code "const, symbol_ref, label_ref")
 262 {
 263   switch (GET_CODE (op))
 264     {
 265     case CONST:
 266       op = XEXP (op, 0);
 267       if (GET_CODE (op) != PLUS
 268           || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
 269           || GET_CODE (XEXP (op, 1)) != CONST_INT)
 270         return false;
 271       op = XEXP (op, 0);
 272       /* FALLTHRU */
 273
 274     case SYMBOL_REF:
 275       return SYMBOL_REF_TLS_MODEL (op) == TLS_MODEL_LOCAL_EXEC;
 276
 277     default:
 278       gcc_unreachable ();
 279     }
 280 })
 281
 282 (define_predicate "aarch64_mov_operand"
 283   (and (match_code "reg,subreg,mem,const,const_int,symbol_ref,label_ref,high,
 284                     const_poly_int,const_vector")
 285        (ior (match_operand 0 "register_operand")
 286             (ior (match_operand 0 "memory_operand")
 287                  (match_test "aarch64_mov_operand_p (op, mode)")))))
 288
 289 (define_predicate "aarch64_nonmemory_operand"
 290   (and (match_code "reg,subreg,const,const_int,symbol_ref,label_ref,high,
 291                     const_poly_int,const_vector")
 292        (ior (match_operand 0 "register_operand")
 293             (match_test "aarch64_mov_operand_p (op, mode)"))))
 294
 295 (define_predicate "aarch64_movti_operand"
 296   (ior (match_operand 0 "register_operand")
 297        (match_operand 0 "memory_operand")
 298        (and (match_operand 0 "const_scalar_int_operand")
 299             (match_test "aarch64_mov128_immediate (op)"))))
 300
 301 (define_predicate "aarch64_reg_or_imm"
 302   (ior (match_operand 0 "register_operand")
 303        (match_operand 0 "const_scalar_int_operand")))
 304
 305 ;; True for integer comparisons and for FP comparisons other than LTGT or UNEQ.
 306 (define_special_predicate "aarch64_comparison_operator"
 307   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 308                ordered,unlt,unle,unge,ungt"))
 309
 310 ;; Same as aarch64_comparison_operator but don't ignore the mode.
 311 ;; RTL SET operations require their operands source and destination have
 312 ;; the same modes, so we can't ignore the modes there.  See PR target/69161.
 313 (define_predicate "aarch64_comparison_operator_mode"
 314   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 315                ordered,unlt,unle,unge,ungt"))
 316
 317 (define_special_predicate "aarch64_comparison_operation"
 318   (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,unordered,
 319                ordered,unlt,unle,unge,ungt")
 320 {
 321   if (XEXP (op, 1) != const0_rtx)
 322     return false;
 323   rtx op0 = XEXP (op, 0);
 324   if (!REG_P (op0) || REGNO (op0) != CC_REGNUM)
 325     return false;
 326   return aarch64_get_condition_code (op) >= 0;
 327 })
 328
 329 (define_special_predicate "aarch64_equality_operator"
 330   (match_code "eq,ne"))
 331
 332 (define_special_predicate "aarch64_carry_operation"
 333   (match_code "ne,geu")
 334 {
 335   if (XEXP (op, 1) != const0_rtx)
 336     return false;
 337   machine_mode ccmode = (GET_CODE (op) == NE ? CC_Cmode : CCmode);
 338   rtx op0 = XEXP (op, 0);
 339   return REG_P (op0) && REGNO (op0) == CC_REGNUM && GET_MODE (op0) == ccmode;
 340 })
 341
 342 (define_special_predicate "aarch64_borrow_operation"
 343   (match_code "eq,ltu")
 344 {
 345   if (XEXP (op, 1) != const0_rtx)
 346     return false;
 347   machine_mode ccmode = (GET_CODE (op) == EQ ? CC_Cmode : CCmode);
 348   rtx op0 = XEXP (op, 0);
 349   return REG_P (op0) && REGNO (op0) == CC_REGNUM && GET_MODE (op0) == ccmode;
 350 })
 351
 352 ;; True if the operand is memory reference suitable for a load/store exclusive.
 353 (define_predicate "aarch64_sync_memory_operand"
 354   (and (match_operand 0 "memory_operand")
 355        (match_code "reg" "0")))
 356
 357 ;; Predicates for parallel expanders based on mode.
 358 (define_special_predicate "vect_par_cnst_hi_half"
 359   (match_code "parallel")
 360 {
 361   return aarch64_simd_check_vect_par_cnst_half (op, mode, true);
 362 })
 363
 364 (define_special_predicate "vect_par_cnst_lo_half"
 365   (match_code "parallel")
 366 {
 367   return aarch64_simd_check_vect_par_cnst_half (op, mode, false);
 368 })
 369
 370 (define_special_predicate "aarch64_simd_lshift_imm"
 371   (match_code "const,const_vector")
 372 {
 373   return aarch64_simd_shift_imm_p (op, mode, true);
 374 })
 375
 376 (define_special_predicate "aarch64_simd_rshift_imm"
 377   (match_code "const,const_vector")
 378 {
 379   return aarch64_simd_shift_imm_p (op, mode, false);
 380 })
 381
 382 (define_predicate "aarch64_simd_imm_zero"
 383   (and (match_code "const,const_vector")
 384        (match_test "op == CONST0_RTX (GET_MODE (op))")))
 385
 386 (define_predicate "aarch64_simd_or_scalar_imm_zero"
 387   (and (match_code "const_int,const_double,const,const_vector")
 388        (match_test "op == CONST0_RTX (GET_MODE (op))")))
 389
 390 (define_predicate "aarch64_simd_imm_minus_one"
 391   (and (match_code "const,const_vector")
 392        (match_test "op == CONSTM1_RTX (GET_MODE (op))")))
 393
 394 (define_predicate "aarch64_simd_reg_or_zero"
 395   (and (match_code "reg,subreg,const_int,const_double,const,const_vector")
 396        (ior (match_operand 0 "register_operand")
 397             (match_test "op == const0_rtx")
 398             (match_operand 0 "aarch64_simd_or_scalar_imm_zero"))))
 399
 400 (define_predicate "aarch64_simd_struct_operand"
 401   (and (match_code "mem")
 402        (match_test "TARGET_SIMD && aarch64_simd_mem_operand_p (op)")))
 403
 404 ;; Like general_operand but allow only valid SIMD addressing modes.
 405 (define_predicate "aarch64_simd_general_operand"
 406   (and (match_operand 0 "general_operand")
 407        (match_test "!MEM_P (op)
 408                     || GET_CODE (XEXP (op, 0)) == POST_INC
 409                     || GET_CODE (XEXP (op, 0)) == REG")))
 410
 411 ;; Like nonimmediate_operand but allow only valid SIMD addressing modes.
 412 (define_predicate "aarch64_simd_nonimmediate_operand"
 413   (and (match_operand 0 "nonimmediate_operand")
 414        (match_test "!MEM_P (op)
 415                     || GET_CODE (XEXP (op, 0)) == POST_INC
 416                     || GET_CODE (XEXP (op, 0)) == REG")))
 417
 418 ;; Predicates used by the various SIMD shift operations.  These
 419 ;; fall in to 3 categories.
 420 ;;   Shifts with a range 0-(bit_size - 1) (aarch64_simd_shift_imm)
 421 ;;   Shifts with a range 1-bit_size (aarch64_simd_shift_imm_offset)
 422 ;;   Shifts with a range 0-bit_size (aarch64_simd_shift_imm_bitsize)
 423 (define_predicate "aarch64_simd_shift_imm_qi"
 424   (and (match_code "const_int")
 425        (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
 426
 427 (define_predicate "aarch64_simd_shift_imm_hi"
 428   (and (match_code "const_int")
 429        (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
 430
 431 (define_predicate "aarch64_simd_shift_imm_si"
 432   (and (match_code "const_int")
 433        (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
 434
 435 (define_predicate "aarch64_simd_shift_imm_di"
 436   (and (match_code "const_int")
 437        (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
 438
 439 (define_predicate "aarch64_simd_shift_imm_offset_qi"
 440   (and (match_code "const_int")
 441        (match_test "IN_RANGE (INTVAL (op), 1, 8)")))
 442
 443 (define_predicate "aarch64_simd_shift_imm_offset_hi"
 444   (and (match_code "const_int")
 445        (match_test "IN_RANGE (INTVAL (op), 1, 16)")))
 446
 447 (define_predicate "aarch64_simd_shift_imm_offset_si"
 448   (and (match_code "const_int")
 449        (match_test "IN_RANGE (INTVAL (op), 1, 32)")))
 450
 451 (define_predicate "aarch64_simd_shift_imm_offset_di"
 452   (and (match_code "const_int")
 453        (match_test "IN_RANGE (INTVAL (op), 1, 64)")))
 454
 455 (define_predicate "aarch64_simd_shift_imm_bitsize_qi"
 456   (and (match_code "const_int")
 457        (match_test "IN_RANGE (INTVAL (op), 0, 8)")))
 458
 459 (define_predicate "aarch64_simd_shift_imm_bitsize_hi"
 460   (and (match_code "const_int")
 461        (match_test "IN_RANGE (INTVAL (op), 0, 16)")))
 462
 463 (define_predicate "aarch64_simd_shift_imm_bitsize_si"
 464   (and (match_code "const_int")
 465        (match_test "IN_RANGE (INTVAL (op), 0, 32)")))
 466
 467 (define_predicate "aarch64_simd_shift_imm_bitsize_di"
 468   (and (match_code "const_int")
 469        (match_test "IN_RANGE (INTVAL (op), 0, 64)")))
 470
 471 (define_predicate "aarch64_constant_pool_symref"
 472    (and (match_code "symbol_ref")
 473         (match_test "CONSTANT_POOL_ADDRESS_P (op)")))
 474
 475 (define_predicate "aarch64_constant_vector_operand"
 476   (match_code "const,const_vector"))
 477
 478 (define_predicate "aarch64_sve_ld1r_operand"
 479   (and (match_operand 0 "memory_operand")
 480        (match_test "aarch64_sve_ld1r_operand_p (op)")))
 481
 482 ;; Like memory_operand, but restricted to addresses that are valid for
 483 ;; SVE LDR and STR instructions.
 484 (define_predicate "aarch64_sve_ldr_operand"
 485   (and (match_code "mem")
 486        (match_test "aarch64_sve_ldr_operand_p (op)")))
 487
 488 (define_predicate "aarch64_sve_nonimmediate_operand"
 489   (ior (match_operand 0 "register_operand")
 490        (match_operand 0 "aarch64_sve_ldr_operand")))
 491
 492 (define_predicate "aarch64_sve_general_operand"
 493   (and (match_code "reg,subreg,mem,const,const_vector")
 494        (ior (match_operand 0 "register_operand")
 495             (match_operand 0 "aarch64_sve_ldr_operand")
 496             (match_test "aarch64_mov_operand_p (op, mode)"))))
 497
 498 (define_predicate "aarch64_sve_struct_memory_operand"
 499   (and (match_code "mem")
 500        (match_test "aarch64_sve_struct_memory_operand_p (op)")))
 501
 502 (define_predicate "aarch64_sve_struct_nonimmediate_operand"
 503   (ior (match_operand 0 "register_operand")
 504        (match_operand 0 "aarch64_sve_struct_memory_operand")))
 505
 506 ;; Doesn't include immediates, since those are handled by the move
 507 ;; patterns instead.
 508 (define_predicate "aarch64_sve_dup_operand"
 509   (ior (match_operand 0 "register_operand")
 510        (match_operand 0 "aarch64_sve_ld1r_operand")))
 511
 512 (define_predicate "aarch64_sve_arith_immediate"
 513   (and (match_code "const,const_vector")
 514        (match_test "aarch64_sve_arith_immediate_p (op, false)")))
 515
 516 (define_predicate "aarch64_sve_sub_arith_immediate"
 517   (and (match_code "const,const_vector")
 518        (match_test "aarch64_sve_arith_immediate_p (op, true)")))
 519
 520 (define_predicate "aarch64_sve_inc_dec_immediate"
 521   (and (match_code "const,const_vector")
 522        (match_test "aarch64_sve_inc_dec_immediate_p (op)")))
 523
 524 (define_predicate "aarch64_sve_logical_immediate"
 525   (and (match_code "const,const_vector")
 526        (match_test "aarch64_sve_bitmask_immediate_p (op)")))
 527
 528 (define_predicate "aarch64_sve_mul_immediate"
 529   (and (match_code "const,const_vector")
 530        (match_test "aarch64_const_vec_all_same_in_range_p (op, -128, 127)")))
 531
 532 (define_predicate "aarch64_sve_dup_immediate"
 533   (and (match_code "const,const_vector")
 534        (match_test "aarch64_sve_dup_immediate_p (op)")))
 535
 536 (define_predicate "aarch64_sve_cmp_vsc_immediate"
 537   (and (match_code "const,const_vector")
 538        (match_test "aarch64_sve_cmp_immediate_p (op, true)")))
 539
 540 (define_predicate "aarch64_sve_cmp_vsd_immediate"
 541   (and (match_code "const,const_vector")
 542        (match_test "aarch64_sve_cmp_immediate_p (op, false)")))
 543
 544 (define_predicate "aarch64_sve_index_immediate"
 545   (and (match_code "const_int")
 546        (match_test "aarch64_sve_index_immediate_p (op)")))
 547
 548 (define_predicate "aarch64_sve_float_arith_immediate"
 549   (and (match_code "const,const_vector")
 550        (match_test "aarch64_sve_float_arith_immediate_p (op, false)")))
 551
 552 (define_predicate "aarch64_sve_float_arith_with_sub_immediate"
 553   (and (match_code "const,const_vector")
 554        (match_test "aarch64_sve_float_arith_immediate_p (op, true)")))
 555
 556 (define_predicate "aarch64_sve_float_mul_immediate"
 557   (and (match_code "const,const_vector")
 558        (match_test "aarch64_sve_float_mul_immediate_p (op)")))
 559
 560 (define_predicate "aarch64_sve_arith_operand"
 561   (ior (match_operand 0 "register_operand")
 562        (match_operand 0 "aarch64_sve_arith_immediate")))
 563
 564 (define_predicate "aarch64_sve_add_operand"
 565   (ior (match_operand 0 "aarch64_sve_arith_operand")
 566        (match_operand 0 "aarch64_sve_sub_arith_immediate")
 567        (match_operand 0 "aarch64_sve_inc_dec_immediate")))
 568
 569 (define_predicate "aarch64_sve_logical_operand"
 570   (ior (match_operand 0 "register_operand")
 571        (match_operand 0 "aarch64_sve_logical_immediate")))
 572
 573 (define_predicate "aarch64_sve_lshift_operand"
 574   (ior (match_operand 0 "register_operand")
 575        (match_operand 0 "aarch64_simd_lshift_imm")))
 576
 577 (define_predicate "aarch64_sve_rshift_operand"
 578   (ior (match_operand 0 "register_operand")
 579        (match_operand 0 "aarch64_simd_rshift_imm")))
 580
 581 (define_predicate "aarch64_sve_mul_operand"
 582   (ior (match_operand 0 "register_operand")
 583        (match_operand 0 "aarch64_sve_mul_immediate")))
 584
 585 (define_predicate "aarch64_sve_cmp_vsc_operand"
 586   (ior (match_operand 0 "register_operand")
 587        (match_operand 0 "aarch64_sve_cmp_vsc_immediate")))
 588
 589 (define_predicate "aarch64_sve_cmp_vsd_operand"
 590   (ior (match_operand 0 "register_operand")
 591        (match_operand 0 "aarch64_sve_cmp_vsd_immediate")))
 592
 593 (define_predicate "aarch64_sve_index_operand"
 594   (ior (match_operand 0 "register_operand")
 595        (match_operand 0 "aarch64_sve_index_immediate")))
 596
 597 (define_predicate "aarch64_sve_float_arith_operand"
 598   (ior (match_operand 0 "register_operand")
 599        (match_operand 0 "aarch64_sve_float_arith_immediate")))
 600
 601 (define_predicate "aarch64_sve_float_arith_with_sub_operand"
 602   (ior (match_operand 0 "aarch64_sve_float_arith_operand")
 603        (match_operand 0 "aarch64_sve_float_arith_with_sub_immediate")))
 604
 605 (define_predicate "aarch64_sve_float_mul_operand"
 606   (ior (match_operand 0 "register_operand")
 607        (match_operand 0 "aarch64_sve_float_mul_immediate")))
 608
 609 (define_predicate "aarch64_sve_vec_perm_operand"
 610   (ior (match_operand 0 "register_operand")
 611        (match_operand 0 "aarch64_constant_vector_operand")))
 612
 613 (define_predicate "aarch64_gather_scale_operand_w"
 614   (and (match_code "const_int")
 615        (match_test "INTVAL (op) == 1 || INTVAL (op) == 4")))
 616
 617 (define_predicate "aarch64_gather_scale_operand_d"
 618   (and (match_code "const_int")
 619        (match_test "INTVAL (op) == 1 || INTVAL (op) == 8")))
 620
 621 ;; A special predicate that doesn't match a particular mode.
 622 (define_special_predicate "aarch64_any_register_operand"
 623   (match_code "reg"))