1 ;; Predicate definitions for IA-32 and x86-64.
2 ;; Copyright (C) 2004-2013 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return true if OP is either a i387 or SSE fp register.
21 (define_predicate "any_fp_register_operand"
22 (and (match_code "reg")
23 (match_test "ANY_FP_REGNO_P (REGNO (op))")))
25 ;; Return true if OP is an i387 fp register.
26 (define_predicate "fp_register_operand"
27 (and (match_code "reg")
28 (match_test "STACK_REGNO_P (REGNO (op))")))
30 ;; Return true if OP is a non-fp register_operand.
31 (define_predicate "register_and_not_any_fp_reg_operand"
32 (and (match_code "reg")
33 (not (match_test "ANY_FP_REGNO_P (REGNO (op))"))))
35 ;; Return true if OP is a register operand other than an i387 fp register.
36 (define_predicate "register_and_not_fp_reg_operand"
37 (and (match_code "reg")
38 (not (match_test "STACK_REGNO_P (REGNO (op))"))))
40 ;; True if the operand is an MMX register.
41 (define_predicate "mmx_reg_operand"
42 (and (match_code "reg")
43 (match_test "MMX_REGNO_P (REGNO (op))")))
45 ;; True if the operand is an SSE register.
46 (define_predicate "sse_reg_operand"
47 (and (match_code "reg")
48 (match_test "SSE_REGNO_P (REGNO (op))")))
50 ;; True if the operand is a Q_REGS class register.
51 (define_predicate "q_regs_operand"
52 (match_operand 0 "register_operand")
54 if (GET_CODE (op) == SUBREG)
56 return ANY_QI_REG_P (op);
59 ;; Match an SI or HImode register for a zero_extract.
60 (define_special_predicate "ext_register_operand"
61 (match_operand 0 "register_operand")
63 if ((!TARGET_64BIT || GET_MODE (op) != DImode)
64 && GET_MODE (op) != SImode && GET_MODE (op) != HImode)
66 if (GET_CODE (op) == SUBREG)
69 /* Be careful to accept only registers having upper parts. */
71 && (REGNO (op) > LAST_VIRTUAL_REGISTER || REGNO (op) <= BX_REG));
74 ;; Match nonimmediate operands, but exclude memory operands on 64bit targets.
75 (define_predicate "nonimmediate_x64nomem_operand"
76 (if_then_else (match_test "TARGET_64BIT")
77 (match_operand 0 "register_operand")
78 (match_operand 0 "nonimmediate_operand")))
80 ;; Match general operands, but exclude memory operands on 64bit targets.
81 (define_predicate "general_x64nomem_operand"
82 (if_then_else (match_test "TARGET_64BIT")
83 (match_operand 0 "nonmemory_operand")
84 (match_operand 0 "general_operand")))
86 ;; Return true if op is the AX register.
87 (define_predicate "ax_reg_operand"
88 (and (match_code "reg")
89 (match_test "REGNO (op) == AX_REG")))
91 ;; Return true if op is the flags register.
92 (define_predicate "flags_reg_operand"
93 (and (match_code "reg")
94 (match_test "REGNO (op) == FLAGS_REG")))
96 ;; Return true if op is one of QImode registers: %[abcd][hl].
97 (define_predicate "QIreg_operand"
98 (match_test "QI_REG_P (op)"))
100 ;; Return true if op is a QImode register operand other than
102 (define_predicate "ext_QIreg_operand"
103 (and (match_code "reg")
104 (match_test "TARGET_64BIT")
105 (match_test "REGNO (op) > BX_REG")))
107 ;; Return true if VALUE can be stored in a sign extended immediate field.
108 (define_predicate "x86_64_immediate_operand"
109 (match_code "const_int,symbol_ref,label_ref,const")
112 return immediate_operand (op, mode);
114 switch (GET_CODE (op))
117 /* CONST_DOUBLES never match, since HOST_BITS_PER_WIDE_INT is known
118 to be at least 32 and this all acceptable constants are
119 represented as CONST_INT. */
120 if (HOST_BITS_PER_WIDE_INT == 32)
124 HOST_WIDE_INT val = trunc_int_for_mode (INTVAL (op), DImode);
125 return trunc_int_for_mode (val, SImode) == val;
130 /* For certain code models, the symbolic references are known to fit.
131 in CM_SMALL_PIC model we know it fits if it is local to the shared
132 library. Don't count TLS SYMBOL_REFs here, since they should fit
133 only if inside of UNSPEC handled below. */
134 /* TLS symbols are not constant. */
135 if (SYMBOL_REF_TLS_MODEL (op))
137 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL
138 || (ix86_cmodel == CM_MEDIUM && !SYMBOL_REF_FAR_ADDR_P (op)));
141 /* For certain code models, the code is near as well. */
142 return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM
143 || ix86_cmodel == CM_KERNEL);
146 /* We also may accept the offsetted memory references in certain
148 if (GET_CODE (XEXP (op, 0)) == UNSPEC)
149 switch (XINT (XEXP (op, 0), 1))
151 case UNSPEC_GOTPCREL:
153 case UNSPEC_GOTNTPOFF:
160 if (GET_CODE (XEXP (op, 0)) == PLUS)
162 rtx op1 = XEXP (XEXP (op, 0), 0);
163 rtx op2 = XEXP (XEXP (op, 0), 1);
164 HOST_WIDE_INT offset;
166 if (ix86_cmodel == CM_LARGE)
168 if (!CONST_INT_P (op2))
170 offset = trunc_int_for_mode (INTVAL (op2), DImode);
171 switch (GET_CODE (op1))
174 /* TLS symbols are not constant. */
175 if (SYMBOL_REF_TLS_MODEL (op1))
177 /* For CM_SMALL assume that latest object is 16MB before
178 end of 31bits boundary. We may also accept pretty
179 large negative constants knowing that all objects are
180 in the positive half of address space. */
181 if ((ix86_cmodel == CM_SMALL
182 || (ix86_cmodel == CM_MEDIUM
183 && !SYMBOL_REF_FAR_ADDR_P (op1)))
184 && offset < 16*1024*1024
185 && trunc_int_for_mode (offset, SImode) == offset)
187 /* For CM_KERNEL we know that all object resist in the
188 negative half of 32bits address space. We may not
189 accept negative offsets, since they may be just off
190 and we may accept pretty large positive ones. */
191 if (ix86_cmodel == CM_KERNEL
193 && trunc_int_for_mode (offset, SImode) == offset)
198 /* These conditions are similar to SYMBOL_REF ones, just the
199 constraints for code models differ. */
200 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
201 && offset < 16*1024*1024
202 && trunc_int_for_mode (offset, SImode) == offset)
204 if (ix86_cmodel == CM_KERNEL
206 && trunc_int_for_mode (offset, SImode) == offset)
211 switch (XINT (op1, 1))
215 if (trunc_int_for_mode (offset, SImode) == offset)
233 ;; Return true if VALUE can be stored in the zero extended immediate field.
234 (define_predicate "x86_64_zext_immediate_operand"
235 (match_code "const_double,const_int,symbol_ref,label_ref,const")
237 switch (GET_CODE (op))
240 if (HOST_BITS_PER_WIDE_INT == 32)
241 return (GET_MODE (op) == VOIDmode && !CONST_DOUBLE_HIGH (op));
246 if (HOST_BITS_PER_WIDE_INT == 32)
247 return INTVAL (op) >= 0;
249 return !(INTVAL (op) & ~(HOST_WIDE_INT) 0xffffffff);
252 /* For certain code models, the symbolic references are known to fit. */
253 /* TLS symbols are not constant. */
254 if (SYMBOL_REF_TLS_MODEL (op))
256 return (ix86_cmodel == CM_SMALL
257 || (ix86_cmodel == CM_MEDIUM
258 && !SYMBOL_REF_FAR_ADDR_P (op)));
261 /* For certain code models, the code is near as well. */
262 return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM;
265 /* We also may accept the offsetted memory references in certain
267 if (GET_CODE (XEXP (op, 0)) == PLUS)
269 rtx op1 = XEXP (XEXP (op, 0), 0);
270 rtx op2 = XEXP (XEXP (op, 0), 1);
272 if (ix86_cmodel == CM_LARGE)
274 switch (GET_CODE (op1))
277 /* TLS symbols are not constant. */
278 if (SYMBOL_REF_TLS_MODEL (op1))
280 /* For small code model we may accept pretty large positive
281 offsets, since one bit is available for free. Negative
282 offsets are limited by the size of NULL pointer area
283 specified by the ABI. */
284 if ((ix86_cmodel == CM_SMALL
285 || (ix86_cmodel == CM_MEDIUM
286 && !SYMBOL_REF_FAR_ADDR_P (op1)))
288 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
289 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
291 /* ??? For the kernel, we may accept adjustment of
292 -0x10000000, since we know that it will just convert
293 negative address space to positive, but perhaps this
294 is not worthwhile. */
298 /* These conditions are similar to SYMBOL_REF ones, just the
299 constraints for code models differ. */
300 if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM)
302 && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000
303 && trunc_int_for_mode (INTVAL (op2), SImode) == INTVAL (op2))
319 ;; Return true if OP is general operand representable on x86_64.
320 (define_predicate "x86_64_general_operand"
321 (if_then_else (match_test "TARGET_64BIT")
322 (ior (match_operand 0 "nonimmediate_operand")
323 (match_operand 0 "x86_64_immediate_operand"))
324 (match_operand 0 "general_operand")))
326 ;; Return true if OP is representable on x86_64 as zero-extended operand.
327 ;; This predicate is used in zero-extending conversion operations that
328 ;; require non-VOIDmode immediate operands.
329 (define_predicate "x86_64_zext_operand"
330 (if_then_else (match_test "TARGET_64BIT")
331 (ior (match_operand 0 "nonimmediate_operand")
332 (and (match_operand 0 "x86_64_zext_immediate_operand")
333 (match_test "GET_MODE (op) != VOIDmode")))
334 (match_operand 0 "nonimmediate_operand")))
336 ;; Return true if OP is general operand representable on x86_64
337 ;; as either sign extended or zero extended constant.
338 (define_predicate "x86_64_szext_general_operand"
339 (if_then_else (match_test "TARGET_64BIT")
340 (ior (match_operand 0 "nonimmediate_operand")
341 (match_operand 0 "x86_64_immediate_operand")
342 (match_operand 0 "x86_64_zext_immediate_operand"))
343 (match_operand 0 "general_operand")))
345 ;; Return true if OP is nonmemory operand representable on x86_64.
346 (define_predicate "x86_64_nonmemory_operand"
347 (if_then_else (match_test "TARGET_64BIT")
348 (ior (match_operand 0 "register_operand")
349 (match_operand 0 "x86_64_immediate_operand"))
350 (match_operand 0 "nonmemory_operand")))
352 ;; Return true if OP is nonmemory operand representable on x86_64.
353 (define_predicate "x86_64_szext_nonmemory_operand"
354 (if_then_else (match_test "TARGET_64BIT")
355 (ior (match_operand 0 "register_operand")
356 (match_operand 0 "x86_64_immediate_operand")
357 (match_operand 0 "x86_64_zext_immediate_operand"))
358 (match_operand 0 "nonmemory_operand")))
360 ;; Return true when operand is PIC expression that can be computed by lea
362 (define_predicate "pic_32bit_operand"
363 (match_code "const,symbol_ref,label_ref")
368 /* Rule out relocations that translate into 64bit constants. */
369 if (TARGET_64BIT && GET_CODE (op) == CONST)
372 if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
374 if (GET_CODE (op) == UNSPEC
375 && (XINT (op, 1) == UNSPEC_GOTOFF
376 || XINT (op, 1) == UNSPEC_GOT))
380 return symbolic_operand (op, mode);
383 ;; Return true if OP is nonmemory operand acceptable by movabs patterns.
384 (define_predicate "x86_64_movabs_operand"
385 (and (match_operand 0 "nonmemory_operand")
386 (not (match_operand 0 "pic_32bit_operand"))))
388 ;; Return true if OP is either a symbol reference or a sum of a symbol
389 ;; reference and a constant.
390 (define_predicate "symbolic_operand"
391 (match_code "symbol_ref,label_ref,const")
393 switch (GET_CODE (op))
401 if (GET_CODE (op) == SYMBOL_REF
402 || GET_CODE (op) == LABEL_REF
403 || (GET_CODE (op) == UNSPEC
404 && (XINT (op, 1) == UNSPEC_GOT
405 || XINT (op, 1) == UNSPEC_GOTOFF
406 || XINT (op, 1) == UNSPEC_PCREL
407 || XINT (op, 1) == UNSPEC_GOTPCREL)))
409 if (GET_CODE (op) != PLUS
410 || !CONST_INT_P (XEXP (op, 1)))
414 if (GET_CODE (op) == SYMBOL_REF
415 || GET_CODE (op) == LABEL_REF)
417 /* Only @GOTOFF gets offsets. */
418 if (GET_CODE (op) != UNSPEC
419 || XINT (op, 1) != UNSPEC_GOTOFF)
422 op = XVECEXP (op, 0, 0);
423 if (GET_CODE (op) == SYMBOL_REF
424 || GET_CODE (op) == LABEL_REF)
433 ;; Return true if OP is a symbolic operand that resolves locally.
434 (define_predicate "local_symbolic_operand"
435 (match_code "const,label_ref,symbol_ref")
437 if (GET_CODE (op) == CONST
438 && GET_CODE (XEXP (op, 0)) == PLUS
439 && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
440 op = XEXP (XEXP (op, 0), 0);
442 if (GET_CODE (op) == LABEL_REF)
445 if (GET_CODE (op) != SYMBOL_REF)
448 if (SYMBOL_REF_TLS_MODEL (op))
451 /* Dll-imported symbols are always external. */
452 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
454 if (SYMBOL_REF_LOCAL_P (op))
457 /* There is, however, a not insubstantial body of code in the rest of
458 the compiler that assumes it can just stick the results of
459 ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */
460 /* ??? This is a hack. Should update the body of the compiler to
461 always create a DECL an invoke targetm.encode_section_info. */
462 if (strncmp (XSTR (op, 0), internal_label_prefix,
463 internal_label_prefix_len) == 0)
469 ;; Test for a legitimate @GOTOFF operand.
471 ;; VxWorks does not impose a fixed gap between segments; the run-time
472 ;; gap can be different from the object-file gap. We therefore can't
473 ;; use @GOTOFF unless we are absolutely sure that the symbol is in the
474 ;; same segment as the GOT. Unfortunately, the flexibility of linker
475 ;; scripts means that we can't be sure of that in general, so assume
476 ;; that @GOTOFF is never valid on VxWorks.
477 (define_predicate "gotoff_operand"
478 (and (not (match_test "TARGET_VXWORKS_RTP"))
479 (match_operand 0 "local_symbolic_operand")))
481 ;; Test for various thread-local symbols.
482 (define_special_predicate "tls_symbolic_operand"
483 (and (match_code "symbol_ref")
484 (match_test "SYMBOL_REF_TLS_MODEL (op)")))
486 (define_special_predicate "tls_modbase_operand"
487 (and (match_code "symbol_ref")
488 (match_test "op == ix86_tls_module_base ()")))
490 ;; Test for a pc-relative call operand
491 (define_predicate "constant_call_address_operand"
492 (match_code "symbol_ref")
494 if (ix86_cmodel == CM_LARGE || ix86_cmodel == CM_LARGE_PIC)
496 if (TARGET_DLLIMPORT_DECL_ATTRIBUTES && SYMBOL_REF_DLLIMPORT_P (op))
501 ;; P6 processors will jump to the address after the decrement when %esp
502 ;; is used as a call operand, so they will execute return address as a code.
503 ;; See Pentium Pro errata 70, Pentium 2 errata A33 and Pentium 3 errata E17.
505 (define_predicate "call_register_no_elim_operand"
506 (match_operand 0 "register_operand")
508 if (GET_CODE (op) == SUBREG)
509 op = SUBREG_REG (op);
511 if (!TARGET_64BIT && op == stack_pointer_rtx)
514 return register_no_elim_operand (op, mode);
517 ;; True for any non-virtual or eliminable register. Used in places where
518 ;; instantiation of such a register may cause the pattern to not be recognized.
519 (define_predicate "register_no_elim_operand"
520 (match_operand 0 "register_operand")
522 if (GET_CODE (op) == SUBREG)
523 op = SUBREG_REG (op);
524 return !(op == arg_pointer_rtx
525 || op == frame_pointer_rtx
526 || IN_RANGE (REGNO (op),
527 FIRST_PSEUDO_REGISTER, LAST_VIRTUAL_REGISTER));
530 ;; Similarly, but include the stack pointer. This is used to prevent esp
531 ;; from being used as an index reg.
532 (define_predicate "index_register_operand"
533 (match_operand 0 "register_operand")
535 if (GET_CODE (op) == SUBREG)
536 op = SUBREG_REG (op);
537 if (reload_in_progress || reload_completed)
538 return REG_OK_FOR_INDEX_STRICT_P (op);
540 return REG_OK_FOR_INDEX_NONSTRICT_P (op);
543 ;; Return false if this is any eliminable register. Otherwise general_operand.
544 (define_predicate "general_no_elim_operand"
545 (if_then_else (match_code "reg,subreg")
546 (match_operand 0 "register_no_elim_operand")
547 (match_operand 0 "general_operand")))
549 ;; Return false if this is any eliminable register. Otherwise
550 ;; register_operand or a constant.
551 (define_predicate "nonmemory_no_elim_operand"
552 (ior (match_operand 0 "register_no_elim_operand")
553 (match_operand 0 "immediate_operand")))
555 ;; Test for a valid operand for indirect branch.
556 (define_predicate "indirect_branch_operand"
557 (ior (match_operand 0 "register_operand")
558 (and (not (match_test "TARGET_X32"))
559 (match_operand 0 "memory_operand"))))
561 ;; Test for a valid operand for a call instruction.
562 ;; Allow constant call address operands in Pmode only.
563 (define_special_predicate "call_insn_operand"
564 (ior (match_test "constant_call_address_operand
565 (op, mode == VOIDmode ? mode : Pmode)")
566 (match_operand 0 "call_register_no_elim_operand")
567 (and (not (match_test "TARGET_X32"))
568 (match_operand 0 "memory_operand"))))
570 ;; Similarly, but for tail calls, in which we cannot allow memory references.
571 (define_special_predicate "sibcall_insn_operand"
572 (ior (match_test "constant_call_address_operand
573 (op, mode == VOIDmode ? mode : Pmode)")
574 (match_operand 0 "register_no_elim_operand")))
576 ;; Return true if OP is a call from MS ABI to SYSV ABI function.
577 (define_predicate "call_rex64_ms_sysv_operation"
578 (match_code "parallel")
580 unsigned creg_size = ARRAY_SIZE (x86_64_ms_sysv_extra_clobbered_registers);
583 if ((unsigned) XVECLEN (op, 0) != creg_size + 2)
586 for (i = 0; i < creg_size; i++)
588 rtx elt = XVECEXP (op, 0, i+2);
589 enum machine_mode mode;
592 if (GET_CODE (elt) != CLOBBER
593 || GET_CODE (SET_DEST (elt)) != REG)
596 regno = x86_64_ms_sysv_extra_clobbered_registers[i];
597 mode = SSE_REGNO_P (regno) ? TImode : DImode;
599 if (GET_MODE (SET_DEST (elt)) != mode
600 || REGNO (SET_DEST (elt)) != regno)
606 ;; Match exactly zero.
607 (define_predicate "const0_operand"
608 (match_code "const_int,const_double,const_vector")
610 if (mode == VOIDmode)
611 mode = GET_MODE (op);
612 return op == CONST0_RTX (mode);
615 ;; Match one or vector filled with ones.
616 (define_predicate "const1_operand"
617 (match_code "const_int,const_double,const_vector")
619 if (mode == VOIDmode)
620 mode = GET_MODE (op);
621 return op == CONST1_RTX (mode);
624 ;; Match exactly eight.
625 (define_predicate "const8_operand"
626 (and (match_code "const_int")
627 (match_test "INTVAL (op) == 8")))
629 ;; Match exactly 128.
630 (define_predicate "const128_operand"
631 (and (match_code "const_int")
632 (match_test "INTVAL (op) == 128")))
634 ;; Match exactly 0x0FFFFFFFF in anddi as a zero-extension operation
635 (define_predicate "const_32bit_mask"
636 (and (match_code "const_int")
637 (match_test "trunc_int_for_mode (INTVAL (op), DImode)
638 == (HOST_WIDE_INT) 0xffffffff")))
640 ;; Match 2, 4, or 8. Used for leal multiplicands.
641 (define_predicate "const248_operand"
642 (match_code "const_int")
644 HOST_WIDE_INT i = INTVAL (op);
645 return i == 2 || i == 4 || i == 8;
648 ;; Match 1, 2, 4, or 8
649 (define_predicate "const1248_operand"
650 (match_code "const_int")
652 HOST_WIDE_INT i = INTVAL (op);
653 return i == 1 || i == 2 || i == 4 || i == 8;
656 ;; Match 3, 5, or 9. Used for leal multiplicands.
657 (define_predicate "const359_operand"
658 (match_code "const_int")
660 HOST_WIDE_INT i = INTVAL (op);
661 return i == 3 || i == 5 || i == 9;
665 (define_predicate "const_0_to_1_operand"
666 (and (match_code "const_int")
667 (ior (match_test "op == const0_rtx")
668 (match_test "op == const1_rtx"))))
671 (define_predicate "const_0_to_3_operand"
672 (and (match_code "const_int")
673 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
676 (define_predicate "const_0_to_7_operand"
677 (and (match_code "const_int")
678 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
681 (define_predicate "const_0_to_15_operand"
682 (and (match_code "const_int")
683 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
686 (define_predicate "const_0_to_31_operand"
687 (and (match_code "const_int")
688 (match_test "IN_RANGE (INTVAL (op), 0, 31)")))
691 (define_predicate "const_0_to_63_operand"
692 (and (match_code "const_int")
693 (match_test "IN_RANGE (INTVAL (op), 0, 63)")))
696 (define_predicate "const_0_to_255_operand"
697 (and (match_code "const_int")
698 (match_test "IN_RANGE (INTVAL (op), 0, 255)")))
700 ;; Match (0 to 255) * 8
701 (define_predicate "const_0_to_255_mul_8_operand"
702 (match_code "const_int")
704 unsigned HOST_WIDE_INT val = INTVAL (op);
705 return val <= 255*8 && val % 8 == 0;
708 ;; Return true if OP is CONST_INT >= 1 and <= 31 (a valid operand
709 ;; for shift & compare patterns, as shifting by 0 does not change flags).
710 (define_predicate "const_1_to_31_operand"
711 (and (match_code "const_int")
712 (match_test "IN_RANGE (INTVAL (op), 1, 31)")))
714 ;; Return true if OP is CONST_INT >= 1 and <= 63 (a valid operand
715 ;; for 64bit shift & compare patterns, as shifting by 0 does not change flags).
716 (define_predicate "const_1_to_63_operand"
717 (and (match_code "const_int")
718 (match_test "IN_RANGE (INTVAL (op), 1, 63)")))
721 (define_predicate "const_2_to_3_operand"
722 (and (match_code "const_int")
723 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
726 (define_predicate "const_4_to_5_operand"
727 (and (match_code "const_int")
728 (match_test "IN_RANGE (INTVAL (op), 4, 5)")))
731 (define_predicate "const_4_to_7_operand"
732 (and (match_code "const_int")
733 (match_test "IN_RANGE (INTVAL (op), 4, 7)")))
736 (define_predicate "const_6_to_7_operand"
737 (and (match_code "const_int")
738 (match_test "IN_RANGE (INTVAL (op), 6, 7)")))
741 (define_predicate "const_8_to_11_operand"
742 (and (match_code "const_int")
743 (match_test "IN_RANGE (INTVAL (op), 8, 11)")))
746 (define_predicate "const_12_to_15_operand"
747 (and (match_code "const_int")
748 (match_test "IN_RANGE (INTVAL (op), 12, 15)")))
750 ;; True if this is a constant appropriate for an increment or decrement.
751 (define_predicate "incdec_operand"
752 (match_code "const_int")
754 /* On Pentium4, the inc and dec operations causes extra dependency on flag
755 registers, since carry flag is not set. */
756 if (!TARGET_USE_INCDEC && !optimize_insn_for_size_p ())
758 return op == const1_rtx || op == constm1_rtx;
761 ;; True for registers, or 1 or -1. Used to optimize double-word shifts.
762 (define_predicate "reg_or_pm1_operand"
763 (ior (match_operand 0 "register_operand")
764 (and (match_code "const_int")
765 (ior (match_test "op == const1_rtx")
766 (match_test "op == constm1_rtx")))))
768 ;; True if OP is acceptable as operand of DImode shift expander.
769 (define_predicate "shiftdi_operand"
770 (if_then_else (match_test "TARGET_64BIT")
771 (match_operand 0 "nonimmediate_operand")
772 (match_operand 0 "register_operand")))
774 (define_predicate "ashldi_input_operand"
775 (if_then_else (match_test "TARGET_64BIT")
776 (match_operand 0 "nonimmediate_operand")
777 (match_operand 0 "reg_or_pm1_operand")))
779 ;; Return true if OP is a vector load from the constant pool with just
780 ;; the first element nonzero.
781 (define_predicate "zero_extended_scalar_load_operand"
785 op = maybe_get_pool_constant (op);
787 if (!(op && GET_CODE (op) == CONST_VECTOR))
790 n_elts = CONST_VECTOR_NUNITS (op);
792 for (n_elts--; n_elts > 0; n_elts--)
794 rtx elt = CONST_VECTOR_ELT (op, n_elts);
795 if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op))))
801 /* Return true if operand is a vector constant that is all ones. */
802 (define_predicate "vector_all_ones_operand"
803 (match_code "const_vector")
805 int nunits = GET_MODE_NUNITS (mode);
807 if (GET_CODE (op) == CONST_VECTOR
808 && CONST_VECTOR_NUNITS (op) == nunits)
811 for (i = 0; i < nunits; ++i)
813 rtx x = CONST_VECTOR_ELT (op, i);
814 if (x != constm1_rtx)
823 ; Return true when OP is operand acceptable for standard SSE move.
824 (define_predicate "vector_move_operand"
825 (ior (match_operand 0 "nonimmediate_operand")
826 (match_operand 0 "const0_operand")))
828 ;; Return true when OP is either nonimmediate operand, or any
830 (define_predicate "nonimmediate_or_const_vector_operand"
831 (ior (match_operand 0 "nonimmediate_operand")
832 (match_code "const_vector")))
834 ;; Return true when OP is nonimmediate or standard SSE constant.
835 (define_predicate "nonimmediate_or_sse_const_operand"
836 (match_operand 0 "general_operand")
838 if (nonimmediate_operand (op, mode))
840 if (standard_sse_constant_p (op) > 0)
845 ;; Return true if OP is a register or a zero.
846 (define_predicate "reg_or_0_operand"
847 (ior (match_operand 0 "register_operand")
848 (match_operand 0 "const0_operand")))
850 ;; Return true if op if a valid address for LEA, and does not contain
851 ;; a segment override. Defined as a special predicate to allow
852 ;; mode-less const_int operands pass to address_operand.
853 (define_special_predicate "lea_address_operand"
854 (match_operand 0 "address_operand")
856 struct ix86_address parts;
859 ok = ix86_decompose_address (op, &parts);
861 return parts.seg == SEG_DEFAULT;
864 ;; Return true for RTX codes that force SImode address.
865 (define_predicate "SImode_address_operand"
866 (match_code "subreg,zero_extend,and"))
868 ;; Return true if op if a valid base register, displacement or
869 ;; sum of base register and displacement for VSIB addressing.
870 (define_predicate "vsib_address_operand"
871 (match_operand 0 "address_operand")
873 struct ix86_address parts;
877 ok = ix86_decompose_address (op, &parts);
879 if (parts.index || parts.seg != SEG_DEFAULT)
882 /* VSIB addressing doesn't support (%rip). */
883 if (parts.disp && GET_CODE (parts.disp) == CONST)
885 disp = XEXP (parts.disp, 0);
886 if (GET_CODE (disp) == PLUS)
887 disp = XEXP (disp, 0);
888 if (GET_CODE (disp) == UNSPEC)
889 switch (XINT (disp, 1))
891 case UNSPEC_GOTPCREL:
893 case UNSPEC_GOTNTPOFF:
901 (define_predicate "vsib_mem_operator"
904 ;; Return true if the rtx is known to be at least 32 bits aligned.
905 (define_predicate "aligned_operand"
906 (match_operand 0 "general_operand")
908 struct ix86_address parts;
911 /* Registers and immediate operands are always "aligned". */
915 /* All patterns using aligned_operand on memory operands ends up
916 in promoting memory operand to 64bit and thus causing memory mismatch. */
917 if (TARGET_MEMORY_MISMATCH_STALL && !optimize_insn_for_size_p ())
920 /* Don't even try to do any aligned optimizations with volatiles. */
921 if (MEM_VOLATILE_P (op))
924 if (MEM_ALIGN (op) >= 32)
929 /* Pushes and pops are only valid on the stack pointer. */
930 if (GET_CODE (op) == PRE_DEC
931 || GET_CODE (op) == POST_INC)
934 /* Decode the address. */
935 ok = ix86_decompose_address (op, &parts);
938 if (parts.base && GET_CODE (parts.base) == SUBREG)
939 parts.base = SUBREG_REG (parts.base);
940 if (parts.index && GET_CODE (parts.index) == SUBREG)
941 parts.index = SUBREG_REG (parts.index);
943 /* Look for some component that isn't known to be aligned. */
946 if (REGNO_POINTER_ALIGN (REGNO (parts.index)) * parts.scale < 32)
951 if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32)
956 if (!CONST_INT_P (parts.disp)
957 || (INTVAL (parts.disp) & 3))
961 /* Didn't find one -- this must be an aligned address. */
965 ;; Return true if OP is memory operand with a displacement.
966 (define_predicate "memory_displacement_operand"
967 (match_operand 0 "memory_operand")
969 struct ix86_address parts;
972 ok = ix86_decompose_address (XEXP (op, 0), &parts);
974 return parts.disp != NULL_RTX;
977 ;; Return true if OP is memory operand with a displacement only.
978 (define_predicate "memory_displacement_only_operand"
979 (match_operand 0 "memory_operand")
981 struct ix86_address parts;
987 ok = ix86_decompose_address (XEXP (op, 0), &parts);
990 if (parts.base || parts.index)
993 return parts.disp != NULL_RTX;
996 ;; Return true if OP is memory operand which will need zero or
997 ;; one register at most, not counting stack pointer or frame pointer.
998 (define_predicate "cmpxchg8b_pic_memory_operand"
999 (match_operand 0 "memory_operand")
1001 struct ix86_address parts;
1004 if (TARGET_64BIT || !flag_pic)
1007 ok = ix86_decompose_address (XEXP (op, 0), &parts);
1010 if (parts.base && GET_CODE (parts.base) == SUBREG)
1011 parts.base = SUBREG_REG (parts.base);
1012 if (parts.index && GET_CODE (parts.index) == SUBREG)
1013 parts.index = SUBREG_REG (parts.index);
1015 if (parts.base == NULL_RTX
1016 || parts.base == arg_pointer_rtx
1017 || parts.base == frame_pointer_rtx
1018 || parts.base == hard_frame_pointer_rtx
1019 || parts.base == stack_pointer_rtx)
1022 if (parts.index == NULL_RTX
1023 || parts.index == arg_pointer_rtx
1024 || parts.index == frame_pointer_rtx
1025 || parts.index == hard_frame_pointer_rtx
1026 || parts.index == stack_pointer_rtx)
1033 ;; Return true if OP is memory operand that cannot be represented
1034 ;; by the modRM array.
1035 (define_predicate "long_memory_operand"
1036 (and (match_operand 0 "memory_operand")
1037 (match_test "memory_address_length (op, false)")))
1039 ;; Return true if OP is a comparison operator that can be issued by fcmov.
1040 (define_predicate "fcmov_comparison_operator"
1041 (match_operand 0 "comparison_operator")
1043 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1044 enum rtx_code code = GET_CODE (op);
1046 if (inmode == CCFPmode || inmode == CCFPUmode)
1048 if (!ix86_trivial_fp_comparison_operator (op, mode))
1050 code = ix86_fp_compare_code_to_integer (code);
1052 /* i387 supports just limited amount of conditional codes. */
1055 case LTU: case GTU: case LEU: case GEU:
1056 if (inmode == CCmode || inmode == CCFPmode || inmode == CCFPUmode
1057 || inmode == CCCmode)
1060 case ORDERED: case UNORDERED:
1068 ;; Return true if OP is a comparison that can be used in the CMPSS/CMPPS insns.
1069 ;; The first set are supported directly; the second set can't be done with
1070 ;; full IEEE support, i.e. NaNs.
1072 (define_predicate "sse_comparison_operator"
1073 (ior (match_code "eq,ne,lt,le,unordered,unge,ungt,ordered")
1074 (and (match_test "TARGET_AVX")
1075 (match_code "ge,gt,uneq,unle,unlt,ltgt"))))
1077 (define_predicate "ix86_comparison_int_operator"
1078 (match_code "ne,eq,ge,gt,le,lt"))
1080 (define_predicate "ix86_comparison_uns_operator"
1081 (match_code "ne,eq,geu,gtu,leu,ltu"))
1083 (define_predicate "bt_comparison_operator"
1084 (match_code "ne,eq"))
1086 ;; Return true if OP is a valid comparison operator in valid mode.
1087 (define_predicate "ix86_comparison_operator"
1088 (match_operand 0 "comparison_operator")
1090 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1091 enum rtx_code code = GET_CODE (op);
1093 if (inmode == CCFPmode || inmode == CCFPUmode)
1094 return ix86_trivial_fp_comparison_operator (op, mode);
1101 if (inmode == CCmode || inmode == CCGCmode
1102 || inmode == CCGOCmode || inmode == CCNOmode)
1105 case LTU: case GTU: case LEU: case GEU:
1106 if (inmode == CCmode || inmode == CCCmode)
1109 case ORDERED: case UNORDERED:
1110 if (inmode == CCmode)
1114 if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode)
1122 ;; Return true if OP is a valid comparison operator
1123 ;; testing carry flag to be set.
1124 (define_predicate "ix86_carry_flag_operator"
1125 (match_code "ltu,lt,unlt,gtu,gt,ungt,le,unle,ge,unge,ltgt,uneq")
1127 enum machine_mode inmode = GET_MODE (XEXP (op, 0));
1128 enum rtx_code code = GET_CODE (op);
1130 if (inmode == CCFPmode || inmode == CCFPUmode)
1132 if (!ix86_trivial_fp_comparison_operator (op, mode))
1134 code = ix86_fp_compare_code_to_integer (code);
1136 else if (inmode == CCCmode)
1137 return code == LTU || code == GTU;
1138 else if (inmode != CCmode)
1144 ;; Return true if this comparison only requires testing one flag bit.
1145 (define_predicate "ix86_trivial_fp_comparison_operator"
1146 (match_code "gt,ge,unlt,unle,uneq,ltgt,ordered,unordered"))
1148 ;; Return true if we know how to do this comparison. Others require
1149 ;; testing more than one flag bit, and we let the generic middle-end
1151 (define_predicate "ix86_fp_comparison_operator"
1152 (if_then_else (match_test "ix86_fp_comparison_strategy (GET_CODE (op))
1153 == IX86_FPCMP_ARITH")
1154 (match_operand 0 "comparison_operator")
1155 (match_operand 0 "ix86_trivial_fp_comparison_operator")))
1157 ;; Same as above, but for swapped comparison used in *jcc<fp>_<int>_i387.
1158 (define_predicate "ix86_swapped_fp_comparison_operator"
1159 (match_operand 0 "comparison_operator")
1161 enum rtx_code code = GET_CODE (op);
1164 PUT_CODE (op, swap_condition (code));
1165 ret = ix86_fp_comparison_operator (op, mode);
1166 PUT_CODE (op, code);
1170 ;; Nearly general operand, but accept any const_double, since we wish
1171 ;; to be able to drop them into memory rather than have them get pulled
1173 (define_predicate "cmp_fp_expander_operand"
1174 (ior (match_code "const_double")
1175 (match_operand 0 "general_operand")))
1177 ;; Return true if this is a valid binary floating-point operation.
1178 (define_predicate "binary_fp_operator"
1179 (match_code "plus,minus,mult,div"))
1181 ;; Return true if this is a multiply operation.
1182 (define_predicate "mult_operator"
1183 (match_code "mult"))
1185 ;; Return true if this is a division operation.
1186 (define_predicate "div_operator"
1189 ;; Return true if this is a plus, minus, and, ior or xor operation.
1190 (define_predicate "plusminuslogic_operator"
1191 (match_code "plus,minus,and,ior,xor"))
1193 ;; Return true if this is a float extend operation.
1194 (define_predicate "float_operator"
1195 (match_code "float"))
1197 ;; Return true for ARITHMETIC_P.
1198 (define_predicate "arith_or_logical_operator"
1199 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax,compare,minus,div,
1200 mod,udiv,umod,ashift,rotate,ashiftrt,lshiftrt,rotatert"))
1202 ;; Return true for COMMUTATIVE_P.
1203 (define_predicate "commutative_operator"
1204 (match_code "plus,mult,and,ior,xor,smin,smax,umin,umax"))
1206 ;; Return true if OP is a binary operator that can be promoted to wider mode.
1207 (define_predicate "promotable_binary_operator"
1208 (ior (match_code "plus,minus,and,ior,xor,ashift")
1209 (and (match_code "mult")
1210 (match_test "TARGET_TUNE_PROMOTE_HIMODE_IMUL"))))
1212 (define_predicate "compare_operator"
1213 (match_code "compare"))
1215 (define_predicate "absneg_operator"
1216 (match_code "abs,neg"))
1218 ;; Return true if OP is misaligned memory operand
1219 (define_predicate "misaligned_operand"
1220 (and (match_code "mem")
1221 (match_test "MEM_ALIGN (op) < GET_MODE_ALIGNMENT (mode)")))
1223 ;; Return true if OP is a emms operation, known to be a PARALLEL.
1224 (define_predicate "emms_operation"
1225 (match_code "parallel")
1229 if (XVECLEN (op, 0) != 17)
1232 for (i = 0; i < 8; i++)
1234 rtx elt = XVECEXP (op, 0, i+1);
1236 if (GET_CODE (elt) != CLOBBER
1237 || GET_CODE (SET_DEST (elt)) != REG
1238 || GET_MODE (SET_DEST (elt)) != XFmode
1239 || REGNO (SET_DEST (elt)) != FIRST_STACK_REG + i)
1242 elt = XVECEXP (op, 0, i+9);
1244 if (GET_CODE (elt) != CLOBBER
1245 || GET_CODE (SET_DEST (elt)) != REG
1246 || GET_MODE (SET_DEST (elt)) != DImode
1247 || REGNO (SET_DEST (elt)) != FIRST_MMX_REG + i)
1253 ;; Return true if OP is a vzeroall operation, known to be a PARALLEL.
1254 (define_predicate "vzeroall_operation"
1255 (match_code "parallel")
1257 unsigned i, nregs = TARGET_64BIT ? 16 : 8;
1259 if ((unsigned) XVECLEN (op, 0) != 1 + nregs)
1262 for (i = 0; i < nregs; i++)
1264 rtx elt = XVECEXP (op, 0, i+1);
1266 if (GET_CODE (elt) != SET
1267 || GET_CODE (SET_DEST (elt)) != REG
1268 || GET_MODE (SET_DEST (elt)) != V8SImode
1269 || REGNO (SET_DEST (elt)) != SSE_REGNO (i)
1270 || SET_SRC (elt) != CONST0_RTX (V8SImode))
1276 ;; return true if OP is a vzeroupper operation.
1277 (define_predicate "vzeroupper_operation"
1278 (and (match_code "unspec_volatile")
1279 (match_test "XINT (op, 1) == UNSPECV_VZEROUPPER")))
1281 ;; Return true if OP is a parallel for a vbroadcast permute.
1283 (define_predicate "avx_vbroadcast_operand"
1284 (and (match_code "parallel")
1285 (match_code "const_int" "a"))
1287 rtx elt = XVECEXP (op, 0, 0);
1288 int i, nelt = XVECLEN (op, 0);
1290 /* Don't bother checking there are the right number of operands,
1291 merely that they're all identical. */
1292 for (i = 1; i < nelt; ++i)
1293 if (XVECEXP (op, 0, i) != elt)
1298 ;; Return true if OP is a proper third operand to vpblendw256.
1299 (define_predicate "avx2_pblendw_operand"
1300 (match_code "const_int")
1302 HOST_WIDE_INT val = INTVAL (op);
1303 HOST_WIDE_INT low = val & 0xff;
1304 return val == ((low << 8) | low);
1307 ;; Return true if OP is nonimmediate_operand or CONST_VECTOR.
1308 (define_predicate "general_vector_operand"
1309 (ior (match_operand 0 "nonimmediate_operand")
1310 (match_code "const_vector")))