libgcc/config/aarch64/linux-unwind.h

   1 /* Copyright (C) 2009-2013 Free Software Foundation, Inc.
   2    Contributed by ARM Ltd.
   3
   4    This file is free software; you can redistribute it and/or modify it
   5    under the terms of the GNU General Public License as published by the
   6    Free Software Foundation; either version 3, or (at your option) any
   7    later version.
   8
   9    This file is distributed in the hope that it will be useful, but
  10    WITHOUT ANY WARRANTY; without even the implied warranty of
  11    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12    General Public License for more details.
  13
  14    Under Section 7 of GPL version 3, you are granted additional
  15    permissions described in the GCC Runtime Library Exception, version
  16    3.1, as published by the Free Software Foundation.
  17
  18    You should have received a copy of the GNU General Public License and
  19    a copy of the GCC Runtime Library Exception along with this program;
  20    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  21    <http://www.gnu.org/licenses/>.  */
  22
  23 #ifndef inhibit_libc
  24
  25 #include <signal.h>
  26 #include <sys/ucontext.h>
  27
  28 #define MD_FALLBACK_FRAME_STATE_FOR aarch64_fallback_frame_state
  29
  30 static _Unwind_Reason_Code
  31 aarch64_fallback_frame_state (struct _Unwind_Context *context,
  32                               _Unwind_FrameState * fs)
  33 {
  34   /* The kernel creates an rt_sigframe on the stack immediately prior
  35      to delivering a signal.
  36
  37      This structure must have the same shape as the linux kernel
  38      equivalent.  */
  39   struct rt_sigframe
  40   {
  41     siginfo_t info;
  42     struct ucontext uc;
  43   };
  44
  45   struct rt_sigframe *rt_;
  46   _Unwind_Ptr new_cfa;
  47   unsigned *pc = context->ra;
  48   struct sigcontext *sc;
  49   struct _aarch64_ctx *extension_marker;
  50   int i;
  51
  52   /* A signal frame will have a return address pointing to
  53      __default_sa_restorer. This code is hardwired as:
  54
  55      0xd2801168         movz x8, #0x8b
  56      0xd4000001         svc  0x0
  57    */
  58   if (pc[0] != 0xd2801168 || pc[1] != 0xd4000001)
  59     {
  60       return _URC_END_OF_STACK;
  61     }
  62
  63   rt_ = context->cfa;
  64   sc = &rt_->uc.uc_mcontext;
  65
  66 /* This define duplicates the definition in aarch64.md */
  67 #define SP_REGNUM 31
  68
  69   new_cfa = (_Unwind_Ptr) sc;
  70   fs->regs.cfa_how = CFA_REG_OFFSET;
  71   fs->regs.cfa_reg = STACK_POINTER_REGNUM;
  72   fs->regs.cfa_offset = new_cfa - (_Unwind_Ptr) context->cfa;
  73
  74   for (i = 0; i < AARCH64_DWARF_NUMBER_R; i++)
  75     {
  76       fs->regs.reg[AARCH64_DWARF_R0 + i].how = REG_SAVED_OFFSET;
  77       fs->regs.reg[AARCH64_DWARF_R0 + i].loc.offset =
  78         (_Unwind_Ptr) & (sc->regs[i]) - new_cfa;
  79     }
  80
  81   /* The core context may be extended with an arbitrary set of
  82      additional contexts appended sequentially. Each additional
  83      context contains a magic identifier and size in bytes.  The size
  84      field can be used to skip over unrecognized context extensions.
  85      The end of the context sequence is marked by a context with magic
  86      0 or size 0.  */
  87   for (extension_marker = (struct _aarch64_ctx *) &sc->__reserved;
  88        extension_marker->magic;
  89        extension_marker = (struct _aarch64_ctx *)
  90        ((unsigned char *) extension_marker + extension_marker->size))
  91     {
  92       if (extension_marker->magic == FPSIMD_MAGIC)
  93         {
  94           struct fpsimd_context *ctx =
  95             (struct fpsimd_context *) extension_marker;
  96           int i;
  97
  98           for (i = 0; i < AARCH64_DWARF_NUMBER_V; i++)
  99             {
 100               _Unwind_Sword offset;
 101
 102               fs->regs.reg[AARCH64_DWARF_V0 + i].how = REG_SAVED_OFFSET;
 103
 104               /* sigcontext contains 32 128bit registers for V0 to
 105                  V31.  The kernel will have saved the contents of the
 106                  V registers.  We want to unwind the callee save D
 107                  registers.  Each D register comprises the least
 108                  significant half of the corresponding V register.  We
 109                  need to offset into the saved V register dependent on
 110                  our endianness to find the saved D register.  */
 111
 112               offset = (_Unwind_Ptr) & (ctx->vregs[i]) - new_cfa;
 113
 114               /* The endianness adjustment code below expects that a
 115                  saved V register is 16 bytes.  */
 116               gcc_assert (sizeof (ctx->vregs[0]) == 16);
 117 #if defined (__AARCH64EB__)
 118               offset = offset + 8;
 119 #endif
 120               fs->regs.reg[AARCH64_DWARF_V0 + i].loc.offset = offset;
 121             }
 122         }
 123       else
 124         {
 125           /* There is context provided that we do not recognize!  */
 126         }
 127     }
 128
 129   fs->regs.reg[31].how = REG_SAVED_OFFSET;
 130   fs->regs.reg[31].loc.offset = (_Unwind_Ptr) & (sc->sp) - new_cfa;
 131
 132   fs->signal_frame = 1;
 133
 134   fs->regs.reg[DWARF_ALT_FRAME_RETURN_COLUMN].how = REG_SAVED_VAL_OFFSET;
 135   fs->regs.reg[DWARF_ALT_FRAME_RETURN_COLUMN].loc.offset =
 136     (_Unwind_Ptr) (sc->pc) - new_cfa;
 137
 138   fs->retaddr_column = DWARF_ALT_FRAME_RETURN_COLUMN;
 139
 140   return _URC_NO_REASON;
 141 }
 142
 143 #endif