gcc/config/i386/driver-i386.c

   1 /* Subroutines for the gcc driver.
   2    Copyright (C) 2006-2013 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 3, or (at your option)
   9 any later version.
  10
  11 GCC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 #include "config.h"
  21 #include "system.h"
  22 #include "coretypes.h"
  23 #include "tm.h"
  24
  25 const char *host_detect_local_cpu (int argc, const char **argv);
  26
  27 #ifdef __GNUC__
  28 #include "cpuid.h"
  29
  30 struct cache_desc
  31 {
  32   unsigned sizekb;
  33   unsigned assoc;
  34   unsigned line;
  35 };
  36
  37 /* Returns command line parameters that describe size and
  38    cache line size of the processor caches.  */
  39
  40 static char *
  41 describe_cache (struct cache_desc level1, struct cache_desc level2)
  42 {
  43   char size[100], line[100], size2[100];
  44
  45   /* At the moment, gcc does not use the information
  46      about the associativity of the cache.  */
  47
  48   snprintf (size, sizeof (size),
  49             "--param l1-cache-size=%u ", level1.sizekb);
  50   snprintf (line, sizeof (line),
  51             "--param l1-cache-line-size=%u ", level1.line);
  52
  53   snprintf (size2, sizeof (size2),
  54             "--param l2-cache-size=%u ", level2.sizekb);
  55
  56   return concat (size, line, size2, NULL);
  57 }
  58
  59 /* Detect L2 cache parameters using CPUID extended function 0x80000006.  */
  60
  61 static void
  62 detect_l2_cache (struct cache_desc *level2)
  63 {
  64   unsigned eax, ebx, ecx, edx;
  65   unsigned assoc;
  66
  67   __cpuid (0x80000006, eax, ebx, ecx, edx);
  68
  69   level2->sizekb = (ecx >> 16) & 0xffff;
  70   level2->line = ecx & 0xff;
  71
  72   assoc = (ecx >> 12) & 0xf;
  73   if (assoc == 6)
  74     assoc = 8;
  75   else if (assoc == 8)
  76     assoc = 16;
  77   else if (assoc >= 0xa && assoc <= 0xc)
  78     assoc = 32 + (assoc - 0xa) * 16;
  79   else if (assoc >= 0xd && assoc <= 0xe)
  80     assoc = 96 + (assoc - 0xd) * 32;
  81
  82   level2->assoc = assoc;
  83 }
  84
  85 /* Returns the description of caches for an AMD processor.  */
  86
  87 static const char *
  88 detect_caches_amd (unsigned max_ext_level)
  89 {
  90   unsigned eax, ebx, ecx, edx;
  91
  92   struct cache_desc level1, level2 = {0, 0, 0};
  93
  94   if (max_ext_level < 0x80000005)
  95     return "";
  96
  97   __cpuid (0x80000005, eax, ebx, ecx, edx);
  98
  99   level1.sizekb = (ecx >> 24) & 0xff;
 100   level1.assoc = (ecx >> 16) & 0xff;
 101   level1.line = ecx & 0xff;
 102
 103   if (max_ext_level >= 0x80000006)
 104     detect_l2_cache (&level2);
 105
 106   return describe_cache (level1, level2);
 107 }
 108
 109 /* Decodes the size, the associativity and the cache line size of
 110    L1/L2 caches of an Intel processor.  Values are based on
 111    "Intel Processor Identification and the CPUID Instruction"
 112    [Application Note 485], revision -032, December 2007.  */
 113
 114 static void
 115 decode_caches_intel (unsigned reg, bool xeon_mp,
 116                      struct cache_desc *level1, struct cache_desc *level2)
 117 {
 118   int i;
 119
 120   for (i = 24; i >= 0; i -= 8)
 121     switch ((reg >> i) & 0xff)
 122       {
 123       case 0x0a:
 124         level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
 125         break;
 126       case 0x0c:
 127         level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
 128         break;
 129       case 0x2c:
 130         level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
 131         break;
 132       case 0x39:
 133         level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
 134         break;
 135       case 0x3a:
 136         level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
 137         break;
 138       case 0x3b:
 139         level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
 140         break;
 141       case 0x3c:
 142         level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
 143         break;
 144       case 0x3d:
 145         level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
 146         break;
 147       case 0x3e:
 148         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 149         break;
 150       case 0x41:
 151         level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
 152         break;
 153       case 0x42:
 154         level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
 155         break;
 156       case 0x43:
 157         level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
 158         break;
 159       case 0x44:
 160         level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
 161         break;
 162       case 0x45:
 163         level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
 164         break;
 165       case 0x49:
 166         if (xeon_mp)
 167           break;
 168         level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
 169         break;
 170       case 0x4e:
 171         level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
 172         break;
 173       case 0x60:
 174         level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
 175         break;
 176       case 0x66:
 177         level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
 178         break;
 179       case 0x67:
 180         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 181         break;
 182       case 0x68:
 183         level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
 184         break;
 185       case 0x78:
 186         level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
 187         break;
 188       case 0x79:
 189         level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
 190         break;
 191       case 0x7a:
 192         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 193         break;
 194       case 0x7b:
 195         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 196         break;
 197       case 0x7c:
 198         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 199         break;
 200       case 0x7d:
 201         level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
 202         break;
 203       case 0x7f:
 204         level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
 205         break;
 206       case 0x82:
 207         level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
 208         break;
 209       case 0x83:
 210         level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
 211         break;
 212       case 0x84:
 213         level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
 214         break;
 215       case 0x85:
 216         level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
 217         break;
 218       case 0x86:
 219         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 220         break;
 221       case 0x87:
 222         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 223
 224       default:
 225         break;
 226       }
 227 }
 228
 229 /* Detect cache parameters using CPUID function 2.  */
 230
 231 static void
 232 detect_caches_cpuid2 (bool xeon_mp,
 233                       struct cache_desc *level1, struct cache_desc *level2)
 234 {
 235   unsigned regs[4];
 236   int nreps, i;
 237
 238   __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 239
 240   nreps = regs[0] & 0x0f;
 241   regs[0] &= ~0x0f;
 242
 243   while (--nreps >= 0)
 244     {
 245       for (i = 0; i < 4; i++)
 246         if (regs[i] && !((regs[i] >> 31) & 1))
 247           decode_caches_intel (regs[i], xeon_mp, level1, level2);
 248
 249       if (nreps)
 250         __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 251     }
 252 }
 253
 254 /* Detect cache parameters using CPUID function 4. This
 255    method doesn't require hardcoded tables.  */
 256
 257 enum cache_type
 258 {
 259   CACHE_END = 0,
 260   CACHE_DATA = 1,
 261   CACHE_INST = 2,
 262   CACHE_UNIFIED = 3
 263 };
 264
 265 static void
 266 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
 267                       struct cache_desc *level3)
 268 {
 269   struct cache_desc *cache;
 270
 271   unsigned eax, ebx, ecx, edx;
 272   int count;
 273
 274   for (count = 0;; count++)
 275     {
 276       __cpuid_count(4, count, eax, ebx, ecx, edx);
 277       switch (eax & 0x1f)
 278         {
 279         case CACHE_END:
 280           return;
 281         case CACHE_DATA:
 282         case CACHE_UNIFIED:
 283           {
 284             switch ((eax >> 5) & 0x07)
 285               {
 286               case 1:
 287                 cache = level1;
 288                 break;
 289               case 2:
 290                 cache = level2;
 291                 break;
 292               case 3:
 293                 cache = level3;
 294                 break;
 295               default:
 296                 cache = NULL;
 297               }
 298
 299             if (cache)
 300               {
 301                 unsigned sets = ecx + 1;
 302                 unsigned part = ((ebx >> 12) & 0x03ff) + 1;
 303
 304                 cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
 305                 cache->line = (ebx & 0x0fff) + 1;
 306
 307                 cache->sizekb = (cache->assoc * part
 308                                  * cache->line * sets) / 1024;
 309               }
 310           }
 311         default:
 312           break;
 313         }
 314     }
 315 }
 316
 317 /* Returns the description of caches for an Intel processor.  */
 318
 319 static const char *
 320 detect_caches_intel (bool xeon_mp, unsigned max_level,
 321                      unsigned max_ext_level, unsigned *l2sizekb)
 322 {
 323   struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0};
 324
 325   if (max_level >= 4)
 326     detect_caches_cpuid4 (&level1, &level2, &level3);
 327   else if (max_level >= 2)
 328     detect_caches_cpuid2 (xeon_mp, &level1, &level2);
 329   else
 330     return "";
 331
 332   if (level1.sizekb == 0)
 333     return "";
 334
 335   /* Let the L3 replace the L2. This assumes inclusive caches
 336      and single threaded program for now. */
 337   if (level3.sizekb)
 338     level2 = level3;
 339
 340   /* Intel CPUs are equipped with AMD style L2 cache info.  Try this
 341      method if other methods fail to provide L2 cache parameters.  */
 342   if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
 343     detect_l2_cache (&level2);
 344
 345   *l2sizekb = level2.sizekb;
 346
 347   return describe_cache (level1, level2);
 348 }
 349
 350 /* This will be called by the spec parser in gcc.c when it sees
 351    a %:local_cpu_detect(args) construct.  Currently it will be called
 352    with either "arch" or "tune" as argument depending on if -march=native
 353    or -mtune=native is to be substituted.
 354
 355    It returns a string containing new command line parameters to be
 356    put at the place of the above two options, depending on what CPU
 357    this is executed.  E.g. "-march=k8" on an AMD64 machine
 358    for -march=native.
 359
 360    ARGC and ARGV are set depending on the actual arguments given
 361    in the spec.  */
 362
 363 const char *host_detect_local_cpu (int argc, const char **argv)
 364 {
 365   enum processor_type processor = PROCESSOR_I386;
 366   const char *cpu = "i386";
 367
 368   const char *cache = "";
 369   const char *options = "";
 370
 371   unsigned int eax, ebx, ecx, edx;
 372
 373   unsigned int max_level, ext_level;
 374
 375   unsigned int vendor;
 376   unsigned int model, family;
 377
 378   unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
 379   unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
 380
 381   /* Extended features */
 382   unsigned int has_lahf_lm = 0, has_sse4a = 0;
 383   unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
 384   unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
 385   unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0, has_avx2 = 0;
 386   unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
 387   unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
 388   unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
 389   unsigned int has_hle = 0, has_rtm = 0;
 390   unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
 391   unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0;
 392   unsigned int has_osxsave = 0, has_fxsr = 0, has_xsave = 0, has_xsaveopt = 0;
 393
 394   bool arch;
 395
 396   unsigned int l2sizekb = 0;
 397
 398   if (argc < 1)
 399     return NULL;
 400
 401   arch = !strcmp (argv[0], "arch");
 402
 403   if (!arch && strcmp (argv[0], "tune"))
 404     return NULL;
 405
 406   max_level = __get_cpuid_max (0, &vendor);
 407   if (max_level < 1)
 408     goto done;
 409
 410   __cpuid (1, eax, ebx, ecx, edx);
 411
 412   model = (eax >> 4) & 0x0f;
 413   family = (eax >> 8) & 0x0f;
 414   if (vendor == signature_INTEL_ebx)
 415     {
 416       unsigned int extended_model, extended_family;
 417
 418       extended_model = (eax >> 12) & 0xf0;
 419       extended_family = (eax >> 20) & 0xff;
 420       if (family == 0x0f)
 421         {
 422           family += extended_family;
 423           model += extended_model;
 424         }
 425       else if (family == 0x06)
 426         model += extended_model;
 427     }
 428
 429   has_sse3 = ecx & bit_SSE3;
 430   has_ssse3 = ecx & bit_SSSE3;
 431   has_sse4_1 = ecx & bit_SSE4_1;
 432   has_sse4_2 = ecx & bit_SSE4_2;
 433   has_avx = ecx & bit_AVX;
 434   has_osxsave = ecx & bit_OSXSAVE;
 435   has_cmpxchg16b = ecx & bit_CMPXCHG16B;
 436   has_movbe = ecx & bit_MOVBE;
 437   has_popcnt = ecx & bit_POPCNT;
 438   has_aes = ecx & bit_AES;
 439   has_pclmul = ecx & bit_PCLMUL;
 440   has_fma = ecx & bit_FMA;
 441   has_f16c = ecx & bit_F16C;
 442   has_rdrnd = ecx & bit_RDRND;
 443   has_xsave = ecx & bit_XSAVE;
 444
 445   has_cmpxchg8b = edx & bit_CMPXCHG8B;
 446   has_cmov = edx & bit_CMOV;
 447   has_mmx = edx & bit_MMX;
 448   has_fxsr = edx & bit_FXSAVE;
 449   has_sse = edx & bit_SSE;
 450   has_sse2 = edx & bit_SSE2;
 451
 452   if (max_level >= 7)
 453     {
 454       __cpuid_count (7, 0, eax, ebx, ecx, edx);
 455
 456       has_bmi = ebx & bit_BMI;
 457       has_hle = ebx & bit_HLE;
 458       has_rtm = ebx & bit_RTM;
 459       has_avx2 = ebx & bit_AVX2;
 460       has_bmi2 = ebx & bit_BMI2;
 461       has_fsgsbase = ebx & bit_FSGSBASE;
 462       has_rdseed = ebx & bit_RDSEED;
 463       has_adx = ebx & bit_ADX;
 464     }
 465
 466   if (max_level >= 13)
 467     {
 468       __cpuid_count (13, 1, eax, ebx, ecx, edx);
 469
 470       has_xsaveopt = eax & bit_XSAVEOPT;
 471     }
 472
 473   /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv.  */
 474 #define XCR_XFEATURE_ENABLED_MASK       0x0
 475 #define XSTATE_FP                       0x1
 476 #define XSTATE_SSE                      0x2
 477 #define XSTATE_YMM                      0x4
 478   if (has_osxsave)
 479     asm (".byte 0x0f; .byte 0x01; .byte 0xd0"
 480          : "=a" (eax), "=d" (edx)
 481          : "c" (XCR_XFEATURE_ENABLED_MASK));
 482
 483   /* Check if SSE and YMM states are supported.  */
 484   if (!has_osxsave
 485       || (eax & (XSTATE_SSE | XSTATE_YMM)) != (XSTATE_SSE | XSTATE_YMM))
 486     {
 487       has_avx = 0;
 488       has_avx2 = 0;
 489       has_fma = 0;
 490       has_fma4 = 0;
 491       has_xop = 0;
 492       has_xsave = 0;
 493       has_xsaveopt = 0;
 494     }
 495
 496   /* Check cpuid level of extended features.  */
 497   __cpuid (0x80000000, ext_level, ebx, ecx, edx);
 498
 499   if (ext_level > 0x80000000)
 500     {
 501       __cpuid (0x80000001, eax, ebx, ecx, edx);
 502
 503       has_lahf_lm = ecx & bit_LAHF_LM;
 504       has_sse4a = ecx & bit_SSE4a;
 505       has_abm = ecx & bit_ABM;
 506       has_lwp = ecx & bit_LWP;
 507       has_fma4 = ecx & bit_FMA4;
 508       has_xop = ecx & bit_XOP;
 509       has_tbm = ecx & bit_TBM;
 510       has_lzcnt = ecx & bit_LZCNT;
 511       has_prfchw = ecx & bit_PRFCHW;
 512
 513       has_longmode = edx & bit_LM;
 514       has_3dnowp = edx & bit_3DNOWP;
 515       has_3dnow = edx & bit_3DNOW;
 516     }
 517
 518   if (!arch)
 519     {
 520       if (vendor == signature_AMD_ebx
 521           || vendor == signature_CENTAUR_ebx
 522           || vendor == signature_CYRIX_ebx
 523           || vendor == signature_NSC_ebx)
 524         cache = detect_caches_amd (ext_level);
 525       else if (vendor == signature_INTEL_ebx)
 526         {
 527           bool xeon_mp = (family == 15 && model == 6);
 528           cache = detect_caches_intel (xeon_mp, max_level,
 529                                        ext_level, &l2sizekb);
 530         }
 531     }
 532
 533   if (vendor == signature_AMD_ebx)
 534     {
 535       unsigned int name;
 536
 537       /* Detect geode processor by its processor signature.  */
 538       if (ext_level > 0x80000001)
 539         __cpuid (0x80000002, name, ebx, ecx, edx);
 540       else
 541         name = 0;
 542
 543       if (name == signature_NSC_ebx)
 544         processor = PROCESSOR_GEODE;
 545       else if (has_movbe)
 546         processor = PROCESSOR_BTVER2;
 547       else if (has_xsaveopt)
 548         processor = PROCESSOR_BDVER3;
 549       else if (has_bmi)
 550         processor = PROCESSOR_BDVER2;
 551       else if (has_xop)
 552         processor = PROCESSOR_BDVER1;
 553       else if (has_sse4a && has_ssse3)
 554         processor = PROCESSOR_BTVER1;
 555       else if (has_sse4a)
 556         processor = PROCESSOR_AMDFAM10;
 557       else if (has_sse2 || has_longmode)
 558         processor = PROCESSOR_K8;
 559       else if (has_3dnowp && family == 6)
 560         processor = PROCESSOR_ATHLON;
 561       else if (has_mmx)
 562         processor = PROCESSOR_K6;
 563       else
 564         processor = PROCESSOR_PENTIUM;
 565     }
 566   else if (vendor == signature_CENTAUR_ebx)
 567     {
 568       if (arch)
 569         {
 570           switch (family)
 571             {
 572             case 6:
 573               if (model > 9)
 574                 /* Use the default detection procedure.  */
 575                 processor = PROCESSOR_GENERIC32;
 576               else if (model == 9)
 577                 cpu = "c3-2";
 578               else if (model >= 6)
 579                 cpu = "c3";
 580               else
 581                 processor = PROCESSOR_GENERIC32;
 582               break;
 583             case 5:
 584               if (has_3dnow)
 585                 cpu = "winchip2";
 586               else if (has_mmx)
 587                 cpu = "winchip2-c6";
 588               else
 589                 processor = PROCESSOR_GENERIC32;
 590               break;
 591             default:
 592               /* We have no idea.  */
 593               processor = PROCESSOR_GENERIC32;
 594             }
 595         }
 596     }
 597   else
 598     {
 599       switch (family)
 600         {
 601         case 4:
 602           processor = PROCESSOR_I486;
 603           break;
 604         case 5:
 605           processor = PROCESSOR_PENTIUM;
 606           break;
 607         case 6:
 608           processor = PROCESSOR_PENTIUMPRO;
 609           break;
 610         case 15:
 611           processor = PROCESSOR_PENTIUM4;
 612           break;
 613         default:
 614           /* We have no idea.  */
 615           processor = PROCESSOR_GENERIC32;
 616         }
 617     }
 618
 619   switch (processor)
 620     {
 621     case PROCESSOR_I386:
 622       /* Default.  */
 623       break;
 624     case PROCESSOR_I486:
 625       cpu = "i486";
 626       break;
 627     case PROCESSOR_PENTIUM:
 628       if (arch && has_mmx)
 629         cpu = "pentium-mmx";
 630       else
 631         cpu = "pentium";
 632       break;
 633     case PROCESSOR_PENTIUMPRO:
 634       switch (model)
 635         {
 636         case 0x1c:
 637         case 0x26:
 638           /* Atom.  */
 639           cpu = "atom";
 640           break;
 641         case 0x1a:
 642         case 0x1e:
 643         case 0x1f:
 644         case 0x2e:
 645           /* Nehalem.  */
 646           cpu = "corei7";
 647           break;
 648         case 0x25:
 649         case 0x2c:
 650         case 0x2f:
 651           /* Westmere.  */
 652           cpu = "corei7";
 653           break;
 654         case 0x2a:
 655         case 0x2d:
 656           /* Sandy Bridge.  */
 657           cpu = "corei7-avx";
 658           break;
 659         case 0x17:
 660         case 0x1d:
 661           /* Penryn.  */
 662           cpu = "core2";
 663           break;
 664         case 0x0f:
 665           /* Merom.  */
 666           cpu = "core2";
 667           break;
 668         default:
 669           if (arch)
 670             {
 671               /* This is unknown family 0x6 CPU.  */
 672               if (has_avx)
 673                 /* Assume Sandy Bridge.  */
 674                 cpu = "corei7-avx";
 675               else if (has_sse4_2)
 676                 {
 677                   if (has_movbe)
 678                     /* Assume SLM.  */
 679                     cpu = "slm";
 680                   else
 681                     /* Assume Core i7.  */
 682                     cpu = "corei7";
 683                 }
 684               else if (has_ssse3)
 685                 {
 686                   if (has_movbe)
 687                     /* Assume Atom.  */
 688                     cpu = "atom";
 689                   else
 690                     /* Assume Core 2.  */
 691                     cpu = "core2";
 692                 }
 693               else if (has_sse3)
 694                 /* It is Core Duo.  */
 695                 cpu = "pentium-m";
 696               else if (has_sse2)
 697                 /* It is Pentium M.  */
 698                 cpu = "pentium-m";
 699               else if (has_sse)
 700                 /* It is Pentium III.  */
 701                 cpu = "pentium3";
 702               else if (has_mmx)
 703                 /* It is Pentium II.  */
 704                 cpu = "pentium2";
 705               else
 706                 /* Default to Pentium Pro.  */
 707                 cpu = "pentiumpro";
 708             }
 709           else
 710             /* For -mtune, we default to -mtune=generic.  */
 711             cpu = "generic";
 712           break;
 713         }
 714       break;
 715     case PROCESSOR_PENTIUM4:
 716       if (has_sse3)
 717         {
 718           if (has_longmode)
 719             cpu = "nocona";
 720           else
 721             cpu = "prescott";
 722         }
 723       else
 724         cpu = "pentium4";
 725       break;
 726     case PROCESSOR_GEODE:
 727       cpu = "geode";
 728       break;
 729     case PROCESSOR_K6:
 730       if (arch && has_3dnow)
 731         cpu = "k6-3";
 732       else
 733         cpu = "k6";
 734       break;
 735     case PROCESSOR_ATHLON:
 736       if (arch && has_sse)
 737         cpu = "athlon-4";
 738       else
 739         cpu = "athlon";
 740       break;
 741     case PROCESSOR_K8:
 742       if (arch && has_sse3)
 743         cpu = "k8-sse3";
 744       else
 745         cpu = "k8";
 746       break;
 747     case PROCESSOR_AMDFAM10:
 748       cpu = "amdfam10";
 749       break;
 750     case PROCESSOR_BDVER1:
 751       cpu = "bdver1";
 752       break;
 753     case PROCESSOR_BDVER2:
 754       cpu = "bdver2";
 755       break;
 756     case PROCESSOR_BDVER3:
 757       cpu = "bdver3";
 758       break;
 759     case PROCESSOR_BTVER1:
 760       cpu = "btver1";
 761       break;
 762     case PROCESSOR_BTVER2:
 763       cpu = "btver2";
 764       break;
 765
 766     default:
 767       /* Use something reasonable.  */
 768       if (arch)
 769         {
 770           if (has_ssse3)
 771             cpu = "core2";
 772           else if (has_sse3)
 773             {
 774               if (has_longmode)
 775                 cpu = "nocona";
 776               else
 777                 cpu = "prescott";
 778             }
 779           else if (has_sse2)
 780             cpu = "pentium4";
 781           else if (has_cmov)
 782             cpu = "pentiumpro";
 783           else if (has_mmx)
 784             cpu = "pentium-mmx";
 785           else if (has_cmpxchg8b)
 786             cpu = "pentium";
 787         }
 788       else
 789         cpu = "generic";
 790     }
 791
 792   if (arch)
 793     {
 794       const char *mmx = has_mmx ? " -mmmx" : " -mno-mmx";
 795       const char *mmx3dnow = has_3dnow ? " -m3dnow" : " -mno-3dnow";
 796       const char *sse = has_sse ? " -msse" : " -mno-sse";
 797       const char *sse2 = has_sse2 ? " -msse2" : " -mno-sse2";
 798       const char *sse3 = has_sse3 ? " -msse3" : " -mno-sse3";
 799       const char *ssse3 = has_ssse3 ? " -mssse3" : " -mno-ssse3";
 800       const char *sse4a = has_sse4a ? " -msse4a" : " -mno-sse4a";
 801       const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16";
 802       const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf";
 803       const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe";
 804       const char *aes = has_aes ? " -maes" : " -mno-aes";
 805       const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul";
 806       const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt";
 807       const char *abm = has_abm ? " -mabm" : " -mno-abm";
 808       const char *lwp = has_lwp ? " -mlwp" : " -mno-lwp";
 809       const char *fma = has_fma ? " -mfma" : " -mno-fma";
 810       const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4";
 811       const char *xop = has_xop ? " -mxop" : " -mno-xop";
 812       const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi";
 813       const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2";
 814       const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm";
 815       const char *avx = has_avx ? " -mavx" : " -mno-avx";
 816       const char *avx2 = has_avx2 ? " -mavx2" : " -mno-avx2";
 817       const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2";
 818       const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1";
 819       const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt";
 820       const char *hle = has_hle ? " -mhle" : " -mno-hle";
 821       const char *rtm = has_rtm ? " -mrtm" : " -mno-rtm";
 822       const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
 823       const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
 824       const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
 825       const char *rdseed = has_rdseed ? " -mrdseed" : " -mno-rdseed";
 826       const char *prfchw = has_prfchw ? " -mprfchw" : " -mno-prfchw";
 827       const char *adx = has_adx ? " -madx" : " -mno-adx";
 828       const char *fxsr = has_fxsr ? " -mfxsr" : " -mno-fxsr";
 829       const char *xsave = has_xsave ? " -mxsave" : " -mno-xsave";
 830       const char *xsaveopt = has_xsaveopt ? " -mxsaveopt" : " -mno-xsaveopt";
 831
 832       options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
 833                         sse4a, cx16, sahf, movbe, aes, pclmul,
 834                         popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
 835                         tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm,
 836                         hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx,
 837                         fxsr, xsave, xsaveopt, NULL);
 838     }
 839
 840 done:
 841   return concat (cache, "-m", argv[0], "=", cpu, options, NULL);
 842 }
 843 #else
 844
 845 /* If we aren't compiling with GCC then the driver will just ignore
 846    -march and -mtune "native" target and will leave to the newly
 847    built compiler to generate code for its default target.  */
 848
 849 const char *host_detect_local_cpu (int argc ATTRIBUTE_UNUSED,
 850                                    const char **argv ATTRIBUTE_UNUSED)
 851 {
 852   return NULL;
 853 }
 854 #endif /* __GNUC__ */