| blob | 21512c6de574db3b3ec1eb2c9d500204b9987fc9 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
92 /* This file should be included last. */
99 #ifndef CHECK_STACK_LIMIT
100 #define CHECK_STACK_LIMIT (-1)
101 #endif
103 /* Return index of given mode in mult and division cost tables. */
104 #define MODE_INDEX(mode) \
105 ((mode) == QImode ? 0 \
106 : (mode) == HImode ? 1 \
107 : (mode) == SImode ? 2 \
108 : (mode) == DImode ? 3 \
109 : 4)
111 /* Processor costs (relative to an add) */
112 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
113 #define COSTS_N_BYTES(N) ((N) * 2)
115 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
124 const
147 in QImode, HImode and SImode.
148 Relative to reg-reg move (2). */
152 in SFmode, DFmode and XFmode */
154 in SFmode, DFmode and XFmode */
157 in SImode and DImode */
159 in SImode and DImode */
162 in SImode, DImode and TImode */
164 in SImode, DImode and TImode */
177 ix86_size_memcpy,
178 ix86_size_memset,
190 };
192 /* Processor costs (relative to an add) */
195 DUMMY_STRINGOP_ALGS};
198 DUMMY_STRINGOP_ALGS};
200 static const
223 in QImode, HImode and SImode.
224 Relative to reg-reg move (2). */
228 in SFmode, DFmode and XFmode */
230 in SFmode, DFmode and XFmode */
233 in SImode and DImode */
235 in SImode and DImode */
238 in SImode, DImode and TImode */
240 in SImode, DImode and TImode */
253 i386_memcpy,
254 i386_memset,
266 };
270 DUMMY_STRINGOP_ALGS};
273 DUMMY_STRINGOP_ALGS};
275 static const
298 in QImode, HImode and SImode.
299 Relative to reg-reg move (2). */
303 in SFmode, DFmode and XFmode */
305 in SFmode, DFmode and XFmode */
308 in SImode and DImode */
310 in SImode and DImode */
313 in SImode, DImode and TImode */
315 in SImode, DImode and TImode */
318 shared for code and data, so 4kB is
319 not really precise. */
330 i486_memcpy,
331 i486_memset,
343 };
347 DUMMY_STRINGOP_ALGS};
350 DUMMY_STRINGOP_ALGS};
352 static const
375 in QImode, HImode and SImode.
376 Relative to reg-reg move (2). */
380 in SFmode, DFmode and XFmode */
382 in SFmode, DFmode and XFmode */
385 in SImode and DImode */
387 in SImode and DImode */
390 in SImode, DImode and TImode */
392 in SImode, DImode and TImode */
405 pentium_memcpy,
406 pentium_memset,
418 };
420 static const
443 in QImode, HImode and SImode.
444 Relative to reg-reg move (2). */
448 in SFmode, DFmode and XFmode */
450 in SFmode, DFmode and XFmode */
453 in SImode and DImode */
455 in SImode and DImode */
458 in SImode, DImode and TImode */
460 in SImode, DImode and TImode */
473 pentium_memcpy,
474 pentium_memset,
486 };
488 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
489 (we ensure the alignment). For small blocks inline loop is still a
490 noticeable win, for bigger blocks either rep movsl or rep movsb is
491 way to go. Rep movsb has apparently more expensive startup time in CPU,
492 but after 4K the difference is down in the noise. */
497 DUMMY_STRINGOP_ALGS};
502 DUMMY_STRINGOP_ALGS};
503 static const
526 in QImode, HImode and SImode.
527 Relative to reg-reg move (2). */
531 in SFmode, DFmode and XFmode */
533 in SFmode, DFmode and XFmode */
536 in SImode and DImode */
538 in SImode and DImode */
541 in SImode, DImode and TImode */
543 in SImode, DImode and TImode */
556 pentiumpro_memcpy,
557 pentiumpro_memset,
569 };
573 DUMMY_STRINGOP_ALGS};
576 DUMMY_STRINGOP_ALGS};
577 static const
600 in QImode, HImode and SImode.
601 Relative to reg-reg move (2). */
605 in SFmode, DFmode and XFmode */
607 in SFmode, DFmode and XFmode */
611 in SImode and DImode */
613 in SImode and DImode */
616 in SImode, DImode and TImode */
618 in SImode, DImode and TImode */
631 geode_memcpy,
632 geode_memset,
644 };
648 DUMMY_STRINGOP_ALGS};
651 DUMMY_STRINGOP_ALGS};
652 static const
675 in QImode, HImode and SImode.
676 Relative to reg-reg move (2). */
680 in SFmode, DFmode and XFmode */
682 in SFmode, DFmode and XFmode */
685 in SImode and DImode */
687 in SImode and DImode */
690 in SImode, DImode and TImode */
692 in SImode, DImode and TImode */
696 have integrated l2 cache, but
697 optimizing for k6 is not important
698 enough to worry about that. */
708 k6_memcpy,
709 k6_memset,
721 };
723 /* For some reason, Athlon deals better with REP prefix (relative to loops)
724 compared to K8. Alignment becomes important after 8 bytes for memcpy and
725 128 bytes for memset. */
728 DUMMY_STRINGOP_ALGS};
731 DUMMY_STRINGOP_ALGS};
732 static const
755 in QImode, HImode and SImode.
756 Relative to reg-reg move (2). */
760 in SFmode, DFmode and XFmode */
762 in SFmode, DFmode and XFmode */
765 in SImode and DImode */
767 in SImode and DImode */
770 in SImode, DImode and TImode */
772 in SImode, DImode and TImode */
785 athlon_memcpy,
786 athlon_memset,
798 };
800 /* K8 has optimized REP instruction for medium sized blocks, but for very
801 small blocks it is better to use loop. For large blocks, libcall can
802 do nontemporary accesses and beat inline considerably. */
813 static const
836 in QImode, HImode and SImode.
837 Relative to reg-reg move (2). */
841 in SFmode, DFmode and XFmode */
843 in SFmode, DFmode and XFmode */
846 in SImode and DImode */
848 in SImode and DImode */
851 in SImode, DImode and TImode */
853 in SImode, DImode and TImode */
858 /* New AMD processors never drop prefetches; if they cannot be performed
859 immediately, they are queued. We set number of simultaneous prefetches
860 to a large constant to reflect this (it probably is not a good idea not
861 to limit number of prefetches at all, as their execution also takes some
862 time). */
872 k8_memcpy,
873 k8_memset,
885 };
887 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
888 very small blocks it is better to use loop. For large blocks, libcall can
889 do nontemporary accesses and beat inline considerably. */
922 in QImode, HImode and SImode.
923 Relative to reg-reg move (2). */
927 in SFmode, DFmode and XFmode */
929 in SFmode, DFmode and XFmode */
932 in SImode and DImode */
934 in SImode and DImode */
937 in SImode, DImode and TImode */
939 in SImode, DImode and TImode */
941 /* On K8:
942 MOVD reg64, xmmreg Double FSTORE 4
943 MOVD reg32, xmmreg Double FSTORE 4
944 On AMDFAM10:
945 MOVD reg64, xmmreg Double FADD 3
946 1/1 1/1
947 MOVD reg32, xmmreg Double FADD 3
948 1/1 1/1 */
952 /* New AMD processors never drop prefetches; if they cannot be performed
953 immediately, they are queued. We set number of simultaneous prefetches
954 to a large constant to reflect this (it probably is not a good idea not
955 to limit number of prefetches at all, as their execution also takes some
956 time). */
966 amdfam10_memcpy,
967 amdfam10_memset,
979 };
981 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
982 very small blocks it is better to use loop. For large blocks, libcall
983 can do nontemporary accesses and beat inline considerably. */
1017 in QImode, HImode and SImode.
1018 Relative to reg-reg move (2). */
1022 in SFmode, DFmode and XFmode */
1024 in SFmode, DFmode and XFmode */
1027 in SImode and DImode */
1029 in SImode and DImode */
1032 in SImode, DImode and TImode */
1034 in SImode, DImode and TImode */
1036 /* On K8:
1037 MOVD reg64, xmmreg Double FSTORE 4
1038 MOVD reg32, xmmreg Double FSTORE 4
1039 On AMDFAM10:
1040 MOVD reg64, xmmreg Double FADD 3
1041 1/1 1/1
1042 MOVD reg32, xmmreg Double FADD 3
1043 1/1 1/1 */
1047 /* New AMD processors never drop prefetches; if they cannot be performed
1048 immediately, they are queued. We set number of simultaneous prefetches
1049 to a large constant to reflect this (it probably is not a good idea not
1050 to limit number of prefetches at all, as their execution also takes some
1051 time). */
1061 bdver1_memcpy,
1062 bdver1_memset,
1074 };
1076 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1077 very small blocks it is better to use loop. For large blocks, libcall
1078 can do nontemporary accesses and beat inline considerably. */
1113 in QImode, HImode and SImode.
1114 Relative to reg-reg move (2). */
1118 in SFmode, DFmode and XFmode */
1120 in SFmode, DFmode and XFmode */
1123 in SImode and DImode */
1125 in SImode and DImode */
1128 in SImode, DImode and TImode */
1130 in SImode, DImode and TImode */
1132 /* On K8:
1133 MOVD reg64, xmmreg Double FSTORE 4
1134 MOVD reg32, xmmreg Double FSTORE 4
1135 On AMDFAM10:
1136 MOVD reg64, xmmreg Double FADD 3
1137 1/1 1/1
1138 MOVD reg32, xmmreg Double FADD 3
1139 1/1 1/1 */
1143 /* New AMD processors never drop prefetches; if they cannot be performed
1144 immediately, they are queued. We set number of simultaneous prefetches
1145 to a large constant to reflect this (it probably is not a good idea not
1146 to limit number of prefetches at all, as their execution also takes some
1147 time). */
1157 bdver2_memcpy,
1158 bdver2_memset,
1170 };
1173 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1174 very small blocks it is better to use loop. For large blocks, libcall
1175 can do nontemporary accesses and beat inline considerably. */
1208 in QImode, HImode and SImode.
1209 Relative to reg-reg move (2). */
1213 in SFmode, DFmode and XFmode */
1215 in SFmode, DFmode and XFmode */
1218 in SImode and DImode */
1220 in SImode and DImode */
1223 in SImode, DImode and TImode */
1225 in SImode, DImode and TImode */
1230 /* New AMD processors never drop prefetches; if they cannot be performed
1231 immediately, they are queued. We set number of simultaneous prefetches
1232 to a large constant to reflect this (it probably is not a good idea not
1233 to limit number of prefetches at all, as their execution also takes some
1234 time). */
1244 bdver3_memcpy,
1245 bdver3_memset,
1257 };
1259 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1260 very small blocks it is better to use loop. For large blocks, libcall
1261 can do nontemporary accesses and beat inline considerably. */
1294 in QImode, HImode and SImode.
1295 Relative to reg-reg move (2). */
1299 in SFmode, DFmode and XFmode */
1301 in SFmode, DFmode and XFmode */
1304 in SImode and DImode */
1306 in SImode and DImode */
1309 in SImode, DImode and TImode */
1311 in SImode, DImode and TImode */
1316 /* New AMD processors never drop prefetches; if they cannot be performed
1317 immediately, they are queued. We set number of simultaneous prefetches
1318 to a large constant to reflect this (it probably is not a good idea not
1319 to limit number of prefetches at all, as their execution also takes some
1320 time). */
1330 bdver4_memcpy,
1331 bdver4_memset,
1343 };
1345 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1346 very small blocks it is better to use loop. For large blocks, libcall can
1347 do nontemporary accesses and beat inline considerably. */
1380 in QImode, HImode and SImode.
1381 Relative to reg-reg move (2). */
1385 in SFmode, DFmode and XFmode */
1387 in SFmode, DFmode and XFmode */
1390 in SImode and DImode */
1392 in SImode and DImode */
1395 in SImode, DImode and TImode */
1397 in SImode, DImode and TImode */
1399 /* On K8:
1400 MOVD reg64, xmmreg Double FSTORE 4
1401 MOVD reg32, xmmreg Double FSTORE 4
1402 On AMDFAM10:
1403 MOVD reg64, xmmreg Double FADD 3
1404 1/1 1/1
1405 MOVD reg32, xmmreg Double FADD 3
1406 1/1 1/1 */
1419 btver1_memcpy,
1420 btver1_memset,
1432 };
1466 in QImode, HImode and SImode.
1467 Relative to reg-reg move (2). */
1471 in SFmode, DFmode and XFmode */
1473 in SFmode, DFmode and XFmode */
1476 in SImode and DImode */
1478 in SImode and DImode */
1481 in SImode, DImode and TImode */
1483 in SImode, DImode and TImode */
1485 /* On K8:
1486 MOVD reg64, xmmreg Double FSTORE 4
1487 MOVD reg32, xmmreg Double FSTORE 4
1488 On AMDFAM10:
1489 MOVD reg64, xmmreg Double FADD 3
1490 1/1 1/1
1491 MOVD reg32, xmmreg Double FADD 3
1492 1/1 1/1 */
1504 btver2_memcpy,
1505 btver2_memset,
1517 };
1521 DUMMY_STRINGOP_ALGS};
1525 DUMMY_STRINGOP_ALGS};
1527 static const
1550 in QImode, HImode and SImode.
1551 Relative to reg-reg move (2). */
1555 in SFmode, DFmode and XFmode */
1557 in SFmode, DFmode and XFmode */
1560 in SImode and DImode */
1562 in SImode and DImode */
1565 in SImode, DImode and TImode */
1567 in SImode, DImode and TImode */
1580 pentium4_memcpy,
1581 pentium4_memset,
1593 };
1606 static const
1629 in QImode, HImode and SImode.
1630 Relative to reg-reg move (2). */
1634 in SFmode, DFmode and XFmode */
1636 in SFmode, DFmode and XFmode */
1639 in SImode and DImode */
1641 in SImode and DImode */
1644 in SImode, DImode and TImode */
1646 in SImode, DImode and TImode */
1659 nocona_memcpy,
1660 nocona_memset,
1672 };
1683 static const
1706 in QImode, HImode and SImode.
1707 Relative to reg-reg move (2). */
1711 in SFmode, DFmode and XFmode */
1713 in SFmode, DFmode and XFmode */
1716 in SImode and DImode */
1718 in SImode and DImode */
1721 in SImode, DImode and TImode */
1723 in SImode, DImode and TImode */
1736 atom_memcpy,
1737 atom_memset,
1749 };
1760 static const
1783 in QImode, HImode and SImode.
1784 Relative to reg-reg move (2). */
1788 in SFmode, DFmode and XFmode */
1790 in SFmode, DFmode and XFmode */
1793 in SImode and DImode */
1795 in SImode and DImode */
1798 in SImode, DImode and TImode */
1800 in SImode, DImode and TImode */
1813 slm_memcpy,
1814 slm_memset,
1826 };
1837 static const
1860 in QImode, HImode and SImode.
1861 Relative to reg-reg move (2). */
1865 in SFmode, DFmode and XFmode */
1867 in SFmode, DFmode and XFmode */
1870 in SImode and DImode */
1872 in SImode and DImode */
1875 in SImode, DImode and TImode */
1877 in SImode, DImode and TImode */
1890 intel_memcpy,
1891 intel_memset,
1903 };
1905 /* Generic should produce code tuned for Core-i7 (and newer chips)
1906 and btver1 (and newer chips). */
1918 static const
1921 /* On all chips taken into consideration lea is 2 cycles and more. With
1922 this cost however our current implementation of synth_mult results in
1923 use of unnecessary temporary registers causing regression on several
1924 SPECfp benchmarks. */
1945 in QImode, HImode and SImode.
1946 Relative to reg-reg move (2). */
1950 in SFmode, DFmode and XFmode */
1952 in SFmode, DFmode and XFmode */
1955 in SImode and DImode */
1957 in SImode and DImode */
1960 in SImode, DImode and TImode */
1962 in SImode, DImode and TImode */
1968 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1969 value is increased to perhaps more appropriate value of 5. */
1977 generic_memcpy,
1978 generic_memset,
1990 };
1992 /* core_cost should produce code tuned for Core familly of CPUs. */
2005 static const
2008 /* On all chips taken into consideration lea is 2 cycles and more. With
2009 this cost however our current implementation of synth_mult results in
2010 use of unnecessary temporary registers causing regression on several
2011 SPECfp benchmarks. */
2032 in QImode, HImode and SImode.
2033 Relative to reg-reg move (2). */
2037 in SFmode, DFmode and XFmode */
2039 in SFmode, DFmode and XFmode */
2042 in SImode and DImode */
2044 in SImode and DImode */
2047 in SImode, DImode and TImode */
2049 in SImode, DImode and TImode */
2055 /* FIXME perhaps more appropriate value is 5. */
2063 core_memcpy,
2064 core_memset,
2076 };
2079 /* Set by -mtune. */
2082 /* Set by -mtune or -Os. */
2085 /* Processor feature/optimization bitmasks. */
2086 #define m_386 (1<<PROCESSOR_I386)
2087 #define m_486 (1<<PROCESSOR_I486)
2088 #define m_PENT (1<<PROCESSOR_PENTIUM)
2089 #define m_IAMCU (1<<PROCESSOR_IAMCU)
2090 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2091 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2092 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2093 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2094 #define m_CORE2 (1<<PROCESSOR_CORE2)
2095 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2096 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2097 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2098 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2099 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2100 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2101 #define m_KNL (1<<PROCESSOR_KNL)
2102 #define m_INTEL (1<<PROCESSOR_INTEL)
2104 #define m_GEODE (1<<PROCESSOR_GEODE)
2105 #define m_K6 (1<<PROCESSOR_K6)
2106 #define m_K6_GEODE (m_K6 | m_GEODE)
2107 #define m_K8 (1<<PROCESSOR_K8)
2108 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2109 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2110 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2111 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2112 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2113 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2114 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2115 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2116 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2117 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2118 #define m_BTVER (m_BTVER1 | m_BTVER2)
2119 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2121 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2124 #undef DEF_TUNE
2125 #define DEF_TUNE(tune, name, selector) name,
2127 #undef DEF_TUNE
2128 };
2130 /* Feature tests against the various tunings. */
2133 /* Feature tests against the various tunings used to create ix86_tune_features
2134 based on the processor mask. */
2136 #undef DEF_TUNE
2137 #define DEF_TUNE(tune, name, selector) selector,
2139 #undef DEF_TUNE
2140 };
2142 /* Feature tests against the various architecture variations. */
2145 /* Feature tests against the various architecture variations, used to create
2146 ix86_arch_features based on the processor mask. */
2148 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2151 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2154 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2157 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2160 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2162 };
2164 /* In case the average insn count for single function invocation is
2165 lower than this constant, emit fast (but longer) prologue and
2166 epilogue code. */
2167 #define FAST_PROLOGUE_INSN_COUNT 20
2169 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2174 /* Array of the smallest class containing reg number REGNO, indexed by
2175 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2178 {
2179 /* ax, dx, cx, bx */
2181 /* si, di, bp, sp */
2183 /* FP registers */
2186 /* arg pointer */
2187 NON_Q_REGS,
2188 /* flags, fpsr, fpcr, frame */
2190 /* SSE registers */
2193 /* MMX registers */
2196 /* REX registers */
2199 /* SSE REX registers */
2202 /* AVX-512 SSE registers */
2207 /* Mask registers. */
2210 /* MPX bound registers */
2212 };
2214 /* The "default" register map used in 32bit mode. */
2217 {
2229 };
2231 /* The "default" register map used in 64bit mode. */
2234 {
2246 };
2248 /* Define the register numbers to be used in Dwarf debugging information.
2249 The SVR4 reference port C compiler uses the following register numbers
2250 in its Dwarf output code:
2251 0 for %eax (gcc regno = 0)
2252 1 for %ecx (gcc regno = 2)
2253 2 for %edx (gcc regno = 1)
2254 3 for %ebx (gcc regno = 3)
2255 4 for %esp (gcc regno = 7)
2256 5 for %ebp (gcc regno = 6)
2257 6 for %esi (gcc regno = 4)
2258 7 for %edi (gcc regno = 5)
2259 The following three DWARF register numbers are never generated by
2260 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2261 believes these numbers have these meanings.
2262 8 for %eip (no gcc equivalent)
2263 9 for %eflags (gcc regno = 17)
2264 10 for %trapno (no gcc equivalent)
2265 It is not at all clear how we should number the FP stack registers
2266 for the x86 architecture. If the version of SDB on x86/svr4 were
2267 a bit less brain dead with respect to floating-point then we would
2268 have a precedent to follow with respect to DWARF register numbers
2269 for x86 FP registers, but the SDB on x86/svr4 is so completely
2270 broken with respect to FP registers that it is hardly worth thinking
2271 of it as something to strive for compatibility with.
2272 The version of x86/svr4 SDB I have at the moment does (partially)
2273 seem to believe that DWARF register number 11 is associated with
2274 the x86 register %st(0), but that's about all. Higher DWARF
2275 register numbers don't seem to be associated with anything in
2276 particular, and even for DWARF regno 11, SDB only seems to under-
2277 stand that it should say that a variable lives in %st(0) (when
2278 asked via an `=' command) if we said it was in DWARF regno 11,
2279 but SDB still prints garbage when asked for the value of the
2280 variable in question (via a `/' command).
2281 (Also note that the labels SDB prints for various FP stack regs
2282 when doing an `x' command are all wrong.)
2283 Note that these problems generally don't affect the native SVR4
2284 C compiler because it doesn't allow the use of -O with -g and
2285 because when it is *not* optimizing, it allocates a memory
2286 location for each floating-point variable, and the memory
2287 location is what gets described in the DWARF AT_location
2288 attribute for the variable in question.
2289 Regardless of the severe mental illness of the x86/svr4 SDB, we
2290 do something sensible here and we use the following DWARF
2291 register numbers. Note that these are all stack-top-relative
2292 numbers.
2293 11 for %st(0) (gcc regno = 8)
2294 12 for %st(1) (gcc regno = 9)
2295 13 for %st(2) (gcc regno = 10)
2296 14 for %st(3) (gcc regno = 11)
2297 15 for %st(4) (gcc regno = 12)
2298 16 for %st(5) (gcc regno = 13)
2299 17 for %st(6) (gcc regno = 14)
2300 18 for %st(7) (gcc regno = 15)
2301 */
2303 {
2315 };
2317 /* Define parameter passing and return registers. */
2320 {
2322 };
2325 {
2327 };
2330 {
2332 };
2334 /* Additional registers that are clobbered by SYSV calls. */
2337 {
2342 };
2344 /* Define the structure for the machine field in struct function. */
2349 rtx rtl;
2351 };
2353 /* Structure describing stack frame layout.
2354 Stack grows downward:
2356 [arguments]
2357 <- ARG_POINTER
2358 saved pc
2360 saved static chain if ix86_static_chain_on_stack
2362 saved frame pointer if frame_pointer_needed
2363 <- HARD_FRAME_POINTER
2364 [saved regs]
2365 <- regs_save_offset
2366 [padding0]
2368 [saved SSE regs]
2369 <- sse_regs_save_offset
2370 [padding1] |
2371 | <- FRAME_POINTER
2372 [va_arg registers] |
2373 |
2374 [frame] |
2375 |
2376 [padding2] | = to_allocate
2377 <- STACK_POINTER
2378 */
2379 struct ix86_frame
2380 {
2387 /* The offsets relative to ARG_POINTER. */
2388 HOST_WIDE_INT frame_pointer_offset;
2389 HOST_WIDE_INT hard_frame_pointer_offset;
2390 HOST_WIDE_INT stack_pointer_offset;
2391 HOST_WIDE_INT hfp_save_offset;
2392 HOST_WIDE_INT reg_save_offset;
2393 HOST_WIDE_INT sse_reg_save_offset;
2395 /* When save_regs_using_mov is set, emit prologue using
2396 move instead of push instructions. */
2398 };
2400 /* Which cpu are we scheduling for. */
2403 /* Which cpu are we optimizing for. */
2406 /* Which instruction set architecture to use. */
2409 /* True if processor has SSE prefetch instruction. */
2412 /* -mstackrealign option */
2430 /* Preferred alignment for stack boundary in bits. */
2433 /* Alignment for incoming stack boundary in bits specified at
2434 command line. */
2437 /* Default alignment for incoming stack boundary in bits. */
2440 /* Alignment for incoming stack boundary in bits. */
2443 /* Calling abi specific va_list type nodes. */
2447 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2451 /* Fence to use after loop using movnt. */
2452 tree x86_mfence;
2454 /* Register class used for passing given 64bit part of the argument.
2455 These represent classes as documented by the PS ABI, with the exception
2456 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2457 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2459 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2460 whenever possible (upper half does contain padding). */
2461 enum x86_64_reg_class
2462 {
2463 X86_64_NO_CLASS,
2464 X86_64_INTEGER_CLASS,
2465 X86_64_INTEGERSI_CLASS,
2466 X86_64_SSE_CLASS,
2467 X86_64_SSESF_CLASS,
2468 X86_64_SSEDF_CLASS,
2469 X86_64_SSEUP_CLASS,
2470 X86_64_X87_CLASS,
2471 X86_64_X87UP_CLASS,
2472 X86_64_COMPLEX_X87_CLASS,
2473 X86_64_MEMORY_CLASS
2474 };
2476 #define MAX_CLASSES 8
2478 /* Table of constants used by fldpi, fldln2, etc.... */
2482 \f
2487 const_tree);
2499 enum ix86_function_specific_strings
2500 {
2501 IX86_FUNCTION_SPECIFIC_ARCH,
2502 IX86_FUNCTION_SPECIFIC_TUNE,
2503 IX86_FUNCTION_SPECIFIC_MAX
2504 };
2526 \f
2527 #ifndef SUBTARGET32_DEFAULT_CPU
2529 #endif
2531 /* Whether -mtune= or -march= were specified */
2535 /* Vectorization library interface and handlers. */
2541 /* Processor target table, indexed by processor number */
2542 struct ptt
2543 {
2551 };
2553 /* This table must be in sync with enum processor_type in i386.h. */
2555 {
2583 };
2584 \f
2585 static unsigned int
2587 {
2590 /* vzeroupper instructions are inserted immediately after reload to
2591 account for possible spills from 256bit registers. The pass
2592 reuses mode switching infrastructure by re-running mode insertion
2593 pass, so disable entities that have already been processed. */
2599 /* Call optimize_mode_switching. */
2602 }
2607 {
2617 };
2620 {
2624 {}
2626 /* opt_pass methods: */
2628 {
2632 }
2635 {
2637 }
2643 rtl_opt_pass *
2645 {
2647 }
2649 /* Return true if a red-zone is in use. */
2653 {
2655 }
2656 \f
2657 /* Return a string that documents the current -m options. The caller is
2658 responsible for freeing the string. */
2664 {
2665 struct ix86_target_opts
2666 {
2669 };
2671 /* This table is ordered so that options like -msse4.2 that imply
2672 preceding options while match those first. */
2674 {
2728 };
2730 /* Flag options. */
2732 {
2761 };
2778 /* Add -march= option. */
2780 {
2783 }
2785 /* Add -mtune= option. */
2787 {
2790 }
2792 /* Add -m32/-m64/-mx32. */
2794 {
2797 else
2799 isa &= ~ (OPTION_MASK_ISA_64BIT
2800 | OPTION_MASK_ABI_64
2802 }
2803 else
2807 /* Pick out the options in isa options. */
2809 {
2811 {
2814 }
2815 }
2818 {
2821 isa);
2822 }
2824 /* Add flag options. */
2826 {
2828 {
2831 }
2832 }
2835 {
2838 }
2840 /* Add -fpmath= option. */
2842 {
2845 {
2860 }
2861 }
2863 /* Any options? */
2869 /* Size the string. */
2873 {
2878 }
2880 /* Build the string. */
2885 {
2892 {
2894 line_len++;
2897 {
2901 }
2902 }
2906 {
2910 }
2911 }
2917 }
2919 /* Return true, if profiling code should be emitted before
2920 prologue. Otherwise it returns false.
2921 Note: For x86 with "hotfix" it is sorried. */
2922 static bool
2924 {
2926 }
2928 /* Function that is callable from the debugger to print the current
2929 options. */
2930 void ATTRIBUTE_UNUSED
2932 {
2938 {
2941 }
2942 else
2946 }
2949 #define DEF_ENUM
2950 #define DEF_ALG(alg, name) #name,
2952 #undef DEF_ENUM
2953 #undef DEF_ALG
2954 };
2956 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2957 The string is of the following form (or comma separated list of it):
2959 strategy_alg:max_size:[align|noalign]
2961 where the full size range for the strategy is either [0, max_size] or
2962 [min_size, max_size], in which min_size is the max_size + 1 of the
2963 preceding range. The last size range must have max_size == -1.
2965 Examples:
2967 1.
2968 -mmemcpy-strategy=libcall:-1:noalign
2970 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2973 2.
2974 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2976 This is to tell the compiler to use the following strategy for memset
2977 1) when the expected size is between [1, 16], use rep_8byte strategy;
2978 2) when the size is between [17, 2048], use vector_loop;
2979 3) when the size is > 2048, use libcall. */
2981 struct stringop_size_range
2982 {
2984 stringop_alg alg;
2986 };
2988 static void
2990 {
2998 else
3003 do
3004 {
3014 {
3018 }
3021 {
3025 }
3032 {
3034 alg_name,
3037 }
3041 {
3042 /* rep; movq isn't available in 32-bit code. */
3045 alg_name,
3048 }
3056 else
3057 {
3061 }
3062 n++;
3064 }
3068 {
3073 }
3076 {
3080 }
3082 /* Now override the default algs array. */
3084 {
3090 }
3091 }
3093 \f
3094 /* parse -mtune-ctrl= option. When DUMP is true,
3095 print the features that are explicitly set. */
3097 static void
3099 {
3107 do
3108 {
3115 {
3116 curr_feature_string++;
3118 }
3120 {
3122 {
3128 }
3129 }
3134 }
3137 }
3139 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3140 processor type. */
3142 static void
3144 {
3149 {
3152 else
3154 }
3157 {
3162 }
3165 }
3168 /* Default align_* from the processor table. */
3170 static void
3172 {
3174 {
3177 }
3179 {
3182 }
3184 {
3186 }
3187 }
3189 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE hook. */
3191 static void
3193 {
3195 }
3197 /* Override various settings based on options. If MAIN_ARGS_P, the
3198 options are from the command line, otherwise they are from
3199 attributes. */
3201 static void
3205 {
3213 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3214 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3215 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3216 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3217 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3218 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3219 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3220 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3221 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3222 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3223 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3224 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3225 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3226 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3227 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3228 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3229 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3230 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3231 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3232 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3233 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3234 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3235 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3236 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3237 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3238 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3239 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3240 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3241 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3242 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3243 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3244 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3245 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3246 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3247 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3248 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3249 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3250 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3251 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3252 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3253 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3254 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3255 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3256 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3257 #define PTA_MPX (HOST_WIDE_INT_1 << 44)
3258 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3259 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3260 #define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
3261 #define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
3262 #define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
3263 #define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
3264 #define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
3265 #define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
3266 #define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 53)
3267 #define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 54)
3268 #define PTA_CLWB (HOST_WIDE_INT_1 << 55)
3269 #define PTA_PCOMMIT (HOST_WIDE_INT_1 << 56)
3270 #define PTA_MWAITX (HOST_WIDE_INT_1 << 57)
3272 #define PTA_CORE2 \
3273 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3274 | PTA_CX16 | PTA_FXSR)
3275 #define PTA_NEHALEM \
3276 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3277 #define PTA_WESTMERE \
3278 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3279 #define PTA_SANDYBRIDGE \
3280 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3281 #define PTA_IVYBRIDGE \
3282 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3283 #define PTA_HASWELL \
3284 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3285 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3286 #define PTA_BROADWELL \
3287 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3288 #define PTA_KNL \
3289 (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
3290 #define PTA_BONNELL \
3291 (PTA_CORE2 | PTA_MOVBE)
3292 #define PTA_SILVERMONT \
3293 (PTA_WESTMERE | PTA_MOVBE)
3295 /* if this reaches 64, need to widen struct pta flags below */
3297 static struct pta
3298 {
3303 }
3305 {
3340 PTA_SANDYBRIDGE},
3342 PTA_SANDYBRIDGE},
3344 PTA_IVYBRIDGE},
3346 PTA_IVYBRIDGE},
3438 PTA_64BIT
3440 };
3442 /* -mrecip options. */
3443 static struct
3444 {
3447 }
3449 {
3456 };
3460 /* Set up prefix/suffix so the error messages refer to either the command
3461 line argument, or the attribute(target). */
3463 {
3467 }
3468 else
3469 {
3473 }
3475 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3476 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3479 #ifdef TARGET_BI_ARCH
3480 else
3481 {
3482 #if TARGET_BI_ARCH == 1
3483 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3484 is on and OPTION_MASK_ABI_X32 is off. We turn off
3485 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3486 -mx32. */
3489 #else
3490 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3491 on and OPTION_MASK_ABI_64 is off. We turn off
3492 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3493 -m64 or OPTION_MASK_CODE16 is turned on by -m16. */
3497 #endif
3502 }
3503 #endif
3506 {
3507 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3508 OPTION_MASK_ABI_64 for TARGET_X32. */
3511 }
3514 | OPTION_MASK_ABI_X32
3517 {
3518 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3519 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3522 }
3524 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3525 SUBTARGET_OVERRIDE_OPTIONS;
3526 #endif
3528 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3529 SUBSUBTARGET_OVERRIDE_OPTIONS;
3530 #endif
3532 /* -fPIC is the default for x86_64. */
3536 /* Need to check -mtune=generic first. */
3538 {
3539 /* As special support for cross compilers we read -mtune=native
3540 as -mtune=generic. With native compilers we won't see the
3541 -mtune=native, as it was changed by the driver. */
3543 {
3545 }
3550 }
3551 else
3552 {
3556 {
3557 opts->x_ix86_tune_string
3560 }
3562 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3563 or defaulted. We need to use a sensible tune option. */
3565 {
3567 }
3568 }
3572 {
3573 /* rep; movq isn't available in 32-bit code. */
3576 }
3579 opts->x_ix86_arch_string
3582 else
3586 {
3594 }
3595 else
3602 /* For targets using ms ABI enable ms-extensions, if not
3603 explicit turned off. For non-ms ABI we turn off this
3604 option. */
3609 {
3611 {
3655 {
3658 }
3666 }
3667 }
3668 else
3669 {
3670 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3671 use of rip-relative addressing. This eliminates fixups that
3672 would otherwise be needed if this object is to be placed in a
3673 DLL, and is essentially just as efficient as direct addressing. */
3679 else
3681 }
3683 {
3686 }
3694 {
3697 /* Default cpu tuning to the architecture. */
3878 }
3887 {
3888 /* Verify that x87/MMX/SSE/AVX is off for -miamcu. */
3892 | OPTION_MASK_ISA_SSE
3898 }
3916 {
3920 {
3922 {
3924 {
3932 }
3933 else
3936 }
3937 }
3938 /* Intel CPUs have always interpreted SSE prefetch instructions as
3939 NOPs; so, we can enable SSE prefetch instructions even when
3940 -mtune (rather than -march) points us to a processor that has them.
3941 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3942 higher processors. */
3947 }
3955 #ifndef USE_IX86_FRAME_POINTER
3956 #define USE_IX86_FRAME_POINTER 0
3957 #endif
3959 #ifndef USE_X86_64_FRAME_POINTER
3960 #define USE_X86_64_FRAME_POINTER 0
3961 #endif
3963 /* Set the default values for switches whose default depends on TARGET_64BIT
3964 in case they weren't overwritten by command line options. */
3966 {
3974 opts->x_flag_unwind_tables
3978 }
3979 else
3980 {
3982 opts->x_flag_omit_frame_pointer
3987 {
3988 /* Intel MCU psABI specifies that -freg-struct-return should
3989 be on. Instead of setting DEFAULT_PCC_STRUCT_RETURN to 1,
3990 we check -miamcu so that -freg-struct-return is always
3991 turned on if -miamcu is used. */
3994 else
3996 }
3997 }
4000 /* TODO: ix86_cost should be chosen at instruction or function granuality
4001 so for cold code we use size_cost even in !optimize_size compilation. */
4004 else
4007 /* Arrange to set up i386_stack_locals for all functions. */
4010 /* Validate -mregparm= value. */
4012 {
4018 {
4022 }
4023 }
4028 /* Default align_* from the processor table. */
4031 /* Provide default for -mbranch-cost= value. */
4036 {
4037 opts->x_target_flags
4040 /* Enable by default the SSE and MMX builtins. Do allow the user to
4041 explicitly disable any of these. In particular, disabling SSE and
4042 MMX for kernel code is extremely useful. */
4044 opts->x_ix86_isa_flags
4051 }
4052 else
4053 {
4054 opts->x_target_flags
4058 opts->x_ix86_isa_flags
4061 /* i386 ABI does not specify red zone. It still makes sense to use it
4062 when programmer takes care to stack from being destroyed. */
4065 }
4067 /* Keep nonleaf frame pointers. */
4073 /* If we're doing fast math, we don't care about comparison order
4074 wrt NaNs. This lets us use a shorter comparison sequence. */
4078 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
4079 since the insns won't need emulation. */
4083 /* Likewise, if the target doesn't have a 387, or we've specified
4084 software floating point, don't use 387 inline intrinsics. */
4088 /* Turn on MMX builtins for -msse. */
4090 opts->x_ix86_isa_flags
4093 /* Enable SSE prefetch. */
4098 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
4101 opts->x_ix86_isa_flags
4104 /* Enable popcnt instruction for -msse4.2 or -mabm. */
4107 opts->x_ix86_isa_flags
4110 /* Enable lzcnt instruction for -mabm. */
4112 opts->x_ix86_isa_flags
4115 /* Validate -mpreferred-stack-boundary= value or default it to
4116 PREFERRED_STACK_BOUNDARY_DEFAULT. */
4119 {
4126 {
4130 else
4133 }
4134 else
4135 ix86_preferred_stack_boundary
4137 }
4139 /* Set the default value for -mstackrealign. */
4145 /* Validate -mincoming-stack-boundary= value or default it to
4146 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
4149 {
4157 else
4158 {
4159 ix86_user_incoming_stack_boundary
4161 ix86_incoming_stack_boundary
4163 }
4164 }
4166 #ifndef NO_PROFILE_COUNTERS
4169 #endif
4173 /* Accept -msseregparm only if at least SSE support is enabled. */
4179 {
4181 {
4183 {
4186 }
4189 {
4192 }
4193 }
4194 }
4195 /* For all chips supporting SSE2, -mfpmath=sse performs better than
4196 fpmath=387. The second is however default at many targets since the
4197 extra 80bit precision of temporaries is considered to be part of ABI.
4198 Overwrite the default at least for -ffast-math.
4199 TODO: -mfpmath=both seems to produce same performing code with bit
4200 smaller binaries. It is however not clear if register allocation is
4201 ready for this setting.
4202 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
4203 codegen. We may switch to 387 with -ffast-math for size optimized
4204 functions. */
4208 else
4211 /* If the i387 is disabled, then do not return values in it. */
4215 /* Use external vectorized library in vectorizing intrinsics. */
4218 {
4229 }
4235 /* If stack probes are required, the space used for large function
4236 arguments on the stack must also be probed, so enable
4237 -maccumulate-outgoing-args so this happens in the prologue. */
4240 {
4245 }
4247 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4248 {
4254 }
4256 /* When scheduling description is not available, disable scheduler pass
4257 so it won't slow down the compilation and make x87 code slower. */
4278 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4280 && HAVE_prefetch
4286 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4287 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4292 {
4295 {
4297 ix86_gen_tls_local_dynamic_base_64
4299 }
4300 else
4301 {
4303 ix86_gen_tls_local_dynamic_base_64
4305 }
4306 }
4307 else
4311 {
4322 }
4323 else
4324 {
4335 }
4337 #ifdef USE_IX86_CLD
4338 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4341 #endif
4344 {
4349 }
4351 {
4355 }
4357 {
4358 #if defined(PROFILE_BEFORE_PROLOGUE)
4360 #else
4362 #endif
4363 }
4373 /* Enable 128-bit AVX instruction generation
4374 for the auto-vectorizer. */
4380 {
4387 {
4390 {
4392 q++;
4393 }
4394 else
4399 else
4400 {
4403 {
4406 }
4409 {
4413 }
4414 }
4419 else
4421 }
4422 }
4429 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4430 for 64-bit Bionic. Also default long double to 64-bit for Intel
4431 MCU psABI. */
4436 ? MASK_LONG_DOUBLE_128
4439 /* Only one of them can be active. */
4443 /* Save the initial options in case the user does function specific
4444 options. */
4446 target_option_default_node = target_option_current_node
4449 /* Handle stack protector */
4451 opts->x_ix86_stack_protector_guard
4454 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4456 {
4460 }
4463 {
4467 }
4468 }
4470 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4472 static void
4474 {
4476 struct register_pass_info insert_vzeroupper_info
4479 };
4484 /* This needs to be done at start up. It's convenient to do it here. */
4486 }
4488 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
4491 {
4495 }
4497 /* Update register usage after having seen the compiler flags. */
4499 static void
4501 {
4504 /* For 32-bit targets, squash the REX registers. */
4506 {
4513 }
4515 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4523 {
4524 /* Set/reset conditionally defined registers from
4525 CALL_USED_REGISTERS initializer. */
4529 /* Calculate registers of CLOBBERED_REGS register set
4530 as call used registers from GENERAL_REGS register set. */
4534 }
4536 /* If MMX is disabled, squash the registers. */
4542 /* If SSE is disabled, squash the registers. */
4548 /* If the FPU is disabled, squash the registers. */
4554 /* If AVX512F is disabled, squash the registers. */
4556 {
4562 }
4564 /* If MPX is disabled, squash the registers. */
4568 }
4570 \f
4571 /* Save the current options */
4573 static void
4576 {
4612 /* The fields are char but the variables are not; make sure the
4613 values fit in the fields. */
4618 }
4620 /* Restore the current options */
4622 static void
4625 {
4631 /* We don't change -fPIC. */
4669 /* TODO: ix86_cost should be chosen at instruction or function granuality
4670 so for cold code we use size_cost even in !optimize_size compilation. */
4673 else
4676 /* Recreate the arch feature tests if the arch changed */
4678 {
4683 }
4685 /* Recreate the tune optimization tests */
4688 }
4690 /* Adjust target options after streaming them in. This is mainly about
4691 reconciling them with global options. */
4693 static void
4695 {
4696 /* flag_pic is a global option, but ix86_cmodel is target saved option
4697 partly computed from flag_pic. If flag_pic is on, adjust x_ix86_cmodel
4698 for PIC, or error out. */
4701 {
4720 }
4721 else
4723 {
4738 }
4739 }
4741 /* Print the current options */
4743 static void
4746 {
4764 {
4767 }
4768 }
4770 \f
4771 /* Inner function to process the attribute((target(...))), take an argument and
4772 set the current options from the argument. If we have a list, recursively go
4773 over the list. */
4775 static bool
4780 {
4784 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4785 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4786 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4787 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4788 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4790 enum ix86_opt_type
4791 {
4792 ix86_opt_unknown,
4793 ix86_opt_yes,
4794 ix86_opt_no,
4795 ix86_opt_str,
4796 ix86_opt_enum,
4797 ix86_opt_isa
4798 };
4800 static const struct
4801 {
4808 /* isa options */
4862 /* enum options */
4865 /* string options */
4869 /* flag options */
4871 OPT_mcld,
4872 MASK_CLD),
4875 OPT_mfancy_math_387,
4876 MASK_NO_FANCY_MATH_387),
4879 OPT_mieee_fp,
4880 MASK_IEEE_FP),
4883 OPT_minline_all_stringops,
4884 MASK_INLINE_ALL_STRINGOPS),
4887 OPT_minline_stringops_dynamically,
4888 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4891 OPT_mno_align_stringops,
4892 MASK_NO_ALIGN_STRINGOPS),
4895 OPT_mrecip,
4896 MASK_RECIP),
4898 };
4900 /* If this is a list, recurse to get the options. */
4902 {
4909 enum_opts_set))
4913 }
4916 {
4919 }
4921 /* Handle multiple arguments separated by commas. */
4925 {
4939 {
4943 }
4944 else
4945 {
4948 }
4950 /* Recognize no-xxx. */
4952 {
4956 }
4957 else
4960 /* Find the option. */
4964 {
4972 {
4977 }
4978 }
4980 /* Process the option. */
4982 {
4985 }
4988 {
4994 }
4997 {
5003 else
5005 }
5008 {
5010 {
5013 }
5014 else
5016 }
5019 {
5027 global_dc);
5028 else
5029 {
5032 }
5033 }
5035 else
5037 }
5040 }
5042 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
5044 tree
5048 {
5063 /* Process each of the options on the chain. */
5068 /* If the changed options are different from the default, rerun
5069 ix86_option_override_internal, and then save the options away.
5070 The string options are attribute options, and will be undone
5071 when we copy the save structure. */
5077 {
5078 /* If we are using the default tune= or arch=, undo the string assigned,
5079 and use the default. */
5090 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
5095 {
5098 }
5100 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
5103 /* Add any builtin functions with the new isa if any. */
5106 /* Save the current options unless we are validating options for
5107 #pragma. */
5114 /* Free up memory allocated to hold the strings */
5117 }
5120 }
5122 /* Hook to validate attribute((target("string"))). */
5124 static bool
5127 tree args,
5129 {
5134 /* attribute((target("default"))) does nothing, beyond
5135 affecting multi-versioning. */
5144 /* Get the optimization options of the current function. */
5150 /* Init func_options. */
5158 /* Initialize func_options to the default before its target options can
5159 be set. */
5172 {
5177 }
5180 }
5182 \f
5183 /* Hook to determine if one function can safely inline another. */
5185 static bool
5187 {
5192 /* If callee has no option attributes, then it is ok to inline. */
5196 /* If caller has no option attributes, but callee does then it is not ok to
5197 inline. */
5201 else
5202 {
5206 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
5207 can inline a SSE2 function but a SSE2 function can't inline a SSE4
5208 function. */
5213 /* See if we have the same non-isa options. */
5217 /* See if arch, tune, etc. are the same. */
5230 else
5232 }
5235 }
5237 \f
5238 /* Remember the last target of ix86_set_current_function. */
5241 /* Set targets globals to the default (or current #pragma GCC target
5242 if active). Invalidate ix86_previous_fndecl cache. */
5244 void
5246 {
5253 else
5256 }
5258 /* Establish appropriate back-end context for processing the function
5259 FNDECL. The argument might be NULL to indicate processing at top
5260 level, outside of any function scope. */
5261 static void
5263 {
5264 /* Only change the context if the function changes. This hook is called
5265 several times in the course of compiling a function, and we don't want to
5266 slow things down too much or call target_reinit when it isn't safe. */
5270 tree old_tree;
5275 else
5279 {
5283 }
5290 {
5296 else
5298 }
5300 }
5302 \f
5303 /* Return true if this goes in large data/bss. */
5305 static bool
5307 {
5311 /* Functions are never large data. */
5315 /* Automatic variables are never large data. */
5320 {
5326 }
5327 else
5328 {
5331 /* If this is an incomplete type with size 0, then we can't put it
5332 in data because it might be too big when completed. Also,
5333 int_size_in_bytes returns -1 if size can vary or is larger than
5334 an integer in which case also it is safer to assume that it goes in
5335 large data. */
5338 }
5341 }
5343 /* Switch to the appropriate section for output of DECL.
5344 DECL is either a `VAR_DECL' node or a constant of some sort.
5345 RELOC indicates whether forming the initial value of DECL requires
5346 link-time relocations. */
5351 {
5353 {
5357 {
5391 /* We don't split these for medium model. Place them into
5392 default sections and hope for best. */
5394 }
5396 {
5397 /* We might get called with string constants, but get_named_section
5398 doesn't like them as they are not DECLs. Also, we need to set
5399 flags in that case. */
5403 }
5404 }
5406 }
5408 /* Select a set of attributes for section NAME based on the properties
5409 of DECL and whether or not RELOC indicates that DECL's initializer
5410 might contain runtime relocations. */
5412 static unsigned int ATTRIBUTE_UNUSED
5414 {
5428 }
5430 /* Build up a unique section name, expressed as a
5431 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5432 RELOC indicates whether the initial value of EXP requires
5433 link-time relocations. */
5435 static void ATTRIBUTE_UNUSED
5437 {
5439 {
5441 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5445 {
5469 /* We don't split these for medium model. Place them into
5470 default sections and hope for best. */
5472 }
5474 {
5481 /* If we're using one_only, then there needs to be a .gnu.linkonce
5482 prefix to the section name. */
5489 }
5490 }
5492 }
5494 #ifdef COMMON_ASM_OP
5495 /* This says how to output assembler code to declare an
5496 uninitialized external linkage data object.
5498 For medium model x86-64 we need to use .largecomm opcode for
5499 large objects. */
5500 void
5504 {
5508 else
5513 }
5514 #endif
5516 /* Utility function for targets to use in implementing
5517 ASM_OUTPUT_ALIGNED_BSS. */
5519 void
5522 {
5526 else
5529 #ifdef ASM_DECLARE_OBJECT_NAME
5532 #else
5533 /* Standard thing is just output label for the object. */
5537 }
5538 \f
5539 /* Decide whether we must probe the stack before any space allocation
5540 on this target. It's essentially TARGET_STACK_PROBE except when
5541 -fstack-check causes the stack to be already probed differently. */
5543 bool
5545 {
5546 /* Do not probe the stack twice if static stack checking is enabled. */
5551 }
5552 \f
5553 /* Decide whether we can make a sibling call to a function. DECL is the
5554 declaration of the function being targeted by the call and EXP is the
5555 CALL_EXPR representing the call. */
5557 static bool
5559 {
5563 /* If we are generating position-independent code, we cannot sibcall
5564 optimize direct calls to global functions, as the PLT requires
5565 %ebx be live. (Darwin does not have a PLT.) */
5567 && !TARGET_64BIT
5568 && flag_pic
5569 && flag_plt
5573 /* If we need to align the outgoing stack, then sibcalling would
5574 unalign the stack, which may break the called function. */
5580 {
5583 }
5584 else
5585 {
5586 /* We're looking at the CALL_EXPR, we need the type of the function. */
5591 }
5593 /* Check that the return value locations are the same. Like
5594 if we are returning floats on the 80387 register stack, we cannot
5595 make a sibcall from a function that doesn't return a float to a
5596 function that does or, conversely, from a function that does return
5597 a float to a function that doesn't; the necessary stack adjustment
5598 would not be executed. This is also the place we notice
5599 differences in the return value ABI. Note that it is ok for one
5600 of the functions to have void return type as long as the return
5601 value of the other is passed in a register. */
5606 {
5609 }
5611 ;
5616 {
5617 /* The SYSV ABI has more call-clobbered registers;
5618 disallow sibcalls from MS to SYSV. */
5622 }
5623 else
5624 {
5625 /* If this call is indirect, we'll need to be able to use a
5626 call-clobbered register for the address of the target function.
5627 Make sure that all such registers are not used for passing
5628 parameters. Note that DLLIMPORT functions are indirect. */
5631 {
5632 /* Check if regparm >= 3 since arg_reg_available is set to
5633 false if regparm == 0. If regparm is 1 or 2, there is
5634 always a call-clobbered register available.
5636 ??? The symbol indirect call doesn't need a call-clobbered
5637 register. But we don't know if this is a symbol indirect
5638 call or not here. */
5642 }
5643 }
5645 /* Otherwise okay. That also includes certain types of indirect calls. */
5647 }
5649 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5650 and "sseregparm" calling convention attributes;
5651 arguments as in struct attribute_spec.handler. */
5653 static tree
5655 tree args,
5658 {
5663 {
5665 name);
5668 }
5670 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5672 {
5673 tree cst;
5676 {
5678 }
5681 {
5683 }
5687 {
5690 name);
5692 }
5694 {
5698 }
5701 }
5704 {
5705 /* Do not warn when emulating the MS ABI. */
5710 name);
5713 }
5715 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5717 {
5719 {
5721 }
5723 {
5725 }
5727 {
5729 }
5731 {
5733 }
5734 }
5736 /* Can combine stdcall with fastcall (redundant), regparm and
5737 sseregparm. */
5739 {
5741 {
5743 }
5745 {
5747 }
5749 {
5751 }
5752 }
5754 /* Can combine cdecl with regparm and sseregparm. */
5756 {
5758 {
5760 }
5762 {
5764 }
5766 {
5768 }
5769 }
5771 {
5774 name);
5776 {
5778 }
5780 {
5782 }
5784 {
5786 }
5787 }
5789 /* Can combine sseregparm with all attributes. */
5792 }
5794 /* The transactional memory builtins are implicitly regparm or fastcall
5795 depending on the ABI. Override the generic do-nothing attribute that
5796 these builtins were declared with, and replace it with one of the two
5797 attributes that we expect elsewhere. */
5799 static tree
5802 {
5803 tree alt;
5805 /* In no case do we want to add the placeholder attribute. */
5808 /* The 64-bit ABI is unchanged for transactional memory. */
5812 /* ??? Is there a better way to validate 32-bit windows? We have
5813 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5816 else
5817 {
5820 }
5824 }
5826 /* This function determines from TYPE the calling-convention. */
5828 unsigned int
5830 {
5833 tree attrs;
5840 {
5850 /* Regparam isn't allowed for thiscall and fastcall. */
5852 {
5857 }
5861 }
5868 || is_stdarg
5874 }
5876 /* Return 0 if the attributes for two types are incompatible, 1 if they
5877 are compatible, and 2 if they are nearly compatible (which causes a
5878 warning to be generated). */
5880 static int
5882 {
5898 }
5899 \f
5900 /* Return the regparm value for a function with the indicated TYPE and DECL.
5901 DECL may be NULL when calling function indirectly
5902 or considering a libcall. */
5904 static int
5906 {
5907 tree attr;
5918 {
5921 {
5924 }
5925 }
5931 /* Use register calling convention for local functions when possible. */
5934 {
5939 /* Caller and callee must agree on the calling convention, so
5940 checking here just optimize means that with
5941 __attribute__((optimize (...))) caller could use regparm convention
5942 and callee not, or vice versa. Instead look at whether the callee
5943 is optimized or not. */
5946 {
5949 {
5952 /* Make sure no regparm register is taken by a
5953 fixed register variable. */
5955 local_regparm++)
5959 /* We don't want to use regparm(3) for nested functions as
5960 these use a static chain pointer in the third argument. */
5964 /* Save a register for the split stack. */
5968 /* Each fixed register usage increases register pressure,
5969 so less registers should be used for argument passing.
5970 This functionality can be overriden by an explicit
5971 regparm value. */
5974 globals++;
5976 local_regparm
5981 }
5982 }
5983 }
5986 }
5988 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5989 DFmode (2) arguments in SSE registers for a function with the
5990 indicated TYPE and DECL. DECL may be NULL when calling function
5991 indirectly or considering a libcall. Return -1 if any FP parameter
5992 should be rejected by error. This is used in siutation we imply SSE
5993 calling convetion but the function is called from another function with
5994 SSE disabled. Otherwise return 0. */
5996 static int
5998 {
6001 /* Use SSE registers to pass SFmode and DFmode arguments if requested
6002 by the sseregparm attribute. */
6005 {
6007 {
6009 {
6013 else
6016 }
6018 }
6021 }
6030 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
6031 (and DFmode for SSE2) arguments in SSE registers. */
6033 /* TARGET_SSE_MATH */
6037 {
6040 {
6041 /* Refuse to produce wrong code when local function with SSE enabled
6042 is called from SSE disabled function.
6043 FIXME: We need a way to detect these cases cross-ltrans partition
6044 and avoid using SSE calling conventions on local functions called
6045 from function with SSE disabled. For now at least delay the
6046 warning until we know we are going to produce wrong code.
6047 See PR66047 */
6052 }
6053 }
6056 }
6058 /* Return true if EAX is live at the start of the function. Used by
6059 ix86_expand_prologue to determine if we need special help before
6060 calling allocate_stack_worker. */
6062 static bool
6064 {
6065 /* Cheat. Don't bother working forward from ix86_function_regparm
6066 to the function type to whether an actual argument is located in
6067 eax. Instead just look at cfg info, which is still close enough
6068 to correct at this point. This gives false positives for broken
6069 functions that might use uninitialized data that happens to be
6070 allocated in eax, but who cares? */
6072 }
6074 static bool
6076 {
6077 tree attr;
6080 {
6086 /* For 32-bit MS-ABI the default is to keep aggregate
6087 return pointer. */
6090 }
6092 }
6094 /* Value is the number of bytes of arguments automatically
6095 popped when returning from a subroutine call.
6096 FUNDECL is the declaration node of the function (as a tree),
6097 FUNTYPE is the data type of the function (as a tree),
6098 or for a library call it is an identifier node for the subroutine name.
6099 SIZE is the number of bytes of arguments passed on the stack.
6101 On the 80386, the RTD insn may be used to pop them if the number
6102 of args is fixed, but if the number is variable then the caller
6103 must pop them all. RTD can't be used for library calls now
6104 because the library is compiled with the Unix compiler.
6105 Use of RTD is a selectable option, since it is incompatible with
6106 standard Unix calling sequences. If the option is not selected,
6107 the caller must always pop the args.
6109 The attribute stdcall is equivalent to RTD on a per module basis. */
6111 static int
6113 {
6116 /* None of the 64-bit ABIs pop arguments. */
6127 /* Lose any fake structure return argument if it is passed on the stack. */
6130 {
6134 }
6137 }
6139 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
6141 static bool
6143 {
6144 /* Check operand constraints in case hard registers were propagated
6145 into insn pattern. This check prevents combine pass from
6146 generating insn patterns with invalid hard register operands.
6147 These invalid insns can eventually confuse reload to error out
6148 with a spill failure. See also PRs 46829 and 46843. */
6150 {
6159 {
6167 /* For pre-AVX disallow unaligned loads/stores where the
6168 instructions don't support it. */
6172 {
6176 }
6178 /* A unary operator may be accepted by the predicate, but it
6179 is irrelevant for matching constraints. */
6184 {
6192 }
6199 /* Operand has no constraints, anything is OK. */
6204 {
6209 && operands_match_p
6213 {
6216 }
6217 }
6221 }
6222 }
6225 }
6226 \f
6227 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
6229 static unsigned HOST_WIDE_INT
6231 {
6235 }
6236 \f
6237 /* Argument support functions. */
6239 /* Return true when register may be used to pass function parameters. */
6240 bool
6242 {
6251 {
6255 else
6261 }
6267 /* TODO: The function should depend on current function ABI but
6268 builtins.c would need updating then. Therefore we use the
6269 default ABI. */
6272 /* RAX is used as hidden argument to va_arg functions. */
6278 else
6286 }
6288 /* Return if we do not know how to pass TYPE solely in registers. */
6290 static bool
6292 {
6296 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
6297 The layout_type routine is crafty and tries to trick us into passing
6298 currently unsupported vector types on the stack by using TImode. */
6301 }
6303 /* It returns the size, in bytes, of the area reserved for arguments passed
6304 in registers for the function represented by fndecl dependent to the used
6305 abi format. */
6306 int
6308 {
6312 else
6317 }
6319 /* We add this as a workaround in order to use libc_has_function
6320 hook in i386.md. */
6321 bool
6323 {
6325 }
6327 /* Returns value SYSV_ABI, MS_ABI dependent on fntype,
6328 specifying the call abi used. */
6329 enum calling_abi
6331 {
6339 {
6344 }
6350 }
6352 static enum calling_abi
6354 {
6356 }
6358 /* Returns value SYSV_ABI, MS_ABI dependent on cfun,
6359 specifying the call abi used. */
6360 enum calling_abi
6362 {
6364 }
6366 static bool
6368 {
6370 {
6374 else
6376 }
6378 }
6380 /* Write the extra assembler code needed to declare a function properly. */
6382 void
6384 tree decl)
6385 {
6389 {
6395 }
6397 #ifdef SUBTARGET_ASM_UNWIND_INIT
6399 #endif
6403 /* Output magic byte marker, if hot-patch attribute is set. */
6405 {
6407 {
6408 /* leaq [%rsp + 0], %rsp */
6411 }
6412 else
6413 {
6414 /* movl.s %edi, %edi
6415 push %ebp
6416 movl.s %esp, %ebp */
6419 }
6420 }
6421 }
6423 /* regclass.c */
6426 /* Implementation of call abi switching target hook. Specific to FNDECL
6427 the specific call register sets are set. See also
6428 ix86_conditional_register_usage for more details. */
6429 void
6431 {
6433 }
6435 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6436 expensive re-initialization of init_regs each time we switch function context
6437 since this is needed only during RTL expansion. */
6438 static void
6440 {
6444 }
6446 /* Return 1 if pseudo register should be created and used to hold
6447 GOT address for PIC code. */
6448 bool
6450 {
6457 }
6459 /* Initialize large model PIC register. */
6461 static void
6463 {
6465 rtx tmp_reg;
6474 label));
6478 }
6480 /* Create and initialize PIC register if required. */
6481 static void
6483 {
6484 edge entry_edge;
6493 {
6496 else
6498 }
6499 else
6500 {
6501 /* If there is future mcount call in the function it is more profitable
6502 to emit SET_GOT into ABI defined REAL_PIC_OFFSET_TABLE_REGNUM. */
6511 }
6519 }
6521 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6522 for a call to a function whose data type is FNTYPE.
6523 For a library call, FNTYPE is 0. */
6525 void
6529 tree fndecl,
6531 {
6538 {
6541 {
6545 }
6546 else
6548 }
6549 else
6554 /* Set up the number of registers to use for passing arguments. */
6557 {
6559 ? X86_64_REGPARM_MAX
6561 }
6563 {
6566 {
6568 ? X86_64_SSE_REGPARM_MAX
6570 }
6571 }
6579 /* Because type might mismatch in between caller and callee, we need to
6580 use actual type of function for local calls.
6581 FIXME: cgraph_analyze can be told to actually record if function uses
6582 va_start so for local functions maybe_vaarg can be made aggressive
6583 helping K&R code.
6584 FIXME: once typesytem is fixed, we won't need this code anymore. */
6598 {
6599 /* If there are variable arguments, then we won't pass anything
6600 in registers in 32-bit mode. */
6602 {
6604 /* Since in 32-bit, variable arguments are always passed on
6605 stack, there is scratch register available for indirect
6606 sibcall. */
6615 }
6617 /* Use ecx and edx registers if function has fastcall attribute,
6618 else look for regparm information. */
6620 {
6623 {
6626 }
6628 {
6631 }
6632 else
6634 }
6636 /* Set up the number of SSE registers used for passing SFmode
6637 and DFmode arguments. Warn for mismatching ABI. */
6639 }
6642 }
6644 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6645 But in the case of vector types, it is some vector mode.
6647 When we have only some of our vector isa extensions enabled, then there
6648 are some modes for which vector_mode_supported_p is false. For these
6649 modes, the generic vector support in gcc will choose some non-vector mode
6650 in order to implement the type. By computing the natural mode, we'll
6651 select the proper ABI location for the operand and not depend on whatever
6652 the middle-end decides to do with these vector types.
6654 The midde-end can't deal with the vector types > 16 bytes. In this
6655 case, we return the original mode and warn ABI change if CUM isn't
6656 NULL.
6658 If INT_RETURN is true, warn ABI change if the vector mode isn't
6659 available for function return value. */
6661 static machine_mode
6664 {
6668 {
6671 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6673 {
6678 else
6681 /* Get the mode which has this inner mode and number of units. */
6685 {
6687 {
6692 {
6696 }
6698 {
6702 }
6705 }
6707 {
6712 {
6716 }
6718 {
6722 }
6725 }
6727 && !TARGET_SSE
6729 {
6734 {
6738 }
6740 {
6744 }
6745 }
6747 && !TARGET_MMX
6749 {
6754 {
6758 }
6760 {
6764 }
6765 }
6767 }
6770 }
6771 }
6774 }
6776 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6777 this may not agree with the mode that the type system has chosen for the
6778 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6779 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6781 static rtx
6784 {
6785 rtx tmp;
6789 else
6790 {
6794 }
6797 }
6799 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6800 of this code is to classify each 8bytes of incoming argument by the register
6801 class and assign registers accordingly. */
6803 /* Return the union class of CLASS1 and CLASS2.
6804 See the x86-64 PS ABI for details. */
6806 static enum x86_64_reg_class
6808 {
6809 /* Rule #1: If both classes are equal, this is the resulting class. */
6813 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6814 the other class. */
6820 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6824 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6832 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6833 MEMORY is used. */
6842 /* Rule #6: Otherwise class SSE is used. */
6844 }
6846 /* Classify the argument of type TYPE and mode MODE.
6847 CLASSES will be filled by the register class used to pass each word
6848 of the operand. The number of words is returned. In case the parameter
6849 should be passed in memory, 0 is returned. As a special case for zero
6850 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6852 BIT_OFFSET is used internally for handling records and specifies offset
6853 of the offset in bits modulo 512 to avoid overflow cases.
6855 See the x86-64 PS ABI for details.
6856 */
6858 static int
6861 {
6862 HOST_WIDE_INT bytes =
6864 int words
6867 /* Variable sized entities are always passed/returned in memory. */
6876 {
6878 tree field;
6881 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6888 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6889 signalize memory class, so handle it as special case. */
6891 {
6894 }
6896 /* Classify each field of record and merge classes. */
6898 {
6900 /* And now merge the fields of structure. */
6902 {
6904 {
6910 /* Bitfields are always classified as integer. Handle them
6911 early, since later code would consider them to be
6912 misaligned integers. */
6914 {
6923 }
6924 else
6925 {
6930 /* Flexible array member is ignored. */
6937 {
6941 {
6944 "the ABI of passing struct with"
6945 " a flexible array member has"
6947 }
6949 }
6951 subclasses,
6961 }
6962 }
6963 }
6967 /* Arrays are handled as small records. */
6968 {
6975 /* The partial classes are now full classes. */
6986 }
6989 /* Unions are similar to RECORD_TYPE but offset is always 0.
6990 */
6992 {
6994 {
7002 bit_offset);
7007 }
7008 }
7013 }
7016 {
7017 /* When size > 16 bytes, if the first one isn't
7018 X86_64_SSE_CLASS or any other ones aren't
7019 X86_64_SSEUP_CLASS, everything should be passed in
7020 memory. */
7027 }
7029 /* Final merger cleanup. */
7031 {
7032 /* If one class is MEMORY, everything should be passed in
7033 memory. */
7037 /* The X86_64_SSEUP_CLASS should be always preceded by
7038 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
7042 {
7043 /* The first one should never be X86_64_SSEUP_CLASS. */
7046 }
7048 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
7049 everything should be passed in memory. */
7052 {
7055 /* The first one should never be X86_64_X87UP_CLASS. */
7058 {
7061 "the ABI of passing union with long double"
7063 }
7065 }
7066 }
7068 }
7070 /* Compute alignment needed. We align all types to natural boundaries with
7071 exception of XFmode that is aligned to 64bits. */
7073 {
7082 /* Misaligned fields are always returned in memory. */
7085 }
7087 /* for V1xx modes, just use the base mode */
7092 /* Classification of atomic types. */
7094 {
7110 {
7113 /* Analyze last 128 bits only. */
7117 {
7120 }
7122 {
7125 }
7127 {
7131 }
7133 {
7136 }
7137 else
7139 }
7146 /* OImode shouldn't be used directly. */
7153 else
7171 else
7172 {
7176 {
7179 "the ABI of passing structure with complex float"
7181 }
7184 }
7193 /* This modes is larger than 16 bytes. */
7251 else
7255 }
7256 }
7258 /* Examine the argument and return set number of register required in each
7259 class. Return true iff parameter should be passed in memory. */
7261 static bool
7264 {
7275 {
7296 }
7299 }
7301 /* Construct container for the argument used by GCC interface. See
7302 FUNCTION_ARG for the detailed description. */
7304 static rtx
7308 {
7309 /* The following variables hold the static issued_error state. */
7314 machine_mode tmpmode;
7323 rtx ret;
7334 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
7335 some less clueful developer tries to use floating-point anyway. */
7337 {
7339 {
7341 {
7344 }
7345 }
7347 {
7350 }
7352 }
7354 /* Likewise, error if the ABI requires us to return values in the
7355 x87 registers and the user specified -mno-80387. */
7361 {
7363 {
7366 }
7368 }
7370 /* First construct simple cases. Avoid SCmode, since we want to use
7371 single register to pass this type. */
7374 {
7389 /* Zero sized array, struct or class. */
7393 }
7432 /* Otherwise figure out the entries of the PARALLEL. */
7434 {
7438 {
7443 /* Merge TImodes on aligned occasions here too. */
7445 tmpmode
7449 else
7451 /* We've requested 24 bytes we
7452 don't have mode for. Use DImode. */
7459 intreg++;
7467 sse_regno++;
7475 sse_regno++;
7480 {
7486 {
7488 i++;
7489 }
7490 else
7515 }
7521 sse_regno++;
7525 }
7526 }
7528 /* Empty aligned struct, union or class. */
7536 }
7538 /* Update the data in CUM to advance over an argument of mode MODE
7539 and data type TYPE. (TYPE is null for libcalls where that information
7540 may not be available.)
7542 Return a number of integer regsiters advanced over. */
7544 static int
7547 HOST_WIDE_INT words)
7548 {
7553 {
7554 /* Intel MCU psABI passes scalars and aggregates no larger than 8
7555 bytes in registers. */
7559 }
7562 {
7569 /* FALLTHRU */
7575 pass_in_reg:
7582 {
7586 }
7590 /* OImode shouldn't be used directly. */
7603 /* FALLTHRU */
7625 {
7630 {
7633 }
7634 }
7644 {
7649 {
7652 }
7653 }
7655 }
7657 {
7663 }
7666 }
7668 static int
7671 {
7674 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7681 {
7687 }
7688 else
7689 {
7694 }
7695 }
7697 static int
7699 HOST_WIDE_INT words)
7700 {
7701 /* Otherwise, this should be passed indirect. */
7706 {
7710 }
7712 }
7714 /* Update the data in CUM to advance over an argument of mode MODE and
7715 data type TYPE. (TYPE is null for libcalls where that information
7716 may not be available.) */
7718 static void
7721 {
7728 else
7737 {
7738 /* If we pass bounds in BT then just update remained bounds count. */
7740 {
7743 }
7745 /* Update remained number of bounds to force. */
7752 }
7754 /* The first arg not going to Bounds Tables resets this counter. */
7756 /* For unnamed args we always pass bounds to avoid bounds mess when
7757 passed and received types do not match. If bounds do not follow
7758 unnamed arg, still pretend required number of bounds were passed. */
7760 {
7763 }
7766 {
7771 else
7773 }
7774 else
7777 /* For stdarg we expect bounds to be passed for each value passed
7778 in register. */
7781 /* For pointers passed in memory we expect bounds passed in Bounds
7782 Table. */
7785 }
7787 /* Define where to put the arguments to a function.
7788 Value is zero to push the argument on the stack,
7789 or a hard register in which to store the argument.
7791 MODE is the argument's machine mode.
7792 TYPE is the data type of the argument (as a tree).
7793 This is null for libcalls where that information may
7794 not be available.
7795 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7796 the preceding args and about the function being called.
7797 NAMED is nonzero if this argument is a named parameter
7798 (otherwise it is an extra parameter matching an ellipsis). */
7800 static rtx
7804 {
7806 /* Avoid the AL settings for the Unix64 ABI. */
7811 {
7812 /* Intel MCU psABI passes scalars and aggregates no larger than 8
7813 bytes in registers. */
7817 }
7820 {
7827 /* FALLTHRU */
7832 pass_in_reg:
7834 {
7837 /* Fastcall allocates the first two DWORD (SImode) or
7838 smaller arguments to ECX and EDX if it isn't an
7839 aggregate type . */
7841 {
7847 /* ECX not EAX is the first allocated register. */
7850 }
7852 }
7865 /* FALLTHRU */
7867 /* In 32bit, we pass TImode in xmm registers. */
7875 {
7879 }
7884 /* OImode and XImode shouldn't be used directly. */
7900 {
7904 }
7914 {
7918 }
7920 }
7922 {
7928 }
7931 }
7933 static rtx
7936 {
7937 /* Handle a hidden AL argument containing number of registers
7938 for varargs x86-64 functions. */
7942 ? X86_64_SSE_REGPARM_MAX
7947 {
7963 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7967 }
7973 }
7975 static rtx
7978 HOST_WIDE_INT bytes)
7979 {
7982 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7983 We use value of -2 to specify that current function call is MSABI. */
7987 /* If we've run out of registers, it goes on the stack. */
7993 /* Only floating point modes are passed in anything but integer regs. */
7995 {
7998 else
7999 {
8002 /* Unnamed floating parameters are passed in both the
8003 SSE and integer registers. */
8009 }
8010 }
8011 /* Handle aggregated types passed in register. */
8013 {
8018 }
8021 }
8023 /* Return where to put the arguments to a function.
8024 Return zero to push the argument on the stack, or a hard register in which to store the argument.
8026 MODE is the argument's machine mode. TYPE is the data type of the
8027 argument. It is null for libcalls where that information may not be
8028 available. CUM gives information about the preceding args and about
8029 the function being called. NAMED is nonzero if this argument is a
8030 named parameter (otherwise it is an extra parameter matching an
8031 ellipsis). */
8033 static rtx
8036 {
8040 rtx arg;
8042 /* All pointer bounds argumntas are handled separately here. */
8045 {
8046 /* Return NULL if bounds are forced to go in Bounds Table. */
8049 /* Return the next available bound reg if any. */
8052 /* Return the next special slot number otherwise. */
8053 else
8057 }
8061 else
8065 /* To simplify the code below, represent vector types with a vector mode
8066 even if MMX/SSE are not active. */
8071 {
8076 else
8078 }
8079 else
8083 }
8085 /* A C expression that indicates when an argument must be passed by
8086 reference. If nonzero for an argument, a copy of that argument is
8087 made in memory and a pointer to the argument is passed instead of
8088 the argument itself. The pointer is passed in whatever way is
8089 appropriate for passing a pointer to that type. */
8091 static bool
8094 {
8097 /* Bounds are never passed by reference. */
8103 {
8106 /* See Windows x64 Software Convention. */
8108 {
8112 {
8113 /* Arrays are passed by reference. */
8118 {
8119 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
8120 are passed by reference. */
8122 }
8123 }
8125 /* __m128 is passed by reference. */
8127 }
8130 }
8133 }
8135 /* Return true when TYPE should be 128bit aligned for 32bit argument
8136 passing ABI. XXX: This function is obsolete and is only used for
8137 checking psABI compatibility with previous versions of GCC. */
8139 static bool
8141 {
8153 {
8154 /* Walk the aggregates recursively. */
8156 {
8160 {
8161 tree field;
8163 /* Walk all the structure fields. */
8165 {
8169 }
8171 }
8174 /* Just for use if some languages passes arrays by value. */
8181 }
8182 }
8184 }
8186 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
8187 XXX: This function is obsolete and is only used for checking psABI
8188 compatibility with previous versions of GCC. */
8190 static unsigned int
8193 {
8194 /* In 32bit, only _Decimal128 and __float128 are aligned to their
8195 natural boundaries. */
8197 {
8198 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
8199 make an exception for SSE modes since these require 128bit
8200 alignment.
8202 The handling here differs from field_alignment. ICC aligns MMX
8203 arguments to 4 byte boundaries, while structure fields are aligned
8204 to 8 byte boundaries. */
8206 {
8209 }
8210 else
8211 {
8214 }
8215 }
8219 }
8221 /* Return true when TYPE should be 128bit aligned for 32bit argument
8222 passing ABI. */
8224 static bool
8226 {
8236 {
8237 /* Walk the aggregates recursively. */
8239 {
8243 {
8244 tree field;
8246 /* Walk all the structure fields. */
8248 field;
8250 {
8254 }
8256 }
8259 /* Just for use if some languages passes arrays by value. */
8266 }
8267 }
8268 else
8272 }
8274 /* Gives the alignment boundary, in bits, of an argument with the
8275 specified mode and type. */
8277 static unsigned int
8279 {
8282 {
8283 /* Since the main variant type is used for call, we convert it to
8284 the main variant type. */
8287 }
8288 else
8292 else
8293 {
8298 {
8299 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
8301 {
8304 }
8310 }
8313 && !warned
8315 saved_align))
8316 {
8319 "The ABI for passing parameters with %d-byte"
8322 }
8323 }
8326 }
8328 /* Return true if N is a possible register number of function value. */
8330 static bool
8332 {
8334 {
8347 /* Complex values are returned in %st(0)/%st(1) pair. */
8350 /* TODO: The function should depend on current function ABI but
8351 builtins.c would need updating then. Therefore we use the
8352 default ABI. */
8357 /* Complex values are returned in %xmm0/%xmm1 pair. */
8366 }
8369 }
8371 /* Define how to find the value returned by a function.
8372 VALTYPE is the data type of the value (as a tree).
8373 If the precise function being called is known, FUNC is its FUNCTION_DECL;
8374 otherwise, FUNC is 0. */
8376 static rtx
8379 {
8382 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
8383 we normally prevent this case when mmx is not available. However
8384 some ABIs may require the result to be returned like DImode. */
8388 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
8389 we prevent this case when sse is not available. However some ABIs
8390 may require the result to be returned like integer TImode. */
8395 /* 32-byte vector modes in %ymm0. */
8399 /* 64-byte vector modes in %zmm0. */
8403 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
8406 else
8407 /* Most things go in %eax. */
8410 /* Override FP return register with %xmm0 for local functions when
8411 SSE math is enabled or for functions with sseregparm attribute. */
8413 {
8416 {
8421 }
8425 }
8427 /* OImode shouldn't be used directly. */
8431 }
8433 static rtx
8435 const_tree valtype)
8436 {
8437 rtx ret;
8439 /* Handle libcalls, which don't provide a type node. */
8441 {
8445 {
8464 }
8467 }
8469 {
8470 /* Pointers are always returned in word_mode. */
8472 }
8478 /* For zero sized structures, construct_container returns NULL, but we
8479 need to keep rest of compiler happy by returning meaningful value. */
8484 }
8486 static rtx
8488 const_tree valtype)
8489 {
8493 {
8495 {
8514 }
8515 }
8517 }
8519 static rtx
8522 {
8537 else
8539 }
8541 static rtx
8543 {
8549 }
8551 /* Return an RTX representing a place where a function returns
8552 or recieves pointer bounds or NULL if no bounds are returned.
8554 VALTYPE is a data type of a value returned by the function.
8556 FN_DECL_OR_TYPE is a tree node representing FUNCTION_DECL
8557 or FUNCTION_TYPE of the function.
8559 If OUTGOING is false, return a place in which the caller will
8560 see the return value. Otherwise, return a place where a
8561 function returns a value. */
8563 static rtx
8565 const_tree fntype_or_decl ATTRIBUTE_UNUSED,
8567 {
8573 {
8574 bitmap slots;
8576 bitmap_iterator bi;
8584 {
8589 }
8595 }
8596 else
8600 }
8602 /* Pointer function arguments and return values are promoted to
8603 word_mode. */
8605 static machine_mode
8609 {
8611 {
8614 }
8616 for_return);
8617 }
8619 /* Return true if a structure, union or array with MODE containing FIELD
8620 should be accessed using BLKmode. */
8622 static bool
8624 {
8625 /* Union with XFmode must be in BLKmode. */
8629 }
8631 rtx
8633 {
8635 }
8637 /* Return true iff type is returned in memory. */
8639 static bool
8641 {
8642 #ifdef SUBTARGET_RETURN_IN_MEMORY
8644 #else
8646 HOST_WIDE_INT size;
8652 {
8654 {
8657 /* __m128 is returned in xmm0. */
8666 /* Otherwise, the size must be exactly in [1248]. */
8668 }
8669 else
8670 {
8675 }
8676 }
8677 else
8678 {
8681 /* Intel MCU psABI returns scalars and aggregates no larger than 8
8682 bytes in registers. */
8693 {
8694 /* User-created vectors small enough to fit in EAX. */
8698 /* Unless ABI prescibes otherwise,
8699 MMX/3dNow values are returned in MM0 if available. */
8704 /* SSE values are returned in XMM0 if available. */
8708 /* AVX values are returned in YMM0 if available. */
8712 /* AVX512F values are returned in ZMM0 if available. */
8715 }
8723 /* OImode shouldn't be used directly. */
8727 }
8728 #endif
8729 }
8731 \f
8732 /* Create the va_list data type. */
8734 static tree
8736 {
8745 unsigned_type_node);
8748 unsigned_type_node);
8751 ptr_type_node);
8754 ptr_type_node);
8773 /* The correct type is an array type of one element. */
8775 }
8777 /* Setup the builtin va_list data type and for 64-bit the additional
8778 calling convention specific va_list data types. */
8780 static tree
8782 {
8784 {
8785 /* Initialize ABI specific va_list builtin types. */
8791 /* For MS_ABI we use plain pointer to argument area. */
8796 }
8797 else
8798 {
8799 /* For i386 we use plain pointer to argument area. */
8801 }
8802 }
8804 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8806 static void
8808 {
8810 alias_set_type set;
8813 /* GPR size of varargs save area. */
8816 else
8819 /* FPR size of varargs save area. We don't need it if we don't pass
8820 anything in SSE registers. */
8823 else
8837 {
8845 }
8848 {
8849 machine_mode smode;
8851 rtx test;
8853 /* Now emit code to save SSE registers. The AX parameter contains number
8854 of SSE parameter registers used to call this function, though all we
8855 actually check here is the zero/non-zero status. */
8860 label));
8862 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8863 we used movdqa (i.e. TImode) instead? Perhaps even better would
8864 be if we could determine the real mode of the data, via a hook
8865 into pass_stdarg. Ignore all that for now. */
8875 {
8884 }
8887 }
8888 }
8890 static void
8892 {
8896 /* Reset to zero, as there might be a sysv vaarg used
8897 before. */
8902 {
8913 }
8914 }
8916 static void
8919 {
8921 CUMULATIVE_ARGS next_cum;
8922 tree fntype;
8924 /* This argument doesn't appear to be used anymore. Which is good,
8925 because the old code here didn't suppress rtl generation. */
8933 /* For varargs, we do not want to skip the dummy va_dcl argument.
8934 For stdargs, we do want to skip the last named argument. */
8942 else
8944 }
8946 static void
8949 tree type,
8952 {
8954 CUMULATIVE_ARGS next_cum;
8955 tree fntype;
8956 rtx save_area;
8961 /* Do nothing if we use plain pointer to argument area. */
8967 /* For varargs, we do not want to skip the dummy va_dcl argument.
8968 For stdargs, we do want to skip the last named argument. */
8982 {
8986 rtx bounds;
8990 else
8991 {
8992 rtx ldx_addr =
8999 }
9005 bnd_reg++;
9006 }
9007 }
9010 /* Checks if TYPE is of kind va_list char *. */
9012 static bool
9014 {
9015 tree canonic;
9017 /* For 32-bit it is always true. */
9023 }
9025 /* Implement va_start. */
9027 static void
9029 {
9033 tree type;
9034 rtx ovf_rtx;
9038 {
9041 /* When we are splitting the stack, we can't refer to the stack
9042 arguments using internal_arg_pointer, because they may be on
9043 the old stack. The split stack prologue will arrange to
9044 leave a pointer to the old stack arguments in a scratch
9045 register, which we here copy to a pseudo-register. The split
9046 stack prologue can't set the pseudo-register directly because
9047 it (the prologue) runs before any registers have been saved. */
9051 {
9052 rtx reg;
9066 }
9067 }
9069 /* Only 64bit target needs something special. */
9071 {
9074 else
9075 {
9085 /* Store zero bounds for va_list. */
9089 next));
9091 }
9093 }
9102 /* The following should be folded into the MEM_REF offset. */
9112 /* Count number of gp and fp argument registers used. */
9118 {
9124 }
9127 {
9133 }
9135 /* Find the overflow area. */
9139 else
9145 /* Store zero bounds for overflow area pointer. */
9154 {
9155 /* Find the register save area.
9156 Prologue of the function save it right above stack frame. */
9162 /* Store zero bounds for save area pointer. */
9169 }
9170 }
9172 /* Implement va_arg. */
9174 static tree
9177 {
9184 rtx container;
9186 tree ptrtype;
9187 machine_mode nat_mode;
9190 /* Only 64bit target needs something special. */
9214 {
9227 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
9229 {
9232 }
9240 }
9242 /* Pull the value out of the saved registers. */
9247 {
9261 /* In case we are passing structure, verify that it is consecutive block
9262 on the register save area. If not we need to do moves. */
9264 {
9265 /* Verify that all registers are strictly consecutive */
9267 {
9271 {
9276 }
9277 }
9278 else
9279 {
9283 {
9288 }
9289 }
9290 }
9292 {
9295 }
9296 else
9297 {
9300 }
9302 /* First ensure that we fit completely in registers. */
9304 {
9311 }
9313 {
9321 }
9323 /* Compute index to start of area used for integer regs. */
9325 {
9326 /* int_addr = gpr + sav; */
9329 }
9331 {
9332 /* sse_addr = fpr + sav; */
9335 }
9337 {
9341 /* addr = &temp; */
9346 {
9350 tree piece_type;
9351 tree addr_type;
9352 tree daddr_type;
9361 {
9366 }
9370 else
9377 {
9380 }
9381 else
9382 {
9385 }
9392 {
9397 }
9398 else
9399 {
9400 tree copy
9405 }
9407 }
9408 }
9411 {
9415 }
9418 {
9422 }
9427 }
9429 /* ... otherwise out of the overflow area. */
9431 /* When we align parameter on stack for caller, if the parameter
9432 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
9433 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
9434 here with caller. */
9439 /* Care for on-stack alignment if needed. */
9442 else
9443 {
9448 }
9465 }
9466 \f
9467 /* Return true if OPNUM's MEM should be matched
9468 in movabs* patterns. */
9470 bool
9472 {
9484 }
9485 \f
9486 /* Initialize the table of extra 80387 mathematical constants. */
9488 static void
9490 {
9492 {
9498 };
9502 {
9504 /* Ensure each constant is rounded to XFmode precision. */
9507 }
9510 }
9512 /* Return non-zero if the constant is something that
9513 can be loaded with a special instruction. */
9515 int
9517 {
9520 REAL_VALUE_TYPE r;
9532 /* For XFmode constants, try to find a special 80387 instruction when
9533 optimizing for size or on those CPUs that benefit from them. */
9536 {
9545 }
9547 /* Load of the constant -0.0 or -1.0 will be split as
9548 fldz;fchs or fld1;fchs sequence. */
9555 }
9557 /* Return the opcode of the special instruction to be used to load
9558 the constant X. */
9562 {
9564 {
9584 }
9585 }
9587 /* Return the CONST_DOUBLE representing the 80387 constant that is
9588 loaded by the specified special instruction. The argument IDX
9589 matches the return value from standard_80387_constant_p. */
9591 rtx
9593 {
9600 {
9611 }
9614 XFmode);
9615 }
9617 /* Return 1 if X is all 0s and 2 if x is all 1s
9618 in supported SSE/AVX vector mode. */
9620 int
9622 {
9623 machine_mode mode;
9634 {
9655 }
9658 }
9660 /* Return the opcode of the special instruction to be used to load
9661 the constant X. */
9665 {
9667 {
9670 {
9697 }
9707 else
9712 }
9714 }
9716 /* Returns true if OP contains a symbol reference */
9718 bool
9720 {
9729 {
9731 {
9737 }
9741 }
9744 }
9746 /* Return true if it is appropriate to emit `ret' instructions in the
9747 body of a function. Do this only if the epilogue is simple, needing a
9748 couple of insns. Prior to reloading, we can't tell how many registers
9749 must be saved, so return false then. Return false if there is no frame
9750 marker to de-allocate. */
9752 bool
9754 {
9760 /* Don't allow more than 32k pop, since that's all we can do
9761 with one instruction. */
9768 }
9769 \f
9770 /* Value should be nonzero if functions must have frame pointers.
9771 Zero means the frame pointer need not be set up (and parms may
9772 be accessed via the stack pointer) in functions that seem suitable. */
9774 static bool
9776 {
9777 /* If we accessed previous frames, then the generated code expects
9778 to be able to access the saved ebp value in our frame. */
9782 /* Several x86 os'es need a frame pointer for other reasons,
9783 usually pertaining to setjmp. */
9787 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9791 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9792 allocation is 4GB. */
9796 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9797 turns off the frame pointer by default. Turn it back on now if
9798 we've not got a leaf function. */
9808 }
9810 /* Record that the current function accesses previous call frames. */
9812 void
9814 {
9816 }
9817 \f
9818 #ifndef USE_HIDDEN_LINKONCE
9819 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9820 # define USE_HIDDEN_LINKONCE 1
9821 # else
9822 # define USE_HIDDEN_LINKONCE 0
9823 # endif
9824 #endif
9828 /* Fills in the label name that should be used for a pc thunk for
9829 the given register. */
9831 static void
9833 {
9838 else
9840 }
9843 /* This function generates code for -fpic that loads %ebx with
9844 the return address of the caller and then returns. */
9846 static void
9848 {
9853 {
9855 tree decl;
9871 #if TARGET_MACHO
9873 {
9882 }
9883 else
9884 #endif
9886 {
9897 }
9898 else
9899 {
9902 }
9908 /* Make sure unwind info is emitted for the thunk if needed. */
9911 /* Pad stack IP move with 4 instructions (two NOPs count
9912 as one instruction). */
9914 {
9919 }
9930 }
9934 }
9936 /* Emit code for the SET_GOT patterns. */
9940 {
9946 {
9947 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9952 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9953 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9954 an unadorned address. */
9959 }
9964 {
9966 /* We don't need a pic base, we're not producing pic. */
9973 }
9974 else
9975 {
9984 #if TARGET_MACHO
9985 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9986 This is what will be referenced by the Mach-O PIC subsystem. */
9990 /* When we are restoring the pic base at the site of a nonlocal label,
9991 and we decided to emit the pic base above, we will still output a
9992 local label used for calculating the correction offset (even though
9993 the offset will be 0 in that case). */
9997 #endif
9998 }
10004 }
10006 /* Generate an "push" pattern for input ARG. */
10008 static rtx
10010 {
10022 stack_pointer_rtx)),
10023 arg);
10024 }
10026 /* Generate an "pop" pattern for input ARG. */
10028 static rtx
10030 {
10037 stack_pointer_rtx)));
10038 }
10040 /* Return >= 0 if there is an unused call-clobbered register available
10041 for the entire function. */
10043 static unsigned int
10045 {
10052 {
10054 /* Can't use the same register for both PIC and DRAP. */
10057 else
10062 }
10065 }
10067 /* Return TRUE if we need to save REGNO. */
10069 static bool
10071 {
10074 {
10076 {
10077 /* REAL_PIC_OFFSET_TABLE_REGNUM used by call to
10078 _mcount in prologue. */
10081 }
10088 }
10091 {
10094 {
10100 }
10101 }
10112 }
10114 /* Return number of saved general prupose registers. */
10116 static int
10118 {
10124 nregs ++;
10126 }
10128 /* Return number of saved SSE registrers. */
10130 static int
10132 {
10140 nregs ++;
10142 }
10144 /* Given FROM and TO register numbers, say whether this elimination is
10145 allowed. If stack alignment is needed, we can only replace argument
10146 pointer with hard frame pointer, or replace frame pointer with stack
10147 pointer. Otherwise, frame pointer elimination is automatically
10148 handled and all other eliminations are valid. */
10150 static bool
10152 {
10158 else
10160 }
10162 /* Return the offset between two registers, one to be eliminated, and the other
10163 its replacement, at the start of a routine. */
10165 HOST_WIDE_INT
10167 {
10176 else
10177 {
10185 }
10186 }
10188 /* In a dynamically-aligned function, we can't know the offset from
10189 stack pointer to frame pointer, so we must ensure that setjmp
10190 eliminates fp against the hard fp (%ebp) rather than trying to
10191 index from %esp up to the top of the frame across a gap that is
10192 of unknown (at compile-time) size. */
10193 static rtx
10195 {
10197 }
10199 /* When using -fsplit-stack, the allocation routines set a field in
10200 the TCB to the bottom of the stack plus this much space, measured
10201 in bytes. */
10203 #define SPLIT_STACK_AVAILABLE 256
10205 /* Fill structure ix86_frame about frame of currently computed function. */
10207 static void
10209 {
10211 HOST_WIDE_INT offset;
10214 HOST_WIDE_INT to_allocate;
10219 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
10220 function prologues and leaf. */
10224 {
10227 }
10228 /* preferred_stack_boundary is never updated for call
10229 expanded from tls descriptor. Update it here. We don't update it in
10230 expand stage because according to the comments before
10231 ix86_current_function_calls_tls_descriptor, tls calls may be optimized
10232 away. */
10235 {
10239 }
10248 /* For SEH we have to limit the amount of code movement into the prologue.
10249 At present we do this via a BLOCKAGE, at which point there's very little
10250 scheduling that can be done, which means that there's very little point
10251 in doing anything except PUSHs. */
10255 /* During reload iteration the amount of registers saved can change.
10256 Recompute the value as needed. Do not recompute when amount of registers
10257 didn't change as reload does multiple calls to the function and does not
10258 expect the decision to change within single iteration. */
10261 {
10267 /* The fast prologue uses move instead of push to save registers. This
10268 is significantly longer, but also executes faster as modern hardware
10269 can execute the moves in parallel, but can't do that for push/pop.
10271 Be careful about choosing what prologue to emit: When function takes
10272 many instructions to execute we may use slow version as well as in
10273 case function is known to be outside hot spot (this is known with
10274 feedback only). Weight the size of function by number of registers
10275 to save as it is cheap to use one or two push instructions but very
10276 slow to use many of them. */
10280 || (flag_branch_probabilities
10283 else
10286 }
10288 frame->save_regs_using_mov
10290 /* If static stack checking is enabled and done with probes,
10291 the registers need to be saved before allocating the frame. */
10294 /* Skip return address. */
10297 /* Skip pushed static chain. */
10301 /* Skip saved base pointer. */
10306 /* The traditional frame pointer location is at the top of the frame. */
10309 /* Register save area */
10313 /* On SEH target, registers are pushed just before the frame pointer
10314 location. */
10318 /* Align and set SSE register save area. */
10320 {
10321 /* The only ABI that has saved SSE registers (Win64) also has a
10322 16-byte aligned default stack, and thus we don't need to be
10323 within the re-aligned local stack frame to save them. */
10327 }
10330 /* The re-aligned stack starts here. Values before this point are not
10331 directly comparable with values below this point. In order to make
10332 sure that no value happens to be the same before and after, force
10333 the alignment computation below to add a non-zero value. */
10337 /* Va-arg area */
10341 /* Align start of frame for local function. */
10350 /* Frame pointer points here. */
10355 /* Add outgoing arguments area. Can be skipped if we eliminated
10356 all the function calls as dead code.
10357 Skipping is however impossible when function calls alloca. Alloca
10358 expander assumes that last crtl->outgoing_args_size
10359 of stack frame are unused. */
10363 {
10366 }
10367 else
10370 /* Align stack boundary. Only needed if we're calling another function
10371 or using alloca. */
10376 /* We've reached end of stack frame. */
10379 /* Size prologue needs to allocate. */
10390 {
10396 }
10397 else
10401 /* The SEH frame pointer location is near the bottom of the frame.
10402 This is enforced by the fact that the difference between the
10403 stack pointer and the frame pointer is limited to 240 bytes in
10404 the unwind data structure. */
10406 {
10407 HOST_WIDE_INT diff;
10409 /* If we can leave the frame pointer where it is, do so. Also, returns
10410 the establisher frame for __builtin_frame_address (0). */
10415 {
10416 /* Ideally we'd determine what portion of the local stack frame
10417 (within the constraint of the lowest 240) is most heavily used.
10418 But without that complication, simply bias the frame pointer
10419 by 128 bytes so as to maximize the amount of the local stack
10420 frame that is addressable with 8-bit offsets. */
10422 }
10423 }
10424 }
10426 /* This is semi-inlined memory_address_length, but simplified
10427 since we know that we're always dealing with reg+offset, and
10428 to avoid having to create and discard all that rtl. */
10432 {
10436 {
10437 /* EBP and R13 cannot be encoded without an offset. */
10439 }
10443 /* ESP and R12 must be encoded with a SIB byte. */
10445 len++;
10448 }
10450 /* Return an RTX that points to CFA_OFFSET within the stack frame.
10451 The valid base registers are taken from CFUN->MACHINE->FS. */
10453 static rtx
10455 {
10461 {
10462 /* Choose the base register most likely to allow the most scheduling
10463 opportunities. Generally FP is valid throughout the function,
10464 while DRAP must be reloaded within the epilogue. But choose either
10465 over the SP due to increased encoding size. */
10468 {
10471 }
10473 {
10476 }
10478 {
10481 }
10482 }
10483 else
10484 {
10485 HOST_WIDE_INT toffset;
10488 /* Choose the base register with the smallest address encoding.
10489 With a tie, choose FP > DRAP > SP. */
10491 {
10495 }
10497 {
10501 {
10505 }
10506 }
10508 {
10512 {
10516 }
10517 }
10518 }
10522 }
10524 /* Emit code to save registers in the prologue. */
10526 static void
10528 {
10534 {
10537 }
10538 }
10540 /* Emit a single register save at CFA - CFA_OFFSET. */
10542 static void
10544 HOST_WIDE_INT cfa_offset)
10545 {
10553 /* For SSE saves, we need to indicate the 128-bit alignment. */
10564 /* When saving registers into a re-aligned local stack frame, avoid
10565 any tricky guessing by dwarf2out. */
10567 {
10571 {
10572 /* A bit of a hack. We force the DRAP register to be saved in
10573 the re-aligned stack frame, which provides us with a copy
10574 of the CFA that will last past the prologue. Install it. */
10580 }
10581 else
10582 {
10583 /* The frame pointer is a stable reference within the
10584 aligned frame. Use it. */
10590 }
10591 }
10593 /* The memory may not be relative to the current CFA register,
10594 which means that we may need to generate a new pattern for
10595 use by the unwind info. */
10597 {
10602 }
10603 }
10605 /* Emit code to save registers using MOV insns.
10606 First register is stored at CFA - CFA_OFFSET. */
10607 static void
10609 {
10614 {
10617 }
10618 }
10620 /* Emit code to save SSE registers using MOV insns.
10621 First register is stored at CFA - CFA_OFFSET. */
10622 static void
10624 {
10629 {
10632 }
10633 }
10637 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
10638 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
10639 Don't add the note if the previously saved value will be left untouched
10640 within stack red-zone till return, as unwinders can find the same value
10641 in the register and on the stack. */
10643 static void
10645 {
10651 {
10654 }
10655 else
10656 queued_cfa_restores
10658 }
10660 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
10662 static void
10664 {
10665 rtx last;
10669 ;
10674 }
10676 /* Expand prologue or epilogue stack adjustment.
10677 The pattern exist to put a dependency on all ebp-based memory accesses.
10678 STYLE should be negative if instructions should be marked as frame related,
10679 zero if %r11 register is live and cannot be freely used and positive
10680 otherwise. */
10682 static void
10685 {
10687 rtx insn;
10694 else
10695 {
10696 rtx tmp;
10697 /* r11 is used by indirect sibcall return as well, set before the
10698 epilogue and used after the epilogue. */
10701 else
10702 {
10706 }
10712 }
10719 {
10720 rtx r;
10730 }
10732 {
10735 {
10739 }
10740 }
10743 {
10748 {
10751 }
10753 {
10756 }
10757 else
10758 {
10759 /* Else there are two possibilities: SP itself, which we set
10760 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10761 taken care of this by hand along the eh_return path. */
10764 }
10768 }
10769 }
10771 /* Find an available register to be used as dynamic realign argument
10772 pointer regsiter. Such a register will be written in prologue and
10773 used in begin of body, so it must not be
10774 1. parameter passing register.
10775 2. GOT pointer.
10776 We reuse static-chain register if it is available. Otherwise, we
10777 use DI for i386 and R13 for x86-64. We chose R13 since it has
10778 shorter encoding.
10780 Return: the regno of chosen register. */
10782 static unsigned int
10784 {
10788 {
10789 /* Use R13 for nested function or function need static chain.
10790 Since function with tail call may use any caller-saved
10791 registers in epilogue, DRAP must not use caller-saved
10792 register in such case. */
10797 }
10798 else
10799 {
10800 /* Use DI for nested function or function need static chain.
10801 Since function with tail call may use any caller-saved
10802 registers in epilogue, DRAP must not use caller-saved
10803 register in such case. */
10807 /* Reuse static chain register if it isn't used for parameter
10808 passing. */
10810 {
10814 }
10816 }
10817 }
10819 /* Return minimum incoming stack alignment. */
10821 static unsigned int
10823 {
10826 /* Prefer the one specified at command line. */
10829 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10830 if -mstackrealign is used, it isn't used for sibcall check and
10831 estimated stack alignment is 128bit. */
10833 && !TARGET_64BIT
10834 && ix86_force_align_arg_pointer
10837 else
10840 /* Incoming stack alignment can be changed on individual functions
10841 via force_align_arg_pointer attribute. We use the smallest
10842 incoming stack boundary. */
10848 /* The incoming stack frame has to be aligned at least at
10849 parm_stack_boundary. */
10853 /* Stack at entrance of main is aligned by runtime. We use the
10854 smallest incoming stack boundary. */
10862 }
10864 /* Update incoming stack boundary and estimated stack alignment. */
10866 static void
10868 {
10869 ix86_incoming_stack_boundary
10872 /* x86_64 vararg needs 16byte stack alignment for register save
10873 area. */
10878 }
10880 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10881 needed or an rtx for DRAP otherwise. */
10883 static rtx
10885 {
10890 {
10891 /* Assign DRAP to vDRAP and returns vDRAP */
10893 rtx drap_vreg;
10894 rtx arg_ptr;
10907 {
10910 }
10912 }
10913 else
10915 }
10917 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10919 static rtx
10921 {
10923 }
10926 rtx reg;
10928 };
10930 /* Return a short-lived scratch register for use on function entry.
10931 In 32-bit mode, it is valid only after the registers are saved
10932 in the prologue. This register must be released by means of
10933 release_scratch_register_on_entry once it is dead. */
10935 static void
10937 {
10943 {
10944 /* We always use R11 in 64-bit mode. */
10946 }
10947 else
10948 {
10950 bool fastcall_p
10952 bool thiscall_p
10956 int drap_regno
10959 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10960 for the static chain register. */
10964 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10965 for the static chain register. */
10970 /* ecx is the static chain register. */
10972 && !static_chain_p
10977 /* esi is the static chain register. */
10983 else
10984 {
10987 }
10988 }
10992 {
10995 }
10996 }
10998 /* Release a scratch register obtained from the preceding function. */
11000 static void
11002 {
11004 {
11008 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
11014 }
11015 }
11017 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
11019 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
11021 static void
11023 {
11024 /* We skip the probe for the first interval + a small dope of 4 words and
11025 probe that many bytes past the specified size to maintain a protection
11026 area at the botton of the stack. */
11030 /* See if we have a constant small number of probes to generate. If so,
11031 that's the easy case. The run-time loop is made up of 11 insns in the
11032 generic case while the compile-time loop is made up of 3+2*(n-1) insns
11033 for n # of intervals. */
11035 {
11039 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
11040 values of N from 1 until it exceeds SIZE. If only one probe is
11041 needed, this will not generate any code. Then adjust and probe
11042 to PROBE_INTERVAL + SIZE. */
11044 {
11046 {
11049 }
11050 else
11057 }
11061 else
11069 /* Adjust back to account for the additional first interval. */
11073 }
11075 /* Otherwise, do the same as above, but in a loop. Note that we must be
11076 extra careful with variables wrapping around because we might be at
11077 the very top (or the very bottom) of the address space and we have
11078 to be able to handle this case properly; in particular, we use an
11079 equality test for the loop condition. */
11080 else
11081 {
11082 HOST_WIDE_INT rounded_size;
11088 /* Step 1: round SIZE to the previous multiple of the interval. */
11093 /* Step 2: compute initial and final value of the loop counter. */
11095 /* SP = SP_0 + PROBE_INTERVAL. */
11100 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
11104 stack_pointer_rtx)));
11107 /* Step 3: the loop
11109 while (SP != LAST_ADDR)
11110 {
11111 SP = SP + PROBE_INTERVAL
11112 probe at SP
11113 }
11115 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
11116 values of N from 1 until it is equal to ROUNDED_SIZE. */
11121 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
11122 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
11125 {
11130 }
11132 /* Adjust back to account for the additional first interval. */
11138 }
11142 /* Even if the stack pointer isn't the CFA register, we need to correctly
11143 describe the adjustments made to it, in particular differentiate the
11144 frame-related ones from the frame-unrelated ones. */
11146 {
11159 }
11161 /* Make sure nothing is scheduled before we are done. */
11163 }
11165 /* Adjust the stack pointer up to REG while probing it. */
11169 {
11179 /* Jump to END_LAB if SP == LAST_ADDR. */
11187 /* SP = SP + PROBE_INTERVAL. */
11191 /* Probe at SP. */
11202 }
11204 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
11205 inclusive. These are offsets from the current stack pointer. */
11207 static void
11209 {
11210 /* See if we have a constant small number of probes to generate. If so,
11211 that's the easy case. The run-time loop is made up of 7 insns in the
11212 generic case while the compile-time loop is made up of n insns for n #
11213 of intervals. */
11215 {
11216 HOST_WIDE_INT i;
11218 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
11219 it exceeds SIZE. If only one probe is needed, this will not
11220 generate any code. Then probe at FIRST + SIZE. */
11227 }
11229 /* Otherwise, do the same as above, but in a loop. Note that we must be
11230 extra careful with variables wrapping around because we might be at
11231 the very top (or the very bottom) of the address space and we have
11232 to be able to handle this case properly; in particular, we use an
11233 equality test for the loop condition. */
11234 else
11235 {
11242 /* Step 1: round SIZE to the previous multiple of the interval. */
11247 /* Step 2: compute initial and final value of the loop counter. */
11249 /* TEST_OFFSET = FIRST. */
11252 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
11256 /* Step 3: the loop
11258 while (TEST_ADDR != LAST_ADDR)
11259 {
11260 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11261 probe at TEST_ADDR
11262 }
11264 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11265 until it is equal to ROUNDED_SIZE. */
11270 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11271 that SIZE is equal to ROUNDED_SIZE. */
11276 stack_pointer_rtx,
11281 }
11283 /* Make sure nothing is scheduled before we are done. */
11285 }
11287 /* Probe a range of stack addresses from REG to END, inclusive. These are
11288 offsets from the current stack pointer. */
11292 {
11302 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11310 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11314 /* Probe at TEST_ADDR. */
11327 }
11329 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
11330 to be generated in correct form. */
11331 static void
11333 {
11334 /* Check if stack realign is really needed after reload, and
11335 stores result in cfun */
11336 unsigned int incoming_stack_boundary
11345 {
11346 /* After stack_realign_needed is finalized, we can't no longer
11347 change it. */
11350 }
11352 /* If the only reason for frame_pointer_needed is that we conservatively
11353 assumed stack realignment might be needed, but in the end nothing that
11354 needed the stack alignment had been spilled, clear frame_pointer_needed
11355 and say we don't need stack realignment. */
11357 && frame_pointer_needed
11359 && flag_omit_frame_pointer
11361 && !ix86_current_function_calls_tls_descriptor
11370 {
11372 basic_block bb;
11379 HARD_FRAME_POINTER_REGNUM);
11381 {
11386 set_up_by_prologue))
11387 {
11391 }
11392 }
11394 /* If drap has been set, but it actually isn't live at the start
11395 of the function, there is no reason to set it up. */
11397 {
11400 {
11403 }
11404 }
11405 else
11420 }
11424 }
11426 /* Delete SET_GOT right after entry block if it is allocated to reg. */
11428 static void
11430 {
11436 {
11439 {
11445 }
11446 }
11447 }
11449 /* Expand the prologue into a bunch of separate insns. */
11451 void
11453 {
11457 HOST_WIDE_INT allocate;
11464 /* DRAP should not coexist with stack_realign_fp */
11469 /* Initialize CFA state for before the prologue. */
11473 /* Track SP offset to the CFA. We continue tracking this after we've
11474 swapped the CFA register away from SP. In the case of re-alignment
11475 this is fudged; we're interested to offsets within the local frame. */
11482 {
11483 /* We should have already generated an error for any use of
11484 ms_hook on a nested function. */
11487 /* Check if profiling is active and we shall use profiling before
11488 prologue variant. If so sorry. */
11493 /* In ix86_asm_output_function_label we emitted:
11494 8b ff movl.s %edi,%edi
11495 55 push %ebp
11496 8b ec movl.s %esp,%ebp
11498 This matches the hookable function prologue in Win32 API
11499 functions in Microsoft Windows XP Service Pack 2 and newer.
11500 Wine uses this to enable Windows apps to hook the Win32 API
11501 functions provided by Wine.
11503 What that means is that we've already set up the frame pointer. */
11507 {
11510 /* We've decided to use the frame pointer already set up.
11511 Describe this to the unwinder by pretending that both
11512 push and mov insns happen right here.
11514 Putting the unwind info here at the end of the ms_hook
11515 is done so that we can make absolutely certain we get
11516 the required byte sequence at the start of the function,
11517 rather than relying on an assembler that can produce
11518 the exact encoding required.
11520 However it does mean (in the unpatched case) that we have
11521 a 1 insn window where the asynchronous unwind info is
11522 incorrect. However, if we placed the unwind info at
11523 its correct location we would have incorrect unwind info
11524 in the patched case. Which is probably all moot since
11525 I don't expect Wine generates dwarf2 unwind info for the
11526 system libraries that use this feature. */
11532 stack_pointer_rtx);
11540 /* Note that gen_push incremented m->fs.cfa_offset, even
11541 though we didn't emit the push insn here. */
11545 }
11546 else
11547 {
11548 /* The frame pointer is not needed so pop %ebp again.
11549 This leaves us with a pristine state. */
11551 }
11552 }
11554 /* The first insn of a function that accepts its static chain on the
11555 stack is to push the register that would be filled in by a direct
11556 call. This insn will be skipped by the trampoline. */
11558 {
11563 /* We don't want to interpret this push insn as a register save,
11564 only as a stack adjustment. The real copy of the register as
11565 a save will be done later, if needed. */
11570 }
11572 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
11573 of DRAP is needed and stack realignment is really needed after reload */
11575 {
11578 /* Only need to push parameter pointer reg if it is caller saved. */
11580 {
11581 /* Push arg pointer reg */
11584 }
11586 /* Grab the argument pointer. */
11593 /* Align the stack. */
11595 stack_pointer_rtx,
11599 /* Replicate the return address on the stack so that return
11600 address can be reached via (argp - 1) slot. This is needed
11601 to implement macro RETURN_ADDR_RTX and intrinsic function
11602 expand_builtin_return_addr etc. */
11608 /* For the purposes of frame and register save area addressing,
11609 we've started over with a new frame. */
11614 {
11615 /* Replicate static chain on the stack so that static chain
11616 can be reached via (argp - 2) slot. This is needed for
11617 nested function with stack realignment. */
11620 }
11621 }
11627 {
11628 /* Note: AT&T enter does NOT have reversed args. Enter is probably
11629 slower on all targets. Also sdb doesn't like it. */
11633 /* Push registers now, before setting the frame pointer
11634 on SEH target. */
11636 && TARGET_SEH
11638 {
11642 }
11645 {
11653 }
11654 }
11657 {
11658 /* If saving registers via PUSH, do so now. */
11660 {
11664 }
11666 /* When using red zone we may start register saving before allocating
11667 the stack frame saving one cycle of the prologue. However, avoid
11668 doing this if we have to probe the stack; at least on x86_64 the
11669 stack probe can turn into a call that clobbers a red zone location. */
11671 && (! TARGET_STACK_PROBE
11673 {
11676 }
11677 }
11680 {
11684 /* The computation of the size of the re-aligned stack frame means
11685 that we must allocate the size of the register save area before
11686 performing the actual alignment. Otherwise we cannot guarantee
11687 that there's enough storage above the realignment point. */
11694 /* Align the stack. */
11696 stack_pointer_rtx,
11699 /* For the purposes of register save area addressing, the stack
11700 pointer is no longer valid. As for the value of sp_offset,
11701 see ix86_compute_frame_layout, which we need to match in order
11702 to pass verification of stack_pointer_offset at the end. */
11705 }
11710 {
11711 /* We start to count from ARG_POINTER. */
11714 /* If it was realigned, take into account the fake frame. */
11716 {
11723 /* This over-estimates by 1 minimal-stack-alignment-unit but
11724 mitigates that by counting in the new return address slot. */
11725 current_function_dynamic_stack_size
11727 }
11730 }
11732 /* On SEH target with very large frame size, allocate an area to save
11733 SSE registers (as the very large allocation won't be described). */
11737 {
11738 HOST_WIDE_INT sse_size =
11743 /* No need to do stack checking as the area will be immediately
11744 written. */
11751 }
11753 /* The stack has already been decremented by the instruction calling us
11754 so probe if the size is non-negative to preserve the protection area. */
11756 {
11757 /* We expect the registers to be saved when probes are used. */
11761 {
11764 {
11767 }
11768 }
11769 else
11770 {
11777 {
11779 {
11782 }
11783 else
11785 }
11786 else
11787 {
11789 {
11793 }
11794 else
11796 }
11797 }
11798 }
11801 ;
11804 {
11808 }
11809 else
11810 {
11822 {
11825 /* Note that SEH directives need to continue tracking the stack
11826 pointer even after the frame pointer has been set up. */
11828 {
11836 }
11837 }
11840 {
11845 {
11853 }
11854 }
11859 /* Use the fact that AX still contains ALLOCATE. */
11861 ? gen_pro_epilogue_adjust_stack_di_sub
11868 {
11876 }
11879 /* Use stack_pointer_rtx for relative addressing so that code
11880 works for realigned stack, too. */
11882 {
11889 }
11891 {
11896 }
11897 }
11900 /* If we havn't already set up the frame pointer, do so now. */
11902 {
11914 }
11921 /* For the mcount profiling on 32 bit PIC mode we need to emit SET_GOT
11922 in PROLOGUE. */
11924 {
11930 /* Deleting already emmitted SET_GOT if exist and allocated to
11931 REAL_PIC_OFFSET_TABLE_REGNUM. */
11933 }
11936 {
11937 /* vDRAP is setup but after reload it turns out stack realign
11938 isn't necessary, here we will emit prologue to setup DRAP
11939 without stack realign adjustment */
11942 }
11944 /* Prevent instructions from being scheduled into register save push
11945 sequence when access to the redzone area is done through frame pointer.
11946 The offset between the frame pointer and the stack pointer is calculated
11947 relative to the value of the stack pointer at the end of the function
11948 prologue, and moving instructions that access redzone area via frame
11949 pointer inside push sequence violates this assumption. */
11953 /* Emit cld instruction if stringops are used in the function. */
11957 /* SEH requires that the prologue end within 256 bytes of the start of
11958 the function. Prevent instruction schedules that would extend that.
11959 Further, prevent alloca modifications to the stack pointer from being
11960 combined with prologue modifications. */
11963 }
11965 /* Emit code to restore REG using a POP insn. */
11967 static void
11969 {
11978 {
11979 /* Previously we'd represented the CFA as an expression
11980 like *(%ebp - 8). We've just popped that value from
11981 the stack, which means we need to reset the CFA to
11982 the drap register. This will remain until we restore
11983 the stack pointer. */
11987 /* This means that the DRAP register is valid for addressing too. */
11990 }
11993 {
12000 }
12002 /* When the frame pointer is the CFA, and we pop it, we are
12003 swapping back to the stack pointer as the CFA. This happens
12004 for stack frames that don't allocate other data, so we assume
12005 the stack pointer is now pointing at the return address, i.e.
12006 the function entry state, which makes the offset be 1 word. */
12008 {
12011 {
12019 }
12020 }
12021 }
12023 /* Emit code to restore saved registers using POP insns. */
12025 static void
12027 {
12033 }
12035 /* Emit code and notes for the LEAVE instruction. */
12037 static void
12039 {
12051 {
12059 }
12062 }
12064 /* Emit code to restore saved registers using MOV insns.
12065 First register is restored from CFA - CFA_OFFSET. */
12066 static void
12069 {
12075 {
12077 rtx mem;
12085 {
12086 /* Previously we'd represented the CFA as an expression
12087 like *(%ebp - 8). We've just popped that value from
12088 the stack, which means we need to reset the CFA to
12089 the drap register. This will remain until we restore
12090 the stack pointer. */
12094 /* This means that the DRAP register is valid for addressing. */
12096 }
12097 else
12101 }
12102 }
12104 /* Emit code to restore saved registers using MOV insns.
12105 First register is restored from CFA - CFA_OFFSET. */
12106 static void
12109 {
12114 {
12116 rtx mem;
12126 }
12127 }
12129 /* Restore function stack, frame, and registers. */
12131 void
12133 {
12149 /* The FP must be valid if the frame pointer is present. */
12154 /* We must have *some* valid pointer to the stack frame. */
12157 /* The DRAP is never valid at this point. */
12160 /* See the comment about red zone and frame
12161 pointer usage in ix86_expand_prologue. */
12168 /* Determine the CFA offset of the end of the red-zone. */
12171 {
12172 /* The red-zone begins below the return address. */
12175 /* When the register save area is in the aligned portion of
12176 the stack, determine the maximum runtime displacement that
12177 matches up with the aligned frame. */
12181 }
12183 /* Special care must be taken for the normal return case of a function
12184 using eh_return: the eax and edx registers are marked as saved, but
12185 not restored along this path. Adjust the save location to match. */
12189 /* EH_RETURN requires the use of moves to function properly. */
12192 /* SEH requires the use of pops to identify the epilogue. */
12195 /* If we're only restoring one register and sp is not valid then
12196 using a move instruction to restore the register since it's
12197 less work than reloading sp and popping the register. */
12210 && TARGET_USE_LEAVE
12214 else
12218 {
12219 /* Ensure that the entire register save area is addressable via
12220 the stack pointer, if we will restore via sp. */
12225 {
12229 style,
12231 }
12232 }
12234 /* If there are any SSE registers to restore, then we have to do it
12235 via moves, since there's obviously no pop for SSE regs. */
12241 {
12242 rtx t;
12247 /* eh_return epilogues need %ecx added to the stack pointer. */
12249 {
12253 /* Stack align doesn't work with eh_return. */
12255 /* Neither does regparm nested functions. */
12259 {
12267 /* Note that we use SA as a temporary CFA, as the return
12268 address is at the proper place relative to it. We
12269 pretend this happens at the FP restore insn because
12270 prior to this insn the FP would be stored at the wrong
12271 offset relative to SA, and after this insn we have no
12272 other reasonable register to use for the CFA. We don't
12273 bother resetting the CFA to the SP for the duration of
12274 the return insn. */
12287 }
12288 else
12289 {
12297 {
12301 UNITS_PER_WORD));
12303 }
12304 }
12307 }
12308 }
12309 else
12310 {
12311 /* SEH requires that the function end with (1) a stack adjustment
12312 if necessary, (2) a sequence of pops, and (3) a return or
12313 jump instruction. Prevent insns from the function body from
12314 being scheduled into this sequence. */
12316 {
12317 /* Prevent a catch region from being adjacent to the standard
12318 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
12319 several other flags that would be interesting to test are
12320 not yet set up. */
12323 else
12325 }
12327 /* First step is to deallocate the stack frame so that we can
12328 pop the registers. Also do it on SEH target for very large
12329 frame as the emitted instructions aren't allowed by the ABI in
12330 epilogues. */
12332 || (TARGET_SEH
12335 {
12340 }
12342 {
12346 style,
12348 }
12351 }
12353 /* If we used a stack pointer and haven't already got rid of it,
12354 then do so now. */
12356 {
12357 /* If the stack pointer is valid and pointing at the frame
12358 pointer store address, then we only need a pop. */
12361 /* Leave results in shorter dependency chains on CPUs that are
12362 able to grok it fast. */
12367 else
12368 {
12370 hard_frame_pointer_rtx,
12373 }
12374 }
12377 {
12405 }
12407 /* At this point the stack pointer must be valid, and we must have
12408 restored all of the registers. We may not have deallocated the
12409 entire stack frame. We've delayed this until now because it may
12410 be possible to merge the local stack deallocation with the
12411 deallocation forced by ix86_static_chain_on_stack. */
12416 {
12420 }
12421 else
12424 /* Sibcall epilogues don't want a return instruction. */
12426 {
12429 }
12432 {
12435 /* i386 can only pop 64K bytes. If asked to pop more, pop return
12436 address, do explicit add, and jump indirectly to the caller. */
12439 {
12443 /* There is no "pascal" calling convention in any 64bit ABI. */
12459 }
12460 else
12462 }
12463 else
12466 /* Restore the state back to the state from the prologue,
12467 so that it's correct for the next epilogue. */
12469 }
12471 /* Reset from the function's potential modifications. */
12473 static void
12475 {
12479 #if TARGET_MACHO
12480 /* Mach-O doesn't support labels at the end of objects, so if
12481 it looks like we might want one, insert a NOP. */
12482 {
12488 {
12489 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
12490 notes only, instead set their CODE_LABEL_NUMBER to -1,
12491 otherwise there would be code generation differences
12492 in between -g and -g0. */
12496 }
12506 }
12507 #endif
12509 }
12511 /* Return a scratch register to use in the split stack prologue. The
12512 split stack prologue is used for -fsplit-stack. It is the first
12513 instructions in the function, even before the regular prologue.
12514 The scratch register can be any caller-saved register which is not
12515 used for parameters or for the static chain. */
12517 static unsigned int
12519 {
12522 else
12523 {
12536 {
12538 {
12542 }
12544 }
12546 {
12550 }
12552 {
12555 else
12556 {
12558 {
12562 }
12564 }
12565 }
12566 else
12567 {
12568 /* FIXME: We could make this work by pushing a register
12569 around the addition and comparison. */
12572 }
12573 }
12574 }
12576 /* A SYMBOL_REF for the function which allocates new stackspace for
12577 -fsplit-stack. */
12581 /* A SYMBOL_REF for the more stack function when using the large
12582 model. */
12586 /* Handle -fsplit-stack. These are the first instructions in the
12587 function, even before the regular prologue. */
12589 void
12591 {
12593 HOST_WIDE_INT allocate;
12599 rtx fn;
12607 /* This is the label we will branch to if we have enough stack
12608 space. We expect the basic block reordering pass to reverse this
12609 branch if optimizing, so that we branch in the unlikely case. */
12612 /* We need to compare the stack pointer minus the frame size with
12613 the stack boundary in the TCB. The stack boundary always gives
12614 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
12615 can compare directly. Otherwise we need to do an addition. */
12618 UNSPEC_STACK_CHECK);
12623 else
12624 {
12626 rtx offset;
12628 /* We need a scratch register to hold the stack pointer minus
12629 the required frame size. Since this is the very start of the
12630 function, the scratch register can be any caller-saved
12631 register which is not used for parameters. */
12638 {
12639 /* We don't use ix86_gen_add3 in this case because it will
12640 want to split to lea, but when not optimizing the insn
12641 will not be split after this point. */
12644 offset)));
12645 }
12646 else
12647 {
12650 stack_pointer_rtx));
12651 }
12653 }
12659 /* Mark the jump as very likely to be taken. */
12664 {
12667 }
12670 /* Get more stack space. We pass in the desired stack space and the
12671 size of the arguments to copy to the new stack. In 32-bit mode
12672 we push the parameters; __morestack will return on a new stack
12673 anyhow. In 64-bit mode we pass the parameters in r10 and
12674 r11. */
12679 {
12685 /* If this function uses a static chain, it will be in %r10.
12686 Preserve it across the call to __morestack. */
12688 {
12689 rtx rax;
12694 }
12698 {
12699 HOST_WIDE_INT argval;
12702 /* When using the large model we need to load the address
12703 into a register, and we've run out of registers. So we
12704 switch to a different calling convention, and we call a
12705 different function: __morestack_large. We pass the
12706 argument size in the upper 32 bits of r10 and pass the
12707 frame size in the lower 32 bits. */
12712 {
12713 split_stack_fn_large =
12716 }
12718 {
12720 rtx x;
12729 UNSPEC_GOT);
12735 }
12736 else
12743 }
12744 else
12745 {
12749 }
12752 }
12753 else
12754 {
12757 }
12763 /* In order to make call/return prediction work right, we now need
12764 to execute a return instruction. See
12765 libgcc/config/i386/morestack.S for the details on how this works.
12767 For flow purposes gcc must not see this as a return
12768 instruction--we need control flow to continue at the subsequent
12769 label. Therefore, we use an unspec. */
12773 /* If we are in 64-bit mode and this function uses a static chain,
12774 we saved %r10 in %rax before calling _morestack. */
12779 /* If this function calls va_start, we need to store a pointer to
12780 the arguments on the old stack, because they may not have been
12781 all copied to the new stack. At this point the old stack can be
12782 found at the frame pointer value used by __morestack, because
12783 __morestack has set that up before calling back to us. Here we
12784 store that pointer in a scratch register, and in
12785 ix86_expand_prologue we store the scratch register in a stack
12786 slot. */
12788 {
12790 rtx frame_reg;
12797 /* 64-bit:
12798 fp -> old fp value
12799 return address within this function
12800 return address of caller of this function
12801 stack arguments
12802 So we add three words to get to the stack arguments.
12804 32-bit:
12805 fp -> old fp value
12806 return address within this function
12807 first argument to __morestack
12808 second argument to __morestack
12809 return address of caller of this function
12810 stack arguments
12811 So we add five words to get to the stack arguments.
12812 */
12823 }
12828 /* If this function calls va_start, we now have to set the scratch
12829 register for the case where we do not call __morestack. In this
12830 case we need to set it based on the stack pointer. */
12832 {
12839 }
12840 }
12842 /* We may have to tell the dataflow pass that the split stack prologue
12843 is initializing a scratch register. */
12845 static void
12847 {
12849 {
12852 }
12853 }
12854 \f
12855 /* Extract the parts of an RTL expression that is a valid memory address
12856 for an instruction. Return 0 if the structure of the address is
12857 grossly off. Return -1 if the address contains ASHIFT, so it is not
12858 strictly valid, but still used for computing length of lea instruction. */
12860 int
12862 {
12867 rtx tmp;
12871 /* Allow zero-extended SImode addresses,
12872 they will be emitted with addr32 prefix. */
12874 {
12877 {
12881 }
12884 {
12891 }
12892 }
12894 /* Allow SImode subregs of DImode addresses,
12895 they will be emitted with addr32 prefix. */
12897 {
12900 {
12904 }
12905 }
12910 {
12913 else
12915 }
12917 {
12922 do
12923 {
12928 }
12935 {
12938 {
12963 /* FALLTHRU */
12967 && TARGET_TLS_DIRECT_SEG_REFS
12970 else
12977 /* FALLTHRU */
12984 else
12999 }
13000 }
13001 }
13003 {
13006 }
13008 {
13009 /* We're called for lea too, which implements ashift on occasion. */
13019 }
13020 else
13024 {
13026 ;
13029 ;
13030 else
13032 }
13034 /* Extract the integral value of scale. */
13036 {
13040 }
13045 /* Avoid useless 0 displacement. */
13049 /* Allow arg pointer and stack pointer as index if there is not scaling. */
13054 {
13057 }
13059 /* Special case: %ebp cannot be encoded as a base without a displacement.
13060 Similarly %r13. */
13062 && base_reg
13071 /* Special case: on K6, [%esi] makes the instruction vector decoded.
13072 Avoid this by transforming to [%esi+0].
13073 Reload calls address legitimization without cfun defined, so we need
13074 to test cfun for being non-NULL. */
13080 /* Special case: encode reg+reg instead of reg*2. */
13084 /* Special case: scaling cannot be encoded without base or displacement. */
13095 }
13096 \f
13097 /* Return cost of the memory address x.
13098 For i386, it is better to use a complex address than let gcc copy
13099 the address into a reg and make a new pseudo. But not if the address
13100 requires to two regs - that would mean more pseudos with longer
13101 lifetimes. */
13102 static int
13104 {
13116 /* Attempt to minimize number of registers in the address by increasing
13117 address cost for each used register. We don't increase address cost
13118 for "pic_offset_table_rtx". When a memopt with "pic_offset_table_rtx"
13119 is not invariant itself it most likely means that base or index is not
13120 invariant. Therefore only "pic_offset_table_rtx" could be hoisted out,
13121 which is not profitable for x86. */
13125 || !pic_offset_table_rtx
13128 cost++;
13133 || !pic_offset_table_rtx
13136 cost++;
13138 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
13139 since it's predecode logic can't detect the length of instructions
13140 and it degenerates to vector decoded. Increase cost of such
13141 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
13142 to split such addresses or even refuse such addresses at all.
13144 Following addressing modes are affected:
13145 [base+scale*index]
13146 [scale*index+disp]
13147 [base+index]
13149 The first and last case may be avoidable by explicitly coding the zero in
13150 memory address, but I don't have AMD-K6 machine handy to check this
13151 theory. */
13160 }
13161 \f
13162 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
13163 this is used for to form addresses to local data when -fPIC is in
13164 use. */
13166 static bool
13168 {
13171 }
13173 /* Determine if a given RTX is a valid constant. We already know this
13174 satisfies CONSTANT_P. */
13176 static bool
13178 {
13179 /* Pointer bounds constants are not valid. */
13184 {
13189 {
13193 }
13198 /* Only some unspecs are valid as "constants". */
13201 {
13217 }
13219 /* We must have drilled down to a symbol. */
13224 /* FALLTHRU */
13227 /* TLS symbols are never valid. */
13231 /* DLLIMPORT symbols are never valid. */
13236 #if TARGET_MACHO
13237 /* mdynamic-no-pic */
13240 #endif
13254 }
13256 /* Otherwise we handle everything else in the move patterns. */
13258 }
13260 /* Determine if it's legal to put X into the constant pool. This
13261 is not possible for the address of thread-local symbols, which
13262 is checked above. */
13264 static bool
13266 {
13267 /* We can always put integral constants and vectors in memory. */
13269 {
13278 }
13280 }
13282 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
13283 otherwise zero. */
13285 static bool
13287 {
13293 }
13296 /* Nonzero if the constant value X is a legitimate general operand
13297 when generating PIC code. It is given that flag_pic is on and
13298 that X satisfies CONSTANT_P. */
13300 bool
13302 {
13303 rtx inner;
13306 {
13313 /* Only some unspecs are valid as "constants". */
13316 {
13329 }
13330 /* FALLTHRU */
13338 }
13339 }
13341 /* Determine if a given CONST RTX is a valid memory displacement
13342 in PIC mode. */
13344 bool
13346 {
13349 /* In 64bit mode we can allow direct addresses of symbols and labels
13350 when they are not dynamic symbols. */
13352 {
13356 {
13380 /* FALLTHRU */
13383 /* TLS references should always be enclosed in UNSPEC.
13384 The dllimported symbol needs always to be resolved. */
13390 {
13398 /* Function-symbols need to be resolved only for
13399 large-model.
13400 For the small-model we don't need to resolve anything
13401 here. */
13406 /* Non-external symbols don't need to be resolved for
13407 large, and medium-model. */
13412 }
13415 || (HAVE_LD_PIE_COPYRELOC
13416 && flag_pie
13425 }
13426 }
13432 {
13433 /* We are unsafe to allow PLUS expressions. This limit allowed distance
13434 of GOT tables. We should not need these anyway. */
13446 }
13450 {
13455 }
13464 {
13468 /* We need to check for both symbols and labels because VxWorks loads
13469 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
13470 details. */
13474 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
13475 While ABI specify also 32bit relocation but we don't produce it in
13476 small PIC model at all. */
13498 }
13501 }
13503 /* Determine if op is suitable RTX for an address register.
13504 Return naked register if a register or a register subreg is
13505 found, otherwise return NULL_RTX. */
13507 static rtx
13509 {
13512 /* Only SImode or DImode registers can form the address. */
13519 {
13527 /* Don't allow SUBREGs that span more than a word. It can
13528 lead to spill failures when the register is one word out
13529 of a two word structure. */
13533 /* Allow only SUBREGs of non-eliminable hard registers. */
13536 }
13538 /* Op is not a register. */
13540 }
13542 /* Recognizes RTL expressions that are valid memory addresses for an
13543 instruction. The MODE argument is the machine mode for the MEM
13544 expression that wants to use this address.
13546 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
13547 convert common non-canonical forms to canonical form so that they will
13548 be recognized. */
13550 static bool
13552 {
13555 HOST_WIDE_INT scale;
13559 /* Decomposition failed. */
13568 /* Validate base register. */
13570 {
13578 /* Base is not valid. */
13580 }
13582 /* Validate index register. */
13584 {
13592 /* Index is not valid. */
13594 }
13596 /* Index and base should have the same mode. */
13601 /* Address override works only on the (%reg) part of %fs:(%reg). */
13607 /* Validate scale factor. */
13609 {
13611 /* Scale without index. */
13615 /* Scale is not a valid multiplier. */
13617 }
13619 /* Validate displacement. */
13621 {
13626 {
13627 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
13628 used. While ABI specify also 32bit relocations, we don't produce
13629 them at all and use IP relative instead. */
13636 /* 64bit address unspec. */
13656 /* Invalid address unspec. */
13658 }
13661 && (flag_pic
13662 || (TARGET_MACHO
13663 #if TARGET_MACHO
13664 && MACHOPIC_INDIRECT
13666 #endif
13667 )))
13668 {
13670 is_legitimate_pic:
13672 {
13673 /* foo@dtpoff(%rX) is ok. */
13680 /* Non-constant pic memory reference. */
13682 }
13685 /* Displacement is an invalid pic construct. */
13687 #if TARGET_MACHO
13690 /* displacment must be referenced via non_lazy_pointer */
13692 #endif
13694 /* This code used to verify that a symbolic pic displacement
13695 includes the pic_offset_table_rtx register.
13697 While this is good idea, unfortunately these constructs may
13698 be created by "adds using lea" optimization for incorrect
13699 code like:
13701 int a;
13702 int foo(int i)
13703 {
13704 return *(&a+i);
13705 }
13707 This code is nonsensical, but results in addressing
13708 GOT table with pic_offset_table_rtx base. We can't
13709 just refuse it easily, since it gets matched by
13710 "addsi3" pattern, that later gets split to lea in the
13711 case output register differs from input. While this
13712 can be handled by separate addsi pattern for this case
13713 that never results in lea, this seems to be easier and
13714 correct fix for crash to disable this test. */
13715 }
13722 /* Displacement is not constant. */
13726 /* Displacement is out of range. */
13728 /* In x32 mode, constant addresses are sign extended to 64bit, so
13729 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13734 }
13736 /* Everything looks valid. */
13738 }
13740 /* Determine if a given RTX is a valid constant address. */
13742 bool
13744 {
13746 }
13747 \f
13748 /* Return a unique alias set for the GOT. */
13750 static alias_set_type
13752 {
13757 }
13759 /* Return a legitimate reference for ORIG (an address) using the
13760 register REG. If REG is 0, a new pseudo is generated.
13762 There are two types of references that must be handled:
13764 1. Global data references must load the address from the GOT, via
13765 the PIC reg. An insn is emitted to do this load, and the reg is
13766 returned.
13768 2. Static data references, constant pool addresses, and code labels
13769 compute the address as an offset from the GOT, whose base is in
13770 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13771 differentiate them from global data objects. The returned
13772 address is the PIC reg + an unspec constant.
13774 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13775 reg also appears in the address. */
13777 static rtx
13779 {
13783 #if TARGET_MACHO
13785 {
13788 /* Use the generic Mach-O PIC machinery. */
13790 }
13791 #endif
13794 {
13798 }
13804 {
13805 rtx tmpreg;
13806 /* This symbol may be referenced via a displacement from the PIC
13807 base address (@GOTOFF). */
13812 {
13814 UNSPEC_GOTOFF);
13816 }
13817 else
13822 else
13827 {
13831 }
13832 else
13834 }
13836 {
13837 /* This symbol may be referenced via a displacement from the PIC
13838 base address (@GOTOFF). */
13843 {
13845 UNSPEC_GOTOFF);
13847 }
13848 else
13854 {
13857 }
13858 }
13860 /* We can't use @GOTOFF for text labels on VxWorks;
13861 see gotoff_operand. */
13863 {
13868 /* For x64 PE-COFF there is no GOT table. So we use address
13869 directly. */
13871 {
13879 }
13881 {
13889 /* Use directly gen_movsi, otherwise the address is loaded
13890 into register for CSE. We don't want to CSE this addresses,
13891 instead we CSE addresses from the GOT table, so skip this. */
13894 }
13895 else
13896 {
13897 /* This symbol must be referenced via a load from the
13898 Global Offset Table (@GOT). */
13912 }
13913 }
13914 else
13915 {
13918 {
13920 {
13923 }
13924 else
13926 }
13928 {
13931 /* We must match stuff we generate before. Assume the only
13932 unspecs that can get here are ours. Not that we could do
13933 anything with them anyway.... */
13939 }
13941 {
13944 /* Check first to see if this is a constant offset from a @GOTOFF
13945 symbol reference. */
13948 {
13950 {
13952 UNSPEC_GOTOFF);
13958 {
13961 }
13962 }
13963 else
13964 {
13967 {
13971 }
13972 }
13973 }
13974 else
13975 {
13978 new_rtx
13982 {
13985 {
13988 new_rtx
13990 }
13991 else
13993 }
13994 else
13995 {
13996 /* For %rip addressing, we have to use just disp32, not
13997 base nor index. */
14004 {
14007 }
14009 }
14010 }
14011 }
14012 }
14014 }
14015 \f
14016 /* Load the thread pointer. If TO_REG is true, force it into a register. */
14018 static rtx
14020 {
14024 {
14029 }
14035 }
14037 /* Construct the SYMBOL_REF for the tls_get_addr function. */
14041 static rtx
14043 {
14045 {
14051 }
14054 {
14056 UNSPEC_PLTOFF);
14059 }
14062 }
14064 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
14068 rtx
14070 {
14072 {
14073 ix86_tls_module_base_symbol
14078 }
14081 }
14083 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
14084 false if we expect this to be used for a memory address and true if
14085 we expect to load the address into a register. */
14087 static rtx
14089 {
14095 /* Fall back to global dynamic model if tool chain cannot support local
14096 dynamic. */
14103 {
14108 {
14111 else
14112 {
14115 }
14116 }
14119 {
14122 else
14132 }
14133 else
14134 {
14138 {
14143 emit_call_insn
14153 }
14154 else
14156 }
14163 {
14166 else
14167 {
14170 }
14171 }
14174 {
14179 else
14185 }
14186 else
14187 {
14191 {
14194 rtx eqv;
14197 emit_call_insn
14202 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
14203 share the LD_BASE result with other LD model accesses. */
14205 UNSPEC_TLS_LD_BASE);
14209 }
14210 else
14212 }
14220 {
14227 }
14232 {
14234 {
14235 /* The Sun linker took the AMD64 TLS spec literally
14236 and can only handle %rax as destination of the
14237 initial executable code sequence. */
14242 }
14244 /* Generate DImode references to avoid %fs:(%reg32)
14245 problems and linker IE->LE relaxation bug. */
14249 }
14251 {
14254 }
14256 {
14260 }
14261 else
14262 {
14265 }
14275 {
14280 }
14281 else
14282 {
14286 }
14296 {
14300 }
14301 else
14302 {
14306 }
14311 }
14314 }
14316 /* Create or return the unique __imp_DECL dllimport symbol corresponding
14317 to symbol DECL if BEIMPORT is true. Otherwise create or return the
14318 unique refptr-DECL symbol corresponding to symbol DECL. */
14321 {
14325 {
14327 }
14329 static int
14331 {
14333 }
14334 };
14338 static tree
14340 {
14346 tree to;
14347 rtx rtl;
14374 else
14387 {
14389 #ifdef SUB_TARGET_RECORD_STUB
14391 #endif
14392 }
14401 }
14403 /* Expand SYMBOL into its corresponding far-addresse symbol.
14404 WANT_REG is true if we require the result be a register. */
14406 static rtx
14408 {
14409 tree imp_decl;
14410 rtx x;
14419 }
14421 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
14422 true if we require the result be a register. */
14424 static rtx
14426 {
14427 tree imp_decl;
14428 rtx x;
14437 }
14439 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
14440 is true if we require the result be a register. */
14442 static rtx
14444 {
14449 {
14456 {
14459 }
14460 }
14476 {
14479 }
14481 }
14483 /* Try machine-dependent ways of modifying an illegitimate address
14484 to be legitimate. If we find one, return the new, valid address.
14485 This macro is used in only one place: `memory_address' in explow.c.
14487 OLDX is the address as it was before break_out_memory_refs was called.
14488 In some cases it is useful to look at this to decide what needs to be done.
14490 It is always safe for this macro to do nothing. It exists to recognize
14491 opportunities to optimize the output.
14493 For the 80386, we handle X+REG by loading X into a register R and
14494 using R+REG. R will go in a general reg and indexing will be used.
14495 However, if REG is a broken-out memory address or multiplication,
14496 nothing needs to be done because REG can certainly go in a general reg.
14498 When -fpic is used, special handling is needed for symbolic references.
14499 See comments by legitimize_pic_address in i386.c for details. */
14501 static rtx
14503 {
14514 {
14518 }
14521 {
14525 }
14530 #if TARGET_MACHO
14533 #endif
14535 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
14539 {
14544 }
14547 {
14548 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
14553 {
14559 }
14564 {
14570 }
14572 /* Put multiply first if it isn't already. */
14574 {
14577 }
14579 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
14580 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
14581 created by virtual register instantiation, register elimination, and
14582 similar optimizations. */
14584 {
14590 }
14592 /* Canonicalize
14593 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
14594 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
14599 {
14600 rtx constant;
14604 {
14607 }
14609 {
14612 }
14613 else
14617 {
14624 }
14625 }
14631 {
14634 }
14637 {
14640 }
14648 {
14651 }
14657 {
14661 {
14664 }
14668 }
14671 {
14675 {
14678 }
14682 }
14683 }
14686 }
14687 \f
14688 /* Print an integer constant expression in assembler syntax. Addition
14689 and subtraction are the only arithmetic that may appear in these
14690 expressions. FILE is the stdio stream to write to, X is the rtx, and
14691 CODE is the operand print code from the output string. */
14693 static void
14695 {
14699 {
14708 else
14709 {
14712 /* Mark the decl as referenced so that cgraph will
14713 output the function. */
14717 #if TARGET_MACHO
14721 #endif
14723 }
14731 /* FALLTHRU */
14742 /* This used to output parentheses around the expression,
14743 but that does not work on the 386 (either ATT or BSD assembler). */
14748 /* We can't handle floating point constants;
14749 TARGET_PRINT_OPERAND must handle them. */
14754 /* Some assemblers need integer constants to appear first. */
14756 {
14760 }
14761 else
14762 {
14767 }
14782 {
14786 }
14791 {
14810 /* FIXME: This might be @TPOFF in Sun ld too. */
14819 else
14829 else
14835 #if TARGET_MACHO
14840 #endif
14844 }
14849 }
14850 }
14852 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14853 We need to emit DTP-relative relocations. */
14855 static void ATTRIBUTE_UNUSED
14857 {
14862 {
14870 }
14871 }
14873 /* Return true if X is a representation of the PIC register. This copes
14874 with calls from ix86_find_base_term, where the register might have
14875 been replaced by a cselib value. */
14877 static bool
14879 {
14886 {
14894 }
14895 else
14897 }
14899 /* Helper function for ix86_delegitimize_address.
14900 Attempt to delegitimize TLS local-exec accesses. */
14902 static rtx
14904 {
14929 {
14934 }
14940 }
14942 /* In the name of slightly smaller debug output, and to cater to
14943 general assembler lossage, recognize PIC+GOTOFF and turn it back
14944 into a direct symbol reference.
14946 On Darwin, this is necessary to avoid a crash, because Darwin
14947 has a different PIC label for each routine but the DWARF debugging
14948 information is not associated with any particular routine, so it's
14949 necessary to remove references to the PIC label from RTL stored by
14950 the DWARF output code. */
14952 static rtx
14954 {
14956 /* addend is NULL or some rtx if x is something+GOTOFF where
14957 something doesn't include the PIC register. */
14959 /* reg_addend is NULL or a multiple of some register. */
14961 /* const_addend is NULL or a const_int. */
14963 /* This is the result, or NULL. */
14972 {
14979 {
14985 }
14992 {
14995 {
15000 }
15002 }
15007 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
15008 and -mcmodel=medium -fpic. */
15009 }
15016 /* %ebx + GOT/GOTOFF */
15017 ;
15019 {
15020 /* %ebx + %reg * scale + GOT/GOTOFF */
15026 else
15027 {
15030 }
15031 }
15032 else
15038 {
15041 }
15062 {
15063 /* If the rest of original X doesn't involve the PIC register, add
15064 addend and subtract pic_offset_table_rtx. This can happen e.g.
15065 for code like:
15066 leal (%ebx, %ecx, 4), %ecx
15067 ...
15068 movl foo@GOTOFF(%ecx), %edx
15069 in which case we return (%ecx - %ebx) + foo
15070 or (%ecx - _GLOBAL_OFFSET_TABLE_) + foo if pseudo_pic_reg
15071 and reload has completed. */
15075 pic_offset_table_rtx),
15076 result);
15078 {
15082 }
15083 else
15085 }
15087 {
15091 }
15093 }
15095 /* If X is a machine specific address (i.e. a symbol or label being
15096 referenced as a displacement from the GOT implemented using an
15097 UNSPEC), then return the base term. Otherwise return X. */
15099 rtx
15101 {
15102 rtx term;
15105 {
15118 }
15121 }
15122 \f
15123 static void
15126 {
15130 {
15133 }
15138 {
15141 {
15160 }
15164 {
15183 }
15190 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
15191 Those same assemblers have the same but opposite lossage on cmov. */
15194 else
15199 {
15212 }
15219 else
15224 {
15237 }
15244 else
15254 else
15265 }
15267 }
15269 /* Print the name of register X to FILE based on its machine mode and number.
15270 If CODE is 'w', pretend the mode is HImode.
15271 If CODE is 'b', pretend the mode is QImode.
15272 If CODE is 'k', pretend the mode is SImode.
15273 If CODE is 'q', pretend the mode is DImode.
15274 If CODE is 'x', pretend the mode is V4SFmode.
15275 If CODE is 't', pretend the mode is V8SFmode.
15276 If CODE is 'g', pretend the mode is V16SFmode.
15277 If CODE is 'h', pretend the reg is the 'high' byte register.
15278 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
15279 If CODE is 'd', duplicate the operand for AVX instruction.
15280 */
15282 void
15284 {
15294 {
15298 }
15301 {
15304 }
15322 else
15336 {
15344 normal:
15360 {
15365 }
15369 }
15373 /* Irritatingly, AMD extended registers use
15374 different naming convention: "r%d[bwd]" */
15376 {
15379 {
15393 /* no suffix */
15398 }
15400 }
15403 {
15406 else
15408 }
15409 }
15411 /* Meaning of CODE:
15412 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
15413 C -- print opcode suffix for set/cmov insn.
15414 c -- like C, but print reversed condition
15415 F,f -- likewise, but for floating-point.
15416 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
15417 otherwise nothing
15418 R -- print embeded rounding and sae.
15419 r -- print only sae.
15420 z -- print the opcode suffix for the size of the current operand.
15421 Z -- likewise, with special suffixes for x87 instructions.
15422 * -- print a star (in certain assembler syntax)
15423 A -- print an absolute memory reference.
15424 E -- print address with DImode register names if TARGET_64BIT.
15425 w -- print the operand as if it's a "word" (HImode) even if it isn't.
15426 s -- print a shift double count, followed by the assemblers argument
15427 delimiter.
15428 b -- print the QImode name of the register for the indicated operand.
15429 %b0 would print %al if operands[0] is reg 0.
15430 w -- likewise, print the HImode name of the register.
15431 k -- likewise, print the SImode name of the register.
15432 q -- likewise, print the DImode name of the register.
15433 x -- likewise, print the V4SFmode name of the register.
15434 t -- likewise, print the V8SFmode name of the register.
15435 g -- likewise, print the V16SFmode name of the register.
15436 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
15437 y -- print "st(0)" instead of "st" as a register.
15438 d -- print duplicated register operand for AVX instruction.
15439 D -- print condition for SSE cmp instruction.
15440 P -- if PIC, print an @PLT suffix.
15441 p -- print raw symbol name.
15442 X -- don't print any sort of PIC '@' suffix for a symbol.
15443 & -- print some in-use local-dynamic symbol name.
15444 H -- print a memory address offset by 8; used for sse high-parts
15445 Y -- print condition for XOP pcom* instruction.
15446 + -- print a branch hint as 'cs' or 'ds' prefix
15447 ; -- print a semicolon (after prefixes due to bug in older gas).
15448 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
15449 @ -- print a segment register of thread base pointer load
15450 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
15451 ! -- print MPX prefix for jxx/call/ret instructions if required.
15452 */
15454 void
15456 {
15458 {
15460 {
15463 {
15469 /* Intel syntax. For absolute addresses, registers should not
15470 be surrounded by braces. */
15472 {
15477 }
15482 }
15488 /* Wrap address in an UNSPEC to declare special handling. */
15526 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15531 {
15545 output_operand_lossage
15548 }
15551 #endif
15556 {
15557 /* Opcodes don't get size suffixes if using Intel opcodes. */
15562 {
15580 output_operand_lossage
15583 }
15584 }
15587 warning
15589 /* FALLTHRU */
15592 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
15597 {
15599 {
15601 #ifdef HAVE_AS_IX86_FILDS
15603 #endif
15611 #ifdef HAVE_AS_IX86_FILDQ
15613 #else
15615 #endif
15620 }
15621 }
15623 {
15624 /* 387 opcodes don't get size suffixes
15625 if the operands are registers. */
15630 {
15646 }
15647 }
15648 else
15649 {
15650 output_operand_lossage
15653 }
15655 output_operand_lossage
15676 {
15679 }
15684 {
15735 }
15739 /* Little bit of braindamage here. The SSE compare instructions
15740 does use completely different names for the comparisons that the
15741 fp conditional moves. */
15743 {
15746 {
15749 }
15755 {
15758 }
15764 {
15767 }
15776 {
15779 }
15785 {
15788 }
15794 {
15797 }
15808 }
15813 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15816 #endif
15821 {
15825 }
15829 file);
15834 {
15838 }
15839 /* It doesn't actually matter what mode we use here, as we're
15840 only going to use this for printing. */
15842 /* Output 'qword ptr' for intel assembler dialect. */
15851 #ifdef HAVE_AS_IX86_HLE
15853 #else
15855 #endif
15857 #ifdef HAVE_AS_IX86_HLE
15859 #else
15861 #endif
15862 /* We do not want to print value of the operand. */
15891 {
15906 }
15919 {
15924 else
15927 }
15930 {
15931 rtx x;
15940 {
15945 {
15947 bool cputaken
15950 /* Emit hints only in the case default branch prediction
15951 heuristics would fail. */
15953 {
15954 /* We use 3e (DS) prefix for taken branches and
15955 2e (CS) prefix for not taken branches. */
15958 else
15960 }
15961 }
15962 }
15964 }
15967 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15969 #endif
15976 /* The kernel uses a different segment register for performance
15977 reasons; a system call would not have to trash the userspace
15978 segment register, which would be expensive. */
15981 else
16001 }
16002 }
16008 {
16009 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
16012 {
16015 {
16024 else
16031 }
16033 /* Check for explicit size override (codes 'b', 'w', 'k',
16034 'q' and 'x') */
16048 }
16051 /* Avoid (%rip) for call operands. */
16057 else
16059 }
16062 {
16063 REAL_VALUE_TYPE r;
16071 /* Sign extend 32bit SFmode immediate to 8 bytes. */
16075 else
16077 }
16080 {
16081 REAL_VALUE_TYPE r;
16090 }
16092 /* These float cases don't actually occur as immediate operands. */
16094 {
16099 }
16101 else
16102 {
16103 /* We have patterns that allow zero sets of memory, for instance.
16104 In 64-bit mode, we should probably support all 8-byte vectors,
16105 since we can in fact encode that into an immediate. */
16107 {
16110 }
16113 {
16115 {
16118 }
16121 {
16124 else
16126 }
16127 }
16132 else
16134 }
16135 }
16137 static bool
16139 {
16142 }
16143 \f
16144 /* Print a memory operand whose address is ADDR. */
16146 static void
16148 {
16157 {
16164 }
16166 {
16170 }
16172 {
16176 {
16179 }
16182 }
16184 {
16189 }
16190 else
16201 {
16212 }
16214 /* Use one byte shorter RIP relative addressing for 64bit mode. */
16216 {
16228 }
16230 {
16231 /* Displacement only requires special attention. */
16234 {
16238 }
16241 else
16243 }
16244 else
16245 {
16246 /* Print SImode register names to force addr32 prefix. */
16248 {
16249 #ifdef ENABLE_CHECKING
16252 {
16263 }
16264 #endif
16267 }
16269 && TARGET_X32
16270 && disp
16273 {
16274 /* X32 runs in 64-bit mode, where displacement, DISP, in
16275 address DISP(%r64), is encoded as 32-bit immediate sign-
16276 extended from 32-bit to 64-bit. For -0x40000300(%r64),
16277 address is %r64 + 0xffffffffbffffd00. When %r64 <
16278 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
16279 which is invalid for x32. The correct address is %r64
16280 - 0x40000300 == 0xf7ffdd64. To properly encode
16281 -0x40000300(%r64) for x32, we zero-extend negative
16282 displacement by forcing addr32 prefix which truncates
16283 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
16284 zero-extend all negative displacements, including -1(%rsp).
16285 However, for small negative displacements, sign-extension
16286 won't cause overflow. We only zero-extend negative
16287 displacements if they < -16*1024*1024, which is also used
16288 to check legitimate address displacements for PIC. */
16290 }
16293 {
16295 {
16300 else
16302 }
16308 {
16313 }
16315 }
16316 else
16317 {
16321 {
16322 /* Pull out the offset of a symbol; print any symbol itself. */
16326 {
16330 }
16338 else
16340 }
16344 {
16347 {
16351 }
16352 }
16355 else
16359 {
16364 }
16366 }
16367 }
16368 }
16370 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
16372 static bool
16374 {
16375 rtx op;
16382 {
16385 /* FIXME: This might be @TPOFF in Sun ld. */
16396 else
16408 else
16415 #if TARGET_MACHO
16421 #endif
16424 {
16429 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
16431 #else
16433 #endif
16436 }
16441 }
16444 }
16445 \f
16446 /* Split one or more double-mode RTL references into pairs of half-mode
16447 references. The RTL can be REG, offsettable MEM, integer constant, or
16448 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
16449 split and "num" is its length. lo_half and hi_half are output arrays
16450 that parallel "operands". */
16452 void
16455 {
16456 machine_mode half_mode;
16460 {
16469 }
16474 {
16477 /* simplify_subreg refuse to split volatile memory addresses,
16478 but we still have to handle it. */
16480 {
16483 }
16484 else
16485 {
16492 }
16493 }
16494 }
16495 \f
16496 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
16497 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
16498 is the expression of the binary operation. The output may either be
16499 emitted here, or returned to the caller, like all output_* functions.
16501 There is no guarantee that the operands are the same mode, as they
16502 might be within FLOAT or FLOAT_EXTEND expressions. */
16504 #ifndef SYSV386_COMPAT
16505 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
16506 wants to fix the assemblers because that causes incompatibility
16507 with gcc. No-one wants to fix gcc because that causes
16508 incompatibility with assemblers... You can use the option of
16509 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
16510 #define SYSV386_COMPAT 1
16511 #endif
16515 {
16521 #ifdef ENABLE_CHECKING
16522 /* Even if we do not want to check the inputs, this documents input
16523 constraints. Which helps in understanding the following code. */
16533 else
16535 #endif
16538 {
16543 else
16552 else
16561 else
16570 else
16577 }
16580 {
16582 {
16586 else
16588 }
16589 else
16590 {
16594 else
16596 }
16598 }
16602 {
16608 /* know operands[0] == operands[1]. */
16611 {
16614 }
16617 {
16619 /* How is it that we are storing to a dead operand[2]?
16620 Well, presumably operands[1] is dead too. We can't
16621 store the result to st(0) as st(0) gets popped on this
16622 instruction. Instead store to operands[2] (which I
16623 think has to be st(1)). st(1) will be popped later.
16624 gcc <= 2.8.1 didn't have this check and generated
16625 assembly code that the Unixware assembler rejected. */
16627 else
16630 }
16634 else
16641 {
16644 }
16647 {
16650 }
16653 {
16654 #if SYSV386_COMPAT
16655 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
16656 derived assemblers, confusingly reverse the direction of
16657 the operation for fsub{r} and fdiv{r} when the
16658 destination register is not st(0). The Intel assembler
16659 doesn't have this brain damage. Read !SYSV386_COMPAT to
16660 figure out what the hardware really does. */
16663 else
16665 #else
16667 /* As above for fmul/fadd, we can't store to st(0). */
16669 else
16671 #endif
16673 }
16676 {
16677 #if SYSV386_COMPAT
16680 else
16682 #else
16685 else
16687 #endif
16689 }
16692 {
16695 else
16698 }
16700 {
16701 #if SYSV386_COMPAT
16703 #else
16705 #endif
16706 }
16707 else
16708 {
16709 #if SYSV386_COMPAT
16711 #else
16713 #endif
16714 }
16719 }
16723 }
16725 /* Check if a 256bit AVX register is referenced inside of EXP. */
16727 static bool
16729 {
16735 }
16737 /* Return needed mode for entity in optimize_mode_switching pass. */
16739 static int
16741 {
16743 {
16744 rtx link;
16746 /* Needed mode is set to AVX_U128_CLEAN if there are
16747 no 256bit modes used in function arguments. */
16749 link;
16751 {
16753 {
16758 }
16759 }
16762 }
16764 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16765 changes state only when a 256bit register is written to, but we need
16766 to prevent the compiler from moving optimal insertion point above
16767 eventual read from 256bit register. */
16774 }
16776 /* Return mode that i387 must be switched into
16777 prior to the execution of insn. */
16779 static int
16781 {
16784 /* The mode UNINITIALIZED is used to store control word after a
16785 function call or ASM pattern. The mode ANY specify that function
16786 has no requirements on the control word and make no changes in the
16787 bits we are interested in. */
16801 {
16824 }
16827 }
16829 /* Return mode that entity must be switched into
16830 prior to the execution of insn. */
16832 static int
16834 {
16836 {
16846 }
16848 }
16850 /* Check if a 256bit AVX register is referenced in stores. */
16852 static void
16854 {
16856 {
16859 }
16860 }
16862 /* Calculate mode of upper 128bit AVX registers after the insn. */
16864 static int
16866 {
16873 /* We know that state is clean after CALL insn if there are no
16874 256bit registers used in the function return register. */
16876 {
16881 }
16883 /* Otherwise, return current mode. Remember that if insn
16884 references AVX 256bit registers, the mode was already changed
16885 to DIRTY from MODE_NEEDED. */
16887 }
16889 /* Return the mode that an insn results in. */
16891 static int
16893 {
16895 {
16905 }
16906 }
16908 static int
16910 {
16911 tree arg;
16913 /* Entry mode is set to AVX_U128_DIRTY if there are
16914 256bit modes used in function arguments. */
16917 {
16922 }
16925 }
16927 /* Return a mode that ENTITY is assumed to be
16928 switched to at function entry. */
16930 static int
16932 {
16934 {
16944 }
16945 }
16947 static int
16949 {
16952 /* Exit mode is set to AVX_U128_DIRTY if there are
16953 256bit modes used in the function return register. */
16958 }
16960 /* Return a mode that ENTITY is assumed to be
16961 switched to at function exit. */
16963 static int
16965 {
16967 {
16977 }
16978 }
16980 static int
16982 {
16984 }
16986 /* Output code to initialize control word copies used by trunc?f?i and
16987 rounding patterns. CURRENT_MODE is set to current control word,
16988 while NEW_MODE is set to new control word. */
16990 static void
16992 {
16994 rtx new_mode;
17005 {
17007 {
17009 /* round toward zero (truncate) */
17015 /* round down toward -oo */
17022 /* round up toward +oo */
17029 /* mask precision exception for nearbyint() */
17036 }
17037 }
17038 else
17039 {
17041 {
17043 /* round toward zero (truncate) */
17049 /* round down toward -oo */
17055 /* round up toward +oo */
17061 /* mask precision exception for nearbyint() */
17068 }
17069 }
17075 }
17077 /* Emit vzeroupper. */
17079 void
17081 {
17084 /* Cancel automatic vzeroupper insertion if there are
17085 live call-saved SSE registers at the insertion point. */
17097 }
17099 /* Generate one or more insns to set ENTITY to MODE. */
17101 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
17102 is the set of hard registers live at the point where the insn(s)
17103 are to be inserted. */
17105 static void
17107 HARD_REG_SET regs_live)
17108 {
17110 {
17125 }
17126 }
17128 /* Output code for INSN to convert a float to a signed int. OPERANDS
17129 are the insn operands. The output may be [HSD]Imode and the input
17130 operand may be [SDX]Fmode. */
17134 {
17139 /* Jump through a hoop or two for DImode, since the hardware has no
17140 non-popping instruction. We used to do this a different way, but
17141 that was somewhat fragile and broke with post-reload splitters. */
17151 else
17152 {
17157 else
17161 }
17164 }
17166 /* Output code for x87 ffreep insn. The OPNO argument, which may only
17167 have the values zero or one, indicates the ffreep insn's operand
17168 from the OPERANDS array. */
17172 {
17174 #ifdef HAVE_AS_IX86_FFREEP
17176 #else
17177 {
17187 }
17188 #endif
17191 }
17194 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
17195 should be used. UNORDERED_P is true when fucom should be used. */
17199 {
17205 {
17208 }
17209 else
17210 {
17213 }
17216 {
17220 else
17222 else
17225 else
17227 }
17234 {
17236 {
17239 }
17240 else
17242 }
17245 && stack_top_dies
17248 {
17249 /* If both the top of the 387 stack dies, and the other operand
17250 is also a stack register that dies, then this must be a
17251 `fcompp' float compare */
17254 {
17255 /* There is no double popping fcomi variant. Fortunately,
17256 eflags is immune from the fstp's cc clobbering. */
17259 else
17262 }
17263 else
17264 {
17267 else
17269 }
17270 }
17271 else
17272 {
17273 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
17276 {
17284 NULL,
17285 NULL,
17292 NULL,
17293 NULL,
17294 NULL,
17295 NULL
17296 };
17311 }
17312 }
17314 void
17316 {
17319 #ifdef ASM_QUAD
17322 #else
17324 #endif
17327 }
17329 void
17331 {
17334 #ifdef ASM_QUAD
17337 #else
17339 #endif
17340 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
17346 #if TARGET_MACHO
17348 {
17352 }
17353 #endif
17354 else
17357 }
17358 \f
17359 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
17360 for the target. */
17362 void
17364 {
17365 rtx tmp;
17367 /* We play register width games, which are only valid after reload. */
17370 /* Avoid HImode and its attendant prefix byte. */
17376 {
17379 }
17382 }
17384 /* X is an unchanging MEM. If it is a constant pool reference, return
17385 the constant pool rtx, else NULL. */
17387 rtx
17389 {
17396 }
17398 void
17400 {
17408 {
17409 rtx tmp;
17413 {
17419 }
17422 }
17426 {
17429 rtx tmp;
17434 else
17438 {
17445 }
17446 }
17450 {
17452 {
17453 #if TARGET_MACHO
17454 /* dynamic-no-pic */
17456 {
17463 }
17465 {
17469 }
17472 else
17473 {
17481 }
17482 /* dynamic-no-pic */
17483 #endif
17484 }
17485 else
17486 {
17490 {
17496 }
17497 }
17498 }
17499 else
17500 {
17511 /* Force large constants in 64bit compilation into register
17512 to get them CSEed. */
17523 {
17524 /* If we are loading a floating point constant to a register,
17525 force the value to memory now, since we'll get better code
17526 out the back end. */
17530 {
17535 }
17536 }
17537 }
17540 }
17542 void
17544 {
17551 /* Force constants other than zero into memory. We do not know how
17552 the instructions used to build constants modify the upper 64 bits
17553 of the register, once we have that information we may be able
17554 to handle some of them more efficiently. */
17563 /* We need to check memory alignment for SSE mode since attribute
17564 can make operands unaligned. */
17569 {
17572 /* ix86_expand_vector_move_misalign() does not like constants ... */
17578 /* ... nor both arguments in memory. */
17586 }
17588 /* Make operand1 a register if it isn't already. */
17592 {
17595 }
17598 }
17600 /* Split 32-byte AVX unaligned load and store if needed. */
17602 static void
17604 {
17605 rtx m;
17609 machine_mode mode;
17612 {
17633 }
17636 {
17639 {
17646 }
17647 /* Normal *mov<mode>_internal pattern will handle
17648 unaligned loads just fine if misaligned_operand
17649 is true, and without the UNSPEC it can be combined
17650 with arithmetic instructions. */
17653 else
17655 }
17657 {
17660 {
17665 }
17666 else
17668 }
17669 else
17671 }
17673 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17674 straight to ix86_expand_vector_move. */
17675 /* Code generation for scalar reg-reg moves of single and double precision data:
17676 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17677 movaps reg, reg
17678 else
17679 movss reg, reg
17680 if (x86_sse_partial_reg_dependency == true)
17681 movapd reg, reg
17682 else
17683 movsd reg, reg
17685 Code generation for scalar loads of double precision data:
17686 if (x86_sse_split_regs == true)
17687 movlpd mem, reg (gas syntax)
17688 else
17689 movsd mem, reg
17691 Code generation for unaligned packed loads of single precision data
17692 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17693 if (x86_sse_unaligned_move_optimal)
17694 movups mem, reg
17696 if (x86_sse_partial_reg_dependency == true)
17697 {
17698 xorps reg, reg
17699 movlps mem, reg
17700 movhps mem+8, reg
17701 }
17702 else
17703 {
17704 movlps mem, reg
17705 movhps mem+8, reg
17706 }
17708 Code generation for unaligned packed loads of double precision data
17709 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17710 if (x86_sse_unaligned_move_optimal)
17711 movupd mem, reg
17713 if (x86_sse_split_regs == true)
17714 {
17715 movlpd mem, reg
17716 movhpd mem+8, reg
17717 }
17718 else
17719 {
17720 movsd mem, reg
17721 movhpd mem+8, reg
17722 }
17723 */
17725 void
17727 {
17736 {
17738 {
17742 {
17744 {
17747 }
17748 else
17750 }
17752 /* FALLTHRU */
17756 {
17771 }
17777 else
17785 }
17788 }
17792 {
17794 {
17798 {
17800 {
17803 }
17804 else
17806 }
17808 /* FALLTHRU */
17818 }
17821 }
17824 {
17825 /* Normal *mov<mode>_internal pattern will handle
17826 unaligned loads just fine if misaligned_operand
17827 is true, and without the UNSPEC it can be combined
17828 with arithmetic instructions. */
17834 /* ??? If we have typed data, then it would appear that using
17835 movdqu is the only way to get unaligned data loaded with
17836 integer type. */
17838 {
17840 {
17843 }
17845 /* We will eventually emit movups based on insn attributes. */
17849 }
17851 {
17852 rtx zero;
17855 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17856 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17858 {
17859 /* We will eventually emit movups based on insn attributes. */
17862 }
17864 /* When SSE registers are split into halves, we can avoid
17865 writing to the top half twice. */
17867 {
17870 }
17871 else
17872 {
17873 /* ??? Not sure about the best option for the Intel chips.
17874 The following would seem to satisfy; the register is
17875 entirely cleared, breaking the dependency chain. We
17876 then store to the upper half, with a dependency depth
17877 of one. A rumor has it that Intel recommends two movsd
17878 followed by an unpacklpd, but this is unconfirmed. And
17879 given that the dependency depth of the unpacklpd would
17880 still be one, I'm not sure why this would be better. */
17882 }
17888 }
17889 else
17890 {
17891 rtx t;
17894 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17895 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17897 {
17899 {
17902 }
17909 }
17913 else
17918 else
17927 }
17928 }
17930 {
17932 {
17935 /* We will eventually emit movups based on insn attributes. */
17937 }
17939 {
17941 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17942 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17944 /* We will eventually emit movups based on insn attributes. */
17946 else
17947 {
17952 }
17953 }
17954 else
17955 {
17960 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17961 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17963 {
17966 }
17967 else
17968 {
17973 }
17974 }
17975 }
17976 else
17978 }
17980 /* Helper function of ix86_fixup_binary_operands to canonicalize
17981 operand order. Returns true if the operands should be swapped. */
17983 static bool
17985 rtx operands[])
17986 {
17991 /* If the operation is not commutative, we can't do anything. */
17995 /* Highest priority is that src1 should match dst. */
18001 /* Next highest priority is that immediate constants come second. */
18007 /* Lowest priority is that memory references should come second. */
18014 }
18017 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
18018 destination to use for the operation. If different from the true
18019 destination in operands[0], a copy operation will be required. */
18021 rtx
18023 rtx operands[])
18024 {
18029 /* Canonicalize operand order. */
18031 {
18032 /* It is invalid to swap operands of different modes. */
18036 }
18038 /* Both source operands cannot be in memory. */
18040 {
18041 /* Optimization: Only read from memory once. */
18043 {
18046 }
18049 else
18051 }
18053 /* If the destination is memory, and we do not have matching source
18054 operands, do things in registers. */
18058 /* Source 1 cannot be a constant. */
18062 /* Source 1 cannot be a non-matching memory. */
18066 /* Improve address combine. */
18075 }
18077 /* Similarly, but assume that the destination has already been
18078 set up properly. */
18080 void
18083 {
18086 }
18088 /* Attempt to expand a binary operator. Make the expansion closer to the
18089 actual machine, then just general_operand, which will allow 3 separate
18090 memory references (one output, two input) in a single insn. */
18092 void
18094 rtx operands[])
18095 {
18102 /* Emit the instruction. */
18109 {
18110 /* This is going to be an LEA; avoid splitting it later. */
18112 }
18113 else
18114 {
18117 }
18119 /* Fix up the destination if needed. */
18122 }
18124 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
18125 the given OPERANDS. */
18127 void
18129 rtx operands[])
18130 {
18133 {
18136 }
18138 {
18141 }
18142 /* Optimize (__m128i) d | (__m128i) e and similar code
18143 when d and e are float vectors into float vector logical
18144 insn. In C/C++ without using intrinsics there is no other way
18145 to express vector logical operation on float vectors than
18146 to cast them temporarily to integer vectors. */
18148 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
18157 {
18158 rtx dst;
18160 {
18169 {
18172 }
18173 else
18174 {
18179 }
18190 }
18191 }
18200 }
18202 /* Return TRUE or FALSE depending on whether the binary operator meets the
18203 appropriate constraints. */
18205 bool
18208 {
18213 /* Both source operands cannot be in memory. */
18217 /* Canonicalize operand order for commutative operators. */
18221 /* If the destination is memory, we must have a matching source operand. */
18225 /* Source 1 cannot be a constant. */
18229 /* Source 1 cannot be a non-matching memory. */
18231 /* Support "andhi/andsi/anddi" as a zero-extending move. */
18239 }
18241 /* Attempt to expand a unary operator. Make the expansion closer to the
18242 actual machine, then just general_operand, which will allow 2 separate
18243 memory references (one output, one input) in a single insn. */
18245 void
18247 rtx operands[])
18248 {
18255 /* If the destination is memory, and we do not have matching source
18256 operands, do things in registers. */
18258 {
18261 else
18263 }
18265 /* When source operand is memory, destination must match. */
18269 /* Emit the instruction. */
18275 else
18276 {
18279 }
18281 /* Fix up the destination if needed. */
18284 }
18286 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
18287 divisor are within the range [0-255]. */
18289 void
18292 {
18301 {
18314 }
18321 /* Use 8bit unsigned divimod if dividend and divisor are within
18322 the range [0-255]. */
18331 pc_rtx);
18336 /* Generate original signed/unsigned divimod. */
18341 /* Branch to the end. */
18345 /* Generate 8bit unsigned divide. */
18347 /* Don't use operands[0] for result of 8bit divide since not all
18348 registers support QImode ZERO_EXTRACT. */
18355 {
18358 }
18359 else
18360 {
18363 }
18365 /* Extract remainder from AH. */
18369 else
18370 {
18371 /* Need a new scratch register since the old one has result
18372 of 8bit divide. */
18376 }
18379 /* Zero extend quotient from AL. */
18385 }
18387 #define LEA_MAX_STALL (3)
18388 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
18390 /* Increase given DISTANCE in half-cycles according to
18391 dependencies between PREV and NEXT instructions.
18392 Add 1 half-cycle if there is no dependency and
18393 go to next cycle if there is some dependecy. */
18395 static unsigned int
18397 {
18413 }
18415 /* Function checks if instruction INSN defines register number
18416 REGNO1 or REGNO2. */
18418 static bool
18421 {
18422 df_ref def;
18432 }
18434 /* Function checks if instruction INSN uses register number
18435 REGNO as a part of address expression. */
18437 static bool
18439 {
18440 df_ref use;
18447 }
18449 /* Search backward for non-agu definition of register number REGNO1
18450 or register number REGNO2 in basic block starting from instruction
18451 START up to head of basic block or instruction INSN.
18453 Function puts true value into *FOUND var if definition was found
18454 and false otherwise.
18456 Distance in half-cycles between START and found instruction or head
18457 of BB is added to DISTANCE and returned. */
18459 static int
18463 {
18473 {
18475 {
18478 {
18481 {
18484 }
18485 }
18488 }
18493 }
18496 }
18498 /* Search backward for non-agu definition of register number REGNO1
18499 or register number REGNO2 in INSN's basic block until
18500 1. Pass LEA_SEARCH_THRESHOLD instructions, or
18501 2. Reach neighbour BBs boundary, or
18502 3. Reach agu definition.
18503 Returns the distance between the non-agu definition point and INSN.
18504 If no definition point, returns -1. */
18506 static int
18509 {
18520 {
18521 edge e;
18522 edge_iterator ei;
18527 {
18530 }
18536 else
18537 {
18542 {
18543 int bb_dist
18549 {
18556 }
18557 }
18560 }
18561 }
18563 /* get_attr_type may modify recog data. We want to make sure
18564 that recog data is valid for instruction INSN, on which
18565 distance_non_agu_define is called. INSN is unchanged here. */
18572 }
18574 /* Return the distance in half-cycles between INSN and the next
18575 insn that uses register number REGNO in memory address added
18576 to DISTANCE. Return -1 if REGNO0 is set.
18578 Put true value into *FOUND if register usage was found and
18579 false otherwise.
18580 Put true value into *REDEFINED if register redefinition was
18581 found and false otherwise. */
18583 static int
18587 {
18596 {
18599 /* If insn and start belong to the same bb, set prev to insn,
18600 so the call to increase_distance will increase the distance
18601 between insns by 1. */
18603 }
18608 {
18610 {
18613 {
18614 /* Return DISTANCE if OP0 is used in memory
18615 address in NEXT. */
18618 }
18621 {
18622 /* Return -1 if OP0 is set in NEXT. */
18625 }
18628 }
18634 }
18637 }
18639 /* Return the distance between INSN and the next insn that uses
18640 register number REGNO0 in memory address. Return -1 if no such
18641 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18643 static int
18645 {
18657 {
18658 edge e;
18659 edge_iterator ei;
18664 {
18667 }
18673 else
18674 {
18680 {
18681 int bb_dist
18686 {
18693 }
18694 }
18697 }
18698 }
18704 }
18706 /* Define this macro to tune LEA priority vs ADD, it take effect when
18707 there is a dilemma of choicing LEA or ADD
18708 Negative value: ADD is more preferred than LEA
18709 Zero: Netrual
18710 Positive value: LEA is more preferred than ADD*/
18711 #define IX86_LEA_PRIORITY 0
18713 /* Return true if usage of lea INSN has performance advantage
18714 over a sequence of instructions. Instructions sequence has
18715 SPLIT_COST cycles higher latency than lea latency. */
18717 static bool
18720 {
18723 /* For Silvermont if using a 2-source or 3-source LEA for
18724 non-destructive destination purposes, or due to wanting
18725 ability to use SCALE, the use of LEA is justified. */
18727 {
18735 }
18741 {
18742 /* If there is no non AGU operand definition, no AGU
18743 operand usage and split cost is 0 then both lea
18744 and non lea variants have same priority. Currently
18745 we prefer lea for 64 bit code and non lea on 32 bit
18746 code. */
18749 else
18751 }
18753 /* With longer definitions distance lea is more preferable.
18754 Here we change it to take into account splitting cost and
18755 lea priority. */
18758 /* If there is no use in memory addess then we just check
18759 that split cost exceeds AGU stall. */
18763 /* If this insn has both backward non-agu dependence and forward
18764 agu dependence, the one with short distance takes effect. */
18766 }
18768 /* Return true if it is legal to clobber flags by INSN and
18769 false otherwise. */
18771 static bool
18773 {
18775 df_ref use;
18776 bitmap live;
18779 {
18781 {
18788 }
18794 }
18798 }
18800 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18801 move and add to avoid AGU stalls. */
18803 bool
18805 {
18808 /* Check if we need to optimize. */
18812 /* Check it is correct to split here. */
18820 /* We need to split only adds with non destructive
18821 destination operand. */
18824 else
18826 }
18828 /* Return true if we should emit lea instruction instead of mov
18829 instruction. */
18831 bool
18833 {
18836 /* Check if we need to optimize. */
18840 /* Use lea for reg to reg moves only. */
18848 }
18850 /* Return true if we need to split lea into a sequence of
18851 instructions to avoid AGU stalls. */
18853 bool
18855 {
18861 /* Check we need to optimize. */
18865 /* The "at least two components" test below might not catch simple
18866 move or zero extension insns if parts.base is non-NULL and parts.disp
18867 is const0_rtx as the only components in the address, e.g. if the
18868 register is %rbp or %r13. As this test is much cheaper and moves or
18869 zero extensions are the common case, do this check first. */
18875 /* Check if it is OK to split here. */
18882 /* There should be at least two components in the address. */
18887 /* We should not split into add if non legitimate pic
18888 operand is used as displacement. */
18903 /* Compute how many cycles we will add to execution time
18904 if split lea into a sequence of instructions. */
18906 {
18907 /* Have to use mov instruction if non desctructive
18908 destination form is used. */
18912 /* Have to add index to base if both exist. */
18916 /* Have to use shift and adds if scale is 2 or greater. */
18918 {
18923 else
18925 }
18927 /* Have to use add instruction with immediate if
18928 disp is non zero. */
18932 /* Subtract the price of lea. */
18934 }
18938 }
18940 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18941 matches destination. RTX includes clobber of FLAGS_REG. */
18943 static void
18946 {
18953 }
18955 /* Return true if regno1 def is nearest to the insn. */
18957 static bool
18959 {
18966 {
18968 {
18971 }
18977 }
18979 /* None of the regs is defined in the bb. */
18981 }
18983 /* Split lea instructions into a sequence of instructions
18984 which are executed on ALU to avoid AGU stalls.
18985 It is assumed that it is allowed to clobber flags register
18986 at lea position. */
18988 void
18990 {
19006 {
19009 }
19012 {
19015 }
19021 {
19022 /* Case r1 = r1 + ... */
19024 {
19025 /* If we have a case r1 = r1 + C * r2 then we
19026 should use multiplication which is very
19027 expensive. Assume cost model is wrong if we
19028 have such case here. */
19033 }
19034 else
19035 {
19036 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
19040 /* Use shift for scaling. */
19049 }
19050 }
19052 {
19055 }
19056 else
19057 {
19059 {
19062 }
19064 {
19067 }
19068 else
19069 {
19074 else
19075 {
19076 rtx tmp1;
19078 /* Find better operand for SET instruction, depending
19079 on which definition is farther from the insn. */
19082 else
19092 }
19095 }
19099 }
19100 }
19102 /* Return true if it is ok to optimize an ADD operation to LEA
19103 operation to avoid flag register consumation. For most processors,
19104 ADD is faster than LEA. For the processors like BONNELL, if the
19105 destination register of LEA holds an actual address which will be
19106 used soon, LEA is better and otherwise ADD is better. */
19108 bool
19110 {
19115 /* If a = b + c, (a!=b && a!=c), must use lea form. */
19123 }
19125 /* Return true if destination reg of SET_BODY is shift count of
19126 USE_BODY. */
19128 static bool
19130 {
19131 rtx set_dest;
19132 rtx shift_rtx;
19135 /* Retrieve destination of SET_BODY. */
19137 {
19146 use_body))
19151 }
19153 /* Retrieve shift count of USE_BODY. */
19155 {
19167 }
19175 {
19178 /* Return true if shift count is dest of SET_BODY. */
19180 {
19181 /* Add check since it can be invoked before register
19182 allocation in pre-reload schedule. */
19188 }
19189 }
19192 }
19194 /* Return true if destination reg of SET_INSN is shift count of
19195 USE_INSN. */
19197 bool
19199 {
19202 }
19204 /* Return TRUE or FALSE depending on whether the unary operator meets the
19205 appropriate constraints. */
19207 bool
19209 machine_mode,
19211 {
19212 /* If one of operands is memory, source and destination must match. */
19218 }
19220 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
19221 are ok, keeping in mind the possible movddup alternative. */
19223 bool
19225 {
19231 }
19233 /* Post-reload splitter for converting an SF or DFmode value in an
19234 SSE register into an unsigned SImode. */
19236 void
19238 {
19239 machine_mode vecmode;
19249 /* Load up the value into the low element. We must ensure that the other
19250 elements are valid floats -- zero is the easiest such value. */
19252 {
19255 else
19257 }
19258 else
19259 {
19264 else
19266 }
19286 else
19291 }
19293 /* Convert an unsigned DImode value into a DFmode, using only SSE.
19294 Expects the 64-bit DImode to be supplied in a pair of integral
19295 registers. Requires SSE2; will use SSE3 if available. For x86_32,
19296 -mfpmath=sse, !optimize_size only. */
19298 void
19300 {
19304 rtx x;
19310 {
19313 }
19314 else
19315 {
19319 }
19327 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
19330 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
19331 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
19332 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
19333 (0x1.0p84 + double(fp_value_hi_xmm)).
19334 Note these exponents differ by 32. */
19338 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
19339 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
19348 /* Add the upper and lower DFmode values together. */
19351 else
19352 {
19356 }
19359 }
19361 /* Not used, but eases macroization of patterns. */
19362 void
19364 {
19366 }
19368 /* Convert an unsigned SImode value into a DFmode. Only currently used
19369 for SSE, but applicable anywhere. */
19371 void
19373 {
19374 REAL_VALUE_TYPE TWO31r;
19389 }
19391 /* Convert a signed DImode value into a DFmode. Only used for SSE in
19392 32-bit mode; otherwise we have a direct convert instruction. */
19394 void
19396 {
19397 REAL_VALUE_TYPE TWO32r;
19415 }
19417 /* Convert an unsigned SImode value into a SFmode, using only SSE.
19418 For x86_32, -mfpmath=sse, !optimize_size only. */
19419 void
19421 {
19422 REAL_VALUE_TYPE ONE16r;
19441 }
19443 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
19444 a vector of unsigned ints VAL to vector of floats TARGET. */
19446 void
19448 {
19450 REAL_VALUE_TYPE TWO16r;
19457 else
19462 OPTAB_DIRECT);
19473 OPTAB_DIRECT);
19475 OPTAB_DIRECT);
19478 }
19480 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
19481 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
19482 This is done by doing just signed conversion if < 0x1p31, and otherwise by
19483 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
19485 rtx
19487 {
19488 REAL_VALUE_TYPE TWO31r;
19503 {
19509 }
19518 OPTAB_DIRECT);
19519 else
19520 {
19526 OPTAB_DIRECT);
19527 }
19530 }
19532 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
19533 then replicate the value for all elements of the vector
19534 register. */
19536 rtx
19538 {
19540 rtvec v;
19541 machine_mode scalar_mode;
19544 {
19577 }
19578 }
19580 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
19581 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
19582 for an SSE register. If VECT is true, then replicate the mask for
19583 all elements of the vector register. If INVERT is true, then create
19584 a mask excluding the sign bit. */
19586 rtx
19588 {
19590 wide_int w;
19594 {
19625 }
19632 /* Force this value into the low part of a fp vector constant. */
19641 }
19643 /* Generate code for floating point ABS or NEG. */
19645 void
19647 rtx operands[])
19648 {
19659 {
19665 }
19667 /* NEG and ABS performed with SSE use bitwise mask operations.
19668 Create the appropriate mask now. */
19671 else
19681 {
19683 rtvec par;
19688 else
19689 {
19692 }
19694 }
19695 else
19697 }
19699 /* Expand a copysign operation. Special case operand 0 being a constant. */
19701 void
19703 {
19717 else
19721 {
19728 {
19731 else
19732 {
19736 }
19737 }
19747 else
19751 }
19752 else
19753 {
19763 else
19767 }
19768 }
19770 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19771 be a constant, and so has already been expanded into a vector constant. */
19773 void
19775 {
19791 {
19794 }
19795 }
19797 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19798 so we have to do two masks. */
19800 void
19802 {
19817 {
19818 /* Shouldn't happen often (it's useless, obviously), but when it does
19819 we'd generate incorrect code if we continue below. */
19822 }
19825 {
19836 }
19837 else
19838 {
19840 {
19842 }
19844 {
19848 }
19852 {
19855 }
19857 {
19862 }
19864 }
19868 }
19870 /* Return TRUE or FALSE depending on whether the first SET in INSN
19871 has source and destination with matching CC modes, and that the
19872 CC mode is at least as constrained as REQ_MODE. */
19874 bool
19876 {
19877 rtx set;
19878 machine_mode set_mode;
19888 {
19898 /* FALLTHRU */
19902 /* FALLTHRU */
19906 /* FALLTHRU */
19921 }
19924 }
19926 /* Generate insn patterns to do an integer compare of OPERANDS. */
19928 static rtx
19930 {
19931 machine_mode cmpmode;
19937 /* This is very simple, but making the interface the same as in the
19938 FP case makes the rest of the code easier. */
19942 /* Return the test that should be put into the flags user, i.e.
19943 the bcc, scc, or cmov instruction. */
19945 }
19947 /* Figure out whether to use ordered or unordered fp comparisons.
19948 Return the appropriate mode to use. */
19950 machine_mode
19952 {
19953 /* ??? In order to make all comparisons reversible, we do all comparisons
19954 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19955 all forms trapping and nontrapping comparisons, we can make inequality
19956 comparisons trapping again, since it results in better code when using
19957 FCOM based compares. */
19959 }
19961 machine_mode
19963 {
19967 {
19970 }
19973 {
19974 /* Only zero flag is needed. */
19978 /* Codes needing carry flag. */
19981 /* Detect overflow checks. They need just the carry flag. */
19985 else
19990 /* Codes possibly doable only with sign flag when
19991 comparing against zero. */
19996 else
19997 /* For other cases Carry flag is not required. */
19999 /* Codes doable only with sign flag when comparing
20000 against zero, but we miss jump instruction for it
20001 so we need to use relational tests against overflow
20002 that thus needs to be zero. */
20007 else
20009 /* strcmp pattern do (use flags) and combine may ask us for proper
20010 mode. */
20015 }
20016 }
20018 /* Return the fixed registers used for condition codes. */
20020 static bool
20022 {
20026 }
20028 /* If two condition code modes are compatible, return a condition code
20029 mode which is compatible with both. Otherwise, return
20030 VOIDmode. */
20032 static machine_mode
20034 {
20051 {
20066 {
20081 }
20085 /* These are only compatible with themselves, which we already
20086 checked above. */
20088 }
20089 }
20092 /* Return a comparison we can do and that it is equivalent to
20093 swap_condition (code) apart possibly from orderedness.
20094 But, never change orderedness if TARGET_IEEE_FP, returning
20095 UNKNOWN in that case if necessary. */
20097 static enum rtx_code
20099 {
20101 {
20112 }
20113 }
20115 /* Return cost of comparison CODE using the best strategy for performance.
20116 All following functions do use number of instructions as a cost metrics.
20117 In future this should be tweaked to compute bytes for optimize_size and
20118 take into account performance of various instructions on various CPUs. */
20120 static int
20122 {
20125 /* The cost of code using bit-twiddling on %ah. */
20127 {
20150 }
20153 {
20160 }
20161 }
20163 /* Return strategy to use for floating-point. We assume that fcomi is always
20164 preferrable where available, since that is also true when looking at size
20165 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
20167 enum ix86_fpcmp_strategy
20169 {
20170 /* Do fcomi/sahf based test when profitable. */
20179 }
20181 /* Swap, force into registers, or otherwise massage the two operands
20182 to a fp comparison. The operands are updated in place; the new
20183 comparison code is returned. */
20185 static enum rtx_code
20187 {
20193 /* All of the unordered compare instructions only work on registers.
20194 The same is true of the fcomi compare instructions. The XFmode
20195 compare instructions require registers except when comparing
20196 against zero or when converting operand 1 from fixed point to
20197 floating point. */
20206 {
20209 }
20210 else
20211 {
20212 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
20213 things around if they appear profitable, otherwise force op0
20214 into a register. */
20220 {
20223 {
20226 }
20227 }
20233 {
20238 {
20241 }
20242 else
20244 }
20245 }
20247 /* Try to rearrange the comparison to make it cheaper. */
20251 {
20256 }
20261 }
20263 /* Convert comparison codes we use to represent FP comparison to integer
20264 code that will result in proper branch. Return UNKNOWN if no such code
20265 is available. */
20267 enum rtx_code
20269 {
20271 {
20294 }
20295 }
20297 /* Generate insn patterns to do a floating point compare of OPERANDS. */
20299 static rtx
20301 {
20308 /* Do fcomi/sahf based test when profitable. */
20310 {
20330 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
20337 /* In the unordered case, we have to check C2 for NaN's, which
20338 doesn't happen to work out to anything nice combination-wise.
20339 So do some bit twiddling on the value we've got in AH to come
20340 up with an appropriate set of condition codes. */
20344 {
20348 {
20351 }
20352 else
20353 {
20359 }
20364 {
20369 }
20370 else
20371 {
20374 }
20379 {
20382 }
20383 else
20384 {
20388 }
20393 {
20399 }
20400 else
20401 {
20404 }
20409 {
20414 }
20415 else
20416 {
20419 }
20424 {
20429 }
20430 else
20431 {
20434 }
20448 }
20453 }
20455 /* Return the test that should be put into the flags user, i.e.
20456 the bcc, scc, or cmov instruction. */
20459 const0_rtx);
20460 }
20462 static rtx
20464 {
20465 rtx ret;
20471 {
20474 }
20475 else
20479 }
20481 void
20483 {
20485 rtx tmp;
20488 {
20495 simple:
20499 pc_rtx);
20507 /* Expand DImode branch into multiple compare+branch. */
20508 {
20512 machine_mode submode;
20515 {
20518 }
20525 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
20526 avoid two branches. This costs one extra insn, so disable when
20527 optimizing for size. */
20532 {
20550 }
20552 /* Otherwise, if we are doing less-than or greater-or-equal-than,
20553 op1 is a constant and the low word is zero, then we can just
20554 examine the high word. Similarly for low word -1 and
20555 less-or-equal-than or greater-than. */
20559 {
20562 {
20565 }
20569 {
20572 }
20576 }
20578 /* Otherwise, we need two or three jumps. */
20587 {
20601 }
20603 /*
20604 * a < b =>
20605 * if (hi(a) < hi(b)) goto true;
20606 * if (hi(a) > hi(b)) goto false;
20607 * if (lo(a) < lo(b)) goto true;
20608 * false:
20609 */
20621 }
20626 }
20627 }
20629 /* Split branch based on floating point condition. */
20630 void
20633 {
20634 rtx condition;
20635 rtx i;
20638 {
20641 }
20644 tmp);
20652 }
20654 void
20656 {
20657 rtx ret;
20664 }
20666 /* Expand comparison setting or clearing carry flag. Return true when
20667 successful and set pop for the operation. */
20668 static bool
20670 {
20671 machine_mode mode =
20674 /* Do not handle double-mode compares that go through special path. */
20679 {
20680 rtx compare_op;
20685 /* Shortcut: following common codes never translate
20686 into carry flag compares. */
20691 /* These comparisons require zero flag; swap operands so they won't. */
20694 {
20697 }
20699 /* Try to expand the comparison and verify that we end up with
20700 carry flag based comparison. This fails to be true only when
20701 we decide to expand comparison using arithmetic that is not
20702 too common scenario. */
20711 else
20720 }
20726 {
20731 /* Convert a==0 into (unsigned)a<1. */
20740 /* Convert a>b into b<a or a>=b-1. */
20744 {
20746 /* Bail out on overflow. We still can swap operands but that
20747 would force loading of the constant into register. */
20752 }
20753 else
20754 {
20757 }
20760 /* Convert a>=0 into (unsigned)a<0x80000000. */
20778 }
20779 /* Swapping operands may cause constant to appear as first operand. */
20781 {
20785 }
20789 }
20791 bool
20793 {
20796 rtx compare_op;
20818 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20819 HImode insns, we'd be swallowed in word prefix ops. */
20825 {
20829 HOST_WIDE_INT diff;
20832 /* Sign bit compares are better done using shifts than we do by using
20833 sbb. */
20836 {
20837 /* Detect overlap between destination and compare sources. */
20841 {
20842 rtx flags;
20851 {
20853 compare_code
20855 }
20857 /* To simplify rest of code, restrict to the GEU case. */
20859 {
20863 }
20864 else
20865 {
20868 reverse_condition_maybe_unordered
20870 else
20873 }
20882 else
20885 }
20886 else
20887 {
20890 else
20891 {
20894 }
20896 }
20899 {
20900 /*
20901 * cmpl op0,op1
20902 * sbbl dest,dest
20903 * [addl dest, ct]
20904 *
20905 * Size 5 - 8.
20906 */
20911 }
20913 {
20914 /*
20915 * cmpl op0,op1
20916 * sbbl dest,dest
20917 * orl $ct, dest
20918 *
20919 * Size 8.
20920 */
20924 }
20926 {
20927 /*
20928 * cmpl op0,op1
20929 * sbbl dest,dest
20930 * notl dest
20931 * [addl dest, cf]
20932 *
20933 * Size 8 - 11.
20934 */
20940 }
20941 else
20942 {
20943 /*
20944 * cmpl op0,op1
20945 * sbbl dest,dest
20946 * [notl dest]
20947 * andl cf - ct, dest
20948 * [addl dest, ct]
20949 *
20950 * Size 8 - 11.
20951 */
20954 {
20958 }
20968 }
20974 }
20977 {
20982 {
20985 /* We may be reversing unordered compare to normal compare, that
20986 is not valid in general (we may convert non-trapping condition
20987 to trapping one), however on i386 we currently emit all
20988 comparisons unordered. */
20990 }
20991 else
20994 {
20998 }
20999 }
21004 {
21009 {
21014 }
21015 }
21017 /* Optimize dest = (op0 < 0) ? -1 : cf. */
21021 {
21022 /* If lea code below could be used, only optimize
21023 if it results in a 2 insn sequence. */
21029 {
21030 /*
21031 * notl op1 (if necessary)
21032 * sarl $31, op1
21033 * orl cf, op1
21034 */
21036 {
21040 }
21051 }
21052 }
21060 {
21061 /*
21062 * xorl dest,dest
21063 * cmpl op1,op2
21064 * setcc dest
21065 * lea cf(dest*(ct-cf)),dest
21066 *
21067 * Size 14.
21068 *
21069 * This also catches the degenerate setcc-only case.
21070 */
21072 rtx tmp;
21078 /* On x86_64 the lea instruction operates on Pmode, so we need
21079 to get arithmetics done in proper mode to match. */
21082 else
21083 {
21084 rtx out1;
21087 nops++;
21089 {
21091 nops++;
21092 }
21093 }
21095 {
21097 nops++;
21098 }
21100 {
21103 else
21105 }
21110 }
21112 /*
21113 * General case: Jumpful:
21114 * xorl dest,dest cmpl op1, op2
21115 * cmpl op1, op2 movl ct, dest
21116 * setcc dest jcc 1f
21117 * decl dest movl cf, dest
21118 * andl (cf-ct),dest 1:
21119 * addl ct,dest
21120 *
21121 * Size 20. Size 14.
21122 *
21123 * This is reasonably steep, but branch mispredict costs are
21124 * high on modern cpus, so consider failing only if optimizing
21125 * for space.
21126 */
21131 {
21133 {
21138 {
21141 /* We may be reversing unordered compare to normal compare,
21142 that is not valid in general (we may convert non-trapping
21143 condition to trapping one), however on i386 we currently
21144 emit all comparisons unordered. */
21146 }
21147 else
21148 {
21152 }
21155 {
21159 }
21160 }
21163 {
21164 /* notl op1 (if needed)
21165 sarl $31, op1
21166 andl (cf-ct), op1
21167 addl ct, op1
21169 For x < 0 (resp. x <= -1) there will be no notl,
21170 so if possible swap the constants to get rid of the
21171 complement.
21172 True/false will be -1/0 while code below (store flag
21173 followed by decrement) is 0/-1, so the constants need
21174 to be exchanged once more. */
21177 {
21180 }
21181 else
21185 }
21186 else
21187 {
21191 constm1_rtx,
21193 }
21205 }
21206 }
21209 {
21210 /* Try a few things more with specific constants and a variable. */
21212 optab op;
21218 /* If one of the two operands is an interesting constant, load a
21219 constant with the above and mask it in with a logical operation. */
21222 {
21228 else
21230 }
21232 {
21238 else
21240 }
21241 else
21248 /* Recurse to get the constant loaded. */
21252 /* Mask in the interesting variable. */
21254 OPTAB_WIDEN);
21259 }
21261 /*
21262 * For comparison with above,
21263 *
21264 * movl cf,dest
21265 * movl ct,tmp
21266 * cmpl op1,op2
21267 * cmovcc tmp,dest
21268 *
21269 * Size 15.
21270 */
21292 }
21294 /* Swap, force into registers, or otherwise massage the two operands
21295 to an sse comparison with a mask result. Thus we differ a bit from
21296 ix86_prepare_fp_compare_args which expects to produce a flags result.
21298 The DEST operand exists to help determine whether to commute commutative
21299 operators. The POP0/POP1 operands are updated in place. The new
21300 comparison code is returned, or UNKNOWN if not implementable. */
21302 static enum rtx_code
21305 {
21307 {
21310 /* AVX supports all the needed comparisons. */
21313 /* We have no LTGT as an operator. We could implement it with
21314 NE & ORDERED, but this requires an extra temporary. It's
21315 not clear that it's worth it. */
21322 /* These are supported directly. */
21329 /* AVX has 3 operand comparisons, no need to swap anything. */
21332 /* For commutative operators, try to canonicalize the destination
21333 operand to be first in the comparison - this helps reload to
21334 avoid extra moves. */
21337 /* FALLTHRU */
21343 /* These are not supported directly before AVX, and furthermore
21344 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
21345 comparison operands to transform into something that is
21346 supported. */
21353 }
21356 }
21358 /* Detect conditional moves that exactly match min/max operational
21359 semantics. Note that this is IEEE safe, as long as we don't
21360 interchange the operands.
21362 Returns FALSE if this conditional move doesn't match a MIN/MAX,
21363 and TRUE if the operation is successful and instructions are emitted. */
21365 static bool
21368 {
21369 machine_mode mode;
21371 rtx tmp;
21374 ;
21377 else
21384 else
21389 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
21390 but MODE may be a vector mode and thus not appropriate. */
21392 {
21394 rtvec v;
21399 }
21400 else
21401 {
21404 }
21408 }
21410 /* Expand an sse vector comparison. Return the register with the result. */
21412 static rtx
21415 {
21419 /* In general case result of comparison can differ from operands' type. */
21420 machine_mode cmp_mode;
21422 /* In AVX512F the result of comparison is an integer mask. */
21424 rtx x;
21427 {
21432 }
21433 else
21446 /* Compare patterns for int modes are unspec in AVX512F only. */
21448 {
21452 {
21469 }
21472 {
21475 }
21476 }
21480 {
21483 }
21484 else
21488 }
21490 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
21491 operations. This is used for both scalar and vector conditional moves. */
21493 static void
21495 {
21499 /* In AVX512F the result of comparison is an integer mask. */
21507 {
21509 }
21512 {
21516 }
21519 {
21524 }
21527 {
21531 }
21534 {
21541 op_true,
21542 op_false)));
21543 }
21544 else
21545 {
21555 {
21569 {
21576 }
21591 {
21598 }
21622 }
21625 {
21629 }
21630 else
21631 {
21637 else
21649 }
21650 }
21651 }
21653 /* Expand a floating-point conditional move. Return true if successful. */
21655 bool
21657 {
21665 {
21666 machine_mode cmode;
21668 /* Since we've no cmove for sse registers, don't force bad register
21669 allocation just to gain access to it. Deny movcc when the
21670 comparison mode doesn't match the move mode. */
21689 }
21696 /* The floating point conditional move instructions don't directly
21697 support conditions resulting from a signed integer comparison. */
21701 {
21706 }
21713 }
21715 /* Expand a floating-point vector conditional move; a vcond operation
21716 rather than a movcc operation. */
21718 bool
21720 {
21722 rtx cmp;
21727 {
21728 rtx temp;
21730 {
21747 }
21749 OPTAB_DIRECT);
21752 }
21762 }
21764 /* Expand a signed/unsigned integral vector conditional move. */
21766 bool
21768 {
21778 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21779 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21788 {
21792 {
21798 }
21801 {
21807 }
21808 }
21817 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21821 ;
21822 else
21823 {
21824 /* Canonicalize the comparison to EQ, GT, GTU. */
21826 {
21843 /* FALLTHRU */
21853 }
21855 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21857 {
21859 {
21861 /* SSE4.1 supports EQ. */
21868 /* SSE4.2 supports GT/GTU. */
21875 }
21876 }
21878 /* Unsigned parallel compare is not supported by the hardware.
21879 Play some tricks to turn this into a signed comparison
21880 against 0. */
21882 {
21886 {
21893 {
21898 {
21907 }
21908 /* Subtract (-(INT MAX) - 1) from both operands to make
21909 them signed. */
21920 }
21929 /* Perform a parallel unsigned saturating subtraction. */
21941 }
21942 }
21943 }
21945 /* Allow the comparison to be done in one mode, but the movcc to
21946 happen in another mode. */
21948 {
21951 }
21952 else
21953 {
21959 }
21964 }
21966 /* AVX512F does support 64-byte integer vector operations,
21967 thus the longest vector we are faced with is V64QImode. */
21968 #define MAX_VECT_LEN 64
21970 struct expand_vec_perm_d
21971 {
21974 machine_mode vmode;
21978 };
21980 static bool
21983 {
21984 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21985 expander, so args are either in d, or in op0, op1 etc. */
21991 {
22022 {
22025 }
22029 {
22032 }
22036 {
22039 }
22055 {
22058 }
22062 {
22065 }
22069 {
22072 }
22076 }
22081 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
22082 expander, so args are either in d, or in op0, op1 etc. */
22084 {
22092 }
22096 }
22098 /* Expand a variable vector permutation. */
22100 void
22102 {
22113 /* Number of elements in the vector. */
22122 {
22124 {
22125 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
22126 an constant shuffle operand. With a tiny bit of effort we can
22127 use VPERMD instead. A re-interpretation stall for V4DFmode is
22128 unfortunate but there's no avoiding it.
22129 Similarly for V16HImode we don't have instructions for variable
22130 shuffling, while for V32QImode we can use after preparing suitable
22131 masks vpshufb; vpshufb; vpermq; vpor. */
22134 {
22138 }
22139 else
22140 {
22144 }
22147 /* Replicate the low bits of the V4DImode mask into V8SImode:
22148 mask = { A B C D }
22149 t1 = { A A B B C C D D }. */
22157 else
22160 /* Multiply the shuffle indicies by two. */
22162 OPTAB_DIRECT);
22164 /* Add one to the odd shuffle indicies:
22165 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
22167 {
22170 }
22174 OPTAB_DIRECT);
22176 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
22181 }
22184 {
22186 /* The VPERMD and VPERMPS instructions already properly ignore
22187 the high bits of the shuffle elements. No need for us to
22188 perform an AND ourselves. */
22190 {
22195 }
22196 else
22197 {
22203 }
22210 else
22211 {
22217 }
22221 /* By combining the two 128-bit input vectors into one 256-bit
22222 input vector, we can use VPERMD and VPERMPS for the full
22223 two-operand shuffle. */
22255 /* From mask create two adjusted masks, which contain the same
22256 bits as mask in the low 7 bits of each vector element.
22257 The first mask will have the most significant bit clear
22258 if it requests element from the same 128-bit lane
22259 and MSB set if it requests element from the other 128-bit lane.
22260 The second mask will have the opposite values of the MSB,
22261 and additionally will have its 128-bit lanes swapped.
22262 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
22263 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
22264 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
22265 stands for other 12 bytes. */
22266 /* The bit whether element is from the same lane or the other
22267 lane is bit 4, so shift it up by 3 to the MSB position. */
22271 /* Clear MSB bits from the mask just in case it had them set. */
22273 /* After this t1 will have MSB set for elements from other lane. */
22275 /* Clear bits other than MSB. */
22277 /* Or in the lower bits from mask into t3. */
22279 /* And invert MSB bits in t1, so MSB is set for elements from the same
22280 lane. */
22282 /* Swap 128-bit lanes in t3. */
22287 /* And or in the lower bits from mask into t1. */
22290 {
22291 /* Each of these shuffles will put 0s in places where
22292 element from the other 128-bit lane is needed, otherwise
22293 will shuffle in the requested value. */
22297 /* For t3 the 128-bit lanes are swapped again. */
22302 /* And oring both together leads to the result. */
22309 }
22312 /* Similarly to the above one_operand_shuffle code,
22313 just for repeated twice for each operand. merge_two:
22314 code will merge the two results together. */
22338 }
22339 }
22342 {
22343 /* The XOP VPPERM insn supports three inputs. By ignoring the
22344 one_operand_shuffle special case, we avoid creating another
22345 set of constant vectors in memory. */
22348 /* mask = mask & {2*w-1, ...} */
22350 }
22351 else
22352 {
22353 /* mask = mask & {w-1, ...} */
22355 }
22363 /* For non-QImode operations, convert the word permutation control
22364 into a byte permutation control. */
22366 {
22371 /* Convert mask to vector of chars. */
22374 /* Replicate each of the input bytes into byte positions:
22375 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
22376 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
22377 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
22384 else
22387 /* Convert it into the byte positions by doing
22388 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
22394 }
22396 /* The actual shuffle operations all operate on V16QImode. */
22401 {
22408 }
22410 {
22417 }
22418 else
22419 {
22423 /* Shuffle the two input vectors independently. */
22429 merge_two:
22430 /* Then merge them together. The key is whether any given control
22431 element contained a bit set that indicates the second word. */
22435 {
22436 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
22437 more shuffle to convert the V2DI input mask into a V4SI
22438 input mask. At which point the masking that expand_int_vcond
22439 will work as desired. */
22447 }
22469 }
22470 }
22472 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
22473 true if we should do zero extension, else sign extension. HIGH_P is
22474 true if we want the N/2 high elements, else the low elements. */
22476 void
22478 {
22480 rtx tmp;
22483 {
22489 {
22493 else
22496 extract
22502 else
22505 extract
22511 else
22514 extract
22520 else
22523 extract
22529 else
22532 extract
22538 else
22541 extract
22547 else
22553 else
22559 else
22564 }
22567 {
22570 }
22572 {
22573 /* Shift higher 8 bytes to lower 8 bytes. */
22578 }
22579 else
22583 }
22584 else
22585 {
22589 {
22593 else
22599 else
22605 else
22610 }
22614 else
22621 }
22622 }
22624 /* Expand conditional increment or decrement using adb/sbb instructions.
22625 The default case using setcc followed by the conditional move can be
22626 done by generic code. */
22627 bool
22629 {
22631 rtx flags;
22633 rtx compare_op;
22636 machine_mode mode;
22651 {
22654 }
22657 {
22661 reverse_condition_maybe_unordered
22663 else
22665 }
22669 /* Construct either adc or sbb insn. */
22671 {
22673 {
22688 }
22689 }
22690 else
22691 {
22693 {
22708 }
22709 }
22713 }
22716 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22717 but works for floating pointer parameters and nonoffsetable memories.
22718 For pushes, it returns just stack offsets; the values will be saved
22719 in the right order. Maximally three parts are generated. */
22721 static int
22723 {
22728 else
22734 /* Optimize constant pool reference to immediates. This is used by fp
22735 moves, that force all constants to memory to allow combining. */
22737 {
22741 }
22744 {
22745 /* The only non-offsetable memories we handle are pushes. */
22754 }
22757 {
22759 /* Caution: if we looked through a constant pool memory above,
22760 the operand may actually have a different mode now. That's
22761 ok, since we want to pun this all the way back to an integer. */
22765 }
22768 {
22771 else
22772 {
22776 {
22780 }
22782 {
22787 }
22789 {
22790 REAL_VALUE_TYPE r;
22795 {
22802 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22803 long double may not be 80-bit. */
22812 }
22815 }
22816 else
22818 }
22819 }
22820 else
22821 {
22825 {
22828 {
22832 }
22834 {
22838 }
22840 {
22841 REAL_VALUE_TYPE r;
22847 /* real_to_target puts 32-bit pieces in each long. */
22849 gen_int_mode
22852 DImode);
22856 else
22858 gen_int_mode
22861 DImode);
22862 }
22863 else
22865 }
22866 }
22869 }
22871 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22872 Return false when normal moves are needed; true when all required
22873 insns have been emitted. Operands 2-4 contain the input values
22874 int the correct order; operands 5-7 contain the output values. */
22876 void
22878 {
22886 /* The DFmode expanders may ask us to move double.
22887 For 64bit target this is single move. By hiding the fact
22888 here we simplify i386.md splitters. */
22890 {
22891 /* Optimize constant pool reference to immediates. This is used by
22892 fp moves, that force all constants to memory to allow combining. */
22899 {
22902 }
22903 else
22908 }
22910 /* The only non-offsettable memory we handle is push. */
22913 else
22920 /* When emitting push, take care for source operands on the stack. */
22923 {
22926 /* Compensate for the stack decrement by 4. */
22931 /* src_base refers to the stack pointer and is
22932 automatically decreased by emitted push. */
22936 }
22938 /* We need to do copy in the right order in case an address register
22939 of the source overlaps the destination. */
22941 {
22942 rtx tmp;
22945 {
22949 collisions++;
22950 }
22952 /* Collision in the middle part can be handled by reordering. */
22954 {
22957 }
22961 {
22963 {
22966 }
22967 else
22968 {
22971 }
22972 }
22974 /* If there are more collisions, we can't handle it by reordering.
22975 Do an lea to the last part and use only one colliding move. */
22977 {
22984 /* Handle the case when the last part isn't valid for lea.
22985 Happens in 64-bit mode storing the 12-byte XFmode. */
22991 {
22996 {
22997 /* It is not valid to use %gs: or %fs: in
22998 lea though, so we need to remove it from the
22999 address used for lea and add it to each individual
23000 memory loads instead. */
23004 {
23006 {
23012 {
23016 }
23017 }
23021 }
23023 }
23024 }
23030 {
23035 }
23036 }
23037 }
23040 {
23042 {
23044 {
23049 }
23051 {
23054 }
23055 }
23056 else
23057 {
23058 /* In 64bit mode we don't have 32bit push available. In case this is
23059 register, it is OK - we will just use larger counterpart. We also
23060 retype memory - these comes from attempt to avoid REX prefix on
23061 moving of second half of TFmode value. */
23063 {
23065 {
23076 }
23080 }
23081 }
23085 }
23087 /* Choose correct order to not overwrite the source before it is copied. */
23097 {
23099 {
23102 }
23103 }
23104 else
23105 {
23107 {
23110 }
23111 }
23113 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
23115 {
23124 }
23130 }
23132 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
23133 left shift by a constant, either using a single shift or
23134 a sequence of add instructions. */
23136 static void
23138 {
23144 {
23148 }
23149 else
23150 {
23153 }
23154 }
23156 void
23158 {
23167 {
23172 {
23178 }
23179 else
23180 {
23188 }
23190 }
23197 {
23198 /* Assuming we've chosen a QImode capable registers, then 1 << N
23199 can be done with two 32/64-bit shifts, no branches, no cmoves. */
23201 {
23217 }
23219 /* Otherwise, we can get the same results by manually performing
23220 a bit extract operation on bit 5/6, and then performing the two
23221 shifts. The two methods of getting 0/1 into low/high are exactly
23222 the same size. Avoiding the shift in the bit extract case helps
23223 pentium4 a bit; no one else seems to care much either way. */
23224 else
23225 {
23226 machine_mode half_mode;
23230 HOST_WIDE_INT bits;
23231 rtx x;
23234 {
23240 }
23241 else
23242 {
23248 }
23252 else
23260 }
23265 }
23268 {
23269 /* For -1 << N, we can avoid the shld instruction, because we
23270 know that we're shifting 0...31/63 ones into a -1. */
23274 else
23276 }
23277 else
23278 {
23286 }
23291 {
23297 }
23298 else
23299 {
23304 }
23305 }
23307 void
23309 {
23319 {
23324 {
23330 }
23332 {
23341 }
23342 else
23343 {
23351 }
23352 }
23353 else
23354 {
23366 {
23374 scratch));
23375 }
23376 else
23377 {
23382 }
23383 }
23384 }
23386 void
23388 {
23398 {
23403 {
23410 }
23411 else
23412 {
23420 }
23421 }
23422 else
23423 {
23435 {
23441 scratch));
23442 }
23443 else
23444 {
23449 }
23450 }
23451 }
23453 /* Predict just emitted jump instruction to be taken with probability PROB. */
23454 static void
23456 {
23460 }
23462 /* Helper function for the string operations below. Dest VARIABLE whether
23463 it is aligned to VALUE bytes. If true, jump to the label. */
23466 {
23471 else
23477 else
23480 }
23482 /* Adjust COUNTER by the VALUE. */
23483 static void
23485 {
23490 }
23492 /* Zero extend possibly SImode EXP to Pmode register. */
23493 rtx
23495 {
23497 }
23499 /* Divide COUNTREG by SCALE. */
23500 static rtx
23502 {
23503 rtx sc;
23515 }
23517 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
23518 DImode for constant loop counts. */
23520 static machine_mode
23522 {
23530 }
23532 /* Copy the address to a Pmode register. This is used for x32 to
23533 truncate DImode TLS address to a SImode register. */
23535 static rtx
23537 {
23538 rtx reg;
23540 {
23544 }
23545 else
23546 {
23551 }
23552 }
23554 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
23555 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
23556 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
23557 memory by VALUE (supposed to be in MODE).
23559 The size is rounded down to whole number of chunk size moved at once.
23560 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
23563 static void
23568 {
23575 rtx size;
23584 /* Those two should combine. */
23586 {
23590 }
23597 /* This assert could be relaxed - in this case we'll need to compute
23598 smallest power of two, containing in PIECE_SIZE_N and pass it to
23599 offset_address. */
23605 {
23609 /* When unrolling for chips that reorder memory reads and writes,
23610 we can save registers by using single temporary.
23611 Also using 4 temporaries is overkill in 32bit mode. */
23613 {
23615 {
23617 {
23618 destmem =
23620 srcmem =
23622 }
23624 }
23625 }
23626 else
23627 {
23631 {
23634 {
23635 srcmem =
23637 }
23639 }
23641 {
23643 {
23644 destmem =
23646 }
23648 }
23649 }
23650 }
23651 else
23653 {
23655 destmem =
23658 }
23668 {
23674 else
23676 }
23677 else
23685 {
23690 }
23692 }
23694 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
23695 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
23696 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
23697 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
23698 ORIG_VALUE is the original value passed to memset to fill the memory with.
23699 Other arguments have same meaning as for previous function. */
23701 static void
23704 rtx count,
23706 {
23707 rtx destexp;
23708 rtx srcexp;
23709 rtx countreg;
23710 HOST_WIDE_INT rounded_count;
23712 /* If possible, it is shorter to use rep movs.
23713 TODO: Maybe it is better to move this logic to decide_alg. */
23724 {
23728 }
23729 else
23732 {
23737 }
23742 {
23745 }
23746 else
23747 {
23751 {
23755 }
23756 else
23759 {
23764 }
23765 else
23766 {
23769 }
23772 }
23773 }
23775 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23776 DESTMEM.
23777 SRC is passed by pointer to be updated on return.
23778 Return value is updated DST. */
23779 static rtx
23781 HOST_WIDE_INT size_to_move)
23782 {
23785 machine_mode move_mode;
23788 /* Find the widest mode in which we could perform moves.
23789 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23790 it until move of such size is supported. */
23795 {
23799 }
23801 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23802 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23804 {
23809 {
23813 }
23814 }
23820 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23824 {
23825 /* We move from memory to memory, so we'll need to do it via
23826 a temporary register. */
23837 piece_size);
23839 piece_size);
23840 }
23842 /* Update DST and SRC rtx. */
23845 }
23847 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23848 static void
23851 {
23854 {
23859 /* For now MAX_SIZE should be a power of 2. This assert could be
23860 relaxed, but it'll require a bit more complicated epilogue
23861 expanding. */
23864 {
23867 }
23869 }
23871 {
23877 }
23879 /* When there are stringops, we can cheaply increase dest and src pointers.
23880 Otherwise we save code size by maintaining offset (zero is readily
23881 available from preceding rep operation) and using x86 addressing modes.
23882 */
23884 {
23886 {
23893 }
23895 {
23902 }
23904 {
23911 }
23912 }
23913 else
23914 {
23916 rtx tmp;
23919 {
23930 }
23932 {
23945 }
23947 {
23956 }
23957 }
23958 }
23960 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23961 with value PROMOTED_VAL.
23962 SRC is passed by pointer to be updated on return.
23963 Return value is updated DST. */
23964 static rtx
23966 HOST_WIDE_INT size_to_move)
23967 {
23970 machine_mode move_mode;
23973 /* Find the widest mode in which we could perform moves.
23974 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23975 it until move of such size is supported. */
23980 {
23983 }
23990 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23994 {
23996 {
23999 piece_size);
24001 }
24009 piece_size);
24010 }
24012 /* Update DST rtx. */
24014 }
24015 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
24016 static void
24019 {
24020 count =
24026 }
24028 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
24029 static void
24032 {
24033 rtx dest;
24036 {
24041 /* For now MAX_SIZE should be a power of 2. This assert could be
24042 relaxed, but it'll require a bit more complicated epilogue
24043 expanding. */
24046 {
24048 {
24051 else
24053 }
24054 }
24056 }
24058 {
24061 }
24063 {
24066 {
24071 }
24072 else
24073 {
24082 }
24085 }
24087 {
24090 {
24093 }
24094 else
24095 {
24100 }
24103 }
24105 {
24111 }
24113 {
24119 }
24121 {
24127 }
24128 }
24130 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
24131 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
24132 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
24133 ignored.
24134 Return value is updated DESTMEM. */
24135 static rtx
24140 {
24143 {
24145 {
24148 {
24151 else
24153 }
24154 else
24160 }
24161 }
24163 }
24165 /* Test if COUNT&SIZE is nonzero and if so, expand movme
24166 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
24167 and jump to DONE_LABEL. */
24168 static void
24174 {
24177 rtx modesize;
24180 /* If we do not have vector value to copy, we must reduce size. */
24182 {
24184 {
24189 }
24190 else
24192 }
24193 else
24194 {
24195 /* Choose appropriate vector mode. */
24201 }
24206 {
24209 else
24210 {
24213 }
24215 }
24221 {
24225 }
24227 {
24230 else
24231 {
24234 }
24236 }
24242 }
24244 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
24245 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
24246 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
24247 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
24248 DONE_LABEL is a label after the whole copying sequence. The label is created
24249 on demand if *DONE_LABEL is NULL.
24250 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
24251 bounds after the initial copies.
24253 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
24254 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
24255 we will dispatch to a library call for large blocks.
24257 In pseudocode we do:
24259 if (COUNT < SIZE)
24260 {
24261 Assume that SIZE is 4. Bigger sizes are handled analogously
24262 if (COUNT & 4)
24263 {
24264 copy 4 bytes from SRCPTR to DESTPTR
24265 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
24266 goto done_label
24267 }
24268 if (!COUNT)
24269 goto done_label;
24270 copy 1 byte from SRCPTR to DESTPTR
24271 if (COUNT & 2)
24272 {
24273 copy 2 bytes from SRCPTR to DESTPTR
24274 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
24275 }
24276 }
24277 else
24278 {
24279 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
24280 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
24282 OLD_DESPTR = DESTPTR;
24283 Align DESTPTR up to DESIRED_ALIGN
24284 SRCPTR += DESTPTR - OLD_DESTPTR
24285 COUNT -= DEST_PTR - OLD_DESTPTR
24286 if (DYNAMIC_CHECK)
24287 Round COUNT down to multiple of SIZE
24288 << optional caller supplied zero size guard is here >>
24289 << optional caller suppplied dynamic check is here >>
24290 << caller supplied main copy loop is here >>
24291 }
24292 done_label:
24293 */
24294 static void
24297 machine_mode mode,
24307 {
24310 rtx modesize;
24312 rtx mode_value;
24314 /* Chose proper value to copy. */
24317 else
24321 /* See if block is big or small, handle small blocks. */
24323 {
24334 /* Handle sizes > 3. */
24341 /* Nothing to copy? Jump to DONE_LABEL if so */
24345 /* Do a byte copy. */
24349 else
24350 {
24353 }
24355 /* Handle sizes 2 and 3. */
24362 else
24363 {
24368 }
24374 }
24375 else
24379 /* Start memcpy for COUNT >= SIZE. */
24381 {
24384 }
24386 /* Copy first desired_align bytes. */
24392 {
24395 else
24396 {
24399 }
24402 }
24405 /* Copy last SIZE bytes. */
24412 else
24413 {
24419 }
24421 {
24425 else
24426 {
24429 }
24430 }
24432 /* Align destination. */
24434 {
24438 /* Align destptr up, place it to new register. */
24447 /* See how many bytes we skipped. */
24451 /* Adjust srcptr and count. */
24457 /* We copied at most size + prolog_size. */
24460 else
24463 /* Our loops always round down the bock size, but for dispatch to library
24464 we need precise value. */
24468 }
24469 else
24470 {
24472 /* Decrease count, so we won't end up copying last word twice. */
24476 else
24480 }
24481 }
24484 /* This function is like the previous one, except here we know how many bytes
24485 need to be copied. That allows us to update alignment not only of DST, which
24486 is returned, but also of SRC, which is passed as a pointer for that
24487 reason. */
24488 static rtx
24493 {
24501 {
24505 }
24510 {
24512 {
24514 {
24517 else
24519 }
24520 else
24523 }
24524 }
24531 {
24537 {
24540 {
24544 }
24549 }
24553 }
24556 }
24558 /* Return true if ALG can be used in current context.
24559 Assume we expand memset if MEMSET is true. */
24560 static bool
24562 {
24567 /* Algorithms using the rep prefix want at least edi and ecx;
24568 additionally, memset wants eax and memcpy wants esi. Don't
24569 consider such algorithms if the user has appropriated those
24570 registers for their own purposes. */
24577 }
24579 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
24580 static enum stringop_alg
24584 {
24595 /* Even if the string operation call is cold, we still might spend a lot
24596 of time processing large blocks. */
24602 else
24608 else
24611 /* See maximal size for user defined algorithm. */
24613 {
24620 }
24622 /* If expected size is not known but max size is small enough
24623 so inline version is a win, set expected size into
24624 the range. */
24629 /* If user specified the algorithm, honnor it if possible. */
24633 /* rep; movq or rep; movl is the smallest variant. */
24635 {
24640 else
24643 }
24644 /* Very tiny blocks are best handled via the loop, REP is expensive to
24645 setup. */
24649 {
24653 {
24654 /* We get here if the algorithms that were not libcall-based
24655 were rep-prefix based and we are unable to use rep prefixes
24656 based on global register usage. Break out of the loop and
24657 use the heuristic below. */
24661 {
24665 {
24668 }
24669 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
24670 last non-libcall inline algorithm. */
24672 {
24673 /* When the current size is best to be copied by a libcall,
24674 but we are still forced to inline, run the heuristic below
24675 that will pick code for medium sized blocks. */
24677 {
24680 }
24683 }
24685 {
24688 }
24689 }
24690 }
24691 }
24692 /* When asked to inline the call anyway, try to pick meaningful choice.
24693 We look for maximal size of block that is faster to copy by hand and
24694 take blocks of at most of that size guessing that average size will
24695 be roughly half of the block.
24697 If this turns out to be bad, we might simply specify the preferred
24698 choice in ix86_costs. */
24702 {
24705 /* If there aren't any usable algorithms, then recursing on
24706 smaller sizes isn't going to find anything. Just return the
24707 simple byte-at-a-time copy loop. */
24709 {
24710 /* Pick something reasonable. */
24714 }
24722 else
24725 }
24728 }
24730 /* Decide on alignment. We know that the operand is already aligned to ALIGN
24731 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
24732 static int
24736 machine_mode move_mode)
24737 {
24748 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
24749 copying whole cacheline at once. */
24762 }
24765 /* Helper function for memcpy. For QImode value 0xXY produce
24766 0xXYXYXYXY of wide specified by MODE. This is essentially
24767 a * 0x10101010, but we can do slightly better than
24768 synth_mult by unwinding the sequence by hand on CPUs with
24769 slow multiply. */
24770 static rtx
24772 {
24774 rtx tmp;
24781 {
24789 }
24798 nops--;
24803 {
24807 OPTAB_DIRECT);
24808 }
24809 else
24810 {
24816 else
24818 else
24819 {
24822 reg =
24824 }
24834 }
24835 }
24837 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24838 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24839 alignment from ALIGN to DESIRED_ALIGN. */
24840 static rtx
24843 {
24844 rtx promoted_val;
24853 else
24857 }
24859 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24860 operations when profitable. The code depends upon architecture, block size
24861 and alignment, but always has one of the following overall structures:
24863 Aligned move sequence:
24865 1) Prologue guard: Conditional that jumps up to epilogues for small
24866 blocks that can be handled by epilogue alone. This is faster
24867 but also needed for correctness, since prologue assume the block
24868 is larger than the desired alignment.
24870 Optional dynamic check for size and libcall for large
24871 blocks is emitted here too, with -minline-stringops-dynamically.
24873 2) Prologue: copy first few bytes in order to get destination
24874 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24875 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24876 copied. We emit either a jump tree on power of two sized
24877 blocks, or a byte loop.
24879 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24880 with specified algorithm.
24882 4) Epilogue: code copying tail of the block that is too small to be
24883 handled by main body (or up to size guarded by prologue guard).
24885 Misaligned move sequence
24887 1) missaligned move prologue/epilogue containing:
24888 a) Prologue handling small memory blocks and jumping to done_label
24889 (skipped if blocks are known to be large enough)
24890 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24891 needed by single possibly misaligned move
24892 (skipped if alignment is not needed)
24893 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24895 2) Zero size guard dispatching to done_label, if needed
24897 3) dispatch to library call, if needed,
24899 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24900 with specified algorithm. */
24901 bool
24907 {
24908 rtx destreg;
24911 rtx tmp;
24927 /* TODO: Once value ranges are available, fill in proper data. */
24935 /* i386 can do misaligned access on reasonably increased cost. */
24939 /* ALIGN is the minimum of destination and source alignment, but we care here
24940 just about destination alignment. */
24946 {
24949 /* When COUNT is 0, there is nothing to do. */
24952 }
24953 else
24954 {
24963 }
24965 /* Make sure we don't need to care about overflow later on. */
24969 /* Step 0: Decide on preferred algorithm, desired alignment and
24970 size of chunks to be copied by main loop. */
24972 issetmem,
24979 /* For now vector-version of memset is generated only for memory zeroing, as
24980 creating of promoted vector value is very cheap in this case. */
24993 {
25012 /* Find the widest supported mode. */
25018 /* Find the corresponding vector mode with the same size as MOVE_MODE.
25019 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
25021 {
25026 }
25038 }
25046 /* Step 1: Prologue guard. */
25048 /* Alignment code needs count to be in register. */
25050 {
25053 {
25054 align_bytes
25058 else
25060 }
25063 }
25066 /* Misaligned move sequences handle both prologue and epilogue at once.
25067 Default code generation results in a smaller code for large alignments
25068 and also avoids redundant job when sizes are known precisely. */
25069 misaligned_prologue_used
25070 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
25076 /* Do the cheap promotion to allow better CSE across the
25077 main loop and epilogue (ie one load of the big constant in the
25078 front of all code.
25079 For now the misaligned move sequences do not have fast path
25080 without broadcasting. */
25082 {
25084 {
25090 }
25091 else
25092 {
25095 }
25096 }
25097 /* Misaligned move sequences handles both prologues and epilogues at once.
25098 Default code generation results in smaller code for large alignments and
25099 also avoids redundant job when sizes are known precisely. */
25101 {
25102 /* Misaligned move prologue handled small blocks by itself. */
25103 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
25108 desired_align < align
25118 {
25119 /* It is possible that we copied enough so the main loop will not
25120 execute. */
25130 else
25132 }
25133 }
25134 /* Ensure that alignment prologue won't copy past end of block. */
25136 {
25138 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
25139 Make sure it is power of 2. */
25142 /* To improve performance of small blocks, we jump around the VAL
25143 promoting mode. This mean that if the promoted VAL is not constant,
25144 we might not use it in the epilogue and have to use byte
25145 loop variant. */
25150 {
25151 /* If main algorithm works on QImode, no epilogue is needed.
25152 For small sizes just don't align anything. */
25155 else
25157 }
25160 {
25167 else
25169 }
25170 }
25172 /* Emit code to decide on runtime whether library call or inline should be
25173 used. */
25175 {
25177 {
25179 {
25183 }
25184 }
25185 else
25186 {
25196 else
25200 }
25201 }
25203 /* Step 2: Alignment prologue. */
25204 /* Do the expensive promotion once we branched off the small blocks. */
25210 {
25212 {
25213 /* Except for the first move in prologue, we no longer know
25214 constant offset in aliasing info. It don't seems to worth
25215 the pain to maintain it for the first move, so throw away
25216 the info early. */
25223 issetmem);
25224 /* At most desired_align - align bytes are copied. */
25227 else
25229 }
25230 else
25231 {
25232 /* If we know how many bytes need to be stored before dst is
25233 sufficiently aligned, maintain aliasing info accurately. */
25235 srcreg,
25236 promoted_val,
25237 vec_promoted_val,
25238 desired_align,
25239 align_bytes,
25240 issetmem);
25247 }
25254 {
25255 /* It is possible that we copied enough so the main loop will not
25256 execute. */
25266 else
25268 }
25269 }
25271 {
25278 }
25282 /* Step 3: Main loop. */
25285 {
25308 }
25309 /* Adjust properly the offset of src and dest memory for aliasing. */
25311 {
25317 }
25318 else
25319 {
25323 }
25325 /* Step 4: Epilogue to copy the remaining bytes. */
25326 epilogue:
25328 {
25329 /* When the main loop is done, COUNT_EXP might hold original count,
25330 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
25331 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
25332 bytes. Compensate if needed. */
25335 {
25336 tmp =
25339 OPTAB_DIRECT);
25342 }
25345 }
25348 {
25351 epilogue_size_needed);
25352 else
25353 {
25357 epilogue_size_needed);
25358 else
25360 epilogue_size_needed);
25361 }
25362 }
25366 }
25369 /* Expand the appropriate insns for doing strlen if not just doing
25370 repnz; scasb
25372 out = result, initialized with the start address
25373 align_rtx = alignment of the address.
25374 scratch = scratch register, initialized with the startaddress when
25375 not aligned, otherwise undefined
25377 This is just the body. It needs the initializations mentioned above and
25378 some address computing at the end. These things are done in i386.md. */
25380 static void
25382 {
25384 rtx tmp;
25389 rtx mem;
25392 rtx cmp;
25398 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
25400 /* Is there a known alignment and is it less than 4? */
25402 {
25405 /* Is there a known alignment and is it not 2? */
25407 {
25411 /* Leave just the 3 lower bits. */
25421 }
25422 else
25423 {
25424 /* Since the alignment is 2, we have to check 2 or 0 bytes;
25425 check if is aligned to 4 - byte. */
25432 }
25436 /* Now compare the bytes. */
25438 /* Compare the first n unaligned byte on a byte per byte basis. */
25442 /* Increment the address. */
25445 /* Not needed with an alignment of 2 */
25447 {
25451 end_0_label);
25456 }
25459 end_0_label);
25462 }
25464 /* Generate loop to check 4 bytes at a time. It is not a good idea to
25465 align this loop. It gives only huge programs, but does not help to
25466 speed up. */
25473 /* This formula yields a nonzero result iff one of the bytes is zero.
25474 This saves three branches inside loop and many cycles. */
25482 align_4_label);
25485 {
25491 /* If zero is not in the first two bytes, move two bytes forward. */
25497 reg,
25498 tmpreg)));
25499 /* Emit lea manually to avoid clobbering of flags. */
25506 reg2,
25507 out)));
25508 }
25509 else
25510 {
25512 /* Is zero in the first two bytes? */
25519 pc_rtx);
25523 /* Not in the first two. Move two bytes forward. */
25529 }
25531 /* Avoid branch in fixing the byte. */
25539 }
25541 /* Expand strlen. */
25543 bool
25545 {
25548 /* The generic case of strlen expander is long. Avoid it's
25549 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
25552 && !TARGET_INLINE_ALL_STRINGOPS
25562 {
25563 /* Well it seems that some optimizer does not combine a call like
25564 foo(strlen(bar), strlen(bar));
25565 when the move and the subtraction is done here. It does calculate
25566 the length just once when these instructions are done inside of
25567 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
25568 often used and I use one fewer register for the lifetime of
25569 output_strlen_unroll() this is better. */
25575 /* strlensi_unroll_1 returns the address of the zero at the end of
25576 the string, like memchr(), so compute the length by subtracting
25577 the start address. */
25579 }
25580 else
25581 {
25582 rtx unspec;
25584 /* Can't use this if the user has appropriated eax, ecx, or edi. */
25597 /* If .md starts supporting :P, this can be done in .md. */
25603 }
25605 }
25607 /* For given symbol (function) construct code to compute address of it's PLT
25608 entry in large x86-64 PIC model. */
25609 static rtx
25611 {
25624 }
25626 rtx
25628 rtx callarg2,
25630 {
25640 {
25641 #if TARGET_MACHO
25644 #endif
25645 }
25646 else
25647 {
25648 /* Static functions and indirect calls don't need the pic register. Also,
25649 check if PLT was explicitly avoided via no-plt or "noplt" attribute, making
25650 it an indirect call. */
25652 && (!TARGET_64BIT
25657 && flag_plt
25661 {
25665 pic_offset_table_rtx);
25666 }
25667 }
25669 /* Skip setting up RAX register for -mskip-rax-setup when there are no
25670 parameters passed in vector registers. */
25675 {
25679 }
25682 && !TARGET_PECOFF
25690 {
25693 }
25698 {
25699 /* We should add bounds as destination register in case
25700 pointer with bounds may be returned. */
25702 {
25706 {
25711 }
25712 else
25713 {
25717 }
25718 }
25721 }
25725 {
25729 }
25733 {
25734 int const cregs_size
25739 {
25744 }
25745 }
25754 }
25756 /* Return true if the function being called was marked with attribute "noplt"
25757 or using -fno-plt and we are compiling for non-PIC and x86_64. We need to
25758 handle the non-PIC case in the backend because there is no easy interface
25759 for the front-end to force non-PLT calls to use the GOT. This is currently
25760 used only with 64-bit ELF targets to call the function marked "noplt"
25761 indirectly. */
25763 static bool
25765 {
25779 }
25781 /* Output the assembly for a call instruction. */
25785 {
25791 {
25796 /* SEH epilogue detection requires the indirect branch case
25797 to include REX.W. */
25800 else
25805 }
25807 /* SEH unwinding can require an extra nop to be emitted in several
25808 circumstances. Determine if we have one of those. */
25810 {
25814 {
25815 /* If we get to another real insn, we don't need the nop. */
25819 /* If we get to the epilogue note, prevent a catch region from
25820 being adjacent to the standard epilogue sequence. If non-
25821 call-exceptions, we'll have done this during epilogue emission. */
25823 && !flag_non_call_exceptions
25825 {
25828 }
25829 }
25831 /* If we didn't find a real insn following the call, prevent the
25832 unwinder from looking into the next function. */
25835 }
25841 else
25850 }
25851 \f
25852 /* Clear stack slot assignments remembered from previous functions.
25853 This is called from INIT_EXPANDERS once before RTL is emitted for each
25854 function. */
25858 {
25866 }
25868 /* Return a MEM corresponding to a stack slot with mode MODE.
25869 Allocate a new slot if necessary.
25871 The RTL for a function can have several slots available: N is
25872 which slot to use. */
25874 rtx
25876 {
25893 }
25895 static void
25897 {
25903 }
25904 \f
25905 /* Check whether x86 address PARTS is a pc-relative address. */
25907 static bool
25909 {
25917 {
25919 {
25936 }
25937 }
25939 }
25941 /* Calculate the length of the memory address in the instruction encoding.
25942 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25943 or other prefixes. We never generate addr32 prefix for LEA insn. */
25945 int
25947 {
25964 /* If this is not LEA instruction, add the length of addr32 prefix. */
25969 len++;
25983 /* Rule of thumb:
25984 - esp as the base always wants an index,
25985 - ebp as the base always wants a displacement,
25986 - r12 as the base always wants an index,
25987 - r13 as the base always wants a displacement. */
25989 /* Register Indirect. */
25991 {
25992 /* esp (for its index) and ebp (for its displacement) need
25993 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25994 code. */
26001 len++;
26002 }
26004 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
26005 is not disp32, but disp32(%rip), so for disp32
26006 SIB byte is needed, unless print_operand_address
26007 optimizes it into disp32(%rip) or (%rip) is implied
26008 by UNSPEC. */
26010 {
26013 len++;
26014 }
26015 else
26016 {
26017 /* Find the length of the displacement constant. */
26019 {
26022 else
26024 }
26025 /* ebp always wants a displacement. Similarly r13. */
26027 len++;
26029 /* An index requires the two-byte modrm form.... */
26031 /* ...like esp (or r12), which always wants an index. */
26035 len++;
26036 }
26039 }
26041 /* Compute default value for "length_immediate" attribute. When SHORTFORM
26042 is set, expect that insn have 8bit immediate alternative. */
26043 int
26045 {
26051 {
26056 {
26059 {
26071 }
26073 {
26076 }
26077 }
26079 {
26089 /* Immediates for DImode instructions are encoded
26090 as 32bit sign extended values. */
26096 }
26097 }
26099 }
26101 /* Compute default value for "length_address" attribute. */
26102 int
26104 {
26108 {
26119 }
26124 {
26127 {
26132 constraints++;
26135 ;
26136 /* Skip ignored operands. */
26139 }
26141 }
26143 }
26145 /* Compute default value for "length_vex" attribute. It includes
26146 2 or 3 byte VEX prefix and 1 opcode byte. */
26148 int
26151 {
26154 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
26155 byte VEX prefix. */
26159 /* We can always use 2 byte VEX prefix in 32bit. */
26167 {
26168 /* REX.W bit uses 3 byte VEX prefix. */
26172 }
26173 else
26174 {
26175 /* REX.X or REX.B bits use 3 byte VEX prefix. */
26179 }
26182 }
26183 \f
26184 /* Return the maximum number of instructions a cpu can issue. */
26186 static int
26188 {
26190 {
26223 }
26224 }
26226 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
26227 by DEP_INSN and nothing set by DEP_INSN. */
26229 static bool
26231 {
26234 /* Simplify the test for uninteresting insns. */
26242 {
26245 }
26250 {
26253 }
26254 else
26260 /* This test is true if the dependent insn reads the flags but
26261 not any other potentially set register. */
26269 }
26271 /* Return true iff USE_INSN has a memory address with operands set by
26272 SET_INSN. */
26274 bool
26276 {
26281 {
26284 }
26286 }
26288 /* Helper function for exact_store_load_dependency.
26289 Return true if addr is found in insn. */
26290 static bool
26292 {
26299 {
26305 CASE_CONST_ANY:
26314 }
26318 {
26320 {
26330 }
26331 }
26333 }
26335 /* Return true if there exists exact dependency for store & load, i.e.
26336 the same memory address is used in them. */
26337 static bool
26339 {
26353 }
26355 static int
26357 {
26363 /* Anti and output dependencies have zero cost on all CPUs. */
26369 /* If we can't recognize the insns, we can't really do anything. */
26377 {
26380 /* Address Generation Interlock adds a cycle of latency. */
26382 {
26393 }
26397 /* ??? Compares pair with jump/setcc. */
26401 /* Floating point stores require value to be ready one cycle earlier. */
26409 /* INT->FP conversion is expensive. */
26413 /* There is one cycle extra latency between an FP op and a store. */
26423 /* Show ability of reorder buffer to hide latency of load by executing
26424 in parallel with previous instruction in case
26425 previous instruction is not needed to compute the address. */
26428 {
26429 /* Claim moves to take one cycle, as core can issue one load
26430 at time and the next load can start cycle later. */
26435 cost--;
26436 }
26440 /* The esp dependency is resolved before
26441 the instruction is really finished. */
26446 /* INT->FP conversion is expensive. */
26452 /* Show ability of reorder buffer to hide latency of load by executing
26453 in parallel with previous instruction in case
26454 previous instruction is not needed to compute the address. */
26457 {
26458 /* Claim moves to take one cycle, as core can issue one load
26459 at time and the next load can start cycle later. */
26465 else
26467 }
26478 /* Stack engine allows to execute push&pop instructions in parall. */
26482 /* FALLTHRU */
26488 /* Show ability of reorder buffer to hide latency of load by executing
26489 in parallel with previous instruction in case
26490 previous instruction is not needed to compute the address. */
26493 {
26497 /* Because of the difference between the length of integer and
26498 floating unit pipeline preparation stages, the memory operands
26499 for floating point are cheaper.
26501 ??? For Athlon it the difference is most probably 2. */
26504 else
26509 else
26511 }
26518 /* Stack engine allows to execute push&pop instructions in parall. */
26525 /* Show ability of reorder buffer to hide latency of load by executing
26526 in parallel with previous instruction in case
26527 previous instruction is not needed to compute the address. */
26530 {
26533 else
26535 }
26544 /* Increase cost of integer loads. */
26547 {
26550 {
26553 else
26554 {
26555 /* Increase cost of ld/st for short int types only
26556 because of store forwarding issue. */
26560 {
26561 /* Increase cost of store/load insn if exact
26562 dependence exists and it is load insn. */
26567 }
26568 }
26569 }
26570 }
26574 }
26577 }
26579 /* How many alternative schedules to try. This should be as wide as the
26580 scheduling freedom in the DFA, but no wider. Making this value too
26581 large results extra work for the scheduler. */
26583 static int
26585 {
26587 {
26600 /* We use lookahead value 4 for BD both before and after reload
26601 schedules. Plan is to have value 8 included for O3. */
26612 /* Generally, we want haifa-sched:max_issue() to look ahead as far
26613 as many instructions can be executed on a cycle, i.e.,
26614 issue_rate. I wonder why tuning for many CPUs does not do this. */
26617 /* Don't use lookahead for pre-reload schedule to save compile time. */
26622 }
26623 }
26625 /* Return true if target platform supports macro-fusion. */
26627 static bool
26629 {
26631 }
26633 /* Check whether current microarchitecture support macro fusion
26634 for insn pair "CONDGEN + CONDJMP". Refer to
26635 "Intel Architectures Optimization Reference Manual". */
26637 static bool
26639 {
26660 {
26665 {
26669 else
26671 }
26672 }
26679 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
26680 supported. */
26687 /* No fusion for RIP-relative address. */
26694 ix86_address parts;
26700 }
26705 /* Check whether conditional jump use Sign or Overflow Flags. */
26713 /* Return true for TYPE_TEST and TYPE_ICMP. */
26718 /* The following is the case that macro-fusion for alu + jmp. */
26722 /* No fusion for alu op with memory destination operand. */
26727 /* Macro-fusion for inc/dec + unsigned conditional jump is not
26728 supported. */
26737 }
26739 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
26740 execution. It is applied if
26741 (1) IMUL instruction is on the top of list;
26742 (2) There exists the only producer of independent IMUL instruction in
26743 ready list.
26744 Return index of IMUL producer if it was found and -1 otherwise. */
26745 static int
26747 {
26750 sd_iterator_def sd_it;
26751 dep_t dep;
26758 /* Check that IMUL instruction is on the top of ready list. */
26767 /* Search for producer of independent IMUL instruction. */
26769 {
26773 /* Skip IMUL instruction. */
26783 {
26784 rtx con;
26795 {
26796 sd_iterator_def sd_it1;
26797 dep_t dep1;
26798 /* Check if there is no other dependee for IMUL. */
26801 {
26802 rtx pro;
26808 }
26811 }
26812 }
26815 }
26817 }
26819 /* Try to find the best candidate on the top of ready list if two insns
26820 have the same priority - candidate is best if its dependees were
26821 scheduled earlier. Applied for Silvermont only.
26822 Return true if top 2 insns must be interchanged. */
26823 static bool
26825 {
26828 rtx set;
26829 sd_iterator_def sd_it;
26830 dep_t dep;
26833 #define INSN_TICK(INSN) (HID (INSN)->tick)
26854 {
26857 /* Determine winner more precise. */
26859 {
26860 rtx pro;
26866 }
26868 {
26869 rtx pro;
26875 }
26878 {
26879 /* Determine winner - load must win. */
26885 }
26887 }
26889 #undef INSN_TICK
26890 }
26892 /* Perform possible reodering of ready list for Atom/Silvermont only.
26893 Return issue rate. */
26894 static int
26897 {
26904 /* Set up issue rate. */
26907 /* Do reodering for BONNELL/SILVERMONT only. */
26911 /* Nothing to do if ready list contains only 1 instruction. */
26915 /* Do reodering for post-reload scheduler only. */
26920 {
26925 /* Put IMUL producer (ready[index]) at the top of ready list. */
26931 }
26933 /* Skip selective scheduling since HID is not populated in it. */
26937 {
26941 /* Swap 2 top elements of ready list. */
26945 }
26947 }
26949 static bool
26952 /* Returns true if lhs of insn is HW function argument register and set up
26953 is_spilled to true if it is likely spilled HW register. */
26954 static bool
26956 {
26957 rtx dst;
26961 /* Call instructions are not movable, ignore it. */
26972 {
26973 /* Is it likely spilled HW register? */
26978 }
26980 }
26982 /* Add output dependencies for chain of function adjacent arguments if only
26983 there is a move to likely spilled HW register. Return first argument
26984 if at least one dependence was added or NULL otherwise. */
26987 {
26995 /* Find nearest to call argument passing instruction. */
26997 {
27006 }
27010 {
27017 {
27020 }
27022 {
27023 /* Add output depdendence between two function arguments if chain
27024 of output arguments contains likely spilled HW registers. */
27028 }
27029 else
27031 }
27035 }
27037 /* Add output or anti dependency from insn to first_arg to restrict its code
27038 motion. */
27039 static void
27041 {
27042 rtx set;
27043 rtx tmp;
27045 /* Add anti dependencies for bounds stores. */
27050 {
27053 }
27060 {
27061 /* Add output dependency to the first function argument. */
27064 }
27065 /* Add anti dependency. */
27067 }
27069 /* Avoid cross block motion of function argument through adding dependency
27070 from the first non-jump instruction in bb. */
27071 static void
27073 {
27077 {
27079 {
27082 {
27085 }
27086 }
27090 }
27091 }
27093 /* Hook for pre-reload schedule - avoid motion of function arguments
27094 passed in likely spilled HW registers. */
27095 static void
27097 {
27106 {
27109 {
27110 /* Add dependee for first argument to predecessors if only
27111 region contains more than one block. */
27115 /* Skip trivial regions and region head blocks that can have
27116 predecessors outside of region. */
27118 {
27119 edge e;
27120 edge_iterator ei;
27122 /* Regions are SCCs with the exception of selective
27123 scheduling with pipelining of outer blocks enabled.
27124 So also check that immediate predecessors of a non-head
27125 block are in the same region. */
27127 {
27128 /* Avoid creating of loop-carried dependencies through
27129 using topological ordering in the region. */
27133 }
27134 }
27138 }
27139 }
27142 }
27144 /* Hook for pre-reload schedule - set priority of moves from likely spilled
27145 HW registers to maximum, to schedule them at soon as possible. These are
27146 moves from function argument registers at the top of the function entry
27147 and moves from function return value registers after call. */
27148 static int
27150 {
27151 rtx set;
27161 {
27168 }
27171 }
27173 /* Model decoder of Core 2/i7.
27174 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
27175 track the instruction fetch block boundaries and make sure that long
27176 (9+ bytes) instructions are assigned to D0. */
27178 /* Maximum length of an insn that can be handled by
27179 a secondary decoder unit. '8' for Core 2/i7. */
27182 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
27183 '16' for Core 2/i7. */
27186 /* Maximum number of instructions decoder can handle per cycle.
27187 '6' for Core 2/i7. */
27191 ix86_first_cycle_multipass_data_t;
27193 const_ix86_first_cycle_multipass_data_t;
27195 /* A variable to store target state across calls to max_issue within
27196 one cycle. */
27200 /* Initialize DATA. */
27201 static void
27203 {
27204 ix86_first_cycle_multipass_data_t data
27211 }
27213 /* Advancing the cycle; reset ifetch block counts. */
27214 static void
27216 {
27223 }
27227 /* Filter out insns from ready_try that the core will not be able to issue
27228 on current cycle due to decoder. */
27229 static void
27230 core2i7_first_cycle_multipass_filter_ready_try
27233 {
27235 {
27246 (!first_cycle_insn_p
27248 /* ... or it would not fit into the ifetch block ... */
27250 /* ... or the decoder is full already ... */
27252 /* ... mask the insn out. */
27253 {
27258 }
27259 }
27260 }
27262 /* Prepare for a new round of multipass lookahead scheduling. */
27263 static void
27267 {
27268 ix86_first_cycle_multipass_data_t data
27270 const_ix86_first_cycle_multipass_data_t prev_data
27273 /* Restore the state from the end of the previous round. */
27277 /* Filter instructions that cannot be issued on current cycle due to
27278 decoder restrictions. */
27280 first_cycle_insn_p);
27281 }
27283 /* INSN is being issued in current solution. Account for its impact on
27284 the decoder model. */
27285 static void
27289 {
27290 ix86_first_cycle_multipass_data_t data
27292 const_ix86_first_cycle_multipass_data_t prev_data
27302 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
27304 {
27307 }
27309 {
27313 }
27316 /* Filter out insns from ready_try that the core will not be able to issue
27317 on current cycle due to decoder. */
27320 }
27322 /* Revert the effect on ready_try. */
27323 static void
27327 {
27328 const_ix86_first_cycle_multipass_data_t data
27331 sbitmap_iterator sbi;
27335 {
27337 }
27338 }
27340 /* Save the result of multipass lookahead scheduling for the next round. */
27341 static void
27343 {
27344 const_ix86_first_cycle_multipass_data_t data
27346 ix86_first_cycle_multipass_data_t next_data
27350 {
27353 }
27354 }
27356 /* Deallocate target data. */
27357 static void
27359 {
27360 ix86_first_cycle_multipass_data_t data
27364 {
27368 }
27369 }
27371 /* Prepare for scheduling pass. */
27372 static void
27374 {
27375 /* Install scheduling hooks for current CPU. Some of these hooks are used
27376 in time-critical parts of the scheduler, so we only set them up when
27377 they are actually used. */
27379 {
27384 /* Do not perform multipass scheduling for pre-reload schedule
27385 to save compile time. */
27387 {
27403 /* Set decoder parameters. */
27408 }
27409 /* ... Fall through ... */
27419 }
27420 }
27422 \f
27423 /* Compute the alignment given to a constant that is being placed in memory.
27424 EXP is the constant and ALIGN is the alignment that the object would
27425 ordinarily have.
27426 The value of this function is used instead of that alignment to align
27427 the object. */
27429 int
27431 {
27434 {
27439 }
27445 }
27447 /* Compute the alignment for a variable for Intel MCU psABI. TYPE is
27448 the data type, and ALIGN is the alignment that the object would
27449 ordinarily have. */
27451 static int
27453 {
27459 /* Intel MCU psABI specifies scalar types > 4 bytes aligned to 4
27460 bytes. */
27463 {
27472 }
27473 }
27475 /* Compute the alignment for a static variable.
27476 TYPE is the data type, and ALIGN is the alignment that
27477 the object would ordinarily have. The value of this function is used
27478 instead of that alignment to align the object. */
27480 int
27482 {
27483 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
27484 for symbols from other compilation units or symbols that don't need
27485 to bind locally. In order to preserve some ABI compatibility with
27486 those compilers, ensure we don't decrease alignment from what we
27487 used to assume. */
27491 /* A data structure, equal or greater than the size of a cache line
27492 (64 bytes in the Pentium 4 and other recent Intel processors, including
27493 processors based on Intel Core microarchitecture) should be aligned
27494 so that its base address is a multiple of a cache line size. */
27496 int max_align
27503 {
27507 }
27516 {
27523 }
27525 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27526 to 16byte boundary. */
27528 {
27535 }
27541 {
27546 }
27548 {
27555 }
27560 {
27565 }
27568 {
27573 }
27576 }
27578 /* Compute the alignment for a local variable or a stack slot. EXP is
27579 the data type or decl itself, MODE is the widest mode available and
27580 ALIGN is the alignment that the object would ordinarily have. The
27581 value of this macro is used instead of that alignment to align the
27582 object. */
27584 unsigned int
27587 {
27591 {
27594 }
27595 else
27596 {
27599 }
27601 /* Don't do dynamic stack realignment for long long objects with
27602 -mpreferred-stack-boundary=2. */
27611 /* If TYPE is NULL, we are allocating a stack slot for caller-save
27612 register in MODE. We will return the largest alignment of XF
27613 and DF. */
27615 {
27619 }
27621 /* Don't increase alignment for Intel MCU psABI. */
27625 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27626 to 16byte boundary. Exact wording is:
27628 An array uses the same alignment as its elements, except that a local or
27629 global array variable of length at least 16 bytes or
27630 a C99 variable-length array variable always has alignment of at least 16 bytes.
27632 This was added to allow use of aligned SSE instructions at arrays. This
27633 rule is meant for static storage (where compiler can not do the analysis
27634 by itself). We follow it for automatic variables only when convenient.
27635 We fully control everything in the function compiled and functions from
27636 other unit can not rely on the alignment.
27638 Exclude va_list type. It is the common case of local array where
27639 we can not benefit from the alignment.
27641 TODO: Probably one should optimize for size only when var is not escaping. */
27644 {
27654 }
27656 {
27661 }
27663 {
27669 }
27674 {
27679 }
27682 {
27688 }
27690 }
27692 /* Compute the minimum required alignment for dynamic stack realignment
27693 purposes for a local variable, parameter or a stack slot. EXP is
27694 the data type or decl itself, MODE is its mode and ALIGN is the
27695 alignment that the object would ordinarily have. */
27697 unsigned int
27700 {
27704 {
27707 }
27708 else
27709 {
27712 }
27717 /* Don't do dynamic stack realignment for long long objects with
27718 -mpreferred-stack-boundary=2. */
27725 }
27726 \f
27727 /* Find a location for the static chain incoming to a nested function.
27728 This is a register, unless all free registers are used by arguments. */
27730 static rtx
27732 {
27735 /* While this function won't be called by the middle-end when a static
27736 chain isn't needed, it's also used throughout the backend so it's
27737 easiest to keep this check centralized. */
27742 {
27743 /* We always use R10 in 64-bit mode. */
27745 }
27746 else
27747 {
27751 /* By default in 32-bit mode we use ECX to pass the static chain. */
27755 {
27758 }
27759 else
27760 {
27763 }
27767 {
27768 /* Fastcall functions use ecx/edx for arguments, which leaves
27769 us with EAX for the static chain.
27770 Thiscall functions use ecx for arguments, which also
27771 leaves us with EAX for the static chain. */
27773 }
27775 {
27776 /* Thiscall functions use ecx for arguments, which leaves
27777 us with EAX and EDX for the static chain.
27778 We are using for abi-compatibility EAX. */
27780 }
27782 {
27783 /* For regparm 3, we have no free call-clobbered registers in
27784 which to store the static chain. In order to implement this,
27785 we have the trampoline push the static chain to the stack.
27786 However, we can't push a value below the return address when
27787 we call the nested function directly, so we have to use an
27788 alternate entry point. For this we use ESI, and have the
27789 alternate entry point push ESI, so that things appear the
27790 same once we're executing the nested function. */
27792 {
27798 }
27800 }
27801 }
27804 }
27806 /* Emit RTL insns to initialize the variable parts of a trampoline.
27807 FNDECL is the decl of the target address; M_TRAMP is a MEM for
27808 the trampoline, and CHAIN_VALUE is an RTX for the static chain
27809 to be passed to the target function. */
27811 static void
27813 {
27821 {
27824 /* Load the function address to r11. Try to load address using
27825 the shorter movl instead of movabs. We may want to support
27826 movq for kernel mode, but kernel does not use trampolines at
27827 the moment. FNADDR is a 32bit address and may not be in
27828 DImode when ptr_mode == SImode. Always use movl in this
27829 case. */
27832 {
27841 }
27842 else
27843 {
27850 }
27852 /* Load static chain using movabs to r10. Use the shorter movl
27853 instead of movabs when ptr_mode == SImode. */
27855 {
27858 }
27859 else
27860 {
27863 }
27872 /* Jump to r11; the last (unused) byte is a nop, only there to
27873 pad the write out to a single 32-bit store. */
27877 }
27878 else
27879 {
27882 /* Depending on the static chain location, either load a register
27883 with a constant, or push the constant to the stack. All of the
27884 instructions are the same size. */
27887 {
27889 {
27896 }
27897 }
27898 else
27913 /* Compute offset from the end of the jmp to the target function.
27914 In the case in which the trampoline stores the static chain on
27915 the stack, we need to skip the first insn which pushes the
27916 (call-saved) register static chain; this push is 1 byte. */
27923 }
27927 #ifdef HAVE_ENABLE_EXECUTE_STACK
27928 #ifdef CHECK_EXECUTE_STACK_ENABLED
27930 #endif
27933 #endif
27934 }
27935 \f
27936 /* The following file contains several enumerations and data structures
27937 built from the definitions in i386-builtin-types.def. */
27941 /* Table for the ix86 builtin non-function types. */
27944 /* Retrieve an element from the above table, building some of
27945 the types lazily. */
27947 static tree
27949 {
27961 {
27962 machine_mode mode;
27969 }
27970 else
27971 {
27977 else
27985 }
27989 }
27991 /* Table for the ix86 builtin function types. */
27994 /* Retrieve an element from the above table, building some of
27995 the types lazily. */
27997 static tree
27999 {
28000 tree type;
28009 {
28017 {
28020 }
28023 }
28024 else
28025 {
28031 }
28035 }
28038 /* Codes for all the SSE/MMX builtins. */
28039 enum ix86_builtins
28040 {
28041 IX86_BUILTIN_ADDPS,
28042 IX86_BUILTIN_ADDSS,
28043 IX86_BUILTIN_DIVPS,
28044 IX86_BUILTIN_DIVSS,
28045 IX86_BUILTIN_MULPS,
28046 IX86_BUILTIN_MULSS,
28047 IX86_BUILTIN_SUBPS,
28048 IX86_BUILTIN_SUBSS,
28050 IX86_BUILTIN_CMPEQPS,
28051 IX86_BUILTIN_CMPLTPS,
28052 IX86_BUILTIN_CMPLEPS,
28053 IX86_BUILTIN_CMPGTPS,
28054 IX86_BUILTIN_CMPGEPS,
28055 IX86_BUILTIN_CMPNEQPS,
28056 IX86_BUILTIN_CMPNLTPS,
28057 IX86_BUILTIN_CMPNLEPS,
28058 IX86_BUILTIN_CMPNGTPS,
28059 IX86_BUILTIN_CMPNGEPS,
28060 IX86_BUILTIN_CMPORDPS,
28061 IX86_BUILTIN_CMPUNORDPS,
28062 IX86_BUILTIN_CMPEQSS,
28063 IX86_BUILTIN_CMPLTSS,
28064 IX86_BUILTIN_CMPLESS,
28065 IX86_BUILTIN_CMPNEQSS,
28066 IX86_BUILTIN_CMPNLTSS,
28067 IX86_BUILTIN_CMPNLESS,
28068 IX86_BUILTIN_CMPORDSS,
28069 IX86_BUILTIN_CMPUNORDSS,
28071 IX86_BUILTIN_COMIEQSS,
28072 IX86_BUILTIN_COMILTSS,
28073 IX86_BUILTIN_COMILESS,
28074 IX86_BUILTIN_COMIGTSS,
28075 IX86_BUILTIN_COMIGESS,
28076 IX86_BUILTIN_COMINEQSS,
28077 IX86_BUILTIN_UCOMIEQSS,
28078 IX86_BUILTIN_UCOMILTSS,
28079 IX86_BUILTIN_UCOMILESS,
28080 IX86_BUILTIN_UCOMIGTSS,
28081 IX86_BUILTIN_UCOMIGESS,
28082 IX86_BUILTIN_UCOMINEQSS,
28084 IX86_BUILTIN_CVTPI2PS,
28085 IX86_BUILTIN_CVTPS2PI,
28086 IX86_BUILTIN_CVTSI2SS,
28087 IX86_BUILTIN_CVTSI642SS,
28088 IX86_BUILTIN_CVTSS2SI,
28089 IX86_BUILTIN_CVTSS2SI64,
28090 IX86_BUILTIN_CVTTPS2PI,
28091 IX86_BUILTIN_CVTTSS2SI,
28092 IX86_BUILTIN_CVTTSS2SI64,
28094 IX86_BUILTIN_MAXPS,
28095 IX86_BUILTIN_MAXSS,
28096 IX86_BUILTIN_MINPS,
28097 IX86_BUILTIN_MINSS,
28099 IX86_BUILTIN_LOADUPS,
28100 IX86_BUILTIN_STOREUPS,
28101 IX86_BUILTIN_MOVSS,
28103 IX86_BUILTIN_MOVHLPS,
28104 IX86_BUILTIN_MOVLHPS,
28105 IX86_BUILTIN_LOADHPS,
28106 IX86_BUILTIN_LOADLPS,
28107 IX86_BUILTIN_STOREHPS,
28108 IX86_BUILTIN_STORELPS,
28110 IX86_BUILTIN_MASKMOVQ,
28111 IX86_BUILTIN_MOVMSKPS,
28112 IX86_BUILTIN_PMOVMSKB,
28114 IX86_BUILTIN_MOVNTPS,
28115 IX86_BUILTIN_MOVNTQ,
28117 IX86_BUILTIN_LOADDQU,
28118 IX86_BUILTIN_STOREDQU,
28120 IX86_BUILTIN_PACKSSWB,
28121 IX86_BUILTIN_PACKSSDW,
28122 IX86_BUILTIN_PACKUSWB,
28124 IX86_BUILTIN_PADDB,
28125 IX86_BUILTIN_PADDW,
28126 IX86_BUILTIN_PADDD,
28127 IX86_BUILTIN_PADDQ,
28128 IX86_BUILTIN_PADDSB,
28129 IX86_BUILTIN_PADDSW,
28130 IX86_BUILTIN_PADDUSB,
28131 IX86_BUILTIN_PADDUSW,
28132 IX86_BUILTIN_PSUBB,
28133 IX86_BUILTIN_PSUBW,
28134 IX86_BUILTIN_PSUBD,
28135 IX86_BUILTIN_PSUBQ,
28136 IX86_BUILTIN_PSUBSB,
28137 IX86_BUILTIN_PSUBSW,
28138 IX86_BUILTIN_PSUBUSB,
28139 IX86_BUILTIN_PSUBUSW,
28141 IX86_BUILTIN_PAND,
28142 IX86_BUILTIN_PANDN,
28143 IX86_BUILTIN_POR,
28144 IX86_BUILTIN_PXOR,
28146 IX86_BUILTIN_PAVGB,
28147 IX86_BUILTIN_PAVGW,
28149 IX86_BUILTIN_PCMPEQB,
28150 IX86_BUILTIN_PCMPEQW,
28151 IX86_BUILTIN_PCMPEQD,
28152 IX86_BUILTIN_PCMPGTB,
28153 IX86_BUILTIN_PCMPGTW,
28154 IX86_BUILTIN_PCMPGTD,
28156 IX86_BUILTIN_PMADDWD,
28158 IX86_BUILTIN_PMAXSW,
28159 IX86_BUILTIN_PMAXUB,
28160 IX86_BUILTIN_PMINSW,
28161 IX86_BUILTIN_PMINUB,
28163 IX86_BUILTIN_PMULHUW,
28164 IX86_BUILTIN_PMULHW,
28165 IX86_BUILTIN_PMULLW,
28167 IX86_BUILTIN_PSADBW,
28168 IX86_BUILTIN_PSHUFW,
28170 IX86_BUILTIN_PSLLW,
28171 IX86_BUILTIN_PSLLD,
28172 IX86_BUILTIN_PSLLQ,
28173 IX86_BUILTIN_PSRAW,
28174 IX86_BUILTIN_PSRAD,
28175 IX86_BUILTIN_PSRLW,
28176 IX86_BUILTIN_PSRLD,
28177 IX86_BUILTIN_PSRLQ,
28178 IX86_BUILTIN_PSLLWI,
28179 IX86_BUILTIN_PSLLDI,
28180 IX86_BUILTIN_PSLLQI,
28181 IX86_BUILTIN_PSRAWI,
28182 IX86_BUILTIN_PSRADI,
28183 IX86_BUILTIN_PSRLWI,
28184 IX86_BUILTIN_PSRLDI,
28185 IX86_BUILTIN_PSRLQI,
28187 IX86_BUILTIN_PUNPCKHBW,
28188 IX86_BUILTIN_PUNPCKHWD,
28189 IX86_BUILTIN_PUNPCKHDQ,
28190 IX86_BUILTIN_PUNPCKLBW,
28191 IX86_BUILTIN_PUNPCKLWD,
28192 IX86_BUILTIN_PUNPCKLDQ,
28194 IX86_BUILTIN_SHUFPS,
28196 IX86_BUILTIN_RCPPS,
28197 IX86_BUILTIN_RCPSS,
28198 IX86_BUILTIN_RSQRTPS,
28199 IX86_BUILTIN_RSQRTPS_NR,
28200 IX86_BUILTIN_RSQRTSS,
28201 IX86_BUILTIN_RSQRTF,
28202 IX86_BUILTIN_SQRTPS,
28203 IX86_BUILTIN_SQRTPS_NR,
28204 IX86_BUILTIN_SQRTSS,
28206 IX86_BUILTIN_UNPCKHPS,
28207 IX86_BUILTIN_UNPCKLPS,
28209 IX86_BUILTIN_ANDPS,
28210 IX86_BUILTIN_ANDNPS,
28211 IX86_BUILTIN_ORPS,
28212 IX86_BUILTIN_XORPS,
28214 IX86_BUILTIN_EMMS,
28215 IX86_BUILTIN_LDMXCSR,
28216 IX86_BUILTIN_STMXCSR,
28217 IX86_BUILTIN_SFENCE,
28219 IX86_BUILTIN_FXSAVE,
28220 IX86_BUILTIN_FXRSTOR,
28221 IX86_BUILTIN_FXSAVE64,
28222 IX86_BUILTIN_FXRSTOR64,
28224 IX86_BUILTIN_XSAVE,
28225 IX86_BUILTIN_XRSTOR,
28226 IX86_BUILTIN_XSAVE64,
28227 IX86_BUILTIN_XRSTOR64,
28229 IX86_BUILTIN_XSAVEOPT,
28230 IX86_BUILTIN_XSAVEOPT64,
28232 IX86_BUILTIN_XSAVEC,
28233 IX86_BUILTIN_XSAVEC64,
28235 IX86_BUILTIN_XSAVES,
28236 IX86_BUILTIN_XRSTORS,
28237 IX86_BUILTIN_XSAVES64,
28238 IX86_BUILTIN_XRSTORS64,
28240 /* 3DNow! Original */
28241 IX86_BUILTIN_FEMMS,
28242 IX86_BUILTIN_PAVGUSB,
28243 IX86_BUILTIN_PF2ID,
28244 IX86_BUILTIN_PFACC,
28245 IX86_BUILTIN_PFADD,
28246 IX86_BUILTIN_PFCMPEQ,
28247 IX86_BUILTIN_PFCMPGE,
28248 IX86_BUILTIN_PFCMPGT,
28249 IX86_BUILTIN_PFMAX,
28250 IX86_BUILTIN_PFMIN,
28251 IX86_BUILTIN_PFMUL,
28252 IX86_BUILTIN_PFRCP,
28253 IX86_BUILTIN_PFRCPIT1,
28254 IX86_BUILTIN_PFRCPIT2,
28255 IX86_BUILTIN_PFRSQIT1,
28256 IX86_BUILTIN_PFRSQRT,
28257 IX86_BUILTIN_PFSUB,
28258 IX86_BUILTIN_PFSUBR,
28259 IX86_BUILTIN_PI2FD,
28260 IX86_BUILTIN_PMULHRW,
28262 /* 3DNow! Athlon Extensions */
28263 IX86_BUILTIN_PF2IW,
28264 IX86_BUILTIN_PFNACC,
28265 IX86_BUILTIN_PFPNACC,
28266 IX86_BUILTIN_PI2FW,
28267 IX86_BUILTIN_PSWAPDSI,
28268 IX86_BUILTIN_PSWAPDSF,
28270 /* SSE2 */
28271 IX86_BUILTIN_ADDPD,
28272 IX86_BUILTIN_ADDSD,
28273 IX86_BUILTIN_DIVPD,
28274 IX86_BUILTIN_DIVSD,
28275 IX86_BUILTIN_MULPD,
28276 IX86_BUILTIN_MULSD,
28277 IX86_BUILTIN_SUBPD,
28278 IX86_BUILTIN_SUBSD,
28280 IX86_BUILTIN_CMPEQPD,
28281 IX86_BUILTIN_CMPLTPD,
28282 IX86_BUILTIN_CMPLEPD,
28283 IX86_BUILTIN_CMPGTPD,
28284 IX86_BUILTIN_CMPGEPD,
28285 IX86_BUILTIN_CMPNEQPD,
28286 IX86_BUILTIN_CMPNLTPD,
28287 IX86_BUILTIN_CMPNLEPD,
28288 IX86_BUILTIN_CMPNGTPD,
28289 IX86_BUILTIN_CMPNGEPD,
28290 IX86_BUILTIN_CMPORDPD,
28291 IX86_BUILTIN_CMPUNORDPD,
28292 IX86_BUILTIN_CMPEQSD,
28293 IX86_BUILTIN_CMPLTSD,
28294 IX86_BUILTIN_CMPLESD,
28295 IX86_BUILTIN_CMPNEQSD,
28296 IX86_BUILTIN_CMPNLTSD,
28297 IX86_BUILTIN_CMPNLESD,
28298 IX86_BUILTIN_CMPORDSD,
28299 IX86_BUILTIN_CMPUNORDSD,
28301 IX86_BUILTIN_COMIEQSD,
28302 IX86_BUILTIN_COMILTSD,
28303 IX86_BUILTIN_COMILESD,
28304 IX86_BUILTIN_COMIGTSD,
28305 IX86_BUILTIN_COMIGESD,
28306 IX86_BUILTIN_COMINEQSD,
28307 IX86_BUILTIN_UCOMIEQSD,
28308 IX86_BUILTIN_UCOMILTSD,
28309 IX86_BUILTIN_UCOMILESD,
28310 IX86_BUILTIN_UCOMIGTSD,
28311 IX86_BUILTIN_UCOMIGESD,
28312 IX86_BUILTIN_UCOMINEQSD,
28314 IX86_BUILTIN_MAXPD,
28315 IX86_BUILTIN_MAXSD,
28316 IX86_BUILTIN_MINPD,
28317 IX86_BUILTIN_MINSD,
28319 IX86_BUILTIN_ANDPD,
28320 IX86_BUILTIN_ANDNPD,
28321 IX86_BUILTIN_ORPD,
28322 IX86_BUILTIN_XORPD,
28324 IX86_BUILTIN_SQRTPD,
28325 IX86_BUILTIN_SQRTSD,
28327 IX86_BUILTIN_UNPCKHPD,
28328 IX86_BUILTIN_UNPCKLPD,
28330 IX86_BUILTIN_SHUFPD,
28332 IX86_BUILTIN_LOADUPD,
28333 IX86_BUILTIN_STOREUPD,
28334 IX86_BUILTIN_MOVSD,
28336 IX86_BUILTIN_LOADHPD,
28337 IX86_BUILTIN_LOADLPD,
28339 IX86_BUILTIN_CVTDQ2PD,
28340 IX86_BUILTIN_CVTDQ2PS,
28342 IX86_BUILTIN_CVTPD2DQ,
28343 IX86_BUILTIN_CVTPD2PI,
28344 IX86_BUILTIN_CVTPD2PS,
28345 IX86_BUILTIN_CVTTPD2DQ,
28346 IX86_BUILTIN_CVTTPD2PI,
28348 IX86_BUILTIN_CVTPI2PD,
28349 IX86_BUILTIN_CVTSI2SD,
28350 IX86_BUILTIN_CVTSI642SD,
28352 IX86_BUILTIN_CVTSD2SI,
28353 IX86_BUILTIN_CVTSD2SI64,
28354 IX86_BUILTIN_CVTSD2SS,
28355 IX86_BUILTIN_CVTSS2SD,
28356 IX86_BUILTIN_CVTTSD2SI,
28357 IX86_BUILTIN_CVTTSD2SI64,
28359 IX86_BUILTIN_CVTPS2DQ,
28360 IX86_BUILTIN_CVTPS2PD,
28361 IX86_BUILTIN_CVTTPS2DQ,
28363 IX86_BUILTIN_MOVNTI,
28364 IX86_BUILTIN_MOVNTI64,
28365 IX86_BUILTIN_MOVNTPD,
28366 IX86_BUILTIN_MOVNTDQ,
28368 IX86_BUILTIN_MOVQ128,
28370 /* SSE2 MMX */
28371 IX86_BUILTIN_MASKMOVDQU,
28372 IX86_BUILTIN_MOVMSKPD,
28373 IX86_BUILTIN_PMOVMSKB128,
28375 IX86_BUILTIN_PACKSSWB128,
28376 IX86_BUILTIN_PACKSSDW128,
28377 IX86_BUILTIN_PACKUSWB128,
28379 IX86_BUILTIN_PADDB128,
28380 IX86_BUILTIN_PADDW128,
28381 IX86_BUILTIN_PADDD128,
28382 IX86_BUILTIN_PADDQ128,
28383 IX86_BUILTIN_PADDSB128,
28384 IX86_BUILTIN_PADDSW128,
28385 IX86_BUILTIN_PADDUSB128,
28386 IX86_BUILTIN_PADDUSW128,
28387 IX86_BUILTIN_PSUBB128,
28388 IX86_BUILTIN_PSUBW128,
28389 IX86_BUILTIN_PSUBD128,
28390 IX86_BUILTIN_PSUBQ128,
28391 IX86_BUILTIN_PSUBSB128,
28392 IX86_BUILTIN_PSUBSW128,
28393 IX86_BUILTIN_PSUBUSB128,
28394 IX86_BUILTIN_PSUBUSW128,
28396 IX86_BUILTIN_PAND128,
28397 IX86_BUILTIN_PANDN128,
28398 IX86_BUILTIN_POR128,
28399 IX86_BUILTIN_PXOR128,
28401 IX86_BUILTIN_PAVGB128,
28402 IX86_BUILTIN_PAVGW128,
28404 IX86_BUILTIN_PCMPEQB128,
28405 IX86_BUILTIN_PCMPEQW128,
28406 IX86_BUILTIN_PCMPEQD128,
28407 IX86_BUILTIN_PCMPGTB128,
28408 IX86_BUILTIN_PCMPGTW128,
28409 IX86_BUILTIN_PCMPGTD128,
28411 IX86_BUILTIN_PMADDWD128,
28413 IX86_BUILTIN_PMAXSW128,
28414 IX86_BUILTIN_PMAXUB128,
28415 IX86_BUILTIN_PMINSW128,
28416 IX86_BUILTIN_PMINUB128,
28418 IX86_BUILTIN_PMULUDQ,
28419 IX86_BUILTIN_PMULUDQ128,
28420 IX86_BUILTIN_PMULHUW128,
28421 IX86_BUILTIN_PMULHW128,
28422 IX86_BUILTIN_PMULLW128,
28424 IX86_BUILTIN_PSADBW128,
28425 IX86_BUILTIN_PSHUFHW,
28426 IX86_BUILTIN_PSHUFLW,
28427 IX86_BUILTIN_PSHUFD,
28429 IX86_BUILTIN_PSLLDQI128,
28430 IX86_BUILTIN_PSLLWI128,
28431 IX86_BUILTIN_PSLLDI128,
28432 IX86_BUILTIN_PSLLQI128,
28433 IX86_BUILTIN_PSRAWI128,
28434 IX86_BUILTIN_PSRADI128,
28435 IX86_BUILTIN_PSRLDQI128,
28436 IX86_BUILTIN_PSRLWI128,
28437 IX86_BUILTIN_PSRLDI128,
28438 IX86_BUILTIN_PSRLQI128,
28440 IX86_BUILTIN_PSLLDQ128,
28441 IX86_BUILTIN_PSLLW128,
28442 IX86_BUILTIN_PSLLD128,
28443 IX86_BUILTIN_PSLLQ128,
28444 IX86_BUILTIN_PSRAW128,
28445 IX86_BUILTIN_PSRAD128,
28446 IX86_BUILTIN_PSRLW128,
28447 IX86_BUILTIN_PSRLD128,
28448 IX86_BUILTIN_PSRLQ128,
28450 IX86_BUILTIN_PUNPCKHBW128,
28451 IX86_BUILTIN_PUNPCKHWD128,
28452 IX86_BUILTIN_PUNPCKHDQ128,
28453 IX86_BUILTIN_PUNPCKHQDQ128,
28454 IX86_BUILTIN_PUNPCKLBW128,
28455 IX86_BUILTIN_PUNPCKLWD128,
28456 IX86_BUILTIN_PUNPCKLDQ128,
28457 IX86_BUILTIN_PUNPCKLQDQ128,
28459 IX86_BUILTIN_CLFLUSH,
28460 IX86_BUILTIN_MFENCE,
28461 IX86_BUILTIN_LFENCE,
28462 IX86_BUILTIN_PAUSE,
28464 IX86_BUILTIN_FNSTENV,
28465 IX86_BUILTIN_FLDENV,
28466 IX86_BUILTIN_FNSTSW,
28467 IX86_BUILTIN_FNCLEX,
28469 IX86_BUILTIN_BSRSI,
28470 IX86_BUILTIN_BSRDI,
28471 IX86_BUILTIN_RDPMC,
28472 IX86_BUILTIN_RDTSC,
28473 IX86_BUILTIN_RDTSCP,
28474 IX86_BUILTIN_ROLQI,
28475 IX86_BUILTIN_ROLHI,
28476 IX86_BUILTIN_RORQI,
28477 IX86_BUILTIN_RORHI,
28479 /* SSE3. */
28480 IX86_BUILTIN_ADDSUBPS,
28481 IX86_BUILTIN_HADDPS,
28482 IX86_BUILTIN_HSUBPS,
28483 IX86_BUILTIN_MOVSHDUP,
28484 IX86_BUILTIN_MOVSLDUP,
28485 IX86_BUILTIN_ADDSUBPD,
28486 IX86_BUILTIN_HADDPD,
28487 IX86_BUILTIN_HSUBPD,
28488 IX86_BUILTIN_LDDQU,
28490 IX86_BUILTIN_MONITOR,
28491 IX86_BUILTIN_MWAIT,
28493 /* SSSE3. */
28494 IX86_BUILTIN_PHADDW,
28495 IX86_BUILTIN_PHADDD,
28496 IX86_BUILTIN_PHADDSW,
28497 IX86_BUILTIN_PHSUBW,
28498 IX86_BUILTIN_PHSUBD,
28499 IX86_BUILTIN_PHSUBSW,
28500 IX86_BUILTIN_PMADDUBSW,
28501 IX86_BUILTIN_PMULHRSW,
28502 IX86_BUILTIN_PSHUFB,
28503 IX86_BUILTIN_PSIGNB,
28504 IX86_BUILTIN_PSIGNW,
28505 IX86_BUILTIN_PSIGND,
28506 IX86_BUILTIN_PALIGNR,
28507 IX86_BUILTIN_PABSB,
28508 IX86_BUILTIN_PABSW,
28509 IX86_BUILTIN_PABSD,
28511 IX86_BUILTIN_PHADDW128,
28512 IX86_BUILTIN_PHADDD128,
28513 IX86_BUILTIN_PHADDSW128,
28514 IX86_BUILTIN_PHSUBW128,
28515 IX86_BUILTIN_PHSUBD128,
28516 IX86_BUILTIN_PHSUBSW128,
28517 IX86_BUILTIN_PMADDUBSW128,
28518 IX86_BUILTIN_PMULHRSW128,
28519 IX86_BUILTIN_PSHUFB128,
28520 IX86_BUILTIN_PSIGNB128,
28521 IX86_BUILTIN_PSIGNW128,
28522 IX86_BUILTIN_PSIGND128,
28523 IX86_BUILTIN_PALIGNR128,
28524 IX86_BUILTIN_PABSB128,
28525 IX86_BUILTIN_PABSW128,
28526 IX86_BUILTIN_PABSD128,
28528 /* AMDFAM10 - SSE4A New Instructions. */
28529 IX86_BUILTIN_MOVNTSD,
28530 IX86_BUILTIN_MOVNTSS,
28531 IX86_BUILTIN_EXTRQI,
28532 IX86_BUILTIN_EXTRQ,
28533 IX86_BUILTIN_INSERTQI,
28534 IX86_BUILTIN_INSERTQ,
28536 /* SSE4.1. */
28537 IX86_BUILTIN_BLENDPD,
28538 IX86_BUILTIN_BLENDPS,
28539 IX86_BUILTIN_BLENDVPD,
28540 IX86_BUILTIN_BLENDVPS,
28541 IX86_BUILTIN_PBLENDVB128,
28542 IX86_BUILTIN_PBLENDW128,
28544 IX86_BUILTIN_DPPD,
28545 IX86_BUILTIN_DPPS,
28547 IX86_BUILTIN_INSERTPS128,
28549 IX86_BUILTIN_MOVNTDQA,
28550 IX86_BUILTIN_MPSADBW128,
28551 IX86_BUILTIN_PACKUSDW128,
28552 IX86_BUILTIN_PCMPEQQ,
28553 IX86_BUILTIN_PHMINPOSUW128,
28555 IX86_BUILTIN_PMAXSB128,
28556 IX86_BUILTIN_PMAXSD128,
28557 IX86_BUILTIN_PMAXUD128,
28558 IX86_BUILTIN_PMAXUW128,
28560 IX86_BUILTIN_PMINSB128,
28561 IX86_BUILTIN_PMINSD128,
28562 IX86_BUILTIN_PMINUD128,
28563 IX86_BUILTIN_PMINUW128,
28565 IX86_BUILTIN_PMOVSXBW128,
28566 IX86_BUILTIN_PMOVSXBD128,
28567 IX86_BUILTIN_PMOVSXBQ128,
28568 IX86_BUILTIN_PMOVSXWD128,
28569 IX86_BUILTIN_PMOVSXWQ128,
28570 IX86_BUILTIN_PMOVSXDQ128,
28572 IX86_BUILTIN_PMOVZXBW128,
28573 IX86_BUILTIN_PMOVZXBD128,
28574 IX86_BUILTIN_PMOVZXBQ128,
28575 IX86_BUILTIN_PMOVZXWD128,
28576 IX86_BUILTIN_PMOVZXWQ128,
28577 IX86_BUILTIN_PMOVZXDQ128,
28579 IX86_BUILTIN_PMULDQ128,
28580 IX86_BUILTIN_PMULLD128,
28582 IX86_BUILTIN_ROUNDSD,
28583 IX86_BUILTIN_ROUNDSS,
28585 IX86_BUILTIN_ROUNDPD,
28586 IX86_BUILTIN_ROUNDPS,
28588 IX86_BUILTIN_FLOORPD,
28589 IX86_BUILTIN_CEILPD,
28590 IX86_BUILTIN_TRUNCPD,
28591 IX86_BUILTIN_RINTPD,
28592 IX86_BUILTIN_ROUNDPD_AZ,
28594 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
28595 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
28596 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
28598 IX86_BUILTIN_FLOORPS,
28599 IX86_BUILTIN_CEILPS,
28600 IX86_BUILTIN_TRUNCPS,
28601 IX86_BUILTIN_RINTPS,
28602 IX86_BUILTIN_ROUNDPS_AZ,
28604 IX86_BUILTIN_FLOORPS_SFIX,
28605 IX86_BUILTIN_CEILPS_SFIX,
28606 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
28608 IX86_BUILTIN_PTESTZ,
28609 IX86_BUILTIN_PTESTC,
28610 IX86_BUILTIN_PTESTNZC,
28612 IX86_BUILTIN_VEC_INIT_V2SI,
28613 IX86_BUILTIN_VEC_INIT_V4HI,
28614 IX86_BUILTIN_VEC_INIT_V8QI,
28615 IX86_BUILTIN_VEC_EXT_V2DF,
28616 IX86_BUILTIN_VEC_EXT_V2DI,
28617 IX86_BUILTIN_VEC_EXT_V4SF,
28618 IX86_BUILTIN_VEC_EXT_V4SI,
28619 IX86_BUILTIN_VEC_EXT_V8HI,
28620 IX86_BUILTIN_VEC_EXT_V2SI,
28621 IX86_BUILTIN_VEC_EXT_V4HI,
28622 IX86_BUILTIN_VEC_EXT_V16QI,
28623 IX86_BUILTIN_VEC_SET_V2DI,
28624 IX86_BUILTIN_VEC_SET_V4SF,
28625 IX86_BUILTIN_VEC_SET_V4SI,
28626 IX86_BUILTIN_VEC_SET_V8HI,
28627 IX86_BUILTIN_VEC_SET_V4HI,
28628 IX86_BUILTIN_VEC_SET_V16QI,
28630 IX86_BUILTIN_VEC_PACK_SFIX,
28631 IX86_BUILTIN_VEC_PACK_SFIX256,
28633 /* SSE4.2. */
28634 IX86_BUILTIN_CRC32QI,
28635 IX86_BUILTIN_CRC32HI,
28636 IX86_BUILTIN_CRC32SI,
28637 IX86_BUILTIN_CRC32DI,
28639 IX86_BUILTIN_PCMPESTRI128,
28640 IX86_BUILTIN_PCMPESTRM128,
28641 IX86_BUILTIN_PCMPESTRA128,
28642 IX86_BUILTIN_PCMPESTRC128,
28643 IX86_BUILTIN_PCMPESTRO128,
28644 IX86_BUILTIN_PCMPESTRS128,
28645 IX86_BUILTIN_PCMPESTRZ128,
28646 IX86_BUILTIN_PCMPISTRI128,
28647 IX86_BUILTIN_PCMPISTRM128,
28648 IX86_BUILTIN_PCMPISTRA128,
28649 IX86_BUILTIN_PCMPISTRC128,
28650 IX86_BUILTIN_PCMPISTRO128,
28651 IX86_BUILTIN_PCMPISTRS128,
28652 IX86_BUILTIN_PCMPISTRZ128,
28654 IX86_BUILTIN_PCMPGTQ,
28656 /* AES instructions */
28657 IX86_BUILTIN_AESENC128,
28658 IX86_BUILTIN_AESENCLAST128,
28659 IX86_BUILTIN_AESDEC128,
28660 IX86_BUILTIN_AESDECLAST128,
28661 IX86_BUILTIN_AESIMC128,
28662 IX86_BUILTIN_AESKEYGENASSIST128,
28664 /* PCLMUL instruction */
28665 IX86_BUILTIN_PCLMULQDQ128,
28667 /* AVX */
28668 IX86_BUILTIN_ADDPD256,
28669 IX86_BUILTIN_ADDPS256,
28670 IX86_BUILTIN_ADDSUBPD256,
28671 IX86_BUILTIN_ADDSUBPS256,
28672 IX86_BUILTIN_ANDPD256,
28673 IX86_BUILTIN_ANDPS256,
28674 IX86_BUILTIN_ANDNPD256,
28675 IX86_BUILTIN_ANDNPS256,
28676 IX86_BUILTIN_BLENDPD256,
28677 IX86_BUILTIN_BLENDPS256,
28678 IX86_BUILTIN_BLENDVPD256,
28679 IX86_BUILTIN_BLENDVPS256,
28680 IX86_BUILTIN_DIVPD256,
28681 IX86_BUILTIN_DIVPS256,
28682 IX86_BUILTIN_DPPS256,
28683 IX86_BUILTIN_HADDPD256,
28684 IX86_BUILTIN_HADDPS256,
28685 IX86_BUILTIN_HSUBPD256,
28686 IX86_BUILTIN_HSUBPS256,
28687 IX86_BUILTIN_MAXPD256,
28688 IX86_BUILTIN_MAXPS256,
28689 IX86_BUILTIN_MINPD256,
28690 IX86_BUILTIN_MINPS256,
28691 IX86_BUILTIN_MULPD256,
28692 IX86_BUILTIN_MULPS256,
28693 IX86_BUILTIN_ORPD256,
28694 IX86_BUILTIN_ORPS256,
28695 IX86_BUILTIN_SHUFPD256,
28696 IX86_BUILTIN_SHUFPS256,
28697 IX86_BUILTIN_SUBPD256,
28698 IX86_BUILTIN_SUBPS256,
28699 IX86_BUILTIN_XORPD256,
28700 IX86_BUILTIN_XORPS256,
28701 IX86_BUILTIN_CMPSD,
28702 IX86_BUILTIN_CMPSS,
28703 IX86_BUILTIN_CMPPD,
28704 IX86_BUILTIN_CMPPS,
28705 IX86_BUILTIN_CMPPD256,
28706 IX86_BUILTIN_CMPPS256,
28707 IX86_BUILTIN_CVTDQ2PD256,
28708 IX86_BUILTIN_CVTDQ2PS256,
28709 IX86_BUILTIN_CVTPD2PS256,
28710 IX86_BUILTIN_CVTPS2DQ256,
28711 IX86_BUILTIN_CVTPS2PD256,
28712 IX86_BUILTIN_CVTTPD2DQ256,
28713 IX86_BUILTIN_CVTPD2DQ256,
28714 IX86_BUILTIN_CVTTPS2DQ256,
28715 IX86_BUILTIN_EXTRACTF128PD256,
28716 IX86_BUILTIN_EXTRACTF128PS256,
28717 IX86_BUILTIN_EXTRACTF128SI256,
28718 IX86_BUILTIN_VZEROALL,
28719 IX86_BUILTIN_VZEROUPPER,
28720 IX86_BUILTIN_VPERMILVARPD,
28721 IX86_BUILTIN_VPERMILVARPS,
28722 IX86_BUILTIN_VPERMILVARPD256,
28723 IX86_BUILTIN_VPERMILVARPS256,
28724 IX86_BUILTIN_VPERMILPD,
28725 IX86_BUILTIN_VPERMILPS,
28726 IX86_BUILTIN_VPERMILPD256,
28727 IX86_BUILTIN_VPERMILPS256,
28728 IX86_BUILTIN_VPERMIL2PD,
28729 IX86_BUILTIN_VPERMIL2PS,
28730 IX86_BUILTIN_VPERMIL2PD256,
28731 IX86_BUILTIN_VPERMIL2PS256,
28732 IX86_BUILTIN_VPERM2F128PD256,
28733 IX86_BUILTIN_VPERM2F128PS256,
28734 IX86_BUILTIN_VPERM2F128SI256,
28735 IX86_BUILTIN_VBROADCASTSS,
28736 IX86_BUILTIN_VBROADCASTSD256,
28737 IX86_BUILTIN_VBROADCASTSS256,
28738 IX86_BUILTIN_VBROADCASTPD256,
28739 IX86_BUILTIN_VBROADCASTPS256,
28740 IX86_BUILTIN_VINSERTF128PD256,
28741 IX86_BUILTIN_VINSERTF128PS256,
28742 IX86_BUILTIN_VINSERTF128SI256,
28743 IX86_BUILTIN_LOADUPD256,
28744 IX86_BUILTIN_LOADUPS256,
28745 IX86_BUILTIN_STOREUPD256,
28746 IX86_BUILTIN_STOREUPS256,
28747 IX86_BUILTIN_LDDQU256,
28748 IX86_BUILTIN_MOVNTDQ256,
28749 IX86_BUILTIN_MOVNTPD256,
28750 IX86_BUILTIN_MOVNTPS256,
28751 IX86_BUILTIN_LOADDQU256,
28752 IX86_BUILTIN_STOREDQU256,
28753 IX86_BUILTIN_MASKLOADPD,
28754 IX86_BUILTIN_MASKLOADPS,
28755 IX86_BUILTIN_MASKSTOREPD,
28756 IX86_BUILTIN_MASKSTOREPS,
28757 IX86_BUILTIN_MASKLOADPD256,
28758 IX86_BUILTIN_MASKLOADPS256,
28759 IX86_BUILTIN_MASKSTOREPD256,
28760 IX86_BUILTIN_MASKSTOREPS256,
28761 IX86_BUILTIN_MOVSHDUP256,
28762 IX86_BUILTIN_MOVSLDUP256,
28763 IX86_BUILTIN_MOVDDUP256,
28765 IX86_BUILTIN_SQRTPD256,
28766 IX86_BUILTIN_SQRTPS256,
28767 IX86_BUILTIN_SQRTPS_NR256,
28768 IX86_BUILTIN_RSQRTPS256,
28769 IX86_BUILTIN_RSQRTPS_NR256,
28771 IX86_BUILTIN_RCPPS256,
28773 IX86_BUILTIN_ROUNDPD256,
28774 IX86_BUILTIN_ROUNDPS256,
28776 IX86_BUILTIN_FLOORPD256,
28777 IX86_BUILTIN_CEILPD256,
28778 IX86_BUILTIN_TRUNCPD256,
28779 IX86_BUILTIN_RINTPD256,
28780 IX86_BUILTIN_ROUNDPD_AZ256,
28782 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
28783 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
28784 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
28786 IX86_BUILTIN_FLOORPS256,
28787 IX86_BUILTIN_CEILPS256,
28788 IX86_BUILTIN_TRUNCPS256,
28789 IX86_BUILTIN_RINTPS256,
28790 IX86_BUILTIN_ROUNDPS_AZ256,
28792 IX86_BUILTIN_FLOORPS_SFIX256,
28793 IX86_BUILTIN_CEILPS_SFIX256,
28794 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
28796 IX86_BUILTIN_UNPCKHPD256,
28797 IX86_BUILTIN_UNPCKLPD256,
28798 IX86_BUILTIN_UNPCKHPS256,
28799 IX86_BUILTIN_UNPCKLPS256,
28801 IX86_BUILTIN_SI256_SI,
28802 IX86_BUILTIN_PS256_PS,
28803 IX86_BUILTIN_PD256_PD,
28804 IX86_BUILTIN_SI_SI256,
28805 IX86_BUILTIN_PS_PS256,
28806 IX86_BUILTIN_PD_PD256,
28808 IX86_BUILTIN_VTESTZPD,
28809 IX86_BUILTIN_VTESTCPD,
28810 IX86_BUILTIN_VTESTNZCPD,
28811 IX86_BUILTIN_VTESTZPS,
28812 IX86_BUILTIN_VTESTCPS,
28813 IX86_BUILTIN_VTESTNZCPS,
28814 IX86_BUILTIN_VTESTZPD256,
28815 IX86_BUILTIN_VTESTCPD256,
28816 IX86_BUILTIN_VTESTNZCPD256,
28817 IX86_BUILTIN_VTESTZPS256,
28818 IX86_BUILTIN_VTESTCPS256,
28819 IX86_BUILTIN_VTESTNZCPS256,
28820 IX86_BUILTIN_PTESTZ256,
28821 IX86_BUILTIN_PTESTC256,
28822 IX86_BUILTIN_PTESTNZC256,
28824 IX86_BUILTIN_MOVMSKPD256,
28825 IX86_BUILTIN_MOVMSKPS256,
28827 /* AVX2 */
28828 IX86_BUILTIN_MPSADBW256,
28829 IX86_BUILTIN_PABSB256,
28830 IX86_BUILTIN_PABSW256,
28831 IX86_BUILTIN_PABSD256,
28832 IX86_BUILTIN_PACKSSDW256,
28833 IX86_BUILTIN_PACKSSWB256,
28834 IX86_BUILTIN_PACKUSDW256,
28835 IX86_BUILTIN_PACKUSWB256,
28836 IX86_BUILTIN_PADDB256,
28837 IX86_BUILTIN_PADDW256,
28838 IX86_BUILTIN_PADDD256,
28839 IX86_BUILTIN_PADDQ256,
28840 IX86_BUILTIN_PADDSB256,
28841 IX86_BUILTIN_PADDSW256,
28842 IX86_BUILTIN_PADDUSB256,
28843 IX86_BUILTIN_PADDUSW256,
28844 IX86_BUILTIN_PALIGNR256,
28845 IX86_BUILTIN_AND256I,
28846 IX86_BUILTIN_ANDNOT256I,
28847 IX86_BUILTIN_PAVGB256,
28848 IX86_BUILTIN_PAVGW256,
28849 IX86_BUILTIN_PBLENDVB256,
28850 IX86_BUILTIN_PBLENDVW256,
28851 IX86_BUILTIN_PCMPEQB256,
28852 IX86_BUILTIN_PCMPEQW256,
28853 IX86_BUILTIN_PCMPEQD256,
28854 IX86_BUILTIN_PCMPEQQ256,
28855 IX86_BUILTIN_PCMPGTB256,
28856 IX86_BUILTIN_PCMPGTW256,
28857 IX86_BUILTIN_PCMPGTD256,
28858 IX86_BUILTIN_PCMPGTQ256,
28859 IX86_BUILTIN_PHADDW256,
28860 IX86_BUILTIN_PHADDD256,
28861 IX86_BUILTIN_PHADDSW256,
28862 IX86_BUILTIN_PHSUBW256,
28863 IX86_BUILTIN_PHSUBD256,
28864 IX86_BUILTIN_PHSUBSW256,
28865 IX86_BUILTIN_PMADDUBSW256,
28866 IX86_BUILTIN_PMADDWD256,
28867 IX86_BUILTIN_PMAXSB256,
28868 IX86_BUILTIN_PMAXSW256,
28869 IX86_BUILTIN_PMAXSD256,
28870 IX86_BUILTIN_PMAXUB256,
28871 IX86_BUILTIN_PMAXUW256,
28872 IX86_BUILTIN_PMAXUD256,
28873 IX86_BUILTIN_PMINSB256,
28874 IX86_BUILTIN_PMINSW256,
28875 IX86_BUILTIN_PMINSD256,
28876 IX86_BUILTIN_PMINUB256,
28877 IX86_BUILTIN_PMINUW256,
28878 IX86_BUILTIN_PMINUD256,
28879 IX86_BUILTIN_PMOVMSKB256,
28880 IX86_BUILTIN_PMOVSXBW256,
28881 IX86_BUILTIN_PMOVSXBD256,
28882 IX86_BUILTIN_PMOVSXBQ256,
28883 IX86_BUILTIN_PMOVSXWD256,
28884 IX86_BUILTIN_PMOVSXWQ256,
28885 IX86_BUILTIN_PMOVSXDQ256,
28886 IX86_BUILTIN_PMOVZXBW256,
28887 IX86_BUILTIN_PMOVZXBD256,
28888 IX86_BUILTIN_PMOVZXBQ256,
28889 IX86_BUILTIN_PMOVZXWD256,
28890 IX86_BUILTIN_PMOVZXWQ256,
28891 IX86_BUILTIN_PMOVZXDQ256,
28892 IX86_BUILTIN_PMULDQ256,
28893 IX86_BUILTIN_PMULHRSW256,
28894 IX86_BUILTIN_PMULHUW256,
28895 IX86_BUILTIN_PMULHW256,
28896 IX86_BUILTIN_PMULLW256,
28897 IX86_BUILTIN_PMULLD256,
28898 IX86_BUILTIN_PMULUDQ256,
28899 IX86_BUILTIN_POR256,
28900 IX86_BUILTIN_PSADBW256,
28901 IX86_BUILTIN_PSHUFB256,
28902 IX86_BUILTIN_PSHUFD256,
28903 IX86_BUILTIN_PSHUFHW256,
28904 IX86_BUILTIN_PSHUFLW256,
28905 IX86_BUILTIN_PSIGNB256,
28906 IX86_BUILTIN_PSIGNW256,
28907 IX86_BUILTIN_PSIGND256,
28908 IX86_BUILTIN_PSLLDQI256,
28909 IX86_BUILTIN_PSLLWI256,
28910 IX86_BUILTIN_PSLLW256,
28911 IX86_BUILTIN_PSLLDI256,
28912 IX86_BUILTIN_PSLLD256,
28913 IX86_BUILTIN_PSLLQI256,
28914 IX86_BUILTIN_PSLLQ256,
28915 IX86_BUILTIN_PSRAWI256,
28916 IX86_BUILTIN_PSRAW256,
28917 IX86_BUILTIN_PSRADI256,
28918 IX86_BUILTIN_PSRAD256,
28919 IX86_BUILTIN_PSRLDQI256,
28920 IX86_BUILTIN_PSRLWI256,
28921 IX86_BUILTIN_PSRLW256,
28922 IX86_BUILTIN_PSRLDI256,
28923 IX86_BUILTIN_PSRLD256,
28924 IX86_BUILTIN_PSRLQI256,
28925 IX86_BUILTIN_PSRLQ256,
28926 IX86_BUILTIN_PSUBB256,
28927 IX86_BUILTIN_PSUBW256,
28928 IX86_BUILTIN_PSUBD256,
28929 IX86_BUILTIN_PSUBQ256,
28930 IX86_BUILTIN_PSUBSB256,
28931 IX86_BUILTIN_PSUBSW256,
28932 IX86_BUILTIN_PSUBUSB256,
28933 IX86_BUILTIN_PSUBUSW256,
28934 IX86_BUILTIN_PUNPCKHBW256,
28935 IX86_BUILTIN_PUNPCKHWD256,
28936 IX86_BUILTIN_PUNPCKHDQ256,
28937 IX86_BUILTIN_PUNPCKHQDQ256,
28938 IX86_BUILTIN_PUNPCKLBW256,
28939 IX86_BUILTIN_PUNPCKLWD256,
28940 IX86_BUILTIN_PUNPCKLDQ256,
28941 IX86_BUILTIN_PUNPCKLQDQ256,
28942 IX86_BUILTIN_PXOR256,
28943 IX86_BUILTIN_MOVNTDQA256,
28944 IX86_BUILTIN_VBROADCASTSS_PS,
28945 IX86_BUILTIN_VBROADCASTSS_PS256,
28946 IX86_BUILTIN_VBROADCASTSD_PD256,
28947 IX86_BUILTIN_VBROADCASTSI256,
28948 IX86_BUILTIN_PBLENDD256,
28949 IX86_BUILTIN_PBLENDD128,
28950 IX86_BUILTIN_PBROADCASTB256,
28951 IX86_BUILTIN_PBROADCASTW256,
28952 IX86_BUILTIN_PBROADCASTD256,
28953 IX86_BUILTIN_PBROADCASTQ256,
28954 IX86_BUILTIN_PBROADCASTB128,
28955 IX86_BUILTIN_PBROADCASTW128,
28956 IX86_BUILTIN_PBROADCASTD128,
28957 IX86_BUILTIN_PBROADCASTQ128,
28958 IX86_BUILTIN_VPERMVARSI256,
28959 IX86_BUILTIN_VPERMDF256,
28960 IX86_BUILTIN_VPERMVARSF256,
28961 IX86_BUILTIN_VPERMDI256,
28962 IX86_BUILTIN_VPERMTI256,
28963 IX86_BUILTIN_VEXTRACT128I256,
28964 IX86_BUILTIN_VINSERT128I256,
28965 IX86_BUILTIN_MASKLOADD,
28966 IX86_BUILTIN_MASKLOADQ,
28967 IX86_BUILTIN_MASKLOADD256,
28968 IX86_BUILTIN_MASKLOADQ256,
28969 IX86_BUILTIN_MASKSTORED,
28970 IX86_BUILTIN_MASKSTOREQ,
28971 IX86_BUILTIN_MASKSTORED256,
28972 IX86_BUILTIN_MASKSTOREQ256,
28973 IX86_BUILTIN_PSLLVV4DI,
28974 IX86_BUILTIN_PSLLVV2DI,
28975 IX86_BUILTIN_PSLLVV8SI,
28976 IX86_BUILTIN_PSLLVV4SI,
28977 IX86_BUILTIN_PSRAVV8SI,
28978 IX86_BUILTIN_PSRAVV4SI,
28979 IX86_BUILTIN_PSRLVV4DI,
28980 IX86_BUILTIN_PSRLVV2DI,
28981 IX86_BUILTIN_PSRLVV8SI,
28982 IX86_BUILTIN_PSRLVV4SI,
28984 IX86_BUILTIN_GATHERSIV2DF,
28985 IX86_BUILTIN_GATHERSIV4DF,
28986 IX86_BUILTIN_GATHERDIV2DF,
28987 IX86_BUILTIN_GATHERDIV4DF,
28988 IX86_BUILTIN_GATHERSIV4SF,
28989 IX86_BUILTIN_GATHERSIV8SF,
28990 IX86_BUILTIN_GATHERDIV4SF,
28991 IX86_BUILTIN_GATHERDIV8SF,
28992 IX86_BUILTIN_GATHERSIV2DI,
28993 IX86_BUILTIN_GATHERSIV4DI,
28994 IX86_BUILTIN_GATHERDIV2DI,
28995 IX86_BUILTIN_GATHERDIV4DI,
28996 IX86_BUILTIN_GATHERSIV4SI,
28997 IX86_BUILTIN_GATHERSIV8SI,
28998 IX86_BUILTIN_GATHERDIV4SI,
28999 IX86_BUILTIN_GATHERDIV8SI,
29001 /* AVX512F */
29002 IX86_BUILTIN_SI512_SI256,
29003 IX86_BUILTIN_PD512_PD256,
29004 IX86_BUILTIN_PS512_PS256,
29005 IX86_BUILTIN_SI512_SI,
29006 IX86_BUILTIN_PD512_PD,
29007 IX86_BUILTIN_PS512_PS,
29008 IX86_BUILTIN_ADDPD512,
29009 IX86_BUILTIN_ADDPS512,
29010 IX86_BUILTIN_ADDSD_ROUND,
29011 IX86_BUILTIN_ADDSS_ROUND,
29012 IX86_BUILTIN_ALIGND512,
29013 IX86_BUILTIN_ALIGNQ512,
29014 IX86_BUILTIN_BLENDMD512,
29015 IX86_BUILTIN_BLENDMPD512,
29016 IX86_BUILTIN_BLENDMPS512,
29017 IX86_BUILTIN_BLENDMQ512,
29018 IX86_BUILTIN_BROADCASTF32X4_512,
29019 IX86_BUILTIN_BROADCASTF64X4_512,
29020 IX86_BUILTIN_BROADCASTI32X4_512,
29021 IX86_BUILTIN_BROADCASTI64X4_512,
29022 IX86_BUILTIN_BROADCASTSD512,
29023 IX86_BUILTIN_BROADCASTSS512,
29024 IX86_BUILTIN_CMPD512,
29025 IX86_BUILTIN_CMPPD512,
29026 IX86_BUILTIN_CMPPS512,
29027 IX86_BUILTIN_CMPQ512,
29028 IX86_BUILTIN_CMPSD_MASK,
29029 IX86_BUILTIN_CMPSS_MASK,
29030 IX86_BUILTIN_COMIDF,
29031 IX86_BUILTIN_COMISF,
29032 IX86_BUILTIN_COMPRESSPD512,
29033 IX86_BUILTIN_COMPRESSPDSTORE512,
29034 IX86_BUILTIN_COMPRESSPS512,
29035 IX86_BUILTIN_COMPRESSPSSTORE512,
29036 IX86_BUILTIN_CVTDQ2PD512,
29037 IX86_BUILTIN_CVTDQ2PS512,
29038 IX86_BUILTIN_CVTPD2DQ512,
29039 IX86_BUILTIN_CVTPD2PS512,
29040 IX86_BUILTIN_CVTPD2UDQ512,
29041 IX86_BUILTIN_CVTPH2PS512,
29042 IX86_BUILTIN_CVTPS2DQ512,
29043 IX86_BUILTIN_CVTPS2PD512,
29044 IX86_BUILTIN_CVTPS2PH512,
29045 IX86_BUILTIN_CVTPS2UDQ512,
29046 IX86_BUILTIN_CVTSD2SS_ROUND,
29047 IX86_BUILTIN_CVTSI2SD64,
29048 IX86_BUILTIN_CVTSI2SS32,
29049 IX86_BUILTIN_CVTSI2SS64,
29050 IX86_BUILTIN_CVTSS2SD_ROUND,
29051 IX86_BUILTIN_CVTTPD2DQ512,
29052 IX86_BUILTIN_CVTTPD2UDQ512,
29053 IX86_BUILTIN_CVTTPS2DQ512,
29054 IX86_BUILTIN_CVTTPS2UDQ512,
29055 IX86_BUILTIN_CVTUDQ2PD512,
29056 IX86_BUILTIN_CVTUDQ2PS512,
29057 IX86_BUILTIN_CVTUSI2SD32,
29058 IX86_BUILTIN_CVTUSI2SD64,
29059 IX86_BUILTIN_CVTUSI2SS32,
29060 IX86_BUILTIN_CVTUSI2SS64,
29061 IX86_BUILTIN_DIVPD512,
29062 IX86_BUILTIN_DIVPS512,
29063 IX86_BUILTIN_DIVSD_ROUND,
29064 IX86_BUILTIN_DIVSS_ROUND,
29065 IX86_BUILTIN_EXPANDPD512,
29066 IX86_BUILTIN_EXPANDPD512Z,
29067 IX86_BUILTIN_EXPANDPDLOAD512,
29068 IX86_BUILTIN_EXPANDPDLOAD512Z,
29069 IX86_BUILTIN_EXPANDPS512,
29070 IX86_BUILTIN_EXPANDPS512Z,
29071 IX86_BUILTIN_EXPANDPSLOAD512,
29072 IX86_BUILTIN_EXPANDPSLOAD512Z,
29073 IX86_BUILTIN_EXTRACTF32X4,
29074 IX86_BUILTIN_EXTRACTF64X4,
29075 IX86_BUILTIN_EXTRACTI32X4,
29076 IX86_BUILTIN_EXTRACTI64X4,
29077 IX86_BUILTIN_FIXUPIMMPD512_MASK,
29078 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
29079 IX86_BUILTIN_FIXUPIMMPS512_MASK,
29080 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
29081 IX86_BUILTIN_FIXUPIMMSD128_MASK,
29082 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
29083 IX86_BUILTIN_FIXUPIMMSS128_MASK,
29084 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
29085 IX86_BUILTIN_GETEXPPD512,
29086 IX86_BUILTIN_GETEXPPS512,
29087 IX86_BUILTIN_GETEXPSD128,
29088 IX86_BUILTIN_GETEXPSS128,
29089 IX86_BUILTIN_GETMANTPD512,
29090 IX86_BUILTIN_GETMANTPS512,
29091 IX86_BUILTIN_GETMANTSD128,
29092 IX86_BUILTIN_GETMANTSS128,
29093 IX86_BUILTIN_INSERTF32X4,
29094 IX86_BUILTIN_INSERTF64X4,
29095 IX86_BUILTIN_INSERTI32X4,
29096 IX86_BUILTIN_INSERTI64X4,
29097 IX86_BUILTIN_LOADAPD512,
29098 IX86_BUILTIN_LOADAPS512,
29099 IX86_BUILTIN_LOADDQUDI512,
29100 IX86_BUILTIN_LOADDQUSI512,
29101 IX86_BUILTIN_LOADUPD512,
29102 IX86_BUILTIN_LOADUPS512,
29103 IX86_BUILTIN_MAXPD512,
29104 IX86_BUILTIN_MAXPS512,
29105 IX86_BUILTIN_MAXSD_ROUND,
29106 IX86_BUILTIN_MAXSS_ROUND,
29107 IX86_BUILTIN_MINPD512,
29108 IX86_BUILTIN_MINPS512,
29109 IX86_BUILTIN_MINSD_ROUND,
29110 IX86_BUILTIN_MINSS_ROUND,
29111 IX86_BUILTIN_MOVAPD512,
29112 IX86_BUILTIN_MOVAPS512,
29113 IX86_BUILTIN_MOVDDUP512,
29114 IX86_BUILTIN_MOVDQA32LOAD512,
29115 IX86_BUILTIN_MOVDQA32STORE512,
29116 IX86_BUILTIN_MOVDQA32_512,
29117 IX86_BUILTIN_MOVDQA64LOAD512,
29118 IX86_BUILTIN_MOVDQA64STORE512,
29119 IX86_BUILTIN_MOVDQA64_512,
29120 IX86_BUILTIN_MOVNTDQ512,
29121 IX86_BUILTIN_MOVNTDQA512,
29122 IX86_BUILTIN_MOVNTPD512,
29123 IX86_BUILTIN_MOVNTPS512,
29124 IX86_BUILTIN_MOVSHDUP512,
29125 IX86_BUILTIN_MOVSLDUP512,
29126 IX86_BUILTIN_MULPD512,
29127 IX86_BUILTIN_MULPS512,
29128 IX86_BUILTIN_MULSD_ROUND,
29129 IX86_BUILTIN_MULSS_ROUND,
29130 IX86_BUILTIN_PABSD512,
29131 IX86_BUILTIN_PABSQ512,
29132 IX86_BUILTIN_PADDD512,
29133 IX86_BUILTIN_PADDQ512,
29134 IX86_BUILTIN_PANDD512,
29135 IX86_BUILTIN_PANDND512,
29136 IX86_BUILTIN_PANDNQ512,
29137 IX86_BUILTIN_PANDQ512,
29138 IX86_BUILTIN_PBROADCASTD512,
29139 IX86_BUILTIN_PBROADCASTD512_GPR,
29140 IX86_BUILTIN_PBROADCASTMB512,
29141 IX86_BUILTIN_PBROADCASTMW512,
29142 IX86_BUILTIN_PBROADCASTQ512,
29143 IX86_BUILTIN_PBROADCASTQ512_GPR,
29144 IX86_BUILTIN_PCMPEQD512_MASK,
29145 IX86_BUILTIN_PCMPEQQ512_MASK,
29146 IX86_BUILTIN_PCMPGTD512_MASK,
29147 IX86_BUILTIN_PCMPGTQ512_MASK,
29148 IX86_BUILTIN_PCOMPRESSD512,
29149 IX86_BUILTIN_PCOMPRESSDSTORE512,
29150 IX86_BUILTIN_PCOMPRESSQ512,
29151 IX86_BUILTIN_PCOMPRESSQSTORE512,
29152 IX86_BUILTIN_PEXPANDD512,
29153 IX86_BUILTIN_PEXPANDD512Z,
29154 IX86_BUILTIN_PEXPANDDLOAD512,
29155 IX86_BUILTIN_PEXPANDDLOAD512Z,
29156 IX86_BUILTIN_PEXPANDQ512,
29157 IX86_BUILTIN_PEXPANDQ512Z,
29158 IX86_BUILTIN_PEXPANDQLOAD512,
29159 IX86_BUILTIN_PEXPANDQLOAD512Z,
29160 IX86_BUILTIN_PMAXSD512,
29161 IX86_BUILTIN_PMAXSQ512,
29162 IX86_BUILTIN_PMAXUD512,
29163 IX86_BUILTIN_PMAXUQ512,
29164 IX86_BUILTIN_PMINSD512,
29165 IX86_BUILTIN_PMINSQ512,
29166 IX86_BUILTIN_PMINUD512,
29167 IX86_BUILTIN_PMINUQ512,
29168 IX86_BUILTIN_PMOVDB512,
29169 IX86_BUILTIN_PMOVDB512_MEM,
29170 IX86_BUILTIN_PMOVDW512,
29171 IX86_BUILTIN_PMOVDW512_MEM,
29172 IX86_BUILTIN_PMOVQB512,
29173 IX86_BUILTIN_PMOVQB512_MEM,
29174 IX86_BUILTIN_PMOVQD512,
29175 IX86_BUILTIN_PMOVQD512_MEM,
29176 IX86_BUILTIN_PMOVQW512,
29177 IX86_BUILTIN_PMOVQW512_MEM,
29178 IX86_BUILTIN_PMOVSDB512,
29179 IX86_BUILTIN_PMOVSDB512_MEM,
29180 IX86_BUILTIN_PMOVSDW512,
29181 IX86_BUILTIN_PMOVSDW512_MEM,
29182 IX86_BUILTIN_PMOVSQB512,
29183 IX86_BUILTIN_PMOVSQB512_MEM,
29184 IX86_BUILTIN_PMOVSQD512,
29185 IX86_BUILTIN_PMOVSQD512_MEM,
29186 IX86_BUILTIN_PMOVSQW512,
29187 IX86_BUILTIN_PMOVSQW512_MEM,
29188 IX86_BUILTIN_PMOVSXBD512,
29189 IX86_BUILTIN_PMOVSXBQ512,
29190 IX86_BUILTIN_PMOVSXDQ512,
29191 IX86_BUILTIN_PMOVSXWD512,
29192 IX86_BUILTIN_PMOVSXWQ512,
29193 IX86_BUILTIN_PMOVUSDB512,
29194 IX86_BUILTIN_PMOVUSDB512_MEM,
29195 IX86_BUILTIN_PMOVUSDW512,
29196 IX86_BUILTIN_PMOVUSDW512_MEM,
29197 IX86_BUILTIN_PMOVUSQB512,
29198 IX86_BUILTIN_PMOVUSQB512_MEM,
29199 IX86_BUILTIN_PMOVUSQD512,
29200 IX86_BUILTIN_PMOVUSQD512_MEM,
29201 IX86_BUILTIN_PMOVUSQW512,
29202 IX86_BUILTIN_PMOVUSQW512_MEM,
29203 IX86_BUILTIN_PMOVZXBD512,
29204 IX86_BUILTIN_PMOVZXBQ512,
29205 IX86_BUILTIN_PMOVZXDQ512,
29206 IX86_BUILTIN_PMOVZXWD512,
29207 IX86_BUILTIN_PMOVZXWQ512,
29208 IX86_BUILTIN_PMULDQ512,
29209 IX86_BUILTIN_PMULLD512,
29210 IX86_BUILTIN_PMULUDQ512,
29211 IX86_BUILTIN_PORD512,
29212 IX86_BUILTIN_PORQ512,
29213 IX86_BUILTIN_PROLD512,
29214 IX86_BUILTIN_PROLQ512,
29215 IX86_BUILTIN_PROLVD512,
29216 IX86_BUILTIN_PROLVQ512,
29217 IX86_BUILTIN_PRORD512,
29218 IX86_BUILTIN_PRORQ512,
29219 IX86_BUILTIN_PRORVD512,
29220 IX86_BUILTIN_PRORVQ512,
29221 IX86_BUILTIN_PSHUFD512,
29222 IX86_BUILTIN_PSLLD512,
29223 IX86_BUILTIN_PSLLDI512,
29224 IX86_BUILTIN_PSLLQ512,
29225 IX86_BUILTIN_PSLLQI512,
29226 IX86_BUILTIN_PSLLVV16SI,
29227 IX86_BUILTIN_PSLLVV8DI,
29228 IX86_BUILTIN_PSRAD512,
29229 IX86_BUILTIN_PSRADI512,
29230 IX86_BUILTIN_PSRAQ512,
29231 IX86_BUILTIN_PSRAQI512,
29232 IX86_BUILTIN_PSRAVV16SI,
29233 IX86_BUILTIN_PSRAVV8DI,
29234 IX86_BUILTIN_PSRLD512,
29235 IX86_BUILTIN_PSRLDI512,
29236 IX86_BUILTIN_PSRLQ512,
29237 IX86_BUILTIN_PSRLQI512,
29238 IX86_BUILTIN_PSRLVV16SI,
29239 IX86_BUILTIN_PSRLVV8DI,
29240 IX86_BUILTIN_PSUBD512,
29241 IX86_BUILTIN_PSUBQ512,
29242 IX86_BUILTIN_PTESTMD512,
29243 IX86_BUILTIN_PTESTMQ512,
29244 IX86_BUILTIN_PTESTNMD512,
29245 IX86_BUILTIN_PTESTNMQ512,
29246 IX86_BUILTIN_PUNPCKHDQ512,
29247 IX86_BUILTIN_PUNPCKHQDQ512,
29248 IX86_BUILTIN_PUNPCKLDQ512,
29249 IX86_BUILTIN_PUNPCKLQDQ512,
29250 IX86_BUILTIN_PXORD512,
29251 IX86_BUILTIN_PXORQ512,
29252 IX86_BUILTIN_RCP14PD512,
29253 IX86_BUILTIN_RCP14PS512,
29254 IX86_BUILTIN_RCP14SD,
29255 IX86_BUILTIN_RCP14SS,
29256 IX86_BUILTIN_RNDSCALEPD,
29257 IX86_BUILTIN_RNDSCALEPS,
29258 IX86_BUILTIN_RNDSCALESD,
29259 IX86_BUILTIN_RNDSCALESS,
29260 IX86_BUILTIN_RSQRT14PD512,
29261 IX86_BUILTIN_RSQRT14PS512,
29262 IX86_BUILTIN_RSQRT14SD,
29263 IX86_BUILTIN_RSQRT14SS,
29264 IX86_BUILTIN_SCALEFPD512,
29265 IX86_BUILTIN_SCALEFPS512,
29266 IX86_BUILTIN_SCALEFSD,
29267 IX86_BUILTIN_SCALEFSS,
29268 IX86_BUILTIN_SHUFPD512,
29269 IX86_BUILTIN_SHUFPS512,
29270 IX86_BUILTIN_SHUF_F32x4,
29271 IX86_BUILTIN_SHUF_F64x2,
29272 IX86_BUILTIN_SHUF_I32x4,
29273 IX86_BUILTIN_SHUF_I64x2,
29274 IX86_BUILTIN_SQRTPD512,
29275 IX86_BUILTIN_SQRTPD512_MASK,
29276 IX86_BUILTIN_SQRTPS512_MASK,
29277 IX86_BUILTIN_SQRTPS_NR512,
29278 IX86_BUILTIN_SQRTSD_ROUND,
29279 IX86_BUILTIN_SQRTSS_ROUND,
29280 IX86_BUILTIN_STOREAPD512,
29281 IX86_BUILTIN_STOREAPS512,
29282 IX86_BUILTIN_STOREDQUDI512,
29283 IX86_BUILTIN_STOREDQUSI512,
29284 IX86_BUILTIN_STOREUPD512,
29285 IX86_BUILTIN_STOREUPS512,
29286 IX86_BUILTIN_SUBPD512,
29287 IX86_BUILTIN_SUBPS512,
29288 IX86_BUILTIN_SUBSD_ROUND,
29289 IX86_BUILTIN_SUBSS_ROUND,
29290 IX86_BUILTIN_UCMPD512,
29291 IX86_BUILTIN_UCMPQ512,
29292 IX86_BUILTIN_UNPCKHPD512,
29293 IX86_BUILTIN_UNPCKHPS512,
29294 IX86_BUILTIN_UNPCKLPD512,
29295 IX86_BUILTIN_UNPCKLPS512,
29296 IX86_BUILTIN_VCVTSD2SI32,
29297 IX86_BUILTIN_VCVTSD2SI64,
29298 IX86_BUILTIN_VCVTSD2USI32,
29299 IX86_BUILTIN_VCVTSD2USI64,
29300 IX86_BUILTIN_VCVTSS2SI32,
29301 IX86_BUILTIN_VCVTSS2SI64,
29302 IX86_BUILTIN_VCVTSS2USI32,
29303 IX86_BUILTIN_VCVTSS2USI64,
29304 IX86_BUILTIN_VCVTTSD2SI32,
29305 IX86_BUILTIN_VCVTTSD2SI64,
29306 IX86_BUILTIN_VCVTTSD2USI32,
29307 IX86_BUILTIN_VCVTTSD2USI64,
29308 IX86_BUILTIN_VCVTTSS2SI32,
29309 IX86_BUILTIN_VCVTTSS2SI64,
29310 IX86_BUILTIN_VCVTTSS2USI32,
29311 IX86_BUILTIN_VCVTTSS2USI64,
29312 IX86_BUILTIN_VFMADDPD512_MASK,
29313 IX86_BUILTIN_VFMADDPD512_MASK3,
29314 IX86_BUILTIN_VFMADDPD512_MASKZ,
29315 IX86_BUILTIN_VFMADDPS512_MASK,
29316 IX86_BUILTIN_VFMADDPS512_MASK3,
29317 IX86_BUILTIN_VFMADDPS512_MASKZ,
29318 IX86_BUILTIN_VFMADDSD3_ROUND,
29319 IX86_BUILTIN_VFMADDSS3_ROUND,
29320 IX86_BUILTIN_VFMADDSUBPD512_MASK,
29321 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
29322 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
29323 IX86_BUILTIN_VFMADDSUBPS512_MASK,
29324 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
29325 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
29326 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
29327 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
29328 IX86_BUILTIN_VFMSUBPD512_MASK3,
29329 IX86_BUILTIN_VFMSUBPS512_MASK3,
29330 IX86_BUILTIN_VFMSUBSD3_MASK3,
29331 IX86_BUILTIN_VFMSUBSS3_MASK3,
29332 IX86_BUILTIN_VFNMADDPD512_MASK,
29333 IX86_BUILTIN_VFNMADDPS512_MASK,
29334 IX86_BUILTIN_VFNMSUBPD512_MASK,
29335 IX86_BUILTIN_VFNMSUBPD512_MASK3,
29336 IX86_BUILTIN_VFNMSUBPS512_MASK,
29337 IX86_BUILTIN_VFNMSUBPS512_MASK3,
29338 IX86_BUILTIN_VPCLZCNTD512,
29339 IX86_BUILTIN_VPCLZCNTQ512,
29340 IX86_BUILTIN_VPCONFLICTD512,
29341 IX86_BUILTIN_VPCONFLICTQ512,
29342 IX86_BUILTIN_VPERMDF512,
29343 IX86_BUILTIN_VPERMDI512,
29344 IX86_BUILTIN_VPERMI2VARD512,
29345 IX86_BUILTIN_VPERMI2VARPD512,
29346 IX86_BUILTIN_VPERMI2VARPS512,
29347 IX86_BUILTIN_VPERMI2VARQ512,
29348 IX86_BUILTIN_VPERMILPD512,
29349 IX86_BUILTIN_VPERMILPS512,
29350 IX86_BUILTIN_VPERMILVARPD512,
29351 IX86_BUILTIN_VPERMILVARPS512,
29352 IX86_BUILTIN_VPERMT2VARD512,
29353 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
29354 IX86_BUILTIN_VPERMT2VARPD512,
29355 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
29356 IX86_BUILTIN_VPERMT2VARPS512,
29357 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
29358 IX86_BUILTIN_VPERMT2VARQ512,
29359 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
29360 IX86_BUILTIN_VPERMVARDF512,
29361 IX86_BUILTIN_VPERMVARDI512,
29362 IX86_BUILTIN_VPERMVARSF512,
29363 IX86_BUILTIN_VPERMVARSI512,
29364 IX86_BUILTIN_VTERNLOGD512_MASK,
29365 IX86_BUILTIN_VTERNLOGD512_MASKZ,
29366 IX86_BUILTIN_VTERNLOGQ512_MASK,
29367 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
29369 /* Mask arithmetic operations */
29370 IX86_BUILTIN_KAND16,
29371 IX86_BUILTIN_KANDN16,
29372 IX86_BUILTIN_KNOT16,
29373 IX86_BUILTIN_KOR16,
29374 IX86_BUILTIN_KORTESTC16,
29375 IX86_BUILTIN_KORTESTZ16,
29376 IX86_BUILTIN_KUNPCKBW,
29377 IX86_BUILTIN_KXNOR16,
29378 IX86_BUILTIN_KXOR16,
29379 IX86_BUILTIN_KMOV16,
29381 /* AVX512VL. */
29382 IX86_BUILTIN_PMOVUSQD256_MEM,
29383 IX86_BUILTIN_PMOVUSQD128_MEM,
29384 IX86_BUILTIN_PMOVSQD256_MEM,
29385 IX86_BUILTIN_PMOVSQD128_MEM,
29386 IX86_BUILTIN_PMOVQD256_MEM,
29387 IX86_BUILTIN_PMOVQD128_MEM,
29388 IX86_BUILTIN_PMOVUSQW256_MEM,
29389 IX86_BUILTIN_PMOVUSQW128_MEM,
29390 IX86_BUILTIN_PMOVSQW256_MEM,
29391 IX86_BUILTIN_PMOVSQW128_MEM,
29392 IX86_BUILTIN_PMOVQW256_MEM,
29393 IX86_BUILTIN_PMOVQW128_MEM,
29394 IX86_BUILTIN_PMOVUSQB256_MEM,
29395 IX86_BUILTIN_PMOVUSQB128_MEM,
29396 IX86_BUILTIN_PMOVSQB256_MEM,
29397 IX86_BUILTIN_PMOVSQB128_MEM,
29398 IX86_BUILTIN_PMOVQB256_MEM,
29399 IX86_BUILTIN_PMOVQB128_MEM,
29400 IX86_BUILTIN_PMOVUSDW256_MEM,
29401 IX86_BUILTIN_PMOVUSDW128_MEM,
29402 IX86_BUILTIN_PMOVSDW256_MEM,
29403 IX86_BUILTIN_PMOVSDW128_MEM,
29404 IX86_BUILTIN_PMOVDW256_MEM,
29405 IX86_BUILTIN_PMOVDW128_MEM,
29406 IX86_BUILTIN_PMOVUSDB256_MEM,
29407 IX86_BUILTIN_PMOVUSDB128_MEM,
29408 IX86_BUILTIN_PMOVSDB256_MEM,
29409 IX86_BUILTIN_PMOVSDB128_MEM,
29410 IX86_BUILTIN_PMOVDB256_MEM,
29411 IX86_BUILTIN_PMOVDB128_MEM,
29412 IX86_BUILTIN_MOVDQA64LOAD256_MASK,
29413 IX86_BUILTIN_MOVDQA64LOAD128_MASK,
29414 IX86_BUILTIN_MOVDQA32LOAD256_MASK,
29415 IX86_BUILTIN_MOVDQA32LOAD128_MASK,
29416 IX86_BUILTIN_MOVDQA64STORE256_MASK,
29417 IX86_BUILTIN_MOVDQA64STORE128_MASK,
29418 IX86_BUILTIN_MOVDQA32STORE256_MASK,
29419 IX86_BUILTIN_MOVDQA32STORE128_MASK,
29420 IX86_BUILTIN_LOADAPD256_MASK,
29421 IX86_BUILTIN_LOADAPD128_MASK,
29422 IX86_BUILTIN_LOADAPS256_MASK,
29423 IX86_BUILTIN_LOADAPS128_MASK,
29424 IX86_BUILTIN_STOREAPD256_MASK,
29425 IX86_BUILTIN_STOREAPD128_MASK,
29426 IX86_BUILTIN_STOREAPS256_MASK,
29427 IX86_BUILTIN_STOREAPS128_MASK,
29428 IX86_BUILTIN_LOADUPD256_MASK,
29429 IX86_BUILTIN_LOADUPD128_MASK,
29430 IX86_BUILTIN_LOADUPS256_MASK,
29431 IX86_BUILTIN_LOADUPS128_MASK,
29432 IX86_BUILTIN_STOREUPD256_MASK,
29433 IX86_BUILTIN_STOREUPD128_MASK,
29434 IX86_BUILTIN_STOREUPS256_MASK,
29435 IX86_BUILTIN_STOREUPS128_MASK,
29436 IX86_BUILTIN_LOADDQUDI256_MASK,
29437 IX86_BUILTIN_LOADDQUDI128_MASK,
29438 IX86_BUILTIN_LOADDQUSI256_MASK,
29439 IX86_BUILTIN_LOADDQUSI128_MASK,
29440 IX86_BUILTIN_LOADDQUHI256_MASK,
29441 IX86_BUILTIN_LOADDQUHI128_MASK,
29442 IX86_BUILTIN_LOADDQUQI256_MASK,
29443 IX86_BUILTIN_LOADDQUQI128_MASK,
29444 IX86_BUILTIN_STOREDQUDI256_MASK,
29445 IX86_BUILTIN_STOREDQUDI128_MASK,
29446 IX86_BUILTIN_STOREDQUSI256_MASK,
29447 IX86_BUILTIN_STOREDQUSI128_MASK,
29448 IX86_BUILTIN_STOREDQUHI256_MASK,
29449 IX86_BUILTIN_STOREDQUHI128_MASK,
29450 IX86_BUILTIN_STOREDQUQI256_MASK,
29451 IX86_BUILTIN_STOREDQUQI128_MASK,
29452 IX86_BUILTIN_COMPRESSPDSTORE256,
29453 IX86_BUILTIN_COMPRESSPDSTORE128,
29454 IX86_BUILTIN_COMPRESSPSSTORE256,
29455 IX86_BUILTIN_COMPRESSPSSTORE128,
29456 IX86_BUILTIN_PCOMPRESSQSTORE256,
29457 IX86_BUILTIN_PCOMPRESSQSTORE128,
29458 IX86_BUILTIN_PCOMPRESSDSTORE256,
29459 IX86_BUILTIN_PCOMPRESSDSTORE128,
29460 IX86_BUILTIN_EXPANDPDLOAD256,
29461 IX86_BUILTIN_EXPANDPDLOAD128,
29462 IX86_BUILTIN_EXPANDPSLOAD256,
29463 IX86_BUILTIN_EXPANDPSLOAD128,
29464 IX86_BUILTIN_PEXPANDQLOAD256,
29465 IX86_BUILTIN_PEXPANDQLOAD128,
29466 IX86_BUILTIN_PEXPANDDLOAD256,
29467 IX86_BUILTIN_PEXPANDDLOAD128,
29468 IX86_BUILTIN_EXPANDPDLOAD256Z,
29469 IX86_BUILTIN_EXPANDPDLOAD128Z,
29470 IX86_BUILTIN_EXPANDPSLOAD256Z,
29471 IX86_BUILTIN_EXPANDPSLOAD128Z,
29472 IX86_BUILTIN_PEXPANDQLOAD256Z,
29473 IX86_BUILTIN_PEXPANDQLOAD128Z,
29474 IX86_BUILTIN_PEXPANDDLOAD256Z,
29475 IX86_BUILTIN_PEXPANDDLOAD128Z,
29476 IX86_BUILTIN_PALIGNR256_MASK,
29477 IX86_BUILTIN_PALIGNR128_MASK,
29478 IX86_BUILTIN_MOVDQA64_256_MASK,
29479 IX86_BUILTIN_MOVDQA64_128_MASK,
29480 IX86_BUILTIN_MOVDQA32_256_MASK,
29481 IX86_BUILTIN_MOVDQA32_128_MASK,
29482 IX86_BUILTIN_MOVAPD256_MASK,
29483 IX86_BUILTIN_MOVAPD128_MASK,
29484 IX86_BUILTIN_MOVAPS256_MASK,
29485 IX86_BUILTIN_MOVAPS128_MASK,
29486 IX86_BUILTIN_MOVDQUHI256_MASK,
29487 IX86_BUILTIN_MOVDQUHI128_MASK,
29488 IX86_BUILTIN_MOVDQUQI256_MASK,
29489 IX86_BUILTIN_MOVDQUQI128_MASK,
29490 IX86_BUILTIN_MINPS128_MASK,
29491 IX86_BUILTIN_MAXPS128_MASK,
29492 IX86_BUILTIN_MINPD128_MASK,
29493 IX86_BUILTIN_MAXPD128_MASK,
29494 IX86_BUILTIN_MAXPD256_MASK,
29495 IX86_BUILTIN_MAXPS256_MASK,
29496 IX86_BUILTIN_MINPD256_MASK,
29497 IX86_BUILTIN_MINPS256_MASK,
29498 IX86_BUILTIN_MULPS128_MASK,
29499 IX86_BUILTIN_DIVPS128_MASK,
29500 IX86_BUILTIN_MULPD128_MASK,
29501 IX86_BUILTIN_DIVPD128_MASK,
29502 IX86_BUILTIN_DIVPD256_MASK,
29503 IX86_BUILTIN_DIVPS256_MASK,
29504 IX86_BUILTIN_MULPD256_MASK,
29505 IX86_BUILTIN_MULPS256_MASK,
29506 IX86_BUILTIN_ADDPD128_MASK,
29507 IX86_BUILTIN_ADDPD256_MASK,
29508 IX86_BUILTIN_ADDPS128_MASK,
29509 IX86_BUILTIN_ADDPS256_MASK,
29510 IX86_BUILTIN_SUBPD128_MASK,
29511 IX86_BUILTIN_SUBPD256_MASK,
29512 IX86_BUILTIN_SUBPS128_MASK,
29513 IX86_BUILTIN_SUBPS256_MASK,
29514 IX86_BUILTIN_XORPD256_MASK,
29515 IX86_BUILTIN_XORPD128_MASK,
29516 IX86_BUILTIN_XORPS256_MASK,
29517 IX86_BUILTIN_XORPS128_MASK,
29518 IX86_BUILTIN_ORPD256_MASK,
29519 IX86_BUILTIN_ORPD128_MASK,
29520 IX86_BUILTIN_ORPS256_MASK,
29521 IX86_BUILTIN_ORPS128_MASK,
29522 IX86_BUILTIN_BROADCASTF32x2_256,
29523 IX86_BUILTIN_BROADCASTI32x2_256,
29524 IX86_BUILTIN_BROADCASTI32x2_128,
29525 IX86_BUILTIN_BROADCASTF64X2_256,
29526 IX86_BUILTIN_BROADCASTI64X2_256,
29527 IX86_BUILTIN_BROADCASTF32X4_256,
29528 IX86_BUILTIN_BROADCASTI32X4_256,
29529 IX86_BUILTIN_EXTRACTF32X4_256,
29530 IX86_BUILTIN_EXTRACTI32X4_256,
29531 IX86_BUILTIN_DBPSADBW256,
29532 IX86_BUILTIN_DBPSADBW128,
29533 IX86_BUILTIN_CVTTPD2QQ256,
29534 IX86_BUILTIN_CVTTPD2QQ128,
29535 IX86_BUILTIN_CVTTPD2UQQ256,
29536 IX86_BUILTIN_CVTTPD2UQQ128,
29537 IX86_BUILTIN_CVTPD2QQ256,
29538 IX86_BUILTIN_CVTPD2QQ128,
29539 IX86_BUILTIN_CVTPD2UQQ256,
29540 IX86_BUILTIN_CVTPD2UQQ128,
29541 IX86_BUILTIN_CVTPD2UDQ256_MASK,
29542 IX86_BUILTIN_CVTPD2UDQ128_MASK,
29543 IX86_BUILTIN_CVTTPS2QQ256,
29544 IX86_BUILTIN_CVTTPS2QQ128,
29545 IX86_BUILTIN_CVTTPS2UQQ256,
29546 IX86_BUILTIN_CVTTPS2UQQ128,
29547 IX86_BUILTIN_CVTTPS2DQ256_MASK,
29548 IX86_BUILTIN_CVTTPS2DQ128_MASK,
29549 IX86_BUILTIN_CVTTPS2UDQ256,
29550 IX86_BUILTIN_CVTTPS2UDQ128,
29551 IX86_BUILTIN_CVTTPD2DQ256_MASK,
29552 IX86_BUILTIN_CVTTPD2DQ128_MASK,
29553 IX86_BUILTIN_CVTTPD2UDQ256_MASK,
29554 IX86_BUILTIN_CVTTPD2UDQ128_MASK,
29555 IX86_BUILTIN_CVTPD2DQ256_MASK,
29556 IX86_BUILTIN_CVTPD2DQ128_MASK,
29557 IX86_BUILTIN_CVTDQ2PD256_MASK,
29558 IX86_BUILTIN_CVTDQ2PD128_MASK,
29559 IX86_BUILTIN_CVTUDQ2PD256_MASK,
29560 IX86_BUILTIN_CVTUDQ2PD128_MASK,
29561 IX86_BUILTIN_CVTDQ2PS256_MASK,
29562 IX86_BUILTIN_CVTDQ2PS128_MASK,
29563 IX86_BUILTIN_CVTUDQ2PS256_MASK,
29564 IX86_BUILTIN_CVTUDQ2PS128_MASK,
29565 IX86_BUILTIN_CVTPS2PD256_MASK,
29566 IX86_BUILTIN_CVTPS2PD128_MASK,
29567 IX86_BUILTIN_PBROADCASTB256_MASK,
29568 IX86_BUILTIN_PBROADCASTB256_GPR_MASK,
29569 IX86_BUILTIN_PBROADCASTB128_MASK,
29570 IX86_BUILTIN_PBROADCASTB128_GPR_MASK,
29571 IX86_BUILTIN_PBROADCASTW256_MASK,
29572 IX86_BUILTIN_PBROADCASTW256_GPR_MASK,
29573 IX86_BUILTIN_PBROADCASTW128_MASK,
29574 IX86_BUILTIN_PBROADCASTW128_GPR_MASK,
29575 IX86_BUILTIN_PBROADCASTD256_MASK,
29576 IX86_BUILTIN_PBROADCASTD256_GPR_MASK,
29577 IX86_BUILTIN_PBROADCASTD128_MASK,
29578 IX86_BUILTIN_PBROADCASTD128_GPR_MASK,
29579 IX86_BUILTIN_PBROADCASTQ256_MASK,
29580 IX86_BUILTIN_PBROADCASTQ256_GPR_MASK,
29581 IX86_BUILTIN_PBROADCASTQ128_MASK,
29582 IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
29583 IX86_BUILTIN_BROADCASTSS256,
29584 IX86_BUILTIN_BROADCASTSS128,
29585 IX86_BUILTIN_BROADCASTSD256,
29586 IX86_BUILTIN_EXTRACTF64X2_256,
29587 IX86_BUILTIN_EXTRACTI64X2_256,
29588 IX86_BUILTIN_INSERTF32X4_256,
29589 IX86_BUILTIN_INSERTI32X4_256,
29590 IX86_BUILTIN_PMOVSXBW256_MASK,
29591 IX86_BUILTIN_PMOVSXBW128_MASK,
29592 IX86_BUILTIN_PMOVSXBD256_MASK,
29593 IX86_BUILTIN_PMOVSXBD128_MASK,
29594 IX86_BUILTIN_PMOVSXBQ256_MASK,
29595 IX86_BUILTIN_PMOVSXBQ128_MASK,
29596 IX86_BUILTIN_PMOVSXWD256_MASK,
29597 IX86_BUILTIN_PMOVSXWD128_MASK,
29598 IX86_BUILTIN_PMOVSXWQ256_MASK,
29599 IX86_BUILTIN_PMOVSXWQ128_MASK,
29600 IX86_BUILTIN_PMOVSXDQ256_MASK,
29601 IX86_BUILTIN_PMOVSXDQ128_MASK,
29602 IX86_BUILTIN_PMOVZXBW256_MASK,
29603 IX86_BUILTIN_PMOVZXBW128_MASK,
29604 IX86_BUILTIN_PMOVZXBD256_MASK,
29605 IX86_BUILTIN_PMOVZXBD128_MASK,
29606 IX86_BUILTIN_PMOVZXBQ256_MASK,
29607 IX86_BUILTIN_PMOVZXBQ128_MASK,
29608 IX86_BUILTIN_PMOVZXWD256_MASK,
29609 IX86_BUILTIN_PMOVZXWD128_MASK,
29610 IX86_BUILTIN_PMOVZXWQ256_MASK,
29611 IX86_BUILTIN_PMOVZXWQ128_MASK,
29612 IX86_BUILTIN_PMOVZXDQ256_MASK,
29613 IX86_BUILTIN_PMOVZXDQ128_MASK,
29614 IX86_BUILTIN_REDUCEPD256_MASK,
29615 IX86_BUILTIN_REDUCEPD128_MASK,
29616 IX86_BUILTIN_REDUCEPS256_MASK,
29617 IX86_BUILTIN_REDUCEPS128_MASK,
29618 IX86_BUILTIN_REDUCESD_MASK,
29619 IX86_BUILTIN_REDUCESS_MASK,
29620 IX86_BUILTIN_VPERMVARHI256_MASK,
29621 IX86_BUILTIN_VPERMVARHI128_MASK,
29622 IX86_BUILTIN_VPERMT2VARHI256,
29623 IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
29624 IX86_BUILTIN_VPERMT2VARHI128,
29625 IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
29626 IX86_BUILTIN_VPERMI2VARHI256,
29627 IX86_BUILTIN_VPERMI2VARHI128,
29628 IX86_BUILTIN_RCP14PD256,
29629 IX86_BUILTIN_RCP14PD128,
29630 IX86_BUILTIN_RCP14PS256,
29631 IX86_BUILTIN_RCP14PS128,
29632 IX86_BUILTIN_RSQRT14PD256_MASK,
29633 IX86_BUILTIN_RSQRT14PD128_MASK,
29634 IX86_BUILTIN_RSQRT14PS256_MASK,
29635 IX86_BUILTIN_RSQRT14PS128_MASK,
29636 IX86_BUILTIN_SQRTPD256_MASK,
29637 IX86_BUILTIN_SQRTPD128_MASK,
29638 IX86_BUILTIN_SQRTPS256_MASK,
29639 IX86_BUILTIN_SQRTPS128_MASK,
29640 IX86_BUILTIN_PADDB128_MASK,
29641 IX86_BUILTIN_PADDW128_MASK,
29642 IX86_BUILTIN_PADDD128_MASK,
29643 IX86_BUILTIN_PADDQ128_MASK,
29644 IX86_BUILTIN_PSUBB128_MASK,
29645 IX86_BUILTIN_PSUBW128_MASK,
29646 IX86_BUILTIN_PSUBD128_MASK,
29647 IX86_BUILTIN_PSUBQ128_MASK,
29648 IX86_BUILTIN_PADDSB128_MASK,
29649 IX86_BUILTIN_PADDSW128_MASK,
29650 IX86_BUILTIN_PSUBSB128_MASK,
29651 IX86_BUILTIN_PSUBSW128_MASK,
29652 IX86_BUILTIN_PADDUSB128_MASK,
29653 IX86_BUILTIN_PADDUSW128_MASK,
29654 IX86_BUILTIN_PSUBUSB128_MASK,
29655 IX86_BUILTIN_PSUBUSW128_MASK,
29656 IX86_BUILTIN_PADDB256_MASK,
29657 IX86_BUILTIN_PADDW256_MASK,
29658 IX86_BUILTIN_PADDD256_MASK,
29659 IX86_BUILTIN_PADDQ256_MASK,
29660 IX86_BUILTIN_PADDSB256_MASK,
29661 IX86_BUILTIN_PADDSW256_MASK,
29662 IX86_BUILTIN_PADDUSB256_MASK,
29663 IX86_BUILTIN_PADDUSW256_MASK,
29664 IX86_BUILTIN_PSUBB256_MASK,
29665 IX86_BUILTIN_PSUBW256_MASK,
29666 IX86_BUILTIN_PSUBD256_MASK,
29667 IX86_BUILTIN_PSUBQ256_MASK,
29668 IX86_BUILTIN_PSUBSB256_MASK,
29669 IX86_BUILTIN_PSUBSW256_MASK,
29670 IX86_BUILTIN_PSUBUSB256_MASK,
29671 IX86_BUILTIN_PSUBUSW256_MASK,
29672 IX86_BUILTIN_SHUF_F64x2_256,
29673 IX86_BUILTIN_SHUF_I64x2_256,
29674 IX86_BUILTIN_SHUF_I32x4_256,
29675 IX86_BUILTIN_SHUF_F32x4_256,
29676 IX86_BUILTIN_PMOVWB128,
29677 IX86_BUILTIN_PMOVWB256,
29678 IX86_BUILTIN_PMOVSWB128,
29679 IX86_BUILTIN_PMOVSWB256,
29680 IX86_BUILTIN_PMOVUSWB128,
29681 IX86_BUILTIN_PMOVUSWB256,
29682 IX86_BUILTIN_PMOVDB128,
29683 IX86_BUILTIN_PMOVDB256,
29684 IX86_BUILTIN_PMOVSDB128,
29685 IX86_BUILTIN_PMOVSDB256,
29686 IX86_BUILTIN_PMOVUSDB128,
29687 IX86_BUILTIN_PMOVUSDB256,
29688 IX86_BUILTIN_PMOVDW128,
29689 IX86_BUILTIN_PMOVDW256,
29690 IX86_BUILTIN_PMOVSDW128,
29691 IX86_BUILTIN_PMOVSDW256,
29692 IX86_BUILTIN_PMOVUSDW128,
29693 IX86_BUILTIN_PMOVUSDW256,
29694 IX86_BUILTIN_PMOVQB128,
29695 IX86_BUILTIN_PMOVQB256,
29696 IX86_BUILTIN_PMOVSQB128,
29697 IX86_BUILTIN_PMOVSQB256,
29698 IX86_BUILTIN_PMOVUSQB128,
29699 IX86_BUILTIN_PMOVUSQB256,
29700 IX86_BUILTIN_PMOVQW128,
29701 IX86_BUILTIN_PMOVQW256,
29702 IX86_BUILTIN_PMOVSQW128,
29703 IX86_BUILTIN_PMOVSQW256,
29704 IX86_BUILTIN_PMOVUSQW128,
29705 IX86_BUILTIN_PMOVUSQW256,
29706 IX86_BUILTIN_PMOVQD128,
29707 IX86_BUILTIN_PMOVQD256,
29708 IX86_BUILTIN_PMOVSQD128,
29709 IX86_BUILTIN_PMOVSQD256,
29710 IX86_BUILTIN_PMOVUSQD128,
29711 IX86_BUILTIN_PMOVUSQD256,
29712 IX86_BUILTIN_RANGEPD256,
29713 IX86_BUILTIN_RANGEPD128,
29714 IX86_BUILTIN_RANGEPS256,
29715 IX86_BUILTIN_RANGEPS128,
29716 IX86_BUILTIN_GETEXPPS256,
29717 IX86_BUILTIN_GETEXPPD256,
29718 IX86_BUILTIN_GETEXPPS128,
29719 IX86_BUILTIN_GETEXPPD128,
29720 IX86_BUILTIN_FIXUPIMMPD256_MASK,
29721 IX86_BUILTIN_FIXUPIMMPD256_MASKZ,
29722 IX86_BUILTIN_FIXUPIMMPS256_MASK,
29723 IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
29724 IX86_BUILTIN_FIXUPIMMPD128_MASK,
29725 IX86_BUILTIN_FIXUPIMMPD128_MASKZ,
29726 IX86_BUILTIN_FIXUPIMMPS128_MASK,
29727 IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
29728 IX86_BUILTIN_PABSQ256,
29729 IX86_BUILTIN_PABSQ128,
29730 IX86_BUILTIN_PABSD256_MASK,
29731 IX86_BUILTIN_PABSD128_MASK,
29732 IX86_BUILTIN_PMULHRSW256_MASK,
29733 IX86_BUILTIN_PMULHRSW128_MASK,
29734 IX86_BUILTIN_PMULHUW128_MASK,
29735 IX86_BUILTIN_PMULHUW256_MASK,
29736 IX86_BUILTIN_PMULHW256_MASK,
29737 IX86_BUILTIN_PMULHW128_MASK,
29738 IX86_BUILTIN_PMULLW256_MASK,
29739 IX86_BUILTIN_PMULLW128_MASK,
29740 IX86_BUILTIN_PMULLQ256,
29741 IX86_BUILTIN_PMULLQ128,
29742 IX86_BUILTIN_ANDPD256_MASK,
29743 IX86_BUILTIN_ANDPD128_MASK,
29744 IX86_BUILTIN_ANDPS256_MASK,
29745 IX86_BUILTIN_ANDPS128_MASK,
29746 IX86_BUILTIN_ANDNPD256_MASK,
29747 IX86_BUILTIN_ANDNPD128_MASK,
29748 IX86_BUILTIN_ANDNPS256_MASK,
29749 IX86_BUILTIN_ANDNPS128_MASK,
29750 IX86_BUILTIN_PSLLWI128_MASK,
29751 IX86_BUILTIN_PSLLDI128_MASK,
29752 IX86_BUILTIN_PSLLQI128_MASK,
29753 IX86_BUILTIN_PSLLW128_MASK,
29754 IX86_BUILTIN_PSLLD128_MASK,
29755 IX86_BUILTIN_PSLLQ128_MASK,
29756 IX86_BUILTIN_PSLLWI256_MASK ,
29757 IX86_BUILTIN_PSLLW256_MASK,
29758 IX86_BUILTIN_PSLLDI256_MASK,
29759 IX86_BUILTIN_PSLLD256_MASK,
29760 IX86_BUILTIN_PSLLQI256_MASK,
29761 IX86_BUILTIN_PSLLQ256_MASK,
29762 IX86_BUILTIN_PSRADI128_MASK,
29763 IX86_BUILTIN_PSRAD128_MASK,
29764 IX86_BUILTIN_PSRADI256_MASK,
29765 IX86_BUILTIN_PSRAD256_MASK,
29766 IX86_BUILTIN_PSRAQI128_MASK,
29767 IX86_BUILTIN_PSRAQ128_MASK,
29768 IX86_BUILTIN_PSRAQI256_MASK,
29769 IX86_BUILTIN_PSRAQ256_MASK,
29770 IX86_BUILTIN_PANDD256,
29771 IX86_BUILTIN_PANDD128,
29772 IX86_BUILTIN_PSRLDI128_MASK,
29773 IX86_BUILTIN_PSRLD128_MASK,
29774 IX86_BUILTIN_PSRLDI256_MASK,
29775 IX86_BUILTIN_PSRLD256_MASK,
29776 IX86_BUILTIN_PSRLQI128_MASK,
29777 IX86_BUILTIN_PSRLQ128_MASK,
29778 IX86_BUILTIN_PSRLQI256_MASK,
29779 IX86_BUILTIN_PSRLQ256_MASK,
29780 IX86_BUILTIN_PANDQ256,
29781 IX86_BUILTIN_PANDQ128,
29782 IX86_BUILTIN_PANDND256,
29783 IX86_BUILTIN_PANDND128,
29784 IX86_BUILTIN_PANDNQ256,
29785 IX86_BUILTIN_PANDNQ128,
29786 IX86_BUILTIN_PORD256,
29787 IX86_BUILTIN_PORD128,
29788 IX86_BUILTIN_PORQ256,
29789 IX86_BUILTIN_PORQ128,
29790 IX86_BUILTIN_PXORD256,
29791 IX86_BUILTIN_PXORD128,
29792 IX86_BUILTIN_PXORQ256,
29793 IX86_BUILTIN_PXORQ128,
29794 IX86_BUILTIN_PACKSSWB256_MASK,
29795 IX86_BUILTIN_PACKSSWB128_MASK,
29796 IX86_BUILTIN_PACKUSWB256_MASK,
29797 IX86_BUILTIN_PACKUSWB128_MASK,
29798 IX86_BUILTIN_RNDSCALEPS256,
29799 IX86_BUILTIN_RNDSCALEPD256,
29800 IX86_BUILTIN_RNDSCALEPS128,
29801 IX86_BUILTIN_RNDSCALEPD128,
29802 IX86_BUILTIN_VTERNLOGQ256_MASK,
29803 IX86_BUILTIN_VTERNLOGQ256_MASKZ,
29804 IX86_BUILTIN_VTERNLOGD256_MASK,
29805 IX86_BUILTIN_VTERNLOGD256_MASKZ,
29806 IX86_BUILTIN_VTERNLOGQ128_MASK,
29807 IX86_BUILTIN_VTERNLOGQ128_MASKZ,
29808 IX86_BUILTIN_VTERNLOGD128_MASK,
29809 IX86_BUILTIN_VTERNLOGD128_MASKZ,
29810 IX86_BUILTIN_SCALEFPD256,
29811 IX86_BUILTIN_SCALEFPS256,
29812 IX86_BUILTIN_SCALEFPD128,
29813 IX86_BUILTIN_SCALEFPS128,
29814 IX86_BUILTIN_VFMADDPD256_MASK,
29815 IX86_BUILTIN_VFMADDPD256_MASK3,
29816 IX86_BUILTIN_VFMADDPD256_MASKZ,
29817 IX86_BUILTIN_VFMADDPD128_MASK,
29818 IX86_BUILTIN_VFMADDPD128_MASK3,
29819 IX86_BUILTIN_VFMADDPD128_MASKZ,
29820 IX86_BUILTIN_VFMADDPS256_MASK,
29821 IX86_BUILTIN_VFMADDPS256_MASK3,
29822 IX86_BUILTIN_VFMADDPS256_MASKZ,
29823 IX86_BUILTIN_VFMADDPS128_MASK,
29824 IX86_BUILTIN_VFMADDPS128_MASK3,
29825 IX86_BUILTIN_VFMADDPS128_MASKZ,
29826 IX86_BUILTIN_VFMSUBPD256_MASK3,
29827 IX86_BUILTIN_VFMSUBPD128_MASK3,
29828 IX86_BUILTIN_VFMSUBPS256_MASK3,
29829 IX86_BUILTIN_VFMSUBPS128_MASK3,
29830 IX86_BUILTIN_VFNMADDPD256_MASK,
29831 IX86_BUILTIN_VFNMADDPD128_MASK,
29832 IX86_BUILTIN_VFNMADDPS256_MASK,
29833 IX86_BUILTIN_VFNMADDPS128_MASK,
29834 IX86_BUILTIN_VFNMSUBPD256_MASK,
29835 IX86_BUILTIN_VFNMSUBPD256_MASK3,
29836 IX86_BUILTIN_VFNMSUBPD128_MASK,
29837 IX86_BUILTIN_VFNMSUBPD128_MASK3,
29838 IX86_BUILTIN_VFNMSUBPS256_MASK,
29839 IX86_BUILTIN_VFNMSUBPS256_MASK3,
29840 IX86_BUILTIN_VFNMSUBPS128_MASK,
29841 IX86_BUILTIN_VFNMSUBPS128_MASK3,
29842 IX86_BUILTIN_VFMADDSUBPD256_MASK,
29843 IX86_BUILTIN_VFMADDSUBPD256_MASK3,
29844 IX86_BUILTIN_VFMADDSUBPD256_MASKZ,
29845 IX86_BUILTIN_VFMADDSUBPD128_MASK,
29846 IX86_BUILTIN_VFMADDSUBPD128_MASK3,
29847 IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
29848 IX86_BUILTIN_VFMADDSUBPS256_MASK,
29849 IX86_BUILTIN_VFMADDSUBPS256_MASK3,
29850 IX86_BUILTIN_VFMADDSUBPS256_MASKZ,
29851 IX86_BUILTIN_VFMADDSUBPS128_MASK,
29852 IX86_BUILTIN_VFMADDSUBPS128_MASK3,
29853 IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
29854 IX86_BUILTIN_VFMSUBADDPD256_MASK3,
29855 IX86_BUILTIN_VFMSUBADDPD128_MASK3,
29856 IX86_BUILTIN_VFMSUBADDPS256_MASK3,
29857 IX86_BUILTIN_VFMSUBADDPS128_MASK3,
29858 IX86_BUILTIN_INSERTF64X2_256,
29859 IX86_BUILTIN_INSERTI64X2_256,
29860 IX86_BUILTIN_PSRAVV16HI,
29861 IX86_BUILTIN_PSRAVV8HI,
29862 IX86_BUILTIN_PMADDUBSW256_MASK,
29863 IX86_BUILTIN_PMADDUBSW128_MASK,
29864 IX86_BUILTIN_PMADDWD256_MASK,
29865 IX86_BUILTIN_PMADDWD128_MASK,
29866 IX86_BUILTIN_PSRLVV16HI,
29867 IX86_BUILTIN_PSRLVV8HI,
29868 IX86_BUILTIN_CVTPS2DQ256_MASK,
29869 IX86_BUILTIN_CVTPS2DQ128_MASK,
29870 IX86_BUILTIN_CVTPS2UDQ256,
29871 IX86_BUILTIN_CVTPS2UDQ128,
29872 IX86_BUILTIN_CVTPS2QQ256,
29873 IX86_BUILTIN_CVTPS2QQ128,
29874 IX86_BUILTIN_CVTPS2UQQ256,
29875 IX86_BUILTIN_CVTPS2UQQ128,
29876 IX86_BUILTIN_GETMANTPS256,
29877 IX86_BUILTIN_GETMANTPS128,
29878 IX86_BUILTIN_GETMANTPD256,
29879 IX86_BUILTIN_GETMANTPD128,
29880 IX86_BUILTIN_MOVDDUP256_MASK,
29881 IX86_BUILTIN_MOVDDUP128_MASK,
29882 IX86_BUILTIN_MOVSHDUP256_MASK,
29883 IX86_BUILTIN_MOVSHDUP128_MASK,
29884 IX86_BUILTIN_MOVSLDUP256_MASK,
29885 IX86_BUILTIN_MOVSLDUP128_MASK,
29886 IX86_BUILTIN_CVTQQ2PS256,
29887 IX86_BUILTIN_CVTQQ2PS128,
29888 IX86_BUILTIN_CVTUQQ2PS256,
29889 IX86_BUILTIN_CVTUQQ2PS128,
29890 IX86_BUILTIN_CVTQQ2PD256,
29891 IX86_BUILTIN_CVTQQ2PD128,
29892 IX86_BUILTIN_CVTUQQ2PD256,
29893 IX86_BUILTIN_CVTUQQ2PD128,
29894 IX86_BUILTIN_VPERMT2VARQ256,
29895 IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
29896 IX86_BUILTIN_VPERMT2VARD256,
29897 IX86_BUILTIN_VPERMT2VARD256_MASKZ,
29898 IX86_BUILTIN_VPERMI2VARQ256,
29899 IX86_BUILTIN_VPERMI2VARD256,
29900 IX86_BUILTIN_VPERMT2VARPD256,
29901 IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
29902 IX86_BUILTIN_VPERMT2VARPS256,
29903 IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
29904 IX86_BUILTIN_VPERMI2VARPD256,
29905 IX86_BUILTIN_VPERMI2VARPS256,
29906 IX86_BUILTIN_VPERMT2VARQ128,
29907 IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
29908 IX86_BUILTIN_VPERMT2VARD128,
29909 IX86_BUILTIN_VPERMT2VARD128_MASKZ,
29910 IX86_BUILTIN_VPERMI2VARQ128,
29911 IX86_BUILTIN_VPERMI2VARD128,
29912 IX86_BUILTIN_VPERMT2VARPD128,
29913 IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
29914 IX86_BUILTIN_VPERMT2VARPS128,
29915 IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
29916 IX86_BUILTIN_VPERMI2VARPD128,
29917 IX86_BUILTIN_VPERMI2VARPS128,
29918 IX86_BUILTIN_PSHUFB256_MASK,
29919 IX86_BUILTIN_PSHUFB128_MASK,
29920 IX86_BUILTIN_PSHUFHW256_MASK,
29921 IX86_BUILTIN_PSHUFHW128_MASK,
29922 IX86_BUILTIN_PSHUFLW256_MASK,
29923 IX86_BUILTIN_PSHUFLW128_MASK,
29924 IX86_BUILTIN_PSHUFD256_MASK,
29925 IX86_BUILTIN_PSHUFD128_MASK,
29926 IX86_BUILTIN_SHUFPD256_MASK,
29927 IX86_BUILTIN_SHUFPD128_MASK,
29928 IX86_BUILTIN_SHUFPS256_MASK,
29929 IX86_BUILTIN_SHUFPS128_MASK,
29930 IX86_BUILTIN_PROLVQ256,
29931 IX86_BUILTIN_PROLVQ128,
29932 IX86_BUILTIN_PROLQ256,
29933 IX86_BUILTIN_PROLQ128,
29934 IX86_BUILTIN_PRORVQ256,
29935 IX86_BUILTIN_PRORVQ128,
29936 IX86_BUILTIN_PRORQ256,
29937 IX86_BUILTIN_PRORQ128,
29938 IX86_BUILTIN_PSRAVQ128,
29939 IX86_BUILTIN_PSRAVQ256,
29940 IX86_BUILTIN_PSLLVV4DI_MASK,
29941 IX86_BUILTIN_PSLLVV2DI_MASK,
29942 IX86_BUILTIN_PSLLVV8SI_MASK,
29943 IX86_BUILTIN_PSLLVV4SI_MASK,
29944 IX86_BUILTIN_PSRAVV8SI_MASK,
29945 IX86_BUILTIN_PSRAVV4SI_MASK,
29946 IX86_BUILTIN_PSRLVV4DI_MASK,
29947 IX86_BUILTIN_PSRLVV2DI_MASK,
29948 IX86_BUILTIN_PSRLVV8SI_MASK,
29949 IX86_BUILTIN_PSRLVV4SI_MASK,
29950 IX86_BUILTIN_PSRAWI256_MASK,
29951 IX86_BUILTIN_PSRAW256_MASK,
29952 IX86_BUILTIN_PSRAWI128_MASK,
29953 IX86_BUILTIN_PSRAW128_MASK,
29954 IX86_BUILTIN_PSRLWI256_MASK,
29955 IX86_BUILTIN_PSRLW256_MASK,
29956 IX86_BUILTIN_PSRLWI128_MASK,
29957 IX86_BUILTIN_PSRLW128_MASK,
29958 IX86_BUILTIN_PRORVD256,
29959 IX86_BUILTIN_PROLVD256,
29960 IX86_BUILTIN_PRORD256,
29961 IX86_BUILTIN_PROLD256,
29962 IX86_BUILTIN_PRORVD128,
29963 IX86_BUILTIN_PROLVD128,
29964 IX86_BUILTIN_PRORD128,
29965 IX86_BUILTIN_PROLD128,
29966 IX86_BUILTIN_FPCLASSPD256,
29967 IX86_BUILTIN_FPCLASSPD128,
29968 IX86_BUILTIN_FPCLASSSD,
29969 IX86_BUILTIN_FPCLASSPS256,
29970 IX86_BUILTIN_FPCLASSPS128,
29971 IX86_BUILTIN_FPCLASSSS,
29972 IX86_BUILTIN_CVTB2MASK128,
29973 IX86_BUILTIN_CVTB2MASK256,
29974 IX86_BUILTIN_CVTW2MASK128,
29975 IX86_BUILTIN_CVTW2MASK256,
29976 IX86_BUILTIN_CVTD2MASK128,
29977 IX86_BUILTIN_CVTD2MASK256,
29978 IX86_BUILTIN_CVTQ2MASK128,
29979 IX86_BUILTIN_CVTQ2MASK256,
29980 IX86_BUILTIN_CVTMASK2B128,
29981 IX86_BUILTIN_CVTMASK2B256,
29982 IX86_BUILTIN_CVTMASK2W128,
29983 IX86_BUILTIN_CVTMASK2W256,
29984 IX86_BUILTIN_CVTMASK2D128,
29985 IX86_BUILTIN_CVTMASK2D256,
29986 IX86_BUILTIN_CVTMASK2Q128,
29987 IX86_BUILTIN_CVTMASK2Q256,
29988 IX86_BUILTIN_PCMPEQB128_MASK,
29989 IX86_BUILTIN_PCMPEQB256_MASK,
29990 IX86_BUILTIN_PCMPEQW128_MASK,
29991 IX86_BUILTIN_PCMPEQW256_MASK,
29992 IX86_BUILTIN_PCMPEQD128_MASK,
29993 IX86_BUILTIN_PCMPEQD256_MASK,
29994 IX86_BUILTIN_PCMPEQQ128_MASK,
29995 IX86_BUILTIN_PCMPEQQ256_MASK,
29996 IX86_BUILTIN_PCMPGTB128_MASK,
29997 IX86_BUILTIN_PCMPGTB256_MASK,
29998 IX86_BUILTIN_PCMPGTW128_MASK,
29999 IX86_BUILTIN_PCMPGTW256_MASK,
30000 IX86_BUILTIN_PCMPGTD128_MASK,
30001 IX86_BUILTIN_PCMPGTD256_MASK,
30002 IX86_BUILTIN_PCMPGTQ128_MASK,
30003 IX86_BUILTIN_PCMPGTQ256_MASK,
30004 IX86_BUILTIN_PTESTMB128,
30005 IX86_BUILTIN_PTESTMB256,
30006 IX86_BUILTIN_PTESTMW128,
30007 IX86_BUILTIN_PTESTMW256,
30008 IX86_BUILTIN_PTESTMD128,
30009 IX86_BUILTIN_PTESTMD256,
30010 IX86_BUILTIN_PTESTMQ128,
30011 IX86_BUILTIN_PTESTMQ256,
30012 IX86_BUILTIN_PTESTNMB128,
30013 IX86_BUILTIN_PTESTNMB256,
30014 IX86_BUILTIN_PTESTNMW128,
30015 IX86_BUILTIN_PTESTNMW256,
30016 IX86_BUILTIN_PTESTNMD128,
30017 IX86_BUILTIN_PTESTNMD256,
30018 IX86_BUILTIN_PTESTNMQ128,
30019 IX86_BUILTIN_PTESTNMQ256,
30020 IX86_BUILTIN_PBROADCASTMB128,
30021 IX86_BUILTIN_PBROADCASTMB256,
30022 IX86_BUILTIN_PBROADCASTMW128,
30023 IX86_BUILTIN_PBROADCASTMW256,
30024 IX86_BUILTIN_COMPRESSPD256,
30025 IX86_BUILTIN_COMPRESSPD128,
30026 IX86_BUILTIN_COMPRESSPS256,
30027 IX86_BUILTIN_COMPRESSPS128,
30028 IX86_BUILTIN_PCOMPRESSQ256,
30029 IX86_BUILTIN_PCOMPRESSQ128,
30030 IX86_BUILTIN_PCOMPRESSD256,
30031 IX86_BUILTIN_PCOMPRESSD128,
30032 IX86_BUILTIN_EXPANDPD256,
30033 IX86_BUILTIN_EXPANDPD128,
30034 IX86_BUILTIN_EXPANDPS256,
30035 IX86_BUILTIN_EXPANDPS128,
30036 IX86_BUILTIN_PEXPANDQ256,
30037 IX86_BUILTIN_PEXPANDQ128,
30038 IX86_BUILTIN_PEXPANDD256,
30039 IX86_BUILTIN_PEXPANDD128,
30040 IX86_BUILTIN_EXPANDPD256Z,
30041 IX86_BUILTIN_EXPANDPD128Z,
30042 IX86_BUILTIN_EXPANDPS256Z,
30043 IX86_BUILTIN_EXPANDPS128Z,
30044 IX86_BUILTIN_PEXPANDQ256Z,
30045 IX86_BUILTIN_PEXPANDQ128Z,
30046 IX86_BUILTIN_PEXPANDD256Z,
30047 IX86_BUILTIN_PEXPANDD128Z,
30048 IX86_BUILTIN_PMAXSD256_MASK,
30049 IX86_BUILTIN_PMINSD256_MASK,
30050 IX86_BUILTIN_PMAXUD256_MASK,
30051 IX86_BUILTIN_PMINUD256_MASK,
30052 IX86_BUILTIN_PMAXSD128_MASK,
30053 IX86_BUILTIN_PMINSD128_MASK,
30054 IX86_BUILTIN_PMAXUD128_MASK,
30055 IX86_BUILTIN_PMINUD128_MASK,
30056 IX86_BUILTIN_PMAXSQ256_MASK,
30057 IX86_BUILTIN_PMINSQ256_MASK,
30058 IX86_BUILTIN_PMAXUQ256_MASK,
30059 IX86_BUILTIN_PMINUQ256_MASK,
30060 IX86_BUILTIN_PMAXSQ128_MASK,
30061 IX86_BUILTIN_PMINSQ128_MASK,
30062 IX86_BUILTIN_PMAXUQ128_MASK,
30063 IX86_BUILTIN_PMINUQ128_MASK,
30064 IX86_BUILTIN_PMINSB256_MASK,
30065 IX86_BUILTIN_PMINUB256_MASK,
30066 IX86_BUILTIN_PMAXSB256_MASK,
30067 IX86_BUILTIN_PMAXUB256_MASK,
30068 IX86_BUILTIN_PMINSB128_MASK,
30069 IX86_BUILTIN_PMINUB128_MASK,
30070 IX86_BUILTIN_PMAXSB128_MASK,
30071 IX86_BUILTIN_PMAXUB128_MASK,
30072 IX86_BUILTIN_PMINSW256_MASK,
30073 IX86_BUILTIN_PMINUW256_MASK,
30074 IX86_BUILTIN_PMAXSW256_MASK,
30075 IX86_BUILTIN_PMAXUW256_MASK,
30076 IX86_BUILTIN_PMINSW128_MASK,
30077 IX86_BUILTIN_PMINUW128_MASK,
30078 IX86_BUILTIN_PMAXSW128_MASK,
30079 IX86_BUILTIN_PMAXUW128_MASK,
30080 IX86_BUILTIN_VPCONFLICTQ256,
30081 IX86_BUILTIN_VPCONFLICTD256,
30082 IX86_BUILTIN_VPCLZCNTQ256,
30083 IX86_BUILTIN_VPCLZCNTD256,
30084 IX86_BUILTIN_UNPCKHPD256_MASK,
30085 IX86_BUILTIN_UNPCKHPD128_MASK,
30086 IX86_BUILTIN_UNPCKHPS256_MASK,
30087 IX86_BUILTIN_UNPCKHPS128_MASK,
30088 IX86_BUILTIN_UNPCKLPD256_MASK,
30089 IX86_BUILTIN_UNPCKLPD128_MASK,
30090 IX86_BUILTIN_UNPCKLPS256_MASK,
30091 IX86_BUILTIN_VPCONFLICTQ128,
30092 IX86_BUILTIN_VPCONFLICTD128,
30093 IX86_BUILTIN_VPCLZCNTQ128,
30094 IX86_BUILTIN_VPCLZCNTD128,
30095 IX86_BUILTIN_UNPCKLPS128_MASK,
30096 IX86_BUILTIN_ALIGND256,
30097 IX86_BUILTIN_ALIGNQ256,
30098 IX86_BUILTIN_ALIGND128,
30099 IX86_BUILTIN_ALIGNQ128,
30100 IX86_BUILTIN_CVTPS2PH256_MASK,
30101 IX86_BUILTIN_CVTPS2PH_MASK,
30102 IX86_BUILTIN_CVTPH2PS_MASK,
30103 IX86_BUILTIN_CVTPH2PS256_MASK,
30104 IX86_BUILTIN_PUNPCKHDQ128_MASK,
30105 IX86_BUILTIN_PUNPCKHDQ256_MASK,
30106 IX86_BUILTIN_PUNPCKHQDQ128_MASK,
30107 IX86_BUILTIN_PUNPCKHQDQ256_MASK,
30108 IX86_BUILTIN_PUNPCKLDQ128_MASK,
30109 IX86_BUILTIN_PUNPCKLDQ256_MASK,
30110 IX86_BUILTIN_PUNPCKLQDQ128_MASK,
30111 IX86_BUILTIN_PUNPCKLQDQ256_MASK,
30112 IX86_BUILTIN_PUNPCKHBW128_MASK,
30113 IX86_BUILTIN_PUNPCKHBW256_MASK,
30114 IX86_BUILTIN_PUNPCKHWD128_MASK,
30115 IX86_BUILTIN_PUNPCKHWD256_MASK,
30116 IX86_BUILTIN_PUNPCKLBW128_MASK,
30117 IX86_BUILTIN_PUNPCKLBW256_MASK,
30118 IX86_BUILTIN_PUNPCKLWD128_MASK,
30119 IX86_BUILTIN_PUNPCKLWD256_MASK,
30120 IX86_BUILTIN_PSLLVV16HI,
30121 IX86_BUILTIN_PSLLVV8HI,
30122 IX86_BUILTIN_PACKSSDW256_MASK,
30123 IX86_BUILTIN_PACKSSDW128_MASK,
30124 IX86_BUILTIN_PACKUSDW256_MASK,
30125 IX86_BUILTIN_PACKUSDW128_MASK,
30126 IX86_BUILTIN_PAVGB256_MASK,
30127 IX86_BUILTIN_PAVGW256_MASK,
30128 IX86_BUILTIN_PAVGB128_MASK,
30129 IX86_BUILTIN_PAVGW128_MASK,
30130 IX86_BUILTIN_VPERMVARSF256_MASK,
30131 IX86_BUILTIN_VPERMVARDF256_MASK,
30132 IX86_BUILTIN_VPERMDF256_MASK,
30133 IX86_BUILTIN_PABSB256_MASK,
30134 IX86_BUILTIN_PABSB128_MASK,
30135 IX86_BUILTIN_PABSW256_MASK,
30136 IX86_BUILTIN_PABSW128_MASK,
30137 IX86_BUILTIN_VPERMILVARPD_MASK,
30138 IX86_BUILTIN_VPERMILVARPS_MASK,
30139 IX86_BUILTIN_VPERMILVARPD256_MASK,
30140 IX86_BUILTIN_VPERMILVARPS256_MASK,
30141 IX86_BUILTIN_VPERMILPD_MASK,
30142 IX86_BUILTIN_VPERMILPS_MASK,
30143 IX86_BUILTIN_VPERMILPD256_MASK,
30144 IX86_BUILTIN_VPERMILPS256_MASK,
30145 IX86_BUILTIN_BLENDMQ256,
30146 IX86_BUILTIN_BLENDMD256,
30147 IX86_BUILTIN_BLENDMPD256,
30148 IX86_BUILTIN_BLENDMPS256,
30149 IX86_BUILTIN_BLENDMQ128,
30150 IX86_BUILTIN_BLENDMD128,
30151 IX86_BUILTIN_BLENDMPD128,
30152 IX86_BUILTIN_BLENDMPS128,
30153 IX86_BUILTIN_BLENDMW256,
30154 IX86_BUILTIN_BLENDMB256,
30155 IX86_BUILTIN_BLENDMW128,
30156 IX86_BUILTIN_BLENDMB128,
30157 IX86_BUILTIN_PMULLD256_MASK,
30158 IX86_BUILTIN_PMULLD128_MASK,
30159 IX86_BUILTIN_PMULUDQ256_MASK,
30160 IX86_BUILTIN_PMULDQ256_MASK,
30161 IX86_BUILTIN_PMULDQ128_MASK,
30162 IX86_BUILTIN_PMULUDQ128_MASK,
30163 IX86_BUILTIN_CVTPD2PS256_MASK,
30164 IX86_BUILTIN_CVTPD2PS_MASK,
30165 IX86_BUILTIN_VPERMVARSI256_MASK,
30166 IX86_BUILTIN_VPERMVARDI256_MASK,
30167 IX86_BUILTIN_VPERMDI256_MASK,
30168 IX86_BUILTIN_CMPQ256,
30169 IX86_BUILTIN_CMPD256,
30170 IX86_BUILTIN_UCMPQ256,
30171 IX86_BUILTIN_UCMPD256,
30172 IX86_BUILTIN_CMPB256,
30173 IX86_BUILTIN_CMPW256,
30174 IX86_BUILTIN_UCMPB256,
30175 IX86_BUILTIN_UCMPW256,
30176 IX86_BUILTIN_CMPPD256_MASK,
30177 IX86_BUILTIN_CMPPS256_MASK,
30178 IX86_BUILTIN_CMPQ128,
30179 IX86_BUILTIN_CMPD128,
30180 IX86_BUILTIN_UCMPQ128,
30181 IX86_BUILTIN_UCMPD128,
30182 IX86_BUILTIN_CMPB128,
30183 IX86_BUILTIN_CMPW128,
30184 IX86_BUILTIN_UCMPB128,
30185 IX86_BUILTIN_UCMPW128,
30186 IX86_BUILTIN_CMPPD128_MASK,
30187 IX86_BUILTIN_CMPPS128_MASK,
30189 IX86_BUILTIN_GATHER3SIV8SF,
30190 IX86_BUILTIN_GATHER3SIV4SF,
30191 IX86_BUILTIN_GATHER3SIV4DF,
30192 IX86_BUILTIN_GATHER3SIV2DF,
30193 IX86_BUILTIN_GATHER3DIV8SF,
30194 IX86_BUILTIN_GATHER3DIV4SF,
30195 IX86_BUILTIN_GATHER3DIV4DF,
30196 IX86_BUILTIN_GATHER3DIV2DF,
30197 IX86_BUILTIN_GATHER3SIV8SI,
30198 IX86_BUILTIN_GATHER3SIV4SI,
30199 IX86_BUILTIN_GATHER3SIV4DI,
30200 IX86_BUILTIN_GATHER3SIV2DI,
30201 IX86_BUILTIN_GATHER3DIV8SI,
30202 IX86_BUILTIN_GATHER3DIV4SI,
30203 IX86_BUILTIN_GATHER3DIV4DI,
30204 IX86_BUILTIN_GATHER3DIV2DI,
30205 IX86_BUILTIN_SCATTERSIV8SF,
30206 IX86_BUILTIN_SCATTERSIV4SF,
30207 IX86_BUILTIN_SCATTERSIV4DF,
30208 IX86_BUILTIN_SCATTERSIV2DF,
30209 IX86_BUILTIN_SCATTERDIV8SF,
30210 IX86_BUILTIN_SCATTERDIV4SF,
30211 IX86_BUILTIN_SCATTERDIV4DF,
30212 IX86_BUILTIN_SCATTERDIV2DF,
30213 IX86_BUILTIN_SCATTERSIV8SI,
30214 IX86_BUILTIN_SCATTERSIV4SI,
30215 IX86_BUILTIN_SCATTERSIV4DI,
30216 IX86_BUILTIN_SCATTERSIV2DI,
30217 IX86_BUILTIN_SCATTERDIV8SI,
30218 IX86_BUILTIN_SCATTERDIV4SI,
30219 IX86_BUILTIN_SCATTERDIV4DI,
30220 IX86_BUILTIN_SCATTERDIV2DI,
30222 /* AVX512DQ. */
30223 IX86_BUILTIN_RANGESD128,
30224 IX86_BUILTIN_RANGESS128,
30225 IX86_BUILTIN_KUNPCKWD,
30226 IX86_BUILTIN_KUNPCKDQ,
30227 IX86_BUILTIN_BROADCASTF32x2_512,
30228 IX86_BUILTIN_BROADCASTI32x2_512,
30229 IX86_BUILTIN_BROADCASTF64X2_512,
30230 IX86_BUILTIN_BROADCASTI64X2_512,
30231 IX86_BUILTIN_BROADCASTF32X8_512,
30232 IX86_BUILTIN_BROADCASTI32X8_512,
30233 IX86_BUILTIN_EXTRACTF64X2_512,
30234 IX86_BUILTIN_EXTRACTF32X8,
30235 IX86_BUILTIN_EXTRACTI64X2_512,
30236 IX86_BUILTIN_EXTRACTI32X8,
30237 IX86_BUILTIN_REDUCEPD512_MASK,
30238 IX86_BUILTIN_REDUCEPS512_MASK,
30239 IX86_BUILTIN_PMULLQ512,
30240 IX86_BUILTIN_XORPD512,
30241 IX86_BUILTIN_XORPS512,
30242 IX86_BUILTIN_ORPD512,
30243 IX86_BUILTIN_ORPS512,
30244 IX86_BUILTIN_ANDPD512,
30245 IX86_BUILTIN_ANDPS512,
30246 IX86_BUILTIN_ANDNPD512,
30247 IX86_BUILTIN_ANDNPS512,
30248 IX86_BUILTIN_INSERTF32X8,
30249 IX86_BUILTIN_INSERTI32X8,
30250 IX86_BUILTIN_INSERTF64X2_512,
30251 IX86_BUILTIN_INSERTI64X2_512,
30252 IX86_BUILTIN_FPCLASSPD512,
30253 IX86_BUILTIN_FPCLASSPS512,
30254 IX86_BUILTIN_CVTD2MASK512,
30255 IX86_BUILTIN_CVTQ2MASK512,
30256 IX86_BUILTIN_CVTMASK2D512,
30257 IX86_BUILTIN_CVTMASK2Q512,
30258 IX86_BUILTIN_CVTPD2QQ512,
30259 IX86_BUILTIN_CVTPS2QQ512,
30260 IX86_BUILTIN_CVTPD2UQQ512,
30261 IX86_BUILTIN_CVTPS2UQQ512,
30262 IX86_BUILTIN_CVTQQ2PS512,
30263 IX86_BUILTIN_CVTUQQ2PS512,
30264 IX86_BUILTIN_CVTQQ2PD512,
30265 IX86_BUILTIN_CVTUQQ2PD512,
30266 IX86_BUILTIN_CVTTPS2QQ512,
30267 IX86_BUILTIN_CVTTPS2UQQ512,
30268 IX86_BUILTIN_CVTTPD2QQ512,
30269 IX86_BUILTIN_CVTTPD2UQQ512,
30270 IX86_BUILTIN_RANGEPS512,
30271 IX86_BUILTIN_RANGEPD512,
30273 /* AVX512BW. */
30274 IX86_BUILTIN_PACKUSDW512,
30275 IX86_BUILTIN_PACKSSDW512,
30276 IX86_BUILTIN_LOADDQUHI512_MASK,
30277 IX86_BUILTIN_LOADDQUQI512_MASK,
30278 IX86_BUILTIN_PSLLDQ512,
30279 IX86_BUILTIN_PSRLDQ512,
30280 IX86_BUILTIN_STOREDQUHI512_MASK,
30281 IX86_BUILTIN_STOREDQUQI512_MASK,
30282 IX86_BUILTIN_PALIGNR512,
30283 IX86_BUILTIN_PALIGNR512_MASK,
30284 IX86_BUILTIN_MOVDQUHI512_MASK,
30285 IX86_BUILTIN_MOVDQUQI512_MASK,
30286 IX86_BUILTIN_PSADBW512,
30287 IX86_BUILTIN_DBPSADBW512,
30288 IX86_BUILTIN_PBROADCASTB512,
30289 IX86_BUILTIN_PBROADCASTB512_GPR,
30290 IX86_BUILTIN_PBROADCASTW512,
30291 IX86_BUILTIN_PBROADCASTW512_GPR,
30292 IX86_BUILTIN_PMOVSXBW512_MASK,
30293 IX86_BUILTIN_PMOVZXBW512_MASK,
30294 IX86_BUILTIN_VPERMVARHI512_MASK,
30295 IX86_BUILTIN_VPERMT2VARHI512,
30296 IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
30297 IX86_BUILTIN_VPERMI2VARHI512,
30298 IX86_BUILTIN_PAVGB512,
30299 IX86_BUILTIN_PAVGW512,
30300 IX86_BUILTIN_PADDB512,
30301 IX86_BUILTIN_PSUBB512,
30302 IX86_BUILTIN_PSUBSB512,
30303 IX86_BUILTIN_PADDSB512,
30304 IX86_BUILTIN_PSUBUSB512,
30305 IX86_BUILTIN_PADDUSB512,
30306 IX86_BUILTIN_PSUBW512,
30307 IX86_BUILTIN_PADDW512,
30308 IX86_BUILTIN_PSUBSW512,
30309 IX86_BUILTIN_PADDSW512,
30310 IX86_BUILTIN_PSUBUSW512,
30311 IX86_BUILTIN_PADDUSW512,
30312 IX86_BUILTIN_PMAXUW512,
30313 IX86_BUILTIN_PMAXSW512,
30314 IX86_BUILTIN_PMINUW512,
30315 IX86_BUILTIN_PMINSW512,
30316 IX86_BUILTIN_PMAXUB512,
30317 IX86_BUILTIN_PMAXSB512,
30318 IX86_BUILTIN_PMINUB512,
30319 IX86_BUILTIN_PMINSB512,
30320 IX86_BUILTIN_PMOVWB512,
30321 IX86_BUILTIN_PMOVSWB512,
30322 IX86_BUILTIN_PMOVUSWB512,
30323 IX86_BUILTIN_PMULHRSW512_MASK,
30324 IX86_BUILTIN_PMULHUW512_MASK,
30325 IX86_BUILTIN_PMULHW512_MASK,
30326 IX86_BUILTIN_PMULLW512_MASK,
30327 IX86_BUILTIN_PSLLWI512_MASK,
30328 IX86_BUILTIN_PSLLW512_MASK,
30329 IX86_BUILTIN_PACKSSWB512,
30330 IX86_BUILTIN_PACKUSWB512,
30331 IX86_BUILTIN_PSRAVV32HI,
30332 IX86_BUILTIN_PMADDUBSW512_MASK,
30333 IX86_BUILTIN_PMADDWD512_MASK,
30334 IX86_BUILTIN_PSRLVV32HI,
30335 IX86_BUILTIN_PUNPCKHBW512,
30336 IX86_BUILTIN_PUNPCKHWD512,
30337 IX86_BUILTIN_PUNPCKLBW512,
30338 IX86_BUILTIN_PUNPCKLWD512,
30339 IX86_BUILTIN_PSHUFB512,
30340 IX86_BUILTIN_PSHUFHW512,
30341 IX86_BUILTIN_PSHUFLW512,
30342 IX86_BUILTIN_PSRAWI512,
30343 IX86_BUILTIN_PSRAW512,
30344 IX86_BUILTIN_PSRLWI512,
30345 IX86_BUILTIN_PSRLW512,
30346 IX86_BUILTIN_CVTB2MASK512,
30347 IX86_BUILTIN_CVTW2MASK512,
30348 IX86_BUILTIN_CVTMASK2B512,
30349 IX86_BUILTIN_CVTMASK2W512,
30350 IX86_BUILTIN_PCMPEQB512_MASK,
30351 IX86_BUILTIN_PCMPEQW512_MASK,
30352 IX86_BUILTIN_PCMPGTB512_MASK,
30353 IX86_BUILTIN_PCMPGTW512_MASK,
30354 IX86_BUILTIN_PTESTMB512,
30355 IX86_BUILTIN_PTESTMW512,
30356 IX86_BUILTIN_PTESTNMB512,
30357 IX86_BUILTIN_PTESTNMW512,
30358 IX86_BUILTIN_PSLLVV32HI,
30359 IX86_BUILTIN_PABSB512,
30360 IX86_BUILTIN_PABSW512,
30361 IX86_BUILTIN_BLENDMW512,
30362 IX86_BUILTIN_BLENDMB512,
30363 IX86_BUILTIN_CMPB512,
30364 IX86_BUILTIN_CMPW512,
30365 IX86_BUILTIN_UCMPB512,
30366 IX86_BUILTIN_UCMPW512,
30368 /* Alternate 4 and 8 element gather/scatter for the vectorizer
30369 where all operands are 32-byte or 64-byte wide respectively. */
30370 IX86_BUILTIN_GATHERALTSIV4DF,
30371 IX86_BUILTIN_GATHERALTDIV8SF,
30372 IX86_BUILTIN_GATHERALTSIV4DI,
30373 IX86_BUILTIN_GATHERALTDIV8SI,
30374 IX86_BUILTIN_GATHER3ALTDIV16SF,
30375 IX86_BUILTIN_GATHER3ALTDIV16SI,
30376 IX86_BUILTIN_GATHER3ALTSIV4DF,
30377 IX86_BUILTIN_GATHER3ALTDIV8SF,
30378 IX86_BUILTIN_GATHER3ALTSIV4DI,
30379 IX86_BUILTIN_GATHER3ALTDIV8SI,
30380 IX86_BUILTIN_GATHER3ALTSIV8DF,
30381 IX86_BUILTIN_GATHER3ALTSIV8DI,
30382 IX86_BUILTIN_GATHER3DIV16SF,
30383 IX86_BUILTIN_GATHER3DIV16SI,
30384 IX86_BUILTIN_GATHER3DIV8DF,
30385 IX86_BUILTIN_GATHER3DIV8DI,
30386 IX86_BUILTIN_GATHER3SIV16SF,
30387 IX86_BUILTIN_GATHER3SIV16SI,
30388 IX86_BUILTIN_GATHER3SIV8DF,
30389 IX86_BUILTIN_GATHER3SIV8DI,
30390 IX86_BUILTIN_SCATTERDIV16SF,
30391 IX86_BUILTIN_SCATTERDIV16SI,
30392 IX86_BUILTIN_SCATTERDIV8DF,
30393 IX86_BUILTIN_SCATTERDIV8DI,
30394 IX86_BUILTIN_SCATTERSIV16SF,
30395 IX86_BUILTIN_SCATTERSIV16SI,
30396 IX86_BUILTIN_SCATTERSIV8DF,
30397 IX86_BUILTIN_SCATTERSIV8DI,
30399 /* AVX512PF */
30400 IX86_BUILTIN_GATHERPFQPD,
30401 IX86_BUILTIN_GATHERPFDPS,
30402 IX86_BUILTIN_GATHERPFDPD,
30403 IX86_BUILTIN_GATHERPFQPS,
30404 IX86_BUILTIN_SCATTERPFDPD,
30405 IX86_BUILTIN_SCATTERPFDPS,
30406 IX86_BUILTIN_SCATTERPFQPD,
30407 IX86_BUILTIN_SCATTERPFQPS,
30409 /* AVX-512ER */
30410 IX86_BUILTIN_EXP2PD_MASK,
30411 IX86_BUILTIN_EXP2PS_MASK,
30412 IX86_BUILTIN_EXP2PS,
30413 IX86_BUILTIN_RCP28PD,
30414 IX86_BUILTIN_RCP28PS,
30415 IX86_BUILTIN_RCP28SD,
30416 IX86_BUILTIN_RCP28SS,
30417 IX86_BUILTIN_RSQRT28PD,
30418 IX86_BUILTIN_RSQRT28PS,
30419 IX86_BUILTIN_RSQRT28SD,
30420 IX86_BUILTIN_RSQRT28SS,
30422 /* AVX-512IFMA */
30423 IX86_BUILTIN_VPMADD52LUQ512,
30424 IX86_BUILTIN_VPMADD52HUQ512,
30425 IX86_BUILTIN_VPMADD52LUQ256,
30426 IX86_BUILTIN_VPMADD52HUQ256,
30427 IX86_BUILTIN_VPMADD52LUQ128,
30428 IX86_BUILTIN_VPMADD52HUQ128,
30429 IX86_BUILTIN_VPMADD52LUQ512_MASKZ,
30430 IX86_BUILTIN_VPMADD52HUQ512_MASKZ,
30431 IX86_BUILTIN_VPMADD52LUQ256_MASKZ,
30432 IX86_BUILTIN_VPMADD52HUQ256_MASKZ,
30433 IX86_BUILTIN_VPMADD52LUQ128_MASKZ,
30434 IX86_BUILTIN_VPMADD52HUQ128_MASKZ,
30436 /* AVX-512VBMI */
30437 IX86_BUILTIN_VPMULTISHIFTQB512,
30438 IX86_BUILTIN_VPMULTISHIFTQB256,
30439 IX86_BUILTIN_VPMULTISHIFTQB128,
30440 IX86_BUILTIN_VPERMVARQI512_MASK,
30441 IX86_BUILTIN_VPERMT2VARQI512,
30442 IX86_BUILTIN_VPERMT2VARQI512_MASKZ,
30443 IX86_BUILTIN_VPERMI2VARQI512,
30444 IX86_BUILTIN_VPERMVARQI256_MASK,
30445 IX86_BUILTIN_VPERMVARQI128_MASK,
30446 IX86_BUILTIN_VPERMT2VARQI256,
30447 IX86_BUILTIN_VPERMT2VARQI256_MASKZ,
30448 IX86_BUILTIN_VPERMT2VARQI128,
30449 IX86_BUILTIN_VPERMT2VARQI128_MASKZ,
30450 IX86_BUILTIN_VPERMI2VARQI256,
30451 IX86_BUILTIN_VPERMI2VARQI128,
30453 /* SHA builtins. */
30454 IX86_BUILTIN_SHA1MSG1,
30455 IX86_BUILTIN_SHA1MSG2,
30456 IX86_BUILTIN_SHA1NEXTE,
30457 IX86_BUILTIN_SHA1RNDS4,
30458 IX86_BUILTIN_SHA256MSG1,
30459 IX86_BUILTIN_SHA256MSG2,
30460 IX86_BUILTIN_SHA256RNDS2,
30462 /* CLWB instructions. */
30463 IX86_BUILTIN_CLWB,
30465 /* PCOMMIT instructions. */
30466 IX86_BUILTIN_PCOMMIT,
30468 /* CLFLUSHOPT instructions. */
30469 IX86_BUILTIN_CLFLUSHOPT,
30471 /* TFmode support builtins. */
30472 IX86_BUILTIN_INFQ,
30473 IX86_BUILTIN_HUGE_VALQ,
30474 IX86_BUILTIN_FABSQ,
30475 IX86_BUILTIN_COPYSIGNQ,
30477 /* Vectorizer support builtins. */
30478 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
30479 IX86_BUILTIN_CPYSGNPS,
30480 IX86_BUILTIN_CPYSGNPD,
30481 IX86_BUILTIN_CPYSGNPS256,
30482 IX86_BUILTIN_CPYSGNPS512,
30483 IX86_BUILTIN_CPYSGNPD256,
30484 IX86_BUILTIN_CPYSGNPD512,
30485 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
30486 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
30489 /* FMA4 instructions. */
30490 IX86_BUILTIN_VFMADDSS,
30491 IX86_BUILTIN_VFMADDSD,
30492 IX86_BUILTIN_VFMADDPS,
30493 IX86_BUILTIN_VFMADDPD,
30494 IX86_BUILTIN_VFMADDPS256,
30495 IX86_BUILTIN_VFMADDPD256,
30496 IX86_BUILTIN_VFMADDSUBPS,
30497 IX86_BUILTIN_VFMADDSUBPD,
30498 IX86_BUILTIN_VFMADDSUBPS256,
30499 IX86_BUILTIN_VFMADDSUBPD256,
30501 /* FMA3 instructions. */
30502 IX86_BUILTIN_VFMADDSS3,
30503 IX86_BUILTIN_VFMADDSD3,
30505 /* XOP instructions. */
30506 IX86_BUILTIN_VPCMOV,
30507 IX86_BUILTIN_VPCMOV_V2DI,
30508 IX86_BUILTIN_VPCMOV_V4SI,
30509 IX86_BUILTIN_VPCMOV_V8HI,
30510 IX86_BUILTIN_VPCMOV_V16QI,
30511 IX86_BUILTIN_VPCMOV_V4SF,
30512 IX86_BUILTIN_VPCMOV_V2DF,
30513 IX86_BUILTIN_VPCMOV256,
30514 IX86_BUILTIN_VPCMOV_V4DI256,
30515 IX86_BUILTIN_VPCMOV_V8SI256,
30516 IX86_BUILTIN_VPCMOV_V16HI256,
30517 IX86_BUILTIN_VPCMOV_V32QI256,
30518 IX86_BUILTIN_VPCMOV_V8SF256,
30519 IX86_BUILTIN_VPCMOV_V4DF256,
30521 IX86_BUILTIN_VPPERM,
30523 IX86_BUILTIN_VPMACSSWW,
30524 IX86_BUILTIN_VPMACSWW,
30525 IX86_BUILTIN_VPMACSSWD,
30526 IX86_BUILTIN_VPMACSWD,
30527 IX86_BUILTIN_VPMACSSDD,
30528 IX86_BUILTIN_VPMACSDD,
30529 IX86_BUILTIN_VPMACSSDQL,
30530 IX86_BUILTIN_VPMACSSDQH,
30531 IX86_BUILTIN_VPMACSDQL,
30532 IX86_BUILTIN_VPMACSDQH,
30533 IX86_BUILTIN_VPMADCSSWD,
30534 IX86_BUILTIN_VPMADCSWD,
30536 IX86_BUILTIN_VPHADDBW,
30537 IX86_BUILTIN_VPHADDBD,
30538 IX86_BUILTIN_VPHADDBQ,
30539 IX86_BUILTIN_VPHADDWD,
30540 IX86_BUILTIN_VPHADDWQ,
30541 IX86_BUILTIN_VPHADDDQ,
30542 IX86_BUILTIN_VPHADDUBW,
30543 IX86_BUILTIN_VPHADDUBD,
30544 IX86_BUILTIN_VPHADDUBQ,
30545 IX86_BUILTIN_VPHADDUWD,
30546 IX86_BUILTIN_VPHADDUWQ,
30547 IX86_BUILTIN_VPHADDUDQ,
30548 IX86_BUILTIN_VPHSUBBW,
30549 IX86_BUILTIN_VPHSUBWD,
30550 IX86_BUILTIN_VPHSUBDQ,
30552 IX86_BUILTIN_VPROTB,
30553 IX86_BUILTIN_VPROTW,
30554 IX86_BUILTIN_VPROTD,
30555 IX86_BUILTIN_VPROTQ,
30556 IX86_BUILTIN_VPROTB_IMM,
30557 IX86_BUILTIN_VPROTW_IMM,
30558 IX86_BUILTIN_VPROTD_IMM,
30559 IX86_BUILTIN_VPROTQ_IMM,
30561 IX86_BUILTIN_VPSHLB,
30562 IX86_BUILTIN_VPSHLW,
30563 IX86_BUILTIN_VPSHLD,
30564 IX86_BUILTIN_VPSHLQ,
30565 IX86_BUILTIN_VPSHAB,
30566 IX86_BUILTIN_VPSHAW,
30567 IX86_BUILTIN_VPSHAD,
30568 IX86_BUILTIN_VPSHAQ,
30570 IX86_BUILTIN_VFRCZSS,
30571 IX86_BUILTIN_VFRCZSD,
30572 IX86_BUILTIN_VFRCZPS,
30573 IX86_BUILTIN_VFRCZPD,
30574 IX86_BUILTIN_VFRCZPS256,
30575 IX86_BUILTIN_VFRCZPD256,
30577 IX86_BUILTIN_VPCOMEQUB,
30578 IX86_BUILTIN_VPCOMNEUB,
30579 IX86_BUILTIN_VPCOMLTUB,
30580 IX86_BUILTIN_VPCOMLEUB,
30581 IX86_BUILTIN_VPCOMGTUB,
30582 IX86_BUILTIN_VPCOMGEUB,
30583 IX86_BUILTIN_VPCOMFALSEUB,
30584 IX86_BUILTIN_VPCOMTRUEUB,
30586 IX86_BUILTIN_VPCOMEQUW,
30587 IX86_BUILTIN_VPCOMNEUW,
30588 IX86_BUILTIN_VPCOMLTUW,
30589 IX86_BUILTIN_VPCOMLEUW,
30590 IX86_BUILTIN_VPCOMGTUW,
30591 IX86_BUILTIN_VPCOMGEUW,
30592 IX86_BUILTIN_VPCOMFALSEUW,
30593 IX86_BUILTIN_VPCOMTRUEUW,
30595 IX86_BUILTIN_VPCOMEQUD,
30596 IX86_BUILTIN_VPCOMNEUD,
30597 IX86_BUILTIN_VPCOMLTUD,
30598 IX86_BUILTIN_VPCOMLEUD,
30599 IX86_BUILTIN_VPCOMGTUD,
30600 IX86_BUILTIN_VPCOMGEUD,
30601 IX86_BUILTIN_VPCOMFALSEUD,
30602 IX86_BUILTIN_VPCOMTRUEUD,
30604 IX86_BUILTIN_VPCOMEQUQ,
30605 IX86_BUILTIN_VPCOMNEUQ,
30606 IX86_BUILTIN_VPCOMLTUQ,
30607 IX86_BUILTIN_VPCOMLEUQ,
30608 IX86_BUILTIN_VPCOMGTUQ,
30609 IX86_BUILTIN_VPCOMGEUQ,
30610 IX86_BUILTIN_VPCOMFALSEUQ,
30611 IX86_BUILTIN_VPCOMTRUEUQ,
30613 IX86_BUILTIN_VPCOMEQB,
30614 IX86_BUILTIN_VPCOMNEB,
30615 IX86_BUILTIN_VPCOMLTB,
30616 IX86_BUILTIN_VPCOMLEB,
30617 IX86_BUILTIN_VPCOMGTB,
30618 IX86_BUILTIN_VPCOMGEB,
30619 IX86_BUILTIN_VPCOMFALSEB,
30620 IX86_BUILTIN_VPCOMTRUEB,
30622 IX86_BUILTIN_VPCOMEQW,
30623 IX86_BUILTIN_VPCOMNEW,
30624 IX86_BUILTIN_VPCOMLTW,
30625 IX86_BUILTIN_VPCOMLEW,
30626 IX86_BUILTIN_VPCOMGTW,
30627 IX86_BUILTIN_VPCOMGEW,
30628 IX86_BUILTIN_VPCOMFALSEW,
30629 IX86_BUILTIN_VPCOMTRUEW,
30631 IX86_BUILTIN_VPCOMEQD,
30632 IX86_BUILTIN_VPCOMNED,
30633 IX86_BUILTIN_VPCOMLTD,
30634 IX86_BUILTIN_VPCOMLED,
30635 IX86_BUILTIN_VPCOMGTD,
30636 IX86_BUILTIN_VPCOMGED,
30637 IX86_BUILTIN_VPCOMFALSED,
30638 IX86_BUILTIN_VPCOMTRUED,
30640 IX86_BUILTIN_VPCOMEQQ,
30641 IX86_BUILTIN_VPCOMNEQ,
30642 IX86_BUILTIN_VPCOMLTQ,
30643 IX86_BUILTIN_VPCOMLEQ,
30644 IX86_BUILTIN_VPCOMGTQ,
30645 IX86_BUILTIN_VPCOMGEQ,
30646 IX86_BUILTIN_VPCOMFALSEQ,
30647 IX86_BUILTIN_VPCOMTRUEQ,
30649 /* LWP instructions. */
30650 IX86_BUILTIN_LLWPCB,
30651 IX86_BUILTIN_SLWPCB,
30652 IX86_BUILTIN_LWPVAL32,
30653 IX86_BUILTIN_LWPVAL64,
30654 IX86_BUILTIN_LWPINS32,
30655 IX86_BUILTIN_LWPINS64,
30657 IX86_BUILTIN_CLZS,
30659 /* RTM */
30660 IX86_BUILTIN_XBEGIN,
30661 IX86_BUILTIN_XEND,
30662 IX86_BUILTIN_XABORT,
30663 IX86_BUILTIN_XTEST,
30665 /* MPX */
30666 IX86_BUILTIN_BNDMK,
30667 IX86_BUILTIN_BNDSTX,
30668 IX86_BUILTIN_BNDLDX,
30669 IX86_BUILTIN_BNDCL,
30670 IX86_BUILTIN_BNDCU,
30671 IX86_BUILTIN_BNDRET,
30672 IX86_BUILTIN_BNDNARROW,
30673 IX86_BUILTIN_BNDINT,
30674 IX86_BUILTIN_SIZEOF,
30675 IX86_BUILTIN_BNDLOWER,
30676 IX86_BUILTIN_BNDUPPER,
30678 /* BMI instructions. */
30679 IX86_BUILTIN_BEXTR32,
30680 IX86_BUILTIN_BEXTR64,
30681 IX86_BUILTIN_CTZS,
30683 /* TBM instructions. */
30684 IX86_BUILTIN_BEXTRI32,
30685 IX86_BUILTIN_BEXTRI64,
30687 /* BMI2 instructions. */
30688 IX86_BUILTIN_BZHI32,
30689 IX86_BUILTIN_BZHI64,
30690 IX86_BUILTIN_PDEP32,
30691 IX86_BUILTIN_PDEP64,
30692 IX86_BUILTIN_PEXT32,
30693 IX86_BUILTIN_PEXT64,
30695 /* ADX instructions. */
30696 IX86_BUILTIN_ADDCARRYX32,
30697 IX86_BUILTIN_ADDCARRYX64,
30699 /* SBB instructions. */
30700 IX86_BUILTIN_SBB32,
30701 IX86_BUILTIN_SBB64,
30703 /* FSGSBASE instructions. */
30704 IX86_BUILTIN_RDFSBASE32,
30705 IX86_BUILTIN_RDFSBASE64,
30706 IX86_BUILTIN_RDGSBASE32,
30707 IX86_BUILTIN_RDGSBASE64,
30708 IX86_BUILTIN_WRFSBASE32,
30709 IX86_BUILTIN_WRFSBASE64,
30710 IX86_BUILTIN_WRGSBASE32,
30711 IX86_BUILTIN_WRGSBASE64,
30713 /* RDRND instructions. */
30714 IX86_BUILTIN_RDRAND16_STEP,
30715 IX86_BUILTIN_RDRAND32_STEP,
30716 IX86_BUILTIN_RDRAND64_STEP,
30718 /* RDSEED instructions. */
30719 IX86_BUILTIN_RDSEED16_STEP,
30720 IX86_BUILTIN_RDSEED32_STEP,
30721 IX86_BUILTIN_RDSEED64_STEP,
30723 /* F16C instructions. */
30724 IX86_BUILTIN_CVTPH2PS,
30725 IX86_BUILTIN_CVTPH2PS256,
30726 IX86_BUILTIN_CVTPS2PH,
30727 IX86_BUILTIN_CVTPS2PH256,
30729 /* MONITORX and MWAITX instrucions. */
30730 IX86_BUILTIN_MONITORX,
30731 IX86_BUILTIN_MWAITX,
30733 /* CFString built-in for darwin */
30734 IX86_BUILTIN_CFSTRING,
30736 /* Builtins to get CPU type and supported features. */
30737 IX86_BUILTIN_CPU_INIT,
30738 IX86_BUILTIN_CPU_IS,
30739 IX86_BUILTIN_CPU_SUPPORTS,
30741 /* Read/write FLAGS register built-ins. */
30742 IX86_BUILTIN_READ_FLAGS,
30743 IX86_BUILTIN_WRITE_FLAGS,
30745 IX86_BUILTIN_MAX
30746 };
30748 /* Table for the ix86 builtin decls. */
30751 /* Table of all of the builtin functions that are possible with different ISA's
30752 but are waiting to be built until a function is declared to use that
30753 ISA. */
30762 };
30766 /* Bits that can still enable any inclusion of a builtin. */
30769 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
30770 of which isa_flags to use in the ix86_builtins_isa array. Stores the
30771 function decl in the ix86_builtins array. Returns the function decl or
30772 NULL_TREE, if the builtin was not added.
30774 If the front end has a special hook for builtin functions, delay adding
30775 builtin functions that aren't in the current ISA until the ISA is changed
30776 with function specific optimization. Doing so, can save about 300K for the
30777 default compiler. When the builtin is expanded, check at that time whether
30778 it is valid.
30780 If the front end doesn't have a special hook, record all builtins, even if
30781 it isn't an instruction set in the current ISA in case the user uses
30782 function specific options for a different ISA, so that we don't get scope
30783 errors if a builtin is added in the middle of a function scope. */
30789 {
30793 {
30802 {
30808 }
30809 else
30810 {
30811 /* Just a MASK where set_and_not_built_p == true can potentially
30812 include a builtin. */
30821 }
30822 }
30825 }
30827 /* Like def_builtin, but also marks the function decl "const". */
30832 {
30836 else
30840 }
30842 /* Add any new builtin functions for a given ISA that may not have been
30843 declared. This saves a bit of space compared to adding all of the
30844 declarations to the tree, even if we didn't use them. */
30846 static void
30848 {
30852 /* Bits in ISA value can be removed from potential isa values. */
30860 {
30863 {
30866 /* Don't define the builtin again. */
30872 NULL_TREE);
30879 NULL_TREE);
30882 }
30883 }
30886 }
30888 /* Bits for builtin_description.flag. */
30890 /* Set when we don't support the comparison natively, and should
30891 swap_comparison in order to support it. */
30892 #define BUILTIN_DESC_SWAP_OPERANDS 1
30894 struct builtin_description
30895 {
30902 };
30905 {
30906 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
30907 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
30908 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
30909 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
30910 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
30911 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
30912 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
30913 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
30914 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
30915 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
30916 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
30917 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
30918 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
30919 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
30920 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
30921 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
30922 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
30923 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
30924 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
30925 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
30926 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
30927 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
30928 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
30929 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
30930 };
30933 {
30934 /* SSE4.2 */
30935 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
30936 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
30937 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
30938 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
30939 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
30940 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
30941 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
30942 };
30945 {
30946 /* SSE4.2 */
30947 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
30948 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
30949 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
30950 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
30951 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
30952 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
30953 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
30954 };
30956 /* Special builtins with variable number of arguments. */
30958 {
30959 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
30960 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
30961 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
30963 /* 80387 (for use internally for atomic compound assignment). */
30964 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
30965 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
30966 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) USHORT_FTYPE_VOID },
30967 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
30969 /* MMX */
30970 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30972 /* 3DNow! */
30973 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30975 /* FXSR, XSAVE, XSAVEOPT, XSAVEC and XSAVES. */
30976 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
30977 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
30978 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30979 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30980 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30981 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xsaves", IX86_BUILTIN_XSAVES, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30982 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xrstors", IX86_BUILTIN_XRSTORS, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30983 { OPTION_MASK_ISA_XSAVEC, CODE_FOR_nothing, "__builtin_ia32_xsavec", IX86_BUILTIN_XSAVEC, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30985 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30986 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30987 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30988 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30989 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30990 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaves64", IX86_BUILTIN_XSAVES64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30991 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30992 { OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30994 /* SSE */
30995 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30996 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30997 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30999 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
31000 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
31001 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
31002 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
31004 /* SSE or 3DNow!A */
31005 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
31006 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
31008 /* SSE2 */
31009 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
31010 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
31011 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
31012 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
31013 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
31014 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
31015 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
31016 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
31017 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
31018 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
31020 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
31021 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
31023 /* SSE3 */
31024 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
31026 /* SSE4.1 */
31027 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
31029 /* SSE4A */
31030 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
31031 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
31033 /* AVX */
31034 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
31035 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
31037 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
31038 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
31039 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
31040 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
31041 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
31043 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
31044 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
31045 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
31046 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
31047 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
31048 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
31049 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
31051 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
31052 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
31053 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
31055 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
31056 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
31057 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
31058 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
31059 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
31060 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
31061 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
31062 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
31064 /* AVX2 */
31065 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
31066 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
31067 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
31068 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
31069 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
31070 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
31071 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
31072 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
31073 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
31075 /* AVX512F */
31076 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
31077 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
31078 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
31079 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
31080 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
31081 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
31082 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
31083 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
31084 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
31085 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
31086 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
31087 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
31088 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
31089 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
31090 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
31091 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
31092 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
31093 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
31094 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
31095 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
31096 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
31097 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
31098 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
31099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
31100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
31101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
31102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
31103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
31104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
31105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
31106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
31107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
31108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
31109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
31110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
31111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
31112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
31113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
31114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
31115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
31116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
31117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
31118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
31119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
31120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
31121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
31122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
31124 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
31125 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
31126 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
31127 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
31128 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
31129 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
31131 /* FSGSBASE */
31132 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
31133 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
31134 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
31135 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
31136 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
31137 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
31138 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
31139 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
31141 /* RTM */
31142 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
31143 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
31144 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
31146 /* AVX512BW */
31147 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_loaddquhi512_mask", IX86_BUILTIN_LOADDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_SI },
31148 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_loaddquqi512_mask", IX86_BUILTIN_LOADDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_DI },
31149 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv32hi_mask, "__builtin_ia32_storedquhi512_mask", IX86_BUILTIN_STOREDQUHI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV32HI_V32HI_SI },
31150 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_DI },
31152 /* AVX512VL */
31153 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_HI },
31154 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_loaddquhi128_mask", IX86_BUILTIN_LOADDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_QI },
31155 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_loaddquqi256_mask", IX86_BUILTIN_LOADDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_SI },
31156 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_loaddquqi128_mask", IX86_BUILTIN_LOADDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_HI },
31157 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64load256_mask", IX86_BUILTIN_MOVDQA64LOAD256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31158 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64load128_mask", IX86_BUILTIN_MOVDQA64LOAD128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31159 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32load256_mask", IX86_BUILTIN_MOVDQA32LOAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31160 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32load128_mask", IX86_BUILTIN_MOVDQA32LOAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31161 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4di_mask, "__builtin_ia32_movdqa64store256_mask", IX86_BUILTIN_MOVDQA64STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
31162 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2di_mask, "__builtin_ia32_movdqa64store128_mask", IX86_BUILTIN_MOVDQA64STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
31163 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8si_mask, "__builtin_ia32_movdqa32store256_mask", IX86_BUILTIN_MOVDQA32STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
31164 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4si_mask, "__builtin_ia32_movdqa32store128_mask", IX86_BUILTIN_MOVDQA32STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
31165 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_loadapd256_mask", IX86_BUILTIN_LOADAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31166 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_loadapd128_mask", IX86_BUILTIN_LOADAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31167 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_loadaps256_mask", IX86_BUILTIN_LOADAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31168 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_loadaps128_mask", IX86_BUILTIN_LOADAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31169 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4df_mask, "__builtin_ia32_storeapd256_mask", IX86_BUILTIN_STOREAPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
31170 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2df_mask, "__builtin_ia32_storeapd128_mask", IX86_BUILTIN_STOREAPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
31171 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8sf_mask, "__builtin_ia32_storeaps256_mask", IX86_BUILTIN_STOREAPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
31172 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4sf_mask, "__builtin_ia32_storeaps128_mask", IX86_BUILTIN_STOREAPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
31173 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadupd256_mask, "__builtin_ia32_loadupd256_mask", IX86_BUILTIN_LOADUPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31174 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loadupd_mask, "__builtin_ia32_loadupd128_mask", IX86_BUILTIN_LOADUPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31175 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadups256_mask, "__builtin_ia32_loadups256_mask", IX86_BUILTIN_LOADUPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31176 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_loadups_mask, "__builtin_ia32_loadups128_mask", IX86_BUILTIN_LOADUPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31177 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd256_mask, "__builtin_ia32_storeupd256_mask", IX86_BUILTIN_STOREUPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
31178 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd_mask, "__builtin_ia32_storeupd128_mask", IX86_BUILTIN_STOREUPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
31179 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups256_mask, "__builtin_ia32_storeups256_mask", IX86_BUILTIN_STOREUPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
31180 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups_mask, "__builtin_ia32_storeups128_mask", IX86_BUILTIN_STOREUPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
31181 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv4di_mask, "__builtin_ia32_loaddqudi256_mask", IX86_BUILTIN_LOADDQUDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31182 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv2di_mask, "__builtin_ia32_loaddqudi128_mask", IX86_BUILTIN_LOADDQUDI128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31183 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv8si_mask, "__builtin_ia32_loaddqusi256_mask", IX86_BUILTIN_LOADDQUSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31184 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv4si_mask, "__builtin_ia32_loaddqusi128_mask", IX86_BUILTIN_LOADDQUSI128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31185 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4di_mask, "__builtin_ia32_storedqudi256_mask", IX86_BUILTIN_STOREDQUDI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
31186 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv2di_mask, "__builtin_ia32_storedqudi128_mask", IX86_BUILTIN_STOREDQUDI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
31187 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8si_mask, "__builtin_ia32_storedqusi256_mask", IX86_BUILTIN_STOREDQUSI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
31188 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4si_mask, "__builtin_ia32_storedqusi128_mask", IX86_BUILTIN_STOREDQUSI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
31189 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16hi_mask, "__builtin_ia32_storedquhi256_mask", IX86_BUILTIN_STOREDQUHI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16HI_HI },
31190 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8hi_mask, "__builtin_ia32_storedquhi128_mask", IX86_BUILTIN_STOREDQUHI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8HI_QI },
31191 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv32qi_mask, "__builtin_ia32_storedquqi256_mask", IX86_BUILTIN_STOREDQUQI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV32QI_V32QI_SI },
31192 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16qi_mask, "__builtin_ia32_storedquqi128_mask", IX86_BUILTIN_STOREDQUQI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16QI_HI },
31193 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4df_mask, "__builtin_ia32_compressstoredf256_mask", IX86_BUILTIN_COMPRESSPDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
31194 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2df_mask, "__builtin_ia32_compressstoredf128_mask", IX86_BUILTIN_COMPRESSPDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
31195 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8sf_mask, "__builtin_ia32_compressstoresf256_mask", IX86_BUILTIN_COMPRESSPSSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
31196 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4sf_mask, "__builtin_ia32_compressstoresf128_mask", IX86_BUILTIN_COMPRESSPSSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
31197 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4di_mask, "__builtin_ia32_compressstoredi256_mask", IX86_BUILTIN_PCOMPRESSQSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
31198 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2di_mask, "__builtin_ia32_compressstoredi128_mask", IX86_BUILTIN_PCOMPRESSQSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
31199 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8si_mask, "__builtin_ia32_compressstoresi256_mask", IX86_BUILTIN_PCOMPRESSDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
31200 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4si_mask, "__builtin_ia32_compressstoresi128_mask", IX86_BUILTIN_PCOMPRESSDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
31201 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expandloaddf256_mask", IX86_BUILTIN_EXPANDPDLOAD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31202 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expandloaddf128_mask", IX86_BUILTIN_EXPANDPDLOAD128, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31203 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandloadsf256_mask", IX86_BUILTIN_EXPANDPSLOAD256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31204 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandloadsf128_mask", IX86_BUILTIN_EXPANDPSLOAD128, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31205 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expandloaddi256_mask", IX86_BUILTIN_PEXPANDQLOAD256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31206 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expandloaddi128_mask", IX86_BUILTIN_PEXPANDQLOAD128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31207 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandloadsi256_mask", IX86_BUILTIN_PEXPANDDLOAD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31208 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandloadsi128_mask", IX86_BUILTIN_PEXPANDDLOAD128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31209 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expandloaddf256_maskz", IX86_BUILTIN_EXPANDPDLOAD256Z, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31210 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expandloaddf128_maskz", IX86_BUILTIN_EXPANDPDLOAD128Z, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31211 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandloadsf256_maskz", IX86_BUILTIN_EXPANDPSLOAD256Z, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31212 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandloadsf128_maskz", IX86_BUILTIN_EXPANDPSLOAD128Z, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31213 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expandloaddi256_maskz", IX86_BUILTIN_PEXPANDQLOAD256Z, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31214 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expandloaddi128_maskz", IX86_BUILTIN_PEXPANDQLOAD128Z, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31215 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandloadsi256_maskz", IX86_BUILTIN_PEXPANDDLOAD256Z, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31216 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandloadsi128_maskz", IX86_BUILTIN_PEXPANDDLOAD128Z, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31217 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask_store, "__builtin_ia32_pmovqd256mem_mask", IX86_BUILTIN_PMOVQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
31218 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask_store, "__builtin_ia32_pmovqd128mem_mask", IX86_BUILTIN_PMOVQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
31219 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask_store, "__builtin_ia32_pmovsqd256mem_mask", IX86_BUILTIN_PMOVSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
31220 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask_store, "__builtin_ia32_pmovsqd128mem_mask", IX86_BUILTIN_PMOVSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
31221 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask_store, "__builtin_ia32_pmovusqd256mem_mask", IX86_BUILTIN_PMOVUSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
31222 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask_store, "__builtin_ia32_pmovusqd128mem_mask", IX86_BUILTIN_PMOVUSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
31223 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovqw256mem_mask", IX86_BUILTIN_PMOVQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
31224 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovqw128mem_mask", IX86_BUILTIN_PMOVQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
31225 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovsqw256mem_mask", IX86_BUILTIN_PMOVSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
31226 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovsqw128mem_mask", IX86_BUILTIN_PMOVSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
31227 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovusqw256mem_mask", IX86_BUILTIN_PMOVUSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
31228 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovusqw128mem_mask", IX86_BUILTIN_PMOVUSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
31229 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovqb256mem_mask", IX86_BUILTIN_PMOVQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
31230 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovqb128mem_mask", IX86_BUILTIN_PMOVQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
31231 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovsqb256mem_mask", IX86_BUILTIN_PMOVSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
31232 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovsqb128mem_mask", IX86_BUILTIN_PMOVSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
31233 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovusqb256mem_mask", IX86_BUILTIN_PMOVUSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
31234 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovusqb128mem_mask", IX86_BUILTIN_PMOVUSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
31235 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovdb256mem_mask", IX86_BUILTIN_PMOVDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
31236 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovdb128mem_mask", IX86_BUILTIN_PMOVDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
31237 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovsdb256mem_mask", IX86_BUILTIN_PMOVSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
31238 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovsdb128mem_mask", IX86_BUILTIN_PMOVSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
31239 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovusdb256mem_mask", IX86_BUILTIN_PMOVUSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
31240 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovusdb128mem_mask", IX86_BUILTIN_PMOVUSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
31241 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovdw256mem_mask", IX86_BUILTIN_PMOVDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
31242 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovdw128mem_mask", IX86_BUILTIN_PMOVDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
31243 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovsdw256mem_mask", IX86_BUILTIN_PMOVSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
31244 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
31245 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
31246 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
31248 /* PCOMMIT. */
31249 { OPTION_MASK_ISA_PCOMMIT, CODE_FOR_pcommit, "__builtin_ia32_pcommit", IX86_BUILTIN_PCOMMIT, UNKNOWN, (int) VOID_FTYPE_VOID },
31250 };
31252 /* Builtins with variable number of arguments. */
31254 {
31255 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
31256 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
31257 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
31258 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
31259 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
31260 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
31261 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
31263 /* MMX */
31264 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31265 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31266 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31267 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31268 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31269 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31271 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31272 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31273 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31274 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31275 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31276 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31277 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31278 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31280 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31281 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31283 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31284 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31285 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31286 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31288 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31289 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31290 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31291 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31292 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31293 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31295 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31296 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31297 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31298 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31299 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
31300 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
31302 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31303 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
31304 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31306 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
31308 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31309 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31310 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31311 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31312 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31313 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31315 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31316 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31317 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31318 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31319 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31320 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31322 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31323 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31324 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31325 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31327 /* 3DNow! */
31328 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31329 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31330 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31331 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31333 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31334 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31335 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31336 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31337 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31338 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31339 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31340 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31341 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31342 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31343 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31344 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31345 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31346 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31347 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31349 /* 3DNow!A */
31350 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31351 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31352 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31353 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31354 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31355 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31357 /* SSE */
31358 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
31359 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31360 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31361 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31362 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31363 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31364 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31365 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31366 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31367 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31368 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31369 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31371 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31373 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31374 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31375 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31376 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31377 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31378 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31379 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31380 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31382 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31383 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31384 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31385 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31386 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31387 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31388 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31389 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31390 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31391 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31392 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
31393 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31394 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31395 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31396 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31397 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31398 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31399 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31400 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31401 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31403 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31404 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31405 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31406 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31408 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31409 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31410 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31411 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31413 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31415 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31416 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31417 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31418 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31419 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31421 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
31422 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
31423 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
31425 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
31427 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31428 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31429 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31431 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
31432 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
31434 /* SSE MMX or 3Dnow!A */
31435 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31436 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31437 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31439 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31440 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31441 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31442 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31444 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
31445 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
31447 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
31449 /* SSE2 */
31450 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31452 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
31453 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
31454 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31455 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
31456 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
31458 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31459 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31460 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
31461 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31462 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31464 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
31466 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31467 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31468 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31469 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31471 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31472 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
31473 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31475 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31476 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31477 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31478 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31479 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31480 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31481 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31482 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31484 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31485 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31486 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31487 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31488 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
31489 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31490 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31491 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31492 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31493 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31494 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31495 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31496 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31497 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31498 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31499 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31500 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31501 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31502 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31503 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31505 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31506 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31507 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31508 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31510 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31511 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31512 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31513 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31515 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31517 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31518 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31519 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31521 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31523 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31524 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31525 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31526 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31527 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31528 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31529 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31530 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31532 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31533 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31534 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31535 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31536 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31537 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31538 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31539 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31541 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31542 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
31544 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31545 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31546 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31547 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31549 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31550 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31552 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31553 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31554 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31555 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31556 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31557 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31559 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31560 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31561 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31562 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31564 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31565 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31566 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31567 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31568 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31569 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31570 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31571 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31573 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31574 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31575 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31577 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31578 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
31580 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
31581 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31583 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
31585 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
31586 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
31587 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
31588 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
31590 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31591 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31592 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31593 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31594 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31595 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31596 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31598 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31599 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31600 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31601 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31602 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31603 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31604 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31606 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31607 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31608 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31609 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31611 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
31612 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31613 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31615 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
31617 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31619 /* SSE2 MMX */
31620 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31621 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31623 /* SSE3 */
31624 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
31625 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31627 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31628 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31629 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31630 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31631 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31632 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31634 /* SSSE3 */
31635 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31636 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
31637 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31638 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
31639 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31640 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31642 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31643 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31644 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31645 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31646 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31647 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31648 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31649 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31650 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31651 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31652 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31653 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31654 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
31655 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
31656 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31657 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31658 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31659 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31660 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31661 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31662 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31663 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31664 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31665 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31667 /* SSSE3. */
31668 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
31669 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
31671 /* SSE4.1 */
31672 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31673 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31674 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
31675 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
31676 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31677 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31678 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31679 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
31680 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
31681 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
31683 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31684 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31685 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31686 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31687 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31688 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31689 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31690 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31691 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31692 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31693 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31694 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31695 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31697 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31698 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31699 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31700 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31701 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31702 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31703 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31704 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31705 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31706 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31707 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31708 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31710 /* SSE4.1 */
31711 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31712 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31713 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31714 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31716 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
31717 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
31718 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
31719 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
31721 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31722 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31724 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31725 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31727 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
31728 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
31729 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
31730 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
31732 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
31733 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
31735 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31736 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31738 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31739 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31740 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31742 /* SSE4.2 */
31743 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31744 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
31745 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
31746 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31747 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31749 /* SSE4A */
31750 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
31751 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
31752 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
31753 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31755 /* AES */
31756 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
31757 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31759 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31760 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31761 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31762 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31764 /* PCLMUL */
31765 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
31767 /* AVX */
31768 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31769 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31770 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31771 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31772 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31773 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31774 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31775 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31776 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31777 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31778 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31779 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31780 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31781 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31782 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31783 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31784 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31785 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31786 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31787 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31788 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31789 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31790 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31791 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31792 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31793 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31795 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
31796 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
31797 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
31798 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31800 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31801 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31802 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
31803 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
31804 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31805 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31806 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31807 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31808 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31809 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31810 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31811 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31812 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31813 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
31814 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
31815 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
31816 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
31817 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
31818 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
31819 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31820 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
31821 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31822 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31823 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31824 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31825 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31826 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31827 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31828 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31829 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31830 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31831 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
31832 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
31833 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
31835 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31836 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31837 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31839 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31840 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31841 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31842 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31843 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31845 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31847 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31848 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31850 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
31851 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
31852 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
31853 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
31855 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31856 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31858 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31859 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31861 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
31862 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
31863 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
31864 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
31866 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
31867 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
31869 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31870 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31872 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31873 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31874 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31875 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31877 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31878 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31879 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31880 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
31881 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
31882 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
31884 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31885 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31886 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31887 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31888 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31889 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31890 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31891 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31892 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31893 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31894 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31895 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31896 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31897 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31898 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31900 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
31901 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
31903 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31904 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31906 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31908 /* AVX2 */
31909 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
31910 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
31911 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
31912 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
31913 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31914 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31915 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31916 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31917 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31918 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31919 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31920 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31921 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31922 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31923 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31924 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31925 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
31926 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31927 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31928 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31929 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31930 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
31931 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
31932 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31933 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31934 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31935 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31936 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31937 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31938 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31939 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31940 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31941 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31942 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31943 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31944 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31945 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31946 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31947 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
31948 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31949 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31950 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31951 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31952 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31953 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31954 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31955 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31956 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31957 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31958 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31959 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31960 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
31961 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31962 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31963 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31964 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31965 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31966 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31967 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31968 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31969 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31970 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31971 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31972 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31973 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31974 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31975 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31976 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31977 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31978 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31979 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31980 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31981 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31982 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31983 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
31984 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31985 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31986 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31987 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31988 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31989 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31990 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31991 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31992 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31993 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31994 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31995 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31996 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31997 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31998 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31999 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
32000 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
32001 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
32002 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
32003 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
32004 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
32005 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
32006 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
32007 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32008 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
32009 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32010 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32011 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32012 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
32013 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32014 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
32015 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32016 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
32017 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32018 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32019 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
32020 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
32021 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32022 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32023 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32024 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
32025 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
32026 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
32027 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
32028 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
32029 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
32030 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
32031 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
32032 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
32033 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
32034 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
32035 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
32036 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
32037 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
32038 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32039 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
32040 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
32041 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
32042 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
32043 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vextractf128v4di, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
32044 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vinsertf128v4di, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
32045 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32046 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
32047 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32048 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32049 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32050 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32051 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
32052 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
32053 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
32054 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32056 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
32058 /* BMI */
32059 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32060 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32061 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
32063 /* TBM */
32064 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32065 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32067 /* F16C */
32068 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
32069 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
32070 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
32071 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
32073 /* BMI2 */
32074 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32075 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32076 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32077 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32078 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
32079 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
32081 /* AVX512F */
32082 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_256si, "__builtin_ia32_si512_256si", IX86_BUILTIN_SI512_SI256, UNKNOWN, (int) V16SI_FTYPE_V8SI },
32083 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_256ps, "__builtin_ia32_ps512_256ps", IX86_BUILTIN_PS512_PS256, UNKNOWN, (int) V16SF_FTYPE_V8SF },
32084 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_256pd, "__builtin_ia32_pd512_256pd", IX86_BUILTIN_PD512_PD256, UNKNOWN, (int) V8DF_FTYPE_V4DF },
32085 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_si, "__builtin_ia32_si512_si", IX86_BUILTIN_SI512_SI, UNKNOWN, (int) V16SI_FTYPE_V4SI },
32086 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_ps, "__builtin_ia32_ps512_ps", IX86_BUILTIN_PS512_PS, UNKNOWN, (int) V16SF_FTYPE_V4SF },
32087 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_pd, "__builtin_ia32_pd512_pd", IX86_BUILTIN_PD512_PD, UNKNOWN, (int) V8DF_FTYPE_V2DF },
32088 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
32089 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
32090 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32091 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32092 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32093 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32094 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
32095 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
32096 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
32097 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
32098 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
32099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
32100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
32101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
32102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
32105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
32106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
32107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
32108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
32113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
32114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
32115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
32116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
32117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
32118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
32119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
32120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32125 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32129 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32130 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32134 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32135 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
32136 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
32137 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
32138 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
32139 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
32140 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
32141 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
32142 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32143 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
32144 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32145 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32146 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32147 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32148 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32149 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32150 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32151 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32152 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32153 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32154 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32155 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32156 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32157 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32158 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32159 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
32160 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
32161 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
32162 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
32163 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
32164 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
32165 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
32166 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
32167 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
32168 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
32169 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
32170 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
32171 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
32172 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
32173 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
32174 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
32175 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
32176 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
32177 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
32178 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
32179 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
32180 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
32181 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
32182 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
32183 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
32184 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
32185 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32186 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
32187 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32188 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32189 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32190 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32191 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32192 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32193 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32194 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32195 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32196 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32197 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32198 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
32199 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32200 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
32201 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32202 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32203 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32204 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
32205 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32206 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
32207 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32208 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32209 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32210 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
32211 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32212 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
32213 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32214 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32215 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32216 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32217 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32218 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
32219 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32220 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
32221 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32222 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32223 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32224 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32225 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32226 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32227 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32228 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32229 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32230 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
32231 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
32232 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32233 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32234 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
32235 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
32236 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
32237 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
32238 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
32239 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
32240 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
32241 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
32242 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
32243 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
32244 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32245 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32246 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32247 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32248 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32249 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32250 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32251 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32252 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32253 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32254 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32255 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32256 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32257 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32258 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32259 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
32260 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32261 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32262 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32263 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32264 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
32265 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
32266 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
32267 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
32268 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32269 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32270 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32271 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32272 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32273 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32274 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
32275 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
32276 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
32277 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
32279 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
32280 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
32281 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
32282 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32283 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32284 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
32285 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32286 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32288 /* Mask arithmetic operations */
32289 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32290 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32291 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
32292 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32293 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32294 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32295 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
32296 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32297 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32298 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
32300 /* SHA */
32301 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32302 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32303 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32304 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
32305 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32306 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32307 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
32309 /* AVX512VL. */
32310 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT },
32311 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT },
32312 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64_256_mask", IX86_BUILTIN_MOVDQA64_256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32313 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64_128_mask", IX86_BUILTIN_MOVDQA64_128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32314 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32_256_mask", IX86_BUILTIN_MOVDQA32_256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32315 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32_128_mask", IX86_BUILTIN_MOVDQA32_128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32316 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_movapd256_mask", IX86_BUILTIN_MOVAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32317 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_movapd128_mask", IX86_BUILTIN_MOVAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32318 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_movaps256_mask", IX86_BUILTIN_MOVAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32319 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_movaps128_mask", IX86_BUILTIN_MOVAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32320 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_movdquhi256_mask", IX86_BUILTIN_MOVDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32321 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_movdquhi128_mask", IX86_BUILTIN_MOVDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32322 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_movdquqi256_mask", IX86_BUILTIN_MOVDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32323 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_movdquqi128_mask", IX86_BUILTIN_MOVDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32324 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4sf3_mask, "__builtin_ia32_minps_mask", IX86_BUILTIN_MINPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32325 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4sf3_mask, "__builtin_ia32_maxps_mask", IX86_BUILTIN_MAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32326 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2df3_mask, "__builtin_ia32_minpd_mask", IX86_BUILTIN_MINPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32327 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2df3_mask, "__builtin_ia32_maxpd_mask", IX86_BUILTIN_MAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32328 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4df3_mask, "__builtin_ia32_maxpd256_mask", IX86_BUILTIN_MAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32329 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8sf3_mask, "__builtin_ia32_maxps256_mask", IX86_BUILTIN_MAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32330 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4df3_mask, "__builtin_ia32_minpd256_mask", IX86_BUILTIN_MINPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32331 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8sf3_mask, "__builtin_ia32_minps256_mask", IX86_BUILTIN_MINPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32332 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4sf3_mask, "__builtin_ia32_mulps_mask", IX86_BUILTIN_MULPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32333 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_divv4sf3_mask, "__builtin_ia32_divps_mask", IX86_BUILTIN_DIVPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32334 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv2df3_mask, "__builtin_ia32_mulpd_mask", IX86_BUILTIN_MULPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32335 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_divv2df3_mask, "__builtin_ia32_divpd_mask", IX86_BUILTIN_DIVPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32336 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv4df3_mask, "__builtin_ia32_divpd256_mask", IX86_BUILTIN_DIVPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32337 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv8sf3_mask, "__builtin_ia32_divps256_mask", IX86_BUILTIN_DIVPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32338 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4df3_mask, "__builtin_ia32_mulpd256_mask", IX86_BUILTIN_MULPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32339 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8sf3_mask, "__builtin_ia32_mulps256_mask", IX86_BUILTIN_MULPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32340 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2df3_mask, "__builtin_ia32_addpd128_mask", IX86_BUILTIN_ADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32341 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4df3_mask, "__builtin_ia32_addpd256_mask", IX86_BUILTIN_ADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32342 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4sf3_mask, "__builtin_ia32_addps128_mask", IX86_BUILTIN_ADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32343 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8sf3_mask, "__builtin_ia32_addps256_mask", IX86_BUILTIN_ADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32344 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2df3_mask, "__builtin_ia32_subpd128_mask", IX86_BUILTIN_SUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32345 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4df3_mask, "__builtin_ia32_subpd256_mask", IX86_BUILTIN_SUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32346 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4sf3_mask, "__builtin_ia32_subps128_mask", IX86_BUILTIN_SUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32347 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8sf3_mask, "__builtin_ia32_subps256_mask", IX86_BUILTIN_SUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32348 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4df3_mask, "__builtin_ia32_xorpd256_mask", IX86_BUILTIN_XORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32349 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2df3_mask, "__builtin_ia32_xorpd128_mask", IX86_BUILTIN_XORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32350 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8sf3_mask, "__builtin_ia32_xorps256_mask", IX86_BUILTIN_XORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32351 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4sf3_mask, "__builtin_ia32_xorps128_mask", IX86_BUILTIN_XORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32352 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4df3_mask, "__builtin_ia32_orpd256_mask", IX86_BUILTIN_ORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32353 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2df3_mask, "__builtin_ia32_orpd128_mask", IX86_BUILTIN_ORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32354 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8sf3_mask, "__builtin_ia32_orps256_mask", IX86_BUILTIN_ORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32355 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4sf3_mask, "__builtin_ia32_orps128_mask", IX86_BUILTIN_ORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32356 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8sf_mask, "__builtin_ia32_broadcastf32x2_256_mask", IX86_BUILTIN_BROADCASTF32x2_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32357 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8si_mask, "__builtin_ia32_broadcasti32x2_256_mask", IX86_BUILTIN_BROADCASTI32x2_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32358 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4si_mask, "__builtin_ia32_broadcasti32x2_128_mask", IX86_BUILTIN_BROADCASTI32x2_128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32359 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4df_mask_1, "__builtin_ia32_broadcastf64x2_256_mask", IX86_BUILTIN_BROADCASTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32360 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4di_mask_1, "__builtin_ia32_broadcasti64x2_256_mask", IX86_BUILTIN_BROADCASTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32361 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8sf_mask_1, "__builtin_ia32_broadcastf32x4_256_mask", IX86_BUILTIN_BROADCASTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32362 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8si_mask_1, "__builtin_ia32_broadcasti32x4_256_mask", IX86_BUILTIN_BROADCASTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32363 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_QI },
32364 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_QI },
32365 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv16hi_mask, "__builtin_ia32_dbpsadbw256_mask", IX86_BUILTIN_DBPSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI },
32366 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI },
32367 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32368 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32369 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32370 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32371 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32372 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32373 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32374 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2uqq128_mask", IX86_BUILTIN_CVTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32375 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin_ia32_cvtpd2udq256_mask", IX86_BUILTIN_CVTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32376 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32377 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32378 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32379 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32380 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32381 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32382 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32383 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32384 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2udq128_mask", IX86_BUILTIN_CVTTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32385 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2dq256_mask", IX86_BUILTIN_CVTTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32386 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvttpd2dq_mask, "__builtin_ia32_cvttpd2dq128_mask", IX86_BUILTIN_CVTTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32387 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2udq256_mask", IX86_BUILTIN_CVTTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32388 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2si2_mask, "__builtin_ia32_cvttpd2udq128_mask", IX86_BUILTIN_CVTTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32389 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2dq256_mask, "__builtin_ia32_cvtpd2dq256_mask", IX86_BUILTIN_CVTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32390 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2dq_mask, "__builtin_ia32_cvtpd2dq128_mask", IX86_BUILTIN_CVTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32391 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4df2_mask, "__builtin_ia32_cvtdq2pd256_mask", IX86_BUILTIN_CVTDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32392 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtdq2pd_mask, "__builtin_ia32_cvtdq2pd128_mask", IX86_BUILTIN_CVTDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32393 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4df2_mask, "__builtin_ia32_cvtudq2pd256_mask", IX86_BUILTIN_CVTUDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32394 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2siv2df2_mask, "__builtin_ia32_cvtudq2pd128_mask", IX86_BUILTIN_CVTUDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32395 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv8siv8sf2_mask, "__builtin_ia32_cvtdq2ps256_mask", IX86_BUILTIN_CVTDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32396 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4sf2_mask, "__builtin_ia32_cvtdq2ps128_mask", IX86_BUILTIN_CVTDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32397 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv8siv8sf2_mask, "__builtin_ia32_cvtudq2ps256_mask", IX86_BUILTIN_CVTUDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32398 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4sf2_mask, "__builtin_ia32_cvtudq2ps128_mask", IX86_BUILTIN_CVTUDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32399 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtps2pd256_mask, "__builtin_ia32_cvtps2pd256_mask", IX86_BUILTIN_CVTPS2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_QI },
32400 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtps2pd_mask, "__builtin_ia32_cvtps2pd128_mask", IX86_BUILTIN_CVTPS2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SF_V2DF_QI },
32401 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv32qi_mask, "__builtin_ia32_pbroadcastb256_mask", IX86_BUILTIN_PBROADCASTB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_SI },
32402 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv32qi_mask, "__builtin_ia32_pbroadcastb256_gpr_mask", IX86_BUILTIN_PBROADCASTB256_GPR_MASK, UNKNOWN, (int) V32QI_FTYPE_QI_V32QI_SI },
32403 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16qi_mask, "__builtin_ia32_pbroadcastb128_mask", IX86_BUILTIN_PBROADCASTB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32404 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16qi_mask, "__builtin_ia32_pbroadcastb128_gpr_mask", IX86_BUILTIN_PBROADCASTB128_GPR_MASK, UNKNOWN, (int) V16QI_FTYPE_QI_V16QI_HI },
32405 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16hi_mask, "__builtin_ia32_pbroadcastw256_mask", IX86_BUILTIN_PBROADCASTW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8HI_V16HI_HI },
32406 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16hi_mask, "__builtin_ia32_pbroadcastw256_gpr_mask", IX86_BUILTIN_PBROADCASTW256_GPR_MASK, UNKNOWN, (int) V16HI_FTYPE_HI_V16HI_HI },
32407 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8hi_mask, "__builtin_ia32_pbroadcastw128_mask", IX86_BUILTIN_PBROADCASTW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32408 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8hi_mask, "__builtin_ia32_pbroadcastw128_gpr_mask", IX86_BUILTIN_PBROADCASTW128_GPR_MASK, UNKNOWN, (int) V8HI_FTYPE_HI_V8HI_QI },
32409 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8si_mask, "__builtin_ia32_pbroadcastd256_mask", IX86_BUILTIN_PBROADCASTD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32410 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8si_mask, "__builtin_ia32_pbroadcastd256_gpr_mask", IX86_BUILTIN_PBROADCASTD256_GPR_MASK, UNKNOWN, (int) V8SI_FTYPE_SI_V8SI_QI },
32411 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4si_mask, "__builtin_ia32_pbroadcastd128_mask", IX86_BUILTIN_PBROADCASTD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32412 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4si_mask, "__builtin_ia32_pbroadcastd128_gpr_mask", IX86_BUILTIN_PBROADCASTD128_GPR_MASK, UNKNOWN, (int) V4SI_FTYPE_SI_V4SI_QI },
32413 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4di_mask, "__builtin_ia32_pbroadcastq256_mask", IX86_BUILTIN_PBROADCASTQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32414 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4di_mask, "__builtin_ia32_pbroadcastq256_gpr_mask", IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
32415 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv2di_mask, "__builtin_ia32_pbroadcastq128_mask", IX86_BUILTIN_PBROADCASTQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32416 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv2di_mask, "__builtin_ia32_pbroadcastq128_gpr_mask", IX86_BUILTIN_PBROADCASTQ128_GPR_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
32417 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8sf_mask, "__builtin_ia32_broadcastss256_mask", IX86_BUILTIN_BROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32418 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4sf_mask, "__builtin_ia32_broadcastss128_mask", IX86_BUILTIN_BROADCASTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32419 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4df_mask, "__builtin_ia32_broadcastsd256_mask", IX86_BUILTIN_BROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32420 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4df, "__builtin_ia32_extractf64x2_256_mask", IX86_BUILTIN_EXTRACTF64X2_256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT_V2DF_QI },
32421 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4di, "__builtin_ia32_extracti64x2_256_mask", IX86_BUILTIN_EXTRACTI64X2_256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT_V2DI_QI },
32422 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8sf, "__builtin_ia32_insertf32x4_256_mask", IX86_BUILTIN_INSERTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI },
32423 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8si, "__builtin_ia32_inserti32x4_256_mask", IX86_BUILTIN_INSERTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI },
32424 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv16qiv16hi2_mask, "__builtin_ia32_pmovsxbw256_mask", IX86_BUILTIN_PMOVSXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32425 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv8qiv8hi2_mask, "__builtin_ia32_pmovsxbw128_mask", IX86_BUILTIN_PMOVSXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32426 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8qiv8si2_mask, "__builtin_ia32_pmovsxbd256_mask", IX86_BUILTIN_PMOVSXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32427 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4qiv4si2_mask, "__builtin_ia32_pmovsxbd128_mask", IX86_BUILTIN_PMOVSXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32428 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4qiv4di2_mask, "__builtin_ia32_pmovsxbq256_mask", IX86_BUILTIN_PMOVSXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32429 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2qiv2di2_mask, "__builtin_ia32_pmovsxbq128_mask", IX86_BUILTIN_PMOVSXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32430 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8hiv8si2_mask, "__builtin_ia32_pmovsxwd256_mask", IX86_BUILTIN_PMOVSXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32431 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4hiv4si2_mask, "__builtin_ia32_pmovsxwd128_mask", IX86_BUILTIN_PMOVSXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32432 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4hiv4di2_mask, "__builtin_ia32_pmovsxwq256_mask", IX86_BUILTIN_PMOVSXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32433 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2hiv2di2_mask, "__builtin_ia32_pmovsxwq128_mask", IX86_BUILTIN_PMOVSXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32434 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4siv4di2_mask, "__builtin_ia32_pmovsxdq256_mask", IX86_BUILTIN_PMOVSXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32435 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2siv2di2_mask, "__builtin_ia32_pmovsxdq128_mask", IX86_BUILTIN_PMOVSXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32436 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv16qiv16hi2_mask, "__builtin_ia32_pmovzxbw256_mask", IX86_BUILTIN_PMOVZXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32437 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv8qiv8hi2_mask, "__builtin_ia32_pmovzxbw128_mask", IX86_BUILTIN_PMOVZXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32438 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8qiv8si2_mask, "__builtin_ia32_pmovzxbd256_mask", IX86_BUILTIN_PMOVZXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32439 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4qiv4si2_mask, "__builtin_ia32_pmovzxbd128_mask", IX86_BUILTIN_PMOVZXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32440 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4qiv4di2_mask, "__builtin_ia32_pmovzxbq256_mask", IX86_BUILTIN_PMOVZXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32441 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2qiv2di2_mask, "__builtin_ia32_pmovzxbq128_mask", IX86_BUILTIN_PMOVZXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32442 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8hiv8si2_mask, "__builtin_ia32_pmovzxwd256_mask", IX86_BUILTIN_PMOVZXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32443 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4hiv4si2_mask, "__builtin_ia32_pmovzxwd128_mask", IX86_BUILTIN_PMOVZXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32444 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4hiv4di2_mask, "__builtin_ia32_pmovzxwq256_mask", IX86_BUILTIN_PMOVZXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32445 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2hiv2di2_mask, "__builtin_ia32_pmovzxwq128_mask", IX86_BUILTIN_PMOVZXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32446 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4siv4di2_mask, "__builtin_ia32_pmovzxdq256_mask", IX86_BUILTIN_PMOVZXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32447 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2siv2di2_mask, "__builtin_ia32_pmovzxdq128_mask", IX86_BUILTIN_PMOVZXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32448 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4df_mask, "__builtin_ia32_reducepd256_mask", IX86_BUILTIN_REDUCEPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32449 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv2df_mask, "__builtin_ia32_reducepd128_mask", IX86_BUILTIN_REDUCEPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32450 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv8sf_mask, "__builtin_ia32_reduceps256_mask", IX86_BUILTIN_REDUCEPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32451 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4sf_mask, "__builtin_ia32_reduceps128_mask", IX86_BUILTIN_REDUCEPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32452 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv2df, "__builtin_ia32_reducesd", IX86_BUILTIN_REDUCESD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32453 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv4sf, "__builtin_ia32_reducess", IX86_BUILTIN_REDUCESS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32454 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32455 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32456 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32457 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32458 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32459 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32460 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32461 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32462 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32463 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v2df_mask, "__builtin_ia32_rcp14pd128_mask", IX86_BUILTIN_RCP14PD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32464 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v8sf_mask, "__builtin_ia32_rcp14ps256_mask", IX86_BUILTIN_RCP14PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32465 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4sf_mask, "__builtin_ia32_rcp14ps128_mask", IX86_BUILTIN_RCP14PS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32466 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4df_mask, "__builtin_ia32_rsqrt14pd256_mask", IX86_BUILTIN_RSQRT14PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32467 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v2df_mask, "__builtin_ia32_rsqrt14pd128_mask", IX86_BUILTIN_RSQRT14PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32468 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v8sf_mask, "__builtin_ia32_rsqrt14ps256_mask", IX86_BUILTIN_RSQRT14PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32469 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4sf_mask, "__builtin_ia32_rsqrt14ps128_mask", IX86_BUILTIN_RSQRT14PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32470 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv4df2_mask, "__builtin_ia32_sqrtpd256_mask", IX86_BUILTIN_SQRTPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32471 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sqrtv2df2_mask, "__builtin_ia32_sqrtpd128_mask", IX86_BUILTIN_SQRTPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32472 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv8sf2_mask, "__builtin_ia32_sqrtps256_mask", IX86_BUILTIN_SQRTPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32473 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_sqrtv4sf2_mask, "__builtin_ia32_sqrtps128_mask", IX86_BUILTIN_SQRTPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32474 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16qi3_mask, "__builtin_ia32_paddb128_mask", IX86_BUILTIN_PADDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32475 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8hi3_mask, "__builtin_ia32_paddw128_mask", IX86_BUILTIN_PADDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32476 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4si3_mask, "__builtin_ia32_paddd128_mask", IX86_BUILTIN_PADDD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32477 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2di3_mask, "__builtin_ia32_paddq128_mask", IX86_BUILTIN_PADDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32478 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16qi3_mask, "__builtin_ia32_psubb128_mask", IX86_BUILTIN_PSUBB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32479 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8hi3_mask, "__builtin_ia32_psubw128_mask", IX86_BUILTIN_PSUBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32480 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4si3_mask, "__builtin_ia32_psubd128_mask", IX86_BUILTIN_PSUBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32481 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2di3_mask, "__builtin_ia32_psubq128_mask", IX86_BUILTIN_PSUBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32482 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv16qi3_mask, "__builtin_ia32_paddsb128_mask", IX86_BUILTIN_PADDSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32483 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv8hi3_mask, "__builtin_ia32_paddsw128_mask", IX86_BUILTIN_PADDSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32484 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv16qi3_mask, "__builtin_ia32_psubsb128_mask", IX86_BUILTIN_PSUBSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32485 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv8hi3_mask, "__builtin_ia32_psubsw128_mask", IX86_BUILTIN_PSUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32486 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv16qi3_mask, "__builtin_ia32_paddusb128_mask", IX86_BUILTIN_PADDUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32487 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv8hi3_mask, "__builtin_ia32_paddusw128_mask", IX86_BUILTIN_PADDUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32488 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv16qi3_mask, "__builtin_ia32_psubusb128_mask", IX86_BUILTIN_PSUBUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32489 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv8hi3_mask, "__builtin_ia32_psubusw128_mask", IX86_BUILTIN_PSUBUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32490 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv32qi3_mask, "__builtin_ia32_paddb256_mask", IX86_BUILTIN_PADDB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32491 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16hi3_mask, "__builtin_ia32_paddw256_mask", IX86_BUILTIN_PADDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32492 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8si3_mask, "__builtin_ia32_paddd256_mask", IX86_BUILTIN_PADDD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32493 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4di3_mask, "__builtin_ia32_paddq256_mask", IX86_BUILTIN_PADDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32494 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv32qi3_mask, "__builtin_ia32_paddsb256_mask", IX86_BUILTIN_PADDSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32495 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv16hi3_mask, "__builtin_ia32_paddsw256_mask", IX86_BUILTIN_PADDSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32496 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv32qi3_mask, "__builtin_ia32_paddusb256_mask", IX86_BUILTIN_PADDUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32497 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv16hi3_mask, "__builtin_ia32_paddusw256_mask", IX86_BUILTIN_PADDUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32498 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv32qi3_mask, "__builtin_ia32_psubb256_mask", IX86_BUILTIN_PSUBB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32499 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16hi3_mask, "__builtin_ia32_psubw256_mask", IX86_BUILTIN_PSUBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32500 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8si3_mask, "__builtin_ia32_psubd256_mask", IX86_BUILTIN_PSUBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32501 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4di3_mask, "__builtin_ia32_psubq256_mask", IX86_BUILTIN_PSUBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32502 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv32qi3_mask, "__builtin_ia32_psubsb256_mask", IX86_BUILTIN_PSUBSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32503 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv16hi3_mask, "__builtin_ia32_psubsw256_mask", IX86_BUILTIN_PSUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32504 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv32qi3_mask, "__builtin_ia32_psubusb256_mask", IX86_BUILTIN_PSUBUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32505 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv16hi3_mask, "__builtin_ia32_psubusw256_mask", IX86_BUILTIN_PSUBUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32506 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_256_mask", IX86_BUILTIN_SHUF_F64x2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32507 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_256_mask", IX86_BUILTIN_SHUF_I64x2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32508 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_256_mask", IX86_BUILTIN_SHUF_I32x4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32509 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_256_mask", IX86_BUILTIN_SHUF_F32x4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32510 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovwb128_mask", IX86_BUILTIN_PMOVWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32511 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovwb256_mask", IX86_BUILTIN_PMOVWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32512 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovswb128_mask", IX86_BUILTIN_PMOVSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32513 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovswb256_mask", IX86_BUILTIN_PMOVSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32514 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovuswb128_mask", IX86_BUILTIN_PMOVUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32515 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovuswb256_mask", IX86_BUILTIN_PMOVUSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32516 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask, "__builtin_ia32_pmovdb128_mask", IX86_BUILTIN_PMOVDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32517 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask, "__builtin_ia32_pmovdb256_mask", IX86_BUILTIN_PMOVDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32518 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask, "__builtin_ia32_pmovsdb128_mask", IX86_BUILTIN_PMOVSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32519 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask, "__builtin_ia32_pmovsdb256_mask", IX86_BUILTIN_PMOVSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32520 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask, "__builtin_ia32_pmovusdb128_mask", IX86_BUILTIN_PMOVUSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32521 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask, "__builtin_ia32_pmovusdb256_mask", IX86_BUILTIN_PMOVUSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32522 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask, "__builtin_ia32_pmovdw128_mask", IX86_BUILTIN_PMOVDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32523 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask, "__builtin_ia32_pmovdw256_mask", IX86_BUILTIN_PMOVDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32524 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask, "__builtin_ia32_pmovsdw128_mask", IX86_BUILTIN_PMOVSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32525 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask, "__builtin_ia32_pmovsdw256_mask", IX86_BUILTIN_PMOVSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32526 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask, "__builtin_ia32_pmovusdw128_mask", IX86_BUILTIN_PMOVUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32527 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask, "__builtin_ia32_pmovusdw256_mask", IX86_BUILTIN_PMOVUSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32528 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask, "__builtin_ia32_pmovqb128_mask", IX86_BUILTIN_PMOVQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32529 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask, "__builtin_ia32_pmovqb256_mask", IX86_BUILTIN_PMOVQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32530 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask, "__builtin_ia32_pmovsqb128_mask", IX86_BUILTIN_PMOVSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32531 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask, "__builtin_ia32_pmovsqb256_mask", IX86_BUILTIN_PMOVSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32532 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask, "__builtin_ia32_pmovusqb128_mask", IX86_BUILTIN_PMOVUSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32533 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask, "__builtin_ia32_pmovusqb256_mask", IX86_BUILTIN_PMOVUSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32534 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask, "__builtin_ia32_pmovqw128_mask", IX86_BUILTIN_PMOVQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32535 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask, "__builtin_ia32_pmovqw256_mask", IX86_BUILTIN_PMOVQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32536 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask, "__builtin_ia32_pmovsqw128_mask", IX86_BUILTIN_PMOVSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32537 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask, "__builtin_ia32_pmovsqw256_mask", IX86_BUILTIN_PMOVSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32538 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask, "__builtin_ia32_pmovusqw128_mask", IX86_BUILTIN_PMOVUSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32539 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask, "__builtin_ia32_pmovusqw256_mask", IX86_BUILTIN_PMOVUSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32540 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask, "__builtin_ia32_pmovqd128_mask", IX86_BUILTIN_PMOVQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32541 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask, "__builtin_ia32_pmovqd256_mask", IX86_BUILTIN_PMOVQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32542 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask, "__builtin_ia32_pmovsqd128_mask", IX86_BUILTIN_PMOVSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32543 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask, "__builtin_ia32_pmovsqd256_mask", IX86_BUILTIN_PMOVSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32544 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask, "__builtin_ia32_pmovusqd128_mask", IX86_BUILTIN_PMOVUSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32545 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask, "__builtin_ia32_pmovusqd256_mask", IX86_BUILTIN_PMOVUSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32546 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4df_mask, "__builtin_ia32_rangepd256_mask", IX86_BUILTIN_RANGEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32547 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv2df_mask, "__builtin_ia32_rangepd128_mask", IX86_BUILTIN_RANGEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32548 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv8sf_mask, "__builtin_ia32_rangeps256_mask", IX86_BUILTIN_RANGEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32549 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4sf_mask, "__builtin_ia32_rangeps128_mask", IX86_BUILTIN_RANGEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32550 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv8sf_mask, "__builtin_ia32_getexpps256_mask", IX86_BUILTIN_GETEXPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32551 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4df_mask, "__builtin_ia32_getexppd256_mask", IX86_BUILTIN_GETEXPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32552 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4sf_mask, "__builtin_ia32_getexpps128_mask", IX86_BUILTIN_GETEXPPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32553 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv2df_mask, "__builtin_ia32_getexppd128_mask", IX86_BUILTIN_GETEXPPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32554 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_mask, "__builtin_ia32_fixupimmpd256_mask", IX86_BUILTIN_FIXUPIMMPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32555 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_maskz, "__builtin_ia32_fixupimmpd256_maskz", IX86_BUILTIN_FIXUPIMMPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32556 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_mask, "__builtin_ia32_fixupimmps256_mask", IX86_BUILTIN_FIXUPIMMPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32557 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_maskz, "__builtin_ia32_fixupimmps256_maskz", IX86_BUILTIN_FIXUPIMMPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32558 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_mask, "__builtin_ia32_fixupimmpd128_mask", IX86_BUILTIN_FIXUPIMMPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32559 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_maskz, "__builtin_ia32_fixupimmpd128_maskz", IX86_BUILTIN_FIXUPIMMPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32560 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_mask, "__builtin_ia32_fixupimmps128_mask", IX86_BUILTIN_FIXUPIMMPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32561 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_maskz, "__builtin_ia32_fixupimmps128_maskz", IX86_BUILTIN_FIXUPIMMPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32562 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4di2_mask, "__builtin_ia32_pabsq256_mask", IX86_BUILTIN_PABSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32563 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv2di2_mask, "__builtin_ia32_pabsq128_mask", IX86_BUILTIN_PABSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32564 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8si2_mask, "__builtin_ia32_pabsd256_mask", IX86_BUILTIN_PABSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32565 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4si2_mask, "__builtin_ia32_pabsd128_mask", IX86_BUILTIN_PABSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32566 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pmulhrswv16hi3_mask , "__builtin_ia32_pmulhrsw256_mask", IX86_BUILTIN_PMULHRSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32567 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pmulhrswv8hi3_mask, "__builtin_ia32_pmulhrsw128_mask", IX86_BUILTIN_PMULHRSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32568 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv8hi3_highpart_mask, "__builtin_ia32_pmulhuw128_mask", IX86_BUILTIN_PMULHUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32569 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv16hi3_highpart_mask, "__builtin_ia32_pmulhuw256_mask" , IX86_BUILTIN_PMULHUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32570 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv16hi3_highpart_mask, "__builtin_ia32_pmulhw256_mask" , IX86_BUILTIN_PMULHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32571 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv8hi3_highpart_mask, "__builtin_ia32_pmulhw128_mask", IX86_BUILTIN_PMULHW128_MASK, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32572 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv16hi3_mask, "__builtin_ia32_pmullw256_mask" , IX86_BUILTIN_PMULLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32573 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8hi3_mask, "__builtin_ia32_pmullw128_mask", IX86_BUILTIN_PMULLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32574 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv4di3_mask, "__builtin_ia32_pmullq256_mask", IX86_BUILTIN_PMULLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32575 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv2di3_mask, "__builtin_ia32_pmullq128_mask", IX86_BUILTIN_PMULLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32576 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4df3_mask, "__builtin_ia32_andpd256_mask", IX86_BUILTIN_ANDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32577 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2df3_mask, "__builtin_ia32_andpd128_mask", IX86_BUILTIN_ANDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32578 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8sf3_mask, "__builtin_ia32_andps256_mask", IX86_BUILTIN_ANDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32579 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4sf3_mask, "__builtin_ia32_andps128_mask", IX86_BUILTIN_ANDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32580 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv4df3_mask, "__builtin_ia32_andnpd256_mask", IX86_BUILTIN_ANDNPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32581 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2df3_mask, "__builtin_ia32_andnpd128_mask", IX86_BUILTIN_ANDNPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32582 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv8sf3_mask, "__builtin_ia32_andnps256_mask", IX86_BUILTIN_ANDNPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32583 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_andnotv4sf3_mask, "__builtin_ia32_andnps128_mask", IX86_BUILTIN_ANDNPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32584 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllwi128_mask", IX86_BUILTIN_PSLLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32585 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslldi128_mask", IX86_BUILTIN_PSLLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32586 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllqi128_mask", IX86_BUILTIN_PSLLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32587 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllw128_mask", IX86_BUILTIN_PSLLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32588 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslld128_mask", IX86_BUILTIN_PSLLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32589 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllq128_mask", IX86_BUILTIN_PSLLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32590 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllwi256_mask", IX86_BUILTIN_PSLLWI256_MASK , UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32591 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllw256_mask", IX86_BUILTIN_PSLLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32592 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslldi256_mask", IX86_BUILTIN_PSLLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32593 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslld256_mask", IX86_BUILTIN_PSLLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32594 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllqi256_mask", IX86_BUILTIN_PSLLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32595 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllq256_mask", IX86_BUILTIN_PSLLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32596 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psradi128_mask", IX86_BUILTIN_PSRADI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32597 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psrad128_mask", IX86_BUILTIN_PSRAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32598 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psradi256_mask", IX86_BUILTIN_PSRADI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32599 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psrad256_mask", IX86_BUILTIN_PSRAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32600 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraqi128_mask", IX86_BUILTIN_PSRAQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32601 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraq128_mask", IX86_BUILTIN_PSRAQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32602 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraqi256_mask", IX86_BUILTIN_PSRAQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32603 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraq256_mask", IX86_BUILTIN_PSRAQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32604 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8si3_mask, "__builtin_ia32_pandd256_mask", IX86_BUILTIN_PANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32605 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4si3_mask, "__builtin_ia32_pandd128_mask", IX86_BUILTIN_PANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32606 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrldi128_mask", IX86_BUILTIN_PSRLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32607 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrld128_mask", IX86_BUILTIN_PSRLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32608 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrldi256_mask", IX86_BUILTIN_PSRLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32609 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrld256_mask", IX86_BUILTIN_PSRLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32610 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlqi128_mask", IX86_BUILTIN_PSRLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32611 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlq128_mask", IX86_BUILTIN_PSRLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32612 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlqi256_mask", IX86_BUILTIN_PSRLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32613 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlq256_mask", IX86_BUILTIN_PSRLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32614 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4di3_mask, "__builtin_ia32_pandq256_mask", IX86_BUILTIN_PANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32615 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2di3_mask, "__builtin_ia32_pandq128_mask", IX86_BUILTIN_PANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32616 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv8si3_mask, "__builtin_ia32_pandnd256_mask", IX86_BUILTIN_PANDND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32617 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv4si3_mask, "__builtin_ia32_pandnd128_mask", IX86_BUILTIN_PANDND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32618 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv4di3_mask, "__builtin_ia32_pandnq256_mask", IX86_BUILTIN_PANDNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32619 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2di3_mask, "__builtin_ia32_pandnq128_mask", IX86_BUILTIN_PANDNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32620 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8si3_mask, "__builtin_ia32_pord256_mask", IX86_BUILTIN_PORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32621 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4si3_mask, "__builtin_ia32_pord128_mask", IX86_BUILTIN_PORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32622 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4di3_mask, "__builtin_ia32_porq256_mask", IX86_BUILTIN_PORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32623 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2di3_mask, "__builtin_ia32_porq128_mask", IX86_BUILTIN_PORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32624 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8si3_mask, "__builtin_ia32_pxord256_mask", IX86_BUILTIN_PXORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32625 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4si3_mask, "__builtin_ia32_pxord128_mask", IX86_BUILTIN_PXORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32626 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4di3_mask, "__builtin_ia32_pxorq256_mask", IX86_BUILTIN_PXORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32627 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2di3_mask, "__builtin_ia32_pxorq128_mask", IX86_BUILTIN_PXORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32628 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packsswb_mask, "__builtin_ia32_packsswb256_mask", IX86_BUILTIN_PACKSSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32629 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packsswb_mask, "__builtin_ia32_packsswb128_mask", IX86_BUILTIN_PACKSSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32630 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packuswb_mask, "__builtin_ia32_packuswb256_mask", IX86_BUILTIN_PACKUSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32631 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packuswb_mask, "__builtin_ia32_packuswb128_mask", IX86_BUILTIN_PACKUSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32632 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev8sf_mask, "__builtin_ia32_rndscaleps_256_mask", IX86_BUILTIN_RNDSCALEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32633 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4df_mask, "__builtin_ia32_rndscalepd_256_mask", IX86_BUILTIN_RNDSCALEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32634 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4sf_mask, "__builtin_ia32_rndscaleps_128_mask", IX86_BUILTIN_RNDSCALEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32635 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev2df_mask, "__builtin_ia32_rndscalepd_128_mask", IX86_BUILTIN_RNDSCALEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32636 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_mask, "__builtin_ia32_pternlogq256_mask", IX86_BUILTIN_VTERNLOGQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32637 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_maskz, "__builtin_ia32_pternlogq256_maskz", IX86_BUILTIN_VTERNLOGQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32638 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_mask, "__builtin_ia32_pternlogd256_mask", IX86_BUILTIN_VTERNLOGD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32639 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_maskz, "__builtin_ia32_pternlogd256_maskz", IX86_BUILTIN_VTERNLOGD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32640 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_mask, "__builtin_ia32_pternlogq128_mask", IX86_BUILTIN_VTERNLOGQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32641 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_maskz, "__builtin_ia32_pternlogq128_maskz", IX86_BUILTIN_VTERNLOGQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32642 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_mask, "__builtin_ia32_pternlogd128_mask", IX86_BUILTIN_VTERNLOGD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32643 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_maskz, "__builtin_ia32_pternlogd128_maskz", IX86_BUILTIN_VTERNLOGD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32644 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4df_mask, "__builtin_ia32_scalefpd256_mask", IX86_BUILTIN_SCALEFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32645 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv8sf_mask, "__builtin_ia32_scalefps256_mask", IX86_BUILTIN_SCALEFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32646 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv2df_mask, "__builtin_ia32_scalefpd128_mask", IX86_BUILTIN_SCALEFPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32647 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4sf_mask, "__builtin_ia32_scalefps128_mask", IX86_BUILTIN_SCALEFPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32648 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask, "__builtin_ia32_vfmaddpd256_mask", IX86_BUILTIN_VFMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32649 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask3, "__builtin_ia32_vfmaddpd256_mask3", IX86_BUILTIN_VFMADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32650 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_maskz, "__builtin_ia32_vfmaddpd256_maskz", IX86_BUILTIN_VFMADDPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32651 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask, "__builtin_ia32_vfmaddpd128_mask", IX86_BUILTIN_VFMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32652 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask3, "__builtin_ia32_vfmaddpd128_mask3", IX86_BUILTIN_VFMADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32653 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_maskz, "__builtin_ia32_vfmaddpd128_maskz", IX86_BUILTIN_VFMADDPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32654 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask, "__builtin_ia32_vfmaddps256_mask", IX86_BUILTIN_VFMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32655 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask3, "__builtin_ia32_vfmaddps256_mask3", IX86_BUILTIN_VFMADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32656 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_maskz, "__builtin_ia32_vfmaddps256_maskz", IX86_BUILTIN_VFMADDPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32657 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask, "__builtin_ia32_vfmaddps128_mask", IX86_BUILTIN_VFMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32658 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask3, "__builtin_ia32_vfmaddps128_mask3", IX86_BUILTIN_VFMADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32659 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_maskz, "__builtin_ia32_vfmaddps128_maskz", IX86_BUILTIN_VFMADDPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32660 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4df_mask3, "__builtin_ia32_vfmsubpd256_mask3", IX86_BUILTIN_VFMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32661 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v2df_mask3, "__builtin_ia32_vfmsubpd128_mask3", IX86_BUILTIN_VFMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32662 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v8sf_mask3, "__builtin_ia32_vfmsubps256_mask3", IX86_BUILTIN_VFMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32663 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4sf_mask3, "__builtin_ia32_vfmsubps128_mask3", IX86_BUILTIN_VFMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32664 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4df_mask, "__builtin_ia32_vfnmaddpd256_mask", IX86_BUILTIN_VFNMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32665 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v2df_mask, "__builtin_ia32_vfnmaddpd128_mask", IX86_BUILTIN_VFNMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32666 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v8sf_mask, "__builtin_ia32_vfnmaddps256_mask", IX86_BUILTIN_VFNMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32667 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4sf_mask, "__builtin_ia32_vfnmaddps128_mask", IX86_BUILTIN_VFNMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32668 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask, "__builtin_ia32_vfnmsubpd256_mask", IX86_BUILTIN_VFNMSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32669 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask3, "__builtin_ia32_vfnmsubpd256_mask3", IX86_BUILTIN_VFNMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32670 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask, "__builtin_ia32_vfnmsubpd128_mask", IX86_BUILTIN_VFNMSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32671 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask3, "__builtin_ia32_vfnmsubpd128_mask3", IX86_BUILTIN_VFNMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32672 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask, "__builtin_ia32_vfnmsubps256_mask", IX86_BUILTIN_VFNMSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32673 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask3, "__builtin_ia32_vfnmsubps256_mask3", IX86_BUILTIN_VFNMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32674 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask, "__builtin_ia32_vfnmsubps128_mask", IX86_BUILTIN_VFNMSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32675 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask3, "__builtin_ia32_vfnmsubps128_mask3", IX86_BUILTIN_VFNMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32676 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask, "__builtin_ia32_vfmaddsubpd256_mask", IX86_BUILTIN_VFMADDSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32677 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask3, "__builtin_ia32_vfmaddsubpd256_mask3", IX86_BUILTIN_VFMADDSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32678 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_maskz, "__builtin_ia32_vfmaddsubpd256_maskz", IX86_BUILTIN_VFMADDSUBPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32679 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask, "__builtin_ia32_vfmaddsubpd128_mask", IX86_BUILTIN_VFMADDSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32680 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask3, "__builtin_ia32_vfmaddsubpd128_mask3", IX86_BUILTIN_VFMADDSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32681 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_maskz, "__builtin_ia32_vfmaddsubpd128_maskz", IX86_BUILTIN_VFMADDSUBPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32682 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask, "__builtin_ia32_vfmaddsubps256_mask", IX86_BUILTIN_VFMADDSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32683 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask3, "__builtin_ia32_vfmaddsubps256_mask3", IX86_BUILTIN_VFMADDSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32684 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_maskz, "__builtin_ia32_vfmaddsubps256_maskz", IX86_BUILTIN_VFMADDSUBPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32685 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask, "__builtin_ia32_vfmaddsubps128_mask", IX86_BUILTIN_VFMADDSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32686 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask3, "__builtin_ia32_vfmaddsubps128_mask3", IX86_BUILTIN_VFMADDSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32687 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_maskz, "__builtin_ia32_vfmaddsubps128_maskz", IX86_BUILTIN_VFMADDSUBPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32688 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4df_mask3, "__builtin_ia32_vfmsubaddpd256_mask3", IX86_BUILTIN_VFMSUBADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32689 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v2df_mask3, "__builtin_ia32_vfmsubaddpd128_mask3", IX86_BUILTIN_VFMSUBADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32690 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3, "__builtin_ia32_vfmsubaddps256_mask3", IX86_BUILTIN_VFMSUBADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32691 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4sf_mask3, "__builtin_ia32_vfmsubaddps128_mask3", IX86_BUILTIN_VFMSUBADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32692 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4df, "__builtin_ia32_insertf64x2_256_mask", IX86_BUILTIN_INSERTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI },
32693 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4di, "__builtin_ia32_inserti64x2_256_mask", IX86_BUILTIN_INSERTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI },
32694 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv16hi_mask, "__builtin_ia32_psrav16hi_mask", IX86_BUILTIN_PSRAVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32695 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv8hi_mask, "__builtin_ia32_psrav8hi_mask", IX86_BUILTIN_PSRAVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32696 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v16hi_mask, "__builtin_ia32_pmaddubsw256_mask", IX86_BUILTIN_PMADDUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_V16HI_HI },
32697 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v8hi_mask, "__builtin_ia32_pmaddubsw128_mask", IX86_BUILTIN_PMADDUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_V8HI_QI },
32698 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v16hi_mask, "__builtin_ia32_pmaddwd256_mask", IX86_BUILTIN_PMADDWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI_V8SI_QI },
32699 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v8hi_mask, "__builtin_ia32_pmaddwd128_mask", IX86_BUILTIN_PMADDWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI_V4SI_QI },
32700 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv16hi_mask, "__builtin_ia32_psrlv16hi_mask", IX86_BUILTIN_PSRLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32701 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv8hi_mask, "__builtin_ia32_psrlv8hi_mask", IX86_BUILTIN_PSRLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32702 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_fix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2dq256_mask", IX86_BUILTIN_CVTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32703 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_fix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2dq128_mask", IX86_BUILTIN_CVTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32704 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2udq256_mask", IX86_BUILTIN_CVTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32705 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2udq128_mask", IX86_BUILTIN_CVTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32706 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv4di_mask, "__builtin_ia32_cvtps2qq256_mask", IX86_BUILTIN_CVTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32707 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv2di_mask, "__builtin_ia32_cvtps2qq128_mask", IX86_BUILTIN_CVTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32708 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv4di_mask, "__builtin_ia32_cvtps2uqq256_mask", IX86_BUILTIN_CVTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32709 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv2di_mask, "__builtin_ia32_cvtps2uqq128_mask", IX86_BUILTIN_CVTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32710 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv8sf_mask, "__builtin_ia32_getmantps256_mask", IX86_BUILTIN_GETMANTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32711 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4sf_mask, "__builtin_ia32_getmantps128_mask", IX86_BUILTIN_GETMANTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32712 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4df_mask, "__builtin_ia32_getmantpd256_mask", IX86_BUILTIN_GETMANTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32713 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv2df_mask, "__builtin_ia32_getmantpd128_mask", IX86_BUILTIN_GETMANTPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32714 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movddup256_mask, "__builtin_ia32_movddup256_mask", IX86_BUILTIN_MOVDDUP256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32715 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_dupv2df_mask, "__builtin_ia32_movddup128_mask", IX86_BUILTIN_MOVDDUP128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32716 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movshdup256_mask, "__builtin_ia32_movshdup256_mask", IX86_BUILTIN_MOVSHDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32717 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movshdup_mask, "__builtin_ia32_movshdup128_mask", IX86_BUILTIN_MOVSHDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32718 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_movsldup256_mask", IX86_BUILTIN_MOVSLDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32719 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32720 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32721 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32722 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32723 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32724 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32725 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32726 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32727 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32728 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32729 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32730 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32731 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_maskz, "__builtin_ia32_vpermt2vard256_maskz", IX86_BUILTIN_VPERMT2VARD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32732 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4di3_mask, "__builtin_ia32_vpermi2varq256_mask", IX86_BUILTIN_VPERMI2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32733 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8si3_mask, "__builtin_ia32_vpermi2vard256_mask", IX86_BUILTIN_VPERMI2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32734 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_mask, "__builtin_ia32_vpermt2varpd256_mask", IX86_BUILTIN_VPERMT2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32735 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_maskz, "__builtin_ia32_vpermt2varpd256_maskz", IX86_BUILTIN_VPERMT2VARPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32736 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_mask, "__builtin_ia32_vpermt2varps256_mask", IX86_BUILTIN_VPERMT2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32737 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_maskz, "__builtin_ia32_vpermt2varps256_maskz", IX86_BUILTIN_VPERMT2VARPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32738 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4df3_mask, "__builtin_ia32_vpermi2varpd256_mask", IX86_BUILTIN_VPERMI2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32739 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8sf3_mask, "__builtin_ia32_vpermi2varps256_mask", IX86_BUILTIN_VPERMI2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32740 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_mask, "__builtin_ia32_vpermt2varq128_mask", IX86_BUILTIN_VPERMT2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32741 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_maskz, "__builtin_ia32_vpermt2varq128_maskz", IX86_BUILTIN_VPERMT2VARQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32742 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_mask, "__builtin_ia32_vpermt2vard128_mask", IX86_BUILTIN_VPERMT2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32743 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_maskz, "__builtin_ia32_vpermt2vard128_maskz", IX86_BUILTIN_VPERMT2VARD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32744 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2di3_mask, "__builtin_ia32_vpermi2varq128_mask", IX86_BUILTIN_VPERMI2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32745 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4si3_mask, "__builtin_ia32_vpermi2vard128_mask", IX86_BUILTIN_VPERMI2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32746 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_mask, "__builtin_ia32_vpermt2varpd128_mask", IX86_BUILTIN_VPERMT2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32747 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_maskz, "__builtin_ia32_vpermt2varpd128_maskz", IX86_BUILTIN_VPERMT2VARPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32748 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_mask, "__builtin_ia32_vpermt2varps128_mask", IX86_BUILTIN_VPERMT2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32749 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_maskz, "__builtin_ia32_vpermt2varps128_maskz", IX86_BUILTIN_VPERMT2VARPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32750 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2df3_mask, "__builtin_ia32_vpermi2varpd128_mask", IX86_BUILTIN_VPERMI2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32751 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4sf3_mask, "__builtin_ia32_vpermi2varps128_mask", IX86_BUILTIN_VPERMI2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32752 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pshufbv32qi3_mask, "__builtin_ia32_pshufb256_mask", IX86_BUILTIN_PSHUFB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32753 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pshufbv16qi3_mask, "__builtin_ia32_pshufb128_mask", IX86_BUILTIN_PSHUFB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32754 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhwv3_mask, "__builtin_ia32_pshufhw256_mask", IX86_BUILTIN_PSHUFHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32755 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhw_mask, "__builtin_ia32_pshufhw128_mask", IX86_BUILTIN_PSHUFHW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32756 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflwv3_mask, "__builtin_ia32_pshuflw256_mask", IX86_BUILTIN_PSHUFLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32757 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflw_mask, "__builtin_ia32_pshuflw128_mask", IX86_BUILTIN_PSHUFLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32758 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufdv3_mask, "__builtin_ia32_pshufd256_mask", IX86_BUILTIN_PSHUFD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32759 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufd_mask, "__builtin_ia32_pshufd128_mask", IX86_BUILTIN_PSHUFD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32760 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufpd256_mask, "__builtin_ia32_shufpd256_mask", IX86_BUILTIN_SHUFPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32761 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_shufpd_mask, "__builtin_ia32_shufpd128_mask", IX86_BUILTIN_SHUFPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32762 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufps256_mask, "__builtin_ia32_shufps256_mask", IX86_BUILTIN_SHUFPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32763 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_shufps_mask, "__builtin_ia32_shufps128_mask", IX86_BUILTIN_SHUFPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32764 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4di_mask, "__builtin_ia32_prolvq256_mask", IX86_BUILTIN_PROLVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32765 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv2di_mask, "__builtin_ia32_prolvq128_mask", IX86_BUILTIN_PROLVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32766 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4di_mask, "__builtin_ia32_prolq256_mask", IX86_BUILTIN_PROLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32767 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv2di_mask, "__builtin_ia32_prolq128_mask", IX86_BUILTIN_PROLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32768 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4di_mask, "__builtin_ia32_prorvq256_mask", IX86_BUILTIN_PRORVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32769 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv2di_mask, "__builtin_ia32_prorvq128_mask", IX86_BUILTIN_PRORVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32770 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4di_mask, "__builtin_ia32_prorq256_mask", IX86_BUILTIN_PRORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32771 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv2di_mask, "__builtin_ia32_prorq128_mask", IX86_BUILTIN_PRORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32772 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv2di_mask, "__builtin_ia32_psravq128_mask", IX86_BUILTIN_PSRAVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32773 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4di_mask, "__builtin_ia32_psravq256_mask", IX86_BUILTIN_PSRAVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32774 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4di_mask, "__builtin_ia32_psllv4di_mask", IX86_BUILTIN_PSLLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32775 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv2di_mask, "__builtin_ia32_psllv2di_mask", IX86_BUILTIN_PSLLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32776 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv8si_mask, "__builtin_ia32_psllv8si_mask", IX86_BUILTIN_PSLLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32777 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4si_mask, "__builtin_ia32_psllv4si_mask", IX86_BUILTIN_PSLLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32778 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv8si_mask, "__builtin_ia32_psrav8si_mask", IX86_BUILTIN_PSRAVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32779 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4si_mask, "__builtin_ia32_psrav4si_mask", IX86_BUILTIN_PSRAVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32780 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4di_mask, "__builtin_ia32_psrlv4di_mask", IX86_BUILTIN_PSRLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32781 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv2di_mask, "__builtin_ia32_psrlv2di_mask", IX86_BUILTIN_PSRLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32782 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv8si_mask, "__builtin_ia32_psrlv8si_mask", IX86_BUILTIN_PSRLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32783 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4si_mask, "__builtin_ia32_psrlv4si_mask", IX86_BUILTIN_PSRLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32784 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psrawi256_mask", IX86_BUILTIN_PSRAWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32785 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psraw256_mask", IX86_BUILTIN_PSRAW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32786 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psrawi128_mask", IX86_BUILTIN_PSRAWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32787 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psraw128_mask", IX86_BUILTIN_PSRAW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32788 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlwi256_mask", IX86_BUILTIN_PSRLWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32789 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlw256_mask", IX86_BUILTIN_PSRLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32790 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlwi128_mask", IX86_BUILTIN_PSRLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32791 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlw128_mask", IX86_BUILTIN_PSRLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32792 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv8si_mask, "__builtin_ia32_prorvd256_mask", IX86_BUILTIN_PRORVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32793 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv8si_mask, "__builtin_ia32_prolvd256_mask", IX86_BUILTIN_PROLVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32794 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv8si_mask, "__builtin_ia32_prord256_mask", IX86_BUILTIN_PRORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32795 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv8si_mask, "__builtin_ia32_prold256_mask", IX86_BUILTIN_PROLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32796 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4si_mask, "__builtin_ia32_prorvd128_mask", IX86_BUILTIN_PRORVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32797 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4si_mask, "__builtin_ia32_prolvd128_mask", IX86_BUILTIN_PROLVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32798 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_ia32_prord128_mask", IX86_BUILTIN_PRORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32799 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32800 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_QI },
32801 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_QI },
32802 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT },
32803 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_QI },
32804 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_QI },
32805 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT },
32806 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) HI_FTYPE_V16QI },
32807 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) SI_FTYPE_V32QI },
32808 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) QI_FTYPE_V8HI },
32809 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv16hi, "__builtin_ia32_cvtw2mask256", IX86_BUILTIN_CVTW2MASK256, UNKNOWN, (int) HI_FTYPE_V16HI },
32810 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv4si, "__builtin_ia32_cvtd2mask128", IX86_BUILTIN_CVTD2MASK128, UNKNOWN, (int) QI_FTYPE_V4SI },
32811 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv8si, "__builtin_ia32_cvtd2mask256", IX86_BUILTIN_CVTD2MASK256, UNKNOWN, (int) QI_FTYPE_V8SI },
32812 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv2di, "__builtin_ia32_cvtq2mask128", IX86_BUILTIN_CVTQ2MASK128, UNKNOWN, (int) QI_FTYPE_V2DI },
32813 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv4di, "__builtin_ia32_cvtq2mask256", IX86_BUILTIN_CVTQ2MASK256, UNKNOWN, (int) QI_FTYPE_V4DI },
32814 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv16qi, "__builtin_ia32_cvtmask2b128", IX86_BUILTIN_CVTMASK2B128, UNKNOWN, (int) V16QI_FTYPE_HI },
32815 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv32qi, "__builtin_ia32_cvtmask2b256", IX86_BUILTIN_CVTMASK2B256, UNKNOWN, (int) V32QI_FTYPE_SI },
32816 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv8hi, "__builtin_ia32_cvtmask2w128", IX86_BUILTIN_CVTMASK2W128, UNKNOWN, (int) V8HI_FTYPE_QI },
32817 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv16hi, "__builtin_ia32_cvtmask2w256", IX86_BUILTIN_CVTMASK2W256, UNKNOWN, (int) V16HI_FTYPE_HI },
32818 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv4si, "__builtin_ia32_cvtmask2d128", IX86_BUILTIN_CVTMASK2D128, UNKNOWN, (int) V4SI_FTYPE_QI },
32819 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv8si, "__builtin_ia32_cvtmask2d256", IX86_BUILTIN_CVTMASK2D256, UNKNOWN, (int) V8SI_FTYPE_QI },
32820 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv2di, "__builtin_ia32_cvtmask2q128", IX86_BUILTIN_CVTMASK2Q128, UNKNOWN, (int) V2DI_FTYPE_QI },
32821 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv4di, "__builtin_ia32_cvtmask2q256", IX86_BUILTIN_CVTMASK2Q256, UNKNOWN, (int) V4DI_FTYPE_QI },
32822 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16qi3_mask, "__builtin_ia32_pcmpeqb128_mask", IX86_BUILTIN_PCMPEQB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32823 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv32qi3_mask, "__builtin_ia32_pcmpeqb256_mask", IX86_BUILTIN_PCMPEQB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32824 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8hi3_mask, "__builtin_ia32_pcmpeqw128_mask", IX86_BUILTIN_PCMPEQW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32825 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16hi3_mask, "__builtin_ia32_pcmpeqw256_mask", IX86_BUILTIN_PCMPEQW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32826 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4si3_mask, "__builtin_ia32_pcmpeqd128_mask", IX86_BUILTIN_PCMPEQD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32827 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8si3_mask, "__builtin_ia32_pcmpeqd256_mask", IX86_BUILTIN_PCMPEQD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32828 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv2di3_mask, "__builtin_ia32_pcmpeqq128_mask", IX86_BUILTIN_PCMPEQQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32829 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4di3_mask, "__builtin_ia32_pcmpeqq256_mask", IX86_BUILTIN_PCMPEQQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32830 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16qi3_mask, "__builtin_ia32_pcmpgtb128_mask", IX86_BUILTIN_PCMPGTB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32831 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv32qi3_mask, "__builtin_ia32_pcmpgtb256_mask", IX86_BUILTIN_PCMPGTB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32832 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8hi3_mask, "__builtin_ia32_pcmpgtw128_mask", IX86_BUILTIN_PCMPGTW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32833 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16hi3_mask, "__builtin_ia32_pcmpgtw256_mask", IX86_BUILTIN_PCMPGTW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32834 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4si3_mask, "__builtin_ia32_pcmpgtd128_mask", IX86_BUILTIN_PCMPGTD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32835 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8si3_mask, "__builtin_ia32_pcmpgtd256_mask", IX86_BUILTIN_PCMPGTD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32836 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv2di3_mask, "__builtin_ia32_pcmpgtq128_mask", IX86_BUILTIN_PCMPGTQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32837 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4di3_mask, "__builtin_ia32_pcmpgtq256_mask", IX86_BUILTIN_PCMPGTQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32838 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16qi3_mask, "__builtin_ia32_ptestmb128", IX86_BUILTIN_PTESTMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32839 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv32qi3_mask, "__builtin_ia32_ptestmb256", IX86_BUILTIN_PTESTMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32840 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8hi3_mask, "__builtin_ia32_ptestmw128", IX86_BUILTIN_PTESTMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32841 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16hi3_mask, "__builtin_ia32_ptestmw256", IX86_BUILTIN_PTESTMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32842 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4si3_mask, "__builtin_ia32_ptestmd128", IX86_BUILTIN_PTESTMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32843 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8si3_mask, "__builtin_ia32_ptestmd256", IX86_BUILTIN_PTESTMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32844 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv2di3_mask, "__builtin_ia32_ptestmq128", IX86_BUILTIN_PTESTMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32845 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4di3_mask, "__builtin_ia32_ptestmq256", IX86_BUILTIN_PTESTMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32846 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16qi3_mask, "__builtin_ia32_ptestnmb128", IX86_BUILTIN_PTESTNMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32847 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv32qi3_mask, "__builtin_ia32_ptestnmb256", IX86_BUILTIN_PTESTNMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32848 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8hi3_mask, "__builtin_ia32_ptestnmw128", IX86_BUILTIN_PTESTNMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32849 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16hi3_mask, "__builtin_ia32_ptestnmw256", IX86_BUILTIN_PTESTNMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32850 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4si3_mask, "__builtin_ia32_ptestnmd128", IX86_BUILTIN_PTESTNMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32851 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8si3_mask, "__builtin_ia32_ptestnmd256", IX86_BUILTIN_PTESTNMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32852 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv2di3_mask, "__builtin_ia32_ptestnmq128", IX86_BUILTIN_PTESTNMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32853 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4di3_mask, "__builtin_ia32_ptestnmq256", IX86_BUILTIN_PTESTNMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32854 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv2di, "__builtin_ia32_broadcastmb128", IX86_BUILTIN_PBROADCASTMB128, UNKNOWN, (int) V2DI_FTYPE_QI },
32855 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv4di, "__builtin_ia32_broadcastmb256", IX86_BUILTIN_PBROADCASTMB256, UNKNOWN, (int) V4DI_FTYPE_QI },
32856 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv4si, "__builtin_ia32_broadcastmw128", IX86_BUILTIN_PBROADCASTMW128, UNKNOWN, (int) V4SI_FTYPE_HI },
32857 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv8si, "__builtin_ia32_broadcastmw256", IX86_BUILTIN_PBROADCASTMW256, UNKNOWN, (int) V8SI_FTYPE_HI },
32858 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4df_mask, "__builtin_ia32_compressdf256_mask", IX86_BUILTIN_COMPRESSPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32859 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2df_mask, "__builtin_ia32_compressdf128_mask", IX86_BUILTIN_COMPRESSPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32860 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8sf_mask, "__builtin_ia32_compresssf256_mask", IX86_BUILTIN_COMPRESSPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32861 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4sf_mask, "__builtin_ia32_compresssf128_mask", IX86_BUILTIN_COMPRESSPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32862 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4di_mask, "__builtin_ia32_compressdi256_mask", IX86_BUILTIN_PCOMPRESSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32863 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2di_mask, "__builtin_ia32_compressdi128_mask", IX86_BUILTIN_PCOMPRESSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32864 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8si_mask, "__builtin_ia32_compresssi256_mask", IX86_BUILTIN_PCOMPRESSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32865 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4si_mask, "__builtin_ia32_compresssi128_mask", IX86_BUILTIN_PCOMPRESSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32866 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expanddf256_mask", IX86_BUILTIN_EXPANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32867 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expanddf128_mask", IX86_BUILTIN_EXPANDPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32868 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandsf256_mask", IX86_BUILTIN_EXPANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32869 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandsf128_mask", IX86_BUILTIN_EXPANDPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32870 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expanddi256_mask", IX86_BUILTIN_PEXPANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32871 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expanddi128_mask", IX86_BUILTIN_PEXPANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32872 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandsi256_mask", IX86_BUILTIN_PEXPANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32873 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandsi128_mask", IX86_BUILTIN_PEXPANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32874 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expanddf256_maskz", IX86_BUILTIN_EXPANDPD256Z, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32875 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expanddf128_maskz", IX86_BUILTIN_EXPANDPD128Z, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32876 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandsf256_maskz", IX86_BUILTIN_EXPANDPS256Z, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32877 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandsf128_maskz", IX86_BUILTIN_EXPANDPS128Z, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32878 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expanddi256_maskz", IX86_BUILTIN_PEXPANDQ256Z, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32879 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expanddi128_maskz", IX86_BUILTIN_PEXPANDQ128Z, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32880 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandsi256_maskz", IX86_BUILTIN_PEXPANDD256Z, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32881 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandsi128_maskz", IX86_BUILTIN_PEXPANDD128Z, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32882 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8si3_mask, "__builtin_ia32_pmaxsd256_mask", IX86_BUILTIN_PMAXSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32883 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8si3_mask, "__builtin_ia32_pminsd256_mask", IX86_BUILTIN_PMINSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32884 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8si3_mask, "__builtin_ia32_pmaxud256_mask", IX86_BUILTIN_PMAXUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32885 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8si3_mask, "__builtin_ia32_pminud256_mask", IX86_BUILTIN_PMINUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32886 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4si3_mask, "__builtin_ia32_pmaxsd128_mask", IX86_BUILTIN_PMAXSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32887 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4si3_mask, "__builtin_ia32_pminsd128_mask", IX86_BUILTIN_PMINSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32888 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4si3_mask, "__builtin_ia32_pmaxud128_mask", IX86_BUILTIN_PMAXUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32889 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4si3_mask, "__builtin_ia32_pminud128_mask", IX86_BUILTIN_PMINUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32890 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4di3_mask, "__builtin_ia32_pmaxsq256_mask", IX86_BUILTIN_PMAXSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32891 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4di3_mask, "__builtin_ia32_pminsq256_mask", IX86_BUILTIN_PMINSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32892 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4di3_mask, "__builtin_ia32_pmaxuq256_mask", IX86_BUILTIN_PMAXUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32893 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4di3_mask, "__builtin_ia32_pminuq256_mask", IX86_BUILTIN_PMINUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32894 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2di3_mask, "__builtin_ia32_pmaxsq128_mask", IX86_BUILTIN_PMAXSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32895 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2di3_mask, "__builtin_ia32_pminsq128_mask", IX86_BUILTIN_PMINSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32896 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv2di3_mask, "__builtin_ia32_pmaxuq128_mask", IX86_BUILTIN_PMAXUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32897 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv2di3_mask, "__builtin_ia32_pminuq128_mask", IX86_BUILTIN_PMINUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32898 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv32qi3_mask, "__builtin_ia32_pminsb256_mask", IX86_BUILTIN_PMINSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32899 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv32qi3_mask, "__builtin_ia32_pminub256_mask", IX86_BUILTIN_PMINUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32900 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv32qi3_mask, "__builtin_ia32_pmaxsb256_mask", IX86_BUILTIN_PMAXSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32901 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv32qi3_mask, "__builtin_ia32_pmaxub256_mask", IX86_BUILTIN_PMAXUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32902 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16qi3_mask, "__builtin_ia32_pminsb128_mask", IX86_BUILTIN_PMINSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32903 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16qi3_mask, "__builtin_ia32_pminub128_mask", IX86_BUILTIN_PMINUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32904 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16qi3_mask, "__builtin_ia32_pmaxsb128_mask", IX86_BUILTIN_PMAXSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32905 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16qi3_mask, "__builtin_ia32_pmaxub128_mask", IX86_BUILTIN_PMAXUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32906 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16hi3_mask, "__builtin_ia32_pminsw256_mask", IX86_BUILTIN_PMINSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32907 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16hi3_mask, "__builtin_ia32_pminuw256_mask", IX86_BUILTIN_PMINUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32908 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16hi3_mask, "__builtin_ia32_pmaxsw256_mask", IX86_BUILTIN_PMAXSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32909 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16hi3_mask, "__builtin_ia32_pmaxuw256_mask", IX86_BUILTIN_PMAXUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32910 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8hi3_mask, "__builtin_ia32_pminsw128_mask", IX86_BUILTIN_PMINSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32911 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8hi3_mask, "__builtin_ia32_pminuw128_mask", IX86_BUILTIN_PMINUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32912 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8hi3_mask, "__builtin_ia32_pmaxsw128_mask", IX86_BUILTIN_PMAXSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32913 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8hi3_mask, "__builtin_ia32_pmaxuw128_mask", IX86_BUILTIN_PMAXUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32914 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4di_mask, "__builtin_ia32_vpconflictdi_256_mask", IX86_BUILTIN_VPCONFLICTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32915 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv8si_mask, "__builtin_ia32_vpconflictsi_256_mask", IX86_BUILTIN_VPCONFLICTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32916 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4di2_mask, "__builtin_ia32_vplzcntq_256_mask", IX86_BUILTIN_VPCLZCNTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32917 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv8si2_mask, "__builtin_ia32_vplzcntd_256_mask", IX86_BUILTIN_VPCLZCNTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32918 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhpd256_mask, "__builtin_ia32_unpckhpd256_mask", IX86_BUILTIN_UNPCKHPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32919 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpckhpd128_mask, "__builtin_ia32_unpckhpd128_mask", IX86_BUILTIN_UNPCKHPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32920 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhps256_mask, "__builtin_ia32_unpckhps256_mask", IX86_BUILTIN_UNPCKHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32921 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4sf_mask, "__builtin_ia32_unpckhps128_mask", IX86_BUILTIN_UNPCKHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32922 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklpd256_mask, "__builtin_ia32_unpcklpd256_mask", IX86_BUILTIN_UNPCKLPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32923 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpcklpd128_mask, "__builtin_ia32_unpcklpd128_mask", IX86_BUILTIN_UNPCKLPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32924 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklps256_mask, "__builtin_ia32_unpcklps256_mask", IX86_BUILTIN_UNPCKLPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32925 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv2di_mask, "__builtin_ia32_vpconflictdi_128_mask", IX86_BUILTIN_VPCONFLICTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32926 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4si_mask, "__builtin_ia32_vpconflictsi_128_mask", IX86_BUILTIN_VPCONFLICTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32927 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv2di2_mask, "__builtin_ia32_vplzcntq_128_mask", IX86_BUILTIN_VPCLZCNTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32928 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4si2_mask, "__builtin_ia32_vplzcntd_128_mask", IX86_BUILTIN_VPCLZCNTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32929 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_unpcklps128_mask, "__builtin_ia32_unpcklps128_mask", IX86_BUILTIN_UNPCKLPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32930 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv8si_mask, "__builtin_ia32_alignd256_mask", IX86_BUILTIN_ALIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32931 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4di_mask, "__builtin_ia32_alignq256_mask", IX86_BUILTIN_ALIGNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32932 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4si_mask, "__builtin_ia32_alignd128_mask", IX86_BUILTIN_ALIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI },
32933 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv2di_mask, "__builtin_ia32_alignq128_mask", IX86_BUILTIN_ALIGNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI },
32934 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph256_mask, "__builtin_ia32_vcvtps2ph256_mask", IX86_BUILTIN_CVTPS2PH256_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT_V8HI_QI },
32935 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph_mask, "__builtin_ia32_vcvtps2ph_mask", IX86_BUILTIN_CVTPS2PH_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT_V8HI_QI },
32936 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps_mask, "__builtin_ia32_vcvtph2ps_mask", IX86_BUILTIN_CVTPH2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V8HI_V4SF_QI },
32937 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps256_mask, "__builtin_ia32_vcvtph2ps256_mask", IX86_BUILTIN_CVTPH2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8HI_V8SF_QI },
32938 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4si_mask, "__builtin_ia32_punpckhdq128_mask", IX86_BUILTIN_PUNPCKHDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32939 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv8si_mask, "__builtin_ia32_punpckhdq256_mask", IX86_BUILTIN_PUNPCKHDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32940 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv2di_mask, "__builtin_ia32_punpckhqdq128_mask", IX86_BUILTIN_PUNPCKHQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32941 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv4di_mask, "__builtin_ia32_punpckhqdq256_mask", IX86_BUILTIN_PUNPCKHQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32942 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv4si_mask, "__builtin_ia32_punpckldq128_mask", IX86_BUILTIN_PUNPCKLDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32943 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv8si_mask, "__builtin_ia32_punpckldq256_mask", IX86_BUILTIN_PUNPCKLDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32944 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv2di_mask, "__builtin_ia32_punpcklqdq128_mask", IX86_BUILTIN_PUNPCKLQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32945 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv4di_mask, "__builtin_ia32_punpcklqdq256_mask", IX86_BUILTIN_PUNPCKLQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32946 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv16qi_mask, "__builtin_ia32_punpckhbw128_mask", IX86_BUILTIN_PUNPCKHBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32947 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv32qi_mask, "__builtin_ia32_punpckhbw256_mask", IX86_BUILTIN_PUNPCKHBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32948 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv8hi_mask, "__builtin_ia32_punpckhwd128_mask", IX86_BUILTIN_PUNPCKHWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32949 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv16hi_mask, "__builtin_ia32_punpckhwd256_mask", IX86_BUILTIN_PUNPCKHWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32950 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv16qi_mask, "__builtin_ia32_punpcklbw128_mask", IX86_BUILTIN_PUNPCKLBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32951 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv32qi_mask, "__builtin_ia32_punpcklbw256_mask", IX86_BUILTIN_PUNPCKLBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32952 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv8hi_mask, "__builtin_ia32_punpcklwd128_mask", IX86_BUILTIN_PUNPCKLWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32953 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv16hi_mask, "__builtin_ia32_punpcklwd256_mask", IX86_BUILTIN_PUNPCKLWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32954 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv16hi_mask, "__builtin_ia32_psllv16hi_mask", IX86_BUILTIN_PSLLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32955 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv8hi_mask, "__builtin_ia32_psllv8hi_mask", IX86_BUILTIN_PSLLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32956 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packssdw_mask, "__builtin_ia32_packssdw256_mask", IX86_BUILTIN_PACKSSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32957 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packssdw_mask, "__builtin_ia32_packssdw128_mask", IX86_BUILTIN_PACKSSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32958 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packusdw_mask, "__builtin_ia32_packusdw256_mask", IX86_BUILTIN_PACKUSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32959 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_packusdw_mask, "__builtin_ia32_packusdw128_mask", IX86_BUILTIN_PACKUSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32960 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv32qi3_mask, "__builtin_ia32_pavgb256_mask", IX86_BUILTIN_PAVGB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32961 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv16hi3_mask, "__builtin_ia32_pavgw256_mask", IX86_BUILTIN_PAVGW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32962 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv16qi3_mask, "__builtin_ia32_pavgb128_mask", IX86_BUILTIN_PAVGB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32963 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv8hi3_mask, "__builtin_ia32_pavgw128_mask", IX86_BUILTIN_PAVGW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32964 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8sf_mask, "__builtin_ia32_permvarsf256_mask", IX86_BUILTIN_VPERMVARSF256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32965 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4df_mask, "__builtin_ia32_permvardf256_mask", IX86_BUILTIN_VPERMVARDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32966 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4df_mask, "__builtin_ia32_permdf256_mask", IX86_BUILTIN_VPERMDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32967 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv32qi2_mask, "__builtin_ia32_pabsb256_mask", IX86_BUILTIN_PABSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32968 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16qi2_mask, "__builtin_ia32_pabsb128_mask", IX86_BUILTIN_PABSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32969 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16hi2_mask, "__builtin_ia32_pabsw256_mask", IX86_BUILTIN_PABSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32970 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8hi2_mask, "__builtin_ia32_pabsw128_mask", IX86_BUILTIN_PABSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32971 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv2df3_mask, "__builtin_ia32_vpermilvarpd_mask", IX86_BUILTIN_VPERMILVARPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32972 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4sf3_mask, "__builtin_ia32_vpermilvarps_mask", IX86_BUILTIN_VPERMILVARPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32973 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4df3_mask, "__builtin_ia32_vpermilvarpd256_mask", IX86_BUILTIN_VPERMILVARPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32974 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv8sf3_mask, "__builtin_ia32_vpermilvarps256_mask", IX86_BUILTIN_VPERMILVARPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32975 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv2df_mask, "__builtin_ia32_vpermilpd_mask", IX86_BUILTIN_VPERMILPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32976 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4sf_mask, "__builtin_ia32_vpermilps_mask", IX86_BUILTIN_VPERMILPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32977 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4df_mask, "__builtin_ia32_vpermilpd256_mask", IX86_BUILTIN_VPERMILPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32978 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv8sf_mask, "__builtin_ia32_vpermilps256_mask", IX86_BUILTIN_VPERMILPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32979 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4di, "__builtin_ia32_blendmq_256_mask", IX86_BUILTIN_BLENDMQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32980 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8si, "__builtin_ia32_blendmd_256_mask", IX86_BUILTIN_BLENDMD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32981 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4df, "__builtin_ia32_blendmpd_256_mask", IX86_BUILTIN_BLENDMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32982 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8sf, "__builtin_ia32_blendmps_256_mask", IX86_BUILTIN_BLENDMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32983 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2di, "__builtin_ia32_blendmq_128_mask", IX86_BUILTIN_BLENDMQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32984 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4si, "__builtin_ia32_blendmd_128_mask", IX86_BUILTIN_BLENDMD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32985 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2df, "__builtin_ia32_blendmpd_128_mask", IX86_BUILTIN_BLENDMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32986 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4sf, "__builtin_ia32_blendmps_128_mask", IX86_BUILTIN_BLENDMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32987 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16hi, "__builtin_ia32_blendmw_256_mask", IX86_BUILTIN_BLENDMW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32988 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv32qi, "__builtin_ia32_blendmb_256_mask", IX86_BUILTIN_BLENDMB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32989 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8hi, "__builtin_ia32_blendmw_128_mask", IX86_BUILTIN_BLENDMW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32990 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16qi, "__builtin_ia32_blendmb_128_mask", IX86_BUILTIN_BLENDMB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32991 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8si3_mask, "__builtin_ia32_pmulld256_mask", IX86_BUILTIN_PMULLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32992 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4si3_mask, "__builtin_ia32_pmulld128_mask", IX86_BUILTIN_PMULLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32993 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v8si_mask, "__builtin_ia32_pmuludq256_mask", IX86_BUILTIN_PMULUDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32994 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_smult_even_v8si_mask, "__builtin_ia32_pmuldq256_mask", IX86_BUILTIN_PMULDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32995 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_mulv2siv2di3_mask, "__builtin_ia32_pmuldq128_mask", IX86_BUILTIN_PMULDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32996 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v4si_mask, "__builtin_ia32_pmuludq128_mask", IX86_BUILTIN_PMULUDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32997 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2ps256_mask, "__builtin_ia32_cvtpd2ps256_mask", IX86_BUILTIN_CVTPD2PS256_MASK, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_QI },
32998 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2ps_mask, "__builtin_ia32_cvtpd2ps_mask", IX86_BUILTIN_CVTPD2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V2DF_V4SF_QI },
32999 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8si_mask, "__builtin_ia32_permvarsi256_mask", IX86_BUILTIN_VPERMVARSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
33000 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4di_mask, "__builtin_ia32_permvardi256_mask", IX86_BUILTIN_VPERMVARDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33001 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4di_mask, "__builtin_ia32_permdi256_mask", IX86_BUILTIN_VPERMDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
33002 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4di3_mask, "__builtin_ia32_cmpq256_mask", IX86_BUILTIN_CMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
33003 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8si3_mask, "__builtin_ia32_cmpd256_mask", IX86_BUILTIN_CMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
33004 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4di3_mask, "__builtin_ia32_ucmpq256_mask", IX86_BUILTIN_UCMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
33005 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8si3_mask, "__builtin_ia32_ucmpd256_mask", IX86_BUILTIN_UCMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
33006 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv32qi3_mask, "__builtin_ia32_cmpb256_mask", IX86_BUILTIN_CMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
33007 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16hi3_mask, "__builtin_ia32_cmpw256_mask", IX86_BUILTIN_CMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
33008 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv32qi3_mask, "__builtin_ia32_ucmpb256_mask", IX86_BUILTIN_UCMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
33009 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16hi3_mask, "__builtin_ia32_ucmpw256_mask", IX86_BUILTIN_UCMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
33010 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4df3_mask, "__builtin_ia32_cmppd256_mask", IX86_BUILTIN_CMPPD256_MASK, UNKNOWN, (int) QI_FTYPE_V4DF_V4DF_INT_QI },
33011 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8sf3_mask, "__builtin_ia32_cmpps256_mask", IX86_BUILTIN_CMPPS256_MASK, UNKNOWN, (int) QI_FTYPE_V8SF_V8SF_INT_QI },
33012 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2di3_mask, "__builtin_ia32_cmpq128_mask", IX86_BUILTIN_CMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
33013 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4si3_mask, "__builtin_ia32_cmpd128_mask", IX86_BUILTIN_CMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
33014 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv2di3_mask, "__builtin_ia32_ucmpq128_mask", IX86_BUILTIN_UCMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
33015 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4si3_mask, "__builtin_ia32_ucmpd128_mask", IX86_BUILTIN_UCMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
33016 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16qi3_mask, "__builtin_ia32_cmpb128_mask", IX86_BUILTIN_CMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
33017 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8hi3_mask, "__builtin_ia32_cmpw128_mask", IX86_BUILTIN_CMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
33018 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16qi3_mask, "__builtin_ia32_ucmpb128_mask", IX86_BUILTIN_UCMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
33019 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8hi3_mask, "__builtin_ia32_ucmpw128_mask", IX86_BUILTIN_UCMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
33020 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2df3_mask, "__builtin_ia32_cmppd128_mask", IX86_BUILTIN_CMPPD128_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI },
33021 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4sf3_mask, "__builtin_ia32_cmpps128_mask", IX86_BUILTIN_CMPPS128_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI },
33023 /* AVX512DQ. */
33024 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x2_512_mask", IX86_BUILTIN_BROADCASTF32x2_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
33025 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask, "__builtin_ia32_broadcasti32x2_512_mask", IX86_BUILTIN_BROADCASTI32x2_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
33026 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8df_mask_1, "__builtin_ia32_broadcastf64x2_512_mask", IX86_BUILTIN_BROADCASTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
33027 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8di_mask_1, "__builtin_ia32_broadcasti64x2_512_mask", IX86_BUILTIN_BROADCASTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
33028 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask_1, "__builtin_ia32_broadcastf32x8_512_mask", IX86_BUILTIN_BROADCASTF32X8_512, UNKNOWN, (int) V16SF_FTYPE_V8SF_V16SF_HI },
33029 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask_1, "__builtin_ia32_broadcasti32x8_512_mask", IX86_BUILTIN_BROADCASTI32X8_512, UNKNOWN, (int) V16SI_FTYPE_V8SI_V16SI_HI },
33030 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf64x2_mask, "__builtin_ia32_extractf64x2_512_mask", IX86_BUILTIN_EXTRACTF64X2_512, UNKNOWN, (int) V2DF_FTYPE_V8DF_INT_V2DF_QI },
33031 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf32x8_mask, "__builtin_ia32_extractf32x8_mask", IX86_BUILTIN_EXTRACTF32X8, UNKNOWN, (int) V8SF_FTYPE_V16SF_INT_V8SF_QI },
33032 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti64x2_mask, "__builtin_ia32_extracti64x2_512_mask", IX86_BUILTIN_EXTRACTI64X2_512, UNKNOWN, (int) V2DI_FTYPE_V8DI_INT_V2DI_QI },
33033 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti32x8_mask, "__builtin_ia32_extracti32x8_mask", IX86_BUILTIN_EXTRACTI32X8, UNKNOWN, (int) V8SI_FTYPE_V16SI_INT_V8SI_QI },
33034 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv8df_mask, "__builtin_ia32_reducepd512_mask", IX86_BUILTIN_REDUCEPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
33035 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv16sf_mask, "__builtin_ia32_reduceps512_mask", IX86_BUILTIN_REDUCEPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
33036 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_mulv8di3_mask, "__builtin_ia32_pmullq512_mask", IX86_BUILTIN_PMULLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33037 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv8df3_mask, "__builtin_ia32_xorpd512_mask", IX86_BUILTIN_XORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
33038 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv16sf3_mask, "__builtin_ia32_xorps512_mask", IX86_BUILTIN_XORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
33039 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv8df3_mask, "__builtin_ia32_orpd512_mask", IX86_BUILTIN_ORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
33040 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv16sf3_mask, "__builtin_ia32_orps512_mask", IX86_BUILTIN_ORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
33041 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv8df3_mask, "__builtin_ia32_andpd512_mask", IX86_BUILTIN_ANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
33042 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv16sf3_mask, "__builtin_ia32_andps512_mask", IX86_BUILTIN_ANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
33043 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv8df3_mask, "__builtin_ia32_andnpd512_mask", IX86_BUILTIN_ANDNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI},
33044 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv16sf3_mask, "__builtin_ia32_andnps512_mask", IX86_BUILTIN_ANDNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
33045 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf32x8_mask, "__builtin_ia32_insertf32x8_mask", IX86_BUILTIN_INSERTF32X8, UNKNOWN, (int) V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI },
33046 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti32x8_mask, "__builtin_ia32_inserti32x8_mask", IX86_BUILTIN_INSERTI32X8, UNKNOWN, (int) V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI },
33047 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf64x2_mask, "__builtin_ia32_insertf64x2_512_mask", IX86_BUILTIN_INSERTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI },
33048 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti64x2_mask, "__builtin_ia32_inserti64x2_512_mask", IX86_BUILTIN_INSERTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI },
33049 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv8df_mask, "__builtin_ia32_fpclasspd512_mask", IX86_BUILTIN_FPCLASSPD512, UNKNOWN, (int) QI_FTYPE_V8DF_INT_QI },
33050 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv16sf_mask, "__builtin_ia32_fpclassps512_mask", IX86_BUILTIN_FPCLASSPS512, UNKNOWN, (int) HI_FTYPE_V16SF_INT_HI },
33051 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtd2maskv16si, "__builtin_ia32_cvtd2mask512", IX86_BUILTIN_CVTD2MASK512, UNKNOWN, (int) HI_FTYPE_V16SI },
33052 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtq2maskv8di, "__builtin_ia32_cvtq2mask512", IX86_BUILTIN_CVTQ2MASK512, UNKNOWN, (int) QI_FTYPE_V8DI },
33053 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2dv16si, "__builtin_ia32_cvtmask2d512", IX86_BUILTIN_CVTMASK2D512, UNKNOWN, (int) V16SI_FTYPE_HI },
33054 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2qv8di, "__builtin_ia32_cvtmask2q512", IX86_BUILTIN_CVTMASK2Q512, UNKNOWN, (int) V8DI_FTYPE_QI },
33056 /* AVX512BW. */
33057 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpcksi, "__builtin_ia32_kunpcksi", IX86_BUILTIN_KUNPCKWD, UNKNOWN, (int) SI_FTYPE_SI_SI },
33058 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpckdi, "__builtin_ia32_kunpckdi", IX86_BUILTIN_KUNPCKDQ, UNKNOWN, (int) DI_FTYPE_DI_DI },
33059 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packusdw_mask, "__builtin_ia32_packusdw512_mask", IX86_BUILTIN_PACKUSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
33060 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlv4ti3, "__builtin_ia32_pslldq512", IX86_BUILTIN_PSLLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
33061 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrv4ti3, "__builtin_ia32_psrldq512", IX86_BUILTIN_PSRLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
33062 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packssdw_mask, "__builtin_ia32_packssdw512_mask", IX86_BUILTIN_PACKSSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
33063 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv4ti, "__builtin_ia32_palignr512", IX86_BUILTIN_PALIGNR512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_CONVERT },
33064 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv64qi_mask, "__builtin_ia32_palignr512_mask", IX86_BUILTIN_PALIGNR512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT },
33065 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_movdquhi512_mask", IX86_BUILTIN_MOVDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
33066 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_movdquqi512_mask", IX86_BUILTIN_MOVDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
33067 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_psadbw, "__builtin_ia32_psadbw512", IX86_BUILTIN_PSADBW512, UNKNOWN, (int) V8DI_FTYPE_V64QI_V64QI },
33068 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_dbpsadbwv32hi_mask, "__builtin_ia32_dbpsadbw512_mask", IX86_BUILTIN_DBPSADBW512, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI },
33069 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv64qi_mask, "__builtin_ia32_pbroadcastb512_mask", IX86_BUILTIN_PBROADCASTB512, UNKNOWN, (int) V64QI_FTYPE_V16QI_V64QI_DI },
33070 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv64qi_mask, "__builtin_ia32_pbroadcastb512_gpr_mask", IX86_BUILTIN_PBROADCASTB512_GPR, UNKNOWN, (int) V64QI_FTYPE_QI_V64QI_DI },
33071 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv32hi_mask, "__builtin_ia32_pbroadcastw512_mask", IX86_BUILTIN_PBROADCASTW512, UNKNOWN, (int) V32HI_FTYPE_V8HI_V32HI_SI },
33072 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv32hi_mask, "__builtin_ia32_pbroadcastw512_gpr_mask", IX86_BUILTIN_PBROADCASTW512_GPR, UNKNOWN, (int) V32HI_FTYPE_HI_V32HI_SI },
33073 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sign_extendv32qiv32hi2_mask, "__builtin_ia32_pmovsxbw512_mask", IX86_BUILTIN_PMOVSXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
33074 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_zero_extendv32qiv32hi2_mask, "__builtin_ia32_pmovzxbw512_mask", IX86_BUILTIN_PMOVZXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
33075 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_permvarv32hi_mask, "__builtin_ia32_permvarhi512_mask", IX86_BUILTIN_VPERMVARHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33076 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_mask, "__builtin_ia32_vpermt2varhi512_mask", IX86_BUILTIN_VPERMT2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33077 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_maskz, "__builtin_ia32_vpermt2varhi512_maskz", IX86_BUILTIN_VPERMT2VARHI512_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33078 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermi2varv32hi3_mask, "__builtin_ia32_vpermi2varhi512_mask", IX86_BUILTIN_VPERMI2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33079 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv64qi3_mask, "__builtin_ia32_pavgb512_mask", IX86_BUILTIN_PAVGB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33080 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv32hi3_mask, "__builtin_ia32_pavgw512_mask", IX86_BUILTIN_PAVGW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33081 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv64qi3_mask, "__builtin_ia32_paddb512_mask", IX86_BUILTIN_PADDB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33082 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv64qi3_mask, "__builtin_ia32_psubb512_mask", IX86_BUILTIN_PSUBB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33083 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv64qi3_mask, "__builtin_ia32_psubsb512_mask", IX86_BUILTIN_PSUBSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33084 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv64qi3_mask, "__builtin_ia32_paddsb512_mask", IX86_BUILTIN_PADDSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33085 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv64qi3_mask, "__builtin_ia32_psubusb512_mask", IX86_BUILTIN_PSUBUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33086 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv64qi3_mask, "__builtin_ia32_paddusb512_mask", IX86_BUILTIN_PADDUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33087 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv32hi3_mask, "__builtin_ia32_psubw512_mask", IX86_BUILTIN_PSUBW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33088 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv32hi3_mask, "__builtin_ia32_paddw512_mask", IX86_BUILTIN_PADDW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33089 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv32hi3_mask, "__builtin_ia32_psubsw512_mask", IX86_BUILTIN_PSUBSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33090 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv32hi3_mask, "__builtin_ia32_paddsw512_mask", IX86_BUILTIN_PADDSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33091 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv32hi3_mask, "__builtin_ia32_psubusw512_mask", IX86_BUILTIN_PSUBUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33092 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv32hi3_mask, "__builtin_ia32_paddusw512_mask", IX86_BUILTIN_PADDUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33093 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv32hi3_mask, "__builtin_ia32_pmaxuw512_mask", IX86_BUILTIN_PMAXUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33094 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv32hi3_mask, "__builtin_ia32_pmaxsw512_mask", IX86_BUILTIN_PMAXSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33095 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv32hi3_mask, "__builtin_ia32_pminuw512_mask", IX86_BUILTIN_PMINUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33096 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv32hi3_mask, "__builtin_ia32_pminsw512_mask", IX86_BUILTIN_PMINSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33097 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv64qi3_mask, "__builtin_ia32_pmaxub512_mask", IX86_BUILTIN_PMAXUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33098 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv64qi3_mask, "__builtin_ia32_pmaxsb512_mask", IX86_BUILTIN_PMAXSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33099 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv64qi3_mask, "__builtin_ia32_pminub512_mask", IX86_BUILTIN_PMINUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33100 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv64qi3_mask, "__builtin_ia32_pminsb512_mask", IX86_BUILTIN_PMINSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33101 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovwb512_mask", IX86_BUILTIN_PMOVWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
33102 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ss_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovswb512_mask", IX86_BUILTIN_PMOVSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
33103 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_us_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovuswb512_mask", IX86_BUILTIN_PMOVUSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
33104 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_umulhrswv32hi3_mask, "__builtin_ia32_pmulhrsw512_mask", IX86_BUILTIN_PMULHRSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33105 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umulv32hi3_highpart_mask, "__builtin_ia32_pmulhuw512_mask" , IX86_BUILTIN_PMULHUW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33106 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smulv32hi3_highpart_mask, "__builtin_ia32_pmulhw512_mask" , IX86_BUILTIN_PMULHW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33107 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_mulv32hi3_mask, "__builtin_ia32_pmullw512_mask", IX86_BUILTIN_PMULLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33108 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllwi512_mask", IX86_BUILTIN_PSLLWI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
33109 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllw512_mask", IX86_BUILTIN_PSLLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
33110 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packsswb_mask, "__builtin_ia32_packsswb512_mask", IX86_BUILTIN_PACKSSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
33111 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packuswb_mask, "__builtin_ia32_packuswb512_mask", IX86_BUILTIN_PACKUSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
33112 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashrvv32hi_mask, "__builtin_ia32_psrav32hi_mask", IX86_BUILTIN_PSRAVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33113 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddubsw512v32hi_mask, "__builtin_ia32_pmaddubsw512_mask", IX86_BUILTIN_PMADDUBSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_V32HI_SI },
33114 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddwd512v32hi_mask, "__builtin_ia32_pmaddwd512_mask", IX86_BUILTIN_PMADDWD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V32HI_V32HI_V16SI_HI },
33115 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrvv32hi_mask, "__builtin_ia32_psrlv32hi_mask", IX86_BUILTIN_PSRLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33116 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv64qi_mask, "__builtin_ia32_punpckhbw512_mask", IX86_BUILTIN_PUNPCKHBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33117 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv32hi_mask, "__builtin_ia32_punpckhwd512_mask", IX86_BUILTIN_PUNPCKHWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33118 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv64qi_mask, "__builtin_ia32_punpcklbw512_mask", IX86_BUILTIN_PUNPCKLBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33119 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv32hi_mask, "__builtin_ia32_punpcklwd512_mask", IX86_BUILTIN_PUNPCKLWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33120 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufbv64qi3_mask, "__builtin_ia32_pshufb512_mask", IX86_BUILTIN_PSHUFB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33121 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufhwv32hi_mask, "__builtin_ia32_pshufhw512_mask", IX86_BUILTIN_PSHUFHW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
33122 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshuflwv32hi_mask, "__builtin_ia32_pshuflw512_mask", IX86_BUILTIN_PSHUFLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
33123 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psrawi512_mask", IX86_BUILTIN_PSRAWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
33124 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psraw512_mask", IX86_BUILTIN_PSRAW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
33125 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlwi512_mask", IX86_BUILTIN_PSRLWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
33126 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlw512_mask", IX86_BUILTIN_PSRLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
33127 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtb2maskv64qi, "__builtin_ia32_cvtb2mask512", IX86_BUILTIN_CVTB2MASK512, UNKNOWN, (int) DI_FTYPE_V64QI },
33128 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtw2maskv32hi, "__builtin_ia32_cvtw2mask512", IX86_BUILTIN_CVTW2MASK512, UNKNOWN, (int) SI_FTYPE_V32HI },
33129 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2bv64qi, "__builtin_ia32_cvtmask2b512", IX86_BUILTIN_CVTMASK2B512, UNKNOWN, (int) V64QI_FTYPE_DI },
33130 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2wv32hi, "__builtin_ia32_cvtmask2w512", IX86_BUILTIN_CVTMASK2W512, UNKNOWN, (int) V32HI_FTYPE_SI },
33131 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv64qi3_mask, "__builtin_ia32_pcmpeqb512_mask", IX86_BUILTIN_PCMPEQB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
33132 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv32hi3_mask, "__builtin_ia32_pcmpeqw512_mask", IX86_BUILTIN_PCMPEQW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
33133 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv64qi3_mask, "__builtin_ia32_pcmpgtb512_mask", IX86_BUILTIN_PCMPGTB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
33134 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv32hi3_mask, "__builtin_ia32_pcmpgtw512_mask", IX86_BUILTIN_PCMPGTW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
33135 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv64qi3_mask, "__builtin_ia32_ptestmb512", IX86_BUILTIN_PTESTMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
33136 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv32hi3_mask, "__builtin_ia32_ptestmw512", IX86_BUILTIN_PTESTMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
33137 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv64qi3_mask, "__builtin_ia32_ptestnmb512", IX86_BUILTIN_PTESTNMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
33138 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv32hi3_mask, "__builtin_ia32_ptestnmw512", IX86_BUILTIN_PTESTNMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
33139 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlvv32hi_mask, "__builtin_ia32_psllv32hi_mask", IX86_BUILTIN_PSLLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
33140 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv64qi2_mask, "__builtin_ia32_pabsb512_mask", IX86_BUILTIN_PABSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
33141 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv32hi2_mask, "__builtin_ia32_pabsw512_mask", IX86_BUILTIN_PABSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
33142 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv32hi, "__builtin_ia32_blendmw_512_mask", IX86_BUILTIN_BLENDMW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
33143 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv64qi, "__builtin_ia32_blendmb_512_mask", IX86_BUILTIN_BLENDMB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
33144 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv64qi3_mask, "__builtin_ia32_cmpb512_mask", IX86_BUILTIN_CMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
33145 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
33146 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
33147 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
33149 /* AVX512IFMA */
33150 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_mask, "__builtin_ia32_vpmadd52luq512_mask", IX86_BUILTIN_VPMADD52LUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33151 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_maskz, "__builtin_ia32_vpmadd52luq512_maskz", IX86_BUILTIN_VPMADD52LUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33152 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_mask, "__builtin_ia32_vpmadd52huq512_mask", IX86_BUILTIN_VPMADD52HUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33153 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_maskz, "__builtin_ia32_vpmadd52huq512_maskz", IX86_BUILTIN_VPMADD52HUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33154 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_mask, "__builtin_ia32_vpmadd52luq256_mask", IX86_BUILTIN_VPMADD52LUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33155 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_maskz, "__builtin_ia32_vpmadd52luq256_maskz", IX86_BUILTIN_VPMADD52LUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33156 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_mask, "__builtin_ia32_vpmadd52huq256_mask", IX86_BUILTIN_VPMADD52HUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33157 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_maskz, "__builtin_ia32_vpmadd52huq256_maskz", IX86_BUILTIN_VPMADD52HUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33158 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_mask, "__builtin_ia32_vpmadd52luq128_mask", IX86_BUILTIN_VPMADD52LUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33159 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_maskz, "__builtin_ia32_vpmadd52luq128_maskz", IX86_BUILTIN_VPMADD52LUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33160 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_mask, "__builtin_ia32_vpmadd52huq128_mask", IX86_BUILTIN_VPMADD52HUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33161 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_maskz, "__builtin_ia32_vpmadd52huq128_maskz", IX86_BUILTIN_VPMADD52HUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33163 /* AVX512VBMI */
33164 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_vpmultishiftqbv64qi_mask, "__builtin_ia32_vpmultishiftqb512_mask", IX86_BUILTIN_VPMULTISHIFTQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33165 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv32qi_mask, "__builtin_ia32_vpmultishiftqb256_mask", IX86_BUILTIN_VPMULTISHIFTQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33166 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv16qi_mask, "__builtin_ia32_vpmultishiftqb128_mask", IX86_BUILTIN_VPMULTISHIFTQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33167 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_permvarv64qi_mask, "__builtin_ia32_permvarqi512_mask", IX86_BUILTIN_VPERMVARQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33168 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_mask, "__builtin_ia32_vpermt2varqi512_mask", IX86_BUILTIN_VPERMT2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33169 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_maskz, "__builtin_ia32_vpermt2varqi512_maskz", IX86_BUILTIN_VPERMT2VARQI512_MASKZ, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33170 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermi2varv64qi3_mask, "__builtin_ia32_vpermi2varqi512_mask", IX86_BUILTIN_VPERMI2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33171 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv32qi_mask, "__builtin_ia32_permvarqi256_mask", IX86_BUILTIN_VPERMVARQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33172 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16qi_mask, "__builtin_ia32_permvarqi128_mask", IX86_BUILTIN_VPERMVARQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33173 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_mask, "__builtin_ia32_vpermt2varqi256_mask", IX86_BUILTIN_VPERMT2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33174 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_maskz, "__builtin_ia32_vpermt2varqi256_maskz", IX86_BUILTIN_VPERMT2VARQI256_MASKZ, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33175 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_mask, "__builtin_ia32_vpermt2varqi128_mask", IX86_BUILTIN_VPERMT2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33176 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_maskz, "__builtin_ia32_vpermt2varqi128_maskz", IX86_BUILTIN_VPERMT2VARQI128_MASKZ, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33177 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv32qi3_mask, "__builtin_ia32_vpermi2varqi256_mask", IX86_BUILTIN_VPERMI2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33178 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16qi3_mask, "__builtin_ia32_vpermi2varqi128_mask", IX86_BUILTIN_VPERMI2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33179 };
33181 /* Builtins with rounding support. */
33183 {
33184 /* AVX512F */
33185 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33186 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33187 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33188 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33189 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
33190 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
33191 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
33192 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
33193 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
33194 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
33195 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
33196 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33197 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
33198 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33199 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
33200 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33201 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
33202 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33203 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
33204 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
33205 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
33206 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
33207 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
33208 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33209 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33210 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33211 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33212 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
33213 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
33214 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
33215 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
33216 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33217 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33218 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33219 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33220 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
33221 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
33222 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
33223 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
33224 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
33225 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
33226 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
33227 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
33228 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33229 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33230 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33231 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33232 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
33233 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
33234 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33235 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33236 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33237 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33238 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33239 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33240 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33241 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33242 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33243 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33244 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33245 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33246 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33247 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33248 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
33249 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
33250 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33251 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33252 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33253 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33254 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33255 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33256 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33257 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33258 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33259 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33260 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33261 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33262 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33263 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33264 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
33265 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33266 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33267 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33268 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33269 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33270 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33271 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33272 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
33273 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33274 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33275 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33276 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33277 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33278 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33279 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33280 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33281 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33282 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33283 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33284 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33285 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33286 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
33287 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
33288 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33289 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33290 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33291 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33292 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33293 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33294 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33295 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33296 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33297 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33298 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33299 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33300 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33301 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33302 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33303 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33305 /* AVX512ER */
33306 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33307 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33308 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33309 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33310 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33311 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33312 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33313 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33314 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33315 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33317 /* AVX512DQ. */
33318 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv2df_round, "__builtin_ia32_rangesd128_round", IX86_BUILTIN_RANGESD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33319 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv4sf_round, "__builtin_ia32_rangess128_round", IX86_BUILTIN_RANGESS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33320 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2qq512_mask", IX86_BUILTIN_CVTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33321 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__builtin_ia32_cvtps2qq512_mask", IX86_BUILTIN_CVTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33322 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33323 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33324 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33325 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33326 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33327 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33328 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33329 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33330 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33331 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33332 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT },
33333 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT },
33334 };
33336 /* Bultins for MPX. */
33338 {
33339 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndstx", IX86_BUILTIN_BNDSTX, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND_PCVOID },
33340 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcl", IX86_BUILTIN_BNDCL, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33341 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcu", IX86_BUILTIN_BNDCU, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33342 };
33344 /* Const builtins for MPX. */
33346 {
33347 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndmk", IX86_BUILTIN_BNDMK, UNKNOWN, (int) BND_FTYPE_PCVOID_ULONG },
33348 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndldx", IX86_BUILTIN_BNDLDX, UNKNOWN, (int) BND_FTYPE_PCVOID_PCVOID },
33349 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_narrow_bounds", IX86_BUILTIN_BNDNARROW, UNKNOWN, (int) PVOID_FTYPE_PCVOID_BND_ULONG },
33350 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndint", IX86_BUILTIN_BNDINT, UNKNOWN, (int) BND_FTYPE_BND_BND },
33351 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_sizeof", IX86_BUILTIN_SIZEOF, UNKNOWN, (int) ULONG_FTYPE_VOID },
33352 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndlower", IX86_BUILTIN_BNDLOWER, UNKNOWN, (int) PVOID_FTYPE_BND },
33353 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndupper", IX86_BUILTIN_BNDUPPER, UNKNOWN, (int) PVOID_FTYPE_BND },
33354 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndret", IX86_BUILTIN_BNDRET, UNKNOWN, (int) BND_FTYPE_PCVOID },
33355 };
33357 /* FMA4 and XOP. */
33358 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
33359 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
33360 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
33361 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
33362 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
33363 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
33364 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
33365 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
33366 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
33367 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
33368 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
33369 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
33370 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
33371 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
33372 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
33373 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
33374 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
33375 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
33376 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
33377 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
33378 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
33379 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
33380 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
33381 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
33382 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
33383 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
33384 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
33385 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
33386 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
33387 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
33388 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
33389 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
33390 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
33391 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
33392 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
33393 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
33394 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
33395 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
33396 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
33397 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
33398 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
33399 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
33400 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
33401 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
33402 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
33403 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
33404 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
33405 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
33406 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
33407 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
33408 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
33409 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
33412 {
33453 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
33454 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
33455 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
33456 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
33457 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
33458 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
33459 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
33461 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33462 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33463 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
33464 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
33465 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
33466 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
33467 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
33469 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
33471 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33472 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33473 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33474 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33475 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33476 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33477 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33478 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33479 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33480 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33481 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33482 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33484 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33485 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
33486 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
33487 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
33488 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
33489 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
33490 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
33491 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
33492 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33493 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
33494 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
33495 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
33496 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33497 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
33498 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
33499 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
33501 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
33502 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
33503 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
33504 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
33505 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
33506 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
33508 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33509 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33510 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33511 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33512 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33513 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33514 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33515 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33516 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33517 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33518 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33519 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33520 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33521 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33522 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33524 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
33525 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33526 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33527 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
33528 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
33529 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
33530 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
33532 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
33533 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33534 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33535 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
33536 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
33537 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
33538 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
33540 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
33541 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33542 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33543 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
33544 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
33545 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
33546 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
33548 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33549 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33550 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33551 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
33552 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
33553 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
33554 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
33556 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
33557 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33558 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33559 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
33560 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
33561 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
33562 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
33564 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
33565 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33566 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33567 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
33568 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
33569 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
33570 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
33572 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
33573 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33574 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33575 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
33576 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
33577 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
33578 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
33580 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33581 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33582 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33583 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
33584 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
33585 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
33586 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
33588 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33589 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33590 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33591 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33592 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33593 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33594 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33595 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33597 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33598 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33599 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33600 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33601 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33602 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33603 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33604 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33606 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
33607 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
33608 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
33609 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
33611 };
33612 \f
33613 /* TM vector builtins. */
33615 /* Reuse the existing x86-specific `struct builtin_description' cause
33616 we're lazy. Add casts to make them fit. */
33618 {
33619 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33620 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33621 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33622 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33623 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33624 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33625 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33627 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33628 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33629 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33630 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33631 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33632 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33633 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33635 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33636 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33637 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33638 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33639 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33640 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33641 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33643 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
33644 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
33645 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
33646 };
33648 /* TM callbacks. */
33650 /* Return the builtin decl needed to load a vector of TYPE. */
33652 static tree
33654 {
33656 {
33658 {
33665 }
33666 }
33668 }
33670 /* Return the builtin decl needed to store a vector of TYPE. */
33672 static tree
33674 {
33676 {
33678 {
33685 }
33686 }
33688 }
33689 \f
33690 /* Initialize the transactional memory vector load/store builtins. */
33692 static void
33694 {
33698 tree decl;
33705 /* If there are no builtins defined, we must be compiling in a
33706 language without trans-mem support. */
33710 /* Use whatever attributes a normal TM load has. */
33714 /* Use whatever attributes a normal TM store has. */
33718 /* Use whatever attributes a normal TM log has. */
33726 {
33730 {
33738 {
33741 }
33743 {
33746 }
33747 else
33748 {
33751 }
33753 /* The builtin without the prefix for
33754 calling it directly. */
33756 attrs);
33757 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
33758 set the TYPE_ATTRIBUTES. */
33762 }
33763 }
33764 }
33766 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
33767 in the current target ISA to allow the user to compile particular modules
33768 with different target specific options that differ from the command line
33769 options. */
33770 static void
33772 {
33777 /* Add all special builtins with variable number of operands. */
33781 {
33787 }
33789 /* Add all builtins with variable number of operands. */
33793 {
33799 }
33801 /* Add all builtins with rounding. */
33805 {
33811 }
33813 /* pcmpestr[im] insns. */
33817 {
33820 else
33823 }
33825 /* pcmpistr[im] insns. */
33829 {
33832 else
33835 }
33837 /* comi/ucomi insns. */
33839 {
33842 else
33845 }
33847 /* SSE */
33853 /* SSE or 3DNow!A */
33856 IX86_BUILTIN_MASKMOVQ);
33858 /* SSE2 */
33867 /* SSE3. */
33873 /* AES */
33887 /* PCLMUL */
33891 /* RDRND */
33898 IX86_BUILTIN_RDRAND64_STEP);
33900 /* AVX2 */
33902 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
33903 IX86_BUILTIN_GATHERSIV2DF);
33906 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
33907 IX86_BUILTIN_GATHERSIV4DF);
33910 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
33911 IX86_BUILTIN_GATHERDIV2DF);
33914 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
33915 IX86_BUILTIN_GATHERDIV4DF);
33918 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
33919 IX86_BUILTIN_GATHERSIV4SF);
33922 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
33923 IX86_BUILTIN_GATHERSIV8SF);
33926 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
33927 IX86_BUILTIN_GATHERDIV4SF);
33930 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
33931 IX86_BUILTIN_GATHERDIV8SF);
33934 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
33935 IX86_BUILTIN_GATHERSIV2DI);
33938 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
33939 IX86_BUILTIN_GATHERSIV4DI);
33942 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
33943 IX86_BUILTIN_GATHERDIV2DI);
33946 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
33947 IX86_BUILTIN_GATHERDIV4DI);
33950 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
33951 IX86_BUILTIN_GATHERSIV4SI);
33954 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
33955 IX86_BUILTIN_GATHERSIV8SI);
33958 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
33959 IX86_BUILTIN_GATHERDIV4SI);
33962 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
33963 IX86_BUILTIN_GATHERDIV8SI);
33966 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
33967 IX86_BUILTIN_GATHERALTSIV4DF);
33970 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
33971 IX86_BUILTIN_GATHERALTDIV8SF);
33974 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
33975 IX86_BUILTIN_GATHERALTSIV4DI);
33978 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
33979 IX86_BUILTIN_GATHERALTDIV8SI);
33981 /* AVX512F */
33983 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
33984 IX86_BUILTIN_GATHER3SIV16SF);
33987 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
33988 IX86_BUILTIN_GATHER3SIV8DF);
33991 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
33992 IX86_BUILTIN_GATHER3DIV16SF);
33995 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
33996 IX86_BUILTIN_GATHER3DIV8DF);
33999 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
34000 IX86_BUILTIN_GATHER3SIV16SI);
34003 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
34004 IX86_BUILTIN_GATHER3SIV8DI);
34007 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
34008 IX86_BUILTIN_GATHER3DIV16SI);
34011 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
34012 IX86_BUILTIN_GATHER3DIV8DI);
34015 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
34016 IX86_BUILTIN_GATHER3ALTSIV8DF);
34019 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
34020 IX86_BUILTIN_GATHER3ALTDIV16SF);
34023 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
34024 IX86_BUILTIN_GATHER3ALTSIV8DI);
34027 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
34028 IX86_BUILTIN_GATHER3ALTDIV16SI);
34031 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
34032 IX86_BUILTIN_SCATTERSIV16SF);
34035 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
34036 IX86_BUILTIN_SCATTERSIV8DF);
34039 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
34040 IX86_BUILTIN_SCATTERDIV16SF);
34043 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
34044 IX86_BUILTIN_SCATTERDIV8DF);
34047 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
34048 IX86_BUILTIN_SCATTERSIV16SI);
34051 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
34052 IX86_BUILTIN_SCATTERSIV8DI);
34055 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
34056 IX86_BUILTIN_SCATTERDIV16SI);
34059 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
34060 IX86_BUILTIN_SCATTERDIV8DI);
34062 /* AVX512VL */
34064 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_QI_INT,
34065 IX86_BUILTIN_GATHER3SIV2DF);
34068 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_QI_INT,
34069 IX86_BUILTIN_GATHER3SIV4DF);
34072 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_QI_INT,
34073 IX86_BUILTIN_GATHER3DIV2DF);
34076 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_QI_INT,
34077 IX86_BUILTIN_GATHER3DIV4DF);
34080 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_QI_INT,
34081 IX86_BUILTIN_GATHER3SIV4SF);
34084 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_QI_INT,
34085 IX86_BUILTIN_GATHER3SIV8SF);
34088 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_QI_INT,
34089 IX86_BUILTIN_GATHER3DIV4SF);
34092 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_QI_INT,
34093 IX86_BUILTIN_GATHER3DIV8SF);
34096 V2DI_FTYPE_V2DI_PCINT64_V4SI_QI_INT,
34097 IX86_BUILTIN_GATHER3SIV2DI);
34100 V4DI_FTYPE_V4DI_PCINT64_V4SI_QI_INT,
34101 IX86_BUILTIN_GATHER3SIV4DI);
34104 V2DI_FTYPE_V2DI_PCINT64_V2DI_QI_INT,
34105 IX86_BUILTIN_GATHER3DIV2DI);
34108 V4DI_FTYPE_V4DI_PCINT64_V4DI_QI_INT,
34109 IX86_BUILTIN_GATHER3DIV4DI);
34112 V4SI_FTYPE_V4SI_PCINT_V4SI_QI_INT,
34113 IX86_BUILTIN_GATHER3SIV4SI);
34116 V8SI_FTYPE_V8SI_PCINT_V8SI_QI_INT,
34117 IX86_BUILTIN_GATHER3SIV8SI);
34120 V4SI_FTYPE_V4SI_PCINT_V2DI_QI_INT,
34121 IX86_BUILTIN_GATHER3DIV4SI);
34124 V4SI_FTYPE_V4SI_PCINT_V4DI_QI_INT,
34125 IX86_BUILTIN_GATHER3DIV8SI);
34128 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
34129 IX86_BUILTIN_GATHER3ALTSIV4DF);
34132 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
34133 IX86_BUILTIN_GATHER3ALTDIV8SF);
34136 V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
34137 IX86_BUILTIN_GATHER3ALTSIV4DI);
34140 V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
34141 IX86_BUILTIN_GATHER3ALTDIV8SI);
34144 VOID_FTYPE_PFLOAT_QI_V8SI_V8SF_INT,
34145 IX86_BUILTIN_SCATTERSIV8SF);
34148 VOID_FTYPE_PFLOAT_QI_V4SI_V4SF_INT,
34149 IX86_BUILTIN_SCATTERSIV4SF);
34152 VOID_FTYPE_PDOUBLE_QI_V4SI_V4DF_INT,
34153 IX86_BUILTIN_SCATTERSIV4DF);
34156 VOID_FTYPE_PDOUBLE_QI_V4SI_V2DF_INT,
34157 IX86_BUILTIN_SCATTERSIV2DF);
34160 VOID_FTYPE_PFLOAT_QI_V4DI_V4SF_INT,
34161 IX86_BUILTIN_SCATTERDIV8SF);
34164 VOID_FTYPE_PFLOAT_QI_V2DI_V4SF_INT,
34165 IX86_BUILTIN_SCATTERDIV4SF);
34168 VOID_FTYPE_PDOUBLE_QI_V4DI_V4DF_INT,
34169 IX86_BUILTIN_SCATTERDIV4DF);
34172 VOID_FTYPE_PDOUBLE_QI_V2DI_V2DF_INT,
34173 IX86_BUILTIN_SCATTERDIV2DF);
34176 VOID_FTYPE_PINT_QI_V8SI_V8SI_INT,
34177 IX86_BUILTIN_SCATTERSIV8SI);
34180 VOID_FTYPE_PINT_QI_V4SI_V4SI_INT,
34181 IX86_BUILTIN_SCATTERSIV4SI);
34184 VOID_FTYPE_PLONGLONG_QI_V4SI_V4DI_INT,
34185 IX86_BUILTIN_SCATTERSIV4DI);
34188 VOID_FTYPE_PLONGLONG_QI_V4SI_V2DI_INT,
34189 IX86_BUILTIN_SCATTERSIV2DI);
34192 VOID_FTYPE_PINT_QI_V4DI_V4SI_INT,
34193 IX86_BUILTIN_SCATTERDIV8SI);
34196 VOID_FTYPE_PINT_QI_V2DI_V4SI_INT,
34197 IX86_BUILTIN_SCATTERDIV4SI);
34200 VOID_FTYPE_PLONGLONG_QI_V4DI_V4DI_INT,
34201 IX86_BUILTIN_SCATTERDIV4DI);
34204 VOID_FTYPE_PLONGLONG_QI_V2DI_V2DI_INT,
34205 IX86_BUILTIN_SCATTERDIV2DI);
34207 /* AVX512PF */
34209 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
34210 IX86_BUILTIN_GATHERPFDPD);
34212 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
34213 IX86_BUILTIN_GATHERPFDPS);
34215 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
34216 IX86_BUILTIN_GATHERPFQPD);
34218 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
34219 IX86_BUILTIN_GATHERPFQPS);
34221 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
34222 IX86_BUILTIN_SCATTERPFDPD);
34224 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
34225 IX86_BUILTIN_SCATTERPFDPS);
34227 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
34228 IX86_BUILTIN_SCATTERPFQPD);
34230 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
34231 IX86_BUILTIN_SCATTERPFQPS);
34233 /* SHA */
34249 /* RTM. */
34253 /* MMX access to the vec_init patterns. */
34258 V4HI_FTYPE_HI_HI_HI_HI,
34259 IX86_BUILTIN_VEC_INIT_V4HI);
34262 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
34263 IX86_BUILTIN_VEC_INIT_V8QI);
34265 /* Access to the vec_extract patterns. */
34287 /* Access to the vec_set patterns. */
34308 /* RDSEED */
34317 /* ADCX */
34322 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34323 IX86_BUILTIN_ADDCARRYX64);
34325 /* SBB */
34330 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34331 IX86_BUILTIN_SBB64);
34333 /* Read/write FLAGS. */
34343 /* CLFLUSHOPT. */
34347 /* CLWB. */
34351 /* MONITORX and MWAITX. */
34357 /* Add FMA4 multi-arg argument instructions */
34359 {
34365 }
34366 }
34368 static void
34370 {
34373 tree decl;
34379 {
34386 /* With no leaf and nothrow flags for MPX builtins
34387 abnormal edges may follow its call when setjmp
34388 presents in the function. Since we may have a lot
34389 of MPX builtins calls it causes lots of useless
34390 edges and enormous PHI nodes. To avoid this we mark
34391 MPX builtins as leaf and nothrow. */
34393 {
34395 NULL_TREE);
34397 }
34398 else
34399 {
34402 }
34403 }
34408 {
34416 {
34418 NULL_TREE);
34420 }
34421 else
34422 {
34425 }
34426 }
34427 }
34429 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
34430 to return a pointer to VERSION_DECL if the outcome of the expression
34431 formed by PREDICATE_CHAIN is true. This function will be called during
34432 version dispatch to decide which function version to execute. It returns
34433 the basic block at the end, to which more conditions can be added. */
34435 static basic_block
34438 {
34439 gimple return_stmt;
34441 gimple convert_stmt;
34442 gimple call_cond_stmt;
34443 gimple if_else_stmt;
34449 gimple_seq gseq;
34466 {
34474 }
34477 {
34492 else
34493 {
34494 gimple assign_stmt;
34495 /* Use MIN_EXPR to check if any integer is zero?.
34496 and_expr_var = min_expr <cond_var, and_expr_var> */
34504 }
34505 }
34508 integer_zero_node,
34538 }
34540 /* This parses the attribute arguments to target in DECL and determines
34541 the right builtin to use to match the platform specification.
34542 It returns the priority value for this version decl. If PREDICATE_LIST
34543 is not NULL, it stores the list of cpu features that need to be checked
34544 before dispatching this function. */
34546 static unsigned int
34548 {
34549 tree attrs;
34551 tree target_node;
34558 /* Priority of i386 features, greater value is higher priority. This is
34559 used to decide the order in which function dispatch must happen. For
34560 instance, a version specialized for SSE4.2 should be checked for dispatch
34561 before a version for SSE3, as SSE4.2 implies SSE3. */
34562 enum feature_priority
34563 {
34565 P_MMX,
34566 P_SSE,
34567 P_SSE2,
34568 P_SSE3,
34569 P_SSSE3,
34570 P_PROC_SSSE3,
34571 P_SSE4_A,
34572 P_PROC_SSE4_A,
34573 P_SSE4_1,
34574 P_SSE4_2,
34575 P_PROC_SSE4_2,
34576 P_POPCNT,
34577 P_AES,
34578 P_AVX,
34579 P_PROC_AVX,
34580 P_BMI,
34581 P_PROC_BMI,
34582 P_FMA4,
34583 P_XOP,
34584 P_PROC_XOP,
34585 P_FMA,
34586 P_PROC_FMA,
34587 P_BMI2,
34588 P_AVX2,
34589 P_PROC_AVX2,
34590 P_AVX512F,
34591 P_PROC_AVX512F
34592 };
34596 /* These are the target attribute strings for which a dispatcher is
34597 available, from fold_builtin_cpu. */
34599 static struct _feature_list
34600 {
34603 }
34605 {
34624 };
34627 static unsigned int NUM_FEATURES
34643 /* Return priority zero for default function. */
34647 /* Handle arch= if specified. For priority, set it to be 1 more than
34648 the best instruction set the processor can handle. For instance, if
34649 there is a version for atom and a version for ssse3 (the highest ISA
34650 priority for atom), the atom version must be checked for dispatch
34651 before the ssse3 version. */
34653 {
34663 {
34665 {
34673 else
34674 /* We translate "arch=corei7" and "arch=nehalem" to
34675 "corei7" so that it will be mapped to M_INTEL_COREI7
34676 as cpu type to cover all M_INTEL_COREI7_XXXs. */
34683 else
34690 else
34734 }
34735 }
34740 {
34744 }
34747 {
34749 /* For a C string literal the length includes the trailing NULL. */
34752 predicate_chain);
34753 }
34754 }
34756 /* Process feature name. */
34763 {
34764 /* Do not process "arch=" */
34766 {
34769 }
34771 {
34773 {
34775 {
34780 predicate_chain);
34781 }
34782 /* Find the maximum priority feature. */
34787 }
34788 }
34790 {
34794 }
34796 }
34800 {
34803 attrs_str);
34805 }
34807 {
34810 }
34813 }
34815 /* This compares the priority of target features in function DECL1
34816 and DECL2. It returns positive value if DECL1 is higher priority,
34817 negative value if DECL2 is higher priority and 0 if they are the
34818 same. */
34820 static int
34822 {
34827 }
34829 /* V1 and V2 point to function versions with different priorities
34830 based on the target ISA. This function compares their priorities. */
34832 static int
34834 {
34836 {
34837 tree version_decl;
34838 tree predicate_chain;
34845 }
34847 /* This function generates the dispatch function for
34848 multi-versioned functions. DISPATCH_DECL is the function which will
34849 contain the dispatch logic. FNDECLS are the function choices for
34850 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
34851 in DISPATCH_DECL in which the dispatch code is generated. */
34853 static int
34857 {
34858 tree default_decl;
34859 gimple ifunc_cpu_init_stmt;
34860 gimple_seq gseq;
34862 tree ele;
34868 struct _function_version_info
34869 {
34870 tree version_decl;
34871 tree predicate_chain;
34879 /*fndecls_p is actually a vector. */
34882 /* At least one more version other than the default. */
34889 /* The first version in the vector is the default decl. */
34895 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
34896 constructors, so explicity call __builtin_cpu_init here. */
34907 {
34911 /* Get attribute string, parse it and find the right predicate decl.
34912 The predicate function could be a lengthy combination of many
34913 features, like arch-type and various isa-variants. */
34924 actual_versions++;
34925 }
34927 /* Sort the versions according to descending order of dispatch priority. The
34928 priority is based on the ISA. This is not a perfect solution. There
34929 could still be ambiguity. If more than one function version is suitable
34930 to execute, which one should be dispatched? In future, allow the user
34931 to specify a dispatch priority next to the version. */
34941 /* dispatch default version at the end. */
34947 }
34949 /* Comparator function to be used in qsort routine to sort attribute
34950 specification strings to "target". */
34952 static int
34954 {
34958 }
34960 /* ARGLIST is the argument to target attribute. This function tokenizes
34961 the comma separated arguments, sorts them and returns a string which
34962 is a unique identifier for the comma separated arguments. It also
34963 replaces non-identifier characters "=,-" with "_". */
34967 {
34968 tree arg;
34977 {
34982 argnum++;
34985 argnum++;
34986 }
34991 {
34997 }
34999 /* Replace "=,-" with "_". */
35012 {
35014 i++;
35016 }
35023 {
35028 }
35033 }
35035 /* This function changes the assembler name for functions that are
35036 versions. If DECL is a function version and has a "target"
35037 attribute, it appends the attribute string to its assembler name. */
35039 static tree
35041 {
35042 tree version_attr;
35050 "Function versions cannot be marked as gnu_inline,"
35059 /* target attribute string cannot be NULL. */
35063 version_string
35074 /* Allow assembler name to be modified if already set. */
35082 }
35084 /* This function returns true if FN1 and FN2 are versions of the same function,
35085 that is, the target strings of the function decls are different. This assumes
35086 that FN1 and FN2 have the same signature. */
35088 static bool
35090 {
35102 /* At least one function decl should have the target attribute specified. */
35106 /* Diagnose missing target attribute if one of the decls is already
35107 multi-versioned. */
35109 {
35111 {
35113 {
35116 }
35119 fn2);
35122 /* Prevent diagnosing of the same error multiple times. */
35127 }
35129 }
35134 /* The sorted target strings must be different for fn1 and fn2
35135 to be versions. */
35138 else
35145 }
35147 static tree
35149 {
35150 /* For function version, add the target suffix to the assembler name. */
35154 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
35156 #endif
35159 }
35161 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
35162 is true, append the full path name of the source file. */
35166 {
35174 /* Get a unique name that can be used globally without any chances
35175 of collision at link time. */
35185 /* Use '.' to concatenate names as it is demangler friendly. */
35188 suffix);
35189 else
35193 }
35195 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
35197 /* Make a dispatcher declaration for the multi-versioned function DECL.
35198 Calls to DECL function will be replaced with calls to the dispatcher
35199 by the front-end. Return the decl created. */
35201 static tree
35203 {
35204 tree func_decl;
35224 /* Mark this func as external, the resolver will flip it again if
35225 it gets generated. */
35227 /* This will be of type IFUNCs have to be externally visible. */
35231 }
35233 #endif
35235 /* Returns true if decl is multi-versioned and DECL is the default function,
35236 that is it is not tagged with target specific optimization. */
35238 static bool
35240 {
35249 }
35251 /* Make a dispatcher declaration for the multi-versioned function DECL.
35252 Calls to DECL function will be replaced with calls to the dispatcher
35253 by the front-end. Returns the decl of the dispatcher function. */
35255 static tree
35257 {
35279 /* Find the default version and make it the first node. */
35281 /* Go to the beginning of the chain. */
35286 {
35291 }
35293 /* If there is no default node, just return NULL. */
35297 /* Make default info the first node. */
35299 {
35306 }
35310 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
35312 {
35317 /* Right now, the dispatching is done via ifunc. */
35323 dispatcher_version_info
35328 /* Set the dispatcher for all the versions. */
35331 {
35334 }
35335 }
35336 else
35337 #endif
35338 {
35340 "multiversioning needs ifunc which is not supported "
35342 }
35345 }
35347 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
35348 it to CHAIN. */
35350 static tree
35352 {
35353 tree attr_name;
35354 tree attr_arg_name;
35355 tree attr_args;
35356 tree attr;
35363 }
35365 /* Make the resolver function decl to dispatch the versions of
35366 a multi-versioned function, DEFAULT_DECL. Create an
35367 empty basic block in the resolver and store the pointer in
35368 EMPTY_BB. Return the decl of the resolver function. */
35370 static tree
35374 {
35379 /* IFUNC's have to be globally visible. So, if the default_decl is
35380 not, then the name of the IFUNC should be made unique. */
35384 /* Append the filename to the resolver function if the versions are
35385 not externally visible. This is because the resolver function has
35386 to be externally visible for the loader to find it. So, appending
35387 the filename will prevent conflicts with a resolver function from
35388 another module which is based on the same version name. */
35391 /* The resolver function should return a (void *). */
35402 /* IFUNC resolvers have to be externally visible. */
35406 /* Resolver is not external, body is generated. */
35416 {
35417 /* In this case, each translation unit with a call to this
35418 versioned function will put out a resolver. Ensure it
35419 is comdat to keep just one copy. */
35422 }
35423 /* Build result decl and add to function_decl. */
35439 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
35443 /* Create the alias for dispatch to resolver here. */
35444 /*cgraph_create_function_alias (dispatch_decl, decl);*/
35448 }
35450 /* Generate the dispatching code body to dispatch multi-versioned function
35451 DECL. The target hook is called to process the "target" attributes and
35452 provide the code to dispatch the right function at run-time. NODE points
35453 to the dispatcher decl whose body will be created. */
35455 static tree
35457 {
35458 tree resolver_decl;
35459 basic_block empty_bb;
35460 tree default_ver_decl;
35476 /* The first version in the chain corresponds to the default version. */
35479 /* node is going to be an alias, so remove the finalized bit. */
35493 {
35495 /* Check for virtual functions here again, as by this time it should
35496 have been determined if this function needs a vtable index or
35497 not. This happens for methods in derived classes that override
35498 virtual methods in base classes but are not explicitly marked as
35499 virtual. */
35504 }
35510 }
35511 /* This builds the processor_model struct type defined in
35512 libgcc/config/i386/cpuinfo.c */
35514 static tree
35516 {
35523 /* The first 3 fields are unsigned int. */
35525 {
35531 }
35533 /* The last field is an array of unsigned integers of size one. */
35544 }
35546 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
35548 static tree
35550 {
35551 tree new_decl;
35554 VAR_DECL,
35556 type);
35569 }
35571 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
35572 into an integer defined in libgcc/config/i386/cpuinfo.c */
35574 static tree
35576 {
35582 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
35583 enum processor_features
35584 {
35586 F_MMX,
35587 F_POPCNT,
35588 F_SSE,
35589 F_SSE2,
35590 F_SSE3,
35591 F_SSSE3,
35592 F_SSE4_1,
35593 F_SSE4_2,
35594 F_AVX,
35595 F_AVX2,
35596 F_SSE4_A,
35597 F_FMA4,
35598 F_XOP,
35599 F_FMA,
35600 F_AVX512F,
35601 F_BMI,
35602 F_BMI2,
35603 F_AES,
35604 F_MAX
35605 };
35607 /* These are the values for vendor types and cpu types and subtypes
35608 in cpuinfo.c. Cpu types and subtypes should be subtracted by
35609 the corresponding start value. */
35610 enum processor_model
35611 {
35613 M_AMD,
35614 M_CPU_TYPE_START,
35615 M_INTEL_BONNELL,
35616 M_INTEL_CORE2,
35617 M_INTEL_COREI7,
35618 M_AMDFAM10H,
35619 M_AMDFAM15H,
35620 M_INTEL_SILVERMONT,
35621 M_INTEL_KNL,
35622 M_AMD_BTVER1,
35623 M_AMD_BTVER2,
35624 M_CPU_SUBTYPE_START,
35625 M_INTEL_COREI7_NEHALEM,
35626 M_INTEL_COREI7_WESTMERE,
35627 M_INTEL_COREI7_SANDYBRIDGE,
35628 M_AMDFAM10H_BARCELONA,
35629 M_AMDFAM10H_SHANGHAI,
35630 M_AMDFAM10H_ISTANBUL,
35631 M_AMDFAM15H_BDVER1,
35632 M_AMDFAM15H_BDVER2,
35633 M_AMDFAM15H_BDVER3,
35634 M_AMDFAM15H_BDVER4,
35635 M_INTEL_COREI7_IVYBRIDGE,
35636 M_INTEL_COREI7_HASWELL,
35637 M_INTEL_COREI7_BROADWELL
35638 };
35640 static struct _arch_names_table
35641 {
35644 }
35646 {
35673 };
35675 static struct _isa_names_table
35676 {
35679 }
35681 {
35701 };
35715 {
35716 /* *args must be a expr that can contain other EXPRS leading to a
35717 STRING_CST. */
35719 {
35722 }
35724 }
35729 {
35730 tree ref;
35731 tree field;
35732 tree final;
35735 unsigned int NUM_ARCH_NAMES
35744 {
35748 }
35753 /* CPU types are stored in the next field. */
35756 {
35759 }
35761 /* CPU subtypes are stored in the next field. */
35763 {
35766 }
35768 /* Get the appropriate field in __cpu_model. */
35772 /* Check the value. */
35776 }
35778 {
35779 tree ref;
35780 tree array_elt;
35781 tree field;
35782 tree final;
35785 unsigned int NUM_ISA_NAMES
35794 {
35798 }
35801 /* Get the last field, which is __cpu_features. */
35805 /* Get the appropriate field: __cpu_model.__cpu_features */
35809 /* Access the 0th element of __cpu_features array. */
35814 /* Return __cpu_model.__cpu_features[0] & field_val */
35818 }
35820 }
35822 static tree
35825 {
35827 {
35832 {
35835 }
35836 }
35838 #ifdef SUBTARGET_FOLD_BUILTIN
35840 #endif
35843 }
35845 /* Make builtins to detect cpu type and features supported. NAME is
35846 the builtin name, CODE is the builtin code, and FTYPE is the function
35847 type of the builtin. */
35849 static void
35852 {
35853 tree decl;
35854 tree type;
35862 }
35864 /* Make builtins to get CPU type and features supported. The created
35865 builtins are :
35867 __builtin_cpu_init (), to detect cpu type and features,
35868 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
35869 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
35870 */
35872 static void
35874 {
35881 }
35883 /* Internal method for ix86_init_builtins. */
35885 static void
35887 {
35899 sysv_va_ref =
35902 fnvoid_va_end_ms =
35904 fnvoid_va_start_ms =
35906 fnvoid_va_end_sysv =
35908 fnvoid_va_start_sysv =
35910 NULL_TREE);
35911 fnvoid_va_copy_ms =
35913 NULL_TREE);
35914 fnvoid_va_copy_sysv =
35930 }
35932 static void
35934 {
35937 /* The __float80 type. */
35940 {
35941 /* The __float80 type. */
35946 }
35949 /* The __float128 type. */
35955 /* This macro is built by i386-builtin-types.awk. */
35956 DEFINE_BUILTIN_PRIMITIVE_TYPES;
35957 }
35959 static void
35961 {
35962 tree t;
35966 /* Builtins to get CPU type and features. */
35969 /* TFmode support builtins. */
35975 /* We will expand them to normal call if SSE isn't available since
35976 they are used by libgcc. */
35996 #ifdef SUBTARGET_INIT_BUILTINS
35997 SUBTARGET_INIT_BUILTINS;
35998 #endif
35999 }
36001 /* Return the ix86 builtin for CODE. */
36003 static tree
36005 {
36010 }
36012 /* Errors in the source file can cause expand_expr to return const0_rtx
36013 where we expect a vector. To avoid crashing, use one of the vector
36014 clear instructions. */
36015 static rtx
36017 {
36021 }
36023 /* Fixup modeless constants to fit required mode. */
36024 static rtx
36026 {
36030 }
36032 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
36034 static rtx
36036 {
36037 rtx pat;
36057 {
36061 }
36075 }
36077 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
36079 static rtx
36083 {
36084 rtx pat;
36092 rtx op;
36093 machine_mode mode;
36099 {
36179 }
36189 {
36196 {
36198 {
36201 {
36219 xop_rotl:
36221 {
36224 gcc_checking_assert
36226 }
36227 else
36228 {
36229 gcc_checking_assert
36240 }
36244 }
36245 }
36246 }
36247 else
36248 {
36249 non_constant:
36253 /* If we aren't optimizing, only allow one memory operand to be
36254 generated. */
36256 num_memory++;
36264 }
36268 }
36271 {
36282 else
36283 {
36289 }
36302 }
36309 }
36311 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
36312 insns with vec_merge. */
36314 static rtx
36316 rtx target)
36317 {
36318 rtx pat;
36345 }
36347 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
36349 static rtx
36352 {
36353 rtx pat;
36358 rtx op2;
36369 /* Swap operands if we have a comparison that isn't available in
36370 hardware. */
36392 }
36394 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
36396 static rtx
36398 rtx target)
36399 {
36400 rtx pat;
36414 /* Swap operands if we have a comparison that isn't available in
36415 hardware. */
36437 const0_rtx)));
36440 }
36442 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
36444 static rtx
36446 rtx target)
36447 {
36448 rtx pat;
36473 }
36475 static rtx
36478 {
36479 rtx pat;
36484 rtx op2;
36511 }
36513 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
36515 static rtx
36517 rtx target)
36518 {
36519 rtx pat;
36551 const0_rtx)));
36554 }
36556 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
36558 static rtx
36561 {
36562 rtx pat;
36600 {
36603 }
36606 {
36615 }
36617 {
36626 }
36627 else
36628 {
36635 }
36643 {
36648 emit_insn
36652 FLAGS_REG),
36653 const0_rtx)));
36655 }
36656 else
36658 }
36661 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
36663 static rtx
36666 {
36667 rtx pat;
36695 {
36698 }
36701 {
36710 }
36712 {
36721 }
36722 else
36723 {
36730 }
36738 {
36743 emit_insn
36747 FLAGS_REG),
36748 const0_rtx)));
36750 }
36751 else
36753 }
36755 /* Subroutine of ix86_expand_builtin to take care of insns with
36756 variable number of operands. */
36758 static rtx
36761 {
36767 struct
36768 {
36769 rtx op;
36770 machine_mode mode;
36781 {
37491 }
37496 {
37499 }
37502 {
37509 }
37510 else
37511 {
37514 }
37517 {
37524 {
37525 /* SIMD shift insns take either an 8-bit immediate or
37526 register as count. But builtin functions take int as
37527 count. If count doesn't match, we put it in register. */
37529 {
37533 }
37534 }
37537 {
37540 {
37649 {
37653 {
37656 }
37662 }
37664 }
37665 }
37666 else
37667 {
37671 /* If we aren't optimizing, only allow one memory operand to
37672 be generated. */
37674 num_memory++;
37679 {
37682 }
37683 else
37684 {
37687 }
37688 }
37692 }
37695 {
37720 }
37727 }
37729 /* Transform pattern of following layout:
37730 (parallel [
37731 set (A B)
37732 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
37733 ])
37734 into:
37735 (set (A B))
37737 Or:
37738 (parallel [ A B
37739 ...
37740 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
37741 ...
37742 ])
37743 into:
37744 (parallel [ A B ... ]) */
37746 static rtx
37748 {
37755 {
37764 }
37765 else
37766 {
37772 {
37777 }
37779 /* No more than 1 occurence was removed. */
37783 }
37784 }
37786 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
37787 with rounding. */
37788 static rtx
37791 {
37808 /* See avxintrin.h for values. */
37810 {
37814 };
37816 {
37821 };
37824 {
37827 }
37829 {
37832 }
37835 {
37838 }
37861 ? CODE_FOR_sse_ucomi_round
37868 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
37870 {
37876 }
37877 else
37878 {
37881 }
37886 set_dst,
37887 const0_rtx)));
37890 }
37892 static rtx
37895 {
37896 rtx pat;
37898 struct
37899 {
37900 rtx op;
37901 machine_mode mode;
37910 {
37993 }
38003 {
38010 {
38012 {
38014 {
38030 }
38031 }
38032 }
38034 {
38036 {
38039 }
38041 /* If there is no rounding use normal version of the pattern. */
38044 }
38045 else
38046 {
38053 {
38056 }
38057 else
38058 {
38061 }
38062 }
38066 }
38069 {
38094 }
38104 }
38106 /* Subroutine of ix86_expand_builtin to take care of special insns
38107 with variable number of operands. */
38109 static rtx
38112 {
38113 tree arg;
38117 struct
38118 {
38119 rtx op;
38120 machine_mode mode;
38129 {
38169 {
38177 }
38196 /* Reserve memory operand for target. */
38199 {
38200 /* These builtins and instructions require the memory
38201 to be properly aligned. */
38220 }
38249 {
38250 /* These builtins and instructions require the memory
38251 to be properly aligned. */
38268 }
38269 /* FALLTHRU */
38307 /* Reserve memory operand for target. */
38334 {
38335 /* These builtins and instructions require the memory
38336 to be properly aligned. */
38359 }
38372 }
38377 {
38382 {
38385 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
38386 on it. Try to improve it using get_pointer_alignment,
38387 and if the special builtin is one that requires strict
38388 mode alignment, also from it's GET_MODE_ALIGNMENT.
38389 Failure to do so could lead to ix86_legitimate_combined_insn
38390 rejecting all changes to such insns. */
38396 }
38397 else
38400 }
38401 else
38402 {
38409 }
38412 {
38421 {
38423 {
38429 else
38432 }
38433 }
38434 else
38435 {
38437 {
38438 /* This must be the memory operand. */
38441 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
38442 on it. Try to improve it using get_pointer_alignment,
38443 and if the special builtin is one that requires strict
38444 mode alignment, also from it's GET_MODE_ALIGNMENT.
38445 Failure to do so could lead to ix86_legitimate_combined_insn
38446 rejecting all changes to such insns. */
38452 }
38453 else
38454 {
38455 /* This must be register. */
38463 else
38464 {
38467 }
38468 }
38469 }
38473 }
38476 {
38491 }
38497 }
38499 /* Return the integer constant in ARG. Constrain it to be in the range
38500 of the subparts of VEC_TYPE; issue an error if not. */
38502 static int
38504 {
38509 {
38512 }
38515 }
38517 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38518 ix86_expand_vector_init. We DO have language-level syntax for this, in
38519 the form of (type){ init-list }. Except that since we can't place emms
38520 instructions from inside the compiler, we can't allow the use of MMX
38521 registers unless the user explicitly asks for it. So we do *not* define
38522 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
38523 we have builtins invoked by mmintrin.h that gives us license to emit
38524 these sorts of instructions. */
38526 static rtx
38528 {
38538 {
38541 }
38548 }
38550 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38551 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
38552 had a language-level syntax for referencing vector elements. */
38554 static rtx
38556 {
38560 rtx op0;
38580 }
38582 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38583 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
38584 a language-level syntax for referencing vector elements. */
38586 static rtx
38588 {
38612 /* OP0 is the source of these builtin functions and shouldn't be
38613 modified. Create a copy, use it and return it as target. */
38619 }
38621 /* Emit conditional move of SRC to DST with condition
38622 OP1 CODE OP2. */
38623 static void
38625 {
38626 rtx t;
38629 {
38633 }
38634 else
38635 {
38641 }
38642 }
38644 /* Choose max of DST and SRC and put it to DST. */
38645 static void
38647 {
38649 }
38651 /* Expand an expression EXP that calls a built-in function,
38652 with result going to TARGET if that's convenient
38653 (and in mode MODE if that's convenient).
38654 SUBTARGET may be used as the target for computing one of EXP's operands.
38655 IGNORE is nonzero if the value is to be ignored. */
38657 static rtx
38660 {
38670 /* For CPU builtins that can be folded, fold first and expand the fold. */
38672 {
38674 {
38675 /* Make it call __cpu_indicator_init in libgcc. */
38681 }
38684 {
38689 }
38690 }
38692 /* Determine whether the builtin function is available under the current ISA.
38693 Originally the builtin was not created if it wasn't applicable to the
38694 current ISA based on the command line switches. With function specific
38695 options, we need to check in the context of the function making the call
38696 whether it is supported. */
38699 {
38705 else
38706 {
38710 }
38712 }
38715 {
38733 /* Builtin arg1 is size of block but instruction op1 should
38734 be (size - 1). */
38825 /* If no bounds were specified for returned value,
38826 then use INIT bounds. It usually happens when
38827 some built-in function is expanded. */
38829 {
38838 }
38844 {
38847 /* Return value and lb. */
38849 /* Bounds. */
38851 /* Size. */
38858 /* Size was passed but we need to use (size - 1) as for bndmk. */
38862 /* Add LB to size and inverse to get UB. */
38872 /* We need to move bounds to memory before any computations. */
38875 else
38876 {
38879 }
38881 /* Generate mem expression to be used for access to LB and UB. */
38887 /* Compute LB. */
38892 /* Compute UB. UB is stored in 1's complement form. Therefore
38893 we also use max here. */
38902 }
38905 {
38923 /* Put first bounds to temporaries. */
38927 {
38931 }
38932 else
38933 {
38937 }
38939 /* Put second bounds to temporaries. */
38943 {
38947 }
38948 else
38949 {
38953 }
38955 /* Compute LB. */
38959 /* Compute UB. UB is stored in 1's complement form. Therefore
38960 we also use max here. */
38967 }
38970 {
38971 tree name;
38972 rtx symbol;
38990 }
38993 {
39004 /* We need to move bounds to memory first. */
39007 else
39008 {
39011 }
39013 /* Generate mem expression to access LB and load it. */
39018 }
39021 {
39032 /* We need to move bounds to memory first. */
39035 else
39036 {
39039 }
39041 /* Generate mem expression to access UB. */
39044 /* We need to inverse all bits of UB. */
39051 }
39056 ? CODE_FOR_mmx_maskmovq
39058 /* Note the arg order is different from the operand order. */
39199 {
39200 REAL_VALUE_TYPE inf;
39201 rtx tmp;
39213 }
39223 {
39229 insn = (TARGET_64BIT
39233 }
39235 {
39236 insn = (TARGET_64BIT
39240 }
39241 else
39242 {
39245 insn = (TARGET_64BIT
39253 {
39256 }
39258 }
39261 {
39262 /* mode is VOIDmode if __builtin_rd* has been called
39263 without lhs. */
39267 }
39270 {
39275 }
39288 {
39309 }
39315 {
39318 }
39344 {
39347 }
39353 {
39357 {
39396 }
39401 }
39402 else
39403 {
39405 {
39426 }
39428 }
39458 ? CODE_FOR_tbm_bextri_si
39461 {
39464 }
39465 else
39466 {
39475 }
39491 rdrand_step:
39498 {
39501 }
39507 /* Emit SImode conditional move. */
39509 {
39512 }
39515 else
39523 const0_rtx);
39542 rdseed_step:
39549 {
39552 }
39558 const0_rtx);
39587 addcarryx:
39595 /* Generate CF from input operand. */
39600 /* Gen ADCX instruction to compute X+Y+CF. */
39615 /* Store the result. */
39618 {
39621 }
39624 /* Return current CF value. */
39666 kortest:
39680 /* Emit kortest. */
39682 /* And use setcc to return result from flags. */
39940 gather_gen:
39941 rtx half;
39954 /* Note the arg order is different from the operand order. */
39965 else
39969 {
39993 else
40000 {
40005 }
40014 else
40021 {
40026 }
40030 }
40032 /* Force memory operand only with base register here. But we
40033 don't want to do it on memory operand for other builtin
40034 functions. */
40047 {
40050 }
40051 else
40052 {
40055 }
40057 {
40060 }
40062 /* Optimize. If mask is known to have all high bits set,
40063 replace op0 with pc_rtx to signal that the instruction
40064 overwrites the whole destination and doesn't use its
40065 previous contents. */
40067 {
40069 {
40072 }
40074 {
40077 {
40081 negative++;
40084 negative++;
40085 }
40088 }
40091 {
40092 /* Recognize also when mask is like:
40093 __v2df src = _mm_setzero_pd ();
40094 __v2df mask = _mm_cmpeq_pd (src, src);
40095 or
40096 __v8sf src = _mm256_setzero_ps ();
40097 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
40098 as that is a cheaper way to load all ones into
40099 a register than having to load a constant from
40100 memory. */
40103 {
40108 {
40115 /* FALLTHRU */
40125 }
40126 }
40127 }
40128 }
40136 {
40162 }
40165 scatter_gen:
40181 /* Force memory operand only with base register here. But we
40182 don't want to do it on memory operand for other builtin
40183 functions. */
40192 {
40195 }
40196 else
40197 {
40200 }
40209 {
40212 }
40221 vec_prefetch_gen:
40241 {
40244 }
40246 {
40249 }
40254 /* Force memory operand only with base register here. But we
40255 don't want to do it on memory operand for other builtin
40256 functions. */
40263 {
40266 }
40269 {
40272 }
40288 {
40291 }
40297 }
40310 {
40314 /* Emit a normal call if SSE isn't available. */
40318 }
40347 }
40349 /* This returns the target-specific builtin with code CODE if
40350 current_function_decl has visibility on this builtin, which is checked
40351 using isa flags. Returns NULL_TREE otherwise. */
40354 {
40358 /* Determine the isa flags of current_function_decl. */
40370 else
40372 }
40374 /* Return function decl for target specific builtin
40375 for given MPX builtin passed i FCODE. */
40376 static tree
40378 {
40380 {
40416 }
40419 }
40421 /* Helper function for ix86_load_bounds and ix86_store_bounds.
40423 Return an address to be used to load/store bounds for pointer
40424 passed in SLOT.
40426 SLOT_NO is an integer constant holding number of a target
40427 dependent special slot to be used in case SLOT is not a memory.
40429 SPECIAL_BASE is a pointer to be used as a base of fake address
40430 to access special slots in Bounds Table. SPECIAL_BASE[-1],
40431 SPECIAL_BASE[-2] etc. will be used as fake pointer locations. */
40433 static rtx
40435 {
40438 /* NULL slot means we pass bounds for pointer not passed to the
40439 function at all. Register slot means we pass pointer in a
40440 register. In both these cases bounds are passed via Bounds
40441 Table. Since we do not have actual pointer stored in memory,
40442 we have to use fake addresses to access Bounds Table. We
40443 start with (special_base - sizeof (void*)) and decrease this
40444 address by pointer size to get addresses for other slots. */
40446 {
40450 }
40451 /* If pointer is passed in a memory then its address is used to
40452 access Bounds Table. */
40454 {
40458 }
40459 else
40463 }
40465 /* Expand pass uses this hook to load bounds for function parameter
40466 PTR passed in SLOT in case its bounds are not passed in a register.
40468 If SLOT is a memory, then bounds are loaded as for regular pointer
40469 loaded from memory. PTR may be NULL in case SLOT is a memory.
40470 In such case value of PTR (if required) may be loaded from SLOT.
40472 If SLOT is NULL or a register then SLOT_NO is an integer constant
40473 holding number of the target dependent special slot which should be
40474 used to obtain bounds.
40476 Return loaded bounds. */
40478 static rtx
40480 {
40482 rtx addr;
40484 /* Get address to be used to access Bounds Table. Special slots start
40485 at the location of return address of the current function. */
40488 /* Load pointer value from a memory if we don't have it. */
40490 {
40493 }
40503 }
40505 /* Expand pass uses this hook to store BOUNDS for call argument PTR
40506 passed in SLOT in case BOUNDS are not passed in a register.
40508 If SLOT is a memory, then BOUNDS are stored as for regular pointer
40509 stored in memory. PTR may be NULL in case SLOT is a memory.
40510 In such case value of PTR (if required) may be loaded from SLOT.
40512 If SLOT is NULL or a register then SLOT_NO is an integer constant
40513 holding number of the target dependent special slot which should be
40514 used to store BOUNDS. */
40516 static void
40518 {
40519 rtx addr;
40521 /* Get address to be used to access Bounds Table. Special slots start
40522 at the location of return address of a called function. */
40525 /* Load pointer value from a memory if we don't have it. */
40527 {
40530 }
40542 }
40544 /* Load and return bounds returned by function in SLOT. */
40546 static rtx
40548 {
40549 rtx res;
40556 }
40558 /* Store BOUNDS returned by function into SLOT. */
40560 static void
40562 {
40565 }
40567 /* Returns a function decl for a vectorized version of the builtin function
40568 with builtin function code FN and the result vector type TYPE, or NULL_TREE
40569 if it is not available. */
40571 static tree
40573 tree type_in)
40574 {
40590 {
40593 {
40600 }
40605 {
40608 }
40613 {
40620 }
40626 /* The round insn does not trap on denormals. */
40631 {
40638 }
40644 /* The round insn does not trap on denormals. */
40649 {
40654 }
40660 /* The round insn does not trap on denormals. */
40665 {
40672 }
40678 /* The round insn does not trap on denormals. */
40683 {
40688 }
40695 {
40700 }
40707 {
40712 }
40718 /* The round insn does not trap on denormals. */
40723 {
40730 }
40736 /* The round insn does not trap on denormals. */
40741 {
40746 }
40751 {
40758 }
40763 {
40770 }
40774 /* The round insn does not trap on denormals. */
40779 {
40784 }
40788 /* The round insn does not trap on denormals. */
40793 {
40798 }
40802 /* The round insn does not trap on denormals. */
40807 {
40812 }
40816 /* The round insn does not trap on denormals. */
40821 {
40826 }
40830 /* The round insn does not trap on denormals. */
40835 {
40840 }
40844 /* The round insn does not trap on denormals. */
40849 {
40854 }
40858 /* The round insn does not trap on denormals. */
40863 {
40868 }
40872 /* The round insn does not trap on denormals. */
40877 {
40882 }
40886 /* The round insn does not trap on denormals. */
40891 {
40896 }
40900 /* The round insn does not trap on denormals. */
40905 {
40910 }
40915 {
40920 }
40925 {
40930 }
40935 }
40937 /* Dispatch to a handler for a vectorization library. */
40940 type_in);
40943 }
40945 /* Handler for an SVML-style interface to
40946 a library with vectorized intrinsics. */
40948 static tree
40950 {
40958 /* The SVML is suitable for unsafe math only. */
40971 {
41018 }
41027 {
41030 }
41031 else
41034 /* Convert to uppercase. */
41039 args;
41041 arity++;
41045 else
41048 /* Build a function declaration for the vectorized function. */
41057 }
41059 /* Handler for an ACML-style interface to
41060 a library with vectorized intrinsics. */
41062 static tree
41064 {
41072 /* The ACML is 64bits only and suitable for unsafe math only as
41073 it does not correctly support parts of IEEE with the required
41074 precision such as denormals. */
41088 {
41118 }
41125 args;
41127 arity++;
41131 else
41134 /* Build a function declaration for the vectorized function. */
41143 }
41145 /* Returns a decl of a function that implements gather load with
41146 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
41147 Return NULL_TREE if it is not available. */
41149 static tree
41152 {
41168 /* v*gather* insn sign extends index to pointer mode. */
41180 {
41184 else
41190 else
41196 else
41202 else
41208 else
41214 else
41220 else
41226 else
41232 else
41238 else
41244 else
41250 else
41255 }
41258 }
41260 /* Returns a code for a target-specific builtin that implements
41261 reciprocal of the function, or NULL_TREE if not available. */
41263 static tree
41265 {
41272 /* Machine dependent builtins. */
41274 {
41275 /* Vectorized version of sqrt to rsqrt conversion. */
41284 }
41285 else
41286 /* Normal builtins. */
41288 {
41289 /* Sqrt to rsqrt conversion. */
41295 }
41296 }
41297 \f
41298 /* Helper for avx_vpermilps256_operand et al. This is also used by
41299 the expansion functions to turn the parallel back into a mask.
41300 The return value is 0 for no match and the imm8+1 for a match. */
41302 int
41304 {
41312 /* Validate that all of the elements are constants, and not totally
41313 out of range. Copy the data into an integral array to make the
41314 subsequent checks easier. */
41316 {
41326 }
41329 {
41331 /* In the 512-bit DFmode case, we can only move elements within
41332 a 128-bit lane. First fill the second part of the mask,
41333 then fallthru. */
41335 {
41339 }
41341 {
41345 }
41346 /* FALLTHRU */
41349 /* In the 256-bit DFmode case, we can only move elements within
41350 a 128-bit lane. */
41352 {
41356 }
41358 {
41362 }
41366 /* In 512 bit SFmode case, permutation in the upper 256 bits
41367 must mirror the permutation in the lower 256-bits. */
41371 /* FALLTHRU */
41374 /* In 256 bit SFmode case, we have full freedom of
41375 movement within the low 128-bit lane, but the high 128-bit
41376 lane must mirror the exact same pattern. */
41381 /* FALLTHRU */
41385 /* In the 128-bit case, we've full freedom in the placement of
41386 the elements from the source operand. */
41393 }
41395 /* Make sure success has a non-zero value by adding one. */
41397 }
41399 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
41400 the expansion functions to turn the parallel back into a mask.
41401 The return value is 0 for no match and the imm8+1 for a match. */
41403 int
41405 {
41413 /* Validate that all of the elements are constants, and not totally
41414 out of range. Copy the data into an integral array to make the
41415 subsequent checks easier. */
41417 {
41427 }
41429 /* Validate that the halves of the permute are halves. */
41437 /* Reconstruct the mask. */
41439 {
41445 }
41447 /* Make sure success has a non-zero value by adding one. */
41449 }
41450 \f
41451 /* Return a register priority for hard reg REGNO. */
41452 static int
41454 {
41455 /* ebp and r13 as the base always wants a displacement, r12 as the
41456 base always wants an index. So discourage their usage in an
41457 address. */
41462 /* New x86-64 int registers result in bigger code size. Discourage
41463 them. */
41466 /* New x86-64 SSE registers result in bigger code size. Discourage
41467 them. */
41470 /* Usage of AX register results in smaller code. Prefer it. */
41474 }
41476 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
41478 Put float CONST_DOUBLE in the constant pool instead of fp regs.
41479 QImode must go into class Q_REGS.
41480 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
41481 movdf to do mem-to-mem moves through integer regs. */
41483 static reg_class_t
41485 {
41488 /* We're only allowed to return a subclass of CLASS. Many of the
41489 following checks fail for NO_REGS, so eliminate that early. */
41493 /* All classes can load zeros. */
41497 /* Force constants into memory if we are loading a (nonzero) constant into
41498 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
41499 instructions to load from a constant. */
41506 /* Prefer SSE regs only, if we can use them for math. */
41510 /* Floating-point constants need more complex checks. */
41512 {
41513 /* General regs can load everything. */
41517 /* Floats can load 0 and 1 plus some others. Note that we eliminated
41518 zero above. We only want to wind up preferring 80387 registers if
41519 we plan on doing computation with them. */
41522 {
41523 /* Limit class to non-sse. */
41532 }
41535 }
41537 /* Generally when we see PLUS here, it's the function invariant
41538 (plus soft-fp const_int). Which can only be computed into general
41539 regs. */
41543 /* QImode constants are easy to load, but non-constant QImode data
41544 must go into Q_REGS. */
41546 {
41552 }
41555 }
41557 /* Discourage putting floating-point values in SSE registers unless
41558 SSE math is being used, and likewise for the 387 registers. */
41559 static reg_class_t
41561 {
41564 /* Restrict the output reload class to the register bank that we are doing
41565 math on. If we would like not to return a subset of CLASS, reject this
41566 alternative: if reload cannot do this, it will still use its choice. */
41572 {
41577 else
41579 }
41582 }
41584 static reg_class_t
41587 {
41588 /* Double-word spills from general registers to non-offsettable memory
41589 references (zero-extended addresses) require special handling. */
41595 {
41597 ? CODE_FOR_reload_noff_load
41599 /* Add the cost of moving address to a temporary. */
41603 }
41605 /* QImode spills from non-QI registers require
41606 intermediate register on 32bit targets. */
41612 {
41617 else
41623 /* Return Q_REGS if the operand is in memory. */
41626 }
41628 /* This condition handles corner case where an expression involving
41629 pointers gets vectorized. We're trying to use the address of a
41630 stack slot as a vector initializer.
41632 (set (reg:V2DI 74 [ vect_cst_.2 ])
41633 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
41635 Eventually frame gets turned into sp+offset like this:
41637 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41638 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41639 (const_int 392 [0x188]))))
41641 That later gets turned into:
41643 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41644 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41645 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
41647 We'll have the following reload recorded:
41649 Reload 0: reload_in (DI) =
41650 (plus:DI (reg/f:DI 7 sp)
41651 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
41652 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41653 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
41654 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
41655 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41656 reload_reg_rtx: (reg:V2DI 22 xmm1)
41658 Which isn't going to work since SSE instructions can't handle scalar
41659 additions. Returning GENERAL_REGS forces the addition into integer
41660 register and reload can handle subsequent reloads without problems. */
41668 }
41670 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
41672 static bool
41674 {
41676 {
41692 }
41695 }
41697 /* If we are copying between general and FP registers, we need a memory
41698 location. The same is true for SSE and MMX registers.
41700 To optimize register_move_cost performance, allow inline variant.
41702 The macro can't work reliably when one of the CLASSES is class containing
41703 registers from multiple units (SSE, MMX, integer). We avoid this by never
41704 combining those units in single alternative in the machine description.
41705 Ensure that this constraint holds to avoid unexpected surprises.
41707 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
41708 enforce these sanity checks. */
41713 {
41722 {
41725 }
41730 /* Between mask and general, we have moves no larger than word size. */
41735 /* ??? This is a lie. We do have moves between mmx/general, and for
41736 mmx/sse2. But by saying we need secondary memory we discourage the
41737 register allocator from using the mmx registers unless needed. */
41742 {
41743 /* SSE1 doesn't have any direct moves from other classes. */
41747 /* If the target says that inter-unit moves are more expensive
41748 than moving through memory, then don't generate them. */
41753 /* Between SSE and general, we have moves no larger than word size. */
41756 }
41759 }
41761 bool
41764 {
41766 }
41768 /* Implement the TARGET_CLASS_MAX_NREGS hook.
41770 On the 80386, this is the size of MODE in words,
41771 except in the FP regs, where a single reg is always enough. */
41773 static unsigned char
41775 {
41777 {
41782 else
41784 }
41785 else
41786 {
41789 else
41791 }
41792 }
41794 /* Return true if the registers in CLASS cannot represent the change from
41795 modes FROM to TO. */
41797 bool
41800 {
41804 /* x87 registers can't do subreg at all, as all values are reformatted
41805 to extended precision. */
41810 {
41811 /* Vector registers do not support QI or HImode loads. If we don't
41812 disallow a change to these modes, reload will assume it's ok to
41813 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
41814 the vec_dupv4hi pattern. */
41817 }
41820 }
41822 /* Return the cost of moving data of mode M between a
41823 register and memory. A value of 2 is the default; this cost is
41824 relative to those in `REGISTER_MOVE_COST'.
41826 This function is used extensively by register_move_cost that is used to
41827 build tables at startup. Make it inline in this case.
41828 When IN is 2, return maximum of in and out move cost.
41830 If moving between registers and memory is more expensive than
41831 between two registers, you should define this macro to express the
41832 relative cost.
41834 Model also increased moving costs of QImode registers in non
41835 Q_REGS classes.
41836 */
41840 {
41843 {
41846 {
41858 }
41862 }
41864 {
41867 {
41879 }
41883 }
41885 {
41888 {
41897 }
41901 }
41903 {
41906 {
41912 else
41917 }
41918 else
41919 {
41924 else
41926 }
41933 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
41940 else
41944 }
41945 }
41947 static int
41950 {
41952 }
41955 /* Return the cost of moving data from a register in class CLASS1 to
41956 one in class CLASS2.
41958 It is not required that the cost always equal 2 when FROM is the same as TO;
41959 on some machines it is expensive to move between registers if they are not
41960 general registers. */
41962 static int
41964 reg_class_t class2_i)
41965 {
41969 /* In case we require secondary memory, compute cost of the store followed
41970 by load. In order to avoid bad register allocation choices, we need
41971 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
41974 {
41980 /* In case of copying from general_purpose_register we may emit multiple
41981 stores followed by single load causing memory size mismatch stall.
41982 Count this as arbitrarily high cost of 20. */
41987 /* In the case of FP/MMX moves, the registers actually overlap, and we
41988 have to switch modes in order to treat them differently. */
41994 }
41996 /* Moves between SSE/MMX and integer unit are expensive. */
42000 /* ??? By keeping returned value relatively high, we limit the number
42001 of moves between integer and MMX/SSE registers for all targets.
42002 Additionally, high value prevents problem with x86_modes_tieable_p(),
42003 where integer modes in MMX/SSE registers are not tieable
42004 because of missing QImode and HImode moves to, from or between
42005 MMX/SSE registers. */
42015 }
42017 /* Return TRUE if hard register REGNO can hold a value of machine-mode
42018 MODE. */
42020 bool
42022 {
42023 /* Flags and only flags can only hold CCmode values. */
42034 || (TARGET_AVX512BW
42039 {
42040 /* We implement the move patterns for all vector modes into and
42041 out of SSE registers, even when no operation instructions
42042 are available. */
42044 /* For AVX-512 we allow, regardless of regno:
42045 - XI mode
42046 - any of 512-bit wide vector mode
42047 - any scalar mode. */
42054 /* TODO check for QI/HI scalars. */
42055 /* AVX512VL allows sse regs16+ for 128/256 bit modes. */
42063 /* xmm16-xmm31 are only available for AVX-512. */
42067 /* OImode and AVX modes are available only when AVX is enabled. */
42074 }
42076 {
42077 /* We implement the move patterns for 3DNOW modes even in MMX mode,
42078 so if the register is available at all, then we can move data of
42079 the given mode into or out of it. */
42082 }
42085 {
42086 /* Take care for QImode values - they can be in non-QI regs,
42087 but then they do cause partial register stalls. */
42092 /* LRA checks if the hard register is OK for the given mode.
42093 QImode values can live in non-QI regs, so we allow all
42094 registers here. */
42098 }
42099 /* We handle both integer and floats in the general purpose registers. */
42106 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
42107 on to use that value in smaller contexts, this can easily force a
42108 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
42109 supporting DImode, allow it. */
42114 }
42116 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
42117 tieable integer mode. */
42119 static bool
42121 {
42123 {
42136 }
42137 }
42139 /* Return true if MODE1 is accessible in a register that can hold MODE2
42140 without copying. That is, all register classes that can hold MODE2
42141 can also hold MODE1. */
42143 bool
42145 {
42153 /* MODE2 being XFmode implies fp stack or general regs, which means we
42154 can tie any smaller floating point modes to it. Note that we do not
42155 tie this with TFmode. */
42159 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
42160 that we can tie it with SFmode. */
42164 /* If MODE2 is only appropriate for an SSE register, then tie with
42165 any other mode acceptable to SSE registers. */
42175 /* If MODE2 is appropriate for an MMX register, then tie
42176 with any other mode acceptable to MMX registers. */
42183 }
42185 /* Return the cost of moving between two registers of mode MODE. */
42187 static int
42189 {
42193 {
42225 }
42227 /* Return the cost of moving between two registers of mode MODE,
42228 assuming that the move will be in pieces of at most UNITS bytes. */
42230 }
42232 /* Compute a (partial) cost for rtx X. Return true if the complete
42233 cost has been computed, and false if subexpressions should be
42234 scanned. In either case, *TOTAL contains the cost result. */
42236 static bool
42239 {
42240 rtx mask;
42246 {
42250 {
42253 }
42265 && !(TARGET_64BIT
42269 /* Use 0 cost for CONST to improve its propagation. */
42272 else
42282 {
42292 }
42294 {
42297 {
42306 }
42307 }
42308 /* Fall back to (MEM (SYMBOL_REF)), since that's where
42309 it'll probably end up. Add a penalty for size. */
42316 /* The zero extensions is often completely free on x86_64, so make
42317 it as cheap as possible. */
42323 else
42335 {
42338 {
42341 }
42344 {
42347 }
42348 }
42349 /* FALLTHRU */
42356 {
42357 /* ??? Should be SSE vector operation cost. */
42358 /* At least for published AMD latencies, this really is the same
42359 as the latency for a simple fpu operation like fabs. */
42360 /* V*QImode is emulated with 1-11 insns. */
42362 {
42365 {
42366 /* For XOP we use vpshab, which requires a broadcast of the
42367 value to the variable shift insn. For constants this
42368 means a V16Q const in mem; even when we can perform the
42369 shift with one insn set the cost to prefer paddb. */
42371 {
42376 }
42378 }
42382 }
42383 else
42385 }
42387 {
42389 {
42392 else
42394 }
42395 else
42396 {
42399 else
42401 }
42402 }
42403 else
42404 {
42409 {
42410 /* Return the cost after shift-and truncation. */
42413 }
42414 else
42416 }
42420 {
42421 rtx sub;
42426 /* ??? SSE scalar/vector cost should be used here. */
42427 /* ??? Bald assumption that fma has the same cost as fmul. */
42431 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
42442 }
42446 {
42447 /* ??? SSE scalar cost should be used here. */
42450 }
42452 {
42455 }
42457 {
42458 /* ??? SSE vector cost should be used here. */
42461 }
42463 {
42464 /* V*QImode is emulated with 7-13 insns. */
42466 {
42473 }
42474 /* V*DImode is emulated with 5-8 insns. */
42476 {
42479 else
42481 }
42482 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
42483 insns, including two PMULUDQ. */
42486 else
42489 }
42490 else
42491 {
42496 {
42499 nbits++;
42500 }
42501 else
42502 /* This is arbitrary. */
42505 /* Compute costs correctly for widening multiplication. */
42509 {
42516 {
42520 else
42522 }
42526 }
42534 }
42541 /* ??? SSE cost should be used here. */
42546 /* ??? SSE vector cost should be used here. */
42548 else
42555 {
42560 {
42563 {
42572 }
42573 }
42576 {
42579 {
42586 }
42587 }
42589 {
42598 }
42599 }
42600 /* FALLTHRU */
42604 {
42605 /* ??? SSE cost should be used here. */
42608 }
42610 {
42613 }
42615 {
42616 /* ??? SSE vector cost should be used here. */
42619 }
42620 /* FALLTHRU */
42627 {
42634 }
42635 /* FALLTHRU */
42639 {
42640 /* ??? SSE cost should be used here. */
42643 }
42645 {
42648 }
42650 {
42651 /* ??? SSE vector cost should be used here. */
42654 }
42655 /* FALLTHRU */
42659 {
42660 /* ??? Should be SSE vector operation cost. */
42661 /* At least for published AMD latencies, this really is the same
42662 as the latency for a simple fpu operation like fabs. */
42664 }
42667 else
42676 {
42677 /* This kind of construct is implemented using test[bwl].
42678 Treat it as if we had an AND. */
42685 }
42687 /* The embedded comparison operand is completely free. */
42701 /* ??? SSE cost should be used here. */
42706 /* ??? SSE vector cost should be used here. */
42712 /* ??? SSE cost should be used here. */
42717 /* ??? SSE vector cost should be used here. */
42729 /* ??? Assume all of these vector manipulation patterns are
42730 recognizable. In which case they all pretty much have the
42731 same cost. */
42736 /* This is masked instruction, assume the same cost,
42737 as nonmasked variant. */
42740 else
42746 }
42747 }
42749 #if TARGET_MACHO
42753 /* Given a symbol name and its associated stub, write out the
42754 definition of the stub. */
42756 void
42758 {
42763 /* For 64-bit we shouldn't get here. */
42766 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
42783 else
42790 {
42792 }
42794 {
42795 /* PIC stub. */
42796 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42802 }
42803 else
42806 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
42807 it needs no stub-binding-helper. */
42814 {
42817 }
42818 else
42823 /* N.B. Keep the correspondence of these
42824 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
42825 old-pic/new-pic/non-pic stubs; altering this will break
42826 compatibility with existing dylibs. */
42828 {
42829 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42831 }
42832 else
42833 /* 16-byte -mdynamic-no-pic stub. */
42839 }
42842 /* Order the registers for register allocator. */
42844 void
42846 {
42850 /* First allocate the local general purpose registers. */
42855 /* Global general purpose registers. */
42860 /* x87 registers come first in case we are doing FP math
42861 using them. */
42866 /* SSE registers. */
42872 /* Extended REX SSE registers. */
42876 /* Mask register. */
42880 /* MPX bound registers. */
42884 /* x87 registers. */
42892 /* Initialize the rest of array as we do not allocate some registers
42893 at all. */
42896 }
42898 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
42899 in struct attribute_spec handler. */
42900 static tree
42902 tree args,
42905 {
42910 {
42912 name);
42915 }
42917 {
42919 name);
42922 }
42924 {
42925 tree cst;
42929 {
42932 name);
42934 }
42937 {
42940 name);
42942 }
42945 }
42948 }
42950 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
42951 struct attribute_spec.handler. */
42952 static tree
42955 {
42960 {
42962 name);
42965 }
42967 /* Can combine regparm with all attributes but fastcall. */
42969 {
42971 {
42973 }
42976 }
42978 {
42980 {
42982 }
42985 }
42988 }
42990 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
42991 struct attribute_spec.handler. */
42992 static tree
42995 {
42998 {
43001 }
43002 else
43006 {
43008 name);
43010 }
43016 {
43018 name);
43020 }
43023 }
43025 static tree
43028 {
43030 {
43032 name);
43034 }
43036 }
43038 static bool
43040 {
43044 }
43046 /* Returns an expression indicating where the this parameter is
43047 located on entry to the FUNCTION. */
43049 static rtx
43051 {
43057 {
43062 else
43065 }
43070 {
43077 {
43082 }
43083 else
43084 {
43087 {
43093 }
43094 }
43096 }
43100 }
43102 /* Determine whether x86_output_mi_thunk can succeed. */
43104 static bool
43106 const_tree function)
43107 {
43108 /* 64-bit can handle anything. */
43112 /* For 32-bit, everything's fine if we have one free register. */
43116 /* Need a free register for vcall_offset. */
43120 /* Need a free register for GOT references. */
43124 /* Otherwise ok. */
43126 }
43128 /* Output the assembler code for a thunk function. THUNK_DECL is the
43129 declaration for the thunk function itself, FUNCTION is the decl for
43130 the target function. DELTA is an immediate constant offset to be
43131 added to THIS. If VCALL_OFFSET is nonzero, the word at
43132 *(*this + vcall_offset) should be added to THIS. */
43134 static void
43137 {
43145 else
43146 {
43152 else
43154 }
43158 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
43159 pull it in now and let DELTA benefit. */
43163 {
43164 /* Put the this parameter into %eax. */
43167 }
43168 else
43171 /* Adjust the this parameter by a fixed constant. */
43173 {
43178 {
43180 {
43184 }
43185 }
43188 }
43190 /* Adjust the this parameter by a value stored in the vtable. */
43192 {
43202 /* Adjust the this parameter. */
43206 {
43210 }
43217 vcall_mem));
43218 else
43220 }
43222 /* If necessary, drop THIS back to its stack slot. */
43228 {
43231 ;
43232 else
43233 {
43237 }
43238 }
43239 else
43240 {
43242 ;
43243 #if TARGET_MACHO
43245 {
43248 }
43250 else
43251 {
43259 }
43260 }
43262 /* Our sibling call patterns do not allow memories, because we have no
43263 predicate that can distinguish between frame and non-frame memory.
43264 For our purposes here, we can get away with (ab)using a jump pattern,
43265 because we're going to do no optimization. */
43267 {
43269 {
43275 }
43276 else
43278 }
43279 else
43280 {
43282 {
43283 // CM_LARGE_PIC always uses pseudo PIC register which is
43284 // uninitialized. Since FUNCTION is local and calling it
43285 // doesn't go through PLT, we use scratch register %r11 as
43286 // PIC register and initialize it here.
43291 }
43294 {
43300 }
43306 }
43309 /* Emit just enough of rest_of_compilation to get the insns emitted.
43310 Note that use_thunk calls assemble_start_function et al. */
43316 }
43318 static void
43320 {
43324 #if TARGET_MACHO
43326 #endif
43333 }
43335 int
43337 {
43338 machine_mode mode;
43351 }
43353 /* Print call to TARGET to FILE. */
43355 static void
43357 {
43360 else
43362 }
43364 /* Output assembler code to FILE to increment profiler label # LABELNO
43365 for profiling a function entry. */
43366 void
43368 {
43372 {
43373 #ifndef NO_PROFILE_COUNTERS
43375 #endif
43379 else
43381 }
43383 {
43384 #ifndef NO_PROFILE_COUNTERS
43387 #endif
43389 }
43390 else
43391 {
43392 #ifndef NO_PROFILE_COUNTERS
43395 #endif
43397 }
43400 {
43404 }
43405 }
43407 /* We don't have exact information about the insn sizes, but we may assume
43408 quite safely that we are informed about all 1 byte insns and memory
43409 address sizes. This is enough to eliminate unnecessary padding in
43410 99% of cases. */
43412 static int
43414 {
43420 /* Discard alignments we've emit and jump instructions. */
43425 /* Important case - calls are always 5 bytes.
43426 It is common to have many calls in the row. */
43435 /* For normal instructions we rely on get_attr_length being exact,
43436 with a few exceptions. */
43438 {
43442 {
43452 /* Otherwise trust get_attr_length. */
43454 }
43459 }
43462 else
43464 }
43466 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43468 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
43469 window. */
43471 static void
43473 {
43478 /* Look for all minimal intervals of instructions containing 4 jumps.
43479 The intervals are bounded by START and INSN. NBYTES is the total
43480 size of instructions in the interval including INSN and not including
43481 START. When the NBYTES is smaller than 16 bytes, it is possible
43482 that the end of START and INSN ends up in the same 16byte page.
43484 The smallest offset in the page INSN can start is the case where START
43485 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
43486 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
43488 Don't consider asm goto as jump, while it can contain a jump, it doesn't
43489 have to, control transfer to label(s) can be performed through other
43490 means, and also we estimate minimum length of all asm stmts as 0. */
43492 {
43496 {
43502 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
43503 already in the current 16 byte page, because otherwise
43504 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
43505 bytes to reach 16 byte boundary. */
43513 {
43515 {
43520 else
43523 }
43524 }
43526 }
43535 njumps++;
43536 else
43540 {
43545 else
43548 }
43555 {
43562 }
43563 }
43564 }
43565 #endif
43567 /* AMD Athlon works faster
43568 when RET is not destination of conditional jump or directly preceded
43569 by other jump instruction. We avoid the penalty by inserting NOP just
43570 before the RET instructions in such cases. */
43571 static void
43573 {
43574 edge e;
43575 edge_iterator ei;
43578 {
43591 {
43592 edge e;
43593 edge_iterator ei;
43598 {
43601 }
43602 }
43604 {
43610 /* Empty functions get branch mispredict even when
43611 the jump destination is not visible to us. */
43614 }
43616 {
43619 }
43620 }
43621 }
43623 /* Count the minimum number of instructions in BB. Return 4 if the
43624 number of instructions >= 4. */
43626 static int
43628 {
43632 /* Count number of instructions in this block. Return 4 if the number
43633 of instructions >= 4. */
43635 {
43636 /* Only happen in exit blocks. */
43644 {
43645 insn_count++;
43648 }
43649 }
43652 }
43655 /* Count the minimum number of instructions in code path in BB.
43656 Return 4 if the number of instructions >= 4. */
43658 static int
43660 {
43661 edge e;
43662 edge_iterator ei;
43665 /* Only bother counting instructions along paths with no
43666 more than 2 basic blocks between entry and exit. Given
43667 that BB has an edge to exit, determine if a predecessor
43668 of BB has an edge from entry. If so, compute the number
43669 of instructions in the predecessor block. If there
43670 happen to be multiple such blocks, compute the minimum. */
43673 {
43674 edge prev_e;
43675 edge_iterator prev_ei;
43678 {
43681 }
43683 {
43685 {
43690 }
43691 }
43692 }
43698 }
43700 /* Pad short function to 4 instructions. */
43702 static void
43704 {
43705 edge e;
43706 edge_iterator ei;
43709 {
43712 {
43715 /* Pad short function. */
43717 {
43720 /* Find epilogue. */
43729 /* Two NOPs count as one instruction. */
43732 }
43733 }
43734 }
43735 }
43737 /* Fix up a Windows system unwinder issue. If an EH region falls through into
43738 the epilogue, the Windows system unwinder will apply epilogue logic and
43739 produce incorrect offsets. This can be avoided by adding a nop between
43740 the last insn that can throw and the first insn of the epilogue. */
43742 static void
43744 {
43745 edge e;
43746 edge_iterator ei;
43749 {
43752 /* Find the beginning of the epilogue. */
43759 /* We only care about preceding insns that can throw. */
43764 /* Do not separate calls from their debug information. */
43770 else
43774 }
43775 }
43777 /* Implement machine specific optimizations. We implement padding of returns
43778 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
43779 static void
43781 {
43782 /* We are freeing block_for_insn in the toplev to keep compatibility
43783 with old MDEP_REORGS that are not CFG based. Recompute it now. */
43790 {
43795 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43798 #endif
43799 }
43800 }
43802 /* Return nonzero when QImode register that must be represented via REX prefix
43803 is used. */
43804 bool
43806 {
43814 }
43816 /* Return true when INSN mentions register that must be encoded using REX
43817 prefix. */
43818 bool
43820 {
43823 {
43828 }
43830 }
43832 /* If profitable, negate (without causing overflow) integer constant
43833 of mode MODE at location LOC. Return true in this case. */
43834 bool
43836 {
43837 HOST_WIDE_INT val;
43843 {
43845 /* DImode x86_64 constants must fit in 32 bits. */
43858 }
43860 /* Avoid overflows. */
43866 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
43867 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
43870 {
43873 }
43876 }
43878 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
43879 optabs would emit if we didn't have TFmode patterns. */
43881 void
43883 {
43918 }
43919 \f
43925 /* Get a vector mode of the same size as the original but with elements
43926 twice as wide. This is only guaranteed to apply to integral vectors. */
43930 {
43931 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
43936 }
43938 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
43939 fill target with val via vec_duplicate. */
43941 static bool
43943 {
43946 rtx dup;
43948 /* First attempt to recognize VAL as-is. */
43952 {
43954 /* If that fails, force VAL into a register. */
43965 }
43967 }
43969 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43970 with all elements equal to VAR. Return true if successful. */
43972 static bool
43975 {
43979 {
43984 /* FALLTHRU */
44004 {
44005 rtx x;
44012 }
44025 {
44029 permute:
44037 /* Extend to SImode using a paradoxical SUBREG. */
44041 /* Insert the SImode value as low element of a V4SImode vector. */
44050 }
44061 widen:
44062 /* Replicate the value once into the next wider mode and recurse. */
44063 {
44065 rtx x;
44082 }
44088 else
44089 {
44098 }
44105 else
44106 {
44115 }
44120 }
44121 }
44123 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
44124 whose ONE_VAR element is VAR, and other elements are zero. Return true
44125 if successful. */
44127 static bool
44130 {
44131 machine_mode vsimode;
44132 rtx new_target;
44137 {
44139 /* For SSE4.1, we normally use vector set. But if the second
44140 element is zero and inter-unit moves are OK, we use movq
44141 instead. */
44143 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
44165 /* Use ix86_expand_vector_set in 64bit mode only. */
44170 }
44173 {
44178 }
44181 {
44186 /* FALLTHRU */
44201 else
44208 {
44209 /* We need to shuffle the value to the correct position, so
44210 create a new pseudo to store the intermediate result. */
44212 /* With SSE2, we can use the integer shuffle insns. */
44214 {
44216 const1_rtx,
44223 }
44225 /* Otherwise convert the intermediate result to V4SFmode and
44226 use the SSE1 shuffle instructions. */
44228 {
44231 }
44232 else
44236 const1_rtx,
44245 }
44260 widen:
44264 /* Zero extend the variable element to SImode and recurse. */
44277 }
44278 }
44280 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
44281 consisting of the values in VALS. It is known that all elements
44282 except ONE_VAR are constants. Return true if successful. */
44284 static bool
44287 {
44289 machine_mode wmode;
44297 {
44302 /* For the two element vectors, it's just as easy to use
44303 the general case. */
44307 /* Use ix86_expand_vector_set in 64bit mode only. */
44329 widen:
44330 /* There's no way to set one QImode entry easily. Combine
44331 the variable value with its adjacent constant value, and
44332 promote to an HImode set. */
44335 {
44340 }
44341 else
44342 {
44345 }
44359 }
44364 }
44366 /* A subroutine of ix86_expand_vector_init_general. Use vector
44367 concatenate to handle the most general case: all values variable,
44368 and none identical. */
44370 static void
44373 {
44376 rtvec v;
44380 {
44383 {
44428 }
44440 {
44455 }
44460 {
44479 }
44484 {
44497 }
44500 half:
44501 /* FIXME: We process inputs backward to help RA. PR 36222. */
44505 {
44510 }
44514 {
44518 {
44522 }
44525 {
44529 }
44532 }
44534 {
44537 {
44541 }
44544 }
44545 else
44551 }
44552 }
44554 /* A subroutine of ix86_expand_vector_init_general. Use vector
44555 interleave to handle the most general case: all values variable,
44556 and none identical. */
44558 static void
44561 {
44570 {
44591 }
44594 {
44595 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
44599 /* Insert the SImode value as low element of V4SImode vector. */
44603 op0),
44605 const1_rtx);
44608 /* Cast the V4SImode vector back to a vector in orignal mode. */
44612 /* Load even elements into the second position. */
44616 const1_rtx));
44618 /* Cast vector to FIRST_IMODE vector. */
44621 }
44623 /* Interleave low FIRST_IMODE vectors. */
44625 {
44629 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
44632 }
44634 /* Interleave low SECOND_IMODE vectors. */
44636 {
44639 {
44644 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
44645 vector. */
44648 }
44651 /* FALLTHRU */
44658 /* Cast the SECOND_IMODE vector back to a vector on original
44659 mode. */
44665 }
44666 }
44668 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
44669 all values variable, and none identical. */
44671 static void
44674 {
44681 {
44686 /* FALLTHRU */
44714 half:
44737 quarter:
44763 /* FALLTHRU */
44769 /* Don't use ix86_expand_vector_init_interleave if we can't
44770 move from GPR to SSE register directly. */
44786 }
44788 {
44790 machine_mode inner_mode;
44800 {
44804 {
44810 else
44811 {
44816 }
44817 }
44820 }
44825 {
44831 }
44833 {
44839 }
44840 else
44842 }
44843 }
44845 /* Initialize vector TARGET via VALS. Suppress the use of MMX
44846 instructions unless MMX_OK is true. */
44848 void
44850 {
44857 rtx x;
44860 {
44870 }
44872 /* Constants are best loaded from the constant pool. */
44874 {
44877 }
44879 /* If all values are identical, broadcast the value. */
44885 /* Values where only one field is non-constant are best loaded from
44886 the pool and overwritten via move later. */
44888 {
44892 one_var))
44897 }
44900 }
44902 void
44904 {
44907 machine_mode half_mode;
44909 rtx tmp;
44911 = {
44918 };
44920 = {
44927 };
44933 {
44937 {
44942 else
44946 }
44958 else
44964 {
44967 /* For the two element vectors, we implement a VEC_CONCAT with
44968 the extraction of the other element. */
44975 else
44980 }
44989 {
44995 /* tmp = target = A B C D */
44997 /* target = A A B B */
44999 /* target = X A B B */
45001 /* target = A X C D */
45008 /* tmp = target = A B C D */
45010 /* tmp = X B C D */
45012 /* target = A B X D */
45019 /* tmp = target = A B C D */
45021 /* tmp = X B C D */
45023 /* target = A B X D */
45031 }
45039 /* Element 0 handled by vec_merge below. */
45041 {
45044 }
45047 {
45048 /* With SSE2, use integer shuffles to swap element 0 and ELT,
45049 store into element 0, then shuffle them back. */
45066 }
45067 else
45068 {
45069 /* For SSE1, we have to reuse the V4SF code. */
45073 }
45126 half:
45127 /* Compute offset. */
45133 /* Extract the half. */
45137 /* Put val in tmp at elt. */
45140 /* Put it back. */
45146 {
45149 }
45154 {
45157 }
45162 {
45165 }
45170 {
45173 }
45178 {
45181 }
45186 {
45189 }
45194 }
45197 {
45203 }
45205 {
45209 }
45210 else
45211 {
45220 }
45221 }
45223 void
45225 {
45229 rtx tmp;
45232 {
45237 /* FALLTHRU */
45250 {
45270 }
45282 {
45284 {
45304 }
45308 }
45309 else
45310 {
45311 /* For SSE1, we have to reuse the V4SF code. */
45315 }
45331 {
45335 else
45339 }
45344 {
45348 else
45352 }
45357 {
45361 else
45365 }
45370 {
45374 else
45378 }
45383 {
45387 else
45391 }
45396 {
45400 else
45404 }
45409 {
45413 else
45417 }
45422 {
45426 else
45430 }
45437 else
45446 else
45455 else
45464 else
45470 /* ??? Could extract the appropriate HImode element and shift. */
45473 }
45476 {
45480 /* Let the rtl optimizers know about the zero extension performed. */
45482 {
45485 }
45488 }
45489 else
45490 {
45497 }
45498 }
45500 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
45501 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
45502 The upper bits of DEST are undefined, though they shouldn't cause
45503 exceptions (some bits from src or all zeros are ok). */
45505 static void
45507 {
45510 {
45514 else
45532 else
45539 else
45547 {
45552 const1_rtx);
45553 }
45554 else
45555 {
45559 }
45581 else
45603 }
45607 }
45609 /* Expand a vector reduction. FN is the binary pattern to reduce;
45610 DEST is the destination; IN is the input vector. */
45612 void
45614 {
45619 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
45623 {
45626 }
45631 {
45636 else
45640 }
45641 }
45642 \f
45643 /* Target hook for scalar_mode_supported_p. */
45644 static bool
45646 {
45651 else
45653 }
45655 /* Implements target hook vector_mode_supported_p. */
45656 static bool
45658 {
45672 }
45674 /* Implement target hook libgcc_floating_mode_supported_p. */
45675 static bool
45677 {
45679 {
45686 #ifdef IX86_NO_LIBGCC_TFMODE
45688 #elif defined IX86_MAYBE_NO_LIBGCC_TFMODE
45690 #else
45692 #endif
45696 }
45697 }
45699 /* Target hook for c_mode_for_suffix. */
45700 static machine_mode
45702 {
45709 }
45711 /* Worker function for TARGET_MD_ASM_ADJUST.
45713 We implement asm flag outputs, and maintain source compatibility
45714 with the old cc0-based compiler. */
45720 {
45728 {
45734 {
45737 }
45747 {
45796 }
45798 {
45801 }
45807 {
45808 /* This is the first asm flag output. Here we put the flags
45809 register in as the real output and adjust the condition to
45810 allow it. */
45814 }
45815 else
45816 {
45817 /* We don't need the flags register as output twice. */
45820 }
45827 {
45830 }
45836 {
45842 {
45847 }
45848 else
45850 }
45853 {
45858 }
45859 else
45861 }
45867 else
45868 {
45869 /* If we had no asm flag outputs, clobber the flags. */
45873 }
45874 }
45876 /* Implements target vector targetm.asm.encode_section_info. */
45878 static void ATTRIBUTE_UNUSED
45880 {
45885 }
45887 /* Worker function for REVERSE_CONDITION. */
45889 enum rtx_code
45891 {
45895 }
45897 /* Output code to perform an x87 FP register move, from OPERANDS[1]
45898 to OPERANDS[0]. */
45902 {
45904 {
45907 {
45911 }
45915 }
45917 {
45921 else
45922 {
45923 /* There is no non-popping store to memory for XFmode.
45924 So if we need one, follow the store with a load. */
45927 else
45929 }
45930 }
45931 else
45933 }
45935 /* Output code to perform a conditional jump to LABEL, if C2 flag in
45936 FP status register is set. */
45938 void
45940 {
45942 rtx temp;
45947 {
45952 }
45953 else
45954 {
45959 }
45963 pc_rtx);
45968 }
45970 /* Output code to perform a log1p XFmode calculation. */
45973 {
45979 rtx test;
45985 XFmode));
45999 }
46001 /* Emit code for round calculation. */
46003 {
46010 rtx insn;
46015 {
46027 }
46030 {
46051 }
46059 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
46061 /* scratch = fxam(op1) */
46064 UNSPEC_FXAM)));
46065 /* e1 = fabs(op1) */
46068 /* e2 = e1 + 0.5 */
46072 /* res = floor(e2) */
46074 {
46078 }
46079 else
46083 {
46086 {
46093 UNSPEC_TRUNC_NOOP)));
46094 }
46110 }
46112 /* flags = signbit(a) */
46115 /* if (flags) then res = -res */
46119 pc_rtx);
46130 }
46132 /* Output code to perform a Newton-Rhapson approximation of a single precision
46133 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
46136 {
46144 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
46148 /* x0 = rcp(b) estimate */
46151 UNSPEC_RCP14)));
46152 else
46154 UNSPEC_RCP)));
46156 /* e0 = x0 * b */
46159 /* e0 = x0 * e0 */
46162 /* e1 = x0 + x0 */
46165 /* x1 = e1 - e0 */
46168 /* res = a * x1 */
46170 }
46172 /* Output code to perform a Newton-Rhapson approximation of a
46173 single precision floating point [reciprocal] square root. */
46177 {
46179 REAL_VALUE_TYPE r;
46196 {
46199 /* There is no 512-bit rsqrt. There is however rsqrt14. */
46202 }
46204 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
46205 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
46209 /* x0 = rsqrt(a) estimate */
46211 unspec)));
46213 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
46215 {
46223 /* Handle masked compare. */
46225 {
46227 /* Imm value 0x4 corresponds to not-equal comparison. */
46230 }
46231 else
46232 {
46236 }
46237 }
46239 /* e0 = x0 * a */
46241 /* e1 = e0 * x0 */
46244 /* e2 = e1 - 3. */
46250 /* e3 = -.5 * x0 */
46252 else
46253 /* e3 = -.5 * e0 */
46255 /* ret = e2 * e3 */
46257 }
46259 #ifdef TARGET_SOLARIS
46260 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
46262 static void
46264 tree decl)
46265 {
46266 /* With Binutils 2.15, the "@unwind" marker must be specified on
46267 every occurrence of the ".eh_frame" section, not just the first
46268 one. */
46271 {
46275 }
46277 #ifndef USE_GAS
46279 {
46282 }
46283 #endif
46286 }
46289 /* Return the mangling of TYPE if it is an extended fundamental type. */
46293 {
46301 {
46303 /* __float128 is "g". */
46306 /* "long double" or __float80 is "e". */
46310 }
46311 }
46313 /* For 32-bit code we can save PIC register setup by using
46314 __stack_chk_fail_local hidden function instead of calling
46315 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
46316 register, so it is better to call __stack_chk_fail directly. */
46318 static tree ATTRIBUTE_UNUSED
46320 {
46321 return TARGET_64BIT
46324 }
46326 /* Select a format to encode pointers in exception handling data. CODE
46327 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
46328 true if the symbol may be affected by dynamic relocations.
46330 ??? All x86 object file formats are capable of representing this.
46331 After all, the relocation needed is the same as for the call insn.
46332 Whether or not a particular assembler allows us to enter such, I
46333 guess we'll have to see. */
46334 int
46336 {
46338 {
46345 }
46350 }
46351 \f
46352 /* Expand copysign from SIGN to the positive value ABS_VALUE
46353 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
46354 the sign-bit. */
46355 static void
46357 {
46361 {
46362 machine_mode vmode;
46368 else
46373 {
46374 /* We need to generate a scalar mode mask in this case. */
46379 }
46380 }
46381 else
46385 }
46387 /* Expand fabs (OP0) and return a new rtx that holds the result. The
46388 mask for masking out the sign-bit is stored in *SMASK, if that is
46389 non-null. */
46390 static rtx
46392 {
46401 else
46405 {
46406 /* We need to generate a scalar mode mask in this case. */
46411 }
46418 }
46420 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
46421 swapping the operands if SWAP_OPERANDS is true. The expanded
46422 code is a forward jump to a newly created label in case the
46423 comparison is true. The generated label rtx is returned. */
46427 {
46430 rtx tmp;
46445 }
46447 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
46448 using comparison code CODE. Operands are swapped for the comparison if
46449 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
46450 static rtx
46453 {
46466 }
46468 /* Generate and return a rtx of mode MODE for 2**n where n is the number
46469 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
46470 static rtx
46472 {
46473 REAL_VALUE_TYPE TWO52r;
46474 rtx TWO52;
46481 }
46483 /* Expand SSE sequence for computing lround from OP1 storing
46484 into OP0. */
46485 void
46487 {
46488 /* C code for the stuff we're doing below:
46489 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
46490 return (long)tmp;
46491 */
46495 rtx adj;
46497 /* load nextafter (0.5, 0.0) */
46502 /* adj = copysign (0.5, op1) */
46506 /* adj = op1 + adj */
46509 /* op0 = (imode)adj */
46511 }
46513 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
46514 into OPERAND0. */
46515 void
46517 {
46518 /* C code for the stuff we're doing below (for do_floor):
46519 xi = (long)op1;
46520 xi -= (double)xi > op1 ? 1 : 0;
46521 return xi;
46522 */
46528 /* reg = (long)op1 */
46532 /* freg = (double)reg */
46536 /* ireg = (freg > op1) ? ireg - 1 : ireg */
46547 }
46549 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
46550 result in OPERAND0. */
46551 void
46553 {
46554 /* C code for the stuff we're doing below:
46555 xa = fabs (operand1);
46556 if (!isless (xa, 2**52))
46557 return operand1;
46558 xa = xa + 2**52 - 2**52;
46559 return copysign (xa, operand1);
46560 */
46568 /* xa = abs (operand1) */
46571 /* if (!isless (xa, TWO52)) goto label; */
46584 }
46586 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46587 into OPERAND0. */
46588 void
46590 {
46591 /* C code for the stuff we expand below.
46592 double xa = fabs (x), x2;
46593 if (!isless (xa, TWO52))
46594 return x;
46595 xa = xa + TWO52 - TWO52;
46596 x2 = copysign (xa, x);
46597 Compensate. Floor:
46598 if (x2 > x)
46599 x2 -= 1;
46600 Compensate. Ceil:
46601 if (x2 < x)
46602 x2 -= -1;
46603 return x2;
46604 */
46611 /* Temporary for holding the result, initialized to the input
46612 operand to ease control flow. */
46616 /* xa = abs (operand1) */
46619 /* if (!isless (xa, TWO52)) goto label; */
46622 /* xa = xa + TWO52 - TWO52; */
46626 /* xa = copysign (xa, operand1) */
46629 /* generate 1.0 or -1.0 */
46634 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46637 /* We always need to subtract here to preserve signed zero. */
46646 }
46648 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46649 into OPERAND0. */
46650 void
46652 {
46653 /* C code for the stuff we expand below.
46654 double xa = fabs (x), x2;
46655 if (!isless (xa, TWO52))
46656 return x;
46657 x2 = (double)(long)x;
46658 Compensate. Floor:
46659 if (x2 > x)
46660 x2 -= 1;
46661 Compensate. Ceil:
46662 if (x2 < x)
46663 x2 += 1;
46664 if (HONOR_SIGNED_ZEROS (mode))
46665 return copysign (x2, x);
46666 return x2;
46667 */
46674 /* Temporary for holding the result, initialized to the input
46675 operand to ease control flow. */
46679 /* xa = abs (operand1) */
46682 /* if (!isless (xa, TWO52)) goto label; */
46685 /* xa = (double)(long)x */
46690 /* generate 1.0 */
46693 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46707 }
46709 /* Expand SSE sequence for computing round from OPERAND1 storing
46710 into OPERAND0. Sequence that works without relying on DImode truncation
46711 via cvttsd2siq that is only available on 64bit targets. */
46712 void
46714 {
46715 /* C code for the stuff we expand below.
46716 double xa = fabs (x), xa2, x2;
46717 if (!isless (xa, TWO52))
46718 return x;
46719 Using the absolute value and copying back sign makes
46720 -0.0 -> -0.0 correct.
46721 xa2 = xa + TWO52 - TWO52;
46722 Compensate.
46723 dxa = xa2 - xa;
46724 if (dxa <= -0.5)
46725 xa2 += 1;
46726 else if (dxa > 0.5)
46727 xa2 -= 1;
46728 x2 = copysign (xa2, x);
46729 return x2;
46730 */
46737 /* Temporary for holding the result, initialized to the input
46738 operand to ease control flow. */
46742 /* xa = abs (operand1) */
46745 /* if (!isless (xa, TWO52)) goto label; */
46748 /* xa2 = xa + TWO52 - TWO52; */
46752 /* dxa = xa2 - xa; */
46755 /* generate 0.5, 1.0 and -0.5 */
46761 /* Compensate. */
46763 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
46767 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
46772 /* res = copysign (xa2, operand1) */
46779 }
46781 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46782 into OPERAND0. */
46783 void
46785 {
46786 /* C code for SSE variant we expand below.
46787 double xa = fabs (x), x2;
46788 if (!isless (xa, TWO52))
46789 return x;
46790 x2 = (double)(long)x;
46791 if (HONOR_SIGNED_ZEROS (mode))
46792 return copysign (x2, x);
46793 return x2;
46794 */
46801 /* Temporary for holding the result, initialized to the input
46802 operand to ease control flow. */
46806 /* xa = abs (operand1) */
46809 /* if (!isless (xa, TWO52)) goto label; */
46812 /* x = (double)(long)x */
46824 }
46826 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46827 into OPERAND0. */
46828 void
46830 {
46835 /* C code for SSE variant we expand below.
46836 double xa = fabs (x), x2;
46837 if (!isless (xa, TWO52))
46838 return x;
46839 xa2 = xa + TWO52 - TWO52;
46840 Compensate:
46841 if (xa2 > xa)
46842 xa2 -= 1.0;
46843 x2 = copysign (xa2, x);
46844 return x2;
46845 */
46849 /* Temporary for holding the result, initialized to the input
46850 operand to ease control flow. */
46854 /* xa = abs (operand1) */
46857 /* if (!isless (xa, TWO52)) goto label; */
46860 /* res = xa + TWO52 - TWO52; */
46865 /* generate 1.0 */
46868 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
46875 /* res = copysign (res, operand1) */
46882 }
46884 /* Expand SSE sequence for computing round from OPERAND1 storing
46885 into OPERAND0. */
46886 void
46888 {
46889 /* C code for the stuff we're doing below:
46890 double xa = fabs (x);
46891 if (!isless (xa, TWO52))
46892 return x;
46893 xa = (double)(long)(xa + nextafter (0.5, 0.0));
46894 return copysign (xa, x);
46895 */
46902 /* Temporary for holding the result, initialized to the input
46903 operand to ease control flow. */
46911 /* load nextafter (0.5, 0.0) */
46916 /* xa = xa + 0.5 */
46920 /* xa = (double)(int64_t)xa */
46925 /* res = copysign (xa, operand1) */
46932 }
46934 /* Expand SSE sequence for computing round
46935 from OP1 storing into OP0 using sse4 round insn. */
46936 void
46938 {
46947 {
46958 }
46960 /* round (a) = trunc (a + copysign (0.5, a)) */
46962 /* load nextafter (0.5, 0.0) */
46968 /* e1 = copysign (0.5, op1) */
46972 /* e2 = op1 + e1 */
46975 /* res = trunc (e2) */
46980 }
46981 \f
46983 /* Table of valid machine attributes. */
46985 {
46986 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
46987 affects_type_identity } */
46988 /* Stdcall attribute says callee is responsible for popping arguments
46989 if they are not variable. */
46992 /* Fastcall attribute says callee is responsible for popping arguments
46993 if they are not variable. */
46996 /* Thiscall attribute says callee is responsible for popping arguments
46997 if they are not variable. */
47000 /* Cdecl attribute says the callee is a normal C declaration */
47003 /* Regparm attribute specifies how many integer arguments are to be
47004 passed in registers. */
47007 /* Sseregparm attribute says we are using x86_64 calling conventions
47008 for FP arguments. */
47011 /* The transactional memory builtins are implicitly regparm or fastcall
47012 depending on the ABI. Override the generic do-nothing attribute that
47013 these builtins were declared with. */
47016 /* force_align_arg_pointer says this function realigns the stack at entry. */
47019 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
47024 #endif
47029 #ifdef SUBTARGET_ATTRIBUTE_TABLE
47030 SUBTARGET_ATTRIBUTE_TABLE,
47031 #endif
47032 /* ms_abi and sysv_abi calling convention function attributes. */
47039 /* End element. */
47041 };
47043 /* Implement targetm.vectorize.builtin_vectorization_cost. */
47044 static int
47047 {
47051 {
47096 }
47097 }
47099 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
47100 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
47101 insn every time. */
47105 /* Initialize vselect_insn. */
47107 static void
47109 {
47111 rtx x;
47122 }
47124 /* Construct (set target (vec_select op0 (parallel perm))) and
47125 return true if that's a valid instruction in the active ISA. */
47127 static bool
47130 {
47156 }
47158 /* Similar, but generate a vec_concat from op0 and op1 as well. */
47160 static bool
47164 {
47165 machine_mode v2mode;
47166 rtx x;
47181 }
47183 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47184 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
47186 static bool
47188 {
47197 && (TARGET_AVX512BW
47199 ;
47201 ;
47203 ;
47205 ;
47206 else
47209 /* This is a blend, not a permute. Elements must stay in their
47210 respective lanes. */
47212 {
47216 }
47221 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
47222 decision should be extracted elsewhere, so that we only try that
47223 sequence once all budget==3 options have been tried. */
47230 {
47260 /* See if bytes move in pairs so we can use pblendw with
47261 an immediate argument, rather than pblendvb with a vector
47262 argument. */
47265 {
47266 use_pblendvb:
47270 finish_pblendvb:
47276 else
47281 }
47286 /* FALLTHRU */
47288 do_subreg:
47295 /* See if bytes move in pairs. If not, vpblendvb must be used. */
47299 /* See if bytes move in quadruplets. If yes, vpblendd
47300 with immediate can be used. */
47305 {
47306 /* See if bytes move the same in both lanes. If yes,
47307 vpblendw with immediate can be used. */
47312 /* Use vpblendw. */
47317 }
47319 /* Use vpblendd. */
47326 /* See if words move in pairs. If yes, vpblendd can be used. */
47331 {
47332 /* See if words move the same in both lanes. If not,
47333 vpblendvb must be used. */
47336 {
47337 /* Use vpblendvb. */
47347 }
47349 /* Use vpblendw. */
47353 }
47355 /* Use vpblendd. */
47362 /* Use vpblendd. */
47370 }
47373 {
47390 }
47394 else
47397 /* This matches five different patterns with the different modes. */
47405 }
47407 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47408 in terms of the variable form of vpermilps.
47410 Note that we will have already failed the immediate input vpermilps,
47411 which requires that the high and low part shuffle be identical; the
47412 variable form doesn't require that. */
47414 static bool
47416 {
47423 /* We can only permute within the 128-bit lane. */
47425 {
47429 }
47435 {
47438 /* Within each 128-bit lane, the elements of op0 are numbered
47439 from 0 and the elements of op1 are numbered from 4. */
47446 }
47453 }
47455 /* Return true if permutation D can be performed as VMODE permutation
47456 instead. */
47458 static bool
47460 {
47475 else
47481 }
47483 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47484 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
47486 static bool
47488 {
47497 {
47499 {
47502 {
47506 /* Use vperm2i128 insn. The pattern uses
47507 V4DImode instead of V2TImode. */
47520 }
47522 }
47523 }
47524 else
47525 {
47527 {
47530 }
47532 {
47536 /* V4DImode should be already handled through
47537 expand_vselect by vpermq instruction. */
47544 {
47545 /* First see if vpermq can be used for
47546 V8SImode/V16HImode/V32QImode. */
47548 {
47556 {
47560 }
47562 }
47564 /* Next see if vpermd can be used. */
47567 }
47568 /* Or if vpermps can be used. */
47573 {
47574 /* vpshufb only works intra lanes, it is not
47575 possible to shuffle bytes in between the lanes. */
47579 }
47580 }
47582 {
47586 /* If vpermq didn't work, vpshufb won't work either. */
47594 {
47595 /* First see if vpermq can be used for
47596 V16SImode/V32HImode/V64QImode. */
47598 {
47606 {
47610 }
47612 }
47614 /* Next see if vpermd can be used. */
47617 }
47618 /* Or if vpermps can be used. */
47622 {
47623 /* vpshufb only works intra lanes, it is not
47624 possible to shuffle bytes in between the lanes. */
47628 }
47629 }
47630 else
47632 }
47643 else
47644 {
47652 else
47656 {
47660 }
47661 }
47672 {
47687 else
47689 }
47690 else
47691 {
47694 }
47699 }
47701 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
47702 in a single instruction. */
47704 static bool
47706 {
47710 /* Check plain VEC_SELECT first, because AVX has instructions that could
47711 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
47712 input where SEL+CONCAT may not. */
47714 {
47720 {
47726 }
47729 {
47733 }
47735 {
47736 /* Use vpbroadcast{b,w,d}. */
47739 {
47782 /* For other modes prefer other shuffles this function creates. */
47784 }
47786 {
47790 }
47791 }
47796 /* There are plenty of patterns in sse.md that are written for
47797 SEL+CONCAT and are not replicated for a single op. Perhaps
47798 that should be changed, to avoid the nastiness here. */
47800 /* Recognize interleave style patterns, which means incrementing
47801 every other permutation operand. */
47803 {
47806 }
47811 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
47813 {
47815 {
47820 }
47825 }
47826 }
47828 /* Finally, try the fully general two operand permute. */
47833 /* Recognize interleave style patterns with reversed operands. */
47835 {
47837 {
47841 else
47844 }
47849 }
47851 /* Try the SSE4.1 blend variable merge instructions. */
47855 /* Try one of the AVX vpermil variable permutations. */
47859 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
47860 vpshufb, vpermd, vpermps or vpermq variable permutation. */
47864 /* Try the AVX2 vpalignr instruction. */
47868 /* Try the AVX512F vpermi2 instructions. */
47873 }
47875 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47876 in terms of a pair of pshuflw + pshufhw instructions. */
47878 static bool
47880 {
47888 /* The two permutations only operate in 64-bit lanes. */
47899 /* Emit the pshuflw. */
47906 /* Emit the pshufhw. */
47914 }
47916 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47917 the permutation using the SSSE3 palignr instruction. This succeeds
47918 when all of the elements in PERM fit within one vector and we merely
47919 need to shift them down so that a single vector permutation has a
47920 chance to succeed. If SINGLE_INSN_ONLY_P, succeed if only
47921 the vpalignr instruction itself can perform the requested permutation. */
47923 static bool
47925 {
47932 /* Even with AVX, palignr only operates on 128-bit vectors,
47933 in AVX2 palignr operates on both 128-bit lanes. */
47943 {
47947 {
47950 }
47959 }
47962 {
47971 }
47973 /* Given that we have SSSE3, we know we'll be able to implement the
47974 single operand permutation after the palignr with pshufb for
47975 128-bit vectors. If SINGLE_INSN_ONLY_P, in_order has to be computed
47976 first. */
47982 {
47987 }
47991 {
47997 else
48002 }
48008 /* For AVX2, test whether we can permute the result in one instruction. */
48010 {
48015 }
48019 {
48023 }
48024 else
48025 {
48030 shift));
48031 }
48035 /* Test for the degenerate case where the alignment by itself
48036 produces the desired permutation. */
48038 {
48041 }
48047 }
48049 /* A subroutine of ix86_expand_vec_perm_const_1. Try to simplify
48050 the permutation using the SSE4_1 pblendv instruction. Potentially
48051 reduces permutation from 2 pshufb and or to 1 pshufb and pblendv. */
48053 static bool
48055 {
48061 /* Use the same checks as in expand_vec_perm_blend. */
48065 ;
48067 ;
48069 ;
48070 else
48073 /* Figure out where permutation elements stay not in their
48074 respective lanes. */
48076 {
48080 }
48081 /* We can pblend the part where elements stay not in their
48082 respective lanes only when these elements are all in one
48083 half of a permutation.
48084 {0 1 8 3 4 5 9 7} is ok as 8, 9 are at not at their respective
48085 lanes, but both 8 and 9 >= 8
48086 {0 1 8 3 4 5 2 7} is not ok as 2 and 8 are not at their
48087 respective lanes and 8 >= 8, but 2 not. */
48093 /* First we apply one operand permutation to the part where
48094 elements stay not in their respective lanes. */
48098 else
48110 else
48115 /* Next we put permuted elements into their positions. */
48119 else
48129 }
48133 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48134 a two vector permutation into a single vector permutation by using
48135 an interleave operation to merge the vectors. */
48137 static bool
48139 {
48148 {
48151 }
48153 {
48156 /* For 32-byte modes allow even d->one_operand_p.
48157 The lack of cross-lane shuffling in some instructions
48158 might prevent a single insn shuffle. */
48161 /* If expand_vec_perm_interleave3 can expand this into
48162 a 3 insn sequence, give up and let it be expanded as
48163 3 insn sequence. While that is one insn longer,
48164 it doesn't need a memory operand and in the common
48165 case that both interleave low and high permutations
48166 with the same operands are adjacent needs 4 insns
48167 for both after CSE. */
48170 }
48171 else
48174 /* Examine from whence the elements come. */
48183 {
48186 /* Split the two input vectors into 4 halves. */
48192 /* If the elements from the low halves use interleave low, and similarly
48193 for interleave high. If the elements are from mis-matched halves, we
48194 can use shufps for V4SF/V4SI or do a DImode shuffle. */
48196 {
48197 /* punpckl* */
48199 {
48204 }
48207 }
48209 {
48210 /* punpckh* */
48212 {
48217 }
48220 }
48222 {
48223 /* shufps */
48225 {
48230 }
48232 {
48233 /* shufpd */
48238 }
48239 }
48241 {
48242 /* shufps */
48244 {
48249 }
48251 {
48252 /* shufpd */
48257 }
48258 }
48259 else
48261 }
48262 else
48263 {
48268 /* Split the two input vectors into 8 quarters. */
48274 {
48277 }
48280 {
48284 }
48286 {
48289 }
48292 {
48294 {
48295 /* Attempt to increase the likelihood that dfinal
48296 shuffle will be intra-lane. */
48298 }
48300 /* vperm2f128 or vperm2i128. */
48302 {
48307 }
48312 {
48316 {
48319 }
48320 }
48321 }
48326 {
48327 /* vpunpckl* */
48329 {
48338 }
48339 }
48342 {
48343 /* vpunpckh* */
48345 {
48354 }
48355 }
48356 else
48358 }
48360 /* Use the remapping array set up above to move the elements from their
48361 swizzled locations into their final destinations. */
48364 {
48367 /* If same_halves is true, both halves of the remapped vector are the
48368 same. Avoid cross-lane accesses if possible. */
48370 {
48373 }
48374 else
48376 }
48378 {
48381 }
48385 /* Test if the final remap can be done with a single insn. For V4SFmode or
48386 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
48399 {
48402 }
48409 }
48411 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48412 a single vector cross-lane permutation into vpermq followed
48413 by any of the single insn permutations. */
48415 static bool
48417 {
48431 {
48434 }
48437 {
48442 }
48455 {
48462 }
48469 {
48474 ;
48477 else
48479 }
48488 }
48490 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
48491 a vector permutation using two instructions, vperm2f128 resp.
48492 vperm2i128 followed by any single in-lane permutation. */
48494 static bool
48496 {
48510 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
48511 immediate. For perm < 16 the second permutation uses
48512 d->op0 as first operand, for perm >= 16 it uses d->op1
48513 as first operand. The second operand is the result of
48514 vperm2[fi]128. */
48516 {
48517 /* Ignore permutations which do not move anything cross-lane. */
48519 {
48520 /* The second shuffle for e.g. V4DFmode has
48521 0123 and ABCD operands.
48522 Ignore AB23, as 23 is already in the second lane
48523 of the first operand. */
48525 /* And 01CD, as 01 is in the first lane of the first
48526 operand. */
48528 /* And 4567, as then the vperm2[fi]128 doesn't change
48529 anything on the original 4567 second operand. */
48531 }
48532 else
48533 {
48534 /* The second shuffle for e.g. V4DFmode has
48535 4567 and ABCD operands.
48536 Ignore AB67, as 67 is already in the second lane
48537 of the first operand. */
48539 /* And 45CD, as 45 is in the first lane of the first
48540 operand. */
48542 /* And 0123, as then the vperm2[fi]128 doesn't change
48543 anything on the original 0123 first operand. */
48545 }
48548 {
48554 else
48556 }
48559 {
48563 }
48564 else
48568 {
48572 /* Found a usable second shuffle. dfirst will be
48573 vperm2f128 on d->op0 and d->op1. */
48585 /* And dsecond is some single insn shuffle, taking
48586 d->op0 and result of vperm2f128 (if perm < 16) or
48587 d->op1 and result of vperm2f128 (otherwise). */
48596 }
48598 /* For one operand, the only useful vperm2f128 permutation is 0x01
48599 aka lanes swap. */
48602 }
48605 }
48607 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48608 a two vector permutation using 2 intra-lane interleave insns
48609 and cross-lane shuffle for 32-byte vectors. */
48611 static bool
48613 {
48620 ;
48622 ;
48623 else
48638 {
48642 else
48648 else
48654 else
48660 else
48666 else
48672 else
48677 }
48681 }
48683 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
48684 a single vector permutation using a single intra-lane vector
48685 permutation, vperm2f128 swapping the lanes and vblend* insn blending
48686 the non-swapped and swapped vectors together. */
48688 static bool
48690 {
48698 || TARGET_AVX2
48707 {
48714 }
48749 }
48751 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
48752 permutation using two vperm2f128, followed by a vshufpd insn blending
48753 the two vectors together. */
48755 static bool
48757 {
48800 }
48802 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
48803 permutation with two pshufb insns and an ior. We should have already
48804 failed all two instruction sequences. */
48806 static bool
48808 {
48822 /* Generate two permutation masks. If the required element is within
48823 the given vector it is shuffled into the proper lane. If the required
48824 element is in the other vector, force a zero into the lane by setting
48825 bit 7 in the permutation mask. */
48828 {
48835 {
48838 }
48839 }
48863 }
48865 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
48866 with two vpshufb insns, vpermq and vpor. We should have already failed
48867 all two or three instruction sequences. */
48869 static bool
48871 {
48886 /* Generate two permutation masks. If the required element is within
48887 the same lane, it is shuffled in. If the required element from the
48888 other lane, force a zero by setting bit 7 in the permutation mask.
48889 In the other mask the mask has non-negative elements if element
48890 is requested from the other lane, but also moved to the other lane,
48891 so that the result of vpshufb can have the two V2TImode halves
48892 swapped. */
48895 {
48900 {
48903 }
48904 }
48913 /* Swap the 128-byte lanes of h into hp. */
48917 const1_rtx));
48934 }
48936 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48937 and extract-odd permutations of two V32QImode and V16QImode operand
48938 with two vpshufb insns, vpor and vpermq. We should have already
48939 failed all two or three instruction sequences. */
48941 static bool
48943 {
48962 /* Generate two permutation masks. In the first permutation mask
48963 the first quarter will contain indexes for the first half
48964 of the op0, the second quarter will contain bit 7 set, third quarter
48965 will contain indexes for the second half of the op0 and the
48966 last quarter bit 7 set. In the second permutation mask
48967 the first quarter will contain bit 7 set, the second quarter
48968 indexes for the first half of the op1, the third quarter bit 7 set
48969 and last quarter indexes for the second half of the op1.
48970 I.e. the first mask e.g. for V32QImode extract even will be:
48971 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
48972 (all values masked with 0xf except for -128) and second mask
48973 for extract even will be
48974 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
48977 {
48983 {
48986 }
48987 }
49006 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
49014 }
49016 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
49017 and extract-odd permutations of two V16QI, V8HI, V16HI or V32QI operands
49018 with two "and" and "pack" or two "shift" and "pack" insns. We should
49019 have already failed all two instruction sequences. */
49021 static bool
49023 {
49027 machine_mode half_mode;
49036 {
49038 /* Required for "pack". */
49049 /* No check as all instructions are SSE2. */
49080 /* Only V8HI, V16QI, V16HI and V32QI modes are more profitable than
49081 general shuffles. */
49083 }
49085 /* Check that permutation is even or odd. */
49100 {
49107 }
49108 else
49109 {
49116 }
49117 /* In AVX2 for 256 bit case we need to permute pack result. */
49119 {
49125 const0_rtx,
49126 const2_rtx,
49127 const1_rtx,
49130 }
49131 else
49135 }
49137 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
49138 and extract-odd permutations. */
49140 static bool
49142 {
49146 {
49153 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
49157 /* Now an unpck[lh]pd will produce the result required. */
49160 else
49166 {
49175 /* Shuffle within the 128-bit lanes to produce:
49176 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
49180 /* Shuffle the lanes around to produce:
49181 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
49185 /* Shuffle within the 128-bit lanes to produce:
49186 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
49189 /* Shuffle within the 128-bit lanes to produce:
49190 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
49193 /* Shuffle the lanes around to produce:
49194 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
49197 }
49204 /* These are always directly implementable by expand_vec_perm_1. */
49212 else
49213 {
49216 /* We need 2*log2(N)-1 operations to achieve odd/even
49217 with interleave. */
49226 else
49229 }
49241 {
49246 else
49251 {
49256 }
49258 }
49266 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
49270 /* Now an vpunpck[lh]qdq will produce the result required. */
49273 else
49280 {
49285 else
49290 {
49295 }
49297 }
49308 /* Shuffle the lanes around into
49309 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
49317 /* Swap the 2nd and 3rd position in each lane into
49318 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
49324 /* Now an vpunpck[lh]qdq will produce
49325 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
49329 else
49338 }
49341 }
49343 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
49344 extract-even and extract-odd permutations. */
49346 static bool
49348 {
49360 }
49362 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
49363 permutations. We assume that expand_vec_perm_1 has already failed. */
49365 static bool
49367 {
49375 {
49378 /* These are special-cased in sse.md so that we can optionally
49379 use the vbroadcast instruction. They expand to two insns
49380 if the input happens to be in a register. */
49387 /* These are always implementable using standard shuffle patterns. */
49392 /* These can be implemented via interleave. We save one insn by
49393 stopping once we have promoted to V4SImode and then use pshufd. */
49396 do
49397 {
49398 rtx dest;
49404 {
49408 }
49415 }
49431 /* For AVX2 broadcasts of the first element vpbroadcast* or
49432 vpermq should be used by expand_vec_perm_1. */
49438 }
49439 }
49441 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
49442 broadcast permutations. */
49444 static bool
49446 {
49458 }
49460 /* Implement arbitrary permutations of two V64QImode operands
49461 will 2 vpermi2w, 2 vpshufb and one vpor instruction. */
49462 static bool
49464 {
49474 machine_mode vmode;
49480 {
49487 }
49489 /* Prepare permutations such that the first one takes care of
49490 putting the even bytes into the right positions or one higher
49491 positions (ds[0]) and the second one takes care of
49492 putting the odd bytes into the right positions or one below
49493 (ds[1]). */
49496 {
49499 {
49502 }
49503 else
49504 {
49507 }
49508 }
49530 }
49532 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
49533 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
49534 all the shorter instruction sequences. */
49536 static bool
49538 {
49554 /* Generate 4 permutation masks. If the required element is within
49555 the same lane, it is shuffled in. If the required element from the
49556 other lane, force a zero by setting bit 7 in the permutation mask.
49557 In the other mask the mask has non-negative elements if element
49558 is requested from the other lane, but also moved to the other lane,
49559 so that the result of vpshufb can have the two V2TImode halves
49560 swapped. */
49563 {
49568 }
49574 {
49582 }
49585 {
49587 {
49590 }
49597 }
49599 /* Swap the 128-byte lanes of h[X]. */
49601 {
49607 const1_rtx));
49609 }
49612 {
49614 {
49617 }
49623 }
49626 {
49628 {
49632 }
49635 }
49645 }
49647 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
49648 With all of the interface bits taken care of, perform the expansion
49649 in D and return true on success. */
49651 static bool
49653 {
49654 /* Try a single instruction expansion. */
49658 /* Try sequences of two instructions. */
49681 /* Try sequences of three instructions. */
49698 /* Try sequences of four instructions. */
49709 /* ??? Look for narrow permutations whose element orderings would
49710 allow the promotion to a wider mode. */
49712 /* ??? Look for sequences of interleave or a wider permute that place
49713 the data into the correct lanes for a half-vector shuffle like
49714 pshuf[lh]w or vpermilps. */
49716 /* ??? Look for sequences of interleave that produce the desired results.
49717 The combinatorics of punpck[lh] get pretty ugly... */
49722 /* Even longer sequences. */
49727 }
49729 /* If a permutation only uses one operand, make it clear. Returns true
49730 if the permutation references both operands. */
49732 static bool
49734 {
49742 {
49748 {
49751 }
49752 /* The elements of PERM do not suggest that only the first operand
49753 is used, but both operands are identical. Allow easier matching
49754 of the permutation by folding the permutation into the single
49755 input vector. */
49756 /* FALLTHRU */
49767 }
49770 }
49772 bool
49774 {
49779 rtx sel;
49796 {
49801 }
49808 /* If the selector says both arguments are needed, but the operands are the
49809 same, the above tried to expand with one_operand_p and flattened selector.
49810 If that didn't work, retry without one_operand_p; we succeeded with that
49811 during testing. */
49813 {
49817 }
49820 }
49822 /* Implement targetm.vectorize.vec_perm_const_ok. */
49824 static bool
49827 {
49836 /* Given sufficient ISA support we can just return true here
49837 for selected vector modes. */
49839 {
49845 /* All implementable with a single vpermi2 insn. */
49850 /* All implementable with a single vpermi2 insn. */
49855 /* Implementable with 2 vpermi2, 2 vpshufb and 1 or insn. */
49863 /* All implementable with a single vpermi2 insn. */
49868 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49873 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49880 /* All implementable with a single vpperm insn. */
49883 /* All implementable with 2 pshufb + 1 ior. */
49889 /* All implementable with shufpd or unpck[lh]pd. */
49893 }
49895 /* Extract the values from the vector CST into the permutation
49896 array in D. */
49899 {
49903 }
49905 /* For all elements from second vector, fold the elements to first. */
49910 /* Check whether the mask can be applied to the vector type. */
49913 /* Implementable with shufps or pshufd. */
49917 /* Otherwise we have to go through the motions and see if we can
49918 figure out how to generate the requested permutation. */
49929 }
49931 void
49933 {
49948 /* We'll either be able to implement the permutation directly... */
49952 /* ... or we use the special-case patterns. */
49954 }
49956 static void
49958 {
49973 {
49976 }
49978 /* Note that for AVX this isn't one instruction. */
49981 }
49984 /* Expand a vector operation CODE for a V*QImode in terms of the
49985 same operation on V*HImode. */
49987 void
49989 {
49991 machine_mode himode;
50001 {
50019 }
50023 {
50025 /* Unpack data such that we've got a source byte in each low byte of
50026 each word. We don't care what goes into the high byte of each word.
50027 Rather than trying to get zero in there, most convenient is to let
50028 it be a copy of the low byte. */
50033 /* FALLTHRU */
50045 /* FALLTHRU */
50055 }
50057 /* Perform the operation. */
50064 /* Merge the data back into the right place. */
50074 {
50075 /* For SSE2, we used an full interleave, so the desired
50076 results are in the even elements. */
50079 }
50080 else
50081 {
50082 /* For AVX, the interleave used above was not cross-lane. So the
50083 extraction is evens but with the second and third quarter swapped.
50084 Happily, that is even one insn shorter than even extraction. */
50087 }
50094 }
50096 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
50097 if op is CONST_VECTOR with all odd elements equal to their
50098 preceding element. */
50100 static bool
50102 {
50112 }
50114 void
50117 {
50120 rtx x;
50128 /* We only play even/odd games with vectors of SImode. */
50131 /* If we're looking for the odd results, shift those members down to
50132 the even slots. For some cpus this is faster than a PSHUFD. */
50134 {
50135 /* For XOP use vpmacsdqh, but only for smult, as it is only
50136 signed. */
50138 {
50142 }
50153 }
50156 {
50159 else
50161 }
50163 {
50166 else
50168 }
50173 else
50174 {
50177 /* The easiest way to implement this without PMULDQ is to go through
50178 the motions as if we are performing a full 64-bit multiply. With
50179 the exception that we need to do less shuffling of the elements. */
50181 /* Compute the sign-extension, aka highparts, of the two operands. */
50187 /* Multiply LO(A) * HI(B), and vice-versa. */
50193 /* Multiply LO(A) * LO(B). */
50197 /* Combine and shift the highparts into place. */
50202 /* Combine high and low parts. */
50205 }
50207 }
50209 void
50212 {
50218 {
50223 {
50224 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
50225 shuffle the elements once so that all elements are in the right
50226 place for immediate use: { A C B D }. */
50231 }
50232 else
50233 {
50234 /* Put the elements into place for the multiply. */
50238 }
50243 /* Shuffle the elements between the lanes. After this we
50244 have { A B E F | C D G H } for each operand. */
50254 /* Shuffle the elements within the lanes. After this we
50255 have { A A B B | C C D D } or { E E F F | G G H H }. */
50296 }
50297 }
50299 void
50301 {
50311 /* Move the results in element 2 down to element 1; we don't care
50312 what goes in elements 2 and 3. Then we can merge the parts
50313 back together with an interleave.
50315 Note that two other sequences were tried:
50316 (1) Use interleaves at the start instead of psrldq, which allows
50317 us to use a single shufps to merge things back at the end.
50318 (2) Use shufps here to combine the two vectors, then pshufd to
50319 put the elements in the correct order.
50320 In both cases the cost of the reformatting stall was too high
50321 and the overall sequence slower. */
50332 }
50334 void
50336 {
50347 {
50348 /* op1: A,B,C,D, op2: E,F,G,H */
50357 /* t1: B,A,D,C */
50364 /* t2: (B*E),(A*F),(D*G),(C*H) */
50367 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
50370 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
50373 /* Multiply lower parts and add all */
50380 }
50381 else
50382 {
50383 machine_mode nmode;
50387 {
50390 }
50392 {
50395 }
50397 {
50400 }
50401 else
50405 /* Multiply low parts. */
50409 /* Shift input vectors right 32 bits so we can multiply high parts. */
50414 /* Multiply high parts by low parts. */
50420 /* Combine and shift the highparts back. */
50424 /* Combine high and low parts. */
50426 }
50430 }
50432 /* Return 1 if control tansfer instruction INSN
50433 should be encoded with bnd prefix.
50434 If insn is NULL then return 1 when control
50435 transfer instructions should be prefixed with
50436 bnd by default for current function. */
50438 bool
50440 {
50441 /* For call insns check special flag. */
50443 {
50447 }
50449 /* All other insns are prefixed only if function is instrumented. */
50451 }
50453 /* Calculate integer abs() using only SSE2 instructions. */
50455 void
50457 {
50462 {
50463 /* For 32-bit signed integer X, the best way to calculate the absolute
50464 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
50476 /* For 16-bit signed integer X, the best way to calculate the absolute
50477 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
50485 /* For 8-bit signed integer X, the best way to calculate the absolute
50486 value of X is min ((unsigned char) X, (unsigned char) (-X)),
50487 as SSE2 provides the PMINUB insn. */
50497 }
50501 }
50503 /* Expand an extract from a vector register through pextr insn.
50504 Return true if successful. */
50506 bool
50508 {
50516 {
50517 /* Reject non-lowpart subregs. */
50521 }
50524 {
50527 }
50530 {
50537 {
50544 {
50572 }
50574 /* Reject extractions from misaligned positions. */
50580 else
50583 /* Construct insn pattern. */
50587 /* Let the rtl optimizers know about the zero extension performed. */
50589 {
50592 }
50599 }
50603 }
50604 }
50606 /* Expand an insert into a vector register through pinsr insn.
50607 Return true if successful. */
50609 bool
50611 {
50619 {
50622 }
50625 {
50632 {
50635 rtx d;
50640 {
50672 }
50674 /* Reject insertions to misaligned positions. */
50679 {
50683 {
50695 }
50696 else
50698 }
50702 else
50711 }
50715 }
50716 }
50717 \f
50718 /* This function returns the calling abi specific va_list type node.
50719 It returns the FNDECL specific va_list type. */
50721 static tree
50723 {
50730 else
50732 }
50734 /* Returns the canonical va_list type specified by TYPE. If there
50735 is no valid TYPE provided, it return NULL_TREE. */
50737 static tree
50739 {
50742 /* Resolve references and pointers to va_list type. */
50751 {
50756 {
50757 /* If va_list is an array type, the argument may have decayed
50758 to a pointer type, e.g. by being passed to another function.
50759 In that case, unwrap both types so that we can compare the
50760 underlying records. */
50763 {
50766 }
50767 }
50774 {
50775 /* If va_list is an array type, the argument may have decayed
50776 to a pointer type, e.g. by being passed to another function.
50777 In that case, unwrap both types so that we can compare the
50778 underlying records. */
50781 {
50784 }
50785 }
50792 {
50793 /* If va_list is an array type, the argument may have decayed
50794 to a pointer type, e.g. by being passed to another function.
50795 In that case, unwrap both types so that we can compare the
50796 underlying records. */
50799 {
50802 }
50803 }
50807 }
50809 }
50811 /* Iterate through the target-specific builtin types for va_list.
50812 IDX denotes the iterator, *PTREE is set to the result type of
50813 the va_list builtin, and *PNAME to its internal type.
50814 Returns zero if there is no element for this index, otherwise
50815 IDX should be increased upon the next call.
50816 Note, do not iterate a base builtin's name like __builtin_va_list.
50817 Used from c_common_nodes_and_builtins. */
50819 static int
50821 {
50823 {
50825 {
50838 }
50839 }
50842 }
50844 #undef TARGET_SCHED_DISPATCH
50845 #define TARGET_SCHED_DISPATCH has_dispatch
50846 #undef TARGET_SCHED_DISPATCH_DO
50847 #define TARGET_SCHED_DISPATCH_DO do_dispatch
50848 #undef TARGET_SCHED_REASSOCIATION_WIDTH
50849 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
50850 #undef TARGET_SCHED_REORDER
50851 #define TARGET_SCHED_REORDER ix86_sched_reorder
50852 #undef TARGET_SCHED_ADJUST_PRIORITY
50853 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
50854 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
50855 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
50856 ix86_dependencies_evaluation_hook
50858 /* The size of the dispatch window is the total number of bytes of
50859 object code allowed in a window. */
50860 #define DISPATCH_WINDOW_SIZE 16
50862 /* Number of dispatch windows considered for scheduling. */
50863 #define MAX_DISPATCH_WINDOWS 3
50865 /* Maximum number of instructions in a window. */
50866 #define MAX_INSN 4
50868 /* Maximum number of immediate operands in a window. */
50869 #define MAX_IMM 4
50871 /* Maximum number of immediate bits allowed in a window. */
50872 #define MAX_IMM_SIZE 128
50874 /* Maximum number of 32 bit immediates allowed in a window. */
50875 #define MAX_IMM_32 4
50877 /* Maximum number of 64 bit immediates allowed in a window. */
50878 #define MAX_IMM_64 2
50880 /* Maximum total of loads or prefetches allowed in a window. */
50881 #define MAX_LOAD 2
50883 /* Maximum total of stores allowed in a window. */
50884 #define MAX_STORE 1
50886 #undef BIG
50887 #define BIG 100
50890 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
50893 disp_load,
50894 disp_store,
50895 disp_load_store,
50896 disp_prefetch,
50897 disp_imm,
50898 disp_imm_32,
50899 disp_imm_64,
50900 disp_branch,
50901 disp_cmp,
50902 disp_jcc,
50903 disp_last
50904 };
50906 /* Number of allowable groups in a dispatch window. It is an array
50907 indexed by dispatch_group enum. 100 is used as a big number,
50908 because the number of these kind of operations does not have any
50909 effect in dispatch window, but we need them for other reasons in
50910 the table. */
50913 };
50919 };
50921 /* Instruction path. */
50927 last_path
50928 };
50930 /* sched_insn_info defines a window to the instructions scheduled in
50931 the basic block. It contains a pointer to the insn_info table and
50932 the instruction scheduled.
50934 Windows are allocated for each basic block and are linked
50935 together. */
50937 rtx insn;
50944 /* Linked list of dispatch windows. This is a two way list of
50945 dispatch windows of a basic block. It contains information about
50946 the number of uops in the window and the total number of
50947 instructions and of bytes in the object code for this dispatch
50948 window. */
50966 /* Immediate valuse used in an insn. */
50968 {
50977 /* Get dispatch group of insn. */
50979 static enum dispatch_group
50981 {
50997 }
50999 /* Return true if insn is a compare instruction. */
51001 static bool
51003 {
51011 }
51013 /* Return true if a dispatch violation encountered. */
51015 static bool
51017 {
51021 }
51023 /* Return true if insn is a branch instruction. */
51025 static bool
51027 {
51029 }
51031 /* Return true if insn is a prefetch instruction. */
51033 static bool
51035 {
51037 }
51039 /* This function initializes a dispatch window and the list container holding a
51040 pointer to the window. */
51042 static void
51044 {
51050 else
51068 {
51074 }
51076 }
51078 /* This function allocates and initializes a dispatch window and the
51079 list container holding a pointer to the window. */
51083 {
51088 }
51090 /* This routine initializes the dispatch scheduling information. It
51091 initiates building dispatch scheduler tables and constructs the
51092 first dispatch window. */
51094 static void
51096 {
51097 /* Allocate a dispatch list and a window. */
51102 }
51104 /* This function returns true if a branch is detected. End of a basic block
51105 does not have to be a branch, but here we assume only branches end a
51106 window. */
51108 static bool
51110 {
51112 }
51114 /* This function is called when the end of a window processing is reached. */
51116 static void
51118 {
51121 {
51126 }
51128 }
51130 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
51131 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
51132 for 48 bytes of instructions. Note that these windows are not dispatch
51133 windows that their sizes are DISPATCH_WINDOW_SIZE. */
51137 {
51139 {
51144 }
51150 }
51152 /* Compute number of immediate operands of an instruction. */
51154 static void
51156 {
51163 {
51170 else
51182 {
51185 }
51190 }
51191 }
51193 /* Return total size of immediate operands of an instruction along with number
51194 of corresponding immediate-operands. It initializes its parameters to zero
51195 befor calling FIND_CONSTANT.
51196 INSN is the input instruction. IMM is the total of immediates.
51197 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
51198 bit immediates. */
51200 static int
51202 {
51210 }
51212 /* This function indicates if an operand of an instruction is an
51213 immediate. */
51215 static bool
51217 {
51226 }
51228 /* Return single or double path for instructions. */
51230 static enum insn_path
51232 {
51242 }
51244 /* Return insn dispatch group. */
51246 static enum dispatch_group
51248 {
51266 }
51268 /* Count number of GROUP restricted instructions in a dispatch
51269 window WINDOW_LIST. */
51271 static int
51273 {
51284 {
51303 }
51316 }
51318 /* This function returns true if insn satisfies dispatch rules on the
51319 last window scheduled. */
51321 static bool
51323 {
51331 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
51332 instructions should be given the lowest priority in the
51333 scheduling process in Haifa scheduler to make sure they will be
51334 scheduled in the same dispatch window as the reference to them. */
51338 /* Check nonrestricted. */
51342 /* Get last dispatch window. */
51347 {
51352 /* Window 1 is full. Go for next window. */
51354 }
51361 /* See if it fits in the first window. */
51363 {
51364 /* The first widow should have only single and double path
51365 uops. */
51371 }
51373 }
51375 /* Add an instruction INSN with NUM_UOPS micro-operations to the
51376 dispatch window WINDOW_LIST. */
51378 static void
51380 {
51398 /* Initialize window with new instruction. */
51419 {
51422 }
51423 }
51425 /* Adds a scheduled instruction, INSN, to the current dispatch window.
51426 If the total bytes of instructions or the number of instructions in
51427 the window exceed allowable, it allocates a new window. */
51429 static void
51431 {
51454 /* Get the last dispatch window. */
51462 else
51465 /* If current window is full, get a new window.
51466 Window number zero is full, if MAX_INSN uops are scheduled in it.
51467 Window number one is full, if window zero's bytes plus window
51468 one's bytes is 32, or if the bytes of the new instruction added
51469 to the total makes it greater than 48, or it has already MAX_INSN
51470 instructions in it. */
51479 {
51482 }
51485 {
51489 {
51492 }
51493 }
51495 {
51500 {
51503 }
51506 }
51507 else
51511 {
51512 /* End of basic block is reached do end-basic-block process. */
51515 }
51516 }
51518 /* Print the dispatch window, WINDOW_NUM, to FILE. */
51520 DEBUG_FUNCTION static void
51522 {
51528 else
51542 {
51545 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
51551 }
51552 }
51554 /* Print to stdout a dispatch window. */
51556 DEBUG_FUNCTION void
51558 {
51560 }
51562 /* Print INSN dispatch information to FILE. */
51564 DEBUG_FUNCTION static void
51566 {
51589 }
51591 /* Print to STDERR the status of the ready list with respect to
51592 dispatch windows. */
51594 DEBUG_FUNCTION void
51596 {
51604 }
51606 /* This routine is the driver of the dispatch scheduler. */
51608 static void
51610 {
51615 }
51617 /* Return TRUE if Dispatch Scheduling is supported. */
51619 static bool
51621 {
51625 {
51641 }
51644 }
51646 /* Implementation of reassociation_width target hook used by
51647 reassoc phase to identify parallelism level in reassociated
51648 tree. Statements tree_code is passed in OPC. Arguments type
51649 is passed in MODE.
51651 Currently parallel reassociation is enabled for Atom
51652 processors only and we set reassociation width to be 2
51653 because Atom may issue up to 2 instructions per cycle.
51655 Return value should be fixed if parallel reassociation is
51656 enabled for other processors. */
51658 static int
51660 {
51661 /* Vector part. */
51663 {
51666 else
51668 }
51670 /* Scalar part. */
51675 else
51677 }
51679 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
51680 place emms and femms instructions. */
51682 static machine_mode
51684 {
51689 {
51708 else
51720 /* FALLTHRU */
51724 }
51725 }
51727 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
51728 vectors. If AVX512F is enabled then try vectorizing with 512bit,
51729 256bit and 128bit vectors. */
51731 static unsigned int
51733 {
51736 }
51738 \f
51740 /* Return class of registers which could be used for pseudo of MODE
51741 and of class RCLASS for spilling instead of memory. Return NO_REGS
51742 if it is not possible or non-profitable. */
51743 static reg_class_t
51745 {
51751 }
51753 /* Implement targetm.vectorize.init_cost. */
51757 {
51761 }
51763 /* Implement targetm.vectorize.add_stmt_cost. */
51765 static unsigned
51769 {
51776 /* Statements in an inner loop relative to the loop being
51777 vectorized are weighted more heavily. The value here is
51778 arbitrary and could potentially be improved with analysis. */
51784 /* We need to multiply all vector stmt cost by 1.7 (estimated cost)
51785 for Silvermont as it has out of order integer pipeline and can execute
51786 2 scalar instruction per tick, but has in order SIMD pipeline. */
51789 {
51793 }
51798 }
51800 /* Implement targetm.vectorize.finish_cost. */
51802 static void
51805 {
51810 }
51812 /* Implement targetm.vectorize.destroy_cost_data. */
51814 static void
51816 {
51818 }
51820 /* Validate target specific memory model bits in VAL. */
51822 static unsigned HOST_WIDE_INT
51824 {
51831 {
51835 }
51838 {
51842 }
51844 {
51848 }
51850 }
51852 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
51853 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
51854 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
51855 or number of vecsize_mangle variants that should be emitted. */
51857 static int
51861 {
51868 {
51872 }
51877 {
51884 /* case SCmode: */
51885 /* case DCmode: */
51891 }
51893 tree t;
51897 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
51899 {
51906 /* case SCmode: */
51907 /* case DCmode: */
51913 }
51916 {
51917 /* Parse here processor clause. If not present, default to 'b'. */
51919 }
51921 {
51922 /* If the function isn't exported, we can pick up just one ISA
51923 for the clones. */
51928 else
51931 }
51932 else
51933 {
51936 }
51938 {
51951 }
51953 {
51956 else
51961 }
51963 }
51965 /* Add target attribute to SIMD clone NODE if needed. */
51967 static void
51969 {
51973 {
51988 }
51998 }
52000 /* If SIMD clone NODE can't be used in a vectorized loop
52001 in current function, return -1, otherwise return a badness of using it
52002 (0 if it is most desirable from vecsize_mangle point of view, 1
52003 slightly less desirable, etc.). */
52005 static int
52007 {
52009 {
52027 }
52028 }
52030 /* This function adjusts the unroll factor based on
52031 the hardware capabilities. For ex, bdver3 has
52032 a loop buffer which makes unrolling of smaller
52033 loops less important. This function decides the
52034 unroll factor using number of memory references
52035 (value 32 is used) as a heuristic. */
52037 static unsigned
52039 {
52048 /* Count the number of memory references within the loop body.
52049 This value determines the unrolling factor for bdver3 and bdver4
52050 architectures. */
52059 {
52064 else
52066 }
52073 }
52076 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
52078 static bool
52080 {
52081 /* For x87 floating point with standard excess precision handling,
52082 there is no adddf3 pattern (since x87 floating point only has
52083 XFmode operations) so the default hook implementation gets this
52084 wrong. */
52086 }
52088 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
52090 static void
52092 {
52097 {
52112 hold_fnclex);
52125 }
52127 {
52136 mxcsr_orig_var,
52146 ldmxcsr_hold_call);
52149 else
52154 ldmxcsr_clear_call);
52155 else
52159 stxmcsr_update_call);
52161 {
52167 exceptions_assign);
52168 }
52169 else
52174 ldmxcsr_update_call);
52175 }
52176 tree atomic_feraiseexcept
52181 atomic_feraiseexcept_call);
52182 }
52184 /* Return mode to be used for bounds or VOIDmode
52185 if bounds are not supported. */
52187 static enum machine_mode
52189 {
52190 /* Do not support pointer checker if MPX
52191 is not enabled. */
52193 {
52198 }
52201 }
52203 /* Return constant used to statically initialize constant bounds.
52205 This function is used to create special bound values. For now
52206 only INIT bounds and NONE bounds are expected. More special
52207 values may be added later. */
52209 static tree
52211 {
52217 /* This function is supposed to be used to create INIT and
52218 NONE bounds only. */
52223 }
52225 /* Generate a list of statements STMTS to initialize pointer bounds
52226 variable VAR with bounds LB and UB. Return the number of generated
52227 statements. */
52229 static int
52231 {
52249 }
52251 #if !TARGET_MACHO && !TARGET_DLLIMPORT_DECL_ATTRIBUTES
52252 /* For i386, common symbol is local only for non-PIE binaries. For
52253 x86-64, common symbol is local only for non-PIE binaries or linker
52254 supports copy reloc in PIE binaries. */
52256 static bool
52258 {
52260 (!flag_pic
52261 || (TARGET_64BIT
52263 }
52264 #endif
52266 /* If MEM is in the form of [base+offset], extract the two parts
52267 of address and set to BASE and OFFSET, otherwise return false. */
52269 static bool
52271 {
52272 rtx addr;
52282 {
52286 }
52292 {
52296 }
52299 }
52301 /* Given OPERANDS of consecutive load/store, check if we can merge
52302 them into move multiple. LOAD is true if they are load instructions.
52303 MODE is the mode of memory operands. */
52305 bool
52308 {
52313 {
52318 }
52319 else
52320 {
52325 }
52332 /* Check if the addresses are in the form of [base+offset]. */
52338 /* Check if the bases are the same. */
52345 /* Check if mem_1 is adjacent to mem_2 and mem_1 has lower address. */
52350 }
52352 /* Initialize the GCC target structure. */
52353 #undef TARGET_RETURN_IN_MEMORY
52354 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
52356 #undef TARGET_LEGITIMIZE_ADDRESS
52357 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
52359 #undef TARGET_ATTRIBUTE_TABLE
52360 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
52361 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
52362 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
52363 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
52364 # undef TARGET_MERGE_DECL_ATTRIBUTES
52365 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
52366 #endif
52368 #undef TARGET_COMP_TYPE_ATTRIBUTES
52369 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
52371 #undef TARGET_INIT_BUILTINS
52372 #define TARGET_INIT_BUILTINS ix86_init_builtins
52373 #undef TARGET_BUILTIN_DECL
52374 #define TARGET_BUILTIN_DECL ix86_builtin_decl
52375 #undef TARGET_EXPAND_BUILTIN
52376 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
52378 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
52379 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
52380 ix86_builtin_vectorized_function
52382 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
52383 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
52385 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
52386 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
52388 #undef TARGET_VECTORIZE_BUILTIN_GATHER
52389 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
52391 #undef TARGET_BUILTIN_RECIPROCAL
52392 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
52394 #undef TARGET_ASM_FUNCTION_EPILOGUE
52395 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
52397 #undef TARGET_ENCODE_SECTION_INFO
52398 #ifndef SUBTARGET_ENCODE_SECTION_INFO
52399 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
52400 #else
52401 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
52402 #endif
52404 #undef TARGET_ASM_OPEN_PAREN
52406 #undef TARGET_ASM_CLOSE_PAREN
52409 #undef TARGET_ASM_BYTE_OP
52410 #define TARGET_ASM_BYTE_OP ASM_BYTE
52412 #undef TARGET_ASM_ALIGNED_HI_OP
52413 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
52414 #undef TARGET_ASM_ALIGNED_SI_OP
52415 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
52416 #ifdef ASM_QUAD
52417 #undef TARGET_ASM_ALIGNED_DI_OP
52418 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
52419 #endif
52421 #undef TARGET_PROFILE_BEFORE_PROLOGUE
52422 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
52424 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
52425 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
52427 #undef TARGET_ASM_UNALIGNED_HI_OP
52428 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
52429 #undef TARGET_ASM_UNALIGNED_SI_OP
52430 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
52431 #undef TARGET_ASM_UNALIGNED_DI_OP
52432 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
52434 #undef TARGET_PRINT_OPERAND
52435 #define TARGET_PRINT_OPERAND ix86_print_operand
52436 #undef TARGET_PRINT_OPERAND_ADDRESS
52437 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
52438 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
52439 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
52440 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
52441 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
52443 #undef TARGET_SCHED_INIT_GLOBAL
52444 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
52445 #undef TARGET_SCHED_ADJUST_COST
52446 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
52447 #undef TARGET_SCHED_ISSUE_RATE
52448 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
52449 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
52450 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
52451 ia32_multipass_dfa_lookahead
52452 #undef TARGET_SCHED_MACRO_FUSION_P
52453 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
52454 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
52455 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
52457 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
52458 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
52460 #undef TARGET_MEMMODEL_CHECK
52461 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
52463 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
52464 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
52466 #ifdef HAVE_AS_TLS
52467 #undef TARGET_HAVE_TLS
52468 #define TARGET_HAVE_TLS true
52469 #endif
52470 #undef TARGET_CANNOT_FORCE_CONST_MEM
52471 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
52472 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
52473 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
52475 #undef TARGET_DELEGITIMIZE_ADDRESS
52476 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
52478 #undef TARGET_MS_BITFIELD_LAYOUT_P
52479 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
52481 #if TARGET_MACHO
52482 #undef TARGET_BINDS_LOCAL_P
52483 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
52484 #else
52485 #undef TARGET_BINDS_LOCAL_P
52486 #define TARGET_BINDS_LOCAL_P ix86_binds_local_p
52487 #endif
52488 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
52489 #undef TARGET_BINDS_LOCAL_P
52490 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
52491 #endif
52493 #undef TARGET_ASM_OUTPUT_MI_THUNK
52494 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
52495 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
52496 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
52498 #undef TARGET_ASM_FILE_START
52499 #define TARGET_ASM_FILE_START x86_file_start
52501 #undef TARGET_OPTION_OVERRIDE
52502 #define TARGET_OPTION_OVERRIDE ix86_option_override
52504 #undef TARGET_REGISTER_MOVE_COST
52505 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
52506 #undef TARGET_MEMORY_MOVE_COST
52507 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
52508 #undef TARGET_RTX_COSTS
52509 #define TARGET_RTX_COSTS ix86_rtx_costs
52510 #undef TARGET_ADDRESS_COST
52511 #define TARGET_ADDRESS_COST ix86_address_cost
52513 #undef TARGET_FIXED_CONDITION_CODE_REGS
52514 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
52515 #undef TARGET_CC_MODES_COMPATIBLE
52516 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
52518 #undef TARGET_MACHINE_DEPENDENT_REORG
52519 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
52521 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
52522 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
52524 #undef TARGET_BUILD_BUILTIN_VA_LIST
52525 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
52527 #undef TARGET_FOLD_BUILTIN
52528 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
52530 #undef TARGET_COMPARE_VERSION_PRIORITY
52531 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
52533 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
52534 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
52535 ix86_generate_version_dispatcher_body
52537 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
52538 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
52539 ix86_get_function_versions_dispatcher
52541 #undef TARGET_ENUM_VA_LIST_P
52542 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
52544 #undef TARGET_FN_ABI_VA_LIST
52545 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
52547 #undef TARGET_CANONICAL_VA_LIST_TYPE
52548 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
52550 #undef TARGET_EXPAND_BUILTIN_VA_START
52551 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
52553 #undef TARGET_MD_ASM_ADJUST
52554 #define TARGET_MD_ASM_ADJUST ix86_md_asm_adjust
52556 #undef TARGET_PROMOTE_PROTOTYPES
52557 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
52558 #undef TARGET_SETUP_INCOMING_VARARGS
52559 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
52560 #undef TARGET_MUST_PASS_IN_STACK
52561 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
52562 #undef TARGET_FUNCTION_ARG_ADVANCE
52563 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
52564 #undef TARGET_FUNCTION_ARG
52565 #define TARGET_FUNCTION_ARG ix86_function_arg
52566 #undef TARGET_INIT_PIC_REG
52567 #define TARGET_INIT_PIC_REG ix86_init_pic_reg
52568 #undef TARGET_USE_PSEUDO_PIC_REG
52569 #define TARGET_USE_PSEUDO_PIC_REG ix86_use_pseudo_pic_reg
52570 #undef TARGET_FUNCTION_ARG_BOUNDARY
52571 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
52572 #undef TARGET_PASS_BY_REFERENCE
52573 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
52574 #undef TARGET_INTERNAL_ARG_POINTER
52575 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
52576 #undef TARGET_UPDATE_STACK_BOUNDARY
52577 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
52578 #undef TARGET_GET_DRAP_RTX
52579 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
52580 #undef TARGET_STRICT_ARGUMENT_NAMING
52581 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
52582 #undef TARGET_STATIC_CHAIN
52583 #define TARGET_STATIC_CHAIN ix86_static_chain
52584 #undef TARGET_TRAMPOLINE_INIT
52585 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
52586 #undef TARGET_RETURN_POPS_ARGS
52587 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
52589 #undef TARGET_LEGITIMATE_COMBINED_INSN
52590 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
52592 #undef TARGET_ASAN_SHADOW_OFFSET
52593 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
52595 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
52596 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
52598 #undef TARGET_SCALAR_MODE_SUPPORTED_P
52599 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
52601 #undef TARGET_VECTOR_MODE_SUPPORTED_P
52602 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
52604 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
52605 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
52606 ix86_libgcc_floating_mode_supported_p
52608 #undef TARGET_C_MODE_FOR_SUFFIX
52609 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
52611 #ifdef HAVE_AS_TLS
52612 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
52613 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
52614 #endif
52616 #ifdef SUBTARGET_INSERT_ATTRIBUTES
52617 #undef TARGET_INSERT_ATTRIBUTES
52618 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
52619 #endif
52621 #undef TARGET_MANGLE_TYPE
52622 #define TARGET_MANGLE_TYPE ix86_mangle_type
52624 #if !TARGET_MACHO
52625 #undef TARGET_STACK_PROTECT_FAIL
52626 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
52627 #endif
52629 #undef TARGET_FUNCTION_VALUE
52630 #define TARGET_FUNCTION_VALUE ix86_function_value
52632 #undef TARGET_FUNCTION_VALUE_REGNO_P
52633 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
52635 #undef TARGET_PROMOTE_FUNCTION_MODE
52636 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
52638 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
52639 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ix86_override_options_after_change
52641 #undef TARGET_MEMBER_TYPE_FORCES_BLK
52642 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
52644 #undef TARGET_INSTANTIATE_DECLS
52645 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
52647 #undef TARGET_SECONDARY_RELOAD
52648 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
52650 #undef TARGET_CLASS_MAX_NREGS
52651 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
52653 #undef TARGET_PREFERRED_RELOAD_CLASS
52654 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
52655 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
52656 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
52657 #undef TARGET_CLASS_LIKELY_SPILLED_P
52658 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
52660 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
52661 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
52662 ix86_builtin_vectorization_cost
52663 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
52664 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
52665 ix86_vectorize_vec_perm_const_ok
52666 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
52667 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
52668 ix86_preferred_simd_mode
52669 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
52670 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
52671 ix86_autovectorize_vector_sizes
52672 #undef TARGET_VECTORIZE_INIT_COST
52673 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
52674 #undef TARGET_VECTORIZE_ADD_STMT_COST
52675 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
52676 #undef TARGET_VECTORIZE_FINISH_COST
52677 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
52678 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
52679 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
52681 #undef TARGET_SET_CURRENT_FUNCTION
52682 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
52684 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
52685 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
52687 #undef TARGET_OPTION_SAVE
52688 #define TARGET_OPTION_SAVE ix86_function_specific_save
52690 #undef TARGET_OPTION_RESTORE
52691 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
52693 #undef TARGET_OPTION_POST_STREAM_IN
52694 #define TARGET_OPTION_POST_STREAM_IN ix86_function_specific_post_stream_in
52696 #undef TARGET_OPTION_PRINT
52697 #define TARGET_OPTION_PRINT ix86_function_specific_print
52699 #undef TARGET_OPTION_FUNCTION_VERSIONS
52700 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
52702 #undef TARGET_CAN_INLINE_P
52703 #define TARGET_CAN_INLINE_P ix86_can_inline_p
52705 #undef TARGET_EXPAND_TO_RTL_HOOK
52706 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
52708 #undef TARGET_LEGITIMATE_ADDRESS_P
52709 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
52711 #undef TARGET_LRA_P
52712 #define TARGET_LRA_P hook_bool_void_true
52714 #undef TARGET_REGISTER_PRIORITY
52715 #define TARGET_REGISTER_PRIORITY ix86_register_priority
52717 #undef TARGET_REGISTER_USAGE_LEVELING_P
52718 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
52720 #undef TARGET_LEGITIMATE_CONSTANT_P
52721 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
52723 #undef TARGET_FRAME_POINTER_REQUIRED
52724 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
52726 #undef TARGET_CAN_ELIMINATE
52727 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
52729 #undef TARGET_EXTRA_LIVE_ON_ENTRY
52730 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
52732 #undef TARGET_ASM_CODE_END
52733 #define TARGET_ASM_CODE_END ix86_code_end
52735 #undef TARGET_CONDITIONAL_REGISTER_USAGE
52736 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
52738 #if TARGET_MACHO
52739 #undef TARGET_INIT_LIBFUNCS
52740 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
52741 #endif
52743 #undef TARGET_LOOP_UNROLL_ADJUST
52744 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
52746 #undef TARGET_SPILL_CLASS
52747 #define TARGET_SPILL_CLASS ix86_spill_class
52749 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
52750 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
52751 ix86_simd_clone_compute_vecsize_and_simdlen
52753 #undef TARGET_SIMD_CLONE_ADJUST
52754 #define TARGET_SIMD_CLONE_ADJUST \
52755 ix86_simd_clone_adjust
52757 #undef TARGET_SIMD_CLONE_USABLE
52758 #define TARGET_SIMD_CLONE_USABLE \
52759 ix86_simd_clone_usable
52761 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
52762 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
52763 ix86_float_exceptions_rounding_supported_p
52765 #undef TARGET_MODE_EMIT
52766 #define TARGET_MODE_EMIT ix86_emit_mode_set
52768 #undef TARGET_MODE_NEEDED
52769 #define TARGET_MODE_NEEDED ix86_mode_needed
52771 #undef TARGET_MODE_AFTER
52772 #define TARGET_MODE_AFTER ix86_mode_after
52774 #undef TARGET_MODE_ENTRY
52775 #define TARGET_MODE_ENTRY ix86_mode_entry
52777 #undef TARGET_MODE_EXIT
52778 #define TARGET_MODE_EXIT ix86_mode_exit
52780 #undef TARGET_MODE_PRIORITY
52781 #define TARGET_MODE_PRIORITY ix86_mode_priority
52783 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
52784 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
52786 #undef TARGET_LOAD_BOUNDS_FOR_ARG
52787 #define TARGET_LOAD_BOUNDS_FOR_ARG ix86_load_bounds
52789 #undef TARGET_STORE_BOUNDS_FOR_ARG
52790 #define TARGET_STORE_BOUNDS_FOR_ARG ix86_store_bounds
52792 #undef TARGET_LOAD_RETURNED_BOUNDS
52793 #define TARGET_LOAD_RETURNED_BOUNDS ix86_load_returned_bounds
52795 #undef TARGET_STORE_RETURNED_BOUNDS
52796 #define TARGET_STORE_RETURNED_BOUNDS ix86_store_returned_bounds
52798 #undef TARGET_CHKP_BOUND_MODE
52799 #define TARGET_CHKP_BOUND_MODE ix86_mpx_bound_mode
52801 #undef TARGET_BUILTIN_CHKP_FUNCTION
52802 #define TARGET_BUILTIN_CHKP_FUNCTION ix86_builtin_mpx_function
52804 #undef TARGET_CHKP_FUNCTION_VALUE_BOUNDS
52805 #define TARGET_CHKP_FUNCTION_VALUE_BOUNDS ix86_function_value_bounds
52807 #undef TARGET_CHKP_MAKE_BOUNDS_CONSTANT
52808 #define TARGET_CHKP_MAKE_BOUNDS_CONSTANT ix86_make_bounds_constant
52810 #undef TARGET_CHKP_INITIALIZE_BOUNDS
52811 #define TARGET_CHKP_INITIALIZE_BOUNDS ix86_initialize_bounds
52813 #undef TARGET_SETUP_INCOMING_VARARG_BOUNDS
52814 #define TARGET_SETUP_INCOMING_VARARG_BOUNDS ix86_setup_incoming_vararg_bounds
52816 #undef TARGET_OFFLOAD_OPTIONS
52817 #define TARGET_OFFLOAD_OPTIONS \
52818 ix86_offload_options
52820 #undef TARGET_ABSOLUTE_BIGGEST_ALIGNMENT
52821 #define TARGET_ABSOLUTE_BIGGEST_ALIGNMENT 512
52824 \f