| blob | 253f4968d12a09fe69f3a0d82f896115b0a92c47 |
1 ;; Instruction Classification for ARM for GNU compiler.
3 ;; Copyright (C) 1991-2017 Free Software Foundation, Inc.
4 ;; Contributed by ARM Ltd.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it
9 ;; under the terms of the GNU General Public License as published
10 ;; by the Free Software Foundation; either version 3, or (at your
11 ;; option) any later version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ; TYPE attribute is used to classify instructions for use in scheduling.
23 ;
24 ; Instruction classification:
25 ;
26 ; adc_imm add/subtract with carry and with an immediate operand.
27 ; adc_reg add/subtract with carry and no immediate operand.
28 ; adcs_imm as adc_imm, setting condition flags.
29 ; adcs_reg as adc_reg, setting condition flags.
30 ; adr calculate address.
31 ; alu_ext From ARMv8-A: any arithmetic instruction that has a
32 ; sign/zero-extended.
33 ; AArch64 Only.
34 ; source operand
35 ; alu_imm any arithmetic instruction that doesn't have a shifted
36 ; operand and has an immediate operand. This
37 ; excludes MOV, MVN and RSB(S) immediate.
38 ; alu_sreg any arithmetic instruction that doesn't have a shifted
39 ; or an immediate operand. This excludes
40 ; MOV and MVN but includes MOVT. This also excludes
41 ; DSP-kind instructions. This is also the default.
42 ; alu_shift_imm any arithmetic instruction that has a source operand
43 ; shifted by a constant. This excludes simple shifts.
44 ; alu_shift_reg as alu_shift_imm, with the shift amount specified in a
45 ; register.
46 ; alu_dsp_reg any DSP-kind instruction like QSUB8.
47 ; alus_ext From ARMv8-A: as alu_ext, setting condition flags.
48 ; AArch64 Only.
49 ; alus_imm as alu_imm, setting condition flags.
50 ; alus_sreg as alu_sreg, setting condition flags.
51 ; alus_shift_imm as alu_shift_imm, setting condition flags.
52 ; alus_shift_reg as alu_shift_reg, setting condition flags.
53 ; bfm bitfield move operation.
54 ; bfx bitfield extract operation.
55 ; block blockage insn, this blocks all functional units.
56 ; branch branch.
57 ; call subroutine call.
58 ; clz count leading zeros (CLZ).
59 ; csel From ARMv8-A: conditional select.
60 ; extend extend instruction (SXTB, SXTH, UXTB, UXTH).
61 ; f_cvt conversion between float representations.
62 ; f_cvtf2i conversion between float and integral types.
63 ; f_cvti2f conversion between integral and float types.
64 ; f_flag transfer of co-processor flags to the CPSR.
65 ; f_load[d,s] double/single load from memory. Used for VFP unit.
66 ; f_mcr transfer arm to vfp reg.
67 ; f_mcrr transfer two arm regs to vfp reg.
68 ; f_minmax[d,s] double/single floating point minimum/maximum.
69 ; f_mrc transfer vfp to arm reg.
70 ; f_mrrc transfer vfp to two arm regs.
71 ; f_rint[d,s] double/single floating point rount to integral.
72 ; f_store[d,s] double/single store to memory. Used for VFP unit.
73 ; fadd[d,s] double/single floating-point scalar addition.
74 ; fccmp[d,s] From ARMv8-A: floating-point conditional compare.
75 ; fcmp[d,s] double/single floating-point compare.
76 ; fconst[d,s] double/single load immediate.
77 ; fcsel From ARMv8-A: Floating-point conditional select.
78 ; fdiv[d,s] double/single precision floating point division.
79 ; ffarith[d,s] double/single floating point abs/neg/cpy.
80 ; ffma[d,s] double/single floating point fused multiply-accumulate.
81 ; float floating point arithmetic operation.
82 ; fmac[d,s] double/single floating point multiply-accumulate.
83 ; fmov floating point to floating point register move.
84 ; fmul[d,s] double/single floating point multiply.
85 ; fsqrt[d,s] double/single precision floating point square root.
86 ; load_acq load-acquire.
87 ; load_byte load byte(s) from memory to arm registers.
88 ; load1 load 1 word from memory to arm registers.
89 ; load2 load 2 words from memory to arm registers.
90 ; load3 load 3 words from memory to arm registers.
91 ; load4 load 4 words from memory to arm registers.
92 ; logic_imm any logical instruction that doesn't have a shifted
93 ; operand and has an immediate operand.
94 ; logic_reg any logical instruction that doesn't have a shifted
95 ; operand or an immediate operand.
96 ; logic_shift_imm any logical instruction that has a source operand
97 ; shifted by a constant. This excludes simple shifts.
98 ; logic_shift_reg as logic_shift_imm, with the shift amount specified in a
99 ; register.
100 ; logics_imm as logic_imm, setting condition flags.
101 ; logics_reg as logic_reg, setting condition flags.
102 ; logics_shift_imm as logic_shift_imm, setting condition flags.
103 ; logics_shift_reg as logic_shift_reg, setting condition flags.
104 ; mla integer multiply accumulate.
105 ; mlas integer multiply accumulate, flag setting.
106 ; mov_imm simple MOV instruction that moves an immediate to
107 ; register. This includes MOVW, but not MOVT.
108 ; mov_reg simple MOV instruction that moves a register to another
109 ; register. This includes MOVW, but not MOVT.
110 ; mov_shift simple MOV instruction, shifted operand by a constant.
111 ; mov_shift_reg simple MOV instruction, shifted operand by a register.
112 ; mrs system/special/co-processor register move.
113 ; mul integer multiply.
114 ; muls integer multiply, flag setting.
115 ; multiple more than one instruction, candidate for future
116 ; splitting, or better modeling.
117 ; mvn_imm inverting move instruction, immediate.
118 ; mvn_reg inverting move instruction, register.
119 ; mvn_shift inverting move instruction, shifted operand by a constant.
120 ; mvn_shift_reg inverting move instruction, shifted operand by a register.
121 ; no_insn an insn which does not represent an instruction in the
122 ; final output, thus having no impact on scheduling.
123 ; rbit reverse bits.
124 ; rev reverse bytes.
125 ; rotate_imm rotate by immediate.
126 ; sdiv signed division.
127 ; shift_imm simple shift operation (LSL, LSR, ASR, ROR) with an
128 ; immediate.
129 ; shift_reg simple shift by a register.
130 ; smlad signed multiply accumulate dual.
131 ; smladx signed multiply accumulate dual reverse.
132 ; smlal signed multiply accumulate long.
133 ; smlald signed multiply accumulate long dual.
134 ; smlals signed multiply accumulate long, flag setting.
135 ; smlalxy signed multiply accumulate, 16x16-bit, 64-bit accumulate.
136 ; smlawx signed multiply accumulate, 32x16-bit, 32-bit accumulate.
137 ; smlawy signed multiply accumulate wide, 32x16-bit,
138 ; 32-bit accumulate.
139 ; smlaxy signed multiply accumulate, 16x16-bit, 32-bit accumulate.
140 ; smlsd signed multiply subtract dual.
141 ; smlsdx signed multiply subtract dual reverse.
142 ; smlsld signed multiply subtract long dual.
143 ; smmla signed most significant word multiply accumulate.
144 ; smmul signed most significant word multiply.
145 ; smmulr signed most significant word multiply, rounded.
146 ; smuad signed dual multiply add.
147 ; smuadx signed dual multiply add reverse.
148 ; smull signed multiply long.
149 ; smulls signed multiply long, flag setting.
150 ; smulwy signed multiply wide, 32x16-bit, 32-bit accumulate.
151 ; smulxy signed multiply, 16x16-bit, 32-bit accumulate.
152 ; smusd signed dual multiply subtract.
153 ; smusdx signed dual multiply subtract reverse.
154 ; store_rel store-release.
155 ; store1 store 1 word to memory from arm registers.
156 ; store2 store 2 words to memory from arm registers.
157 ; store3 store 3 words to memory from arm registers.
158 ; store4 store 4 (or more) words to memory from arm registers.
159 ; trap cause a trap in the kernel.
160 ; udiv unsigned division.
161 ; umaal unsigned multiply accumulate accumulate long.
162 ; umlal unsigned multiply accumulate long.
163 ; umlals unsigned multiply accumulate long, flag setting.
164 ; umull unsigned multiply long.
165 ; umulls unsigned multiply long, flag setting.
166 ; untyped insn without type information - default, and error,
167 ; case.
168 ;
169 ; The classification below is for instructions used by the Wireless MMX
170 ; Technology. Each attribute value is used to classify an instruction of the
171 ; same name or family.
172 ;
173 ; wmmx_tandc
174 ; wmmx_tbcst
175 ; wmmx_textrc
176 ; wmmx_textrm
177 ; wmmx_tinsr
178 ; wmmx_tmcr
179 ; wmmx_tmcrr
180 ; wmmx_tmia
181 ; wmmx_tmiaph
182 ; wmmx_tmiaxy
183 ; wmmx_tmrc
184 ; wmmx_tmrrc
185 ; wmmx_tmovmsk
186 ; wmmx_torc
187 ; wmmx_torvsc
188 ; wmmx_wabs
189 ; wmmx_wdiff
190 ; wmmx_wacc
191 ; wmmx_wadd
192 ; wmmx_waddbhus
193 ; wmmx_waddsubhx
194 ; wmmx_waligni
195 ; wmmx_walignr
196 ; wmmx_wand
197 ; wmmx_wandn
198 ; wmmx_wavg2
199 ; wmmx_wavg4
200 ; wmmx_wcmpeq
201 ; wmmx_wcmpgt
202 ; wmmx_wmac
203 ; wmmx_wmadd
204 ; wmmx_wmax
205 ; wmmx_wmerge
206 ; wmmx_wmiawxy
207 ; wmmx_wmiaxy
208 ; wmmx_wmin
209 ; wmmx_wmov
210 ; wmmx_wmul
211 ; wmmx_wmulw
212 ; wmmx_wldr
213 ; wmmx_wor
214 ; wmmx_wpack
215 ; wmmx_wqmiaxy
216 ; wmmx_wqmulm
217 ; wmmx_wqmulwm
218 ; wmmx_wror
219 ; wmmx_wsad
220 ; wmmx_wshufh
221 ; wmmx_wsll
222 ; wmmx_wsra
223 ; wmmx_wsrl
224 ; wmmx_wstr
225 ; wmmx_wsub
226 ; wmmx_wsubaddhx
227 ; wmmx_wunpckeh
228 ; wmmx_wunpckel
229 ; wmmx_wunpckih
230 ; wmmx_wunpckil
231 ; wmmx_wxor
232 ;
233 ; The classification below is for NEON instructions.
234 ;
235 ; neon_add
236 ; neon_add_q
237 ; neon_add_widen
238 ; neon_add_long
239 ; neon_qadd
240 ; neon_qadd_q
241 ; neon_add_halve
242 ; neon_add_halve_q
243 ; neon_add_halve_narrow_q
244 ; neon_sub
245 ; neon_sub_q
246 ; neon_sub_widen
247 ; neon_sub_long
248 ; neon_qsub
249 ; neon_qsub_q
250 ; neon_sub_halve
251 ; neon_sub_halve_q
252 ; neon_sub_halve_narrow_q
253 ; neon_abs
254 ; neon_abs_q
255 ; neon_neg
256 ; neon_neg_q
257 ; neon_qneg
258 ; neon_qneg_q
259 ; neon_qabs
260 ; neon_qabs_q
261 ; neon_abd
262 ; neon_abd_q
263 ; neon_abd_long
264 ; neon_minmax
265 ; neon_minmax_q
266 ; neon_compare
267 ; neon_compare_q
268 ; neon_compare_zero
269 ; neon_compare_zero_q
270 ; neon_arith_acc
271 ; neon_arith_acc_q
272 ; neon_reduc_add
273 ; neon_reduc_add_q
274 ; neon_reduc_add_long
275 ; neon_reduc_add_acc
276 ; neon_reduc_add_acc_q
277 ; neon_reduc_minmax
278 ; neon_reduc_minmax_q
279 ; neon_logic
280 ; neon_logic_q
281 ; neon_tst
282 ; neon_tst_q
283 ; neon_shift_imm
284 ; neon_shift_imm_q
285 ; neon_shift_imm_narrow_q
286 ; neon_shift_imm_long
287 ; neon_shift_reg
288 ; neon_shift_reg_q
289 ; neon_shift_acc
290 ; neon_shift_acc_q
291 ; neon_sat_shift_imm
292 ; neon_sat_shift_imm_q
293 ; neon_sat_shift_imm_narrow_q
294 ; neon_sat_shift_reg
295 ; neon_sat_shift_reg_q
296 ; neon_ins
297 ; neon_ins_q
298 ; neon_move
299 ; neon_move_q
300 ; neon_move_narrow_q
301 ; neon_permute
302 ; neon_permute_q
303 ; neon_zip
304 ; neon_zip_q
305 ; neon_tbl1
306 ; neon_tbl1_q
307 ; neon_tbl2
308 ; neon_tbl2_q
309 ; neon_tbl3
310 ; neon_tbl3_q
311 ; neon_tbl4
312 ; neon_tbl4_q
313 ; neon_bsl
314 ; neon_bsl_q
315 ; neon_cls
316 ; neon_cls_q
317 ; neon_cnt
318 ; neon_cnt_q
319 ; neon_ext
320 ; neon_ext_q
321 ; neon_rbit
322 ; neon_rbit_q
323 ; neon_rev
324 ; neon_rev_q
325 ; neon_mul_b
326 ; neon_mul_b_q
327 ; neon_mul_h
328 ; neon_mul_h_q
329 ; neon_mul_s
330 ; neon_mul_s_q
331 ; neon_mul_b_long
332 ; neon_mul_h_long
333 ; neon_mul_s_long
334 ; neon_mul_d_long
335 ; neon_mul_h_scalar
336 ; neon_mul_h_scalar_q
337 ; neon_mul_s_scalar
338 ; neon_mul_s_scalar_q
339 ; neon_mul_h_scalar_long
340 ; neon_mul_s_scalar_long
341 ; neon_sat_mul_b
342 ; neon_sat_mul_b_q
343 ; neon_sat_mul_h
344 ; neon_sat_mul_h_q
345 ; neon_sat_mul_s
346 ; neon_sat_mul_s_q
347 ; neon_sat_mul_b_long
348 ; neon_sat_mul_h_long
349 ; neon_sat_mul_s_long
350 ; neon_sat_mul_h_scalar
351 ; neon_sat_mul_h_scalar_q
352 ; neon_sat_mul_s_scalar
353 ; neon_sat_mul_s_scalar_q
354 ; neon_sat_mul_h_scalar_long
355 ; neon_sat_mul_s_scalar_long
356 ; neon_mla_b
357 ; neon_mla_b_q
358 ; neon_mla_h
359 ; neon_mla_h_q
360 ; neon_mla_s
361 ; neon_mla_s_q
362 ; neon_mla_b_long
363 ; neon_mla_h_long
364 ; neon_mla_s_long
365 ; neon_mla_h_scalar
366 ; neon_mla_h_scalar_q
367 ; neon_mla_s_scalar
368 ; neon_mla_s_scalar_q
369 ; neon_mla_h_scalar_long
370 ; neon_mla_s_scalar_long
371 ; neon_sat_mla_b_long
372 ; neon_sat_mla_h_long
373 ; neon_sat_mla_s_long
374 ; neon_sat_mla_h_scalar_long
375 ; neon_sat_mla_s_scalar_long
376 ; neon_to_gp
377 ; neon_to_gp_q
378 ; neon_from_gp
379 ; neon_from_gp_q
380 ; neon_ldr
381 ; neon_ldp
382 ; neon_ldp_q
383 ; neon_load1_1reg
384 ; neon_load1_1reg_q
385 ; neon_load1_2reg
386 ; neon_load1_2reg_q
387 ; neon_load1_3reg
388 ; neon_load1_3reg_q
389 ; neon_load1_4reg
390 ; neon_load1_4reg_q
391 ; neon_load1_all_lanes
392 ; neon_load1_all_lanes_q
393 ; neon_load1_one_lane
394 ; neon_load1_one_lane_q
395 ; neon_load2_2reg
396 ; neon_load2_2reg_q
397 ; neon_load2_4reg
398 ; neon_load2_4reg_q
399 ; neon_load2_all_lanes
400 ; neon_load2_all_lanes_q
401 ; neon_load2_one_lane
402 ; neon_load2_one_lane_q
403 ; neon_load3_3reg
404 ; neon_load3_3reg_q
405 ; neon_load3_all_lanes
406 ; neon_load3_all_lanes_q
407 ; neon_load3_one_lane
408 ; neon_load3_one_lane_q
409 ; neon_load4_4reg
410 ; neon_load4_4reg_q
411 ; neon_load4_all_lanes
412 ; neon_load4_all_lanes_q
413 ; neon_load4_one_lane
414 ; neon_load4_one_lane_q
415 ; neon_str
416 ; neon_stp
417 ; neon_stp_q
418 ; neon_store1_1reg
419 ; neon_store1_1reg_q
420 ; neon_store1_2reg
421 ; neon_store1_2reg_q
422 ; neon_store1_3reg
423 ; neon_store1_3reg_q
424 ; neon_store1_4reg
425 ; neon_store1_4reg_q
426 ; neon_store1_one_lane
427 ; neon_store1_one_lane_q
428 ; neon_store2_2reg
429 ; neon_store2_2reg_q
430 ; neon_store2_4reg
431 ; neon_store2_4reg_q
432 ; neon_store2_one_lane
433 ; neon_store2_one_lane_q
434 ; neon_store3_3reg
435 ; neon_store3_3reg_q
436 ; neon_store3_one_lane
437 ; neon_store3_one_lane_q
438 ; neon_store4_4reg
439 ; neon_store4_4reg_q
440 ; neon_store4_one_lane
441 ; neon_store4_one_lane_q
442 ; neon_fp_abs_s
443 ; neon_fp_abs_s_q
444 ; neon_fp_abs_d
445 ; neon_fp_abs_d_q
446 ; neon_fp_neg_s
447 ; neon_fp_neg_s_q
448 ; neon_fp_neg_d
449 ; neon_fp_neg_d_q
450 ; neon_fp_abd_s
451 ; neon_fp_abd_s_q
452 ; neon_fp_abd_d
453 ; neon_fp_abd_d_q
454 ; neon_fp_addsub_s
455 ; neon_fp_addsub_s_q
456 ; neon_fp_addsub_d
457 ; neon_fp_addsub_d_q
458 ; neon_fp_compare_s
459 ; neon_fp_compare_s_q
460 ; neon_fp_compare_d
461 ; neon_fp_compare_d_q
462 ; neon_fp_minmax_s
463 ; neon_fp_minmax_s_q
464 ; neon_fp_minmax_d
465 ; neon_fp_minmax_d_q
466 ; neon_fp_reduc_add_s
467 ; neon_fp_reduc_add_s_q
468 ; neon_fp_reduc_add_d
469 ; neon_fp_reduc_add_d_q
470 ; neon_fp_reduc_minmax_s
471 ; neon_fp_reduc_minmax_s_q
472 ; neon_fp_reduc_minmax_d
473 ; neon_fp_reduc_minmax_d_q
474 ; neon_fp_cvt_narrow_s_q
475 ; neon_fp_cvt_narrow_d_q
476 ; neon_fp_cvt_widen_h
477 ; neon_fp_cvt_widen_s
478 ; neon_fp_to_int_s
479 ; neon_fp_to_int_s_q
480 ; neon_fp_to_int_d
481 ; neon_fp_to_int_d_q
482 ; neon_int_to_fp_s
483 ; neon_int_to_fp_s_q
484 ; neon_int_to_fp_d
485 ; neon_int_to_fp_d_q
486 ; neon_fp_round_s
487 ; neon_fp_round_s_q
488 ; neon_fp_round_d
489 ; neon_fp_round_d_q
490 ; neon_fp_recpe_s
491 ; neon_fp_recpe_s_q
492 ; neon_fp_recpe_d
493 ; neon_fp_recpe_d_q
494 ; neon_fp_recps_s
495 ; neon_fp_recps_s_q
496 ; neon_fp_recps_d
497 ; neon_fp_recps_d_q
498 ; neon_fp_recpx_s
499 ; neon_fp_recpx_s_q
500 ; neon_fp_recpx_d
501 ; neon_fp_recpx_d_q
502 ; neon_fp_rsqrte_s
503 ; neon_fp_rsqrte_s_q
504 ; neon_fp_rsqrte_d
505 ; neon_fp_rsqrte_d_q
506 ; neon_fp_rsqrts_s
507 ; neon_fp_rsqrts_s_q
508 ; neon_fp_rsqrts_d
509 ; neon_fp_rsqrts_d_q
510 ; neon_fp_mul_s
511 ; neon_fp_mul_s_q
512 ; neon_fp_mul_s_scalar
513 ; neon_fp_mul_s_scalar_q
514 ; neon_fp_mul_d
515 ; neon_fp_mul_d_q
516 ; neon_fp_mul_d_scalar_q
517 ; neon_fp_mla_s
518 ; neon_fp_mla_s_q
519 ; neon_fp_mla_s_scalar
520 ; neon_fp_mla_s_scalar_q
521 ; neon_fp_mla_d
522 ; neon_fp_mla_d_q
523 ; neon_fp_mla_d_scalar_q
524 ; neon_fp_sqrt_s
525 ; neon_fp_sqrt_s_q
526 ; neon_fp_sqrt_d
527 ; neon_fp_sqrt_d_q
528 ; neon_fp_div_s
529 ; neon_fp_div_s_q
530 ; neon_fp_div_d
531 ; neon_fp_div_d_q
532 ;
533 ; The classification below is for Crypto instructions.
534 ;
535 ; crypto_aese
536 ; crypto_aesmc
537 ; crypto_sha1_xor
538 ; crypto_sha1_fast
539 ; crypto_sha1_slow
540 ; crypto_sha256_fast
541 ; crypto_sha256_slow
542 ; crypto_pmull
543 ;
544 ; The classification below is for coprocessor instructions
545 ;
546 ; coproc
548 (define_attr "type"
549 "adc_imm,\
550 adc_reg,\
551 adcs_imm,\
552 adcs_reg,\
553 adr,\
554 alu_ext,\
555 alu_imm,\
556 alu_sreg,\
557 alu_shift_imm,\
558 alu_shift_reg,\
559 alu_dsp_reg,\
560 alus_ext,\
561 alus_imm,\
562 alus_sreg,\
563 alus_shift_imm,\
564 alus_shift_reg,\
565 bfm,\
566 bfx,\
567 block,\
568 branch,\
569 call,\
570 clz,\
571 no_insn,\
572 csel,\
573 crc,\
574 extend,\
575 f_cvt,\
576 f_cvtf2i,\
577 f_cvti2f,\
578 f_flag,\
579 f_loadd,\
580 f_loads,\
581 f_mcr,\
582 f_mcrr,\
583 f_minmaxd,\
584 f_minmaxs,\
585 f_mrc,\
586 f_mrrc,\
587 f_rintd,\
588 f_rints,\
589 f_stored,\
590 f_stores,\
591 faddd,\
592 fadds,\
593 fccmpd,\
594 fccmps,\
595 fcmpd,\
596 fcmps,\
597 fconstd,\
598 fconsts,\
599 fcsel,\
600 fdivd,\
601 fdivs,\
602 ffarithd,\
603 ffariths,\
604 ffmad,\
605 ffmas,\
606 float,\
607 fmacd,\
608 fmacs,\
609 fmov,\
610 fmuld,\
611 fmuls,\
612 fsqrts,\
613 fsqrtd,\
614 load_acq,\
615 load_byte,\
616 load1,\
617 load2,\
618 load3,\
619 load4,\
620 logic_imm,\
621 logic_reg,\
622 logic_shift_imm,\
623 logic_shift_reg,\
624 logics_imm,\
625 logics_reg,\
626 logics_shift_imm,\
627 logics_shift_reg,\
628 mla,\
629 mlas,\
630 mov_imm,\
631 mov_reg,\
632 mov_shift,\
633 mov_shift_reg,\
634 mrs,\
635 mul,\
636 muls,\
637 multiple,\
638 mvn_imm,\
639 mvn_reg,\
640 mvn_shift,\
641 mvn_shift_reg,\
642 nop,\
643 rbit,\
644 rev,\
645 rotate_imm,\
646 sdiv,\
647 shift_imm,\
648 shift_reg,\
649 smlad,\
650 smladx,\
651 smlal,\
652 smlald,\
653 smlals,\
654 smlalxy,\
655 smlawx,\
656 smlawy,\
657 smlaxy,\
658 smlsd,\
659 smlsdx,\
660 smlsld,\
661 smmla,\
662 smmul,\
663 smmulr,\
664 smuad,\
665 smuadx,\
666 smull,\
667 smulls,\
668 smulwy,\
669 smulxy,\
670 smusd,\
671 smusdx,\
672 store_rel,\
673 store1,\
674 store2,\
675 store3,\
676 store4,\
677 trap,\
678 udiv,\
679 umaal,\
680 umlal,\
681 umlals,\
682 umull,\
683 umulls,\
684 untyped,\
685 wmmx_tandc,\
686 wmmx_tbcst,\
687 wmmx_textrc,\
688 wmmx_textrm,\
689 wmmx_tinsr,\
690 wmmx_tmcr,\
691 wmmx_tmcrr,\
692 wmmx_tmia,\
693 wmmx_tmiaph,\
694 wmmx_tmiaxy,\
695 wmmx_tmrc,\
696 wmmx_tmrrc,\
697 wmmx_tmovmsk,\
698 wmmx_torc,\
699 wmmx_torvsc,\
700 wmmx_wabs,\
701 wmmx_wabsdiff,\
702 wmmx_wacc,\
703 wmmx_wadd,\
704 wmmx_waddbhus,\
705 wmmx_waddsubhx,\
706 wmmx_waligni,\
707 wmmx_walignr,\
708 wmmx_wand,\
709 wmmx_wandn,\
710 wmmx_wavg2,\
711 wmmx_wavg4,\
712 wmmx_wcmpeq,\
713 wmmx_wcmpgt,\
714 wmmx_wmac,\
715 wmmx_wmadd,\
716 wmmx_wmax,\
717 wmmx_wmerge,\
718 wmmx_wmiawxy,\
719 wmmx_wmiaxy,\
720 wmmx_wmin,\
721 wmmx_wmov,\
722 wmmx_wmul,\
723 wmmx_wmulw,\
724 wmmx_wldr,\
725 wmmx_wor,\
726 wmmx_wpack,\
727 wmmx_wqmiaxy,\
728 wmmx_wqmulm,\
729 wmmx_wqmulwm,\
730 wmmx_wror,\
731 wmmx_wsad,\
732 wmmx_wshufh,\
733 wmmx_wsll,\
734 wmmx_wsra,\
735 wmmx_wsrl,\
736 wmmx_wstr,\
737 wmmx_wsub,\
738 wmmx_wsubaddhx,\
739 wmmx_wunpckeh,\
740 wmmx_wunpckel,\
741 wmmx_wunpckih,\
742 wmmx_wunpckil,\
743 wmmx_wxor,\
744 \
745 neon_add,\
746 neon_add_q,\
747 neon_add_widen,\
748 neon_add_long,\
749 neon_qadd,\
750 neon_qadd_q,\
751 neon_add_halve,\
752 neon_add_halve_q,\
753 neon_add_halve_narrow_q,\
754 \
755 neon_sub,\
756 neon_sub_q,\
757 neon_sub_widen,\
758 neon_sub_long,\
759 neon_qsub,\
760 neon_qsub_q,\
761 neon_sub_halve,\
762 neon_sub_halve_q,\
763 neon_sub_halve_narrow_q,\
764 \
765 neon_abs,\
766 neon_abs_q,\
767 neon_neg,\
768 neon_neg_q,\
769 neon_qneg,\
770 neon_qneg_q,\
771 neon_qabs,\
772 neon_qabs_q,\
773 neon_abd,\
774 neon_abd_q,\
775 neon_abd_long,\
776 \
777 neon_minmax,\
778 neon_minmax_q,\
779 neon_compare,\
780 neon_compare_q,\
781 neon_compare_zero,\
782 neon_compare_zero_q,\
783 \
784 neon_arith_acc,\
785 neon_arith_acc_q,\
786 neon_reduc_add,\
787 neon_reduc_add_q,\
788 neon_reduc_add_long,\
789 neon_reduc_add_acc,\
790 neon_reduc_add_acc_q,\
791 neon_reduc_minmax,\
792 neon_reduc_minmax_q,\
793 neon_logic,\
794 neon_logic_q,\
795 neon_tst,\
796 neon_tst_q,\
797 \
798 neon_shift_imm,\
799 neon_shift_imm_q,\
800 neon_shift_imm_narrow_q,\
801 neon_shift_imm_long,\
802 neon_shift_reg,\
803 neon_shift_reg_q,\
804 neon_shift_acc,\
805 neon_shift_acc_q,\
806 neon_sat_shift_imm,\
807 neon_sat_shift_imm_q,\
808 neon_sat_shift_imm_narrow_q,\
809 neon_sat_shift_reg,\
810 neon_sat_shift_reg_q,\
811 \
812 neon_ins,\
813 neon_ins_q,\
814 neon_move,\
815 neon_move_q,\
816 neon_move_narrow_q,\
817 neon_permute,\
818 neon_permute_q,\
819 neon_zip,\
820 neon_zip_q,\
821 neon_tbl1,\
822 neon_tbl1_q,\
823 neon_tbl2,\
824 neon_tbl2_q,\
825 neon_tbl3,\
826 neon_tbl3_q,\
827 neon_tbl4,\
828 neon_tbl4_q,\
829 \
830 neon_bsl,\
831 neon_bsl_q,\
832 neon_cls,\
833 neon_cls_q,\
834 neon_cnt,\
835 neon_cnt_q,\
836 neon_dup,\
837 neon_dup_q,\
838 neon_ext,\
839 neon_ext_q,\
840 neon_rbit,\
841 neon_rbit_q,\
842 neon_rev,\
843 neon_rev_q,\
844 \
845 neon_mul_b,\
846 neon_mul_b_q,\
847 neon_mul_h,\
848 neon_mul_h_q,\
849 neon_mul_s,\
850 neon_mul_s_q,\
851 neon_mul_b_long,\
852 neon_mul_h_long,\
853 neon_mul_s_long,\
854 neon_mul_d_long,\
855 neon_mul_h_scalar,\
856 neon_mul_h_scalar_q,\
857 neon_mul_s_scalar,\
858 neon_mul_s_scalar_q,\
859 neon_mul_h_scalar_long,\
860 neon_mul_s_scalar_long,\
861 \
862 neon_sat_mul_b,\
863 neon_sat_mul_b_q,\
864 neon_sat_mul_h,\
865 neon_sat_mul_h_q,\
866 neon_sat_mul_s,\
867 neon_sat_mul_s_q,\
868 neon_sat_mul_b_long,\
869 neon_sat_mul_h_long,\
870 neon_sat_mul_s_long,\
871 neon_sat_mul_h_scalar,\
872 neon_sat_mul_h_scalar_q,\
873 neon_sat_mul_s_scalar,\
874 neon_sat_mul_s_scalar_q,\
875 neon_sat_mul_h_scalar_long,\
876 neon_sat_mul_s_scalar_long,\
877 \
878 neon_mla_b,\
879 neon_mla_b_q,\
880 neon_mla_h,\
881 neon_mla_h_q,\
882 neon_mla_s,\
883 neon_mla_s_q,\
884 neon_mla_b_long,\
885 neon_mla_h_long,\
886 neon_mla_s_long,\
887 neon_mla_h_scalar,\
888 neon_mla_h_scalar_q,\
889 neon_mla_s_scalar,\
890 neon_mla_s_scalar_q,\
891 neon_mla_h_scalar_long,\
892 neon_mla_s_scalar_long,\
893 \
894 neon_sat_mla_b_long,\
895 neon_sat_mla_h_long,\
896 neon_sat_mla_s_long,\
897 neon_sat_mla_h_scalar_long,\
898 neon_sat_mla_s_scalar_long,\
899 \
900 neon_to_gp,\
901 neon_to_gp_q,\
902 neon_from_gp,\
903 neon_from_gp_q,\
904 \
905 neon_ldr,\
906 neon_ldp,\
907 neon_ldp_q,\
908 neon_load1_1reg,\
909 neon_load1_1reg_q,\
910 neon_load1_2reg,\
911 neon_load1_2reg_q,\
912 neon_load1_3reg,\
913 neon_load1_3reg_q,\
914 neon_load1_4reg,\
915 neon_load1_4reg_q,\
916 neon_load1_all_lanes,\
917 neon_load1_all_lanes_q,\
918 neon_load1_one_lane,\
919 neon_load1_one_lane_q,\
920 \
921 neon_load2_2reg,\
922 neon_load2_2reg_q,\
923 neon_load2_4reg,\
924 neon_load2_4reg_q,\
925 neon_load2_all_lanes,\
926 neon_load2_all_lanes_q,\
927 neon_load2_one_lane,\
928 neon_load2_one_lane_q,\
929 \
930 neon_load3_3reg,\
931 neon_load3_3reg_q,\
932 neon_load3_all_lanes,\
933 neon_load3_all_lanes_q,\
934 neon_load3_one_lane,\
935 neon_load3_one_lane_q,\
936 \
937 neon_load4_4reg,\
938 neon_load4_4reg_q,\
939 neon_load4_all_lanes,\
940 neon_load4_all_lanes_q,\
941 neon_load4_one_lane,\
942 neon_load4_one_lane_q,\
943 \
944 neon_str,\
945 neon_stp,\
946 neon_stp_q,\
947 neon_store1_1reg,\
948 neon_store1_1reg_q,\
949 neon_store1_2reg,\
950 neon_store1_2reg_q,\
951 neon_store1_3reg,\
952 neon_store1_3reg_q,\
953 neon_store1_4reg,\
954 neon_store1_4reg_q,\
955 neon_store1_one_lane,\
956 neon_store1_one_lane_q,\
957 \
958 neon_store2_2reg,\
959 neon_store2_2reg_q,\
960 neon_store2_4reg,\
961 neon_store2_4reg_q,\
962 neon_store2_one_lane,\
963 neon_store2_one_lane_q,\
964 \
965 neon_store3_3reg,\
966 neon_store3_3reg_q,\
967 neon_store3_one_lane,\
968 neon_store3_one_lane_q,\
969 \
970 neon_store4_4reg,\
971 neon_store4_4reg_q,\
972 neon_store4_one_lane,\
973 neon_store4_one_lane_q,\
974 \
975 neon_fp_abs_s,\
976 neon_fp_abs_s_q,\
977 neon_fp_abs_d,\
978 neon_fp_abs_d_q,\
979 neon_fp_neg_s,\
980 neon_fp_neg_s_q,\
981 neon_fp_neg_d,\
982 neon_fp_neg_d_q,\
983 \
984 neon_fp_abd_s,\
985 neon_fp_abd_s_q,\
986 neon_fp_abd_d,\
987 neon_fp_abd_d_q,\
988 neon_fp_addsub_s,\
989 neon_fp_addsub_s_q,\
990 neon_fp_addsub_d,\
991 neon_fp_addsub_d_q,\
992 neon_fp_compare_s,\
993 neon_fp_compare_s_q,\
994 neon_fp_compare_d,\
995 neon_fp_compare_d_q,\
996 neon_fp_minmax_s,\
997 neon_fp_minmax_s_q,\
998 neon_fp_minmax_d,\
999 neon_fp_minmax_d_q,\
1000 \
1001 neon_fp_reduc_add_s,\
1002 neon_fp_reduc_add_s_q,\
1003 neon_fp_reduc_add_d,\
1004 neon_fp_reduc_add_d_q,\
1005 neon_fp_reduc_minmax_s,\
1006 neon_fp_reduc_minmax_s_q,\
1007 neon_fp_reduc_minmax_d,\
1008 neon_fp_reduc_minmax_d_q,\
1009 \
1010 neon_fp_cvt_narrow_s_q,\
1011 neon_fp_cvt_narrow_d_q,\
1012 neon_fp_cvt_widen_h,\
1013 neon_fp_cvt_widen_s,\
1014 \
1015 neon_fp_to_int_s,\
1016 neon_fp_to_int_s_q,\
1017 neon_fp_to_int_d,\
1018 neon_fp_to_int_d_q,\
1019 neon_int_to_fp_s,\
1020 neon_int_to_fp_s_q,\
1021 neon_int_to_fp_d,\
1022 neon_int_to_fp_d_q,\
1023 neon_fp_round_s,\
1024 neon_fp_round_s_q,\
1025 neon_fp_round_d,\
1026 neon_fp_round_d_q,\
1027 \
1028 neon_fp_recpe_s,\
1029 neon_fp_recpe_s_q,\
1030 neon_fp_recpe_d,\
1031 neon_fp_recpe_d_q,\
1032 neon_fp_recps_s,\
1033 neon_fp_recps_s_q,\
1034 neon_fp_recps_d,\
1035 neon_fp_recps_d_q,\
1036 neon_fp_recpx_s,\
1037 neon_fp_recpx_s_q,\
1038 neon_fp_recpx_d,\
1039 neon_fp_recpx_d_q,\
1040 \
1041 neon_fp_rsqrte_s,\
1042 neon_fp_rsqrte_s_q,\
1043 neon_fp_rsqrte_d,\
1044 neon_fp_rsqrte_d_q,\
1045 neon_fp_rsqrts_s,\
1046 neon_fp_rsqrts_s_q,\
1047 neon_fp_rsqrts_d,\
1048 neon_fp_rsqrts_d_q,\
1049 \
1050 neon_fp_mul_s,\
1051 neon_fp_mul_s_q,\
1052 neon_fp_mul_s_scalar,\
1053 neon_fp_mul_s_scalar_q,\
1054 neon_fp_mul_d,\
1055 neon_fp_mul_d_q,\
1056 neon_fp_mul_d_scalar_q,\
1057 \
1058 neon_fp_mla_s,\
1059 neon_fp_mla_s_q,\
1060 neon_fp_mla_s_scalar,\
1061 neon_fp_mla_s_scalar_q,\
1062 neon_fp_mla_d,\
1063 neon_fp_mla_d_q,\
1064 neon_fp_mla_d_scalar_q,\
1065 \
1066 neon_fp_sqrt_s,\
1067 neon_fp_sqrt_s_q,\
1068 neon_fp_sqrt_d,\
1069 neon_fp_sqrt_d_q,\
1070 neon_fp_div_s,\
1071 neon_fp_div_s_q,\
1072 neon_fp_div_d,\
1073 neon_fp_div_d_q,\
1074 \
1075 crypto_aese,\
1076 crypto_aesmc,\
1077 crypto_sha1_xor,\
1078 crypto_sha1_fast,\
1079 crypto_sha1_slow,\
1080 crypto_sha256_fast,\
1081 crypto_sha256_slow,\
1082 crypto_pmull,\
1083 coproc"
1084 (const_string "untyped"))
1086 ; Is this an (integer side) multiply with a 32-bit (or smaller) result?
1087 (define_attr "mul32" "no,yes"
1088 (if_then_else
1089 (eq_attr "type"
1090 "smulxy,smlaxy,smulwy,smlawx,mul,muls,mla,mlas,smlawy,smuad,smuadx,\
1091 smlad,smladx,smusd,smusdx,smlsd,smlsdx,smmul,smmulr,smmla,smlald,smlsld")
1092 (const_string "yes")
1093 (const_string "no")))
1095 ; Is this an (integer side) multiply with a 64-bit result?
1096 (define_attr "mul64" "no,yes"
1097 (if_then_else
1098 (eq_attr "type"
1099 "smlalxy,umull,umulls,umaal,umlal,umlals,smull,smulls,smlal,smlals")
1100 (const_string "yes")
1101 (const_string "no")))
1103 ; YES if the "type" attribute assigned to the insn denotes an
1104 ; Advanced SIMD instruction, NO otherwise.
1105 (define_attr "is_neon_type" "yes,no"
1106 (if_then_else (eq_attr "type"
1107 "neon_add, neon_add_q, neon_add_widen, neon_add_long,\
1108 neon_qadd, neon_qadd_q, neon_add_halve, neon_add_halve_q,\
1109 neon_add_halve_narrow_q,\
1110 neon_sub, neon_sub_q, neon_sub_widen, neon_sub_long, neon_qsub,\
1111 neon_qsub_q, neon_sub_halve, neon_sub_halve_q,\
1112 neon_sub_halve_narrow_q,\
1113 neon_abs, neon_abs_q, neon_neg, neon_neg_q, neon_qneg,\
1114 neon_qneg_q, neon_qabs, neon_qabs_q, neon_abd, neon_abd_q,\
1115 neon_abd_long, neon_minmax, neon_minmax_q, neon_compare,\
1116 neon_compare_q, neon_compare_zero, neon_compare_zero_q,\
1117 neon_arith_acc, neon_arith_acc_q, neon_reduc_add,\
1118 neon_reduc_add_q, neon_reduc_add_long, neon_reduc_add_acc,\
1119 neon_reduc_add_acc_q, neon_reduc_minmax, neon_reduc_minmax_q,\
1120 neon_logic, neon_logic_q, neon_tst, neon_tst_q,\
1121 neon_shift_imm, neon_shift_imm_q, neon_shift_imm_narrow_q,\
1122 neon_shift_imm_long, neon_shift_reg, neon_shift_reg_q,\
1123 neon_shift_acc, neon_shift_acc_q, neon_sat_shift_imm,\
1124 neon_sat_shift_imm_q, neon_sat_shift_imm_narrow_q,\
1125 neon_sat_shift_reg, neon_sat_shift_reg_q,\
1126 neon_ins, neon_ins_q, neon_move, neon_move_q, neon_move_narrow_q,\
1127 neon_permute, neon_permute_q, neon_zip, neon_zip_q, neon_tbl1,\
1128 neon_tbl1_q, neon_tbl2, neon_tbl2_q, neon_tbl3, neon_tbl3_q,\
1129 neon_tbl4, neon_tbl4_q, neon_bsl, neon_bsl_q, neon_cls,\
1130 neon_cls_q, neon_cnt, neon_cnt_q, neon_dup, neon_dup_q,\
1131 neon_ext, neon_ext_q, neon_rbit, neon_rbit_q,\
1132 neon_rev, neon_rev_q, neon_mul_b, neon_mul_b_q, neon_mul_h,\
1133 neon_mul_h_q, neon_mul_s, neon_mul_s_q, neon_mul_b_long,\
1134 neon_mul_h_long, neon_mul_s_long, neon_mul_d_long, neon_mul_h_scalar,\
1135 neon_mul_h_scalar_q, neon_mul_s_scalar, neon_mul_s_scalar_q,\
1136 neon_mul_h_scalar_long, neon_mul_s_scalar_long, neon_sat_mul_b,\
1137 neon_sat_mul_b_q, neon_sat_mul_h, neon_sat_mul_h_q,\
1138 neon_sat_mul_s, neon_sat_mul_s_q, neon_sat_mul_b_long,\
1139 neon_sat_mul_h_long, neon_sat_mul_s_long, neon_sat_mul_h_scalar,\
1140 neon_sat_mul_h_scalar_q, neon_sat_mul_s_scalar,\
1141 neon_sat_mul_s_scalar_q, neon_sat_mul_h_scalar_long,\
1142 neon_sat_mul_s_scalar_long, neon_mla_b, neon_mla_b_q, neon_mla_h,\
1143 neon_mla_h_q, neon_mla_s, neon_mla_s_q, neon_mla_b_long,\
1144 neon_mla_h_long, neon_mla_s_long, neon_mla_h_scalar,\
1145 neon_mla_h_scalar_q, neon_mla_s_scalar, neon_mla_s_scalar_q,\
1146 neon_mla_h_scalar_long, neon_mla_s_scalar_long,\
1147 neon_sat_mla_b_long, neon_sat_mla_h_long,\
1148 neon_sat_mla_s_long, neon_sat_mla_h_scalar_long,\
1149 neon_sat_mla_s_scalar_long,\
1150 neon_to_gp, neon_to_gp_q, neon_from_gp, neon_from_gp_q,\
1151 neon_ldr, neon_ldp, neon_ldp_q,\
1152 neon_load1_1reg, neon_load1_1reg_q, neon_load1_2reg,\
1153 neon_load1_2reg_q, neon_load1_3reg, neon_load1_3reg_q,\
1154 neon_load1_4reg, neon_load1_4reg_q, neon_load1_all_lanes,\
1155 neon_load1_all_lanes_q, neon_load1_one_lane, neon_load1_one_lane_q,\
1156 neon_load2_2reg, neon_load2_2reg_q, neon_load2_4reg,\
1157 neon_load2_4reg_q, neon_load2_all_lanes, neon_load2_all_lanes_q,\
1158 neon_load2_one_lane, neon_load2_one_lane_q,\
1159 neon_load3_3reg, neon_load3_3reg_q, neon_load3_all_lanes,\
1160 neon_load3_all_lanes_q, neon_load3_one_lane, neon_load3_one_lane_q,\
1161 neon_load4_4reg, neon_load4_4reg_q, neon_load4_all_lanes,\
1162 neon_load4_all_lanes_q, neon_load4_one_lane, neon_load4_one_lane_q,\
1163 neon_str, neon_stp, neon_stp_q,\
1164 neon_store1_1reg, neon_store1_1reg_q, neon_store1_2reg,\
1165 neon_store1_2reg_q, neon_store1_3reg, neon_store1_3reg_q,\
1166 neon_store1_4reg, neon_store1_4reg_q, neon_store1_one_lane,\
1167 neon_store1_one_lane_q, neon_store2_2reg, neon_store2_2reg_q,\
1168 neon_store2_4reg, neon_store2_4reg_q, neon_store2_one_lane,\
1169 neon_store2_one_lane_q, neon_store3_3reg, neon_store3_3reg_q,\
1170 neon_store3_one_lane, neon_store3_one_lane_q, neon_store4_4reg,\
1171 neon_store4_4reg_q, neon_store4_one_lane, neon_store4_one_lane_q,\
1172 neon_fp_abd_s, neon_fp_abd_s_q, neon_fp_abd_d, neon_fp_abd_d_q,\
1173 neon_fp_abs_s, neon_fp_abs_s_q, neon_fp_abs_d, neon_fp_abs_d_q,\
1174 neon_fp_addsub_s, neon_fp_addsub_s_q, neon_fp_addsub_d,\
1175 neon_fp_addsub_d_q, neon_fp_compare_s, neon_fp_compare_s_q,\
1176 neon_fp_compare_d, neon_fp_compare_d_q, neon_fp_minmax_s,\
1177 neon_fp_minmax_s_q, neon_fp_minmax_d, neon_fp_minmax_d_q,\
1178 neon_fp_neg_s, neon_fp_neg_s_q, neon_fp_neg_d, neon_fp_neg_d_q,\
1179 neon_fp_reduc_add_s, neon_fp_reduc_add_s_q, neon_fp_reduc_add_d,\
1180 neon_fp_reduc_add_d_q, neon_fp_reduc_minmax_s,
1181 neon_fp_reduc_minmax_s_q, neon_fp_reduc_minmax_d,\
1182 neon_fp_reduc_minmax_d_q,\
1183 neon_fp_cvt_narrow_s_q, neon_fp_cvt_narrow_d_q,\
1184 neon_fp_cvt_widen_h, neon_fp_cvt_widen_s, neon_fp_to_int_s,\
1185 neon_fp_to_int_s_q, neon_int_to_fp_s, neon_int_to_fp_s_q,\
1186 neon_fp_to_int_d, neon_fp_to_int_d_q,\
1187 neon_int_to_fp_d, neon_int_to_fp_d_q,\
1188 neon_fp_round_s, neon_fp_round_s_q, neon_fp_recpe_s,\
1189 neon_fp_recpe_s_q,\
1190 neon_fp_recpe_d, neon_fp_recpe_d_q, neon_fp_recps_s,\
1191 neon_fp_recps_s_q, neon_fp_recps_d, neon_fp_recps_d_q,\
1192 neon_fp_recpx_s, neon_fp_recpx_s_q, neon_fp_recpx_d,\
1193 neon_fp_recpx_d_q, neon_fp_rsqrte_s, neon_fp_rsqrte_s_q,\
1194 neon_fp_rsqrte_d, neon_fp_rsqrte_d_q, neon_fp_rsqrts_s,\
1195 neon_fp_rsqrts_s_q, neon_fp_rsqrts_d, neon_fp_rsqrts_d_q,\
1196 neon_fp_mul_s, neon_fp_mul_s_q, neon_fp_mul_s_scalar,\
1197 neon_fp_mul_s_scalar_q, neon_fp_mul_d, neon_fp_mul_d_q,\
1198 neon_fp_mul_d_scalar_q, neon_fp_mla_s, neon_fp_mla_s_q,\
1199 neon_fp_mla_s_scalar, neon_fp_mla_s_scalar_q, neon_fp_mla_d,\
1200 neon_fp_mla_d_q, neon_fp_mla_d_scalar_q, neon_fp_sqrt_s,\
1201 neon_fp_sqrt_s_q, neon_fp_sqrt_d, neon_fp_sqrt_d_q,\
1202 neon_fp_div_s, neon_fp_div_s_q, neon_fp_div_d, neon_fp_div_d_q, crypto_aese,\
1203 crypto_aesmc, crypto_sha1_xor, crypto_sha1_fast, crypto_sha1_slow,\
1204 crypto_sha256_fast, crypto_sha256_slow")
1205 (const_string "yes")
1206 (const_string "no")))