| blob | 2e7580f220eae1524fef69719b1796f50f5cf27c |
1 ;; ARM Thumb-2 Machine Description
2 ;; Copyright (C) 2007-2017 Free Software Foundation, Inc.
3 ;; Written by CodeSourcery, LLC.
4 ;;
5 ;; This file is part of GCC.
6 ;;
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
10 ;; any later version.
11 ;;
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
16 ;;
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>. */
21 ;; Note: Thumb-2 is the variant of the Thumb architecture that adds
22 ;; 32-bit encodings of [almost all of] the Arm instruction set.
23 ;; Some old documents refer to the relatively minor interworking
24 ;; changes made in armv5t as "thumb2". These are considered part
25 ;; the 16-bit Thumb-1 instruction set.
27 ;; Thumb-2 only allows shift by constant on data processing instructions
28 (define_insn "*thumb_andsi_not_shiftsi_si"
29 [(set (match_operand:SI 0 "s_register_operand" "=r")
30 (and:SI (not:SI (match_operator:SI 4 "shift_operator"
31 [(match_operand:SI 2 "s_register_operand" "r")
32 (match_operand:SI 3 "const_int_operand" "M")]))
33 (match_operand:SI 1 "s_register_operand" "r")))]
34 "TARGET_THUMB2"
35 "bic%?\\t%0, %1, %2%S4"
36 [(set_attr "predicable" "yes")
37 (set_attr "predicable_short_it" "no")
38 (set_attr "shift" "2")
39 (set_attr "type" "alu_shift_imm")]
40 )
42 ;; We use the '0' constraint for operand 1 because reload should
43 ;; be smart enough to generate an appropriate move for the r/r/r case.
44 (define_insn_and_split "*thumb2_smaxsi3"
45 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
46 (smax:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
47 (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
48 (clobber (reg:CC CC_REGNUM))]
49 "TARGET_THUMB2"
50 "#"
51 ; cmp\\t%1, %2\;it\\tlt\;movlt\\t%0, %2
52 "TARGET_THUMB2 && reload_completed"
53 [(set (reg:CC CC_REGNUM)
54 (compare:CC (match_dup 1) (match_dup 2)))
55 (cond_exec (lt:SI (reg:CC CC_REGNUM) (const_int 0))
56 (set (match_dup 0)
57 (match_dup 2)))]
58 ""
59 [(set_attr "conds" "clob")
60 (set_attr "enabled_for_depr_it" "yes,yes,no")
61 (set_attr "length" "6,6,10")
62 (set_attr "type" "multiple")]
63 )
65 (define_insn_and_split "*thumb2_sminsi3"
66 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
67 (smin:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
68 (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
69 (clobber (reg:CC CC_REGNUM))]
70 "TARGET_THUMB2"
71 "#"
72 ; cmp\\t%1, %2\;it\\tge\;movge\\t%0, %2
73 "TARGET_THUMB2 && reload_completed"
74 [(set (reg:CC CC_REGNUM)
75 (compare:CC (match_dup 1) (match_dup 2)))
76 (cond_exec (ge:SI (reg:CC CC_REGNUM) (const_int 0))
77 (set (match_dup 0)
78 (match_dup 2)))]
79 ""
80 [(set_attr "conds" "clob")
81 (set_attr "enabled_for_depr_it" "yes,yes,no")
82 (set_attr "length" "6,6,10")
83 (set_attr "type" "multiple")]
84 )
86 (define_insn_and_split "*thumb32_umaxsi3"
87 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
88 (umax:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
89 (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
90 (clobber (reg:CC CC_REGNUM))]
91 "TARGET_THUMB2"
92 "#"
93 ; cmp\\t%1, %2\;it\\tcc\;movcc\\t%0, %2
94 "TARGET_THUMB2 && reload_completed"
95 [(set (reg:CC CC_REGNUM)
96 (compare:CC (match_dup 1) (match_dup 2)))
97 (cond_exec (ltu:SI (reg:CC CC_REGNUM) (const_int 0))
98 (set (match_dup 0)
99 (match_dup 2)))]
100 ""
101 [(set_attr "conds" "clob")
102 (set_attr "length" "6,6,10")
103 (set_attr "enabled_for_depr_it" "yes,yes,no")
104 (set_attr "type" "multiple")]
105 )
107 (define_insn_and_split "*thumb2_uminsi3"
108 [(set (match_operand:SI 0 "s_register_operand" "=r,l,r")
109 (umin:SI (match_operand:SI 1 "s_register_operand" "%0,0,0")
110 (match_operand:SI 2 "arm_rhs_operand" "r,Py,I")))
111 (clobber (reg:CC CC_REGNUM))]
112 "TARGET_THUMB2"
113 "#"
114 ; cmp\\t%1, %2\;it\\tcs\;movcs\\t%0, %2
115 "TARGET_THUMB2 && reload_completed"
116 [(set (reg:CC CC_REGNUM)
117 (compare:CC (match_dup 1) (match_dup 2)))
118 (cond_exec (geu:SI (reg:CC CC_REGNUM) (const_int 0))
119 (set (match_dup 0)
120 (match_dup 2)))]
121 ""
122 [(set_attr "conds" "clob")
123 (set_attr "length" "6,6,10")
124 (set_attr "enabled_for_depr_it" "yes,yes,no")
125 (set_attr "type" "multiple")]
126 )
128 (define_insn_and_split "*thumb2_abssi2"
129 [(set (match_operand:SI 0 "s_register_operand" "=&r,l,r")
130 (abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0")))
131 (clobber (reg:CC CC_REGNUM))]
132 "TARGET_THUMB2"
133 "#"
134 ; eor%?\\t%0, %1, %1, asr #31\;sub%?\\t%0, %0, %1, asr #31
135 ; cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
136 ; cmp\\t%0, #0\;it\tlt\;rsblt\\t%0, %0, #0
137 "&& reload_completed"
138 [(const_int 0)]
139 {
140 if (REGNO(operands[0]) == REGNO(operands[1]))
141 {
142 rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
144 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (CCmode, operands[0],
145 const0_rtx)));
146 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
147 (gen_rtx_LT (SImode,
148 cc_reg,
149 const0_rtx)),
150 (gen_rtx_SET (operands[0],
151 (gen_rtx_MINUS (SImode,
152 const0_rtx,
153 operands[1]))))));
154 }
155 else
156 {
157 emit_insn (gen_rtx_SET (operands[0],
158 gen_rtx_XOR (SImode,
159 gen_rtx_ASHIFTRT (SImode,
160 operands[1],
161 GEN_INT (31)),
162 operands[1])));
163 emit_insn (gen_rtx_SET (operands[0],
164 gen_rtx_MINUS (SImode,
165 operands[0],
166 gen_rtx_ASHIFTRT (SImode,
167 operands[1],
168 GEN_INT (31)))));
169 }
170 DONE;
171 }
172 [(set_attr "conds" "*,clob,clob")
173 (set_attr "shift" "1")
174 (set_attr "predicable" "yes,no,no")
175 (set_attr "predicable_short_it" "no")
176 (set_attr "enabled_for_depr_it" "yes,yes,no")
177 (set_attr "ce_count" "2")
178 (set_attr "length" "8,6,10")
179 (set_attr "type" "multiple")]
180 )
182 (define_insn_and_split "*thumb2_neg_abssi2"
183 [(set (match_operand:SI 0 "s_register_operand" "=&r,l,r")
184 (neg:SI (abs:SI (match_operand:SI 1 "s_register_operand" "r,0,0"))))
185 (clobber (reg:CC CC_REGNUM))]
186 "TARGET_THUMB2"
187 "#"
188 ; eor%?\\t%0, %1, %1, asr #31\;rsb%?\\t%0, %0, %1, asr #31
189 ; cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
190 ; cmp\\t%0, #0\;it\\tgt\;rsbgt\\t%0, %0, #0
191 "&& reload_completed"
192 [(const_int 0)]
193 {
194 if (REGNO(operands[0]) == REGNO(operands[1]))
195 {
196 rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
198 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (CCmode, operands[0],
199 const0_rtx)));
200 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
201 (gen_rtx_GT (SImode,
202 cc_reg,
203 const0_rtx)),
204 (gen_rtx_SET (operands[0],
205 (gen_rtx_MINUS (SImode,
206 const0_rtx,
207 operands[1]))))));
208 }
209 else
210 {
211 emit_insn (gen_rtx_SET (operands[0],
212 gen_rtx_XOR (SImode,
213 gen_rtx_ASHIFTRT (SImode,
214 operands[1],
215 GEN_INT (31)),
216 operands[1])));
217 emit_insn (gen_rtx_SET (operands[0],
218 gen_rtx_MINUS (SImode,
219 gen_rtx_ASHIFTRT (SImode,
220 operands[1],
221 GEN_INT (31)),
222 operands[0])));
223 }
224 DONE;
225 }
226 [(set_attr "conds" "*,clob,clob")
227 (set_attr "shift" "1")
228 (set_attr "predicable" "yes,no,no")
229 (set_attr "enabled_for_depr_it" "yes,yes,no")
230 (set_attr "predicable_short_it" "no")
231 (set_attr "ce_count" "2")
232 (set_attr "length" "8,6,10")
233 (set_attr "type" "multiple")]
234 )
236 ;; Pop a single register as its size is preferred over a post-incremental load
237 (define_insn "*thumb2_pop_single"
238 [(set (match_operand:SI 0 "low_register_operand" "=r")
239 (mem:SI (post_inc:SI (reg:SI SP_REGNUM))))]
240 "TARGET_THUMB2 && (reload_in_progress || reload_completed)"
241 "pop\t{%0}"
242 [(set_attr "type" "load1")
243 (set_attr "length" "2")
244 (set_attr "predicable" "yes")]
245 )
247 ;; We have two alternatives here for memory loads (and similarly for stores)
248 ;; to reflect the fact that the permissible constant pool ranges differ
249 ;; between ldr instructions taking low regs and ldr instructions taking high
250 ;; regs. The high register alternatives are not taken into account when
251 ;; choosing register preferences in order to reflect their expense.
252 (define_insn "*thumb2_movsi_insn"
253 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,l,r,r,l ,*hk,m,*m")
254 (match_operand:SI 1 "general_operand" "rk,I,Py,K,j,mi,*mi,l,*hk"))]
255 "TARGET_THUMB2 && !TARGET_IWMMXT && !TARGET_HARD_FLOAT
256 && ( register_operand (operands[0], SImode)
257 || register_operand (operands[1], SImode))"
258 "@
259 mov%?\\t%0, %1
260 mov%?\\t%0, %1
261 mov%?\\t%0, %1
262 mvn%?\\t%0, #%B1
263 movw%?\\t%0, %1
264 ldr%?\\t%0, %1
265 ldr%?\\t%0, %1
266 str%?\\t%1, %0
267 str%?\\t%1, %0"
268 [(set_attr "type" "mov_reg,mov_imm,mov_imm,mvn_imm,mov_imm,load1,load1,store1,store1")
269 (set_attr "length" "2,4,2,4,4,4,4,4,4")
270 (set_attr "predicable" "yes")
271 (set_attr "predicable_short_it" "yes,no,yes,no,no,no,no,no,no")
272 (set_attr "pool_range" "*,*,*,*,*,1018,4094,*,*")
273 (set_attr "neg_pool_range" "*,*,*,*,*,0,0,*,*")]
274 )
276 (define_insn "tls_load_dot_plus_four"
277 [(set (match_operand:SI 0 "register_operand" "=l,l,r,r")
278 (mem:SI (unspec:SI [(match_operand:SI 2 "register_operand" "0,1,0,1")
279 (const_int 4)
280 (match_operand 3 "" "")]
281 UNSPEC_PIC_BASE)))
282 (clobber (match_scratch:SI 1 "=X,l,X,r"))]
283 "TARGET_THUMB2"
284 "*
285 (*targetm.asm_out.internal_label) (asm_out_file, \"LPIC\",
286 INTVAL (operands[3]));
287 return \"add\\t%2, %|pc\;ldr%?\\t%0, [%2]\";
288 "
289 [(set_attr "length" "4,4,6,6")
290 (set_attr "type" "multiple")]
291 )
293 ;; Thumb-2 always has load/store halfword instructions, so we can avoid a lot
294 ;; of the messiness associated with the ARM patterns.
295 (define_insn "*thumb2_movhi_insn"
296 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,l,r,m,r")
297 (match_operand:HI 1 "general_operand" "rk,I,Py,n,r,m"))]
298 "TARGET_THUMB2
299 && (register_operand (operands[0], HImode)
300 || register_operand (operands[1], HImode))"
301 "@
302 mov%?\\t%0, %1\\t%@ movhi
303 mov%?\\t%0, %1\\t%@ movhi
304 mov%?\\t%0, %1\\t%@ movhi
305 movw%?\\t%0, %L1\\t%@ movhi
306 strh%?\\t%1, %0\\t%@ movhi
307 ldrh%?\\t%0, %1\\t%@ movhi"
308 [(set_attr "type" "mov_reg,mov_imm,mov_imm,mov_imm,store1,load1")
309 (set_attr "predicable" "yes")
310 (set_attr "predicable_short_it" "yes,no,yes,no,no,no")
311 (set_attr "length" "2,4,2,4,4,4")
312 (set_attr "pool_range" "*,*,*,*,*,4094")
313 (set_attr "neg_pool_range" "*,*,*,*,*,250")]
314 )
316 (define_insn "*thumb2_storewb_pairsi"
317 [(set (match_operand:SI 0 "register_operand" "=&kr")
318 (plus:SI (match_operand:SI 1 "register_operand" "0")
319 (match_operand:SI 2 "const_int_operand" "n")))
320 (set (mem:SI (plus:SI (match_dup 0) (match_dup 2)))
321 (match_operand:SI 3 "register_operand" "r"))
322 (set (mem:SI (plus:SI (match_dup 0)
323 (match_operand:SI 5 "const_int_operand" "n")))
324 (match_operand:SI 4 "register_operand" "r"))]
325 "TARGET_THUMB2
326 && INTVAL (operands[5]) == INTVAL (operands[2]) + 4"
327 "strd\\t%3, %4, [%0, %2]!"
328 [(set_attr "type" "store2")]
329 )
331 (define_insn "*thumb2_cmpsi_neg_shiftsi"
332 [(set (reg:CC CC_REGNUM)
333 (compare:CC (match_operand:SI 0 "s_register_operand" "r")
334 (neg:SI (match_operator:SI 3 "shift_operator"
335 [(match_operand:SI 1 "s_register_operand" "r")
336 (match_operand:SI 2 "const_int_operand" "M")]))))]
337 "TARGET_THUMB2"
338 "cmn%?\\t%0, %1%S3"
339 [(set_attr "conds" "set")
340 (set_attr "shift" "1")
341 (set_attr "type" "alus_shift_imm")]
342 )
344 (define_insn_and_split "*thumb2_mov_scc"
345 [(set (match_operand:SI 0 "s_register_operand" "=l,r")
346 (match_operator:SI 1 "arm_comparison_operator_mode"
347 [(match_operand 2 "cc_register" "") (const_int 0)]))]
348 "TARGET_THUMB2"
349 "#" ; "ite\\t%D1\;mov%D1\\t%0, #0\;mov%d1\\t%0, #1"
350 "TARGET_THUMB2"
351 [(set (match_dup 0)
352 (if_then_else:SI (match_dup 1)
353 (const_int 1)
354 (const_int 0)))]
355 ""
356 [(set_attr "conds" "use")
357 (set_attr "enabled_for_depr_it" "yes,no")
358 (set_attr "length" "8,10")
359 (set_attr "type" "multiple")]
360 )
362 (define_insn_and_split "*thumb2_mov_negscc"
363 [(set (match_operand:SI 0 "s_register_operand" "=r")
364 (neg:SI (match_operator:SI 1 "arm_comparison_operator_mode"
365 [(match_operand 2 "cc_register" "") (const_int 0)])))]
366 "TARGET_THUMB2 && !arm_restrict_it"
367 "#" ; "ite\\t%D1\;mov%D1\\t%0, #0\;mvn%d1\\t%0, #0"
368 "TARGET_THUMB2"
369 [(set (match_dup 0)
370 (if_then_else:SI (match_dup 1)
371 (match_dup 3)
372 (const_int 0)))]
373 {
374 operands[3] = GEN_INT (~0);
375 }
376 [(set_attr "conds" "use")
377 (set_attr "length" "10")
378 (set_attr "type" "multiple")]
379 )
381 (define_insn_and_split "*thumb2_mov_negscc_strict_it"
382 [(set (match_operand:SI 0 "low_register_operand" "=l")
383 (neg:SI (match_operator:SI 1 "arm_comparison_operator_mode"
384 [(match_operand 2 "cc_register" "") (const_int 0)])))]
385 "TARGET_THUMB2 && arm_restrict_it"
386 "#" ; ";mvn\\t%0, #0 ;it\\t%D1\;mov%D1\\t%0, #0\"
387 "&& reload_completed"
388 [(set (match_dup 0)
389 (match_dup 3))
390 (cond_exec (match_dup 4)
391 (set (match_dup 0)
392 (const_int 0)))]
393 {
394 operands[3] = GEN_INT (~0);
395 machine_mode mode = GET_MODE (operands[2]);
396 enum rtx_code rc = GET_CODE (operands[1]);
398 if (mode == CCFPmode || mode == CCFPEmode)
399 rc = reverse_condition_maybe_unordered (rc);
400 else
401 rc = reverse_condition (rc);
402 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
404 }
405 [(set_attr "conds" "use")
406 (set_attr "length" "8")
407 (set_attr "type" "multiple")]
408 )
410 (define_insn_and_split "*thumb2_mov_notscc"
411 [(set (match_operand:SI 0 "s_register_operand" "=r")
412 (not:SI (match_operator:SI 1 "arm_comparison_operator_mode"
413 [(match_operand 2 "cc_register" "") (const_int 0)])))]
414 "TARGET_THUMB2 && !arm_restrict_it"
415 "#" ; "ite\\t%D1\;mvn%D1\\t%0, #0\;mvn%d1\\t%0, #1"
416 "TARGET_THUMB2"
417 [(set (match_dup 0)
418 (if_then_else:SI (match_dup 1)
419 (match_dup 3)
420 (match_dup 4)))]
421 {
422 operands[3] = GEN_INT (~1);
423 operands[4] = GEN_INT (~0);
424 }
425 [(set_attr "conds" "use")
426 (set_attr "length" "10")
427 (set_attr "type" "multiple")]
428 )
430 (define_insn_and_split "*thumb2_mov_notscc_strict_it"
431 [(set (match_operand:SI 0 "low_register_operand" "=l")
432 (not:SI (match_operator:SI 1 "arm_comparison_operator_mode"
433 [(match_operand 2 "cc_register" "") (const_int 0)])))]
434 "TARGET_THUMB2 && arm_restrict_it"
435 "#" ; "mvn %0, #0 ; it%d1 ; lsl%d1 %0, %0, #1"
436 "&& reload_completed"
437 [(set (match_dup 0)
438 (match_dup 3))
439 (cond_exec (match_dup 4)
440 (set (match_dup 0)
441 (ashift:SI (match_dup 0)
442 (const_int 1))))]
443 {
444 operands[3] = GEN_INT (~0);
445 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
446 VOIDmode, operands[2], const0_rtx);
447 }
448 [(set_attr "conds" "use")
449 (set_attr "length" "8")
450 (set_attr "type" "multiple")]
451 )
453 (define_insn_and_split "*thumb2_movsicc_insn"
454 [(set (match_operand:SI 0 "s_register_operand" "=l,l,r,r,r,r,r,r,r,r,r,r")
455 (if_then_else:SI
456 (match_operator 3 "arm_comparison_operator"
457 [(match_operand 4 "cc_register" "") (const_int 0)])
458 (match_operand:SI 1 "arm_not_operand" "0 ,lPy,0 ,0,rI,K,I ,r,rI,K ,K,r")
459 (match_operand:SI 2 "arm_not_operand" "lPy,0 ,rI,K,0 ,0,rI,I,K ,rI,K,r")))]
460 "TARGET_THUMB2"
461 "@
462 it\\t%D3\;mov%D3\\t%0, %2
463 it\\t%d3\;mov%d3\\t%0, %1
464 it\\t%D3\;mov%D3\\t%0, %2
465 it\\t%D3\;mvn%D3\\t%0, #%B2
466 it\\t%d3\;mov%d3\\t%0, %1
467 it\\t%d3\;mvn%d3\\t%0, #%B1
468 #
469 #
470 #
471 #
472 #
473 #"
474 ; alt 6: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
475 ; alt 7: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
476 ; alt 8: ite\\t%d3\;mov%d3\\t%0, %1\;mvn%D3\\t%0, #%B2
477 ; alt 9: ite\\t%d3\;mvn%d3\\t%0, #%B1\;mov%D3\\t%0, %2
478 ; alt 10: ite\\t%d3\;mvn%d3\\t%0, #%B1\;mvn%D3\\t%0, #%B2
479 ; alt 11: ite\\t%d3\;mov%d3\\t%0, %1\;mov%D3\\t%0, %2
480 "&& reload_completed"
481 [(const_int 0)]
482 {
483 enum rtx_code rev_code;
484 machine_mode mode;
485 rtx rev_cond;
487 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
488 operands[3],
489 gen_rtx_SET (operands[0], operands[1])));
490 rev_code = GET_CODE (operands[3]);
491 mode = GET_MODE (operands[4]);
492 if (mode == CCFPmode || mode == CCFPEmode)
493 rev_code = reverse_condition_maybe_unordered (rev_code);
494 else
495 rev_code = reverse_condition (rev_code);
497 rev_cond = gen_rtx_fmt_ee (rev_code,
498 VOIDmode,
499 gen_rtx_REG (mode, CC_REGNUM),
500 const0_rtx);
501 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
502 rev_cond,
503 gen_rtx_SET (operands[0], operands[2])));
504 DONE;
505 }
506 [(set_attr "length" "4,4,6,6,6,6,10,8,10,10,10,6")
507 (set_attr "enabled_for_depr_it" "yes,yes,no,no,no,no,no,no,no,no,no,yes")
508 (set_attr "conds" "use")
509 (set_attr_alternative "type"
510 [(if_then_else (match_operand 2 "const_int_operand" "")
511 (const_string "mov_imm")
512 (const_string "mov_reg"))
513 (if_then_else (match_operand 1 "const_int_operand" "")
514 (const_string "mov_imm")
515 (const_string "mov_reg"))
516 (if_then_else (match_operand 2 "const_int_operand" "")
517 (const_string "mov_imm")
518 (const_string "mov_reg"))
519 (const_string "mvn_imm")
520 (if_then_else (match_operand 1 "const_int_operand" "")
521 (const_string "mov_imm")
522 (const_string "mov_reg"))
523 (const_string "mvn_imm")
524 (const_string "multiple")
525 (const_string "multiple")
526 (const_string "multiple")
527 (const_string "multiple")
528 (const_string "multiple")
529 (const_string "multiple")])]
530 )
532 (define_insn "*thumb2_movsfcc_soft_insn"
533 [(set (match_operand:SF 0 "s_register_operand" "=r,r")
534 (if_then_else:SF (match_operator 3 "arm_comparison_operator"
535 [(match_operand 4 "cc_register" "") (const_int 0)])
536 (match_operand:SF 1 "s_register_operand" "0,r")
537 (match_operand:SF 2 "s_register_operand" "r,0")))]
538 "TARGET_THUMB2 && TARGET_SOFT_FLOAT"
539 "@
540 it\\t%D3\;mov%D3\\t%0, %2
541 it\\t%d3\;mov%d3\\t%0, %1"
542 [(set_attr "length" "6,6")
543 (set_attr "conds" "use")
544 (set_attr "type" "multiple")]
545 )
547 (define_insn "*call_reg_thumb2"
548 [(call (mem:SI (match_operand:SI 0 "s_register_operand" "r"))
549 (match_operand 1 "" ""))
550 (use (match_operand 2 "" ""))
551 (clobber (reg:SI LR_REGNUM))]
552 "TARGET_THUMB2"
553 "blx%?\\t%0"
554 [(set_attr "type" "call")]
555 )
557 (define_insn "*nonsecure_call_reg_thumb2"
558 [(call (unspec:SI [(mem:SI (match_operand:SI 0 "s_register_operand" "r"))]
559 UNSPEC_NONSECURE_MEM)
560 (match_operand 1 "" ""))
561 (use (match_operand 2 "" ""))
562 (clobber (reg:SI LR_REGNUM))
563 (clobber (match_dup 0))]
564 "TARGET_THUMB2 && use_cmse"
565 "bl\\t__gnu_cmse_nonsecure_call"
566 [(set_attr "length" "4")
567 (set_attr "type" "call")]
568 )
570 (define_insn "*call_value_reg_thumb2"
571 [(set (match_operand 0 "" "")
572 (call (mem:SI (match_operand:SI 1 "register_operand" "l*r"))
573 (match_operand 2 "" "")))
574 (use (match_operand 3 "" ""))
575 (clobber (reg:SI LR_REGNUM))]
576 "TARGET_THUMB2"
577 "blx\\t%1"
578 [(set_attr "type" "call")]
579 )
581 (define_insn "*nonsecure_call_value_reg_thumb2"
582 [(set (match_operand 0 "" "")
583 (call
584 (unspec:SI [(mem:SI (match_operand:SI 1 "register_operand" "l*r"))]
585 UNSPEC_NONSECURE_MEM)
586 (match_operand 2 "" "")))
587 (use (match_operand 3 "" ""))
588 (clobber (reg:SI LR_REGNUM))
589 (clobber (match_dup 1))]
590 "TARGET_THUMB2 && use_cmse"
591 "bl\t__gnu_cmse_nonsecure_call"
592 [(set_attr "length" "4")
593 (set_attr "type" "call")]
594 )
596 (define_insn "*thumb2_indirect_jump"
597 [(set (pc)
598 (match_operand:SI 0 "register_operand" "l*r"))]
599 "TARGET_THUMB2"
600 "bx\\t%0"
601 [(set_attr "conds" "clob")
602 (set_attr "type" "branch")]
603 )
604 ;; Don't define thumb2_load_indirect_jump because we can't guarantee label
605 ;; addresses will have the thumb bit set correctly.
608 (define_insn_and_split "*thumb2_and_scc"
609 [(set (match_operand:SI 0 "s_register_operand" "=Ts")
610 (and:SI (match_operator:SI 1 "arm_comparison_operator"
611 [(match_operand 2 "cc_register" "") (const_int 0)])
612 (match_operand:SI 3 "s_register_operand" "r")))]
613 "TARGET_THUMB2"
614 "#" ; "and\\t%0, %3, #1\;it\\t%D1\;mov%D1\\t%0, #0"
615 "&& reload_completed"
616 [(set (match_dup 0)
617 (and:SI (match_dup 3) (const_int 1)))
618 (cond_exec (match_dup 4) (set (match_dup 0) (const_int 0)))]
619 {
620 machine_mode mode = GET_MODE (operands[2]);
621 enum rtx_code rc = GET_CODE (operands[1]);
623 if (mode == CCFPmode || mode == CCFPEmode)
624 rc = reverse_condition_maybe_unordered (rc);
625 else
626 rc = reverse_condition (rc);
627 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
628 }
629 [(set_attr "conds" "use")
630 (set_attr "type" "multiple")
631 (set (attr "length") (if_then_else (match_test "arm_restrict_it")
632 (const_int 8)
633 (const_int 10)))]
634 )
636 (define_insn_and_split "*thumb2_ior_scc"
637 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
638 (ior:SI (match_operator:SI 1 "arm_comparison_operator"
639 [(match_operand 2 "cc_register" "") (const_int 0)])
640 (match_operand:SI 3 "s_register_operand" "0,?r")))]
641 "TARGET_THUMB2 && !arm_restrict_it"
642 "@
643 it\\t%d1\;orr%d1\\t%0, %3, #1
644 #"
645 ; alt 1: ite\\t%D1\;mov%D1\\t%0, %3\;orr%d1\\t%0, %3, #1
646 "&& reload_completed
647 && REGNO (operands [0]) != REGNO (operands[3])"
648 [(cond_exec (match_dup 5) (set (match_dup 0) (match_dup 3)))
649 (cond_exec (match_dup 4) (set (match_dup 0)
650 (ior:SI (match_dup 3) (const_int 1))))]
651 {
652 machine_mode mode = GET_MODE (operands[2]);
653 enum rtx_code rc = GET_CODE (operands[1]);
655 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
656 if (mode == CCFPmode || mode == CCFPEmode)
657 rc = reverse_condition_maybe_unordered (rc);
658 else
659 rc = reverse_condition (rc);
660 operands[5] = gen_rtx_fmt_ee (rc, VOIDmode, operands[2], const0_rtx);
661 }
662 [(set_attr "conds" "use")
663 (set_attr "length" "6,10")
664 (set_attr "type" "multiple")]
665 )
667 (define_insn_and_split "*thumb2_ior_scc_strict_it"
668 [(set (match_operand:SI 0 "s_register_operand" "=&r")
669 (ior:SI (match_operator:SI 2 "arm_comparison_operator"
670 [(match_operand 3 "cc_register" "") (const_int 0)])
671 (match_operand:SI 1 "s_register_operand" "r")))]
672 "TARGET_THUMB2 && arm_restrict_it"
673 "#" ; orr\\t%0, %1, #1\;it\\t%D2\;mov%D2\\t%0, %1
674 "&& reload_completed"
675 [(set (match_dup 0) (ior:SI (match_dup 1) (const_int 1)))
676 (cond_exec (match_dup 4)
677 (set (match_dup 0) (match_dup 1)))]
678 {
679 machine_mode mode = GET_MODE (operands[3]);
680 rtx_code rc = GET_CODE (operands[2]);
682 if (mode == CCFPmode || mode == CCFPEmode)
683 rc = reverse_condition_maybe_unordered (rc);
684 else
685 rc = reverse_condition (rc);
686 operands[4] = gen_rtx_fmt_ee (rc, VOIDmode, operands[3], const0_rtx);
687 }
688 [(set_attr "conds" "use")
689 (set_attr "length" "8")
690 (set_attr "type" "multiple")]
691 )
693 (define_insn "*thumb2_cond_move"
694 [(set (match_operand:SI 0 "s_register_operand" "=r,r,r")
695 (if_then_else:SI (match_operator 3 "equality_operator"
696 [(match_operator 4 "arm_comparison_operator"
697 [(match_operand 5 "cc_register" "") (const_int 0)])
698 (const_int 0)])
699 (match_operand:SI 1 "arm_rhs_operand" "0,rI,?rI")
700 (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI")))]
701 "TARGET_THUMB2"
702 "*
703 if (GET_CODE (operands[3]) == NE)
704 {
705 if (which_alternative != 1)
706 output_asm_insn (\"it\\t%D4\;mov%D4\\t%0, %2\", operands);
707 if (which_alternative != 0)
708 output_asm_insn (\"it\\t%d4\;mov%d4\\t%0, %1\", operands);
709 return \"\";
710 }
711 switch (which_alternative)
712 {
713 case 0:
714 output_asm_insn (\"it\\t%d4\", operands);
715 break;
716 case 1:
717 output_asm_insn (\"it\\t%D4\", operands);
718 break;
719 case 2:
720 if (arm_restrict_it)
721 output_asm_insn (\"it\\t%D4\", operands);
722 else
723 output_asm_insn (\"ite\\t%D4\", operands);
724 break;
725 default:
726 abort();
727 }
728 if (which_alternative != 0)
729 {
730 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
731 if (arm_restrict_it && which_alternative == 2)
732 output_asm_insn (\"it\\t%d4\", operands);
733 }
734 if (which_alternative != 1)
735 output_asm_insn (\"mov%d4\\t%0, %2\", operands);
736 return \"\";
737 "
738 [(set_attr "conds" "use")
739 (set_attr "length" "6,6,10")
740 (set_attr "type" "multiple")]
741 )
743 (define_insn "*thumb2_cond_arith"
744 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
745 (match_operator:SI 5 "shiftable_operator"
746 [(match_operator:SI 4 "arm_comparison_operator"
747 [(match_operand:SI 2 "s_register_operand" "r,r")
748 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
749 (match_operand:SI 1 "s_register_operand" "0,?r")]))
750 (clobber (reg:CC CC_REGNUM))]
751 "TARGET_THUMB2 && !arm_restrict_it"
752 "*
753 if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
754 return \"%i5\\t%0, %1, %2, lsr #31\";
756 output_asm_insn (\"cmp\\t%2, %3\", operands);
757 if (GET_CODE (operands[5]) == AND)
758 {
759 output_asm_insn (\"ite\\t%D4\", operands);
760 output_asm_insn (\"mov%D4\\t%0, #0\", operands);
761 }
762 else if (GET_CODE (operands[5]) == MINUS)
763 {
764 output_asm_insn (\"ite\\t%D4\", operands);
765 output_asm_insn (\"rsb%D4\\t%0, %1, #0\", operands);
766 }
767 else if (which_alternative != 0)
768 {
769 output_asm_insn (\"ite\\t%D4\", operands);
770 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
771 }
772 else
773 output_asm_insn (\"it\\t%d4\", operands);
774 return \"%i5%d4\\t%0, %1, #1\";
775 "
776 [(set_attr "conds" "clob")
777 (set_attr "length" "14")
778 (set_attr "type" "multiple")]
779 )
781 (define_insn_and_split "*thumb2_cond_arith_strict_it"
782 [(set (match_operand:SI 0 "s_register_operand" "=l")
783 (match_operator:SI 5 "shiftable_operator_strict_it"
784 [(match_operator:SI 4 "arm_comparison_operator"
785 [(match_operand:SI 2 "s_register_operand" "r")
786 (match_operand:SI 3 "arm_rhs_operand" "rI")])
787 (match_operand:SI 1 "s_register_operand" "0")]))
788 (clobber (reg:CC CC_REGNUM))]
789 "TARGET_THUMB2 && arm_restrict_it"
790 "#"
791 "&& reload_completed"
792 [(const_int 0)]
793 {
794 if (GET_CODE (operands[4]) == LT && operands[3] == const0_rtx)
795 {
796 /* %i5 %0, %1, %2, lsr #31 */
797 rtx shifted_op = gen_rtx_LSHIFTRT (SImode, operands[2], GEN_INT (31));
798 rtx op = NULL_RTX;
800 switch (GET_CODE (operands[5]))
801 {
802 case AND:
803 op = gen_rtx_AND (SImode, shifted_op, operands[1]);
804 break;
805 case PLUS:
806 op = gen_rtx_PLUS (SImode, shifted_op, operands[1]);
807 break;
808 default: gcc_unreachable ();
809 }
810 emit_insn (gen_rtx_SET (operands[0], op));
811 DONE;
812 }
814 /* "cmp %2, %3" */
815 emit_insn (gen_rtx_SET (gen_rtx_REG (CCmode, CC_REGNUM),
816 gen_rtx_COMPARE (CCmode, operands[2],
817 operands[3])));
819 if (GET_CODE (operands[5]) == AND)
820 {
821 /* %i5 %0, %1, #1
822 it%D4
823 mov%D4 %0, #0 */
824 enum rtx_code rc = reverse_condition (GET_CODE (operands[4]));
825 emit_insn (gen_rtx_SET (operands[0], gen_rtx_AND (SImode, operands[1],
826 GEN_INT (1))));
827 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
828 gen_rtx_fmt_ee (rc, VOIDmode, gen_rtx_REG (CCmode, CC_REGNUM), const0_rtx),
829 gen_rtx_SET (operands[0], const0_rtx)));
830 DONE;
831 }
832 else
833 {
834 /* it\\t%d4
835 %i5%d4\\t%0, %1, #1 */
836 emit_insn (gen_rtx_COND_EXEC (VOIDmode, gen_rtx_fmt_ee (GET_CODE (operands[4]),
837 VOIDmode,
838 gen_rtx_REG (CCmode, CC_REGNUM), const0_rtx),
839 gen_rtx_SET (operands[0],
840 gen_rtx_PLUS (SImode,
841 operands[1],
842 GEN_INT (1)))));
843 DONE;
844 }
845 FAIL;
846 }
847 [(set_attr "conds" "clob")
848 (set_attr "length" "12")
849 (set_attr "type" "multiple")]
850 )
852 (define_insn "*thumb2_cond_sub"
853 [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts")
854 (minus:SI (match_operand:SI 1 "s_register_operand" "0,?Ts")
855 (match_operator:SI 4 "arm_comparison_operator"
856 [(match_operand:SI 2 "s_register_operand" "r,r")
857 (match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
858 (clobber (reg:CC CC_REGNUM))]
859 "TARGET_THUMB2"
860 "*
861 output_asm_insn (\"cmp\\t%2, %3\", operands);
862 if (which_alternative != 0)
863 {
864 if (arm_restrict_it)
865 {
866 output_asm_insn (\"mov\\t%0, %1\", operands);
867 output_asm_insn (\"it\\t%d4\", operands);
868 }
869 else
870 {
871 output_asm_insn (\"ite\\t%D4\", operands);
872 output_asm_insn (\"mov%D4\\t%0, %1\", operands);
873 }
874 }
875 else
876 output_asm_insn (\"it\\t%d4\", operands);
877 return \"sub%d4\\t%0, %1, #1\";
878 "
879 [(set_attr "conds" "clob")
880 (set_attr "length" "10,14")
881 (set_attr "type" "multiple")]
882 )
884 (define_insn_and_split "*thumb2_negscc"
885 [(set (match_operand:SI 0 "s_register_operand" "=Ts")
886 (neg:SI (match_operator 3 "arm_comparison_operator"
887 [(match_operand:SI 1 "s_register_operand" "r")
888 (match_operand:SI 2 "arm_rhs_operand" "rI")])))
889 (clobber (reg:CC CC_REGNUM))]
890 "TARGET_THUMB2"
891 "#"
892 "&& reload_completed"
893 [(const_int 0)]
894 {
895 rtx cc_reg = gen_rtx_REG (CCmode, CC_REGNUM);
897 if (GET_CODE (operands[3]) == LT && operands[2] == const0_rtx)
898 {
899 /* Emit asr\\t%0, %1, #31 */
900 emit_insn (gen_rtx_SET (operands[0],
901 gen_rtx_ASHIFTRT (SImode,
902 operands[1],
903 GEN_INT (31))));
904 DONE;
905 }
906 else if (GET_CODE (operands[3]) == NE && !arm_restrict_it)
907 {
908 /* Emit subs\\t%0, %1, %2\;it\\tne\;mvnne\\t%0, #0 */
909 if (CONST_INT_P (operands[2]))
910 emit_insn (gen_cmpsi2_addneg (operands[0], operands[1], operands[2],
911 GEN_INT (- INTVAL (operands[2]))));
912 else
913 emit_insn (gen_subsi3_compare (operands[0], operands[1], operands[2]));
915 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
916 gen_rtx_NE (SImode,
917 cc_reg,
918 const0_rtx),
919 gen_rtx_SET (operands[0],
920 GEN_INT (~0))));
921 DONE;
922 }
923 else
924 {
925 /* Emit: cmp\\t%1, %2\;mvn\\t%0, #0\;it\\t%D3\;mov%D3\\t%0, #0\;*/
926 enum rtx_code rc = reverse_condition (GET_CODE (operands[3]));
927 machine_mode mode = SELECT_CC_MODE (rc, operands[1], operands[2]);
928 rtx tmp1 = gen_rtx_REG (mode, CC_REGNUM);
930 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (CCmode, operands[1],
931 operands[2])));
933 emit_insn (gen_rtx_SET (operands[0], GEN_INT (~0)));
935 emit_insn (gen_rtx_COND_EXEC (VOIDmode,
936 gen_rtx_fmt_ee (rc,
937 VOIDmode,
938 tmp1,
939 const0_rtx),
940 gen_rtx_SET (operands[0], const0_rtx)));
941 DONE;
942 }
943 FAIL;
944 }
945 [(set_attr "conds" "clob")
946 (set_attr "length" "14")
947 (set_attr "type" "multiple")]
948 )
950 (define_insn "*thumb2_movcond"
951 [(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts,Ts")
952 (if_then_else:SI
953 (match_operator 5 "arm_comparison_operator"
954 [(match_operand:SI 3 "s_register_operand" "r,r,r")
955 (match_operand:SI 4 "arm_add_operand" "rIL,rIL,rIL")])
956 (match_operand:SI 1 "arm_rhs_operand" "0,TsI,?TsI")
957 (match_operand:SI 2 "arm_rhs_operand" "TsI,0,TsI")))
958 (clobber (reg:CC CC_REGNUM))]
959 "TARGET_THUMB2"
960 "*
961 if (GET_CODE (operands[5]) == LT
962 && (operands[4] == const0_rtx))
963 {
964 if (which_alternative != 1 && REG_P (operands[1]))
965 {
966 if (operands[2] == const0_rtx)
967 return \"and\\t%0, %1, %3, asr #31\";
968 return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\";
969 }
970 else if (which_alternative != 0 && REG_P (operands[2]))
971 {
972 if (operands[1] == const0_rtx)
973 return \"bic\\t%0, %2, %3, asr #31\";
974 return \"bics\\t%0, %2, %3, asr #32\;it\\tcs\;movcs\\t%0, %1\";
975 }
976 /* The only case that falls through to here is when both ops 1 & 2
977 are constants. */
978 }
980 if (GET_CODE (operands[5]) == GE
981 && (operands[4] == const0_rtx))
982 {
983 if (which_alternative != 1 && REG_P (operands[1]))
984 {
985 if (operands[2] == const0_rtx)
986 return \"bic\\t%0, %1, %3, asr #31\";
987 return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\";
988 }
989 else if (which_alternative != 0 && REG_P (operands[2]))
990 {
991 if (operands[1] == const0_rtx)
992 return \"and\\t%0, %2, %3, asr #31\";
993 return \"ands\\t%0, %2, %3, asr #32\;it\tcc\;movcc\\t%0, %1\";
994 }
995 /* The only case that falls through to here is when both ops 1 & 2
996 are constants. */
997 }
998 if (CONST_INT_P (operands[4])
999 && !const_ok_for_arm (INTVAL (operands[4])))
1000 output_asm_insn (\"cmn\\t%3, #%n4\", operands);
1001 else
1002 output_asm_insn (\"cmp\\t%3, %4\", operands);
1003 switch (which_alternative)
1004 {
1005 case 0:
1006 output_asm_insn (\"it\\t%D5\", operands);
1007 break;
1008 case 1:
1009 output_asm_insn (\"it\\t%d5\", operands);
1010 break;
1011 case 2:
1012 if (arm_restrict_it)
1013 {
1014 output_asm_insn (\"mov\\t%0, %1\", operands);
1015 output_asm_insn (\"it\\t%D5\", operands);
1016 }
1017 else
1018 output_asm_insn (\"ite\\t%d5\", operands);
1019 break;
1020 default:
1021 abort();
1022 }
1023 if (which_alternative != 0 && !(arm_restrict_it && which_alternative == 2))
1024 output_asm_insn (\"mov%d5\\t%0, %1\", operands);
1025 if (which_alternative != 1)
1026 output_asm_insn (\"mov%D5\\t%0, %2\", operands);
1027 return \"\";
1028 "
1029 [(set_attr "conds" "clob")
1030 (set_attr "length" "10,10,14")
1031 (set_attr "type" "multiple")]
1032 )
1034 ;; Zero and sign extension instructions.
1036 ;; All supported Thumb2 implementations are armv6, so only that case is
1037 ;; provided.
1038 (define_insn "*thumb2_extendqisi_v6"
1039 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1040 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1041 "TARGET_THUMB2 && arm_arch6"
1042 "@
1043 sxtb%?\\t%0, %1
1044 ldrsb%?\\t%0, %1"
1045 [(set_attr "type" "extend,load_byte")
1046 (set_attr "predicable" "yes")
1047 (set_attr "predicable_short_it" "no")
1048 (set_attr "pool_range" "*,4094")
1049 (set_attr "neg_pool_range" "*,250")]
1050 )
1052 (define_insn "*thumb2_zero_extendhisi2_v6"
1053 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1054 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1055 "TARGET_THUMB2 && arm_arch6"
1056 "@
1057 uxth%?\\t%0, %1
1058 ldrh%?\\t%0, %1"
1059 [(set_attr "type" "extend,load_byte")
1060 (set_attr "predicable" "yes")
1061 (set_attr "predicable_short_it" "no")
1062 (set_attr "pool_range" "*,4094")
1063 (set_attr "neg_pool_range" "*,250")]
1064 )
1066 (define_insn "thumb2_zero_extendqisi2_v6"
1067 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
1068 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1069 "TARGET_THUMB2 && arm_arch6"
1070 "@
1071 uxtb%?\\t%0, %1
1072 ldrb%?\\t%0, %1\\t%@ zero_extendqisi2"
1073 [(set_attr "type" "extend,load_byte")
1074 (set_attr "predicable" "yes")
1075 (set_attr "predicable_short_it" "no")
1076 (set_attr "pool_range" "*,4094")
1077 (set_attr "neg_pool_range" "*,250")]
1078 )
1080 (define_insn "thumb2_casesi_internal"
1081 [(parallel [(set (pc)
1082 (if_then_else
1083 (leu (match_operand:SI 0 "s_register_operand" "r")
1084 (match_operand:SI 1 "arm_rhs_operand" "rI"))
1085 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
1086 (label_ref (match_operand 2 "" ""))))
1087 (label_ref (match_operand 3 "" ""))))
1088 (clobber (reg:CC CC_REGNUM))
1089 (clobber (match_scratch:SI 4 "=&r"))
1090 (use (label_ref (match_dup 2)))])]
1091 "TARGET_THUMB2 && !flag_pic"
1092 "* return thumb2_output_casesi(operands);"
1093 [(set_attr "conds" "clob")
1094 (set_attr "length" "16")
1095 (set_attr "type" "multiple")]
1096 )
1098 (define_insn "thumb2_casesi_internal_pic"
1099 [(parallel [(set (pc)
1100 (if_then_else
1101 (leu (match_operand:SI 0 "s_register_operand" "r")
1102 (match_operand:SI 1 "arm_rhs_operand" "rI"))
1103 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
1104 (label_ref (match_operand 2 "" ""))))
1105 (label_ref (match_operand 3 "" ""))))
1106 (clobber (reg:CC CC_REGNUM))
1107 (clobber (match_scratch:SI 4 "=&r"))
1108 (clobber (match_scratch:SI 5 "=r"))
1109 (use (label_ref (match_dup 2)))])]
1110 "TARGET_THUMB2 && flag_pic"
1111 "* return thumb2_output_casesi(operands);"
1112 [(set_attr "conds" "clob")
1113 (set_attr "length" "20")
1114 (set_attr "type" "multiple")]
1115 )
1117 (define_insn "*thumb2_return"
1118 [(simple_return)]
1119 "TARGET_THUMB2 && !IS_CMSE_ENTRY (arm_current_func_type ())"
1120 "* return output_return_instruction (const_true_rtx, true, false, true);"
1121 [(set_attr "type" "branch")
1122 (set_attr "length" "4")]
1123 )
1125 (define_insn "*thumb2_cmse_entry_return"
1126 [(simple_return)]
1127 "TARGET_THUMB2 && IS_CMSE_ENTRY (arm_current_func_type ())"
1128 "* return output_return_instruction (const_true_rtx, true, false, true);"
1129 [(set_attr "type" "branch")
1130 ; This is a return from a cmse_nonsecure_entry function so code will be
1131 ; added to clear the APSR and potentially the FPSCR if VFP is available, so
1132 ; we adapt the length accordingly.
1133 (set (attr "length")
1134 (if_then_else (match_test "TARGET_HARD_FLOAT")
1135 (const_int 12)
1136 (const_int 8)))
1137 ; We do not support predicate execution of returns from cmse_nonsecure_entry
1138 ; functions because we need to clear the APSR. Since predicable has to be
1139 ; a constant, we had to duplicate the thumb2_return pattern for CMSE entry
1140 ; functions.
1141 (set_attr "predicable" "no")]
1142 )
1144 (define_insn_and_split "thumb2_eh_return"
1145 [(unspec_volatile [(match_operand:SI 0 "s_register_operand" "r")]
1146 VUNSPEC_EH_RETURN)
1147 (clobber (match_scratch:SI 1 "=&r"))]
1148 "TARGET_THUMB2"
1149 "#"
1150 "&& reload_completed"
1151 [(const_int 0)]
1152 "
1153 {
1154 thumb_set_return_address (operands[0], operands[1]);
1155 DONE;
1156 }"
1157 )
1159 (define_insn "*thumb2_alusi3_short"
1160 [(set (match_operand:SI 0 "s_register_operand" "=l")
1161 (match_operator:SI 3 "thumb_16bit_operator"
1162 [(match_operand:SI 1 "s_register_operand" "0")
1163 (match_operand:SI 2 "s_register_operand" "l")]))
1164 (clobber (reg:CC CC_REGNUM))]
1165 "TARGET_THUMB2 && reload_completed
1166 && GET_CODE(operands[3]) != PLUS
1167 && GET_CODE(operands[3]) != MINUS"
1168 "%I3%!\\t%0, %1, %2"
1169 [(set_attr "predicable" "yes")
1170 (set_attr "length" "2")
1171 (set_attr "type" "alu_sreg")]
1172 )
1174 (define_insn "*thumb2_shiftsi3_short"
1175 [(set (match_operand:SI 0 "low_register_operand" "=l,l")
1176 (match_operator:SI 3 "shift_operator"
1177 [(match_operand:SI 1 "low_register_operand" "0,l")
1178 (match_operand:SI 2 "low_reg_or_int_operand" "l,M")]))
1179 (clobber (reg:CC CC_REGNUM))]
1180 "TARGET_THUMB2 && reload_completed
1181 && ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
1182 || REG_P (operands[2]))"
1183 "* return arm_output_shift(operands, 2);"
1184 [(set_attr "predicable" "yes")
1185 (set_attr "shift" "1")
1186 (set_attr "length" "2")
1187 (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
1188 (const_string "alu_shift_imm")
1189 (const_string "alu_shift_reg")))]
1190 )
1192 (define_insn "*thumb2_mov<mode>_shortim"
1193 [(set (match_operand:QHSI 0 "low_register_operand" "=l")
1194 (match_operand:QHSI 1 "const_int_operand" "I"))
1195 (clobber (reg:CC CC_REGNUM))]
1196 "TARGET_THUMB2 && reload_completed"
1197 "mov%!\t%0, %1"
1198 [(set_attr "predicable" "yes")
1199 (set_attr "length" "2")
1200 (set_attr "type" "mov_imm")]
1201 )
1203 (define_insn "*thumb2_addsi_short"
1204 [(set (match_operand:SI 0 "low_register_operand" "=l,l")
1205 (plus:SI (match_operand:SI 1 "low_register_operand" "l,0")
1206 (match_operand:SI 2 "low_reg_or_int_operand" "lPt,Ps")))
1207 (clobber (reg:CC CC_REGNUM))]
1208 "TARGET_THUMB2 && reload_completed"
1209 "*
1210 HOST_WIDE_INT val;
1212 if (CONST_INT_P (operands[2]))
1213 val = INTVAL(operands[2]);
1214 else
1215 val = 0;
1217 /* We prefer eg. subs rn, rn, #1 over adds rn, rn, #0xffffffff. */
1218 if (val < 0 && const_ok_for_arm(ARM_SIGN_EXTEND (-val)))
1219 return \"sub%!\\t%0, %1, #%n2\";
1220 else
1221 return \"add%!\\t%0, %1, %2\";
1222 "
1223 [(set_attr "predicable" "yes")
1224 (set_attr "length" "2")
1225 (set_attr_alternative "type"
1226 [(if_then_else (match_operand 2 "const_int_operand" "")
1227 (const_string "alu_imm")
1228 (const_string "alu_sreg"))
1229 (const_string "alu_imm")])]
1230 )
1232 (define_insn "*thumb2_subsi_short"
1233 [(set (match_operand:SI 0 "low_register_operand" "=l")
1234 (minus:SI (match_operand:SI 1 "low_register_operand" "l")
1235 (match_operand:SI 2 "low_register_operand" "l")))
1236 (clobber (reg:CC CC_REGNUM))]
1237 "TARGET_THUMB2 && reload_completed"
1238 "sub%!\\t%0, %1, %2"
1239 [(set_attr "predicable" "yes")
1240 (set_attr "length" "2")
1241 (set_attr "type" "alu_sreg")]
1242 )
1244 (define_peephole2
1245 [(set (match_operand:CC 0 "cc_register" "")
1246 (compare:CC (match_operand:SI 1 "low_register_operand" "")
1247 (match_operand:SI 2 "const_int_operand" "")))]
1248 "TARGET_THUMB2
1249 && peep2_reg_dead_p (1, operands[1])
1250 && satisfies_constraint_Pw (operands[2])"
1251 [(parallel
1252 [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
1253 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 3)))])]
1254 "operands[3] = GEN_INT (- INTVAL (operands[2]));"
1255 )
1257 (define_peephole2
1258 [(match_scratch:SI 3 "l")
1259 (set (match_operand:CC 0 "cc_register" "")
1260 (compare:CC (match_operand:SI 1 "low_register_operand" "")
1261 (match_operand:SI 2 "const_int_operand" "")))]
1262 "TARGET_THUMB2
1263 && satisfies_constraint_Px (operands[2])"
1264 [(parallel
1265 [(set (match_dup 0) (compare:CC (match_dup 1) (match_dup 2)))
1266 (set (match_dup 3) (plus:SI (match_dup 1) (match_dup 4)))])]
1267 "operands[4] = GEN_INT (- INTVAL (operands[2]));"
1268 )
1270 (define_insn "thumb2_addsi3_compare0"
1271 [(set (reg:CC_NOOV CC_REGNUM)
1272 (compare:CC_NOOV
1273 (plus:SI (match_operand:SI 1 "s_register_operand" "l, 0, r")
1274 (match_operand:SI 2 "arm_add_operand" "lPt,Ps,rIL"))
1275 (const_int 0)))
1276 (set (match_operand:SI 0 "s_register_operand" "=l,l,r")
1277 (plus:SI (match_dup 1) (match_dup 2)))]
1278 "TARGET_THUMB2"
1279 "*
1280 HOST_WIDE_INT val;
1282 if (CONST_INT_P (operands[2]))
1283 val = INTVAL (operands[2]);
1284 else
1285 val = 0;
1287 if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
1288 return \"subs\\t%0, %1, #%n2\";
1289 else
1290 return \"adds\\t%0, %1, %2\";
1291 "
1292 [(set_attr "conds" "set")
1293 (set_attr "length" "2,2,4")
1294 (set_attr_alternative "type"
1295 [(if_then_else (match_operand 2 "const_int_operand" "")
1296 (const_string "alus_imm")
1297 (const_string "alus_sreg"))
1298 (const_string "alus_imm")
1299 (if_then_else (match_operand 2 "const_int_operand" "")
1300 (const_string "alus_imm")
1301 (const_string "alus_sreg"))])]
1302 )
1304 (define_insn "*thumb2_addsi3_compare0_scratch"
1305 [(set (reg:CC_NOOV CC_REGNUM)
1306 (compare:CC_NOOV
1307 (plus:SI (match_operand:SI 0 "s_register_operand" "l, r")
1308 (match_operand:SI 1 "arm_add_operand" "lPv,rIL"))
1309 (const_int 0)))]
1310 "TARGET_THUMB2"
1311 "*
1312 HOST_WIDE_INT val;
1314 if (CONST_INT_P (operands[1]))
1315 val = INTVAL (operands[1]);
1316 else
1317 val = 0;
1319 if (val < 0 && const_ok_for_arm (ARM_SIGN_EXTEND (-val)))
1320 return \"cmp\\t%0, #%n1\";
1321 else
1322 return \"cmn\\t%0, %1\";
1323 "
1324 [(set_attr "conds" "set")
1325 (set_attr "length" "2,4")
1326 (set (attr "type") (if_then_else (match_operand 1 "const_int_operand" "")
1327 (const_string "alus_imm")
1328 (const_string "alus_sreg")))]
1329 )
1331 (define_insn "*thumb2_mulsi_short"
1332 [(set (match_operand:SI 0 "low_register_operand" "=l")
1333 (mult:SI (match_operand:SI 1 "low_register_operand" "%0")
1334 (match_operand:SI 2 "low_register_operand" "l")))
1335 (clobber (reg:CC CC_REGNUM))]
1336 "TARGET_THUMB2 && optimize_size && reload_completed"
1337 "mul%!\\t%0, %2, %0"
1338 [(set_attr "predicable" "yes")
1339 (set_attr "length" "2")
1340 (set_attr "type" "muls")])
1342 (define_insn "*thumb2_mulsi_short_compare0"
1343 [(set (reg:CC_NOOV CC_REGNUM)
1344 (compare:CC_NOOV
1345 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1346 (match_operand:SI 2 "register_operand" "l"))
1347 (const_int 0)))
1348 (set (match_operand:SI 0 "register_operand" "=l")
1349 (mult:SI (match_dup 1) (match_dup 2)))]
1350 "TARGET_THUMB2 && optimize_size"
1351 "muls\\t%0, %2, %0"
1352 [(set_attr "length" "2")
1353 (set_attr "type" "muls")])
1355 (define_insn "*thumb2_mulsi_short_compare0_scratch"
1356 [(set (reg:CC_NOOV CC_REGNUM)
1357 (compare:CC_NOOV
1358 (mult:SI (match_operand:SI 1 "register_operand" "%0")
1359 (match_operand:SI 2 "register_operand" "l"))
1360 (const_int 0)))
1361 (clobber (match_scratch:SI 0 "=l"))]
1362 "TARGET_THUMB2 && optimize_size"
1363 "muls\\t%0, %2, %0"
1364 [(set_attr "length" "2")
1365 (set_attr "type" "muls")])
1367 (define_insn "*thumb2_cbz"
1368 [(set (pc) (if_then_else
1369 (eq (match_operand:SI 0 "s_register_operand" "l,?r")
1370 (const_int 0))
1371 (label_ref (match_operand 1 "" ""))
1372 (pc)))
1373 (clobber (reg:CC CC_REGNUM))]
1374 "TARGET_THUMB2"
1375 "*
1376 if (get_attr_length (insn) == 2)
1377 return \"cbz\\t%0, %l1\";
1378 else
1379 return \"cmp\\t%0, #0\;beq\\t%l1\";
1380 "
1381 [(set (attr "length")
1382 (if_then_else
1383 (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1384 (le (minus (match_dup 1) (pc)) (const_int 128))
1385 (not (match_test "which_alternative")))
1386 (const_int 2)
1387 (const_int 8)))
1388 (set_attr "type" "branch,multiple")]
1389 )
1391 (define_insn "*thumb2_cbnz"
1392 [(set (pc) (if_then_else
1393 (ne (match_operand:SI 0 "s_register_operand" "l,?r")
1394 (const_int 0))
1395 (label_ref (match_operand 1 "" ""))
1396 (pc)))
1397 (clobber (reg:CC CC_REGNUM))]
1398 "TARGET_THUMB2"
1399 "*
1400 if (get_attr_length (insn) == 2)
1401 return \"cbnz\\t%0, %l1\";
1402 else
1403 return \"cmp\\t%0, #0\;bne\\t%l1\";
1404 "
1405 [(set (attr "length")
1406 (if_then_else
1407 (and (ge (minus (match_dup 1) (pc)) (const_int 2))
1408 (le (minus (match_dup 1) (pc)) (const_int 128))
1409 (not (match_test "which_alternative")))
1410 (const_int 2)
1411 (const_int 8)))
1412 (set_attr "type" "branch,multiple")]
1413 )
1415 (define_insn "*thumb2_one_cmplsi2_short"
1416 [(set (match_operand:SI 0 "low_register_operand" "=l")
1417 (not:SI (match_operand:SI 1 "low_register_operand" "l")))
1418 (clobber (reg:CC CC_REGNUM))]
1419 "TARGET_THUMB2 && reload_completed"
1420 "mvn%!\t%0, %1"
1421 [(set_attr "predicable" "yes")
1422 (set_attr "length" "2")
1423 (set_attr "type" "mvn_reg")]
1424 )
1426 (define_insn "*thumb2_negsi2_short"
1427 [(set (match_operand:SI 0 "low_register_operand" "=l")
1428 (neg:SI (match_operand:SI 1 "low_register_operand" "l")))
1429 (clobber (reg:CC CC_REGNUM))]
1430 "TARGET_THUMB2 && reload_completed"
1431 "neg%!\t%0, %1"
1432 [(set_attr "predicable" "yes")
1433 (set_attr "length" "2")
1434 (set_attr "type" "alu_sreg")]
1435 )
1437 ; Constants for op 2 will never be given to these patterns.
1438 (define_insn_and_split "*iordi_notdi_di"
1439 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1440 (ior:DI (not:DI (match_operand:DI 1 "s_register_operand" "0,r"))
1441 (match_operand:DI 2 "s_register_operand" "r,0")))]
1442 "TARGET_THUMB2"
1443 "#"
1444 "TARGET_THUMB2 && reload_completed"
1445 [(set (match_dup 0) (ior:SI (not:SI (match_dup 1)) (match_dup 2)))
1446 (set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))]
1447 "
1448 {
1449 operands[3] = gen_highpart (SImode, operands[0]);
1450 operands[0] = gen_lowpart (SImode, operands[0]);
1451 operands[4] = gen_highpart (SImode, operands[1]);
1452 operands[1] = gen_lowpart (SImode, operands[1]);
1453 operands[5] = gen_highpart (SImode, operands[2]);
1454 operands[2] = gen_lowpart (SImode, operands[2]);
1455 }"
1456 [(set_attr "length" "8")
1457 (set_attr "predicable" "yes")
1458 (set_attr "predicable_short_it" "no")
1459 (set_attr "type" "multiple")]
1460 )
1462 (define_insn_and_split "*iordi_notzesidi_di"
1463 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1464 (ior:DI (not:DI (zero_extend:DI
1465 (match_operand:SI 2 "s_register_operand" "r,r")))
1466 (match_operand:DI 1 "s_register_operand" "0,?r")))]
1467 "TARGET_THUMB2"
1468 "#"
1469 ; (not (zero_extend...)) means operand0 will always be 0xffffffff
1470 "TARGET_THUMB2 && reload_completed"
1471 [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
1472 (set (match_dup 3) (const_int -1))]
1473 "
1474 {
1475 operands[3] = gen_highpart (SImode, operands[0]);
1476 operands[0] = gen_lowpart (SImode, operands[0]);
1477 operands[1] = gen_lowpart (SImode, operands[1]);
1478 }"
1479 [(set_attr "length" "4,8")
1480 (set_attr "predicable" "yes")
1481 (set_attr "predicable_short_it" "no")
1482 (set_attr "type" "multiple")]
1483 )
1485 (define_insn_and_split "*iordi_notdi_zesidi"
1486 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1487 (ior:DI (not:DI (match_operand:DI 2 "s_register_operand" "0,?r"))
1488 (zero_extend:DI
1489 (match_operand:SI 1 "s_register_operand" "r,r"))))]
1490 "TARGET_THUMB2"
1491 "#"
1492 "TARGET_THUMB2 && reload_completed"
1493 [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
1494 (set (match_dup 3) (not:SI (match_dup 4)))]
1495 "
1496 {
1497 operands[3] = gen_highpart (SImode, operands[0]);
1498 operands[0] = gen_lowpart (SImode, operands[0]);
1499 operands[1] = gen_lowpart (SImode, operands[1]);
1500 operands[4] = gen_highpart (SImode, operands[2]);
1501 operands[2] = gen_lowpart (SImode, operands[2]);
1502 }"
1503 [(set_attr "length" "8")
1504 (set_attr "predicable" "yes")
1505 (set_attr "predicable_short_it" "no")
1506 (set_attr "type" "multiple")]
1507 )
1509 (define_insn_and_split "*iordi_notsesidi_di"
1510 [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
1511 (ior:DI (not:DI (sign_extend:DI
1512 (match_operand:SI 2 "s_register_operand" "r,r")))
1513 (match_operand:DI 1 "s_register_operand" "0,r")))]
1514 "TARGET_THUMB2"
1515 "#"
1516 "TARGET_THUMB2 && reload_completed"
1517 [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1)))
1518 (set (match_dup 3) (ior:SI (not:SI
1519 (ashiftrt:SI (match_dup 2) (const_int 31)))
1520 (match_dup 4)))]
1521 "
1522 {
1523 operands[3] = gen_highpart (SImode, operands[0]);
1524 operands[0] = gen_lowpart (SImode, operands[0]);
1525 operands[4] = gen_highpart (SImode, operands[1]);
1526 operands[1] = gen_lowpart (SImode, operands[1]);
1527 }"
1528 [(set_attr "length" "8")
1529 (set_attr "predicable" "yes")
1530 (set_attr "predicable_short_it" "no")
1531 (set_attr "type" "multiple")]
1532 )
1534 (define_insn "*orsi_notsi_si"
1535 [(set (match_operand:SI 0 "s_register_operand" "=r")
1536 (ior:SI (not:SI (match_operand:SI 2 "s_register_operand" "r"))
1537 (match_operand:SI 1 "s_register_operand" "r")))]
1538 "TARGET_THUMB2"
1539 "orn%?\\t%0, %1, %2"
1540 [(set_attr "predicable" "yes")
1541 (set_attr "predicable_short_it" "no")
1542 (set_attr "type" "logic_reg")]
1543 )
1545 (define_insn "*orsi_not_shiftsi_si"
1546 [(set (match_operand:SI 0 "s_register_operand" "=r")
1547 (ior:SI (not:SI (match_operator:SI 4 "shift_operator"
1548 [(match_operand:SI 2 "s_register_operand" "r")
1549 (match_operand:SI 3 "const_int_operand" "M")]))
1550 (match_operand:SI 1 "s_register_operand" "r")))]
1551 "TARGET_THUMB2"
1552 "orn%?\\t%0, %1, %2%S4"
1553 [(set_attr "predicable" "yes")
1554 (set_attr "predicable_short_it" "no")
1555 (set_attr "shift" "2")
1556 (set_attr "type" "alu_shift_imm")]
1557 )
1559 (define_peephole2
1560 [(set (match_operand:CC_NOOV 0 "cc_register" "")
1561 (compare:CC_NOOV (zero_extract:SI
1562 (match_operand:SI 1 "low_register_operand" "")
1563 (const_int 1)
1564 (match_operand:SI 2 "const_int_operand" ""))
1565 (const_int 0)))
1566 (match_scratch:SI 3 "l")
1567 (set (pc)
1568 (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
1569 [(match_dup 0) (const_int 0)])
1570 (match_operand 5 "" "")
1571 (match_operand 6 "" "")))]
1572 "TARGET_THUMB2
1573 && (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32)
1574 && peep2_reg_dead_p (2, operands[0])"
1575 [(parallel [(set (match_dup 0)
1576 (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
1577 (const_int 0)))
1578 (clobber (match_dup 3))])
1579 (set (pc)
1580 (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
1581 (match_dup 5) (match_dup 6)))]
1582 "
1583 operands[2] = GEN_INT (31 - INTVAL (operands[2]));
1584 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[4]) == NE ? LT : GE,
1585 VOIDmode, operands[0], const0_rtx);
1586 ")
1588 (define_peephole2
1589 [(set (match_operand:CC_NOOV 0 "cc_register" "")
1590 (compare:CC_NOOV (zero_extract:SI
1591 (match_operand:SI 1 "low_register_operand" "")
1592 (match_operand:SI 2 "const_int_operand" "")
1593 (const_int 0))
1594 (const_int 0)))
1595 (match_scratch:SI 3 "l")
1596 (set (pc)
1597 (if_then_else (match_operator:CC_NOOV 4 "equality_operator"
1598 [(match_dup 0) (const_int 0)])
1599 (match_operand 5 "" "")
1600 (match_operand 6 "" "")))]
1601 "TARGET_THUMB2
1602 && (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 32)
1603 && peep2_reg_dead_p (2, operands[0])"
1604 [(parallel [(set (match_dup 0)
1605 (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2))
1606 (const_int 0)))
1607 (clobber (match_dup 3))])
1608 (set (pc)
1609 (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)])
1610 (match_dup 5) (match_dup 6)))]
1611 "
1612 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
1613 ")
1615 ;; Define the subtract-one-and-jump insns so loop.c
1616 ;; knows what to generate.
1617 (define_expand "doloop_end"
1618 [(use (match_operand 0 "" "")) ; loop pseudo
1619 (use (match_operand 1 "" ""))] ; label
1620 "TARGET_32BIT"
1621 "
1622 {
1623 /* Currently SMS relies on the do-loop pattern to recognize loops
1624 where (1) the control part consists of all insns defining and/or
1625 using a certain 'count' register and (2) the loop count can be
1626 adjusted by modifying this register prior to the loop.
1627 ??? The possible introduction of a new block to initialize the
1628 new IV can potentially affect branch optimizations. */
1629 if (optimize > 0 && flag_modulo_sched)
1630 {
1631 rtx s0;
1632 rtx bcomp;
1633 rtx loc_ref;
1634 rtx cc_reg;
1635 rtx insn;
1636 rtx cmp;
1638 if (GET_MODE (operands[0]) != SImode)
1639 FAIL;
1641 s0 = operands [0];
1642 if (TARGET_THUMB2)
1643 insn = emit_insn (gen_thumb2_addsi3_compare0 (s0, s0, GEN_INT (-1)));
1644 else
1645 insn = emit_insn (gen_addsi3_compare0 (s0, s0, GEN_INT (-1)));
1647 cmp = XVECEXP (PATTERN (insn), 0, 0);
1648 cc_reg = SET_DEST (cmp);
1649 bcomp = gen_rtx_NE (VOIDmode, cc_reg, const0_rtx);
1650 loc_ref = gen_rtx_LABEL_REF (VOIDmode, operands [1]);
1651 emit_jump_insn (gen_rtx_SET (pc_rtx,
1652 gen_rtx_IF_THEN_ELSE (VOIDmode, bcomp,
1653 loc_ref, pc_rtx)));
1654 DONE;
1655 }else
1656 FAIL;
1657 }")