1 ;; Predicate definitions for ARM and Thumb
2 ;; Copyright (C) 2004-2017 Free Software Foundation, Inc.
3 ;; Contributed by ARM Ltd.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 (define_predicate "s_register_operand"
22 (match_code "reg,subreg")
24 if (GET_CODE (op) == SUBREG)
26 /* We don't consider registers whose class is NO_REGS
27 to be a register operand. */
28 /* XXX might have to check for lo regs only for thumb ??? */
30 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
31 || REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
34 (define_predicate "imm_for_neon_inv_logic_operand"
35 (match_code "const_vector")
38 && neon_immediate_valid_for_logic (op, mode, 1, NULL, NULL));
41 (define_predicate "neon_inv_logic_op2"
42 (ior (match_operand 0 "imm_for_neon_inv_logic_operand")
43 (match_operand 0 "s_register_operand")))
45 (define_predicate "imm_for_neon_logic_operand"
46 (match_code "const_vector")
49 && neon_immediate_valid_for_logic (op, mode, 0, NULL, NULL));
52 (define_predicate "neon_logic_op2"
53 (ior (match_operand 0 "imm_for_neon_logic_operand")
54 (match_operand 0 "s_register_operand")))
56 ;; Any general register.
57 (define_predicate "arm_hard_general_register_operand"
60 return REGNO (op) <= LAST_ARM_REGNUM;
64 (define_predicate "low_register_operand"
65 (and (match_code "reg")
66 (match_test "REGNO (op) <= LAST_LO_REGNUM")))
68 ;; A low register or const_int.
69 (define_predicate "low_reg_or_int_operand"
70 (ior (match_code "const_int")
71 (match_operand 0 "low_register_operand")))
73 ;; Any core register, or any pseudo. */
74 (define_predicate "arm_general_register_operand"
75 (match_code "reg,subreg")
77 if (GET_CODE (op) == SUBREG)
81 && (REGNO (op) <= LAST_ARM_REGNUM
82 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
85 (define_predicate "vfp_register_operand"
86 (match_code "reg,subreg")
88 if (GET_CODE (op) == SUBREG)
91 /* We don't consider registers whose class is NO_REGS
92 to be a register operand. */
94 && (REGNO (op) >= FIRST_PSEUDO_REGISTER
95 || REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS
96 || REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS
98 && REGNO_REG_CLASS (REGNO (op)) == VFP_REGS)));
101 (define_predicate "vfp_hard_register_operand"
104 return (IS_VFP_REGNUM (REGNO (op)));
107 (define_predicate "zero_operand"
108 (and (match_code "const_int,const_double,const_vector")
109 (match_test "op == CONST0_RTX (mode)")))
111 ;; Match a register, or zero in the appropriate mode.
112 (define_predicate "reg_or_zero_operand"
113 (ior (match_operand 0 "s_register_operand")
114 (match_operand 0 "zero_operand")))
116 (define_special_predicate "subreg_lowpart_operator"
117 (and (match_code "subreg")
118 (match_test "subreg_lowpart_p (op)")))
120 ;; Reg, subreg(reg) or const_int.
121 (define_predicate "reg_or_int_operand"
122 (ior (match_code "const_int")
123 (match_operand 0 "s_register_operand")))
125 (define_predicate "arm_immediate_operand"
126 (and (match_code "const_int")
127 (match_test "const_ok_for_arm (INTVAL (op))")))
129 ;; A constant value which fits into two instructions, each taking
130 ;; an arithmetic constant operand for one of the words.
131 (define_predicate "arm_immediate_di_operand"
132 (and (match_code "const_int,const_double")
133 (match_test "arm_const_double_by_immediates (op)")))
135 (define_predicate "arm_neg_immediate_operand"
136 (and (match_code "const_int")
137 (match_test "const_ok_for_arm (-INTVAL (op))")))
139 (define_predicate "arm_not_immediate_operand"
140 (and (match_code "const_int")
141 (match_test "const_ok_for_arm (~INTVAL (op))")))
143 (define_predicate "const0_operand"
144 (match_test "op == CONST0_RTX (mode)"))
146 ;; Something valid on the RHS of an ARM data-processing instruction
147 (define_predicate "arm_rhs_operand"
148 (ior (match_operand 0 "s_register_operand")
149 (match_operand 0 "arm_immediate_operand")))
151 (define_predicate "arm_rhsm_operand"
152 (ior (match_operand 0 "arm_rhs_operand")
153 (match_operand 0 "memory_operand")))
155 (define_predicate "const_int_I_operand"
156 (and (match_operand 0 "const_int_operand")
157 (match_test "satisfies_constraint_I (op)")))
159 (define_predicate "const_int_M_operand"
160 (and (match_operand 0 "const_int_operand")
161 (match_test "satisfies_constraint_M (op)")))
163 ;; This doesn't have to do much because the constant is already checked
164 ;; in the shift_operator predicate.
165 (define_predicate "shift_amount_operand"
166 (ior (and (match_test "TARGET_ARM")
167 (match_operand 0 "s_register_operand"))
168 (match_operand 0 "const_int_operand")))
170 (define_predicate "const_neon_scalar_shift_amount_operand"
171 (and (match_code "const_int")
172 (match_test "IN_RANGE (UINTVAL (op), 1, GET_MODE_BITSIZE (mode))")))
174 (define_predicate "ldrd_strd_offset_operand"
175 (and (match_operand 0 "const_int_operand")
176 (match_test "TARGET_LDRD && offset_ok_for_ldrd_strd (INTVAL (op))")))
178 (define_predicate "arm_add_operand"
179 (ior (match_operand 0 "arm_rhs_operand")
180 (match_operand 0 "arm_neg_immediate_operand")))
182 (define_predicate "arm_anddi_operand_neon"
183 (ior (match_operand 0 "s_register_operand")
184 (and (match_code "const_int")
185 (match_test "const_ok_for_dimode_op (INTVAL (op), AND)"))
186 (match_operand 0 "neon_inv_logic_op2")))
188 (define_predicate "arm_iordi_operand_neon"
189 (ior (match_operand 0 "s_register_operand")
190 (and (match_code "const_int")
191 (match_test "const_ok_for_dimode_op (INTVAL (op), IOR)"))
192 (match_operand 0 "neon_logic_op2")))
194 (define_predicate "arm_xordi_operand"
195 (ior (match_operand 0 "s_register_operand")
196 (and (match_code "const_int")
197 (match_test "const_ok_for_dimode_op (INTVAL (op), XOR)"))))
199 (define_predicate "arm_adddi_operand"
200 (ior (match_operand 0 "s_register_operand")
201 (and (match_code "const_int")
202 (match_test "const_ok_for_dimode_op (INTVAL (op), PLUS)"))))
204 (define_predicate "arm_addimm_operand"
205 (ior (match_operand 0 "arm_immediate_operand")
206 (match_operand 0 "arm_neg_immediate_operand")))
208 (define_predicate "arm_not_operand"
209 (ior (match_operand 0 "arm_rhs_operand")
210 (match_operand 0 "arm_not_immediate_operand")))
212 (define_predicate "arm_di_operand"
213 (ior (match_operand 0 "s_register_operand")
214 (match_operand 0 "arm_immediate_di_operand")))
216 ;; True if the operand is a memory reference which contains an
217 ;; offsettable address.
218 (define_predicate "offsettable_memory_operand"
219 (and (match_code "mem")
221 "offsettable_address_p (reload_completed | reload_in_progress,
222 mode, XEXP (op, 0))")))
224 ;; True if the operand is a memory operand that does not have an
225 ;; automodified base register (and thus will not generate output reloads).
226 (define_predicate "call_memory_operand"
227 (and (match_code "mem")
228 (and (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0)))
230 (match_operand 0 "memory_operand"))))
232 (define_predicate "arm_reload_memory_operand"
233 (and (match_code "mem,reg,subreg")
234 (match_test "(!CONSTANT_P (op)
235 && (true_regnum(op) == -1
237 && REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
239 (define_predicate "vfp_compare_operand"
240 (ior (match_operand 0 "s_register_operand")
241 (and (match_code "const_double")
242 (match_test "arm_const_double_rtx (op)"))))
244 ;; True for valid index operands.
245 (define_predicate "index_operand"
246 (ior (match_operand 0 "s_register_operand")
247 (and (match_operand 0 "immediate_operand")
248 (match_test "(!CONST_INT_P (op)
249 || (INTVAL (op) < 4096 && INTVAL (op) > -4096))"))))
251 ;; True for operators that can be combined with a shift in ARM state.
252 (define_special_predicate "shiftable_operator"
253 (and (match_code "plus,minus,ior,xor,and")
254 (match_test "mode == GET_MODE (op)")))
256 (define_special_predicate "shiftable_operator_strict_it"
257 (and (match_code "plus,and")
258 (match_test "mode == GET_MODE (op)")))
260 ;; True for logical binary operators.
261 (define_special_predicate "logical_binary_operator"
262 (and (match_code "ior,xor,and")
263 (match_test "mode == GET_MODE (op)")))
265 ;; True for commutative operators
266 (define_special_predicate "commutative_binary_operator"
267 (and (match_code "ior,xor,and,plus")
268 (match_test "mode == GET_MODE (op)")))
270 ;; True for shift operators.
272 ;; * mult is only permitted with a constant shift amount
273 ;; * patterns that permit register shift amounts only in ARM mode use
274 ;; shift_amount_operand, patterns that always allow registers do not,
275 ;; so we don't have to worry about that sort of thing here.
276 (define_special_predicate "shift_operator"
277 (and (ior (ior (and (match_code "mult")
278 (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
279 (and (match_code "rotate")
280 (match_test "CONST_INT_P (XEXP (op, 1))
281 && (UINTVAL (XEXP (op, 1))) < 32")))
282 (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
283 (match_test "!CONST_INT_P (XEXP (op, 1))
284 || (UINTVAL (XEXP (op, 1))) < 32")))
285 (match_test "mode == GET_MODE (op)")))
287 (define_special_predicate "shift_nomul_operator"
288 (and (ior (and (match_code "rotate")
289 (match_test "CONST_INT_P (XEXP (op, 1))
290 && (UINTVAL (XEXP (op, 1))) < 32"))
291 (and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
292 (match_test "!CONST_INT_P (XEXP (op, 1))
293 || (UINTVAL (XEXP (op, 1))) < 32")))
294 (match_test "mode == GET_MODE (op)")))
296 ;; True for shift operators which can be used with saturation instructions.
297 (define_special_predicate "sat_shift_operator"
298 (and (ior (and (match_code "mult")
299 (match_test "power_of_two_operand (XEXP (op, 1), mode)"))
300 (and (match_code "ashift,ashiftrt")
301 (match_test "CONST_INT_P (XEXP (op, 1))
302 && (UINTVAL (XEXP (op, 1)) < 32)")))
303 (match_test "mode == GET_MODE (op)")))
305 ;; True for MULT, to identify which variant of shift_operator is in use.
306 (define_special_predicate "mult_operator"
309 ;; True for operators that have 16-bit thumb variants. */
310 (define_special_predicate "thumb_16bit_operator"
311 (match_code "plus,minus,and,ior,xor"))
314 (define_special_predicate "equality_operator"
315 (match_code "eq,ne"))
317 ;; True for integer comparisons and, if FP is active, for comparisons
318 ;; other than LTGT or UNEQ.
319 (define_special_predicate "expandable_comparison_operator"
320 (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
321 unordered,ordered,unlt,unle,unge,ungt"))
323 ;; Likewise, but only accept comparisons that are directly supported
324 ;; by ARM condition codes.
325 (define_special_predicate "arm_comparison_operator"
326 (and (match_operand 0 "expandable_comparison_operator")
327 (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
329 ;; Likewise, but don't ignore the mode.
330 ;; RTL SET operations require their operands source and destination have
331 ;; the same modes, so we can't ignore the modes there. See PR target/69161.
332 (define_predicate "arm_comparison_operator_mode"
333 (and (match_operand 0 "expandable_comparison_operator")
334 (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
336 (define_special_predicate "lt_ge_comparison_operator"
337 (match_code "lt,ge"))
339 ;; The vsel instruction only accepts the ARM condition codes listed below.
340 (define_special_predicate "arm_vsel_comparison_operator"
341 (and (match_operand 0 "expandable_comparison_operator")
342 (match_test "maybe_get_arm_condition_code (op) == ARM_GE
343 || maybe_get_arm_condition_code (op) == ARM_GT
344 || maybe_get_arm_condition_code (op) == ARM_EQ
345 || maybe_get_arm_condition_code (op) == ARM_VS
346 || maybe_get_arm_condition_code (op) == ARM_LT
347 || maybe_get_arm_condition_code (op) == ARM_LE
348 || maybe_get_arm_condition_code (op) == ARM_NE
349 || maybe_get_arm_condition_code (op) == ARM_VC")))
351 (define_special_predicate "arm_cond_move_operator"
352 (if_then_else (match_test "arm_restrict_it")
353 (and (match_test "TARGET_FPU_ARMV8")
354 (match_operand 0 "arm_vsel_comparison_operator"))
355 (match_operand 0 "expandable_comparison_operator")))
357 (define_special_predicate "noov_comparison_operator"
358 (match_code "lt,ge,eq,ne"))
360 (define_special_predicate "minmax_operator"
361 (and (match_code "smin,smax,umin,umax")
362 (match_test "mode == GET_MODE (op)")))
364 (define_special_predicate "cc_register"
365 (and (match_code "reg")
366 (and (match_test "REGNO (op) == CC_REGNUM")
367 (ior (match_test "mode == GET_MODE (op)")
368 (match_test "mode == VOIDmode && GET_MODE_CLASS (GET_MODE (op)) == MODE_CC")))))
370 (define_special_predicate "dominant_cc_register"
373 if (mode == VOIDmode)
375 mode = GET_MODE (op);
377 if (GET_MODE_CLASS (mode) != MODE_CC)
381 return (cc_register (op, mode)
382 && (mode == CC_DNEmode
383 || mode == CC_DEQmode
384 || mode == CC_DLEmode
385 || mode == CC_DLTmode
386 || mode == CC_DGEmode
387 || mode == CC_DGTmode
388 || mode == CC_DLEUmode
389 || mode == CC_DLTUmode
390 || mode == CC_DGEUmode
391 || mode == CC_DGTUmode));
394 ;; Any register, including CC
395 (define_predicate "cc_register_operand"
396 (and (match_code "reg")
397 (ior (match_operand 0 "s_register_operand")
398 (match_operand 0 "cc_register"))))
400 (define_special_predicate "arm_extendqisi_mem_op"
401 (and (match_operand 0 "memory_operand")
402 (match_test "TARGET_ARM ? arm_legitimate_address_outer_p (mode,
406 : memory_address_p (QImode, XEXP (op, 0))")))
408 (define_special_predicate "arm_reg_or_extendqisi_mem_op"
409 (ior (match_operand 0 "arm_extendqisi_mem_op")
410 (match_operand 0 "s_register_operand")))
412 (define_predicate "power_of_two_operand"
413 (match_code "const_int")
415 unsigned HOST_WIDE_INT value = INTVAL (op) & 0xffffffff;
417 return value != 0 && (value & (value - 1)) == 0;
420 (define_predicate "nonimmediate_di_operand"
421 (match_code "reg,subreg,mem")
423 if (s_register_operand (op, mode))
426 if (GET_CODE (op) == SUBREG)
427 op = SUBREG_REG (op);
429 return MEM_P (op) && memory_address_p (DImode, XEXP (op, 0));
432 (define_predicate "di_operand"
433 (ior (match_code "const_int,const_double")
434 (and (match_code "reg,subreg,mem")
435 (match_operand 0 "nonimmediate_di_operand"))))
437 (define_predicate "nonimmediate_soft_df_operand"
438 (match_code "reg,subreg,mem")
440 if (s_register_operand (op, mode))
443 if (GET_CODE (op) == SUBREG)
444 op = SUBREG_REG (op);
446 return MEM_P (op) && memory_address_p (DFmode, XEXP (op, 0));
449 (define_predicate "soft_df_operand"
450 (ior (match_code "const_double")
451 (and (match_code "reg,subreg,mem")
452 (match_operand 0 "nonimmediate_soft_df_operand"))))
454 (define_special_predicate "load_multiple_operation"
455 (match_code "parallel")
457 return ldm_stm_operation_p (op, /*load=*/true, SImode,
458 /*consecutive=*/false,
459 /*return_pc=*/false);
462 (define_special_predicate "store_multiple_operation"
463 (match_code "parallel")
465 return ldm_stm_operation_p (op, /*load=*/false, SImode,
466 /*consecutive=*/false,
467 /*return_pc=*/false);
470 (define_special_predicate "pop_multiple_return"
471 (match_code "parallel")
473 return ldm_stm_operation_p (op, /*load=*/true, SImode,
474 /*consecutive=*/false,
478 (define_special_predicate "pop_multiple_fp"
479 (match_code "parallel")
481 return ldm_stm_operation_p (op, /*load=*/true, DFmode,
482 /*consecutive=*/true,
483 /*return_pc=*/false);
486 (define_special_predicate "multi_register_push"
487 (match_code "parallel")
489 if ((GET_CODE (XVECEXP (op, 0, 0)) != SET)
490 || (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC)
491 || (XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPEC_PUSH_MULT))
497 (define_predicate "push_mult_memory_operand"
500 /* ??? Given how PUSH_MULT is generated in the prologues, is there
501 any point in testing for thumb1 specially? All of the variants
502 use the same form. */
505 /* ??? No attempt is made to represent STMIA, or validate that
506 the stack adjustment matches the register count. This is
507 true of the ARM/Thumb2 path as well. */
508 rtx x = XEXP (op, 0);
509 if (GET_CODE (x) != PRE_MODIFY)
511 if (XEXP (x, 0) != stack_pointer_rtx)
514 if (GET_CODE (x) != PLUS)
516 if (XEXP (x, 0) != stack_pointer_rtx)
518 return CONST_INT_P (XEXP (x, 1));
521 /* ARM and Thumb2 handle pre-modify in their legitimate_address. */
522 return memory_operand (op, mode);
525 ;;-------------------------------------------------------------------------
530 (define_predicate "thumb1_cmp_operand"
531 (ior (and (match_code "reg,subreg")
532 (match_operand 0 "s_register_operand"))
533 (and (match_code "const_int")
534 (match_test "(UINTVAL (op)) < 256"))))
536 (define_predicate "thumb1_cmpneg_operand"
537 (and (match_code "const_int")
538 (match_test "INTVAL (op) < 0 && INTVAL (op) > -256")))
540 ;; Return TRUE if a result can be stored in OP without clobbering the
541 ;; condition code register. Prior to reload we only accept a
542 ;; register. After reload we have to be able to handle memory as
543 ;; well, since a pseudo may not get a hard reg and reload cannot
544 ;; handle output-reloads on jump insns.
546 ;; We could possibly handle mem before reload as well, but that might
547 ;; complicate things with the need to handle increment
549 (define_predicate "thumb_cbrch_target_operand"
550 (and (match_code "reg,subreg,mem")
551 (ior (match_operand 0 "s_register_operand")
552 (and (match_test "reload_in_progress || reload_completed")
553 (match_operand 0 "memory_operand")))))
555 ;;-------------------------------------------------------------------------
560 (define_predicate "imm_or_reg_operand"
561 (ior (match_operand 0 "immediate_operand")
562 (match_operand 0 "register_operand")))
566 (define_predicate "const_multiple_of_8_operand"
567 (match_code "const_int")
569 unsigned HOST_WIDE_INT val = INTVAL (op);
570 return (val & 7) == 0;
573 (define_predicate "imm_for_neon_mov_operand"
574 (match_code "const_vector,const_int")
576 return neon_immediate_valid_for_move (op, mode, NULL, NULL);
579 (define_predicate "imm_for_neon_lshift_operand"
580 (match_code "const_vector")
582 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, true);
585 (define_predicate "imm_for_neon_rshift_operand"
586 (match_code "const_vector")
588 return neon_immediate_valid_for_shift (op, mode, NULL, NULL, false);
591 (define_predicate "imm_lshift_or_reg_neon"
592 (ior (match_operand 0 "s_register_operand")
593 (match_operand 0 "imm_for_neon_lshift_operand")))
595 (define_predicate "imm_rshift_or_reg_neon"
596 (ior (match_operand 0 "s_register_operand")
597 (match_operand 0 "imm_for_neon_rshift_operand")))
599 ;; Predicates for named expanders that overlap multiple ISAs.
601 (define_predicate "cmpdi_operand"
602 (and (match_test "TARGET_32BIT")
603 (match_operand 0 "arm_di_operand")))
605 ;; True if the operand is memory reference suitable for a ldrex/strex.
606 (define_predicate "arm_sync_memory_operand"
607 (and (match_operand 0 "memory_operand")
608 (match_code "reg" "0")))
610 ;; Predicates for parallel expanders based on mode.
611 (define_special_predicate "vect_par_constant_high"
612 (match_code "parallel")
614 return arm_simd_check_vect_par_cnst_half_p (op, mode, true);
617 (define_special_predicate "vect_par_constant_low"
618 (match_code "parallel")
620 return arm_simd_check_vect_par_cnst_half_p (op, mode, false);
623 (define_predicate "const_double_vcvt_power_of_two_reciprocal"
624 (and (match_code "const_double")
625 (match_test "TARGET_32BIT
626 && vfp3_const_double_for_fract_bits (op)")))
628 (define_predicate "const_double_vcvt_power_of_two"
629 (and (match_code "const_double")
630 (match_test "TARGET_32BIT
631 && vfp3_const_double_for_bits (op) > 0")))
633 (define_predicate "neon_struct_operand"
634 (and (match_code "mem")
635 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, true)")))
637 (define_predicate "neon_permissive_struct_operand"
638 (and (match_code "mem")
639 (match_test "TARGET_32BIT && neon_vector_mem_operand (op, 2, false)")))
641 (define_predicate "neon_perm_struct_or_reg_operand"
642 (ior (match_operand 0 "neon_permissive_struct_operand")
643 (match_operand 0 "s_register_operand")))
645 (define_special_predicate "add_operator"
648 (define_predicate "mem_noofs_operand"
649 (and (match_code "mem")
650 (match_code "reg" "0")))
652 (define_predicate "call_insn_operand"
653 (ior (and (match_code "symbol_ref")
654 (match_test "!arm_is_long_call_p (SYMBOL_REF_DECL (op))"))
655 (match_operand 0 "s_register_operand")))