gcc/config/arm/arm-isa.h

   1 /* ISA feature bits for ARM.
   2    Copyright (C) 2016-2017 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    Under Section 7 of GPL version 3, you are granted additional
  18    permissions described in the GCC Runtime Library Exception, version
  19    3.1, as published by the Free Software Foundation.
  20
  21    You should have received a copy of the GNU General Public License and
  22    a copy of the GCC Runtime Library Exception along with this program;
  23    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  24    <http://www.gnu.org/licenses/>.  */
  25
  26 #ifndef ARM_ISA_FEATURE_H
  27 #define ARM_ISA_FEATURE_H
  28
  29 enum isa_feature
  30   {
  31     isa_nobit,          /* Must be first.  */
  32     isa_bit_ARMv3m,     /* Extended multiply.  */
  33     isa_bit_mode26,     /* 26-bit mode support.  */
  34     isa_bit_mode32,     /* 32-bit mode support.  */
  35     isa_bit_ARMv4,      /* Architecture rel 4.  */
  36     isa_bit_ARMv5,      /* Architecture rel 5.  */
  37     isa_bit_thumb,      /* Thumb aware.  */
  38     isa_bit_ARMv5e,     /* Architecture rel 5e.  */
  39     isa_bit_xscale,     /* XScale.  */
  40     isa_bit_ARMv6,      /* Architecture rel 6.  */
  41     isa_bit_ARMv6k,     /* Architecture rel 6k.  */
  42     isa_bit_thumb2,     /* Thumb-2.  */
  43     isa_bit_notm,       /* Instructions not present in 'M' profile.  */
  44     isa_bit_be8,        /* Architecture uses be8 mode in big-endian.  */
  45     isa_bit_tdiv,       /* Thumb division instructions.  */
  46     isa_bit_ARMv7em,    /* Architecture rel 7e-m.  */
  47     isa_bit_ARMv7,      /* Architecture rel 7.  */
  48     isa_bit_adiv,       /* ARM division instructions.  */
  49     isa_bit_ARMv8,      /* Architecture rel 8.  */
  50     isa_bit_crc32,      /* ARMv8 CRC32 instructions.  */
  51     isa_bit_iwmmxt,     /* XScale v2 (Wireless MMX).  */
  52     isa_bit_iwmmxt2,    /* XScale Wireless MMX2.  */
  53     isa_bit_ARMv8_1,    /* Architecture rel 8.1.  */
  54     isa_bit_ARMv8_2,    /* Architecutre rel 8.2.  */
  55     isa_bit_cmse,       /* M-Profile security extensions.  */
  56     /* Floating point and Neon extensions.  */
  57     /* VFPv1 is not supported in GCC.  */
  58     isa_bit_VFPv2,      /* Vector floating point v2.  */
  59     isa_bit_VFPv3,      /* Vector floating point v3.  */
  60     isa_bit_VFPv4,      /* Vector floating point v4.  */
  61     isa_bit_FPv5,       /* Floating point v5.  */
  62     isa_bit_lpae,       /* ARMv7-A LPAE.  */
  63     isa_bit_FP_ARMv8,   /* ARMv8 floating-point extension.  */
  64     isa_bit_neon,       /* Advanced SIMD instructions.  */
  65     isa_bit_fp16conv,   /* Conversions to/from fp16 (VFPv3 extension).  */
  66     isa_bit_fp_dbl,     /* Double precision operations supported.  */
  67     isa_bit_fp_d32,     /* 32 Double precision registers.  */
  68     isa_bit_crypto,     /* Crypto extension to ARMv8.  */
  69     isa_bit_fp16,       /* FP16 data processing (half-precision float).  */
  70
  71     /* ISA Quirks (errata?).  Don't forget to add this to the list of
  72        all quirks below.  */
  73     isa_quirk_no_volatile_ce,   /* No volatile memory in IT blocks.  */
  74     isa_quirk_ARMv6kz,          /* Previously mis-identified by GCC.  */
  75     isa_quirk_cm3_ldrd,         /* Cortex-M3 LDRD quirk.  */
  76
  77     /* Aren't currently, but probably should be tuning bits.  */
  78     isa_bit_smallmul,   /* Slow multiply operations.  */
  79
  80     /* Tuning bits.  Should be elsewhere.  */
  81     isa_tune_co_proc,   /* Has co-processor bus.  */
  82     isa_tune_ldsched,   /* Load scheduling necessary.  */
  83     isa_tune_strong,    /* StrongARM.  */
  84     isa_tune_wbuf,      /* Schedule for write buffer ops (ARM6 & 7 only).  */
  85
  86     /* Must be last, used to dimension arrays.  */
  87     isa_num_bits
  88   };
  89
  90 /* Helper macros for use when defining CPUs and architectures.
  91
  92    There must be no parenthesees in these lists, since they are used
  93    to initialize arrays.  */
  94
  95 #define ISA_ARMv2       isa_bit_notm
  96 #define ISA_ARMv3       ISA_ARMv2, isa_bit_mode32
  97 #define ISA_ARMv3m      ISA_ARMv3, isa_bit_ARMv3m
  98 #define ISA_ARMv4       ISA_ARMv3m, isa_bit_ARMv4
  99 #define ISA_ARMv4t      ISA_ARMv4, isa_bit_thumb
 100 #define ISA_ARMv5       ISA_ARMv4, isa_bit_ARMv5
 101 #define ISA_ARMv5t      ISA_ARMv5, isa_bit_thumb
 102 #define ISA_ARMv5e      ISA_ARMv5, isa_bit_ARMv5e
 103 #define ISA_ARMv5te     ISA_ARMv5e, isa_bit_thumb
 104 #define ISA_ARMv5tej    ISA_ARMv5te
 105 #define ISA_ARMv6       ISA_ARMv5te, isa_bit_ARMv6, isa_bit_be8
 106 #define ISA_ARMv6j      ISA_ARMv6
 107 #define ISA_ARMv6k      ISA_ARMv6, isa_bit_ARMv6k
 108 #define ISA_ARMv6z      ISA_ARMv6
 109 #define ISA_ARMv6kz     ISA_ARMv6k, isa_quirk_ARMv6kz
 110 #define ISA_ARMv6zk     ISA_ARMv6k
 111 #define ISA_ARMv6t2     ISA_ARMv6, isa_bit_thumb2
 112
 113 /* This is suspect.  ARMv6-m doesn't really pull in any useful features
 114    from ARMv5* or ARMv6.  */
 115 #define ISA_ARMv6m      isa_bit_mode32, isa_bit_ARMv3m, isa_bit_ARMv4, \
 116     isa_bit_thumb, isa_bit_ARMv5, isa_bit_ARMv5e, isa_bit_ARMv6
 117 /* This is suspect, the 'common' ARMv7 subset excludes the thumb2 'DSP' and
 118    integer SIMD instructions that are in ARMv6T2.  */
 119 #define ISA_ARMv7       ISA_ARMv6m, isa_bit_thumb2, isa_bit_ARMv7
 120 #define ISA_ARMv7a      ISA_ARMv7, isa_bit_notm, isa_bit_ARMv6k
 121 #define ISA_ARMv7ve     ISA_ARMv7a, isa_bit_adiv, isa_bit_tdiv, isa_bit_lpae
 122 #define ISA_ARMv7r      ISA_ARMv7a, isa_bit_tdiv
 123 #define ISA_ARMv7m      ISA_ARMv7, isa_bit_tdiv
 124 #define ISA_ARMv7em     ISA_ARMv7m, isa_bit_ARMv7em
 125 #define ISA_ARMv8a      ISA_ARMv7ve, isa_bit_ARMv8
 126 #define ISA_ARMv8_1a    ISA_ARMv8a, isa_bit_crc32, isa_bit_ARMv8_1
 127 #define ISA_ARMv8_2a    ISA_ARMv8_1a, isa_bit_ARMv8_2
 128 #define ISA_ARMv8m_base ISA_ARMv6m, isa_bit_ARMv8, isa_bit_cmse, isa_bit_tdiv
 129 #define ISA_ARMv8m_main ISA_ARMv7m, isa_bit_ARMv8, isa_bit_cmse
 130 #define ISA_ARMv8r      ISA_ARMv8a
 131
 132 /* List of all cryptographic extensions to stripout if crypto is
 133    disabled.  Currently, that's trivial, but we define it anyway for
 134    consistency with the SIMD and FP disable lists.  */
 135 #define ISA_ALL_CRYPTO  isa_bit_crypto
 136
 137 /* List of all SIMD bits to strip out if SIMD is disabled.  This does
 138    strip off 32 D-registers, but does not remove support for
 139    double-precision FP.  */
 140 #define ISA_ALL_SIMD    isa_bit_fp_d32, isa_bit_neon, ISA_ALL_CRYPTO
 141
 142 /* List of all FPU bits to strip out if -mfpu is used to override the
 143    default.  isa_bit_fp16 is deliberately missing from this list.  */
 144 #define ISA_ALL_FPU_INTERNAL                                            \
 145   isa_bit_VFPv2, isa_bit_VFPv3, isa_bit_VFPv4, isa_bit_FPv5,            \
 146   isa_bit_FP_ARMv8, isa_bit_fp16conv, isa_bit_fp_dbl, ISA_ALL_SIMD
 147
 148 /* Similarly, but including fp16 and other extensions that aren't part of
 149    -mfpu support.  */
 150 #define ISA_ALL_FP      isa_bit_fp16, ISA_ALL_FPU_INTERNAL
 151
 152 /* Useful combinations.  */
 153 #define ISA_VFPv2       isa_bit_VFPv2
 154 #define ISA_VFPv3       ISA_VFPv2, isa_bit_VFPv3
 155 #define ISA_VFPv4       ISA_VFPv3, isa_bit_VFPv4, isa_bit_fp16conv
 156 #define ISA_FPv5        ISA_VFPv4, isa_bit_FPv5
 157 #define ISA_FP_ARMv8    ISA_FPv5, isa_bit_FP_ARMv8
 158
 159 #define ISA_FP_DBL      isa_bit_fp_dbl
 160 #define ISA_FP_D32      ISA_FP_DBL, isa_bit_fp_d32
 161 #define ISA_NEON        ISA_FP_D32, isa_bit_neon
 162 #define ISA_CRYPTO      ISA_NEON, isa_bit_crypto
 163
 164 /* List of all quirk bits to strip out when comparing CPU features with
 165    architectures.  */
 166 #define ISA_ALL_QUIRKS  isa_quirk_no_volatile_ce, isa_quirk_ARMv6kz,    \
 167     isa_quirk_cm3_ldrd
 168
 169 /* Helper macro so that we can concatenate multiple features together
 170    with arm-*.def files, since macro substitution can't have commas within an
 171    argument that lacks parenthesis.  */
 172 #define ISA_FEAT(X)     X,
 173 #endif