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* common.opt (-Wattributes): New. Default true.
[official-gcc.git] / gcc / config / m32r / m32r.c
blobc27b2441127b22bd29e54489ddc2fbd9b9424de9
1 /* Subroutines used for code generation on the Renesas M32R cpu.
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3 2005 Free Software Foundation, Inc.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 2, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
21
22 #include "config.h"
23 #include "system.h"
24 #include "coretypes.h"
25 #include "tm.h"
26 #include "tree.h"
27 #include "rtl.h"
28 #include "regs.h"
29 #include "hard-reg-set.h"
30 #include "real.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "output.h"
34 #include "insn-attr.h"
35 #include "flags.h"
36 #include "expr.h"
37 #include "function.h"
38 #include "recog.h"
39 #include "toplev.h"
40 #include "ggc.h"
41 #include "integrate.h"
42 #include "tm_p.h"
43 #include "target.h"
44 #include "target-def.h"
45
46 /* Save the operands last given to a compare for use when we
47 generate a scc or bcc insn. */
48 rtx m32r_compare_op0, m32r_compare_op1;
49
50 /* Array of valid operand punctuation characters. */
51 char m32r_punct_chars[256];
52
53 /* Selected code model. */
54 enum m32r_model m32r_model = M32R_MODEL_DEFAULT;
55
56 /* Selected SDA support. */
57 enum m32r_sdata m32r_sdata = M32R_SDATA_DEFAULT;
58
59 /* Machine-specific symbol_ref flags. */
60 #define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
61 #define SYMBOL_REF_MODEL(X) \
62 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3))
63
64 /* For string literals, etc. */
65 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.')
66
67 /* Cache-flush support. Cache-flush is used at trampoline.
68 Default cache-flush is "trap 12".
69 default cache-flush function is "_flush_cache" (CACHE_FLUSH_FUNC)
70 default cache-flush trap-interrupt number is 12 (CACHE_FLUSH_TRAP)
71 You can change how to generate code of cache-flush with following options.
72 -mflush-func=FLUSH-FUNC-NAME
73 -mno-flush-func (sets m32r_cache_flush_func to NULL)
74 -mfluch-trap=TRAP-NUMBER
75 -mno-flush-trap. (sets m32r_cache_flush_trap to -1). */
76 const char *m32r_cache_flush_func = CACHE_FLUSH_FUNC;
77 int m32r_cache_flush_trap = CACHE_FLUSH_TRAP;
78
79 /* Forward declaration. */
80 static bool m32r_handle_option (size_t, const char *, int);
81 static void init_reg_tables (void);
82 static void block_move_call (rtx, rtx, rtx);
83 static int m32r_is_insn (rtx);
84 const struct attribute_spec m32r_attribute_table[];
85 static tree m32r_handle_model_attribute (tree *, tree, tree, int, bool *);
86 static void m32r_output_function_prologue (FILE *, HOST_WIDE_INT);
87 static void m32r_output_function_epilogue (FILE *, HOST_WIDE_INT);
88
89 static void m32r_file_start (void);
90
91 static int m32r_adjust_priority (rtx, int);
92 static int m32r_issue_rate (void);
93
94 static void m32r_encode_section_info (tree, rtx, int);
95 static bool m32r_in_small_data_p (tree);
96 static bool m32r_return_in_memory (tree, tree);
97 static void m32r_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
98 tree, int *, int);
99 static void init_idents (void);
100 static bool m32r_rtx_costs (rtx, int, int, int *);
101 static bool m32r_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
102 tree, bool);
103 static int m32r_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
104 tree, bool);
105 \f
106 /* Initialize the GCC target structure. */
107 #undef TARGET_ATTRIBUTE_TABLE
108 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table
109
110 #undef TARGET_ASM_ALIGNED_HI_OP
111 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
112 #undef TARGET_ASM_ALIGNED_SI_OP
113 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
114
115 #undef TARGET_ASM_FUNCTION_PROLOGUE
116 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue
117 #undef TARGET_ASM_FUNCTION_EPILOGUE
118 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue
119
120 #undef TARGET_ASM_FILE_START
121 #define TARGET_ASM_FILE_START m32r_file_start
122
123 #undef TARGET_SCHED_ADJUST_PRIORITY
124 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority
125 #undef TARGET_SCHED_ISSUE_RATE
126 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate
127
128 #undef TARGET_DEFAULT_TARGET_FLAGS
129 #define TARGET_DEFAULT_TARGET_FLAGS TARGET_CPU_DEFAULT
130 #undef TARGET_HANDLE_OPTION
131 #define TARGET_HANDLE_OPTION m32r_handle_option
132
133 #undef TARGET_ENCODE_SECTION_INFO
134 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info
135 #undef TARGET_IN_SMALL_DATA_P
136 #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p
137
138 #undef TARGET_RTX_COSTS
139 #define TARGET_RTX_COSTS m32r_rtx_costs
140 #undef TARGET_ADDRESS_COST
141 #define TARGET_ADDRESS_COST hook_int_rtx_0
142
143 #undef TARGET_PROMOTE_PROTOTYPES
144 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
145 #undef TARGET_RETURN_IN_MEMORY
146 #define TARGET_RETURN_IN_MEMORY m32r_return_in_memory
147 #undef TARGET_SETUP_INCOMING_VARARGS
148 #define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs
149 #undef TARGET_MUST_PASS_IN_STACK
150 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
151 #undef TARGET_PASS_BY_REFERENCE
152 #define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference
153 #undef TARGET_ARG_PARTIAL_BYTES
154 #define TARGET_ARG_PARTIAL_BYTES m32r_arg_partial_bytes
155
156 struct gcc_target targetm = TARGET_INITIALIZER;
157 \f
158 /* Implement TARGET_HANDLE_OPTION. */
159
160 static bool
161 m32r_handle_option (size_t code, const char *arg, int value)
162 {
163 switch (code)
164 {
165 case OPT_m32r:
166 target_flags &= ~(MASK_M32R2 | MASK_M32RX);
167 return true;
168
169 case OPT_mmodel_:
170 if (strcmp (arg, "small") == 0)
171 m32r_model = M32R_MODEL_SMALL;
172 else if (strcmp (arg, "medium") == 0)
173 m32r_model = M32R_MODEL_MEDIUM;
174 else if (strcmp (arg, "large") == 0)
175 m32r_model = M32R_MODEL_LARGE;
176 else
177 return false;
178 return true;
179
180 case OPT_msdata_:
181 if (strcmp (arg, "none") == 0)
182 m32r_sdata = M32R_SDATA_NONE;
183 else if (strcmp (arg, "sdata") == 0)
184 m32r_sdata = M32R_SDATA_SDATA;
185 else if (strcmp (arg, "use") == 0)
186 m32r_sdata = M32R_SDATA_USE;
187 else
188 return false;
189 return true;
190
191 case OPT_mflush_func_:
192 m32r_cache_flush_func = arg;
193 return true;
194
195 case OPT_mno_flush_func:
196 m32r_cache_flush_func = NULL;
197 return true;
198
199 case OPT_mflush_trap_:
200 m32r_cache_flush_trap = value;
201 return m32r_cache_flush_trap <= 15;
202
203 case OPT_mno_flush_trap:
204 m32r_cache_flush_trap = -1;
205 return true;
206
207 default:
208 return true;
209 }
210 }
211
212 /* Called by OVERRIDE_OPTIONS to initialize various things. */
213
214 void
215 m32r_init (void)
216 {
217 init_reg_tables ();
218
219 /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P. */
220 memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
221 m32r_punct_chars['#'] = 1;
222 m32r_punct_chars['@'] = 1; /* ??? no longer used */
223
224 /* Provide default value if not specified. */
225 if (!g_switch_set)
226 g_switch_value = SDATA_DEFAULT_SIZE;
227 }
228
229 /* Vectors to keep interesting information about registers where it can easily
230 be got. We use to use the actual mode value as the bit number, but there
231 is (or may be) more than 32 modes now. Instead we use two tables: one
232 indexed by hard register number, and one indexed by mode. */
233
234 /* The purpose of m32r_mode_class is to shrink the range of modes so that
235 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
236 mapped into one m32r_mode_class mode. */
237
238 enum m32r_mode_class
239 {
240 C_MODE,
241 S_MODE, D_MODE, T_MODE, O_MODE,
242 SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
243 };
244
245 /* Modes for condition codes. */
246 #define C_MODES (1 << (int) C_MODE)
247
248 /* Modes for single-word and smaller quantities. */
249 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
250
251 /* Modes for double-word and smaller quantities. */
252 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
253
254 /* Modes for quad-word and smaller quantities. */
255 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
256
257 /* Modes for accumulators. */
258 #define A_MODES (1 << (int) A_MODE)
259
260 /* Value is 1 if register/mode pair is acceptable on arc. */
261
262 const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
263 {
264 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
265 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
266 S_MODES, C_MODES, A_MODES, A_MODES
267 };
268
269 unsigned int m32r_mode_class [NUM_MACHINE_MODES];
270
271 enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
272
273 static void
274 init_reg_tables (void)
275 {
276 int i;
277
278 for (i = 0; i < NUM_MACHINE_MODES; i++)
279 {
280 switch (GET_MODE_CLASS (i))
281 {
282 case MODE_INT:
283 case MODE_PARTIAL_INT:
284 case MODE_COMPLEX_INT:
285 if (GET_MODE_SIZE (i) <= 4)
286 m32r_mode_class[i] = 1 << (int) S_MODE;
287 else if (GET_MODE_SIZE (i) == 8)
288 m32r_mode_class[i] = 1 << (int) D_MODE;
289 else if (GET_MODE_SIZE (i) == 16)
290 m32r_mode_class[i] = 1 << (int) T_MODE;
291 else if (GET_MODE_SIZE (i) == 32)
292 m32r_mode_class[i] = 1 << (int) O_MODE;
293 else
294 m32r_mode_class[i] = 0;
295 break;
296 case MODE_FLOAT:
297 case MODE_COMPLEX_FLOAT:
298 if (GET_MODE_SIZE (i) <= 4)
299 m32r_mode_class[i] = 1 << (int) SF_MODE;
300 else if (GET_MODE_SIZE (i) == 8)
301 m32r_mode_class[i] = 1 << (int) DF_MODE;
302 else if (GET_MODE_SIZE (i) == 16)
303 m32r_mode_class[i] = 1 << (int) TF_MODE;
304 else if (GET_MODE_SIZE (i) == 32)
305 m32r_mode_class[i] = 1 << (int) OF_MODE;
306 else
307 m32r_mode_class[i] = 0;
308 break;
309 case MODE_CC:
310 m32r_mode_class[i] = 1 << (int) C_MODE;
311 break;
312 default:
313 m32r_mode_class[i] = 0;
314 break;
315 }
316 }
317
318 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
319 {
320 if (GPR_P (i))
321 m32r_regno_reg_class[i] = GENERAL_REGS;
322 else if (i == ARG_POINTER_REGNUM)
323 m32r_regno_reg_class[i] = GENERAL_REGS;
324 else
325 m32r_regno_reg_class[i] = NO_REGS;
326 }
327 }
328 \f
329 /* M32R specific attribute support.
330
331 interrupt - for interrupt functions
332
333 model - select code model used to access object
334
335 small: addresses use 24 bits, use bl to make calls
336 medium: addresses use 32 bits, use bl to make calls
337 large: addresses use 32 bits, use seth/add3/jl to make calls
338
339 Grep for MODEL in m32r.h for more info. */
340
341 static tree small_ident1;
342 static tree small_ident2;
343 static tree medium_ident1;
344 static tree medium_ident2;
345 static tree large_ident1;
346 static tree large_ident2;
347
348 static void
349 init_idents (void)
350 {
351 if (small_ident1 == 0)
352 {
353 small_ident1 = get_identifier ("small");
354 small_ident2 = get_identifier ("__small__");
355 medium_ident1 = get_identifier ("medium");
356 medium_ident2 = get_identifier ("__medium__");
357 large_ident1 = get_identifier ("large");
358 large_ident2 = get_identifier ("__large__");
359 }
360 }
361
362 const struct attribute_spec m32r_attribute_table[] =
363 {
364 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
365 { "interrupt", 0, 0, true, false, false, NULL },
366 { "model", 1, 1, true, false, false, m32r_handle_model_attribute },
367 { NULL, 0, 0, false, false, false, NULL }
368 };
369
370
371 /* Handle an "model" attribute; arguments as in
372 struct attribute_spec.handler. */
373 static tree
374 m32r_handle_model_attribute (tree *node ATTRIBUTE_UNUSED, tree name,
375 tree args, int flags ATTRIBUTE_UNUSED,
376 bool *no_add_attrs)
377 {
378 tree arg;
379
380 init_idents ();
381 arg = TREE_VALUE (args);
382
383 if (arg != small_ident1
384 && arg != small_ident2
385 && arg != medium_ident1
386 && arg != medium_ident2
387 && arg != large_ident1
388 && arg != large_ident2)
389 {
390 warning (OPT_Wattributes, "invalid argument of %qs attribute",
391 IDENTIFIER_POINTER (name));
392 *no_add_attrs = true;
393 }
394
395 return NULL_TREE;
396 }
397 \f
398 /* Encode section information of DECL, which is either a VAR_DECL,
399 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
400
401 For the M32R we want to record:
402
403 - whether the object lives in .sdata/.sbss.
404 - what code model should be used to access the object
405 */
406
407 static void
408 m32r_encode_section_info (tree decl, rtx rtl, int first)
409 {
410 int extra_flags = 0;
411 tree model_attr;
412 enum m32r_model model;
413
414 default_encode_section_info (decl, rtl, first);
415
416 if (!DECL_P (decl))
417 return;
418
419 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl));
420 if (model_attr)
421 {
422 tree id;
423
424 init_idents ();
425
426 id = TREE_VALUE (TREE_VALUE (model_attr));
427
428 if (id == small_ident1 || id == small_ident2)
429 model = M32R_MODEL_SMALL;
430 else if (id == medium_ident1 || id == medium_ident2)
431 model = M32R_MODEL_MEDIUM;
432 else if (id == large_ident1 || id == large_ident2)
433 model = M32R_MODEL_LARGE;
434 else
435 gcc_unreachable (); /* shouldn't happen */
436 }
437 else
438 {
439 if (TARGET_MODEL_SMALL)
440 model = M32R_MODEL_SMALL;
441 else if (TARGET_MODEL_MEDIUM)
442 model = M32R_MODEL_MEDIUM;
443 else if (TARGET_MODEL_LARGE)
444 model = M32R_MODEL_LARGE;
445 else
446 gcc_unreachable (); /* shouldn't happen */
447 }
448 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
449
450 if (extra_flags)
451 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags;
452 }
453
454 /* Only mark the object as being small data area addressable if
455 it hasn't been explicitly marked with a code model.
456
457 The user can explicitly put an object in the small data area with the
458 section attribute. If the object is in sdata/sbss and marked with a
459 code model do both [put the object in .sdata and mark it as being
460 addressed with a specific code model - don't mark it as being addressed
461 with an SDA reloc though]. This is ok and might be useful at times. If
462 the object doesn't fit the linker will give an error. */
463
464 static bool
465 m32r_in_small_data_p (tree decl)
466 {
467 tree section;
468
469 if (TREE_CODE (decl) != VAR_DECL)
470 return false;
471
472 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl)))
473 return false;
474
475 section = DECL_SECTION_NAME (decl);
476 if (section)
477 {
478 char *name = (char *) TREE_STRING_POINTER (section);
479 if (strcmp (name, ".sdata") == 0 || strcmp (name, ".sbss") == 0)
480 return true;
481 }
482 else
483 {
484 if (! TREE_READONLY (decl) && ! TARGET_SDATA_NONE)
485 {
486 int size = int_size_in_bytes (TREE_TYPE (decl));
487
488 if (size > 0 && (unsigned HOST_WIDE_INT) size <= g_switch_value)
489 return true;
490 }
491 }
492
493 return false;
494 }
495
496 /* Do anything needed before RTL is emitted for each function. */
497
498 void
499 m32r_init_expanders (void)
500 {
501 /* ??? At one point there was code here. The function is left in
502 to make it easy to experiment. */
503 }
504 \f
505 int
506 call_operand (rtx op, enum machine_mode mode)
507 {
508 if (GET_CODE (op) != MEM)
509 return 0;
510 op = XEXP (op, 0);
511 return call_address_operand (op, mode);
512 }
513
514 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */
515
516 int
517 small_data_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
518 {
519 if (! TARGET_SDATA_USE)
520 return 0;
521
522 if (GET_CODE (op) == SYMBOL_REF)
523 return SYMBOL_REF_SMALL_P (op);
524
525 if (GET_CODE (op) == CONST
526 && GET_CODE (XEXP (op, 0)) == PLUS
527 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
528 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
529 && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
530 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0));
531
532 return 0;
533 }
534
535 /* Return 1 if OP is a symbol that can use 24 bit addressing. */
536
537 int
538 addr24_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
539 {
540 rtx sym;
541
542 if (flag_pic)
543 return 0;
544
545 if (GET_CODE (op) == LABEL_REF)
546 return TARGET_ADDR24;
547
548 if (GET_CODE (op) == SYMBOL_REF)
549 sym = op;
550 else if (GET_CODE (op) == CONST
551 && GET_CODE (XEXP (op, 0)) == PLUS
552 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
553 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
554 && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
555 sym = XEXP (XEXP (op, 0), 0);
556 else
557 return 0;
558
559 if (SYMBOL_REF_MODEL (sym) == M32R_MODEL_SMALL)
560 return 1;
561
562 if (TARGET_ADDR24
563 && (CONSTANT_POOL_ADDRESS_P (sym)
564 || LIT_NAME_P (XSTR (sym, 0))))
565 return 1;
566
567 return 0;
568 }
569
570 /* Return 1 if OP is a symbol that needs 32 bit addressing. */
571
572 int
573 addr32_operand (rtx op, enum machine_mode mode)
574 {
575 rtx sym;
576
577 if (GET_CODE (op) == LABEL_REF)
578 return TARGET_ADDR32;
579
580 if (GET_CODE (op) == SYMBOL_REF)
581 sym = op;
582 else if (GET_CODE (op) == CONST
583 && GET_CODE (XEXP (op, 0)) == PLUS
584 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
585 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
586 && ! flag_pic)
587 sym = XEXP (XEXP (op, 0), 0);
588 else
589 return 0;
590
591 return (! addr24_operand (sym, mode)
592 && ! small_data_operand (sym, mode));
593 }
594
595 /* Return 1 if OP is a function that can be called with the `bl' insn. */
596
597 int
598 call26_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
599 {
600 if (flag_pic)
601 return 1;
602
603 if (GET_CODE (op) == SYMBOL_REF)
604 return SYMBOL_REF_MODEL (op) != M32R_MODEL_LARGE;
605
606 return TARGET_CALL26;
607 }
608
609 /* Return 1 if OP is a DImode const we want to handle inline.
610 This must match the code in the movdi pattern.
611 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */
612
613 int
614 easy_di_const (rtx op)
615 {
616 rtx high_rtx, low_rtx;
617 HOST_WIDE_INT high, low;
618
619 split_double (op, &high_rtx, &low_rtx);
620 high = INTVAL (high_rtx);
621 low = INTVAL (low_rtx);
622 /* Pick constants loadable with 2 16 bit `ldi' insns. */
623 if (high >= -128 && high <= 127
624 && low >= -128 && low <= 127)
625 return 1;
626 return 0;
627 }
628
629 /* Return 1 if OP is a DFmode const we want to handle inline.
630 This must match the code in the movdf pattern.
631 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */
632
633 int
634 easy_df_const (rtx op)
635 {
636 REAL_VALUE_TYPE r;
637 long l[2];
638
639 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
640 REAL_VALUE_TO_TARGET_DOUBLE (r, l);
641 if (l[0] == 0 && l[1] == 0)
642 return 1;
643 if ((l[0] & 0xffff) == 0 && l[1] == 0)
644 return 1;
645 return 0;
646 }
647
648 /* Return 1 if OP is (mem (reg ...)).
649 This is used in insn length calcs. */
650
651 int
652 memreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
653 {
654 return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
655 }
656
657 /* Return nonzero if TYPE must be passed by indirect reference. */
658
659 static bool
660 m32r_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
661 enum machine_mode mode, tree type,
662 bool named ATTRIBUTE_UNUSED)
663 {
664 int size;
665
666 if (type)
667 size = int_size_in_bytes (type);
668 else
669 size = GET_MODE_SIZE (mode);
670
671 return (size < 0 || size > 8);
672 }
673 \f
674 /* Comparisons. */
675
676 /* X and Y are two things to compare using CODE. Emit the compare insn and
677 return the rtx for compare [arg0 of the if_then_else].
678 If need_compare is true then the comparison insn must be generated, rather
679 than being subsumed into the following branch instruction. */
680
681 rtx
682 gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare)
683 {
684 enum rtx_code compare_code;
685 enum rtx_code branch_code;
686 rtx cc_reg = gen_rtx_REG (CCmode, CARRY_REGNUM);
687 int must_swap = 0;
688
689 switch (code)
690 {
691 case EQ: compare_code = EQ; branch_code = NE; break;
692 case NE: compare_code = EQ; branch_code = EQ; break;
693 case LT: compare_code = LT; branch_code = NE; break;
694 case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break;
695 case GT: compare_code = LT; branch_code = NE; must_swap = 1; break;
696 case GE: compare_code = LT; branch_code = EQ; break;
697 case LTU: compare_code = LTU; branch_code = NE; break;
698 case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
699 case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
700 case GEU: compare_code = LTU; branch_code = EQ; break;
701
702 default:
703 gcc_unreachable ();
704 }
705
706 if (need_compare)
707 {
708 switch (compare_code)
709 {
710 case EQ:
711 if (GET_CODE (y) == CONST_INT
712 && CMP_INT16_P (INTVAL (y)) /* Reg equal to small const. */
713 && y != const0_rtx)
714 {
715 rtx tmp = gen_reg_rtx (SImode);
716
717 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
718 x = tmp;
719 y = const0_rtx;
720 }
721 else if (CONSTANT_P (y)) /* Reg equal to const. */
722 {
723 rtx tmp = force_reg (GET_MODE (x), y);
724 y = tmp;
725 }
726
727 if (register_operand (y, SImode) /* Reg equal to reg. */
728 || y == const0_rtx) /* Reg equal to zero. */
729 {
730 emit_insn (gen_cmp_eqsi_insn (x, y));
731
732 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
733 }
734 break;
735
736 case LT:
737 if (register_operand (y, SImode)
738 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
739 {
740 rtx tmp = gen_reg_rtx (SImode); /* Reg compared to reg. */
741
742 switch (code)
743 {
744 case LT:
745 emit_insn (gen_cmp_ltsi_insn (x, y));
746 code = EQ;
747 break;
748 case LE:
749 if (y == const0_rtx)
750 tmp = const1_rtx;
751 else
752 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
753 emit_insn (gen_cmp_ltsi_insn (x, tmp));
754 code = EQ;
755 break;
756 case GT:
757 if (GET_CODE (y) == CONST_INT)
758 tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
759 else
760 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
761 emit_insn (gen_cmp_ltsi_insn (x, tmp));
762 code = NE;
763 break;
764 case GE:
765 emit_insn (gen_cmp_ltsi_insn (x, y));
766 code = NE;
767 break;
768 default:
769 gcc_unreachable ();
770 }
771
772 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
773 }
774 break;
775
776 case LTU:
777 if (register_operand (y, SImode)
778 || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
779 {
780 rtx tmp = gen_reg_rtx (SImode); /* Reg (unsigned) compared to reg. */
781
782 switch (code)
783 {
784 case LTU:
785 emit_insn (gen_cmp_ltusi_insn (x, y));
786 code = EQ;
787 break;
788 case LEU:
789 if (y == const0_rtx)
790 tmp = const1_rtx;
791 else
792 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
793 emit_insn (gen_cmp_ltusi_insn (x, tmp));
794 code = EQ;
795 break;
796 case GTU:
797 if (GET_CODE (y) == CONST_INT)
798 tmp = gen_rtx_PLUS (SImode, y, const1_rtx);
799 else
800 emit_insn (gen_addsi3 (tmp, y, constm1_rtx));
801 emit_insn (gen_cmp_ltusi_insn (x, tmp));
802 code = NE;
803 break;
804 case GEU:
805 emit_insn (gen_cmp_ltusi_insn (x, y));
806 code = NE;
807 break;
808 default:
809 gcc_unreachable ();
810 }
811
812 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx);
813 }
814 break;
815
816 default:
817 gcc_unreachable ();
818 }
819 }
820 else
821 {
822 /* Reg/reg equal comparison. */
823 if (compare_code == EQ
824 && register_operand (y, SImode))
825 return gen_rtx_fmt_ee (code, CCmode, x, y);
826
827 /* Reg/zero signed comparison. */
828 if ((compare_code == EQ || compare_code == LT)
829 && y == const0_rtx)
830 return gen_rtx_fmt_ee (code, CCmode, x, y);
831
832 /* Reg/smallconst equal comparison. */
833 if (compare_code == EQ
834 && GET_CODE (y) == CONST_INT
835 && CMP_INT16_P (INTVAL (y)))
836 {
837 rtx tmp = gen_reg_rtx (SImode);
838
839 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y))));
840 return gen_rtx_fmt_ee (code, CCmode, tmp, const0_rtx);
841 }
842
843 /* Reg/const equal comparison. */
844 if (compare_code == EQ
845 && CONSTANT_P (y))
846 {
847 rtx tmp = force_reg (GET_MODE (x), y);
848
849 return gen_rtx_fmt_ee (code, CCmode, x, tmp);
850 }
851 }
852
853 if (CONSTANT_P (y))
854 {
855 if (must_swap)
856 y = force_reg (GET_MODE (x), y);
857 else
858 {
859 int ok_const = reg_or_int16_operand (y, GET_MODE (y));
860
861 if (! ok_const)
862 y = force_reg (GET_MODE (x), y);
863 }
864 }
865
866 switch (compare_code)
867 {
868 case EQ :
869 emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
870 break;
871 case LT :
872 emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
873 break;
874 case LTU :
875 emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
876 break;
877
878 default:
879 gcc_unreachable ();
880 }
881
882 return gen_rtx_fmt_ee (branch_code, VOIDmode, cc_reg, CONST0_RTX (CCmode));
883 }
884 \f
885 /* Split a 2 word move (DI or DF) into component parts. */
886
887 rtx
888 gen_split_move_double (rtx operands[])
889 {
890 enum machine_mode mode = GET_MODE (operands[0]);
891 rtx dest = operands[0];
892 rtx src = operands[1];
893 rtx val;
894
895 /* We might have (SUBREG (MEM)) here, so just get rid of the
896 subregs to make this code simpler. It is safe to call
897 alter_subreg any time after reload. */
898 if (GET_CODE (dest) == SUBREG)
899 alter_subreg (&dest);
900 if (GET_CODE (src) == SUBREG)
901 alter_subreg (&src);
902
903 start_sequence ();
904 if (GET_CODE (dest) == REG)
905 {
906 int dregno = REGNO (dest);
907
908 /* Reg = reg. */
909 if (GET_CODE (src) == REG)
910 {
911 int sregno = REGNO (src);
912
913 int reverse = (dregno == sregno + 1);
914
915 /* We normally copy the low-numbered register first. However, if
916 the first register operand 0 is the same as the second register of
917 operand 1, we must copy in the opposite order. */
918 emit_insn (gen_rtx_SET (VOIDmode,
919 operand_subword (dest, reverse, TRUE, mode),
920 operand_subword (src, reverse, TRUE, mode)));
921
922 emit_insn (gen_rtx_SET (VOIDmode,
923 operand_subword (dest, !reverse, TRUE, mode),
924 operand_subword (src, !reverse, TRUE, mode)));
925 }
926
927 /* Reg = constant. */
928 else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
929 {
930 rtx words[2];
931 split_double (src, &words[0], &words[1]);
932 emit_insn (gen_rtx_SET (VOIDmode,
933 operand_subword (dest, 0, TRUE, mode),
934 words[0]));
935
936 emit_insn (gen_rtx_SET (VOIDmode,
937 operand_subword (dest, 1, TRUE, mode),
938 words[1]));
939 }
940
941 /* Reg = mem. */
942 else if (GET_CODE (src) == MEM)
943 {
944 /* If the high-address word is used in the address, we must load it
945 last. Otherwise, load it first. */
946 int reverse
947 = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0);
948
949 /* We used to optimize loads from single registers as
950
951 ld r1,r3+; ld r2,r3
952
953 if r3 were not used subsequently. However, the REG_NOTES aren't
954 propagated correctly by the reload phase, and it can cause bad
955 code to be generated. We could still try:
956
957 ld r1,r3+; ld r2,r3; addi r3,-4
958
959 which saves 2 bytes and doesn't force longword alignment. */
960 emit_insn (gen_rtx_SET (VOIDmode,
961 operand_subword (dest, reverse, TRUE, mode),
962 adjust_address (src, SImode,
963 reverse * UNITS_PER_WORD)));
964
965 emit_insn (gen_rtx_SET (VOIDmode,
966 operand_subword (dest, !reverse, TRUE, mode),
967 adjust_address (src, SImode,
968 !reverse * UNITS_PER_WORD)));
969 }
970 else
971 gcc_unreachable ();
972 }
973
974 /* Mem = reg. */
975 /* We used to optimize loads from single registers as
976
977 st r1,r3; st r2,+r3
978
979 if r3 were not used subsequently. However, the REG_NOTES aren't
980 propagated correctly by the reload phase, and it can cause bad
981 code to be generated. We could still try:
982
983 st r1,r3; st r2,+r3; addi r3,-4
984
985 which saves 2 bytes and doesn't force longword alignment. */
986 else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
987 {
988 emit_insn (gen_rtx_SET (VOIDmode,
989 adjust_address (dest, SImode, 0),
990 operand_subword (src, 0, TRUE, mode)));
991
992 emit_insn (gen_rtx_SET (VOIDmode,
993 adjust_address (dest, SImode, UNITS_PER_WORD),
994 operand_subword (src, 1, TRUE, mode)));
995 }
996
997 else
998 gcc_unreachable ();
999
1000 val = get_insns ();
1001 end_sequence ();
1002 return val;
1003 }
1004
1005 \f
1006 static int
1007 m32r_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1008 tree type, bool named ATTRIBUTE_UNUSED)
1009 {
1010 int words;
1011 unsigned int size =
1012 (((mode == BLKmode && type)
1013 ? (unsigned int) int_size_in_bytes (type)
1014 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1)
1015 / UNITS_PER_WORD;
1016
1017 if (*cum >= M32R_MAX_PARM_REGS)
1018 words = 0;
1019 else if (*cum + size > M32R_MAX_PARM_REGS)
1020 words = (*cum + size) - M32R_MAX_PARM_REGS;
1021 else
1022 words = 0;
1023
1024 return words * UNITS_PER_WORD;
1025 }
1026
1027 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1028
1029 static bool
1030 m32r_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
1031 {
1032 return m32r_pass_by_reference (NULL, TYPE_MODE (type), type, false);
1033 }
1034
1035 /* Do any needed setup for a variadic function. For the M32R, we must
1036 create a register parameter block, and then copy any anonymous arguments
1037 in registers to memory.
1038
1039 CUM has not been updated for the last named argument which has type TYPE
1040 and mode MODE, and we rely on this fact. */
1041
1042 static void
1043 m32r_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1044 tree type, int *pretend_size, int no_rtl)
1045 {
1046 int first_anon_arg;
1047
1048 if (no_rtl)
1049 return;
1050
1051 /* All BLKmode values are passed by reference. */
1052 gcc_assert (mode != BLKmode);
1053
1054 first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
1055 + ROUND_ADVANCE_ARG (mode, type));
1056
1057 if (first_anon_arg < M32R_MAX_PARM_REGS)
1058 {
1059 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */
1060 int first_reg_offset = first_anon_arg;
1061 /* Size in words to "pretend" allocate. */
1062 int size = M32R_MAX_PARM_REGS - first_reg_offset;
1063 rtx regblock;
1064
1065 regblock = gen_rtx_MEM (BLKmode,
1066 plus_constant (arg_pointer_rtx,
1067 FIRST_PARM_OFFSET (0)));
1068 set_mem_alias_set (regblock, get_varargs_alias_set ());
1069 move_block_from_reg (first_reg_offset, regblock, size);
1070
1071 *pretend_size = (size * UNITS_PER_WORD);
1072 }
1073 }
1074
1075 \f
1076 /* Return true if INSN is real instruction bearing insn. */
1077
1078 static int
1079 m32r_is_insn (rtx insn)
1080 {
1081 return (INSN_P (insn)
1082 && GET_CODE (PATTERN (insn)) != USE
1083 && GET_CODE (PATTERN (insn)) != CLOBBER
1084 && GET_CODE (PATTERN (insn)) != ADDR_VEC);
1085 }
1086
1087 /* Increase the priority of long instructions so that the
1088 short instructions are scheduled ahead of the long ones. */
1089
1090 static int
1091 m32r_adjust_priority (rtx insn, int priority)
1092 {
1093 if (m32r_is_insn (insn)
1094 && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1095 priority <<= 3;
1096
1097 return priority;
1098 }
1099
1100 \f
1101 /* Indicate how many instructions can be issued at the same time.
1102 This is sort of a lie. The m32r can issue only 1 long insn at
1103 once, but it can issue 2 short insns. The default therefore is
1104 set at 2, but this can be overridden by the command line option
1105 -missue-rate=1. */
1106
1107 static int
1108 m32r_issue_rate (void)
1109 {
1110 return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2);
1111 }
1112 \f
1113 /* Cost functions. */
1114
1115 static bool
1116 m32r_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int *total)
1117 {
1118 switch (code)
1119 {
1120 /* Small integers are as cheap as registers. 4 byte values can be
1121 fetched as immediate constants - let's give that the cost of an
1122 extra insn. */
1123 case CONST_INT:
1124 if (INT16_P (INTVAL (x)))
1125 {
1126 *total = 0;
1127 return true;
1128 }
1129 /* FALLTHRU */
1130
1131 case CONST:
1132 case LABEL_REF:
1133 case SYMBOL_REF:
1134 *total = COSTS_N_INSNS (1);
1135 return true;
1136
1137 case CONST_DOUBLE:
1138 {
1139 rtx high, low;
1140
1141 split_double (x, &high, &low);
1142 *total = COSTS_N_INSNS (!INT16_P (INTVAL (high))
1143 + !INT16_P (INTVAL (low)));
1144 return true;
1145 }
1146
1147 case MULT:
1148 *total = COSTS_N_INSNS (3);
1149 return true;
1150
1151 case DIV:
1152 case UDIV:
1153 case MOD:
1154 case UMOD:
1155 *total = COSTS_N_INSNS (10);
1156 return true;
1157
1158 default:
1159 return false;
1160 }
1161 }
1162 \f
1163 /* Type of function DECL.
1164
1165 The result is cached. To reset the cache at the end of a function,
1166 call with DECL = NULL_TREE. */
1167
1168 enum m32r_function_type
1169 m32r_compute_function_type (tree decl)
1170 {
1171 /* Cached value. */
1172 static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1173 /* Last function we were called for. */
1174 static tree last_fn = NULL_TREE;
1175
1176 /* Resetting the cached value? */
1177 if (decl == NULL_TREE)
1178 {
1179 fn_type = M32R_FUNCTION_UNKNOWN;
1180 last_fn = NULL_TREE;
1181 return fn_type;
1182 }
1183
1184 if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1185 return fn_type;
1186
1187 /* Compute function type. */
1188 fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE
1189 ? M32R_FUNCTION_INTERRUPT
1190 : M32R_FUNCTION_NORMAL);
1191
1192 last_fn = decl;
1193 return fn_type;
1194 }
1195 \f/* Function prologue/epilogue handlers. */
1196
1197 /* M32R stack frames look like:
1198
1199 Before call After call
1200 +-----------------------+ +-----------------------+
1201 | | | |
1202 high | local variables, | | local variables, |
1203 mem | reg save area, etc. | | reg save area, etc. |
1204 | | | |
1205 +-----------------------+ +-----------------------+
1206 | | | |
1207 | arguments on stack. | | arguments on stack. |
1208 | | | |
1209 SP+0->+-----------------------+ +-----------------------+
1210 | reg parm save area, |
1211 | only created for |
1212 | variable argument |
1213 | functions |
1214 +-----------------------+
1215 | previous frame ptr |
1216 +-----------------------+
1217 | |
1218 | register save area |
1219 | |
1220 +-----------------------+
1221 | return address |
1222 +-----------------------+
1223 | |
1224 | local variables |
1225 | |
1226 +-----------------------+
1227 | |
1228 | alloca allocations |
1229 | |
1230 +-----------------------+
1231 | |
1232 low | arguments on stack |
1233 memory | |
1234 SP+0->+-----------------------+
1235
1236 Notes:
1237 1) The "reg parm save area" does not exist for non variable argument fns.
1238 2) The "reg parm save area" can be eliminated completely if we saved regs
1239 containing anonymous args separately but that complicates things too
1240 much (so it's not done).
1241 3) The return address is saved after the register save area so as to have as
1242 many insns as possible between the restoration of `lr' and the `jmp lr'. */
1243
1244 /* Structure to be filled in by m32r_compute_frame_size with register
1245 save masks, and offsets for the current function. */
1246 struct m32r_frame_info
1247 {
1248 unsigned int total_size; /* # bytes that the entire frame takes up. */
1249 unsigned int extra_size; /* # bytes of extra stuff. */
1250 unsigned int pretend_size; /* # bytes we push and pretend caller did. */
1251 unsigned int args_size; /* # bytes that outgoing arguments take up. */
1252 unsigned int reg_size; /* # bytes needed to store regs. */
1253 unsigned int var_size; /* # bytes that variables take up. */
1254 unsigned int gmask; /* Mask of saved gp registers. */
1255 unsigned int save_fp; /* Nonzero if fp must be saved. */
1256 unsigned int save_lr; /* Nonzero if lr (return addr) must be saved. */
1257 int initialized; /* Nonzero if frame size already calculated. */
1258 };
1259
1260 /* Current frame information calculated by m32r_compute_frame_size. */
1261 static struct m32r_frame_info current_frame_info;
1262
1263 /* Zero structure to initialize current_frame_info. */
1264 static struct m32r_frame_info zero_frame_info;
1265
1266 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1267 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1268
1269 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1270 The return address and frame pointer are treated separately.
1271 Don't consider them here. */
1272 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1273 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1274 && (regs_ever_live[regno] && (!call_really_used_regs[regno] || interrupt_p)))
1275
1276 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1277 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM] || current_function_profile)
1278
1279 #define SHORT_INSN_SIZE 2 /* Size of small instructions. */
1280 #define LONG_INSN_SIZE 4 /* Size of long instructions. */
1281
1282 /* Return the bytes needed to compute the frame pointer from the current
1283 stack pointer.
1284
1285 SIZE is the size needed for local variables. */
1286
1287 unsigned int
1288 m32r_compute_frame_size (int size) /* # of var. bytes allocated. */
1289 {
1290 int regno;
1291 unsigned int total_size, var_size, args_size, pretend_size, extra_size;
1292 unsigned int reg_size, frame_size;
1293 unsigned int gmask;
1294 enum m32r_function_type fn_type;
1295 int interrupt_p;
1296 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table);
1297
1298 var_size = M32R_STACK_ALIGN (size);
1299 args_size = M32R_STACK_ALIGN (current_function_outgoing_args_size);
1300 pretend_size = current_function_pretend_args_size;
1301 extra_size = FIRST_PARM_OFFSET (0);
1302 total_size = extra_size + pretend_size + args_size + var_size;
1303 reg_size = 0;
1304 gmask = 0;
1305
1306 /* See if this is an interrupt handler. Call used registers must be saved
1307 for them too. */
1308 fn_type = m32r_compute_function_type (current_function_decl);
1309 interrupt_p = M32R_INTERRUPT_P (fn_type);
1310
1311 /* Calculate space needed for registers. */
1312 for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1313 {
1314 if (MUST_SAVE_REGISTER (regno, interrupt_p)
1315 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used))
1316 {
1317 reg_size += UNITS_PER_WORD;
1318 gmask |= 1 << regno;
1319 }
1320 }
1321
1322 current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
1323 current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR || pic_reg_used;
1324
1325 reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1326 * UNITS_PER_WORD);
1327 total_size += reg_size;
1328
1329 /* ??? Not sure this is necessary, and I don't think the epilogue
1330 handler will do the right thing if this changes total_size. */
1331 total_size = M32R_STACK_ALIGN (total_size);
1332
1333 frame_size = total_size - (pretend_size + reg_size);
1334
1335 /* Save computed information. */
1336 current_frame_info.total_size = total_size;
1337 current_frame_info.extra_size = extra_size;
1338 current_frame_info.pretend_size = pretend_size;
1339 current_frame_info.var_size = var_size;
1340 current_frame_info.args_size = args_size;
1341 current_frame_info.reg_size = reg_size;
1342 current_frame_info.gmask = gmask;
1343 current_frame_info.initialized = reload_completed;
1344
1345 /* Ok, we're done. */
1346 return total_size;
1347 }
1348 \f
1349 /* The table we use to reference PIC data. */
1350 static rtx global_offset_table;
1351
1352 static void
1353 m32r_reload_lr (rtx sp, int size)
1354 {
1355 rtx lr = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM);
1356
1357 if (size == 0)
1358 emit_insn (gen_movsi (lr, gen_rtx_MEM (Pmode, sp)));
1359 else if (size <= 32768)
1360 emit_insn (gen_movsi (lr, gen_rtx_MEM (Pmode,
1361 gen_rtx_PLUS (Pmode, sp,
1362 GEN_INT (size)))));
1363 else
1364 {
1365 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1366
1367 emit_insn (gen_movsi (tmp, GEN_INT (size)));
1368 emit_insn (gen_addsi3 (tmp, tmp, sp));
1369 emit_insn (gen_movsi (lr, gen_rtx_MEM (Pmode, tmp)));
1370 }
1371
1372 emit_insn (gen_rtx_USE (VOIDmode, lr));
1373 }
1374
1375 void
1376 m32r_load_pic_register (void)
1377 {
1378 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
1379 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
1380 GEN_INT (TARGET_MODEL_SMALL)));
1381
1382 /* Need to emit this whether or not we obey regdecls,
1383 since setjmp/longjmp can cause life info to screw up. */
1384 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
1385 }
1386
1387 /* Expand the m32r prologue as a series of insns. */
1388
1389 void
1390 m32r_expand_prologue (void)
1391 {
1392 int regno;
1393 int frame_size;
1394 unsigned int gmask;
1395 int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table);
1396
1397 if (! current_frame_info.initialized)
1398 m32r_compute_frame_size (get_frame_size ());
1399
1400 gmask = current_frame_info.gmask;
1401
1402 /* These cases shouldn't happen. Catch them now. */
1403 gcc_assert (current_frame_info.total_size || !gmask);
1404
1405 /* Allocate space for register arguments if this is a variadic function. */
1406 if (current_frame_info.pretend_size != 0)
1407 {
1408 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1409 the wrong result on a 64-bit host. */
1410 HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1411 emit_insn (gen_addsi3 (stack_pointer_rtx,
1412 stack_pointer_rtx,
1413 GEN_INT (-pretend_size)));
1414 }
1415
1416 /* Save any registers we need to and set up fp. */
1417 if (current_frame_info.save_fp)
1418 emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
1419
1420 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1421
1422 /* Save any needed call-saved regs (and call-used if this is an
1423 interrupt handler). */
1424 for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
1425 {
1426 if ((gmask & (1 << regno)) != 0)
1427 emit_insn (gen_movsi_push (stack_pointer_rtx,
1428 gen_rtx_REG (Pmode, regno)));
1429 }
1430
1431 if (current_frame_info.save_lr)
1432 emit_insn (gen_movsi_push (stack_pointer_rtx,
1433 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1434
1435 /* Allocate the stack frame. */
1436 frame_size = (current_frame_info.total_size
1437 - (current_frame_info.pretend_size
1438 + current_frame_info.reg_size));
1439
1440 if (frame_size == 0)
1441 ; /* Nothing to do. */
1442 else if (frame_size <= 32768)
1443 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1444 GEN_INT (-frame_size)));
1445 else
1446 {
1447 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1448
1449 emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
1450 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
1451 }
1452
1453 if (frame_pointer_needed)
1454 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
1455
1456 if (current_function_profile)
1457 /* Push lr for mcount (form_pc, x). */
1458 emit_insn (gen_movsi_push (stack_pointer_rtx,
1459 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1460
1461 if (pic_reg_used)
1462 {
1463 m32r_load_pic_register ();
1464 m32r_reload_lr (stack_pointer_rtx,
1465 (current_function_profile ? 0 : frame_size));
1466 }
1467
1468 if (current_function_profile && !pic_reg_used)
1469 emit_insn (gen_blockage ());
1470 }
1471
1472 \f
1473 /* Set up the stack and frame pointer (if desired) for the function.
1474 Note, if this is changed, you need to mirror the changes in
1475 m32r_compute_frame_size which calculates the prolog size. */
1476
1477 static void
1478 m32r_output_function_prologue (FILE * file, HOST_WIDE_INT size)
1479 {
1480 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1481
1482 /* If this is an interrupt handler, mark it as such. */
1483 if (M32R_INTERRUPT_P (fn_type))
1484 fprintf (file, "\t%s interrupt handler\n", ASM_COMMENT_START);
1485
1486 if (! current_frame_info.initialized)
1487 m32r_compute_frame_size (size);
1488
1489 /* This is only for the human reader. */
1490 fprintf (file,
1491 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
1492 ASM_COMMENT_START,
1493 current_frame_info.var_size,
1494 current_frame_info.reg_size / 4,
1495 current_frame_info.args_size,
1496 current_frame_info.extra_size);
1497 }
1498 \f
1499 /* Do any necessary cleanup after a function to restore stack, frame,
1500 and regs. */
1501
1502 static void
1503 m32r_output_function_epilogue (FILE * file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1504 {
1505 int regno;
1506 int noepilogue = FALSE;
1507 int total_size;
1508 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1509
1510 /* This is only for the human reader. */
1511 fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
1512
1513 gcc_assert (current_frame_info.initialized);
1514 total_size = current_frame_info.total_size;
1515
1516 if (total_size == 0)
1517 {
1518 rtx insn = get_last_insn ();
1519
1520 /* If the last insn was a BARRIER, we don't have to write any code
1521 because a jump (aka return) was put there. */
1522 if (GET_CODE (insn) == NOTE)
1523 insn = prev_nonnote_insn (insn);
1524 if (insn && GET_CODE (insn) == BARRIER)
1525 noepilogue = TRUE;
1526 }
1527
1528 if (!noepilogue)
1529 {
1530 unsigned int var_size = current_frame_info.var_size;
1531 unsigned int args_size = current_frame_info.args_size;
1532 unsigned int gmask = current_frame_info.gmask;
1533 int can_trust_sp_p = !current_function_calls_alloca;
1534 const char * sp_str = reg_names[STACK_POINTER_REGNUM];
1535 const char * fp_str = reg_names[FRAME_POINTER_REGNUM];
1536
1537 /* The first thing to do is point the sp at the bottom of the register
1538 save area. */
1539 if (can_trust_sp_p)
1540 {
1541 unsigned int reg_offset = var_size + args_size;
1542 if (reg_offset == 0)
1543 ; /* Nothing to do. */
1544 else if (reg_offset < 128)
1545 fprintf (file, "\taddi %s,%s%d\n",
1546 sp_str, IMMEDIATE_PREFIX, reg_offset);
1547 else if (reg_offset < 32768)
1548 fprintf (file, "\tadd3 %s,%s,%s%d\n",
1549 sp_str, sp_str, IMMEDIATE_PREFIX, reg_offset);
1550 else
1551 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
1552 reg_names[PROLOGUE_TMP_REGNUM],
1553 IMMEDIATE_PREFIX, reg_offset,
1554 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
1555 }
1556 else if (frame_pointer_needed)
1557 {
1558 unsigned int reg_offset = var_size + args_size;
1559
1560 if (reg_offset == 0)
1561 fprintf (file, "\tmv %s,%s\n", sp_str, fp_str);
1562 else if (reg_offset < 32768)
1563 fprintf (file, "\tadd3 %s,%s,%s%d\n",
1564 sp_str, fp_str, IMMEDIATE_PREFIX, reg_offset);
1565 else
1566 fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
1567 reg_names[PROLOGUE_TMP_REGNUM],
1568 IMMEDIATE_PREFIX, reg_offset,
1569 sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
1570 }
1571 else
1572 gcc_unreachable ();
1573
1574 if (current_frame_info.save_lr)
1575 fprintf (file, "\tpop %s\n", reg_names[RETURN_ADDR_REGNUM]);
1576
1577 /* Restore any saved registers, in reverse order of course. */
1578 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1579 for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
1580 {
1581 if ((gmask & (1L << regno)) != 0)
1582 fprintf (file, "\tpop %s\n", reg_names[regno]);
1583 }
1584
1585 if (current_frame_info.save_fp)
1586 fprintf (file, "\tpop %s\n", fp_str);
1587
1588 /* Remove varargs area if present. */
1589 if (current_frame_info.pretend_size != 0)
1590 fprintf (file, "\taddi %s,%s%d\n",
1591 sp_str, IMMEDIATE_PREFIX, current_frame_info.pretend_size);
1592
1593 /* Emit the return instruction. */
1594 if (M32R_INTERRUPT_P (fn_type))
1595 fprintf (file, "\trte\n");
1596 else
1597 fprintf (file, "\tjmp %s\n", reg_names[RETURN_ADDR_REGNUM]);
1598 }
1599
1600 /* Reset state info for each function. */
1601 current_frame_info = zero_frame_info;
1602 m32r_compute_function_type (NULL_TREE);
1603 }
1604 \f
1605 /* Return nonzero if this function is known to have a null or 1 instruction
1606 epilogue. */
1607
1608 int
1609 direct_return (void)
1610 {
1611 if (!reload_completed)
1612 return FALSE;
1613
1614 if (! current_frame_info.initialized)
1615 m32r_compute_frame_size (get_frame_size ());
1616
1617 return current_frame_info.total_size == 0;
1618 }
1619
1620 \f
1621 /* PIC. */
1622
1623 int
1624 m32r_legitimate_pic_operand_p (rtx x)
1625 {
1626 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1627 return 0;
1628
1629 if (GET_CODE (x) == CONST
1630 && GET_CODE (XEXP (x, 0)) == PLUS
1631 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
1632 || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
1633 && (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
1634 return 0;
1635
1636 return 1;
1637 }
1638
1639 rtx
1640 m32r_legitimize_pic_address (rtx orig, rtx reg)
1641 {
1642 #ifdef DEBUG_PIC
1643 printf("m32r_legitimize_pic_address()\n");
1644 #endif
1645
1646 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
1647 {
1648 rtx pic_ref, address;
1649 rtx insn;
1650 int subregs = 0;
1651
1652 if (reg == 0)
1653 {
1654 gcc_assert (!reload_in_progress && !reload_completed);
1655 reg = gen_reg_rtx (Pmode);
1656
1657 subregs = 1;
1658 }
1659
1660 if (subregs)
1661 address = gen_reg_rtx (Pmode);
1662 else
1663 address = reg;
1664
1665 current_function_uses_pic_offset_table = 1;
1666
1667 if (GET_CODE (orig) == LABEL_REF
1668 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
1669 {
1670 emit_insn (gen_gotoff_load_addr (reg, orig));
1671 emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx));
1672 return reg;
1673 }
1674
1675 emit_insn (gen_pic_load_addr (address, orig));
1676
1677 emit_insn (gen_addsi3 (address, address, pic_offset_table_rtx));
1678 pic_ref = gen_const_mem (Pmode, address);
1679 insn = emit_move_insn (reg, pic_ref);
1680 #if 0
1681 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1682 by loop. */
1683 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
1684 REG_NOTES (insn));
1685 #endif
1686 return reg;
1687 }
1688 else if (GET_CODE (orig) == CONST)
1689 {
1690 rtx base, offset;
1691
1692 if (GET_CODE (XEXP (orig, 0)) == PLUS
1693 && XEXP (XEXP (orig, 0), 1) == pic_offset_table_rtx)
1694 return orig;
1695
1696 if (reg == 0)
1697 {
1698 gcc_assert (!reload_in_progress && !reload_completed);
1699 reg = gen_reg_rtx (Pmode);
1700 }
1701
1702 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1703 {
1704 base = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg);
1705 if (base == reg)
1706 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), NULL_RTX);
1707 else
1708 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), reg);
1709 }
1710 else
1711 return orig;
1712
1713 if (GET_CODE (offset) == CONST_INT)
1714 {
1715 if (INT16_P (INTVAL (offset)))
1716 return plus_constant (base, INTVAL (offset));
1717 else
1718 {
1719 gcc_assert (! reload_in_progress && ! reload_completed);
1720 offset = force_reg (Pmode, offset);
1721 }
1722 }
1723
1724 return gen_rtx_PLUS (Pmode, base, offset);
1725 }
1726
1727 return orig;
1728 }
1729
1730 /* Emit special PIC prologues and epilogues. */
1731
1732 void
1733 m32r_finalize_pic (void)
1734 {
1735 current_function_uses_pic_offset_table |= current_function_profile;
1736 }
1737 \f
1738 /* Nested function support. */
1739
1740 /* Emit RTL insns to initialize the variable parts of a trampoline.
1741 FNADDR is an RTX for the address of the function's pure code.
1742 CXT is an RTX for the static chain value for the function. */
1743
1744 void
1745 m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED,
1746 rtx fnaddr ATTRIBUTE_UNUSED,
1747 rtx cxt ATTRIBUTE_UNUSED)
1748 {
1749 }
1750 \f
1751 static void
1752 m32r_file_start (void)
1753 {
1754 default_file_start ();
1755
1756 if (flag_verbose_asm)
1757 fprintf (asm_out_file,
1758 "%s M32R/D special options: -G " HOST_WIDE_INT_PRINT_UNSIGNED "\n",
1759 ASM_COMMENT_START, g_switch_value);
1760
1761 if (TARGET_LITTLE_ENDIAN)
1762 fprintf (asm_out_file, "\t.little\n");
1763 }
1764 \f
1765 /* Print operand X (an rtx) in assembler syntax to file FILE.
1766 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1767 For `%' followed by punctuation, CODE is the punctuation and X is null. */
1768
1769 void
1770 m32r_print_operand (FILE * file, rtx x, int code)
1771 {
1772 rtx addr;
1773
1774 switch (code)
1775 {
1776 /* The 's' and 'p' codes are used by output_block_move() to
1777 indicate post-increment 's'tores and 'p're-increment loads. */
1778 case 's':
1779 if (GET_CODE (x) == REG)
1780 fprintf (file, "@+%s", reg_names [REGNO (x)]);
1781 else
1782 output_operand_lossage ("invalid operand to %%s code");
1783 return;
1784
1785 case 'p':
1786 if (GET_CODE (x) == REG)
1787 fprintf (file, "@%s+", reg_names [REGNO (x)]);
1788 else
1789 output_operand_lossage ("invalid operand to %%p code");
1790 return;
1791
1792 case 'R' :
1793 /* Write second word of DImode or DFmode reference,
1794 register or memory. */
1795 if (GET_CODE (x) == REG)
1796 fputs (reg_names[REGNO (x)+1], file);
1797 else if (GET_CODE (x) == MEM)
1798 {
1799 fprintf (file, "@(");
1800 /* Handle possible auto-increment. Since it is pre-increment and
1801 we have already done it, we can just use an offset of four. */
1802 /* ??? This is taken from rs6000.c I think. I don't think it is
1803 currently necessary, but keep it around. */
1804 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1805 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1806 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
1807 else
1808 output_address (plus_constant (XEXP (x, 0), 4));
1809 fputc (')', file);
1810 }
1811 else
1812 output_operand_lossage ("invalid operand to %%R code");
1813 return;
1814
1815 case 'H' : /* High word. */
1816 case 'L' : /* Low word. */
1817 if (GET_CODE (x) == REG)
1818 {
1819 /* L = least significant word, H = most significant word. */
1820 if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
1821 fputs (reg_names[REGNO (x)], file);
1822 else
1823 fputs (reg_names[REGNO (x)+1], file);
1824 }
1825 else if (GET_CODE (x) == CONST_INT
1826 || GET_CODE (x) == CONST_DOUBLE)
1827 {
1828 rtx first, second;
1829
1830 split_double (x, &first, &second);
1831 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
1832 code == 'L' ? INTVAL (first) : INTVAL (second));
1833 }
1834 else
1835 output_operand_lossage ("invalid operand to %%H/%%L code");
1836 return;
1837
1838 case 'A' :
1839 {
1840 char str[30];
1841
1842 if (GET_CODE (x) != CONST_DOUBLE
1843 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
1844 fatal_insn ("bad insn for 'A'", x);
1845
1846 real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (x), sizeof (str), 0, 1);
1847 fprintf (file, "%s", str);
1848 return;
1849 }
1850
1851 case 'B' : /* Bottom half. */
1852 case 'T' : /* Top half. */
1853 /* Output the argument to a `seth' insn (sets the Top half-word).
1854 For constants output arguments to a seth/or3 pair to set Top and
1855 Bottom halves. For symbols output arguments to a seth/add3 pair to
1856 set Top and Bottom halves. The difference exists because for
1857 constants seth/or3 is more readable but for symbols we need to use
1858 the same scheme as `ld' and `st' insns (16 bit addend is signed). */
1859 switch (GET_CODE (x))
1860 {
1861 case CONST_INT :
1862 case CONST_DOUBLE :
1863 {
1864 rtx first, second;
1865
1866 split_double (x, &first, &second);
1867 x = WORDS_BIG_ENDIAN ? second : first;
1868 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
1869 (code == 'B'
1870 ? INTVAL (x) & 0xffff
1871 : (INTVAL (x) >> 16) & 0xffff));
1872 }
1873 return;
1874 case CONST :
1875 case SYMBOL_REF :
1876 if (code == 'B'
1877 && small_data_operand (x, VOIDmode))
1878 {
1879 fputs ("sda(", file);
1880 output_addr_const (file, x);
1881 fputc (')', file);
1882 return;
1883 }
1884 /* fall through */
1885 case LABEL_REF :
1886 fputs (code == 'T' ? "shigh(" : "low(", file);
1887 output_addr_const (file, x);
1888 fputc (')', file);
1889 return;
1890 default :
1891 output_operand_lossage ("invalid operand to %%T/%%B code");
1892 return;
1893 }
1894 break;
1895
1896 case 'U' :
1897 /* ??? wip */
1898 /* Output a load/store with update indicator if appropriate. */
1899 if (GET_CODE (x) == MEM)
1900 {
1901 if (GET_CODE (XEXP (x, 0)) == PRE_INC
1902 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
1903 fputs (".a", file);
1904 }
1905 else
1906 output_operand_lossage ("invalid operand to %%U code");
1907 return;
1908
1909 case 'N' :
1910 /* Print a constant value negated. */
1911 if (GET_CODE (x) == CONST_INT)
1912 output_addr_const (file, GEN_INT (- INTVAL (x)));
1913 else
1914 output_operand_lossage ("invalid operand to %%N code");
1915 return;
1916
1917 case 'X' :
1918 /* Print a const_int in hex. Used in comments. */
1919 if (GET_CODE (x) == CONST_INT)
1920 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x));
1921 return;
1922
1923 case '#' :
1924 fputs (IMMEDIATE_PREFIX, file);
1925 return;
1926
1927 case 0 :
1928 /* Do nothing special. */
1929 break;
1930
1931 default :
1932 /* Unknown flag. */
1933 output_operand_lossage ("invalid operand output code");
1934 }
1935
1936 switch (GET_CODE (x))
1937 {
1938 case REG :
1939 fputs (reg_names[REGNO (x)], file);
1940 break;
1941
1942 case MEM :
1943 addr = XEXP (x, 0);
1944 if (GET_CODE (addr) == PRE_INC)
1945 {
1946 if (GET_CODE (XEXP (addr, 0)) != REG)
1947 fatal_insn ("pre-increment address is not a register", x);
1948
1949 fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
1950 }
1951 else if (GET_CODE (addr) == PRE_DEC)
1952 {
1953 if (GET_CODE (XEXP (addr, 0)) != REG)
1954 fatal_insn ("pre-decrement address is not a register", x);
1955
1956 fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
1957 }
1958 else if (GET_CODE (addr) == POST_INC)
1959 {
1960 if (GET_CODE (XEXP (addr, 0)) != REG)
1961 fatal_insn ("post-increment address is not a register", x);
1962
1963 fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
1964 }
1965 else
1966 {
1967 fputs ("@(", file);
1968 output_address (XEXP (x, 0));
1969 fputc (')', file);
1970 }
1971 break;
1972
1973 case CONST_DOUBLE :
1974 /* We handle SFmode constants here as output_addr_const doesn't. */
1975 if (GET_MODE (x) == SFmode)
1976 {
1977 REAL_VALUE_TYPE d;
1978 long l;
1979
1980 REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1981 REAL_VALUE_TO_TARGET_SINGLE (d, l);
1982 fprintf (file, "0x%08lx", l);
1983 break;
1984 }
1985
1986 /* Fall through. Let output_addr_const deal with it. */
1987
1988 default :
1989 output_addr_const (file, x);
1990 break;
1991 }
1992 }
1993
1994 /* Print a memory address as an operand to reference that memory location. */
1995
1996 void
1997 m32r_print_operand_address (FILE * file, rtx addr)
1998 {
1999 rtx base;
2000 rtx index = 0;
2001 int offset = 0;
2002
2003 switch (GET_CODE (addr))
2004 {
2005 case REG :
2006 fputs (reg_names[REGNO (addr)], file);
2007 break;
2008
2009 case PLUS :
2010 if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
2011 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
2012 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2013 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
2014 else
2015 base = XEXP (addr, 0), index = XEXP (addr, 1);
2016 if (GET_CODE (base) == REG)
2017 {
2018 /* Print the offset first (if present) to conform to the manual. */
2019 if (index == 0)
2020 {
2021 if (offset != 0)
2022 fprintf (file, "%d,", offset);
2023 fputs (reg_names[REGNO (base)], file);
2024 }
2025 /* The chip doesn't support this, but left in for generality. */
2026 else if (GET_CODE (index) == REG)
2027 fprintf (file, "%s,%s",
2028 reg_names[REGNO (base)], reg_names[REGNO (index)]);
2029 /* Not sure this can happen, but leave in for now. */
2030 else if (GET_CODE (index) == SYMBOL_REF)
2031 {
2032 output_addr_const (file, index);
2033 fputc (',', file);
2034 fputs (reg_names[REGNO (base)], file);
2035 }
2036 else
2037 fatal_insn ("bad address", addr);
2038 }
2039 else if (GET_CODE (base) == LO_SUM)
2040 {
2041 gcc_assert (!index && GET_CODE (XEXP (base, 0)) == REG);
2042 if (small_data_operand (XEXP (base, 1), VOIDmode))
2043 fputs ("sda(", file);
2044 else
2045 fputs ("low(", file);
2046 output_addr_const (file, plus_constant (XEXP (base, 1), offset));
2047 fputs ("),", file);
2048 fputs (reg_names[REGNO (XEXP (base, 0))], file);
2049 }
2050 else
2051 fatal_insn ("bad address", addr);
2052 break;
2053
2054 case LO_SUM :
2055 if (GET_CODE (XEXP (addr, 0)) != REG)
2056 fatal_insn ("lo_sum not of register", addr);
2057 if (small_data_operand (XEXP (addr, 1), VOIDmode))
2058 fputs ("sda(", file);
2059 else
2060 fputs ("low(", file);
2061 output_addr_const (file, XEXP (addr, 1));
2062 fputs ("),", file);
2063 fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2064 break;
2065
2066 case PRE_INC : /* Assume SImode. */
2067 fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2068 break;
2069
2070 case PRE_DEC : /* Assume SImode. */
2071 fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2072 break;
2073
2074 case POST_INC : /* Assume SImode. */
2075 fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
2076 break;
2077
2078 default :
2079 output_addr_const (file, addr);
2080 break;
2081 }
2082 }
2083
2084 /* Return true if the operands are the constants 0 and 1. */
2085
2086 int
2087 zero_and_one (rtx operand1, rtx operand2)
2088 {
2089 return
2090 GET_CODE (operand1) == CONST_INT
2091 && GET_CODE (operand2) == CONST_INT
2092 && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2093 ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2094 }
2095
2096 /* Generate the correct assembler code to handle the conditional loading of a
2097 value into a register. It is known that the operands satisfy the
2098 conditional_move_operand() function above. The destination is operand[0].
2099 The condition is operand [1]. The 'true' value is operand [2] and the
2100 'false' value is operand [3]. */
2101
2102 char *
2103 emit_cond_move (rtx * operands, rtx insn ATTRIBUTE_UNUSED)
2104 {
2105 static char buffer [100];
2106 const char * dest = reg_names [REGNO (operands [0])];
2107
2108 buffer [0] = 0;
2109
2110 /* Destination must be a register. */
2111 gcc_assert (GET_CODE (operands [0]) == REG);
2112 gcc_assert (conditional_move_operand (operands [2], SImode));
2113 gcc_assert (conditional_move_operand (operands [3], SImode));
2114
2115 /* Check to see if the test is reversed. */
2116 if (GET_CODE (operands [1]) == NE)
2117 {
2118 rtx tmp = operands [2];
2119 operands [2] = operands [3];
2120 operands [3] = tmp;
2121 }
2122
2123 sprintf (buffer, "mvfc %s, cbr", dest);
2124
2125 /* If the true value was '0' then we need to invert the results of the move. */
2126 if (INTVAL (operands [2]) == 0)
2127 sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2128 dest, dest);
2129
2130 return buffer;
2131 }
2132
2133 /* Returns true if the registers contained in the two
2134 rtl expressions are different. */
2135
2136 int
2137 m32r_not_same_reg (rtx a, rtx b)
2138 {
2139 int reg_a = -1;
2140 int reg_b = -2;
2141
2142 while (GET_CODE (a) == SUBREG)
2143 a = SUBREG_REG (a);
2144
2145 if (GET_CODE (a) == REG)
2146 reg_a = REGNO (a);
2147
2148 while (GET_CODE (b) == SUBREG)
2149 b = SUBREG_REG (b);
2150
2151 if (GET_CODE (b) == REG)
2152 reg_b = REGNO (b);
2153
2154 return reg_a != reg_b;
2155 }
2156
2157 \f
2158 rtx
2159 m32r_function_symbol (const char *name)
2160 {
2161 int extra_flags = 0;
2162 enum m32r_model model;
2163 rtx sym = gen_rtx_SYMBOL_REF (Pmode, name);
2164
2165 if (TARGET_MODEL_SMALL)
2166 model = M32R_MODEL_SMALL;
2167 else if (TARGET_MODEL_MEDIUM)
2168 model = M32R_MODEL_MEDIUM;
2169 else if (TARGET_MODEL_LARGE)
2170 model = M32R_MODEL_LARGE;
2171 else
2172 gcc_unreachable (); /* Shouldn't happen. */
2173 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT;
2174
2175 if (extra_flags)
2176 SYMBOL_REF_FLAGS (sym) |= extra_flags;
2177
2178 return sym;
2179 }
2180
2181 /* Use a library function to move some bytes. */
2182
2183 static void
2184 block_move_call (rtx dest_reg, rtx src_reg, rtx bytes_rtx)
2185 {
2186 /* We want to pass the size as Pmode, which will normally be SImode
2187 but will be DImode if we are using 64 bit longs and pointers. */
2188 if (GET_MODE (bytes_rtx) != VOIDmode
2189 && GET_MODE (bytes_rtx) != Pmode)
2190 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2191
2192 emit_library_call (m32r_function_symbol ("memcpy"), 0,
2193 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
2194 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2195 TYPE_UNSIGNED (sizetype)),
2196 TYPE_MODE (sizetype));
2197 }
2198
2199 /* Expand string/block move operations.
2200
2201 operands[0] is the pointer to the destination.
2202 operands[1] is the pointer to the source.
2203 operands[2] is the number of bytes to move.
2204 operands[3] is the alignment.
2205
2206 Returns 1 upon success, 0 otherwise. */
2207
2208 int
2209 m32r_expand_block_move (rtx operands[])
2210 {
2211 rtx orig_dst = operands[0];
2212 rtx orig_src = operands[1];
2213 rtx bytes_rtx = operands[2];
2214 rtx align_rtx = operands[3];
2215 int constp = GET_CODE (bytes_rtx) == CONST_INT;
2216 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0;
2217 int align = INTVAL (align_rtx);
2218 int leftover;
2219 rtx src_reg;
2220 rtx dst_reg;
2221
2222 if (constp && bytes <= 0)
2223 return 1;
2224
2225 /* Move the address into scratch registers. */
2226 dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2227 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2228
2229 if (align > UNITS_PER_WORD)
2230 align = UNITS_PER_WORD;
2231
2232 /* If we prefer size over speed, always use a function call.
2233 If we do not know the size, use a function call.
2234 If the blocks are not word aligned, use a function call. */
2235 if (optimize_size || ! constp || align != UNITS_PER_WORD)
2236 {
2237 block_move_call (dst_reg, src_reg, bytes_rtx);
2238 return 0;
2239 }
2240
2241 leftover = bytes % MAX_MOVE_BYTES;
2242 bytes -= leftover;
2243
2244 /* If necessary, generate a loop to handle the bulk of the copy. */
2245 if (bytes)
2246 {
2247 rtx label = NULL_RTX;
2248 rtx final_src = NULL_RTX;
2249 rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2250 rtx rounded_total = GEN_INT (bytes);
2251 rtx new_dst_reg = gen_reg_rtx (SImode);
2252 rtx new_src_reg = gen_reg_rtx (SImode);
2253
2254 /* If we are going to have to perform this loop more than
2255 once, then generate a label and compute the address the
2256 source register will contain upon completion of the final
2257 iteration. */
2258 if (bytes > MAX_MOVE_BYTES)
2259 {
2260 final_src = gen_reg_rtx (Pmode);
2261
2262 if (INT16_P(bytes))
2263 emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
2264 else
2265 {
2266 emit_insn (gen_movsi (final_src, rounded_total));
2267 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2268 }
2269
2270 label = gen_label_rtx ();
2271 emit_label (label);
2272 }
2273
2274 /* It is known that output_block_move() will update src_reg to point
2275 to the word after the end of the source block, and dst_reg to point
2276 to the last word of the destination block, provided that the block
2277 is MAX_MOVE_BYTES long. */
2278 emit_insn (gen_movmemsi_internal (dst_reg, src_reg, at_a_time,
2279 new_dst_reg, new_src_reg));
2280 emit_move_insn (dst_reg, new_dst_reg);
2281 emit_move_insn (src_reg, new_src_reg);
2282 emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
2283
2284 if (bytes > MAX_MOVE_BYTES)
2285 {
2286 emit_insn (gen_cmpsi (src_reg, final_src));
2287 emit_jump_insn (gen_bne (label));
2288 }
2289 }
2290
2291 if (leftover)
2292 emit_insn (gen_movmemsi_internal (dst_reg, src_reg, GEN_INT (leftover),
2293 gen_reg_rtx (SImode),
2294 gen_reg_rtx (SImode)));
2295 return 1;
2296 }
2297
2298 \f
2299 /* Emit load/stores for a small constant word aligned block_move.
2300
2301 operands[0] is the memory address of the destination.
2302 operands[1] is the memory address of the source.
2303 operands[2] is the number of bytes to move.
2304 operands[3] is a temp register.
2305 operands[4] is a temp register. */
2306
2307 void
2308 m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[])
2309 {
2310 HOST_WIDE_INT bytes = INTVAL (operands[2]);
2311 int first_time;
2312 int got_extra = 0;
2313
2314 gcc_assert (bytes >= 1 && bytes <= MAX_MOVE_BYTES);
2315
2316 /* We do not have a post-increment store available, so the first set of
2317 stores are done without any increment, then the remaining ones can use
2318 the pre-increment addressing mode.
2319
2320 Note: expand_block_move() also relies upon this behavior when building
2321 loops to copy large blocks. */
2322 first_time = 1;
2323
2324 while (bytes > 0)
2325 {
2326 if (bytes >= 8)
2327 {
2328 if (first_time)
2329 {
2330 output_asm_insn ("ld\t%5, %p1", operands);
2331 output_asm_insn ("ld\t%6, %p1", operands);
2332 output_asm_insn ("st\t%5, @%0", operands);
2333 output_asm_insn ("st\t%6, %s0", operands);
2334 }
2335 else
2336 {
2337 output_asm_insn ("ld\t%5, %p1", operands);
2338 output_asm_insn ("ld\t%6, %p1", operands);
2339 output_asm_insn ("st\t%5, %s0", operands);
2340 output_asm_insn ("st\t%6, %s0", operands);
2341 }
2342
2343 bytes -= 8;
2344 }
2345 else if (bytes >= 4)
2346 {
2347 if (bytes > 4)
2348 got_extra = 1;
2349
2350 output_asm_insn ("ld\t%5, %p1", operands);
2351
2352 if (got_extra)
2353 output_asm_insn ("ld\t%6, %p1", operands);
2354
2355 if (first_time)
2356 output_asm_insn ("st\t%5, @%0", operands);
2357 else
2358 output_asm_insn ("st\t%5, %s0", operands);
2359
2360 bytes -= 4;
2361 }
2362 else
2363 {
2364 /* Get the entire next word, even though we do not want all of it.
2365 The saves us from doing several smaller loads, and we assume that
2366 we cannot cause a page fault when at least part of the word is in
2367 valid memory [since we don't get called if things aren't properly
2368 aligned]. */
2369 int dst_offset = first_time ? 0 : 4;
2370 /* The amount of increment we have to make to the
2371 destination pointer. */
2372 int dst_inc_amount = dst_offset + bytes - 4;
2373 /* The same for the source pointer. */
2374 int src_inc_amount = bytes;
2375 int last_shift;
2376 rtx my_operands[3];
2377
2378 /* If got_extra is true then we have already loaded
2379 the next word as part of loading and storing the previous word. */
2380 if (! got_extra)
2381 output_asm_insn ("ld\t%6, @%1", operands);
2382
2383 if (bytes >= 2)
2384 {
2385 bytes -= 2;
2386
2387 output_asm_insn ("sra3\t%5, %6, #16", operands);
2388 my_operands[0] = operands[5];
2389 my_operands[1] = GEN_INT (dst_offset);
2390 my_operands[2] = operands[0];
2391 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
2392
2393 /* If there is a byte left to store then increment the
2394 destination address and shift the contents of the source
2395 register down by 8 bits. We could not do the address
2396 increment in the store half word instruction, because it does
2397 not have an auto increment mode. */
2398 if (bytes > 0) /* assert (bytes == 1) */
2399 {
2400 dst_offset += 2;
2401 last_shift = 8;
2402 }
2403 }
2404 else
2405 last_shift = 24;
2406
2407 if (bytes > 0)
2408 {
2409 my_operands[0] = operands[6];
2410 my_operands[1] = GEN_INT (last_shift);
2411 output_asm_insn ("srai\t%0, #%1", my_operands);
2412 my_operands[0] = operands[6];
2413 my_operands[1] = GEN_INT (dst_offset);
2414 my_operands[2] = operands[0];
2415 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2416 }
2417
2418 /* Update the destination pointer if needed. We have to do
2419 this so that the patterns matches what we output in this
2420 function. */
2421 if (dst_inc_amount
2422 && !find_reg_note (insn, REG_UNUSED, operands[0]))
2423 {
2424 my_operands[0] = operands[0];
2425 my_operands[1] = GEN_INT (dst_inc_amount);
2426 output_asm_insn ("addi\t%0, #%1", my_operands);
2427 }
2428
2429 /* Update the source pointer if needed. We have to do this
2430 so that the patterns matches what we output in this
2431 function. */
2432 if (src_inc_amount
2433 && !find_reg_note (insn, REG_UNUSED, operands[1]))
2434 {
2435 my_operands[0] = operands[1];
2436 my_operands[1] = GEN_INT (src_inc_amount);
2437 output_asm_insn ("addi\t%0, #%1", my_operands);
2438 }
2439
2440 bytes = 0;
2441 }
2442
2443 first_time = 0;
2444 }
2445 }
2446
2447 /* Return true if using NEW_REG in place of OLD_REG is ok. */
2448
2449 int
2450 m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED,
2451 unsigned int new_reg)
2452 {
2453 /* Interrupt routines can't clobber any register that isn't already used. */
2454 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl))
2455 && !regs_ever_live[new_reg])
2456 return 0;
2457
2458 /* We currently emit epilogues as text, not rtl, so the liveness
2459 of the return address register isn't visible. */
2460 if (current_function_is_leaf && new_reg == RETURN_ADDR_REGNUM)
2461 return 0;
2462
2463 return 1;
2464 }
2465
2466 rtx
2467 m32r_return_addr (int count)
2468 {
2469 if (count != 0)
2470 return const0_rtx;
2471
2472 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM);
2473 }
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