2001-04-09 Andrew MacLeod <amacleod@redhat.com>
[official-gcc.git] / gcc / regclass.c
blobf65b2e9dd917ed0d3004e0de1c4bbdaa78a06fca
1 /* Compute register class preferences for pseudo-registers.
2 Copyright (C) 1987, 1988, 1991, 1992, 1993, 1994, 1995, 1996
3 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* This file contains two passes of the compiler: reg_scan and reg_class.
24 It also defines some tables of information about the hardware registers
25 and a function init_reg_sets to initialize the tables. */
27 #include "config.h"
28 #include "system.h"
29 #include "rtl.h"
30 #include "tm_p.h"
31 #include "hard-reg-set.h"
32 #include "flags.h"
33 #include "basic-block.h"
34 #include "regs.h"
35 #include "function.h"
36 #include "insn-config.h"
37 #include "recog.h"
38 #include "reload.h"
39 #include "real.h"
40 #include "toplev.h"
41 #include "output.h"
42 #include "ggc.h"
44 #ifndef REGISTER_MOVE_COST
45 #define REGISTER_MOVE_COST(m, x, y) 2
46 #endif
48 static void init_reg_sets_1 PARAMS ((void));
49 static void init_reg_modes PARAMS ((void));
51 /* If we have auto-increment or auto-decrement and we can have secondary
52 reloads, we are not allowed to use classes requiring secondary
53 reloads for pseudos auto-incremented since reload can't handle it. */
55 #ifdef AUTO_INC_DEC
56 #if defined(SECONDARY_INPUT_RELOAD_CLASS) || defined(SECONDARY_OUTPUT_RELOAD_CLASS)
57 #define FORBIDDEN_INC_DEC_CLASSES
58 #endif
59 #endif
61 /* Register tables used by many passes. */
63 /* Indexed by hard register number, contains 1 for registers
64 that are fixed use (stack pointer, pc, frame pointer, etc.).
65 These are the registers that cannot be used to allocate
66 a pseudo reg for general use. */
68 char fixed_regs[FIRST_PSEUDO_REGISTER];
70 /* Same info as a HARD_REG_SET. */
72 HARD_REG_SET fixed_reg_set;
74 /* Data for initializing the above. */
76 static char initial_fixed_regs[] = FIXED_REGISTERS;
78 /* Indexed by hard register number, contains 1 for registers
79 that are fixed use or are clobbered by function calls.
80 These are the registers that cannot be used to allocate
81 a pseudo reg whose life crosses calls unless we are able
82 to save/restore them across the calls. */
84 char call_used_regs[FIRST_PSEUDO_REGISTER];
86 /* Same info as a HARD_REG_SET. */
88 HARD_REG_SET call_used_reg_set;
90 /* HARD_REG_SET of registers we want to avoid caller saving. */
91 HARD_REG_SET losing_caller_save_reg_set;
93 /* Data for initializing the above. */
95 static char initial_call_used_regs[] = CALL_USED_REGISTERS;
97 /* Indexed by hard register number, contains 1 for registers that are
98 fixed use or call used registers that cannot hold quantities across
99 calls even if we are willing to save and restore them. call fixed
100 registers are a subset of call used registers. */
102 char call_fixed_regs[FIRST_PSEUDO_REGISTER];
104 /* The same info as a HARD_REG_SET. */
106 HARD_REG_SET call_fixed_reg_set;
108 /* Number of non-fixed registers. */
110 int n_non_fixed_regs;
112 /* Indexed by hard register number, contains 1 for registers
113 that are being used for global register decls.
114 These must be exempt from ordinary flow analysis
115 and are also considered fixed. */
117 char global_regs[FIRST_PSEUDO_REGISTER];
119 /* Table of register numbers in the order in which to try to use them. */
120 #ifdef REG_ALLOC_ORDER
121 int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER;
123 /* The inverse of reg_alloc_order. */
124 int inv_reg_alloc_order[FIRST_PSEUDO_REGISTER];
125 #endif
127 /* For each reg class, a HARD_REG_SET saying which registers are in it. */
129 HARD_REG_SET reg_class_contents[N_REG_CLASSES];
131 /* The same information, but as an array of unsigned ints. We copy from
132 these unsigned ints to the table above. We do this so the tm.h files
133 do not have to be aware of the wordsize for machines with <= 64 regs. */
135 #define N_REG_INTS \
136 ((FIRST_PSEUDO_REGISTER + (HOST_BITS_PER_INT - 1)) / HOST_BITS_PER_INT)
138 static unsigned int_reg_class_contents[N_REG_CLASSES][N_REG_INTS]
139 = REG_CLASS_CONTENTS;
141 /* For each reg class, number of regs it contains. */
143 unsigned int reg_class_size[N_REG_CLASSES];
145 /* For each reg class, table listing all the containing classes. */
147 enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES];
149 /* For each reg class, table listing all the classes contained in it. */
151 enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES];
153 /* For each pair of reg classes,
154 a largest reg class contained in their union. */
156 enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES];
158 /* For each pair of reg classes,
159 the smallest reg class containing their union. */
161 enum reg_class reg_class_superunion[N_REG_CLASSES][N_REG_CLASSES];
163 /* Array containing all of the register names. Unless
164 DEBUG_REGISTER_NAMES is defined, use the copy in print-rtl.c. */
166 #ifdef DEBUG_REGISTER_NAMES
167 const char * reg_names[] = REGISTER_NAMES;
168 #endif
170 /* For each hard register, the widest mode object that it can contain.
171 This will be a MODE_INT mode if the register can hold integers. Otherwise
172 it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
173 register. */
175 enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
177 /* 1 if class does contain register of given mode. */
179 static char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE];
181 /* Maximum cost of moving from a register in one class to a register in
182 another class. Based on REGISTER_MOVE_COST. */
184 static int move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
186 /* Similar, but here we don't have to move if the first index is a subset
187 of the second so in that case the cost is zero. */
189 static int may_move_in_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
191 /* Similar, but here we don't have to move if the first index is a superset
192 of the second so in that case the cost is zero. */
194 static int may_move_out_cost[MAX_MACHINE_MODE][N_REG_CLASSES][N_REG_CLASSES];
196 #ifdef FORBIDDEN_INC_DEC_CLASSES
198 /* These are the classes that regs which are auto-incremented or decremented
199 cannot be put in. */
201 static int forbidden_inc_dec_class[N_REG_CLASSES];
203 /* Indexed by n, is non-zero if (REG n) is used in an auto-inc or auto-dec
204 context. */
206 static char *in_inc_dec;
208 #endif /* FORBIDDEN_INC_DEC_CLASSES */
210 #ifdef CLASS_CANNOT_CHANGE_MODE
212 /* These are the classes containing only registers that can be used in
213 a SUBREG expression that changes the mode of the register in some
214 way that is illegal. */
216 static int class_can_change_mode[N_REG_CLASSES];
218 /* Registers, including pseudos, which change modes in some way that
219 is illegal. */
221 static regset reg_changes_mode;
223 #endif /* CLASS_CANNOT_CHANGE_MODE */
225 #ifdef HAVE_SECONDARY_RELOADS
227 /* Sample MEM values for use by memory_move_secondary_cost. */
229 static rtx top_of_stack[MAX_MACHINE_MODE];
231 #endif /* HAVE_SECONDARY_RELOADS */
233 /* Linked list of reg_info structures allocated for reg_n_info array.
234 Grouping all of the allocated structures together in one lump
235 means only one call to bzero to clear them, rather than n smaller
236 calls. */
237 struct reg_info_data {
238 struct reg_info_data *next; /* next set of reg_info structures */
239 size_t min_index; /* minimum index # */
240 size_t max_index; /* maximum index # */
241 char used_p; /* non-zero if this has been used previously */
242 reg_info data[1]; /* beginning of the reg_info data */
245 static struct reg_info_data *reg_info_head;
247 /* No more global register variables may be declared; true once
248 regclass has been initialized. */
250 static int no_global_reg_vars = 0;
253 /* Function called only once to initialize the above data on reg usage.
254 Once this is done, various switches may override. */
256 void
257 init_reg_sets ()
259 register int i, j;
261 /* First copy the register information from the initial int form into
262 the regsets. */
264 for (i = 0; i < N_REG_CLASSES; i++)
266 CLEAR_HARD_REG_SET (reg_class_contents[i]);
268 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
269 if (int_reg_class_contents[i][j / HOST_BITS_PER_INT]
270 & ((unsigned) 1 << (j % HOST_BITS_PER_INT)))
271 SET_HARD_REG_BIT (reg_class_contents[i], j);
274 memcpy (fixed_regs, initial_fixed_regs, sizeof fixed_regs);
275 memcpy (call_used_regs, initial_call_used_regs, sizeof call_used_regs);
276 memset (global_regs, 0, sizeof global_regs);
278 /* Do any additional initialization regsets may need */
279 INIT_ONCE_REG_SET ();
281 #ifdef REG_ALLOC_ORDER
282 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
283 inv_reg_alloc_order[reg_alloc_order[i]] = i;
284 #endif
287 /* After switches have been processed, which perhaps alter
288 `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */
290 static void
291 init_reg_sets_1 ()
293 register unsigned int i, j;
294 register unsigned int /* enum machine_mode */ m;
295 char allocatable_regs_of_mode [MAX_MACHINE_MODE];
297 /* This macro allows the fixed or call-used registers
298 and the register classes to depend on target flags. */
300 #ifdef CONDITIONAL_REGISTER_USAGE
301 CONDITIONAL_REGISTER_USAGE;
302 #endif
304 /* Compute number of hard regs in each class. */
306 memset ((char *) reg_class_size, 0, sizeof reg_class_size);
307 for (i = 0; i < N_REG_CLASSES; i++)
308 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
309 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
310 reg_class_size[i]++;
312 /* Initialize the table of subunions.
313 reg_class_subunion[I][J] gets the largest-numbered reg-class
314 that is contained in the union of classes I and J. */
316 for (i = 0; i < N_REG_CLASSES; i++)
318 for (j = 0; j < N_REG_CLASSES; j++)
320 #ifdef HARD_REG_SET
321 register /* Declare it register if it's a scalar. */
322 #endif
323 HARD_REG_SET c;
324 register int k;
326 COPY_HARD_REG_SET (c, reg_class_contents[i]);
327 IOR_HARD_REG_SET (c, reg_class_contents[j]);
328 for (k = 0; k < N_REG_CLASSES; k++)
330 GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c,
331 subclass1);
332 continue;
334 subclass1:
335 /* keep the largest subclass */ /* SPEE 900308 */
336 GO_IF_HARD_REG_SUBSET (reg_class_contents[k],
337 reg_class_contents[(int) reg_class_subunion[i][j]],
338 subclass2);
339 reg_class_subunion[i][j] = (enum reg_class) k;
340 subclass2:
346 /* Initialize the table of superunions.
347 reg_class_superunion[I][J] gets the smallest-numbered reg-class
348 containing the union of classes I and J. */
350 for (i = 0; i < N_REG_CLASSES; i++)
352 for (j = 0; j < N_REG_CLASSES; j++)
354 #ifdef HARD_REG_SET
355 register /* Declare it register if it's a scalar. */
356 #endif
357 HARD_REG_SET c;
358 register int k;
360 COPY_HARD_REG_SET (c, reg_class_contents[i]);
361 IOR_HARD_REG_SET (c, reg_class_contents[j]);
362 for (k = 0; k < N_REG_CLASSES; k++)
363 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[k], superclass);
365 superclass:
366 reg_class_superunion[i][j] = (enum reg_class) k;
370 /* Initialize the tables of subclasses and superclasses of each reg class.
371 First clear the whole table, then add the elements as they are found. */
373 for (i = 0; i < N_REG_CLASSES; i++)
375 for (j = 0; j < N_REG_CLASSES; j++)
377 reg_class_superclasses[i][j] = LIM_REG_CLASSES;
378 reg_class_subclasses[i][j] = LIM_REG_CLASSES;
382 for (i = 0; i < N_REG_CLASSES; i++)
384 if (i == (int) NO_REGS)
385 continue;
387 for (j = i + 1; j < N_REG_CLASSES; j++)
389 enum reg_class *p;
391 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j],
392 subclass);
393 continue;
394 subclass:
395 /* Reg class I is a subclass of J.
396 Add J to the table of superclasses of I. */
397 p = &reg_class_superclasses[i][0];
398 while (*p != LIM_REG_CLASSES) p++;
399 *p = (enum reg_class) j;
400 /* Add I to the table of superclasses of J. */
401 p = &reg_class_subclasses[j][0];
402 while (*p != LIM_REG_CLASSES) p++;
403 *p = (enum reg_class) i;
407 /* Initialize "constant" tables. */
409 CLEAR_HARD_REG_SET (fixed_reg_set);
410 CLEAR_HARD_REG_SET (call_used_reg_set);
411 CLEAR_HARD_REG_SET (call_fixed_reg_set);
413 memcpy (call_fixed_regs, fixed_regs, sizeof call_fixed_regs);
415 n_non_fixed_regs = 0;
417 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
419 if (fixed_regs[i])
420 SET_HARD_REG_BIT (fixed_reg_set, i);
421 else
422 n_non_fixed_regs++;
424 if (call_used_regs[i])
425 SET_HARD_REG_BIT (call_used_reg_set, i);
426 if (call_fixed_regs[i])
427 SET_HARD_REG_BIT (call_fixed_reg_set, i);
428 if (CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (i)))
429 SET_HARD_REG_BIT (losing_caller_save_reg_set, i);
431 memset (contains_reg_of_mode, 0, sizeof (contains_reg_of_mode));
432 memset (allocatable_regs_of_mode, 0, sizeof (allocatable_regs_of_mode));
433 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++)
434 for (i = 0; i < N_REG_CLASSES; i++)
435 if (CLASS_MAX_NREGS (i, m) <= reg_class_size[i])
436 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
437 if (!fixed_regs [j] && TEST_HARD_REG_BIT (reg_class_contents[i], j)
438 && HARD_REGNO_MODE_OK (j, m))
440 contains_reg_of_mode [i][m] = 1;
441 allocatable_regs_of_mode [m] = 1;
442 break;
445 /* Initialize the move cost table. Find every subset of each class
446 and take the maximum cost of moving any subset to any other. */
448 for (m = 0; m < (unsigned int) MAX_MACHINE_MODE; m++)
449 if (allocatable_regs_of_mode [m])
451 for (i = 0; i < N_REG_CLASSES; i++)
452 if (contains_reg_of_mode [i][m])
453 for (j = 0; j < N_REG_CLASSES; j++)
455 int cost;
456 enum reg_class *p1, *p2;
458 if (!contains_reg_of_mode [j][m])
460 move_cost[m][i][j] = 65536;
461 may_move_in_cost[m][i][j] = 65536;
462 may_move_out_cost[m][i][j] = 65536;
464 else
466 cost = i == j ? 2 : REGISTER_MOVE_COST (m, i, j);
468 for (p2 = &reg_class_subclasses[j][0];
469 *p2 != LIM_REG_CLASSES;
470 p2++)
471 if (*p2 != i && contains_reg_of_mode [*p2][m])
472 cost = MAX (cost, move_cost [m][i][*p2]);
474 for (p1 = &reg_class_subclasses[i][0];
475 *p1 != LIM_REG_CLASSES;
476 p1++)
477 if (*p1 != j && contains_reg_of_mode [*p1][m])
478 cost = MAX (cost, move_cost [m][*p1][j]);
480 move_cost[m][i][j] = cost;
482 if (reg_class_subset_p (i, j))
483 may_move_in_cost[m][i][j] = 0;
484 else
485 may_move_in_cost[m][i][j] = cost;
487 if (reg_class_subset_p (j, i))
488 may_move_out_cost[m][i][j] = 0;
489 else
490 may_move_out_cost[m][i][j] = cost;
493 else
494 for (j = 0; j < N_REG_CLASSES; j++)
496 move_cost[m][i][j] = 65536;
497 may_move_in_cost[m][i][j] = 65536;
498 may_move_out_cost[m][i][j] = 65536;
502 #ifdef CLASS_CANNOT_CHANGE_MODE
504 HARD_REG_SET c;
505 COMPL_HARD_REG_SET (c, reg_class_contents[CLASS_CANNOT_CHANGE_MODE]);
507 for (i = 0; i < N_REG_CLASSES; i++)
509 GO_IF_HARD_REG_SUBSET (reg_class_contents[i], c, ok_class);
510 class_can_change_mode [i] = 0;
511 continue;
512 ok_class:
513 class_can_change_mode [i] = 1;
516 #endif /* CLASS_CANNOT_CHANGE_MODE */
519 /* Compute the table of register modes.
520 These values are used to record death information for individual registers
521 (as opposed to a multi-register mode). */
523 static void
524 init_reg_modes ()
526 register int i;
528 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
530 reg_raw_mode[i] = choose_hard_reg_mode (i, 1);
532 /* If we couldn't find a valid mode, just use the previous mode.
533 ??? One situation in which we need to do this is on the mips where
534 HARD_REGNO_NREGS (fpreg, [SD]Fmode) returns 2. Ideally we'd like
535 to use DF mode for the even registers and VOIDmode for the odd
536 (for the cpu models where the odd ones are inaccessible). */
537 if (reg_raw_mode[i] == VOIDmode)
538 reg_raw_mode[i] = i == 0 ? word_mode : reg_raw_mode[i-1];
542 /* Finish initializing the register sets and
543 initialize the register modes. */
545 void
546 init_regs ()
548 /* This finishes what was started by init_reg_sets, but couldn't be done
549 until after register usage was specified. */
550 init_reg_sets_1 ();
552 init_reg_modes ();
554 #ifdef HAVE_SECONDARY_RELOADS
556 /* Make some fake stack-frame MEM references for use in
557 memory_move_secondary_cost. */
558 int i;
560 for (i = 0; i < MAX_MACHINE_MODE; i++)
561 top_of_stack[i] = gen_rtx_MEM (i, stack_pointer_rtx);
562 ggc_add_rtx_root (top_of_stack, MAX_MACHINE_MODE);
564 #endif
567 #ifdef HAVE_SECONDARY_RELOADS
569 /* Compute extra cost of moving registers to/from memory due to reloads.
570 Only needed if secondary reloads are required for memory moves. */
573 memory_move_secondary_cost (mode, class, in)
574 enum machine_mode mode;
575 enum reg_class class;
576 int in;
578 enum reg_class altclass;
579 int partial_cost = 0;
580 /* We need a memory reference to feed to SECONDARY... macros. */
581 /* mem may be unused even if the SECONDARY_ macros are defined. */
582 rtx mem ATTRIBUTE_UNUSED = top_of_stack[(int) mode];
585 if (in)
587 #ifdef SECONDARY_INPUT_RELOAD_CLASS
588 altclass = SECONDARY_INPUT_RELOAD_CLASS (class, mode, mem);
589 #else
590 altclass = NO_REGS;
591 #endif
593 else
595 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
596 altclass = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, mem);
597 #else
598 altclass = NO_REGS;
599 #endif
602 if (altclass == NO_REGS)
603 return 0;
605 if (in)
606 partial_cost = REGISTER_MOVE_COST (mode, altclass, class);
607 else
608 partial_cost = REGISTER_MOVE_COST (mode, class, altclass);
610 if (class == altclass)
611 /* This isn't simply a copy-to-temporary situation. Can't guess
612 what it is, so MEMORY_MOVE_COST really ought not to be calling
613 here in that case.
615 I'm tempted to put in an abort here, but returning this will
616 probably only give poor estimates, which is what we would've
617 had before this code anyways. */
618 return partial_cost;
620 /* Check if the secondary reload register will also need a
621 secondary reload. */
622 return memory_move_secondary_cost (mode, altclass, in) + partial_cost;
624 #endif
626 /* Return a machine mode that is legitimate for hard reg REGNO and large
627 enough to save nregs. If we can't find one, return VOIDmode. */
629 enum machine_mode
630 choose_hard_reg_mode (regno, nregs)
631 unsigned int regno ATTRIBUTE_UNUSED;
632 unsigned int nregs;
634 unsigned int /* enum machine_mode */ m;
635 enum machine_mode found_mode = VOIDmode, mode;
637 /* We first look for the largest integer mode that can be validly
638 held in REGNO. If none, we look for the largest floating-point mode.
639 If we still didn't find a valid mode, try CCmode. */
641 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT);
642 mode != VOIDmode;
643 mode = GET_MODE_WIDER_MODE (mode))
644 if (HARD_REGNO_NREGS (regno, mode) == nregs
645 && HARD_REGNO_MODE_OK (regno, mode))
646 found_mode = mode;
648 if (found_mode != VOIDmode)
649 return found_mode;
651 for (mode = GET_CLASS_NARROWEST_MODE (MODE_FLOAT);
652 mode != VOIDmode;
653 mode = GET_MODE_WIDER_MODE (mode))
654 if (HARD_REGNO_NREGS (regno, mode) == nregs
655 && HARD_REGNO_MODE_OK (regno, mode))
656 found_mode = mode;
658 if (found_mode != VOIDmode)
659 return found_mode;
661 /* Iterate over all of the CCmodes. */
662 for (m = (unsigned int) CCmode; m < (unsigned int) NUM_MACHINE_MODES; ++m)
664 mode = (enum machine_mode) m;
665 if (HARD_REGNO_NREGS (regno, mode) == nregs
666 && HARD_REGNO_MODE_OK (regno, mode))
667 return mode;
670 /* We can't find a mode valid for this register. */
671 return VOIDmode;
674 /* Specify the usage characteristics of the register named NAME.
675 It should be a fixed register if FIXED and a
676 call-used register if CALL_USED. */
678 void
679 fix_register (name, fixed, call_used)
680 const char *name;
681 int fixed, call_used;
683 int i;
685 /* Decode the name and update the primary form of
686 the register info. */
688 if ((i = decode_reg_name (name)) >= 0)
690 if ((i == STACK_POINTER_REGNUM
691 #ifdef HARD_FRAME_POINTER_REGNUM
692 || i == HARD_FRAME_POINTER_REGNUM
693 #else
694 || i == FRAME_POINTER_REGNUM
695 #endif
697 && (fixed == 0 || call_used == 0))
699 static const char * const what_option[2][2] = {
700 { "call-saved", "call-used" },
701 { "no-such-option", "fixed" }};
703 error ("can't use '%s' as a %s register", name,
704 what_option[fixed][call_used]);
706 else
708 fixed_regs[i] = fixed;
709 call_used_regs[i] = call_used;
712 else
714 warning ("unknown register name: %s", name);
718 /* Mark register number I as global. */
720 void
721 globalize_reg (i)
722 int i;
724 if (fixed_regs[i] == 0 && no_global_reg_vars)
725 error ("global register variable follows a function definition");
727 if (global_regs[i])
729 warning ("register used for two global register variables");
730 return;
733 if (call_used_regs[i] && ! fixed_regs[i])
734 warning ("call-clobbered register used for global register variable");
736 global_regs[i] = 1;
738 /* If already fixed, nothing else to do. */
739 if (fixed_regs[i])
740 return;
742 fixed_regs[i] = call_used_regs[i] = call_fixed_regs[i] = 1;
743 n_non_fixed_regs--;
745 SET_HARD_REG_BIT (fixed_reg_set, i);
746 SET_HARD_REG_BIT (call_used_reg_set, i);
747 SET_HARD_REG_BIT (call_fixed_reg_set, i);
750 /* Now the data and code for the `regclass' pass, which happens
751 just before local-alloc. */
753 /* The `costs' struct records the cost of using a hard register of each class
754 and of using memory for each pseudo. We use this data to set up
755 register class preferences. */
757 struct costs
759 int cost[N_REG_CLASSES];
760 int mem_cost;
763 /* Structure used to record preferrences of given pseudo. */
764 struct reg_pref
766 /* (enum reg_class) prefclass is the preferred class. */
767 char prefclass;
769 /* altclass is a register class that we should use for allocating
770 pseudo if no register in the preferred class is available.
771 If no register in this class is available, memory is preferred.
773 It might appear to be more general to have a bitmask of classes here,
774 but since it is recommended that there be a class corresponding to the
775 union of most major pair of classes, that generality is not required. */
776 char altclass;
779 /* Record the cost of each class for each pseudo. */
781 static struct costs *costs;
783 /* Initialized once, and used to initialize cost values for each insn. */
785 static struct costs init_cost;
787 /* Record preferrences of each pseudo.
788 This is available after `regclass' is run. */
790 static struct reg_pref *reg_pref;
792 /* Allocated buffers for reg_pref. */
794 static struct reg_pref *reg_pref_buffer;
796 /* Account for the fact that insns within a loop are executed very commonly,
797 but don't keep doing this as loops go too deep. */
799 static int loop_cost;
801 static rtx scan_one_insn PARAMS ((rtx, int));
802 static void record_operand_costs PARAMS ((rtx, struct costs *, struct reg_pref *));
803 static void dump_regclass PARAMS ((FILE *));
804 static void record_reg_classes PARAMS ((int, int, rtx *, enum machine_mode *,
805 const char **, rtx,
806 struct costs *, struct reg_pref *));
807 static int copy_cost PARAMS ((rtx, enum machine_mode,
808 enum reg_class, int));
809 static void record_address_regs PARAMS ((rtx, enum reg_class, int));
810 #ifdef FORBIDDEN_INC_DEC_CLASSES
811 static int auto_inc_dec_reg_p PARAMS ((rtx, enum machine_mode));
812 #endif
813 static void reg_scan_mark_refs PARAMS ((rtx, rtx, int, unsigned int));
815 /* Return the reg_class in which pseudo reg number REGNO is best allocated.
816 This function is sometimes called before the info has been computed.
817 When that happens, just return GENERAL_REGS, which is innocuous. */
819 enum reg_class
820 reg_preferred_class (regno)
821 int regno;
823 if (reg_pref == 0)
824 return GENERAL_REGS;
825 return (enum reg_class) reg_pref[regno].prefclass;
828 enum reg_class
829 reg_alternate_class (regno)
830 int regno;
832 if (reg_pref == 0)
833 return ALL_REGS;
835 return (enum reg_class) reg_pref[regno].altclass;
838 /* Initialize some global data for this pass. */
840 void
841 regclass_init ()
843 int i;
845 init_cost.mem_cost = 10000;
846 for (i = 0; i < N_REG_CLASSES; i++)
847 init_cost.cost[i] = 10000;
849 /* This prevents dump_flow_info from losing if called
850 before regclass is run. */
851 reg_pref = NULL;
853 /* No more global register variables may be declared. */
854 no_global_reg_vars = 1;
857 /* Dump register costs. */
858 static void
859 dump_regclass (dump)
860 FILE *dump;
862 static const char *const reg_class_names[] = REG_CLASS_NAMES;
863 int i;
864 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
866 int /* enum reg_class */ class;
867 if (REG_N_REFS (i))
869 fprintf (dump, " Register %i costs:", i);
870 for (class = 0; class < (int) N_REG_CLASSES; class++)
871 if (contains_reg_of_mode [(enum reg_class) class][PSEUDO_REGNO_MODE (i)]
872 #ifdef FORBIDDEN_INC_DEC_CLASSES
873 && (!in_inc_dec[i]
874 || !forbidden_inc_dec_class[(enum reg_class) class])
875 #endif
876 #ifdef CLASS_CANNOT_CHANGE_MODE
877 && (!REGNO_REG_SET_P (reg_changes_mode, i)
878 || class_can_change_mode [(enum reg_class) class])
879 #endif
881 fprintf (dump, " %s:%i", reg_class_names[class],
882 costs[i].cost[(enum reg_class) class]);
883 fprintf (dump, " MEM:%i\n", costs[i].mem_cost);
889 /* Calculate the costs of insn operands. */
891 static void
892 record_operand_costs (insn, op_costs, reg_pref)
893 rtx insn;
894 struct costs *op_costs;
895 struct reg_pref *reg_pref;
897 const char *constraints[MAX_RECOG_OPERANDS];
898 enum machine_mode modes[MAX_RECOG_OPERANDS];
899 int i;
901 for (i = 0; i < recog_data.n_operands; i++)
903 constraints[i] = recog_data.constraints[i];
904 modes[i] = recog_data.operand_mode[i];
907 /* If we get here, we are set up to record the costs of all the
908 operands for this insn. Start by initializing the costs.
909 Then handle any address registers. Finally record the desired
910 classes for any pseudos, doing it twice if some pair of
911 operands are commutative. */
913 for (i = 0; i < recog_data.n_operands; i++)
915 op_costs[i] = init_cost;
917 if (GET_CODE (recog_data.operand[i]) == SUBREG)
919 rtx inner = SUBREG_REG (recog_data.operand[i]);
920 #ifdef CLASS_CANNOT_CHANGE_MODE
921 if (GET_CODE (inner) == REG
922 && CLASS_CANNOT_CHANGE_MODE_P (modes[i], GET_MODE (inner)))
923 SET_REGNO_REG_SET (reg_changes_mode, REGNO (inner));
924 #endif
925 recog_data.operand[i] = inner;
928 if (GET_CODE (recog_data.operand[i]) == MEM)
929 record_address_regs (XEXP (recog_data.operand[i], 0),
930 BASE_REG_CLASS, loop_cost * 2);
931 else if (constraints[i][0] == 'p')
932 record_address_regs (recog_data.operand[i],
933 BASE_REG_CLASS, loop_cost * 2);
936 /* Check for commutative in a separate loop so everything will
937 have been initialized. We must do this even if one operand
938 is a constant--see addsi3 in m68k.md. */
940 for (i = 0; i < (int) recog_data.n_operands - 1; i++)
941 if (constraints[i][0] == '%')
943 const char *xconstraints[MAX_RECOG_OPERANDS];
944 int j;
946 /* Handle commutative operands by swapping the constraints.
947 We assume the modes are the same. */
949 for (j = 0; j < recog_data.n_operands; j++)
950 xconstraints[j] = constraints[j];
952 xconstraints[i] = constraints[i+1];
953 xconstraints[i+1] = constraints[i];
954 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
955 recog_data.operand, modes,
956 xconstraints, insn, op_costs, reg_pref);
959 record_reg_classes (recog_data.n_alternatives, recog_data.n_operands,
960 recog_data.operand, modes,
961 constraints, insn, op_costs, reg_pref);
964 /* Subroutine of regclass, processes one insn INSN. Scan it and record each
965 time it would save code to put a certain register in a certain class.
966 PASS, when nonzero, inhibits some optimizations which need only be done
967 once.
968 Return the last insn processed, so that the scan can be continued from
969 there. */
971 static rtx
972 scan_one_insn (insn, pass)
973 rtx insn;
974 int pass;
976 enum rtx_code code = GET_CODE (insn);
977 enum rtx_code pat_code;
978 rtx set, note;
979 int i, j;
980 struct costs op_costs[MAX_RECOG_OPERANDS];
982 if (GET_RTX_CLASS (code) != 'i')
983 return insn;
985 pat_code = GET_CODE (PATTERN (insn));
986 if (pat_code == USE
987 || pat_code == CLOBBER
988 || pat_code == ASM_INPUT
989 || pat_code == ADDR_VEC
990 || pat_code == ADDR_DIFF_VEC)
991 return insn;
993 set = single_set (insn);
994 extract_insn (insn);
996 /* If this insn loads a parameter from its stack slot, then
997 it represents a savings, rather than a cost, if the
998 parameter is stored in memory. Record this fact. */
1000 if (set != 0 && GET_CODE (SET_DEST (set)) == REG
1001 && GET_CODE (SET_SRC (set)) == MEM
1002 && (note = find_reg_note (insn, REG_EQUIV,
1003 NULL_RTX)) != 0
1004 && GET_CODE (XEXP (note, 0)) == MEM)
1006 costs[REGNO (SET_DEST (set))].mem_cost
1007 -= (MEMORY_MOVE_COST (GET_MODE (SET_DEST (set)),
1008 GENERAL_REGS, 1)
1009 * loop_cost);
1010 record_address_regs (XEXP (SET_SRC (set), 0),
1011 BASE_REG_CLASS, loop_cost * 2);
1012 return insn;
1015 /* Improve handling of two-address insns such as
1016 (set X (ashift CONST Y)) where CONST must be made to
1017 match X. Change it into two insns: (set X CONST)
1018 (set X (ashift X Y)). If we left this for reloading, it
1019 would probably get three insns because X and Y might go
1020 in the same place. This prevents X and Y from receiving
1021 the same hard reg.
1023 We can only do this if the modes of operands 0 and 1
1024 (which might not be the same) are tieable and we only need
1025 do this during our first pass. */
1027 if (pass == 0 && optimize
1028 && recog_data.n_operands >= 3
1029 && recog_data.constraints[1][0] == '0'
1030 && recog_data.constraints[1][1] == 0
1031 && CONSTANT_P (recog_data.operand[1])
1032 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[1])
1033 && ! rtx_equal_p (recog_data.operand[0], recog_data.operand[2])
1034 && GET_CODE (recog_data.operand[0]) == REG
1035 && MODES_TIEABLE_P (GET_MODE (recog_data.operand[0]),
1036 recog_data.operand_mode[1]))
1038 rtx previnsn = prev_real_insn (insn);
1039 rtx dest
1040 = gen_lowpart (recog_data.operand_mode[1],
1041 recog_data.operand[0]);
1042 rtx newinsn
1043 = emit_insn_before (gen_move_insn (dest, recog_data.operand[1]), insn);
1045 /* If this insn was the start of a basic block,
1046 include the new insn in that block.
1047 We need not check for code_label here;
1048 while a basic block can start with a code_label,
1049 INSN could not be at the beginning of that block. */
1050 if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN)
1052 int b;
1053 for (b = 0; b < n_basic_blocks; b++)
1054 if (insn == BLOCK_HEAD (b))
1055 BLOCK_HEAD (b) = newinsn;
1058 /* This makes one more setting of new insns's dest. */
1059 REG_N_SETS (REGNO (recog_data.operand[0]))++;
1061 *recog_data.operand_loc[1] = recog_data.operand[0];
1062 for (i = recog_data.n_dups - 1; i >= 0; i--)
1063 if (recog_data.dup_num[i] == 1)
1064 *recog_data.dup_loc[i] = recog_data.operand[0];
1066 return PREV_INSN (newinsn);
1069 record_operand_costs (insn, op_costs, reg_pref);
1071 /* Now add the cost for each operand to the total costs for
1072 its register. */
1074 for (i = 0; i < recog_data.n_operands; i++)
1075 if (GET_CODE (recog_data.operand[i]) == REG
1076 && REGNO (recog_data.operand[i]) >= FIRST_PSEUDO_REGISTER)
1078 int regno = REGNO (recog_data.operand[i]);
1079 struct costs *p = &costs[regno], *q = &op_costs[i];
1081 p->mem_cost += q->mem_cost * loop_cost;
1082 for (j = 0; j < N_REG_CLASSES; j++)
1083 p->cost[j] += q->cost[j] * loop_cost;
1086 return insn;
1089 /* This is a pass of the compiler that scans all instructions
1090 and calculates the preferred class for each pseudo-register.
1091 This information can be accessed later by calling `reg_preferred_class'.
1092 This pass comes just before local register allocation. */
1094 void
1095 regclass (f, nregs, dump)
1096 rtx f;
1097 int nregs;
1098 FILE *dump;
1100 register rtx insn;
1101 register int i;
1102 int pass;
1104 init_recog ();
1106 costs = (struct costs *) xmalloc (nregs * sizeof (struct costs));
1108 #ifdef CLASS_CANNOT_CHANGE_MODE
1109 reg_changes_mode = BITMAP_XMALLOC();
1110 #endif
1112 #ifdef FORBIDDEN_INC_DEC_CLASSES
1114 in_inc_dec = (char *) xmalloc (nregs);
1116 /* Initialize information about which register classes can be used for
1117 pseudos that are auto-incremented or auto-decremented. It would
1118 seem better to put this in init_reg_sets, but we need to be able
1119 to allocate rtx, which we can't do that early. */
1121 for (i = 0; i < N_REG_CLASSES; i++)
1123 rtx r = gen_rtx_REG (VOIDmode, 0);
1124 enum machine_mode m;
1125 register int j;
1127 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++)
1128 if (TEST_HARD_REG_BIT (reg_class_contents[i], j))
1130 REGNO (r) = j;
1132 for (m = VOIDmode; (int) m < (int) MAX_MACHINE_MODE;
1133 m = (enum machine_mode) ((int) m + 1))
1134 if (HARD_REGNO_MODE_OK (j, m))
1136 PUT_MODE (r, m);
1138 /* If a register is not directly suitable for an
1139 auto-increment or decrement addressing mode and
1140 requires secondary reloads, disallow its class from
1141 being used in such addresses. */
1143 if ((0
1144 #ifdef SECONDARY_RELOAD_CLASS
1145 || (SECONDARY_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1146 != NO_REGS)
1147 #else
1148 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1149 || (SECONDARY_INPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1150 != NO_REGS)
1151 #endif
1152 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1153 || (SECONDARY_OUTPUT_RELOAD_CLASS (BASE_REG_CLASS, m, r)
1154 != NO_REGS)
1155 #endif
1156 #endif
1158 && ! auto_inc_dec_reg_p (r, m))
1159 forbidden_inc_dec_class[i] = 1;
1163 #endif /* FORBIDDEN_INC_DEC_CLASSES */
1165 /* Normally we scan the insns once and determine the best class to use for
1166 each register. However, if -fexpensive_optimizations are on, we do so
1167 twice, the second time using the tentative best classes to guide the
1168 selection. */
1170 for (pass = 0; pass <= flag_expensive_optimizations; pass++)
1172 int index;
1174 if (dump)
1175 fprintf (dump, "\n\nPass %i\n\n",pass);
1176 /* Zero out our accumulation of the cost of each class for each reg. */
1178 memset ((char *) costs, 0, nregs * sizeof (struct costs));
1180 #ifdef FORBIDDEN_INC_DEC_CLASSES
1181 memset (in_inc_dec, 0, nregs);
1182 #endif
1184 /* Scan the instructions and record each time it would
1185 save code to put a certain register in a certain class. */
1187 if (!optimize)
1189 loop_cost = 1;
1190 for (insn = f; insn; insn = NEXT_INSN (insn))
1191 insn = scan_one_insn (insn, pass);
1193 else
1194 for (index = 0; index < n_basic_blocks; index++)
1196 basic_block bb = BASIC_BLOCK (index);
1198 /* Show that an insn inside a loop is likely to be executed three
1199 times more than insns outside a loop. This is much more
1200 aggressive than the assumptions made elsewhere and is being
1201 tried as an experiment. */
1202 if (optimize_size)
1203 loop_cost = 1;
1204 else
1205 loop_cost = 1 << (2 * MIN (bb->loop_depth, 5));
1206 for (insn = bb->head; ; insn = NEXT_INSN (insn))
1208 insn = scan_one_insn (insn, pass);
1209 if (insn == bb->end)
1210 break;
1214 /* Now for each register look at how desirable each class is
1215 and find which class is preferred. Store that in
1216 `prefclass'. Record in `altclass' the largest register
1217 class any of whose registers is better than memory. */
1219 if (pass == 0)
1220 reg_pref = reg_pref_buffer;
1222 if (dump)
1224 dump_regclass (dump);
1225 fprintf (dump,"\n");
1227 for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++)
1229 register int best_cost = (1 << (HOST_BITS_PER_INT - 2)) - 1;
1230 enum reg_class best = ALL_REGS, alt = NO_REGS;
1231 /* This is an enum reg_class, but we call it an int
1232 to save lots of casts. */
1233 register int class;
1234 register struct costs *p = &costs[i];
1236 /* In non-optimizing compilation REG_N_REFS is not initialized
1237 yet. */
1238 if (optimize && !REG_N_REFS (i))
1239 continue;
1241 for (class = (int) ALL_REGS - 1; class > 0; class--)
1243 /* Ignore classes that are too small for this operand or
1244 invalid for a operand that was auto-incremented. */
1245 if (!contains_reg_of_mode [class][PSEUDO_REGNO_MODE (i)]
1246 #ifdef FORBIDDEN_INC_DEC_CLASSES
1247 || (in_inc_dec[i] && forbidden_inc_dec_class[class])
1248 #endif
1249 #ifdef CLASS_CANNOT_CHANGE_MODE
1250 || (REGNO_REG_SET_P (reg_changes_mode, i)
1251 && ! class_can_change_mode [class])
1252 #endif
1255 else if (p->cost[class] < best_cost)
1257 best_cost = p->cost[class];
1258 best = (enum reg_class) class;
1260 else if (p->cost[class] == best_cost)
1261 best = reg_class_subunion[(int)best][class];
1264 /* Record the alternate register class; i.e., a class for which
1265 every register in it is better than using memory. If adding a
1266 class would make a smaller class (i.e., no union of just those
1267 classes exists), skip that class. The major unions of classes
1268 should be provided as a register class. Don't do this if we
1269 will be doing it again later. */
1271 if ((pass == 1 || dump) || ! flag_expensive_optimizations)
1272 for (class = 0; class < N_REG_CLASSES; class++)
1273 if (p->cost[class] < p->mem_cost
1274 && (reg_class_size[(int) reg_class_subunion[(int) alt][class]]
1275 > reg_class_size[(int) alt])
1276 #ifdef FORBIDDEN_INC_DEC_CLASSES
1277 && ! (in_inc_dec[i] && forbidden_inc_dec_class[class])
1278 #endif
1279 #ifdef CLASS_CANNOT_CHANGE_MODE
1280 && ! (REGNO_REG_SET_P (reg_changes_mode, i)
1281 && ! class_can_change_mode [class])
1282 #endif
1284 alt = reg_class_subunion[(int) alt][class];
1286 /* If we don't add any classes, nothing to try. */
1287 if (alt == best)
1288 alt = NO_REGS;
1290 if (dump
1291 && (reg_pref[i].prefclass != (int) best
1292 || reg_pref[i].altclass != (int) alt))
1294 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1295 fprintf (dump, " Register %i", i);
1296 if (alt == ALL_REGS || best == ALL_REGS)
1297 fprintf (dump, " pref %s\n", reg_class_names[(int) best]);
1298 else if (alt == NO_REGS)
1299 fprintf (dump, " pref %s or none\n", reg_class_names[(int) best]);
1300 else
1301 fprintf (dump, " pref %s, else %s\n",
1302 reg_class_names[(int) best],
1303 reg_class_names[(int) alt]);
1306 /* We cast to (int) because (char) hits bugs in some compilers. */
1307 reg_pref[i].prefclass = (int) best;
1308 reg_pref[i].altclass = (int) alt;
1312 #ifdef FORBIDDEN_INC_DEC_CLASSES
1313 free (in_inc_dec);
1314 #endif
1315 #ifdef CLASS_CANNOT_CHANGE_MODE
1316 BITMAP_XFREE (reg_changes_mode);
1317 #endif
1318 free (costs);
1321 /* Record the cost of using memory or registers of various classes for
1322 the operands in INSN.
1324 N_ALTS is the number of alternatives.
1326 N_OPS is the number of operands.
1328 OPS is an array of the operands.
1330 MODES are the modes of the operands, in case any are VOIDmode.
1332 CONSTRAINTS are the constraints to use for the operands. This array
1333 is modified by this procedure.
1335 This procedure works alternative by alternative. For each alternative
1336 we assume that we will be able to allocate all pseudos to their ideal
1337 register class and calculate the cost of using that alternative. Then
1338 we compute for each operand that is a pseudo-register, the cost of
1339 having the pseudo allocated to each register class and using it in that
1340 alternative. To this cost is added the cost of the alternative.
1342 The cost of each class for this insn is its lowest cost among all the
1343 alternatives. */
1345 static void
1346 record_reg_classes (n_alts, n_ops, ops, modes,
1347 constraints, insn, op_costs, reg_pref)
1348 int n_alts;
1349 int n_ops;
1350 rtx *ops;
1351 enum machine_mode *modes;
1352 const char **constraints;
1353 rtx insn;
1354 struct costs *op_costs;
1355 struct reg_pref *reg_pref;
1357 int alt;
1358 int i, j;
1359 rtx set;
1361 /* Process each alternative, each time minimizing an operand's cost with
1362 the cost for each operand in that alternative. */
1364 for (alt = 0; alt < n_alts; alt++)
1366 struct costs this_op_costs[MAX_RECOG_OPERANDS];
1367 int alt_fail = 0;
1368 int alt_cost = 0;
1369 enum reg_class classes[MAX_RECOG_OPERANDS];
1370 int allows_mem[MAX_RECOG_OPERANDS];
1371 int class;
1373 for (i = 0; i < n_ops; i++)
1375 const char *p = constraints[i];
1376 rtx op = ops[i];
1377 enum machine_mode mode = modes[i];
1378 int allows_addr = 0;
1379 int win = 0;
1380 unsigned char c;
1382 /* Initially show we know nothing about the register class. */
1383 classes[i] = NO_REGS;
1384 allows_mem[i] = 0;
1386 /* If this operand has no constraints at all, we can conclude
1387 nothing about it since anything is valid. */
1389 if (*p == 0)
1391 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1392 memset ((char *) &this_op_costs[i], 0, sizeof this_op_costs[i]);
1394 continue;
1397 /* If this alternative is only relevant when this operand
1398 matches a previous operand, we do different things depending
1399 on whether this operand is a pseudo-reg or not. We must process
1400 any modifiers for the operand before we can make this test. */
1402 while (*p == '%' || *p == '=' || *p == '+' || *p == '&')
1403 p++;
1405 if (p[0] >= '0' && p[0] <= '0' + i && (p[1] == ',' || p[1] == 0))
1407 /* Copy class and whether memory is allowed from the matching
1408 alternative. Then perform any needed cost computations
1409 and/or adjustments. */
1410 j = p[0] - '0';
1411 classes[i] = classes[j];
1412 allows_mem[i] = allows_mem[j];
1414 if (GET_CODE (op) != REG || REGNO (op) < FIRST_PSEUDO_REGISTER)
1416 /* If this matches the other operand, we have no added
1417 cost and we win. */
1418 if (rtx_equal_p (ops[j], op))
1419 win = 1;
1421 /* If we can put the other operand into a register, add to
1422 the cost of this alternative the cost to copy this
1423 operand to the register used for the other operand. */
1425 else if (classes[j] != NO_REGS)
1426 alt_cost += copy_cost (op, mode, classes[j], 1), win = 1;
1428 else if (GET_CODE (ops[j]) != REG
1429 || REGNO (ops[j]) < FIRST_PSEUDO_REGISTER)
1431 /* This op is a pseudo but the one it matches is not. */
1433 /* If we can't put the other operand into a register, this
1434 alternative can't be used. */
1436 if (classes[j] == NO_REGS)
1437 alt_fail = 1;
1439 /* Otherwise, add to the cost of this alternative the cost
1440 to copy the other operand to the register used for this
1441 operand. */
1443 else
1444 alt_cost += copy_cost (ops[j], mode, classes[j], 1);
1446 else
1448 /* The costs of this operand are not the same as the other
1449 operand since move costs are not symmetric. Moreover,
1450 if we cannot tie them, this alternative needs to do a
1451 copy, which is one instruction. */
1453 struct costs *pp = &this_op_costs[i];
1455 for (class = 0; class < N_REG_CLASSES; class++)
1456 pp->cost[class]
1457 = ((recog_data.operand_type[i] != OP_OUT
1458 ? may_move_in_cost[mode][class][(int) classes[i]]
1459 : 0)
1460 + (recog_data.operand_type[i] != OP_IN
1461 ? may_move_out_cost[mode][(int) classes[i]][class]
1462 : 0));
1464 /* If the alternative actually allows memory, make things
1465 a bit cheaper since we won't need an extra insn to
1466 load it. */
1468 pp->mem_cost
1469 = ((recog_data.operand_type[i] != OP_IN
1470 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1471 : 0)
1472 + (recog_data.operand_type[i] != OP_OUT
1473 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1474 : 0) - allows_mem[i]);
1476 /* If we have assigned a class to this register in our
1477 first pass, add a cost to this alternative corresponding
1478 to what we would add if this register were not in the
1479 appropriate class. */
1481 if (reg_pref)
1482 alt_cost
1483 += (may_move_in_cost[mode]
1484 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1485 [(int) classes[i]]);
1487 if (REGNO (ops[i]) != REGNO (ops[j])
1488 && ! find_reg_note (insn, REG_DEAD, op))
1489 alt_cost += 2;
1491 /* This is in place of ordinary cost computation
1492 for this operand, so skip to the end of the
1493 alternative (should be just one character). */
1494 while (*p && *p++ != ',')
1497 constraints[i] = p;
1498 continue;
1502 /* Scan all the constraint letters. See if the operand matches
1503 any of the constraints. Collect the valid register classes
1504 and see if this operand accepts memory. */
1506 while (*p && (c = *p++) != ',')
1507 switch (c)
1509 case '*':
1510 /* Ignore the next letter for this pass. */
1511 p++;
1512 break;
1514 case '?':
1515 alt_cost += 2;
1516 case '!': case '#': case '&':
1517 case '0': case '1': case '2': case '3': case '4':
1518 case '5': case '6': case '7': case '8': case '9':
1519 break;
1521 case 'p':
1522 allows_addr = 1;
1523 win = address_operand (op, GET_MODE (op));
1524 /* We know this operand is an address, so we want it to be
1525 allocated to a register that can be the base of an
1526 address, ie BASE_REG_CLASS. */
1527 classes[i]
1528 = reg_class_subunion[(int) classes[i]]
1529 [(int) BASE_REG_CLASS];
1530 break;
1532 case 'm': case 'o': case 'V':
1533 /* It doesn't seem worth distinguishing between offsettable
1534 and non-offsettable addresses here. */
1535 allows_mem[i] = 1;
1536 if (GET_CODE (op) == MEM)
1537 win = 1;
1538 break;
1540 case '<':
1541 if (GET_CODE (op) == MEM
1542 && (GET_CODE (XEXP (op, 0)) == PRE_DEC
1543 || GET_CODE (XEXP (op, 0)) == POST_DEC))
1544 win = 1;
1545 break;
1547 case '>':
1548 if (GET_CODE (op) == MEM
1549 && (GET_CODE (XEXP (op, 0)) == PRE_INC
1550 || GET_CODE (XEXP (op, 0)) == POST_INC))
1551 win = 1;
1552 break;
1554 case 'E':
1555 #ifndef REAL_ARITHMETIC
1556 /* Match any floating double constant, but only if
1557 we can examine the bits of it reliably. */
1558 if ((HOST_FLOAT_FORMAT != TARGET_FLOAT_FORMAT
1559 || HOST_BITS_PER_WIDE_INT != BITS_PER_WORD)
1560 && GET_MODE (op) != VOIDmode && ! flag_pretend_float)
1561 break;
1562 #endif
1563 if (GET_CODE (op) == CONST_DOUBLE)
1564 win = 1;
1565 break;
1567 case 'F':
1568 if (GET_CODE (op) == CONST_DOUBLE)
1569 win = 1;
1570 break;
1572 case 'G':
1573 case 'H':
1574 if (GET_CODE (op) == CONST_DOUBLE
1575 && CONST_DOUBLE_OK_FOR_LETTER_P (op, c))
1576 win = 1;
1577 break;
1579 case 's':
1580 if (GET_CODE (op) == CONST_INT
1581 || (GET_CODE (op) == CONST_DOUBLE
1582 && GET_MODE (op) == VOIDmode))
1583 break;
1584 case 'i':
1585 if (CONSTANT_P (op)
1586 #ifdef LEGITIMATE_PIC_OPERAND_P
1587 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1588 #endif
1590 win = 1;
1591 break;
1593 case 'n':
1594 if (GET_CODE (op) == CONST_INT
1595 || (GET_CODE (op) == CONST_DOUBLE
1596 && GET_MODE (op) == VOIDmode))
1597 win = 1;
1598 break;
1600 case 'I':
1601 case 'J':
1602 case 'K':
1603 case 'L':
1604 case 'M':
1605 case 'N':
1606 case 'O':
1607 case 'P':
1608 if (GET_CODE (op) == CONST_INT
1609 && CONST_OK_FOR_LETTER_P (INTVAL (op), c))
1610 win = 1;
1611 break;
1613 case 'X':
1614 win = 1;
1615 break;
1617 case 'g':
1618 if (GET_CODE (op) == MEM
1619 || (CONSTANT_P (op)
1620 #ifdef LEGITIMATE_PIC_OPERAND_P
1621 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op))
1622 #endif
1624 win = 1;
1625 allows_mem[i] = 1;
1626 case 'r':
1627 classes[i]
1628 = reg_class_subunion[(int) classes[i]][(int) GENERAL_REGS];
1629 break;
1631 default:
1632 if (REG_CLASS_FROM_LETTER (c) != NO_REGS)
1633 classes[i]
1634 = reg_class_subunion[(int) classes[i]]
1635 [(int) REG_CLASS_FROM_LETTER (c)];
1636 #ifdef EXTRA_CONSTRAINT
1637 else if (EXTRA_CONSTRAINT (op, c))
1638 win = 1;
1639 #endif
1640 break;
1643 constraints[i] = p;
1645 /* How we account for this operand now depends on whether it is a
1646 pseudo register or not. If it is, we first check if any
1647 register classes are valid. If not, we ignore this alternative,
1648 since we want to assume that all pseudos get allocated for
1649 register preferencing. If some register class is valid, compute
1650 the costs of moving the pseudo into that class. */
1652 if (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)
1654 if (classes[i] == NO_REGS)
1656 /* We must always fail if the operand is a REG, but
1657 we did not find a suitable class.
1659 Otherwise we may perform an uninitialized read
1660 from this_op_costs after the `continue' statement
1661 below. */
1662 alt_fail = 1;
1664 else
1666 struct costs *pp = &this_op_costs[i];
1668 for (class = 0; class < N_REG_CLASSES; class++)
1669 pp->cost[class]
1670 = ((recog_data.operand_type[i] != OP_OUT
1671 ? may_move_in_cost[mode][class][(int) classes[i]]
1672 : 0)
1673 + (recog_data.operand_type[i] != OP_IN
1674 ? may_move_out_cost[mode][(int) classes[i]][class]
1675 : 0));
1677 /* If the alternative actually allows memory, make things
1678 a bit cheaper since we won't need an extra insn to
1679 load it. */
1681 pp->mem_cost
1682 = ((recog_data.operand_type[i] != OP_IN
1683 ? MEMORY_MOVE_COST (mode, classes[i], 0)
1684 : 0)
1685 + (recog_data.operand_type[i] != OP_OUT
1686 ? MEMORY_MOVE_COST (mode, classes[i], 1)
1687 : 0) - allows_mem[i]);
1689 /* If we have assigned a class to this register in our
1690 first pass, add a cost to this alternative corresponding
1691 to what we would add if this register were not in the
1692 appropriate class. */
1694 if (reg_pref)
1695 alt_cost
1696 += (may_move_in_cost[mode]
1697 [(unsigned char) reg_pref[REGNO (op)].prefclass]
1698 [(int) classes[i]]);
1702 /* Otherwise, if this alternative wins, either because we
1703 have already determined that or if we have a hard register of
1704 the proper class, there is no cost for this alternative. */
1706 else if (win
1707 || (GET_CODE (op) == REG
1708 && reg_fits_class_p (op, classes[i], 0, GET_MODE (op))))
1711 /* If registers are valid, the cost of this alternative includes
1712 copying the object to and/or from a register. */
1714 else if (classes[i] != NO_REGS)
1716 if (recog_data.operand_type[i] != OP_OUT)
1717 alt_cost += copy_cost (op, mode, classes[i], 1);
1719 if (recog_data.operand_type[i] != OP_IN)
1720 alt_cost += copy_cost (op, mode, classes[i], 0);
1723 /* The only other way this alternative can be used is if this is a
1724 constant that could be placed into memory. */
1726 else if (CONSTANT_P (op) && (allows_addr || allows_mem[i]))
1727 alt_cost += MEMORY_MOVE_COST (mode, classes[i], 1);
1728 else
1729 alt_fail = 1;
1732 if (alt_fail)
1733 continue;
1735 /* Finally, update the costs with the information we've calculated
1736 about this alternative. */
1738 for (i = 0; i < n_ops; i++)
1739 if (GET_CODE (ops[i]) == REG
1740 && REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1742 struct costs *pp = &op_costs[i], *qq = &this_op_costs[i];
1743 int scale = 1 + (recog_data.operand_type[i] == OP_INOUT);
1745 pp->mem_cost = MIN (pp->mem_cost,
1746 (qq->mem_cost + alt_cost) * scale);
1748 for (class = 0; class < N_REG_CLASSES; class++)
1749 pp->cost[class] = MIN (pp->cost[class],
1750 (qq->cost[class] + alt_cost) * scale);
1754 /* If this insn is a single set copying operand 1 to operand 0
1755 and one operand is a pseudo with the other a hard reg or a pseudo
1756 that prefers a register that is in its own register class then
1757 we may want to adjust the cost of that register class to -1.
1759 Avoid the adjustment if the source does not die to avoid stressing of
1760 register allocator by preferrencing two coliding registers into single
1761 class.
1763 Also avoid the adjustment if a copy between registers of the class
1764 is expensive (ten times the cost of a default copy is considered
1765 arbitrarily expensive). This avoids losing when the preferred class
1766 is very expensive as the source of a copy instruction. */
1768 if ((set = single_set (insn)) != 0
1769 && ops[0] == SET_DEST (set) && ops[1] == SET_SRC (set)
1770 && GET_CODE (ops[0]) == REG && GET_CODE (ops[1]) == REG
1771 && find_regno_note (insn, REG_DEAD, REGNO (ops[1])))
1772 for (i = 0; i <= 1; i++)
1773 if (REGNO (ops[i]) >= FIRST_PSEUDO_REGISTER)
1775 unsigned int regno = REGNO (ops[!i]);
1776 enum machine_mode mode = GET_MODE (ops[!i]);
1777 int class;
1778 unsigned int nr;
1780 if (regno >= FIRST_PSEUDO_REGISTER && reg_pref != 0)
1782 enum reg_class pref = reg_pref[regno].prefclass;
1784 if ((reg_class_size[(unsigned char) pref]
1785 == CLASS_MAX_NREGS (pref, mode))
1786 && REGISTER_MOVE_COST (mode, pref, pref) < 10 * 2)
1787 op_costs[i].cost[(unsigned char) pref] = -1;
1789 else if (regno < FIRST_PSEUDO_REGISTER)
1790 for (class = 0; class < N_REG_CLASSES; class++)
1791 if (TEST_HARD_REG_BIT (reg_class_contents[class], regno)
1792 && reg_class_size[class] == CLASS_MAX_NREGS (class, mode))
1794 if (reg_class_size[class] == 1)
1795 op_costs[i].cost[class] = -1;
1796 else
1798 for (nr = 0; nr < HARD_REGNO_NREGS (regno, mode); nr++)
1800 if (! TEST_HARD_REG_BIT (reg_class_contents[class],
1801 regno + nr))
1802 break;
1805 if (nr == HARD_REGNO_NREGS (regno,mode))
1806 op_costs[i].cost[class] = -1;
1812 /* Compute the cost of loading X into (if TO_P is non-zero) or from (if
1813 TO_P is zero) a register of class CLASS in mode MODE.
1815 X must not be a pseudo. */
1817 static int
1818 copy_cost (x, mode, class, to_p)
1819 rtx x;
1820 enum machine_mode mode ATTRIBUTE_UNUSED;
1821 enum reg_class class;
1822 int to_p ATTRIBUTE_UNUSED;
1824 #ifdef HAVE_SECONDARY_RELOADS
1825 enum reg_class secondary_class = NO_REGS;
1826 #endif
1828 /* If X is a SCRATCH, there is actually nothing to move since we are
1829 assuming optimal allocation. */
1831 if (GET_CODE (x) == SCRATCH)
1832 return 0;
1834 /* Get the class we will actually use for a reload. */
1835 class = PREFERRED_RELOAD_CLASS (x, class);
1837 #ifdef HAVE_SECONDARY_RELOADS
1838 /* If we need a secondary reload (we assume here that we are using
1839 the secondary reload as an intermediate, not a scratch register), the
1840 cost is that to load the input into the intermediate register, then
1841 to copy them. We use a special value of TO_P to avoid recursion. */
1843 #ifdef SECONDARY_INPUT_RELOAD_CLASS
1844 if (to_p == 1)
1845 secondary_class = SECONDARY_INPUT_RELOAD_CLASS (class, mode, x);
1846 #endif
1848 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
1849 if (! to_p)
1850 secondary_class = SECONDARY_OUTPUT_RELOAD_CLASS (class, mode, x);
1851 #endif
1853 if (secondary_class != NO_REGS)
1854 return (move_cost[mode][(int) secondary_class][(int) class]
1855 + copy_cost (x, mode, secondary_class, 2));
1856 #endif /* HAVE_SECONDARY_RELOADS */
1858 /* For memory, use the memory move cost, for (hard) registers, use the
1859 cost to move between the register classes, and use 2 for everything
1860 else (constants). */
1862 if (GET_CODE (x) == MEM || class == NO_REGS)
1863 return MEMORY_MOVE_COST (mode, class, to_p);
1865 else if (GET_CODE (x) == REG)
1866 return move_cost[mode][(int) REGNO_REG_CLASS (REGNO (x))][(int) class];
1868 else
1869 /* If this is a constant, we may eventually want to call rtx_cost here. */
1870 return COSTS_N_INSNS (1);
1873 /* Record the pseudo registers we must reload into hard registers
1874 in a subexpression of a memory address, X.
1876 CLASS is the class that the register needs to be in and is either
1877 BASE_REG_CLASS or INDEX_REG_CLASS.
1879 SCALE is twice the amount to multiply the cost by (it is twice so we
1880 can represent half-cost adjustments). */
1882 static void
1883 record_address_regs (x, class, scale)
1884 rtx x;
1885 enum reg_class class;
1886 int scale;
1888 register enum rtx_code code = GET_CODE (x);
1890 switch (code)
1892 case CONST_INT:
1893 case CONST:
1894 case CC0:
1895 case PC:
1896 case SYMBOL_REF:
1897 case LABEL_REF:
1898 return;
1900 case PLUS:
1901 /* When we have an address that is a sum,
1902 we must determine whether registers are "base" or "index" regs.
1903 If there is a sum of two registers, we must choose one to be
1904 the "base". Luckily, we can use the REG_POINTER to make a good
1905 choice most of the time. We only need to do this on machines
1906 that can have two registers in an address and where the base
1907 and index register classes are different.
1909 ??? This code used to set REGNO_POINTER_FLAG in some cases, but
1910 that seems bogus since it should only be set when we are sure
1911 the register is being used as a pointer. */
1914 rtx arg0 = XEXP (x, 0);
1915 rtx arg1 = XEXP (x, 1);
1916 register enum rtx_code code0 = GET_CODE (arg0);
1917 register enum rtx_code code1 = GET_CODE (arg1);
1919 /* Look inside subregs. */
1920 if (code0 == SUBREG)
1921 arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0);
1922 if (code1 == SUBREG)
1923 arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1);
1925 /* If this machine only allows one register per address, it must
1926 be in the first operand. */
1928 if (MAX_REGS_PER_ADDRESS == 1)
1929 record_address_regs (arg0, class, scale);
1931 /* If index and base registers are the same on this machine, just
1932 record registers in any non-constant operands. We assume here,
1933 as well as in the tests below, that all addresses are in
1934 canonical form. */
1936 else if (INDEX_REG_CLASS == BASE_REG_CLASS)
1938 record_address_regs (arg0, class, scale);
1939 if (! CONSTANT_P (arg1))
1940 record_address_regs (arg1, class, scale);
1943 /* If the second operand is a constant integer, it doesn't change
1944 what class the first operand must be. */
1946 else if (code1 == CONST_INT || code1 == CONST_DOUBLE)
1947 record_address_regs (arg0, class, scale);
1949 /* If the second operand is a symbolic constant, the first operand
1950 must be an index register. */
1952 else if (code1 == SYMBOL_REF || code1 == CONST || code1 == LABEL_REF)
1953 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1955 /* If both operands are registers but one is already a hard register
1956 of index or base class, give the other the class that the hard
1957 register is not. */
1959 #ifdef REG_OK_FOR_BASE_P
1960 else if (code0 == REG && code1 == REG
1961 && REGNO (arg0) < FIRST_PSEUDO_REGISTER
1962 && (REG_OK_FOR_BASE_P (arg0) || REG_OK_FOR_INDEX_P (arg0)))
1963 record_address_regs (arg1,
1964 REG_OK_FOR_BASE_P (arg0)
1965 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1966 scale);
1967 else if (code0 == REG && code1 == REG
1968 && REGNO (arg1) < FIRST_PSEUDO_REGISTER
1969 && (REG_OK_FOR_BASE_P (arg1) || REG_OK_FOR_INDEX_P (arg1)))
1970 record_address_regs (arg0,
1971 REG_OK_FOR_BASE_P (arg1)
1972 ? INDEX_REG_CLASS : BASE_REG_CLASS,
1973 scale);
1974 #endif
1976 /* If one operand is known to be a pointer, it must be the base
1977 with the other operand the index. Likewise if the other operand
1978 is a MULT. */
1980 else if ((code0 == REG && REG_POINTER (arg0))
1981 || code1 == MULT)
1983 record_address_regs (arg0, BASE_REG_CLASS, scale);
1984 record_address_regs (arg1, INDEX_REG_CLASS, scale);
1986 else if ((code1 == REG && REG_POINTER (arg1))
1987 || code0 == MULT)
1989 record_address_regs (arg0, INDEX_REG_CLASS, scale);
1990 record_address_regs (arg1, BASE_REG_CLASS, scale);
1993 /* Otherwise, count equal chances that each might be a base
1994 or index register. This case should be rare. */
1996 else
1998 record_address_regs (arg0, BASE_REG_CLASS, scale / 2);
1999 record_address_regs (arg0, INDEX_REG_CLASS, scale / 2);
2000 record_address_regs (arg1, BASE_REG_CLASS, scale / 2);
2001 record_address_regs (arg1, INDEX_REG_CLASS, scale / 2);
2004 break;
2006 /* Double the importance of a pseudo register that is incremented
2007 or decremented, since it would take two extra insns
2008 if it ends up in the wrong place. */
2009 case POST_MODIFY:
2010 case PRE_MODIFY:
2011 record_address_regs (XEXP (x, 0), BASE_REG_CLASS, 2 * scale);
2012 if (REG_P (XEXP (XEXP (x, 1), 1)))
2013 record_address_regs (XEXP (XEXP (x, 1), 1),
2014 INDEX_REG_CLASS, 2 * scale);
2015 break;
2017 case POST_INC:
2018 case PRE_INC:
2019 case POST_DEC:
2020 case PRE_DEC:
2021 /* Double the importance of a pseudo register that is incremented
2022 or decremented, since it would take two extra insns
2023 if it ends up in the wrong place. If the operand is a pseudo,
2024 show it is being used in an INC_DEC context. */
2026 #ifdef FORBIDDEN_INC_DEC_CLASSES
2027 if (GET_CODE (XEXP (x, 0)) == REG
2028 && REGNO (XEXP (x, 0)) >= FIRST_PSEUDO_REGISTER)
2029 in_inc_dec[REGNO (XEXP (x, 0))] = 1;
2030 #endif
2032 record_address_regs (XEXP (x, 0), class, 2 * scale);
2033 break;
2035 case REG:
2037 register struct costs *pp = &costs[REGNO (x)];
2038 register int i;
2040 pp->mem_cost += (MEMORY_MOVE_COST (Pmode, class, 1) * scale) / 2;
2042 for (i = 0; i < N_REG_CLASSES; i++)
2043 pp->cost[i] += (may_move_in_cost[Pmode][i][(int) class] * scale) / 2;
2045 break;
2047 default:
2049 register const char *fmt = GET_RTX_FORMAT (code);
2050 register int i;
2051 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2052 if (fmt[i] == 'e')
2053 record_address_regs (XEXP (x, i), class, scale);
2058 #ifdef FORBIDDEN_INC_DEC_CLASSES
2060 /* Return 1 if REG is valid as an auto-increment memory reference
2061 to an object of MODE. */
2063 static int
2064 auto_inc_dec_reg_p (reg, mode)
2065 rtx reg;
2066 enum machine_mode mode;
2068 if (HAVE_POST_INCREMENT
2069 && memory_address_p (mode, gen_rtx_POST_INC (Pmode, reg)))
2070 return 1;
2072 if (HAVE_POST_DECREMENT
2073 && memory_address_p (mode, gen_rtx_POST_DEC (Pmode, reg)))
2074 return 1;
2076 if (HAVE_PRE_INCREMENT
2077 && memory_address_p (mode, gen_rtx_PRE_INC (Pmode, reg)))
2078 return 1;
2080 if (HAVE_PRE_DECREMENT
2081 && memory_address_p (mode, gen_rtx_PRE_DEC (Pmode, reg)))
2082 return 1;
2084 return 0;
2086 #endif
2088 static short *renumber;
2089 static size_t regno_allocated;
2090 static unsigned int reg_n_max;
2092 /* Allocate enough space to hold NUM_REGS registers for the tables used for
2093 reg_scan and flow_analysis that are indexed by the register number. If
2094 NEW_P is non zero, initialize all of the registers, otherwise only
2095 initialize the new registers allocated. The same table is kept from
2096 function to function, only reallocating it when we need more room. If
2097 RENUMBER_P is non zero, allocate the reg_renumber array also. */
2099 void
2100 allocate_reg_info (num_regs, new_p, renumber_p)
2101 size_t num_regs;
2102 int new_p;
2103 int renumber_p;
2105 size_t size_info;
2106 size_t size_renumber;
2107 size_t min = (new_p) ? 0 : reg_n_max;
2108 struct reg_info_data *reg_data;
2110 if (num_regs > regno_allocated)
2112 size_t old_allocated = regno_allocated;
2114 regno_allocated = num_regs + (num_regs / 20); /* add some slop space */
2115 size_renumber = regno_allocated * sizeof (short);
2117 if (!reg_n_info)
2119 VARRAY_REG_INIT (reg_n_info, regno_allocated, "reg_n_info");
2120 renumber = (short *) xmalloc (size_renumber);
2121 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2122 * sizeof (struct reg_pref));
2125 else
2127 VARRAY_GROW (reg_n_info, regno_allocated);
2129 if (new_p) /* if we're zapping everything, no need to realloc */
2131 free ((char *)renumber);
2132 free ((char *)reg_pref);
2133 renumber = (short *) xmalloc (size_renumber);
2134 reg_pref_buffer = (struct reg_pref *) xmalloc (regno_allocated
2135 * sizeof (struct reg_pref));
2138 else
2140 renumber = (short *) xrealloc ((char *)renumber, size_renumber);
2141 reg_pref_buffer = (struct reg_pref *) xrealloc ((char *)reg_pref_buffer,
2142 regno_allocated
2143 * sizeof (struct reg_pref));
2147 size_info = (regno_allocated - old_allocated) * sizeof (reg_info)
2148 + sizeof (struct reg_info_data) - sizeof (reg_info);
2149 reg_data = (struct reg_info_data *) xcalloc (size_info, 1);
2150 reg_data->min_index = old_allocated;
2151 reg_data->max_index = regno_allocated - 1;
2152 reg_data->next = reg_info_head;
2153 reg_info_head = reg_data;
2156 reg_n_max = num_regs;
2157 if (min < num_regs)
2159 /* Loop through each of the segments allocated for the actual
2160 reg_info pages, and set up the pointers, zero the pages, etc. */
2161 for (reg_data = reg_info_head;
2162 reg_data && reg_data->max_index >= min;
2163 reg_data = reg_data->next)
2165 size_t min_index = reg_data->min_index;
2166 size_t max_index = reg_data->max_index;
2167 size_t max = MIN (max_index, num_regs);
2168 size_t local_min = min - min_index;
2169 size_t i;
2171 if (reg_data->min_index > num_regs)
2172 continue;
2174 if (min < min_index)
2175 local_min = 0;
2176 if (!reg_data->used_p) /* page just allocated with calloc */
2177 reg_data->used_p = 1; /* no need to zero */
2178 else
2179 memset ((char *) &reg_data->data[local_min], 0,
2180 sizeof (reg_info) * (max - min_index - local_min + 1));
2182 for (i = min_index+local_min; i <= max; i++)
2184 VARRAY_REG (reg_n_info, i) = &reg_data->data[i-min_index];
2185 REG_BASIC_BLOCK (i) = REG_BLOCK_UNKNOWN;
2186 renumber[i] = -1;
2187 reg_pref_buffer[i].prefclass = (char) NO_REGS;
2188 reg_pref_buffer[i].altclass = (char) NO_REGS;
2193 /* If {pref,alt}class have already been allocated, update the pointers to
2194 the newly realloced ones. */
2195 if (reg_pref)
2196 reg_pref = reg_pref_buffer;
2198 if (renumber_p)
2199 reg_renumber = renumber;
2201 /* Tell the regset code about the new number of registers */
2202 MAX_REGNO_REG_SET (num_regs, new_p, renumber_p);
2205 /* Free up the space allocated by allocate_reg_info. */
2206 void
2207 free_reg_info ()
2209 if (reg_n_info)
2211 struct reg_info_data *reg_data;
2212 struct reg_info_data *reg_next;
2214 VARRAY_FREE (reg_n_info);
2215 for (reg_data = reg_info_head; reg_data; reg_data = reg_next)
2217 reg_next = reg_data->next;
2218 free ((char *)reg_data);
2221 free (reg_pref_buffer);
2222 reg_pref_buffer = (struct reg_pref *)0;
2223 reg_info_head = (struct reg_info_data *)0;
2224 renumber = (short *)0;
2226 regno_allocated = 0;
2227 reg_n_max = 0;
2230 /* This is the `regscan' pass of the compiler, run just before cse
2231 and again just before loop.
2233 It finds the first and last use of each pseudo-register
2234 and records them in the vectors regno_first_uid, regno_last_uid
2235 and counts the number of sets in the vector reg_n_sets.
2237 REPEAT is nonzero the second time this is called. */
2239 /* Maximum number of parallel sets and clobbers in any insn in this fn.
2240 Always at least 3, since the combiner could put that many together
2241 and we want this to remain correct for all the remaining passes.
2242 This corresponds to the maximum number of times note_stores will call
2243 a function for any insn. */
2245 int max_parallel;
2247 /* Used as a temporary to record the largest number of registers in
2248 PARALLEL in a SET_DEST. This is added to max_parallel. */
2250 static int max_set_parallel;
2252 void
2253 reg_scan (f, nregs, repeat)
2254 rtx f;
2255 unsigned int nregs;
2256 int repeat ATTRIBUTE_UNUSED;
2258 register rtx insn;
2260 allocate_reg_info (nregs, TRUE, FALSE);
2261 max_parallel = 3;
2262 max_set_parallel = 0;
2264 for (insn = f; insn; insn = NEXT_INSN (insn))
2265 if (GET_CODE (insn) == INSN
2266 || GET_CODE (insn) == CALL_INSN
2267 || GET_CODE (insn) == JUMP_INSN)
2269 if (GET_CODE (PATTERN (insn)) == PARALLEL
2270 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2271 max_parallel = XVECLEN (PATTERN (insn), 0);
2272 reg_scan_mark_refs (PATTERN (insn), insn, 0, 0);
2274 if (REG_NOTES (insn))
2275 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, 0);
2278 max_parallel += max_set_parallel;
2281 /* Update 'regscan' information by looking at the insns
2282 from FIRST to LAST. Some new REGs have been created,
2283 and any REG with number greater than OLD_MAX_REGNO is
2284 such a REG. We only update information for those. */
2286 void
2287 reg_scan_update (first, last, old_max_regno)
2288 rtx first;
2289 rtx last;
2290 unsigned int old_max_regno;
2292 register rtx insn;
2294 allocate_reg_info (max_reg_num (), FALSE, FALSE);
2296 for (insn = first; insn != last; insn = NEXT_INSN (insn))
2297 if (GET_CODE (insn) == INSN
2298 || GET_CODE (insn) == CALL_INSN
2299 || GET_CODE (insn) == JUMP_INSN)
2301 if (GET_CODE (PATTERN (insn)) == PARALLEL
2302 && XVECLEN (PATTERN (insn), 0) > max_parallel)
2303 max_parallel = XVECLEN (PATTERN (insn), 0);
2304 reg_scan_mark_refs (PATTERN (insn), insn, 0, old_max_regno);
2306 if (REG_NOTES (insn))
2307 reg_scan_mark_refs (REG_NOTES (insn), insn, 1, old_max_regno);
2311 /* X is the expression to scan. INSN is the insn it appears in.
2312 NOTE_FLAG is nonzero if X is from INSN's notes rather than its body.
2313 We should only record information for REGs with numbers
2314 greater than or equal to MIN_REGNO. */
2316 static void
2317 reg_scan_mark_refs (x, insn, note_flag, min_regno)
2318 rtx x;
2319 rtx insn;
2320 int note_flag;
2321 unsigned int min_regno;
2323 register enum rtx_code code;
2324 register rtx dest;
2325 register rtx note;
2327 code = GET_CODE (x);
2328 switch (code)
2330 case CONST:
2331 case CONST_INT:
2332 case CONST_DOUBLE:
2333 case CC0:
2334 case PC:
2335 case SYMBOL_REF:
2336 case LABEL_REF:
2337 case ADDR_VEC:
2338 case ADDR_DIFF_VEC:
2339 return;
2341 case REG:
2343 unsigned int regno = REGNO (x);
2345 if (regno >= min_regno)
2347 REGNO_LAST_NOTE_UID (regno) = INSN_UID (insn);
2348 if (!note_flag)
2349 REGNO_LAST_UID (regno) = INSN_UID (insn);
2350 if (REGNO_FIRST_UID (regno) == 0)
2351 REGNO_FIRST_UID (regno) = INSN_UID (insn);
2354 break;
2356 case EXPR_LIST:
2357 if (XEXP (x, 0))
2358 reg_scan_mark_refs (XEXP (x, 0), insn, note_flag, min_regno);
2359 if (XEXP (x, 1))
2360 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2361 break;
2363 case INSN_LIST:
2364 if (XEXP (x, 1))
2365 reg_scan_mark_refs (XEXP (x, 1), insn, note_flag, min_regno);
2366 break;
2368 case SET:
2369 /* Count a set of the destination if it is a register. */
2370 for (dest = SET_DEST (x);
2371 GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
2372 || GET_CODE (dest) == ZERO_EXTEND;
2373 dest = XEXP (dest, 0))
2376 /* For a PARALLEL, record the number of things (less the usual one for a
2377 SET) that are set. */
2378 if (GET_CODE (dest) == PARALLEL)
2379 max_set_parallel = MAX (max_set_parallel, XVECLEN (dest, 0) - 1);
2381 if (GET_CODE (dest) == REG
2382 && REGNO (dest) >= min_regno)
2383 REG_N_SETS (REGNO (dest))++;
2385 /* If this is setting a pseudo from another pseudo or the sum of a
2386 pseudo and a constant integer and the other pseudo is known to be
2387 a pointer, set the destination to be a pointer as well.
2389 Likewise if it is setting the destination from an address or from a
2390 value equivalent to an address or to the sum of an address and
2391 something else.
2393 But don't do any of this if the pseudo corresponds to a user
2394 variable since it should have already been set as a pointer based
2395 on the type. */
2397 if (GET_CODE (SET_DEST (x)) == REG
2398 && REGNO (SET_DEST (x)) >= FIRST_PSEUDO_REGISTER
2399 && REGNO (SET_DEST (x)) >= min_regno
2400 /* If the destination pseudo is set more than once, then other
2401 sets might not be to a pointer value (consider access to a
2402 union in two threads of control in the presense of global
2403 optimizations). So only set REG_POINTER on the destination
2404 pseudo if this is the only set of that pseudo. */
2405 && REG_N_SETS (REGNO (SET_DEST (x))) == 1
2406 && ! REG_USERVAR_P (SET_DEST (x))
2407 && ! REG_POINTER (SET_DEST (x))
2408 && ((GET_CODE (SET_SRC (x)) == REG
2409 && REG_POINTER (SET_SRC (x)))
2410 || ((GET_CODE (SET_SRC (x)) == PLUS
2411 || GET_CODE (SET_SRC (x)) == LO_SUM)
2412 && GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
2413 && GET_CODE (XEXP (SET_SRC (x), 0)) == REG
2414 && REG_POINTER (XEXP (SET_SRC (x), 0)))
2415 || GET_CODE (SET_SRC (x)) == CONST
2416 || GET_CODE (SET_SRC (x)) == SYMBOL_REF
2417 || GET_CODE (SET_SRC (x)) == LABEL_REF
2418 || (GET_CODE (SET_SRC (x)) == HIGH
2419 && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
2420 || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
2421 || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
2422 || ((GET_CODE (SET_SRC (x)) == PLUS
2423 || GET_CODE (SET_SRC (x)) == LO_SUM)
2424 && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
2425 || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
2426 || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
2427 || ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
2428 && (GET_CODE (XEXP (note, 0)) == CONST
2429 || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
2430 || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
2431 REG_POINTER (SET_DEST (x)) = 1;
2433 /* ... fall through ... */
2435 default:
2437 register const char *fmt = GET_RTX_FORMAT (code);
2438 register int i;
2439 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2441 if (fmt[i] == 'e')
2442 reg_scan_mark_refs (XEXP (x, i), insn, note_flag, min_regno);
2443 else if (fmt[i] == 'E' && XVEC (x, i) != 0)
2445 register int j;
2446 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
2447 reg_scan_mark_refs (XVECEXP (x, i, j), insn, note_flag, min_regno);
2454 /* Return nonzero if C1 is a subset of C2, i.e., if every register in C1
2455 is also in C2. */
2458 reg_class_subset_p (c1, c2)
2459 register enum reg_class c1;
2460 register enum reg_class c2;
2462 if (c1 == c2) return 1;
2464 if (c2 == ALL_REGS)
2465 win:
2466 return 1;
2467 GO_IF_HARD_REG_SUBSET (reg_class_contents[(int)c1],
2468 reg_class_contents[(int)c2],
2469 win);
2470 return 0;
2473 /* Return nonzero if there is a register that is in both C1 and C2. */
2476 reg_classes_intersect_p (c1, c2)
2477 register enum reg_class c1;
2478 register enum reg_class c2;
2480 #ifdef HARD_REG_SET
2481 register
2482 #endif
2483 HARD_REG_SET c;
2485 if (c1 == c2) return 1;
2487 if (c1 == ALL_REGS || c2 == ALL_REGS)
2488 return 1;
2490 COPY_HARD_REG_SET (c, reg_class_contents[(int) c1]);
2491 AND_HARD_REG_SET (c, reg_class_contents[(int) c2]);
2493 GO_IF_HARD_REG_SUBSET (c, reg_class_contents[(int) NO_REGS], lose);
2494 return 1;
2496 lose:
2497 return 0;
2500 /* Release any memory allocated by register sets. */
2502 void
2503 regset_release_memory ()
2505 bitmap_release_memory ();