| blob | fc8c8c9ccd4418bfa224788a5693a23239367cbc |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 91-98, 1999 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
10 ;; any later version.
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 \f
24 ;; Define an insn type attribute. This is used in function unit delay
25 ;; computations.
26 (define_attr "type" "integer,load,store,fpload,fpstore,imul,idiv,branch,compare,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg"
27 (const_string "integer"))
29 ;; Length (in bytes).
30 (define_attr "length" ""
31 (if_then_else (eq_attr "type" "branch")
32 (if_then_else (and (ge (minus (pc) (match_dup 0))
33 (const_int -32768))
34 (lt (minus (pc) (match_dup 0))
35 (const_int 32767)))
36 (const_int 8)
37 (const_int 12))
38 (const_int 4)))
40 ;; Processor type -- this attribute must exactly match the processor_type
41 ;; enumeration in rs6000.h.
43 (define_attr "cpu" "rios1,rios2,mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"
44 (const (symbol_ref "rs6000_cpu_attr")))
46 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
47 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
49 ; Load/Store Unit -- pure PowerPC only
50 ; (POWER and 601 use Integer Unit)
51 (define_function_unit "lsu" 1 0
52 (and (eq_attr "type" "load")
53 (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc604e,ppc620,ppc750"))
54 2 1)
56 (define_function_unit "lsu" 1 0
57 (and (eq_attr "type" "store,fpstore")
58 (eq_attr "cpu" "mpccore,ppc603,ppc604,ppc604e,ppc620,ppc750"))
59 1 1)
61 (define_function_unit "lsu" 1 0
62 (and (eq_attr "type" "fpload")
63 (eq_attr "cpu" "mpccore,ppc603,ppc750"))
64 2 1)
66 (define_function_unit "lsu" 1 0
67 (and (eq_attr "type" "fpload")
68 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
69 3 1)
71 (define_function_unit "iu" 1 0
72 (and (eq_attr "type" "load")
73 (eq_attr "cpu" "rios1,ppc403,ppc601"))
74 2 1)
76 (define_function_unit "iu" 1 0
77 (and (eq_attr "type" "store,fpstore")
78 (eq_attr "cpu" "rios1,ppc403,ppc601"))
79 1 1)
81 (define_function_unit "fpu" 1 0
82 (and (eq_attr "type" "fpstore")
83 (eq_attr "cpu" "rios1,ppc601"))
84 0 1)
86 (define_function_unit "iu" 1 0
87 (and (eq_attr "type" "fpload")
88 (eq_attr "cpu" "rios1"))
89 2 1)
91 (define_function_unit "iu" 1 0
92 (and (eq_attr "type" "fpload")
93 (eq_attr "cpu" "ppc601"))
94 3 1)
96 (define_function_unit "iu2" 2 0
97 (and (eq_attr "type" "load,fpload")
98 (eq_attr "cpu" "rios2"))
99 2 1)
101 (define_function_unit "iu2" 2 0
102 (and (eq_attr "type" "store,fpstore")
103 (eq_attr "cpu" "rios2"))
104 1 1)
106 ; Integer Unit (RIOS1, PPC601, PPC603)
107 (define_function_unit "iu" 1 0
108 (and (eq_attr "type" "integer")
109 (eq_attr "cpu" "rios1,mpccore,ppc403,ppc601,ppc603"))
110 1 1)
112 (define_function_unit "iu" 1 0
113 (and (eq_attr "type" "imul")
114 (eq_attr "cpu" "ppc403"))
115 4 4)
117 (define_function_unit "iu" 1 0
118 (and (eq_attr "type" "imul")
119 (eq_attr "cpu" "rios1,ppc601,ppc603"))
120 5 5)
122 (define_function_unit "iu" 1 0
123 (and (eq_attr "type" "idiv")
124 (eq_attr "cpu" "rios1"))
125 19 19)
127 (define_function_unit "iu" 1 0
128 (and (eq_attr "type" "idiv")
129 (eq_attr "cpu" "ppc403"))
130 33 33)
132 (define_function_unit "iu" 1 0
133 (and (eq_attr "type" "idiv")
134 (eq_attr "cpu" "ppc601"))
135 36 36)
137 (define_function_unit "iu" 1 0
138 (and (eq_attr "type" "idiv")
139 (eq_attr "cpu" "ppc603"))
140 37 36)
142 ; RIOS2 has two integer units: a primary one which can perform all
143 ; operations and a secondary one which is fed in lock step with the first
144 ; and can perform "simple" integer operations.
145 ; To catch this we define a 'dummy' imuldiv-unit that is also needed
146 ; for the complex insns.
147 (define_function_unit "iu2" 2 0
148 (and (eq_attr "type" "integer")
149 (eq_attr "cpu" "rios2"))
150 1 1)
152 (define_function_unit "iu2" 2 0
153 (and (eq_attr "type" "imul")
154 (eq_attr "cpu" "rios2"))
155 2 2)
157 (define_function_unit "iu2" 2 0
158 (and (eq_attr "type" "idiv")
159 (eq_attr "cpu" "rios2"))
160 13 13)
162 (define_function_unit "imuldiv" 1 0
163 (and (eq_attr "type" "imul")
164 (eq_attr "cpu" "rios2"))
165 2 2)
167 (define_function_unit "imuldiv" 1 0
168 (and (eq_attr "type" "idiv")
169 (eq_attr "cpu" "rios2"))
170 13 13)
172 ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions
173 ; Divide latency varies greatly from 2-11, use 6 as average
174 (define_function_unit "imuldiv" 1 0
175 (and (eq_attr "type" "imul")
176 (eq_attr "cpu" "mpccore"))
177 2 1)
179 (define_function_unit "imuldiv" 1 0
180 (and (eq_attr "type" "idiv")
181 (eq_attr "cpu" "mpccore"))
182 6 6)
184 ; PPC604{,e} has two units that perform integer operations
185 ; and one unit for divide/multiply operations (and move
186 ; from/to spr).
187 (define_function_unit "iu2" 2 0
188 (and (eq_attr "type" "integer")
189 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
190 1 1)
192 (define_function_unit "imuldiv" 1 0
193 (and (eq_attr "type" "imul")
194 (eq_attr "cpu" "ppc604,ppc620"))
195 4 2)
197 (define_function_unit "imuldiv" 1 0
198 (and (eq_attr "type" "imul")
199 (eq_attr "cpu" "ppc604e"))
200 2 1)
202 (define_function_unit "imuldiv" 1 0
203 (and (eq_attr "type" "idiv")
204 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
205 20 19)
207 ; PPC750 has two integer units: a primary one which can perform all
208 ; operations and a secondary one which is fed in lock step with the first
209 ; and can perform "simple" integer operations.
210 ; To catch this we define a 'dummy' imuldiv-unit that is also needed
211 ; for the complex insns.
212 (define_function_unit "iu2" 2 0
213 (and (eq_attr "type" "integer")
214 (eq_attr "cpu" "ppc750"))
215 1 1)
217 (define_function_unit "iu2" 2 0
218 (and (eq_attr "type" "imul")
219 (eq_attr "cpu" "ppc750"))
220 4 2)
222 (define_function_unit "imuldiv" 1 0
223 (and (eq_attr "type" "imul")
224 (eq_attr "cpu" "ppc750"))
225 4 2)
227 (define_function_unit "imuldiv" 1 0
228 (and (eq_attr "type" "idiv")
229 (eq_attr "cpu" "ppc750"))
230 19 19)
232 ; compare is done on integer unit, but feeds insns which
233 ; execute on the branch unit.
234 (define_function_unit "iu" 1 0
235 (and (eq_attr "type" "compare")
236 (eq_attr "cpu" "rios1"))
237 4 1)
239 (define_function_unit "iu" 1 0
240 (and (eq_attr "type" "delayed_compare")
241 (eq_attr "cpu" "rios1"))
242 5 1)
244 (define_function_unit "iu" 1 0
245 (and (eq_attr "type" "compare,delayed_compare")
246 (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"))
247 3 1)
249 (define_function_unit "iu2" 2 0
250 (and (eq_attr "type" "compare,delayed_compare")
251 (eq_attr "cpu" "rios2"))
252 3 1)
254 (define_function_unit "iu2" 2 0
255 (and (eq_attr "type" "compare,delayed_compare")
256 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc750"))
257 1 1)
259 ; fp compare uses fp unit
260 (define_function_unit "fpu" 1 0
261 (and (eq_attr "type" "fpcompare")
262 (eq_attr "cpu" "rios1"))
263 9 1)
265 ; rios1 and rios2 have different fpcompare delays
266 (define_function_unit "fpu2" 2 0
267 (and (eq_attr "type" "fpcompare")
268 (eq_attr "cpu" "rios2"))
269 5 1)
271 ; on ppc601 and ppc603, fpcompare takes also 2 cycles from
272 ; the integer unit
273 ; here we do not define delays, just occupy the unit. The dependencies
274 ; will be assigned by the fpcompare definition in the fpu.
275 (define_function_unit "iu" 1 0
276 (and (eq_attr "type" "fpcompare")
277 (eq_attr "cpu" "ppc601,ppc603"))
278 0 2)
280 ; fp compare uses fp unit
281 (define_function_unit "fpu" 1 0
282 (and (eq_attr "type" "fpcompare")
283 (eq_attr "cpu" "ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"))
284 5 1)
286 (define_function_unit "fpu" 1 0
287 (and (eq_attr "type" "fpcompare")
288 (eq_attr "cpu" "mpccore"))
289 1 1)
291 (define_function_unit "bpu" 1 0
292 (and (eq_attr "type" "mtjmpr")
293 (eq_attr "cpu" "rios1,rios2"))
294 5 1)
296 (define_function_unit "bpu" 1 0
297 (and (eq_attr "type" "mtjmpr")
298 (eq_attr "cpu" "mpccore,ppc403,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc750"))
299 4 1)
301 ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines.
302 (define_function_unit "bpu" 1 0
303 (eq_attr "type" "jmpreg")
304 1 1)
306 (define_function_unit "bpu" 1 0
307 (eq_attr "type" "branch")
308 1 1)
310 ; Floating Point Unit
311 (define_function_unit "fpu" 1 0
312 (and (eq_attr "type" "fp,dmul")
313 (eq_attr "cpu" "rios1"))
314 2 1)
316 (define_function_unit "fpu" 1 0
317 (and (eq_attr "type" "fp")
318 (eq_attr "cpu" "mpccore"))
319 4 4)
321 (define_function_unit "fpu" 1 0
322 (and (eq_attr "type" "fp")
323 (eq_attr "cpu" "ppc601"))
324 4 1)
326 (define_function_unit "fpu" 1 0
327 (and (eq_attr "type" "fp")
328 (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620,ppc750"))
329 3 1)
331 (define_function_unit "fpu" 1 0
332 (and (eq_attr "type" "dmul")
333 (eq_attr "cpu" "mpccore"))
334 5 5)
336 (define_function_unit "fpu" 1 0
337 (and (eq_attr "type" "dmul")
338 (eq_attr "cpu" "ppc601"))
339 5 2)
341 ; is this true?
342 (define_function_unit "fpu" 1 0
343 (and (eq_attr "type" "dmul")
344 (eq_attr "cpu" "ppc603,ppc750"))
345 4 2)
347 (define_function_unit "fpu" 1 0
348 (and (eq_attr "type" "dmul")
349 (eq_attr "cpu" "ppc604,ppc604e,ppc620"))
350 3 1)
352 (define_function_unit "fpu" 1 0
353 (and (eq_attr "type" "sdiv,ddiv")
354 (eq_attr "cpu" "rios1"))
355 19 19)
357 (define_function_unit "fpu" 1 0
358 (and (eq_attr "type" "sdiv")
359 (eq_attr "cpu" "ppc601"))
360 17 17)
362 (define_function_unit "fpu" 1 0
363 (and (eq_attr "type" "sdiv")
364 (eq_attr "cpu" "mpccore"))
365 10 10)
367 (define_function_unit "fpu" 1 0
368 (and (eq_attr "type" "sdiv")
369 (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620"))
370 18 18)
372 (define_function_unit "fpu" 1 0
373 (and (eq_attr "type" "ddiv")
374 (eq_attr "cpu" "mpccore"))
375 17 17)
377 (define_function_unit "fpu" 1 0
378 (and (eq_attr "type" "ddiv")
379 (eq_attr "cpu" "ppc601,ppc604,ppc604e,ppc620,ppc750"))
380 31 31)
382 (define_function_unit "fpu" 1 0
383 (and (eq_attr "type" "ddiv")
384 (eq_attr "cpu" "ppc603"))
385 33 33)
387 (define_function_unit "fpu" 1 0
388 (and (eq_attr "type" "ssqrt")
389 (eq_attr "cpu" "ppc620"))
390 31 31)
392 (define_function_unit "fpu" 1 0
393 (and (eq_attr "type" "dsqrt")
394 (eq_attr "cpu" "ppc620"))
395 31 31)
397 ; RIOS2 has two symmetric FPUs.
398 (define_function_unit "fpu2" 2 0
399 (and (eq_attr "type" "fp")
400 (eq_attr "cpu" "rios2"))
401 2 1)
403 (define_function_unit "fpu2" 2 0
404 (and (eq_attr "type" "dmul")
405 (eq_attr "cpu" "rios2"))
406 2 1)
408 (define_function_unit "fpu2" 2 0
409 (and (eq_attr "type" "sdiv,ddiv")
410 (eq_attr "cpu" "rios2"))
411 17 17)
413 (define_function_unit "fpu2" 2 0
414 (and (eq_attr "type" "ssqrt,dsqrt")
415 (eq_attr "cpu" "rios2"))
416 26 26)
418 \f
419 ;; Start with fixed-point load and store insns. Here we put only the more
420 ;; complex forms. Basic data transfer is done later.
422 (define_expand "zero_extendqidi2"
423 [(set (match_operand:DI 0 "gpc_reg_operand" "")
424 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
425 "TARGET_POWERPC64"
426 "")
428 (define_insn ""
429 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
430 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
431 "TARGET_POWERPC64"
432 "@
433 lbz%U1%X1 %0,%1
434 rldicl %0,%1,0,56"
435 [(set_attr "type" "load,*")])
437 (define_insn ""
438 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
439 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
440 (const_int 0)))
441 (clobber (match_scratch:DI 2 "=r,r"))]
442 "TARGET_POWERPC64"
443 "@
444 rldicl. %2,%1,0,56
445 #"
446 [(set_attr "type" "compare")
447 (set_attr "length" "4,8")])
449 (define_split
450 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
451 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
452 (const_int 0)))
453 (clobber (match_scratch:DI 2 "=r"))]
454 "TARGET_POWERPC64 && reload_completed"
455 [(set (match_dup 2)
456 (zero_extend:DI (match_dup 1)))
457 (set (match_dup 0)
458 (compare:CC (match_dup 2)
459 (const_int 0)))]
460 "")
462 (define_insn ""
463 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
464 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
465 (const_int 0)))
466 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
467 (zero_extend:DI (match_dup 1)))]
468 "TARGET_POWERPC64"
469 "@
470 rldicl. %0,%1,0,56
471 #"
472 [(set_attr "type" "compare")
473 (set_attr "length" "4,8")])
475 (define_split
476 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
477 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
478 (const_int 0)))
479 (set (match_operand:DI 0 "gpc_reg_operand" "")
480 (zero_extend:DI (match_dup 1)))]
481 "TARGET_POWERPC64 && reload_completed"
482 [(set (match_dup 0)
483 (zero_extend:DI (match_dup 1)))
484 (set (match_dup 2)
485 (compare:CC (match_dup 0)
486 (const_int 0)))]
487 "")
489 (define_insn "extendqidi2"
490 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
491 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
492 "TARGET_POWERPC64"
493 "extsb %0,%1")
495 (define_insn ""
496 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
497 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
498 (const_int 0)))
499 (clobber (match_scratch:DI 2 "=r,r"))]
500 "TARGET_POWERPC64"
501 "@
502 extsb. %2,%1
503 #"
504 [(set_attr "type" "compare")
505 (set_attr "length" "4,8")])
507 (define_split
508 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
509 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
510 (const_int 0)))
511 (clobber (match_scratch:DI 2 ""))]
512 "TARGET_POWERPC64 && reload_completed"
513 [(set (match_dup 2)
514 (sign_extend:DI (match_dup 1)))
515 (set (match_dup 0)
516 (compare:CC (match_dup 2)
517 (const_int 0)))]
518 "")
520 (define_insn ""
521 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
522 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
523 (const_int 0)))
524 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
525 (sign_extend:DI (match_dup 1)))]
526 "TARGET_POWERPC64"
527 "@
528 extsb. %0,%1
529 #"
530 [(set_attr "type" "compare")
531 (set_attr "length" "4,8")])
533 (define_split
534 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
535 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
536 (const_int 0)))
537 (set (match_operand:DI 0 "gpc_reg_operand" "")
538 (sign_extend:DI (match_dup 1)))]
539 "TARGET_POWERPC64 && reload_completed"
540 [(set (match_dup 0)
541 (sign_extend:DI (match_dup 1)))
542 (set (match_dup 2)
543 (compare:CC (match_dup 0)
544 (const_int 0)))]
545 "")
547 (define_expand "zero_extendhidi2"
548 [(set (match_operand:DI 0 "gpc_reg_operand" "")
549 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
550 "TARGET_POWERPC64"
551 "")
553 (define_insn ""
554 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
555 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
556 "TARGET_POWERPC64"
557 "@
558 lhz%U1%X1 %0,%1
559 rldicl %0,%1,0,48"
560 [(set_attr "type" "load,*")])
562 (define_insn ""
563 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
564 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
565 (const_int 0)))
566 (clobber (match_scratch:DI 2 "=r,r"))]
567 "TARGET_POWERPC64"
568 "@
569 rldicl. %2,%1,0,48
570 #"
571 [(set_attr "type" "compare")
572 (set_attr "length" "4,8")])
574 (define_split
575 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
576 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
577 (const_int 0)))
578 (clobber (match_scratch:DI 2 ""))]
579 "TARGET_POWERPC64 && reload_completed"
580 [(set (match_dup 2)
581 (zero_extend:DI (match_dup 1)))
582 (set (match_dup 0)
583 (compare:CC (match_dup 2)
584 (const_int 0)))]
585 "")
587 (define_insn ""
588 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
589 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
590 (const_int 0)))
591 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
592 (zero_extend:DI (match_dup 1)))]
593 "TARGET_POWERPC64"
594 "@
595 rldicl. %0,%1,0,48
596 #"
597 [(set_attr "type" "compare")
598 (set_attr "length" "4,8")])
600 (define_split
601 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
602 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
603 (const_int 0)))
604 (set (match_operand:DI 0 "gpc_reg_operand" "")
605 (zero_extend:DI (match_dup 1)))]
606 "TARGET_POWERPC64 && reload_completed"
607 [(set (match_dup 0)
608 (zero_extend:DI (match_dup 1)))
609 (set (match_dup 2)
610 (compare:CC (match_dup 0)
611 (const_int 0)))]
612 "")
614 (define_expand "extendhidi2"
615 [(set (match_operand:DI 0 "gpc_reg_operand" "")
616 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
617 "TARGET_POWERPC64"
618 "")
620 (define_insn ""
621 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
622 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
623 "TARGET_POWERPC64"
624 "@
625 lha%U1%X1 %0,%1
626 extsh %0,%1"
627 [(set_attr "type" "load,*")])
629 (define_insn ""
630 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
631 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
632 (const_int 0)))
633 (clobber (match_scratch:DI 2 "=r,r"))]
634 "TARGET_POWERPC64"
635 "@
636 extsh. %2,%1
637 #"
638 [(set_attr "type" "compare")
639 (set_attr "length" "4,8")])
641 (define_split
642 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
643 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
644 (const_int 0)))
645 (clobber (match_scratch:DI 2 ""))]
646 "TARGET_POWERPC64 && reload_completed"
647 [(set (match_dup 2)
648 (sign_extend:DI (match_dup 1)))
649 (set (match_dup 0)
650 (compare:CC (match_dup 2)
651 (const_int 0)))]
652 "")
654 (define_insn ""
655 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
656 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
657 (const_int 0)))
658 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
659 (sign_extend:DI (match_dup 1)))]
660 "TARGET_POWERPC64"
661 "@
662 extsh. %0,%1
663 #"
664 [(set_attr "type" "compare")
665 (set_attr "length" "4,8")])
667 (define_split
668 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
669 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
670 (const_int 0)))
671 (set (match_operand:DI 0 "gpc_reg_operand" "")
672 (sign_extend:DI (match_dup 1)))]
673 "TARGET_POWERPC64 && reload_completed"
674 [(set (match_dup 0)
675 (sign_extend:DI (match_dup 1)))
676 (set (match_dup 2)
677 (compare:CC (match_dup 0)
678 (const_int 0)))]
679 "")
681 (define_expand "zero_extendsidi2"
682 [(set (match_operand:DI 0 "gpc_reg_operand" "")
683 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
684 "TARGET_POWERPC64"
685 "")
687 (define_insn ""
688 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
689 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
690 "TARGET_POWERPC64"
691 "@
692 lwz%U1%X1 %0,%1
693 rldicl %0,%1,0,32"
694 [(set_attr "type" "load,*")])
696 (define_insn ""
697 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
698 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
699 (const_int 0)))
700 (clobber (match_scratch:DI 2 "=r,r"))]
701 "TARGET_POWERPC64"
702 "@
703 rldicl. %2,%1,0,32
704 #"
705 [(set_attr "type" "compare")
706 (set_attr "length" "4,8")])
708 (define_split
709 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
710 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
711 (const_int 0)))
712 (clobber (match_scratch:DI 2 ""))]
713 "TARGET_POWERPC64 && reload_completed"
714 [(set (match_dup 2)
715 (zero_extend:DI (match_dup 1)))
716 (set (match_dup 0)
717 (compare:CC (match_dup 2)
718 (const_int 0)))]
719 "")
721 (define_insn ""
722 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
723 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
724 (const_int 0)))
725 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
726 (zero_extend:DI (match_dup 1)))]
727 "TARGET_POWERPC64"
728 "@
729 rldicl. %0,%1,0,32
730 #"
731 [(set_attr "type" "compare")
732 (set_attr "length" "4,8")])
734 (define_split
735 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
736 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
737 (const_int 0)))
738 (set (match_operand:DI 0 "gpc_reg_operand" "")
739 (zero_extend:DI (match_dup 1)))]
740 "TARGET_POWERPC64 && reload_completed"
741 [(set (match_dup 0)
742 (zero_extend:DI (match_dup 1)))
743 (set (match_dup 2)
744 (compare:CC (match_dup 0)
745 (const_int 0)))]
746 "")
748 (define_expand "extendsidi2"
749 [(set (match_operand:DI 0 "gpc_reg_operand" "")
750 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
751 "TARGET_POWERPC64"
752 "")
754 (define_insn ""
755 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
756 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
757 "TARGET_POWERPC64"
758 "@
759 lwa%U1%X1 %0,%1
760 extsw %0,%1"
761 [(set_attr "type" "load,*")])
763 (define_insn ""
764 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
765 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
766 (const_int 0)))
767 (clobber (match_scratch:DI 2 "=r,r"))]
768 "TARGET_POWERPC64"
769 "@
770 extsw. %2,%1
771 #"
772 [(set_attr "type" "compare")
773 (set_attr "length" "4,8")])
775 (define_split
776 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
777 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
778 (const_int 0)))
779 (clobber (match_scratch:DI 2 ""))]
780 "TARGET_POWERPC64 && reload_completed"
781 [(set (match_dup 2)
782 (sign_extend:DI (match_dup 1)))
783 (set (match_dup 0)
784 (compare:CC (match_dup 2)
785 (const_int 0)))]
786 "")
788 (define_insn ""
789 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
790 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
791 (const_int 0)))
792 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
793 (sign_extend:DI (match_dup 1)))]
794 "TARGET_POWERPC64"
795 "@
796 extsw. %0,%1
797 #"
798 [(set_attr "type" "compare")
799 (set_attr "length" "4,8")])
801 (define_split
802 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
803 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
804 (const_int 0)))
805 (set (match_operand:DI 0 "gpc_reg_operand" "")
806 (sign_extend:DI (match_dup 1)))]
807 "TARGET_POWERPC64 && reload_completed"
808 [(set (match_dup 0)
809 (sign_extend:DI (match_dup 1)))
810 (set (match_dup 2)
811 (compare:CC (match_dup 0)
812 (const_int 0)))]
813 "")
815 (define_expand "zero_extendqisi2"
816 [(set (match_operand:SI 0 "gpc_reg_operand" "")
817 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
818 ""
819 "")
821 (define_insn ""
822 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
823 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
824 ""
825 "@
826 lbz%U1%X1 %0,%1
827 {rlinm|rlwinm} %0,%1,0,0xff"
828 [(set_attr "type" "load,*")])
830 (define_insn ""
831 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
832 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
833 (const_int 0)))
834 (clobber (match_scratch:SI 2 "=r,r"))]
835 ""
836 "@
837 {andil.|andi.} %2,%1,0xff
838 #"
839 [(set_attr "type" "compare")
840 (set_attr "length" "4,8")])
842 (define_split
843 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
844 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
845 (const_int 0)))
846 (clobber (match_scratch:SI 2 ""))]
847 "reload_completed"
848 [(set (match_dup 2)
849 (zero_extend:SI (match_dup 1)))
850 (set (match_dup 0)
851 (compare:CC (match_dup 2)
852 (const_int 0)))]
853 "")
855 (define_insn ""
856 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
857 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
858 (const_int 0)))
859 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
860 (zero_extend:SI (match_dup 1)))]
861 ""
862 "@
863 {andil.|andi.} %0,%1,0xff
864 #"
865 [(set_attr "type" "compare")
866 (set_attr "length" "4,8")])
868 (define_split
869 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
870 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
871 (const_int 0)))
872 (set (match_operand:SI 0 "gpc_reg_operand" "")
873 (zero_extend:SI (match_dup 1)))]
874 "reload_completed"
875 [(set (match_dup 0)
876 (zero_extend:SI (match_dup 1)))
877 (set (match_dup 2)
878 (compare:CC (match_dup 0)
879 (const_int 0)))]
880 "")
882 (define_expand "extendqisi2"
883 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
884 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
885 ""
886 "
887 {
888 if (TARGET_POWERPC)
889 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
890 else if (TARGET_POWER)
891 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
892 else
893 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
894 DONE;
895 }")
897 (define_insn "extendqisi2_ppc"
898 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
899 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
900 "TARGET_POWERPC"
901 "extsb %0,%1")
903 (define_insn ""
904 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
905 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
906 (const_int 0)))
907 (clobber (match_scratch:SI 2 "=r,r"))]
908 "TARGET_POWERPC"
909 "@
910 extsb. %2,%1
911 #"
912 [(set_attr "type" "compare")
913 (set_attr "length" "4,8")])
915 (define_split
916 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
917 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
918 (const_int 0)))
919 (clobber (match_scratch:SI 2 ""))]
920 "TARGET_POWERPC && reload_completed"
921 [(set (match_dup 2)
922 (sign_extend:SI (match_dup 1)))
923 (set (match_dup 0)
924 (compare:CC (match_dup 2)
925 (const_int 0)))]
926 "")
928 (define_insn ""
929 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
930 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
931 (const_int 0)))
932 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
933 (sign_extend:SI (match_dup 1)))]
934 "TARGET_POWERPC"
935 "@
936 extsb. %0,%1
937 #"
938 [(set_attr "type" "compare")
939 (set_attr "length" "4,8")])
941 (define_split
942 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
943 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
944 (const_int 0)))
945 (set (match_operand:SI 0 "gpc_reg_operand" "")
946 (sign_extend:SI (match_dup 1)))]
947 "TARGET_POWERPC && reload_completed"
948 [(set (match_dup 0)
949 (sign_extend:SI (match_dup 1)))
950 (set (match_dup 2)
951 (compare:CC (match_dup 0)
952 (const_int 0)))]
953 "")
955 (define_expand "extendqisi2_power"
956 [(parallel [(set (match_dup 2)
957 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
958 (const_int 24)))
959 (clobber (scratch:SI))])
960 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
961 (ashiftrt:SI (match_dup 2)
962 (const_int 24)))
963 (clobber (scratch:SI))])]
964 "TARGET_POWER"
965 "
966 { operands[1] = gen_lowpart (SImode, operands[1]);
967 operands[2] = gen_reg_rtx (SImode); }")
969 (define_expand "extendqisi2_no_power"
970 [(set (match_dup 2)
971 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
972 (const_int 24)))
973 (set (match_operand:SI 0 "gpc_reg_operand" "")
974 (ashiftrt:SI (match_dup 2)
975 (const_int 24)))]
976 "! TARGET_POWER && ! TARGET_POWERPC"
977 "
978 { operands[1] = gen_lowpart (SImode, operands[1]);
979 operands[2] = gen_reg_rtx (SImode); }")
981 (define_expand "zero_extendqihi2"
982 [(set (match_operand:HI 0 "gpc_reg_operand" "")
983 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
984 ""
985 "")
987 (define_insn ""
988 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
989 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
990 ""
991 "@
992 lbz%U1%X1 %0,%1
993 {rlinm|rlwinm} %0,%1,0,0xff"
994 [(set_attr "type" "load,*")])
996 (define_insn ""
997 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
998 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
999 (const_int 0)))
1000 (clobber (match_scratch:HI 2 "=r,r"))]
1001 ""
1002 "@
1003 {andil.|andi.} %2,%1,0xff
1004 #"
1005 [(set_attr "type" "compare")
1006 (set_attr "length" "4,8")])
1008 (define_split
1009 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1010 (compare:CC (zero_extend:HI (match_operand:HI 1 "gpc_reg_operand" ""))
1011 (const_int 0)))
1012 (clobber (match_scratch:SI 2 ""))]
1013 "reload_completed"
1014 [(set (match_dup 2)
1015 (zero_extend:SI (match_dup 1)))
1016 (set (match_dup 0)
1017 (compare:CC (match_dup 3)
1018 (const_int 0)))]
1019 "
1020 {
1021 rtx reg;
1022 int offset;
1023 if (GET_CODE (operands[2]) == REG)
1024 {
1025 reg = operands[2];
1026 offset = 0;
1027 }
1028 else if (GET_CODE (operands[2]) == SUBREG)
1029 {
1030 reg = SUBREG_REG (operands[2]);
1031 offset = SUBREG_WORD (operands[2]);
1032 }
1033 else
1034 abort ();
1036 operands[3] = gen_rtx_SUBREG (SImode, reg, offset);
1037 }")
1039 (define_insn ""
1040 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1041 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1042 (const_int 0)))
1043 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1044 (zero_extend:HI (match_dup 1)))]
1045 ""
1046 "@
1047 {andil.|andi.} %0,%1,0xff
1048 #"
1049 [(set_attr "type" "compare")
1050 (set_attr "length" "4,8")])
1052 (define_split
1053 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1054 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1055 (const_int 0)))
1056 (set (match_operand:HI 0 "gpc_reg_operand" "")
1057 (zero_extend:HI (match_dup 1)))]
1058 "reload_completed"
1059 [(set (match_dup 0)
1060 (zero_extend:HI (match_dup 1)))
1061 (set (match_dup 2)
1062 (compare:CC (match_dup 3)
1063 (const_int 0)))]
1064 "
1065 {
1066 rtx reg;
1067 int offset;
1068 if (GET_CODE (operands[0]) == REG)
1069 {
1070 reg = operands[2];
1071 offset = 0;
1072 }
1073 else if (GET_CODE (operands[2]) == SUBREG)
1074 {
1075 reg = SUBREG_REG (operands[2]);
1076 offset = SUBREG_WORD (operands[2]);
1077 }
1078 else
1079 abort ();
1081 operands[3] = gen_rtx_SUBREG (SImode, reg, offset);
1082 }")
1084 (define_expand "extendqihi2"
1085 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
1086 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
1087 ""
1088 "
1089 {
1090 if (TARGET_POWERPC)
1091 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
1092 else if (TARGET_POWER)
1093 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
1094 else
1095 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
1096 DONE;
1097 }")
1099 (define_insn "extendqihi2_ppc"
1100 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
1101 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
1102 "TARGET_POWERPC"
1103 "extsb %0,%1")
1105 (define_insn ""
1106 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1107 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1108 (const_int 0)))
1109 (clobber (match_scratch:HI 2 "=r,r"))]
1110 "TARGET_POWERPC"
1111 "@
1112 extsb. %2,%1
1113 #"
1114 [(set_attr "type" "compare")
1115 (set_attr "length" "4,8")])
1117 (define_split
1118 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1119 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1120 (const_int 0)))
1121 (clobber (match_scratch:HI 2 ""))]
1122 "TARGET_POWERPC && reload_completed"
1123 [(set (match_dup 2)
1124 (zero_extend:HI (match_dup 1)))
1125 (set (match_dup 0)
1126 (compare:CC (match_dup 3)
1127 (const_int 0)))]
1128 "
1129 {
1130 rtx reg;
1131 int offset;
1132 if (GET_CODE (operands[2]) == REG)
1133 {
1134 reg = operands[2];
1135 offset = 0;
1136 }
1137 else if (GET_CODE (operands[2]) == SUBREG)
1138 {
1139 reg = SUBREG_REG (operands[2]);
1140 offset = SUBREG_WORD (operands[2]);
1141 }
1142 else
1143 abort ();
1145 operands[3] = gen_rtx_SUBREG (SImode, reg, offset);
1146 }")
1148 (define_insn ""
1149 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1150 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1151 (const_int 0)))
1152 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1153 (sign_extend:HI (match_dup 1)))]
1154 "TARGET_POWERPC"
1155 "@
1156 extsb. %0,%1
1157 #"
1158 [(set_attr "type" "compare")
1159 (set_attr "length" "4,8")])
1161 (define_split
1162 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1163 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1164 (const_int 0)))
1165 (set (match_operand:HI 0 "gpc_reg_operand" "")
1166 (sign_extend:HI (match_dup 1)))]
1167 "TARGET_POWERPC && reload_completed"
1168 [(set (match_dup 0)
1169 (zero_extend:HI (match_dup 1)))
1170 (set (match_dup 2)
1171 (compare:CC (match_dup 3)
1172 (const_int 0)))]
1173 "
1174 {
1175 rtx reg;
1176 int offset;
1177 if (GET_CODE (operands[0]) == REG)
1178 {
1179 reg = operands[0];
1180 offset = 0;
1181 }
1182 else if (GET_CODE (operands[0]) == SUBREG)
1183 {
1184 reg = SUBREG_REG (operands[0]);
1185 offset = SUBREG_WORD (operands[0]);
1186 }
1187 else
1188 abort ();
1190 operands[3] = gen_rtx_SUBREG (SImode, reg, offset);
1191 }")
1193 (define_expand "extendqihi2_power"
1194 [(parallel [(set (match_dup 2)
1195 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1196 (const_int 24)))
1197 (clobber (scratch:SI))])
1198 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
1199 (ashiftrt:SI (match_dup 2)
1200 (const_int 24)))
1201 (clobber (scratch:SI))])]
1202 "TARGET_POWER"
1203 "
1204 { operands[0] = gen_lowpart (SImode, operands[0]);
1205 operands[1] = gen_lowpart (SImode, operands[1]);
1206 operands[2] = gen_reg_rtx (SImode); }")
1208 (define_expand "extendqihi2_no_power"
1209 [(set (match_dup 2)
1210 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1211 (const_int 24)))
1212 (set (match_operand:HI 0 "gpc_reg_operand" "")
1213 (ashiftrt:SI (match_dup 2)
1214 (const_int 24)))]
1215 "! TARGET_POWER && ! TARGET_POWERPC"
1216 "
1217 { operands[0] = gen_lowpart (SImode, operands[0]);
1218 operands[1] = gen_lowpart (SImode, operands[1]);
1219 operands[2] = gen_reg_rtx (SImode); }")
1221 (define_expand "zero_extendhisi2"
1222 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1223 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1224 ""
1225 "")
1227 (define_insn ""
1228 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1229 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1230 ""
1231 "@
1232 lhz%U1%X1 %0,%1
1233 {rlinm|rlwinm} %0,%1,0,0xffff"
1234 [(set_attr "type" "load,*")])
1236 (define_insn ""
1237 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1238 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1239 (const_int 0)))
1240 (clobber (match_scratch:SI 2 "=r,r"))]
1241 ""
1242 "@
1243 {andil.|andi.} %2,%1,0xffff
1244 #"
1245 [(set_attr "type" "compare")
1246 (set_attr "length" "4,8")])
1248 (define_split
1249 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1250 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1251 (const_int 0)))
1252 (clobber (match_scratch:SI 2 ""))]
1253 "reload_completed"
1254 [(set (match_dup 2)
1255 (zero_extend:SI (match_dup 1)))
1256 (set (match_dup 0)
1257 (compare:CC (match_dup 2)
1258 (const_int 0)))]
1259 "")
1261 (define_insn ""
1262 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1263 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1264 (const_int 0)))
1265 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1266 (zero_extend:SI (match_dup 1)))]
1267 ""
1268 "@
1269 {andil.|andi.} %0,%1,0xffff
1270 #"
1271 [(set_attr "type" "compare")
1272 (set_attr "length" "4,8")])
1274 (define_split
1275 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1276 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1277 (const_int 0)))
1278 (set (match_operand:SI 0 "gpc_reg_operand" "")
1279 (zero_extend:SI (match_dup 1)))]
1280 "reload_completed"
1281 [(set (match_dup 0)
1282 (zero_extend:SI (match_dup 1)))
1283 (set (match_dup 2)
1284 (compare:CC (match_dup 0)
1285 (const_int 0)))]
1286 "")
1288 (define_expand "extendhisi2"
1289 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1290 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1291 ""
1292 "")
1294 (define_insn ""
1295 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1296 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1297 ""
1298 "@
1299 lha%U1%X1 %0,%1
1300 {exts|extsh} %0,%1"
1301 [(set_attr "type" "load,*")])
1303 (define_insn ""
1304 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1305 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1306 (const_int 0)))
1307 (clobber (match_scratch:SI 2 "=r,r"))]
1308 ""
1309 "@
1310 {exts.|extsh.} %2,%1
1311 #"
1312 [(set_attr "type" "compare")
1313 (set_attr "length" "4,8")])
1315 (define_insn ""
1316 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "=x,?y")
1317 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1318 (const_int 0)))
1319 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1320 (sign_extend:SI (match_dup 1)))]
1321 ""
1322 "@
1323 {exts.|extsh.} %0,%1
1324 #"
1325 [(set_attr "type" "compare")
1326 (set_attr "length" "4,8")])
1328 (define_split
1329 [(set (match_operand:CC 2 "cc_reg_operand" "")
1330 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1331 (const_int 0)))
1332 (set (match_operand:SI 0 "gpc_reg_operand" "")
1333 (sign_extend:SI (match_dup 1)))]
1334 "reload_completed"
1335 [(set (match_dup 0)
1336 (sign_extend:SI (match_dup 1)))
1337 (set (match_dup 2)
1338 (compare:CC (match_dup 0)
1339 (const_int 0)))]
1340 "")
1342 \f
1343 ;; Fixed-point arithmetic insns.
1345 ;; Discourage ai/addic because of carry but provide it in an alternative
1346 ;; allowing register zero as source.
1347 (define_expand "addsi3"
1348 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1349 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1350 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1351 ""
1352 "
1353 {
1354 if (GET_CODE (operands[2]) == CONST_INT && !add_operand (operands[2], SImode))
1355 {
1356 rtx tmp = ((reload_in_progress || reload_completed
1357 || rtx_equal_p (operands[0], operands[1]))
1358 ? operands[0] : gen_reg_rtx (SImode));
1360 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
1361 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
1363 if (low & 0x8000)
1364 high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
1366 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (high)));
1367 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
1368 DONE;
1369 }
1370 }")
1372 (define_insn "*addsi3_internal1"
1373 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
1374 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
1375 (match_operand:SI 2 "add_operand" "r,I,I,J")))]
1376 ""
1377 "@
1378 {cax|add} %0,%1,%2
1379 {cal %0,%2(%1)|addi %0,%1,%2}
1380 {ai|addic} %0,%1,%2
1381 {cau|addis} %0,%1,%v2"
1382 [(set_attr "length" "4,4,4,4")])
1384 (define_insn "*addsi3_internal2"
1385 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1386 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1387 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1388 (const_int 0)))
1389 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1390 ""
1391 "@
1392 {cax.|add.} %3,%1,%2
1393 {ai.|addic.} %3,%1,%2
1394 #
1395 #"
1396 [(set_attr "type" "compare")
1397 (set_attr "length" "4,4,8,8")])
1399 (define_split
1400 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1401 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1402 (match_operand:SI 2 "reg_or_short_operand" ""))
1403 (const_int 0)))
1404 (clobber (match_scratch:SI 3 ""))]
1405 "reload_completed"
1406 [(set (match_dup 3)
1407 (plus:SI (match_dup 1)
1408 (match_dup 2)))
1409 (set (match_dup 0)
1410 (compare:CC (match_dup 3)
1411 (const_int 0)))]
1412 "")
1414 (define_insn "*addsi3_internal3"
1415 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1416 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1417 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1418 (const_int 0)))
1419 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1420 (plus:SI (match_dup 1)
1421 (match_dup 2)))]
1422 ""
1423 "@
1424 {cax.|add.} %0,%1,%2
1425 {ai.|addic.} %0,%1,%2
1426 #
1427 #"
1428 [(set_attr "type" "compare")
1429 (set_attr "length" "4,4,8,8")])
1431 (define_split
1432 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1433 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1434 (match_operand:SI 2 "reg_or_short_operand" ""))
1435 (const_int 0)))
1436 (set (match_operand:SI 0 "gpc_reg_operand" "")
1437 (plus:SI (match_dup 1) (match_dup 2)))]
1438 "reload_completed"
1439 [(set (match_dup 0)
1440 (plus:SI (match_dup 1)
1441 (match_dup 2)))
1442 (set (match_dup 3)
1443 (compare:CC (match_dup 0)
1444 (const_int 0)))]
1445 "")
1447 ;; Split an add that we can't do in one insn into two insns, each of which
1448 ;; does one 16-bit part. This is used by combine. Note that the low-order
1449 ;; add should be last in case the result gets used in an address.
1451 (define_split
1452 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1453 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1454 (match_operand:SI 2 "non_add_cint_operand" "")))]
1455 ""
1456 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1457 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1458 "
1459 {
1460 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
1461 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
1463 if (low & 0x8000)
1464 high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
1466 operands[3] = GEN_INT (high);
1467 operands[4] = GEN_INT (low);
1468 }")
1470 (define_insn "one_cmplsi2"
1471 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1472 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1473 ""
1474 "nor %0,%1,%1")
1476 (define_insn ""
1477 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1478 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1479 (const_int 0)))
1480 (clobber (match_scratch:SI 2 "=r,r"))]
1481 ""
1482 "@
1483 nor. %2,%1,%1
1484 #"
1485 [(set_attr "type" "compare")
1486 (set_attr "length" "4,8")])
1488 (define_split
1489 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1490 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1491 (const_int 0)))
1492 (clobber (match_scratch:SI 2 ""))]
1493 "reload_completed"
1494 [(set (match_dup 2)
1495 (not:SI (match_dup 1)))
1496 (set (match_dup 0)
1497 (compare:CC (match_dup 2)
1498 (const_int 0)))]
1499 "")
1501 (define_insn ""
1502 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1503 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1504 (const_int 0)))
1505 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1506 (not:SI (match_dup 1)))]
1507 ""
1508 "@
1509 nor. %0,%1,%1
1510 #"
1511 [(set_attr "type" "compare")
1512 (set_attr "length" "4,8")])
1514 (define_split
1515 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1516 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1517 (const_int 0)))
1518 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1519 (not:SI (match_dup 1)))]
1520 "reload_completed"
1521 [(set (match_dup 0)
1522 (not:SI (match_dup 1)))
1523 (set (match_dup 2)
1524 (compare:CC (match_dup 0)
1525 (const_int 0)))]
1526 "")
1528 (define_insn ""
1529 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1530 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1531 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1532 "! TARGET_POWERPC"
1533 "{sf%I1|subf%I1c} %0,%2,%1")
1535 (define_insn ""
1536 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1537 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1538 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1539 "TARGET_POWERPC"
1540 "@
1541 subf %0,%2,%1
1542 subfic %0,%2,%1")
1544 (define_insn ""
1545 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1546 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1547 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1548 (const_int 0)))
1549 (clobber (match_scratch:SI 3 "=r,r"))]
1550 "! TARGET_POWERPC"
1551 "@
1552 {sf.|subfc.} %3,%2,%1
1553 #"
1554 [(set_attr "type" "compare")
1555 (set_attr "length" "4,8")])
1557 (define_split
1558 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1559 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1560 (match_operand:SI 2 "gpc_reg_operand" ""))
1561 (const_int 0)))
1562 (clobber (match_scratch:SI 3 ""))]
1563 "! TARGET_POWERPC && reload_completed"
1564 [(set (match_dup 3)
1565 (minus:SI (match_dup 1)
1566 (match_dup 2)))
1567 (set (match_dup 0)
1568 (compare:CC (match_dup 3)
1569 (const_int 0)))]
1570 "")
1572 (define_insn ""
1573 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1574 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1575 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1576 (const_int 0)))
1577 (clobber (match_scratch:SI 3 "=r,r"))]
1578 "TARGET_POWERPC"
1579 "@
1580 subf. %3,%2,%1
1581 #"
1582 [(set_attr "type" "compare")
1583 (set_attr "length" "4,8")])
1585 (define_split
1586 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1587 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1588 (match_operand:SI 2 "gpc_reg_operand" ""))
1589 (const_int 0)))
1590 (clobber (match_scratch:SI 3 ""))]
1591 "TARGET_POWERPC && reload_completed"
1592 [(set (match_dup 3)
1593 (minus:SI (match_dup 1)
1594 (match_dup 2)))
1595 (set (match_dup 0)
1596 (compare:CC (match_dup 3)
1597 (const_int 0)))]
1598 "")
1600 (define_insn ""
1601 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1602 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1603 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1604 (const_int 0)))
1605 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1606 (minus:SI (match_dup 1) (match_dup 2)))]
1607 "! TARGET_POWERPC"
1608 "@
1609 {sf.|subfc.} %0,%2,%1
1610 #"
1611 [(set_attr "type" "compare")
1612 (set_attr "length" "4,8")])
1614 (define_split
1615 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1616 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1617 (match_operand:SI 2 "gpc_reg_operand" ""))
1618 (const_int 0)))
1619 (set (match_operand:SI 0 "gpc_reg_operand" "")
1620 (minus:SI (match_dup 1)
1621 (match_dup 2)))]
1622 "reload_completed"
1623 [(set (match_dup 0)
1624 (minus:SI (match_dup 1)
1625 (match_dup 2)))
1626 (set (match_dup 3)
1627 (compare:CC (match_dup 0)
1628 (const_int 0)))]
1629 "")
1631 (define_insn ""
1632 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1633 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1634 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1635 (const_int 0)))
1636 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1637 (minus:SI (match_dup 1)
1638 (match_dup 2)))]
1639 "TARGET_POWERPC"
1640 "subf. %0,%2,%1"
1641 [(set_attr "type" "compare")
1642 (set_attr "length" "4,8")])
1644 (define_split
1645 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1646 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1647 (match_operand:SI 2 "reg_or_short_operand" ""))
1648 (const_int 0)))
1649 (set (match_operand:SI 0 "gpc_reg_operand" "")
1650 (minus:SI (match_dup 1)
1651 (match_dup 2)))]
1652 "TARGET_POWERPC && reload_completed"
1653 [(set (match_dup 0)
1654 (minus:SI (match_dup 1)
1655 (match_dup 2)))
1656 (set (match_dup 3)
1657 (compare:CC (match_dup 0)
1658 (const_int 0)))]
1659 "")
1661 (define_expand "subsi3"
1662 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1663 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
1664 (match_operand:SI 2 "reg_or_cint_operand" "")))]
1665 ""
1666 "
1667 {
1668 if (GET_CODE (operands[2]) == CONST_INT)
1669 {
1670 emit_insn (gen_addsi3 (operands[0], operands[1],
1671 negate_rtx (SImode, operands[2])));
1672 DONE;
1673 }
1674 }")
1676 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1677 ;; instruction and some auxiliary computations. Then we just have a single
1678 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1679 ;; combine.
1681 (define_expand "sminsi3"
1682 [(set (match_dup 3)
1683 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1684 (match_operand:SI 2 "reg_or_short_operand" ""))
1685 (const_int 0)
1686 (minus:SI (match_dup 2) (match_dup 1))))
1687 (set (match_operand:SI 0 "gpc_reg_operand" "")
1688 (minus:SI (match_dup 2) (match_dup 3)))]
1689 "TARGET_POWER"
1690 "
1691 { operands[3] = gen_reg_rtx (SImode); }")
1693 (define_split
1694 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1695 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1696 (match_operand:SI 2 "reg_or_short_operand" "")))
1697 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1698 "TARGET_POWER"
1699 [(set (match_dup 3)
1700 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1701 (const_int 0)
1702 (minus:SI (match_dup 2) (match_dup 1))))
1703 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1704 "")
1706 (define_expand "smaxsi3"
1707 [(set (match_dup 3)
1708 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1709 (match_operand:SI 2 "reg_or_short_operand" ""))
1710 (const_int 0)
1711 (minus:SI (match_dup 2) (match_dup 1))))
1712 (set (match_operand:SI 0 "gpc_reg_operand" "")
1713 (plus:SI (match_dup 3) (match_dup 1)))]
1714 "TARGET_POWER"
1715 "
1716 { operands[3] = gen_reg_rtx (SImode); }")
1718 (define_split
1719 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1720 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1721 (match_operand:SI 2 "reg_or_short_operand" "")))
1722 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1723 "TARGET_POWER"
1724 [(set (match_dup 3)
1725 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1726 (const_int 0)
1727 (minus:SI (match_dup 2) (match_dup 1))))
1728 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1729 "")
1731 (define_expand "uminsi3"
1732 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1733 (match_dup 5)))
1734 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1735 (match_dup 5)))
1736 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1737 (const_int 0)
1738 (minus:SI (match_dup 4) (match_dup 3))))
1739 (set (match_operand:SI 0 "gpc_reg_operand" "")
1740 (minus:SI (match_dup 2) (match_dup 3)))]
1741 "TARGET_POWER"
1742 "
1743 {
1744 operands[3] = gen_reg_rtx (SImode);
1745 operands[4] = gen_reg_rtx (SImode);
1746 operands[5] = GEN_INT (-2147483647 - 1);
1747 }")
1749 (define_expand "umaxsi3"
1750 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1751 (match_dup 5)))
1752 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1753 (match_dup 5)))
1754 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1755 (const_int 0)
1756 (minus:SI (match_dup 4) (match_dup 3))))
1757 (set (match_operand:SI 0 "gpc_reg_operand" "")
1758 (plus:SI (match_dup 3) (match_dup 1)))]
1759 "TARGET_POWER"
1760 "
1761 {
1762 operands[3] = gen_reg_rtx (SImode);
1763 operands[4] = gen_reg_rtx (SImode);
1764 operands[5] = GEN_INT (-2147483647 - 1);
1765 }")
1767 (define_insn ""
1768 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1769 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1770 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1771 (const_int 0)
1772 (minus:SI (match_dup 2) (match_dup 1))))]
1773 "TARGET_POWER"
1774 "doz%I2 %0,%1,%2")
1776 (define_insn ""
1777 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1778 (compare:CC
1779 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1780 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1781 (const_int 0)
1782 (minus:SI (match_dup 2) (match_dup 1)))
1783 (const_int 0)))
1784 (clobber (match_scratch:SI 3 "=r,r"))]
1785 "TARGET_POWER"
1786 "@
1787 doz%I2. %3,%1,%2
1788 #"
1789 [(set_attr "type" "delayed_compare")
1790 (set_attr "length" "4,8")])
1792 (define_split
1793 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "=x,?y")
1794 (compare:CC
1795 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1796 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1797 (const_int 0)
1798 (minus:SI (match_dup 2) (match_dup 1)))
1799 (const_int 0)))
1800 (clobber (match_scratch:SI 3 "=r,r"))]
1801 "TARGET_POWER && reload_completed"
1802 [(set (match_dup 3)
1803 (if_then_else:SI (gt (match_dup 1)
1804 (match_dup 2))
1805 (const_int 0)
1806 (minus:SI (match_dup 2)
1807 (match_dup 1))))
1808 (set (match_dup 0)
1809 (compare:CC (match_dup 3)
1810 (const_int 0)))]
1811 "")
1813 (define_insn ""
1814 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1815 (compare:CC
1816 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1817 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1818 (const_int 0)
1819 (minus:SI (match_dup 2) (match_dup 1)))
1820 (const_int 0)))
1821 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1822 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
1823 (const_int 0)
1824 (minus:SI (match_dup 2) (match_dup 1))))]
1825 "TARGET_POWER"
1826 "doz%I2. %0,%1,%2"
1827 [(set_attr "type" "delayed_compare")])
1829 (define_split
1830 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "=x,?y")
1831 (compare:CC
1832 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1833 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1834 (const_int 0)
1835 (minus:SI (match_dup 2) (match_dup 1)))
1836 (const_int 0)))
1837 (set (match_operand:SI 0 "gpc_reg_operand" "")
1838 (if_then_else:SI (gt (match_dup 1)
1839 (match_dup 2))
1840 (const_int 0)
1841 (minus:SI (match_dup 2)
1842 (match_dup 1))))]
1843 "TARGET_POWER && reload_completed"
1844 [(set (match_dup 0)
1845 (if_then_else:SI (gt (match_dup 1)
1846 (match_dup 2))
1847 (const_int 0)
1848 (minus:SI (match_dup 2)
1849 (match_dup 1))))
1850 (set (match_dup 3)
1851 (compare:CC (match_dup 0)
1852 (const_int 0)))]
1853 "")
1855 ;; We don't need abs with condition code because such comparisons should
1856 ;; never be done.
1857 (define_expand "abssi2"
1858 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1859 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1860 ""
1861 "
1862 {
1863 if (!TARGET_POWER)
1864 {
1865 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1866 DONE;
1867 }
1868 }")
1870 (define_insn "abssi2_power"
1871 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1872 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1873 "TARGET_POWER"
1874 "abs %0,%1")
1876 (define_insn "abssi2_nopower"
1877 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1878 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1879 (clobber (match_scratch:SI 2 "=&r,&r"))]
1880 "!TARGET_POWER"
1881 "*
1882 {
1883 return (TARGET_POWERPC)
1884 ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\"
1885 : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\";
1886 }"
1887 [(set_attr "length" "12")])
1889 (define_split
1890 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1891 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
1892 (clobber (match_scratch:SI 2 "=&r,&r"))]
1893 "!TARGET_POWER && reload_completed"
1894 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1895 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1896 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
1897 "")
1899 (define_insn "*nabs_power"
1900 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1901 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
1902 "TARGET_POWER"
1903 "nabs %0,%1")
1905 (define_insn "*nabs_no_power"
1906 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1907 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1908 (clobber (match_scratch:SI 2 "=&r,&r"))]
1909 "!TARGET_POWER"
1910 "*
1911 {
1912 return (TARGET_POWERPC)
1913 ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\"
1914 : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\";
1915 }"
1916 [(set_attr "length" "12")])
1918 (define_split
1919 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
1920 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
1921 (clobber (match_scratch:SI 2 "=&r,&r"))]
1922 "!TARGET_POWER && reload_completed"
1923 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
1924 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
1925 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
1926 "")
1928 (define_insn "negsi2"
1929 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1930 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1931 ""
1932 "neg %0,%1")
1934 (define_insn ""
1935 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1936 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1937 (const_int 0)))
1938 (clobber (match_scratch:SI 2 "=r,r"))]
1939 ""
1940 "@
1941 neg. %2,%1
1942 #"
1943 [(set_attr "type" "compare")
1944 (set_attr "length" "4,8")])
1946 (define_split
1947 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1948 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1949 (const_int 0)))
1950 (clobber (match_scratch:SI 2 ""))]
1951 "reload_completed"
1952 [(set (match_dup 2)
1953 (neg:SI (match_dup 1)))
1954 (set (match_dup 0)
1955 (compare:CC (match_dup 2)
1956 (const_int 0)))]
1957 "")
1959 (define_insn ""
1960 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1961 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1962 (const_int 0)))
1963 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1964 (neg:SI (match_dup 1)))]
1965 ""
1966 "@
1967 neg. %0,%1
1968 #"
1969 [(set_attr "type" "compare")
1970 (set_attr "length" "4,8")])
1972 (define_split
1973 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1974 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1975 (const_int 0)))
1976 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1977 (neg:SI (match_dup 1)))]
1978 "reload_completed"
1979 [(set (match_dup 0)
1980 (neg:SI (match_dup 1)))
1981 (set (match_dup 2)
1982 (compare:CC (match_dup 0)
1983 (const_int 0)))]
1984 "")
1986 (define_insn "ffssi2"
1987 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
1988 (ffs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1989 ""
1990 "neg %0,%1\;and %0,%0,%1\;{cntlz|cntlzw} %0,%0\;{sfi|subfic} %0,%0,32"
1991 [(set_attr "length" "16")])
1993 (define_expand "mulsi3"
1994 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1995 (use (match_operand:SI 1 "gpc_reg_operand" ""))
1996 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
1997 ""
1998 "
1999 {
2000 if (TARGET_POWER)
2001 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2002 else
2003 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2004 DONE;
2005 }")
2007 (define_insn "mulsi3_mq"
2008 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2009 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2010 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2011 (clobber (match_scratch:SI 3 "=q,q"))]
2012 "TARGET_POWER"
2013 "@
2014 {muls|mullw} %0,%1,%2
2015 {muli|mulli} %0,%1,%2"
2016 [(set_attr "type" "imul")])
2018 (define_insn "mulsi3_no_mq"
2019 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2020 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2021 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2022 "! TARGET_POWER"
2023 "@
2024 {muls|mullw} %0,%1,%2
2025 {muli|mulli} %0,%1,%2"
2026 [(set_attr "type" "imul")])
2028 (define_insn ""
2029 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2030 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2031 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2032 (const_int 0)))
2033 (clobber (match_scratch:SI 3 "=r,r"))
2034 (clobber (match_scratch:SI 4 "=q,q"))]
2035 "TARGET_POWER"
2036 "@
2037 {muls.|mullw.} %3,%1,%2
2038 #"
2039 [(set_attr "type" "delayed_compare")
2040 (set_attr "length" "4,8")])
2042 (define_split
2043 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2044 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2045 (match_operand:SI 2 "gpc_reg_operand" ""))
2046 (const_int 0)))
2047 (clobber (match_scratch:SI 3 ""))
2048 (clobber (match_scratch:SI 4 ""))]
2049 "TARGET_POWER && reload_completed"
2050 [(parallel [(set (match_dup 3)
2051 (mult:SI (match_dup 1)
2052 (match_dup 2)))
2053 (clobber (match_dup 4))])
2054 (set (match_dup 0)
2055 (compare:CC (match_dup 3)
2056 (const_int 0)))]
2057 "")
2059 (define_insn ""
2060 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2061 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2062 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2063 (const_int 0)))
2064 (clobber (match_scratch:SI 3 "=r,r"))]
2065 "! TARGET_POWER"
2066 "@
2067 {muls.|mullw.} %3,%1,%2
2068 #"
2069 [(set_attr "type" "delayed_compare")
2070 (set_attr "length" "4,8")])
2072 (define_split
2073 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2074 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2075 (match_operand:SI 2 "gpc_reg_operand" ""))
2076 (const_int 0)))
2077 (clobber (match_scratch:SI 3 ""))]
2078 "reload_completed"
2079 [(set (match_dup 3)
2080 (mult:SI (match_dup 1)
2081 (match_dup 2)))
2082 (set (match_dup 0)
2083 (compare:CC (match_dup 3)
2084 (const_int 0)))]
2085 "")
2087 (define_insn ""
2088 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2089 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2090 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2091 (const_int 0)))
2092 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2093 (mult:SI (match_dup 1)
2094 (match_dup 2)))
2095 (clobber (match_scratch:SI 4 "=q,q"))]
2096 "TARGET_POWER"
2097 "@
2098 {muls.|mullw.} %0,%1,%2
2099 #"
2100 [(set_attr "type" "delayed_compare")
2101 (set_attr "length" "4,8")])
2103 (define_split
2104 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2105 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2106 (match_operand:SI 2 "gpc_reg_operand" ""))
2107 (const_int 0)))
2108 (set (match_operand:SI 0 "gpc_reg_operand" "")
2109 (mult:SI (match_dup 1)
2110 (match_dup 2)))
2111 (clobber (match_scratch:SI 4 ""))]
2112 "TARGET_POWER && reload_completed"
2113 [(parallel [(set (match_dup 0)
2114 (mult:SI (match_dup 1)
2115 (match_dup 2)))
2116 (clobber (match_dup 4))])
2117 (set (match_dup 3)
2118 (compare:CC (match_dup 0)
2119 (const_int 0)))]
2120 "")
2122 (define_insn ""
2123 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2124 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2125 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2126 (const_int 0)))
2127 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2128 (mult:SI (match_dup 1) (match_dup 2)))]
2129 "! TARGET_POWER"
2130 "@
2131 {muls.|mullw.} %0,%1,%2
2132 #"
2133 [(set_attr "type" "delayed_compare")
2134 (set_attr "length" "4,8")])
2136 (define_split
2137 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2138 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2139 (match_operand:SI 2 "gpc_reg_operand" ""))
2140 (const_int 0)))
2141 (set (match_operand:SI 0 "gpc_reg_operand" "")
2142 (mult:SI (match_dup 1)
2143 (match_dup 2)))]
2144 "!TARGET_POWER && reload_completed"
2145 [(set (match_dup 0)
2146 (mult:SI (match_dup 1)
2147 (match_dup 2)))
2148 (set (match_dup 3)
2149 (compare:CC (match_dup 0)
2150 (const_int 0)))]
2151 "")
2153 ;; Operand 1 is divided by operand 2; quotient goes to operand
2154 ;; 0 and remainder to operand 3.
2155 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2157 (define_expand "divmodsi4"
2158 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2159 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2160 (match_operand:SI 2 "gpc_reg_operand" "")))
2161 (set (match_operand:SI 3 "gpc_reg_operand" "")
2162 (mod:SI (match_dup 1) (match_dup 2)))])]
2163 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2164 "
2165 {
2166 if (! TARGET_POWER && ! TARGET_POWERPC)
2167 {
2168 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2169 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2170 emit_insn (gen_divss_call ());
2171 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2172 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2173 DONE;
2174 }
2175 }")
2177 (define_insn ""
2178 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2179 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2180 (match_operand:SI 2 "gpc_reg_operand" "r")))
2181 (set (match_operand:SI 3 "gpc_reg_operand" "=q")
2182 (mod:SI (match_dup 1) (match_dup 2)))]
2183 "TARGET_POWER"
2184 "divs %0,%1,%2"
2185 [(set_attr "type" "idiv")])
2187 (define_expand "udivsi3"
2188 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2189 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2190 (match_operand:SI 2 "gpc_reg_operand" "")))]
2191 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2192 "
2193 {
2194 if (! TARGET_POWER && ! TARGET_POWERPC)
2195 {
2196 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2197 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2198 emit_insn (gen_quous_call ());
2199 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2200 DONE;
2201 }
2202 else if (TARGET_POWER)
2203 {
2204 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2205 DONE;
2206 }
2207 }")
2209 (define_insn "udivsi3_mq"
2210 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2211 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2212 (match_operand:SI 2 "gpc_reg_operand" "r")))
2213 (clobber (match_scratch:SI 3 "=q"))]
2214 "TARGET_POWERPC && TARGET_POWER"
2215 "divwu %0,%1,%2"
2216 [(set_attr "type" "idiv")])
2218 (define_insn "*udivsi3_no_mq"
2219 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2220 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2221 (match_operand:SI 2 "gpc_reg_operand" "r")))]
2222 "TARGET_POWERPC && ! TARGET_POWER"
2223 "divwu %0,%1,%2"
2224 [(set_attr "type" "idiv")])
2226 ;; For powers of two we can do srai/aze for divide and then adjust for
2227 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2228 ;; used; for PowerPC, force operands into register and do a normal divide;
2229 ;; for AIX common-mode, use quoss call on register operands.
2230 (define_expand "divsi3"
2231 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2232 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2233 (match_operand:SI 2 "reg_or_cint_operand" "")))]
2234 ""
2235 "
2236 {
2237 if (GET_CODE (operands[2]) == CONST_INT
2238 && exact_log2 (INTVAL (operands[2])) >= 0)
2239 ;
2240 else if (TARGET_POWERPC)
2241 {
2242 operands[2] = force_reg (SImode, operands[2]);
2243 if (TARGET_POWER)
2244 {
2245 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2246 DONE;
2247 }
2248 }
2249 else if (TARGET_POWER)
2250 FAIL;
2251 else
2252 {
2253 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2254 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2255 emit_insn (gen_quoss_call ());
2256 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2257 DONE;
2258 }
2259 }")
2261 (define_insn "divsi3_mq"
2262 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2263 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2264 (match_operand:SI 2 "gpc_reg_operand" "r")))
2265 (clobber (match_scratch:SI 3 "=q"))]
2266 "TARGET_POWERPC && TARGET_POWER"
2267 "divw %0,%1,%2"
2268 [(set_attr "type" "idiv")])
2270 (define_insn "*divsi3_no_mq"
2271 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2272 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2273 (match_operand:SI 2 "gpc_reg_operand" "r")))]
2274 "TARGET_POWERPC && ! TARGET_POWER"
2275 "divw %0,%1,%2"
2276 [(set_attr "type" "idiv")])
2278 (define_expand "modsi3"
2279 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2280 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2281 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
2282 ""
2283 "
2284 {
2285 int i = exact_log2 (INTVAL (operands[2]));
2286 rtx temp1;
2287 rtx temp2;
2289 if (GET_CODE (operands[2]) != CONST_INT || i < 0)
2290 FAIL;
2292 temp1 = gen_reg_rtx (SImode);
2293 temp2 = gen_reg_rtx (SImode);
2295 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
2296 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
2297 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
2298 DONE;
2299 }")
2301 (define_insn ""
2302 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2303 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2304 (match_operand:SI 2 "const_int_operand" "N")))]
2305 "exact_log2 (INTVAL (operands[2])) >= 0"
2306 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
2307 [(set_attr "length" "8")])
2309 (define_insn ""
2310 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2311 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2312 (match_operand:SI 2 "const_int_operand" "N,N"))
2313 (const_int 0)))
2314 (clobber (match_scratch:SI 3 "=r,r"))]
2315 "exact_log2 (INTVAL (operands[2])) >= 0"
2316 "@
2317 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
2318 #"
2319 [(set_attr "type" "compare")
2320 (set_attr "length" "8,12")])
2322 (define_split
2323 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2324 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2325 (match_operand:SI 2 "const_int_operand" ""))
2326 (const_int 0)))
2327 (clobber (match_scratch:SI 3 ""))]
2328 "reload_completed && exact_log2 (INTVAL (operands[2])) >= 0"
2329 [(set (match_dup 3)
2330 (div:SI (match_dup 1)
2331 (match_dup 2)))
2332 (set (match_dup 0)
2333 (compare:CC (match_dup 3)
2334 (const_int 0)))]
2335 "")
2337 (define_insn ""
2338 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2339 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2340 (match_operand:SI 2 "const_int_operand" "N,N"))
2341 (const_int 0)))
2342 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2343 (div:SI (match_dup 1)
2344 (match_dup 2)))]
2345 "exact_log2 (INTVAL (operands[2])) >= 0"
2346 "@
2347 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
2348 #"
2349 [(set_attr "type" "compare")
2350 (set_attr "length" "8,12")])
2352 (define_split
2353 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2354 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2355 (match_operand:SI 2 "reg_or_short_operand" ""))
2356 (const_int 0)))
2357 (set (match_operand:SI 0 "gpc_reg_operand" "")
2358 (div:SI (match_dup 1)
2359 (match_dup 2)))]
2360 "reload_completed"
2361 [(set (match_dup 3)
2362 (div:SI (match_dup 1)
2363 (match_dup 2)))
2364 (set (match_dup 0)
2365 (compare:CC (match_dup 3)
2366 (const_int 0)))]
2367 "")
2369 (define_insn ""
2370 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2371 (udiv:SI
2372 (plus:DI (ashift:DI
2373 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2374 (const_int 32))
2375 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2376 (match_operand:SI 3 "gpc_reg_operand" "r")))
2377 (set (match_operand:SI 2 "register_operand" "=*q")
2378 (umod:SI
2379 (plus:DI (ashift:DI
2380 (zero_extend:DI (match_dup 1)) (const_int 32))
2381 (zero_extend:DI (match_dup 4)))
2382 (match_dup 3)))]
2383 "TARGET_POWER"
2384 "div %0,%1,%3"
2385 [(set_attr "type" "idiv")])
2387 ;; To do unsigned divide we handle the cases of the divisor looking like a
2388 ;; negative number. If it is a constant that is less than 2**31, we don't
2389 ;; have to worry about the branches. So make a few subroutines here.
2390 ;;
2391 ;; First comes the normal case.
2392 (define_expand "udivmodsi4_normal"
2393 [(set (match_dup 4) (const_int 0))
2394 (parallel [(set (match_operand:SI 0 "" "")
2395 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2396 (const_int 32))
2397 (zero_extend:DI (match_operand:SI 1 "" "")))
2398 (match_operand:SI 2 "" "")))
2399 (set (match_operand:SI 3 "" "")
2400 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2401 (const_int 32))
2402 (zero_extend:DI (match_dup 1)))
2403 (match_dup 2)))])]
2404 "TARGET_POWER"
2405 "
2406 { operands[4] = gen_reg_rtx (SImode); }")
2408 ;; This handles the branches.
2409 (define_expand "udivmodsi4_tests"
2410 [(set (match_operand:SI 0 "" "") (const_int 0))
2411 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2412 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2413 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2414 (label_ref (match_operand:SI 4 "" "")) (pc)))
2415 (set (match_dup 0) (const_int 1))
2416 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2417 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2418 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2419 (label_ref (match_dup 4)) (pc)))]
2420 "TARGET_POWER"
2421 "
2422 { operands[5] = gen_reg_rtx (CCUNSmode);
2423 operands[6] = gen_reg_rtx (CCmode);
2424 }")
2426 (define_expand "udivmodsi4"
2427 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2428 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2429 (match_operand:SI 2 "reg_or_cint_operand" "")))
2430 (set (match_operand:SI 3 "gpc_reg_operand" "")
2431 (umod:SI (match_dup 1) (match_dup 2)))])]
2432 ""
2433 "
2434 {
2435 rtx label = 0;
2437 if (! TARGET_POWER)
2438 {
2439 if (! TARGET_POWERPC)
2440 {
2441 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2442 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2443 emit_insn (gen_divus_call ());
2444 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2445 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2446 DONE;
2447 }
2448 else
2449 FAIL;
2450 }
2452 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2453 {
2454 operands[2] = force_reg (SImode, operands[2]);
2455 label = gen_label_rtx ();
2456 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2457 operands[3], label));
2458 }
2459 else
2460 operands[2] = force_reg (SImode, operands[2]);
2462 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2463 operands[3]));
2464 if (label)
2465 emit_label (label);
2467 DONE;
2468 }")
2470 ;; AIX architecture-independent common-mode multiply (DImode),
2471 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2472 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2473 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2474 ;; assumed unused if generating common-mode, so ignore.
2475 (define_insn "mulh_call"
2476 [(set (reg:SI 3)
2477 (truncate:SI
2478 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2479 (sign_extend:DI (reg:SI 4)))
2480 (const_int 32))))
2481 (clobber (match_scratch:SI 0 "=l"))]
2482 "! TARGET_POWER && ! TARGET_POWERPC"
2483 "bla __mulh"
2484 [(set_attr "type" "imul")])
2486 (define_insn "mull_call"
2487 [(set (reg:DI 3)
2488 (mult:DI (sign_extend:DI (reg:SI 3))
2489 (sign_extend:DI (reg:SI 4))))
2490 (clobber (match_scratch:SI 0 "=l"))
2491 (clobber (reg:SI 0))]
2492 "! TARGET_POWER && ! TARGET_POWERPC"
2493 "bla __mull"
2494 [(set_attr "type" "imul")])
2496 (define_insn "divss_call"
2497 [(set (reg:SI 3)
2498 (div:SI (reg:SI 3) (reg:SI 4)))
2499 (set (reg:SI 4)
2500 (mod:SI (reg:SI 3) (reg:SI 4)))
2501 (clobber (match_scratch:SI 0 "=l"))
2502 (clobber (reg:SI 0))]
2503 "! TARGET_POWER && ! TARGET_POWERPC"
2504 "bla __divss"
2505 [(set_attr "type" "idiv")])
2507 (define_insn "divus_call"
2508 [(set (reg:SI 3)
2509 (udiv:SI (reg:SI 3) (reg:SI 4)))
2510 (set (reg:SI 4)
2511 (umod:SI (reg:SI 3) (reg:SI 4)))
2512 (clobber (match_scratch:SI 0 "=l"))
2513 (clobber (reg:SI 0))
2514 (clobber (match_scratch:CC 1 "=x"))
2515 (clobber (reg:CC 69))]
2516 "! TARGET_POWER && ! TARGET_POWERPC"
2517 "bla __divus"
2518 [(set_attr "type" "idiv")])
2520 (define_insn "quoss_call"
2521 [(set (reg:SI 3)
2522 (div:SI (reg:SI 3) (reg:SI 4)))
2523 (clobber (match_scratch:SI 0 "=l"))]
2524 "! TARGET_POWER && ! TARGET_POWERPC"
2525 "bla __quoss"
2526 [(set_attr "type" "idiv")])
2528 (define_insn "quous_call"
2529 [(set (reg:SI 3)
2530 (udiv:SI (reg:SI 3) (reg:SI 4)))
2531 (clobber (match_scratch:SI 0 "=l"))
2532 (clobber (reg:SI 0))
2533 (clobber (match_scratch:CC 1 "=x"))
2534 (clobber (reg:CC 69))]
2535 "! TARGET_POWER && ! TARGET_POWERPC"
2536 "bla __quous"
2537 [(set_attr "type" "idiv")])
2538 \f
2539 ;; Logical instructions
2540 (define_expand "andsi3"
2541 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2542 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2543 (match_operand:SI 2 "and_operand" "?r,L,K,J")))
2544 (clobber (match_scratch:CC 3 "=X,X,x,x"))])]
2545 ""
2546 "")
2548 ;; If cr0 isn't available, and we want to do an andi, load the register into
2549 ;; the destination first.
2551 (define_insn "andsi3_internal1"
2552 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,&??r,&??r")
2553 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
2554 (match_operand:SI 2 "and_operand" "?r,L,K,J,K,J")))
2555 (clobber (match_operand:CC 3 "scratch_operand" "=X,X,x,x,X,X"))]
2556 ""
2557 "@
2558 and %0,%1,%2
2559 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2560 {andil.|andi.} %0,%1,%b2
2561 {andiu.|andis.} %0,%1,%u2
2562 #
2563 #"
2564 [(set_attr "length" "4,4,4,4,8,8")])
2566 (define_split
2567 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2568 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2569 (match_operand:SI 2 "const_int_operand" "")))
2570 (clobber (scratch:CC))]
2571 "reload_completed"
2572 [(set (match_dup 0)
2573 (match_dup 2))
2574 (parallel [(set (match_dup 0)
2575 (and:SI (match_dup 0)
2576 (match_dup 1)))
2577 (clobber (scratch:CC))])]
2578 "")
2580 ;; Note to set cr's other than cr0 we do the and immediate and then
2581 ;; the test again -- this avoids a mcrf which on the higher end
2582 ;; machines causes an execution serialization
2584 (define_insn "*andsi3_internal2"
2585 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y,???y,???y")
2586 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
2587 (match_operand:SI 2 "and_operand" "r,K,J,L,r,K,J,L,K,L"))
2588 (const_int 0)))
2589 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r,&r,&r"))
2590 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X,X,X"))]
2591 ""
2592 "@
2593 and. %3,%1,%2
2594 {andil.|andi.} %3,%1,%b2
2595 {andiu.|andis.} %3,%1,%u2
2596 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2597 #
2598 #
2599 #
2600 #
2601 #
2602 #"
2603 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare")
2604 (set_attr "length" "4,4,4,4,8,12,12,8,16,16")])
2606 (define_split
2607 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2608 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2609 (match_operand:SI 2 "and_operand" ""))
2610 (const_int 0)))
2611 (clobber (match_scratch:SI 3 ""))
2612 (clobber (match_scratch:CC 4 ""))]
2613 "reload_completed"
2614 [(parallel [(set (match_dup 3)
2615 (and:SI (match_dup 1)
2616 (match_dup 2)))
2617 (clobber (match_dup 4))])
2618 (set (match_dup 0)
2619 (compare:CC (match_dup 3)
2620 (const_int 0)))]
2621 "")
2623 (define_insn "*andsi3_internal3"
2624 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y,???y,???y")
2625 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
2626 (match_operand:SI 2 "and_operand" "r,K,J,L,r,K,J,L,K,J"))
2627 (const_int 0)))
2628 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,&r,&r")
2629 (and:SI (match_dup 1)
2630 (match_dup 2)))
2631 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X,X,X"))]
2632 ""
2633 "@
2634 and. %0,%1,%2
2635 {andil.|andi.} %0,%1,%b2
2636 {andiu.|andis.} %0,%1,%u2
2637 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
2638 #
2639 #
2640 #
2641 #
2642 #
2643 #"
2644 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare")])
2646 (define_split
2647 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2648 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2649 (match_operand:SI 2 "and_operand" ""))
2650 (const_int 0)))
2651 (set (match_operand:SI 0 "gpc_reg_operand" "")
2652 (and:SI (match_dup 1)
2653 (match_dup 2)))
2654 (clobber (match_scratch:CC 4 ""))]
2655 "reload_completed"
2656 [(parallel [(set (match_dup 0)
2657 (and:SI (match_dup 1)
2658 (match_dup 2)))
2659 (clobber (match_dup 4))])
2660 (set (match_dup 3)
2661 (compare:CC (match_dup 0)
2662 (const_int 0)))]
2663 "")
2665 (define_expand "iorsi3"
2666 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2667 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2668 (match_operand:SI 2 "reg_or_cint_operand" "")))]
2669 ""
2670 "
2671 {
2672 if (GET_CODE (operands[2]) == CONST_INT
2673 && !logical_operand (operands[2], SImode))
2674 {
2675 HOST_WIDE_INT value = INTVAL (operands[2]);
2676 rtx tmp = ((reload_in_progress || reload_completed
2677 || rtx_equal_p (operands[0], operands[1]))
2678 ? operands[0] : gen_reg_rtx (SImode));
2680 emit_insn (gen_iorsi3 (tmp, operands[1],
2681 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2682 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2683 DONE;
2684 }
2685 }")
2687 (define_insn "*iorsi3_internal1"
2688 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2689 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2690 (match_operand:SI 2 "logical_operand" "r,K,J")))]
2691 ""
2692 "@
2693 or %0,%1,%2
2694 {oril|ori} %0,%1,%b2
2695 {oriu|oris} %0,%1,%u2"
2696 [(set_attr "length" "4,4,4")])
2698 (define_insn "*iorsi3_internal2"
2699 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2700 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2701 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2702 (const_int 0)))
2703 (clobber (match_scratch:SI 3 "=r,r"))]
2704 ""
2705 "@
2706 or. %3,%1,%2
2707 #"
2708 [(set_attr "type" "compare")
2709 (set_attr "length" "4,8")])
2711 (define_split
2712 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2713 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2714 (match_operand:SI 2 "gpc_reg_operand" ""))
2715 (const_int 0)))
2716 (clobber (match_scratch:SI 3 ""))]
2717 "reload_completed"
2718 [(set (match_dup 3)
2719 (ior:SI (match_dup 1)
2720 (match_dup 2)))
2721 (set (match_dup 0)
2722 (compare:CC (match_dup 3)
2723 (const_int 0)))]
2724 "")
2726 (define_insn "*iorsi3_internal3"
2727 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2728 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2729 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2730 (const_int 0)))
2731 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2732 (ior:SI (match_dup 1)
2733 (match_dup 2)))]
2734 ""
2735 "or. %0,%1,%2"
2736 [(set_attr "type" "compare")])
2738 (define_split
2739 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2740 (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2741 (match_operand:SI 2 "gpc_reg_operand" ""))
2742 (const_int 0)))
2743 (set (match_operand:SI 0 "gpc_reg_operand" "")
2744 (ior:SI (match_dup 1) (match_dup 2)))]
2745 "reload_completed"
2746 [(set (match_dup 0)
2747 (ior:SI (match_dup 1)
2748 (match_dup 2)))
2749 (set (match_dup 3)
2750 (compare:CC (match_dup 0)
2751 (const_int 0)))]
2752 "")
2754 ;; Split an IOR that we can't do in one insn into two insns, each of which
2755 ;; does one 16-bit part. This is used by combine.
2757 (define_split
2758 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2759 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
2760 (match_operand:SI 2 "non_logical_cint_operand" "")))]
2761 ""
2762 [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))
2763 (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))]
2764 "
2765 {
2766 operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2767 operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff);
2768 }")
2770 (define_expand "xorsi3"
2771 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2772 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2773 (match_operand:SI 2 "reg_or_cint_operand" "")))]
2774 ""
2775 "
2776 {
2777 if (GET_CODE (operands[2]) == CONST_INT
2778 && !logical_operand (operands[2], SImode))
2779 {
2780 HOST_WIDE_INT value = INTVAL (operands[2]);
2781 rtx tmp = ((reload_in_progress || reload_completed
2782 || rtx_equal_p (operands[0], operands[1]))
2783 ? operands[0] : gen_reg_rtx (SImode));
2785 emit_insn (gen_xorsi3 (tmp, operands[1],
2786 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
2787 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
2788 DONE;
2789 }
2790 }")
2792 (define_insn "*xorsi3_internal1"
2793 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
2794 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
2795 (match_operand:SI 2 "logical_operand" "r,K,J")))]
2796 ""
2797 "@
2798 xor %0,%1,%2
2799 {xoril|xori} %0,%1,%b2
2800 {xoriu|xoris} %0,%1,%u2"
2801 [(set_attr "length" "4,4,4")])
2803 (define_insn "*xorsi3_internal2"
2804 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2805 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2806 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2807 (const_int 0)))
2808 (clobber (match_scratch:SI 3 "=r,r"))]
2809 ""
2810 "@
2811 xor. %3,%1,%2
2812 #"
2813 [(set_attr "type" "compare")
2814 (set_attr "length" "4,8")])
2816 (define_split
2817 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2818 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2819 (match_operand:SI 2 "gpc_reg_operand" ""))
2820 (const_int 0)))
2821 (clobber (match_scratch:SI 3 ""))]
2822 "reload_completed"
2823 [(set (match_dup 3)
2824 (xor:SI (match_dup 1)
2825 (match_dup 2)))
2826 (set (match_dup 0)
2827 (compare:CC (match_dup 3)
2828 (const_int 0)))]
2829 "")
2831 (define_insn "*xorsi3_internal3"
2832 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2833 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2834 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2835 (const_int 0)))
2836 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2837 (xor:SI (match_dup 1)
2838 (match_dup 2)))]
2839 ""
2840 "@
2841 xor. %0,%1,%2
2842 #"
2843 [(set_attr "type" "compare")
2844 (set_attr "length" "4,8")])
2846 (define_split
2847 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2848 (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2849 (match_operand:SI 2 "gpc_reg_operand" ""))
2850 (const_int 0)))
2851 (set (match_operand:SI 0 "gpc_reg_operand" "")
2852 (xor:SI (match_dup 1) (match_dup 2)))]
2853 "reload_completed"
2854 [(set (match_dup 0)
2855 (xor:SI (match_dup 1)
2856 (match_dup 2)))
2857 (set (match_dup 3)
2858 (compare:CC (match_dup 0)
2859 (const_int 0)))]
2860 "")
2862 ;; Split an XOR that we can't do in one insn into two insns, each of which
2863 ;; does one 16-bit part. This is used by combine.
2865 (define_split
2866 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2867 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2868 (match_operand:SI 2 "non_logical_cint_operand" "")))]
2869 ""
2870 [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))
2871 (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))]
2872 "
2873 {
2874 operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
2875 operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff);
2876 }")
2878 (define_insn "*eqvsi3_internal1"
2879 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2880 (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
2881 (match_operand:SI 2 "gpc_reg_operand" "r"))))]
2882 ""
2883 "eqv %0,%1,%2")
2885 (define_insn "*eqvsi3_internal2"
2886 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2887 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2888 (match_operand:SI 2 "gpc_reg_operand" "r,r")))
2889 (const_int 0)))
2890 (clobber (match_scratch:SI 3 "=r,r"))]
2891 ""
2892 "@
2893 eqv. %3,%1,%2
2894 #"
2895 [(set_attr "type" "compare")
2896 (set_attr "length" "4,8")])
2898 (define_split
2899 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2900 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2901 (match_operand:SI 2 "gpc_reg_operand" "")))
2902 (const_int 0)))
2903 (clobber (match_scratch:SI 3 ""))]
2904 "reload_completed"
2905 [(set (match_dup 3)
2906 (not:SI (xor:SI (match_dup 1)
2907 (match_dup 2))))
2908 (set (match_dup 0)
2909 (compare:CC (match_dup 3)
2910 (const_int 0)))]
2911 "")
2913 (define_insn "*eqvsi3_internal3"
2914 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2915 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2916 (match_operand:SI 2 "gpc_reg_operand" "r,r")))
2917 (const_int 0)))
2918 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2919 (not:SI (xor:SI (match_dup 1) (match_dup 2))))]
2920 ""
2921 "@
2922 eqv. %0,%1,%2
2923 #"
2924 [(set_attr "type" "compare")
2925 (set_attr "length" "4,8")])
2927 (define_split
2928 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2929 (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2930 (match_operand:SI 2 "reg_or_short_operand" "")))
2931 (const_int 0)))
2932 (set (match_operand:SI 0 "gpc_reg_operand" "")
2933 (not:SI (xor:SI (match_dup 1)
2934 (match_dup 2))))]
2935 "reload_completed"
2936 [(set (match_dup 0)
2937 (not:SI (xor:SI (match_dup 1)
2938 (match_dup 2))))
2939 (set (match_dup 3)
2940 (compare:CC (match_dup 0)
2941 (const_int 0)))]
2942 "")
2944 (define_insn "*andcsi3_internal1"
2945 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2946 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
2947 (match_operand:SI 2 "gpc_reg_operand" "r")))]
2948 ""
2949 "andc %0,%2,%1")
2951 (define_insn "*andcsi3_internal2"
2952 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2953 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2954 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2955 (const_int 0)))
2956 (clobber (match_scratch:SI 3 "=r,r"))]
2957 ""
2958 "@
2959 andc. %3,%2,%1
2960 #"
2961 [(set_attr "type" "compare")
2962 (set_attr "length" "4,8")])
2964 (define_split
2965 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2966 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2967 (match_operand:SI 2 "gpc_reg_operand" ""))
2968 (const_int 0)))
2969 (clobber (match_scratch:SI 3 ""))]
2970 "reload_completed"
2971 [(set (match_dup 3)
2972 (and:SI (not:SI (match_dup 1))
2973 (match_dup 2)))
2974 (set (match_dup 0)
2975 (compare:CC (match_dup 3)
2976 (const_int 0)))]
2977 "")
2979 (define_insn "*andcsi3_internal3"
2980 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2981 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2982 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2983 (const_int 0)))
2984 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2985 (and:SI (not:SI (match_dup 1))
2986 (match_dup 2)))]
2987 ""
2988 "@
2989 andc. %0,%2,%1
2990 #"
2991 [(set_attr "type" "compare")
2992 (set_attr "length" "4,8")])
2994 (define_split
2995 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2996 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2997 (match_operand:SI 2 "gpc_reg_operand" ""))
2998 (const_int 0)))
2999 (set (match_operand:SI 0 "gpc_reg_operand" "")
3000 (and:SI (not:SI (match_dup 1))
3001 (match_dup 2)))]
3002 "reload_completed"
3003 [(set (match_dup 0)
3004 (and:SI (not:SI (match_dup 1))
3005 (match_dup 2)))
3006 (set (match_dup 3)
3007 (compare:CC (match_dup 0)
3008 (const_int 0)))]
3009 "")
3011 (define_insn "*iorcsi3_internal1"
3012 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3013 (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3014 (match_operand:SI 2 "gpc_reg_operand" "r")))]
3015 ""
3016 "orc %0,%2,%1")
3018 (define_insn "*iorcsi3_internal2"
3019 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3020 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3021 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3022 (const_int 0)))
3023 (clobber (match_scratch:SI 3 "=r,r"))]
3024 ""
3025 "@
3026 orc. %3,%2,%1
3027 #"
3028 [(set_attr "type" "compare")
3029 (set_attr "length" "4,8")])
3031 (define_split
3032 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3033 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3034 (match_operand:SI 2 "gpc_reg_operand" ""))
3035 (const_int 0)))
3036 (clobber (match_scratch:SI 3 ""))]
3037 "reload_completed"
3038 [(set (match_dup 3)
3039 (ior:SI (not:SI (match_dup 1))
3040 (match_dup 2)))
3041 (set (match_dup 0)
3042 (compare:CC (match_dup 3)
3043 (const_int 0)))]
3044 "")
3046 (define_insn "*iorcsi3_internal3"
3047 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3048 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3049 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3050 (const_int 0)))
3051 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3052 (ior:SI (not:SI (match_dup 1)) (match_dup 2)))]
3053 ""
3054 "@
3055 orc. %0,%2,%1
3056 #"
3057 [(set_attr "type" "compare")])
3059 (define_split
3060 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3061 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3062 (match_operand:SI 2 "gpc_reg_operand" ""))
3063 (const_int 0)))
3064 (set (match_operand:SI 0 "gpc_reg_operand" "")
3065 (ior:SI (not:SI (match_dup 1))
3066 (match_dup 2)))]
3067 "reload_completed"
3068 [(set (match_dup 0)
3069 (ior:SI (not:SI (match_dup 1))
3070 (match_dup 2)))
3071 (set (match_dup 3)
3072 (compare:CC (match_dup 0)
3073 (const_int 0)))]
3074 "")
3076 (define_insn "*nandsi3_internal1"
3077 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3078 (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3079 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
3080 ""
3081 "nand %0,%1,%2")
3083 (define_insn "*nandsi3_internal2"
3084 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3085 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3086 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")))
3087 (const_int 0)))
3088 (clobber (match_scratch:SI 3 "=r,r"))]
3089 ""
3090 "@
3091 nand. %3,%1,%2
3092 #"
3093 [(set_attr "type" "compare")
3094 (set_attr "length" "4,8")])
3096 (define_split
3097 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3098 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3099 (not:SI (match_operand:SI 2 "gpc_reg_operand" "")))
3100 (const_int 0)))
3101 (clobber (match_scratch:SI 3 ""))]
3102 "reload_completed"
3103 [(set (match_dup 3)
3104 (ior:SI (not:SI (match_dup 1))
3105 (not:SI (match_dup 2))))
3106 (set (match_dup 0)
3107 (compare:CC (match_dup 3)
3108 (const_int 0)))]
3109 "")
3111 (define_insn "*nandsi3_internal3"
3112 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3113 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3114 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")))
3115 (const_int 0)))
3116 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3117 (ior:SI (not:SI (match_dup 1))
3118 (not:SI (match_dup 2))))]
3119 ""
3120 "@
3121 nand. %0,%1,%2
3122 #"
3123 [(set_attr "type" "compare")
3124 (set_attr "length" "4,8")])
3126 (define_split
3127 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3128 (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3129 (not:SI (match_operand:SI 2 "gpc_reg_operand" "")))
3130 (const_int 0)))
3131 (set (match_operand:SI 0 "gpc_reg_operand" "")
3132 (ior:SI (not:SI (match_dup 1))
3133 (not:SI (match_dup 2))))]
3134 "reload_completed"
3135 [(set (match_dup 0)
3136 (ior:SI (not:SI (match_dup 1))
3137 (not:SI (match_dup 2))))
3138 (set (match_dup 3)
3139 (compare:CC (match_dup 0)
3140 (const_int 0)))]
3141 "")
3143 (define_insn "*norsi3_internal1"
3144 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3145 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3146 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
3147 ""
3148 "nor %0,%1,%2")
3150 (define_insn "*norsi3_internal2"
3151 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3152 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3153 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")))
3154 (const_int 0)))
3155 (clobber (match_scratch:SI 3 "=r,r"))]
3156 ""
3157 "@
3158 nor. %3,%1,%2
3159 #"
3160 [(set_attr "type" "compare")
3161 (set_attr "length" "4,8")])
3163 (define_split
3164 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3165 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3166 (not:SI (match_operand:SI 2 "gpc_reg_operand" "")))
3167 (const_int 0)))
3168 (clobber (match_scratch:SI 3 ""))]
3169 "reload_completed"
3170 [(set (match_dup 3)
3171 (and:SI (not:SI (match_dup 1))
3172 (not:SI (match_dup 2))))
3173 (set (match_dup 0)
3174 (compare:CC (match_dup 3)
3175 (const_int 0)))]
3176 "")
3178 (define_insn "*norsi3_internal3"
3179 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3180 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3181 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")))
3182 (const_int 0)))
3183 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3184 (and:SI (not:SI (match_dup 1))
3185 (not:SI (match_dup 2))))]
3186 ""
3187 "@
3188 nor. %0,%1,%2
3189 #"
3190 [(set_attr "type" "compare")
3191 (set_attr "length" "4,8")])
3193 (define_split
3194 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3195 (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3196 (not:SI (match_operand:SI 2 "gpc_reg_operand" "")))
3197 (const_int 0)))
3198 (set (match_operand:SI 0 "gpc_reg_operand" "")
3199 (and:SI (not:SI (match_dup 1))
3200 (not:SI (match_dup 2))))]
3201 "reload_completed"
3202 [(set (match_dup 0)
3203 (and:SI (not:SI (match_dup 1))
3204 (not:SI (match_dup 2))))
3205 (set (match_dup 3)
3206 (compare:CC (match_dup 0)
3207 (const_int 0)))]
3208 "")
3210 ;; maskir insn. We need four forms because things might be in arbitrary
3211 ;; orders. Don't define forms that only set CR fields because these
3212 ;; would modify an input register.
3214 (define_insn "*maskir_internal1"
3215 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3216 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3217 (match_operand:SI 1 "gpc_reg_operand" "0"))
3218 (and:SI (match_dup 2)
3219 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3220 "TARGET_POWER"
3221 "maskir %0,%3,%2")
3223 (define_insn "*maskir_internal2"
3224 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3225 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3226 (match_operand:SI 1 "gpc_reg_operand" "0"))
3227 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3228 (match_dup 2))))]
3229 "TARGET_POWER"
3230 "maskir %0,%3,%2")
3232 (define_insn "*maskir_internal3"
3233 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3234 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3235 (match_operand:SI 3 "gpc_reg_operand" "r"))
3236 (and:SI (not:SI (match_dup 2))
3237 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3238 "TARGET_POWER"
3239 "maskir %0,%3,%2")
3241 (define_insn "*maskir_internal4"
3242 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3243 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3244 (match_operand:SI 2 "gpc_reg_operand" "r"))
3245 (and:SI (not:SI (match_dup 2))
3246 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3247 "TARGET_POWER"
3248 "maskir %0,%3,%2")
3250 (define_insn "*maskir_internal5"
3251 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3252 (compare:CC
3253 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3254 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3255 (and:SI (match_dup 2)
3256 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3257 (const_int 0)))
3258 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3259 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3260 (and:SI (match_dup 2) (match_dup 3))))]
3261 "TARGET_POWER"
3262 "@
3263 maskir. %0,%3,%2
3264 #"
3265 [(set_attr "type" "compare")
3266 (set_attr "length" "4,8")])
3268 (define_split
3269 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3270 (compare:CC
3271 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3272 (match_operand:SI 1 "gpc_reg_operand" ""))
3273 (and:SI (match_dup 2)
3274 (match_operand:SI 3 "gpc_reg_operand" "")))
3275 (const_int 0)))
3276 (set (match_operand:SI 0 "gpc_reg_operand" "")
3277 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3278 (and:SI (match_dup 2) (match_dup 3))))]
3279 "TARGET_POWER && reload_completed"
3280 [(set (match_dup 0)
3281 (ior:SI (and:SI (not:SI (match_dup 2))
3282 (match_dup 1))
3283 (and:SI (match_dup 2)
3284 (match_dup 3))))
3285 (set (match_dup 4)
3286 (compare:CC (match_dup 0)
3287 (const_int 0)))]
3288 "")
3291 (define_insn "*maskir_internal6"
3292 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3293 (compare:CC
3294 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3295 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3296 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3297 (match_dup 2)))
3298 (const_int 0)))
3299 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3300 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3301 (and:SI (match_dup 3) (match_dup 2))))]
3302 "TARGET_POWER"
3303 "@
3304 maskir. %0,%3,%2
3305 #"
3306 [(set_attr "type" "compare")
3307 (set_attr "length" "4,8")])
3309 (define_split
3310 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3311 (compare:CC
3312 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3313 (match_operand:SI 1 "gpc_reg_operand" ""))
3314 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3315 (match_dup 2)))
3316 (const_int 0)))
3317 (set (match_operand:SI 0 "gpc_reg_operand" "")
3318 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3319 (and:SI (match_dup 3) (match_dup 2))))]
3320 "TARGET_POWER && reload_completed"
3321 [(set (match_dup 0)
3322 (ior:SI (and:SI (not:SI (match_dup 2))
3323 (match_dup 1))
3324 (and:SI (match_dup 3)
3325 (match_dup 2))))
3326 (set (match_dup 4)
3327 (compare:CC (match_dup 0)
3328 (const_int 0)))]
3329 "")
3331 (define_insn "*maskir_internal7"
3332 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3333 (compare:CC
3334 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3335 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3336 (and:SI (not:SI (match_dup 2))
3337 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3338 (const_int 0)))
3339 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3340 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3341 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3342 "TARGET_POWER"
3343 "@
3344 maskir. %0,%3,%2
3345 #"
3346 [(set_attr "type" "compare")
3347 (set_attr "length" "4,8")])
3349 (define_split
3350 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3351 (compare:CC
3352 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3353 (match_operand:SI 3 "gpc_reg_operand" ""))
3354 (and:SI (not:SI (match_dup 2))
3355 (match_operand:SI 1 "gpc_reg_operand" "")))
3356 (const_int 0)))
3357 (set (match_operand:SI 0 "gpc_reg_operand" "")
3358 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3359 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3360 "TARGET_POWER"
3361 [(set (match_dup 0)
3362 (ior:SI (and:SI (match_dup 2)
3363 (match_dup 3))
3364 (and:SI (not:SI (match_dup 2))
3365 (match_dup 1))))
3366 (set (match_dup 4)
3367 (compare:CC (match_dup 0)
3368 (const_int 0)))]
3369 "")
3371 (define_insn "*maskir_internal8"
3372 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3373 (compare:CC
3374 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3375 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3376 (and:SI (not:SI (match_dup 2))
3377 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3378 (const_int 0)))
3379 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3380 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3381 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3382 "TARGET_POWER"
3383 "@
3384 maskir. %0,%3,%2
3385 #"
3386 [(set_attr "type" "compare")
3387 (set_attr "length" "4,8")])
3389 (define_split
3390 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3391 (compare:CC
3392 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3393 (match_operand:SI 2 "gpc_reg_operand" ""))
3394 (and:SI (not:SI (match_dup 2))
3395 (match_operand:SI 1 "gpc_reg_operand" "")))
3396 (const_int 0)))
3397 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3398 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3399 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3400 "TARGET_POWER && reload_completed"
3401 [(set (match_dup 0)
3402 (ior:SI (and:SI (match_dup 3)
3403 (match_dup 2))
3404 (and:SI (not:SI (match_dup 2))
3405 (match_dup 1))))
3406 (set (match_dup 4)
3407 (compare:CC (match_dup 0)
3408 (const_int 0)))]
3409 "")
3411 \f
3412 ;; Rotate and shift insns, in all their variants. These support shifts,
3413 ;; field inserts and extracts, and various combinations thereof.
3414 (define_expand "insv"
3415 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3416 (match_operand:SI 1 "const_int_operand" "i")
3417 (match_operand:SI 2 "const_int_operand" "i"))
3418 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3419 ""
3420 "
3421 {
3422 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3423 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3424 compiler if the address of the structure is taken later. */
3425 if (GET_CODE (operands[0]) == SUBREG
3426 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3427 FAIL;
3428 }")
3430 (define_insn ""
3431 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3432 (match_operand:SI 1 "const_int_operand" "i")
3433 (match_operand:SI 2 "const_int_operand" "i"))
3434 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3435 ""
3436 "*
3437 {
3438 int start = INTVAL (operands[2]) & 31;
3439 int size = INTVAL (operands[1]) & 31;
3441 operands[4] = GEN_INT (32 - start - size);
3442 operands[1] = GEN_INT (start + size - 1);
3443 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3444 }")
3446 (define_insn ""
3447 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3448 (match_operand:SI 1 "const_int_operand" "i")
3449 (match_operand:SI 2 "const_int_operand" "i"))
3450 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3451 (match_operand:SI 4 "const_int_operand" "i")))]
3452 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3453 "*
3454 {
3455 int shift = INTVAL (operands[4]) & 31;
3456 int start = INTVAL (operands[2]) & 31;
3457 int size = INTVAL (operands[1]) & 31;
3459 operands[4] = GEN_INT (shift - start - size);
3460 operands[1] = GEN_INT (start + size - 1);
3461 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3462 }")
3464 (define_insn ""
3465 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3466 (match_operand:SI 1 "const_int_operand" "i")
3467 (match_operand:SI 2 "const_int_operand" "i"))
3468 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3469 (match_operand:SI 4 "const_int_operand" "i")))]
3470 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3471 "*
3472 {
3473 int shift = INTVAL (operands[4]) & 31;
3474 int start = INTVAL (operands[2]) & 31;
3475 int size = INTVAL (operands[1]) & 31;
3477 operands[4] = GEN_INT (32 - shift - start - size);
3478 operands[1] = GEN_INT (start + size - 1);
3479 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3480 }")
3482 (define_insn ""
3483 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3484 (match_operand:SI 1 "const_int_operand" "i")
3485 (match_operand:SI 2 "const_int_operand" "i"))
3486 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3487 (match_operand:SI 4 "const_int_operand" "i")))]
3488 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3489 "*
3490 {
3491 int shift = INTVAL (operands[4]) & 31;
3492 int start = INTVAL (operands[2]) & 31;
3493 int size = INTVAL (operands[1]) & 31;
3495 operands[4] = GEN_INT (32 - shift - start - size);
3496 operands[1] = GEN_INT (start + size - 1);
3497 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3498 }")
3500 (define_insn ""
3501 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3502 (match_operand:SI 1 "const_int_operand" "i")
3503 (match_operand:SI 2 "const_int_operand" "i"))
3504 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3505 (match_operand:SI 4 "const_int_operand" "i")
3506 (match_operand:SI 5 "const_int_operand" "i")))]
3507 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3508 "*
3509 {
3510 int extract_start = INTVAL (operands[5]) & 31;
3511 int extract_size = INTVAL (operands[4]) & 31;
3512 int insert_start = INTVAL (operands[2]) & 31;
3513 int insert_size = INTVAL (operands[1]) & 31;
3515 /* Align extract field with insert field */
3516 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3517 operands[1] = GEN_INT (insert_start + insert_size - 1);
3518 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3519 }")
3521 (define_insn ""
3522 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3523 (match_operand:DI 1 "const_int_operand" "i")
3524 (match_operand:DI 2 "const_int_operand" "i"))
3525 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3526 "TARGET_POWERPC64"
3527 "*
3528 {
3529 int start = INTVAL (operands[2]) & 63;
3530 int size = INTVAL (operands[1]) & 63;
3532 operands[2] = GEN_INT (64 - start - size);
3533 return \"rldimi %0,%3,%H2,%H1\";
3534 }")
3536 (define_expand "extzv"
3537 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3538 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3539 (match_operand:SI 2 "const_int_operand" "i")
3540 (match_operand:SI 3 "const_int_operand" "i")))]
3541 ""
3542 "
3543 {
3544 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3545 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3546 compiler if the address of the structure is taken later. */
3547 if (GET_CODE (operands[0]) == SUBREG
3548 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3549 FAIL;
3550 }")
3552 (define_insn ""
3553 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3554 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3555 (match_operand:SI 2 "const_int_operand" "i")
3556 (match_operand:SI 3 "const_int_operand" "i")))]
3557 ""
3558 "*
3559 {
3560 int start = INTVAL (operands[3]) & 31;
3561 int size = INTVAL (operands[2]) & 31;
3563 if (start + size >= 32)
3564 operands[3] = const0_rtx;
3565 else
3566 operands[3] = GEN_INT (start + size);
3567 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3568 }")
3570 (define_insn ""
3571 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3572 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3573 (match_operand:SI 2 "const_int_operand" "i,i")
3574 (match_operand:SI 3 "const_int_operand" "i,i"))
3575 (const_int 0)))
3576 (clobber (match_scratch:SI 4 "=r,r"))]
3577 ""
3578 "*
3579 {
3580 int start = INTVAL (operands[3]) & 31;
3581 int size = INTVAL (operands[2]) & 31;
3583 /* Split insn if not setting cr0. */
3584 if (cc_reg_not_cr0_operand (operands[0], CCmode))
3585 return \"#\";
3587 /* If the bitfield being tested fits in the upper or lower half of a
3588 word, it is possible to use andiu. or andil. to test it. This is
3589 useful because the condition register set-use delay is smaller for
3590 andi[ul]. than for rlinm. This doesn't work when the starting bit
3591 position is 0 because the LT and GT bits may be set wrong. */
3593 if ((start > 0 && start + size <= 16) || start >= 16)
3594 {
3595 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3596 - (1 << (16 - (start & 15) - size))));
3597 if (start < 16)
3598 return \"{andiu.|andis.} %4,%1,%3\";
3599 else
3600 return \"{andil.|andi.} %4,%1,%3\";
3601 }
3603 if (start + size >= 32)
3604 operands[3] = const0_rtx;
3605 else
3606 operands[3] = GEN_INT (start + size);
3607 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3608 }"
3609 [(set_attr "type" "compare")
3610 (set_attr "length" "4,8")])
3612 (define_split
3613 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3614 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3615 (match_operand:SI 2 "const_int_operand" "")
3616 (match_operand:SI 3 "const_int_operand" ""))
3617 (const_int 0)))
3618 (clobber (match_scratch:SI 4 ""))]
3619 "reload_completed"
3620 [(set (match_dup 4)
3621 (zero_extract:SI (match_dup 1)
3622 (match_dup 2)
3623 (match_dup 3)))
3624 (set (match_dup 0)
3625 (compare:CC (match_dup 4)
3626 (const_int 0)))]
3627 "")
3629 (define_insn ""
3630 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3631 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3632 (match_operand:SI 2 "const_int_operand" "i,i")
3633 (match_operand:SI 3 "const_int_operand" "i,i"))
3634 (const_int 0)))
3635 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3636 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3637 ""
3638 "*
3639 {
3640 int start = INTVAL (operands[3]) & 31;
3641 int size = INTVAL (operands[2]) & 31;
3643 /* Split insn if not setting cr0. */
3644 if (cc_reg_not_cr0_operand (operands[0], CCmode))
3645 return \"#\";
3647 if (start >= 16 && start + size == 32)
3648 {
3649 operands[3] = GEN_INT ((1 << (32 - start)) - 1);
3650 return \"{andil.|andi.} %0,%1,%3\";
3651 }
3653 if (start + size >= 32)
3654 operands[3] = const0_rtx;
3655 else
3656 operands[3] = GEN_INT (start + size);
3657 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3658 }"
3659 [(set_attr "type" "delayed_compare")])
3661 (define_split
3662 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3663 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3664 (match_operand:SI 2 "const_int_operand" "")
3665 (match_operand:SI 3 "const_int_operand" ""))
3666 (const_int 0)))
3667 (set (match_dup 0)
3668 (zero_extract:SI (match_dup 1)
3669 (match_dup 2)
3670 (match_dup 3)))]
3671 "reload_completed"
3672 [(set (match_dup 0)
3673 (zero_extract:SI (match_dup 1)
3674 (match_dup 2)
3675 (match_dup 3)))
3676 (set (match_dup 4)
3677 (compare:CC (match_dup 0)
3678 (const_int 0)))]
3679 "")
3681 (define_insn ""
3682 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3683 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3684 (match_operand:DI 2 "const_int_operand" "i")
3685 (match_operand:DI 3 "const_int_operand" "i")))]
3686 "TARGET_POWERPC64"
3687 "*
3688 {
3689 int start = INTVAL (operands[3]) & 63;
3690 int size = INTVAL (operands[2]) & 63;
3692 if (start + size >= 64)
3693 operands[3] = const0_rtx;
3694 else
3695 operands[3] = GEN_INT (start + size);
3696 operands[2] = GEN_INT (64 - size);
3697 return \"rldicl %0,%1,%3,%2\";
3698 }")
3700 (define_insn ""
3701 [(set (match_operand:CC 0 "gpc_reg_operand" "=x,?y")
3702 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
3703 (match_operand:DI 2 "const_int_operand" "i,i")
3704 (match_operand:DI 3 "const_int_operand" "i,i"))
3705 (const_int 0)))
3706 (clobber (match_scratch:DI 4 "=r,r"))]
3707 "TARGET_POWERPC64"
3708 "*
3709 {
3710 int start = INTVAL (operands[3]) & 63;
3711 int size = INTVAL (operands[2]) & 63;
3713 /* Split insn if not setting cr0. */
3714 if (cc_reg_not_cr0_operand (operands[0], CCmode))
3715 return \"#\";
3717 if (start + size >= 64)
3718 operands[3] = const0_rtx;
3719 else
3720 operands[3] = GEN_INT (start + size);
3721 operands[2] = GEN_INT (64 - size);
3722 return \"rldicl. %4,%1,%3,%2\";
3723 }")
3725 (define_split
3726 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3727 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "")
3728 (match_operand:DI 2 "const_int_operand" "")
3729 (match_operand:DI 3 "const_int_operand" ""))
3730 (const_int 0)))
3731 (clobber (match_scratch:DI 4 ""))]
3732 "reload_completed"
3733 [(set (match_dup 4)
3734 (zero_extract:DI (match_dup 1)
3735 (match_dup 2)
3736 (match_dup 3)))
3737 (set (match_dup 0)
3738 (compare:CC (match_dup 4)
3739 (const_int 0)))]
3740 "")
3742 (define_insn ""
3743 [(set (match_operand:CC 4 "gpc_reg_operand" "=x,?y")
3744 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
3745 (match_operand:DI 2 "const_int_operand" "i,i")
3746 (match_operand:DI 3 "const_int_operand" "i,i"))
3747 (const_int 0)))
3748 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3749 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3750 "TARGET_POWERPC64"
3751 "*
3752 {
3753 int start = INTVAL (operands[3]) & 63;
3754 int size = INTVAL (operands[2]) & 63;
3756 /* Split insn if not setting cr0. */
3757 if (cc_reg_not_cr0_operand (operands[0], CCmode))
3758 return \"#\";
3760 if (start + size >= 64)
3761 operands[3] = const0_rtx;
3762 else
3763 operands[3] = GEN_INT (start + size);
3764 operands[2] = GEN_INT (64 - size);
3765 return \"rldicl. %0,%1,%3,%2\";
3766 }")
3768 (define_split
3769 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3770 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "")
3771 (match_operand:DI 2 "const_int_operand" "")
3772 (match_operand:DI 3 "const_int_operand" ""))
3773 (const_int 0)))
3774 (set (match_dup 0)
3775 (zero_extract:DI (match_dup 1)
3776 (match_dup 2)
3777 (match_dup 3)))]
3778 "reload_completed"
3779 [(set (match_dup 0)
3780 (zero_extract:DI (match_dup 1)
3781 (match_dup 2)
3782 (match_dup 3)))
3783 (set (match_dup 4)
3784 (compare:CC (match_dup 0)
3785 (const_int 0)))]
3786 "")
3788 (define_insn "rotlsi3"
3789 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3790 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3791 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
3792 ""
3793 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
3795 (define_insn "*rotlsi3_internal2"
3796 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3797 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3798 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3799 (const_int 0)))
3800 (clobber (match_scratch:SI 3 "=r,r"))]
3801 ""
3802 "@
3803 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
3804 #"
3805 [(set_attr "type" "delayed_compare")
3806 (set_attr "length" "4,8")])
3808 (define_split
3809 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3810 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3811 (match_operand:SI 2 "reg_or_cint_operand" ""))
3812 (const_int 0)))
3813 (clobber (match_scratch:SI 3 ""))]
3814 "reload_completed"
3815 [(set (match_dup 3)
3816 (rotate:SI (match_dup 1)
3817 (match_dup 2)))
3818 (set (match_dup 0)
3819 (compare:CC (match_dup 3)
3820 (const_int 0)))]
3821 "")
3823 (define_insn "*rotlsi3_internal3"
3824 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3825 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3826 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3827 (const_int 0)))
3828 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3829 (rotate:SI (match_dup 1) (match_dup 2)))]
3830 ""
3831 "@
3832 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
3833 #"
3834 [(set_attr "type" "delayed_compare")
3835 (set_attr "length" "4,8")])
3837 (define_split
3838 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3839 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3840 (match_operand:SI 2 "reg_or_cint_operand" ""))
3841 (const_int 0)))
3842 (set (match_operand:SI 0 "gpc_reg_operand" "")
3843 (rotate:SI (match_dup 1)
3844 (match_dup 2)))]
3845 "reload_completed"
3846 [(set (match_dup 0)
3847 (rotate:SI (match_dup 1)
3848 (match_dup 2)))
3849 (set (match_dup 3)
3850 (compare:CC (match_dup 0)
3851 (const_int 0)))]
3852 "")
3854 (define_insn "*rotlsi3_internal4"
3855 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3856 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3857 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
3858 (match_operand:SI 3 "mask_operand" "L")))]
3859 ""
3860 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
3862 (define_insn "*rotlsi3_internal5"
3863 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3864 (compare:CC (and:SI
3865 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3866 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3867 (match_operand:SI 3 "mask_operand" "L,L"))
3868 (const_int 0)))
3869 (clobber (match_scratch:SI 4 "=r,r"))]
3870 ""
3871 "@
3872 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
3873 #"
3874 [(set_attr "type" "delayed_compare")
3875 (set_attr "length" "4,8")])
3877 (define_split
3878 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3879 (compare:CC (and:SI
3880 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3881 (match_operand:SI 2 "reg_or_cint_operand" ""))
3882 (match_operand:SI 3 "mask_operand" ""))
3883 (const_int 0)))
3884 (clobber (match_scratch:SI 4 ""))]
3885 "reload_completed"
3886 [(set (match_dup 4)
3887 (and:SI (rotate:SI (match_dup 1)
3888 (match_dup 2))
3889 (match_dup 3)))
3890 (set (match_dup 0)
3891 (compare:CC (match_dup 4)
3892 (const_int 0)))]
3893 "")
3895 (define_insn "*rotlsi3_internal6"
3896 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3897 (compare:CC (and:SI
3898 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3899 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
3900 (match_operand:SI 3 "mask_operand" "L,L"))
3901 (const_int 0)))
3902 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3903 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
3904 ""
3905 "@
3906 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
3907 #"
3908 [(set_attr "type" "delayed_compare")
3909 (set_attr "length" "4,8")])
3911 (define_split
3912 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3913 (compare:CC (and:SI
3914 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3915 (match_operand:SI 2 "reg_or_cint_operand" ""))
3916 (match_operand:SI 3 "mask_operand" ""))
3917 (const_int 0)))
3918 (set (match_operand:SI 0 "gpc_reg_operand" "")
3919 (and:SI
3920 (rotate:SI (match_dup 1)
3921 (match_dup 2))
3922 (match_dup 3)))]
3923 "reload_completed"
3924 [(set (match_dup 0)
3925 (and:SI (rotate:SI (match_dup 1)
3926 (match_dup 2))
3927 (match_dup 3)))
3928 (set (match_dup 4)
3929 (compare:CC (match_dup 0)
3930 (const_int 0)))]
3931 "")
3933 (define_insn "*rotlsi3_internal7"
3934 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3935 (zero_extend:SI
3936 (subreg:QI
3937 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3938 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
3939 ""
3940 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
3942 (define_insn "*rotlsi3_internal8"
3943 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3944 (compare:CC (zero_extend:SI
3945 (subreg:QI
3946 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3947 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3948 (const_int 0)))
3949 (clobber (match_scratch:SI 3 "=r,r"))]
3950 ""
3951 "@
3952 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
3953 #"
3954 [(set_attr "type" "delayed_compare")
3955 (set_attr "length" "4,8")])
3957 (define_split
3958 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3959 (compare:CC (zero_extend:SI
3960 (subreg:QI
3961 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3962 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
3963 (const_int 0)))
3964 (clobber (match_scratch:SI 3 ""))]
3965 "reload_completed"
3966 [(set (match_dup 3)
3967 (zero_extend:SI
3968 (subreg:QI
3969 (rotate:SI (match_dup 1)
3970 (match_dup 2)) 0)))
3971 (set (match_dup 0)
3972 (compare:CC (match_dup 3)
3973 (const_int 0)))]
3974 "")
3976 (define_insn "*rotlsi3_internal9"
3977 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3978 (compare:CC (zero_extend:SI
3979 (subreg:QI
3980 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3981 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3982 (const_int 0)))
3983 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3984 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
3985 ""
3986 "@
3987 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
3988 #"
3989 [(set_attr "type" "delayed_compare")
3990 (set_attr "length" "4,8")])
3992 (define_split
3993 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "=x,?y")
3994 (compare:CC (zero_extend:SI
3995 (subreg:QI
3996 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3997 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
3998 (const_int 0)))
3999 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4000 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4001 "reload_completed"
4002 [(set (match_dup 0)
4003 (zero_extend:SI
4004 (subreg:QI
4005 (rotate:SI (match_dup 1)
4006 (match_dup 2)) 0)))
4007 (set (match_dup 3)
4008 (compare:CC (match_dup 0)
4009 (const_int 0)))]
4010 "")
4012 (define_insn "*rotlsi3_internal10"
4013 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4014 (zero_extend:SI
4015 (subreg:HI
4016 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4017 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4018 ""
4019 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
4021 (define_insn "*rotlsi3_internal11"
4022 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4023 (compare:CC (zero_extend:SI
4024 (subreg:HI
4025 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4026 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
4027 (const_int 0)))
4028 (clobber (match_scratch:SI 3 "=r,r"))]
4029 ""
4030 "@
4031 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
4032 #"
4033 [(set_attr "type" "delayed_compare")
4034 (set_attr "length" "4,8")])
4036 (define_split
4037 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4038 (compare:CC (zero_extend:SI
4039 (subreg:HI
4040 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4041 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4042 (const_int 0)))
4043 (clobber (match_scratch:SI 3 ""))]
4044 "reload_completed"
4045 [(set (match_dup 3)
4046 (zero_extend:SI
4047 (subreg:HI
4048 (rotate:SI (match_dup 1)
4049 (match_dup 2)) 0)))
4050 (set (match_dup 0)
4051 (compare:CC (match_dup 3)
4052 (const_int 0)))]
4053 "")
4055 (define_insn "*rotlsi3_internal12"
4056 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4057 (compare:CC (zero_extend:SI
4058 (subreg:HI
4059 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4060 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
4061 (const_int 0)))
4062 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4063 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4064 ""
4065 "@
4066 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
4067 #"
4068 [(set_attr "type" "delayed_compare")
4069 (set_attr "length" "4,8")])
4071 (define_split
4072 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "=x,?y")
4073 (compare:CC (zero_extend:SI
4074 (subreg:HI
4075 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4076 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
4077 (const_int 0)))
4078 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4079 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4080 "reload_completed"
4081 [(set (match_dup 0)
4082 (zero_extend:SI
4083 (subreg:HI
4084 (rotate:SI (match_dup 1)
4085 (match_dup 2)) 0)))
4086 (set (match_dup 3)
4087 (compare:CC (match_dup 0)
4088 (const_int 0)))]
4089 "")
4091 ;; Note that we use "sle." instead of "sl." so that we can set
4092 ;; SHIFT_COUNT_TRUNCATED.
4094 (define_expand "ashlsi3"
4095 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4096 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4097 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4098 ""
4099 "
4100 {
4101 if (TARGET_POWER)
4102 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4103 else
4104 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4105 DONE;
4106 }")
4108 (define_insn "ashlsi3_power"
4109 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4110 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4111 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4112 (clobber (match_scratch:SI 3 "=q,X"))]
4113 "TARGET_POWER"
4114 "@
4115 sle %0,%1,%2
4116 {sli|slwi} %0,%1,%h2"
4117 [(set_attr "length" "8")])
4119 (define_insn "ashlsi3_no_power"
4120 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4121 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4122 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4123 "! TARGET_POWER"
4124 "{sl|slw}%I2 %0,%1,%h2"
4125 [(set_attr "length" "8")])
4127 (define_insn ""
4128 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4129 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4130 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4131 (const_int 0)))
4132 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4133 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4134 "TARGET_POWER"
4135 "@
4136 sle. %3,%1,%2
4137 {sli.|slwi.} %3,%1,%h2
4138 #
4139 #"
4140 [(set_attr "type" "delayed_compare")
4141 (set_attr "length" "4,4,8,8")])
4143 (define_split
4144 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4145 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4146 (match_operand:SI 2 "reg_or_cint_operand" ""))
4147 (const_int 0)))
4148 (clobber (match_scratch:SI 3 ""))
4149 (clobber (match_scratch:SI 4 ""))]
4150 "TARGET_POWER && reload_completed"
4151 [(parallel [(set (match_dup 3)
4152 (ashift:SI (match_dup 1)
4153 (match_dup 2)))
4154 (clobber (match_dup 4))])
4155 (set (match_dup 0)
4156 (compare:CC (match_dup 3)
4157 (const_int 0)))]
4158 "")
4160 (define_insn ""
4161 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4162 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4163 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4164 (const_int 0)))
4165 (clobber (match_scratch:SI 3 "=r,r"))]
4166 "! TARGET_POWER"
4167 "@
4168 {sl|slw}%I2. %3,%1,%h2
4169 #"
4170 [(set_attr "type" "delayed_compare")
4171 (set_attr "length" "4,8")])
4173 (define_split
4174 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4175 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4176 (match_operand:SI 2 "reg_or_cint_operand" ""))
4177 (const_int 0)))
4178 (clobber (match_scratch:SI 3 ""))]
4179 "! TARGET_POWER && reload_completed"
4180 [(set (match_dup 3)
4181 (ashift:SI (match_dup 1)
4182 (match_dup 2)))
4183 (set (match_dup 0)
4184 (compare:CC (match_dup 3)
4185 (const_int 0)))]
4186 "")
4188 (define_insn ""
4189 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4190 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4191 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4192 (const_int 0)))
4193 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4194 (ashift:SI (match_dup 1) (match_dup 2)))
4195 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4196 "TARGET_POWER"
4197 "@
4198 sle. %0,%1,%2
4199 {sli.|slwi.} %0,%1,%h2
4200 #
4201 #"
4202 [(set_attr "type" "delayed_compare")])
4204 (define_split
4205 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4206 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4207 (match_operand:SI 2 "reg_or_cint_operand" ""))
4208 (const_int 0)))
4209 (set (match_operand:SI 0 "gpc_reg_operand" "")
4210 (ashift:SI (match_dup 1)
4211 (match_dup 2)))
4212 (clobber (match_scratch:SI 4 ""))]
4213 "TARGET_POWER && reload_completed"
4214 [(parallel [(set (match_dup 0)
4215 (ashift:SI (match_dup 1)
4216 (match_dup 2)))
4217 (clobber (match_dup 4))])
4218 (set (match_dup 3)
4219 (compare:CC (match_dup 0)
4220 (const_int 0)))]
4221 "")
4223 (define_insn ""
4224 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4225 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4226 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4227 (const_int 0)))
4228 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4229 (ashift:SI (match_dup 1) (match_dup 2)))]
4230 "! TARGET_POWER"
4231 "{sl|slw}%I2. %0,%1,%h2"
4232 [(set_attr "type" "delayed_compare")])
4234 (define_split
4235 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4236 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4237 (match_operand:SI 2 "reg_or_cint_operand" ""))
4238 (const_int 0)))
4239 (set (match_operand:SI 0 "gpc_reg_operand" "")
4240 (ashift:SI (match_dup 1)
4241 (match_dup 2)))]
4242 "! TARGET_POWER && reload_completed"
4243 [(set (match_dup 0)
4244 (ashift:SI (match_dup 1)
4245 (match_dup 2)))
4246 (set (match_dup 3)
4247 (compare:CC (match_dup 0)
4248 (const_int 0)))]
4249 "")
4251 (define_insn ""
4252 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4253 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4254 (match_operand:SI 2 "const_int_operand" "i"))
4255 (match_operand:SI 3 "mask_operand" "L")))]
4256 "includes_lshift_p (operands[2], operands[3])"
4257 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4259 (define_insn ""
4260 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4261 (compare:CC
4262 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4263 (match_operand:SI 2 "const_int_operand" "i,i"))
4264 (match_operand:SI 3 "mask_operand" "L,L"))
4265 (const_int 0)))
4266 (clobber (match_scratch:SI 4 "=r,r"))]
4267 "includes_lshift_p (operands[2], operands[3])"
4268 "{rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3"
4269 [(set_attr "type" "delayed_compare")])
4271 (define_split
4272 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4273 (compare:CC
4274 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4275 (match_operand:SI 2 "const_int_operand" ""))
4276 (match_operand:SI 3 "mask_operand" ""))
4277 (const_int 0)))
4278 (clobber (match_scratch:SI 4 ""))]
4279 "reload_completed && includes_lshift_p (operands[2], operands[3])"
4280 [(set (match_dup 4)
4281 (and:SI (ashift:SI (match_dup 1)
4282 (match_dup 2))
4283 (match_dup 3)))
4284 (set (match_dup 0)
4285 (compare:CC (match_dup 4)
4286 (const_int 0)))]
4287 "")
4289 (define_insn ""
4290 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4291 (compare:CC
4292 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4293 (match_operand:SI 2 "const_int_operand" "i,i"))
4294 (match_operand:SI 3 "mask_operand" "L,L"))
4295 (const_int 0)))
4296 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4297 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4298 "includes_lshift_p (operands[2], operands[3])"
4299 "{rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3"
4300 [(set_attr "type" "delayed_compare")])
4302 (define_split
4303 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4304 (compare:CC
4305 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4306 (match_operand:SI 2 "const_int_operand" ""))
4307 (match_operand:SI 3 "mask_operand" ""))
4308 (const_int 0)))
4309 (set (match_operand:SI 0 "gpc_reg_operand" "")
4310 (and:SI (ashift:SI (match_dup 1)
4311 (match_dup 2))
4312 (match_dup 3)))]
4313 "reload_completed && includes_lshift_p (operands[2], operands[3])"
4314 [(set (match_dup 4)
4315 (and:SI (ashift:SI (match_dup 1)
4316 (match_dup 2))
4317 (match_dup 3)))
4318 (set (match_dup 0)
4319 (compare:CC (match_dup 4)
4320 (const_int 0)))]
4321 "")
4323 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4324 ;; "sli x,x,0".
4325 (define_expand "lshrsi3"
4326 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4327 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4328 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4329 ""
4330 "
4331 {
4332 if (TARGET_POWER)
4333 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4334 else
4335 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4336 DONE;
4337 }")
4339 (define_insn "lshrsi3_power"
4340 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4341 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4342 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4343 (clobber (match_scratch:SI 3 "=q,X,X"))]
4344 "TARGET_POWER"
4345 "@
4346 sre %0,%1,%2
4347 mr %0,%1
4348 {s%A2i|s%A2wi} %0,%1,%h2")
4350 (define_insn "lshrsi3_no_power"
4351 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4352 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4353 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
4354 "! TARGET_POWER"
4355 "@
4356 mr %0,%1
4357 {sr|srw}%I2 %0,%1,%h2")
4359 (define_insn ""
4360 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,y,?y")
4361 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4362 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4363 (const_int 0)))
4364 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4365 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4366 "TARGET_POWER"
4367 "@
4368 sre. %3,%1,%2
4369 mr. %1,%1
4370 {s%A2i.|s%A2wi.} %3,%1,%h2
4371 #
4372 cmpli %0,%1,0
4373 #"
4374 [(set_attr "type" "delayed_compare")
4375 (set_attr "length" "4,4,4,8,8,8")])
4377 (define_split
4378 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4379 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4380 (match_operand:SI 2 "reg_or_cint_operand" ""))
4381 (const_int 0)))
4382 (clobber (match_scratch:SI 3 ""))
4383 (clobber (match_scratch:SI 4 ""))]
4384 "TARGET_POWER && reload_completed
4385 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
4386 [(parallel [(set (match_dup 3)
4387 (lshiftrt:SI (match_dup 1)
4388 (match_dup 2)))
4389 (clobber (match_dup 4))])
4390 (set (match_dup 0)
4391 (compare:CC (match_dup 3)
4392 (const_int 0)))]
4393 "")
4395 (define_insn ""
4396 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,y,?y")
4397 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4398 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4399 (const_int 0)))
4400 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
4401 "! TARGET_POWER"
4402 "@
4403 mr. %1,%1
4404 {sr|srw}%I2. %3,%1,%h2
4405 cmpli %0,%1,0
4406 #"
4407 [(set_attr "type" "delayed_compare")
4408 (set_attr "length" "4,4,4,8")])
4410 (define_split
4411 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4412 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4413 (match_operand:SI 2 "reg_or_cint_operand" ""))
4414 (const_int 0)))
4415 (clobber (match_scratch:SI 3 ""))]
4416 "! TARGET_POWER && reload_completed
4417 && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
4418 [(set (match_dup 3)
4419 (lshiftrt:SI (match_dup 1)
4420 (match_dup 2)))
4421 (set (match_dup 0)
4422 (compare:CC (match_dup 3)
4423 (const_int 0)))]
4424 "")
4426 (define_insn ""
4427 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y")
4428 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4429 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,rOi"))
4430 (const_int 0)))
4431 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4432 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4433 (clobber (match_scratch:SI 4 "=q,X,X,q"))]
4434 "TARGET_POWER"
4435 "@
4436 sre. %0,%1,%2
4437 mr. %0,%1
4438 {s%A2i.|s%A2wi.} %0,%1,%h2
4439 #"
4440 [(set_attr "type" "delayed_compare")
4441 (set_attr "length" "4,4,4,8")])
4443 (define_split
4444 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4445 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4446 (match_operand:SI 2 "reg_or_cint_operand" ""))
4447 (const_int 0)))
4448 (set (match_operand:SI 0 "gpc_reg_operand" "")
4449 (lshiftrt:SI (match_dup 1)
4450 (match_dup 2)))
4451 (clobber (match_scratch:SI 4 ""))]
4452 "TARGET_POWER && reload_completed"
4453 [(parallel [(set (match_dup 3)
4454 (lshiftrt:SI (match_dup 1)
4455 (match_dup 2)))
4456 (clobber (match_dup 4))])
4457 (set (match_dup 0)
4458 (compare:CC (match_dup 3)
4459 (const_int 0)))]
4460 "")
4462 (define_insn ""
4463 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4464 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4465 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4466 (const_int 0)))
4467 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4468 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4469 "! TARGET_POWER"
4470 "@
4471 mr. %0,%1
4472 {sr|srw}%I2. %0,%1,%h2
4473 #
4474 #"
4475 [(set_attr "type" "delayed_compare")
4476 (set_attr "length" "4,4,8,8")])
4478 (define_split
4479 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4480 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4481 (match_operand:SI 2 "reg_or_cint_operand" ""))
4482 (const_int 0)))
4483 (set (match_operand:SI 0 "gpc_reg_operand" "")
4484 (lshiftrt:SI (match_dup 1)
4485 (match_dup 2)))]
4486 "! TARGET_POWER && reload_completed"
4487 [(set (match_dup 0)
4488 (lshiftrt:SI (match_dup 1)
4489 (match_dup 2)))
4490 (set (match_dup 3)
4491 (compare:CC (match_dup 0)
4492 (const_int 0)))]
4493 "")
4495 (define_insn ""
4496 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4497 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4498 (match_operand:SI 2 "const_int_operand" "i"))
4499 (match_operand:SI 3 "mask_operand" "L")))]
4500 "includes_rshift_p (operands[2], operands[3])"
4501 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4503 (define_insn ""
4504 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4505 (compare:CC
4506 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4507 (match_operand:SI 2 "const_int_operand" "i,i"))
4508 (match_operand:SI 3 "mask_operand" "L,L"))
4509 (const_int 0)))
4510 (clobber (match_scratch:SI 4 "=r,r"))]
4511 "includes_rshift_p (operands[2], operands[3])"
4512 "@
4513 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4514 #"
4515 [(set_attr "type" "delayed_compare")
4516 (set_attr "length" "4,8")])
4518 (define_split
4519 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4520 (compare:CC
4521 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4522 (match_operand:SI 2 "const_int_operand" ""))
4523 (match_operand:SI 3 "mask_operand" ""))
4524 (const_int 0)))
4525 (clobber (match_scratch:SI 4 ""))]
4526 "reload_completed && includes_rshift_p (operands[2], operands[3])"
4527 [(set (match_dup 4)
4528 (and:SI (lshiftrt:SI (match_dup 1)
4529 (match_dup 2))
4530 (match_dup 3)))
4531 (set (match_dup 0)
4532 (compare:CC (match_dup 4)
4533 (const_int 0)))]
4534 "")
4536 (define_insn ""
4537 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4538 (compare:CC
4539 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4540 (match_operand:SI 2 "const_int_operand" "i,i"))
4541 (match_operand:SI 3 "mask_operand" "L,L"))
4542 (const_int 0)))
4543 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4544 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4545 "includes_rshift_p (operands[2], operands[3])"
4546 "@
4547 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4548 #"
4549 [(set_attr "type" "delayed_compare")
4550 (set_attr "length" "4,8")])
4552 (define_split
4553 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4554 (compare:CC
4555 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4556 (match_operand:SI 2 "const_int_operand" ""))
4557 (match_operand:SI 3 "mask_operand" ""))
4558 (const_int 0)))
4559 (set (match_operand:SI 0 "gpc_reg_operand" "")
4560 (and:SI (lshiftrt:SI (match_dup 1)
4561 (match_dup 2))
4562 (match_dup 3)))]
4563 "reload_completed && includes_rshift_p (operands[2], operands[3])"
4564 [(set (match_dup 4)
4565 (and:SI (lshiftrt:SI (match_dup 1)
4566 (match_dup 2))
4567 (match_dup 3)))
4568 (set (match_dup 0)
4569 (compare:CC (match_dup 4)
4570 (const_int 0)))]
4571 "")
4573 (define_insn ""
4574 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4575 (zero_extend:SI
4576 (subreg:QI
4577 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4578 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4579 "includes_rshift_p (operands[2], GEN_INT (255))"
4580 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4582 (define_insn ""
4583 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4584 (compare:CC
4585 (zero_extend:SI
4586 (subreg:QI
4587 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4588 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4589 (const_int 0)))
4590 (clobber (match_scratch:SI 3 "=r,r"))]
4591 "includes_rshift_p (operands[2], GEN_INT (255))"
4592 "@
4593 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4594 #"
4595 [(set_attr "type" "delayed_compare")
4596 (set_attr "length" "4,8")])
4598 (define_split
4599 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4600 (compare:CC
4601 (zero_extend:SI
4602 (subreg:QI
4603 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4604 (match_operand:SI 2 "const_int_operand" "")) 0))
4605 (const_int 0)))
4606 (clobber (match_scratch:SI 3 ""))]
4607 "reload_completed && includes_rshift_p (operands[2], GEN_INT (255))"
4608 [(set (match_dup 3)
4609 (zero_extend:SI
4610 (subreg:QI
4611 (lshiftrt:SI (match_dup 1)
4612 (match_dup 2)) 0)))
4613 (set (match_dup 0)
4614 (compare:CC (match_dup 3)
4615 (const_int 0)))]
4616 "")
4618 (define_insn ""
4619 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4620 (compare:CC
4621 (zero_extend:SI
4622 (subreg:QI
4623 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4624 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4625 (const_int 0)))
4626 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4627 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4628 "includes_rshift_p (operands[2], GEN_INT (255))"
4629 "@
4630 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4631 #"
4632 [(set_attr "type" "delayed_compare")
4633 (set_attr "length" "4,8")])
4635 (define_split
4636 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4637 (compare:CC
4638 (zero_extend:SI
4639 (subreg:QI
4640 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4641 (match_operand:SI 2 "const_int_operand" "")) 0))
4642 (const_int 0)))
4643 (set (match_operand:SI 0 "gpc_reg_operand" "")
4644 (zero_extend:SI
4645 (subreg:QI
4646 (lshiftrt:SI (match_dup 1)
4647 (match_dup 2)) 0)))]
4648 "reload_completed && includes_rshift_p (operands[2], GEN_INT (255))"
4649 [(set (match_dup 0)
4650 (zero_extend:SI
4651 (subreg:QI
4652 (lshiftrt:SI (match_dup 1)
4653 (match_dup 2)) 0)))
4654 (set (match_dup 3)
4655 (compare:CC (match_dup 0)
4656 (const_int 0)))]
4657 "")
4659 (define_insn ""
4660 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4661 (zero_extend:SI
4662 (subreg:HI
4663 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4664 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4665 "includes_rshift_p (operands[2], GEN_INT (65535))"
4666 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4668 (define_split
4669 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4670 (compare:CC
4671 (zero_extend:SI
4672 (subreg:HI
4673 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4674 (match_operand:SI 2 "const_int_operand" "")) 0))
4675 (const_int 0)))
4676 (clobber (match_scratch:SI 3 ""))]
4677 "reload_completed && includes_rshift_p (operands[2], GEN_INT (255))"
4678 [(set (match_dup 3)
4679 (zero_extend:SI
4680 (subreg:HI
4681 (lshiftrt:SI (match_dup 1)
4682 (match_dup 2)) 0)))
4683 (set (match_dup 0)
4684 (compare:CC (match_dup 3)
4685 (const_int 0)))]
4686 "")
4688 (define_insn ""
4689 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4690 (compare:CC
4691 (zero_extend:SI
4692 (subreg:HI
4693 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4694 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4695 (const_int 0)))
4696 (clobber (match_scratch:SI 3 "=r,r"))]
4697 "includes_rshift_p (operands[2], GEN_INT (65535))"
4698 "@
4699 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4700 #"
4701 [(set_attr "type" "delayed_compare")
4702 (set_attr "length" "4,8")])
4704 (define_insn ""
4705 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4706 (compare:CC
4707 (zero_extend:SI
4708 (subreg:HI
4709 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4710 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4711 (const_int 0)))
4712 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4713 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4714 "includes_rshift_p (operands[2], GEN_INT (65535))"
4715 "{rlinm.|rlwinm.} %0,%1,%s2,0xffff"
4716 [(set_attr "type" "delayed_compare")])
4718 (define_split
4719 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4720 (compare:CC
4721 (zero_extend:SI
4722 (subreg:HI
4723 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4724 (match_operand:SI 2 "const_int_operand" "")) 0))
4725 (const_int 0)))
4726 (set (match_operand:SI 0 "gpc_reg_operand" "")
4727 (zero_extend:SI
4728 (subreg:HI
4729 (lshiftrt:SI (match_dup 1)
4730 (match_dup 2)) 0)))]
4731 "reload_completed && includes_rshift_p (operands[2], GEN_INT (255))"
4732 [(set (match_dup 0)
4733 (zero_extend:SI
4734 (subreg:HI
4735 (lshiftrt:SI (match_dup 1)
4736 (match_dup 2)) 0)))
4737 (set (match_dup 3)
4738 (compare:CC (match_dup 0)
4739 (const_int 0)))]
4740 "")
4742 (define_insn ""
4743 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4744 (const_int 1)
4745 (match_operand:SI 1 "gpc_reg_operand" "r"))
4746 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4747 (const_int 31)))]
4748 "TARGET_POWER"
4749 "rrib %0,%1,%2")
4751 (define_insn ""
4752 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4753 (const_int 1)
4754 (match_operand:SI 1 "gpc_reg_operand" "r"))
4755 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4756 (const_int 31)))]
4757 "TARGET_POWER"
4758 "rrib %0,%1,%2")
4760 (define_insn ""
4761 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4762 (const_int 1)
4763 (match_operand:SI 1 "gpc_reg_operand" "r"))
4764 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4765 (const_int 1)
4766 (const_int 0)))]
4767 "TARGET_POWER"
4768 "rrib %0,%1,%2")
4770 (define_expand "ashrsi3"
4771 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4772 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4773 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4774 ""
4775 "
4776 {
4777 if (TARGET_POWER)
4778 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4779 else
4780 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4781 DONE;
4782 }")
4784 (define_insn "ashrsi3_power"
4785 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4786 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4787 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4788 (clobber (match_scratch:SI 3 "=q,X"))]
4789 "TARGET_POWER"
4790 "@
4791 srea %0,%1,%2
4792 {srai|srawi} %0,%1,%h2")
4794 (define_insn "ashrsi3_no_power"
4795 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4796 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4797 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4798 "! TARGET_POWER"
4799 "{sra|sraw}%I2 %0,%1,%h2")
4801 (define_insn ""
4802 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4803 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4804 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4805 (const_int 0)))
4806 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4807 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4808 "TARGET_POWER"
4809 "@
4810 srea. %3,%1,%2
4811 {srai.|srawi.} %3,%1,%h2
4812 #
4813 #"
4814 [(set_attr "type" "delayed_compare")
4815 (set_attr "length" "4,4,8,8")])
4817 (define_split
4818 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4819 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4820 (match_operand:SI 2 "reg_or_cint_operand" ""))
4821 (const_int 0)))
4822 (clobber (match_scratch:SI 3 ""))
4823 (clobber (match_scratch:SI 4 ""))]
4824 "TARGET_POWER && reload_completed"
4825 [(parallel [(set (match_dup 3)
4826 (ashiftrt:SI (match_dup 1)
4827 (match_dup 2)))
4828 (clobber (match_dup 4))])
4829 (set (match_dup 0)
4830 (compare:CC (match_dup 3)
4831 (const_int 0)))]
4832 "")
4834 (define_insn ""
4835 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4836 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4837 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4838 (const_int 0)))
4839 (clobber (match_scratch:SI 3 "=r,r"))]
4840 "! TARGET_POWER"
4841 "@
4842 {sra|sraw}%I2. %3,%1,%h2
4843 #"
4844 [(set_attr "type" "delayed_compare")
4845 (set_attr "length" "4,8")])
4847 (define_split
4848 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4849 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4850 (match_operand:SI 2 "reg_or_cint_operand" ""))
4851 (const_int 0)))
4852 (clobber (match_scratch:SI 3 ""))]
4853 "reload_completed"
4854 [(set (match_dup 3)
4855 (ashiftrt:SI (match_dup 1)
4856 (match_dup 2)))
4857 (set (match_dup 0)
4858 (compare:CC (match_dup 3)
4859 (const_int 0)))]
4860 "")
4862 (define_insn ""
4863 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4864 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4865 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4866 (const_int 0)))
4867 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4868 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4869 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4870 "TARGET_POWER"
4871 "@
4872 srea. %0,%1,%2
4873 {srai.|srawi.} %0,%1,%h2
4874 #
4875 #"
4876 [(set_attr "type" "delayed_compare")
4877 (set_attr "length" "4,4,8,8")])
4879 (define_split
4880 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4881 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4882 (match_operand:SI 2 "reg_or_cint_operand" ""))
4883 (const_int 0)))
4884 (set (match_operand:SI 0 "gpc_reg_operand" "")
4885 (ashiftrt:SI (match_dup 1)
4886 (match_dup 2)))
4887 (clobber (match_scratch:SI 4 ""))]
4888 "TARGET_POWER && reload_completed"
4889 [(parallel [(set (match_dup 0)
4890 (ashiftrt:SI (match_dup 1)
4891 (match_dup 2)))
4892 (clobber (match_dup 4))])
4893 (set (match_dup 3)
4894 (compare:CC (match_dup 0)
4895 (const_int 0)))]
4896 "")
4898 (define_insn ""
4899 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4900 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4901 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4902 (const_int 0)))
4903 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4904 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4905 "! TARGET_POWER"
4906 "@
4907 {sra|sraw}%I2. %0,%1,%h2
4908 #"
4909 [(set_attr "type" "delayed_compare")
4910 (set_attr "length" "4,8")])
4912 (define_split
4913 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4914 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4915 (match_operand:SI 2 "reg_or_cint_operand" ""))
4916 (const_int 0)))
4917 (set (match_operand:SI 0 "gpc_reg_operand" "")
4918 (ashiftrt:SI (match_dup 1)
4919 (match_dup 2)))]
4920 "! TARGET_POWER && reload_completed"
4921 [(set (match_dup 0)
4922 (ashiftrt:SI (match_dup 1)
4923 (match_dup 2)))
4924 (set (match_dup 3)
4925 (compare:CC (match_dup 0)
4926 (const_int 0)))]
4927 "")
4928 \f
4929 ;; Floating-point insns, excluding normal data motion.
4930 ;;
4931 ;; PowerPC has a full set of single-precision floating point instructions.
4932 ;;
4933 ;; For the POWER architecture, we pretend that we have both SFmode and
4934 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4935 ;; The only conversions we will do will be when storing to memory. In that
4936 ;; case, we will use the "frsp" instruction before storing.
4937 ;;
4938 ;; Note that when we store into a single-precision memory location, we need to
4939 ;; use the frsp insn first. If the register being stored isn't dead, we
4940 ;; need a scratch register for the frsp. But this is difficult when the store
4941 ;; is done by reload. It is not incorrect to do the frsp on the register in
4942 ;; this case, we just lose precision that we would have otherwise gotten but
4943 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4945 (define_insn "extendsfdf2"
4946 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
4947 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4948 "TARGET_HARD_FLOAT"
4949 "*
4950 {
4951 if (REGNO (operands[0]) == REGNO (operands[1]))
4952 return \"\";
4953 else
4954 return \"fmr %0,%1\";
4955 }"
4956 [(set_attr "type" "fp")])
4958 (define_insn "truncdfsf2"
4959 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4960 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
4961 "TARGET_HARD_FLOAT"
4962 "frsp %0,%1"
4963 [(set_attr "type" "fp")])
4965 (define_insn "aux_truncdfsf2"
4966 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4967 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))]
4968 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
4969 "frsp %0,%1"
4970 [(set_attr "type" "fp")])
4972 (define_insn "negsf2"
4973 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4974 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4975 "TARGET_HARD_FLOAT"
4976 "fneg %0,%1"
4977 [(set_attr "type" "fp")])
4979 (define_insn "abssf2"
4980 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4981 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4982 "TARGET_HARD_FLOAT"
4983 "fabs %0,%1"
4984 [(set_attr "type" "fp")])
4986 (define_insn ""
4987 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4988 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4989 "TARGET_HARD_FLOAT"
4990 "fnabs %0,%1"
4991 [(set_attr "type" "fp")])
4993 (define_expand "addsf3"
4994 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4995 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4996 (match_operand:SF 2 "gpc_reg_operand" "")))]
4997 "TARGET_HARD_FLOAT"
4998 "")
5000 (define_insn ""
5001 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5002 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5003 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5004 "TARGET_POWERPC && TARGET_HARD_FLOAT"
5005 "fadds %0,%1,%2"
5006 [(set_attr "type" "fp")])
5008 (define_insn ""
5009 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5010 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5011 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5012 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
5013 "{fa|fadd} %0,%1,%2"
5014 [(set_attr "type" "fp")])
5016 (define_expand "subsf3"
5017 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5018 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5019 (match_operand:SF 2 "gpc_reg_operand" "")))]
5020 "TARGET_HARD_FLOAT"
5021 "")
5023 (define_insn ""
5024 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5025 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5026 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5027 "TARGET_POWERPC && TARGET_HARD_FLOAT"
5028 "fsubs %0,%1,%2"
5029 [(set_attr "type" "fp")])
5031 (define_insn ""
5032 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5033 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5034 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5035 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
5036 "{fs|fsub} %0,%1,%2"
5037 [(set_attr "type" "fp")])
5039 (define_expand "mulsf3"
5040 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5041 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5042 (match_operand:SF 2 "gpc_reg_operand" "")))]
5043 "TARGET_HARD_FLOAT"
5044 "")
5046 (define_insn ""
5047 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5048 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5049 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5050 "TARGET_POWERPC && TARGET_HARD_FLOAT"
5051 "fmuls %0,%1,%2"
5052 [(set_attr "type" "fp")])
5054 (define_insn ""
5055 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5056 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5057 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5058 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
5059 "{fm|fmul} %0,%1,%2"
5060 [(set_attr "type" "dmul")])
5062 (define_expand "divsf3"
5063 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5064 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5065 (match_operand:SF 2 "gpc_reg_operand" "")))]
5066 "TARGET_HARD_FLOAT"
5067 "")
5069 (define_insn ""
5070 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5071 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5072 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5073 "TARGET_POWERPC && TARGET_HARD_FLOAT"
5074 "fdivs %0,%1,%2"
5075 [(set_attr "type" "sdiv")])
5077 (define_insn ""
5078 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5079 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5080 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5081 "! TARGET_POWERPC && TARGET_HARD_FLOAT"
5082 "{fd|fdiv} %0,%1,%2"
5083 [(set_attr "type" "ddiv")])
5085 (define_insn ""
5086 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5087 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5088 (match_operand:SF 2 "gpc_reg_operand" "f"))
5089 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5090 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5091 "fmadds %0,%1,%2,%3"
5092 [(set_attr "type" "fp")])
5094 (define_insn ""
5095 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5096 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5097 (match_operand:SF 2 "gpc_reg_operand" "f"))
5098 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5099 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5100 "{fma|fmadd} %0,%1,%2,%3"
5101 [(set_attr "type" "dmul")])
5103 (define_insn ""
5104 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5105 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5106 (match_operand:SF 2 "gpc_reg_operand" "f"))
5107 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5108 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5109 "fmsubs %0,%1,%2,%3"
5110 [(set_attr "type" "fp")])
5112 (define_insn ""
5113 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5114 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5115 (match_operand:SF 2 "gpc_reg_operand" "f"))
5116 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5117 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5118 "{fms|fmsub} %0,%1,%2,%3"
5119 [(set_attr "type" "dmul")])
5121 (define_insn ""
5122 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5123 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5124 (match_operand:SF 2 "gpc_reg_operand" "f"))
5125 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5126 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5127 "fnmadds %0,%1,%2,%3"
5128 [(set_attr "type" "fp")])
5130 (define_insn ""
5131 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5132 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5133 (match_operand:SF 2 "gpc_reg_operand" "f"))
5134 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5135 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5136 "{fnma|fnmadd} %0,%1,%2,%3"
5137 [(set_attr "type" "dmul")])
5139 (define_insn ""
5140 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5141 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5142 (match_operand:SF 2 "gpc_reg_operand" "f"))
5143 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5144 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5145 "fnmsubs %0,%1,%2,%3"
5146 [(set_attr "type" "fp")])
5148 (define_insn ""
5149 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5150 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5151 (match_operand:SF 2 "gpc_reg_operand" "f"))
5152 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5153 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5154 "{fnms|fnmsub} %0,%1,%2,%3"
5155 [(set_attr "type" "dmul")])
5157 (define_expand "sqrtsf2"
5158 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5159 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5160 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
5161 "")
5163 (define_insn ""
5164 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5165 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5166 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT"
5167 "fsqrts %0,%1"
5168 [(set_attr "type" "ssqrt")])
5170 (define_insn ""
5171 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5172 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5173 "TARGET_POWER2 && TARGET_HARD_FLOAT"
5174 "fsqrt %0,%1"
5175 [(set_attr "type" "dsqrt")])
5177 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5178 ;; fsel instruction and some auxiliary computations. Then we just have a
5179 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5180 ;; combine.
5181 (define_expand "maxsf3"
5182 [(set (match_dup 3)
5183 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5184 (match_operand:SF 2 "gpc_reg_operand" "")))
5185 (set (match_operand:SF 0 "gpc_reg_operand" "")
5186 (if_then_else:SF (ge (match_dup 3)
5187 (const_int 0))
5188 (match_dup 1)
5189 (match_dup 2)))]
5190 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5191 "
5192 { operands[3] = gen_reg_rtx (SFmode); }")
5194 (define_split
5195 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5196 (smax:SF (match_operand:SF 1 "gpc_reg_operand" "")
5197 (match_operand:SF 2 "gpc_reg_operand" "")))
5198 (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
5199 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5200 [(set (match_dup 3)
5201 (minus:SF (match_dup 1) (match_dup 2)))
5202 (set (match_dup 0)
5203 (if_then_else:SF (ge (match_dup 3)
5204 (const_int 0))
5205 (match_dup 1)
5206 (match_dup 2)))]
5207 "")
5209 (define_expand "minsf3"
5210 [(set (match_dup 3)
5211 (minus:SF (match_operand:SF 2 "gpc_reg_operand" "")
5212 (match_operand:SF 1 "gpc_reg_operand" "")))
5213 (set (match_operand:SF 0 "gpc_reg_operand" "")
5214 (if_then_else:SF (ge (match_dup 3)
5215 (const_int 0))
5216 (match_dup 1)
5217 (match_dup 2)))]
5218 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5219 "
5220 { operands[3] = gen_reg_rtx (SFmode); }")
5222 (define_split
5223 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5224 (smin:SF (match_operand:SF 1 "gpc_reg_operand" "")
5225 (match_operand:SF 2 "gpc_reg_operand" "")))
5226 (clobber (match_operand:SF 3 "gpc_reg_operand" ""))]
5227 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5228 [(set (match_dup 3)
5229 (minus:SF (match_dup 2) (match_dup 1)))
5230 (set (match_dup 0)
5231 (if_then_else:SF (ge (match_dup 3)
5232 (const_int 0))
5233 (match_dup 1)
5234 (match_dup 2)))]
5235 "")
5237 (define_expand "movsfcc"
5238 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5239 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5240 (match_operand:SF 2 "gpc_reg_operand" "f")
5241 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5242 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5243 "
5244 {
5245 rtx temp, op0, op1;
5246 enum rtx_code code = GET_CODE (operands[1]);
5247 if (! rs6000_compare_fp_p)
5248 FAIL;
5249 switch (code)
5250 {
5251 case GE: case EQ: case NE:
5252 op0 = rs6000_compare_op0;
5253 op1 = rs6000_compare_op1;
5254 break;
5255 case GT:
5256 op0 = rs6000_compare_op1;
5257 op1 = rs6000_compare_op0;
5258 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
5259 break;
5260 case LE:
5261 op0 = rs6000_compare_op1;
5262 op1 = rs6000_compare_op0;
5263 break;
5264 case LT:
5265 op0 = rs6000_compare_op0;
5266 op1 = rs6000_compare_op1;
5267 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
5268 break;
5269 default:
5270 FAIL;
5271 }
5272 if (GET_MODE (rs6000_compare_op0) == DFmode)
5273 {
5274 temp = gen_reg_rtx (DFmode);
5275 emit_insn (gen_subdf3 (temp, op0, op1));
5276 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[2], operands[3]));
5277 if (code == EQ)
5278 {
5279 emit_insn (gen_negdf2 (temp, temp));
5280 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[0], operands[3]));
5281 }
5282 else if (code == NE)
5283 {
5284 emit_insn (gen_negdf2 (temp, temp));
5285 emit_insn (gen_fseldfsf4 (operands[0], temp, operands[3], operands[0]));
5286 }
5287 }
5288 else
5289 {
5290 temp = gen_reg_rtx (SFmode);
5291 emit_insn (gen_subsf3 (temp, op0, op1));
5292 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[2], operands[3]));
5293 if (code == EQ)
5294 {
5295 emit_insn (gen_negsf2 (temp, temp));
5296 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[0], operands[3]));
5297 }
5298 else if (code == NE)
5299 {
5300 emit_insn (gen_negsf2 (temp, temp));
5301 emit_insn (gen_fselsfsf4 (operands[0], temp, operands[3], operands[0]));
5302 }
5303 }
5304 DONE;
5305 }")
5307 (define_insn "fselsfsf4"
5308 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5309 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5310 (const_int 0))
5311 (match_operand:SF 2 "gpc_reg_operand" "f")
5312 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5313 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5314 "fsel %0,%1,%2,%3"
5315 [(set_attr "type" "fp")])
5317 (define_insn "fseldfsf4"
5318 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5319 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5320 (const_int 0))
5321 (match_operand:SF 2 "gpc_reg_operand" "f")
5322 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5323 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5324 "fsel %0,%1,%2,%3"
5325 [(set_attr "type" "fp")])
5327 (define_insn "negdf2"
5328 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5329 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5330 "TARGET_HARD_FLOAT"
5331 "fneg %0,%1"
5332 [(set_attr "type" "fp")])
5334 (define_insn "absdf2"
5335 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5336 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5337 "TARGET_HARD_FLOAT"
5338 "fabs %0,%1"
5339 [(set_attr "type" "fp")])
5341 (define_insn ""
5342 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5343 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5344 "TARGET_HARD_FLOAT"
5345 "fnabs %0,%1"
5346 [(set_attr "type" "fp")])
5348 (define_insn "adddf3"
5349 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5350 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5351 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5352 "TARGET_HARD_FLOAT"
5353 "{fa|fadd} %0,%1,%2"
5354 [(set_attr "type" "fp")])
5356 (define_insn "subdf3"
5357 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5358 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5359 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5360 "TARGET_HARD_FLOAT"
5361 "{fs|fsub} %0,%1,%2"
5362 [(set_attr "type" "fp")])
5364 (define_insn "muldf3"
5365 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5366 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5367 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5368 "TARGET_HARD_FLOAT"
5369 "{fm|fmul} %0,%1,%2"
5370 [(set_attr "type" "dmul")])
5372 (define_insn "divdf3"
5373 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5374 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5375 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5376 "TARGET_HARD_FLOAT"
5377 "{fd|fdiv} %0,%1,%2"
5378 [(set_attr "type" "ddiv")])
5380 (define_insn ""
5381 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5382 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5383 (match_operand:DF 2 "gpc_reg_operand" "f"))
5384 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5385 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5386 "{fma|fmadd} %0,%1,%2,%3"
5387 [(set_attr "type" "dmul")])
5389 (define_insn ""
5390 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5391 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5392 (match_operand:DF 2 "gpc_reg_operand" "f"))
5393 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5394 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5395 "{fms|fmsub} %0,%1,%2,%3"
5396 [(set_attr "type" "dmul")])
5398 (define_insn ""
5399 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5400 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5401 (match_operand:DF 2 "gpc_reg_operand" "f"))
5402 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5403 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5404 "{fnma|fnmadd} %0,%1,%2,%3"
5405 [(set_attr "type" "dmul")])
5407 (define_insn ""
5408 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5409 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5410 (match_operand:DF 2 "gpc_reg_operand" "f"))
5411 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5412 "TARGET_HARD_FLOAT && TARGET_FUSED_MADD"
5413 "{fnms|fnmsub} %0,%1,%2,%3"
5414 [(set_attr "type" "dmul")])
5416 (define_insn "sqrtdf2"
5417 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5418 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5419 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT"
5420 "fsqrt %0,%1"
5421 [(set_attr "type" "dsqrt")])
5423 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5424 ;; fsel instruction and some auxiliary computations. Then we just have a
5425 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5426 ;; combine.
5428 (define_expand "maxdf3"
5429 [(set (match_dup 3)
5430 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5431 (match_operand:DF 2 "gpc_reg_operand" "")))
5432 (set (match_operand:DF 0 "gpc_reg_operand" "")
5433 (if_then_else:DF (ge (match_dup 3)
5434 (const_int 0))
5435 (match_dup 1)
5436 (match_dup 2)))]
5437 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5438 "
5439 { operands[3] = gen_reg_rtx (DFmode); }")
5441 (define_split
5442 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5443 (smax:DF (match_operand:DF 1 "gpc_reg_operand" "")
5444 (match_operand:DF 2 "gpc_reg_operand" "")))
5445 (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
5446 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5447 [(set (match_dup 3)
5448 (minus:DF (match_dup 1) (match_dup 2)))
5449 (set (match_dup 0)
5450 (if_then_else:DF (ge (match_dup 3)
5451 (const_int 0))
5452 (match_dup 1)
5453 (match_dup 2)))]
5454 "")
5456 (define_expand "mindf3"
5457 [(set (match_dup 3)
5458 (minus:DF (match_operand:DF 2 "gpc_reg_operand" "")
5459 (match_operand:DF 1 "gpc_reg_operand" "")))
5460 (set (match_operand:DF 0 "gpc_reg_operand" "")
5461 (if_then_else:DF (ge (match_dup 3)
5462 (const_int 0))
5463 (match_dup 1)
5464 (match_dup 2)))]
5465 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5466 "
5467 { operands[3] = gen_reg_rtx (DFmode); }")
5469 (define_split
5470 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5471 (smin:DF (match_operand:DF 1 "gpc_reg_operand" "")
5472 (match_operand:DF 2 "gpc_reg_operand" "")))
5473 (clobber (match_operand:DF 3 "gpc_reg_operand" ""))]
5474 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5475 [(set (match_dup 3)
5476 (minus:DF (match_dup 2) (match_dup 1)))
5477 (set (match_dup 0)
5478 (if_then_else:DF (ge (match_dup 3)
5479 (const_int 0))
5480 (match_dup 1)
5481 (match_dup 2)))]
5482 "")
5484 (define_expand "movdfcc"
5485 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5486 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5487 (match_operand:DF 2 "gpc_reg_operand" "f")
5488 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5489 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5490 "
5491 {
5492 rtx temp, op0, op1;
5493 enum rtx_code code = GET_CODE (operands[1]);
5494 if (! rs6000_compare_fp_p)
5495 FAIL;
5496 switch (code)
5497 {
5498 case GE: case EQ: case NE:
5499 op0 = rs6000_compare_op0;
5500 op1 = rs6000_compare_op1;
5501 break;
5502 case GT:
5503 op0 = rs6000_compare_op1;
5504 op1 = rs6000_compare_op0;
5505 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
5506 break;
5507 case LE:
5508 op0 = rs6000_compare_op1;
5509 op1 = rs6000_compare_op0;
5510 break;
5511 case LT:
5512 op0 = rs6000_compare_op0;
5513 op1 = rs6000_compare_op1;
5514 temp = operands[2]; operands[2] = operands[3]; operands[3] = temp;
5515 break;
5516 default:
5517 FAIL;
5518 }
5519 if (GET_MODE (rs6000_compare_op0) == DFmode)
5520 {
5521 temp = gen_reg_rtx (DFmode);
5522 emit_insn (gen_subdf3 (temp, op0, op1));
5523 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[2], operands[3]));
5524 if (code == EQ)
5525 {
5526 emit_insn (gen_negdf2 (temp, temp));
5527 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[0], operands[3]));
5528 }
5529 else if (code == NE)
5530 {
5531 emit_insn (gen_negdf2 (temp, temp));
5532 emit_insn (gen_fseldfdf4 (operands[0], temp, operands[3], operands[0]));
5533 }
5534 }
5535 else
5536 {
5537 temp = gen_reg_rtx (SFmode);
5538 emit_insn (gen_subsf3 (temp, op0, op1));
5539 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[2], operands[3]));
5540 if (code == EQ)
5541 {
5542 emit_insn (gen_negsf2 (temp, temp));
5543 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[0], operands[3]));
5544 }
5545 else if (code == NE)
5546 {
5547 emit_insn (gen_negsf2 (temp, temp));
5548 emit_insn (gen_fselsfdf4 (operands[0], temp, operands[3], operands[0]));
5549 }
5550 }
5551 DONE;
5552 }")
5554 (define_insn "fseldfdf4"
5555 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5556 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5557 (const_int 0))
5558 (match_operand:DF 2 "gpc_reg_operand" "f")
5559 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5560 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT"
5561 "fsel %0,%1,%2,%3"
5562 [(set_attr "type" "fp")])
5564 (define_insn "fselsfdf4"
5565 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5566 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5567 (const_int 0))
5568 (match_operand:DF 2 "gpc_reg_operand" "f")
5569 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5570 "TARGET_PPC_GFXOPT"
5571 "fsel %0,%1,%2,%3"
5572 [(set_attr "type" "fp")])
5573 \f
5574 ;; Conversions to and from floating-point.
5576 (define_expand "floatsidf2"
5577 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5578 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5579 (use (match_dup 2))
5580 (use (match_dup 3))
5581 (clobber (match_dup 4))
5582 (clobber (match_dup 5))
5583 (clobber (reg:DF 76))])]
5584 "TARGET_HARD_FLOAT"
5585 "
5586 {
5587 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5588 operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode));
5589 operands[4] = gen_reg_rtx (SImode);
5590 operands[5] = gen_reg_rtx (Pmode);
5591 }")
5593 (define_insn "*floatsidf2_internal"
5594 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5595 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5596 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5597 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5598 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
5599 (clobber (match_operand 5 "gpc_reg_operand" "=b"))
5600 (clobber (reg:DF 76))]
5601 "TARGET_HARD_FLOAT"
5602 "#"
5603 [(set_attr "length" "24")])
5605 (define_split
5606 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5607 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5608 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5609 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5610 (clobber (match_operand:SI 4 "gpc_reg_operand" ""))
5611 (clobber (match_operand 5 "gpc_reg_operand" ""))
5612 (clobber (reg:DF 76))]
5613 "TARGET_HARD_FLOAT"
5614 [(set (match_dup 4)
5615 (xor:SI (match_dup 1)
5616 (match_dup 6)))
5617 (set (match_dup 5)
5618 (unspec [(const_int 0)] 11))
5619 (set (match_dup 7)
5620 (unspec [(match_dup 4)
5621 (match_dup 5)] 12)) ;; low word
5622 (set (match_dup 7)
5623 (unspec [(match_dup 2)
5624 (match_dup 5)
5625 (match_dup 7)] 13)) ;; high word
5626 (set (match_dup 0)
5627 (unspec [(match_dup 7)
5628 (match_dup 5)] 14))
5629 (set (match_dup 0)
5630 (minus:DF (match_dup 0)
5631 (match_dup 3)))]
5632 "
5633 {
5634 operands[6] = GEN_INT (0x80000000);
5635 operands[7] = gen_rtx_REG (DFmode, FPMEM_REGNUM);
5636 }")
5638 (define_expand "floatunssidf2"
5639 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5640 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5641 (use (match_dup 2))
5642 (use (match_dup 3))
5643 (clobber (match_dup 4))
5644 (clobber (reg:DF 76))])]
5645 "TARGET_HARD_FLOAT"
5646 "
5647 {
5648 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5649 operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode));
5650 operands[4] = gen_reg_rtx (Pmode);
5651 }")
5653 (define_insn "*floatunssidf2_internal"
5654 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5655 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5656 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5657 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5658 (clobber (match_operand 4 "gpc_reg_operand" "=b"))
5659 (clobber (reg:DF 76))]
5660 "TARGET_HARD_FLOAT"
5661 "#"
5662 [(set_attr "length" "20")])
5664 (define_split
5665 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5666 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5667 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5668 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5669 (clobber (match_operand 4 "gpc_reg_operand" ""))
5670 (clobber (reg:DF 76))]
5671 "TARGET_HARD_FLOAT"
5672 [(set (match_dup 4)
5673 (unspec [(const_int 0)] 11))
5674 (set (match_dup 5)
5675 (unspec [(match_dup 1)
5676 (match_dup 4)] 12)) ;; low word
5677 (set (match_dup 5)
5678 (unspec [(match_dup 2)
5679 (match_dup 4)
5680 (match_dup 5)] 13)) ;; high word
5681 (set (match_dup 0)
5682 (unspec [(match_dup 5)
5683 (match_dup 4)] 14))
5684 (set (match_dup 0)
5685 (minus:DF (match_dup 0)
5686 (match_dup 3)))]
5687 "operands[5] = gen_rtx_REG (DFmode, FPMEM_REGNUM);")
5689 ;; Load up scratch register with base address + offset if needed
5690 (define_insn "*floatsidf2_loadaddr"
5691 [(set (match_operand 0 "gpc_reg_operand" "=b")
5692 (unspec [(const_int 0)] 11))]
5693 "TARGET_HARD_FLOAT"
5694 "*
5695 {
5696 if (rs6000_fpmem_offset > 32760)
5697 {
5698 rtx xop[3];
5700 xop[0] = operands[0];
5701 xop[1] = (frame_pointer_needed) ? frame_pointer_rtx : stack_pointer_rtx;
5702 xop[2] = GEN_INT ((rs6000_fpmem_offset >> 16) + ((rs6000_fpmem_offset & 0x8000) >> 15));
5703 output_asm_insn (\"{cau|addis} %0,%1,%2\", xop);
5704 }
5706 return \"\";
5707 }"
5708 [(set_attr "length" "4")])
5710 (define_insn "*floatsidf2_store1"
5711 [(set (reg:DF 76)
5712 (unspec [(match_operand:SI 0 "gpc_reg_operand" "r")
5713 (match_operand 1 "gpc_reg_operand" "b")] 12))]
5714 "TARGET_HARD_FLOAT"
5715 "*
5716 {
5717 rtx indx;
5719 if (rs6000_fpmem_offset > 32760)
5720 indx = operands[1];
5721 else if (frame_pointer_needed)
5722 indx = frame_pointer_rtx;
5723 else
5724 indx = stack_pointer_rtx;
5726 operands[2] = gen_rtx_MEM (SImode,
5727 gen_rtx_PLUS (Pmode,
5728 indx,
5729 GEN_INT ((((rs6000_fpmem_offset & 0xffff) ^ 0x8000) - 0x8000)
5730 + ((WORDS_BIG_ENDIAN != 0) * 4))));
5732 return \"{st|stw} %0,%2\";
5733 }"
5734 [(set_attr "type" "store")])
5736 (define_insn "*floatsidf2_store2"
5737 [(set (reg:DF 76)
5738 (unspec [(match_operand:SI 0 "gpc_reg_operand" "r")
5739 (match_operand 1 "gpc_reg_operand" "b")
5740 (reg:DF 76)] 13))]
5741 "TARGET_HARD_FLOAT"
5742 "*
5743 {
5744 rtx indx;
5746 if (rs6000_fpmem_offset > 32760)
5747 indx = operands[1];
5748 else if (frame_pointer_needed)
5749 indx = frame_pointer_rtx;
5750 else
5751 indx = stack_pointer_rtx;
5753 operands[2] = gen_rtx_MEM (SImode,
5754 gen_rtx_PLUS (Pmode,
5755 indx,
5756 GEN_INT ((((rs6000_fpmem_offset & 0xffff) ^ 0x8000) - 0x8000)
5757 + ((WORDS_BIG_ENDIAN == 0) * 4))));
5759 return \"{st|stw} %0,%2\";
5760 }"
5761 [(set_attr "type" "store")])
5763 (define_insn "*floatsidf2_load"
5764 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5765 (unspec [(reg:DF 76)
5766 (match_operand 1 "gpc_reg_operand" "b")] 14))]
5767 "TARGET_HARD_FLOAT"
5768 "*
5769 {
5770 rtx indx;
5771 HOST_WIDE_INT offset = rs6000_fpmem_offset;
5773 if (rs6000_fpmem_offset > 32760)
5774 {
5775 indx = operands[1];
5776 offset = (((offset & 0xffff) ^ 0x8000) - 0x8000);
5777 }
5778 else if (frame_pointer_needed)
5779 indx = frame_pointer_rtx;
5780 else
5781 indx = stack_pointer_rtx;
5783 operands[2] = gen_rtx_MEM (SImode,
5784 gen_rtx_PLUS (Pmode, indx, GEN_INT (offset)));
5786 return \"lfd %0,%2\";
5787 }"
5788 [(set_attr "type" "fpload")])
5790 (define_expand "fix_truncdfsi2"
5791 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5792 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5793 (clobber (match_dup 2))
5794 (clobber (match_dup 3))
5795 (clobber (match_dup 4))])]
5796 "TARGET_HARD_FLOAT"
5797 "
5798 {
5799 if (!TARGET_POWER2 && !TARGET_POWERPC)
5800 {
5801 emit_insn (gen_trunc_call (operands[0], operands[1],
5802 gen_rtx_SYMBOL_REF (Pmode, RS6000_ITRUNC)));
5803 DONE;
5804 }
5806 operands[2] = gen_reg_rtx (DImode);
5807 operands[3] = gen_reg_rtx (Pmode);
5808 operands[4] = gen_rtx_REG (DImode, FPMEM_REGNUM);
5809 }")
5811 (define_insn "*fix_truncdfsi2_internal"
5812 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5813 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5814 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5815 (clobber (match_operand 3 "gpc_reg_operand" "=b"))
5816 (clobber (reg:DI 76))]
5817 "TARGET_HARD_FLOAT"
5818 "#"
5819 [(set_attr "length" "12")])
5821 (define_split
5822 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5823 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5824 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5825 (clobber (match_operand 3 "gpc_reg_operand" ""))
5826 (clobber (reg:DI 76))]
5827 "TARGET_HARD_FLOAT"
5828 [(set (match_dup 2)
5829 (sign_extend:DI (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))))
5830 (set (match_dup 3)
5831 (unspec [(const_int 0)] 11))
5832 (set (match_dup 4)
5833 (unspec [(match_dup 2)
5834 (match_dup 3)] 15))
5835 (set (match_operand:SI 0 "gpc_reg_operand" "")
5836 (unspec [(match_dup 4)
5837 (match_dup 3)] 16))]
5838 "operands[4] = gen_rtx_REG (DImode, FPMEM_REGNUM);")
5840 (define_insn "*fix_truncdfsi2_store"
5841 [(set (reg:DI 76)
5842 (unspec [(match_operand:DI 0 "gpc_reg_operand" "f")
5843 (match_operand 1 "gpc_reg_operand" "b")] 15))]
5844 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
5845 "*
5846 {
5847 rtx indx;
5849 if (rs6000_fpmem_offset > 32760)
5850 indx = operands[1];
5851 else if (frame_pointer_needed)
5852 indx = frame_pointer_rtx;
5853 else
5854 indx = stack_pointer_rtx;
5856 operands[2] = gen_rtx_MEM (DFmode,
5857 gen_rtx_PLUS (Pmode,
5858 indx,
5859 GEN_INT ((((rs6000_fpmem_offset & 0xffff)
5860 ^ 0x8000) - 0x8000))));
5862 return \"stfd %0,%2\";
5863 }"
5864 [(set_attr "type" "fpstore")])
5866 (define_insn "*fix_truncdfsi2_load"
5867 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5868 (unspec [(reg:DI 76)
5869 (match_operand 1 "gpc_reg_operand" "b")] 16))]
5870 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
5871 "*
5872 {
5873 rtx indx;
5875 if (rs6000_fpmem_offset > 32760)
5876 indx = operands[1];
5877 else if (frame_pointer_needed)
5878 indx = frame_pointer_rtx;
5879 else
5880 indx = stack_pointer_rtx;
5882 operands[2] = gen_rtx_MEM (DFmode,
5883 gen_rtx_PLUS (Pmode,
5884 indx,
5885 GEN_INT ((((rs6000_fpmem_offset & 0xffff) ^ 0x8000) - 0x8000)
5886 + ((WORDS_BIG_ENDIAN) ? 4 : 0))));
5888 return \"{l|lwz} %0,%2\";
5889 }"
5890 [(set_attr "type" "load")])
5892 (define_expand "fixuns_truncdfsi2"
5893 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5894 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
5895 "! TARGET_POWER2 && ! TARGET_POWERPC && TARGET_HARD_FLOAT"
5896 "
5897 {
5898 emit_insn (gen_trunc_call (operands[0], operands[1],
5899 gen_rtx_SYMBOL_REF (Pmode, RS6000_UITRUNC)));
5900 DONE;
5901 }")
5903 (define_expand "trunc_call"
5904 [(parallel [(set (match_operand:SI 0 "" "")
5905 (fix:SI (match_operand:DF 1 "" "")))
5906 (use (match_operand:SI 2 "" ""))])]
5907 "TARGET_HARD_FLOAT"
5908 "
5909 {
5910 rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]);
5911 rtx first = XVECEXP (insns, 0, 0);
5912 rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
5914 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
5915 REG_NOTES (first));
5916 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first, REG_NOTES (last));
5918 emit_insn (insns);
5919 DONE;
5920 }")
5922 (define_expand "trunc_call_rtl"
5923 [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" ""))
5924 (use (reg:DF 33))
5925 (parallel [(set (reg:SI 3)
5926 (call (mem:SI (match_operand 2 "" "")) (const_int 0)))
5927 (use (const_int 0))
5928 (clobber (scratch:SI))])
5929 (set (match_operand:SI 0 "gpc_reg_operand" "")
5930 (reg:SI 3))]
5931 "TARGET_HARD_FLOAT"
5932 "
5933 {
5934 rs6000_trunc_used = 1;
5935 }")
5937 (define_insn "*fctiwz"
5938 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5939 (sign_extend:DI (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5940 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
5941 "{fcirz|fctiwz} %0,%1"
5942 [(set_attr "type" "fp")])
5944 (define_insn "floatdidf2"
5945 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5946 (float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))]
5947 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5948 "fcfid %0,%1"
5949 [(set_attr "type" "fp")])
5951 (define_insn "fix_truncdfdi2"
5952 [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
5953 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5954 "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
5955 "fctidz %0,%1"
5956 [(set_attr "type" "fp")])
5957 \f
5958 ;; Define the DImode operations that can be done in a small number
5959 ;; of instructions. The & constraints are to prevent the register
5960 ;; allocator from allocating registers that overlap with the inputs
5961 ;; (for example, having an input in 7,8 and an output in 6,7). We
5962 ;; also allow for the output being the same as one of the inputs.
5964 (define_insn "*adddi3_noppc64"
5965 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
5966 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
5967 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
5968 "! TARGET_POWERPC64"
5969 "*
5970 {
5971 if (WORDS_BIG_ENDIAN)
5972 return (GET_CODE (operands[2])) != CONST_INT
5973 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
5974 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
5975 else
5976 return (GET_CODE (operands[2])) != CONST_INT
5977 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
5978 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
5979 }"
5980 [(set_attr "length" "8")])
5982 (define_insn "*subdi3_noppc64"
5983 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
5984 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
5985 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
5986 "! TARGET_POWERPC64"
5987 "*
5988 {
5989 if (WORDS_BIG_ENDIAN)
5990 return (GET_CODE (operands[1]) != CONST_INT)
5991 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
5992 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
5993 else
5994 return (GET_CODE (operands[1]) != CONST_INT)
5995 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
5996 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
5997 }"
5998 [(set_attr "length" "8")])
6000 (define_insn "*negdi2_noppc64"
6001 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6002 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6003 "! TARGET_POWERPC64"
6004 "*
6005 {
6006 return (WORDS_BIG_ENDIAN)
6007 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6008 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6009 }"
6010 [(set_attr "length" "8")])
6012 (define_expand "mulsidi3"
6013 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6014 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6015 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6016 "! TARGET_POWERPC64"
6017 "
6018 {
6019 if (! TARGET_POWER && ! TARGET_POWERPC)
6020 {
6021 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6022 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6023 emit_insn (gen_mull_call ());
6024 if (WORDS_BIG_ENDIAN)
6025 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6026 else
6027 {
6028 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6029 gen_rtx_REG (SImode, 3));
6030 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6031 gen_rtx_REG (SImode, 4));
6032 }
6033 DONE;
6034 }
6035 else if (TARGET_POWER)
6036 {
6037 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6038 DONE;
6039 }
6040 }")
6042 (define_insn "mulsidi3_mq"
6043 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6044 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6045 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6046 (clobber (match_scratch:SI 3 "=q"))]
6047 "TARGET_POWER"
6048 "mul %0,%1,%2\;mfmq %L0"
6049 [(set_attr "type" "imul")
6050 (set_attr "length" "8")])
6052 (define_insn "*mulsidi3_no_mq"
6053 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6054 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6055 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6056 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6057 "*
6058 {
6059 return (WORDS_BIG_ENDIAN)
6060 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6061 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6062 }"
6063 [(set_attr "type" "imul")
6064 (set_attr "length" "8")])
6066 (define_split
6067 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6068 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6069 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6070 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6071 [(set (match_dup 3)
6072 (truncate:SI
6073 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6074 (sign_extend:DI (match_dup 2)))
6075 (const_int 32))))
6076 (set (match_dup 4)
6077 (mult:SI (match_dup 1)
6078 (match_dup 2)))]
6079 "
6080 {
6081 int endian = (WORDS_BIG_ENDIAN == 0);
6082 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6083 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6084 }")
6086 (define_expand "umulsidi3"
6087 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6088 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6089 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6090 "TARGET_POWERPC && ! TARGET_POWERPC64"
6091 "
6092 {
6093 if (TARGET_POWER)
6094 {
6095 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6096 DONE;
6097 }
6098 }")
6100 (define_insn "umulsidi3_mq"
6101 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6102 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6103 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6104 (clobber (match_scratch:SI 3 "=q"))]
6105 "TARGET_POWERPC && TARGET_POWER"
6106 "*
6107 {
6108 return (WORDS_BIG_ENDIAN)
6109 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6110 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6111 }"
6112 [(set_attr "type" "imul")
6113 (set_attr "length" "8")])
6115 (define_insn "*umulsidi3_no_mq"
6116 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6117 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6118 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6119 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6120 "*
6121 {
6122 return (WORDS_BIG_ENDIAN)
6123 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6124 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6125 }"
6126 [(set_attr "type" "imul")
6127 (set_attr "length" "8")])
6129 (define_split
6130 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6131 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6132 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6133 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6134 [(set (match_dup 3)
6135 (truncate:SI
6136 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6137 (zero_extend:DI (match_dup 2)))
6138 (const_int 32))))
6139 (set (match_dup 4)
6140 (mult:SI (match_dup 1)
6141 (match_dup 2)))]
6142 "
6143 {
6144 int endian = (WORDS_BIG_ENDIAN == 0);
6145 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6146 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6147 }")
6149 (define_expand "smulsi3_highpart"
6150 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6151 (truncate:SI
6152 (lshiftrt:DI (mult:DI (sign_extend:DI
6153 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6154 (sign_extend:DI
6155 (match_operand:SI 2 "gpc_reg_operand" "r")))
6156 (const_int 32))))]
6157 ""
6158 "
6159 {
6160 if (! TARGET_POWER && ! TARGET_POWERPC)
6161 {
6162 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6163 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6164 emit_insn (gen_mulh_call ());
6165 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6166 DONE;
6167 }
6168 else if (TARGET_POWER)
6169 {
6170 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6171 DONE;
6172 }
6173 }")
6175 (define_insn "smulsi3_highpart_mq"
6176 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6177 (truncate:SI
6178 (lshiftrt:DI (mult:DI (sign_extend:DI
6179 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6180 (sign_extend:DI
6181 (match_operand:SI 2 "gpc_reg_operand" "r")))
6182 (const_int 32))))
6183 (clobber (match_scratch:SI 3 "=q"))]
6184 "TARGET_POWER"
6185 "mul %0,%1,%2"
6186 [(set_attr "type" "imul")])
6188 (define_insn "*smulsi3_highpart_no_mq"
6189 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6190 (truncate:SI
6191 (lshiftrt:DI (mult:DI (sign_extend:DI
6192 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6193 (sign_extend:DI
6194 (match_operand:SI 2 "gpc_reg_operand" "r")))
6195 (const_int 32))))]
6196 "TARGET_POWERPC && ! TARGET_POWER"
6197 "mulhw %0,%1,%2"
6198 [(set_attr "type" "imul")])
6200 (define_expand "umulsi3_highpart"
6201 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6202 (truncate:SI
6203 (lshiftrt:DI (mult:DI (zero_extend:DI
6204 (match_operand:SI 1 "gpc_reg_operand" ""))
6205 (zero_extend:DI
6206 (match_operand:SI 2 "gpc_reg_operand" "")))
6207 (const_int 32))))]
6208 "TARGET_POWERPC"
6209 "
6210 {
6211 if (TARGET_POWER)
6212 {
6213 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6214 DONE;
6215 }
6216 }")
6218 (define_insn "umulsi3_highpart_mq"
6219 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6220 (truncate:SI
6221 (lshiftrt:DI (mult:DI (zero_extend:DI
6222 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6223 (zero_extend:DI
6224 (match_operand:SI 2 "gpc_reg_operand" "r")))
6225 (const_int 32))))
6226 (clobber (match_scratch:SI 3 "=q"))]
6227 "TARGET_POWERPC && TARGET_POWER"
6228 "mulhwu %0,%1,%2"
6229 [(set_attr "type" "imul")])
6231 (define_insn "*umulsi3_highpart_no_mq"
6232 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6233 (truncate:SI
6234 (lshiftrt:DI (mult:DI (zero_extend:DI
6235 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6236 (zero_extend:DI
6237 (match_operand:SI 2 "gpc_reg_operand" "r")))
6238 (const_int 32))))]
6239 "TARGET_POWERPC && ! TARGET_POWER"
6240 "mulhwu %0,%1,%2"
6241 [(set_attr "type" "imul")])
6243 ;; If operands 0 and 2 are in the same register, we have a problem. But
6244 ;; operands 0 and 1 (the usual case) can be in the same register. That's
6245 ;; why we have the strange constraints below.
6246 (define_insn "ashldi3_power"
6247 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6248 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6249 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6250 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6251 "TARGET_POWER"
6252 "@
6253 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6254 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6255 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6256 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6257 [(set_attr "length" "8")])
6259 (define_insn "lshrdi3_power"
6260 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6261 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6262 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6263 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6264 "TARGET_POWER"
6265 "@
6266 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
6267 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6268 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6269 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6270 [(set_attr "length" "8")])
6272 ;; Shift by a variable amount is too complex to be worth open-coding. We
6273 ;; just handle shifts by constants.
6274 (define_insn "ashrdi3_power"
6275 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6276 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6277 (match_operand:SI 2 "const_int_operand" "M,i")))
6278 (clobber (match_scratch:SI 3 "=X,q"))]
6279 "TARGET_POWER"
6280 "@
6281 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6282 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
6283 [(set_attr "length" "8")])
6284 \f
6285 ;; PowerPC64 DImode operations.
6287 (define_expand "adddi3"
6288 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6289 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
6290 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6291 ""
6292 "
6293 {
6294 if (! TARGET_POWERPC64)
6295 {
6296 if (non_short_cint_operand (operands[2], DImode))
6297 FAIL;
6298 }
6299 else
6300 if (GET_CODE (operands[2]) == CONST_INT
6301 && !add_operand (operands[2], DImode))
6302 {
6303 rtx tmp = ((reload_in_progress || reload_completed
6304 || rtx_equal_p (operands[0], operands[1]))
6305 ? operands[0] : gen_reg_rtx (DImode));
6307 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
6308 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
6310 if (low & 0x8000)
6311 high += 0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
6313 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (high)));
6314 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
6315 DONE;
6316 }
6317 }")
6319 ;; Discourage ai/addic because of carry but provide it in an alternative
6320 ;; allowing register zero as source.
6322 (define_insn "*adddi3_internal1"
6323 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
6324 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
6325 (match_operand:DI 2 "add_operand" "r,I,I,J")))]
6326 "TARGET_POWERPC64"
6327 "@
6328 add %0,%1,%2
6329 addi %0,%1,%2
6330 addic %0,%1,%2
6331 addis %0,%1,%v2")
6333 (define_insn "*adddi3_internal2"
6334 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6335 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
6336 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
6337 (const_int 0)))
6338 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6339 "TARGET_POWERPC64"
6340 "@
6341 add. %3,%1,%2
6342 addic. %3,%1,%2
6343 #
6344 #"
6345 [(set_attr "type" "compare")
6346 (set_attr "length" "4,4,8,8")])
6348 (define_split
6349 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6350 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
6351 (match_operand:DI 2 "reg_or_short_operand" ""))
6352 (const_int 0)))
6353 (clobber (match_scratch:DI 3 ""))]
6354 "reload_completed"
6355 [(set (match_dup 3)
6356 (plus:DI (match_dup 1)
6357 (match_dup 2)))
6358 (set (match_dup 0)
6359 (compare:CC (match_dup 3)
6360 (const_int 0)))]
6361 "")
6363 (define_insn "*adddi3_internal3"
6364 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6365 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
6366 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
6367 (const_int 0)))
6368 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6369 (plus:DI (match_dup 1) (match_dup 2)))]
6370 "TARGET_POWERPC64"
6371 "@
6372 add. %0,%1,%2
6373 addic. %0,%1,%2
6374 #
6375 #"
6376 [(set_attr "type" "compare")
6377 (set_attr "length" "4,4,8,8")])
6379 (define_split
6380 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6381 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
6382 (match_operand:DI 2 "reg_or_short_operand" ""))
6383 (const_int 0)))
6384 (set (match_operand:DI 0 "gpc_reg_operand" "")
6385 (plus:DI (match_dup 1)
6386 (match_dup 2)))]
6387 "reload_completed"
6388 [(set (match_dup 0)
6389 (plus:DI (match_dup 1)
6390 (match_dup 2)))
6391 (set (match_dup 3)
6392 (compare:CC (match_dup 0)
6393 (const_int 0)))]
6394 "")
6396 ;; Split an add that we can't do in one insn into two insns, each of which
6397 ;; does one 16-bit part. This is used by combine. Note that the low-order
6398 ;; add should be last in case the result gets used in an address.
6400 (define_split
6401 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6402 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
6403 (match_operand:DI 2 "non_add_cint_operand" "")))]
6404 "TARGET_POWERPC64"
6405 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
6406 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
6407 "
6408 {
6409 HOST_WIDE_INT low = INTVAL (operands[2]) & 0xffff;
6410 HOST_WIDE_INT high = INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff);
6412 if (low & 0x8000)
6413 high+=0x10000, low |= ((HOST_WIDE_INT) -1) << 16;
6415 operands[3] = GEN_INT (high);
6416 operands[4] = GEN_INT (low);
6417 }")
6419 (define_insn "one_cmpldi2"
6420 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6421 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6422 "TARGET_POWERPC64"
6423 "nor %0,%1,%1")
6425 (define_insn ""
6426 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6427 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6428 (const_int 0)))
6429 (clobber (match_scratch:DI 2 "=r,r"))]
6430 "TARGET_POWERPC64"
6431 "nor. %2,%1,%1"
6432 [(set_attr "type" "compare")
6433 (set_attr "length" "4,8")])
6435 (define_split
6436 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6437 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6438 (const_int 0)))
6439 (clobber (match_scratch:DI 2 ""))]
6440 "reload_completed"
6441 [(set (match_dup 2)
6442 (not:DI (match_dup 1)))
6443 (set (match_dup 0)
6444 (compare:CC (match_dup 2)
6445 (const_int 0)))]
6446 "")
6448 (define_insn ""
6449 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
6450 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6451 (const_int 0)))
6452 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6453 (not:DI (match_dup 1)))]
6454 "TARGET_POWERPC64"
6455 "nor. %0,%1,%1"
6456 [(set_attr "type" "compare")])
6458 (define_split
6459 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
6460 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6461 (const_int 0)))
6462 (set (match_operand:DI 0 "gpc_reg_operand" "")
6463 (not:DI (match_dup 1)))]
6464 "TARGET_POWERPC64 && reload_completed"
6465 [(set (match_dup 0)
6466 (not:DI (match_dup 1)))
6467 (set (match_dup 2)
6468 (compare:CC (match_dup 0)
6469 (const_int 0)))]
6470 "")
6472 (define_insn ""
6473 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6474 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
6475 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
6476 "TARGET_POWERPC64"
6477 "@
6478 subf %0,%2,%1
6479 subfic %0,%2,%1")
6481 (define_insn ""
6482 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6483 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6484 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6485 (const_int 0)))
6486 (clobber (match_scratch:DI 3 "=r,r"))]
6487 "TARGET_POWERPC64"
6488 "subf. %3,%2,%1"
6489 [(set_attr "type" "compare")
6490 (set_attr "length" "4,8")])
6492 (define_split
6493 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6494 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
6495 (match_operand:DI 2 "gpc_reg_operand" ""))
6496 (const_int 0)))
6497 (clobber (match_scratch:DI 3 ""))]
6498 "TARGET_POWERPC64 && reload_completed"
6499 [(set (match_dup 3)
6500 (minus:DI (match_dup 1)
6501 (match_dup 2)))
6502 (set (match_dup 0)
6503 (compare:CC (match_dup 3)
6504 (const_int 0)))]
6505 "")
6507 (define_insn ""
6508 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6509 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6510 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6511 (const_int 0)))
6512 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6513 (minus:DI (match_dup 1) (match_dup 2)))]
6514 "TARGET_POWERPC64"
6515 "subf. %0,%2,%1"
6516 [(set_attr "type" "compare")])
6518 (define_split
6519 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6520 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
6521 (match_operand:DI 2 "gpc_reg_operand" ""))
6522 (const_int 0)))
6523 (set (match_operand:DI 0 "gpc_reg_operand" "")
6524 (minus:DI (match_dup 1)
6525 (match_dup 2)))]
6526 "TARGET_POWERPC64 && reload_completed"
6527 [(set (match_dup 0)
6528 (minus:DI (match_dup 1)
6529 (match_dup 2)))
6530 (set (match_dup 3)
6531 (compare:CC (match_dup 0)
6532 (const_int 0)))]
6533 "")
6535 (define_expand "subdi3"
6536 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6537 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
6538 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6539 ""
6540 "
6541 {
6542 if (GET_CODE (operands[2]) == CONST_INT)
6543 {
6544 emit_insn (gen_adddi3 (operands[0], operands[1],
6545 negate_rtx (DImode, operands[2])));
6546 DONE;
6547 }
6548 }")
6550 (define_insn "absdi2"
6551 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6552 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6553 (clobber (match_scratch:DI 2 "=&r,&r"))]
6554 "TARGET_POWERPC64"
6555 "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%2,%0"
6556 [(set_attr "length" "12")])
6558 (define_split
6559 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6560 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6561 (clobber (match_scratch:DI 2 "=&r,&r"))]
6562 "TARGET_POWERPC64 && reload_completed"
6563 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6564 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6565 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6566 "")
6568 (define_insn ""
6569 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6570 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6571 (clobber (match_scratch:DI 2 "=&r,&r"))]
6572 "TARGET_POWERPC64"
6573 "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%0,%2"
6574 [(set_attr "length" "12")])
6576 (define_split
6577 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6578 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6579 (clobber (match_scratch:DI 2 "=&r,&r"))]
6580 "TARGET_POWERPC64 && reload_completed"
6581 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6582 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6583 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6584 "")
6586 (define_expand "negdi2"
6587 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6588 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
6589 ""
6590 "")
6592 (define_insn ""
6593 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6594 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6595 "TARGET_POWERPC64"
6596 "neg %0,%1")
6598 (define_insn ""
6599 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6600 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6601 (const_int 0)))
6602 (clobber (match_scratch:DI 2 "=r,r"))]
6603 "TARGET_POWERPC64"
6604 "@
6605 neg. %2,%1
6606 #"
6607 [(set_attr "type" "compare")
6608 (set_attr "length" "4,8")])
6610 (define_split
6611 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6612 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6613 (const_int 0)))
6614 (clobber (match_scratch:DI 2 ""))]
6615 "TARGET_POWERPC64 && reload_completed"
6616 [(set (match_dup 2)
6617 (neg:DI (match_dup 1)))
6618 (set (match_dup 0)
6619 (compare:CC (match_dup 2)
6620 (const_int 0)))]
6621 "")
6623 (define_insn ""
6624 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
6625 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6626 (const_int 0)))
6627 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6628 (neg:DI (match_dup 1)))]
6629 "TARGET_POWERPC64"
6630 "@
6631 neg. %0,%1
6632 #"
6633 [(set_attr "type" "compare")
6634 (set_attr "length" "4,8")])
6636 (define_split
6637 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
6638 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6639 (const_int 0)))
6640 (set (match_operand:DI 0 "gpc_reg_operand" "")
6641 (neg:DI (match_dup 1)))]
6642 "TARGET_POWERPC64 && reload_completed"
6643 [(set (match_dup 0)
6644 (neg:DI (match_dup 1)))
6645 (set (match_dup 2)
6646 (compare:CC (match_dup 0)
6647 (const_int 0)))]
6648 "")
6650 (define_insn "ffsdi2"
6651 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6652 (ffs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6653 "TARGET_POWERPC64"
6654 "neg %0,%1\;and %0,%0,%1\;cntlzd %0,%0\;subfic %0,%0,64"
6655 [(set_attr "length" "16")])
6657 (define_insn "muldi3"
6658 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6659 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
6660 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6661 "TARGET_POWERPC64"
6662 "mulld %0,%1,%2"
6663 [(set_attr "type" "imul")])
6665 (define_insn "smuldi3_highpart"
6666 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6667 (truncate:DI
6668 (lshiftrt:TI (mult:TI (sign_extend:TI
6669 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6670 (sign_extend:TI
6671 (match_operand:DI 2 "gpc_reg_operand" "r")))
6672 (const_int 64))))]
6673 "TARGET_POWERPC64"
6674 "mulhd %0,%1,%2"
6675 [(set_attr "type" "imul")])
6677 (define_insn "umuldi3_highpart"
6678 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6679 (truncate:DI
6680 (lshiftrt:TI (mult:TI (zero_extend:TI
6681 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6682 (zero_extend:TI
6683 (match_operand:DI 2 "gpc_reg_operand" "r")))
6684 (const_int 64))))]
6685 "TARGET_POWERPC64"
6686 "mulhdu %0,%1,%2"
6687 [(set_attr "type" "imul")])
6689 (define_expand "divdi3"
6690 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6691 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6692 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6693 "TARGET_POWERPC64"
6694 "
6695 {
6696 if (GET_CODE (operands[2]) == CONST_INT
6697 && exact_log2 (INTVAL (operands[2])) >= 0)
6698 ;
6699 else
6700 operands[2] = force_reg (DImode, operands[2]);
6701 }")
6703 (define_expand "moddi3"
6704 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6705 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6706 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6707 "TARGET_POWERPC64"
6708 "
6709 {
6710 int i = exact_log2 (INTVAL (operands[2]));
6711 rtx temp1;
6712 rtx temp2;
6714 if (GET_CODE (operands[2]) != CONST_INT || i < 0)
6715 FAIL;
6717 temp1 = gen_reg_rtx (DImode);
6718 temp2 = gen_reg_rtx (DImode);
6720 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6721 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6722 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6723 DONE;
6724 }")
6726 (define_insn ""
6727 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6728 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6729 (match_operand:DI 2 "const_int_operand" "N")))]
6730 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
6731 "sradi %0,%1,%p2\;addze %0,%0"
6732 [(set_attr "length" "8")])
6734 (define_insn ""
6735 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6736 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6737 (match_operand:DI 2 "const_int_operand" "N,N"))
6738 (const_int 0)))
6739 (clobber (match_scratch:DI 3 "=r,r"))]
6740 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
6741 "@
6742 sradi %3,%1,%p2\;addze. %3,%3
6743 #"
6744 [(set_attr "type" "compare")
6745 (set_attr "length" "8,12")])
6747 (define_split
6748 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6749 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6750 (match_operand:DI 2 "const_int_operand" ""))
6751 (const_int 0)))
6752 (clobber (match_scratch:DI 3 ""))]
6753 "TARGET_POWERPC64 && reload_completed && exact_log2 (INTVAL (operands[2])) >= 0"
6754 [(set (match_dup 3)
6755 (div:DI (match_dup 1)
6756 (match_dup 2)))
6757 (set (match_dup 0)
6758 (compare:CC (match_dup 3)
6759 (const_int 0)))]
6760 "")
6762 (define_insn ""
6763 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6764 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6765 (match_operand:DI 2 "const_int_operand" "N,N"))
6766 (const_int 0)))
6767 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6768 (div:DI (match_dup 1) (match_dup 2)))]
6769 "TARGET_POWERPC64 && exact_log2 (INTVAL (operands[2])) >= 0"
6770 "@
6771 sradi %0,%1,%p2\;addze. %0,%0
6772 #"
6773 [(set_attr "type" "compare")
6774 (set_attr "length" "8,12")])
6776 (define_split
6777 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6778 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6779 (match_operand:DI 2 "const_int_operand" ""))
6780 (const_int 0)))
6781 (set (match_operand:DI 0 "gpc_reg_operand" "")
6782 (div:DI (match_dup 1)
6783 (match_dup 2)))]
6784 "TARGET_POWERPC64 && reload_completed && exact_log2 (INTVAL (operands[2])) >= 0"
6785 [(set (match_dup 0)
6786 (div:DI (match_dup 1)
6787 (match_dup 2)))
6788 (set (match_dup 3)
6789 (compare:CC (match_dup 0)
6790 (const_int 0)))]
6791 "")
6793 (define_insn ""
6794 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6795 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6796 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6797 "TARGET_POWERPC64"
6798 "divd %0,%1,%2"
6799 [(set_attr "type" "idiv")])
6801 (define_insn "udivdi3"
6802 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6803 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6804 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6805 "TARGET_POWERPC64"
6806 "divdu %0,%1,%2"
6807 [(set_attr "type" "idiv")])
6809 (define_insn "rotldi3"
6810 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6811 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6812 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6813 "TARGET_POWERPC64"
6814 "rld%I2cl %0,%1,%H2,0")
6816 (define_insn "*rotldi3_internal2"
6817 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6818 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6819 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6820 (const_int 0)))
6821 (clobber (match_scratch:DI 3 "=r,r"))]
6822 "TARGET_POWERPC64"
6823 "@
6824 rld%I2cl. %3,%1,%H2,0
6825 #"
6826 [(set_attr "type" "delayed_compare")
6827 (set_attr "length" "4,8")])
6829 (define_split
6830 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6831 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6832 (match_operand:DI 2 "reg_or_cint_operand" ""))
6833 (const_int 0)))
6834 (clobber (match_scratch:DI 3 ""))]
6835 "TARGET_POWERPC64 && reload_completed"
6836 [(set (match_dup 3)
6837 (rotate:DI (match_dup 1)
6838 (match_dup 2)))
6839 (set (match_dup 0)
6840 (compare:CC (match_dup 3)
6841 (const_int 0)))]
6842 "")
6844 (define_insn "*rotldi3_internal3"
6845 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6846 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6847 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6848 (const_int 0)))
6849 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6850 (rotate:DI (match_dup 1) (match_dup 2)))]
6851 "TARGET_POWERPC64"
6852 "@
6853 rld%I2cl. %0,%1,%H2,0
6854 #"
6855 [(set_attr "type" "delayed_compare")
6856 (set_attr "length" "4,8")])
6858 (define_split
6859 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6860 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6861 (match_operand:DI 2 "reg_or_cint_operand" ""))
6862 (const_int 0)))
6863 (set (match_operand:DI 0 "gpc_reg_operand" "")
6864 (rotate:DI (match_dup 1)
6865 (match_dup 2)))]
6866 "TARGET_POWERPC64 && reload_completed"
6867 [(set (match_dup 0)
6868 (rotate:DI (match_dup 1)
6869 (match_dup 2)))
6870 (set (match_dup 3)
6871 (compare:CC (match_dup 0)
6872 (const_int 0)))]
6873 "")
6875 (define_insn "*rotldi3_internal4"
6876 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6877 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6878 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6879 (match_operand:DI 3 "mask64_operand" "S")))]
6880 "TARGET_POWERPC64"
6881 "rld%I2c%B3 %0,%1,%H2,%S3")
6883 (define_insn "*rotldi3_internal5"
6884 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6885 (compare:CC (and:DI
6886 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6887 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6888 (match_operand:DI 3 "mask64_operand" "S,S"))
6889 (const_int 0)))
6890 (clobber (match_scratch:DI 4 "=r,r"))]
6891 "TARGET_POWERPC64"
6892 "@
6893 rld%I2c%B3. %4,%1,%H2,%S3
6894 #"
6895 [(set_attr "type" "delayed_compare")
6896 (set_attr "length" "4,8")])
6898 (define_split
6899 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6900 (compare:CC (and:DI
6901 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6902 (match_operand:DI 2 "reg_or_cint_operand" ""))
6903 (match_operand:DI 3 "mask64_operand" ""))
6904 (const_int 0)))
6905 (clobber (match_scratch:DI 4 ""))]
6906 "TARGET_POWERPC64 && reload_completed"
6907 [(set (match_dup 4)
6908 (and:DI
6909 (rotate:DI (match_dup 1)
6910 (match_dup 2))
6911 (match_dup 3)))
6912 (set (match_dup 0)
6913 (compare:CC (match_dup 4)
6914 (const_int 0)))]
6915 "")
6917 (define_insn "*rotldi3_internal6"
6918 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
6919 (compare:CC (and:DI
6920 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6921 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6922 (match_operand:DI 3 "mask64_operand" "S,S"))
6923 (const_int 0)))
6924 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6925 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6926 "TARGET_POWERPC64"
6927 "@
6928 rld%I2c%B3. %0,%1,%H2,%S3
6929 #"
6930 [(set_attr "type" "delayed_compare")
6931 (set_attr "length" "4,8")])
6933 (define_split
6934 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
6935 (compare:CC (and:DI
6936 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6937 (match_operand:DI 2 "reg_or_cint_operand" ""))
6938 (match_operand:DI 3 "mask64_operand" ""))
6939 (const_int 0)))
6940 (set (match_operand:DI 0 "gpc_reg_operand" "")
6941 (and:DI
6942 (rotate:DI (match_dup 1)
6943 (match_dup 2))
6944 (match_dup 3)))]
6945 "TARGET_POWERPC64 && reload_completed"
6946 [(set (match_dup 0)
6947 (and:DI
6948 (rotate:DI (match_dup 1)
6949 (match_dup 2))
6950 (match_dup 3)))
6951 (set (match_dup 4)
6952 (compare:CC (match_dup 0)
6953 (const_int 0)))]
6954 "")
6956 (define_insn "*rotldi3_internal7"
6957 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6958 (zero_extend:DI
6959 (subreg:QI
6960 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6961 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
6962 "TARGET_POWERPC64"
6963 "rld%I2cl %0,%1,%H2,56")
6965 (define_insn "*rotldi3_internal8"
6966 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6967 (compare:CC (zero_extend:DI
6968 (subreg:QI
6969 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6970 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
6971 (const_int 0)))
6972 (clobber (match_scratch:DI 3 "=r,r"))]
6973 "TARGET_POWERPC64"
6974 "@
6975 rld%I2cl. %3,%1,%H2,56
6976 #"
6977 [(set_attr "type" "delayed_compare")
6978 (set_attr "length" "4,8")])
6980 (define_split
6981 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6982 (compare:CC (zero_extend:DI
6983 (subreg:QI
6984 (rotate:DI
6985 (match_operand:DI 1 "gpc_reg_operand" "")
6986 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
6987 (const_int 0)))
6988 (clobber (match_scratch:DI 3 ""))]
6989 "TARGET_POWERPC64 && reload_completed"
6990 [(set (match_dup 3)
6991 (zero_extend:DI
6992 (subreg:QI
6993 (rotate:DI
6994 (match_dup 1)
6995 (match_dup 2)) 0)))
6996 (set (match_dup 0)
6997 (compare:CC (match_dup 3)
6998 (const_int 0)))]
6999 "")
7001 (define_insn "*rotldi3_internal9"
7002 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7003 (compare:CC (zero_extend:DI
7004 (subreg:QI
7005 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7006 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
7007 (const_int 0)))
7008 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7009 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7010 "TARGET_POWERPC64"
7011 "@
7012 rld%I2cl. %0,%1,%H2,56
7013 #"
7014 [(set_attr "type" "delayed_compare")
7015 (set_attr "length" "4,8")])
7017 (define_split
7018 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7019 (compare:CC (zero_extend:DI
7020 (subreg:QI
7021 (rotate:DI
7022 (match_operand:DI 1 "gpc_reg_operand" "")
7023 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7024 (const_int 0)))
7025 (set (match_operand:DI 0 "gpc_reg_operand" "")
7026 (zero_extend:DI
7027 (subreg:QI
7028 (rotate:DI
7029 (match_dup 1)
7030 (match_dup 2)) 0)))]
7031 "TARGET_POWERPC64 && reload_completed"
7032 [(set (match_dup 0)
7033 (zero_extend:DI
7034 (subreg:QI
7035 (rotate:DI
7036 (match_dup 1)
7037 (match_dup 2)) 0)))
7038 (set (match_dup 3)
7039 (compare:CC (match_dup 0)
7040 (const_int 0)))]
7041 "")
7043 (define_insn "*rotldi3_internal10"
7044 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7045 (zero_extend:DI
7046 (subreg:HI
7047 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7048 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
7049 "TARGET_POWERPC64"
7050 "rld%I2cl %0,%1,%H2,48")
7052 (define_insn "*rotldi3_internal11"
7053 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7054 (compare:CC (zero_extend:DI
7055 (subreg:HI
7056 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7057 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
7058 (const_int 0)))
7059 (clobber (match_scratch:DI 3 "=r,r"))]
7060 "TARGET_POWERPC64"
7061 "@
7062 rld%I2cl. %3,%1,%H2,48
7063 #"
7064 [(set_attr "type" "delayed_compare")
7065 (set_attr "length" "4,8")])
7067 (define_split
7068 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7069 (compare:CC (zero_extend:DI
7070 (subreg:HI
7071 (rotate:DI
7072 (match_operand:DI 1 "gpc_reg_operand" "")
7073 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7074 (const_int 0)))
7075 (clobber (match_scratch:DI 3 ""))]
7076 "TARGET_POWERPC64 && reload_completed"
7077 [(set (match_dup 3)
7078 (zero_extend:DI
7079 (subreg:HI
7080 (rotate:DI
7081 (match_dup 1)
7082 (match_dup 2)) 0)))
7083 (set (match_dup 0)
7084 (compare:CC (match_dup 3)
7085 (const_int 0)))]
7086 "")
7088 (define_insn "*rotldi3_internal12"
7089 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7090 (compare:CC (zero_extend:DI
7091 (subreg:HI
7092 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7093 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
7094 (const_int 0)))
7095 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7096 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7097 "TARGET_POWERPC64"
7098 "@
7099 rld%I2cl. %0,%1,%H2,48
7100 #"
7101 [(set_attr "type" "delayed_compare")
7102 (set_attr "length" "4,8")])
7104 (define_split
7105 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7106 (compare:CC (zero_extend:DI
7107 (subreg:HI
7108 (rotate:DI
7109 (match_operand:DI 1 "gpc_reg_operand" "")
7110 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7111 (const_int 0)))
7112 (set (match_operand:DI 0 "gpc_reg_operand" "")
7113 (zero_extend:DI
7114 (subreg:HI
7115 (rotate:DI
7116 (match_dup 1)
7117 (match_dup 2)) 0)))]
7118 "TARGET_POWERPC64 && reload_completed"
7119 [(set (match_dup 0)
7120 (zero_extend:DI
7121 (subreg:QI
7122 (rotate:DI
7123 (match_dup 1)
7124 (match_dup 2)) 0)))
7125 (set (match_dup 3)
7126 (compare:CC (match_dup 0)
7127 (const_int 0)))]
7128 "")
7130 (define_insn "*rotldi3_internal13"
7131 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7132 (zero_extend:DI
7133 (subreg:SI
7134 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7135 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
7136 "TARGET_POWERPC64"
7137 "rld%I2cl %0,%1,%H2,32")
7139 (define_insn "*rotldi3_internal14"
7140 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7141 (compare:CC (zero_extend:DI
7142 (subreg:SI
7143 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7144 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
7145 (const_int 0)))
7146 (clobber (match_scratch:DI 3 "=r,r"))]
7147 "TARGET_POWERPC64"
7148 "@
7149 rld%I2cl. %3,%1,%H2,32
7150 #"
7151 [(set_attr "type" "delayed_compare")
7152 (set_attr "length" "4,8")])
7154 (define_split
7155 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7156 (compare:CC (zero_extend:DI
7157 (subreg:SI
7158 (rotate:DI
7159 (match_operand:DI 1 "gpc_reg_operand" "")
7160 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7161 (const_int 0)))
7162 (clobber (match_scratch:DI 3 ""))]
7163 "TARGET_POWERPC64 && reload_completed"
7164 [(set (match_dup 3)
7165 (zero_extend:DI
7166 (subreg:SI
7167 (rotate:DI
7168 (match_dup 1)
7169 (match_dup 2)) 0)))
7170 (set (match_dup 0)
7171 (compare:CC (match_dup 3)
7172 (const_int 0)))]
7173 "")
7175 (define_insn "*rotldi3_internal15"
7176 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7177 (compare:CC (zero_extend:DI
7178 (subreg:SI
7179 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7180 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
7181 (const_int 0)))
7182 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7183 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7184 "TARGET_POWERPC64"
7185 "@
7186 rld%I2cl. %0,%1,%H2,32
7187 #"
7188 [(set_attr "type" "delayed_compare")
7189 (set_attr "length" "4,8")])
7191 (define_split
7192 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7193 (compare:CC (zero_extend:DI
7194 (subreg:SI
7195 (rotate:DI
7196 (match_operand:DI 1 "gpc_reg_operand" "")
7197 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7198 (const_int 0)))
7199 (set (match_operand:DI 0 "gpc_reg_operand" "")
7200 (zero_extend:DI
7201 (subreg:SI
7202 (rotate:DI
7203 (match_dup 1)
7204 (match_dup 2)) 0)))]
7205 "TARGET_POWERPC64 && reload_completed"
7206 [(set (match_dup 0)
7207 (zero_extend:DI
7208 (subreg:QI
7209 (rotate:DI
7210 (match_dup 1)
7211 (match_dup 2)) 0)))
7212 (set (match_dup 3)
7213 (compare:CC (match_dup 0)
7214 (const_int 0)))]
7215 "")
7217 (define_expand "ashldi3"
7218 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7219 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7220 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7221 "TARGET_POWERPC64 || TARGET_POWER"
7222 "
7223 {
7224 if (TARGET_POWERPC64)
7225 ;
7226 else if (TARGET_POWER)
7227 {
7228 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7229 DONE;
7230 }
7231 else
7232 FAIL;
7233 }")
7235 (define_insn ""
7236 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7237 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7238 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7239 "TARGET_POWERPC64"
7240 "sld%I2 %0,%1,%H2"
7241 [(set_attr "length" "8")])
7243 (define_insn ""
7244 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7245 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7246 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7247 (const_int 0)))
7248 (clobber (match_scratch:DI 3 "=r,r"))]
7249 "TARGET_POWERPC64"
7250 "@
7251 sld%I2. %3,%1,%H2
7252 #"
7253 [(set_attr "type" "delayed_compare")
7254 (set_attr "length" "4,8")])
7256 (define_split
7257 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7258 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7259 (match_operand:DI 2 "reg_or_cint_operand" ""))
7260 (const_int 0)))
7261 (clobber (match_scratch:DI 3 ""))]
7262 "TARGET_POWERPC64 && reload_completed"
7263 [(set (match_dup 3)
7264 (ashift:DI (match_dup 1)
7265 (match_dup 2)))
7266 (set (match_dup 0)
7267 (compare:CC (match_dup 3)
7268 (const_int 0)))]
7269 "")
7271 (define_insn ""
7272 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7273 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7274 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7275 (const_int 0)))
7276 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7277 (ashift:DI (match_dup 1) (match_dup 2)))]
7278 "TARGET_POWERPC64"
7279 "@
7280 sld%I2. %0,%1,%H2
7281 #"
7282 [(set_attr "type" "delayed_compare")
7283 (set_attr "length" "4,8")])
7285 (define_split
7286 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7287 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7288 (match_operand:DI 2 "reg_or_cint_operand" ""))
7289 (const_int 0)))
7290 (set (match_operand:DI 0 "gpc_reg_operand" "")
7291 (ashift:DI (match_dup 1)
7292 (match_dup 2)))]
7293 "TARGET_POWERPC64 && reload_completed"
7294 [(set (match_dup 0)
7295 (ashift:DI (match_dup 1)
7296 (match_dup 2)))
7297 (set (match_dup 3)
7298 (compare:CC (match_dup 0)
7299 (const_int 0)))]
7300 "")
7302 (define_expand "lshrdi3"
7303 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7304 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7305 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7306 "TARGET_POWERPC64 || TARGET_POWER"
7307 "
7308 {
7309 if (TARGET_POWERPC64)
7310 ;
7311 else if (TARGET_POWER)
7312 {
7313 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7314 DONE;
7315 }
7316 else
7317 FAIL;
7318 }")
7320 (define_insn ""
7321 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7322 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7323 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7324 "TARGET_POWERPC64"
7325 "srd%I2 %0,%1,%H2")
7327 (define_insn ""
7328 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7329 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7330 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7331 (const_int 0)))
7332 (clobber (match_scratch:DI 3 "=r,r"))]
7333 "TARGET_POWERPC64"
7334 "@
7335 srd%I2. %3,%1,%H2
7336 #"
7337 [(set_attr "type" "delayed_compare")
7338 (set_attr "length" "4,8")])
7340 (define_split
7341 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7342 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7343 (match_operand:DI 2 "reg_or_cint_operand" ""))
7344 (const_int 0)))
7345 (clobber (match_scratch:DI 3 ""))]
7346 "TARGET_POWERPC64 && reload_completed"
7347 [(set (match_dup 3)
7348 (lshiftrt:DI (match_dup 1)
7349 (match_dup 2)))
7350 (set (match_dup 0)
7351 (compare:CC (match_dup 3)
7352 (const_int 0)))]
7353 "")
7355 (define_insn ""
7356 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7357 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7358 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7359 (const_int 0)))
7360 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7361 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7362 "TARGET_POWERPC64"
7363 "@
7364 srd%I2. %0,%1,%H2
7365 #"
7366 [(set_attr "type" "delayed_compare")
7367 (set_attr "length" "4,8")])
7369 (define_split
7370 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7371 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7372 (match_operand:DI 2 "reg_or_cint_operand" ""))
7373 (const_int 0)))
7374 (set (match_operand:DI 0 "gpc_reg_operand" "")
7375 (lshiftrt:DI (match_dup 1)
7376 (match_dup 2)))]
7377 "TARGET_POWERPC64 && reload_completed"
7378 [(set (match_dup 0)
7379 (lshiftrt:DI (match_dup 1)
7380 (match_dup 2)))
7381 (set (match_dup 3)
7382 (compare:CC (match_dup 0)
7383 (const_int 0)))]
7384 "")
7386 (define_expand "ashrdi3"
7387 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7388 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7389 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7390 "TARGET_POWERPC64 || TARGET_POWER"
7391 "
7392 {
7393 if (TARGET_POWERPC64)
7394 ;
7395 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7396 {
7397 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7398 DONE;
7399 }
7400 else
7401 FAIL;
7402 }")
7404 (define_insn ""
7405 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7406 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7407 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7408 "TARGET_POWERPC64"
7409 "srad%I2 %0,%1,%H2")
7411 (define_insn ""
7412 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7413 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7414 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7415 (const_int 0)))
7416 (clobber (match_scratch:DI 3 "=r,r"))]
7417 "TARGET_POWERPC64"
7418 "@
7419 srad%I2. %3,%1,%H2
7420 #"
7421 [(set_attr "type" "delayed_compare")
7422 (set_attr "length" "4,8")])
7424 (define_split
7425 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7426 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7427 (match_operand:DI 2 "reg_or_cint_operand" ""))
7428 (const_int 0)))
7429 (clobber (match_scratch:DI 3 ""))]
7430 "TARGET_POWERPC64 && reload_completed"
7431 [(set (match_dup 3)
7432 (ashiftrt:DI (match_dup 1)
7433 (match_dup 2)))
7434 (set (match_dup 0)
7435 (compare:CC (match_dup 3)
7436 (const_int 0)))]
7437 "")
7439 (define_insn ""
7440 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7441 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7442 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7443 (const_int 0)))
7444 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7445 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7446 "TARGET_POWERPC64"
7447 "@
7448 srad%I2. %0,%1,%H2
7449 #"
7450 [(set_attr "type" "delayed_compare")
7451 (set_attr "length" "4,8")])
7453 (define_split
7454 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7455 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7456 (match_operand:DI 2 "reg_or_cint_operand" ""))
7457 (const_int 0)))
7458 (set (match_operand:DI 0 "gpc_reg_operand" "")
7459 (ashiftrt (match_dup 1)
7460 (match_dup 2)))]
7461 "TARGET_POWERPC64 && reload_completed"
7462 [(set (match_dup 0)
7463 (ashiftrt (match_dup 1)
7464 (match_dup 2)))
7465 (set (match_dup 3)
7466 (compare:CC (match_dup 0)
7467 (const_int 0)))]
7468 "")
7470 (define_expand "anddi3"
7471 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7472 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
7473 (match_operand:DI 2 "and_operand" "?r,L,K,J")))
7474 (clobber (match_scratch:CC 3 "=X,X,x,x"))])]
7475 ""
7476 "")
7478 ;; If cr0 isn't available, and we want to do an andi, load the register into
7479 ;; the destination first.
7481 (define_insn "anddi3_internal1"
7482 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,&??r,&??r")
7483 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7484 (match_operand:DI 2 "and_operand" "?r,L,K,J,K,J")))
7485 (clobber (match_operand:CC 3 "scratch_operand" "=X,X,x,x,X,X"))]
7486 ""
7487 "@
7488 and %0,%1,%2
7489 {rlinm|rlwinm} %0,%1,0,%m2,%M2
7490 {andil.|andi.} %0,%1,%b2
7491 {andiu.|andis.} %0,%1,%u2
7492 #
7493 #"
7494 [(set_attr "length" "4,4,4,4,8,8")])
7496 (define_split
7497 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7498 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7499 (match_operand:DI 2 "const_int_operand" "")))
7500 (clobber (scratch:CC))]
7501 "reload_completed"
7502 [(set (match_dup 0)
7503 (match_dup 2))
7504 (parallel [(set (match_dup 0)
7505 (and:DI (match_dup 0)
7506 (match_dup 1)))
7507 (clobber (scratch:CC))])]
7508 "")
7510 ;; Note to set cr's other than cr0 we do the and immediate and then
7511 ;; the test again -- this avoids a mcrf which on the higher end
7512 ;; machines causes an execution serialization
7514 (define_insn "*anddi3_internal2"
7515 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y,???y,???y")
7516 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7517 (match_operand:DI 2 "and_operand" "r,K,J,L,r,K,J,L,K,L"))
7518 (const_int 0)))
7519 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,&r,&r"))
7520 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X,X,X"))]
7521 ""
7522 "@
7523 and. %3,%1,%2
7524 {andil.|andi.} %3,%1,%b2
7525 {andiu.|andis.} %3,%1,%u2
7526 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
7527 #
7528 #
7529 #
7530 #
7531 #
7532 #"
7533 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare")
7534 (set_attr "length" "4,4,4,4,8,12,12,8,16,16")])
7536 (define_split
7537 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7538 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7539 (match_operand:DI 2 "and_operand" ""))
7540 (const_int 0)))
7541 (clobber (match_scratch:DI 3 ""))
7542 (clobber (match_scratch:CC 4 ""))]
7543 "reload_completed"
7544 [(parallel [(set (match_dup 3)
7545 (and:DI (match_dup 1)
7546 (match_dup 2)))
7547 (clobber (match_dup 4))])
7548 (set (match_dup 0)
7549 (compare:CC (match_dup 3)
7550 (const_int 0)))]
7551 "")
7553 (define_insn "*anddi3_internal3"
7554 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y,???y,???y")
7555 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7556 (match_operand:DI 2 "and_operand" "r,K,J,L,r,K,J,L,K,J"))
7557 (const_int 0)))
7558 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,&r,&r")
7559 (and:DI (match_dup 1)
7560 (match_dup 2)))
7561 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X,X,X"))]
7562 ""
7563 "@
7564 and. %0,%1,%2
7565 {andil.|andi.} %0,%1,%b2
7566 {andiu.|andis.} %0,%1,%u2
7567 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
7568 #
7569 #
7570 #
7571 #
7572 #
7573 #"
7574 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare,compare")])
7576 (define_split
7577 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7578 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7579 (match_operand:DI 2 "and_operand" ""))
7580 (const_int 0)))
7581 (set (match_operand:DI 0 "gpc_reg_operand" "")
7582 (and:DI (match_dup 1)
7583 (match_dup 2)))
7584 (clobber (match_scratch:CC 4 ""))]
7585 "reload_completed"
7586 [(parallel [(set (match_dup 0)
7587 (and:DI (match_dup 1)
7588 (match_dup 2)))
7589 (clobber (match_dup 4))])
7590 (set (match_dup 3)
7591 (compare:CC (match_dup 0)
7592 (const_int 0)))]
7593 "")
7595 (define_expand "iordi3"
7596 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7597 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7598 (match_operand:DI 2 "reg_or_cint_operand" "")))]
7599 "TARGET_POWERPC64"
7600 "
7601 {
7602 if (GET_CODE (operands[2]) == CONST_INT
7603 && !logical_operand (operands[2], DImode))
7604 {
7605 HOST_WIDE_INT value = INTVAL (operands[2]);
7606 rtx tmp = ((reload_in_progress || reload_completed
7607 || rtx_equal_p (operands[0], operands[1]))
7608 ? operands[0] : gen_reg_rtx (DImode));
7610 emit_insn (gen_iordi3 (tmp, operands[1],
7611 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7612 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7613 DONE;
7614 }
7615 }")
7617 (define_insn "*iordi3_internal1"
7618 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7619 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7620 (match_operand:DI 2 "logical_operand" "r,K,J")))]
7621 "TARGET_POWERPC64"
7622 "@
7623 or %0,%1,%2
7624 ori %0,%1,%b2
7625 oris %0,%1,%u2")
7627 (define_insn "*iordi3_internal2"
7628 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7629 (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7630 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7631 (const_int 0)))
7632 (clobber (match_scratch:DI 3 "=r,r"))]
7633 "TARGET_POWERPC64"
7634 "@
7635 or. %3,%1,%2
7636 #"
7637 [(set_attr "type" "compare")
7638 (set_attr "length" "4,8")])
7640 (define_split
7641 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7642 (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7643 (match_operand:DI 2 "gpc_reg_operand" ""))
7644 (const_int 0)))
7645 (clobber (match_scratch:DI 3 ""))]
7646 "reload_completed"
7647 [(set (match_dup 3)
7648 (ior:DI (match_dup 1)
7649 (match_dup 2)))
7650 (set (match_dup 0)
7651 (compare:CC (match_dup 3)
7652 (const_int 0)))]
7653 "")
7655 (define_insn "*iordi3_internal3"
7656 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7657 (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7658 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7659 (const_int 0)))
7660 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7661 (ior:DI (match_dup 1) (match_dup 2)))]
7662 "TARGET_POWERPC64"
7663 "@
7664 or. %0,%1,%2
7665 #"
7666 [(set_attr "type" "compare")
7667 (set_attr "length" "4,8")])
7669 (define_split
7670 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7671 (compare:CC (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7672 (match_operand:DI 2 "gpc_reg_operand" ""))
7673 (const_int 0)))
7674 (set (match_operand:DI 0 "gpc_reg_operand" "")
7675 (ior:DI (match_dup 1) (match_dup 2)))]
7676 "reload_completed"
7677 [(set (match_dup 0)
7678 (ior:DI (match_dup 1)
7679 (match_dup 2)))
7680 (set (match_dup 3)
7681 (compare:CC (match_dup 0)
7682 (const_int 0)))]
7683 "")
7685 ;; Split an IOR that we can't do in one insn into two insns, each of which
7686 ;; does one 16-bit part. This is used by combine.
7688 (define_split
7689 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7690 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7691 (match_operand:DI 2 "non_logical_cint_operand" "")))]
7692 "TARGET_POWERPC64"
7693 [(set (match_dup 0) (ior:DI (match_dup 1) (match_dup 3)))
7694 (set (match_dup 0) (ior:DI (match_dup 0) (match_dup 4)))]
7695 "
7696 {
7697 operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
7698 operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff);
7699 }")
7701 (define_expand "xordi3"
7702 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7703 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7704 (match_operand:DI 2 "reg_or_cint_operand" "")))]
7705 "TARGET_POWERPC64"
7706 "
7707 {
7708 if (GET_CODE (operands[2]) == CONST_INT
7709 && !logical_operand (operands[2], DImode))
7710 {
7711 HOST_WIDE_INT value = INTVAL (operands[2]);
7712 rtx tmp = ((reload_in_progress || reload_completed
7713 || rtx_equal_p (operands[0], operands[1]))
7714 ? operands[0] : gen_reg_rtx (DImode));
7716 emit_insn (gen_xordi3 (tmp, operands[1],
7717 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7718 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7719 DONE;
7720 }
7721 }")
7723 (define_insn "*xordi3_internal1"
7724 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7725 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7726 (match_operand:DI 2 "logical_operand" "r,K,J")))]
7727 "TARGET_POWERPC64"
7728 "@
7729 xor %0,%1,%2
7730 xori %0,%1,%b2
7731 xoris %0,%1,%u2")
7733 (define_insn "*xordi3_internal2"
7734 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7735 (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7736 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7737 (const_int 0)))
7738 (clobber (match_scratch:DI 3 "=r,r"))]
7739 "TARGET_POWERPC64"
7740 "@
7741 xor. %3,%1,%2
7742 #"
7743 [(set_attr "type" "compare")
7744 (set_attr "length" "4,8")])
7746 (define_split
7747 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7748 (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7749 (match_operand:DI 2 "gpc_reg_operand" ""))
7750 (const_int 0)))
7751 (clobber (match_scratch:DI 3 ""))]
7752 "reload_completed"
7753 [(set (match_dup 3)
7754 (xor:DI (match_dup 1)
7755 (match_dup 2)))
7756 (set (match_dup 0)
7757 (compare:CC (match_dup 3)
7758 (const_int 0)))]
7759 "")
7761 (define_insn "*xordi3_internal3"
7762 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7763 (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7764 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7765 (const_int 0)))
7766 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7767 (xor:DI (match_dup 1) (match_dup 2)))]
7768 "TARGET_POWERPC64"
7769 "@
7770 xor. %0,%1,%2
7771 #"
7772 [(set_attr "type" "compare")
7773 (set_attr "length" "4,8")])
7775 (define_split
7776 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7777 (compare:CC (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7778 (match_operand:DI 2 "gpc_reg_operand" ""))
7779 (const_int 0)))
7780 (set (match_operand:DI 0 "gpc_reg_operand" "")
7781 (xor:DI (match_dup 1) (match_dup 2)))]
7782 "reload_completed"
7783 [(set (match_dup 0)
7784 (xor:DI (match_dup 1)
7785 (match_dup 2)))
7786 (set (match_dup 3)
7787 (compare:CC (match_dup 0)
7788 (const_int 0)))]
7789 "")
7791 ;; Split an XOR that we can't do in one insn into two insns, each of which
7792 ;; does one 16-bit part. This is used by combine.
7794 (define_split
7795 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7796 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7797 (match_operand:DI 2 "non_logical_cint_operand" "")))]
7798 "TARGET_POWERPC64"
7799 [(set (match_dup 0) (xor:DI (match_dup 1) (match_dup 3)))
7800 (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 4)))]
7801 "
7802 {
7803 operands[3] = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
7804 operands[4] = GEN_INT (INTVAL (operands[2]) & 0xffff);
7805 }")
7807 (define_insn "*eqvdi3_internal1"
7808 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7809 (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
7810 (match_operand:DI 2 "gpc_reg_operand" "r"))))]
7811 "TARGET_POWERPC64"
7812 "eqv %0,%1,%2")
7814 (define_insn "*eqvdi3_internal2"
7815 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7816 (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7817 (match_operand:DI 2 "gpc_reg_operand" "r,r")))
7818 (const_int 0)))
7819 (clobber (match_scratch:DI 3 "=r,r"))]
7820 "TARGET_POWERPC64"
7821 "@
7822 eqv. %3,%1,%2
7823 #"
7824 [(set_attr "type" "compare")
7825 (set_attr "length" "4,8")])
7827 (define_split
7828 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7829 (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7830 (match_operand:DI 2 "gpc_reg_operand" "")))
7831 (const_int 0)))
7832 (clobber (match_scratch:DI 3 ""))]
7833 "reload_completed"
7834 [(set (match_dup 3)
7835 (not:DI (xor:DI (match_dup 1)
7836 (match_dup 2))))
7837 (set (match_dup 0)
7838 (compare:CC (match_dup 3)
7839 (const_int 0)))]
7840 "")
7842 (define_insn "*eqvdi3_internal3"
7843 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7844 (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7845 (match_operand:DI 2 "gpc_reg_operand" "r,r")))
7846 (const_int 0)))
7847 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7848 (not:DI (xor:DI (match_dup 1) (match_dup 2))))]
7849 "TARGET_POWERPC64"
7850 "@
7851 eqv. %0,%1,%2
7852 #"
7853 [(set_attr "type" "compare")
7854 (set_attr "length" "4,8")])
7856 (define_split
7857 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7858 (compare:CC (not:DI (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7859 (match_operand:DI 2 "reg_or_short_operand" "")))
7860 (const_int 0)))
7861 (set (match_operand:DI 0 "gpc_reg_operand" "")
7862 (not:DI (xor:DI (match_dup 1)
7863 (match_dup 2))))]
7864 "reload_completed"
7865 [(set (match_dup 0)
7866 (not:DI (xor:DI (match_dup 1)
7867 (match_dup 2))))
7868 (set (match_dup 3)
7869 (compare:CC (match_dup 0)
7870 (const_int 0)))]
7871 "")
7873 (define_insn "*andcdi3_internal1"
7874 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7875 (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7876 (match_operand:DI 2 "gpc_reg_operand" "r")))]
7877 "TARGET_POWERPC64"
7878 "andc %0,%2,%1")
7880 (define_insn "*andcdi3_internal2"
7881 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7882 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7883 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7884 (const_int 0)))
7885 (clobber (match_scratch:DI 3 "=r,r"))]
7886 "TARGET_POWERPC64"
7887 "@
7888 andc. %3,%2,%1
7889 #"
7890 [(set_attr "type" "compare")
7891 (set_attr "length" "4,8")])
7893 (define_split
7894 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7895 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7896 (match_operand:DI 2 "gpc_reg_operand" ""))
7897 (const_int 0)))
7898 (clobber (match_scratch:DI 3 ""))]
7899 "reload_completed"
7900 [(set (match_dup 3)
7901 (and:DI (not:DI (match_dup 1))
7902 (match_dup 2)))
7903 (set (match_dup 0)
7904 (compare:CC (match_dup 3)
7905 (const_int 0)))]
7906 "")
7908 (define_insn "*andcdi3_internal3"
7909 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7910 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7911 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7912 (const_int 0)))
7913 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7914 (and:DI (not:DI (match_dup 1)) (match_dup 2)))]
7915 "TARGET_POWERPC64"
7916 "@
7917 andc. %0,%2,%1
7918 #"
7919 [(set_attr "type" "compare")
7920 (set_attr "length" "4,8")])
7922 (define_split
7923 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7924 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7925 (match_operand:DI 2 "gpc_reg_operand" ""))
7926 (const_int 0)))
7927 (set (match_operand:DI 0 "gpc_reg_operand" "")
7928 (and:DI (not:DI (match_dup 1))
7929 (match_dup 2)))]
7930 "reload_completed"
7931 [(set (match_dup 0)
7932 (and:DI (not:DI (match_dup 1))
7933 (match_dup 2)))
7934 (set (match_dup 3)
7935 (compare:CC (match_dup 0)
7936 (const_int 0)))]
7937 "")
7939 (define_insn "*iorcdi3_internal1"
7940 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7941 (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
7942 (match_operand:DI 2 "gpc_reg_operand" "r")))]
7943 "TARGET_POWERPC64"
7944 "orc %0,%2,%1")
7946 (define_insn "*iorcdi3_inernal2"
7947 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7948 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7949 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7950 (const_int 0)))
7951 (clobber (match_scratch:DI 3 "=r,r"))]
7952 "TARGET_POWERPC64"
7953 "@
7954 orc. %3,%2,%1
7955 #"
7956 [(set_attr "type" "compare")
7957 (set_attr "length" "4,8")])
7959 (define_split
7960 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7961 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7962 (match_operand:DI 2 "gpc_reg_operand" ""))
7963 (const_int 0)))
7964 (clobber (match_scratch:DI 3 ""))]
7965 "reload_completed"
7966 [(set (match_dup 3)
7967 (ior:DI (not:DI (match_dup 1))
7968 (match_dup 2)))
7969 (set (match_dup 0)
7970 (compare:CC (match_dup 3)
7971 (const_int 0)))]
7972 "")
7974 (define_insn "*iorcdi3_internal3"
7975 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7976 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
7977 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7978 (const_int 0)))
7979 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7980 (ior:DI (not:DI (match_dup 1)) (match_dup 2)))]
7981 "TARGET_POWERPC64"
7982 "@
7983 orc. %0,%2,%1
7984 #"
7985 [(set_attr "type" "compare")
7986 (set_attr "length" "4,8")])
7988 (define_split
7989 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7990 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
7991 (match_operand:DI 2 "gpc_reg_operand" ""))
7992 (const_int 0)))
7993 (set (match_operand:DI 0 "gpc_reg_operand" "")
7994 (ior:DI (not:DI (match_dup 1))
7995 (match_dup 2)))]
7996 "reload_completed"
7997 [(set (match_dup 0)
7998 (ior:DI (not:DI (match_dup 1))
7999 (match_dup 2)))
8000 (set (match_dup 3)
8001 (compare:CC (match_dup 0)
8002 (const_int 0)))]
8003 "")
8005 (define_insn "*nanddi3_internal1"
8006 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8007 (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8008 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))]
8009 "TARGET_POWERPC64"
8010 "nand %0,%1,%2")
8012 (define_insn "*nanddi3_internal2"
8013 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8014 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8015 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r")))
8016 (const_int 0)))
8017 (clobber (match_scratch:DI 3 "=r,r"))]
8018 "TARGET_POWERPC64"
8019 "@
8020 nand. %3,%1,%2
8021 #"
8022 [(set_attr "type" "compare")
8023 (set_attr "length" "4,8")])
8025 (define_split
8026 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8027 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8028 (not:DI (match_operand:DI 2 "gpc_reg_operand" "")))
8029 (const_int 0)))
8030 (clobber (match_scratch:DI 3 ""))]
8031 "reload_completed"
8032 [(set (match_dup 3)
8033 (ior:DI (not:DI (match_dup 1))
8034 (not:DI (match_dup 2))))
8035 (set (match_dup 0)
8036 (compare:CC (match_dup 3)
8037 (const_int 0)))]
8038 "")
8040 (define_insn "*nanddi3_internal3"
8041 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8042 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8043 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r")))
8044 (const_int 0)))
8045 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8046 (ior:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))]
8047 "TARGET_POWERPC64"
8048 "@
8049 nand. %0,%1,%2
8050 #"
8051 [(set_attr "type" "compare")
8052 (set_attr "length" "4,8")])
8054 (define_split
8055 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8056 (compare:CC (ior:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8057 (not:DI (match_operand:DI 2 "gpc_reg_operand" "")))
8058 (const_int 0)))
8059 (set (match_operand:DI 0 "gpc_reg_operand" "")
8060 (ior:DI (not:DI (match_dup 1))
8061 (not:DI (match_dup 2))))]
8062 "reload_completed"
8063 [(set (match_dup 0)
8064 (ior:DI (not:DI (match_dup 1))
8065 (not:DI (match_dup 2))))
8066 (set (match_dup 3)
8067 (compare:CC (match_dup 0)
8068 (const_int 0)))]
8069 "")
8071 (define_insn "*nordi3_internal1"
8072 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8073 (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8074 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))))]
8075 "TARGET_POWERPC64"
8076 "nor %0,%1,%2")
8078 (define_insn "*nordi3_internal2"
8079 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8080 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8081 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r")))
8082 (const_int 0)))
8083 (clobber (match_scratch:DI 3 "=r,r"))]
8084 "TARGET_POWERPC64"
8085 "@
8086 nor. %3,%1,%2
8087 #"
8088 [(set_attr "type" "compare")
8089 (set_attr "length" "4,8")])
8091 (define_split
8092 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8093 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8094 (not:DI (match_operand:DI 2 "gpc_reg_operand" "")))
8095 (const_int 0)))
8096 (clobber (match_scratch:DI 3 ""))]
8097 "reload_completed"
8098 [(set (match_dup 3)
8099 (and:DI (not:DI (match_dup 1))
8100 (not:DI (match_dup 2))))
8101 (set (match_dup 0)
8102 (compare:CC (match_dup 3)
8103 (const_int 0)))]
8104 "")
8106 (define_insn "*nordi3_internal3"
8107 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8108 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8109 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r")))
8110 (const_int 0)))
8111 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8112 (and:DI (not:DI (match_dup 1)) (not:DI (match_dup 2))))]
8113 "TARGET_POWERPC64"
8114 "@
8115 nor. %0,%1,%2
8116 #"
8117 [(set_attr "type" "compare")
8118 (set_attr "length" "4,8")])
8120 (define_split
8121 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8122 (compare:CC (and:DI (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8123 (not:DI (match_operand:DI 2 "gpc_reg_operand" "")))
8124 (const_int 0)))
8125 (set (match_operand:DI 0 "gpc_reg_operand" "")
8126 (and:DI (not:DI (match_dup 1))
8127 (not:DI (match_dup 2))))]
8128 "reload_completed"
8129 [(set (match_dup 0)
8130 (and:DI (not:DI (match_dup 1))
8131 (not:DI (match_dup 2))))
8132 (set (match_dup 3)
8133 (compare:CC (match_dup 0)
8134 (const_int 0)))]
8135 "")
8137 \f
8138 ;; Now define ways of moving data around.
8140 ;; Elf specific ways of loading addresses for non-PIC code.
8141 ;; The output of this could be r0, but we limit it to base
8142 ;; registers, since almost all uses of this will need it
8143 ;; in a base register shortly.
8144 (define_insn "elf_high"
8145 [(set (match_operand:SI 0 "register_operand" "=b")
8146 (high:SI (match_operand 1 "" "")))]
8147 "TARGET_ELF && !TARGET_64BIT"
8148 "{liu|lis} %0,%1@ha")
8150 (define_insn "elf_low"
8151 [(set (match_operand:SI 0 "register_operand" "=r")
8152 (lo_sum:SI (match_operand:SI 1 "register_operand" "b")
8153 (match_operand 2 "" "")))]
8154 "TARGET_ELF && !TARGET_64BIT"
8155 "{cal|la} %0,%2@l(%1)")
8157 ;; Set up a register with a value from the GOT table
8159 (define_expand "movsi_got"
8160 [(set (match_operand:SI 0 "register_operand" "")
8161 (unspec [(match_operand:SI 1 "got_operand" "")
8162 (match_dup 2)] 8))]
8163 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1"
8164 "
8165 {
8166 if (GET_CODE (operands[1]) == CONST)
8167 {
8168 rtx offset = const0_rtx;
8169 HOST_WIDE_INT value;
8171 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8172 value = INTVAL (offset);
8173 if (value != 0)
8174 {
8175 rtx tmp = ((reload_in_progress || reload_completed)
8176 ? operands[0]
8177 : gen_reg_rtx (Pmode));
8178 emit_insn (gen_movsi_got (tmp, operands[1]));
8179 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8180 DONE;
8181 }
8182 }
8184 operands[2] = rs6000_got_register (operands[1]);
8185 }")
8187 (define_insn "*movsi_got_internal"
8188 [(set (match_operand:SI 0 "register_operand" "=r")
8189 (unspec [(match_operand:SI 1 "got_no_const_operand" "")
8190 (match_operand:SI 2 "register_operand" "b")] 8))]
8191 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS) && flag_pic == 1"
8192 "{l|lwz} %0,%a1@got(%2)"
8193 [(set_attr "type" "load")])
8195 ;; Sometimes, though, the GOT `register' will be on the stack. Deal with
8196 ;; this case specially.
8197 ;; Force final to split this insn (if it hasn't been split already) to
8198 ;; avoid having to create a suitable output template.
8199 (define_insn "*movsi_got_internal_mem"
8200 [(set (match_operand:SI 0 "register_operand" "=r")
8201 (unspec [(match_operand:SI 1 "got_no_const_operand" "")
8202 (match_operand:SI 2 "memory_operand" "m")] 8))]
8203 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
8204 && flag_pic == 1
8205 && (reload_in_progress || reload_completed)"
8206 "#"
8207 [(set_attr "type" "load")
8208 (set_attr "length" "8")])
8210 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8211 ;; didn't get allocated to a hard register.
8212 (define_split
8213 [(set (match_operand:SI 0 "register_operand" "=r")
8214 (unspec [(match_operand:SI 1 "got_no_const_operand" "")
8215 (match_operand:SI 2 "memory_operand" "m")] 8))]
8216 "(DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
8217 && flag_pic == 1
8218 && (reload_in_progress || reload_completed)"
8219 [(set (match_dup 0) (match_dup 2))
8220 (set (match_dup 0) (unspec [(match_dup 1)(match_dup 0)] 8))]
8221 "")
8223 ;; For SI, we special-case integers that can't be loaded in one insn. We
8224 ;; do the load 16-bits at a time. We could do this by loading from memory,
8225 ;; and this is even supposed to be faster, but it is simpler not to get
8226 ;; integers in the TOC.
8227 (define_expand "movsi"
8228 [(set (match_operand:SI 0 "general_operand" "")
8229 (match_operand:SI 1 "any_operand" ""))]
8230 ""
8231 "
8232 {
8233 if (GET_CODE (operands[0]) != REG)
8234 operands[1] = force_reg (SImode, operands[1]);
8236 /* Convert a move of a CONST_DOUBLE into a CONST_INT */
8237 if (GET_CODE (operands[1]) == CONST_DOUBLE)
8238 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8240 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
8241 if (GET_CODE (operands[1]) == CONST
8242 && GET_CODE (XEXP (operands[1], 0)) == CONSTANT_P_RTX)
8243 {
8244 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
8245 DONE;
8246 }
8248 /* Use default pattern for address of ELF small data */
8249 if (TARGET_ELF
8250 && (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
8251 && (GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == CONST)
8252 && small_data_operand (operands[1], SImode))
8253 {
8254 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
8255 DONE;
8256 }
8258 if ((DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
8259 && flag_pic == 1 && got_operand (operands[1], SImode))
8260 {
8261 emit_insn (gen_movsi_got (operands[0], operands[1]));
8262 DONE;
8263 }
8265 if (TARGET_ELF && TARGET_NO_TOC && !TARGET_64BIT
8266 && !flag_pic
8267 && CONSTANT_P (operands[1])
8268 && GET_CODE (operands[1]) != HIGH
8269 && GET_CODE (operands[1]) != CONST_INT)
8270 {
8271 rtx target = (reload_completed || reload_in_progress)
8272 ? operands[0] : gen_reg_rtx (SImode);
8274 /* If this is a function address on -mcall-aixdesc or -mcall-nt,
8275 convert it to the address of the descriptor. */
8276 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
8277 && GET_CODE (operands[1]) == SYMBOL_REF
8278 && XSTR (operands[1], 0)[0] == '.')
8279 {
8280 char *name = XSTR (operands[1], 0);
8281 rtx new_ref;
8282 while (*name == '.')
8283 name++;
8284 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
8285 CONSTANT_POOL_ADDRESS_P (new_ref) = CONSTANT_POOL_ADDRESS_P (operands[1]);
8286 SYMBOL_REF_FLAG (new_ref) = SYMBOL_REF_FLAG (operands[1]);
8287 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
8288 operands[1] = new_ref;
8289 }
8291 emit_insn (gen_elf_high (target, operands[1]));
8292 emit_insn (gen_elf_low (operands[0], target, operands[1]));
8293 DONE;
8294 }
8296 if (GET_CODE (operands[1]) == CONST
8297 && DEFAULT_ABI == ABI_NT
8298 && !side_effects_p (operands[0]))
8299 {
8300 rtx const_term = const0_rtx;
8301 rtx sym = eliminate_constant_term (XEXP (operands[1], 0), &const_term);
8302 if (sym && GET_CODE (const_term) == CONST_INT
8303 && (GET_CODE (sym) == SYMBOL_REF || GET_CODE (sym) == LABEL_REF))
8304 {
8305 unsigned HOST_WIDE_INT value = INTVAL (const_term);
8306 int new_reg_p = (flag_expensive_optimizations
8307 && !reload_completed
8308 && !reload_in_progress);
8309 rtx tmp1 = (new_reg_p && value != 0) ? gen_reg_rtx (SImode) : operands[0];
8311 emit_insn (gen_movsi (tmp1, sym));
8312 if (INTVAL (const_term) != 0)
8313 emit_insn (gen_addsi3 (operands[0], tmp1, GEN_INT (value)));
8314 DONE;
8315 }
8316 else
8317 rs6000_fatal_bad_address (operands[1]);
8318 }
8320 if ((!TARGET_WINDOWS_NT || DEFAULT_ABI != ABI_NT)
8321 && CONSTANT_P (operands[1])
8322 && GET_CODE (operands[1]) != CONST_INT
8323 && GET_CODE (operands[1]) != HIGH
8324 && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]))
8325 {
8326 /* Emit a USE operation so that the constant isn't deleted if
8327 expensive optimizations are turned on because nobody
8328 references it. This should only be done for operands that
8329 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
8330 This should not be done for operands that contain LABEL_REFs.
8331 For now, we just handle the obvious case. */
8332 if (GET_CODE (operands[1]) != LABEL_REF)
8333 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
8335 /* If we are to limit the number of things we put in the TOC and
8336 this is a symbol plus a constant we can add in one insn,
8337 just put the symbol in the TOC and add the constant. Don't do
8338 this if reload is in progress. */
8339 if (GET_CODE (operands[1]) == CONST
8340 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
8341 && GET_CODE (XEXP (operands[1], 0)) == PLUS
8342 && add_operand (XEXP (XEXP (operands[1], 0), 1), SImode)
8343 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
8344 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
8345 && ! side_effects_p (operands[0]))
8346 {
8347 rtx sym = force_const_mem (SImode, XEXP (XEXP (operands[1], 0), 0));
8348 rtx other = XEXP (XEXP (operands[1], 0), 1);
8350 emit_insn (gen_addsi3 (operands[0], force_reg (SImode, sym), other));
8351 DONE;
8352 }
8354 operands[1] = force_const_mem (SImode, operands[1]);
8355 if (! memory_address_p (SImode, XEXP (operands[1], 0))
8356 && ! reload_in_progress)
8357 operands[1] = change_address (operands[1], SImode,
8358 XEXP (operands[1], 0));
8359 }
8360 }")
8362 (define_insn ""
8363 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h")
8364 (match_operand:SI 1 "input_operand" "r,U,m,r,I,J,n,R,*h,r,r,0"))]
8365 "gpc_reg_operand (operands[0], SImode)
8366 || gpc_reg_operand (operands[1], SImode)"
8367 "@
8368 mr %0,%1
8369 {cal|la} %0,%a1
8370 {l%U1%X1|lwz%U1%X1} %0,%1
8371 {st%U0%X0|stw%U0%X0} %1,%0
8372 {lil|li} %0,%1
8373 {liu|lis} %0,%v1
8374 #
8375 {cal|la} %0,%1(%*)
8376 mf%1 %0
8377 mt%0 %1
8378 mt%0 %1
8379 cror 0,0,0"
8380 [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*")
8381 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4")])
8383 ;; Split a load of a large constant into the appropriate two-insn
8384 ;; sequence.
8386 (define_split
8387 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8388 (match_operand:SI 1 "const_int_operand" ""))]
8389 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8390 && (INTVAL (operands[1]) & 0xffff) != 0"
8391 [(set (match_dup 0)
8392 (match_dup 2))
8393 (set (match_dup 0)
8394 (ior:SI (match_dup 0)
8395 (match_dup 3)))]
8396 "
8397 {
8398 operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000);
8399 operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
8400 }")
8402 (define_insn ""
8403 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
8404 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r")
8405 (const_int 0)))
8406 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
8407 ""
8408 "mr. %0,%1"
8409 [(set_attr "type" "compare")])
8411 (define_split
8412 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8413 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
8414 (const_int 0)))
8415 (set (match_operand:SI 0 "gpc_reg_operand" "")
8416 (match_dup 1))]
8417 "reload_completed && rtx_equal_p (operands[0], operands[1])"
8418 [(set (match_dup 2)
8419 (compare:CC (match_dup 1)
8420 (const_int 0)))]
8421 "")
8423 (define_split
8424 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8425 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
8426 (const_int 0)))
8427 (set (match_operand:SI 0 "gpc_reg_operand" "")
8428 (match_dup 1))]
8429 "reload_completed && !rtx_equal_p (operands[0], operands[1])"
8430 [(set (match_dup 2)
8431 (compare:CC (match_dup 1)
8432 (const_int 0)))
8433 (set (match_dup 0)
8434 (match_dup 1))]
8435 "")
8437 \f
8438 (define_expand "movhi"
8439 [(set (match_operand:HI 0 "general_operand" "")
8440 (match_operand:HI 1 "any_operand" ""))]
8441 ""
8442 "
8443 {
8444 if (GET_CODE (operands[0]) != REG)
8445 operands[1] = force_reg (HImode, operands[1]);
8447 if (CONSTANT_P (operands[1])
8448 && GET_CODE (operands[1]) != CONST_INT)
8449 {
8450 operands[1] = force_const_mem (HImode, operands[1]);
8451 if (! memory_address_p (HImode, XEXP (operands[1], 0))
8452 && ! reload_in_progress)
8453 operands[1] = change_address (operands[1], HImode,
8454 XEXP (operands[1], 0));
8455 }
8456 }")
8458 (define_insn ""
8459 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8460 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8461 "gpc_reg_operand (operands[0], HImode)
8462 || gpc_reg_operand (operands[1], HImode)"
8463 "@
8464 mr %0,%1
8465 lhz%U1%X1 %0,%1
8466 sth%U0%X0 %1,%0
8467 {lil|li} %0,%w1
8468 mf%1 %0
8469 mt%0 %1
8470 mt%0 %1
8471 cror 0,0,0"
8472 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
8474 (define_expand "movqi"
8475 [(set (match_operand:QI 0 "general_operand" "")
8476 (match_operand:QI 1 "any_operand" ""))]
8477 ""
8478 "
8479 {
8480 if (GET_CODE (operands[0]) != REG)
8481 operands[1] = force_reg (QImode, operands[1]);
8483 if (CONSTANT_P (operands[1])
8484 && GET_CODE (operands[1]) != CONST_INT)
8485 {
8486 operands[1] = force_const_mem (QImode, operands[1]);
8487 if (! memory_address_p (QImode, XEXP (operands[1], 0))
8488 && ! reload_in_progress)
8489 operands[1] = change_address (operands[1], QImode,
8490 XEXP (operands[1], 0));
8491 }
8492 }")
8494 (define_insn ""
8495 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8496 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8497 "gpc_reg_operand (operands[0], QImode)
8498 || gpc_reg_operand (operands[1], QImode)"
8499 "@
8500 mr %0,%1
8501 lbz%U1%X1 %0,%1
8502 stb%U0%X0 %1,%0
8503 {lil|li} %0,%1
8504 mf%1 %0
8505 mt%0 %1
8506 mt%0 %1
8507 cror 0,0,0"
8508 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
8509 \f
8510 ;; Here is how to move condition codes around. When we store CC data in
8511 ;; an integer register or memory, we store just the high-order 4 bits.
8512 ;; This lets us not shift in the most common case of CR0.
8513 (define_expand "movcc"
8514 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8515 (match_operand:CC 1 "nonimmediate_operand" ""))]
8516 ""
8517 "")
8519 (define_insn ""
8520 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
8521 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
8522 "register_operand (operands[0], CCmode)
8523 || register_operand (operands[1], CCmode)"
8524 "@
8525 mcrf %0,%1
8526 mtcrf 128,%1
8527 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8528 mfcr %0
8529 mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8530 mr %0,%1
8531 {l%U1%X1|lwz%U1%X1} %0,%1
8532 {st%U0%U1|stw%U0%U1} %1,%0"
8533 [(set_attr "type" "*,*,*,compare,*,*,load,store")
8534 (set_attr "length" "*,*,12,*,8,*,*,*")])
8535 \f
8536 ;; For floating-point, we normally deal with the floating-point registers
8537 ;; unless -msoft-float is used. The sole exception is that parameter passing
8538 ;; can produce floating-point values in fixed-point registers. Unless the
8539 ;; value is a simple constant or already in memory, we deal with this by
8540 ;; allocating memory and copying the value explicitly via that memory location.
8541 (define_expand "movsf"
8542 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8543 (match_operand:SF 1 "any_operand" ""))]
8544 ""
8545 "
8546 {
8547 /* If we are called from reload, we might be getting a SUBREG of a hard
8548 reg. So expand it. */
8549 if (GET_CODE (operands[0]) == SUBREG
8550 && GET_CODE (SUBREG_REG (operands[0])) == REG
8551 && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
8552 operands[0] = alter_subreg (operands[0]);
8553 if (GET_CODE (operands[1]) == SUBREG
8554 && GET_CODE (SUBREG_REG (operands[1])) == REG
8555 && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
8556 operands[1] = alter_subreg (operands[1]);
8558 if (GET_CODE (operands[0]) == MEM)
8559 {
8560 /* If operands[1] is a register, it may have double-precision data
8561 in it, so truncate it to single precision. We need not do
8562 this for POWERPC. */
8563 if (! TARGET_POWERPC && TARGET_HARD_FLOAT
8564 && GET_CODE (operands[1]) == REG
8565 && (FP_REGNO_P (REGNO (operands[1]))
8566 || REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))
8567 {
8568 rtx newreg
8569 = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
8570 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
8571 operands[1] = newreg;
8572 }
8574 operands[1] = force_reg (SFmode, operands[1]);
8575 }
8577 if (CONSTANT_P (operands[1]) && TARGET_HARD_FLOAT)
8578 {
8579 operands[1] = force_const_mem (SFmode, operands[1]);
8580 if (! memory_address_p (SFmode, XEXP (operands[1], 0))
8581 && ! reload_in_progress)
8582 operands[1] = change_address (operands[1], SFmode,
8583 XEXP (operands[1], 0));
8584 }
8585 }")
8587 (define_split
8588 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8589 (match_operand:SF 1 "const_double_operand" ""))]
8590 "reload_completed
8591 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8592 || (GET_CODE (operands[0]) == SUBREG
8593 && GET_CODE (SUBREG_REG (operands[0])) == REG
8594 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8595 [(set (match_dup 2) (match_dup 3))]
8596 "
8597 {
8598 long l;
8599 REAL_VALUE_TYPE rv;
8601 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8602 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8604 if (! TARGET_POWERPC64)
8605 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8606 else
8607 operands[2] = gen_lowpart (SImode, operands[0]);
8609 operands[3] = GEN_INT(l);
8610 }")
8612 (define_insn "*movsf_hardfloat"
8613 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!r,!r")
8614 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,G,Fn"))]
8615 "(gpc_reg_operand (operands[0], SFmode)
8616 || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT"
8617 "@
8618 mr %0,%1
8619 {l%U1%X1|lwz%U1%X1} %0,%1
8620 {st%U0%X0|stw%U0%X0} %1,%0
8621 fmr %0,%1
8622 lfs%U1%X1 %0,%1
8623 stfs%U0%X0 %1,%0
8624 #
8625 #"
8626 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*")
8627 (set_attr "length" "4,4,4,4,4,4,4,8")])
8629 (define_insn "*movsf_softfloat"
8630 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r")
8631 (match_operand:SF 1 "input_operand" "r,m,r,I,J,R,G,Fn"))]
8632 "(gpc_reg_operand (operands[0], SFmode)
8633 || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT"
8634 "@
8635 mr %0,%1
8636 {l%U1%X1|lwz%U1%X1} %0,%1
8637 {st%U0%X0|stw%U0%X0} %1,%0
8638 {lil|li} %0,%1
8639 {liu|lis} %0,%v1
8640 {cal|la} %0,%1(%*)
8641 #
8642 #"
8643 [(set_attr "type" "*,load,store,*,*,*,*,*")
8644 (set_attr "length" "4,4,4,4,4,4,4,8")])
8646 \f
8647 (define_expand "movdf"
8648 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8649 (match_operand:DF 1 "any_operand" ""))]
8650 ""
8651 "
8652 {
8653 if (GET_CODE (operands[0]) != REG)
8654 operands[1] = force_reg (DFmode, operands[1]);
8656 if (CONSTANT_P (operands[1]) && ! easy_fp_constant (operands[1], DFmode))
8657 {
8658 operands[1] = force_const_mem (DFmode, operands[1]);
8659 if (! memory_address_p (DFmode, XEXP (operands[1], 0))
8660 && ! reload_in_progress)
8661 operands[1] = change_address (operands[1], DFmode,
8662 XEXP (operands[1], 0));
8663 }
8664 }")
8666 (define_split
8667 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8668 (match_operand:DF 1 "const_int_operand" ""))]
8669 "! TARGET_POWERPC64 && reload_completed
8670 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8671 || (GET_CODE (operands[0]) == SUBREG
8672 && GET_CODE (SUBREG_REG (operands[0])) == REG
8673 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8674 [(set (match_dup 2) (match_dup 4))
8675 (set (match_dup 3) (match_dup 1))]
8676 "
8677 {
8678 int endian = (WORDS_BIG_ENDIAN == 0);
8679 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8680 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8681 operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx;
8682 }")
8684 (define_split
8685 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8686 (match_operand:DF 1 "const_double_operand" ""))]
8687 "! TARGET_POWERPC64 && reload_completed
8688 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8689 || (GET_CODE (operands[0]) == SUBREG
8690 && GET_CODE (SUBREG_REG (operands[0])) == REG
8691 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8692 [(set (match_dup 2) (match_dup 4))
8693 (set (match_dup 3) (match_dup 5))]
8694 "
8695 {
8696 int endian = (WORDS_BIG_ENDIAN == 0);
8697 long l[2];
8698 REAL_VALUE_TYPE rv;
8700 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8701 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8703 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8704 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8705 operands[4] = GEN_INT (l[endian]);
8706 operands[5] = GEN_INT (l[1 - endian]);
8707 }")
8709 (define_split
8710 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8711 (match_operand:DF 1 "easy_fp_constant" ""))]
8712 "TARGET_POWERPC64 && reload_completed
8713 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8714 || (GET_CODE (operands[0]) == SUBREG
8715 && GET_CODE (SUBREG_REG (operands[0])) == REG
8716 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8717 [(set (match_dup 2) (match_dup 3))]
8718 "
8719 {
8720 int endian = (WORDS_BIG_ENDIAN == 0);
8721 long l[2];
8722 REAL_VALUE_TYPE rv;
8724 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8725 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8727 operands[2] = gen_lowpart (DImode, operands[0]);
8728 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8729 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8730 }")
8732 ;; Don't have reload use general registers to load a constant. First,
8733 ;; it might not work if the output operand is the equivalent of
8734 ;; a non-offsettable memref, but also it is less efficient than loading
8735 ;; the constant into an FP register, since it will probably be used there.
8736 ;; The "??" is a kludge until we can figure out a more reasonable way
8737 ;; of handling these non-offsettable values.
8738 (define_insn "*movdf_hardfloat32"
8739 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,o,!r,!r,!r,f,f,m")
8740 (match_operand:DF 1 "input_operand" "r,o,r,G,H,F,f,m,f"))]
8741 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT
8742 && (register_operand (operands[0], DFmode)
8743 || register_operand (operands[1], DFmode))"
8744 "*
8745 {
8746 switch (which_alternative)
8747 {
8748 default:
8749 abort ();
8750 case 0:
8751 /* We normally copy the low-numbered register first. However, if
8752 the first register operand 0 is the same as the second register of
8753 operand 1, we must copy in the opposite order. */
8754 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8755 return \"mr %L0,%L1\;mr %0,%1\";
8756 else
8757 return \"mr %0,%1\;mr %L0,%L1\";
8758 case 1:
8759 /* If the low-address word is used in the address, we must load it
8760 last. Otherwise, load it first. Note that we cannot have
8761 auto-increment in that case since the address register is known to be
8762 dead. */
8763 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8764 operands [1], 0))
8765 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8766 else
8767 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8768 case 2:
8769 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8770 case 3:
8771 case 4:
8772 case 5:
8773 return \"#\";
8774 case 6:
8775 return \"fmr %0,%1\";
8776 case 7:
8777 return \"lfd%U1%X1 %0,%1\";
8778 case 8:
8779 return \"stfd%U0%X0 %1,%0\";
8780 }
8781 }"
8782 [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
8783 (set_attr "length" "8,8,8,8,12,16,*,*,*")])
8785 (define_insn "*movdf_softfloat32"
8786 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8787 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8788 "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT
8789 && (register_operand (operands[0], DFmode)
8790 || register_operand (operands[1], DFmode))"
8791 "*
8792 {
8793 switch (which_alternative)
8794 {
8795 default:
8796 abort ();
8797 case 0:
8798 /* We normally copy the low-numbered register first. However, if
8799 the first register operand 0 is the same as the second register of
8800 operand 1, we must copy in the opposite order. */
8801 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8802 return \"mr %L0,%L1\;mr %0,%1\";
8803 else
8804 return \"mr %0,%1\;mr %L0,%L1\";
8805 case 1:
8806 /* If the low-address word is used in the address, we must load it
8807 last. Otherwise, load it first. Note that we cannot have
8808 auto-increment in that case since the address register is known to be
8809 dead. */
8810 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8811 operands [1], 0))
8812 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8813 else
8814 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8815 case 2:
8816 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8817 case 3:
8818 case 4:
8819 case 5:
8820 return \"#\";
8821 }
8822 }"
8823 [(set_attr "type" "*,load,store,*,*,*")
8824 (set_attr "length" "8,8,8,8,12,16")])
8826 (define_insn "*movdf_hardfloat64"
8827 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m")
8828 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))]
8829 "TARGET_POWERPC64 && TARGET_HARD_FLOAT
8830 && (register_operand (operands[0], DFmode)
8831 || register_operand (operands[1], DFmode))"
8832 "@
8833 mr %0,%1
8834 ld%U1%X1 %0,%1
8835 std%U0%X0 %1,%0
8836 #
8837 #
8838 #
8839 fmr %0,%1
8840 lfd%U1%X1 %0,%1
8841 stfd%U0%X0 %1,%0"
8842 [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore")
8843 (set_attr "length" "4,4,4,8,12,16,4,4,4")])
8845 (define_insn "*movdf_softfloat64"
8846 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8847 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8848 "TARGET_POWERPC64 && TARGET_SOFT_FLOAT
8849 && (register_operand (operands[0], DFmode)
8850 || register_operand (operands[1], DFmode))"
8851 "@
8852 mr %0,%1
8853 ld%U1%X1 %0,%1
8854 std%U0%X0 %1,%0
8855 #
8856 #
8857 #"
8858 [(set_attr "type" "*,load,store,*,*,*")
8859 (set_attr "length" "*,*,*,8,12,16")])
8860 \f
8861 ;; Next come the multi-word integer load and store and the load and store
8862 ;; multiple insns.
8863 (define_expand "movdi"
8864 [(set (match_operand:DI 0 "general_operand" "")
8865 (match_operand:DI 1 "any_operand" ""))]
8866 ""
8867 "
8868 {
8869 if (GET_CODE (operands[0]) != REG)
8870 operands[1] = force_reg (DImode, operands[1]);
8872 /* Convert a move of a CONST_DOUBLE into a CONST_INT
8873 only if sign-extended lower-half for 32-bit host. */
8874 if (GET_CODE (operands[1]) == CONST_DOUBLE
8875 #if HOST_BITS_PER_WIDE_INT == 32
8876 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
8877 && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0)
8878 || (CONST_DOUBLE_HIGH (operands[1]) == 0xffffffff
8879 && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0))
8880 #endif
8881 )
8882 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
8884 /* Only a tiny bit of handling for CONSTANT_P_RTX is necessary. */
8885 if (GET_CODE (operands[1]) == CONST
8886 && GET_CODE (XEXP (operands[1], 0)) == CONSTANT_P_RTX)
8887 {
8888 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
8889 DONE;
8890 }
8892 if (TARGET_64BIT
8893 && CONSTANT_P (operands[1])
8894 #if HOST_BITS_PER_WIDE_INT == 32
8895 && GET_CODE (operands[1]) != CONST_INT
8896 #endif
8897 && ! easy_fp_constant (operands[1], DImode)
8898 && ! LEGITIMATE_CONSTANT_POOL_ADDRESS_P (operands[1]))
8899 {
8900 /* Emit a USE operation so that the constant isn't deleted if
8901 expensive optimizations are turned on because nobody
8902 references it. This should only be done for operands that
8903 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
8904 This should not be done for operands that contain LABEL_REFs.
8905 For now, we just handle the obvious case. */
8906 if (GET_CODE (operands[1]) != LABEL_REF)
8907 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
8909 /* If we are to limit the number of things we put in the TOC and
8910 this is a symbol plus a constant we can add in one insn,
8911 just put the symbol in the TOC and add the constant. Don't do
8912 this if reload is in progress. */
8913 if (GET_CODE (operands[1]) == CONST
8914 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
8915 && GET_CODE (XEXP (operands[1], 0)) == PLUS
8916 && add_operand (XEXP (XEXP (operands[1], 0), 1), DImode)
8917 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
8918 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
8919 && ! side_effects_p (operands[0]))
8920 {
8921 rtx sym = force_const_mem (DImode, XEXP (XEXP (operands[1], 0), 0));
8922 rtx other = XEXP (XEXP (operands[1], 0), 1);
8924 emit_insn (gen_adddi3 (operands[0], force_reg (DImode, sym), other));
8925 DONE;
8926 }
8928 operands[1] = force_const_mem (DImode, operands[1]);
8929 if (! memory_address_p (DImode, XEXP (operands[1], 0))
8930 && ! reload_in_progress)
8931 operands[1] = change_address (operands[1], DImode,
8932 XEXP (operands[1], 0));
8933 }
8934 }")
8936 (define_insn "*movdi_32"
8937 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
8938 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
8939 "! TARGET_POWERPC64
8940 && (gpc_reg_operand (operands[0], DImode)
8941 || gpc_reg_operand (operands[1], DImode))"
8942 "*
8943 {
8944 switch (which_alternative)
8945 {
8946 default:
8947 abort ();
8948 case 0:
8949 /* We normally copy the low-numbered register first. However, if
8950 the first register operand 0 is the same as the second register of
8951 operand 1, we must copy in the opposite order. */
8952 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8953 return \"mr %L0,%L1\;mr %0,%1\";
8954 else
8955 return \"mr %0,%1\;mr %L0,%L1\";
8956 case 1:
8957 /* If the low-address word is used in the address, we must load it
8958 last. Otherwise, load it first. Note that we cannot have
8959 auto-increment in that case since the address register is known to be
8960 dead. */
8961 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8962 operands [1], 0))
8963 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8964 else
8965 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8966 case 2:
8967 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8968 case 3:
8969 return \"fmr %0,%1\";
8970 case 4:
8971 return \"lfd%U1%X1 %0,%1\";
8972 case 5:
8973 return \"stfd%U0%X0 %1,%0\";
8974 case 6:
8975 case 7:
8976 case 8:
8977 case 9:
8978 case 10:
8979 return \"#\";
8980 }
8981 }"
8982 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")
8983 (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")])
8985 (define_split
8986 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8987 (match_operand:DI 1 "const_int_operand" ""))]
8988 "! TARGET_POWERPC64 && reload_completed"
8989 [(set (match_dup 2) (match_dup 4))
8990 (set (match_dup 3) (match_dup 1))]
8991 "
8992 {
8993 operands[2] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN == 0);
8994 operands[3] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN != 0);
8995 operands[4] = (INTVAL (operands[1]) & 0x80000000) ? constm1_rtx : const0_rtx;
8996 }")
8998 (define_split
8999 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9000 (match_operand:DI 1 "const_double_operand" ""))]
9001 "! TARGET_POWERPC64 && reload_completed"
9002 [(set (match_dup 2) (match_dup 4))
9003 (set (match_dup 3) (match_dup 5))]
9004 "
9005 {
9006 operands[2] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN == 0);
9007 operands[3] = gen_rtx_SUBREG (SImode, operands[0], WORDS_BIG_ENDIAN != 0);
9008 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9009 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9010 }")
9012 (define_insn "*movdi_64"
9013 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h")
9014 (match_operand:DI 1 "input_operand" "r,m,r,I,J,nF,R,f,m,f,*h,r,0"))]
9015 "TARGET_POWERPC64
9016 && (gpc_reg_operand (operands[0], DImode)
9017 || gpc_reg_operand (operands[1], DImode))"
9018 "@
9019 mr %0,%1
9020 ld%U1%X1 %0,%1
9021 std%U0%X0 %1,%0
9022 li %0,%1
9023 lis %0,%v1
9024 #
9025 {cal|la} %0,%1(%*)
9026 fmr %0,%1
9027 lfd%U1%X1 %0,%1
9028 stfd%U0%X0 %1,%0
9029 mf%1 %0
9030 mt%0 %1
9031 cror 0,0,0"
9032 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*")
9033 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9035 (define_insn ""
9036 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9037 (match_operand:DI 1 "const_double_operand" "F"))]
9038 "TARGET_POWERPC64 && GET_CODE (operands[1]) == CONST_DOUBLE
9039 && num_insns_constant (operands[1], DImode) == 1"
9040 "*
9041 {
9042 return ((unsigned HOST_WIDE_INT)
9043 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9044 ? \"li %0,%1\" : \"lis %0,%v1\";
9045 }")
9047 (define_split
9048 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9049 (match_operand:DI 1 "const_int_operand" ""))]
9050 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9051 && num_insns_constant (operands[1], DImode) > 1"
9052 [(set (match_dup 0)
9053 (match_dup 2))
9054 (set (match_dup 0)
9055 (ior:DI (match_dup 0)
9056 (match_dup 3)))]
9057 "
9058 {
9059 operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000);
9060 operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff);
9061 }")
9063 (define_split
9064 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9065 (match_operand:DI 1 "const_double_operand" ""))]
9066 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9067 && GET_CODE (operands[1]) == CONST_DOUBLE
9068 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
9069 && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) == 0)
9070 || (CONST_DOUBLE_HIGH (operands[1]) == 0xffffffff
9071 && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0))"
9072 [(set (match_dup 0)
9073 (match_dup 2))
9074 (set (match_dup 0)
9075 (ior:DI (match_dup 0)
9076 (match_dup 3)))]
9077 "
9078 {
9079 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xffff0000);
9080 operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[1]) & 0xffff);
9081 }")
9083 (define_split
9084 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9085 (match_operand:DI 1 "const_double_operand" ""))]
9086 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9087 && GET_CODE (operands[1]) == CONST_DOUBLE
9088 && CONST_DOUBLE_HIGH (operands[1]) == 0
9089 && (CONST_DOUBLE_LOW (operands[1]) & 0x80000000) != 0"
9090 [(set (match_dup 0)
9091 (match_dup 2))
9092 (set (match_dup 0)
9093 (zero_extend:DI (subreg:SI (match_dup 0) 0)))]
9094 "
9095 { operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); }")
9097 (define_split
9098 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9099 (match_operand:DI 1 "const_double_operand" ""))]
9100 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9101 && GET_CODE (operands[1]) == CONST_DOUBLE
9102 && CONST_DOUBLE_LOW (operands[1]) == 0"
9103 [(set (match_dup 0)
9104 (match_dup 2))
9105 (set (match_dup 0)
9106 (ashift:DI (match_dup 0)
9107 (const_int 32)))]
9108 "
9109 { operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); }")
9111 ;; Generate all one-bits and clear left or right.
9112 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9113 (define_split
9114 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9115 (match_operand:DI 1 "mask64_operand" ""))]
9116 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9117 [(set (match_dup 0) (const_int -1))
9118 (set (match_dup 0)
9119 (and:DI (rotate:DI (match_dup 0)
9120 (const_int 0))
9121 (match_dup 1)))]
9122 "")
9124 ;; Split a load of a large constant into the appropriate five-instruction
9125 ;; sequence. Handle anything in a constant number of insns.
9126 ;; When non-easy constants can go in the TOC, this should use
9127 ;; easy_fp_constant predicate.
9128 (define_split
9129 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9130 (match_operand:DI 1 "const_double_operand" ""))]
9131 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9132 [(set (match_dup 0)
9133 (match_dup 2))
9134 (set (match_dup 0)
9135 (ashift:DI (match_dup 0)
9136 (const_int 32)))
9137 (set (match_dup 0)
9138 (ior:DI (match_dup 0)
9139 (match_dup 3)))]
9140 "
9141 {
9142 HOST_WIDE_INT low;
9143 HOST_WIDE_INT high;
9145 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9146 {
9147 low = CONST_DOUBLE_LOW (operands[1]);
9148 high = CONST_DOUBLE_HIGH (operands[1]);
9149 }
9150 else
9151 #if HOST_BITS_PER_WIDE_INT == 32
9152 {
9153 low = INTVAL (operands[1]);
9154 high = (low < 0) ? ~0 : 0;
9155 }
9156 #else
9157 {
9158 low = INTVAL (operands[1]) & 0xffffffff;
9159 high = (HOST_WIDE_INT) INTVAL (operands[1]) >> 32;
9160 }
9161 #endif
9163 operands[2] = GEN_INT (high);
9164 operands[3] = GEN_INT (low);
9165 }")
9167 (define_insn ""
9168 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
9169 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r")
9170 (const_int 0)))
9171 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
9172 "TARGET_POWERPC64"
9173 "mr. %0,%1"
9174 [(set_attr "type" "compare")])
9176 (define_insn ""
9177 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
9178 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r")
9179 (const_int 0)))
9180 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
9181 ""
9182 "mr. %0,%1"
9183 [(set_attr "type" "compare")])
9185 (define_split
9186 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
9187 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
9188 (const_int 0)))
9189 (set (match_operand:DI 0 "gpc_reg_operand" "")
9190 (match_dup 1))]
9191 "reload_completed && rtx_equal_p (operands[0], operands[1])"
9192 [(set (match_dup 2)
9193 (compare:CC (match_dup 1)
9194 (const_int 0)))]
9195 "")
9197 (define_split
9198 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
9199 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
9200 (const_int 0)))
9201 (set (match_operand:DI 0 "gpc_reg_operand" "")
9202 (match_dup 1))]
9203 "reload_completed && !rtx_equal_p (operands[0], operands[1])"
9204 [(set (match_dup 2)
9205 (compare:CC (match_dup 1)
9206 (const_int 0)))
9207 (set (match_dup 0)
9208 (match_dup 1))]
9209 "")
9210 \f
9211 ;; TImode is similar, except that we usually want to compute the address into
9212 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
9213 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
9214 (define_expand "movti"
9215 [(parallel [(set (match_operand:TI 0 "general_operand" "")
9216 (match_operand:TI 1 "general_operand" ""))
9217 (clobber (scratch:SI))])]
9218 "TARGET_STRING || TARGET_POWERPC64"
9219 "
9220 {
9221 if (GET_CODE (operands[0]) == MEM)
9222 operands[1] = force_reg (TImode, operands[1]);
9224 if (GET_CODE (operands[0]) == MEM
9225 && GET_CODE (XEXP (operands[0], 0)) != REG
9226 && ! reload_in_progress)
9227 operands[0] = change_address (operands[0], TImode,
9228 copy_addr_to_reg (XEXP (operands[0], 0)));
9230 if (GET_CODE (operands[1]) == MEM
9231 && GET_CODE (XEXP (operands[1], 0)) != REG
9232 && ! reload_in_progress)
9233 operands[1] = change_address (operands[1], TImode,
9234 copy_addr_to_reg (XEXP (operands[1], 0)));
9235 }")
9237 ;; We say that MQ is clobbered in the last alternative because the first
9238 ;; alternative would never get used otherwise since it would need a reload
9239 ;; while the 2nd alternative would not. We put memory cases first so they
9240 ;; are preferred. Otherwise, we'd try to reload the output instead of
9241 ;; giving the SCRATCH mq.
9242 (define_insn "*movti_power"
9243 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
9244 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
9245 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
9246 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9247 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9248 "*
9249 {
9250 switch (which_alternative)
9251 {
9252 default:
9253 abort ();
9255 case 0:
9256 return \"{stsi|stswi} %1,%P0,16\";
9258 case 1:
9259 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
9261 case 2:
9262 /* Normally copy registers with lowest numbered register copied first.
9263 But copy in the other order if the first register of the output
9264 is the second, third, or fourth register in the input. */
9265 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
9266 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
9267 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
9268 else
9269 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
9270 case 3:
9271 /* If the address is not used in the output, we can use lsi. Otherwise,
9272 fall through to generating four loads. */
9273 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
9274 return \"{lsi|lswi} %0,%P1,16\";
9275 /* ... fall through ... */
9276 case 4:
9277 /* If the address register is the same as the register for the lowest-
9278 addressed word, load it last. Similarly for the next two words.
9279 Otherwise load lowest address to highest. */
9280 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
9281 operands[1], 0))
9282 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
9283 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
9284 REGNO (operands[0]) + 2, operands[1], 0))
9285 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
9286 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
9287 REGNO (operands[0]) + 3, operands[1], 0))
9288 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
9289 else
9290 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
9291 }
9292 }"
9293 [(set_attr "type" "store,store,*,load,load")
9294 (set_attr "length" "*,16,16,*,16")])
9296 (define_insn "*movti_string"
9297 [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r")
9298 (match_operand:TI 1 "reg_or_mem_operand" "r,r,m"))
9299 (clobber (match_scratch:SI 2 "=X,X,X"))]
9300 "TARGET_STRING && !TARGET_POWER && ! TARGET_POWERPC64
9301 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9302 "*
9303 {
9304 switch (which_alternative)
9305 {
9306 default:
9307 abort ();
9309 case 0:
9310 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
9312 case 1:
9313 /* Normally copy registers with lowest numbered register copied first.
9314 But copy in the other order if the first register of the output
9315 is the second, third, or fourth register in the input. */
9316 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
9317 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
9318 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
9319 else
9320 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
9321 case 2:
9322 /* If the address register is the same as the register for the lowest-
9323 addressed word, load it last. Similarly for the next two words.
9324 Otherwise load lowest address to highest. */
9325 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
9326 operands[1], 0))
9327 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
9328 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
9329 REGNO (operands[0]) + 2, operands[1], 0))
9330 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
9331 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
9332 REGNO (operands[0]) + 3, operands[1], 0))
9333 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
9334 else
9335 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
9336 }
9337 }"
9338 [(set_attr "type" "store,*,load")
9339 (set_attr "length" "16,16,16")])
9341 (define_insn "*movti_ppc64"
9342 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
9343 (match_operand:TI 1 "input_operand" "r,m,r"))]
9344 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9345 || gpc_reg_operand (operands[1], TImode))"
9346 "*
9347 {
9348 switch (which_alternative)
9349 {
9350 default:
9351 abort ();
9352 case 0:
9353 /* We normally copy the low-numbered register first. However, if
9354 the first register operand 0 is the same as the second register of
9355 operand 1, we must copy in the opposite order. */
9356 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9357 return \"mr %L0,%L1\;mr %0,%1\";
9358 else
9359 return \"mr %0,%1\;mr %L0,%L1\";
9360 case 1:
9361 /* If the low-address word is used in the address, we must load it
9362 last. Otherwise, load it first. Note that we cannot have
9363 auto-increment in that case since the address register is known to be
9364 dead. */
9365 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
9366 operands [1], 0))
9367 return \"ld %L0,%L1\;ld %0,%1\";
9368 else
9369 return \"ld%U1 %0,%1\;ld %L0,%L1\";
9370 case 2:
9371 return \"std%U0 %1,%0\;std %L1,%L0\";
9372 }
9373 }"
9374 [(set_attr "type" "*,load,store")
9375 (set_attr "length" "8,8,8")])
9376 \f
9377 (define_expand "load_multiple"
9378 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9379 (match_operand:SI 1 "" ""))
9380 (use (match_operand:SI 2 "" ""))])]
9381 "TARGET_STRING"
9382 "
9383 {
9384 int regno;
9385 int count;
9386 rtx from;
9387 int i;
9389 /* Support only loading a constant number of fixed-point registers from
9390 memory and only bother with this if more than two; the machine
9391 doesn't support more than eight. */
9392 if (GET_CODE (operands[2]) != CONST_INT
9393 || INTVAL (operands[2]) <= 2
9394 || INTVAL (operands[2]) > 8
9395 || GET_CODE (operands[1]) != MEM
9396 || GET_CODE (operands[0]) != REG
9397 || REGNO (operands[0]) >= 32)
9398 FAIL;
9400 count = INTVAL (operands[2]);
9401 regno = REGNO (operands[0]);
9403 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9404 from = force_reg (SImode, XEXP (operands[1], 0));
9406 for (i = 0; i < count; i++)
9407 XVECEXP (operands[3], 0, i)
9408 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9409 change_address (operands[1], SImode,
9410 plus_constant (from, i * 4)));
9411 }")
9413 (define_insn ""
9414 [(match_parallel 0 "load_multiple_operation"
9415 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
9416 (mem:SI (match_operand:SI 2 "register_operand" "b")))])]
9417 "TARGET_STRING"
9418 "*
9419 {
9420 /* We have to handle the case where the pseudo used to contain the address
9421 is assigned to one of the output registers. */
9422 int i, j;
9423 int words = XVECLEN (operands[0], 0);
9424 rtx xop[10];
9426 if (XVECLEN (operands[0], 0) == 1)
9427 return \"{l|lwz} %1,0(%2)\";
9429 for (i = 0; i < words; i++)
9430 if (refers_to_regno_p (REGNO (operands[1]) + i,
9431 REGNO (operands[1]) + i + 1, operands[2], 0))
9432 {
9433 if (i == words-1)
9434 {
9435 xop[0] = operands[1];
9436 xop[1] = operands[2];
9437 xop[2] = GEN_INT (4 * (words-1));
9438 output_asm_insn (\"{lsi|lswi} %0,%1,%2\;{l|lwz} %1,%2(%1)\", xop);
9439 return \"\";
9440 }
9441 else if (i == 0)
9442 {
9443 xop[0] = operands[1];
9444 xop[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
9445 xop[2] = GEN_INT (4 * (words-1));
9446 output_asm_insn (\"{cal %0,4(%0)|addi %0,%0,4}\;{lsi|lswi} %1,%0,%2\;{l|lwz} %0,-4(%0)\", xop);
9447 return \"\";
9448 }
9449 else
9450 {
9451 for (j = 0; j < words; j++)
9452 if (j != i)
9453 {
9454 xop[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + j);
9455 xop[1] = operands[2];
9456 xop[2] = GEN_INT (j * 4);
9457 output_asm_insn (\"{l|lwz} %0,%2(%1)\", xop);
9458 }
9459 xop[0] = operands[2];
9460 xop[1] = GEN_INT (i * 4);
9461 output_asm_insn (\"{l|lwz} %0,%1(%0)\", xop);
9462 return \"\";
9463 }
9464 }
9466 return \"{lsi|lswi} %1,%2,%N0\";
9467 }"
9468 [(set_attr "type" "load")
9469 (set_attr "length" "32")])
9471 \f
9472 (define_expand "store_multiple"
9473 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9474 (match_operand:SI 1 "" ""))
9475 (clobber (scratch:SI))
9476 (use (match_operand:SI 2 "" ""))])]
9477 "TARGET_STRING"
9478 "
9479 {
9480 int regno;
9481 int count;
9482 rtx to;
9483 int i;
9485 /* Support only storing a constant number of fixed-point registers to
9486 memory and only bother with this if more than two; the machine
9487 doesn't support more than eight. */
9488 if (GET_CODE (operands[2]) != CONST_INT
9489 || INTVAL (operands[2]) <= 2
9490 || INTVAL (operands[2]) > 8
9491 || GET_CODE (operands[0]) != MEM
9492 || GET_CODE (operands[1]) != REG
9493 || REGNO (operands[1]) >= 32)
9494 FAIL;
9496 count = INTVAL (operands[2]);
9497 regno = REGNO (operands[1]);
9499 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9500 to = force_reg (SImode, XEXP (operands[0], 0));
9502 XVECEXP (operands[3], 0, 0)
9503 = gen_rtx_SET (VOIDmode, change_address (operands[0], SImode, to),
9504 operands[1]);
9505 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9506 gen_rtx_SCRATCH (SImode));
9508 for (i = 1; i < count; i++)
9509 XVECEXP (operands[3], 0, i + 1)
9510 = gen_rtx_SET (VOIDmode,
9511 change_address (operands[0], SImode,
9512 plus_constant (to, i * 4)),
9513 gen_rtx_REG (SImode, regno + i));
9514 }")
9516 (define_insn ""
9517 [(match_parallel 0 "store_multiple_operation"
9518 [(set (match_operand:SI 1 "indirect_operand" "=Q")
9519 (match_operand:SI 2 "gpc_reg_operand" "r"))
9520 (clobber (match_scratch:SI 3 "=q"))])]
9521 "TARGET_STRING && TARGET_POWER"
9522 "{stsi|stswi} %2,%P1,%O0"
9523 [(set_attr "type" "store")])
9525 (define_insn ""
9526 [(match_parallel 0 "store_multiple_operation"
9527 [(set (mem:SI (match_operand:SI 1 "register_operand" "b"))
9528 (match_operand:SI 2 "gpc_reg_operand" "r"))
9529 (clobber (match_scratch:SI 3 "X"))])]
9530 "TARGET_STRING && !TARGET_POWER"
9531 "{stsi|stswi} %2,%1,%O0"
9532 [(set_attr "type" "store")])
9534 \f
9535 ;; String/block move insn.
9536 ;; Argument 0 is the destination
9537 ;; Argument 1 is the source
9538 ;; Argument 2 is the length
9539 ;; Argument 3 is the alignment
9541 (define_expand "movstrsi"
9542 [(parallel [(set (match_operand:BLK 0 "" "")
9543 (match_operand:BLK 1 "" ""))
9544 (use (match_operand:SI 2 "" ""))
9545 (use (match_operand:SI 3 "" ""))])]
9546 ""
9547 "
9548 {
9549 if (expand_block_move (operands))
9550 DONE;
9551 else
9552 FAIL;
9553 }")
9555 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9556 ;; register allocator doesn't have a clue about allocating 8 word registers
9557 (define_expand "movstrsi_8reg"
9558 [(parallel [(set (match_operand 0 "" "")
9559 (match_operand 1 "" ""))
9560 (use (match_operand 2 "" ""))
9561 (use (match_operand 3 "" ""))
9562 (clobber (reg:SI 5))
9563 (clobber (reg:SI 6))
9564 (clobber (reg:SI 7))
9565 (clobber (reg:SI 8))
9566 (clobber (reg:SI 9))
9567 (clobber (reg:SI 10))
9568 (clobber (reg:SI 11))
9569 (clobber (reg:SI 12))
9570 (clobber (match_scratch:SI 4 ""))])]
9571 "TARGET_STRING"
9572 "")
9574 (define_insn ""
9575 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
9576 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
9577 (use (match_operand:SI 2 "immediate_operand" "i"))
9578 (use (match_operand:SI 3 "immediate_operand" "i"))
9579 (clobber (match_operand:SI 4 "register_operand" "=r"))
9580 (clobber (reg:SI 6))
9581 (clobber (reg:SI 7))
9582 (clobber (reg:SI 8))
9583 (clobber (reg:SI 9))
9584 (clobber (reg:SI 10))
9585 (clobber (reg:SI 11))
9586 (clobber (reg:SI 12))
9587 (clobber (match_scratch:SI 5 "=q"))]
9588 "TARGET_STRING && TARGET_POWER
9589 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0)
9590 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9591 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9592 && REGNO (operands[4]) == 5"
9593 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9594 [(set_attr "type" "load")
9595 (set_attr "length" "8")])
9597 (define_insn ""
9598 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
9599 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
9600 (use (match_operand:SI 2 "immediate_operand" "i"))
9601 (use (match_operand:SI 3 "immediate_operand" "i"))
9602 (clobber (match_operand:SI 4 "register_operand" "=r"))
9603 (clobber (reg:SI 6))
9604 (clobber (reg:SI 7))
9605 (clobber (reg:SI 8))
9606 (clobber (reg:SI 9))
9607 (clobber (reg:SI 10))
9608 (clobber (reg:SI 11))
9609 (clobber (reg:SI 12))
9610 (clobber (match_scratch:SI 5 "X"))]
9611 "TARGET_STRING && !TARGET_POWER
9612 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) || INTVAL (operands[2]) == 0)
9613 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9614 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9615 && REGNO (operands[4]) == 5"
9616 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9617 [(set_attr "type" "load")
9618 (set_attr "length" "8")])
9620 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9621 ;; register allocator doesn't have a clue about allocating 6 word registers
9622 (define_expand "movstrsi_6reg"
9623 [(parallel [(set (match_operand 0 "" "")
9624 (match_operand 1 "" ""))
9625 (use (match_operand 2 "" ""))
9626 (use (match_operand 3 "" ""))
9627 (clobber (reg:SI 7))
9628 (clobber (reg:SI 8))
9629 (clobber (reg:SI 9))
9630 (clobber (reg:SI 10))
9631 (clobber (reg:SI 11))
9632 (clobber (reg:SI 12))
9633 (clobber (match_scratch:SI 4 ""))])]
9634 "TARGET_STRING"
9635 "")
9637 (define_insn ""
9638 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
9639 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
9640 (use (match_operand:SI 2 "immediate_operand" "i"))
9641 (use (match_operand:SI 3 "immediate_operand" "i"))
9642 (clobber (match_operand:SI 4 "register_operand" "=r"))
9643 (clobber (reg:SI 8))
9644 (clobber (reg:SI 9))
9645 (clobber (reg:SI 10))
9646 (clobber (reg:SI 11))
9647 (clobber (reg:SI 12))
9648 (clobber (match_scratch:SI 5 "=q"))]
9649 "TARGET_STRING && TARGET_POWER
9650 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9651 && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12)
9652 && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12)
9653 && REGNO (operands[4]) == 7"
9654 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9655 [(set_attr "type" "load")
9656 (set_attr "length" "8")])
9658 (define_insn ""
9659 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
9660 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
9661 (use (match_operand:SI 2 "immediate_operand" "i"))
9662 (use (match_operand:SI 3 "immediate_operand" "i"))
9663 (clobber (match_operand:SI 4 "register_operand" "=r"))
9664 (clobber (reg:SI 8))
9665 (clobber (reg:SI 9))
9666 (clobber (reg:SI 10))
9667 (clobber (reg:SI 11))
9668 (clobber (reg:SI 12))
9669 (clobber (match_scratch:SI 5 "X"))]
9670 "TARGET_STRING && !TARGET_POWER
9671 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9672 && (REGNO (operands[0]) < 7 || REGNO (operands[0]) > 12)
9673 && (REGNO (operands[1]) < 7 || REGNO (operands[1]) > 12)
9674 && REGNO (operands[4]) == 7"
9675 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9676 [(set_attr "type" "load")
9677 (set_attr "length" "8")])
9679 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill problems
9680 ;; with TImode
9681 (define_expand "movstrsi_4reg"
9682 [(parallel [(set (match_operand 0 "" "")
9683 (match_operand 1 "" ""))
9684 (use (match_operand 2 "" ""))
9685 (use (match_operand 3 "" ""))
9686 (clobber (reg:SI 9))
9687 (clobber (reg:SI 10))
9688 (clobber (reg:SI 11))
9689 (clobber (reg:SI 12))
9690 (clobber (match_scratch:SI 4 ""))])]
9691 "TARGET_STRING"
9692 "")
9694 (define_insn ""
9695 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
9696 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
9697 (use (match_operand:SI 2 "immediate_operand" "i"))
9698 (use (match_operand:SI 3 "immediate_operand" "i"))
9699 (clobber (match_operand:SI 4 "register_operand" "=r"))
9700 (clobber (reg:SI 10))
9701 (clobber (reg:SI 11))
9702 (clobber (reg:SI 12))
9703 (clobber (match_scratch:SI 5 "=q"))]
9704 "TARGET_STRING && TARGET_POWER
9705 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9706 && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12)
9707 && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12)
9708 && REGNO (operands[4]) == 9"
9709 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9710 [(set_attr "type" "load")
9711 (set_attr "length" "8")])
9713 (define_insn ""
9714 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
9715 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
9716 (use (match_operand:SI 2 "immediate_operand" "i"))
9717 (use (match_operand:SI 3 "immediate_operand" "i"))
9718 (clobber (match_operand:SI 4 "register_operand" "=r"))
9719 (clobber (reg:SI 10))
9720 (clobber (reg:SI 11))
9721 (clobber (reg:SI 12))
9722 (clobber (match_scratch:SI 5 "X"))]
9723 "TARGET_STRING && !TARGET_POWER
9724 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9725 && (REGNO (operands[0]) < 9 || REGNO (operands[0]) > 12)
9726 && (REGNO (operands[1]) < 9 || REGNO (operands[1]) > 12)
9727 && REGNO (operands[4]) == 9"
9728 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9729 [(set_attr "type" "load")
9730 (set_attr "length" "8")])
9732 ;; Move up to 8 bytes at a time.
9733 (define_expand "movstrsi_2reg"
9734 [(parallel [(set (match_operand 0 "" "")
9735 (match_operand 1 "" ""))
9736 (use (match_operand 2 "" ""))
9737 (use (match_operand 3 "" ""))
9738 (clobber (match_scratch:DI 4 ""))
9739 (clobber (match_scratch:SI 5 ""))])]
9740 "TARGET_STRING && !TARGET_64BIT"
9741 "")
9743 (define_insn ""
9744 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
9745 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
9746 (use (match_operand:SI 2 "immediate_operand" "i"))
9747 (use (match_operand:SI 3 "immediate_operand" "i"))
9748 (clobber (match_scratch:DI 4 "=&r"))
9749 (clobber (match_scratch:SI 5 "=q"))]
9750 "TARGET_STRING && TARGET_POWER && !TARGET_64BIT
9751 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9752 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9753 [(set_attr "type" "load")
9754 (set_attr "length" "8")])
9756 (define_insn ""
9757 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
9758 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
9759 (use (match_operand:SI 2 "immediate_operand" "i"))
9760 (use (match_operand:SI 3 "immediate_operand" "i"))
9761 (clobber (match_scratch:DI 4 "=&r"))
9762 (clobber (match_scratch:SI 5 "X"))]
9763 "TARGET_STRING && !TARGET_POWER && !TARGET_64BIT
9764 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9765 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9766 [(set_attr "type" "load")
9767 (set_attr "length" "8")])
9769 ;; Move up to 4 bytes at a time.
9770 (define_expand "movstrsi_1reg"
9771 [(parallel [(set (match_operand 0 "" "")
9772 (match_operand 1 "" ""))
9773 (use (match_operand 2 "" ""))
9774 (use (match_operand 3 "" ""))
9775 (clobber (match_scratch:SI 4 ""))
9776 (clobber (match_scratch:SI 5 ""))])]
9777 "TARGET_STRING"
9778 "")
9780 (define_insn ""
9781 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
9782 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
9783 (use (match_operand:SI 2 "immediate_operand" "i"))
9784 (use (match_operand:SI 3 "immediate_operand" "i"))
9785 (clobber (match_scratch:SI 4 "=&r"))
9786 (clobber (match_scratch:SI 5 "=q"))]
9787 "TARGET_STRING && TARGET_POWER
9788 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9789 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9790 [(set_attr "type" "load")
9791 (set_attr "length" "8")])
9793 (define_insn ""
9794 [(set (mem:BLK (match_operand:SI 0 "register_operand" "b"))
9795 (mem:BLK (match_operand:SI 1 "register_operand" "b")))
9796 (use (match_operand:SI 2 "immediate_operand" "i"))
9797 (use (match_operand:SI 3 "immediate_operand" "i"))
9798 (clobber (match_scratch:SI 4 "=&r"))
9799 (clobber (match_scratch:SI 5 "X"))]
9800 "TARGET_STRING && !TARGET_POWER
9801 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9802 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9803 [(set_attr "type" "load")
9804 (set_attr "length" "8")])
9806 \f
9807 ;; Define insns that do load or store with update. Some of these we can
9808 ;; get by using pre-decrement or pre-increment, but the hardware can also
9809 ;; do cases where the increment is not the size of the object.
9810 ;;
9811 ;; In all these cases, we use operands 0 and 1 for the register being
9812 ;; incremented because those are the operands that local-alloc will
9813 ;; tie and these are the pair most likely to be tieable (and the ones
9814 ;; that will benefit the most).
9816 (define_insn "*movdi_update1"
9817 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9818 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9819 (match_operand:DI 2 "reg_or_short_operand" "r,I"))))
9820 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9821 (plus:DI (match_dup 1) (match_dup 2)))]
9822 "TARGET_POWERPC64 && TARGET_UPDATE"
9823 "@
9824 ldux %3,%0,%2
9825 ldu %3,%2(%0)"
9826 [(set_attr "type" "load")])
9828 (define_insn "*movdi_update2"
9829 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9830 (sign_extend:DI
9831 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9832 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9833 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9834 (plus:DI (match_dup 1) (match_dup 2)))]
9835 "TARGET_POWERPC64"
9836 "lwaux %3,%0,%2"
9837 [(set_attr "type" "load")])
9839 (define_insn "movdi_update"
9840 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9841 (match_operand:DI 2 "reg_or_short_operand" "r,I")))
9842 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9843 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9844 (plus:DI (match_dup 1) (match_dup 2)))]
9845 "TARGET_POWERPC64 && TARGET_UPDATE"
9846 "@
9847 stdux %3,%0,%2
9848 stdu %3,%2(%0)"
9849 [(set_attr "type" "store")])
9851 (define_insn "*movsi_update1"
9852 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9853 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9854 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9855 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9856 (plus:SI (match_dup 1) (match_dup 2)))]
9857 ""
9858 "@
9859 {lux|lwzux} %3,%0,%2
9860 {lu|lwzu} %3,%2(%0)"
9861 [(set_attr "type" "load")])
9863 (define_insn "movsi_update"
9864 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9865 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9866 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9867 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9868 (plus:SI (match_dup 1) (match_dup 2)))]
9869 "TARGET_UPDATE"
9870 "@
9871 {stux|stwux} %3,%0,%2
9872 {stu|stwu} %3,%2(%0)"
9873 [(set_attr "type" "store")])
9875 (define_insn "*movhi_update"
9876 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9877 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9878 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9879 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9880 (plus:SI (match_dup 1) (match_dup 2)))]
9881 "TARGET_UPDATE"
9882 "@
9883 lhzux %3,%0,%2
9884 lhzu %3,%2(%0)"
9885 [(set_attr "type" "load")])
9887 (define_insn "*movhi_update2"
9888 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9889 (zero_extend:SI
9890 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9891 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9892 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9893 (plus:SI (match_dup 1) (match_dup 2)))]
9894 "TARGET_UPDATE"
9895 "@
9896 lhzux %3,%0,%2
9897 lhzu %3,%2(%0)"
9898 [(set_attr "type" "load")])
9900 (define_insn "*movhi_update3"
9901 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9902 (sign_extend:SI
9903 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9904 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9905 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9906 (plus:SI (match_dup 1) (match_dup 2)))]
9907 "TARGET_UPDATE"
9908 "@
9909 lhaux %3,%0,%2
9910 lhau %3,%2(%0)"
9911 [(set_attr "type" "load")])
9913 (define_insn "*movhi_update4"
9914 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9915 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9916 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9917 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9918 (plus:SI (match_dup 1) (match_dup 2)))]
9919 "TARGET_UPDATE"
9920 "@
9921 sthux %3,%0,%2
9922 sthu %3,%2(%0)"
9923 [(set_attr "type" "store")])
9925 (define_insn "*movqi_update1"
9926 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
9927 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9928 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9929 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9930 (plus:SI (match_dup 1) (match_dup 2)))]
9931 "TARGET_UPDATE"
9932 "@
9933 lbzux %3,%0,%2
9934 lbzu %3,%2(%0)"
9935 [(set_attr "type" "load")])
9937 (define_insn "*movqi_update2"
9938 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9939 (zero_extend:SI
9940 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9941 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9942 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9943 (plus:SI (match_dup 1) (match_dup 2)))]
9944 "TARGET_UPDATE"
9945 "@
9946 lbzux %3,%0,%2
9947 lbzu %3,%2(%0)"
9948 [(set_attr "type" "load")])
9950 (define_insn "*movqi_update3"
9951 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9952 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9953 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
9954 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9955 (plus:SI (match_dup 1) (match_dup 2)))]
9956 "TARGET_UPDATE"
9957 "@
9958 stbux %3,%0,%2
9959 stbu %3,%2(%0)"
9960 [(set_attr "type" "store")])
9962 (define_insn "*movsf_update1"
9963 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
9964 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9965 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9966 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9967 (plus:SI (match_dup 1) (match_dup 2)))]
9968 "TARGET_HARD_FLOAT && TARGET_UPDATE"
9969 "@
9970 lfsux %3,%0,%2
9971 lfsu %3,%2(%0)"
9972 [(set_attr "type" "fpload")])
9974 (define_insn "*movsf_update2"
9975 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9976 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9977 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
9978 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9979 (plus:SI (match_dup 1) (match_dup 2)))]
9980 "TARGET_HARD_FLOAT && TARGET_UPDATE"
9981 "@
9982 stfsux %3,%0,%2
9983 stfsu %3,%2(%0)"
9984 [(set_attr "type" "fpstore")])
9986 (define_insn "*movsf_update3"
9987 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
9988 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9989 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9990 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9991 (plus:SI (match_dup 1) (match_dup 2)))]
9992 "TARGET_SOFT_FLOAT && TARGET_UPDATE"
9993 "@
9994 {lux|lwzux} %3,%0,%2
9995 {lu|lwzu} %3,%2(%0)"
9996 [(set_attr "type" "load")])
9998 (define_insn "*movsf_update4"
9999 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10000 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10001 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10002 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10003 (plus:SI (match_dup 1) (match_dup 2)))]
10004 "TARGET_SOFT_FLOAT && TARGET_UPDATE"
10005 "@
10006 {stux|stwux} %3,%0,%2
10007 {stu|stwu} %3,%2(%0)"
10008 [(set_attr "type" "store")])
10010 (define_insn "*movdf_update1"
10011 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
10012 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10013 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10014 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10015 (plus:SI (match_dup 1) (match_dup 2)))]
10016 "TARGET_HARD_FLOAT && TARGET_UPDATE"
10017 "@
10018 lfdux %3,%0,%2
10019 lfdu %3,%2(%0)"
10020 [(set_attr "type" "fpload")])
10022 (define_insn "*movdf_update2"
10023 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10024 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10025 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
10026 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10027 (plus:SI (match_dup 1) (match_dup 2)))]
10028 "TARGET_HARD_FLOAT && TARGET_UPDATE"
10029 "@
10030 stfdux %3,%0,%2
10031 stfdu %3,%2(%0)"
10032 [(set_attr "type" "fpstore")])
10034 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10036 (define_peephole
10037 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
10038 (match_operand:DF 1 "memory_operand" ""))
10039 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
10040 (match_operand:DF 3 "memory_operand" ""))]
10041 "TARGET_POWER2
10042 && TARGET_HARD_FLOAT
10043 && registers_ok_for_quad_peep (operands[0], operands[2])
10044 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
10045 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
10046 "lfq%U1%X1 %0,%1")
10048 (define_peephole
10049 [(set (match_operand:DF 0 "memory_operand" "")
10050 (match_operand:DF 1 "gpc_reg_operand" "f"))
10051 (set (match_operand:DF 2 "memory_operand" "")
10052 (match_operand:DF 3 "gpc_reg_operand" "f"))]
10053 "TARGET_POWER2
10054 && TARGET_HARD_FLOAT
10055 && registers_ok_for_quad_peep (operands[1], operands[3])
10056 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
10057 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
10058 "stfq%U0%X0 %1,%0")
10059 \f
10060 ;; Next come insns related to the calling sequence.
10061 ;;
10062 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10063 ;; We move the back-chain and decrement the stack pointer.
10065 (define_expand "allocate_stack"
10066 [(set (match_operand 0 "register_operand" "=r")
10067 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10068 (set (reg 1)
10069 (minus (reg 1) (match_dup 1)))]
10070 ""
10071 "
10072 { rtx chain = gen_reg_rtx (Pmode);
10073 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10074 rtx neg_op0;
10076 emit_move_insn (chain, stack_bot);
10078 /* Under Windows NT, we need to add stack probes for large/variable
10079 allocations, so do it via a call to the external function alloca
10080 instead of doing it inline. */
10081 if (DEFAULT_ABI == ABI_NT
10082 && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) > 4096))
10083 {
10084 rtx tmp = gen_reg_rtx (Pmode);
10085 emit_library_call_value (gen_rtx_SYMBOL_REF (Pmode, \"__allocate_stack\"),
10086 tmp, 0, Pmode, 1, operands[1], Pmode);
10087 emit_insn (gen_set_sp (tmp));
10088 emit_move_insn (operands[0], tmp);
10089 DONE;
10090 }
10092 if (GET_CODE (operands[1]) != CONST_INT
10093 || INTVAL (operands[1]) < -32767
10094 || INTVAL (operands[1]) > 32768)
10095 {
10096 neg_op0 = gen_reg_rtx (Pmode);
10097 if (TARGET_32BIT)
10098 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10099 else
10100 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10101 }
10102 else
10103 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10105 if (TARGET_UPDATE)
10106 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update))
10107 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
10109 else
10110 {
10111 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10112 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
10113 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
10114 }
10116 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10117 DONE;
10118 }")
10120 ;; Marker to indicate that the stack pointer was changed under NT in
10121 ;; ways not known to the compiler
10123 (define_insn "set_sp"
10124 [(set (reg:SI 1)
10125 (unspec [(match_operand:SI 0 "register_operand" "r")] 7))]
10126 ""
10127 ""
10128 [(set_attr "length" "0")])
10130 ;; These patterns say how to save and restore the stack pointer. We need not
10131 ;; save the stack pointer at function level since we are careful to
10132 ;; preserve the backchain. At block level, we have to restore the backchain
10133 ;; when we restore the stack pointer.
10134 ;;
10135 ;; For nonlocal gotos, we must save both the stack pointer and its
10136 ;; backchain and restore both. Note that in the nonlocal case, the
10137 ;; save area is a memory location.
10139 (define_expand "save_stack_function"
10140 [(match_operand 0 "any_operand" "")
10141 (match_operand 1 "any_operand" "")]
10142 ""
10143 "DONE;")
10145 (define_expand "restore_stack_function"
10146 [(match_operand 0 "any_operand" "")
10147 (match_operand 1 "any_operand" "")]
10148 ""
10149 "DONE;")
10151 (define_expand "restore_stack_block"
10152 [(use (match_operand 0 "register_operand" ""))
10153 (set (match_dup 2) (match_dup 3))
10154 (set (match_dup 0) (match_operand 1 "register_operand" ""))
10155 (set (match_dup 3) (match_dup 2))]
10156 ""
10157 "
10158 {
10159 operands[2] = gen_reg_rtx (Pmode);
10160 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
10161 }")
10163 (define_expand "save_stack_nonlocal"
10164 [(match_operand 0 "memory_operand" "")
10165 (match_operand 1 "register_operand" "")]
10166 ""
10167 "
10168 {
10169 rtx temp = gen_reg_rtx (Pmode);
10171 /* Copy the backchain to the first word, sp to the second. */
10172 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
10173 emit_move_insn (operand_subword (operands[0], 0, 0, (TARGET_32BIT ? DImode : TImode)),
10174 temp);
10175 emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)),
10176 operands[1]);
10177 DONE;
10178 }")
10180 (define_expand "restore_stack_nonlocal"
10181 [(match_operand 0 "register_operand" "")
10182 (match_operand 1 "memory_operand" "")]
10183 ""
10184 "
10185 {
10186 rtx temp = gen_reg_rtx (Pmode);
10188 /* Restore the backchain from the first word, sp from the second. */
10189 emit_move_insn (temp,
10190 operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode)));
10191 emit_move_insn (operands[0],
10192 operand_subword (operands[1], 1, 0, (TARGET_32BIT ? DImode : TImode)));
10193 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
10194 DONE;
10195 }")
10197 ;; If we have -mminimal-toc, we need to reload r30 after a nonlocal goto.
10199 (define_insn "nonlocal_goto_receiver"
10200 [(unspec_volatile [(const_int 0)] 1)]
10201 "TARGET_TOC && TARGET_MINIMAL_TOC"
10202 "*
10203 {
10204 rs6000_output_load_toc_table (asm_out_file, 30);
10205 return \"\";
10206 }"
10207 [(set_attr "type" "load")])
10208 \f
10209 ;; A function pointer under AIX is a pointer to a data area whose first word
10210 ;; contains the actual address of the function, whose second word contains a
10211 ;; pointer to its TOC, and whose third word contains a value to place in the
10212 ;; static chain register (r11). Note that if we load the static chain, our
10213 ;; "trampoline" need not have any executable code.
10214 ;;
10215 ;; operands[0] is a register pointing to the 3 word descriptor (aka, the function address)
10216 ;; operands[1] is the stack size to clean up
10217 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument (must be 0 for AIX)
10218 ;; operands[3] is location to store the TOC
10219 ;; operands[4] is the TOC register
10220 ;; operands[5] is the static chain register
10221 ;;
10222 ;; We do not break this into separate insns, so that the scheduler will not try
10223 ;; to move the load of the new TOC before any loads from the TOC.
10225 (define_insn "call_indirect_aix32"
10226 [(call (mem:SI (match_operand:SI 0 "register_operand" "b"))
10227 (match_operand 1 "const_int_operand" "n"))
10228 (use (match_operand 2 "const_int_operand" "n"))
10229 (use (match_operand 3 "offsettable_mem_operand" "o"))
10230 (use (match_operand 4 "register_operand" "r"))
10231 (clobber (match_operand 5 "register_operand" "=r"))
10232 (clobber (match_scratch:SI 6 "=&r"))
10233 (clobber (match_scratch:SI 7 "=l"))]
10234 "DEFAULT_ABI == ABI_AIX
10235 && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)"
10236 "{st|stw} %4,%3\;{l|lwz} %6,0(%0)\;{l|lwz} %4,4(%0)\;mt%7 %6\;{l|lwz} %5,8(%0)\;{brl|blrl}\;{l|lwz} %4,%3"
10237 [(set_attr "type" "load")
10238 (set_attr "length" "28")])
10240 (define_insn "call_indirect_aix64"
10241 [(call (mem:SI (match_operand:DI 0 "register_operand" "b"))
10242 (match_operand 1 "const_int_operand" "n"))
10243 (use (match_operand 2 "const_int_operand" "n"))
10244 (use (match_operand 3 "offsettable_mem_operand" "o"))
10245 (use (match_operand 4 "register_operand" "r"))
10246 (clobber (match_operand 5 "register_operand" "=r"))
10247 (clobber (match_scratch:SI 6 "=&r"))
10248 (clobber (match_scratch:SI 7 "=l"))]
10249 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX
10250 && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)"
10251 "std %4,%3\;ld %6,0(%0)\;ld %4,8(%0)\;mt%7 %6\;ld %5,16(%0)\;blrl\;ld %4,%3"
10252 [(set_attr "type" "load")
10253 (set_attr "length" "28")])
10255 (define_insn "call_value_indirect_aix32"
10256 [(set (match_operand 0 "register_operand" "fg")
10257 (call (mem:SI (match_operand:SI 1 "register_operand" "b"))
10258 (match_operand 2 "const_int_operand" "n")))
10259 (use (match_operand 3 "const_int_operand" "n"))
10260 (use (match_operand 4 "offsettable_mem_operand" "o"))
10261 (use (match_operand 5 "register_operand" "r"))
10262 (clobber (match_operand 6 "register_operand" "=r"))
10263 (clobber (match_scratch:SI 7 "=&r"))
10264 (clobber (match_scratch:SI 8 "=l"))]
10265 "DEFAULT_ABI == ABI_AIX
10266 && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)"
10267 "{st|stw} %5,%4\;{l|lwz} %7,0(%1)\;{l|lwz} %5,4(%1)\;mt%8 %7\;{l|lwz} %6,8(%1)\;{brl|blrl}\;{l|lwz} %5,%4"
10268 [(set_attr "type" "load")
10269 (set_attr "length" "28")])
10271 (define_insn "call_value_indirect_aix64"
10272 [(set (match_operand 0 "register_operand" "fg")
10273 (call (mem:SI (match_operand:DI 1 "register_operand" "b"))
10274 (match_operand 2 "const_int_operand" "n")))
10275 (use (match_operand 3 "const_int_operand" "n"))
10276 (use (match_operand 4 "offsettable_mem_operand" "o"))
10277 (use (match_operand 5 "register_operand" "r"))
10278 (clobber (match_operand 6 "register_operand" "=r"))
10279 (clobber (match_scratch:SI 7 "=&r"))
10280 (clobber (match_scratch:SI 8 "=l"))]
10281 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX
10282 && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)"
10283 "std %5,%4\;ld %7,0(%1)\;ld %5,8(%1)\;mt%8 %7\;ld %6,16(%1)\;blrl\;ld %5,%4"
10284 [(set_attr "type" "load")
10285 (set_attr "length" "28")])
10287 ;; A function pointer undef NT is a pointer to a data area whose first word
10288 ;; contains the actual address of the function, whose second word contains a
10289 ;; pointer to its TOC. The static chain is not stored under NT, which means
10290 ;; that we need a trampoline.
10291 ;;
10292 ;; operands[0] is an SImode pseudo in which we place the address of the function.
10293 ;; operands[1] is the stack size to clean up
10294 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument (must be 0 for NT)
10295 ;; operands[3] is location to store the TOC
10296 ;; operands[4] is the TOC register
10297 ;;
10298 ;; We do not break this into separate insns, so that the scheduler will not try
10299 ;; to move the load of the new TOC before any loads from the TOC.
10301 (define_insn "call_indirect_nt"
10302 [(call (mem:SI (match_operand:SI 0 "register_operand" "b"))
10303 (match_operand 1 "const_int_operand" "n"))
10304 (use (match_operand 2 "const_int_operand" "n"))
10305 (use (match_operand 3 "offsettable_mem_operand" "o"))
10306 (use (match_operand 4 "register_operand" "r"))
10307 (clobber (match_scratch:SI 5 "=&r"))
10308 (clobber (match_scratch:SI 6 "=l"))]
10309 "DEFAULT_ABI == ABI_NT
10310 && (INTVAL (operands[2]) == CALL_NORMAL || (INTVAL (operands[2]) & CALL_LONG) != 0)"
10311 "{st|stw} %4,%a3\;{l|lwz} %5,0(%0)\;{l|lwz} %4,4(%0)\;mt%6 %5\;{brl|blrl}\;{l|lwz} %4,%a3"
10312 [(set_attr "type" "load")
10313 (set_attr "length" "24")])
10315 (define_insn "call_value_indirect_nt"
10316 [(set (match_operand 0 "register_operand" "fg")
10317 (call (mem:SI (match_operand:SI 1 "register_operand" "b"))
10318 (match_operand 2 "const_int_operand" "n")))
10319 (use (match_operand 3 "const_int_operand" "n"))
10320 (use (match_operand 4 "offsettable_mem_operand" "o"))
10321 (use (match_operand 5 "register_operand" "r"))
10322 (clobber (match_scratch:SI 6 "=&r"))
10323 (clobber (match_scratch:SI 7 "=l"))]
10324 "DEFAULT_ABI == ABI_NT
10325 && (INTVAL (operands[3]) == CALL_NORMAL || (INTVAL (operands[3]) & CALL_LONG) != 0)"
10326 "{st|stw} %5,%a4\;{l|lwz} %6,0(%1)\;{l|lwz} %5,4(%1)\;mt%7 %6\;{brl|blrl}\;{l|lwz} %5,%a4"
10327 [(set_attr "type" "load")
10328 (set_attr "length" "24")])
10330 ;; A function pointer under System V is just a normal pointer
10331 ;; operands[0] is the function pointer
10332 ;; operands[1] is the stack size to clean up
10333 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument which indicates how to set cr1
10335 (define_insn "call_indirect_sysv"
10336 [(call (mem:SI (match_operand:SI 0 "register_operand" "l,l"))
10337 (match_operand 1 "const_int_operand" "n,n"))
10338 (use (match_operand 2 "const_int_operand" "O,n"))
10339 (clobber (match_scratch:SI 3 "=l,l"))]
10340 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC"
10341 "*
10342 {
10343 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10344 output_asm_insn (\"crxor 6,6,6\", operands);
10346 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10347 output_asm_insn (\"creqv 6,6,6\", operands);
10349 return \"{brl|blrl}\";
10350 }"
10351 [(set_attr "type" "jmpreg")
10352 (set_attr "length" "4,8")])
10354 (define_insn "call_value_indirect_sysv"
10355 [(set (match_operand 0 "register_operand" "=fg,fg")
10356 (call (mem:SI (match_operand:SI 1 "register_operand" "l,l"))
10357 (match_operand 2 "const_int_operand" "n,n")))
10358 (use (match_operand 3 "const_int_operand" "O,n"))
10359 (clobber (match_scratch:SI 4 "=l,l"))]
10360 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS || DEFAULT_ABI == ABI_AIX_NODESC"
10361 "*
10362 {
10363 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10364 output_asm_insn (\"crxor 6,6,6\", operands);
10366 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10367 output_asm_insn (\"creqv 6,6,6\", operands);
10369 return \"{brl|blrl}\";
10370 }"
10371 [(set_attr "type" "jmpreg")
10372 (set_attr "length" "4,8")])
10374 ;; Now the definitions for the call and call_value insns
10375 (define_expand "call"
10376 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10377 (match_operand 1 "" ""))
10378 (use (match_operand 2 "" ""))
10379 (clobber (scratch:SI))])]
10380 ""
10381 "
10382 {
10383 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10384 abort ();
10386 operands[0] = XEXP (operands[0], 0);
10388 /* Convert NT DLL imports into an indirect call. */
10389 if (GET_CODE (operands[0]) == SYMBOL_REF
10390 && (INTVAL (operands[2]) & CALL_NT_DLLIMPORT) != 0)
10391 {
10392 operands[0] = rs6000_dll_import_ref (operands[0]);
10393 operands[2] = GEN_INT ((int)CALL_NORMAL);
10394 }
10396 if (GET_CODE (operands[0]) != SYMBOL_REF
10397 || (INTVAL (operands[2]) & CALL_LONG) != 0)
10398 {
10399 if (INTVAL (operands[2]) & CALL_LONG)
10400 operands[0] = rs6000_longcall_ref (operands[0]);
10402 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS)
10403 emit_call_insn (gen_call_indirect_sysv (force_reg (Pmode, operands[0]),
10404 operands[1], operands[2]));
10405 else
10406 {
10407 rtx toc_reg = gen_rtx_REG (Pmode, 2);
10408 rtx toc_addr = RS6000_SAVE_TOC;
10410 if (DEFAULT_ABI == ABI_AIX)
10411 {
10412 /* AIX function pointers are really pointers to a three word area */
10413 rtx static_chain = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
10414 emit_call_insn (TARGET_32BIT
10415 ? gen_call_indirect_aix32 (force_reg (Pmode, operands[0]),
10416 operands[1], operands[2],
10417 toc_addr, toc_reg, static_chain)
10418 : gen_call_indirect_aix64 (force_reg (Pmode, operands[0]),
10419 operands[1], operands[2],
10420 toc_addr, toc_reg, static_chain));
10421 }
10422 else if (DEFAULT_ABI == ABI_NT)
10423 {
10424 /* NT function pointers are really pointers to a two word area */
10425 emit_call_insn (gen_call_indirect_nt (force_reg (Pmode, operands[0]),
10426 operands[1], operands[2],
10427 toc_addr, toc_reg));
10428 }
10429 else
10430 abort ();
10431 }
10432 DONE;
10433 }
10434 }")
10436 (define_expand "call_value"
10437 [(parallel [(set (match_operand 0 "" "")
10438 (call (mem:SI (match_operand 1 "address_operand" ""))
10439 (match_operand 2 "" "")))
10440 (use (match_operand 3 "" ""))
10441 (clobber (scratch:SI))])]
10442 ""
10443 "
10444 {
10445 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10446 abort ();
10448 operands[1] = XEXP (operands[1], 0);
10450 /* Convert NT DLL imports into an indirect call. */
10451 if (GET_CODE (operands[1]) == SYMBOL_REF
10452 && (INTVAL (operands[3]) & CALL_NT_DLLIMPORT) != 0)
10453 {
10454 operands[1] = rs6000_dll_import_ref (operands[1]);
10455 operands[3] = GEN_INT ((int)CALL_NORMAL);
10456 }
10458 if (GET_CODE (operands[1]) != SYMBOL_REF
10459 || (INTVAL (operands[3]) & CALL_LONG) != 0)
10460 {
10461 if (INTVAL (operands[2]) & CALL_LONG)
10462 operands[1] = rs6000_longcall_ref (operands[1]);
10464 if (DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_SOLARIS)
10465 emit_call_insn (gen_call_value_indirect_sysv (operands[0], operands[1],
10466 operands[2], operands[3]));
10467 else
10468 {
10469 rtx toc_reg = gen_rtx_REG (Pmode, 2);
10470 rtx toc_addr = RS6000_SAVE_TOC;
10472 if (DEFAULT_ABI == ABI_AIX)
10473 {
10474 /* AIX function pointers are really pointers to a three word area */
10475 rtx static_chain = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM);
10476 emit_call_insn (TARGET_32BIT
10477 ? gen_call_value_indirect_aix32 (operands[0],
10478 force_reg (Pmode, operands[1]),
10479 operands[2], operands[3],
10480 toc_addr, toc_reg, static_chain)
10481 : gen_call_value_indirect_aix64 (operands[0],
10482 force_reg (Pmode, operands[1]),
10483 operands[2], operands[3],
10484 toc_addr, toc_reg, static_chain));
10485 }
10486 else if (DEFAULT_ABI == ABI_NT)
10487 {
10488 /* NT function pointers are really pointers to a two word area */
10489 emit_call_insn (gen_call_value_indirect_nt (operands[0],
10490 force_reg (Pmode, operands[1]),
10491 operands[2], operands[3],
10492 toc_addr, toc_reg));
10493 }
10494 else
10495 abort ();
10496 }
10497 DONE;
10498 }
10499 }")
10501 ;; Call to function in current module. No TOC pointer reload needed.
10502 ;; Operand2 is non-zero if we are using the V.4 calling sequence and
10503 ;; either the function was not prototyped, or it was prototyped as a
10504 ;; variable argument function. It is > 0 if FP registers were passed
10505 ;; and < 0 if they were not.
10507 (define_insn "*call_local32"
10508 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10509 (match_operand 1 "" "g,g"))
10510 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10511 (clobber (match_scratch:SI 3 "=l,l"))]
10512 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10513 "*
10514 {
10515 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10516 output_asm_insn (\"crxor 6,6,6\", operands);
10518 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10519 output_asm_insn (\"creqv 6,6,6\", operands);
10521 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10522 }"
10523 [(set_attr "type" "branch")
10524 (set_attr "length" "4,8")])
10526 (define_insn "*call_local64"
10527 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10528 (match_operand 1 "" "g,g"))
10529 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10530 (clobber (match_scratch:SI 3 "=l,l"))]
10531 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10532 "*
10533 {
10534 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10535 output_asm_insn (\"crxor 6,6,6\", operands);
10537 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10538 output_asm_insn (\"creqv 6,6,6\", operands);
10540 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10541 }"
10542 [(set_attr "type" "branch")
10543 (set_attr "length" "4,8")])
10545 (define_insn "*ret_call_local32"
10546 [(set (match_operand 0 "" "=fg,fg")
10547 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10548 (match_operand 2 "" "g,g")))
10549 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10550 (clobber (match_scratch:SI 4 "=l,l"))]
10551 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10552 "*
10553 {
10554 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10555 output_asm_insn (\"crxor 6,6,6\", operands);
10557 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10558 output_asm_insn (\"creqv 6,6,6\", operands);
10560 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10561 }"
10562 [(set_attr "type" "branch")
10563 (set_attr "length" "4,8")])
10566 (define_insn "*ret_call_local64"
10567 [(set (match_operand 0 "" "=fg,fg")
10568 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10569 (match_operand 2 "" "g,g")))
10570 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10571 (clobber (match_scratch:SI 4 "=l,l"))]
10572 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10573 "*
10574 {
10575 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10576 output_asm_insn (\"crxor 6,6,6\", operands);
10578 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10579 output_asm_insn (\"creqv 6,6,6\", operands);
10581 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10582 }"
10583 [(set_attr "type" "branch")
10584 (set_attr "length" "4,8")])
10586 ;; Call to function which may be in another module. Restore the TOC
10587 ;; pointer (r2) after the call unless this is System V.
10588 ;; Operand2 is non-zero if we are using the V.4 calling sequence and
10589 ;; either the function was not prototyped, or it was prototyped as a
10590 ;; variable argument function. It is > 0 if FP registers were passed
10591 ;; and < 0 if they were not.
10593 (define_insn "*call_nonlocal_aix32"
10594 [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s"))
10595 (match_operand 1 "" "fg,fg"))
10596 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10597 (clobber (match_scratch:SI 3 "=l,l"))]
10598 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
10599 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10600 "*
10601 {
10602 /* Indirect calls should go through call_indirect */
10603 if (GET_CODE (operands[0]) == REG)
10604 abort ();
10606 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10607 output_asm_insn (\"crxor 6,6,6\", operands);
10609 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10610 output_asm_insn (\"creqv 6,6,6\", operands);
10612 return (TARGET_WINDOWS_NT) ? \"bl %z0\;.znop %z0\" : \"bl %z0\;%.\";
10613 }"
10614 [(set_attr "type" "branch")
10615 (set_attr "length" "8,12")])
10617 (define_insn "*call_nonlocal_aix64"
10618 [(call (mem:SI (match_operand:DI 0 "call_operand" "s,s"))
10619 (match_operand 1 "" "fg,fg"))
10620 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10621 (clobber (match_scratch:SI 3 "=l,l"))]
10622 "TARGET_64BIT && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
10623 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10624 "*
10625 {
10626 /* Indirect calls should go through call_indirect */
10627 if (GET_CODE (operands[0]) == REG)
10628 abort ();
10630 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10631 output_asm_insn (\"crxor 6,6,6\", operands);
10633 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10634 output_asm_insn (\"creqv 6,6,6\", operands);
10636 return (TARGET_WINDOWS_NT) ? \"bl %z0\;.znop %z0\" : \"bl %z0\;%.\";
10637 }"
10638 [(set_attr "type" "branch")
10639 (set_attr "length" "8,12")])
10641 (define_insn "*call_nonlocal_sysv"
10642 [(call (mem:SI (match_operand:SI 0 "call_operand" "s,s"))
10643 (match_operand 1 "" "fg,fg"))
10644 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10645 (clobber (match_scratch:SI 3 "=l,l"))]
10646 "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
10647 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10648 "*
10649 {
10650 /* Indirect calls should go through call_indirect */
10651 if (GET_CODE (operands[0]) == REG)
10652 abort ();
10654 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10655 output_asm_insn (\"crxor 6,6,6\", operands);
10657 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10658 output_asm_insn (\"creqv 6,6,6\", operands);
10660 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@plt\" : \"bl %z0\";
10661 }"
10662 [(set_attr "type" "branch")
10663 (set_attr "length" "4,8")])
10665 (define_insn "*ret_call_nonlocal_aix32"
10666 [(set (match_operand 0 "" "=fg,fg")
10667 (call (mem:SI (match_operand:SI 1 "call_operand" "s,s"))
10668 (match_operand 2 "" "fg,fg")))
10669 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10670 (clobber (match_scratch:SI 4 "=l,l"))]
10671 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
10672 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10673 "*
10674 {
10675 /* This should be handled by call_value_indirect */
10676 if (GET_CODE (operands[1]) == REG)
10677 abort ();
10679 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10680 output_asm_insn (\"crxor 6,6,6\", operands);
10682 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10683 output_asm_insn (\"creqv 6,6,6\", operands);
10685 return (TARGET_WINDOWS_NT) ? \"bl %z1\;.znop %z1\" : \"bl %z1\;%.\";
10686 }"
10687 [(set_attr "type" "branch")
10688 (set_attr "length" "8,12")])
10690 (define_insn "*ret_call_nonlocal_aix64"
10691 [(set (match_operand 0 "" "=fg,fg")
10692 (call (mem:SI (match_operand:DI 1 "call_operand" "s,s"))
10693 (match_operand 2 "" "fg,fg")))
10694 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10695 (clobber (match_scratch:SI 4 "=l,l"))]
10696 "TARGET_64BIT && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_NT)
10697 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10698 "*
10699 {
10700 /* This should be handled by call_value_indirect */
10701 if (GET_CODE (operands[1]) == REG)
10702 abort ();
10704 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10705 output_asm_insn (\"crxor 6,6,6\", operands);
10707 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10708 output_asm_insn (\"creqv 6,6,6\", operands);
10710 return (TARGET_WINDOWS_NT) ? \"bl %z1\;.znop %z1\" : \"bl %z1\;%.\";
10711 }"
10712 [(set_attr "type" "branch")
10713 (set_attr "length" "8,12")])
10715 (define_insn "*ret_call_nonlocal_sysv"
10716 [(set (match_operand 0 "" "=fg,fg")
10717 (call (mem:SI (match_operand:SI 1 "call_operand" "s,s"))
10718 (match_operand 2 "" "fg,fg")))
10719 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10720 (clobber (match_scratch:SI 4 "=l,l"))]
10721 "(DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS)
10722 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10723 "*
10724 {
10725 /* This should be handled by call_value_indirect */
10726 if (GET_CODE (operands[1]) == REG)
10727 abort ();
10729 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10730 output_asm_insn (\"crxor 6,6,6\", operands);
10732 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10733 output_asm_insn (\"creqv 6,6,6\", operands);
10735 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@plt\" : \"bl %z1\";
10736 }"
10737 [(set_attr "type" "branch")
10738 (set_attr "length" "4,8")])
10740 ;; Call subroutine returning any type.
10741 (define_expand "untyped_call"
10742 [(parallel [(call (match_operand 0 "" "")
10743 (const_int 0))
10744 (match_operand 1 "" "")
10745 (match_operand 2 "" "")])]
10746 ""
10747 "
10748 {
10749 int i;
10751 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx, const0_rtx));
10753 for (i = 0; i < XVECLEN (operands[2], 0); i++)
10754 {
10755 rtx set = XVECEXP (operands[2], 0, i);
10756 emit_move_insn (SET_DEST (set), SET_SRC (set));
10757 }
10759 /* The optimizer does not know that the call sets the function value
10760 registers we stored in the result block. We avoid problems by
10761 claiming that all hard registers are used and clobbered at this
10762 point. */
10763 emit_insn (gen_blockage ());
10765 DONE;
10766 }")
10768 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
10769 ;; all of memory. This blocks insns from being moved across this point.
10771 (define_insn "blockage"
10772 [(unspec_volatile [(const_int 0)] 0)]
10773 ""
10774 "")
10776 ;; V.4 specific code to initialize the PIC register
10778 (define_insn "init_v4_pic"
10779 [(set (match_operand:SI 0 "register_operand" "=l")
10780 (unspec [(const_int 0)] 7))]
10781 "DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_SOLARIS"
10782 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10783 [(set_attr "type" "branch")
10784 (set_attr "length" "4")])
10786 \f
10787 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
10788 ;; signed & unsigned, and one type of branch.
10789 ;;
10790 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
10791 ;; insns, and branches. We store the operands of compares until we see
10792 ;; how it is used.
10793 (define_expand "cmpsi"
10794 [(set (cc0)
10795 (compare (match_operand:SI 0 "gpc_reg_operand" "")
10796 (match_operand:SI 1 "reg_or_short_operand" "")))]
10797 ""
10798 "
10799 {
10800 /* Take care of the possibility that operands[1] might be negative but
10801 this might be a logical operation. That insn doesn't exist. */
10802 if (GET_CODE (operands[1]) == CONST_INT
10803 && INTVAL (operands[1]) < 0)
10804 operands[1] = force_reg (SImode, operands[1]);
10806 rs6000_compare_op0 = operands[0];
10807 rs6000_compare_op1 = operands[1];
10808 rs6000_compare_fp_p = 0;
10809 DONE;
10810 }")
10812 (define_expand "cmpdi"
10813 [(set (cc0)
10814 (compare (match_operand:DI 0 "gpc_reg_operand" "")
10815 (match_operand:DI 1 "reg_or_short_operand" "")))]
10816 "TARGET_POWERPC64"
10817 "
10818 {
10819 /* Take care of the possibility that operands[1] might be negative but
10820 this might be a logical operation. That insn doesn't exist. */
10821 if (GET_CODE (operands[1]) == CONST_INT
10822 && INTVAL (operands[1]) < 0)
10823 operands[1] = force_reg (DImode, operands[1]);
10825 rs6000_compare_op0 = operands[0];
10826 rs6000_compare_op1 = operands[1];
10827 rs6000_compare_fp_p = 0;
10828 DONE;
10829 }")
10831 (define_expand "cmpsf"
10832 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
10833 (match_operand:SF 1 "gpc_reg_operand" "")))]
10834 "TARGET_HARD_FLOAT"
10835 "
10836 {
10837 rs6000_compare_op0 = operands[0];
10838 rs6000_compare_op1 = operands[1];
10839 rs6000_compare_fp_p = 1;
10840 DONE;
10841 }")
10843 (define_expand "cmpdf"
10844 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
10845 (match_operand:DF 1 "gpc_reg_operand" "")))]
10846 "TARGET_HARD_FLOAT"
10847 "
10848 {
10849 rs6000_compare_op0 = operands[0];
10850 rs6000_compare_op1 = operands[1];
10851 rs6000_compare_fp_p = 1;
10852 DONE;
10853 }")
10855 (define_expand "beq"
10856 [(set (match_dup 2) (match_dup 1))
10857 (set (pc)
10858 (if_then_else (eq (match_dup 2)
10859 (const_int 0))
10860 (label_ref (match_operand 0 "" ""))
10861 (pc)))]
10862 ""
10863 "
10864 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
10865 operands[1] = gen_rtx_COMPARE (mode,
10866 rs6000_compare_op0, rs6000_compare_op1);
10867 operands[2] = gen_reg_rtx (mode);
10868 }")
10870 (define_expand "bne"
10871 [(set (match_dup 2) (match_dup 1))
10872 (set (pc)
10873 (if_then_else (ne (match_dup 2)
10874 (const_int 0))
10875 (label_ref (match_operand 0 "" ""))
10876 (pc)))]
10877 ""
10878 "
10879 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
10880 operands[1] = gen_rtx_COMPARE (mode,
10881 rs6000_compare_op0, rs6000_compare_op1);
10882 operands[2] = gen_reg_rtx (mode);
10883 }")
10885 (define_expand "blt"
10886 [(set (match_dup 2) (match_dup 1))
10887 (set (pc)
10888 (if_then_else (lt (match_dup 2)
10889 (const_int 0))
10890 (label_ref (match_operand 0 "" ""))
10891 (pc)))]
10892 ""
10893 "
10894 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
10895 operands[1] = gen_rtx_COMPARE (mode,
10896 rs6000_compare_op0, rs6000_compare_op1);
10897 operands[2] = gen_reg_rtx (mode);
10898 }")
10900 (define_expand "bgt"
10901 [(set (match_dup 2) (match_dup 1))
10902 (set (pc)
10903 (if_then_else (gt (match_dup 2)
10904 (const_int 0))
10905 (label_ref (match_operand 0 "" ""))
10906 (pc)))]
10907 ""
10908 "
10909 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
10910 operands[1] = gen_rtx_COMPARE (mode,
10911 rs6000_compare_op0, rs6000_compare_op1);
10912 operands[2] = gen_reg_rtx (mode);
10913 }")
10915 (define_expand "ble"
10916 [(set (match_dup 2) (match_dup 1))
10917 (set (pc)
10918 (if_then_else (le (match_dup 2)
10919 (const_int 0))
10920 (label_ref (match_operand 0 "" ""))
10921 (pc)))]
10922 ""
10923 "
10924 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
10925 operands[1] = gen_rtx_COMPARE (mode,
10926 rs6000_compare_op0, rs6000_compare_op1);
10927 operands[2] = gen_reg_rtx (mode);
10928 }")
10930 (define_expand "bge"
10931 [(set (match_dup 2) (match_dup 1))
10932 (set (pc)
10933 (if_then_else (ge (match_dup 2)
10934 (const_int 0))
10935 (label_ref (match_operand 0 "" ""))
10936 (pc)))]
10937 ""
10938 "
10939 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
10940 operands[1] = gen_rtx_COMPARE (mode,
10941 rs6000_compare_op0, rs6000_compare_op1);
10942 operands[2] = gen_reg_rtx (mode);
10943 }")
10945 (define_expand "bgtu"
10946 [(set (match_dup 2) (match_dup 1))
10947 (set (pc)
10948 (if_then_else (gtu (match_dup 2)
10949 (const_int 0))
10950 (label_ref (match_operand 0 "" ""))
10951 (pc)))]
10952 ""
10953 "
10954 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
10955 rs6000_compare_op0, rs6000_compare_op1);
10956 operands[2] = gen_reg_rtx (CCUNSmode);
10957 }")
10959 (define_expand "bltu"
10960 [(set (match_dup 2) (match_dup 1))
10961 (set (pc)
10962 (if_then_else (ltu (match_dup 2)
10963 (const_int 0))
10964 (label_ref (match_operand 0 "" ""))
10965 (pc)))]
10966 ""
10967 "
10968 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
10969 rs6000_compare_op0, rs6000_compare_op1);
10970 operands[2] = gen_reg_rtx (CCUNSmode);
10971 }")
10973 (define_expand "bgeu"
10974 [(set (match_dup 2) (match_dup 1))
10975 (set (pc)
10976 (if_then_else (geu (match_dup 2)
10977 (const_int 0))
10978 (label_ref (match_operand 0 "" ""))
10979 (pc)))]
10980 ""
10981 "
10982 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
10983 rs6000_compare_op0, rs6000_compare_op1);
10984 operands[2] = gen_reg_rtx (CCUNSmode);
10985 }")
10987 (define_expand "bleu"
10988 [(set (match_dup 2) (match_dup 1))
10989 (set (pc)
10990 (if_then_else (leu (match_dup 2)
10991 (const_int 0))
10992 (label_ref (match_operand 0 "" ""))
10993 (pc)))]
10994 ""
10995 "
10996 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
10997 rs6000_compare_op0, rs6000_compare_op1);
10998 operands[2] = gen_reg_rtx (CCUNSmode);
10999 }")
11001 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11002 ;; For SEQ, likewise, except that comparisons with zero should be done
11003 ;; with an scc insns. However, due to the order that combine see the
11004 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11005 ;; the cases we don't want to handle.
11006 (define_expand "seq"
11007 [(set (match_dup 2) (match_dup 1))
11008 (set (match_operand:SI 0 "gpc_reg_operand" "")
11009 (eq:SI (match_dup 2) (const_int 0)))]
11010 ""
11011 "
11012 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
11013 operands[1] = gen_rtx_COMPARE (mode,
11014 rs6000_compare_op0, rs6000_compare_op1);
11015 operands[2] = gen_reg_rtx (mode);
11016 }")
11018 (define_expand "sne"
11019 [(set (match_dup 2) (match_dup 1))
11020 (set (match_operand:SI 0 "gpc_reg_operand" "")
11021 (ne:SI (match_dup 2) (const_int 0)))]
11022 ""
11023 "
11024 { if (! rs6000_compare_fp_p)
11025 FAIL;
11027 operands[1] = gen_rtx_COMPARE (CCFPmode,
11028 rs6000_compare_op0, rs6000_compare_op1);
11029 operands[2] = gen_reg_rtx (CCFPmode);
11030 }")
11032 ;; A > 0 is best done using the portable sequence, so fail in that case.
11033 (define_expand "sgt"
11034 [(set (match_dup 2) (match_dup 1))
11035 (set (match_operand:SI 0 "gpc_reg_operand" "")
11036 (gt:SI (match_dup 2) (const_int 0)))]
11037 ""
11038 "
11039 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
11041 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11042 FAIL;
11044 operands[1] = gen_rtx_COMPARE (mode,
11045 rs6000_compare_op0, rs6000_compare_op1);
11046 operands[2] = gen_reg_rtx (mode);
11047 }")
11049 ;; A < 0 is best done in the portable way for A an integer.
11050 (define_expand "slt"
11051 [(set (match_dup 2) (match_dup 1))
11052 (set (match_operand:SI 0 "gpc_reg_operand" "")
11053 (lt:SI (match_dup 2) (const_int 0)))]
11054 ""
11055 "
11056 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
11058 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11059 FAIL;
11061 operands[1] = gen_rtx_COMPARE (mode,
11062 rs6000_compare_op0, rs6000_compare_op1);
11063 operands[2] = gen_reg_rtx (mode);
11064 }")
11066 (define_expand "sge"
11067 [(set (match_dup 2) (match_dup 1))
11068 (set (match_operand:SI 0 "gpc_reg_operand" "")
11069 (ge:SI (match_dup 2) (const_int 0)))]
11070 ""
11071 "
11072 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
11073 operands[1] = gen_rtx_COMPARE (mode,
11074 rs6000_compare_op0, rs6000_compare_op1);
11075 operands[2] = gen_reg_rtx (mode);
11076 }")
11078 ;; A <= 0 is best done the portable way for A an integer.
11079 (define_expand "sle"
11080 [(set (match_dup 2) (match_dup 1))
11081 (set (match_operand:SI 0 "gpc_reg_operand" "")
11082 (le:SI (match_dup 2) (const_int 0)))]
11083 ""
11084 "
11085 { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
11087 if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
11088 FAIL;
11090 operands[1] = gen_rtx_COMPARE (mode,
11091 rs6000_compare_op0, rs6000_compare_op1);
11092 operands[2] = gen_reg_rtx (mode);
11093 }")
11095 (define_expand "sgtu"
11096 [(set (match_dup 2) (match_dup 1))
11097 (set (match_operand:SI 0 "gpc_reg_operand" "")
11098 (gtu:SI (match_dup 2) (const_int 0)))]
11099 ""
11100 "
11101 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
11102 rs6000_compare_op0, rs6000_compare_op1);
11103 operands[2] = gen_reg_rtx (CCUNSmode);
11104 }")
11106 (define_expand "sltu"
11107 [(set (match_dup 2) (match_dup 1))
11108 (set (match_operand:SI 0 "gpc_reg_operand" "")
11109 (ltu:SI (match_dup 2) (const_int 0)))]
11110 ""
11111 "
11112 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
11113 rs6000_compare_op0, rs6000_compare_op1);
11114 operands[2] = gen_reg_rtx (CCUNSmode);
11115 }")
11117 (define_expand "sgeu"
11118 [(set (match_dup 2) (match_dup 1))
11119 (set (match_operand:SI 0 "gpc_reg_operand" "")
11120 (geu:SI (match_dup 2) (const_int 0)))]
11121 ""
11122 "
11123 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
11124 rs6000_compare_op0, rs6000_compare_op1);
11125 operands[2] = gen_reg_rtx (CCUNSmode);
11126 }")
11128 (define_expand "sleu"
11129 [(set (match_dup 2) (match_dup 1))
11130 (set (match_operand:SI 0 "gpc_reg_operand" "")
11131 (leu:SI (match_dup 2) (const_int 0)))]
11132 ""
11133 "
11134 { operands[1] = gen_rtx_COMPARE (CCUNSmode,
11135 rs6000_compare_op0, rs6000_compare_op1);
11136 operands[2] = gen_reg_rtx (CCUNSmode);
11137 }")
11138 \f
11139 ;; Here are the actual compare insns.
11140 (define_insn ""
11141 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11142 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11143 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11144 ""
11145 "{cmp%I2|cmpw%I2} %0,%1,%2"
11146 [(set_attr "type" "compare")])
11148 (define_insn ""
11149 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11150 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
11151 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11152 "TARGET_POWERPC64"
11153 "cmpd%I2 %0,%1,%2"
11154 [(set_attr "type" "compare")])
11156 ;; If we are comparing a register for equality with a large constant,
11157 ;; we can do this with an XOR followed by a compare. But we need a scratch
11158 ;; register for the result of the XOR.
11160 (define_split
11161 [(set (match_operand:CC 0 "cc_reg_operand" "")
11162 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11163 (match_operand:SI 2 "non_short_cint_operand" "")))
11164 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
11165 "find_single_use (operands[0], insn, 0)
11166 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
11167 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
11168 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
11169 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
11170 "
11171 {
11172 /* Get the constant we are comparing against, C, and see what it looks like
11173 sign-extended to 16 bits. Then see what constant could be XOR'ed
11174 with C to get the sign-extended value. */
11176 int c = INTVAL (operands[2]);
11177 int sextc = (c << 16) >> 16;
11178 int xorv = c ^ sextc;
11180 operands[4] = GEN_INT (xorv);
11181 operands[5] = GEN_INT (sextc);
11182 }")
11184 (define_insn ""
11185 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11186 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11187 (match_operand:SI 2 "reg_or_u_short_operand" "rI")))]
11188 ""
11189 "{cmpl%I2|cmplw%I2} %0,%1,%W2"
11190 [(set_attr "type" "compare")])
11192 (define_insn ""
11193 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11194 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11195 (match_operand:DI 2 "reg_or_u_short_operand" "rI")))]
11196 ""
11197 "cmpld%I2 %0,%1,%W2"
11198 [(set_attr "type" "compare")])
11200 ;; The following two insns don't exist as single insns, but if we provide
11201 ;; them, we can swap an add and compare, which will enable us to overlap more
11202 ;; of the required delay between a compare and branch. We generate code for
11203 ;; them by splitting.
11205 (define_insn ""
11206 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11207 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11208 (match_operand:SI 2 "short_cint_operand" "i")))
11209 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11210 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11211 ""
11212 "#"
11213 [(set_attr "length" "8")])
11215 (define_insn ""
11216 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11217 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11218 (match_operand:SI 2 "u_short_cint_operand" "i")))
11219 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11220 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11221 ""
11222 "#"
11223 [(set_attr "length" "8")])
11225 (define_split
11226 [(set (match_operand:CC 3 "cc_reg_operand" "")
11227 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11228 (match_operand:SI 2 "short_cint_operand" "")))
11229 (set (match_operand:SI 0 "gpc_reg_operand" "")
11230 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11231 ""
11232 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11233 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11235 (define_split
11236 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11237 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11238 (match_operand:SI 2 "u_short_cint_operand" "")))
11239 (set (match_operand:SI 0 "gpc_reg_operand" "")
11240 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11241 ""
11242 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11243 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11245 (define_insn ""
11246 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11247 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11248 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11249 "TARGET_HARD_FLOAT"
11250 "fcmpu %0,%1,%2"
11251 [(set_attr "type" "fpcompare")])
11253 (define_insn ""
11254 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11255 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11256 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11257 "TARGET_HARD_FLOAT"
11258 "fcmpu %0,%1,%2"
11259 [(set_attr "type" "fpcompare")])
11260 \f
11261 ;; Now we have the scc insns. We can do some combinations because of the
11262 ;; way the machine works.
11263 ;;
11264 ;; Note that this is probably faster if we can put an insn between the
11265 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11266 ;; cases the insns below which don't use an intermediate CR field will
11267 ;; be used instead.
11268 (define_insn ""
11269 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11270 (match_operator:SI 1 "scc_comparison_operator"
11271 [(match_operand 2 "cc_reg_operand" "y")
11272 (const_int 0)]))]
11273 ""
11274 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
11275 [(set_attr "length" "12")])
11277 (define_insn ""
11278 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
11279 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11280 [(match_operand 2 "cc_reg_operand" "y")
11281 (const_int 0)])
11282 (const_int 0)))
11283 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11284 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11285 ""
11286 "%D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1"
11287 [(set_attr "type" "delayed_compare")
11288 (set_attr "length" "12")])
11290 (define_insn ""
11291 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11292 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11293 [(match_operand 2 "cc_reg_operand" "y")
11294 (const_int 0)])
11295 (match_operand:SI 3 "const_int_operand" "n")))]
11296 ""
11297 "*
11298 {
11299 int is_bit = ccr_bit (operands[1], 1);
11300 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11301 int count;
11303 if (is_bit >= put_bit)
11304 count = is_bit - put_bit;
11305 else
11306 count = 32 - (put_bit - is_bit);
11308 operands[4] = GEN_INT (count);
11309 operands[5] = GEN_INT (put_bit);
11311 return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11312 }"
11313 [(set_attr "length" "12")])
11315 (define_insn ""
11316 [(set (match_operand:CC 0 "cc_reg_operand" "=x")
11317 (compare:CC
11318 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11319 [(match_operand 2 "cc_reg_operand" "y")
11320 (const_int 0)])
11321 (match_operand:SI 3 "const_int_operand" "n"))
11322 (const_int 0)))
11323 (set (match_operand:SI 4 "gpc_reg_operand" "=r")
11324 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11325 (match_dup 3)))]
11326 ""
11327 "*
11328 {
11329 int is_bit = ccr_bit (operands[1], 1);
11330 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11331 int count;
11333 if (is_bit >= put_bit)
11334 count = is_bit - put_bit;
11335 else
11336 count = 32 - (put_bit - is_bit);
11338 operands[5] = GEN_INT (count);
11339 operands[6] = GEN_INT (put_bit);
11341 return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11342 }"
11343 [(set_attr "type" "delayed_compare")
11344 (set_attr "length" "12")])
11346 ;; If we are comparing the result of two comparisons, this can be done
11347 ;; using creqv or crxor.
11349 (define_insn ""
11350 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
11351 (compare:CCEQ (match_operator 1 "scc_comparison_operator"
11352 [(match_operand 2 "cc_reg_operand" "y")
11353 (const_int 0)])
11354 (match_operator 3 "scc_comparison_operator"
11355 [(match_operand 4 "cc_reg_operand" "y")
11356 (const_int 0)])))]
11357 "REGNO (operands[2]) != REGNO (operands[4])"
11358 "*
11359 {
11360 enum rtx_code code1, code2;
11362 code1 = GET_CODE (operands[1]);
11363 code2 = GET_CODE (operands[3]);
11365 if ((code1 == EQ || code1 == LT || code1 == GT
11366 || code1 == LTU || code1 == GTU
11367 || (code1 != NE && GET_MODE (operands[2]) == CCFPmode))
11368 !=
11369 (code2 == EQ || code2 == LT || code2 == GT
11370 || code2 == LTU || code2 == GTU
11371 || (code2 != NE && GET_MODE (operands[4]) == CCFPmode)))
11372 return \"%C1%C3crxor %E0,%j1,%j3\";
11373 else
11374 return \"%C1%C3creqv %E0,%j1,%j3\";
11375 }"
11376 [(set_attr "length" "12")])
11378 ;; There is a 3 cycle delay between consecutive mfcr instructions
11379 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11381 (define_peephole
11382 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11383 (match_operator:SI 1 "scc_comparison_operator"
11384 [(match_operand 2 "cc_reg_operand" "y")
11385 (const_int 0)]))
11386 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11387 (match_operator:SI 4 "scc_comparison_operator"
11388 [(match_operand 5 "cc_reg_operand" "y")
11389 (const_int 0)]))]
11390 "REGNO (operands[2]) != REGNO (operands[5])"
11391 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11392 [(set_attr "length" "20")])
11394 ;; There are some scc insns that can be done directly, without a compare.
11395 ;; These are faster because they don't involve the communications between
11396 ;; the FXU and branch units. In fact, we will be replacing all of the
11397 ;; integer scc insns here or in the portable methods in emit_store_flag.
11398 ;;
11399 ;; Also support (neg (scc ..)) since that construct is used to replace
11400 ;; branches, (plus (scc ..) ..) since that construct is common and
11401 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11402 ;; cases where it is no more expensive than (neg (scc ..)).
11404 ;; Have reload force a constant into a register for the simple insns that
11405 ;; otherwise won't accept constants. We do this because it is faster than
11406 ;; the cmp/mfcr sequence we would otherwise generate.
11408 (define_insn ""
11409 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11410 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11411 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")))
11412 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11413 ""
11414 "@
11415 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11416 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11417 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11418 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11419 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11420 [(set_attr "length" "12,8,12,12,12")])
11422 (define_insn ""
11423 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
11424 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
11425 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
11426 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
11427 "TARGET_POWERPC64"
11428 "@
11429 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
11430 subfic %3,%1,0\;adde %0,%3,%1
11431 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
11432 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
11433 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
11434 [(set_attr "length" "12,8,12,12,12")])
11436 (define_insn ""
11437 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11438 (compare:CC
11439 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11440 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
11441 (const_int 0)))
11442 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11443 (eq:SI (match_dup 1) (match_dup 2)))
11444 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11445 ""
11446 "@
11447 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11448 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
11449 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11450 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11451 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11452 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11453 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1\;cmpli %4,%0,0
11454 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0\;cmpli %4,%0,0
11455 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0\;cmpli %4,%0,0
11456 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0\;cmpli %4,%0,0"
11457 [(set_attr "type" "compare")
11458 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11460 (define_insn ""
11461 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11462 (compare:CC
11463 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11464 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
11465 (const_int 0)))
11466 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11467 (eq:DI (match_dup 1) (match_dup 2)))
11468 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11469 "TARGET_POWERPC64"
11470 "@
11471 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11472 subfic %3,%1,0\;adde. %0,%3,%1
11473 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
11474 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
11475 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11476 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11477 subfic %3,%1,0\;adde %0,%3,%1\;cmpli %4,%0,0
11478 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0\;cmpli %4,%0,0
11479 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0\;cmpli %4,%0,0
11480 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0\;cmpli %4,%0,0"
11481 [(set_attr "type" "compare")
11482 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11484 ;; We have insns of the form shown by the first define_insn below. If
11485 ;; there is something inside the comparison operation, we must split it.
11486 (define_split
11487 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11488 (plus:SI (match_operator 1 "comparison_operator"
11489 [(match_operand:SI 2 "" "")
11490 (match_operand:SI 3
11491 "reg_or_cint_operand" "")])
11492 (match_operand:SI 4 "gpc_reg_operand" "")))
11493 (clobber (match_operand:SI 5 "register_operand" ""))]
11494 "! gpc_reg_operand (operands[2], SImode)"
11495 [(set (match_dup 5) (match_dup 2))
11496 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11497 (match_dup 4)))])
11499 (define_insn ""
11500 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11501 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11502 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
11503 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))
11504 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
11505 ""
11506 "@
11507 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
11508 {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3
11509 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
11510 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
11511 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
11512 [(set_attr "length" "12,8,12,12,12")])
11514 (define_insn ""
11515 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11516 (compare:CC
11517 (plus:SI
11518 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11519 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
11520 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11521 (const_int 0)))
11522 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11523 ""
11524 "@
11525 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11526 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11527 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11528 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11529 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11530 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3\;cmpli %0,%4,0
11531 {sfi|subfic} %4,%1,0\;{aze|addze} %0,%3\;cmpli %0,%4,0
11532 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze|addze} %4,%3\;cmpli %0,%4,0
11533 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze|addze} %4,%3\;cmpli %0,%4,0
11534 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %4,%3\;cmpli %0,%4,0"
11535 [(set_attr "type" "compare")
11536 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11538 (define_insn ""
11539 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11540 (compare:CC
11541 (plus:SI
11542 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11543 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
11544 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
11545 (const_int 0)))
11546 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11547 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11548 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
11549 ""
11550 "@
11551 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
11552 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
11553 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
11554 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
11555 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
11556 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3\;cmpli %5,%0,0
11557 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3\;cmpli %5,%0,0
11558 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3\;cmpli %5,%0,0
11559 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3\;cmpli %5,%0,0
11560 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3\;cmpli %5,%0,0"
11561 [(set_attr "type" "compare")
11562 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11564 (define_insn ""
11565 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11566 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11567 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
11568 ""
11569 "@
11570 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11571 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
11572 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11573 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11574 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
11575 [(set_attr "length" "12,8,12,12,12")])
11577 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
11578 ;; since it nabs/sr is just as fast.
11579 (define_insn "*ne0"
11580 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
11581 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11582 (const_int 31)))
11583 (clobber (match_scratch:SI 2 "=&r"))]
11584 "!TARGET_POWER"
11585 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
11586 [(set_attr "length" "8")])
11588 (define_insn ""
11589 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11590 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11591 (const_int 63)))
11592 (clobber (match_scratch:DI 2 "=&r"))]
11593 "TARGET_POWERPC64"
11594 "addic %2,%1,-1\;subfe %0,%2,%1"
11595 [(set_attr "length" "8")])
11597 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
11598 (define_insn ""
11599 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11600 (plus:SI (lshiftrt:SI
11601 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
11602 (const_int 31))
11603 (match_operand:SI 2 "gpc_reg_operand" "r")))
11604 (clobber (match_scratch:SI 3 "=&r"))]
11605 ""
11606 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
11607 [(set_attr "length" "8")])
11609 (define_insn ""
11610 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11611 (plus:DI (lshiftrt:DI
11612 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
11613 (const_int 63))
11614 (match_operand:DI 2 "gpc_reg_operand" "r")))
11615 (clobber (match_scratch:DI 3 "=&r"))]
11616 "TARGET_POWERPC64"
11617 "addic %3,%1,-1\;addze %0,%2"
11618 [(set_attr "length" "8")])
11620 (define_insn ""
11621 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11622 (compare:CC
11623 (plus:SI (lshiftrt:SI
11624 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11625 (const_int 31))
11626 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11627 (const_int 0)))
11628 (clobber (match_scratch:SI 3 "=&r,&r"))]
11629 ""
11630 "@
11631 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
11632 {ai|addic} %3,%1,-1\;{aze|addze} %3,%2\;cmpli %0,%3,0"
11633 [(set_attr "type" "compare")
11634 (set_attr "length" "8,12")])
11636 (define_insn ""
11637 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11638 (compare:CC
11639 (plus:DI (lshiftrt:DI
11640 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11641 (const_int 63))
11642 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11643 (const_int 0)))
11644 (clobber (match_scratch:DI 3 "=&r,&r"))]
11645 "TARGET_POWERPC64"
11646 "@
11647 addic %3,%1,-1\;addze. %3,%2
11648 addic %3,%1,-1\;addze. %3,%2\;cmpdi %0,%3,0"
11649 [(set_attr "type" "compare")
11650 (set_attr "length" "8,12")])
11652 (define_insn ""
11653 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11654 (compare:CC
11655 (plus:SI (lshiftrt:SI
11656 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
11657 (const_int 31))
11658 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
11659 (const_int 0)))
11660 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11661 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
11662 (match_dup 2)))
11663 (clobber (match_scratch:SI 3 "=&r,&r"))]
11664 ""
11665 "@
11666 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
11667 {ai|addic} %3,%1,-1\;{aze|addze} %0,%2\;cmpli %4,%0,0"
11668 [(set_attr "type" "compare")
11669 (set_attr "length" "8,12")])
11671 (define_insn ""
11672 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
11673 (compare:CC
11674 (plus:DI (lshiftrt:DI
11675 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
11676 (const_int 63))
11677 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
11678 (const_int 0)))
11679 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
11680 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
11681 (match_dup 2)))
11682 (clobber (match_scratch:DI 3 "=&r,&r"))]
11683 "TARGET_POWERPC64"
11684 "@
11685 addic %3,%1,-1\;addze. %0,%2
11686 addic %3,%1,-1\;addze. %0,%2\;cmpdi %4,%0,0"
11687 [(set_attr "type" "compare")
11688 (set_attr "length" "8,12")])
11690 (define_insn ""
11691 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11692 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11693 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
11694 (clobber (match_scratch:SI 3 "=r,X"))]
11695 "TARGET_POWER"
11696 "@
11697 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
11698 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
11699 [(set_attr "length" "12")])
11701 (define_insn ""
11702 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
11703 (compare:CC
11704 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11705 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11706 (const_int 0)))
11707 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11708 (le:SI (match_dup 1) (match_dup 2)))
11709 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
11710 "TARGET_POWER"
11711 "@
11712 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
11713 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
11714 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3\;cmpli %4,%0,0
11715 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31\;cmpli %4,%0,0"
11716 [(set_attr "type" "compare,delayed_compare,compare,compare")
11717 (set_attr "length" "12,12,16,16")])
11719 (define_insn ""
11720 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11721 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11722 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
11723 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
11724 (clobber (match_scratch:SI 4 "=&r,&r"))]
11725 "TARGET_POWER"
11726 "@
11727 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3
11728 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze|addze} %0,%3"
11729 [(set_attr "length" "12")])
11731 (define_insn ""
11732 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
11733 (compare:CC
11734 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11735 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11736 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11737 (const_int 0)))
11738 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11739 "TARGET_POWER"
11740 "@
11741 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
11742 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
11743 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %4,%3\;cmpli %0,%4,0
11744 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3\;cmpli %0,%4,0"
11745 [(set_attr "type" "compare")
11746 (set_attr "length" "12,12,16,16")])
11748 (define_insn ""
11749 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
11750 (compare:CC
11751 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11752 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
11753 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
11754 (const_int 0)))
11755 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11756 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11757 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
11758 "TARGET_POWER"
11759 "@
11760 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
11761 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3
11762 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3\;cmpli %5,%0,0
11763 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %0,%3\;cmpli %5,%0,0"
11764 [(set_attr "type" "compare")
11765 (set_attr "length" "12,12,16,16")])
11767 (define_insn ""
11768 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11769 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11770 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
11771 "TARGET_POWER"
11772 "@
11773 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
11774 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
11775 [(set_attr "length" "12")])
11777 (define_insn ""
11778 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11779 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11780 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11781 ""
11782 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
11783 [(set_attr "length" "12")])
11785 (define_insn ""
11786 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11787 (compare:CC
11788 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11789 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11790 (const_int 0)))
11791 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11792 (leu:SI (match_dup 1) (match_dup 2)))]
11793 ""
11794 "@
11795 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
11796 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0\;cmpli %3,%0,0"
11797 [(set_attr "type" "compare")
11798 (set_attr "length" "12,16")])
11800 (define_insn ""
11801 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11802 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11803 (match_operand:SI 2 "reg_or_short_operand" "rI"))
11804 (match_operand:SI 3 "gpc_reg_operand" "r")))
11805 (clobber (match_scratch:SI 4 "=&r"))]
11806 ""
11807 "{sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3"
11808 [(set_attr "length" "8")])
11810 (define_insn ""
11811 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11812 (compare:CC
11813 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11814 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11815 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11816 (const_int 0)))
11817 (clobber (match_scratch:SI 4 "=&r,&r"))]
11818 ""
11819 "@
11820 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
11821 {sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %4,%3\;cmpli %0,%4,0"
11822 [(set_attr "type" "compare")
11823 (set_attr "length" "8,12")])
11825 (define_insn ""
11826 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
11827 (compare:CC
11828 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11829 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11830 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11831 (const_int 0)))
11832 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11833 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11834 (clobber (match_scratch:SI 4 "=&r,&r"))]
11835 ""
11836 "@
11837 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %0,%3
11838 {sf%I2|subf%I2c} %4,%1,%2\;{aze|addze} %0,%3\;cmpli %5,%0,0"
11839 [(set_attr "type" "compare")
11840 (set_attr "length" "8,12")])
11842 (define_insn ""
11843 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11844 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11845 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
11846 ""
11847 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
11848 [(set_attr "length" "12")])
11850 (define_insn ""
11851 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11852 (and:SI (neg:SI
11853 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11854 (match_operand:SI 2 "reg_or_short_operand" "rI")))
11855 (match_operand:SI 3 "gpc_reg_operand" "r")))
11856 (clobber (match_scratch:SI 4 "=&r"))]
11857 ""
11858 "{sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
11859 [(set_attr "length" "12")])
11861 (define_insn ""
11862 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11863 (compare:CC
11864 (and:SI (neg:SI
11865 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11866 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
11867 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11868 (const_int 0)))
11869 (clobber (match_scratch:SI 4 "=&r,&r"))]
11870 ""
11871 "@
11872 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
11873 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %4,%3,%4\;cmpli %0,%4,0"
11874 [(set_attr "type" "compare")
11875 (set_attr "length" "12,16")])
11877 (define_insn ""
11878 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
11879 (compare:CC
11880 (and:SI (neg:SI
11881 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11882 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
11883 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11884 (const_int 0)))
11885 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11886 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
11887 (clobber (match_scratch:SI 4 "=&r,&r"))]
11888 ""
11889 "@
11890 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
11891 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4\;cmpli %5,%0,0"
11892 [(set_attr "type" "compare")
11893 (set_attr "length" "12,16")])
11895 (define_insn ""
11896 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11897 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11898 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11899 "TARGET_POWER"
11900 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
11901 [(set_attr "length" "12")])
11903 (define_insn ""
11904 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
11905 (compare:CC
11906 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11907 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11908 (const_int 0)))
11909 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11910 (lt:SI (match_dup 1) (match_dup 2)))]
11911 "TARGET_POWER"
11912 "@
11913 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
11914 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31\;cmpli %3,%0,0"
11915 [(set_attr "type" "delayed_compare,compare")
11916 (set_attr "length" "12,16")])
11918 (define_insn ""
11919 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11920 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11921 (match_operand:SI 2 "reg_or_short_operand" "rI"))
11922 (match_operand:SI 3 "gpc_reg_operand" "r")))
11923 (clobber (match_scratch:SI 4 "=&r"))]
11924 "TARGET_POWER"
11925 "doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
11926 [(set_attr "length" "12")])
11928 (define_insn ""
11929 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11930 (compare:CC
11931 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11932 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11933 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11934 (const_int 0)))
11935 (clobber (match_scratch:SI 4 "=&r,&r"))]
11936 "TARGET_POWER"
11937 "@
11938 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
11939 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %4,%3\;cmpli %0,%4,0"
11940 [(set_attr "type" "compare")
11941 (set_attr "length" "12,16")])
11943 (define_insn ""
11944 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
11945 (compare:CC
11946 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11947 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
11948 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
11949 (const_int 0)))
11950 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11951 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
11952 (clobber (match_scratch:SI 4 "=&r,&r"))]
11953 "TARGET_POWER"
11954 "@
11955 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3
11956 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3\;cmpli %5,%0,0"
11957 [(set_attr "type" "compare")
11958 (set_attr "length" "12,16")])
11960 (define_insn ""
11961 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11962 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11963 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
11964 "TARGET_POWER"
11965 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
11966 [(set_attr "length" "12")])
11968 (define_insn ""
11969 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11970 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
11971 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
11972 ""
11973 "@
11974 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
11975 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
11976 [(set_attr "length" "12")])
11978 (define_insn ""
11979 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
11980 (compare:CC
11981 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11982 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
11983 (const_int 0)))
11984 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11985 (ltu:SI (match_dup 1) (match_dup 2)))]
11986 ""
11987 "@
11988 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
11989 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
11990 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0\;cmpli %3,%0,0
11991 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0\;cmpli %3,%0,0"
11992 [(set_attr "type" "compare")
11993 (set_attr "length" "12,12,16,16")])
11995 (define_insn ""
11996 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
11997 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
11998 (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
11999 (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))
12000 (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
12001 ""
12002 "@
12003 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
12004 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
12005 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
12006 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
12007 [(set_attr "length" "12")])
12009 (define_insn ""
12010 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12011 (compare:CC
12012 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12013 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12014 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12015 (const_int 0)))
12016 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12017 ""
12018 "@
12019 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12020 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12021 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf|subfc} %4,%4,%3\;cmpli %0,%4,0
12022 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf|subfc} %4,%4,%3\;cmpli %0,%4,0"
12023 [(set_attr "type" "compare")
12024 (set_attr "length" "12,12,16,16")])
12026 (define_insn ""
12027 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
12028 (compare:CC
12029 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12030 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12031 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12032 (const_int 0)))
12033 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12034 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12035 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12036 ""
12037 "@
12038 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
12039 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
12040 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf|subfc} %0,%4,%3\;cmpli %5,%0,0
12041 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf|subfc} %0,%4,%3\;cmpli %5,%0,0"
12042 [(set_attr "type" "compare")
12043 (set_attr "length" "12,12,16,16")])
12045 (define_insn ""
12046 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12047 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12048 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
12049 ""
12050 "@
12051 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12052 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12053 [(set_attr "length" "8")])
12055 (define_insn ""
12056 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12057 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12058 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12059 (clobber (match_scratch:SI 3 "=r"))]
12060 "TARGET_POWER"
12061 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12062 [(set_attr "length" "12")])
12064 (define_insn ""
12065 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12066 (compare:CC
12067 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12068 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12069 (const_int 0)))
12070 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12071 (ge:SI (match_dup 1) (match_dup 2)))
12072 (clobber (match_scratch:SI 3 "=r,r"))]
12073 "TARGET_POWER"
12074 "@
12075 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12076 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3\;cmpli %4,%0,0"
12077 [(set_attr "type" "compare")
12078 (set_attr "length" "12,16")])
12080 (define_insn ""
12081 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12082 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12083 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12084 (match_operand:SI 3 "gpc_reg_operand" "r")))
12085 (clobber (match_scratch:SI 4 "=&r"))]
12086 "TARGET_POWER"
12087 "doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3"
12088 [(set_attr "length" "12")])
12090 (define_insn ""
12091 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12092 (compare:CC
12093 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12094 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12095 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12096 (const_int 0)))
12097 (clobber (match_scratch:SI 4 "=&r,&r"))]
12098 "TARGET_POWER"
12099 "@
12100 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12101 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %4,%3\;cmpli %0,%4,0"
12102 [(set_attr "type" "compare")
12103 (set_attr "length" "12,16")])
12105 (define_insn ""
12106 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
12107 (compare:CC
12108 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12109 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12110 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12111 (const_int 0)))
12112 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12113 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12114 (clobber (match_scratch:SI 4 "=&r,&r"))]
12115 "TARGET_POWER"
12116 "@
12117 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %0,%3
12118 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze|addze} %0,%3\;cmpli %5,%0,0"
12119 [(set_attr "type" "compare")
12120 (set_attr "length" "12,16")])
12122 (define_insn ""
12123 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12124 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12125 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12126 "TARGET_POWER"
12127 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12128 [(set_attr "length" "12")])
12130 ;; This is (and (neg (ge X (const_int 0))) Y).
12131 (define_insn ""
12132 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12133 (and:SI (neg:SI
12134 (lshiftrt:SI
12135 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
12136 (const_int 31)))
12137 (match_operand:SI 2 "gpc_reg_operand" "r")))
12138 (clobber (match_scratch:SI 3 "=&r"))]
12139 ""
12140 "{srai|srawi} %3,%1,31\;andc %0,%2,%3"
12141 [(set_attr "length" "8")])
12143 (define_insn ""
12144 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12145 (compare:CC
12146 (and:SI (neg:SI
12147 (lshiftrt:SI
12148 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
12149 (const_int 31)))
12150 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12151 (const_int 0)))
12152 (clobber (match_scratch:SI 3 "=&r,&r"))]
12153 ""
12154 "@
12155 {srai|srawi} %3,%1,31\;andc. %3,%2,%3
12156 {srai|srawi} %3,%1,31\;andc %3,%2,%3\;cmpli %0,%3,0"
12157 [(set_attr "type" "compare")
12158 (set_attr "length" "8,12")])
12160 (define_insn ""
12161 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12162 (compare:CC
12163 (and:SI (neg:SI
12164 (lshiftrt:SI
12165 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
12166 (const_int 31)))
12167 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12168 (const_int 0)))
12169 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12170 (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
12171 (const_int 31)))
12172 (match_dup 2)))
12173 (clobber (match_scratch:SI 3 "=&r,&r"))]
12174 ""
12175 "@
12176 {srai|srawi} %3,%1,31\;andc. %0,%2,%3
12177 {srai|srawi} %3,%1,31\;andc %0,%2,%3\;cmpli %4,%0,0"
12178 [(set_attr "type" "compare")
12179 (set_attr "length" "8,12")])
12181 (define_insn ""
12182 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12183 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12184 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12185 ""
12186 "@
12187 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
12188 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12189 [(set_attr "length" "12")])
12191 (define_insn ""
12192 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12193 (compare:CC
12194 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12195 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12196 (const_int 0)))
12197 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12198 (geu:SI (match_dup 1) (match_dup 2)))]
12199 ""
12200 "@
12201 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12202 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12203 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0\;cmpli %3,%0,0
12204 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0\;cmpli %3,%0,0"
12205 [(set_attr "type" "compare")
12206 (set_attr "length" "12,12,16,16")])
12208 (define_insn ""
12209 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12210 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12211 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12212 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
12213 (clobber (match_scratch:SI 4 "=&r,&r"))]
12214 ""
12215 "@
12216 {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3
12217 {ai|addic} %4,%1,%n2\;{aze|addze} %0,%3"
12218 [(set_attr "length" "8")])
12220 (define_insn ""
12221 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12222 (compare:CC
12223 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12224 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12225 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12226 (const_int 0)))
12227 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12228 ""
12229 "@
12230 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
12231 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12232 {sf|subfc} %4,%2,%1\;{aze|addze} %4,%3\;cmpli %0,%4,0
12233 {ai|addic} %4,%1,%n2\;{aze|addze} %4,%3\;cmpli %0,%4,0"
12234 [(set_attr "type" "compare")
12235 (set_attr "length" "8,8,12,12")])
12237 (define_insn ""
12238 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
12239 (compare:CC
12240 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12241 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12242 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12243 (const_int 0)))
12244 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12245 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12246 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12247 ""
12248 "@
12249 {sf|subfc} %4,%2,%1\;{aze.|addze.} %0,%3
12250 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
12251 {sf|subfc} %4,%2,%1\;{aze|addze} %0,%3\;cmpli %5,%0,0
12252 {ai|addic} %4,%1,%n2\;{aze|addze} %4,%3\;cmpli %5,%0,0"
12253 [(set_attr "type" "compare")
12254 (set_attr "length" "8,8,12,12")])
12256 (define_insn ""
12257 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12258 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12259 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
12260 ""
12261 "@
12262 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
12263 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
12264 [(set_attr "length" "12")])
12266 (define_insn ""
12267 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12268 (and:SI (neg:SI
12269 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12270 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
12271 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
12272 (clobber (match_scratch:SI 4 "=&r,&r"))]
12273 ""
12274 "@
12275 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4
12276 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4"
12277 [(set_attr "length" "12")])
12279 (define_insn ""
12280 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12281 (compare:CC
12282 (and:SI (neg:SI
12283 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12284 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12285 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12286 (const_int 0)))
12287 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12288 ""
12289 "@
12290 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12291 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12292 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %4,%3,%4\;cmpli %0,%4,0
12293 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4\;cmpli %0,%4,0"
12294 [(set_attr "type" "compare")
12295 (set_attr "length" "12,12,16,16")])
12297 (define_insn ""
12298 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
12299 (compare:CC
12300 (and:SI (neg:SI
12301 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12302 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
12303 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12304 (const_int 0)))
12305 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12306 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
12307 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12308 ""
12309 "@
12310 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
12311 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %0,%3,%4
12312 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4\;cmpli %5,%0,0
12313 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc %0,%3,%4\;cmpli %5,%0,0"
12314 [(set_attr "type" "compare")
12315 (set_attr "length" "12,12,16,16")])
12317 (define_insn ""
12318 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12319 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12320 (const_int 0)))]
12321 ""
12322 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
12323 [(set_attr "length" "12")])
12325 (define_insn ""
12326 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
12327 (compare:CC
12328 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12329 (const_int 0))
12330 (const_int 0)))
12331 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12332 (gt:SI (match_dup 1) (const_int 0)))]
12333 ""
12334 "@
12335 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
12336 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31\;cmpli %2,%0,0"
12337 [(set_attr "type" "delayed_compare,compare")
12338 (set_attr "length" "12,8")])
12340 (define_insn ""
12341 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12342 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12343 (match_operand:SI 2 "reg_or_short_operand" "r")))]
12344 "TARGET_POWER"
12345 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12346 [(set_attr "length" "12")])
12348 (define_insn ""
12349 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12350 (compare:CC
12351 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12352 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12353 (const_int 0)))
12354 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12355 (gt:SI (match_dup 1) (match_dup 2)))]
12356 "TARGET_POWER"
12357 "@
12358 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12359 doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31\;cmpli %3,%0,0"
12360 [(set_attr "type" "delayed_compare,compare")
12361 (set_attr "length" "12,16")])
12363 (define_insn ""
12364 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12365 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12366 (const_int 0))
12367 (match_operand:SI 2 "gpc_reg_operand" "r")))
12368 (clobber (match_scratch:SI 3 "=&r"))]
12369 ""
12370 "{a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %0,%2"
12371 [(set_attr "length" "12")])
12373 (define_insn ""
12374 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12375 (compare:CC
12376 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12377 (const_int 0))
12378 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12379 (const_int 0)))
12380 (clobber (match_scratch:SI 3 "=&r,&r"))]
12381 ""
12382 "@
12383 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
12384 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %3,%2\;cmpli %0,%3"
12385 [(set_attr "type" "compare")
12386 (set_attr "length" "12,16")])
12388 (define_insn ""
12389 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12390 (compare:CC
12391 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12392 (const_int 0))
12393 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12394 (const_int 0)))
12395 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12396 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
12397 (clobber (match_scratch:SI 3 "=&r,&r"))]
12398 ""
12399 "@
12400 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
12401 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze|addze} %3,%2\;cmpli %4,%3"
12402 [(set_attr "type" "compare")
12403 (set_attr "length" "12,16")])
12405 (define_insn ""
12406 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12407 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12408 (match_operand:SI 2 "reg_or_short_operand" "r"))
12409 (match_operand:SI 3 "gpc_reg_operand" "r")))
12410 (clobber (match_scratch:SI 4 "=&r"))]
12411 "TARGET_POWER"
12412 "doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3"
12413 [(set_attr "length" "12")])
12415 (define_insn ""
12416 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12417 (compare:CC
12418 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12419 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12420 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12421 (const_int 0)))
12422 (clobber (match_scratch:SI 4 "=&r,&r"))]
12423 "TARGET_POWER"
12424 "@
12425 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12426 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %4,%3\;cmpli %0,%4,0"
12427 [(set_attr "type" "compare")
12428 (set_attr "length" "12,16")])
12430 (define_insn ""
12431 [(set (match_operand:CC 5 "cc_reg_operand" "=x,?y")
12432 (compare:CC
12433 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12434 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
12435 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12436 (const_int 0)))
12437 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12438 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12439 (clobber (match_scratch:SI 4 "=&r,&r"))]
12440 "TARGET_POWER"
12441 "@
12442 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %0,%3
12443 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze|addze} %0,%3\;cmpli %5,%0,0"
12444 [(set_attr "type" "compare")
12445 (set_attr "length" "12,16")])
12447 (define_insn ""
12448 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12449 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12450 (const_int 0))))]
12451 ""
12452 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
12453 [(set_attr "length" "12")])
12455 (define_insn ""
12456 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12457 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12458 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
12459 "TARGET_POWER"
12460 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12461 [(set_attr "length" "12")])
12463 (define_insn ""
12464 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12465 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12466 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12467 ""
12468 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
12469 [(set_attr "length" "12")])
12471 (define_insn ""
12472 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12473 (compare:CC
12474 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12475 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12476 (const_int 0)))
12477 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12478 (gtu:SI (match_dup 1) (match_dup 2)))]
12479 ""
12480 "@
12481 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12482 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0\;cmpli %3,%0,0"
12483 [(set_attr "type" "compare")
12484 (set_attr "length" "12,16")])
12486 (define_insn ""
12487 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
12488 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
12489 (match_operand:SI 2 "reg_or_short_operand" "I,r,rI"))
12490 (match_operand:SI 3 "reg_or_short_operand" "r,r,I")))
12491 (clobber (match_scratch:SI 4 "=&r,&r,&r"))]
12492 ""
12493 "@
12494 {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3
12495 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3
12496 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf%I3|subf%I3c} %0,%4,%3"
12497 [(set_attr "length" "8,12,12")])
12499 (define_insn ""
12500 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12501 (compare:CC
12502 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12503 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
12504 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12505 (const_int 0)))
12506 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12507 ""
12508 "@
12509 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
12510 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12511 {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3\;cmpli %0,%4,0
12512 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3\;cmpli %0,%4,0"
12513 [(set_attr "type" "compare")
12514 (set_attr "length" "8,12,12,16")])
12516 (define_insn ""
12517 [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,?y,?y")
12518 (compare:CC
12519 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12520 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
12521 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12522 (const_int 0)))
12523 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12524 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12525 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12526 ""
12527 "@
12528 {ai|addic} %4,%1,%k2\;{aze.|addze.} %0,%3
12529 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %0,%4,%3
12530 {ai|addic} %4,%1,%k2\;{aze|addze} %0,%3\;cmpli %5,%0,0
12531 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf|subfc} %0,%4,%3\;cmpli %5,%0,0"
12532 [(set_attr "type" "compare")
12533 (set_attr "length" "8,12,12,16")])
12535 (define_insn ""
12536 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12537 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12538 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12539 ""
12540 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
12541 [(set_attr "length" "8")])
12542 \f
12543 ;; Define both directions of branch and return. If we need a reload
12544 ;; register, we'd rather use CR0 since it is much easier to copy a
12545 ;; register CC value to there.
12547 (define_insn ""
12548 [(set (pc)
12549 (if_then_else (match_operator 1 "branch_comparison_operator"
12550 [(match_operand 2
12551 "cc_reg_operand" "x,?y")
12552 (const_int 0)])
12553 (label_ref (match_operand 0 "" ""))
12554 (pc)))]
12555 ""
12556 "*
12557 {
12558 if (get_attr_length (insn) == 8)
12559 return \"%C1bc %t1,%j1,%l0\";
12560 else
12561 return \"%C1bc %T1,%j1,%$+8\;b %l0\";
12563 }"
12564 [(set_attr "type" "branch")])
12566 (define_insn ""
12567 [(set (pc)
12568 (if_then_else (match_operator 0 "branch_comparison_operator"
12569 [(match_operand 1
12570 "cc_reg_operand" "x,?y")
12571 (const_int 0)])
12572 (return)
12573 (pc)))]
12574 "direct_return ()"
12575 "{%C0bcr|%C0bclr} %t0,%j0"
12576 [(set_attr "type" "branch")
12577 (set_attr "length" "8")])
12579 (define_insn ""
12580 [(set (pc)
12581 (if_then_else (match_operator 1 "branch_comparison_operator"
12582 [(match_operand 2
12583 "cc_reg_operand" "x,?y")
12584 (const_int 0)])
12585 (pc)
12586 (label_ref (match_operand 0 "" ""))))]
12587 ""
12588 "*
12589 {
12590 if (get_attr_length (insn) == 8)
12591 return \"%C1bc %T1,%j1,%l0\";
12592 else
12593 return \"%C1bc %t1,%j1,%$+8\;b %l0\";
12594 }"
12595 [(set_attr "type" "branch")])
12597 (define_insn ""
12598 [(set (pc)
12599 (if_then_else (match_operator 0 "branch_comparison_operator"
12600 [(match_operand 1
12601 "cc_reg_operand" "x,?y")
12602 (const_int 0)])
12603 (pc)
12604 (return)))]
12605 "direct_return ()"
12606 "{%C0bcr|%C0bclr} %T0,%j0"
12607 [(set_attr "type" "branch")
12608 (set_attr "length" "8")])
12610 ;; Unconditional branch and return.
12612 (define_insn "jump"
12613 [(set (pc)
12614 (label_ref (match_operand 0 "" "")))]
12615 ""
12616 "b %l0"
12617 [(set_attr "type" "branch")])
12619 (define_insn "return"
12620 [(return)]
12621 "direct_return ()"
12622 "{br|blr}"
12623 [(set_attr "type" "jmpreg")])
12625 (define_insn "indirect_jump"
12626 [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))]
12627 ""
12628 "@
12629 bctr
12630 {br|blr}"
12631 [(set_attr "type" "jmpreg")])
12633 (define_insn ""
12634 [(set (pc) (match_operand:DI 0 "register_operand" "c,l"))]
12635 "TARGET_POWERPC64"
12636 "@
12637 bctr
12638 {br|blr}"
12639 [(set_attr "type" "jmpreg")])
12641 ;; Table jump for switch statements:
12642 (define_expand "tablejump"
12643 [(use (match_operand 0 "" ""))
12644 (use (label_ref (match_operand 1 "" "")))]
12645 ""
12646 "
12647 {
12648 if (TARGET_32BIT)
12649 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
12650 else
12651 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
12652 DONE;
12653 }")
12655 (define_expand "tablejumpsi"
12656 [(set (match_dup 3)
12657 (plus:SI (match_operand:SI 0 "" "")
12658 (match_dup 2)))
12659 (parallel [(set (pc) (match_dup 3))
12660 (use (label_ref (match_operand 1 "" "")))])]
12661 ""
12662 "
12663 { operands[0] = force_reg (SImode, operands[0]);
12664 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (VOIDmode, operands[1]));
12665 operands[3] = gen_reg_rtx (SImode);
12666 }")
12668 (define_expand "tablejumpdi"
12669 [(set (match_dup 3)
12670 (plus:DI (match_operand:DI 0 "" "")
12671 (match_dup 2)))
12672 (parallel [(set (pc) (match_dup 3))
12673 (use (label_ref (match_operand 1 "" "")))])]
12674 ""
12675 "
12676 { operands[0] = force_reg (DImode, operands[0]);
12677 operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (VOIDmode, operands[1]));
12678 operands[3] = gen_reg_rtx (DImode);
12679 }")
12681 (define_insn ""
12682 [(set (pc)
12683 (match_operand:SI 0 "register_operand" "c,l"))
12684 (use (label_ref (match_operand 1 "" "")))]
12685 ""
12686 "@
12687 bctr
12688 {br|blr}"
12689 [(set_attr "type" "jmpreg")])
12691 (define_insn ""
12692 [(set (pc)
12693 (match_operand:DI 0 "register_operand" "c,l"))
12694 (use (label_ref (match_operand 1 "" "")))]
12695 "TARGET_POWERPC64"
12696 "@
12697 bctr
12698 {br|blr}"
12699 [(set_attr "type" "jmpreg")])
12701 (define_insn "nop"
12702 [(const_int 0)]
12703 ""
12704 "{cror 0,0,0|nop}")
12705 \f
12706 ;; Define the subtract-one-and-jump insns, starting with the template
12707 ;; so loop.c knows what to generate.
12709 (define_expand "decrement_and_branch_on_count"
12710 [(parallel [(set (pc) (if_then_else (ne (match_operand:SI 0 "register_operand" "")
12711 (const_int 1))
12712 (label_ref (match_operand 1 "" ""))
12713 (pc)))
12714 (set (match_dup 0)
12715 (plus:SI (match_dup 0)
12716 (const_int -1)))
12717 (clobber (match_scratch:CC 2 ""))
12718 (clobber (match_scratch:SI 3 ""))])]
12719 ""
12720 "")
12722 ;; We need to be able to do this for any operand, including MEM, or we
12723 ;; will cause reload to blow up since we don't allow output reloads on
12724 ;; JUMP_INSNs.
12725 ;; In order that the length attribute is calculated correctly, the
12726 ;; label MUST be operand 0.
12728 (define_insn ""
12729 [(set (pc)
12730 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
12731 (const_int 1))
12732 (label_ref (match_operand 0 "" ""))
12733 (pc)))
12734 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
12735 (plus:SI (match_dup 1)
12736 (const_int -1)))
12737 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12738 (clobber (match_scratch:SI 4 "=X,X,r"))]
12739 ""
12740 "*
12741 {
12742 if (which_alternative != 0)
12743 return \"#\";
12744 else if (get_attr_length (insn) == 8)
12745 return \"{bdn|bdnz} %l0\";
12746 else
12747 return \"bdz %$+8\;b %l0\";
12748 }"
12749 [(set_attr "type" "branch")
12750 (set_attr "length" "*,12,16")])
12752 (define_insn ""
12753 [(set (pc)
12754 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
12755 (const_int 1))
12756 (pc)
12757 (label_ref (match_operand 0 "" ""))))
12758 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
12759 (plus:SI (match_dup 1)
12760 (const_int -1)))
12761 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12762 (clobber (match_scratch:SI 4 "=X,X,r"))]
12763 ""
12764 "*
12765 {
12766 if (which_alternative != 0)
12767 return \"#\";
12768 else if (get_attr_length (insn) == 8)
12769 return \"bdz %l0\";
12770 else
12771 return \"{bdn|bdnz} %$+8\;b %l0\";
12772 }"
12773 [(set_attr "type" "branch")
12774 (set_attr "length" "*,12,16")])
12776 ;; Similar, but we can use GE since we have a REG_NONNEG.
12777 (define_insn ""
12778 [(set (pc)
12779 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
12780 (const_int 0))
12781 (label_ref (match_operand 0 "" ""))
12782 (pc)))
12783 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
12784 (plus:SI (match_dup 1)
12785 (const_int -1)))
12786 (clobber (match_scratch:CC 3 "=X,&x,&X"))
12787 (clobber (match_scratch:SI 4 "=X,X,r"))]
12788 "find_reg_note (insn, REG_NONNEG, 0)"
12789 "*
12790 {
12791 if (which_alternative != 0)
12792 return \"#\";
12793 else if (get_attr_length (insn) == 8)
12794 return \"{bdn|bdnz} %l0\";
12795 else
12796 return \"bdz %$+8\;b %l0\";
12797 }"
12798 [(set_attr "type" "branch")
12799 (set_attr "length" "*,12,16")])
12801 (define_insn ""
12802 [(set (pc)
12803 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
12804 (const_int 0))
12805 (pc)
12806 (label_ref (match_operand 0 "" ""))))
12807 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
12808 (plus:SI (match_dup 1)
12809 (const_int -1)))
12810 (clobber (match_scratch:CC 3 "=X,&x,&X"))
12811 (clobber (match_scratch:SI 4 "=X,X,r"))]
12812 "find_reg_note (insn, REG_NONNEG, 0)"
12813 "*
12814 {
12815 if (which_alternative != 0)
12816 return \"#\";
12817 else if (get_attr_length (insn) == 8)
12818 return \"bdz %l0\";
12819 else
12820 return \"{bdn|bdnz} %$+8\;b %l0\";
12821 }"
12822 [(set_attr "type" "branch")
12823 (set_attr "length" "*,12,16")])
12825 (define_insn ""
12826 [(set (pc)
12827 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
12828 (const_int 1))
12829 (label_ref (match_operand 0 "" ""))
12830 (pc)))
12831 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
12832 (plus:SI (match_dup 1)
12833 (const_int -1)))
12834 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12835 (clobber (match_scratch:SI 4 "=X,X,r"))]
12836 ""
12837 "*
12838 {
12839 if (which_alternative != 0)
12840 return \"#\";
12841 else if (get_attr_length (insn) == 8)
12842 return \"bdz %l0\";
12843 else
12844 return \"{bdn|bdnz} %$+8\;b %l0\";
12845 }"
12846 [(set_attr "type" "branch")
12847 (set_attr "length" "*,12,16")])
12849 (define_insn ""
12850 [(set (pc)
12851 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
12852 (const_int 1))
12853 (pc)
12854 (label_ref (match_operand 0 "" ""))))
12855 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
12856 (plus:SI (match_dup 1)
12857 (const_int -1)))
12858 (clobber (match_scratch:CC 3 "=X,&x,&x"))
12859 (clobber (match_scratch:SI 4 "=X,X,r"))]
12860 ""
12861 "*
12862 {
12863 if (which_alternative != 0)
12864 return \"#\";
12865 else if (get_attr_length (insn) == 8)
12866 return \"{bdn|bdnz} %l0\";
12867 else
12868 return \"bdz %$+8\;b %l0\";
12869 }"
12870 [(set_attr "type" "branch")
12871 (set_attr "length" "*,12,16")])
12873 (define_split
12874 [(set (pc)
12875 (if_then_else (match_operator 2 "comparison_operator"
12876 [(match_operand:SI 1 "gpc_reg_operand" "")
12877 (const_int 1)])
12878 (match_operand 5 "" "")
12879 (match_operand 6 "" "")))
12880 (set (match_operand:SI 0 "gpc_reg_operand" "")
12881 (plus:SI (match_dup 1)
12882 (const_int -1)))
12883 (clobber (match_scratch:CC 3 ""))
12884 (clobber (match_scratch:SI 4 ""))]
12885 "reload_completed"
12886 [(parallel [(set (match_dup 3)
12887 (compare:CC (plus:SI (match_dup 1)
12888 (const_int -1))
12889 (const_int 0)))
12890 (set (match_dup 0)
12891 (plus:SI (match_dup 1)
12892 (const_int -1)))])
12893 (set (pc) (if_then_else (match_dup 7)
12894 (match_dup 5)
12895 (match_dup 6)))]
12896 "
12897 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
12898 const0_rtx); }")
12900 (define_split
12901 [(set (pc)
12902 (if_then_else (match_operator 2 "comparison_operator"
12903 [(match_operand:SI 1 "gpc_reg_operand" "")
12904 (const_int 1)])
12905 (match_operand 5 "" "")
12906 (match_operand 6 "" "")))
12907 (set (match_operand:SI 0 "general_operand" "")
12908 (plus:SI (match_dup 1) (const_int -1)))
12909 (clobber (match_scratch:CC 3 ""))
12910 (clobber (match_scratch:SI 4 ""))]
12911 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
12912 [(parallel [(set (match_dup 3)
12913 (compare:CC (plus:SI (match_dup 1)
12914 (const_int -1))
12915 (const_int 0)))
12916 (set (match_dup 4)
12917 (plus:SI (match_dup 1)
12918 (const_int -1)))])
12919 (set (match_dup 0)
12920 (match_dup 4))
12921 (set (pc) (if_then_else (match_dup 7)
12922 (match_dup 5)
12923 (match_dup 6)))]
12924 "
12925 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
12926 const0_rtx); }")
12927 \f
12928 (define_insn "trap"
12929 [(trap_if (const_int 1) (const_int 0))]
12930 ""
12931 "{t 31,0,0|trap}")
12933 (define_expand "conditional_trap"
12934 [(trap_if (match_operator 0 "trap_comparison_operator"
12935 [(match_dup 2) (match_dup 3)])
12936 (match_operand 1 "const_int_operand" ""))]
12937 ""
12938 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
12939 operands[2] = rs6000_compare_op0;
12940 operands[3] = rs6000_compare_op1;")
12942 (define_insn ""
12943 [(trap_if (match_operator 0 "trap_comparison_operator"
12944 [(match_operand:SI 1 "register_operand" "r")
12945 (match_operand:SI 2 "reg_or_short_operand" "rI")])
12946 (const_int 0))]
12947 ""
12948 "t%V0%I2 %1,%2")