gcc/config/m32r/m32r.c

   1 /* Subroutines used for code generation on the Mitsubishi M32R cpu.
   2    Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
   3
   4 This file is part of GNU CC.
   5
   6 GNU CC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 2, or (at your option)
   9 any later version.
  10
  11 GNU CC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GNU CC; see the file COPYING.  If not, write to
  18 the Free Software Foundation, 59 Temple Place - Suite 330,
  19 Boston, MA 02111-1307, USA.  */
  20
  21 #include "config.h"
  22 #include "system.h"
  23 #include "tree.h"
  24 #include "rtl.h"
  25 #include "regs.h"
  26 #include "hard-reg-set.h"
  27 #include "real.h"
  28 #include "insn-config.h"
  29 #include "conditions.h"
  30 #include "insn-flags.h"
  31 #include "output.h"
  32 #include "insn-attr.h"
  33 #include "flags.h"
  34 #include "expr.h"
  35 #include "function.h"
  36 #include "recog.h"
  37 #include "toplev.h"
  38 #include "m32r-protos.h"
  39
  40 /* Save the operands last given to a compare for use when we
  41    generate a scc or bcc insn.  */
  42 rtx m32r_compare_op0, m32r_compare_op1;
  43
  44 /* Array of valid operand punctuation characters.  */
  45 char m32r_punct_chars[256];
  46
  47 /* Selected code model.  */
  48 const char * m32r_model_string = M32R_MODEL_DEFAULT;
  49 enum m32r_model m32r_model;
  50
  51 /* Selected SDA support.  */
  52 const char * m32r_sdata_string = M32R_SDATA_DEFAULT;
  53 enum m32r_sdata m32r_sdata;
  54
  55 /* Scheduler support */
  56 int m32r_sched_odd_word_p;
  57
  58 /* Forward declaration.  */
  59 static void init_reg_tables                     PARAMS ((void));
  60
  61 /* Called by OVERRIDE_OPTIONS to initialize various things.  */
  62
  63 void
  64 m32r_init ()
  65 {
  66   init_reg_tables ();
  67
  68   /* Initialize array for PRINT_OPERAND_PUNCT_VALID_P.  */
  69   memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars));
  70   m32r_punct_chars['#'] = 1;
  71   m32r_punct_chars['@'] = 1; /* ??? no longer used */
  72
  73   /* Provide default value if not specified.  */
  74   if (!g_switch_set)
  75     g_switch_value = SDATA_DEFAULT_SIZE;
  76
  77   if (strcmp (m32r_model_string, "small") == 0)
  78     m32r_model = M32R_MODEL_SMALL;
  79   else if (strcmp (m32r_model_string, "medium") == 0)
  80     m32r_model = M32R_MODEL_MEDIUM;
  81   else if (strcmp (m32r_model_string, "large") == 0)
  82     m32r_model = M32R_MODEL_LARGE;
  83   else
  84     error ("bad value (%s) for -mmodel switch", m32r_model_string);
  85
  86   if (strcmp (m32r_sdata_string, "none") == 0)
  87     m32r_sdata = M32R_SDATA_NONE;
  88   else if (strcmp (m32r_sdata_string, "sdata") == 0)
  89     m32r_sdata = M32R_SDATA_SDATA;
  90   else if (strcmp (m32r_sdata_string, "use") == 0)
  91     m32r_sdata = M32R_SDATA_USE;
  92   else
  93     error ("bad value (%s) for -msdata switch", m32r_sdata_string);
  94 }
  95
  96 /* Vectors to keep interesting information about registers where it can easily
  97    be got.  We use to use the actual mode value as the bit number, but there
  98    is (or may be) more than 32 modes now.  Instead we use two tables: one
  99    indexed by hard register number, and one indexed by mode.  */
 100
 101 /* The purpose of m32r_mode_class is to shrink the range of modes so that
 102    they all fit (as bit numbers) in a 32 bit word (again).  Each real mode is
 103    mapped into one m32r_mode_class mode.  */
 104
 105 enum m32r_mode_class
 106 {
 107   C_MODE,
 108   S_MODE, D_MODE, T_MODE, O_MODE,
 109   SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE
 110 };
 111
 112 /* Modes for condition codes.  */
 113 #define C_MODES (1 << (int) C_MODE)
 114
 115 /* Modes for single-word and smaller quantities.  */
 116 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
 117
 118 /* Modes for double-word and smaller quantities.  */
 119 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
 120
 121 /* Modes for quad-word and smaller quantities.  */
 122 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
 123
 124 /* Modes for accumulators.  */
 125 #define A_MODES (1 << (int) A_MODE)
 126
 127 /* Value is 1 if register/mode pair is acceptable on arc.  */
 128
 129 unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] =
 130 {
 131   T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES,
 132   T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES,
 133   S_MODES, C_MODES, A_MODES
 134 };
 135
 136 unsigned int m32r_mode_class [NUM_MACHINE_MODES];
 137
 138 enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER];
 139
 140 static void
 141 init_reg_tables ()
 142 {
 143   int i;
 144
 145   for (i = 0; i < NUM_MACHINE_MODES; i++)
 146     {
 147       switch (GET_MODE_CLASS (i))
 148         {
 149         case MODE_INT:
 150         case MODE_PARTIAL_INT:
 151         case MODE_COMPLEX_INT:
 152           if (GET_MODE_SIZE (i) <= 4)
 153             m32r_mode_class[i] = 1 << (int) S_MODE;
 154           else if (GET_MODE_SIZE (i) == 8)
 155             m32r_mode_class[i] = 1 << (int) D_MODE;
 156           else if (GET_MODE_SIZE (i) == 16)
 157             m32r_mode_class[i] = 1 << (int) T_MODE;
 158           else if (GET_MODE_SIZE (i) == 32)
 159             m32r_mode_class[i] = 1 << (int) O_MODE;
 160           else
 161             m32r_mode_class[i] = 0;
 162           break;
 163         case MODE_FLOAT:
 164         case MODE_COMPLEX_FLOAT:
 165           if (GET_MODE_SIZE (i) <= 4)
 166             m32r_mode_class[i] = 1 << (int) SF_MODE;
 167           else if (GET_MODE_SIZE (i) == 8)
 168             m32r_mode_class[i] = 1 << (int) DF_MODE;
 169           else if (GET_MODE_SIZE (i) == 16)
 170             m32r_mode_class[i] = 1 << (int) TF_MODE;
 171           else if (GET_MODE_SIZE (i) == 32)
 172             m32r_mode_class[i] = 1 << (int) OF_MODE;
 173           else
 174             m32r_mode_class[i] = 0;
 175           break;
 176         case MODE_CC:
 177         default:
 178           /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
 179              we must explicitly check for them here.  */
 180           if (i == (int) CCmode)
 181             m32r_mode_class[i] = 1 << (int) C_MODE;
 182           else
 183             m32r_mode_class[i] = 0;
 184           break;
 185         }
 186     }
 187
 188   for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
 189     {
 190       if (GPR_P (i))
 191         m32r_regno_reg_class[i] = GENERAL_REGS;
 192       else if (i == ARG_POINTER_REGNUM)
 193         m32r_regno_reg_class[i] = GENERAL_REGS;
 194       else
 195         m32r_regno_reg_class[i] = NO_REGS;
 196     }
 197 }
 198 \f
 199 /* M32R specific attribute support.
 200
 201    interrupt - for interrupt functions
 202
 203    model - select code model used to access object
 204
 205         small: addresses use 24 bits, use bl to make calls
 206         medium: addresses use 32 bits, use bl to make calls
 207         large: addresses use 32 bits, use seth/add3/jl to make calls
 208
 209         Grep for MODEL in m32r.h for more info.
 210 */
 211
 212 static tree interrupt_ident1;
 213 static tree interrupt_ident2;
 214 static tree model_ident1;
 215 static tree model_ident2;
 216 static tree small_ident1;
 217 static tree small_ident2;
 218 static tree medium_ident1;
 219 static tree medium_ident2;
 220 static tree large_ident1;
 221 static tree large_ident2;
 222
 223 static void
 224 init_idents PARAMS ((void))
 225 {
 226   if (interrupt_ident1 == 0)
 227     {
 228       interrupt_ident1 = get_identifier ("interrupt");
 229       interrupt_ident2 = get_identifier ("__interrupt__");
 230       model_ident1 = get_identifier ("model");
 231       model_ident2 = get_identifier ("__model__");
 232       small_ident1 = get_identifier ("small");
 233       small_ident2 = get_identifier ("__small__");
 234       medium_ident1 = get_identifier ("medium");
 235       medium_ident2 = get_identifier ("__medium__");
 236       large_ident1 = get_identifier ("large");
 237       large_ident2 = get_identifier ("__large__");
 238     }
 239 }
 240
 241 /* Return nonzero if IDENTIFIER is a valid decl attribute.  */
 242
 243 int
 244 m32r_valid_machine_decl_attribute (type, attributes, identifier, args)
 245      tree type ATTRIBUTE_UNUSED;
 246      tree attributes ATTRIBUTE_UNUSED;
 247      tree identifier;
 248      tree args;
 249 {
 250   init_idents ();
 251
 252   if ((identifier == interrupt_ident1
 253        || identifier == interrupt_ident2)
 254       && list_length (args) == 0)
 255     return 1;
 256
 257   if ((identifier == model_ident1
 258        || identifier == model_ident2)
 259       && list_length (args) == 1
 260       && (TREE_VALUE (args) == small_ident1
 261           || TREE_VALUE (args) == small_ident2
 262           || TREE_VALUE (args) == medium_ident1
 263           || TREE_VALUE (args) == medium_ident2
 264           || TREE_VALUE (args) == large_ident1
 265           || TREE_VALUE (args) == large_ident2))
 266     return 1;
 267
 268   return 0;
 269 }
 270
 271 /* Return zero if TYPE1 and TYPE are incompatible, one if they are compatible,
 272    and two if they are nearly compatible (which causes a warning to be
 273    generated).  */
 274
 275 int
 276 m32r_comp_type_attributes (type1, type2)
 277      tree type1 ATTRIBUTE_UNUSED;
 278      tree type2 ATTRIBUTE_UNUSED;
 279 {
 280   return 1;
 281 }
 282
 283 /* Set the default attributes for TYPE.  */
 284
 285 void
 286 m32r_set_default_type_attributes (type)
 287      tree type ATTRIBUTE_UNUSED;
 288 {
 289 }
 290 \f
 291 /* A C statement or statements to switch to the appropriate
 292    section for output of DECL.  DECL is either a `VAR_DECL' node
 293    or a constant of some sort.  RELOC indicates whether forming
 294    the initial value of DECL requires link-time relocations.  */
 295
 296 void
 297 m32r_select_section (decl, reloc)
 298      tree decl;
 299      int reloc;
 300 {
 301   if (TREE_CODE (decl) == STRING_CST)
 302     {
 303       if (! flag_writable_strings)
 304         const_section ();
 305       else
 306         data_section ();
 307     }
 308   else if (TREE_CODE (decl) == VAR_DECL)
 309     {
 310       if (SDATA_NAME_P (XSTR (XEXP (DECL_RTL (decl), 0), 0)))
 311         sdata_section ();
 312       else if ((flag_pic && reloc)
 313                || !TREE_READONLY (decl)
 314                || TREE_SIDE_EFFECTS (decl)
 315                || !DECL_INITIAL (decl)
 316                || (DECL_INITIAL (decl) != error_mark_node
 317                    && !TREE_CONSTANT (DECL_INITIAL (decl))))
 318         data_section ();
 319       else
 320         const_section ();
 321     }
 322   else
 323     const_section ();
 324 }
 325
 326 /* Encode section information of DECL, which is either a VAR_DECL,
 327    FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???.
 328
 329    For the M32R we want to record:
 330
 331    - whether the object lives in .sdata/.sbss.
 332      objects living in .sdata/.sbss are prefixed with SDATA_FLAG_CHAR
 333
 334    - what code model should be used to access the object
 335      small: recorded with no flag - for space efficiency since they'll
 336             be the most common
 337      medium: prefixed with MEDIUM_FLAG_CHAR
 338      large: prefixed with LARGE_FLAG_CHAR
 339 */
 340
 341 void
 342 m32r_encode_section_info (decl)
 343      tree decl;
 344 {
 345   char prefix = 0;
 346   tree model = 0;
 347
 348   switch (TREE_CODE (decl))
 349     {
 350     case VAR_DECL :
 351     case FUNCTION_DECL :
 352       model = lookup_attribute ("model", DECL_MACHINE_ATTRIBUTES (decl));
 353       break;
 354     case STRING_CST :
 355     case CONSTRUCTOR :
 356       /* ??? document all others that can appear here */
 357     default :
 358       return;
 359     }
 360
 361   /* Only mark the object as being small data area addressable if
 362      it hasn't been explicitly marked with a code model.
 363
 364      The user can explicitly put an object in the small data area with the
 365      section attribute.  If the object is in sdata/sbss and marked with a
 366      code model do both [put the object in .sdata and mark it as being
 367      addressed with a specific code model - don't mark it as being addressed
 368      with an SDA reloc though].  This is ok and might be useful at times.  If
 369      the object doesn't fit the linker will give an error.  */
 370
 371   if (! model)
 372     {
 373       if (TREE_CODE_CLASS (TREE_CODE (decl)) == 'd'
 374           && DECL_SECTION_NAME (decl) != NULL_TREE)
 375         {
 376           char *name = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
 377           if (! strcmp (name, ".sdata") || ! strcmp (name, ".sbss"))
 378             {
 379 #if 0 /* ??? There's no reason to disallow this, is there?  */
 380               if (TREE_READONLY (decl))
 381                 error_with_decl (decl, "const objects cannot go in .sdata/.sbss");
 382 #endif
 383               prefix = SDATA_FLAG_CHAR;
 384             }
 385         }
 386       else
 387         {
 388           if (TREE_CODE (decl) == VAR_DECL
 389               && ! TREE_READONLY (decl)
 390               && ! TARGET_SDATA_NONE)
 391             {
 392               int size = int_size_in_bytes (TREE_TYPE (decl));
 393
 394               if (size > 0 && size <= g_switch_value)
 395                 prefix = SDATA_FLAG_CHAR;
 396             }
 397         }
 398     }
 399
 400   /* If data area not decided yet, check for a code model.  */
 401   if (prefix == 0)
 402     {
 403       if (model)
 404         {
 405           tree id;
 406
 407           init_idents ();
 408
 409           id = TREE_VALUE (TREE_VALUE (model));
 410
 411           if (id == small_ident1 || id == small_ident2)
 412             ; /* don't mark the symbol specially */
 413           else if (id == medium_ident1 || id == medium_ident2)
 414             prefix = MEDIUM_FLAG_CHAR;
 415           else if (id == large_ident1 || id == large_ident2)
 416             prefix = LARGE_FLAG_CHAR;
 417           else
 418             abort (); /* shouldn't happen */
 419         }
 420       else
 421         {
 422           if (TARGET_MODEL_SMALL)
 423             ; /* don't mark the symbol specially */
 424           else if (TARGET_MODEL_MEDIUM)
 425             prefix = MEDIUM_FLAG_CHAR;
 426           else if (TARGET_MODEL_LARGE)
 427             prefix = LARGE_FLAG_CHAR;
 428           else
 429             abort (); /* shouldn't happen */
 430         }
 431     }
 432
 433   if (prefix != 0)
 434     {
 435       rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd'
 436                  ? TREE_CST_RTL (decl) : DECL_RTL (decl));
 437       const char *str = XSTR (XEXP (rtl, 0), 0);
 438       int len = strlen (str);
 439       char *newstr = savealloc (len + 2);
 440       strcpy (newstr + 1, str);
 441       *newstr = prefix;
 442       XSTR (XEXP (rtl, 0), 0) = newstr;
 443     }
 444 }
 445
 446 /* Do anything needed before RTL is emitted for each function.  */
 447
 448 void
 449 m32r_init_expanders ()
 450 {
 451   /* ??? At one point there was code here.  The function is left in
 452      to make it easy to experiment.  */
 453 }
 454 \f
 455 /* Acceptable arguments to the call insn.  */
 456
 457 int
 458 call_address_operand (op, mode)
 459      rtx op;
 460      enum machine_mode mode;
 461 {
 462   return symbolic_operand (op, mode);
 463
 464 /* Constants and values in registers are not OK, because
 465    the m32r BL instruction can only support PC relative branching.  */
 466 }
 467
 468 int
 469 call_operand (op, mode)
 470      rtx op;
 471      enum machine_mode mode;
 472 {
 473   if (GET_CODE (op) != MEM)
 474     return 0;
 475   op = XEXP (op, 0);
 476   return call_address_operand (op, mode);
 477 }
 478
 479 /* Returns 1 if OP is a symbol reference.  */
 480
 481 int
 482 symbolic_operand (op, mode)
 483      rtx op;
 484      enum machine_mode mode ATTRIBUTE_UNUSED;
 485 {
 486   switch (GET_CODE (op))
 487     {
 488     case SYMBOL_REF:
 489     case LABEL_REF:
 490     case CONST :
 491       return 1;
 492
 493     default:
 494       return 0;
 495     }
 496 }
 497
 498 /* Return 1 if OP is a reference to an object in .sdata/.sbss.  */
 499
 500 int
 501 small_data_operand (op, mode)
 502      rtx op;
 503      enum machine_mode mode ATTRIBUTE_UNUSED;
 504 {
 505   if (! TARGET_SDATA_USE)
 506     return 0;
 507
 508   if (GET_CODE (op) == SYMBOL_REF)
 509     return SDATA_NAME_P (XSTR (op, 0));
 510
 511   if (GET_CODE (op) == CONST
 512       && GET_CODE (XEXP (op, 0)) == PLUS
 513       && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
 514       && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
 515       && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
 516     return SDATA_NAME_P (XSTR (XEXP (XEXP (op, 0), 0), 0));
 517
 518   return 0;
 519 }
 520
 521 /* Return 1 if OP is a symbol that can use 24 bit addressing.  */
 522
 523 int
 524 addr24_operand (op, mode)
 525      rtx op;
 526      enum machine_mode mode ATTRIBUTE_UNUSED;
 527 {
 528   if (GET_CODE (op) == LABEL_REF)
 529     return TARGET_ADDR24;
 530
 531   if (GET_CODE (op) == SYMBOL_REF)
 532     return (SMALL_NAME_P (XSTR (op, 0))
 533             || (TARGET_ADDR24
 534                 && (CONSTANT_POOL_ADDRESS_P (op)
 535                     || LIT_NAME_P (XSTR (op, 0)))));
 536
 537   if (GET_CODE (op) == CONST
 538       && GET_CODE (XEXP (op, 0)) == PLUS
 539       && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
 540       && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
 541       && UINT24_P (INTVAL (XEXP (XEXP (op, 0), 1))))
 542     {
 543       rtx sym = XEXP (XEXP (op, 0), 0);
 544       return (SMALL_NAME_P (XSTR (sym, 0))
 545               || (TARGET_ADDR24
 546                   && (CONSTANT_POOL_ADDRESS_P (op)
 547                       || LIT_NAME_P (XSTR (op, 0)))));
 548     }
 549
 550   return 0;
 551 }
 552
 553 /* Return 1 if OP is a symbol that needs 32 bit addressing.  */
 554
 555 int
 556 addr32_operand (op, mode)
 557      rtx op;
 558      enum machine_mode mode;
 559 {
 560   if (GET_CODE (op) == LABEL_REF)
 561     return TARGET_ADDR32;
 562
 563   if (GET_CODE (op) == SYMBOL_REF)
 564     return (! addr24_operand (op, mode)
 565             && ! small_data_operand (op, mode));
 566
 567   if (GET_CODE (op) == CONST
 568       && GET_CODE (XEXP (op, 0)) == PLUS
 569       && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
 570       && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
 571     {
 572       return (! addr24_operand (op, mode)
 573               && ! small_data_operand (op, mode));
 574     }
 575
 576   return 0;
 577 }
 578
 579 /* Return 1 if OP is a function that can be called with the `bl' insn.  */
 580
 581 int
 582 call26_operand (op, mode)
 583      rtx op;
 584      enum machine_mode mode ATTRIBUTE_UNUSED;
 585 {
 586   if (GET_CODE (op) == SYMBOL_REF)
 587     return ! LARGE_NAME_P (XSTR (op, 0));
 588
 589   return TARGET_CALL26;
 590 }
 591
 592 /* Returns 1 if OP is an acceptable operand for seth/add3.  */
 593
 594 int
 595 seth_add3_operand (op, mode)
 596      rtx op;
 597      enum machine_mode mode ATTRIBUTE_UNUSED;
 598 {
 599   if (GET_CODE (op) == SYMBOL_REF
 600       || GET_CODE (op) == LABEL_REF)
 601     return 1;
 602
 603   if (GET_CODE (op) == CONST
 604       && GET_CODE (XEXP (op, 0)) == PLUS
 605       && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
 606       && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
 607       && INT16_P (INTVAL (XEXP (XEXP (op, 0), 1))))
 608     return 1;
 609
 610   return 0;
 611 }
 612
 613 /* Return true if OP is a signed 8 bit immediate value.  */
 614
 615 int
 616 int8_operand (op, mode)
 617      rtx op;
 618      enum machine_mode mode ATTRIBUTE_UNUSED;
 619 {
 620   if (GET_CODE (op) != CONST_INT)
 621     return 0;
 622   return INT8_P (INTVAL (op));
 623 }
 624
 625 /* Return true if OP is a signed 16 bit immediate value
 626    useful in comparisons.  */
 627
 628 int
 629 cmp_int16_operand (op, mode)
 630      rtx op;
 631      enum machine_mode mode ATTRIBUTE_UNUSED;
 632 {
 633   if (GET_CODE (op) != CONST_INT)
 634     return 0;
 635   return CMP_INT16_P (INTVAL (op));
 636 }
 637
 638 /* Return true if OP is an unsigned 16 bit immediate value.  */
 639
 640 int
 641 uint16_operand (op, mode)
 642      rtx op;
 643      enum machine_mode mode ATTRIBUTE_UNUSED;
 644 {
 645   if (GET_CODE (op) != CONST_INT)
 646     return 0;
 647   return UINT16_P (INTVAL (op));
 648 }
 649
 650 /* Return true if OP is a register or signed 16 bit value.  */
 651
 652 int
 653 reg_or_int16_operand (op, mode)
 654      rtx op;
 655      enum machine_mode mode;
 656 {
 657   if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
 658     return register_operand (op, mode);
 659   if (GET_CODE (op) != CONST_INT)
 660     return 0;
 661   return INT16_P (INTVAL (op));
 662 }
 663
 664 /* Return true if OP is a register or an unsigned 16 bit value.  */
 665
 666 int
 667 reg_or_uint16_operand (op, mode)
 668      rtx op;
 669      enum machine_mode mode;
 670 {
 671   if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
 672     return register_operand (op, mode);
 673   if (GET_CODE (op) != CONST_INT)
 674     return 0;
 675   return UINT16_P (INTVAL (op));
 676 }
 677
 678 /* Return true if OP is a register or an integer value that can be
 679    used is SEQ/SNE.  We can use either XOR of the value or ADD of
 680    the negative of the value for the constant.  Don't allow 0,
 681    because that is special cased.  */
 682
 683 int
 684 reg_or_eq_int16_operand (op, mode)
 685      rtx op;
 686      enum machine_mode mode;
 687 {
 688   HOST_WIDE_INT value;
 689
 690   if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
 691     return register_operand (op, mode);
 692
 693   if (GET_CODE (op) != CONST_INT)
 694     return 0;
 695
 696   value = INTVAL (op);
 697   return (value != 0) && (UINT16_P (value) || CMP_INT16_P (-value));
 698 }
 699
 700 /* Return true if OP is a register or signed 16 bit value for compares.  */
 701
 702 int
 703 reg_or_cmp_int16_operand (op, mode)
 704      rtx op;
 705      enum machine_mode mode;
 706 {
 707   if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
 708     return register_operand (op, mode);
 709   if (GET_CODE (op) != CONST_INT)
 710     return 0;
 711   return CMP_INT16_P (INTVAL (op));
 712 }
 713
 714 /* Return true if OP is a const_int requiring two instructions to load.  */
 715
 716 int
 717 two_insn_const_operand (op, mode)
 718      rtx op;
 719      enum machine_mode mode ATTRIBUTE_UNUSED;
 720 {
 721   if (GET_CODE (op) != CONST_INT)
 722     return 0;
 723   if (INT16_P (INTVAL (op))
 724       || UINT24_P (INTVAL (op))
 725       || UPPER16_P (INTVAL (op)))
 726     return 0;
 727   return 1;
 728 }
 729
 730 /* Return true if OP is an acceptable argument for a single word
 731    move source.  */
 732
 733 int
 734 move_src_operand (op, mode)
 735      rtx op;
 736      enum machine_mode mode;
 737 {
 738   switch (GET_CODE (op))
 739     {
 740     case SYMBOL_REF :
 741     case CONST :
 742       return addr24_operand (op, mode);
 743     case CONST_INT :
 744       /* ??? We allow more cse opportunities if we only allow constants
 745          loadable with one insn, and split the rest into two.  The instances
 746          where this would help should be rare and the current way is
 747          simpler.  */
 748       return INT32_P (INTVAL (op));
 749     case LABEL_REF :
 750       return TARGET_ADDR24;
 751     case CONST_DOUBLE :
 752       if (mode == SFmode)
 753         return 1;
 754       else if (mode == SImode)
 755         {
 756           /* Large unsigned constants are represented as const_double's.  */
 757           unsigned HOST_WIDE_INT low, high;
 758
 759           low = CONST_DOUBLE_LOW (op);
 760           high = CONST_DOUBLE_HIGH (op);
 761           return high == 0 && low <= 0xffffffff;
 762         }
 763       else
 764         return 0;
 765     case REG :
 766       return register_operand (op, mode);
 767     case SUBREG :
 768       /* (subreg (mem ...) ...) can occur here if the inner part was once a
 769          pseudo-reg and is now a stack slot.  */
 770       if (GET_CODE (SUBREG_REG (op)) == MEM)
 771         return address_operand (XEXP (SUBREG_REG (op), 0), mode);
 772       else
 773         return register_operand (op, mode);
 774     case MEM :
 775       if (GET_CODE (XEXP (op, 0)) == PRE_INC
 776           || GET_CODE (XEXP (op, 0)) == PRE_DEC)
 777         return 0;               /* loads can't do pre-{inc,dec} */
 778       return address_operand (XEXP (op, 0), mode);
 779     default :
 780       return 0;
 781     }
 782 }
 783
 784 /* Return true if OP is an acceptable argument for a double word
 785    move source.  */
 786
 787 int
 788 move_double_src_operand (op, mode)
 789      rtx op;
 790      enum machine_mode mode;
 791 {
 792   switch (GET_CODE (op))
 793     {
 794     case CONST_INT :
 795     case CONST_DOUBLE :
 796       return 1;
 797     case REG :
 798       return register_operand (op, mode);
 799     case SUBREG :
 800       /* (subreg (mem ...) ...) can occur here if the inner part was once a
 801          pseudo-reg and is now a stack slot.  */
 802       if (GET_CODE (SUBREG_REG (op)) == MEM)
 803         return move_double_src_operand (SUBREG_REG (op), mode);
 804       else
 805         return register_operand (op, mode);
 806     case MEM :
 807       /* Disallow auto inc/dec for now.  */
 808       if (GET_CODE (XEXP (op, 0)) == PRE_DEC
 809           || GET_CODE (XEXP (op, 0)) == PRE_INC)
 810         return 0;
 811       return address_operand (XEXP (op, 0), mode);
 812     default :
 813       return 0;
 814     }
 815 }
 816
 817 /* Return true if OP is an acceptable argument for a move destination.  */
 818
 819 int
 820 move_dest_operand (op, mode)
 821      rtx op;
 822      enum machine_mode mode;
 823 {
 824   switch (GET_CODE (op))
 825     {
 826     case REG :
 827       return register_operand (op, mode);
 828     case SUBREG :
 829       /* (subreg (mem ...) ...) can occur here if the inner part was once a
 830          pseudo-reg and is now a stack slot.  */
 831       if (GET_CODE (SUBREG_REG (op)) == MEM)
 832         return address_operand (XEXP (SUBREG_REG (op), 0), mode);
 833       else
 834         return register_operand (op, mode);
 835     case MEM :
 836       if (GET_CODE (XEXP (op, 0)) == POST_INC)
 837         return 0;               /* stores can't do post inc */
 838       return address_operand (XEXP (op, 0), mode);
 839     default :
 840       return 0;
 841     }
 842 }
 843
 844 /* Return 1 if OP is a DImode const we want to handle inline.
 845    This must match the code in the movdi pattern.
 846    It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER.  */
 847
 848 int
 849 easy_di_const (op)
 850      rtx op;
 851 {
 852   rtx high_rtx, low_rtx;
 853   HOST_WIDE_INT high, low;
 854
 855   split_double (op, &high_rtx, &low_rtx);
 856   high = INTVAL (high_rtx);
 857   low = INTVAL (low_rtx);
 858   /* Pick constants loadable with 2 16 bit `ldi' insns.  */
 859   if (high >= -128 && high <= 127
 860       && low >= -128 && low <= 127)
 861     return 1;
 862   return 0;
 863 }
 864
 865 /* Return 1 if OP is a DFmode const we want to handle inline.
 866    This must match the code in the movdf pattern.
 867    It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER.  */
 868
 869 int
 870 easy_df_const (op)
 871      rtx op;
 872 {
 873   REAL_VALUE_TYPE r;
 874   long l[2];
 875
 876   REAL_VALUE_FROM_CONST_DOUBLE (r, op);
 877   REAL_VALUE_TO_TARGET_DOUBLE (r, l);
 878   if (l[0] == 0 && l[1] == 0)
 879     return 1;
 880   if ((l[0] & 0xffff) == 0 && l[1] == 0)
 881     return 1;
 882   return 0;
 883 }
 884
 885 /* Return 1 if OP is an EQ or NE comparison operator.  */
 886
 887 int
 888 eqne_comparison_operator (op, mode)
 889     rtx op;
 890     enum machine_mode mode ATTRIBUTE_UNUSED;
 891 {
 892   enum rtx_code code = GET_CODE (op);
 893
 894   if (GET_RTX_CLASS (code) != '<')
 895     return 0;
 896   return (code == EQ || code == NE);
 897 }
 898
 899 /* Return 1 if OP is a signed comparison operator.  */
 900
 901 int
 902 signed_comparison_operator (op, mode)
 903     rtx op;
 904     enum machine_mode mode ATTRIBUTE_UNUSED;
 905 {
 906   enum rtx_code code = GET_CODE (op);
 907
 908   if (GET_RTX_CLASS (code) != '<')
 909     return 0;
 910   return (code == EQ || code == NE
 911           || code == LT || code == LE || code == GT || code == GE);
 912 }
 913
 914 /* Return 1 if OP is (mem (reg ...)).
 915    This is used in insn length calcs.  */
 916
 917 int
 918 memreg_operand (op, mode)
 919      rtx op;
 920      enum machine_mode mode ATTRIBUTE_UNUSED;
 921 {
 922   return GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == REG;
 923 }
 924
 925 /* Return true if OP is an acceptable input argument for a zero/sign extend
 926    operation.  */
 927
 928 int
 929 extend_operand (op, mode)
 930      rtx op;
 931      enum machine_mode mode;
 932 {
 933   rtx addr;
 934
 935   switch (GET_CODE (op))
 936     {
 937     case REG :
 938     case SUBREG :
 939       return register_operand (op, mode);
 940
 941     case MEM :
 942       addr = XEXP (op, 0);
 943       if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
 944         return 0;               /* loads can't do pre inc/pre dec */
 945
 946       return address_operand (addr, mode);
 947
 948     default :
 949       return 0;
 950     }
 951 }
 952
 953 /* Return non-zero if the operand is an insn that is a small insn.
 954    Allow const_int 0 as well, which is a placeholder for NOP slots.  */
 955
 956 int
 957 small_insn_p (op, mode)
 958      rtx op;
 959      enum machine_mode mode ATTRIBUTE_UNUSED;
 960 {
 961   if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
 962     return 1;
 963
 964   if (GET_RTX_CLASS (GET_CODE (op)) != 'i')
 965     return 0;
 966
 967   return get_attr_length (op) == 2;
 968 }
 969
 970 /* Return non-zero if the operand is an insn that is a large insn.  */
 971
 972 int
 973 large_insn_p (op, mode)
 974      rtx op;
 975      enum machine_mode mode ATTRIBUTE_UNUSED;
 976 {
 977   if (GET_RTX_CLASS (GET_CODE (op)) != 'i')
 978     return 0;
 979
 980   return get_attr_length (op) != 2;
 981 }
 982
 983 \f
 984 /* Comparisons.  */
 985
 986 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
 987    return the mode to be used for the comparison.  */
 988
 989 int
 990 m32r_select_cc_mode (op, x, y)
 991      int op ATTRIBUTE_UNUSED;
 992      rtx x ATTRIBUTE_UNUSED;
 993      rtx y ATTRIBUTE_UNUSED;
 994 {
 995   return (int) CCmode;
 996 }
 997
 998 /* X and Y are two things to compare using CODE.  Emit the compare insn and
 999    return the rtx for compare [arg0 of the if_then_else].
1000    If need_compare is true then the comparison insn must be generated, rather
1001    than being susummed into the following branch instruction.  */
1002
1003 rtx
1004 gen_compare (code, x, y, need_compare)
1005      enum rtx_code code;
1006      rtx x, y;
1007      int need_compare;
1008 {
1009   enum machine_mode mode = SELECT_CC_MODE (code, x, y);
1010   enum rtx_code compare_code, branch_code;
1011   rtx cc_reg = gen_rtx_REG (mode, CARRY_REGNUM);
1012   int must_swap = 0;
1013
1014   switch (code)
1015     {
1016     case EQ:  compare_code = EQ;  branch_code = NE; break;
1017     case NE:  compare_code = EQ;  branch_code = EQ; break;
1018     case LT:  compare_code = LT;  branch_code = NE; break;
1019     case LE:  compare_code = LT;  branch_code = EQ; must_swap = 1; break;
1020     case GT:  compare_code = LT;  branch_code = NE; must_swap = 1; break;
1021     case GE:  compare_code = LT;  branch_code = EQ; break;
1022     case LTU: compare_code = LTU; branch_code = NE; break;
1023     case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break;
1024     case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break;
1025     case GEU: compare_code = LTU; branch_code = EQ; break;
1026
1027     default:
1028       abort ();
1029     }
1030
1031   if (need_compare)
1032     {
1033       switch (compare_code)
1034         {
1035         case EQ:
1036           if (GET_CODE (y) == CONST_INT
1037               && CMP_INT16_P (INTVAL (y))               /* reg equal to small const.  */
1038               && y != const0_rtx)
1039             {
1040               rtx tmp = gen_reg_rtx (SImode);
1041
1042               emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
1043               x = tmp;
1044               y = const0_rtx;
1045             }
1046           else if (CONSTANT_P (y))                      /* reg equal to const.  */
1047             {
1048               rtx tmp = force_reg (GET_MODE (x), y);
1049               y = tmp;
1050             }
1051
1052           if (register_operand (y, SImode)              /* reg equal to reg.  */
1053               || y == const0_rtx)                       /* req equal to zero. */
1054             {
1055               emit_insn (gen_cmp_eqsi_insn (x, y));
1056
1057               return gen_rtx (code, mode, cc_reg, const0_rtx);
1058             }
1059           break;
1060
1061         case LT:
1062           if (register_operand (y, SImode)
1063               || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1064             {
1065               rtx tmp = gen_reg_rtx (SImode);         /* reg compared to reg. */
1066
1067               switch (code)
1068                 {
1069                 case LT:
1070                   emit_insn (gen_cmp_ltsi_insn (x, y));
1071                   code = EQ;
1072                   break;
1073                 case LE:
1074                   if (y == const0_rtx)
1075                     tmp = const1_rtx;
1076                   else
1077                     emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1078                   emit_insn (gen_cmp_ltsi_insn (x, tmp));
1079                   code = EQ;
1080                   break;
1081                 case GT:
1082                   if (GET_CODE (y) == CONST_INT)
1083                     tmp = gen_rtx (PLUS, SImode, y, const1_rtx);
1084                   else
1085                     emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1086                   emit_insn (gen_cmp_ltsi_insn (x, tmp));
1087                   code = NE;
1088                   break;
1089                 case GE:
1090                   emit_insn (gen_cmp_ltsi_insn (x, y));
1091                   code = NE;
1092                   break;
1093                 default:
1094                   abort ();
1095                 }
1096
1097               return gen_rtx (code, mode, cc_reg, const0_rtx);
1098             }
1099           break;
1100
1101         case LTU:
1102           if (register_operand (y, SImode)
1103               || (GET_CODE (y) == CONST_INT && CMP_INT16_P (INTVAL (y))))
1104             {
1105               rtx tmp = gen_reg_rtx (SImode);         /* reg (unsigned) compared to reg. */
1106
1107               switch (code)
1108                 {
1109                 case LTU:
1110                   emit_insn (gen_cmp_ltusi_insn (x, y));
1111                   code = EQ;
1112                   break;
1113                 case LEU:
1114                   if (y == const0_rtx)
1115                     tmp = const1_rtx;
1116                   else
1117                     emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1118                   emit_insn (gen_cmp_ltusi_insn (x, tmp));
1119                   code = EQ;
1120                   break;
1121                 case GTU:
1122                   if (GET_CODE (y) == CONST_INT)
1123                     tmp = gen_rtx (PLUS, SImode, y, const1_rtx);
1124                   else
1125                     emit_insn (gen_cmp_ne_small_const_insn (tmp, y, const1_rtx));
1126                   emit_insn (gen_cmp_ltusi_insn (x, tmp));
1127                   code = NE;
1128                   break;
1129                 case GEU:
1130                   emit_insn (gen_cmp_ltusi_insn (x, y));
1131                   code = NE;
1132                   break;
1133                 default:
1134                   abort();
1135                 }
1136
1137               return gen_rtx (code, mode, cc_reg, const0_rtx);
1138             }
1139           break;
1140
1141         default:
1142           abort();
1143         }
1144     }
1145   else
1146     {
1147       /* reg/reg equal comparison */
1148       if (compare_code == EQ
1149           && register_operand (y, SImode))
1150         return gen_rtx (code, mode, x, y);
1151
1152       /* reg/zero signed comparison */
1153       if ((compare_code == EQ || compare_code == LT)
1154           && y == const0_rtx)
1155         return gen_rtx (code, mode, x, y);
1156
1157       /* reg/smallconst equal comparison */
1158       if (compare_code == EQ
1159           && GET_CODE (y) == CONST_INT
1160           && CMP_INT16_P (INTVAL (y)))
1161         {
1162           rtx tmp = gen_reg_rtx (SImode);
1163           emit_insn (gen_cmp_ne_small_const_insn (tmp, x, y));
1164           return gen_rtx (code, mode, tmp, const0_rtx);
1165         }
1166
1167       /* reg/const equal comparison */
1168       if (compare_code == EQ
1169           && CONSTANT_P (y))
1170         {
1171           rtx tmp = force_reg (GET_MODE (x), y);
1172           return gen_rtx (code, mode, x, tmp);
1173         }
1174     }
1175
1176   if (CONSTANT_P (y))
1177     {
1178       if (must_swap)
1179         y = force_reg (GET_MODE (x), y);
1180       else
1181         {
1182           int ok_const =
1183             (code == LTU || code == LEU || code == GTU || code == GEU)
1184             ? uint16_operand (y, GET_MODE (y))
1185             : reg_or_cmp_int16_operand (y, GET_MODE (y));
1186
1187           if (! ok_const)
1188             y = force_reg (GET_MODE (x), y);
1189         }
1190     }
1191
1192   switch (compare_code)
1193     {
1194     case EQ :
1195       emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y));
1196       break;
1197     case LT :
1198       emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y));
1199       break;
1200     case LTU :
1201       emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y));
1202       break;
1203
1204     default:
1205       abort ();
1206     }
1207
1208   return gen_rtx (branch_code, VOIDmode, cc_reg, CONST0_RTX (mode));
1209 }
1210 \f
1211 /* Split a 2 word move (DI or DF) into component parts.  */
1212
1213 rtx
1214 gen_split_move_double (operands)
1215      rtx operands[];
1216 {
1217   enum machine_mode mode = GET_MODE (operands[0]);
1218   rtx dest = operands[0];
1219   rtx src  = operands[1];
1220   rtx val;
1221
1222   /* We might have (SUBREG (MEM)) here, so just get rid of the
1223      subregs to make this code simpler.  It is safe to call
1224      alter_subreg any time after reload.  */
1225   if (GET_CODE (dest) == SUBREG)
1226     dest = alter_subreg (dest);
1227   if (GET_CODE (src) == SUBREG)
1228     src = alter_subreg (src);
1229
1230   start_sequence ();
1231   if (GET_CODE (dest) == REG)
1232     {
1233       int dregno = REGNO (dest);
1234
1235       /* reg = reg */
1236       if (GET_CODE (src) == REG)
1237         {
1238           int sregno = REGNO (src);
1239
1240           int reverse = (dregno == sregno + 1);
1241
1242           /* We normally copy the low-numbered register first.  However, if
1243              the first register operand 0 is the same as the second register of
1244              operand 1, we must copy in the opposite order.  */
1245           emit_insn (gen_rtx_SET (VOIDmode,
1246                                   operand_subword (dest, reverse, TRUE, mode),
1247                                   operand_subword (src,  reverse, TRUE, mode)));
1248
1249           emit_insn (gen_rtx_SET (VOIDmode,
1250                                   operand_subword (dest, !reverse, TRUE, mode),
1251                                   operand_subword (src,  !reverse, TRUE, mode)));
1252         }
1253
1254       /* reg = constant */
1255       else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
1256         {
1257           rtx words[2];
1258           split_double (src, &words[0], &words[1]);
1259           emit_insn (gen_rtx_SET (VOIDmode,
1260                                   operand_subword (dest, 0, TRUE, mode),
1261                                   words[0]));
1262
1263           emit_insn (gen_rtx_SET (VOIDmode,
1264                                   operand_subword (dest, 1, TRUE, mode),
1265                                   words[1]));
1266         }
1267
1268       /* reg = mem */
1269       else if (GET_CODE (src) == MEM)
1270         {
1271           /* If the high-address word is used in the address, we must load it
1272              last.  Otherwise, load it first.  */
1273           rtx addr = XEXP (src, 0);
1274           int reverse = (refers_to_regno_p (dregno, dregno+1, addr, 0) != 0);
1275
1276           /* We used to optimize loads from single registers as
1277
1278                 ld r1,r3+; ld r2,r3
1279
1280              if r3 were not used subsequently.  However, the REG_NOTES aren't
1281              propigated correctly by the reload phase, and it can cause bad
1282              code to be generated.  We could still try:
1283
1284                 ld r1,r3+; ld r2,r3; addi r3,-4
1285
1286              which saves 2 bytes and doesn't force longword alignment.  */
1287           emit_insn (gen_rtx_SET (VOIDmode,
1288                                   operand_subword (dest, reverse, TRUE, mode),
1289                                   change_address (src, SImode,
1290                                                   plus_constant (addr,
1291                                                                  reverse * UNITS_PER_WORD))));
1292
1293           emit_insn (gen_rtx_SET (VOIDmode,
1294                                   operand_subword (dest, !reverse, TRUE, mode),
1295                                   change_address (src, SImode,
1296                                                   plus_constant (addr,
1297                                                                  (!reverse) * UNITS_PER_WORD))));
1298         }
1299
1300       else
1301         abort ();
1302     }
1303
1304   /* mem = reg */
1305   /* We used to optimize loads from single registers as
1306
1307         st r1,r3; st r2,+r3
1308
1309      if r3 were not used subsequently.  However, the REG_NOTES aren't
1310      propigated correctly by the reload phase, and it can cause bad
1311      code to be generated.  We could still try:
1312
1313         st r1,r3; st r2,+r3; addi r3,-4
1314
1315      which saves 2 bytes and doesn't force longword alignment.  */
1316   else if (GET_CODE (dest) == MEM && GET_CODE (src) == REG)
1317     {
1318       rtx addr = XEXP (dest, 0);
1319
1320       emit_insn (gen_rtx_SET (VOIDmode,
1321                               change_address (dest, SImode, addr),
1322                               operand_subword (src, 0, TRUE, mode)));
1323
1324       emit_insn (gen_rtx_SET (VOIDmode,
1325                               change_address (dest, SImode,
1326                                               plus_constant (addr, UNITS_PER_WORD)),
1327                               operand_subword (src, 1, TRUE, mode)));
1328     }
1329
1330   else
1331     abort ();
1332
1333   val = gen_sequence ();
1334   end_sequence ();
1335   return val;
1336 }
1337
1338 \f
1339 /* Implements the FUNCTION_ARG_PARTIAL_NREGS macro.  */
1340
1341 int
1342 function_arg_partial_nregs (cum, mode, type, named)
1343      CUMULATIVE_ARGS *cum;
1344      enum machine_mode mode;
1345      tree type;
1346      int named ATTRIBUTE_UNUSED;
1347 {
1348   int ret;
1349   int size = (((mode == BLKmode && type)
1350                ? int_size_in_bytes (type)
1351                : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
1352
1353   if (*cum >= M32R_MAX_PARM_REGS)
1354     ret = 0;
1355   else if (*cum + size > M32R_MAX_PARM_REGS)
1356     ret = (*cum + size) - M32R_MAX_PARM_REGS;
1357   else
1358     ret = 0;
1359
1360   return ret;
1361 }
1362
1363 /* Do any needed setup for a variadic function.  For the M32R, we must
1364    create a register parameter block, and then copy any anonymous arguments
1365    in registers to memory.
1366
1367    CUM has not been updated for the last named argument which has type TYPE
1368    and mode MODE, and we rely on this fact.  */
1369
1370 void
1371 m32r_setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl)
1372      CUMULATIVE_ARGS *cum;
1373      enum machine_mode mode;
1374      tree type;
1375      int *pretend_size;
1376      int no_rtl;
1377 {
1378   int first_anon_arg;
1379
1380   if (no_rtl)
1381     return;
1382
1383   /* All BLKmode values are passed by reference.  */
1384   if (mode == BLKmode)
1385     abort ();
1386
1387   /* We must treat `__builtin_va_alist' as an anonymous arg.  */
1388   if (current_function_varargs)
1389     first_anon_arg = *cum;
1390   else
1391     first_anon_arg = (ROUND_ADVANCE_CUM (*cum, mode, type)
1392                       + ROUND_ADVANCE_ARG (mode, type));
1393
1394   if (first_anon_arg < M32R_MAX_PARM_REGS)
1395     {
1396       /* Note that first_reg_offset < M32R_MAX_PARM_REGS.  */
1397       int first_reg_offset = first_anon_arg;
1398       /* Size in words to "pretend" allocate.  */
1399       int size = M32R_MAX_PARM_REGS - first_reg_offset;
1400       rtx regblock;
1401
1402       regblock = gen_rtx_MEM (BLKmode,
1403                               plus_constant (arg_pointer_rtx,
1404                                              FIRST_PARM_OFFSET (0)));
1405       MEM_ALIAS_SET (regblock) = get_varargs_alias_set ();
1406       move_block_from_reg (first_reg_offset, regblock,
1407                            size, size * UNITS_PER_WORD);
1408
1409       *pretend_size = (size * UNITS_PER_WORD);
1410     }
1411 }
1412
1413 \f
1414 /* Implement `va_arg'.  */
1415
1416 rtx
1417 m32r_va_arg (valist, type)
1418      tree valist, type;
1419 {
1420   HOST_WIDE_INT size, rsize;
1421   tree t;
1422   rtx addr_rtx;
1423
1424   size = int_size_in_bytes (type);
1425   rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
1426
1427   if (size > 8)
1428     {
1429       tree type_ptr, type_ptr_ptr;
1430
1431       /* Pass by reference.  */
1432
1433       type_ptr = build_pointer_type (type);
1434       type_ptr_ptr = build_pointer_type (type_ptr);
1435
1436       t = build (POSTINCREMENT_EXPR, va_list_type_node, valist,
1437                  build_int_2 (UNITS_PER_WORD, 0));
1438       TREE_SIDE_EFFECTS (t) = 1;
1439       t = build1 (NOP_EXPR, type_ptr_ptr, t);
1440       TREE_SIDE_EFFECTS (t) = 1;
1441       t = build1 (INDIRECT_REF, type_ptr, t);
1442
1443       addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1444     }
1445   else
1446     {
1447       /* Pass by value.  */
1448
1449       if (size < UNITS_PER_WORD)
1450         {
1451           /* Care for bigendian correction on the aligned address.  */
1452           t = build (PLUS_EXPR, ptr_type_node, valist,
1453                      build_int_2 (rsize - size, 0));
1454           addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1455           addr_rtx = copy_to_reg (addr_rtx);
1456
1457           /* Increment AP.  */
1458           t = build (PLUS_EXPR, va_list_type_node, valist,
1459                      build_int_2 (rsize, 0));
1460           t = build (MODIFY_EXPR, va_list_type_node, valist, t);
1461           TREE_SIDE_EFFECTS (t) = 1;
1462           expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
1463         }
1464       else
1465         {
1466           t = build (POSTINCREMENT_EXPR, va_list_type_node, valist,
1467                      build_int_2 (rsize, 0));
1468           TREE_SIDE_EFFECTS (t) = 1;
1469           addr_rtx = expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1470         }
1471     }
1472
1473   return addr_rtx;
1474 }
1475 \f
1476 int
1477 m32r_adjust_cost (insn, link, dep_insn, cost)
1478      rtx insn ATTRIBUTE_UNUSED;
1479      rtx link ATTRIBUTE_UNUSED;
1480      rtx dep_insn ATTRIBUTE_UNUSED;
1481      int cost;
1482 {
1483   return cost;
1484 }
1485
1486 \f
1487 /* A C statement (sans semicolon) to update the integer scheduling
1488    priority `INSN_PRIORITY(INSN)'.  Reduce the priority to execute
1489    the INSN earlier, increase the priority to execute INSN later.
1490    Do not define this macro if you do not need to adjust the
1491    scheduling priorities of insns.
1492
1493    On the m32r, increase the priority of long instructions so that
1494    the short instructions are scheduled ahead of the long ones.  */
1495
1496 int
1497 m32r_adjust_priority (insn, priority)
1498      rtx insn;
1499      int priority;
1500 {
1501   if (GET_RTX_CLASS (GET_CODE (insn)) == 'i')
1502     {
1503       enum rtx_code code = GET_CODE (PATTERN (insn));
1504       if (code != USE && code != CLOBBER && code != ADDR_VEC
1505           && get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1506         priority <<= 3;
1507     }
1508
1509   return priority;
1510 }
1511
1512 \f
1513 /* Initialize for scheduling a group of instructions.  */
1514
1515 void
1516 m32r_sched_init (stream, verbose)
1517      FILE * stream ATTRIBUTE_UNUSED;
1518      int verbose ATTRIBUTE_UNUSED;
1519 {
1520   m32r_sched_odd_word_p = FALSE;
1521 }
1522
1523 \f
1524 /* Reorder the schedulers priority list if needed */
1525
1526 void
1527 m32r_sched_reorder (stream, verbose, ready, n_ready)
1528      FILE * stream;
1529      int verbose;
1530      rtx * ready;
1531      int n_ready;
1532 {
1533   if (TARGET_DEBUG)
1534     return;
1535
1536   if (verbose <= 7)
1537     stream = (FILE *)0;
1538
1539   if (stream)
1540     fprintf (stream,
1541              ";;\t\t::: Looking at %d insn(s) on ready list, boundary is %s word\n",
1542              n_ready,
1543              (m32r_sched_odd_word_p) ? "odd" : "even");
1544
1545   if (n_ready > 1)
1546     {
1547       rtx * long_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1548       rtx * long_tail = long_head;
1549       rtx * short_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1550       rtx * short_tail = short_head;
1551       rtx * new_head = (rtx *) alloca (sizeof (rtx) * n_ready);
1552       rtx * new_tail = new_head + (n_ready - 1);
1553       int   i;
1554
1555       /* Loop through the instructions, classifing them as short/long.  Try
1556          to keep 2 short together and/or 1 long.  Note, the ready list is
1557          actually ordered backwards, so keep it in that manner.  */
1558       for (i = n_ready-1; i >= 0; i--)
1559         {
1560           rtx insn = ready[i];
1561           enum rtx_code code;
1562
1563           if (GET_RTX_CLASS (GET_CODE (insn)) != 'i'
1564               || (code = GET_CODE (PATTERN (insn))) == USE
1565               || code == CLOBBER || code == ADDR_VEC)
1566             {
1567               /* Dump all current short/long insns just in case */
1568               while (long_head != long_tail)
1569                 *new_tail-- = *long_head++;
1570
1571               while (short_head != short_tail)
1572                 *new_tail-- = *short_head++;
1573
1574               *new_tail-- = insn;
1575               if (stream)
1576                 fprintf (stream,
1577                          ";;\t\t::: Skipping non instruction %d\n",
1578                          INSN_UID (insn));
1579
1580             }
1581
1582           else
1583             {
1584               if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1585                 *long_tail++ = insn;
1586
1587               else
1588                 *short_tail++ = insn;
1589             }
1590         }
1591
1592       /* If we are on an odd word, emit a single short instruction if
1593          we can */
1594       if (m32r_sched_odd_word_p && short_head != short_tail)
1595         *new_tail-- = *short_head++;
1596
1597       /* Now dump out all of the long instructions */
1598       while (long_head != long_tail)
1599         *new_tail-- = *long_head++;
1600
1601       /* Now dump out all of the short instructions */
1602       while (short_head != short_tail)
1603         *new_tail-- = *short_head++;
1604
1605       if (new_tail+1 != new_head)
1606         abort ();
1607
1608       bcopy ((char *) new_head, (char *) ready, sizeof (rtx) * n_ready);
1609       if (stream)
1610         {
1611 #ifdef HAIFA
1612           fprintf (stream, ";;\t\t::: New ready list:               ");
1613           debug_ready_list (ready, n_ready);
1614 #else
1615           int i;
1616           for (i = 0; i < n_ready; i++)
1617             {
1618               rtx insn = ready[i];
1619               enum rtx_code code;
1620
1621               fprintf (stream, " %d", INSN_UID (ready[i]));
1622               if (GET_RTX_CLASS (GET_CODE (insn)) != 'i'
1623                   || (code = GET_CODE (PATTERN (insn))) == USE
1624                   || code == CLOBBER || code == ADDR_VEC)
1625                 fputs ("(?)", stream);
1626
1627               else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1628                 fputs ("(l)", stream);
1629
1630               else
1631                 fputs ("(s)", stream);
1632             }
1633
1634           fprintf (stream, "\n");
1635 #endif
1636         }
1637     }
1638 }
1639
1640 \f
1641 /* If we have a machine that can issue a variable # of instructions
1642    per cycle, indicate how many more instructions can be issued
1643    after the current one.  */
1644 int
1645 m32r_sched_variable_issue (stream, verbose, insn, how_many)
1646      FILE * stream;
1647      int verbose;
1648      rtx insn;
1649      int how_many;
1650 {
1651   int orig_odd_word_p = m32r_sched_odd_word_p;
1652   int short_p = FALSE;
1653
1654   how_many--;
1655   if (how_many > 0 && !TARGET_DEBUG)
1656     {
1657       if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
1658         how_many++;
1659
1660       else if (GET_CODE (PATTERN (insn)) == USE
1661                || GET_CODE (PATTERN (insn)) == CLOBBER
1662                || GET_CODE (PATTERN (insn)) == ADDR_VEC)
1663         how_many++;
1664
1665       else if (get_attr_insn_size (insn) != INSN_SIZE_SHORT)
1666         {
1667           how_many = 0;
1668           m32r_sched_odd_word_p = 0;
1669         }
1670       else
1671         {
1672           m32r_sched_odd_word_p = !m32r_sched_odd_word_p;
1673           short_p = TRUE;
1674         }
1675     }
1676
1677   if (verbose > 7 && stream)
1678     fprintf (stream,
1679              ";;\t\t::: %s insn %d starts on an %s word, can emit %d more instruction(s)\n",
1680              short_p ? "short" : "long",
1681              INSN_UID (insn),
1682              orig_odd_word_p ? "odd" : "even",
1683              how_many);
1684
1685   return how_many;
1686 }
1687 \f
1688 /* Cost functions.  */
1689
1690 /* Provide the costs of an addressing mode that contains ADDR.
1691    If ADDR is not a valid address, its cost is irrelevant.
1692
1693    This function is trivial at the moment.  This code doesn't live
1694    in m32r.h so it's easy to experiment.  */
1695
1696 int
1697 m32r_address_cost (addr)
1698      rtx addr ATTRIBUTE_UNUSED;
1699 {
1700   return 1;
1701 }
1702 \f
1703 /* Type of function DECL.
1704
1705    The result is cached.  To reset the cache at the end of a function,
1706    call with DECL = NULL_TREE.  */
1707
1708 enum m32r_function_type
1709 m32r_compute_function_type (decl)
1710      tree decl;
1711 {
1712   /* Cached value.  */
1713   static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN;
1714   /* Last function we were called for.  */
1715   static tree last_fn = NULL_TREE;
1716
1717   /* Resetting the cached value?  */
1718   if (decl == NULL_TREE)
1719     {
1720       fn_type = M32R_FUNCTION_UNKNOWN;
1721       last_fn = NULL_TREE;
1722       return fn_type;
1723     }
1724
1725   if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN)
1726     return fn_type;
1727
1728   /* Compute function type.  */
1729   fn_type = (lookup_attribute ("interrupt", DECL_MACHINE_ATTRIBUTES (current_function_decl)) != NULL_TREE
1730              ? M32R_FUNCTION_INTERRUPT
1731              : M32R_FUNCTION_NORMAL);
1732
1733   last_fn = decl;
1734   return fn_type;
1735 }
1736 \f/* Function prologue/epilogue handlers.  */
1737
1738 /* M32R stack frames look like:
1739
1740              Before call                       After call
1741         +-----------------------+       +-----------------------+
1742         |                       |       |                       |
1743    high |  local variables,     |       |  local variables,     |
1744    mem  |  reg save area, etc.  |       |  reg save area, etc.  |
1745         |                       |       |                       |
1746         +-----------------------+       +-----------------------+
1747         |                       |       |                       |
1748         |  arguments on stack.  |       |  arguments on stack.  |
1749         |                       |       |                       |
1750   SP+0->+-----------------------+       +-----------------------+
1751                                         |  reg parm save area,  |
1752                                         |  only created for     |
1753                                         |  variable argument    |
1754                                         |  functions            |
1755                                         +-----------------------+
1756                                         |   previous frame ptr  |
1757                                         +-----------------------+
1758                                         |                       |
1759                                         |  register save area   |
1760                                         |                       |
1761                                         +-----------------------+
1762                                         |    return address     |
1763                                         +-----------------------+
1764                                         |                       |
1765                                         |  local variables      |
1766                                         |                       |
1767                                         +-----------------------+
1768                                         |                       |
1769                                         |  alloca allocations   |
1770                                         |                       |
1771                                         +-----------------------+
1772                                         |                       |
1773    low                                  |  arguments on stack   |
1774    memory                               |                       |
1775                                   SP+0->+-----------------------+
1776
1777 Notes:
1778 1) The "reg parm save area" does not exist for non variable argument fns.
1779 2) The "reg parm save area" can be eliminated completely if we saved regs
1780    containing anonymous args separately but that complicates things too
1781    much (so it's not done).
1782 3) The return address is saved after the register save area so as to have as
1783    many insns as possible between the restoration of `lr' and the `jmp lr'.
1784 */
1785
1786 /* Structure to be filled in by m32r_compute_frame_size with register
1787    save masks, and offsets for the current function.  */
1788 struct m32r_frame_info
1789 {
1790   unsigned int total_size;      /* # bytes that the entire frame takes up */
1791   unsigned int extra_size;      /* # bytes of extra stuff */
1792   unsigned int pretend_size;    /* # bytes we push and pretend caller did */
1793   unsigned int args_size;       /* # bytes that outgoing arguments take up */
1794   unsigned int reg_size;        /* # bytes needed to store regs */
1795   unsigned int var_size;        /* # bytes that variables take up */
1796   unsigned int gmask;           /* mask of saved gp registers */
1797   unsigned int save_fp;         /* nonzero if fp must be saved */
1798   unsigned int save_lr;         /* nonzero if lr (return addr) must be saved */
1799   int          initialized;     /* nonzero if frame size already calculated */
1800 };
1801
1802 /* Current frame information calculated by m32r_compute_frame_size.  */
1803 static struct m32r_frame_info current_frame_info;
1804
1805 /* Zero structure to initialize current_frame_info.  */
1806 static struct m32r_frame_info zero_frame_info;
1807
1808 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
1809 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
1810
1811 /* Tell prologue and epilogue if register REGNO should be saved / restored.
1812    The return address and frame pointer are treated separately.
1813    Don't consider them here.  */
1814 #define MUST_SAVE_REGISTER(regno, interrupt_p) \
1815 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \
1816  && (regs_ever_live[regno] && (!call_used_regs[regno] || interrupt_p)))
1817
1818 #define MUST_SAVE_FRAME_POINTER (regs_ever_live[FRAME_POINTER_REGNUM])
1819 #define MUST_SAVE_RETURN_ADDR (regs_ever_live[RETURN_ADDR_REGNUM] || profile_flag)
1820
1821 #define SHORT_INSN_SIZE 2       /* size of small instructions */
1822 #define LONG_INSN_SIZE 4        /* size of long instructions */
1823
1824 /* Return the bytes needed to compute the frame pointer from the current
1825    stack pointer.
1826
1827    SIZE is the size needed for local variables.  */
1828
1829 unsigned int
1830 m32r_compute_frame_size (size)
1831      int size;                  /* # of var. bytes allocated.  */
1832 {
1833   int regno;
1834   unsigned int total_size, var_size, args_size, pretend_size, extra_size;
1835   unsigned int reg_size, frame_size;
1836   unsigned int gmask;
1837   enum m32r_function_type fn_type;
1838   int interrupt_p;
1839
1840   var_size      = M32R_STACK_ALIGN (size);
1841   args_size     = M32R_STACK_ALIGN (current_function_outgoing_args_size);
1842   pretend_size  = current_function_pretend_args_size;
1843   extra_size    = FIRST_PARM_OFFSET (0);
1844   total_size    = extra_size + pretend_size + args_size + var_size;
1845   reg_size      = 0;
1846   gmask         = 0;
1847
1848   /* See if this is an interrupt handler.  Call used registers must be saved
1849      for them too.  */
1850   fn_type = m32r_compute_function_type (current_function_decl);
1851   interrupt_p = M32R_INTERRUPT_P (fn_type);
1852
1853   /* Calculate space needed for registers.  */
1854
1855   for (regno = 0; regno < M32R_MAX_INT_REGS; regno++)
1856     {
1857       if (MUST_SAVE_REGISTER (regno, interrupt_p))
1858         {
1859           reg_size += UNITS_PER_WORD;
1860           gmask |= 1 << regno;
1861         }
1862     }
1863
1864   current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER;
1865   current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR;
1866
1867   reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr)
1868                * UNITS_PER_WORD);
1869   total_size += reg_size;
1870
1871   /* ??? Not sure this is necessary, and I don't think the epilogue
1872      handler will do the right thing if this changes total_size.  */
1873   total_size = M32R_STACK_ALIGN (total_size);
1874
1875   frame_size = total_size - (pretend_size + reg_size);
1876
1877   /* Save computed information.  */
1878   current_frame_info.total_size   = total_size;
1879   current_frame_info.extra_size   = extra_size;
1880   current_frame_info.pretend_size = pretend_size;
1881   current_frame_info.var_size     = var_size;
1882   current_frame_info.args_size    = args_size;
1883   current_frame_info.reg_size     = reg_size;
1884   current_frame_info.gmask        = gmask;
1885   current_frame_info.initialized  = reload_completed;
1886
1887   /* Ok, we're done.  */
1888   return total_size;
1889 }
1890 \f
1891 /* When the `length' insn attribute is used, this macro specifies the
1892    value to be assigned to the address of the first insn in a
1893    function.  If not specified, 0 is used.  */
1894
1895 int
1896 m32r_first_insn_address ()
1897 {
1898   if (! current_frame_info.initialized)
1899     m32r_compute_frame_size (get_frame_size ());
1900
1901   return 0;
1902 }
1903 \f
1904 /* Expand the m32r prologue as a series of insns.  */
1905
1906 void
1907 m32r_expand_prologue ()
1908 {
1909   int regno;
1910   int frame_size;
1911   unsigned int gmask;
1912
1913   if (! current_frame_info.initialized)
1914     m32r_compute_frame_size (get_frame_size ());
1915
1916   gmask = current_frame_info.gmask;
1917
1918   /* These cases shouldn't happen.  Catch them now.  */
1919   if (current_frame_info.total_size == 0 && gmask)
1920     abort ();
1921
1922   /* Allocate space for register arguments if this is a variadic function.  */
1923   if (current_frame_info.pretend_size != 0)
1924     {
1925       /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives
1926          the wrong result on a 64-bit host.  */
1927       HOST_WIDE_INT pretend_size = current_frame_info.pretend_size;
1928       emit_insn (gen_addsi3 (stack_pointer_rtx,
1929                              stack_pointer_rtx,
1930                              GEN_INT (-pretend_size)));
1931     }
1932
1933   /* Save any registers we need to and set up fp.  */
1934
1935   if (current_frame_info.save_fp)
1936     emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx));
1937
1938   gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
1939
1940   /* Save any needed call-saved regs (and call-used if this is an
1941      interrupt handler).  */
1942   for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno)
1943     {
1944       if ((gmask & (1 << regno)) != 0)
1945         emit_insn (gen_movsi_push (stack_pointer_rtx,
1946                                    gen_rtx_REG (Pmode, regno)));
1947     }
1948
1949   if (current_frame_info.save_lr)
1950     emit_insn (gen_movsi_push (stack_pointer_rtx,
1951                                gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)));
1952
1953   /* Allocate the stack frame.  */
1954   frame_size = (current_frame_info.total_size
1955                 - (current_frame_info.pretend_size
1956                    + current_frame_info.reg_size));
1957
1958   if (frame_size == 0)
1959     ; /* nothing to do */
1960   else if (frame_size <= 32768)
1961     emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
1962                            GEN_INT (-frame_size)));
1963   else
1964     {
1965       rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM);
1966       emit_insn (gen_movsi (tmp, GEN_INT (frame_size)));
1967       emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp));
1968     }
1969
1970   if (frame_pointer_needed)
1971     emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx));
1972
1973   if (profile_flag || profile_block_flag)
1974     emit_insn (gen_blockage ());
1975 }
1976
1977 \f
1978 /* Set up the stack and frame pointer (if desired) for the function.
1979    Note, if this is changed, you need to mirror the changes in
1980    m32r_compute_frame_size which calculates the prolog size.  */
1981
1982 void
1983 m32r_output_function_prologue (file, size)
1984      FILE * file;
1985      int    size;
1986 {
1987   enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
1988
1989   /* If this is an interrupt handler, mark it as such.  */
1990   if (M32R_INTERRUPT_P (fn_type))
1991     {
1992       fprintf (file, "\t%s interrupt handler\n",
1993                ASM_COMMENT_START);
1994     }
1995
1996   if (! current_frame_info.initialized)
1997     m32r_compute_frame_size (size);
1998
1999   /* This is only for the human reader.  */
2000   fprintf (file,
2001            "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n",
2002            ASM_COMMENT_START,
2003            current_frame_info.var_size,
2004            current_frame_info.reg_size / 4,
2005            current_frame_info.args_size,
2006            current_frame_info.extra_size);
2007 }
2008 \f
2009 /* Do any necessary cleanup after a function to restore stack, frame,
2010    and regs. */
2011
2012 void
2013 m32r_output_function_epilogue (file, size)
2014      FILE * file;
2015      int    size ATTRIBUTE_UNUSED;
2016 {
2017   int regno;
2018   int noepilogue = FALSE;
2019   int total_size;
2020   enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl);
2021
2022   /* This is only for the human reader.  */
2023   fprintf (file, "\t%s EPILOGUE\n", ASM_COMMENT_START);
2024
2025   if (!current_frame_info.initialized)
2026     abort ();
2027   total_size = current_frame_info.total_size;
2028
2029   if (total_size == 0)
2030     {
2031       rtx insn = get_last_insn ();
2032
2033       /* If the last insn was a BARRIER, we don't have to write any code
2034          because a jump (aka return) was put there.  */
2035       if (GET_CODE (insn) == NOTE)
2036         insn = prev_nonnote_insn (insn);
2037       if (insn && GET_CODE (insn) == BARRIER)
2038         noepilogue = TRUE;
2039     }
2040
2041   if (!noepilogue)
2042     {
2043       unsigned int var_size = current_frame_info.var_size;
2044       unsigned int args_size = current_frame_info.args_size;
2045       unsigned int gmask = current_frame_info.gmask;
2046       int can_trust_sp_p = !current_function_calls_alloca;
2047       const char * sp_str = reg_names[STACK_POINTER_REGNUM];
2048       const char * fp_str = reg_names[FRAME_POINTER_REGNUM];
2049
2050       /* The first thing to do is point the sp at the bottom of the register
2051          save area.  */
2052       if (can_trust_sp_p)
2053         {
2054           unsigned int reg_offset = var_size + args_size;
2055           if (reg_offset == 0)
2056             ; /* nothing to do */
2057           else if (reg_offset < 128)
2058             fprintf (file, "\taddi %s,%s%d\n",
2059                      sp_str, IMMEDIATE_PREFIX, reg_offset);
2060           else if (reg_offset < 32768)
2061             fprintf (file, "\tadd3 %s,%s,%s%d\n",
2062                      sp_str, sp_str, IMMEDIATE_PREFIX, reg_offset);
2063           else
2064             fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2065                      reg_names[PROLOGUE_TMP_REGNUM],
2066                      IMMEDIATE_PREFIX, reg_offset,
2067                      sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
2068         }
2069       else if (frame_pointer_needed)
2070         {
2071           unsigned int reg_offset = var_size + args_size;
2072           if (reg_offset == 0)
2073             fprintf (file, "\tmv %s,%s\n", sp_str, fp_str);
2074           else if (reg_offset < 32768)
2075             fprintf (file, "\tadd3 %s,%s,%s%d\n",
2076                      sp_str, fp_str, IMMEDIATE_PREFIX, reg_offset);
2077           else
2078             fprintf (file, "\tld24 %s,%s%d\n\tadd %s,%s\n",
2079                      reg_names[PROLOGUE_TMP_REGNUM],
2080                      IMMEDIATE_PREFIX, reg_offset,
2081                      sp_str, reg_names[PROLOGUE_TMP_REGNUM]);
2082         }
2083       else
2084         abort ();
2085
2086       if (current_frame_info.save_lr)
2087         fprintf (file, "\tpop %s\n", reg_names[RETURN_ADDR_REGNUM]);
2088
2089       /* Restore any saved registers, in reverse order of course.  */
2090       gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK);
2091       for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno)
2092         {
2093           if ((gmask & (1L << regno)) != 0)
2094             fprintf (file, "\tpop %s\n", reg_names[regno]);
2095         }
2096
2097       if (current_frame_info.save_fp)
2098         fprintf (file, "\tpop %s\n", fp_str);
2099
2100       /* Remove varargs area if present.  */
2101       if (current_frame_info.pretend_size != 0)
2102         fprintf (file, "\taddi %s,%s%d\n",
2103                  sp_str, IMMEDIATE_PREFIX, current_frame_info.pretend_size);
2104
2105       /* Emit the return instruction.  */
2106       if (M32R_INTERRUPT_P (fn_type))
2107         fprintf (file, "\trte\n");
2108       else
2109         fprintf (file, "\tjmp %s\n", reg_names[RETURN_ADDR_REGNUM]);
2110     }
2111
2112 #if 0 /* no longer needed */
2113   /* Ensure the function cleanly ends on a 32 bit boundary.  */
2114   fprintf (file, "\t.fillinsn\n");
2115 #endif
2116
2117   /* Reset state info for each function.  */
2118   current_frame_info = zero_frame_info;
2119   m32r_compute_function_type (NULL_TREE);
2120 }
2121 \f
2122 /* Return non-zero if this function is known to have a null or 1 instruction
2123    epilogue.  */
2124
2125 int
2126 direct_return ()
2127 {
2128   if (!reload_completed)
2129     return FALSE;
2130
2131   if (! current_frame_info.initialized)
2132     m32r_compute_frame_size (get_frame_size ());
2133
2134   return current_frame_info.total_size == 0;
2135 }
2136
2137 \f
2138 /* PIC */
2139
2140 /* Emit special PIC prologues and epilogues.  */
2141
2142 void
2143 m32r_finalize_pic ()
2144 {
2145   /* nothing to do */
2146 }
2147 \f
2148 /* Nested function support.  */
2149
2150 /* Emit RTL insns to initialize the variable parts of a trampoline.
2151    FNADDR is an RTX for the address of the function's pure code.
2152    CXT is an RTX for the static chain value for the function.  */
2153
2154 void
2155 m32r_initialize_trampoline (tramp, fnaddr, cxt)
2156      rtx tramp ATTRIBUTE_UNUSED;
2157      rtx fnaddr ATTRIBUTE_UNUSED;
2158      rtx cxt ATTRIBUTE_UNUSED;
2159 {
2160 }
2161 \f
2162 /* Set the cpu type and print out other fancy things,
2163    at the top of the file.  */
2164
2165 void
2166 m32r_asm_file_start (file)
2167      FILE * file;
2168 {
2169   if (flag_verbose_asm)
2170     fprintf (file, "%s M32R/D special options: -G %d\n",
2171              ASM_COMMENT_START, g_switch_value);
2172 }
2173 \f
2174 /* Print operand X (an rtx) in assembler syntax to file FILE.
2175    CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2176    For `%' followed by punctuation, CODE is the punctuation and X is null.  */
2177
2178 void
2179 m32r_print_operand (file, x, code)
2180      FILE * file;
2181      rtx    x;
2182      int    code;
2183 {
2184   rtx addr;
2185
2186   switch (code)
2187     {
2188       /* The 's' and 'p' codes are used by output_block_move() to
2189          indicate post-increment 's'tores and 'p're-increment loads.  */
2190     case 's':
2191       if (GET_CODE (x) == REG)
2192         fprintf (file, "@+%s", reg_names [REGNO (x)]);
2193       else
2194         output_operand_lossage ("invalid operand to %s code");
2195       return;
2196
2197     case 'p':
2198       if (GET_CODE (x) == REG)
2199         fprintf (file, "@%s+", reg_names [REGNO (x)]);
2200       else
2201         output_operand_lossage ("invalid operand to %p code");
2202       return;
2203
2204     case 'R' :
2205       /* Write second word of DImode or DFmode reference,
2206          register or memory.  */
2207       if (GET_CODE (x) == REG)
2208         fputs (reg_names[REGNO (x)+1], file);
2209       else if (GET_CODE (x) == MEM)
2210         {
2211           fprintf (file, "@(");
2212           /* Handle possible auto-increment.  Since it is pre-increment and
2213              we have already done it, we can just use an offset of four.  */
2214           /* ??? This is taken from rs6000.c I think.  I don't think it is
2215              currently necessary, but keep it around.  */
2216           if (GET_CODE (XEXP (x, 0)) == PRE_INC
2217               || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2218             output_address (plus_constant (XEXP (XEXP (x, 0), 0), 4));
2219           else
2220             output_address (plus_constant (XEXP (x, 0), 4));
2221           fputc (')', file);
2222         }
2223       else
2224         output_operand_lossage ("invalid operand to %R code");
2225       return;
2226
2227     case 'H' : /* High word */
2228     case 'L' : /* Low word */
2229       if (GET_CODE (x) == REG)
2230         {
2231           /* L = least significant word, H = most significant word */
2232           if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
2233             fputs (reg_names[REGNO (x)], file);
2234           else
2235             fputs (reg_names[REGNO (x)+1], file);
2236         }
2237       else if (GET_CODE (x) == CONST_INT
2238                || GET_CODE (x) == CONST_DOUBLE)
2239         {
2240           rtx first, second;
2241
2242           split_double (x, &first, &second);
2243           fprintf (file, HOST_WIDE_INT_PRINT_HEX,
2244                    code == 'L' ? INTVAL (first) : INTVAL (second));
2245         }
2246       else
2247         output_operand_lossage ("invalid operand to %H/%L code");
2248       return;
2249
2250     case 'A' :
2251       {
2252         REAL_VALUE_TYPE d;
2253         char str[30];
2254
2255         if (GET_CODE (x) != CONST_DOUBLE
2256             || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
2257           fatal_insn ("Bad insn for 'A'", x);
2258         REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2259         REAL_VALUE_TO_DECIMAL (d, "%.20e", str);
2260         fprintf (file, "%s", str);
2261         return;
2262       }
2263
2264     case 'B' : /* Bottom half */
2265     case 'T' : /* Top half */
2266       /* Output the argument to a `seth' insn (sets the Top half-word).
2267          For constants output arguments to a seth/or3 pair to set Top and
2268          Bottom halves.  For symbols output arguments to a seth/add3 pair to
2269          set Top and Bottom halves.  The difference exists because for
2270          constants seth/or3 is more readable but for symbols we need to use
2271          the same scheme as `ld' and `st' insns (16 bit addend is signed).  */
2272       switch (GET_CODE (x))
2273         {
2274         case CONST_INT :
2275         case CONST_DOUBLE :
2276           {
2277             rtx first, second;
2278
2279             split_double (x, &first, &second);
2280             x = WORDS_BIG_ENDIAN ? second : first;
2281             fprintf (file,
2282 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
2283                      "0x%x",
2284 #else
2285                      "0x%lx",
2286 #endif
2287                      (code == 'B'
2288                       ? INTVAL (x) & 0xffff
2289                       : (INTVAL (x) >> 16) & 0xffff));
2290           }
2291           return;
2292         case CONST :
2293         case SYMBOL_REF :
2294           if (code == 'B'
2295               && small_data_operand (x, VOIDmode))
2296             {
2297               fputs ("sda(", file);
2298               output_addr_const (file, x);
2299               fputc (')', file);
2300               return;
2301             }
2302           /* fall through */
2303         case LABEL_REF :
2304           fputs (code == 'T' ? "shigh(" : "low(", file);
2305           output_addr_const (file, x);
2306           fputc (')', file);
2307           return;
2308         default :
2309           output_operand_lossage ("invalid operand to %T/%B code");
2310           return;
2311         }
2312       break;
2313
2314     case 'U' :
2315       /* ??? wip */
2316       /* Output a load/store with update indicator if appropriate.  */
2317       if (GET_CODE (x) == MEM)
2318         {
2319           if (GET_CODE (XEXP (x, 0)) == PRE_INC
2320               || GET_CODE (XEXP (x, 0)) == PRE_DEC)
2321             fputs (".a", file);
2322         }
2323       else
2324         output_operand_lossage ("invalid operand to %U code");
2325       return;
2326
2327     case 'N' :
2328       /* Print a constant value negated.  */
2329       if (GET_CODE (x) == CONST_INT)
2330         output_addr_const (file, GEN_INT (- INTVAL (x)));
2331       else
2332         output_operand_lossage ("invalid operand to %N code");
2333       return;
2334
2335     case 'X' :
2336       /* Print a const_int in hex.  Used in comments.  */
2337       if (GET_CODE (x) == CONST_INT)
2338         fprintf (file,
2339 #if HOST_BITS_PER_WIDE_INT == HOST_BITS_PER_INT
2340                  "0x%x",
2341 #else
2342                  "0x%lx",
2343 #endif
2344                  INTVAL (x));
2345       return;
2346
2347     case '#' :
2348       fputs (IMMEDIATE_PREFIX, file);
2349       return;
2350
2351 #if 0 /* ??? no longer used */
2352     case '@' :
2353       fputs (reg_names[SDA_REGNUM], file);
2354       return;
2355 #endif
2356
2357     case 0 :
2358       /* Do nothing special.  */
2359       break;
2360
2361     default :
2362       /* Unknown flag.  */
2363       output_operand_lossage ("invalid operand output code");
2364     }
2365
2366   switch (GET_CODE (x))
2367     {
2368     case REG :
2369       fputs (reg_names[REGNO (x)], file);
2370       break;
2371
2372     case MEM :
2373       addr = XEXP (x, 0);
2374       if (GET_CODE (addr) == PRE_INC)
2375         {
2376           if (GET_CODE (XEXP (addr, 0)) != REG)
2377             fatal_insn ("Pre-increment address is not a register", x);
2378
2379           fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]);
2380         }
2381       else if (GET_CODE (addr) == PRE_DEC)
2382         {
2383           if (GET_CODE (XEXP (addr, 0)) != REG)
2384             fatal_insn ("Pre-decrement address is not a register", x);
2385
2386           fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]);
2387         }
2388       else if (GET_CODE (addr) == POST_INC)
2389         {
2390           if (GET_CODE (XEXP (addr, 0)) != REG)
2391             fatal_insn ("Post-increment address is not a register", x);
2392
2393           fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]);
2394         }
2395       else
2396         {
2397           fputs ("@(", file);
2398           output_address (XEXP (x, 0));
2399           fputc (')', file);
2400         }
2401       break;
2402
2403     case CONST_DOUBLE :
2404       /* We handle SFmode constants here as output_addr_const doesn't.  */
2405       if (GET_MODE (x) == SFmode)
2406         {
2407           REAL_VALUE_TYPE d;
2408           long l;
2409
2410           REAL_VALUE_FROM_CONST_DOUBLE (d, x);
2411           REAL_VALUE_TO_TARGET_SINGLE (d, l);
2412           fprintf (file, "0x%08lx", l);
2413           break;
2414         }
2415
2416       /* Fall through.  Let output_addr_const deal with it.  */
2417
2418     default :
2419       output_addr_const (file, x);
2420       break;
2421     }
2422 }
2423
2424 /* Print a memory address as an operand to reference that memory location.  */
2425
2426 void
2427 m32r_print_operand_address (file, addr)
2428      FILE * file;
2429      rtx    addr;
2430 {
2431   register rtx base;
2432   register rtx index = 0;
2433   int          offset = 0;
2434
2435   switch (GET_CODE (addr))
2436     {
2437     case REG :
2438       fputs (reg_names[REGNO (addr)], file);
2439       break;
2440
2441     case PLUS :
2442       if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
2443         offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
2444       else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
2445         offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
2446       else
2447         base = XEXP (addr, 0), index = XEXP (addr, 1);
2448       if (GET_CODE (base) == REG)
2449         {
2450           /* Print the offset first (if present) to conform to the manual.  */
2451           if (index == 0)
2452             {
2453               if (offset != 0)
2454                 fprintf (file, "%d,", offset);
2455               fputs (reg_names[REGNO (base)], file);
2456             }
2457           /* The chip doesn't support this, but left in for generality.  */
2458           else if (GET_CODE (index) == REG)
2459             fprintf (file, "%s,%s",
2460                      reg_names[REGNO (base)], reg_names[REGNO (index)]);
2461           /* Not sure this can happen, but leave in for now.  */
2462           else if (GET_CODE (index) == SYMBOL_REF)
2463             {
2464               output_addr_const (file, index);
2465               fputc (',', file);
2466               fputs (reg_names[REGNO (base)], file);
2467             }
2468           else
2469             fatal_insn ("Bad address", addr);
2470         }
2471       else if (GET_CODE (base) == LO_SUM)
2472         {
2473           if (index != 0
2474               || GET_CODE (XEXP (base, 0)) != REG)
2475             abort ();
2476           if (small_data_operand (XEXP (base, 1), VOIDmode))
2477             fputs ("sda(", file);
2478           else
2479             fputs ("low(", file);
2480           output_addr_const (file, plus_constant (XEXP (base, 1), offset));
2481           fputs ("),", file);
2482           fputs (reg_names[REGNO (XEXP (base, 0))], file);
2483         }
2484       else
2485         fatal_insn ("Bad address", addr);
2486       break;
2487
2488     case LO_SUM :
2489       if (GET_CODE (XEXP (addr, 0)) != REG)
2490         fatal_insn ("Lo_sum not of register", addr);
2491       if (small_data_operand (XEXP (addr, 1), VOIDmode))
2492         fputs ("sda(", file);
2493       else
2494         fputs ("low(", file);
2495       output_addr_const (file, XEXP (addr, 1));
2496       fputs ("),", file);
2497       fputs (reg_names[REGNO (XEXP (addr, 0))], file);
2498       break;
2499
2500     case PRE_INC :      /* Assume SImode */
2501       fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]);
2502       break;
2503
2504     case PRE_DEC :      /* Assume SImode */
2505       fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]);
2506       break;
2507
2508     case POST_INC :     /* Assume SImode */
2509       fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]);
2510       break;
2511
2512     default :
2513       output_addr_const (file, addr);
2514       break;
2515     }
2516 }
2517
2518 /* Return true if the operands are the constants 0 and 1.  */
2519 int
2520 zero_and_one (operand1, operand2)
2521      rtx operand1;
2522      rtx operand2;
2523 {
2524   return
2525        GET_CODE (operand1) == CONST_INT
2526     && GET_CODE (operand2) == CONST_INT
2527     && (  ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1))
2528         ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0)));
2529 }
2530
2531 /* Return non-zero if the operand is suitable for use in a conditional move sequence.  */
2532 int
2533 conditional_move_operand (operand, mode)
2534      rtx operand;
2535      enum machine_mode mode;
2536 {
2537   /* Only defined for simple integers so far... */
2538   if (mode != SImode && mode != HImode && mode != QImode)
2539     return FALSE;
2540
2541   /* At the moment we can hanndle moving registers and loading constants.  */
2542   /* To be added: Addition/subtraction/bitops/multiplication of registers.  */
2543
2544   switch (GET_CODE (operand))
2545     {
2546     case REG:
2547       return 1;
2548
2549     case CONST_INT:
2550       return INT8_P (INTVAL (operand));
2551
2552     default:
2553 #if 0
2554       fprintf (stderr, "Test for cond move op of type: %s\n",
2555                GET_RTX_NAME (GET_CODE (operand)));
2556 #endif
2557       return 0;
2558     }
2559 }
2560
2561 /* Return true if the code is a test of the carry bit */
2562 int
2563 carry_compare_operand (op, mode)
2564      rtx op;
2565      enum machine_mode mode ATTRIBUTE_UNUSED;
2566 {
2567   rtx x;
2568
2569   if (GET_MODE (op) != CCmode && GET_MODE (op) != VOIDmode)
2570     return FALSE;
2571
2572   if (GET_CODE (op) != NE && GET_CODE (op) != EQ)
2573     return FALSE;
2574
2575   x = XEXP (op, 0);
2576   if (GET_CODE (x) != REG || REGNO (x) != CARRY_REGNUM)
2577     return FALSE;
2578
2579   x = XEXP (op, 1);
2580   if (GET_CODE (x) != CONST_INT || INTVAL (x) != 0)
2581     return FALSE;
2582
2583   return TRUE;
2584 }
2585
2586 /* Generate the correct assembler code to handle the conditional loading of a
2587    value into a register.  It is known that the operands satisfy the
2588    conditional_move_operand() function above.  The destination is operand[0].
2589    The condition is operand [1].  The 'true' value is operand [2] and the
2590    'false' value is operand [3].  */
2591 char *
2592 emit_cond_move (operands, insn)
2593      rtx * operands;
2594      rtx   insn ATTRIBUTE_UNUSED;
2595 {
2596   static char buffer [100];
2597   const char * dest = reg_names [REGNO (operands [0])];
2598
2599   buffer [0] = 0;
2600
2601   /* Destination must be a register.  */
2602   if (GET_CODE (operands [0]) != REG)
2603     abort();
2604   if (! conditional_move_operand (operands [2], SImode))
2605     abort();
2606   if (! conditional_move_operand (operands [3], SImode))
2607     abort();
2608
2609   /* Check to see if the test is reversed.  */
2610   if (GET_CODE (operands [1]) == NE)
2611     {
2612       rtx tmp = operands [2];
2613       operands [2] = operands [3];
2614       operands [3] = tmp;
2615     }
2616
2617   sprintf (buffer, "mvfc %s, cbr", dest);
2618
2619   /* If the true value was '0' then we need to invert the results of the move.  */
2620   if (INTVAL (operands [2]) == 0)
2621     sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1",
2622              dest, dest);
2623
2624   return buffer;
2625 }
2626
2627 /* Returns true if the registers contained in the two
2628    rtl expressions are different. */
2629 int
2630 m32r_not_same_reg (a, b)
2631      rtx a;
2632      rtx b;
2633 {
2634   int reg_a = -1;
2635   int reg_b = -2;
2636
2637   while (GET_CODE (a) == SUBREG)
2638     a = SUBREG_REG (a);
2639
2640   if (GET_CODE (a) == REG)
2641     reg_a = REGNO (a);
2642
2643   while (GET_CODE (b) == SUBREG)
2644     b = SUBREG_REG (b);
2645
2646   if (GET_CODE (b) == REG)
2647     reg_b = REGNO (b);
2648
2649   return reg_a != reg_b;
2650 }
2651
2652 \f
2653 /* Use a library function to move some bytes.  */
2654 static void
2655 block_move_call (dest_reg, src_reg, bytes_rtx)
2656      rtx dest_reg;
2657      rtx src_reg;
2658      rtx bytes_rtx;
2659 {
2660   /* We want to pass the size as Pmode, which will normally be SImode
2661      but will be DImode if we are using 64 bit longs and pointers.  */
2662   if (GET_MODE (bytes_rtx) != VOIDmode
2663       && GET_MODE (bytes_rtx) != Pmode)
2664     bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1);
2665
2666 #ifdef TARGET_MEM_FUNCTIONS
2667   emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
2668                      VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode,
2669                      convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
2670                                       TREE_UNSIGNED (sizetype)),
2671                      TYPE_MODE (sizetype));
2672 #else
2673   emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
2674                      VOIDmode, 3, src_reg, Pmode, dest_reg, Pmode,
2675                      convert_to_mode (TYPE_MODE (integer_type_node), bytes_rtx,
2676                                       TREE_UNSIGNED (integer_type_node)),
2677                      TYPE_MODE (integer_type_node));
2678 #endif
2679 }
2680
2681 /* The maximum number of bytes to copy using pairs of load/store instructions.
2682    If a block is larger than this then a loop will be generated to copy
2683    MAX_MOVE_BYTES chunks at a time.  The value of 32 is a semi-arbitary choice.
2684    A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte
2685    string copy in it.  */
2686 #define MAX_MOVE_BYTES 32
2687
2688 /* Expand string/block move operations.
2689
2690    operands[0] is the pointer to the destination.
2691    operands[1] is the pointer to the source.
2692    operands[2] is the number of bytes to move.
2693    operands[3] is the alignment.  */
2694
2695 void
2696 m32r_expand_block_move (operands)
2697      rtx operands[];
2698 {
2699   rtx           orig_dst  = operands[0];
2700   rtx           orig_src  = operands[1];
2701   rtx           bytes_rtx = operands[2];
2702   rtx           align_rtx = operands[3];
2703   int           constp    = GET_CODE (bytes_rtx) == CONST_INT;
2704   HOST_WIDE_INT bytes     = constp ? INTVAL (bytes_rtx) : 0;
2705   int           align     = INTVAL (align_rtx);
2706   int           leftover;
2707   rtx           src_reg;
2708   rtx           dst_reg;
2709
2710   if (constp && bytes <= 0)
2711     return;
2712
2713   /* Move the address into scratch registers.  */
2714   dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0));
2715   src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
2716
2717   if (align > UNITS_PER_WORD)
2718     align = UNITS_PER_WORD;
2719
2720   /* If we prefer size over speed, always use a function call.
2721      If we do not know the size, use a function call.
2722      If the blocks are not word aligned, use a function call.  */
2723   if (optimize_size || ! constp || align != UNITS_PER_WORD)
2724     {
2725       block_move_call (dst_reg, src_reg, bytes_rtx);
2726       return;
2727     }
2728
2729   leftover = bytes % MAX_MOVE_BYTES;
2730   bytes   -= leftover;
2731
2732   /* If necessary, generate a loop to handle the bulk of the copy.  */
2733   if (bytes)
2734     {
2735       rtx label;
2736       rtx final_src;
2737       rtx at_a_time = GEN_INT (MAX_MOVE_BYTES);
2738       rtx rounded_total = GEN_INT (bytes);
2739
2740       /* If we are going to have to perform this loop more than
2741          once, then generate a label and compute the address the
2742          source register will contain upon completion of the final
2743          itteration.  */
2744       if (bytes > MAX_MOVE_BYTES)
2745         {
2746           final_src = gen_reg_rtx (Pmode);
2747
2748           if (INT16_P(bytes))
2749             emit_insn (gen_addsi3 (final_src, src_reg, rounded_total));
2750           else
2751             {
2752               emit_insn (gen_movsi (final_src, rounded_total));
2753               emit_insn (gen_addsi3 (final_src, final_src, src_reg));
2754             }
2755
2756           label = gen_label_rtx ();
2757           emit_label (label);
2758         }
2759
2760       /* It is known that output_block_move() will update src_reg to point
2761          to the word after the end of the source block, and dst_reg to point
2762          to the last word of the destination block, provided that the block
2763          is MAX_MOVE_BYTES long.  */
2764       emit_insn (gen_movstrsi_internal (dst_reg, src_reg, at_a_time));
2765       emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4)));
2766
2767       if (bytes > MAX_MOVE_BYTES)
2768         {
2769           emit_insn (gen_cmpsi (src_reg, final_src));
2770           emit_jump_insn (gen_bne (label));
2771         }
2772     }
2773
2774   if (leftover)
2775     emit_insn (gen_movstrsi_internal (dst_reg, src_reg, GEN_INT (leftover)));
2776 }
2777
2778 \f
2779 /* Emit load/stores for a small constant word aligned block_move.
2780
2781    operands[0] is the memory address of the destination.
2782    operands[1] is the memory address of the source.
2783    operands[2] is the number of bytes to move.
2784    operands[3] is a temp register.
2785    operands[4] is a temp register.  */
2786
2787 char *
2788 m32r_output_block_move (insn, operands)
2789      rtx insn ATTRIBUTE_UNUSED;
2790      rtx operands[];
2791 {
2792   HOST_WIDE_INT bytes = INTVAL (operands[2]);
2793   int           first_time;
2794   int           got_extra = 0;
2795
2796   if (bytes < 1 || bytes > MAX_MOVE_BYTES)
2797     abort ();
2798
2799   /* We do not have a post-increment store available, so the first set of
2800      stores are done without any increment, then the remaining ones can use
2801      the pre-increment addressing mode.
2802
2803      Note: expand_block_move() also relies upon this behaviour when building
2804      loops to copy large blocks.  */
2805   first_time = 1;
2806
2807   while (bytes > 0)
2808     {
2809       if (bytes >= 8)
2810         {
2811           if (first_time)
2812             {
2813               output_asm_insn ("ld\t%3, %p1", operands);
2814               output_asm_insn ("ld\t%4, %p1", operands);
2815               output_asm_insn ("st\t%3, @%0", operands);
2816               output_asm_insn ("st\t%4, %s0", operands);
2817             }
2818           else
2819             {
2820               output_asm_insn ("ld\t%3, %p1", operands);
2821               output_asm_insn ("ld\t%4, %p1", operands);
2822               output_asm_insn ("st\t%3, %s0", operands);
2823               output_asm_insn ("st\t%4, %s0", operands);
2824             }
2825
2826           bytes -= 8;
2827         }
2828       else if (bytes >= 4)
2829         {
2830           if (bytes > 4)
2831             got_extra = 1;
2832
2833           output_asm_insn ("ld\t%3, %p1", operands);
2834
2835           if (got_extra)
2836             output_asm_insn ("ld\t%4, %p1", operands);
2837
2838           if (first_time)
2839             output_asm_insn ("st\t%3, @%0", operands);
2840           else
2841             output_asm_insn ("st\t%3, %s0", operands);
2842
2843           bytes -= 4;
2844         }
2845       else
2846         {
2847           /* Get the entire next word, even though we do not want all of it.
2848              The saves us from doing several smaller loads, and we assume that
2849              we cannot cause a page fault when at least part of the word is in
2850              valid memory [since we don't get called if things aren't properly
2851              aligned].  */
2852           int dst_offset = first_time ? 0 : 4;
2853           int last_shift;
2854           rtx my_operands[3];
2855
2856           /* If got_extra is true then we have already loaded
2857              the next word as part of loading and storing the previous word.  */
2858           if (! got_extra)
2859             output_asm_insn ("ld\t%4, @%1", operands);
2860
2861           if (bytes >= 2)
2862             {
2863               bytes -= 2;
2864
2865               output_asm_insn ("sra3\t%3, %4, #16", operands);
2866               my_operands[0] = operands[3];
2867               my_operands[1] = GEN_INT (dst_offset);
2868               my_operands[2] = operands[0];
2869               output_asm_insn ("sth\t%0, @(%1,%2)", my_operands);
2870
2871               /* If there is a byte left to store then increment the
2872                  destination address and shift the contents of the source
2873                  register down by 8 bits.  We could not do the address
2874                  increment in the store half word instruction, because it does
2875                  not have an auto increment mode.  */
2876               if (bytes > 0)  /* assert (bytes == 1) */
2877                 {
2878                   dst_offset += 2;
2879                   last_shift = 8;
2880                 }
2881             }
2882           else
2883             last_shift = 24;
2884
2885           if (bytes > 0)
2886             {
2887               my_operands[0] = operands[4];
2888               my_operands[1] = GEN_INT (last_shift);
2889               output_asm_insn ("srai\t%0, #%1", my_operands);
2890               my_operands[0] = operands[4];
2891               my_operands[1] = GEN_INT (dst_offset);
2892               my_operands[2] = operands[0];
2893               output_asm_insn ("stb\t%0, @(%1,%2)", my_operands);
2894             }
2895
2896           bytes = 0;
2897         }
2898
2899       first_time = 0;
2900     }
2901
2902   return "";
2903 }
2904
2905 /* Return true if op is an integer constant, less than or equal to
2906    MAX_MOVE_BYTES.  */
2907 int
2908 m32r_block_immediate_operand (op, mode)
2909      rtx op;
2910      enum machine_mode mode ATTRIBUTE_UNUSED;
2911 {
2912   if (GET_CODE (op) != CONST_INT
2913       || INTVAL (op) > MAX_MOVE_BYTES
2914       || INTVAL (op) <= 0)
2915     return 0;
2916
2917   return 1;
2918 }