1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 /* This module is essentially the "combiner" phase of the U. of Arizona
24 Portable Optimizer, but redone to work on our list-structured
25 representation for RTL instead of their string representation.
27 The LOG_LINKS of each insn identify the most recent assignment
28 to each REG used in the insn. It is a list of previous insns,
29 each of which contains a SET for a REG that is used in this insn
30 and not used or set in between. LOG_LINKs never cross basic blocks.
31 They were set up by the preceding pass (lifetime analysis).
33 We try to combine each pair of insns joined by a logical link.
34 We also try to combine triples of insns A, B and C when
35 C has a link back to B and B has a link back to A.
37 LOG_LINKS does not have links for use of the CC0. They don't
38 need to, because the insn that sets the CC0 is always immediately
39 before the insn that tests it. So we always regard a branch
40 insn as having a logical link to the preceding insn. The same is true
41 for an insn explicitly using CC0.
43 We check (with use_crosses_set_p) to avoid combining in such a way
44 as to move a computation to a place where its value would be different.
46 Combination is done by mathematically substituting the previous
47 insn(s) values for the regs they set into the expressions in
48 the later insns that refer to these regs. If the result is a valid insn
49 for our target machine, according to the machine description,
50 we install it, delete the earlier insns, and update the data flow
51 information (LOG_LINKS and REG_NOTES) for what we did.
53 There are a few exceptions where the dataflow information created by
54 flow.c aren't completely updated:
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_regnotes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
84 #include "hard-reg-set.h"
85 #include "basic-block.h"
86 #include "insn-config.h"
88 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
90 #include "insn-flags.h"
91 #include "insn-codes.h"
92 #include "insn-attr.h"
97 /* It is not safe to use ordinary gen_lowpart in combine.
98 Use gen_lowpart_for_combine instead. See comments there. */
99 #define gen_lowpart dont_use_gen_lowpart_you_dummy
101 /* Number of attempts to combine instructions in this function. */
103 static int combine_attempts
;
105 /* Number of attempts that got as far as substitution in this function. */
107 static int combine_merges
;
109 /* Number of instructions combined with added SETs in this function. */
111 static int combine_extras
;
113 /* Number of instructions combined in this function. */
115 static int combine_successes
;
117 /* Totals over entire compilation. */
119 static int total_attempts
, total_merges
, total_extras
, total_successes
;
121 /* Define a default value for REVERSIBLE_CC_MODE.
122 We can never assume that a condition code mode is safe to reverse unless
123 the md tells us so. */
124 #ifndef REVERSIBLE_CC_MODE
125 #define REVERSIBLE_CC_MODE(MODE) 0
128 /* Vector mapping INSN_UIDs to cuids.
129 The cuids are like uids but increase monotonically always.
130 Combine always uses cuids so that it can compare them.
131 But actually renumbering the uids, which we used to do,
132 proves to be a bad idea because it makes it hard to compare
133 the dumps produced by earlier passes with those from later passes. */
135 static int *uid_cuid
;
136 static int max_uid_cuid
;
138 /* Get the cuid of an insn. */
140 #define INSN_CUID(INSN) \
141 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
143 /* Maximum register number, which is the size of the tables below. */
145 static int combine_max_regno
;
147 /* Record last point of death of (hard or pseudo) register n. */
149 static rtx
*reg_last_death
;
151 /* Record last point of modification of (hard or pseudo) register n. */
153 static rtx
*reg_last_set
;
155 /* Record the cuid of the last insn that invalidated memory
156 (anything that writes memory, and subroutine calls, but not pushes). */
158 static int mem_last_set
;
160 /* Record the cuid of the last CALL_INSN
161 so we can tell whether a potential combination crosses any calls. */
163 static int last_call_cuid
;
165 /* When `subst' is called, this is the insn that is being modified
166 (by combining in a previous insn). The PATTERN of this insn
167 is still the old pattern partially modified and it should not be
168 looked at, but this may be used to examine the successors of the insn
169 to judge whether a simplification is valid. */
171 static rtx subst_insn
;
173 /* This is an insn that belongs before subst_insn, but is not currently
174 on the insn chain. */
176 static rtx subst_prev_insn
;
178 /* This is the lowest CUID that `subst' is currently dealing with.
179 get_last_value will not return a value if the register was set at or
180 after this CUID. If not for this mechanism, we could get confused if
181 I2 or I1 in try_combine were an insn that used the old value of a register
182 to obtain a new value. In that case, we might erroneously get the
183 new value of the register when we wanted the old one. */
185 static int subst_low_cuid
;
187 /* This contains any hard registers that are used in newpat; reg_dead_at_p
188 must consider all these registers to be always live. */
190 static HARD_REG_SET newpat_used_regs
;
192 /* This is an insn to which a LOG_LINKS entry has been added. If this
193 insn is the earlier than I2 or I3, combine should rescan starting at
196 static rtx added_links_insn
;
198 /* Basic block number of the block in which we are performing combines. */
199 static int this_basic_block
;
201 /* A bitmap indicating which blocks had registers go dead at entry.
202 After combine, we'll need to re-do global life analysis with
203 those blocks as starting points. */
204 static sbitmap refresh_blocks
;
205 static int need_refresh
;
207 /* The next group of arrays allows the recording of the last value assigned
208 to (hard or pseudo) register n. We use this information to see if a
209 operation being processed is redundant given a prior operation performed
210 on the register. For example, an `and' with a constant is redundant if
211 all the zero bits are already known to be turned off.
213 We use an approach similar to that used by cse, but change it in the
216 (1) We do not want to reinitialize at each label.
217 (2) It is useful, but not critical, to know the actual value assigned
218 to a register. Often just its form is helpful.
220 Therefore, we maintain the following arrays:
222 reg_last_set_value the last value assigned
223 reg_last_set_label records the value of label_tick when the
224 register was assigned
225 reg_last_set_table_tick records the value of label_tick when a
226 value using the register is assigned
227 reg_last_set_invalid set to non-zero when it is not valid
228 to use the value of this register in some
231 To understand the usage of these tables, it is important to understand
232 the distinction between the value in reg_last_set_value being valid
233 and the register being validly contained in some other expression in the
236 Entry I in reg_last_set_value is valid if it is non-zero, and either
237 reg_n_sets[i] is 1 or reg_last_set_label[i] == label_tick.
239 Register I may validly appear in any expression returned for the value
240 of another register if reg_n_sets[i] is 1. It may also appear in the
241 value for register J if reg_last_set_label[i] < reg_last_set_label[j] or
242 reg_last_set_invalid[j] is zero.
244 If an expression is found in the table containing a register which may
245 not validly appear in an expression, the register is replaced by
246 something that won't match, (clobber (const_int 0)).
248 reg_last_set_invalid[i] is set non-zero when register I is being assigned
249 to and reg_last_set_table_tick[i] == label_tick. */
251 /* Record last value assigned to (hard or pseudo) register n. */
253 static rtx
*reg_last_set_value
;
255 /* Record the value of label_tick when the value for register n is placed in
256 reg_last_set_value[n]. */
258 static int *reg_last_set_label
;
260 /* Record the value of label_tick when an expression involving register n
261 is placed in reg_last_set_value. */
263 static int *reg_last_set_table_tick
;
265 /* Set non-zero if references to register n in expressions should not be
268 static char *reg_last_set_invalid
;
270 /* Incremented for each label. */
272 static int label_tick
;
274 /* Some registers that are set more than once and used in more than one
275 basic block are nevertheless always set in similar ways. For example,
276 a QImode register may be loaded from memory in two places on a machine
277 where byte loads zero extend.
279 We record in the following array what we know about the nonzero
280 bits of a register, specifically which bits are known to be zero.
282 If an entry is zero, it means that we don't know anything special. */
284 static unsigned HOST_WIDE_INT
*reg_nonzero_bits
;
286 /* Mode used to compute significance in reg_nonzero_bits. It is the largest
287 integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
289 static enum machine_mode nonzero_bits_mode
;
291 /* Nonzero if we know that a register has some leading bits that are always
292 equal to the sign bit. */
294 static char *reg_sign_bit_copies
;
296 /* Nonzero when reg_nonzero_bits and reg_sign_bit_copies can be safely used.
297 It is zero while computing them and after combine has completed. This
298 former test prevents propagating values based on previously set values,
299 which can be incorrect if a variable is modified in a loop. */
301 static int nonzero_sign_valid
;
303 /* These arrays are maintained in parallel with reg_last_set_value
304 and are used to store the mode in which the register was last set,
305 the bits that were known to be zero when it was last set, and the
306 number of sign bits copies it was known to have when it was last set. */
308 static enum machine_mode
*reg_last_set_mode
;
309 static unsigned HOST_WIDE_INT
*reg_last_set_nonzero_bits
;
310 static char *reg_last_set_sign_bit_copies
;
312 /* Record one modification to rtl structure
313 to be undone by storing old_contents into *where.
314 is_int is 1 if the contents are an int. */
320 union {rtx r
; int i
;} old_contents
;
321 union {rtx
*r
; int *i
;} where
;
324 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
325 num_undo says how many are currently recorded.
327 storage is nonzero if we must undo the allocation of new storage.
328 The value of storage is what to pass to obfree.
330 other_insn is nonzero if we have modified some other insn in the process
331 of working on subst_insn. It must be verified too.
333 previous_undos is the value of undobuf.undos when we started processing
334 this substitution. This will prevent gen_rtx_combine from re-used a piece
335 from the previous expression. Doing so can produce circular rtl
343 struct undo
*previous_undos
;
347 static struct undobuf undobuf
;
349 /* Number of times the pseudo being substituted for
350 was found and replaced. */
352 static int n_occurrences
;
354 static void do_SUBST
PARAMS ((rtx
*, rtx
));
355 static void do_SUBST_INT
PARAMS ((int *, int));
356 static void init_reg_last_arrays
PARAMS ((void));
357 static void setup_incoming_promotions
PARAMS ((void));
358 static void set_nonzero_bits_and_sign_copies
PARAMS ((rtx
, rtx
, void *));
359 static int can_combine_p
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
*, rtx
*));
360 static int sets_function_arg_p
PARAMS ((rtx
));
361 static int combinable_i3pat
PARAMS ((rtx
, rtx
*, rtx
, rtx
, int, rtx
*));
362 static int contains_muldiv
PARAMS ((rtx
));
363 static rtx try_combine
PARAMS ((rtx
, rtx
, rtx
, int *));
364 static void undo_all
PARAMS ((void));
365 static void undo_commit
PARAMS ((void));
366 static rtx
*find_split_point
PARAMS ((rtx
*, rtx
));
367 static rtx subst
PARAMS ((rtx
, rtx
, rtx
, int, int));
368 static rtx combine_simplify_rtx
PARAMS ((rtx
, enum machine_mode
, int, int));
369 static rtx simplify_if_then_else
PARAMS ((rtx
));
370 static rtx simplify_set
PARAMS ((rtx
));
371 static rtx simplify_logical
PARAMS ((rtx
, int));
372 static rtx expand_compound_operation
PARAMS ((rtx
));
373 static rtx expand_field_assignment
PARAMS ((rtx
));
374 static rtx make_extraction
PARAMS ((enum machine_mode
, rtx
, int, rtx
, int,
376 static rtx extract_left_shift
PARAMS ((rtx
, int));
377 static rtx make_compound_operation
PARAMS ((rtx
, enum rtx_code
));
378 static int get_pos_from_mask
PARAMS ((unsigned HOST_WIDE_INT
, int *));
379 static rtx force_to_mode
PARAMS ((rtx
, enum machine_mode
,
380 unsigned HOST_WIDE_INT
, rtx
, int));
381 static rtx if_then_else_cond
PARAMS ((rtx
, rtx
*, rtx
*));
382 static rtx known_cond
PARAMS ((rtx
, enum rtx_code
, rtx
, rtx
));
383 static int rtx_equal_for_field_assignment_p
PARAMS ((rtx
, rtx
));
384 static rtx make_field_assignment
PARAMS ((rtx
));
385 static rtx apply_distributive_law
PARAMS ((rtx
));
386 static rtx simplify_and_const_int
PARAMS ((rtx
, enum machine_mode
, rtx
,
387 unsigned HOST_WIDE_INT
));
388 static unsigned HOST_WIDE_INT nonzero_bits
PARAMS ((rtx
, enum machine_mode
));
389 static int num_sign_bit_copies
PARAMS ((rtx
, enum machine_mode
));
390 static int merge_outer_ops
PARAMS ((enum rtx_code
*, HOST_WIDE_INT
*,
391 enum rtx_code
, HOST_WIDE_INT
,
392 enum machine_mode
, int *));
393 static rtx simplify_shift_const
PARAMS ((rtx
, enum rtx_code
, enum machine_mode
,
395 static int recog_for_combine
PARAMS ((rtx
*, rtx
, rtx
*));
396 static rtx gen_lowpart_for_combine
PARAMS ((enum machine_mode
, rtx
));
397 static rtx gen_rtx_combine
PARAMS ((enum rtx_code code
, enum machine_mode mode
,
399 static rtx gen_binary
PARAMS ((enum rtx_code
, enum machine_mode
,
401 static rtx gen_unary
PARAMS ((enum rtx_code
, enum machine_mode
,
402 enum machine_mode
, rtx
));
403 static enum rtx_code simplify_comparison
PARAMS ((enum rtx_code
, rtx
*, rtx
*));
404 static int reversible_comparison_p
PARAMS ((rtx
));
405 static void update_table_tick
PARAMS ((rtx
));
406 static void record_value_for_reg
PARAMS ((rtx
, rtx
, rtx
));
407 static void check_promoted_subreg
PARAMS ((rtx
, rtx
));
408 static void record_dead_and_set_regs_1
PARAMS ((rtx
, rtx
, void *));
409 static void record_dead_and_set_regs
PARAMS ((rtx
));
410 static int get_last_value_validate
PARAMS ((rtx
*, rtx
, int, int));
411 static rtx get_last_value
PARAMS ((rtx
));
412 static int use_crosses_set_p
PARAMS ((rtx
, int));
413 static void reg_dead_at_p_1
PARAMS ((rtx
, rtx
, void *));
414 static int reg_dead_at_p
PARAMS ((rtx
, rtx
));
415 static void move_deaths
PARAMS ((rtx
, rtx
, int, rtx
, rtx
*));
416 static int reg_bitfield_target_p
PARAMS ((rtx
, rtx
));
417 static void distribute_notes
PARAMS ((rtx
, rtx
, rtx
, rtx
, rtx
, rtx
));
418 static void distribute_links
PARAMS ((rtx
));
419 static void mark_used_regs_combine
PARAMS ((rtx
));
420 static int insn_cuid
PARAMS ((rtx
));
421 static void record_promoted_value
PARAMS ((rtx
, rtx
));
423 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
424 insn. The substitution can be undone by undo_all. If INTO is already
425 set to NEWVAL, do not record this change. Because computing NEWVAL might
426 also call SUBST, we have to compute it before we put anything into
430 do_SUBST(into
, newval
)
436 if (oldval
== newval
)
440 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
442 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
446 buf
->old_contents
.r
= oldval
;
449 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
452 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
454 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
455 for the value of a HOST_WIDE_INT value (including CONST_INT) is
459 do_SUBST_INT(into
, newval
)
465 if (oldval
== newval
)
469 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
471 buf
= (struct undo
*) xmalloc (sizeof (struct undo
));
475 buf
->old_contents
.i
= oldval
;
478 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
481 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
483 /* Main entry point for combiner. F is the first insn of the function.
484 NREGS is the first unused pseudo-reg number.
486 Return non-zero if the combiner has turned an indirect jump
487 instruction into a direct jump. */
489 combine_instructions (f
, nregs
)
493 register rtx insn
, next
;
498 register rtx links
, nextlinks
;
500 int new_direct_jump_p
= 0;
502 combine_attempts
= 0;
505 combine_successes
= 0;
507 combine_max_regno
= nregs
;
509 reg_nonzero_bits
= ((unsigned HOST_WIDE_INT
*)
510 xcalloc (nregs
, sizeof (unsigned HOST_WIDE_INT
)));
511 reg_sign_bit_copies
= (char *) xcalloc (nregs
, sizeof (char));
513 reg_last_death
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
514 reg_last_set
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
515 reg_last_set_value
= (rtx
*) xmalloc (nregs
* sizeof (rtx
));
516 reg_last_set_table_tick
= (int *) xmalloc (nregs
* sizeof (int));
517 reg_last_set_label
= (int *) xmalloc (nregs
* sizeof (int));
518 reg_last_set_invalid
= (char *) xmalloc (nregs
* sizeof (char));
520 = (enum machine_mode
*) xmalloc (nregs
* sizeof (enum machine_mode
));
521 reg_last_set_nonzero_bits
522 = (unsigned HOST_WIDE_INT
*) xmalloc (nregs
* sizeof (HOST_WIDE_INT
));
523 reg_last_set_sign_bit_copies
524 = (char *) xmalloc (nregs
* sizeof (char));
526 init_reg_last_arrays ();
528 init_recog_no_volatile ();
530 /* Compute maximum uid value so uid_cuid can be allocated. */
532 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
533 if (INSN_UID (insn
) > i
)
536 uid_cuid
= (int *) xmalloc ((i
+ 1) * sizeof (int));
539 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
541 /* Don't use reg_nonzero_bits when computing it. This can cause problems
542 when, for example, we have j <<= 1 in a loop. */
544 nonzero_sign_valid
= 0;
546 /* Compute the mapping from uids to cuids.
547 Cuids are numbers assigned to insns, like uids,
548 except that cuids increase monotonically through the code.
550 Scan all SETs and see if we can deduce anything about what
551 bits are known to be zero for some registers and how many copies
552 of the sign bit are known to exist for those registers.
554 Also set any known values so that we can use it while searching
555 for what bits are known to be set. */
559 /* We need to initialize it here, because record_dead_and_set_regs may call
561 subst_prev_insn
= NULL_RTX
;
563 setup_incoming_promotions ();
565 refresh_blocks
= sbitmap_alloc (n_basic_blocks
);
566 sbitmap_zero (refresh_blocks
);
569 for (insn
= f
, i
= 0; insn
; insn
= NEXT_INSN (insn
))
571 uid_cuid
[INSN_UID (insn
)] = ++i
;
575 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
577 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
579 record_dead_and_set_regs (insn
);
582 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
583 if (REG_NOTE_KIND (links
) == REG_INC
)
584 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
589 if (GET_CODE (insn
) == CODE_LABEL
)
593 nonzero_sign_valid
= 1;
595 /* Now scan all the insns in forward order. */
597 this_basic_block
= -1;
601 init_reg_last_arrays ();
602 setup_incoming_promotions ();
604 for (insn
= f
; insn
; insn
= next
? next
: NEXT_INSN (insn
))
608 /* If INSN starts a new basic block, update our basic block number. */
609 if (this_basic_block
+ 1 < n_basic_blocks
610 && BLOCK_HEAD (this_basic_block
+ 1) == insn
)
613 if (GET_CODE (insn
) == CODE_LABEL
)
616 else if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i')
618 /* See if we know about function return values before this
619 insn based upon SUBREG flags. */
620 check_promoted_subreg (insn
, PATTERN (insn
));
622 /* Try this insn with each insn it links back to. */
624 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
625 if ((next
= try_combine (insn
, XEXP (links
, 0),
626 NULL_RTX
, &new_direct_jump_p
)) != 0)
629 /* Try each sequence of three linked insns ending with this one. */
631 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
632 for (nextlinks
= LOG_LINKS (XEXP (links
, 0)); nextlinks
;
633 nextlinks
= XEXP (nextlinks
, 1))
634 if ((next
= try_combine (insn
, XEXP (links
, 0),
636 &new_direct_jump_p
)) != 0)
640 /* Try to combine a jump insn that uses CC0
641 with a preceding insn that sets CC0, and maybe with its
642 logical predecessor as well.
643 This is how we make decrement-and-branch insns.
644 We need this special code because data flow connections
645 via CC0 do not get entered in LOG_LINKS. */
647 if (GET_CODE (insn
) == JUMP_INSN
648 && (prev
= prev_nonnote_insn (insn
)) != 0
649 && GET_CODE (prev
) == INSN
650 && sets_cc0_p (PATTERN (prev
)))
652 if ((next
= try_combine (insn
, prev
,
653 NULL_RTX
, &new_direct_jump_p
)) != 0)
656 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
657 nextlinks
= XEXP (nextlinks
, 1))
658 if ((next
= try_combine (insn
, prev
,
660 &new_direct_jump_p
)) != 0)
664 /* Do the same for an insn that explicitly references CC0. */
665 if (GET_CODE (insn
) == INSN
666 && (prev
= prev_nonnote_insn (insn
)) != 0
667 && GET_CODE (prev
) == INSN
668 && sets_cc0_p (PATTERN (prev
))
669 && GET_CODE (PATTERN (insn
)) == SET
670 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
672 if ((next
= try_combine (insn
, prev
,
673 NULL_RTX
, &new_direct_jump_p
)) != 0)
676 for (nextlinks
= LOG_LINKS (prev
); nextlinks
;
677 nextlinks
= XEXP (nextlinks
, 1))
678 if ((next
= try_combine (insn
, prev
,
680 &new_direct_jump_p
)) != 0)
684 /* Finally, see if any of the insns that this insn links to
685 explicitly references CC0. If so, try this insn, that insn,
686 and its predecessor if it sets CC0. */
687 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
688 if (GET_CODE (XEXP (links
, 0)) == INSN
689 && GET_CODE (PATTERN (XEXP (links
, 0))) == SET
690 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (XEXP (links
, 0))))
691 && (prev
= prev_nonnote_insn (XEXP (links
, 0))) != 0
692 && GET_CODE (prev
) == INSN
693 && sets_cc0_p (PATTERN (prev
))
694 && (next
= try_combine (insn
, XEXP (links
, 0),
695 prev
, &new_direct_jump_p
)) != 0)
699 /* Try combining an insn with two different insns whose results it
701 for (links
= LOG_LINKS (insn
); links
; links
= XEXP (links
, 1))
702 for (nextlinks
= XEXP (links
, 1); nextlinks
;
703 nextlinks
= XEXP (nextlinks
, 1))
704 if ((next
= try_combine (insn
, XEXP (links
, 0),
706 &new_direct_jump_p
)) != 0)
709 if (GET_CODE (insn
) != NOTE
)
710 record_dead_and_set_regs (insn
);
719 compute_bb_for_insn (get_max_uid ());
720 update_life_info (refresh_blocks
, UPDATE_LIFE_GLOBAL_RM_NOTES
,
725 sbitmap_free (refresh_blocks
);
726 free (reg_nonzero_bits
);
727 free (reg_sign_bit_copies
);
728 free (reg_last_death
);
730 free (reg_last_set_value
);
731 free (reg_last_set_table_tick
);
732 free (reg_last_set_label
);
733 free (reg_last_set_invalid
);
734 free (reg_last_set_mode
);
735 free (reg_last_set_nonzero_bits
);
736 free (reg_last_set_sign_bit_copies
);
740 struct undo
*undo
, *next
;
741 for (undo
= undobuf
.frees
; undo
; undo
= next
)
749 total_attempts
+= combine_attempts
;
750 total_merges
+= combine_merges
;
751 total_extras
+= combine_extras
;
752 total_successes
+= combine_successes
;
754 nonzero_sign_valid
= 0;
756 /* Make recognizer allow volatile MEMs again. */
759 return new_direct_jump_p
;
762 /* Wipe the reg_last_xxx arrays in preparation for another pass. */
765 init_reg_last_arrays ()
767 int nregs
= combine_max_regno
;
769 bzero ((char *) reg_last_death
, nregs
* sizeof (rtx
));
770 bzero ((char *) reg_last_set
, nregs
* sizeof (rtx
));
771 bzero ((char *) reg_last_set_value
, nregs
* sizeof (rtx
));
772 bzero ((char *) reg_last_set_table_tick
, nregs
* sizeof (int));
773 bzero ((char *) reg_last_set_label
, nregs
* sizeof (int));
774 bzero (reg_last_set_invalid
, nregs
* sizeof (char));
775 bzero ((char *) reg_last_set_mode
, nregs
* sizeof (enum machine_mode
));
776 bzero ((char *) reg_last_set_nonzero_bits
, nregs
* sizeof (HOST_WIDE_INT
));
777 bzero (reg_last_set_sign_bit_copies
, nregs
* sizeof (char));
780 /* Set up any promoted values for incoming argument registers. */
783 setup_incoming_promotions ()
785 #ifdef PROMOTE_FUNCTION_ARGS
788 enum machine_mode mode
;
790 rtx first
= get_insns ();
792 #ifndef OUTGOING_REGNO
793 #define OUTGOING_REGNO(N) N
795 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
796 /* Check whether this register can hold an incoming pointer
797 argument. FUNCTION_ARG_REGNO_P tests outgoing register
798 numbers, so translate if necessary due to register windows. */
799 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno
))
800 && (reg
= promoted_input_arg (regno
, &mode
, &unsignedp
)) != 0)
803 (reg
, first
, gen_rtx_fmt_e ((unsignedp
? ZERO_EXTEND
806 gen_rtx_CLOBBER (mode
, const0_rtx
)));
811 /* Called via note_stores. If X is a pseudo that is narrower than
812 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
814 If we are setting only a portion of X and we can't figure out what
815 portion, assume all bits will be used since we don't know what will
818 Similarly, set how many bits of X are known to be copies of the sign bit
819 at all locations in the function. This is the smallest number implied
823 set_nonzero_bits_and_sign_copies (x
, set
, data
)
826 void *data ATTRIBUTE_UNUSED
;
830 if (GET_CODE (x
) == REG
831 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
832 /* If this register is undefined at the start of the file, we can't
833 say what its contents were. */
834 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
, REGNO (x
))
835 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
837 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
839 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
840 reg_sign_bit_copies
[REGNO (x
)] = 1;
844 /* If this is a complex assignment, see if we can convert it into a
845 simple assignment. */
846 set
= expand_field_assignment (set
);
848 /* If this is a simple assignment, or we have a paradoxical SUBREG,
849 set what we know about X. */
851 if (SET_DEST (set
) == x
852 || (GET_CODE (SET_DEST (set
)) == SUBREG
853 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set
)))
854 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set
)))))
855 && SUBREG_REG (SET_DEST (set
)) == x
))
857 rtx src
= SET_SRC (set
);
859 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
860 /* If X is narrower than a word and SRC is a non-negative
861 constant that would appear negative in the mode of X,
862 sign-extend it for use in reg_nonzero_bits because some
863 machines (maybe most) will actually do the sign-extension
864 and this is the conservative approach.
866 ??? For 2.5, try to tighten up the MD files in this regard
867 instead of this kludge. */
869 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
870 && GET_CODE (src
) == CONST_INT
872 && 0 != (INTVAL (src
)
874 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
875 src
= GEN_INT (INTVAL (src
)
876 | ((HOST_WIDE_INT
) (-1)
877 << GET_MODE_BITSIZE (GET_MODE (x
))));
880 reg_nonzero_bits
[REGNO (x
)]
881 |= nonzero_bits (src
, nonzero_bits_mode
);
882 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
883 if (reg_sign_bit_copies
[REGNO (x
)] == 0
884 || reg_sign_bit_copies
[REGNO (x
)] > num
)
885 reg_sign_bit_copies
[REGNO (x
)] = num
;
889 reg_nonzero_bits
[REGNO (x
)] = GET_MODE_MASK (GET_MODE (x
));
890 reg_sign_bit_copies
[REGNO (x
)] = 1;
895 /* See if INSN can be combined into I3. PRED and SUCC are optionally
896 insns that were previously combined into I3 or that will be combined
897 into the merger of INSN and I3.
899 Return 0 if the combination is not allowed for any reason.
901 If the combination is allowed, *PDEST will be set to the single
902 destination of INSN and *PSRC to the single source, and this function
906 can_combine_p (insn
, i3
, pred
, succ
, pdest
, psrc
)
909 rtx pred ATTRIBUTE_UNUSED
;
914 rtx set
= 0, src
, dest
;
919 int all_adjacent
= (succ
? (next_active_insn (insn
) == succ
920 && next_active_insn (succ
) == i3
)
921 : next_active_insn (insn
) == i3
);
923 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
924 or a PARALLEL consisting of such a SET and CLOBBERs.
926 If INSN has CLOBBER parallel parts, ignore them for our processing.
927 By definition, these happen during the execution of the insn. When it
928 is merged with another insn, all bets are off. If they are, in fact,
929 needed and aren't also supplied in I3, they may be added by
930 recog_for_combine. Otherwise, it won't match.
932 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
935 Get the source and destination of INSN. If more than one, can't
938 if (GET_CODE (PATTERN (insn
)) == SET
)
939 set
= PATTERN (insn
);
940 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
941 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
943 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
945 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
947 switch (GET_CODE (elt
))
949 /* This is important to combine floating point insns
952 /* Combining an isolated USE doesn't make sense.
953 We depend here on combinable_i3_pat to reject them. */
954 /* The code below this loop only verifies that the inputs of
955 the SET in INSN do not change. We call reg_set_between_p
956 to verify that the REG in the USE does not change betweeen
958 If the USE in INSN was for a pseudo register, the matching
959 insn pattern will likely match any register; combining this
960 with any other USE would only be safe if we knew that the
961 used registers have identical values, or if there was
962 something to tell them apart, e.g. different modes. For
963 now, we forgo such compilcated tests and simply disallow
964 combining of USES of pseudo registers with any other USE. */
965 if (GET_CODE (XEXP (elt
, 0)) == REG
966 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
968 rtx i3pat
= PATTERN (i3
);
969 int i
= XVECLEN (i3pat
, 0) - 1;
970 int regno
= REGNO (XEXP (elt
, 0));
973 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
974 if (GET_CODE (i3elt
) == USE
975 && GET_CODE (XEXP (i3elt
, 0)) == REG
976 && (REGNO (XEXP (i3elt
, 0)) == regno
977 ? reg_set_between_p (XEXP (elt
, 0),
978 PREV_INSN (insn
), i3
)
979 : regno
>= FIRST_PSEUDO_REGISTER
))
986 /* We can ignore CLOBBERs. */
991 /* Ignore SETs whose result isn't used but not those that
992 have side-effects. */
993 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
994 && ! side_effects_p (elt
))
997 /* If we have already found a SET, this is a second one and
998 so we cannot combine with this insn. */
1006 /* Anything else means we can't combine. */
1012 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1013 so don't do anything with it. */
1014 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1023 set
= expand_field_assignment (set
);
1024 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1026 /* Don't eliminate a store in the stack pointer. */
1027 if (dest
== stack_pointer_rtx
1028 /* If we couldn't eliminate a field assignment, we can't combine. */
1029 || GET_CODE (dest
) == ZERO_EXTRACT
|| GET_CODE (dest
) == STRICT_LOW_PART
1030 /* Don't combine with an insn that sets a register to itself if it has
1031 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1032 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1033 /* Can't merge a function call. */
1034 || GET_CODE (src
) == CALL
1035 /* Don't eliminate a function call argument. */
1036 || (GET_CODE (i3
) == CALL_INSN
1037 && (find_reg_fusage (i3
, USE
, dest
)
1038 || (GET_CODE (dest
) == REG
1039 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1040 && global_regs
[REGNO (dest
)])))
1041 /* Don't substitute into an incremented register. */
1042 || FIND_REG_INC_NOTE (i3
, dest
)
1043 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1045 /* Don't combine the end of a libcall into anything. */
1046 /* ??? This gives worse code, and appears to be unnecessary, since no
1047 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1048 use REG_RETVAL notes for noconflict blocks, but other code here
1049 makes sure that those insns don't disappear. */
1050 || find_reg_note (insn
, REG_RETVAL
, NULL_RTX
)
1052 /* Make sure that DEST is not used after SUCC but before I3. */
1053 || (succ
&& ! all_adjacent
1054 && reg_used_between_p (dest
, succ
, i3
))
1055 /* Make sure that the value that is to be substituted for the register
1056 does not use any registers whose values alter in between. However,
1057 If the insns are adjacent, a use can't cross a set even though we
1058 think it might (this can happen for a sequence of insns each setting
1059 the same destination; reg_last_set of that register might point to
1060 a NOTE). If INSN has a REG_EQUIV note, the register is always
1061 equivalent to the memory so the substitution is valid even if there
1062 are intervening stores. Also, don't move a volatile asm or
1063 UNSPEC_VOLATILE across any other insns. */
1065 && (((GET_CODE (src
) != MEM
1066 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1067 && use_crosses_set_p (src
, INSN_CUID (insn
)))
1068 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1069 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1070 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1071 better register allocation by not doing the combine. */
1072 || find_reg_note (i3
, REG_NO_CONFLICT
, dest
)
1073 || (succ
&& find_reg_note (succ
, REG_NO_CONFLICT
, dest
))
1074 /* Don't combine across a CALL_INSN, because that would possibly
1075 change whether the life span of some REGs crosses calls or not,
1076 and it is a pain to update that information.
1077 Exception: if source is a constant, moving it later can't hurt.
1078 Accept that special case, because it helps -fforce-addr a lot. */
1079 || (INSN_CUID (insn
) < last_call_cuid
&& ! CONSTANT_P (src
)))
1082 /* DEST must either be a REG or CC0. */
1083 if (GET_CODE (dest
) == REG
)
1085 /* If register alignment is being enforced for multi-word items in all
1086 cases except for parameters, it is possible to have a register copy
1087 insn referencing a hard register that is not allowed to contain the
1088 mode being copied and which would not be valid as an operand of most
1089 insns. Eliminate this problem by not combining with such an insn.
1091 Also, on some machines we don't want to extend the life of a hard
1094 This is the same test done in can_combine except that we don't test
1095 if SRC is a CALL operation to permit a hard register with
1096 SMALL_REGISTER_CLASSES, and that we have to take all_adjacent
1099 if (GET_CODE (src
) == REG
1100 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1101 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1102 /* Don't extend the life of a hard register unless it is
1103 user variable (if we have few registers) or it can't
1104 fit into the desired register (meaning something special
1106 Also avoid substituting a return register into I3, because
1107 reload can't handle a conflict with constraints of other
1109 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
1110 && (! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
))
1111 || (SMALL_REGISTER_CLASSES
1112 && ((! all_adjacent
&& ! REG_USERVAR_P (src
))
1113 || (FUNCTION_VALUE_REGNO_P (REGNO (src
))
1114 && ! REG_USERVAR_P (src
))))))))
1117 else if (GET_CODE (dest
) != CC0
)
1120 /* Don't substitute for a register intended as a clobberable operand.
1121 Similarly, don't substitute an expression containing a register that
1122 will be clobbered in I3. */
1123 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
1124 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
1125 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
1126 && (reg_overlap_mentioned_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0),
1128 || rtx_equal_p (XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0), dest
)))
1131 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1132 or not), reject, unless nothing volatile comes between it and I3 */
1134 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
1136 /* Make sure succ doesn't contain a volatile reference. */
1137 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
1140 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1141 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i'
1142 && p
!= succ
&& volatile_refs_p (PATTERN (p
)))
1146 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1147 to be an explicit register variable, and was chosen for a reason. */
1149 if (GET_CODE (src
) == ASM_OPERANDS
1150 && GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
1153 /* If there are any volatile insns between INSN and I3, reject, because
1154 they might affect machine state. */
1156 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
1157 if (GET_RTX_CLASS (GET_CODE (p
)) == 'i'
1158 && p
!= succ
&& volatile_insn_p (PATTERN (p
)))
1161 /* If INSN or I2 contains an autoincrement or autodecrement,
1162 make sure that register is not used between there and I3,
1163 and not already used in I3 either.
1164 Also insist that I3 not be a jump; if it were one
1165 and the incremented register were spilled, we would lose. */
1168 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
1169 if (REG_NOTE_KIND (link
) == REG_INC
1170 && (GET_CODE (i3
) == JUMP_INSN
1171 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
1172 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
1177 /* Don't combine an insn that follows a CC0-setting insn.
1178 An insn that uses CC0 must not be separated from the one that sets it.
1179 We do, however, allow I2 to follow a CC0-setting insn if that insn
1180 is passed as I1; in that case it will be deleted also.
1181 We also allow combining in this case if all the insns are adjacent
1182 because that would leave the two CC0 insns adjacent as well.
1183 It would be more logical to test whether CC0 occurs inside I1 or I2,
1184 but that would be much slower, and this ought to be equivalent. */
1186 p
= prev_nonnote_insn (insn
);
1187 if (p
&& p
!= pred
&& GET_CODE (p
) == INSN
&& sets_cc0_p (PATTERN (p
))
1192 /* If we get here, we have passed all the tests and the combination is
1201 /* Check if PAT is an insn - or a part of it - used to set up an
1202 argument for a function in a hard register. */
1205 sets_function_arg_p (pat
)
1211 switch (GET_CODE (pat
))
1214 return sets_function_arg_p (PATTERN (pat
));
1217 for (i
= XVECLEN (pat
, 0); --i
>= 0;)
1218 if (sets_function_arg_p (XVECEXP (pat
, 0, i
)))
1224 inner_dest
= SET_DEST (pat
);
1225 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1226 || GET_CODE (inner_dest
) == SUBREG
1227 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1228 inner_dest
= XEXP (inner_dest
, 0);
1230 return (GET_CODE (inner_dest
) == REG
1231 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1232 && FUNCTION_ARG_REGNO_P (REGNO (inner_dest
)));
1241 /* LOC is the location within I3 that contains its pattern or the component
1242 of a PARALLEL of the pattern. We validate that it is valid for combining.
1244 One problem is if I3 modifies its output, as opposed to replacing it
1245 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1246 so would produce an insn that is not equivalent to the original insns.
1250 (set (reg:DI 101) (reg:DI 100))
1251 (set (subreg:SI (reg:DI 101) 0) <foo>)
1253 This is NOT equivalent to:
1255 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1256 (set (reg:DI 101) (reg:DI 100))])
1258 Not only does this modify 100 (in which case it might still be valid
1259 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1261 We can also run into a problem if I2 sets a register that I1
1262 uses and I1 gets directly substituted into I3 (not via I2). In that
1263 case, we would be getting the wrong value of I2DEST into I3, so we
1264 must reject the combination. This case occurs when I2 and I1 both
1265 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1266 If I1_NOT_IN_SRC is non-zero, it means that finding I1 in the source
1267 of a SET must prevent combination from occurring.
1269 On machines where SMALL_REGISTER_CLASSES is non-zero, we don't combine
1270 if the destination of a SET is a hard register that isn't a user
1273 Before doing the above check, we first try to expand a field assignment
1274 into a set of logical operations.
1276 If PI3_DEST_KILLED is non-zero, it is a pointer to a location in which
1277 we place a register that is both set and used within I3. If more than one
1278 such register is detected, we fail.
1280 Return 1 if the combination is valid, zero otherwise. */
1283 combinable_i3pat (i3
, loc
, i2dest
, i1dest
, i1_not_in_src
, pi3dest_killed
)
1289 rtx
*pi3dest_killed
;
1293 if (GET_CODE (x
) == SET
)
1295 rtx set
= expand_field_assignment (x
);
1296 rtx dest
= SET_DEST (set
);
1297 rtx src
= SET_SRC (set
);
1298 rtx inner_dest
= dest
;
1301 rtx inner_src
= src
;
1306 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
1307 || GET_CODE (inner_dest
) == SUBREG
1308 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
1309 inner_dest
= XEXP (inner_dest
, 0);
1311 /* We probably don't need this any more now that LIMIT_RELOAD_CLASS
1314 while (GET_CODE (inner_src
) == STRICT_LOW_PART
1315 || GET_CODE (inner_src
) == SUBREG
1316 || GET_CODE (inner_src
) == ZERO_EXTRACT
)
1317 inner_src
= XEXP (inner_src
, 0);
1319 /* If it is better that two different modes keep two different pseudos,
1320 avoid combining them. This avoids producing the following pattern
1322 (set (subreg:SI (reg/v:QI 21) 0)
1323 (lshiftrt:SI (reg/v:SI 20)
1325 If that were made, reload could not handle the pair of
1326 reg 20/21, since it would try to get any GENERAL_REGS
1327 but some of them don't handle QImode. */
1329 if (rtx_equal_p (inner_src
, i2dest
)
1330 && GET_CODE (inner_dest
) == REG
1331 && ! MODES_TIEABLE_P (GET_MODE (i2dest
), GET_MODE (inner_dest
)))
1335 /* Check for the case where I3 modifies its output, as
1337 if ((inner_dest
!= dest
1338 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
1339 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))))
1341 /* This is the same test done in can_combine_p except that we
1342 allow a hard register with SMALL_REGISTER_CLASSES if SRC is a
1343 CALL operation. Moreover, we can't test all_adjacent; we don't
1344 have to, since this instruction will stay in place, thus we are
1345 not considering increasing the lifetime of INNER_DEST.
1347 Also, if this insn sets a function argument, combining it with
1348 something that might need a spill could clobber a previous
1349 function argument; the all_adjacent test in can_combine_p also
1350 checks this; here, we do a more specific test for this case. */
1352 || (GET_CODE (inner_dest
) == REG
1353 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
1354 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
1355 GET_MODE (inner_dest
))
1356 || (SMALL_REGISTER_CLASSES
&& GET_CODE (src
) != CALL
1357 && ! REG_USERVAR_P (inner_dest
)
1358 && (FUNCTION_VALUE_REGNO_P (REGNO (inner_dest
))
1359 || (FUNCTION_ARG_REGNO_P (REGNO (inner_dest
))
1361 && sets_function_arg_p (prev_nonnote_insn (i3
)))))))
1362 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
)))
1365 /* If DEST is used in I3, it is being killed in this insn,
1366 so record that for later.
1367 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1368 STACK_POINTER_REGNUM, since these are always considered to be
1369 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1370 if (pi3dest_killed
&& GET_CODE (dest
) == REG
1371 && reg_referenced_p (dest
, PATTERN (i3
))
1372 && REGNO (dest
) != FRAME_POINTER_REGNUM
1373 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1374 && REGNO (dest
) != HARD_FRAME_POINTER_REGNUM
1376 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1377 && (REGNO (dest
) != ARG_POINTER_REGNUM
1378 || ! fixed_regs
[REGNO (dest
)])
1380 && REGNO (dest
) != STACK_POINTER_REGNUM
)
1382 if (*pi3dest_killed
)
1385 *pi3dest_killed
= dest
;
1389 else if (GET_CODE (x
) == PARALLEL
)
1393 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
1394 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
,
1395 i1_not_in_src
, pi3dest_killed
))
1402 /* Return 1 if X is an arithmetic expression that contains a multiplication
1403 and division. We don't count multiplications by powers of two here. */
1409 switch (GET_CODE (x
))
1411 case MOD
: case DIV
: case UMOD
: case UDIV
:
1415 return ! (GET_CODE (XEXP (x
, 1)) == CONST_INT
1416 && exact_log2 (INTVAL (XEXP (x
, 1))) >= 0);
1418 switch (GET_RTX_CLASS (GET_CODE (x
)))
1420 case 'c': case '<': case '2':
1421 return contains_muldiv (XEXP (x
, 0))
1422 || contains_muldiv (XEXP (x
, 1));
1425 return contains_muldiv (XEXP (x
, 0));
1433 /* Try to combine the insns I1 and I2 into I3.
1434 Here I1 and I2 appear earlier than I3.
1435 I1 can be zero; then we combine just I2 into I3.
1437 It we are combining three insns and the resulting insn is not recognized,
1438 try splitting it into two insns. If that happens, I2 and I3 are retained
1439 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1442 Return 0 if the combination does not work. Then nothing is changed.
1443 If we did the combination, return the insn at which combine should
1446 Set NEW_DIRECT_JUMP_P to a non-zero value if try_combine creates a
1447 new direct jump instruction. */
1450 try_combine (i3
, i2
, i1
, new_direct_jump_p
)
1451 register rtx i3
, i2
, i1
;
1452 register int *new_direct_jump_p
;
1454 /* New patterns for I3 and I3, respectively. */
1455 rtx newpat
, newi2pat
= 0;
1456 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1457 int added_sets_1
, added_sets_2
;
1458 /* Total number of SETs to put into I3. */
1460 /* Nonzero is I2's body now appears in I3. */
1462 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1463 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
1464 /* Contains I3 if the destination of I3 is used in its source, which means
1465 that the old life of I3 is being killed. If that usage is placed into
1466 I2 and not in I3, a REG_DEAD note must be made. */
1467 rtx i3dest_killed
= 0;
1468 /* SET_DEST and SET_SRC of I2 and I1. */
1469 rtx i2dest
, i2src
, i1dest
= 0, i1src
= 0;
1470 /* PATTERN (I2), or a copy of it in certain cases. */
1472 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1473 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
1474 int i1_feeds_i3
= 0;
1475 /* Notes that must be added to REG_NOTES in I3 and I2. */
1476 rtx new_i3_notes
, new_i2_notes
;
1477 /* Notes that we substituted I3 into I2 instead of the normal case. */
1478 int i3_subst_into_i2
= 0;
1479 /* Notes that I1, I2 or I3 is a MULT operation. */
1487 /* If any of I1, I2, and I3 isn't really an insn, we can't do anything.
1488 This can occur when flow deletes an insn that it has merged into an
1489 auto-increment address. We also can't do anything if I3 has a
1490 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1493 if (GET_RTX_CLASS (GET_CODE (i3
)) != 'i'
1494 || GET_RTX_CLASS (GET_CODE (i2
)) != 'i'
1495 || (i1
&& GET_RTX_CLASS (GET_CODE (i1
)) != 'i')
1497 /* ??? This gives worse code, and appears to be unnecessary, since no
1498 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1499 || find_reg_note (i3
, REG_LIBCALL
, NULL_RTX
)
1505 undobuf
.other_insn
= 0;
1507 /* Save the current high-water-mark so we can free storage if we didn't
1508 accept this combination. */
1509 undobuf
.storage
= (char *) oballoc (0);
1511 /* Reset the hard register usage information. */
1512 CLEAR_HARD_REG_SET (newpat_used_regs
);
1514 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1515 code below, set I1 to be the earlier of the two insns. */
1516 if (i1
&& INSN_CUID (i1
) > INSN_CUID (i2
))
1517 temp
= i1
, i1
= i2
, i2
= temp
;
1519 added_links_insn
= 0;
1521 /* First check for one important special-case that the code below will
1522 not handle. Namely, the case where I1 is zero, I2 has multiple sets,
1523 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1524 we may be able to replace that destination with the destination of I3.
1525 This occurs in the common code where we compute both a quotient and
1526 remainder into a structure, in which case we want to do the computation
1527 directly into the structure to avoid register-register copies.
1529 We make very conservative checks below and only try to handle the
1530 most common cases of this. For example, we only handle the case
1531 where I2 and I3 are adjacent to avoid making difficult register
1534 if (i1
== 0 && GET_CODE (i3
) == INSN
&& GET_CODE (PATTERN (i3
)) == SET
1535 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1536 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1537 && (! SMALL_REGISTER_CLASSES
1538 || (GET_CODE (SET_DEST (PATTERN (i3
))) != REG
1539 || REGNO (SET_DEST (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
1540 || REG_USERVAR_P (SET_DEST (PATTERN (i3
)))))
1541 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
1542 && GET_CODE (PATTERN (i2
)) == PARALLEL
1543 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
1544 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1545 below would need to check what is inside (and reg_overlap_mentioned_p
1546 doesn't support those codes anyway). Don't allow those destinations;
1547 the resulting insn isn't likely to be recognized anyway. */
1548 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
1549 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
1550 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
1551 SET_DEST (PATTERN (i3
)))
1552 && next_real_insn (i2
) == i3
)
1554 rtx p2
= PATTERN (i2
);
1556 /* Make sure that the destination of I3,
1557 which we are going to substitute into one output of I2,
1558 is not used within another output of I2. We must avoid making this:
1559 (parallel [(set (mem (reg 69)) ...)
1560 (set (reg 69) ...)])
1561 which is not well-defined as to order of actions.
1562 (Besides, reload can't handle output reloads for this.)
1564 The problem can also happen if the dest of I3 is a memory ref,
1565 if another dest in I2 is an indirect memory ref. */
1566 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1567 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1568 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1569 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
1570 SET_DEST (XVECEXP (p2
, 0, i
))))
1573 if (i
== XVECLEN (p2
, 0))
1574 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
1575 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
1576 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
1577 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
1582 subst_low_cuid
= INSN_CUID (i2
);
1584 added_sets_2
= added_sets_1
= 0;
1585 i2dest
= SET_SRC (PATTERN (i3
));
1587 /* Replace the dest in I2 with our dest and make the resulting
1588 insn the new pattern for I3. Then skip to where we
1589 validate the pattern. Everything was set up above. */
1590 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)),
1591 SET_DEST (PATTERN (i3
)));
1594 i3_subst_into_i2
= 1;
1595 goto validate_replacement
;
1599 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1600 one of those words to another constant, merge them by making a new
1603 && (temp
= single_set (i2
)) != 0
1604 && (GET_CODE (SET_SRC (temp
)) == CONST_INT
1605 || GET_CODE (SET_SRC (temp
)) == CONST_DOUBLE
)
1606 && GET_CODE (SET_DEST (temp
)) == REG
1607 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp
))) == MODE_INT
1608 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp
))) == 2 * UNITS_PER_WORD
1609 && GET_CODE (PATTERN (i3
)) == SET
1610 && GET_CODE (SET_DEST (PATTERN (i3
))) == SUBREG
1611 && SUBREG_REG (SET_DEST (PATTERN (i3
))) == SET_DEST (temp
)
1612 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3
)))) == MODE_INT
1613 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3
)))) == UNITS_PER_WORD
1614 && GET_CODE (SET_SRC (PATTERN (i3
))) == CONST_INT
)
1616 HOST_WIDE_INT lo
, hi
;
1618 if (GET_CODE (SET_SRC (temp
)) == CONST_INT
)
1619 lo
= INTVAL (SET_SRC (temp
)), hi
= lo
< 0 ? -1 : 0;
1622 lo
= CONST_DOUBLE_LOW (SET_SRC (temp
));
1623 hi
= CONST_DOUBLE_HIGH (SET_SRC (temp
));
1626 if (subreg_lowpart_p (SET_DEST (PATTERN (i3
))))
1627 lo
= INTVAL (SET_SRC (PATTERN (i3
)));
1629 hi
= INTVAL (SET_SRC (PATTERN (i3
)));
1633 subst_low_cuid
= INSN_CUID (i2
);
1634 added_sets_2
= added_sets_1
= 0;
1635 i2dest
= SET_DEST (temp
);
1637 SUBST (SET_SRC (temp
),
1638 immed_double_const (lo
, hi
, GET_MODE (SET_DEST (temp
))));
1640 newpat
= PATTERN (i2
);
1641 i3_subst_into_i2
= 1;
1642 goto validate_replacement
;
1646 /* If we have no I1 and I2 looks like:
1647 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1649 make up a dummy I1 that is
1652 (set (reg:CC X) (compare:CC Y (const_int 0)))
1654 (We can ignore any trailing CLOBBERs.)
1656 This undoes a previous combination and allows us to match a branch-and-
1659 if (i1
== 0 && GET_CODE (PATTERN (i2
)) == PARALLEL
1660 && XVECLEN (PATTERN (i2
), 0) >= 2
1661 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 0)) == SET
1662 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
1664 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
1665 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
1666 && GET_CODE (XVECEXP (PATTERN (i2
), 0, 1)) == SET
1667 && GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1))) == REG
1668 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
1669 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1))))
1671 for (i
= XVECLEN (PATTERN (i2
), 0) - 1; i
>= 2; i
--)
1672 if (GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) != CLOBBER
)
1677 /* We make I1 with the same INSN_UID as I2. This gives it
1678 the same INSN_CUID for value tracking. Our fake I1 will
1679 never appear in the insn stream so giving it the same INSN_UID
1680 as I2 will not cause a problem. */
1682 subst_prev_insn
= i1
1683 = gen_rtx_INSN (VOIDmode
, INSN_UID (i2
), NULL_RTX
, i2
,
1684 XVECEXP (PATTERN (i2
), 0, 1), -1, NULL_RTX
,
1687 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
1688 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
1689 SET_DEST (PATTERN (i1
)));
1694 /* Verify that I2 and I1 are valid for combining. */
1695 if (! can_combine_p (i2
, i3
, i1
, NULL_RTX
, &i2dest
, &i2src
)
1696 || (i1
&& ! can_combine_p (i1
, i3
, NULL_RTX
, i2
, &i1dest
, &i1src
)))
1702 /* Record whether I2DEST is used in I2SRC and similarly for the other
1703 cases. Knowing this will help in register status updating below. */
1704 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
1705 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
1706 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
1708 /* See if I1 directly feeds into I3. It does if I1DEST is not used
1710 i1_feeds_i3
= i1
&& ! reg_overlap_mentioned_p (i1dest
, i2src
);
1712 /* Ensure that I3's pattern can be the destination of combines. */
1713 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
,
1714 i1
&& i2dest_in_i1src
&& i1_feeds_i3
,
1721 /* See if any of the insns is a MULT operation. Unless one is, we will
1722 reject a combination that is, since it must be slower. Be conservative
1724 if (GET_CODE (i2src
) == MULT
1725 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
1726 || (GET_CODE (PATTERN (i3
)) == SET
1727 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
1730 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
1731 We used to do this EXCEPT in one case: I3 has a post-inc in an
1732 output operand. However, that exception can give rise to insns like
1734 which is a famous insn on the PDP-11 where the value of r3 used as the
1735 source was model-dependent. Avoid this sort of thing. */
1738 if (!(GET_CODE (PATTERN (i3
)) == SET
1739 && GET_CODE (SET_SRC (PATTERN (i3
))) == REG
1740 && GET_CODE (SET_DEST (PATTERN (i3
))) == MEM
1741 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
1742 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
1743 /* It's not the exception. */
1746 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
1747 if (REG_NOTE_KIND (link
) == REG_INC
1748 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
1750 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
1757 /* See if the SETs in I1 or I2 need to be kept around in the merged
1758 instruction: whenever the value set there is still needed past I3.
1759 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
1761 For the SET in I1, we have two cases: If I1 and I2 independently
1762 feed into I3, the set in I1 needs to be kept around if I1DEST dies
1763 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
1764 in I1 needs to be kept around unless I1DEST dies or is set in either
1765 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
1766 I1DEST. If so, we know I1 feeds into I2. */
1768 added_sets_2
= ! dead_or_set_p (i3
, i2dest
);
1771 = i1
&& ! (i1_feeds_i3
? dead_or_set_p (i3
, i1dest
)
1772 : (dead_or_set_p (i3
, i1dest
) || dead_or_set_p (i2
, i1dest
)));
1774 /* If the set in I2 needs to be kept around, we must make a copy of
1775 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
1776 PATTERN (I2), we are only substituting for the original I1DEST, not into
1777 an already-substituted copy. This also prevents making self-referential
1778 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
1781 i2pat
= (GET_CODE (PATTERN (i2
)) == PARALLEL
1782 ? gen_rtx_SET (VOIDmode
, i2dest
, i2src
)
1786 i2pat
= copy_rtx (i2pat
);
1790 /* Substitute in the latest insn for the regs set by the earlier ones. */
1792 maxreg
= max_reg_num ();
1796 /* It is possible that the source of I2 or I1 may be performing an
1797 unneeded operation, such as a ZERO_EXTEND of something that is known
1798 to have the high part zero. Handle that case by letting subst look at
1799 the innermost one of them.
1801 Another way to do this would be to have a function that tries to
1802 simplify a single insn instead of merging two or more insns. We don't
1803 do this because of the potential of infinite loops and because
1804 of the potential extra memory required. However, doing it the way
1805 we are is a bit of a kludge and doesn't catch all cases.
1807 But only do this if -fexpensive-optimizations since it slows things down
1808 and doesn't usually win. */
1810 if (flag_expensive_optimizations
)
1812 /* Pass pc_rtx so no substitutions are done, just simplifications.
1813 The cases that we are interested in here do not involve the few
1814 cases were is_replaced is checked. */
1817 subst_low_cuid
= INSN_CUID (i1
);
1818 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0);
1822 subst_low_cuid
= INSN_CUID (i2
);
1823 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0);
1826 undobuf
.previous_undos
= undobuf
.undos
;
1830 /* Many machines that don't use CC0 have insns that can both perform an
1831 arithmetic operation and set the condition code. These operations will
1832 be represented as a PARALLEL with the first element of the vector
1833 being a COMPARE of an arithmetic operation with the constant zero.
1834 The second element of the vector will set some pseudo to the result
1835 of the same arithmetic operation. If we simplify the COMPARE, we won't
1836 match such a pattern and so will generate an extra insn. Here we test
1837 for this case, where both the comparison and the operation result are
1838 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
1839 I2SRC. Later we will make the PARALLEL that contains I2. */
1841 if (i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
1842 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
1843 && XEXP (SET_SRC (PATTERN (i3
)), 1) == const0_rtx
1844 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
1846 #ifdef EXTRA_CC_MODES
1848 enum machine_mode compare_mode
;
1851 newpat
= PATTERN (i3
);
1852 SUBST (XEXP (SET_SRC (newpat
), 0), i2src
);
1856 #ifdef EXTRA_CC_MODES
1857 /* See if a COMPARE with the operand we substituted in should be done
1858 with the mode that is currently being used. If not, do the same
1859 processing we do in `subst' for a SET; namely, if the destination
1860 is used only once, try to replace it with a register of the proper
1861 mode and also replace the COMPARE. */
1862 if (undobuf
.other_insn
== 0
1863 && (cc_use
= find_single_use (SET_DEST (newpat
), i3
,
1864 &undobuf
.other_insn
))
1865 && ((compare_mode
= SELECT_CC_MODE (GET_CODE (*cc_use
),
1867 != GET_MODE (SET_DEST (newpat
))))
1869 int regno
= REGNO (SET_DEST (newpat
));
1870 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
1872 if (regno
< FIRST_PSEUDO_REGISTER
1873 || (REG_N_SETS (regno
) == 1 && ! added_sets_2
1874 && ! REG_USERVAR_P (SET_DEST (newpat
))))
1876 if (regno
>= FIRST_PSEUDO_REGISTER
)
1877 SUBST (regno_reg_rtx
[regno
], new_dest
);
1879 SUBST (SET_DEST (newpat
), new_dest
);
1880 SUBST (XEXP (*cc_use
, 0), new_dest
);
1881 SUBST (SET_SRC (newpat
),
1882 gen_rtx_combine (COMPARE
, compare_mode
,
1883 i2src
, const0_rtx
));
1886 undobuf
.other_insn
= 0;
1893 n_occurrences
= 0; /* `subst' counts here */
1895 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
1896 need to make a unique copy of I2SRC each time we substitute it
1897 to avoid self-referential rtl. */
1899 subst_low_cuid
= INSN_CUID (i2
);
1900 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0,
1901 ! i1_feeds_i3
&& i1dest_in_i1src
);
1902 undobuf
.previous_undos
= undobuf
.undos
;
1904 /* Record whether i2's body now appears within i3's body. */
1905 i2_is_used
= n_occurrences
;
1908 /* If we already got a failure, don't try to do more. Otherwise,
1909 try to substitute in I1 if we have it. */
1911 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
1913 /* Before we can do this substitution, we must redo the test done
1914 above (see detailed comments there) that ensures that I1DEST
1915 isn't mentioned in any SETs in NEWPAT that are field assignments. */
1917 if (! combinable_i3pat (NULL_RTX
, &newpat
, i1dest
, NULL_RTX
,
1925 subst_low_cuid
= INSN_CUID (i1
);
1926 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0);
1927 undobuf
.previous_undos
= undobuf
.undos
;
1930 /* Fail if an autoincrement side-effect has been duplicated. Be careful
1931 to count all the ways that I2SRC and I1SRC can be used. */
1932 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
1933 && i2_is_used
+ added_sets_2
> 1)
1934 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
1935 && (n_occurrences
+ added_sets_1
+ (added_sets_2
&& ! i1_feeds_i3
)
1937 /* Fail if we tried to make a new register (we used to abort, but there's
1938 really no reason to). */
1939 || max_reg_num () != maxreg
1940 /* Fail if we couldn't do something and have a CLOBBER. */
1941 || GET_CODE (newpat
) == CLOBBER
1942 /* Fail if this new pattern is a MULT and we didn't have one before
1943 at the outer level. */
1944 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
1951 /* If the actions of the earlier insns must be kept
1952 in addition to substituting them into the latest one,
1953 we must make a new PARALLEL for the latest insn
1954 to hold additional the SETs. */
1956 if (added_sets_1
|| added_sets_2
)
1960 if (GET_CODE (newpat
) == PARALLEL
)
1962 rtvec old
= XVEC (newpat
, 0);
1963 total_sets
= XVECLEN (newpat
, 0) + added_sets_1
+ added_sets_2
;
1964 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1965 bcopy ((char *) &old
->elem
[0], (char *) XVEC (newpat
, 0)->elem
,
1966 sizeof (old
->elem
[0]) * old
->num_elem
);
1971 total_sets
= 1 + added_sets_1
+ added_sets_2
;
1972 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
1973 XVECEXP (newpat
, 0, 0) = old
;
1977 XVECEXP (newpat
, 0, --total_sets
)
1978 = (GET_CODE (PATTERN (i1
)) == PARALLEL
1979 ? gen_rtx_SET (VOIDmode
, i1dest
, i1src
) : PATTERN (i1
));
1983 /* If there is no I1, use I2's body as is. We used to also not do
1984 the subst call below if I2 was substituted into I3,
1985 but that could lose a simplification. */
1987 XVECEXP (newpat
, 0, --total_sets
) = i2pat
;
1989 /* See comment where i2pat is assigned. */
1990 XVECEXP (newpat
, 0, --total_sets
)
1991 = subst (i2pat
, i1dest
, i1src
, 0, 0);
1995 /* We come here when we are replacing a destination in I2 with the
1996 destination of I3. */
1997 validate_replacement
:
1999 /* Note which hard regs this insn has as inputs. */
2000 mark_used_regs_combine (newpat
);
2002 /* Is the result of combination a valid instruction? */
2003 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2005 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2006 the second SET's destination is a register that is unused. In that case,
2007 we just need the first SET. This can occur when simplifying a divmod
2008 insn. We *must* test for this case here because the code below that
2009 splits two independent SETs doesn't handle this case correctly when it
2010 updates the register status. Also check the case where the first
2011 SET's destination is unused. That would not cause incorrect code, but
2012 does cause an unneeded insn to remain. */
2014 if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2015 && XVECLEN (newpat
, 0) == 2
2016 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2017 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2018 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == REG
2019 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 1)))
2020 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 1)))
2021 && asm_noperands (newpat
) < 0)
2023 newpat
= XVECEXP (newpat
, 0, 0);
2024 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2027 else if (insn_code_number
< 0 && GET_CODE (newpat
) == PARALLEL
2028 && XVECLEN (newpat
, 0) == 2
2029 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2030 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2031 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) == REG
2032 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (XVECEXP (newpat
, 0, 0)))
2033 && ! side_effects_p (SET_SRC (XVECEXP (newpat
, 0, 0)))
2034 && asm_noperands (newpat
) < 0)
2036 newpat
= XVECEXP (newpat
, 0, 1);
2037 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2040 /* If we were combining three insns and the result is a simple SET
2041 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2042 insns. There are two ways to do this. It can be split using a
2043 machine-specific method (like when you have an addition of a large
2044 constant) or by combine in the function find_split_point. */
2046 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
2047 && asm_noperands (newpat
) < 0)
2049 rtx m_split
, *split
;
2050 rtx ni2dest
= i2dest
;
2052 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2053 use I2DEST as a scratch register will help. In the latter case,
2054 convert I2DEST to the mode of the source of NEWPAT if we can. */
2056 m_split
= split_insns (newpat
, i3
);
2058 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2059 inputs of NEWPAT. */
2061 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2062 possible to try that as a scratch reg. This would require adding
2063 more code to make it work though. */
2065 if (m_split
== 0 && ! reg_overlap_mentioned_p (ni2dest
, newpat
))
2067 /* If I2DEST is a hard register or the only use of a pseudo,
2068 we can change its mode. */
2069 if (GET_MODE (SET_DEST (newpat
)) != GET_MODE (i2dest
)
2070 && GET_MODE (SET_DEST (newpat
)) != VOIDmode
2071 && GET_CODE (i2dest
) == REG
2072 && (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2073 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2074 && ! REG_USERVAR_P (i2dest
))))
2075 ni2dest
= gen_rtx_REG (GET_MODE (SET_DEST (newpat
)),
2078 m_split
= split_insns (gen_rtx_PARALLEL
2080 gen_rtvec (2, newpat
,
2081 gen_rtx_CLOBBER (VOIDmode
,
2086 if (m_split
&& GET_CODE (m_split
) == SEQUENCE
2087 && XVECLEN (m_split
, 0) == 2
2088 && (next_real_insn (i2
) == i3
2089 || ! use_crosses_set_p (PATTERN (XVECEXP (m_split
, 0, 0)),
2093 rtx newi3pat
= PATTERN (XVECEXP (m_split
, 0, 1));
2094 newi2pat
= PATTERN (XVECEXP (m_split
, 0, 0));
2096 i3set
= single_set (XVECEXP (m_split
, 0, 1));
2097 i2set
= single_set (XVECEXP (m_split
, 0, 0));
2099 /* In case we changed the mode of I2DEST, replace it in the
2100 pseudo-register table here. We can't do it above in case this
2101 code doesn't get executed and we do a split the other way. */
2103 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2104 SUBST (regno_reg_rtx
[REGNO (i2dest
)], ni2dest
);
2106 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2108 /* If I2 or I3 has multiple SETs, we won't know how to track
2109 register status, so don't use these insns. If I2's destination
2110 is used between I2 and I3, we also can't use these insns. */
2112 if (i2_code_number
>= 0 && i2set
&& i3set
2113 && (next_real_insn (i2
) == i3
2114 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
2115 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
2117 if (insn_code_number
>= 0)
2120 /* It is possible that both insns now set the destination of I3.
2121 If so, we must show an extra use of it. */
2123 if (insn_code_number
>= 0)
2125 rtx new_i3_dest
= SET_DEST (i3set
);
2126 rtx new_i2_dest
= SET_DEST (i2set
);
2128 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
2129 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
2130 || GET_CODE (new_i3_dest
) == SUBREG
)
2131 new_i3_dest
= XEXP (new_i3_dest
, 0);
2133 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
2134 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
2135 || GET_CODE (new_i2_dest
) == SUBREG
)
2136 new_i2_dest
= XEXP (new_i2_dest
, 0);
2138 if (GET_CODE (new_i3_dest
) == REG
2139 && GET_CODE (new_i2_dest
) == REG
2140 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
))
2141 REG_N_SETS (REGNO (new_i2_dest
))++;
2145 /* If we can split it and use I2DEST, go ahead and see if that
2146 helps things be recognized. Verify that none of the registers
2147 are set between I2 and I3. */
2148 if (insn_code_number
< 0 && (split
= find_split_point (&newpat
, i3
)) != 0
2150 && GET_CODE (i2dest
) == REG
2152 /* We need I2DEST in the proper mode. If it is a hard register
2153 or the only use of a pseudo, we can change its mode. */
2154 && (GET_MODE (*split
) == GET_MODE (i2dest
)
2155 || GET_MODE (*split
) == VOIDmode
2156 || REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
2157 || (REG_N_SETS (REGNO (i2dest
)) == 1 && ! added_sets_2
2158 && ! REG_USERVAR_P (i2dest
)))
2159 && (next_real_insn (i2
) == i3
2160 || ! use_crosses_set_p (*split
, INSN_CUID (i2
)))
2161 /* We can't overwrite I2DEST if its value is still used by
2163 && ! reg_referenced_p (i2dest
, newpat
))
2165 rtx newdest
= i2dest
;
2166 enum rtx_code split_code
= GET_CODE (*split
);
2167 enum machine_mode split_mode
= GET_MODE (*split
);
2169 /* Get NEWDEST as a register in the proper mode. We have already
2170 validated that we can do this. */
2171 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
2173 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
2175 if (REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
2176 SUBST (regno_reg_rtx
[REGNO (i2dest
)], newdest
);
2179 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2180 an ASHIFT. This can occur if it was inside a PLUS and hence
2181 appeared to be a memory address. This is a kludge. */
2182 if (split_code
== MULT
2183 && GET_CODE (XEXP (*split
, 1)) == CONST_INT
2184 && (i
= exact_log2 (INTVAL (XEXP (*split
, 1)))) >= 0)
2186 SUBST (*split
, gen_rtx_combine (ASHIFT
, split_mode
,
2187 XEXP (*split
, 0), GEN_INT (i
)));
2188 /* Update split_code because we may not have a multiply
2190 split_code
= GET_CODE (*split
);
2193 #ifdef INSN_SCHEDULING
2194 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2195 be written as a ZERO_EXTEND. */
2196 if (split_code
== SUBREG
&& GET_CODE (SUBREG_REG (*split
)) == MEM
)
2197 SUBST (*split
, gen_rtx_combine (ZERO_EXTEND
, split_mode
,
2201 newi2pat
= gen_rtx_combine (SET
, VOIDmode
, newdest
, *split
);
2202 SUBST (*split
, newdest
);
2203 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2205 /* If the split point was a MULT and we didn't have one before,
2206 don't use one now. */
2207 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
2208 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2212 /* Check for a case where we loaded from memory in a narrow mode and
2213 then sign extended it, but we need both registers. In that case,
2214 we have a PARALLEL with both loads from the same memory location.
2215 We can split this into a load from memory followed by a register-register
2216 copy. This saves at least one insn, more if register allocation can
2219 We cannot do this if the destination of the second assignment is
2220 a register that we have already assumed is zero-extended. Similarly
2221 for a SUBREG of such a register. */
2223 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2224 && GET_CODE (newpat
) == PARALLEL
2225 && XVECLEN (newpat
, 0) == 2
2226 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2227 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
2228 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2229 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2230 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
2231 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2233 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2234 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2235 && ! (temp
= SET_DEST (XVECEXP (newpat
, 0, 1)),
2236 (GET_CODE (temp
) == REG
2237 && reg_nonzero_bits
[REGNO (temp
)] != 0
2238 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2239 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2240 && (reg_nonzero_bits
[REGNO (temp
)]
2241 != GET_MODE_MASK (word_mode
))))
2242 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
2243 && (temp
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
2244 (GET_CODE (temp
) == REG
2245 && reg_nonzero_bits
[REGNO (temp
)] != 0
2246 && GET_MODE_BITSIZE (GET_MODE (temp
)) < BITS_PER_WORD
2247 && GET_MODE_BITSIZE (GET_MODE (temp
)) < HOST_BITS_PER_INT
2248 && (reg_nonzero_bits
[REGNO (temp
)]
2249 != GET_MODE_MASK (word_mode
)))))
2250 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2251 SET_SRC (XVECEXP (newpat
, 0, 1)))
2252 && ! find_reg_note (i3
, REG_UNUSED
,
2253 SET_DEST (XVECEXP (newpat
, 0, 0))))
2257 newi2pat
= XVECEXP (newpat
, 0, 0);
2258 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
2259 newpat
= XVECEXP (newpat
, 0, 1);
2260 SUBST (SET_SRC (newpat
),
2261 gen_lowpart_for_combine (GET_MODE (SET_SRC (newpat
)), ni2dest
));
2262 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2264 if (i2_code_number
>= 0)
2265 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2267 if (insn_code_number
>= 0)
2272 /* If we will be able to accept this, we have made a change to the
2273 destination of I3. This can invalidate a LOG_LINKS pointing
2274 to I3. No other part of combine.c makes such a transformation.
2276 The new I3 will have a destination that was previously the
2277 destination of I1 or I2 and which was used in i2 or I3. Call
2278 distribute_links to make a LOG_LINK from the next use of
2279 that destination. */
2281 PATTERN (i3
) = newpat
;
2282 distribute_links (gen_rtx_INSN_LIST (VOIDmode
, i3
, NULL_RTX
));
2284 /* I3 now uses what used to be its destination and which is
2285 now I2's destination. That means we need a LOG_LINK from
2286 I3 to I2. But we used to have one, so we still will.
2288 However, some later insn might be using I2's dest and have
2289 a LOG_LINK pointing at I3. We must remove this link.
2290 The simplest way to remove the link is to point it at I1,
2291 which we know will be a NOTE. */
2293 for (insn
= NEXT_INSN (i3
);
2294 insn
&& (this_basic_block
== n_basic_blocks
- 1
2295 || insn
!= BLOCK_HEAD (this_basic_block
+ 1));
2296 insn
= NEXT_INSN (insn
))
2298 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
2299 && reg_referenced_p (ni2dest
, PATTERN (insn
)))
2301 for (link
= LOG_LINKS (insn
); link
;
2302 link
= XEXP (link
, 1))
2303 if (XEXP (link
, 0) == i3
)
2304 XEXP (link
, 0) = i1
;
2312 /* Similarly, check for a case where we have a PARALLEL of two independent
2313 SETs but we started with three insns. In this case, we can do the sets
2314 as two separate insns. This case occurs when some SET allows two
2315 other insns to combine, but the destination of that SET is still live. */
2317 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
2318 && GET_CODE (newpat
) == PARALLEL
2319 && XVECLEN (newpat
, 0) == 2
2320 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
2321 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
2322 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
2323 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
2324 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
2325 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
2326 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
2328 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2329 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != USE
2330 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != USE
2331 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
2332 XVECEXP (newpat
, 0, 0))
2333 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
2334 XVECEXP (newpat
, 0, 1))
2335 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
2336 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
2338 /* Normally, it doesn't matter which of the two is done first,
2339 but it does if one references cc0. In that case, it has to
2342 if (reg_referenced_p (cc0_rtx
, XVECEXP (newpat
, 0, 0)))
2344 newi2pat
= XVECEXP (newpat
, 0, 0);
2345 newpat
= XVECEXP (newpat
, 0, 1);
2350 newi2pat
= XVECEXP (newpat
, 0, 1);
2351 newpat
= XVECEXP (newpat
, 0, 0);
2354 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
2356 if (i2_code_number
>= 0)
2357 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
2360 /* If it still isn't recognized, fail and change things back the way they
2362 if ((insn_code_number
< 0
2363 /* Is the result a reasonable ASM_OPERANDS? */
2364 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
2370 /* If we had to change another insn, make sure it is valid also. */
2371 if (undobuf
.other_insn
)
2373 rtx other_pat
= PATTERN (undobuf
.other_insn
);
2374 rtx new_other_notes
;
2377 CLEAR_HARD_REG_SET (newpat_used_regs
);
2379 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
2382 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
2388 PATTERN (undobuf
.other_insn
) = other_pat
;
2390 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2391 are still valid. Then add any non-duplicate notes added by
2392 recog_for_combine. */
2393 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
2395 next
= XEXP (note
, 1);
2397 if (REG_NOTE_KIND (note
) == REG_UNUSED
2398 && ! reg_set_p (XEXP (note
, 0), PATTERN (undobuf
.other_insn
)))
2400 if (GET_CODE (XEXP (note
, 0)) == REG
)
2401 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
2403 remove_note (undobuf
.other_insn
, note
);
2407 for (note
= new_other_notes
; note
; note
= XEXP (note
, 1))
2408 if (GET_CODE (XEXP (note
, 0)) == REG
)
2409 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
2411 distribute_notes (new_other_notes
, undobuf
.other_insn
,
2412 undobuf
.other_insn
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2415 /* If I2 is the setter CC0 and I3 is the user CC0 then check whether
2416 they are adjacent to each other or not. */
2418 rtx p
= prev_nonnote_insn (i3
);
2419 if (p
&& p
!= i2
&& GET_CODE (p
) == INSN
&& newi2pat
&& sets_cc0_p (newi2pat
))
2427 /* We now know that we can do this combination. Merge the insns and
2428 update the status of registers and LOG_LINKS. */
2431 rtx i3notes
, i2notes
, i1notes
= 0;
2432 rtx i3links
, i2links
, i1links
= 0;
2435 /* Compute which registers we expect to eliminate. newi2pat may be setting
2436 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2437 same as i3dest, in which case newi2pat may be setting i1dest. */
2438 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2439 || i2dest_in_i2src
|| i2dest_in_i1src
2441 rtx elim_i1
= (i1
== 0 || i1dest_in_i1src
2442 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2445 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2447 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
2448 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
2450 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
2452 /* Ensure that we do not have something that should not be shared but
2453 occurs multiple times in the new insns. Check this by first
2454 resetting all the `used' flags and then copying anything is shared. */
2456 reset_used_flags (i3notes
);
2457 reset_used_flags (i2notes
);
2458 reset_used_flags (i1notes
);
2459 reset_used_flags (newpat
);
2460 reset_used_flags (newi2pat
);
2461 if (undobuf
.other_insn
)
2462 reset_used_flags (PATTERN (undobuf
.other_insn
));
2464 i3notes
= copy_rtx_if_shared (i3notes
);
2465 i2notes
= copy_rtx_if_shared (i2notes
);
2466 i1notes
= copy_rtx_if_shared (i1notes
);
2467 newpat
= copy_rtx_if_shared (newpat
);
2468 newi2pat
= copy_rtx_if_shared (newi2pat
);
2469 if (undobuf
.other_insn
)
2470 reset_used_flags (PATTERN (undobuf
.other_insn
));
2472 INSN_CODE (i3
) = insn_code_number
;
2473 PATTERN (i3
) = newpat
;
2474 if (undobuf
.other_insn
)
2475 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
2477 /* We had one special case above where I2 had more than one set and
2478 we replaced a destination of one of those sets with the destination
2479 of I3. In that case, we have to update LOG_LINKS of insns later
2480 in this basic block. Note that this (expensive) case is rare.
2482 Also, in this case, we must pretend that all REG_NOTEs for I2
2483 actually came from I3, so that REG_UNUSED notes from I2 will be
2484 properly handled. */
2486 if (i3_subst_into_i2
)
2488 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
2490 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
2491 if (GET_CODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))) == REG
2492 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
2493 && ! find_reg_note (i2
, REG_UNUSED
,
2494 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
2495 for (temp
= NEXT_INSN (i2
);
2496 temp
&& (this_basic_block
== n_basic_blocks
- 1
2497 || BLOCK_HEAD (this_basic_block
) != temp
);
2498 temp
= NEXT_INSN (temp
))
2499 if (temp
!= i3
&& GET_RTX_CLASS (GET_CODE (temp
)) == 'i')
2500 for (link
= LOG_LINKS (temp
); link
; link
= XEXP (link
, 1))
2501 if (XEXP (link
, 0) == i2
)
2502 XEXP (link
, 0) = i3
;
2508 while (XEXP (link
, 1))
2509 link
= XEXP (link
, 1);
2510 XEXP (link
, 1) = i2notes
;
2524 INSN_CODE (i2
) = i2_code_number
;
2525 PATTERN (i2
) = newi2pat
;
2529 PUT_CODE (i2
, NOTE
);
2530 NOTE_LINE_NUMBER (i2
) = NOTE_INSN_DELETED
;
2531 NOTE_SOURCE_FILE (i2
) = 0;
2538 PUT_CODE (i1
, NOTE
);
2539 NOTE_LINE_NUMBER (i1
) = NOTE_INSN_DELETED
;
2540 NOTE_SOURCE_FILE (i1
) = 0;
2543 /* Get death notes for everything that is now used in either I3 or
2544 I2 and used to die in a previous insn. If we built two new
2545 patterns, move from I1 to I2 then I2 to I3 so that we get the
2546 proper movement on registers that I2 modifies. */
2550 move_deaths (newi2pat
, NULL_RTX
, INSN_CUID (i1
), i2
, &midnotes
);
2551 move_deaths (newpat
, newi2pat
, INSN_CUID (i1
), i3
, &midnotes
);
2554 move_deaths (newpat
, NULL_RTX
, i1
? INSN_CUID (i1
) : INSN_CUID (i2
),
2557 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2559 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL_RTX
,
2562 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL_RTX
,
2565 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL_RTX
,
2568 distribute_notes (midnotes
, NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2571 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2572 know these are REG_UNUSED and want them to go to the desired insn,
2573 so we always pass it as i3. We have not counted the notes in
2574 reg_n_deaths yet, so we need to do so now. */
2576 if (newi2pat
&& new_i2_notes
)
2578 for (temp
= new_i2_notes
; temp
; temp
= XEXP (temp
, 1))
2579 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2580 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2582 distribute_notes (new_i2_notes
, i2
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2587 for (temp
= new_i3_notes
; temp
; temp
= XEXP (temp
, 1))
2588 if (GET_CODE (XEXP (temp
, 0)) == REG
)
2589 REG_N_DEATHS (REGNO (XEXP (temp
, 0)))++;
2591 distribute_notes (new_i3_notes
, i3
, i3
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2594 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
2595 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
2596 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
2597 in that case, it might delete I2. Similarly for I2 and I1.
2598 Show an additional death due to the REG_DEAD note we make here. If
2599 we discard it in distribute_notes, we will decrement it again. */
2603 if (GET_CODE (i3dest_killed
) == REG
)
2604 REG_N_DEATHS (REGNO (i3dest_killed
))++;
2606 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
2607 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2609 NULL_RTX
, i2
, NULL_RTX
, elim_i2
, elim_i1
);
2611 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i3dest_killed
,
2613 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2617 if (i2dest_in_i2src
)
2619 if (GET_CODE (i2dest
) == REG
)
2620 REG_N_DEATHS (REGNO (i2dest
))++;
2622 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
2623 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2624 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2626 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i2dest
, NULL_RTX
),
2627 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2628 NULL_RTX
, NULL_RTX
);
2631 if (i1dest_in_i1src
)
2633 if (GET_CODE (i1dest
) == REG
)
2634 REG_N_DEATHS (REGNO (i1dest
))++;
2636 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
2637 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2638 NULL_RTX
, i2
, NULL_RTX
, NULL_RTX
, NULL_RTX
);
2640 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD
, i1dest
, NULL_RTX
),
2641 NULL_RTX
, i3
, newi2pat
? i2
: NULL_RTX
,
2642 NULL_RTX
, NULL_RTX
);
2645 distribute_links (i3links
);
2646 distribute_links (i2links
);
2647 distribute_links (i1links
);
2649 if (GET_CODE (i2dest
) == REG
)
2652 rtx i2_insn
= 0, i2_val
= 0, set
;
2654 /* The insn that used to set this register doesn't exist, and
2655 this life of the register may not exist either. See if one of
2656 I3's links points to an insn that sets I2DEST. If it does,
2657 that is now the last known value for I2DEST. If we don't update
2658 this and I2 set the register to a value that depended on its old
2659 contents, we will get confused. If this insn is used, thing
2660 will be set correctly in combine_instructions. */
2662 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2663 if ((set
= single_set (XEXP (link
, 0))) != 0
2664 && rtx_equal_p (i2dest
, SET_DEST (set
)))
2665 i2_insn
= XEXP (link
, 0), i2_val
= SET_SRC (set
);
2667 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
2669 /* If the reg formerly set in I2 died only once and that was in I3,
2670 zero its use count so it won't make `reload' do any work. */
2672 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
2673 && ! i2dest_in_i2src
)
2675 regno
= REGNO (i2dest
);
2676 REG_N_SETS (regno
)--;
2680 if (i1
&& GET_CODE (i1dest
) == REG
)
2683 rtx i1_insn
= 0, i1_val
= 0, set
;
2685 for (link
= LOG_LINKS (i3
); link
; link
= XEXP (link
, 1))
2686 if ((set
= single_set (XEXP (link
, 0))) != 0
2687 && rtx_equal_p (i1dest
, SET_DEST (set
)))
2688 i1_insn
= XEXP (link
, 0), i1_val
= SET_SRC (set
);
2690 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
2692 regno
= REGNO (i1dest
);
2693 if (! added_sets_1
&& ! i1dest_in_i1src
)
2695 REG_N_SETS (regno
)--;
2699 /* Update reg_nonzero_bits et al for any changes that may have been made
2702 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
2704 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
2706 /* Set new_direct_jump_p if a new return or simple jump instruction
2709 If I3 is now an unconditional jump, ensure that it has a
2710 BARRIER following it since it may have initially been a
2711 conditional jump. It may also be the last nonnote insn. */
2713 if (GET_CODE (newpat
) == RETURN
|| simplejump_p (i3
))
2715 *new_direct_jump_p
= 1;
2717 if ((temp
= next_nonnote_insn (i3
)) == NULL_RTX
2718 || GET_CODE (temp
) != BARRIER
)
2719 emit_barrier_after (i3
);
2723 combine_successes
++;
2726 /* Clear this here, so that subsequent get_last_value calls are not
2728 subst_prev_insn
= NULL_RTX
;
2730 if (added_links_insn
2731 && (newi2pat
== 0 || INSN_CUID (added_links_insn
) < INSN_CUID (i2
))
2732 && INSN_CUID (added_links_insn
) < INSN_CUID (i3
))
2733 return added_links_insn
;
2735 return newi2pat
? i2
: i3
;
2738 /* Undo all the modifications recorded in undobuf. */
2743 struct undo
*undo
, *next
;
2745 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2749 *undo
->where
.i
= undo
->old_contents
.i
;
2751 *undo
->where
.r
= undo
->old_contents
.r
;
2753 undo
->next
= undobuf
.frees
;
2754 undobuf
.frees
= undo
;
2757 obfree (undobuf
.storage
);
2758 undobuf
.undos
= undobuf
.previous_undos
= 0;
2760 /* Clear this here, so that subsequent get_last_value calls are not
2762 subst_prev_insn
= NULL_RTX
;
2765 /* We've committed to accepting the changes we made. Move all
2766 of the undos to the free list. */
2771 struct undo
*undo
, *next
;
2773 for (undo
= undobuf
.undos
; undo
; undo
= next
)
2776 undo
->next
= undobuf
.frees
;
2777 undobuf
.frees
= undo
;
2779 undobuf
.undos
= undobuf
.previous_undos
= 0;
2783 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
2784 where we have an arithmetic expression and return that point. LOC will
2787 try_combine will call this function to see if an insn can be split into
2791 find_split_point (loc
, insn
)
2796 enum rtx_code code
= GET_CODE (x
);
2798 int len
= 0, pos
= 0, unsignedp
= 0;
2799 rtx inner
= NULL_RTX
;
2801 /* First special-case some codes. */
2805 #ifdef INSN_SCHEDULING
2806 /* If we are making a paradoxical SUBREG invalid, it becomes a split
2808 if (GET_CODE (SUBREG_REG (x
)) == MEM
)
2811 return find_split_point (&SUBREG_REG (x
), insn
);
2815 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
2816 using LO_SUM and HIGH. */
2817 if (GET_CODE (XEXP (x
, 0)) == CONST
2818 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
)
2821 gen_rtx_combine (LO_SUM
, Pmode
,
2822 gen_rtx_combine (HIGH
, Pmode
, XEXP (x
, 0)),
2824 return &XEXP (XEXP (x
, 0), 0);
2828 /* If we have a PLUS whose second operand is a constant and the
2829 address is not valid, perhaps will can split it up using
2830 the machine-specific way to split large constants. We use
2831 the first pseudo-reg (one of the virtual regs) as a placeholder;
2832 it will not remain in the result. */
2833 if (GET_CODE (XEXP (x
, 0)) == PLUS
2834 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2835 && ! memory_address_p (GET_MODE (x
), XEXP (x
, 0)))
2837 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
2838 rtx seq
= split_insns (gen_rtx_SET (VOIDmode
, reg
, XEXP (x
, 0)),
2841 /* This should have produced two insns, each of which sets our
2842 placeholder. If the source of the second is a valid address,
2843 we can make put both sources together and make a split point
2846 if (seq
&& XVECLEN (seq
, 0) == 2
2847 && GET_CODE (XVECEXP (seq
, 0, 0)) == INSN
2848 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 0))) == SET
2849 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 0))) == reg
2850 && ! reg_mentioned_p (reg
,
2851 SET_SRC (PATTERN (XVECEXP (seq
, 0, 0))))
2852 && GET_CODE (XVECEXP (seq
, 0, 1)) == INSN
2853 && GET_CODE (PATTERN (XVECEXP (seq
, 0, 1))) == SET
2854 && SET_DEST (PATTERN (XVECEXP (seq
, 0, 1))) == reg
2855 && memory_address_p (GET_MODE (x
),
2856 SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)))))
2858 rtx src1
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 0)));
2859 rtx src2
= SET_SRC (PATTERN (XVECEXP (seq
, 0, 1)));
2861 /* Replace the placeholder in SRC2 with SRC1. If we can
2862 find where in SRC2 it was placed, that can become our
2863 split point and we can replace this address with SRC2.
2864 Just try two obvious places. */
2866 src2
= replace_rtx (src2
, reg
, src1
);
2868 if (XEXP (src2
, 0) == src1
)
2869 split
= &XEXP (src2
, 0);
2870 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
2871 && XEXP (XEXP (src2
, 0), 0) == src1
)
2872 split
= &XEXP (XEXP (src2
, 0), 0);
2876 SUBST (XEXP (x
, 0), src2
);
2881 /* If that didn't work, perhaps the first operand is complex and
2882 needs to be computed separately, so make a split point there.
2883 This will occur on machines that just support REG + CONST
2884 and have a constant moved through some previous computation. */
2886 else if (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) != 'o'
2887 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
2888 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (XEXP (x
, 0), 0))))
2890 return &XEXP (XEXP (x
, 0), 0);
2896 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
2897 ZERO_EXTRACT, the most likely reason why this doesn't match is that
2898 we need to put the operand into a register. So split at that
2901 if (SET_DEST (x
) == cc0_rtx
2902 && GET_CODE (SET_SRC (x
)) != COMPARE
2903 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
2904 && GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) != 'o'
2905 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
2906 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (SET_SRC (x
)))) == 'o'))
2907 return &SET_SRC (x
);
2910 /* See if we can split SET_SRC as it stands. */
2911 split
= find_split_point (&SET_SRC (x
), insn
);
2912 if (split
&& split
!= &SET_SRC (x
))
2915 /* See if we can split SET_DEST as it stands. */
2916 split
= find_split_point (&SET_DEST (x
), insn
);
2917 if (split
&& split
!= &SET_DEST (x
))
2920 /* See if this is a bitfield assignment with everything constant. If
2921 so, this is an IOR of an AND, so split it into that. */
2922 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
2923 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)))
2924 <= HOST_BITS_PER_WIDE_INT
)
2925 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
2926 && GET_CODE (XEXP (SET_DEST (x
), 2)) == CONST_INT
2927 && GET_CODE (SET_SRC (x
)) == CONST_INT
2928 && ((INTVAL (XEXP (SET_DEST (x
), 1))
2929 + INTVAL (XEXP (SET_DEST (x
), 2)))
2930 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0))))
2931 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
2933 int pos
= INTVAL (XEXP (SET_DEST (x
), 2));
2934 int len
= INTVAL (XEXP (SET_DEST (x
), 1));
2935 int src
= INTVAL (SET_SRC (x
));
2936 rtx dest
= XEXP (SET_DEST (x
), 0);
2937 enum machine_mode mode
= GET_MODE (dest
);
2938 unsigned HOST_WIDE_INT mask
= ((HOST_WIDE_INT
) 1 << len
) - 1;
2940 if (BITS_BIG_ENDIAN
)
2941 pos
= GET_MODE_BITSIZE (mode
) - len
- pos
;
2943 if ((unsigned HOST_WIDE_INT
) src
== mask
)
2945 gen_binary (IOR
, mode
, dest
, GEN_INT (src
<< pos
)));
2948 gen_binary (IOR
, mode
,
2949 gen_binary (AND
, mode
, dest
,
2950 GEN_INT (~ (mask
<< pos
)
2951 & GET_MODE_MASK (mode
))),
2952 GEN_INT (src
<< pos
)));
2954 SUBST (SET_DEST (x
), dest
);
2956 split
= find_split_point (&SET_SRC (x
), insn
);
2957 if (split
&& split
!= &SET_SRC (x
))
2961 /* Otherwise, see if this is an operation that we can split into two.
2962 If so, try to split that. */
2963 code
= GET_CODE (SET_SRC (x
));
2968 /* If we are AND'ing with a large constant that is only a single
2969 bit and the result is only being used in a context where we
2970 need to know if it is zero or non-zero, replace it with a bit
2971 extraction. This will avoid the large constant, which might
2972 have taken more than one insn to make. If the constant were
2973 not a valid argument to the AND but took only one insn to make,
2974 this is no worse, but if it took more than one insn, it will
2977 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
2978 && GET_CODE (XEXP (SET_SRC (x
), 0)) == REG
2979 && (pos
= exact_log2 (INTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
2980 && GET_CODE (SET_DEST (x
)) == REG
2981 && (split
= find_single_use (SET_DEST (x
), insn
, NULL_PTR
)) != 0
2982 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
2983 && XEXP (*split
, 0) == SET_DEST (x
)
2984 && XEXP (*split
, 1) == const0_rtx
)
2986 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
2987 XEXP (SET_SRC (x
), 0),
2988 pos
, NULL_RTX
, 1, 1, 0, 0);
2989 if (extraction
!= 0)
2991 SUBST (SET_SRC (x
), extraction
);
2992 return find_split_point (loc
, insn
);
2998 /* if STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
2999 is known to be on, this can be converted into a NEG of a shift. */
3000 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
3001 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
3002 && 1 <= (pos
= exact_log2
3003 (nonzero_bits (XEXP (SET_SRC (x
), 0),
3004 GET_MODE (XEXP (SET_SRC (x
), 0))))))
3006 enum machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
3009 gen_rtx_combine (NEG
, mode
,
3010 gen_rtx_combine (LSHIFTRT
, mode
,
3011 XEXP (SET_SRC (x
), 0),
3014 split
= find_split_point (&SET_SRC (x
), insn
);
3015 if (split
&& split
!= &SET_SRC (x
))
3021 inner
= XEXP (SET_SRC (x
), 0);
3023 /* We can't optimize if either mode is a partial integer
3024 mode as we don't know how many bits are significant
3026 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
3027 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
3031 len
= GET_MODE_BITSIZE (GET_MODE (inner
));
3037 if (GET_CODE (XEXP (SET_SRC (x
), 1)) == CONST_INT
3038 && GET_CODE (XEXP (SET_SRC (x
), 2)) == CONST_INT
)
3040 inner
= XEXP (SET_SRC (x
), 0);
3041 len
= INTVAL (XEXP (SET_SRC (x
), 1));
3042 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
3044 if (BITS_BIG_ENDIAN
)
3045 pos
= GET_MODE_BITSIZE (GET_MODE (inner
)) - len
- pos
;
3046 unsignedp
= (code
== ZERO_EXTRACT
);
3054 if (len
&& pos
>= 0 && pos
+ len
<= GET_MODE_BITSIZE (GET_MODE (inner
)))
3056 enum machine_mode mode
= GET_MODE (SET_SRC (x
));
3058 /* For unsigned, we have a choice of a shift followed by an
3059 AND or two shifts. Use two shifts for field sizes where the
3060 constant might be too large. We assume here that we can
3061 always at least get 8-bit constants in an AND insn, which is
3062 true for every current RISC. */
3064 if (unsignedp
&& len
<= 8)
3069 gen_rtx_combine (LSHIFTRT
, mode
,
3070 gen_lowpart_for_combine (mode
, inner
),
3072 GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1)));
3074 split
= find_split_point (&SET_SRC (x
), insn
);
3075 if (split
&& split
!= &SET_SRC (x
))
3082 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
3083 gen_rtx_combine (ASHIFT
, mode
,
3084 gen_lowpart_for_combine (mode
, inner
),
3085 GEN_INT (GET_MODE_BITSIZE (mode
)
3087 GEN_INT (GET_MODE_BITSIZE (mode
) - len
)));
3089 split
= find_split_point (&SET_SRC (x
), insn
);
3090 if (split
&& split
!= &SET_SRC (x
))
3095 /* See if this is a simple operation with a constant as the second
3096 operand. It might be that this constant is out of range and hence
3097 could be used as a split point. */
3098 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3099 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3100 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<')
3101 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
3102 && (GET_RTX_CLASS (GET_CODE (XEXP (SET_SRC (x
), 0))) == 'o'
3103 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
3104 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (SET_SRC (x
), 0))))
3106 return &XEXP (SET_SRC (x
), 1);
3108 /* Finally, see if this is a simple operation with its first operand
3109 not in a register. The operation might require this operand in a
3110 register, so return it as a split point. We can always do this
3111 because if the first operand were another operation, we would have
3112 already found it as a split point. */
3113 if ((GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '2'
3114 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == 'c'
3115 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '<'
3116 || GET_RTX_CLASS (GET_CODE (SET_SRC (x
))) == '1')
3117 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
3118 return &XEXP (SET_SRC (x
), 0);
3124 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3125 it is better to write this as (not (ior A B)) so we can split it.
3126 Similarly for IOR. */
3127 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
3130 gen_rtx_combine (NOT
, GET_MODE (x
),
3131 gen_rtx_combine (code
== IOR
? AND
: IOR
,
3133 XEXP (XEXP (x
, 0), 0),
3134 XEXP (XEXP (x
, 1), 0))));
3135 return find_split_point (loc
, insn
);
3138 /* Many RISC machines have a large set of logical insns. If the
3139 second operand is a NOT, put it first so we will try to split the
3140 other operand first. */
3141 if (GET_CODE (XEXP (x
, 1)) == NOT
)
3143 rtx tem
= XEXP (x
, 0);
3144 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3145 SUBST (XEXP (x
, 1), tem
);
3153 /* Otherwise, select our actions depending on our rtx class. */
3154 switch (GET_RTX_CLASS (code
))
3156 case 'b': /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3158 split
= find_split_point (&XEXP (x
, 2), insn
);
3161 /* ... fall through ... */
3165 split
= find_split_point (&XEXP (x
, 1), insn
);
3168 /* ... fall through ... */
3170 /* Some machines have (and (shift ...) ...) insns. If X is not
3171 an AND, but XEXP (X, 0) is, use it as our split point. */
3172 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
3173 return &XEXP (x
, 0);
3175 split
= find_split_point (&XEXP (x
, 0), insn
);
3181 /* Otherwise, we don't have a split point. */
3185 /* Throughout X, replace FROM with TO, and return the result.
3186 The result is TO if X is FROM;
3187 otherwise the result is X, but its contents may have been modified.
3188 If they were modified, a record was made in undobuf so that
3189 undo_all will (among other things) return X to its original state.
3191 If the number of changes necessary is too much to record to undo,
3192 the excess changes are not made, so the result is invalid.
3193 The changes already made can still be undone.
3194 undobuf.num_undo is incremented for such changes, so by testing that
3195 the caller can tell whether the result is valid.
3197 `n_occurrences' is incremented each time FROM is replaced.
3199 IN_DEST is non-zero if we are processing the SET_DEST of a SET.
3201 UNIQUE_COPY is non-zero if each substitution must be unique. We do this
3202 by copying if `n_occurrences' is non-zero. */
3205 subst (x
, from
, to
, in_dest
, unique_copy
)
3206 register rtx x
, from
, to
;
3210 register enum rtx_code code
= GET_CODE (x
);
3211 enum machine_mode op0_mode
= VOIDmode
;
3212 register const char *fmt
;
3213 register int len
, i
;
3216 /* Two expressions are equal if they are identical copies of a shared
3217 RTX or if they are both registers with the same register number
3220 #define COMBINE_RTX_EQUAL_P(X,Y) \
3222 || (GET_CODE (X) == REG && GET_CODE (Y) == REG \
3223 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3225 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
3228 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
3231 /* If X and FROM are the same register but different modes, they will
3232 not have been seen as equal above. However, flow.c will make a
3233 LOG_LINKS entry for that case. If we do nothing, we will try to
3234 rerecognize our original insn and, when it succeeds, we will
3235 delete the feeding insn, which is incorrect.
3237 So force this insn not to match in this (rare) case. */
3238 if (! in_dest
&& code
== REG
&& GET_CODE (from
) == REG
3239 && REGNO (x
) == REGNO (from
))
3240 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
3242 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3243 of which may contain things that can be combined. */
3244 if (code
!= MEM
&& code
!= LO_SUM
&& GET_RTX_CLASS (code
) == 'o')
3247 /* It is possible to have a subexpression appear twice in the insn.
3248 Suppose that FROM is a register that appears within TO.
3249 Then, after that subexpression has been scanned once by `subst',
3250 the second time it is scanned, TO may be found. If we were
3251 to scan TO here, we would find FROM within it and create a
3252 self-referent rtl structure which is completely wrong. */
3253 if (COMBINE_RTX_EQUAL_P (x
, to
))
3256 /* Parallel asm_operands need special attention because all of the
3257 inputs are shared across the arms. Furthermore, unsharing the
3258 rtl results in recognition failures. Failure to handle this case
3259 specially can result in circular rtl.
3261 Solve this by doing a normal pass across the first entry of the
3262 parallel, and only processing the SET_DESTs of the subsequent
3265 if (code
== PARALLEL
3266 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
3267 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
3269 new = subst (XVECEXP (x
, 0, 0), from
, to
, 0, unique_copy
);
3271 /* If this substitution failed, this whole thing fails. */
3272 if (GET_CODE (new) == CLOBBER
3273 && XEXP (new, 0) == const0_rtx
)
3276 SUBST (XVECEXP (x
, 0, 0), new);
3278 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
3280 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
3282 if (GET_CODE (dest
) != REG
3283 && GET_CODE (dest
) != CC0
3284 && GET_CODE (dest
) != PC
)
3286 new = subst (dest
, from
, to
, 0, unique_copy
);
3288 /* If this substitution failed, this whole thing fails. */
3289 if (GET_CODE (new) == CLOBBER
3290 && XEXP (new, 0) == const0_rtx
)
3293 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new);
3299 len
= GET_RTX_LENGTH (code
);
3300 fmt
= GET_RTX_FORMAT (code
);
3302 /* We don't need to process a SET_DEST that is a register, CC0,
3303 or PC, so set up to skip this common case. All other cases
3304 where we want to suppress replacing something inside a
3305 SET_SRC are handled via the IN_DEST operand. */
3307 && (GET_CODE (SET_DEST (x
)) == REG
3308 || GET_CODE (SET_DEST (x
)) == CC0
3309 || GET_CODE (SET_DEST (x
)) == PC
))
3312 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3315 op0_mode
= GET_MODE (XEXP (x
, 0));
3317 for (i
= 0; i
< len
; i
++)
3322 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3324 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
3326 new = (unique_copy
&& n_occurrences
3327 ? copy_rtx (to
) : to
);
3332 new = subst (XVECEXP (x
, i
, j
), from
, to
, 0,
3335 /* If this substitution failed, this whole thing
3337 if (GET_CODE (new) == CLOBBER
3338 && XEXP (new, 0) == const0_rtx
)
3342 SUBST (XVECEXP (x
, i
, j
), new);
3345 else if (fmt
[i
] == 'e')
3347 if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
3349 /* In general, don't install a subreg involving two
3350 modes not tieable. It can worsen register
3351 allocation, and can even make invalid reload
3352 insns, since the reg inside may need to be copied
3353 from in the outside mode, and that may be invalid
3354 if it is an fp reg copied in integer mode.
3356 We allow two exceptions to this: It is valid if
3357 it is inside another SUBREG and the mode of that
3358 SUBREG and the mode of the inside of TO is
3359 tieable and it is valid if X is a SET that copies
3362 if (GET_CODE (to
) == SUBREG
3363 && ! MODES_TIEABLE_P (GET_MODE (to
),
3364 GET_MODE (SUBREG_REG (to
)))
3365 && ! (code
== SUBREG
3366 && MODES_TIEABLE_P (GET_MODE (x
),
3367 GET_MODE (SUBREG_REG (to
))))
3369 && ! (code
== SET
&& i
== 1 && XEXP (x
, 0) == cc0_rtx
)
3372 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
3374 new = (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
3378 /* If we are in a SET_DEST, suppress most cases unless we
3379 have gone inside a MEM, in which case we want to
3380 simplify the address. We assume here that things that
3381 are actually part of the destination have their inner
3382 parts in the first expression. This is true for SUBREG,
3383 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3384 things aside from REG and MEM that should appear in a
3386 new = subst (XEXP (x
, i
), from
, to
,
3388 && (code
== SUBREG
|| code
== STRICT_LOW_PART
3389 || code
== ZERO_EXTRACT
))
3391 && i
== 0), unique_copy
);
3393 /* If we found that we will have to reject this combination,
3394 indicate that by returning the CLOBBER ourselves, rather than
3395 an expression containing it. This will speed things up as
3396 well as prevent accidents where two CLOBBERs are considered
3397 to be equal, thus producing an incorrect simplification. */
3399 if (GET_CODE (new) == CLOBBER
&& XEXP (new, 0) == const0_rtx
)
3402 SUBST (XEXP (x
, i
), new);
3407 /* Try to simplify X. If the simplification changed the code, it is likely
3408 that further simplification will help, so loop, but limit the number
3409 of repetitions that will be performed. */
3411 for (i
= 0; i
< 4; i
++)
3413 /* If X is sufficiently simple, don't bother trying to do anything
3415 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
3416 x
= combine_simplify_rtx (x
, op0_mode
, i
== 3, in_dest
);
3418 if (GET_CODE (x
) == code
)
3421 code
= GET_CODE (x
);
3423 /* We no longer know the original mode of operand 0 since we
3424 have changed the form of X) */
3425 op0_mode
= VOIDmode
;
3431 /* Simplify X, a piece of RTL. We just operate on the expression at the
3432 outer level; call `subst' to simplify recursively. Return the new
3435 OP0_MODE is the original mode of XEXP (x, 0); LAST is nonzero if this
3436 will be the iteration even if an expression with a code different from
3437 X is returned; IN_DEST is nonzero if we are inside a SET_DEST. */
3440 combine_simplify_rtx (x
, op0_mode
, last
, in_dest
)
3442 enum machine_mode op0_mode
;
3446 enum rtx_code code
= GET_CODE (x
);
3447 enum machine_mode mode
= GET_MODE (x
);
3451 /* If this is a commutative operation, put a constant last and a complex
3452 expression first. We don't need to do this for comparisons here. */
3453 if (GET_RTX_CLASS (code
) == 'c'
3454 && ((CONSTANT_P (XEXP (x
, 0)) && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
3455 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == 'o'
3456 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')
3457 || (GET_CODE (XEXP (x
, 0)) == SUBREG
3458 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == 'o'
3459 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o')))
3462 SUBST (XEXP (x
, 0), XEXP (x
, 1));
3463 SUBST (XEXP (x
, 1), temp
);
3466 /* If this is a PLUS, MINUS, or MULT, and the first operand is the
3467 sign extension of a PLUS with a constant, reverse the order of the sign
3468 extension and the addition. Note that this not the same as the original
3469 code, but overflow is undefined for signed values. Also note that the
3470 PLUS will have been partially moved "inside" the sign-extension, so that
3471 the first operand of X will really look like:
3472 (ashiftrt (plus (ashift A C4) C5) C4).
3474 (plus (ashiftrt (ashift A C4) C2) C4)
3475 and replace the first operand of X with that expression. Later parts
3476 of this function may simplify the expression further.
3478 For example, if we start with (mult (sign_extend (plus A C1)) C2),
3479 we swap the SIGN_EXTEND and PLUS. Later code will apply the
3480 distributive law to produce (plus (mult (sign_extend X) C1) C3).
3482 We do this to simplify address expressions. */
3484 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
)
3485 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3486 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == PLUS
3487 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ASHIFT
3488 && GET_CODE (XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1)) == CONST_INT
3489 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3490 && XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 1) == XEXP (XEXP (x
, 0), 1)
3491 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
3492 && (temp
= simplify_binary_operation (ASHIFTRT
, mode
,
3493 XEXP (XEXP (XEXP (x
, 0), 0), 1),
3494 XEXP (XEXP (x
, 0), 1))) != 0)
3497 = simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
3498 XEXP (XEXP (XEXP (XEXP (x
, 0), 0), 0), 0),
3499 INTVAL (XEXP (XEXP (x
, 0), 1)));
3501 new = simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
, new,
3502 INTVAL (XEXP (XEXP (x
, 0), 1)));
3504 SUBST (XEXP (x
, 0), gen_binary (PLUS
, mode
, new, temp
));
3507 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3508 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3509 things. Check for cases where both arms are testing the same
3512 Don't do anything if all operands are very simple. */
3514 if (((GET_RTX_CLASS (code
) == '2' || GET_RTX_CLASS (code
) == 'c'
3515 || GET_RTX_CLASS (code
) == '<')
3516 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3517 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3518 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3520 || (GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) != 'o'
3521 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
3522 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 1))))
3524 || (GET_RTX_CLASS (code
) == '1'
3525 && ((GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) != 'o'
3526 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
3527 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0))))
3530 rtx cond
, true, false;
3532 cond
= if_then_else_cond (x
, &true, &false);
3534 /* If everything is a comparison, what we have is highly unlikely
3535 to be simpler, so don't use it. */
3536 && ! (GET_RTX_CLASS (code
) == '<'
3537 && (GET_RTX_CLASS (GET_CODE (true)) == '<'
3538 || GET_RTX_CLASS (GET_CODE (false)) == '<')))
3540 rtx cop1
= const0_rtx
;
3541 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
3543 if (cond_code
== NE
&& GET_RTX_CLASS (GET_CODE (cond
)) == '<')
3546 /* Simplify the alternative arms; this may collapse the true and
3547 false arms to store-flag values. */
3548 true = subst (true, pc_rtx
, pc_rtx
, 0, 0);
3549 false = subst (false, pc_rtx
, pc_rtx
, 0, 0);
3551 /* Restarting if we generate a store-flag expression will cause
3552 us to loop. Just drop through in this case. */
3554 /* If the result values are STORE_FLAG_VALUE and zero, we can
3555 just make the comparison operation. */
3556 if (true == const_true_rtx
&& false == const0_rtx
)
3557 x
= gen_binary (cond_code
, mode
, cond
, cop1
);
3558 else if (true == const0_rtx
&& false == const_true_rtx
)
3559 x
= gen_binary (reverse_condition (cond_code
), mode
, cond
, cop1
);
3561 /* Likewise, we can make the negate of a comparison operation
3562 if the result values are - STORE_FLAG_VALUE and zero. */
3563 else if (GET_CODE (true) == CONST_INT
3564 && INTVAL (true) == - STORE_FLAG_VALUE
3565 && false == const0_rtx
)
3566 x
= gen_unary (NEG
, mode
, mode
,
3567 gen_binary (cond_code
, mode
, cond
, cop1
));
3568 else if (GET_CODE (false) == CONST_INT
3569 && INTVAL (false) == - STORE_FLAG_VALUE
3570 && true == const0_rtx
)
3571 x
= gen_unary (NEG
, mode
, mode
,
3572 gen_binary (reverse_condition (cond_code
),
3575 return gen_rtx_IF_THEN_ELSE (mode
,
3576 gen_binary (cond_code
, VOIDmode
,
3580 code
= GET_CODE (x
);
3581 op0_mode
= VOIDmode
;
3585 /* Try to fold this expression in case we have constants that weren't
3588 switch (GET_RTX_CLASS (code
))
3591 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
3594 temp
= simplify_relational_operation (code
, op0_mode
,
3595 XEXP (x
, 0), XEXP (x
, 1));
3596 #ifdef FLOAT_STORE_FLAG_VALUE
3597 if (temp
!= 0 && GET_MODE_CLASS (mode
) == MODE_FLOAT
)
3599 if (temp
== const0_rtx
)
3600 temp
= CONST0_RTX (mode
);
3602 temp
= immed_real_const_1 (FLOAT_STORE_FLAG_VALUE (mode
), mode
);
3608 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
3612 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
3613 XEXP (x
, 1), XEXP (x
, 2));
3618 x
= temp
, code
= GET_CODE (temp
);
3620 /* First see if we can apply the inverse distributive law. */
3621 if (code
== PLUS
|| code
== MINUS
3622 || code
== AND
|| code
== IOR
|| code
== XOR
)
3624 x
= apply_distributive_law (x
);
3625 code
= GET_CODE (x
);
3628 /* If CODE is an associative operation not otherwise handled, see if we
3629 can associate some operands. This can win if they are constants or
3630 if they are logically related (i.e. (a & b) & a. */
3631 if ((code
== PLUS
|| code
== MINUS
3632 || code
== MULT
|| code
== AND
|| code
== IOR
|| code
== XOR
3633 || code
== DIV
|| code
== UDIV
3634 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
3635 && INTEGRAL_MODE_P (mode
))
3637 if (GET_CODE (XEXP (x
, 0)) == code
)
3639 rtx other
= XEXP (XEXP (x
, 0), 0);
3640 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
3641 rtx inner_op1
= XEXP (x
, 1);
3644 /* Make sure we pass the constant operand if any as the second
3645 one if this is a commutative operation. */
3646 if (CONSTANT_P (inner_op0
) && GET_RTX_CLASS (code
) == 'c')
3648 rtx tem
= inner_op0
;
3649 inner_op0
= inner_op1
;
3652 inner
= simplify_binary_operation (code
== MINUS
? PLUS
3653 : code
== DIV
? MULT
3654 : code
== UDIV
? MULT
3656 mode
, inner_op0
, inner_op1
);
3658 /* For commutative operations, try the other pair if that one
3660 if (inner
== 0 && GET_RTX_CLASS (code
) == 'c')
3662 other
= XEXP (XEXP (x
, 0), 1);
3663 inner
= simplify_binary_operation (code
, mode
,
3664 XEXP (XEXP (x
, 0), 0),
3669 return gen_binary (code
, mode
, other
, inner
);
3673 /* A little bit of algebraic simplification here. */
3677 /* Ensure that our address has any ASHIFTs converted to MULT in case
3678 address-recognizing predicates are called later. */
3679 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
3680 SUBST (XEXP (x
, 0), temp
);
3684 /* (subreg:A (mem:B X) N) becomes a modified MEM unless the SUBREG
3685 is paradoxical. If we can't do that safely, then it becomes
3686 something nonsensical so that this combination won't take place. */
3688 if (GET_CODE (SUBREG_REG (x
)) == MEM
3689 && (GET_MODE_SIZE (mode
)
3690 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))))
3692 rtx inner
= SUBREG_REG (x
);
3693 int endian_offset
= 0;
3694 /* Don't change the mode of the MEM
3695 if that would change the meaning of the address. */
3696 if (MEM_VOLATILE_P (SUBREG_REG (x
))
3697 || mode_dependent_address_p (XEXP (inner
, 0)))
3698 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3700 if (BYTES_BIG_ENDIAN
)
3702 if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
3703 endian_offset
+= UNITS_PER_WORD
- GET_MODE_SIZE (mode
);
3704 if (GET_MODE_SIZE (GET_MODE (inner
)) < UNITS_PER_WORD
)
3705 endian_offset
-= (UNITS_PER_WORD
3706 - GET_MODE_SIZE (GET_MODE (inner
)));
3708 /* Note if the plus_constant doesn't make a valid address
3709 then this combination won't be accepted. */
3710 x
= gen_rtx_MEM (mode
,
3711 plus_constant (XEXP (inner
, 0),
3712 (SUBREG_WORD (x
) * UNITS_PER_WORD
3714 RTX_UNCHANGING_P (x
) = RTX_UNCHANGING_P (inner
);
3715 MEM_COPY_ATTRIBUTES (x
, inner
);
3719 /* If we are in a SET_DEST, these other cases can't apply. */
3723 /* Changing mode twice with SUBREG => just change it once,
3724 or not at all if changing back to starting mode. */
3725 if (GET_CODE (SUBREG_REG (x
)) == SUBREG
)
3727 if (mode
== GET_MODE (SUBREG_REG (SUBREG_REG (x
)))
3728 && SUBREG_WORD (x
) == 0 && SUBREG_WORD (SUBREG_REG (x
)) == 0)
3729 return SUBREG_REG (SUBREG_REG (x
));
3731 SUBST_INT (SUBREG_WORD (x
),
3732 SUBREG_WORD (x
) + SUBREG_WORD (SUBREG_REG (x
)));
3733 SUBST (SUBREG_REG (x
), SUBREG_REG (SUBREG_REG (x
)));
3736 /* SUBREG of a hard register => just change the register number
3737 and/or mode. If the hard register is not valid in that mode,
3738 suppress this combination. If the hard register is the stack,
3739 frame, or argument pointer, leave this as a SUBREG. */
3741 if (GET_CODE (SUBREG_REG (x
)) == REG
3742 && REGNO (SUBREG_REG (x
)) < FIRST_PSEUDO_REGISTER
3743 && REGNO (SUBREG_REG (x
)) != FRAME_POINTER_REGNUM
3744 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3745 && REGNO (SUBREG_REG (x
)) != HARD_FRAME_POINTER_REGNUM
3747 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
3748 && REGNO (SUBREG_REG (x
)) != ARG_POINTER_REGNUM
3750 && REGNO (SUBREG_REG (x
)) != STACK_POINTER_REGNUM
)
3752 if (HARD_REGNO_MODE_OK (REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
),
3754 return gen_rtx_REG (mode
,
3755 REGNO (SUBREG_REG (x
)) + SUBREG_WORD (x
));
3757 return gen_rtx_CLOBBER (mode
, const0_rtx
);
3760 /* For a constant, try to pick up the part we want. Handle a full
3761 word and low-order part. Only do this if we are narrowing
3762 the constant; if it is being widened, we have no idea what
3763 the extra bits will have been set to. */
3765 if (CONSTANT_P (SUBREG_REG (x
)) && op0_mode
!= VOIDmode
3766 && GET_MODE_SIZE (mode
) == UNITS_PER_WORD
3767 && GET_MODE_SIZE (op0_mode
) > UNITS_PER_WORD
3768 && GET_MODE_CLASS (mode
) == MODE_INT
)
3770 temp
= operand_subword (SUBREG_REG (x
), SUBREG_WORD (x
),
3776 /* If we want a subreg of a constant, at offset 0,
3777 take the low bits. On a little-endian machine, that's
3778 always valid. On a big-endian machine, it's valid
3779 only if the constant's mode fits in one word. Note that we
3780 cannot use subreg_lowpart_p since SUBREG_REG may be VOIDmode. */
3781 if (CONSTANT_P (SUBREG_REG (x
))
3782 && ((GET_MODE_SIZE (op0_mode
) <= UNITS_PER_WORD
3783 || ! WORDS_BIG_ENDIAN
)
3784 ? SUBREG_WORD (x
) == 0
3786 == ((GET_MODE_SIZE (op0_mode
)
3787 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
3789 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (op0_mode
)
3790 && (! WORDS_BIG_ENDIAN
3791 || GET_MODE_BITSIZE (op0_mode
) <= BITS_PER_WORD
))
3792 return gen_lowpart_for_combine (mode
, SUBREG_REG (x
));
3794 /* A paradoxical SUBREG of a VOIDmode constant is the same constant,
3795 since we are saying that the high bits don't matter. */
3796 if (CONSTANT_P (SUBREG_REG (x
)) && GET_MODE (SUBREG_REG (x
)) == VOIDmode
3797 && GET_MODE_SIZE (mode
) > GET_MODE_SIZE (op0_mode
))
3799 if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))) > UNITS_PER_WORD
3800 && (WORDS_BIG_ENDIAN
|| SUBREG_WORD (x
) != 0))
3801 return operand_subword (SUBREG_REG (x
), SUBREG_WORD (x
), 0, mode
);
3802 return SUBREG_REG (x
);
3805 /* Note that we cannot do any narrowing for non-constants since
3806 we might have been counting on using the fact that some bits were
3807 zero. We now do this in the SET. */
3812 /* (not (plus X -1)) can become (neg X). */
3813 if (GET_CODE (XEXP (x
, 0)) == PLUS
3814 && XEXP (XEXP (x
, 0), 1) == constm1_rtx
)
3815 return gen_rtx_combine (NEG
, mode
, XEXP (XEXP (x
, 0), 0));
3817 /* Similarly, (not (neg X)) is (plus X -1). */
3818 if (GET_CODE (XEXP (x
, 0)) == NEG
)
3819 return gen_rtx_combine (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
3822 /* (not (xor X C)) for C constant is (xor X D) with D = ~ C. */
3823 if (GET_CODE (XEXP (x
, 0)) == XOR
3824 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3825 && (temp
= simplify_unary_operation (NOT
, mode
,
3826 XEXP (XEXP (x
, 0), 1),
3828 return gen_binary (XOR
, mode
, XEXP (XEXP (x
, 0), 0), temp
);
3830 /* (not (ashift 1 X)) is (rotate ~1 X). We used to do this for operands
3831 other than 1, but that is not valid. We could do a similar
3832 simplification for (not (lshiftrt C X)) where C is just the sign bit,
3833 but this doesn't seem common enough to bother with. */
3834 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
3835 && XEXP (XEXP (x
, 0), 0) == const1_rtx
)
3836 return gen_rtx_ROTATE (mode
, gen_unary (NOT
, mode
, mode
, const1_rtx
),
3837 XEXP (XEXP (x
, 0), 1));
3839 if (GET_CODE (XEXP (x
, 0)) == SUBREG
3840 && subreg_lowpart_p (XEXP (x
, 0))
3841 && (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0)))
3842 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (x
, 0)))))
3843 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == ASHIFT
3844 && XEXP (SUBREG_REG (XEXP (x
, 0)), 0) == const1_rtx
)
3846 enum machine_mode inner_mode
= GET_MODE (SUBREG_REG (XEXP (x
, 0)));
3848 x
= gen_rtx_ROTATE (inner_mode
,
3849 gen_unary (NOT
, inner_mode
, inner_mode
,
3851 XEXP (SUBREG_REG (XEXP (x
, 0)), 1));
3852 return gen_lowpart_for_combine (mode
, x
);
3855 /* If STORE_FLAG_VALUE is -1, (not (comparison foo bar)) can be done by
3856 reversing the comparison code if valid. */
3857 if (STORE_FLAG_VALUE
== -1
3858 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
3859 && reversible_comparison_p (XEXP (x
, 0)))
3860 return gen_rtx_combine (reverse_condition (GET_CODE (XEXP (x
, 0))),
3861 mode
, XEXP (XEXP (x
, 0), 0),
3862 XEXP (XEXP (x
, 0), 1));
3864 /* (ashiftrt foo C) where C is the number of bits in FOO minus 1
3865 is (lt foo (const_int 0)) if STORE_FLAG_VALUE is -1, so we can
3866 perform the above simplification. */
3868 if (STORE_FLAG_VALUE
== -1
3869 && GET_CODE (XEXP (x
, 0)) == ASHIFTRT
3870 && XEXP (x
, 1) == const1_rtx
3871 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
3872 && INTVAL (XEXP (XEXP (x
, 0), 1)) == GET_MODE_BITSIZE (mode
) - 1)
3873 return gen_rtx_combine (GE
, mode
, XEXP (XEXP (x
, 0), 0), const0_rtx
);
3875 /* Apply De Morgan's laws to reduce number of patterns for machines
3876 with negating logical insns (and-not, nand, etc.). If result has
3877 only one NOT, put it first, since that is how the patterns are
3880 if (GET_CODE (XEXP (x
, 0)) == IOR
|| GET_CODE (XEXP (x
, 0)) == AND
)
3882 rtx in1
= XEXP (XEXP (x
, 0), 0), in2
= XEXP (XEXP (x
, 0), 1);
3884 if (GET_CODE (in1
) == NOT
)
3885 in1
= XEXP (in1
, 0);
3887 in1
= gen_rtx_combine (NOT
, GET_MODE (in1
), in1
);
3889 if (GET_CODE (in2
) == NOT
)
3890 in2
= XEXP (in2
, 0);
3891 else if (GET_CODE (in2
) == CONST_INT
3892 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
3893 in2
= GEN_INT (GET_MODE_MASK (mode
) & ~ INTVAL (in2
));
3895 in2
= gen_rtx_combine (NOT
, GET_MODE (in2
), in2
);
3897 if (GET_CODE (in2
) == NOT
)
3900 in2
= in1
; in1
= tem
;
3903 return gen_rtx_combine (GET_CODE (XEXP (x
, 0)) == IOR
? AND
: IOR
,
3909 /* (neg (plus X 1)) can become (not X). */
3910 if (GET_CODE (XEXP (x
, 0)) == PLUS
3911 && XEXP (XEXP (x
, 0), 1) == const1_rtx
)
3912 return gen_rtx_combine (NOT
, mode
, XEXP (XEXP (x
, 0), 0));
3914 /* Similarly, (neg (not X)) is (plus X 1). */
3915 if (GET_CODE (XEXP (x
, 0)) == NOT
)
3916 return plus_constant (XEXP (XEXP (x
, 0), 0), 1);
3918 /* (neg (minus X Y)) can become (minus Y X). */
3919 if (GET_CODE (XEXP (x
, 0)) == MINUS
3920 && (! FLOAT_MODE_P (mode
)
3921 /* x-y != -(y-x) with IEEE floating point. */
3922 || TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
3924 return gen_binary (MINUS
, mode
, XEXP (XEXP (x
, 0), 1),
3925 XEXP (XEXP (x
, 0), 0));
3927 /* (neg (xor A 1)) is (plus A -1) if A is known to be either 0 or 1. */
3928 if (GET_CODE (XEXP (x
, 0)) == XOR
&& XEXP (XEXP (x
, 0), 1) == const1_rtx
3929 && nonzero_bits (XEXP (XEXP (x
, 0), 0), mode
) == 1)
3930 return gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0), constm1_rtx
);
3932 /* NEG commutes with ASHIFT since it is multiplication. Only do this
3933 if we can then eliminate the NEG (e.g.,
3934 if the operand is a constant). */
3936 if (GET_CODE (XEXP (x
, 0)) == ASHIFT
)
3938 temp
= simplify_unary_operation (NEG
, mode
,
3939 XEXP (XEXP (x
, 0), 0), mode
);
3942 SUBST (XEXP (XEXP (x
, 0), 0), temp
);
3947 temp
= expand_compound_operation (XEXP (x
, 0));
3949 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
3950 replaced by (lshiftrt X C). This will convert
3951 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
3953 if (GET_CODE (temp
) == ASHIFTRT
3954 && GET_CODE (XEXP (temp
, 1)) == CONST_INT
3955 && INTVAL (XEXP (temp
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
3956 return simplify_shift_const (temp
, LSHIFTRT
, mode
, XEXP (temp
, 0),
3957 INTVAL (XEXP (temp
, 1)));
3959 /* If X has only a single bit that might be nonzero, say, bit I, convert
3960 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
3961 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
3962 (sign_extract X 1 Y). But only do this if TEMP isn't a register
3963 or a SUBREG of one since we'd be making the expression more
3964 complex if it was just a register. */
3966 if (GET_CODE (temp
) != REG
3967 && ! (GET_CODE (temp
) == SUBREG
3968 && GET_CODE (SUBREG_REG (temp
)) == REG
)
3969 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
3971 rtx temp1
= simplify_shift_const
3972 (NULL_RTX
, ASHIFTRT
, mode
,
3973 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
3974 GET_MODE_BITSIZE (mode
) - 1 - i
),
3975 GET_MODE_BITSIZE (mode
) - 1 - i
);
3977 /* If all we did was surround TEMP with the two shifts, we
3978 haven't improved anything, so don't use it. Otherwise,
3979 we are better off with TEMP1. */
3980 if (GET_CODE (temp1
) != ASHIFTRT
3981 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
3982 || XEXP (XEXP (temp1
, 0), 0) != temp
)
3988 /* We can't handle truncation to a partial integer mode here
3989 because we don't know the real bitsize of the partial
3991 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
3994 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
3995 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
3996 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))))
3998 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
3999 GET_MODE_MASK (mode
), NULL_RTX
, 0));
4001 /* (truncate:SI ({sign,zero}_extend:DI foo:SI)) == foo:SI. */
4002 if ((GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4003 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4004 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4005 return XEXP (XEXP (x
, 0), 0);
4007 /* (truncate:SI (OP:DI ({sign,zero}_extend:DI foo:SI))) is
4008 (OP:SI foo:SI) if OP is NEG or ABS. */
4009 if ((GET_CODE (XEXP (x
, 0)) == ABS
4010 || GET_CODE (XEXP (x
, 0)) == NEG
)
4011 && (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SIGN_EXTEND
4012 || GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
)
4013 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4014 return gen_unary (GET_CODE (XEXP (x
, 0)), mode
, mode
,
4015 XEXP (XEXP (XEXP (x
, 0), 0), 0));
4017 /* (truncate:SI (subreg:DI (truncate:SI X) 0)) is
4019 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4020 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == TRUNCATE
4021 && subreg_lowpart_p (XEXP (x
, 0)))
4022 return SUBREG_REG (XEXP (x
, 0));
4024 /* If we know that the value is already truncated, we can
4025 replace the TRUNCATE with a SUBREG if TRULY_NOOP_TRUNCATION
4026 is nonzero for the corresponding modes. But don't do this
4027 for an (LSHIFTRT (MULT ...)) since this will cause problems
4028 with the umulXi3_highpart patterns. */
4029 if (TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
4030 GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
4031 && num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4032 >= GET_MODE_BITSIZE (mode
) + 1
4033 && ! (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4034 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
))
4035 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4037 /* A truncate of a comparison can be replaced with a subreg if
4038 STORE_FLAG_VALUE permits. This is like the previous test,
4039 but it works even if the comparison is done in a mode larger
4040 than HOST_BITS_PER_WIDE_INT. */
4041 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4042 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4043 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
&~ GET_MODE_MASK (mode
)) == 0)
4044 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4046 /* Similarly, a truncate of a register whose value is a
4047 comparison can be replaced with a subreg if STORE_FLAG_VALUE
4049 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4050 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
&~ GET_MODE_MASK (mode
)) == 0
4051 && (temp
= get_last_value (XEXP (x
, 0)))
4052 && GET_RTX_CLASS (GET_CODE (temp
)) == '<')
4053 return gen_lowpart_for_combine (mode
, XEXP (x
, 0));
4057 case FLOAT_TRUNCATE
:
4058 /* (float_truncate:SF (float_extend:DF foo:SF)) = foo:SF. */
4059 if (GET_CODE (XEXP (x
, 0)) == FLOAT_EXTEND
4060 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == mode
)
4061 return XEXP (XEXP (x
, 0), 0);
4063 /* (float_truncate:SF (OP:DF (float_extend:DF foo:sf))) is
4064 (OP:SF foo:SF) if OP is NEG or ABS. */
4065 if ((GET_CODE (XEXP (x
, 0)) == ABS
4066 || GET_CODE (XEXP (x
, 0)) == NEG
)
4067 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == FLOAT_EXTEND
4068 && GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == mode
)
4069 return gen_unary (GET_CODE (XEXP (x
, 0)), mode
, mode
,
4070 XEXP (XEXP (XEXP (x
, 0), 0), 0));
4072 /* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
4073 is (float_truncate:SF x). */
4074 if (GET_CODE (XEXP (x
, 0)) == SUBREG
4075 && subreg_lowpart_p (XEXP (x
, 0))
4076 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == FLOAT_TRUNCATE
)
4077 return SUBREG_REG (XEXP (x
, 0));
4082 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4083 using cc0, in which case we want to leave it as a COMPARE
4084 so we can distinguish it from a register-register-copy. */
4085 if (XEXP (x
, 1) == const0_rtx
)
4088 /* In IEEE floating point, x-0 is not the same as x. */
4089 if ((TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
4090 || ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0)))
4092 && XEXP (x
, 1) == CONST0_RTX (GET_MODE (XEXP (x
, 0))))
4098 /* (const (const X)) can become (const X). Do it this way rather than
4099 returning the inner CONST since CONST can be shared with a
4101 if (GET_CODE (XEXP (x
, 0)) == CONST
)
4102 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4107 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4108 can add in an offset. find_split_point will split this address up
4109 again if it doesn't match. */
4110 if (GET_CODE (XEXP (x
, 0)) == HIGH
4111 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
4117 /* If we have (plus (plus (A const) B)), associate it so that CONST is
4118 outermost. That's because that's the way indexed addresses are
4119 supposed to appear. This code used to check many more cases, but
4120 they are now checked elsewhere. */
4121 if (GET_CODE (XEXP (x
, 0)) == PLUS
4122 && CONSTANT_ADDRESS_P (XEXP (XEXP (x
, 0), 1)))
4123 return gen_binary (PLUS
, mode
,
4124 gen_binary (PLUS
, mode
, XEXP (XEXP (x
, 0), 0),
4126 XEXP (XEXP (x
, 0), 1));
4128 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4129 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4130 bit-field and can be replaced by either a sign_extend or a
4131 sign_extract. The `and' may be a zero_extend and the two
4132 <c>, -<c> constants may be reversed. */
4133 if (GET_CODE (XEXP (x
, 0)) == XOR
4134 && GET_CODE (XEXP (x
, 1)) == CONST_INT
4135 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
4136 && INTVAL (XEXP (x
, 1)) == - INTVAL (XEXP (XEXP (x
, 0), 1))
4137 && ((i
= exact_log2 (INTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
4138 || (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
4139 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4140 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
4141 && GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)) == CONST_INT
4142 && (INTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
4143 == ((HOST_WIDE_INT
) 1 << (i
+ 1)) - 1))
4144 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
4145 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
4147 return simplify_shift_const
4148 (NULL_RTX
, ASHIFTRT
, mode
,
4149 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4150 XEXP (XEXP (XEXP (x
, 0), 0), 0),
4151 GET_MODE_BITSIZE (mode
) - (i
+ 1)),
4152 GET_MODE_BITSIZE (mode
) - (i
+ 1));
4154 /* (plus (comparison A B) C) can become (neg (rev-comp A B)) if
4155 C is 1 and STORE_FLAG_VALUE is -1 or if C is -1 and STORE_FLAG_VALUE
4156 is 1. This produces better code than the alternative immediately
4158 if (GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4159 && reversible_comparison_p (XEXP (x
, 0))
4160 && ((STORE_FLAG_VALUE
== -1 && XEXP (x
, 1) == const1_rtx
)
4161 || (STORE_FLAG_VALUE
== 1 && XEXP (x
, 1) == constm1_rtx
)))
4163 gen_unary (NEG
, mode
, mode
,
4164 gen_binary (reverse_condition (GET_CODE (XEXP (x
, 0))),
4165 mode
, XEXP (XEXP (x
, 0), 0),
4166 XEXP (XEXP (x
, 0), 1)));
4168 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4169 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4170 the bitsize of the mode - 1. This allows simplification of
4171 "a = (b & 8) == 0;" */
4172 if (XEXP (x
, 1) == constm1_rtx
4173 && GET_CODE (XEXP (x
, 0)) != REG
4174 && ! (GET_CODE (XEXP (x
,0)) == SUBREG
4175 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
)
4176 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
4177 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
4178 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4179 gen_rtx_combine (XOR
, mode
,
4180 XEXP (x
, 0), const1_rtx
),
4181 GET_MODE_BITSIZE (mode
) - 1),
4182 GET_MODE_BITSIZE (mode
) - 1);
4184 /* If we are adding two things that have no bits in common, convert
4185 the addition into an IOR. This will often be further simplified,
4186 for example in cases like ((a & 1) + (a & 2)), which can
4189 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4190 && (nonzero_bits (XEXP (x
, 0), mode
)
4191 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
4192 return gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
4196 /* If STORE_FLAG_VALUE is 1, (minus 1 (comparison foo bar)) can be done
4197 by reversing the comparison code if valid. */
4198 if (STORE_FLAG_VALUE
== 1
4199 && XEXP (x
, 0) == const1_rtx
4200 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<'
4201 && reversible_comparison_p (XEXP (x
, 1)))
4202 return gen_binary (reverse_condition (GET_CODE (XEXP (x
, 1))),
4203 mode
, XEXP (XEXP (x
, 1), 0),
4204 XEXP (XEXP (x
, 1), 1));
4206 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4207 (and <foo> (const_int pow2-1)) */
4208 if (GET_CODE (XEXP (x
, 1)) == AND
4209 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
4210 && exact_log2 (- INTVAL (XEXP (XEXP (x
, 1), 1))) >= 0
4211 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
4212 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
4213 - INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
4215 /* Canonicalize (minus A (plus B C)) to (minus (minus A B) C) for
4217 if (GET_CODE (XEXP (x
, 1)) == PLUS
&& INTEGRAL_MODE_P (mode
))
4218 return gen_binary (MINUS
, mode
,
4219 gen_binary (MINUS
, mode
, XEXP (x
, 0),
4220 XEXP (XEXP (x
, 1), 0)),
4221 XEXP (XEXP (x
, 1), 1));
4225 /* If we have (mult (plus A B) C), apply the distributive law and then
4226 the inverse distributive law to see if things simplify. This
4227 occurs mostly in addresses, often when unrolling loops. */
4229 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
4231 x
= apply_distributive_law
4232 (gen_binary (PLUS
, mode
,
4233 gen_binary (MULT
, mode
,
4234 XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)),
4235 gen_binary (MULT
, mode
,
4236 XEXP (XEXP (x
, 0), 1),
4237 copy_rtx (XEXP (x
, 1)))));
4239 if (GET_CODE (x
) != MULT
)
4245 /* If this is a divide by a power of two, treat it as a shift if
4246 its first operand is a shift. */
4247 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
4248 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0
4249 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
4250 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
4251 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
4252 || GET_CODE (XEXP (x
, 0)) == ROTATE
4253 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
4254 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
4258 case GT
: case GTU
: case GE
: case GEU
:
4259 case LT
: case LTU
: case LE
: case LEU
:
4260 /* If the first operand is a condition code, we can't do anything
4262 if (GET_CODE (XEXP (x
, 0)) == COMPARE
4263 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
4265 && XEXP (x
, 0) != cc0_rtx
4269 rtx op0
= XEXP (x
, 0);
4270 rtx op1
= XEXP (x
, 1);
4271 enum rtx_code new_code
;
4273 if (GET_CODE (op0
) == COMPARE
)
4274 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
4276 /* Simplify our comparison, if possible. */
4277 new_code
= simplify_comparison (code
, &op0
, &op1
);
4279 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4280 if only the low-order bit is possibly nonzero in X (such as when
4281 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4282 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4283 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4286 Remove any ZERO_EXTRACT we made when thinking this was a
4287 comparison. It may now be simpler to use, e.g., an AND. If a
4288 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4289 the call to make_compound_operation in the SET case. */
4291 if (STORE_FLAG_VALUE
== 1
4292 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4293 && op1
== const0_rtx
&& nonzero_bits (op0
, mode
) == 1)
4294 return gen_lowpart_for_combine (mode
,
4295 expand_compound_operation (op0
));
4297 else if (STORE_FLAG_VALUE
== 1
4298 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4299 && op1
== const0_rtx
4300 && (num_sign_bit_copies (op0
, mode
)
4301 == GET_MODE_BITSIZE (mode
)))
4303 op0
= expand_compound_operation (op0
);
4304 return gen_unary (NEG
, mode
, mode
,
4305 gen_lowpart_for_combine (mode
, op0
));
4308 else if (STORE_FLAG_VALUE
== 1
4309 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4310 && op1
== const0_rtx
4311 && nonzero_bits (op0
, mode
) == 1)
4313 op0
= expand_compound_operation (op0
);
4314 return gen_binary (XOR
, mode
,
4315 gen_lowpart_for_combine (mode
, op0
),
4319 else if (STORE_FLAG_VALUE
== 1
4320 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4321 && op1
== const0_rtx
4322 && (num_sign_bit_copies (op0
, mode
)
4323 == GET_MODE_BITSIZE (mode
)))
4325 op0
= expand_compound_operation (op0
);
4326 return plus_constant (gen_lowpart_for_combine (mode
, op0
), 1);
4329 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4331 if (STORE_FLAG_VALUE
== -1
4332 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4333 && op1
== const0_rtx
4334 && (num_sign_bit_copies (op0
, mode
)
4335 == GET_MODE_BITSIZE (mode
)))
4336 return gen_lowpart_for_combine (mode
,
4337 expand_compound_operation (op0
));
4339 else if (STORE_FLAG_VALUE
== -1
4340 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4341 && op1
== const0_rtx
4342 && nonzero_bits (op0
, mode
) == 1)
4344 op0
= expand_compound_operation (op0
);
4345 return gen_unary (NEG
, mode
, mode
,
4346 gen_lowpart_for_combine (mode
, op0
));
4349 else if (STORE_FLAG_VALUE
== -1
4350 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4351 && op1
== const0_rtx
4352 && (num_sign_bit_copies (op0
, mode
)
4353 == GET_MODE_BITSIZE (mode
)))
4355 op0
= expand_compound_operation (op0
);
4356 return gen_unary (NOT
, mode
, mode
,
4357 gen_lowpart_for_combine (mode
, op0
));
4360 /* If X is 0/1, (eq X 0) is X-1. */
4361 else if (STORE_FLAG_VALUE
== -1
4362 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
4363 && op1
== const0_rtx
4364 && nonzero_bits (op0
, mode
) == 1)
4366 op0
= expand_compound_operation (op0
);
4367 return plus_constant (gen_lowpart_for_combine (mode
, op0
), -1);
4370 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4371 one bit that might be nonzero, we can convert (ne x 0) to
4372 (ashift x c) where C puts the bit in the sign bit. Remove any
4373 AND with STORE_FLAG_VALUE when we are done, since we are only
4374 going to test the sign bit. */
4375 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
4376 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4377 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4378 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE(mode
)-1))
4379 && op1
== const0_rtx
4380 && mode
== GET_MODE (op0
)
4381 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
4383 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4384 expand_compound_operation (op0
),
4385 GET_MODE_BITSIZE (mode
) - 1 - i
);
4386 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
4392 /* If the code changed, return a whole new comparison. */
4393 if (new_code
!= code
)
4394 return gen_rtx_combine (new_code
, mode
, op0
, op1
);
4396 /* Otherwise, keep this operation, but maybe change its operands.
4397 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4398 SUBST (XEXP (x
, 0), op0
);
4399 SUBST (XEXP (x
, 1), op1
);
4404 return simplify_if_then_else (x
);
4410 /* If we are processing SET_DEST, we are done. */
4414 return expand_compound_operation (x
);
4417 return simplify_set (x
);
4422 return simplify_logical (x
, last
);
4425 /* (abs (neg <foo>)) -> (abs <foo>) */
4426 if (GET_CODE (XEXP (x
, 0)) == NEG
)
4427 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4429 /* If the mode of the operand is VOIDmode (i.e. if it is ASM_OPERANDS),
4431 if (GET_MODE (XEXP (x
, 0)) == VOIDmode
)
4434 /* If operand is something known to be positive, ignore the ABS. */
4435 if (GET_CODE (XEXP (x
, 0)) == FFS
|| GET_CODE (XEXP (x
, 0)) == ABS
4436 || ((GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
4437 <= HOST_BITS_PER_WIDE_INT
)
4438 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
4439 & ((HOST_WIDE_INT
) 1
4440 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1)))
4445 /* If operand is known to be only -1 or 0, convert ABS to NEG. */
4446 if (num_sign_bit_copies (XEXP (x
, 0), mode
) == GET_MODE_BITSIZE (mode
))
4447 return gen_rtx_combine (NEG
, mode
, XEXP (x
, 0));
4452 /* (ffs (*_extend <X>)) = (ffs <X>) */
4453 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
4454 || GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
)
4455 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4459 /* (float (sign_extend <X>)) = (float <X>). */
4460 if (GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
4461 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
4469 /* If this is a shift by a constant amount, simplify it. */
4470 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
4471 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
4472 INTVAL (XEXP (x
, 1)));
4474 #ifdef SHIFT_COUNT_TRUNCATED
4475 else if (SHIFT_COUNT_TRUNCATED
&& GET_CODE (XEXP (x
, 1)) != REG
)
4477 force_to_mode (XEXP (x
, 1), GET_MODE (x
),
4479 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
4493 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4496 simplify_if_then_else (x
)
4499 enum machine_mode mode
= GET_MODE (x
);
4500 rtx cond
= XEXP (x
, 0);
4501 rtx
true = XEXP (x
, 1);
4502 rtx
false = XEXP (x
, 2);
4503 enum rtx_code true_code
= GET_CODE (cond
);
4504 int comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4508 /* Simplify storing of the truth value. */
4509 if (comparison_p
&& true == const_true_rtx
&& false == const0_rtx
)
4510 return gen_binary (true_code
, mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4512 /* Also when the truth value has to be reversed. */
4513 if (comparison_p
&& reversible_comparison_p (cond
)
4514 && true == const0_rtx
&& false == const_true_rtx
)
4515 return gen_binary (reverse_condition (true_code
),
4516 mode
, XEXP (cond
, 0), XEXP (cond
, 1));
4518 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4519 in it is being compared against certain values. Get the true and false
4520 comparisons and see if that says anything about the value of each arm. */
4522 if (comparison_p
&& reversible_comparison_p (cond
)
4523 && GET_CODE (XEXP (cond
, 0)) == REG
)
4526 rtx from
= XEXP (cond
, 0);
4527 enum rtx_code false_code
= reverse_condition (true_code
);
4528 rtx true_val
= XEXP (cond
, 1);
4529 rtx false_val
= true_val
;
4532 /* If FALSE_CODE is EQ, swap the codes and arms. */
4534 if (false_code
== EQ
)
4536 swapped
= 1, true_code
= EQ
, false_code
= NE
;
4537 temp
= true, true = false, false = temp
;
4540 /* If we are comparing against zero and the expression being tested has
4541 only a single bit that might be nonzero, that is its value when it is
4542 not equal to zero. Similarly if it is known to be -1 or 0. */
4544 if (true_code
== EQ
&& true_val
== const0_rtx
4545 && exact_log2 (nzb
= nonzero_bits (from
, GET_MODE (from
))) >= 0)
4546 false_code
= EQ
, false_val
= GEN_INT (nzb
);
4547 else if (true_code
== EQ
&& true_val
== const0_rtx
4548 && (num_sign_bit_copies (from
, GET_MODE (from
))
4549 == GET_MODE_BITSIZE (GET_MODE (from
))))
4550 false_code
= EQ
, false_val
= constm1_rtx
;
4552 /* Now simplify an arm if we know the value of the register in the
4553 branch and it is used in the arm. Be careful due to the potential
4554 of locally-shared RTL. */
4556 if (reg_mentioned_p (from
, true))
4557 true = subst (known_cond (copy_rtx (true), true_code
, from
, true_val
),
4558 pc_rtx
, pc_rtx
, 0, 0);
4559 if (reg_mentioned_p (from
, false))
4560 false = subst (known_cond (copy_rtx (false), false_code
,
4562 pc_rtx
, pc_rtx
, 0, 0);
4564 SUBST (XEXP (x
, 1), swapped
? false : true);
4565 SUBST (XEXP (x
, 2), swapped
? true : false);
4567 true = XEXP (x
, 1), false = XEXP (x
, 2), true_code
= GET_CODE (cond
);
4570 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4571 reversed, do so to avoid needing two sets of patterns for
4572 subtract-and-branch insns. Similarly if we have a constant in the true
4573 arm, the false arm is the same as the first operand of the comparison, or
4574 the false arm is more complicated than the true arm. */
4576 if (comparison_p
&& reversible_comparison_p (cond
)
4578 || (CONSTANT_P (true)
4579 && GET_CODE (false) != CONST_INT
&& false != pc_rtx
)
4580 || true == const0_rtx
4581 || (GET_RTX_CLASS (GET_CODE (true)) == 'o'
4582 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4583 || (GET_CODE (true) == SUBREG
4584 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (true))) == 'o'
4585 && GET_RTX_CLASS (GET_CODE (false)) != 'o')
4586 || reg_mentioned_p (true, false)
4587 || rtx_equal_p (false, XEXP (cond
, 0))))
4589 true_code
= reverse_condition (true_code
);
4591 gen_binary (true_code
, GET_MODE (cond
), XEXP (cond
, 0),
4594 SUBST (XEXP (x
, 1), false);
4595 SUBST (XEXP (x
, 2), true);
4597 temp
= true, true = false, false = temp
, cond
= XEXP (x
, 0);
4599 /* It is possible that the conditional has been simplified out. */
4600 true_code
= GET_CODE (cond
);
4601 comparison_p
= GET_RTX_CLASS (true_code
) == '<';
4604 /* If the two arms are identical, we don't need the comparison. */
4606 if (rtx_equal_p (true, false) && ! side_effects_p (cond
))
4609 /* Convert a == b ? b : a to "a". */
4610 if (true_code
== EQ
&& ! side_effects_p (cond
)
4611 && rtx_equal_p (XEXP (cond
, 0), false)
4612 && rtx_equal_p (XEXP (cond
, 1), true))
4614 else if (true_code
== NE
&& ! side_effects_p (cond
)
4615 && rtx_equal_p (XEXP (cond
, 0), true)
4616 && rtx_equal_p (XEXP (cond
, 1), false))
4619 /* Look for cases where we have (abs x) or (neg (abs X)). */
4621 if (GET_MODE_CLASS (mode
) == MODE_INT
4622 && GET_CODE (false) == NEG
4623 && rtx_equal_p (true, XEXP (false, 0))
4625 && rtx_equal_p (true, XEXP (cond
, 0))
4626 && ! side_effects_p (true))
4631 return gen_unary (ABS
, mode
, mode
, true);
4634 return gen_unary (NEG
, mode
, mode
, gen_unary (ABS
, mode
, mode
, true));
4639 /* Look for MIN or MAX. */
4641 if ((! FLOAT_MODE_P (mode
) || flag_fast_math
)
4643 && rtx_equal_p (XEXP (cond
, 0), true)
4644 && rtx_equal_p (XEXP (cond
, 1), false)
4645 && ! side_effects_p (cond
))
4650 return gen_binary (SMAX
, mode
, true, false);
4653 return gen_binary (SMIN
, mode
, true, false);
4656 return gen_binary (UMAX
, mode
, true, false);
4659 return gen_binary (UMIN
, mode
, true, false);
4664 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4665 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4666 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4667 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4668 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4669 neither 1 or -1, but it isn't worth checking for. */
4671 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4672 && comparison_p
&& mode
!= VOIDmode
&& ! side_effects_p (x
))
4674 rtx t
= make_compound_operation (true, SET
);
4675 rtx f
= make_compound_operation (false, SET
);
4676 rtx cond_op0
= XEXP (cond
, 0);
4677 rtx cond_op1
= XEXP (cond
, 1);
4678 enum rtx_code op
= NIL
, extend_op
= NIL
;
4679 enum machine_mode m
= mode
;
4680 rtx z
= 0, c1
= NULL_RTX
;
4682 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
4683 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
4684 || GET_CODE (t
) == ASHIFT
4685 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
4686 && rtx_equal_p (XEXP (t
, 0), f
))
4687 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
4689 /* If an identity-zero op is commutative, check whether there
4690 would be a match if we swapped the operands. */
4691 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
4692 || GET_CODE (t
) == XOR
)
4693 && rtx_equal_p (XEXP (t
, 1), f
))
4694 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
4695 else if (GET_CODE (t
) == SIGN_EXTEND
4696 && (GET_CODE (XEXP (t
, 0)) == PLUS
4697 || GET_CODE (XEXP (t
, 0)) == MINUS
4698 || GET_CODE (XEXP (t
, 0)) == IOR
4699 || GET_CODE (XEXP (t
, 0)) == XOR
4700 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4701 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4702 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4703 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4704 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4705 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4706 && (num_sign_bit_copies (f
, GET_MODE (f
))
4707 > (GET_MODE_BITSIZE (mode
)
4708 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
4710 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4711 extend_op
= SIGN_EXTEND
;
4712 m
= GET_MODE (XEXP (t
, 0));
4714 else if (GET_CODE (t
) == SIGN_EXTEND
4715 && (GET_CODE (XEXP (t
, 0)) == PLUS
4716 || GET_CODE (XEXP (t
, 0)) == IOR
4717 || GET_CODE (XEXP (t
, 0)) == XOR
)
4718 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4719 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4720 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4721 && (num_sign_bit_copies (f
, GET_MODE (f
))
4722 > (GET_MODE_BITSIZE (mode
)
4723 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
4725 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4726 extend_op
= SIGN_EXTEND
;
4727 m
= GET_MODE (XEXP (t
, 0));
4729 else if (GET_CODE (t
) == ZERO_EXTEND
4730 && (GET_CODE (XEXP (t
, 0)) == PLUS
4731 || GET_CODE (XEXP (t
, 0)) == MINUS
4732 || GET_CODE (XEXP (t
, 0)) == IOR
4733 || GET_CODE (XEXP (t
, 0)) == XOR
4734 || GET_CODE (XEXP (t
, 0)) == ASHIFT
4735 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
4736 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
4737 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
4738 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4739 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
4740 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
4741 && ((nonzero_bits (f
, GET_MODE (f
))
4742 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
4745 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4746 extend_op
= ZERO_EXTEND
;
4747 m
= GET_MODE (XEXP (t
, 0));
4749 else if (GET_CODE (t
) == ZERO_EXTEND
4750 && (GET_CODE (XEXP (t
, 0)) == PLUS
4751 || GET_CODE (XEXP (t
, 0)) == IOR
4752 || GET_CODE (XEXP (t
, 0)) == XOR
)
4753 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
4754 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4755 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
4756 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
4757 && ((nonzero_bits (f
, GET_MODE (f
))
4758 & ~ GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
4761 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
4762 extend_op
= ZERO_EXTEND
;
4763 m
= GET_MODE (XEXP (t
, 0));
4768 temp
= subst (gen_binary (true_code
, m
, cond_op0
, cond_op1
),
4769 pc_rtx
, pc_rtx
, 0, 0);
4770 temp
= gen_binary (MULT
, m
, temp
,
4771 gen_binary (MULT
, m
, c1
, const_true_rtx
));
4772 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0);
4773 temp
= gen_binary (op
, m
, gen_lowpart_for_combine (m
, z
), temp
);
4775 if (extend_op
!= NIL
)
4776 temp
= gen_unary (extend_op
, mode
, m
, temp
);
4782 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4783 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4784 negation of a single bit, we can convert this operation to a shift. We
4785 can actually do this more generally, but it doesn't seem worth it. */
4787 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
4788 && false == const0_rtx
&& GET_CODE (true) == CONST_INT
4789 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
4790 && (i
= exact_log2 (INTVAL (true))) >= 0)
4791 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
4792 == GET_MODE_BITSIZE (mode
))
4793 && (i
= exact_log2 (- INTVAL (true))) >= 0)))
4795 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
4796 gen_lowpart_for_combine (mode
, XEXP (cond
, 0)), i
);
4801 /* Simplify X, a SET expression. Return the new expression. */
4807 rtx src
= SET_SRC (x
);
4808 rtx dest
= SET_DEST (x
);
4809 enum machine_mode mode
4810 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
4814 /* (set (pc) (return)) gets written as (return). */
4815 if (GET_CODE (dest
) == PC
&& GET_CODE (src
) == RETURN
)
4818 /* Now that we know for sure which bits of SRC we are using, see if we can
4819 simplify the expression for the object knowing that we only need the
4822 if (GET_MODE_CLASS (mode
) == MODE_INT
)
4824 src
= force_to_mode (src
, mode
, GET_MODE_MASK (mode
), NULL_RTX
, 0);
4825 SUBST (SET_SRC (x
), src
);
4828 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4829 the comparison result and try to simplify it unless we already have used
4830 undobuf.other_insn. */
4831 if ((GET_CODE (src
) == COMPARE
4836 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
4837 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
4838 && GET_RTX_CLASS (GET_CODE (*cc_use
)) == '<'
4839 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
4841 enum rtx_code old_code
= GET_CODE (*cc_use
);
4842 enum rtx_code new_code
;
4844 int other_changed
= 0;
4845 enum machine_mode compare_mode
= GET_MODE (dest
);
4847 if (GET_CODE (src
) == COMPARE
)
4848 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
4850 op0
= src
, op1
= const0_rtx
;
4852 /* Simplify our comparison, if possible. */
4853 new_code
= simplify_comparison (old_code
, &op0
, &op1
);
4855 #ifdef EXTRA_CC_MODES
4856 /* If this machine has CC modes other than CCmode, check to see if we
4857 need to use a different CC mode here. */
4858 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
4859 #endif /* EXTRA_CC_MODES */
4861 #if !defined (HAVE_cc0) && defined (EXTRA_CC_MODES)
4862 /* If the mode changed, we have to change SET_DEST, the mode in the
4863 compare, and the mode in the place SET_DEST is used. If SET_DEST is
4864 a hard register, just build new versions with the proper mode. If it
4865 is a pseudo, we lose unless it is only time we set the pseudo, in
4866 which case we can safely change its mode. */
4867 if (compare_mode
!= GET_MODE (dest
))
4869 int regno
= REGNO (dest
);
4870 rtx new_dest
= gen_rtx_REG (compare_mode
, regno
);
4872 if (regno
< FIRST_PSEUDO_REGISTER
4873 || (REG_N_SETS (regno
) == 1 && ! REG_USERVAR_P (dest
)))
4875 if (regno
>= FIRST_PSEUDO_REGISTER
)
4876 SUBST (regno_reg_rtx
[regno
], new_dest
);
4878 SUBST (SET_DEST (x
), new_dest
);
4879 SUBST (XEXP (*cc_use
, 0), new_dest
);
4887 /* If the code changed, we have to build a new comparison in
4888 undobuf.other_insn. */
4889 if (new_code
!= old_code
)
4891 unsigned HOST_WIDE_INT mask
;
4893 SUBST (*cc_use
, gen_rtx_combine (new_code
, GET_MODE (*cc_use
),
4896 /* If the only change we made was to change an EQ into an NE or
4897 vice versa, OP0 has only one bit that might be nonzero, and OP1
4898 is zero, check if changing the user of the condition code will
4899 produce a valid insn. If it won't, we can keep the original code
4900 in that insn by surrounding our operation with an XOR. */
4902 if (((old_code
== NE
&& new_code
== EQ
)
4903 || (old_code
== EQ
&& new_code
== NE
))
4904 && ! other_changed
&& op1
== const0_rtx
4905 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
4906 && exact_log2 (mask
= nonzero_bits (op0
, GET_MODE (op0
))) >= 0)
4908 rtx pat
= PATTERN (other_insn
), note
= 0;
4910 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
4911 && ! check_asm_operands (pat
)))
4913 PUT_CODE (*cc_use
, old_code
);
4916 op0
= gen_binary (XOR
, GET_MODE (op0
), op0
, GEN_INT (mask
));
4924 undobuf
.other_insn
= other_insn
;
4927 /* If we are now comparing against zero, change our source if
4928 needed. If we do not use cc0, we always have a COMPARE. */
4929 if (op1
== const0_rtx
&& dest
== cc0_rtx
)
4931 SUBST (SET_SRC (x
), op0
);
4937 /* Otherwise, if we didn't previously have a COMPARE in the
4938 correct mode, we need one. */
4939 if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
)
4942 gen_rtx_combine (COMPARE
, compare_mode
, op0
, op1
));
4947 /* Otherwise, update the COMPARE if needed. */
4948 SUBST (XEXP (src
, 0), op0
);
4949 SUBST (XEXP (src
, 1), op1
);
4954 /* Get SET_SRC in a form where we have placed back any
4955 compound expressions. Then do the checks below. */
4956 src
= make_compound_operation (src
, SET
);
4957 SUBST (SET_SRC (x
), src
);
4960 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
4961 and X being a REG or (subreg (reg)), we may be able to convert this to
4962 (set (subreg:m2 x) (op)).
4964 We can always do this if M1 is narrower than M2 because that means that
4965 we only care about the low bits of the result.
4967 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
4968 perform a narrower operation than requested since the high-order bits will
4969 be undefined. On machine where it is defined, this transformation is safe
4970 as long as M1 and M2 have the same number of words. */
4972 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
4973 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (src
))) != 'o'
4974 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
4976 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
4977 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
4978 #ifndef WORD_REGISTER_OPERATIONS
4979 && (GET_MODE_SIZE (GET_MODE (src
))
4980 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
4982 #ifdef CLASS_CANNOT_CHANGE_SIZE
4983 && ! (GET_CODE (dest
) == REG
&& REGNO (dest
) < FIRST_PSEUDO_REGISTER
4984 && (TEST_HARD_REG_BIT
4985 (reg_class_contents
[(int) CLASS_CANNOT_CHANGE_SIZE
],
4987 && (GET_MODE_SIZE (GET_MODE (src
))
4988 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))))
4990 && (GET_CODE (dest
) == REG
4991 || (GET_CODE (dest
) == SUBREG
4992 && GET_CODE (SUBREG_REG (dest
)) == REG
)))
4994 SUBST (SET_DEST (x
),
4995 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (src
)),
4997 SUBST (SET_SRC (x
), SUBREG_REG (src
));
4999 src
= SET_SRC (x
), dest
= SET_DEST (x
);
5002 #ifdef LOAD_EXTEND_OP
5003 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5004 would require a paradoxical subreg. Replace the subreg with a
5005 zero_extend to avoid the reload that would otherwise be required. */
5007 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
5008 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != NIL
5009 && SUBREG_WORD (src
) == 0
5010 && (GET_MODE_SIZE (GET_MODE (src
))
5011 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
))))
5012 && GET_CODE (SUBREG_REG (src
)) == MEM
)
5015 gen_rtx_combine (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
5016 GET_MODE (src
), XEXP (src
, 0)));
5022 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5023 are comparing an item known to be 0 or -1 against 0, use a logical
5024 operation instead. Check for one of the arms being an IOR of the other
5025 arm with some value. We compute three terms to be IOR'ed together. In
5026 practice, at most two will be nonzero. Then we do the IOR's. */
5028 if (GET_CODE (dest
) != PC
5029 && GET_CODE (src
) == IF_THEN_ELSE
5030 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
5031 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
5032 && XEXP (XEXP (src
, 0), 1) == const0_rtx
5033 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
5034 #ifdef HAVE_conditional_move
5035 && ! can_conditionally_move_p (GET_MODE (src
))
5037 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
5038 GET_MODE (XEXP (XEXP (src
, 0), 0)))
5039 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src
, 0), 0))))
5040 && ! side_effects_p (src
))
5042 rtx
true = (GET_CODE (XEXP (src
, 0)) == NE
5043 ? XEXP (src
, 1) : XEXP (src
, 2));
5044 rtx
false = (GET_CODE (XEXP (src
, 0)) == NE
5045 ? XEXP (src
, 2) : XEXP (src
, 1));
5046 rtx term1
= const0_rtx
, term2
, term3
;
5048 if (GET_CODE (true) == IOR
&& rtx_equal_p (XEXP (true, 0), false))
5049 term1
= false, true = XEXP (true, 1), false = const0_rtx
;
5050 else if (GET_CODE (true) == IOR
5051 && rtx_equal_p (XEXP (true, 1), false))
5052 term1
= false, true = XEXP (true, 0), false = const0_rtx
;
5053 else if (GET_CODE (false) == IOR
5054 && rtx_equal_p (XEXP (false, 0), true))
5055 term1
= true, false = XEXP (false, 1), true = const0_rtx
;
5056 else if (GET_CODE (false) == IOR
5057 && rtx_equal_p (XEXP (false, 1), true))
5058 term1
= true, false = XEXP (false, 0), true = const0_rtx
;
5060 term2
= gen_binary (AND
, GET_MODE (src
), XEXP (XEXP (src
, 0), 0), true);
5061 term3
= gen_binary (AND
, GET_MODE (src
),
5062 gen_unary (NOT
, GET_MODE (src
), GET_MODE (src
),
5063 XEXP (XEXP (src
, 0), 0)),
5067 gen_binary (IOR
, GET_MODE (src
),
5068 gen_binary (IOR
, GET_MODE (src
), term1
, term2
),
5074 #ifdef HAVE_conditional_arithmetic
5075 /* If we have conditional arithmetic and the operand of a SET is
5076 a conditional expression, replace this with an IF_THEN_ELSE.
5077 We can either have a conditional expression or a MULT of that expression
5079 if ((GET_RTX_CLASS (GET_CODE (src
)) == '1'
5080 || GET_RTX_CLASS (GET_CODE (src
)) == '2'
5081 || GET_RTX_CLASS (GET_CODE (src
)) == 'c')
5082 && (GET_RTX_CLASS (GET_CODE (XEXP (src
, 0))) == '<'
5083 || (GET_CODE (XEXP (src
, 0)) == MULT
5084 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (src
, 0), 0))) == '<'
5085 && GET_CODE (XEXP (XEXP (src
, 0), 1)) == CONST_INT
)))
5087 rtx cond
= XEXP (src
, 0);
5088 rtx true_val
= const1_rtx
;
5089 rtx false_arm
, true_arm
;
5091 if (GET_CODE (cond
) == MULT
)
5093 true_val
= XEXP (cond
, 1);
5094 cond
= XEXP (cond
, 0);
5097 if (GET_RTX_CLASS (GET_CODE (src
)) == '1')
5099 true_arm
= gen_unary (GET_CODE (src
), GET_MODE (src
),
5100 GET_MODE (XEXP (src
, 0)), true_val
);
5101 false_arm
= gen_unary (GET_CODE (src
), GET_MODE (src
),
5102 GET_MODE (XEXP (src
, 0)), const0_rtx
);
5106 true_arm
= gen_binary (GET_CODE (src
), GET_MODE (src
),
5107 true_val
, XEXP (src
, 1));
5108 false_arm
= gen_binary (GET_CODE (src
), GET_MODE (src
),
5109 const0_rtx
, XEXP (src
, 1));
5112 /* Canonicalize if true_arm is the simpler one. */
5113 if (GET_RTX_CLASS (GET_CODE (true_arm
)) == 'o'
5114 && GET_RTX_CLASS (GET_CODE (false_arm
)) != 'o'
5115 && reversible_comparison_p (cond
))
5117 rtx temp
= true_arm
;
5119 true_arm
= false_arm
;
5122 cond
= gen_rtx_combine (reverse_condition (GET_CODE (cond
)),
5123 GET_MODE (cond
), XEXP (cond
, 0),
5127 src
= gen_rtx_combine (IF_THEN_ELSE
, GET_MODE (src
),
5128 gen_rtx_combine (GET_CODE (cond
), VOIDmode
,
5131 true_arm
, false_arm
);
5132 SUBST (SET_SRC (x
), src
);
5136 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5137 whole thing fail. */
5138 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
5140 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
5143 /* Convert this into a field assignment operation, if possible. */
5144 return make_field_assignment (x
);
5147 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5148 result. LAST is nonzero if this is the last retry. */
5151 simplify_logical (x
, last
)
5155 enum machine_mode mode
= GET_MODE (x
);
5156 rtx op0
= XEXP (x
, 0);
5157 rtx op1
= XEXP (x
, 1);
5159 switch (GET_CODE (x
))
5162 /* Convert (A ^ B) & A to A & (~ B) since the latter is often a single
5163 insn (and may simplify more). */
5164 if (GET_CODE (op0
) == XOR
5165 && rtx_equal_p (XEXP (op0
, 0), op1
)
5166 && ! side_effects_p (op1
))
5167 x
= gen_binary (AND
, mode
,
5168 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 1)), op1
);
5170 if (GET_CODE (op0
) == XOR
5171 && rtx_equal_p (XEXP (op0
, 1), op1
)
5172 && ! side_effects_p (op1
))
5173 x
= gen_binary (AND
, mode
,
5174 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 0)), op1
);
5176 /* Similarly for (~ (A ^ B)) & A. */
5177 if (GET_CODE (op0
) == NOT
5178 && GET_CODE (XEXP (op0
, 0)) == XOR
5179 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), op1
)
5180 && ! side_effects_p (op1
))
5181 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 1), op1
);
5183 if (GET_CODE (op0
) == NOT
5184 && GET_CODE (XEXP (op0
, 0)) == XOR
5185 && rtx_equal_p (XEXP (XEXP (op0
, 0), 1), op1
)
5186 && ! side_effects_p (op1
))
5187 x
= gen_binary (AND
, mode
, XEXP (XEXP (op0
, 0), 0), op1
);
5189 /* We can call simplify_and_const_int only if we don't lose
5190 any (sign) bits when converting INTVAL (op1) to
5191 "unsigned HOST_WIDE_INT". */
5192 if (GET_CODE (op1
) == CONST_INT
5193 && (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5194 || INTVAL (op1
) > 0))
5196 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
5198 /* If we have (ior (and (X C1) C2)) and the next restart would be
5199 the last, simplify this by making C1 as small as possible
5202 && GET_CODE (x
) == IOR
&& GET_CODE (op0
) == AND
5203 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5204 && GET_CODE (op1
) == CONST_INT
)
5205 return gen_binary (IOR
, mode
,
5206 gen_binary (AND
, mode
, XEXP (op0
, 0),
5207 GEN_INT (INTVAL (XEXP (op0
, 1))
5208 & ~ INTVAL (op1
))), op1
);
5210 if (GET_CODE (x
) != AND
)
5213 if (GET_RTX_CLASS (GET_CODE (x
)) == 'c'
5214 || GET_RTX_CLASS (GET_CODE (x
)) == '2')
5215 op0
= XEXP (x
, 0), op1
= XEXP (x
, 1);
5218 /* Convert (A | B) & A to A. */
5219 if (GET_CODE (op0
) == IOR
5220 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5221 || rtx_equal_p (XEXP (op0
, 1), op1
))
5222 && ! side_effects_p (XEXP (op0
, 0))
5223 && ! side_effects_p (XEXP (op0
, 1)))
5226 /* In the following group of tests (and those in case IOR below),
5227 we start with some combination of logical operations and apply
5228 the distributive law followed by the inverse distributive law.
5229 Most of the time, this results in no change. However, if some of
5230 the operands are the same or inverses of each other, simplifications
5233 For example, (and (ior A B) (not B)) can occur as the result of
5234 expanding a bit field assignment. When we apply the distributive
5235 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
5236 which then simplifies to (and (A (not B))).
5238 If we have (and (ior A B) C), apply the distributive law and then
5239 the inverse distributive law to see if things simplify. */
5241 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
5243 x
= apply_distributive_law
5244 (gen_binary (GET_CODE (op0
), mode
,
5245 gen_binary (AND
, mode
, XEXP (op0
, 0), op1
),
5246 gen_binary (AND
, mode
, XEXP (op0
, 1),
5248 if (GET_CODE (x
) != AND
)
5252 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
5253 return apply_distributive_law
5254 (gen_binary (GET_CODE (op1
), mode
,
5255 gen_binary (AND
, mode
, XEXP (op1
, 0), op0
),
5256 gen_binary (AND
, mode
, XEXP (op1
, 1),
5259 /* Similarly, taking advantage of the fact that
5260 (and (not A) (xor B C)) == (xor (ior A B) (ior A C)) */
5262 if (GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == XOR
)
5263 return apply_distributive_law
5264 (gen_binary (XOR
, mode
,
5265 gen_binary (IOR
, mode
, XEXP (op0
, 0), XEXP (op1
, 0)),
5266 gen_binary (IOR
, mode
, copy_rtx (XEXP (op0
, 0)),
5269 else if (GET_CODE (op1
) == NOT
&& GET_CODE (op0
) == XOR
)
5270 return apply_distributive_law
5271 (gen_binary (XOR
, mode
,
5272 gen_binary (IOR
, mode
, XEXP (op1
, 0), XEXP (op0
, 0)),
5273 gen_binary (IOR
, mode
, copy_rtx (XEXP (op1
, 0)), XEXP (op0
, 1))));
5277 /* (ior A C) is C if all bits of A that might be nonzero are on in C. */
5278 if (GET_CODE (op1
) == CONST_INT
5279 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5280 && (nonzero_bits (op0
, mode
) & ~ INTVAL (op1
)) == 0)
5283 /* Convert (A & B) | A to A. */
5284 if (GET_CODE (op0
) == AND
5285 && (rtx_equal_p (XEXP (op0
, 0), op1
)
5286 || rtx_equal_p (XEXP (op0
, 1), op1
))
5287 && ! side_effects_p (XEXP (op0
, 0))
5288 && ! side_effects_p (XEXP (op0
, 1)))
5291 /* If we have (ior (and A B) C), apply the distributive law and then
5292 the inverse distributive law to see if things simplify. */
5294 if (GET_CODE (op0
) == AND
)
5296 x
= apply_distributive_law
5297 (gen_binary (AND
, mode
,
5298 gen_binary (IOR
, mode
, XEXP (op0
, 0), op1
),
5299 gen_binary (IOR
, mode
, XEXP (op0
, 1),
5302 if (GET_CODE (x
) != IOR
)
5306 if (GET_CODE (op1
) == AND
)
5308 x
= apply_distributive_law
5309 (gen_binary (AND
, mode
,
5310 gen_binary (IOR
, mode
, XEXP (op1
, 0), op0
),
5311 gen_binary (IOR
, mode
, XEXP (op1
, 1),
5314 if (GET_CODE (x
) != IOR
)
5318 /* Convert (ior (ashift A CX) (lshiftrt A CY)) where CX+CY equals the
5319 mode size to (rotate A CX). */
5321 if (((GET_CODE (op0
) == ASHIFT
&& GET_CODE (op1
) == LSHIFTRT
)
5322 || (GET_CODE (op1
) == ASHIFT
&& GET_CODE (op0
) == LSHIFTRT
))
5323 && rtx_equal_p (XEXP (op0
, 0), XEXP (op1
, 0))
5324 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5325 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
5326 && (INTVAL (XEXP (op0
, 1)) + INTVAL (XEXP (op1
, 1))
5327 == GET_MODE_BITSIZE (mode
)))
5328 return gen_rtx_ROTATE (mode
, XEXP (op0
, 0),
5329 (GET_CODE (op0
) == ASHIFT
5330 ? XEXP (op0
, 1) : XEXP (op1
, 1)));
5332 /* If OP0 is (ashiftrt (plus ...) C), it might actually be
5333 a (sign_extend (plus ...)). If so, OP1 is a CONST_INT, and the PLUS
5334 does not affect any of the bits in OP1, it can really be done
5335 as a PLUS and we can associate. We do this by seeing if OP1
5336 can be safely shifted left C bits. */
5337 if (GET_CODE (op1
) == CONST_INT
&& GET_CODE (op0
) == ASHIFTRT
5338 && GET_CODE (XEXP (op0
, 0)) == PLUS
5339 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
5340 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5341 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
)
5343 int count
= INTVAL (XEXP (op0
, 1));
5344 HOST_WIDE_INT mask
= INTVAL (op1
) << count
;
5346 if (mask
>> count
== INTVAL (op1
)
5347 && (mask
& nonzero_bits (XEXP (op0
, 0), mode
)) == 0)
5349 SUBST (XEXP (XEXP (op0
, 0), 1),
5350 GEN_INT (INTVAL (XEXP (XEXP (op0
, 0), 1)) | mask
));
5357 /* If we are XORing two things that have no bits in common,
5358 convert them into an IOR. This helps to detect rotation encoded
5359 using those methods and possibly other simplifications. */
5361 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5362 && (nonzero_bits (op0
, mode
)
5363 & nonzero_bits (op1
, mode
)) == 0)
5364 return (gen_binary (IOR
, mode
, op0
, op1
));
5366 /* Convert (XOR (NOT x) (NOT y)) to (XOR x y).
5367 Also convert (XOR (NOT x) y) to (NOT (XOR x y)), similarly for
5370 int num_negated
= 0;
5372 if (GET_CODE (op0
) == NOT
)
5373 num_negated
++, op0
= XEXP (op0
, 0);
5374 if (GET_CODE (op1
) == NOT
)
5375 num_negated
++, op1
= XEXP (op1
, 0);
5377 if (num_negated
== 2)
5379 SUBST (XEXP (x
, 0), op0
);
5380 SUBST (XEXP (x
, 1), op1
);
5382 else if (num_negated
== 1)
5383 return gen_unary (NOT
, mode
, mode
, gen_binary (XOR
, mode
, op0
, op1
));
5386 /* Convert (xor (and A B) B) to (and (not A) B). The latter may
5387 correspond to a machine insn or result in further simplifications
5388 if B is a constant. */
5390 if (GET_CODE (op0
) == AND
5391 && rtx_equal_p (XEXP (op0
, 1), op1
)
5392 && ! side_effects_p (op1
))
5393 return gen_binary (AND
, mode
,
5394 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 0)),
5397 else if (GET_CODE (op0
) == AND
5398 && rtx_equal_p (XEXP (op0
, 0), op1
)
5399 && ! side_effects_p (op1
))
5400 return gen_binary (AND
, mode
,
5401 gen_unary (NOT
, mode
, mode
, XEXP (op0
, 1)),
5404 /* (xor (comparison foo bar) (const_int 1)) can become the reversed
5405 comparison if STORE_FLAG_VALUE is 1. */
5406 if (STORE_FLAG_VALUE
== 1
5407 && op1
== const1_rtx
5408 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5409 && reversible_comparison_p (op0
))
5410 return gen_rtx_combine (reverse_condition (GET_CODE (op0
)),
5411 mode
, XEXP (op0
, 0), XEXP (op0
, 1));
5413 /* (lshiftrt foo C) where C is the number of bits in FOO minus 1
5414 is (lt foo (const_int 0)), so we can perform the above
5415 simplification if STORE_FLAG_VALUE is 1. */
5417 if (STORE_FLAG_VALUE
== 1
5418 && op1
== const1_rtx
5419 && GET_CODE (op0
) == LSHIFTRT
5420 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
5421 && INTVAL (XEXP (op0
, 1)) == GET_MODE_BITSIZE (mode
) - 1)
5422 return gen_rtx_combine (GE
, mode
, XEXP (op0
, 0), const0_rtx
);
5424 /* (xor (comparison foo bar) (const_int sign-bit))
5425 when STORE_FLAG_VALUE is the sign bit. */
5426 if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
5427 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
5428 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1))
5429 && op1
== const_true_rtx
5430 && GET_RTX_CLASS (GET_CODE (op0
)) == '<'
5431 && reversible_comparison_p (op0
))
5432 return gen_rtx_combine (reverse_condition (GET_CODE (op0
)),
5433 mode
, XEXP (op0
, 0), XEXP (op0
, 1));
5444 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5445 operations" because they can be replaced with two more basic operations.
5446 ZERO_EXTEND is also considered "compound" because it can be replaced with
5447 an AND operation, which is simpler, though only one operation.
5449 The function expand_compound_operation is called with an rtx expression
5450 and will convert it to the appropriate shifts and AND operations,
5451 simplifying at each stage.
5453 The function make_compound_operation is called to convert an expression
5454 consisting of shifts and ANDs into the equivalent compound expression.
5455 It is the inverse of this function, loosely speaking. */
5458 expand_compound_operation (x
)
5466 switch (GET_CODE (x
))
5471 /* We can't necessarily use a const_int for a multiword mode;
5472 it depends on implicitly extending the value.
5473 Since we don't know the right way to extend it,
5474 we can't tell whether the implicit way is right.
5476 Even for a mode that is no wider than a const_int,
5477 we can't win, because we need to sign extend one of its bits through
5478 the rest of it, and we don't know which bit. */
5479 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
5482 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5483 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5484 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5485 reloaded. If not for that, MEM's would very rarely be safe.
5487 Reject MODEs bigger than a word, because we might not be able
5488 to reference a two-register group starting with an arbitrary register
5489 (and currently gen_lowpart might crash for a SUBREG). */
5491 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
5494 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)));
5495 /* If the inner object has VOIDmode (the only way this can happen
5496 is if it is a ASM_OPERANDS), we can't do anything since we don't
5497 know how much masking to do. */
5506 /* If the operand is a CLOBBER, just return it. */
5507 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
5510 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
5511 || GET_CODE (XEXP (x
, 2)) != CONST_INT
5512 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
5515 len
= INTVAL (XEXP (x
, 1));
5516 pos
= INTVAL (XEXP (x
, 2));
5518 /* If this goes outside the object being extracted, replace the object
5519 with a (use (mem ...)) construct that only combine understands
5520 and is used only for this purpose. */
5521 if (len
+ pos
> GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))))
5522 SUBST (XEXP (x
, 0), gen_rtx_USE (GET_MODE (x
), XEXP (x
, 0)));
5524 if (BITS_BIG_ENDIAN
)
5525 pos
= GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - len
- pos
;
5532 /* Convert sign extension to zero extension, if we know that the high
5533 bit is not set, as this is easier to optimize. It will be converted
5534 back to cheaper alternative in make_extraction. */
5535 if (GET_CODE (x
) == SIGN_EXTEND
5536 && (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5537 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
5538 & ~ (((unsigned HOST_WIDE_INT
)
5539 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
5543 rtx temp
= gen_rtx_ZERO_EXTEND (GET_MODE (x
), XEXP (x
, 0));
5544 return expand_compound_operation (temp
);
5547 /* We can optimize some special cases of ZERO_EXTEND. */
5548 if (GET_CODE (x
) == ZERO_EXTEND
)
5550 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5551 know that the last value didn't have any inappropriate bits
5553 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5554 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5555 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5556 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
5557 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5558 return XEXP (XEXP (x
, 0), 0);
5560 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5561 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5562 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5563 && subreg_lowpart_p (XEXP (x
, 0))
5564 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
5565 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
5566 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5567 return SUBREG_REG (XEXP (x
, 0));
5569 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5570 is a comparison and STORE_FLAG_VALUE permits. This is like
5571 the first case, but it works even when GET_MODE (x) is larger
5572 than HOST_WIDE_INT. */
5573 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
5574 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
5575 && GET_RTX_CLASS (GET_CODE (XEXP (XEXP (x
, 0), 0))) == '<'
5576 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5577 <= HOST_BITS_PER_WIDE_INT
)
5578 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5579 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5580 return XEXP (XEXP (x
, 0), 0);
5582 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5583 if (GET_CODE (XEXP (x
, 0)) == SUBREG
5584 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
5585 && subreg_lowpart_p (XEXP (x
, 0))
5586 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (XEXP (x
, 0)))) == '<'
5587 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
5588 <= HOST_BITS_PER_WIDE_INT
)
5589 && ((HOST_WIDE_INT
) STORE_FLAG_VALUE
5590 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
5591 return SUBREG_REG (XEXP (x
, 0));
5595 /* If we reach here, we want to return a pair of shifts. The inner
5596 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5597 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5598 logical depending on the value of UNSIGNEDP.
5600 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5601 converted into an AND of a shift.
5603 We must check for the case where the left shift would have a negative
5604 count. This can happen in a case like (x >> 31) & 255 on machines
5605 that can't shift by a constant. On those machines, we would first
5606 combine the shift with the AND to produce a variable-position
5607 extraction. Then the constant of 31 would be substituted in to produce
5608 a such a position. */
5610 modewidth
= GET_MODE_BITSIZE (GET_MODE (x
));
5611 if (modewidth
>= pos
- len
)
5612 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
5614 simplify_shift_const (NULL_RTX
, ASHIFT
,
5617 modewidth
- pos
- len
),
5620 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
5621 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
5622 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
5625 ((HOST_WIDE_INT
) 1 << len
) - 1);
5627 /* Any other cases we can't handle. */
5631 /* If we couldn't do this for some reason, return the original
5633 if (GET_CODE (tem
) == CLOBBER
)
5639 /* X is a SET which contains an assignment of one object into
5640 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5641 or certain SUBREGS). If possible, convert it into a series of
5644 We half-heartedly support variable positions, but do not at all
5645 support variable lengths. */
5648 expand_field_assignment (x
)
5652 rtx pos
; /* Always counts from low bit. */
5655 enum machine_mode compute_mode
;
5657 /* Loop until we find something we can't simplify. */
5660 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
5661 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
5663 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
5664 len
= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x
), 0)));
5665 pos
= GEN_INT (BITS_PER_WORD
* SUBREG_WORD (XEXP (SET_DEST (x
), 0)));
5667 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
5668 && GET_CODE (XEXP (SET_DEST (x
), 1)) == CONST_INT
)
5670 inner
= XEXP (SET_DEST (x
), 0);
5671 len
= INTVAL (XEXP (SET_DEST (x
), 1));
5672 pos
= XEXP (SET_DEST (x
), 2);
5674 /* If the position is constant and spans the width of INNER,
5675 surround INNER with a USE to indicate this. */
5676 if (GET_CODE (pos
) == CONST_INT
5677 && INTVAL (pos
) + len
> GET_MODE_BITSIZE (GET_MODE (inner
)))
5678 inner
= gen_rtx_USE (GET_MODE (SET_DEST (x
)), inner
);
5680 if (BITS_BIG_ENDIAN
)
5682 if (GET_CODE (pos
) == CONST_INT
)
5683 pos
= GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
)) - len
5685 else if (GET_CODE (pos
) == MINUS
5686 && GET_CODE (XEXP (pos
, 1)) == CONST_INT
5687 && (INTVAL (XEXP (pos
, 1))
5688 == GET_MODE_BITSIZE (GET_MODE (inner
)) - len
))
5689 /* If position is ADJUST - X, new position is X. */
5690 pos
= XEXP (pos
, 0);
5692 pos
= gen_binary (MINUS
, GET_MODE (pos
),
5693 GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner
))
5699 /* A SUBREG between two modes that occupy the same numbers of words
5700 can be done by moving the SUBREG to the source. */
5701 else if (GET_CODE (SET_DEST (x
)) == SUBREG
5702 /* We need SUBREGs to compute nonzero_bits properly. */
5703 && nonzero_sign_valid
5704 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
5705 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
5706 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
5707 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
5709 x
= gen_rtx_SET (VOIDmode
, SUBREG_REG (SET_DEST (x
)),
5710 gen_lowpart_for_combine
5711 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
5718 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5719 inner
= SUBREG_REG (inner
);
5721 compute_mode
= GET_MODE (inner
);
5723 /* Don't attempt bitwise arithmetic on non-integral modes. */
5724 if (! INTEGRAL_MODE_P (compute_mode
))
5726 enum machine_mode imode
;
5728 /* Something is probably seriously wrong if this matches. */
5729 if (! FLOAT_MODE_P (compute_mode
))
5732 /* Try to find an integral mode to pun with. */
5733 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
5734 if (imode
== BLKmode
)
5737 compute_mode
= imode
;
5738 inner
= gen_lowpart_for_combine (imode
, inner
);
5741 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5742 if (len
< HOST_BITS_PER_WIDE_INT
)
5743 mask
= GEN_INT (((HOST_WIDE_INT
) 1 << len
) - 1);
5747 /* Now compute the equivalent expression. Make a copy of INNER
5748 for the SET_DEST in case it is a MEM into which we will substitute;
5749 we don't want shared RTL in that case. */
5751 (VOIDmode
, copy_rtx (inner
),
5752 gen_binary (IOR
, compute_mode
,
5753 gen_binary (AND
, compute_mode
,
5754 gen_unary (NOT
, compute_mode
,
5760 gen_binary (ASHIFT
, compute_mode
,
5761 gen_binary (AND
, compute_mode
,
5762 gen_lowpart_for_combine
5763 (compute_mode
, SET_SRC (x
)),
5771 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5772 it is an RTX that represents a variable starting position; otherwise,
5773 POS is the (constant) starting bit position (counted from the LSB).
5775 INNER may be a USE. This will occur when we started with a bitfield
5776 that went outside the boundary of the object in memory, which is
5777 allowed on most machines. To isolate this case, we produce a USE
5778 whose mode is wide enough and surround the MEM with it. The only
5779 code that understands the USE is this routine. If it is not removed,
5780 it will cause the resulting insn not to match.
5782 UNSIGNEDP is non-zero for an unsigned reference and zero for a
5785 IN_DEST is non-zero if this is a reference in the destination of a
5786 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If non-zero,
5787 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5790 IN_COMPARE is non-zero if we are in a COMPARE. This means that a
5791 ZERO_EXTRACT should be built even for bits starting at bit 0.
5793 MODE is the desired mode of the result (if IN_DEST == 0).
5795 The result is an RTX for the extraction or NULL_RTX if the target
5799 make_extraction (mode
, inner
, pos
, pos_rtx
, len
,
5800 unsignedp
, in_dest
, in_compare
)
5801 enum machine_mode mode
;
5807 int in_dest
, in_compare
;
5809 /* This mode describes the size of the storage area
5810 to fetch the overall value from. Within that, we
5811 ignore the POS lowest bits, etc. */
5812 enum machine_mode is_mode
= GET_MODE (inner
);
5813 enum machine_mode inner_mode
;
5814 enum machine_mode wanted_inner_mode
= byte_mode
;
5815 enum machine_mode wanted_inner_reg_mode
= word_mode
;
5816 enum machine_mode pos_mode
= word_mode
;
5817 enum machine_mode extraction_mode
= word_mode
;
5818 enum machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
5821 rtx orig_pos_rtx
= pos_rtx
;
5824 /* Get some information about INNER and get the innermost object. */
5825 if (GET_CODE (inner
) == USE
)
5826 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5827 /* We don't need to adjust the position because we set up the USE
5828 to pretend that it was a full-word object. */
5829 spans_byte
= 1, inner
= XEXP (inner
, 0);
5830 else if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
5832 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5833 consider just the QI as the memory to extract from.
5834 The subreg adds or removes high bits; its mode is
5835 irrelevant to the meaning of this extraction,
5836 since POS and LEN count from the lsb. */
5837 if (GET_CODE (SUBREG_REG (inner
)) == MEM
)
5838 is_mode
= GET_MODE (SUBREG_REG (inner
));
5839 inner
= SUBREG_REG (inner
);
5842 inner_mode
= GET_MODE (inner
);
5844 if (pos_rtx
&& GET_CODE (pos_rtx
) == CONST_INT
)
5845 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
5847 /* See if this can be done without an extraction. We never can if the
5848 width of the field is not the same as that of some integer mode. For
5849 registers, we can only avoid the extraction if the position is at the
5850 low-order bit and this is either not in the destination or we have the
5851 appropriate STRICT_LOW_PART operation available.
5853 For MEM, we can avoid an extract if the field starts on an appropriate
5854 boundary and we can change the mode of the memory reference. However,
5855 we cannot directly access the MEM if we have a USE and the underlying
5856 MEM is not TMODE. This combination means that MEM was being used in a
5857 context where bits outside its mode were being referenced; that is only
5858 valid in bit-field insns. */
5860 if (tmode
!= BLKmode
5861 && ! (spans_byte
&& inner_mode
!= tmode
)
5862 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
5863 && GET_CODE (inner
) != MEM
5865 || (GET_CODE (inner
) == REG
5866 && (movstrict_optab
->handlers
[(int) tmode
].insn_code
5867 != CODE_FOR_nothing
))))
5868 || (GET_CODE (inner
) == MEM
&& pos_rtx
== 0
5870 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
5871 : BITS_PER_UNIT
)) == 0
5872 /* We can't do this if we are widening INNER_MODE (it
5873 may not be aligned, for one thing). */
5874 && GET_MODE_BITSIZE (inner_mode
) >= GET_MODE_BITSIZE (tmode
)
5875 && (inner_mode
== tmode
5876 || (! mode_dependent_address_p (XEXP (inner
, 0))
5877 && ! MEM_VOLATILE_P (inner
))))))
5879 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5880 field. If the original and current mode are the same, we need not
5881 adjust the offset. Otherwise, we do if bytes big endian.
5883 If INNER is not a MEM, get a piece consisting of just the field
5884 of interest (in this case POS % BITS_PER_WORD must be 0). */
5886 if (GET_CODE (inner
) == MEM
)
5889 /* POS counts from lsb, but make OFFSET count in memory order. */
5890 if (BYTES_BIG_ENDIAN
)
5891 offset
= (GET_MODE_BITSIZE (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
5893 offset
= pos
/ BITS_PER_UNIT
;
5895 new = gen_rtx_MEM (tmode
, plus_constant (XEXP (inner
, 0), offset
));
5896 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (inner
);
5897 MEM_COPY_ATTRIBUTES (new, inner
);
5899 else if (GET_CODE (inner
) == REG
)
5901 /* We can't call gen_lowpart_for_combine here since we always want
5902 a SUBREG and it would sometimes return a new hard register. */
5903 if (tmode
!= inner_mode
)
5904 new = gen_rtx_SUBREG (tmode
, inner
,
5906 && (GET_MODE_SIZE (inner_mode
)
5908 ? (((GET_MODE_SIZE (inner_mode
)
5909 - GET_MODE_SIZE (tmode
))
5911 - pos
/ BITS_PER_WORD
)
5912 : pos
/ BITS_PER_WORD
));
5917 new = force_to_mode (inner
, tmode
,
5918 len
>= HOST_BITS_PER_WIDE_INT
5919 ? GET_MODE_MASK (tmode
)
5920 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
5923 /* If this extraction is going into the destination of a SET,
5924 make a STRICT_LOW_PART unless we made a MEM. */
5927 return (GET_CODE (new) == MEM
? new
5928 : (GET_CODE (new) != SUBREG
5929 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
5930 : gen_rtx_combine (STRICT_LOW_PART
, VOIDmode
, new)));
5935 /* If we know that no extraneous bits are set, and that the high
5936 bit is not set, convert the extraction to the cheaper of
5937 sign and zero extension, that are equivalent in these cases. */
5938 if (flag_expensive_optimizations
5939 && (GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
5940 && ((nonzero_bits (new, tmode
)
5941 & ~ (((unsigned HOST_WIDE_INT
)
5942 GET_MODE_MASK (tmode
))
5946 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new);
5947 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new);
5949 /* Prefer ZERO_EXTENSION, since it gives more information to
5951 if (rtx_cost (temp
, SET
) < rtx_cost (temp1
, SET
))
5956 /* Otherwise, sign- or zero-extend unless we already are in the
5959 return (gen_rtx_combine (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
5963 /* Unless this is a COMPARE or we have a funny memory reference,
5964 don't do anything with zero-extending field extracts starting at
5965 the low-order bit since they are simple AND operations. */
5966 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
5967 && ! in_compare
&& ! spans_byte
&& unsignedp
)
5970 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
5971 we would be spanning bytes or if the position is not a constant and the
5972 length is not 1. In all other cases, we would only be going outside
5973 our object in cases when an original shift would have been
5975 if (! spans_byte
&& GET_CODE (inner
) == MEM
5976 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_BITSIZE (is_mode
))
5977 || (pos_rtx
!= 0 && len
!= 1)))
5980 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5981 and the mode for the result. */
5985 wanted_inner_reg_mode
5986 = insn_data
[(int) CODE_FOR_insv
].operand
[0].mode
;
5987 if (wanted_inner_reg_mode
== VOIDmode
)
5988 wanted_inner_reg_mode
= word_mode
;
5990 pos_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[2].mode
;
5991 if (pos_mode
== VOIDmode
)
5992 pos_mode
= word_mode
;
5994 extraction_mode
= insn_data
[(int) CODE_FOR_insv
].operand
[3].mode
;
5995 if (extraction_mode
== VOIDmode
)
5996 extraction_mode
= word_mode
;
6001 if (! in_dest
&& unsignedp
)
6003 wanted_inner_reg_mode
6004 = insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
6005 if (wanted_inner_reg_mode
== VOIDmode
)
6006 wanted_inner_reg_mode
= word_mode
;
6008 pos_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[3].mode
;
6009 if (pos_mode
== VOIDmode
)
6010 pos_mode
= word_mode
;
6012 extraction_mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[0].mode
;
6013 if (extraction_mode
== VOIDmode
)
6014 extraction_mode
= word_mode
;
6019 if (! in_dest
&& ! unsignedp
)
6021 wanted_inner_reg_mode
6022 = insn_data
[(int) CODE_FOR_extv
].operand
[1].mode
;
6023 if (wanted_inner_reg_mode
== VOIDmode
)
6024 wanted_inner_reg_mode
= word_mode
;
6026 pos_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[3].mode
;
6027 if (pos_mode
== VOIDmode
)
6028 pos_mode
= word_mode
;
6030 extraction_mode
= insn_data
[(int) CODE_FOR_extv
].operand
[0].mode
;
6031 if (extraction_mode
== VOIDmode
)
6032 extraction_mode
= word_mode
;
6036 /* Never narrow an object, since that might not be safe. */
6038 if (mode
!= VOIDmode
6039 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
6040 extraction_mode
= mode
;
6042 if (pos_rtx
&& GET_MODE (pos_rtx
) != VOIDmode
6043 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6044 pos_mode
= GET_MODE (pos_rtx
);
6046 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
6047 if we have to change the mode of memory and cannot, the desired mode is
6049 if (GET_CODE (inner
) != MEM
)
6050 wanted_inner_mode
= wanted_inner_reg_mode
;
6051 else if (inner_mode
!= wanted_inner_mode
6052 && (mode_dependent_address_p (XEXP (inner
, 0))
6053 || MEM_VOLATILE_P (inner
)))
6054 wanted_inner_mode
= extraction_mode
;
6058 if (BITS_BIG_ENDIAN
)
6060 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
6061 BITS_BIG_ENDIAN style. If position is constant, compute new
6062 position. Otherwise, build subtraction.
6063 Note that POS is relative to the mode of the original argument.
6064 If it's a MEM we need to recompute POS relative to that.
6065 However, if we're extracting from (or inserting into) a register,
6066 we want to recompute POS relative to wanted_inner_mode. */
6067 int width
= (GET_CODE (inner
) == MEM
6068 ? GET_MODE_BITSIZE (is_mode
)
6069 : GET_MODE_BITSIZE (wanted_inner_mode
));
6072 pos
= width
- len
- pos
;
6075 = gen_rtx_combine (MINUS
, GET_MODE (pos_rtx
),
6076 GEN_INT (width
- len
), pos_rtx
);
6077 /* POS may be less than 0 now, but we check for that below.
6078 Note that it can only be less than 0 if GET_CODE (inner) != MEM. */
6081 /* If INNER has a wider mode, make it smaller. If this is a constant
6082 extract, try to adjust the byte to point to the byte containing
6084 if (wanted_inner_mode
!= VOIDmode
6085 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
6086 && ((GET_CODE (inner
) == MEM
6087 && (inner_mode
== wanted_inner_mode
6088 || (! mode_dependent_address_p (XEXP (inner
, 0))
6089 && ! MEM_VOLATILE_P (inner
))))))
6093 /* The computations below will be correct if the machine is big
6094 endian in both bits and bytes or little endian in bits and bytes.
6095 If it is mixed, we must adjust. */
6097 /* If bytes are big endian and we had a paradoxical SUBREG, we must
6098 adjust OFFSET to compensate. */
6099 if (BYTES_BIG_ENDIAN
6101 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
6102 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
6104 /* If this is a constant position, we can move to the desired byte. */
6107 offset
+= pos
/ BITS_PER_UNIT
;
6108 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
6111 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
6113 && is_mode
!= wanted_inner_mode
)
6114 offset
= (GET_MODE_SIZE (is_mode
)
6115 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
6117 if (offset
!= 0 || inner_mode
!= wanted_inner_mode
)
6119 rtx newmem
= gen_rtx_MEM (wanted_inner_mode
,
6120 plus_constant (XEXP (inner
, 0), offset
));
6121 RTX_UNCHANGING_P (newmem
) = RTX_UNCHANGING_P (inner
);
6122 MEM_COPY_ATTRIBUTES (newmem
, inner
);
6127 /* If INNER is not memory, we can always get it into the proper mode. If we
6128 are changing its mode, POS must be a constant and smaller than the size
6130 else if (GET_CODE (inner
) != MEM
)
6132 if (GET_MODE (inner
) != wanted_inner_mode
6134 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
6137 inner
= force_to_mode (inner
, wanted_inner_mode
,
6139 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
6140 ? GET_MODE_MASK (wanted_inner_mode
)
6141 : ((((unsigned HOST_WIDE_INT
) 1 << len
) - 1)
6146 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6147 have to zero extend. Otherwise, we can just use a SUBREG. */
6149 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6151 rtx temp
= gen_rtx_combine (ZERO_EXTEND
, pos_mode
, pos_rtx
);
6153 /* If we know that no extraneous bits are set, and that the high
6154 bit is not set, convert extraction to cheaper one - eighter
6155 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6157 if (flag_expensive_optimizations
6158 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx
)) <= HOST_BITS_PER_WIDE_INT
6159 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
6160 & ~ (((unsigned HOST_WIDE_INT
)
6161 GET_MODE_MASK (GET_MODE (pos_rtx
)))
6165 rtx temp1
= gen_rtx_SIGN_EXTEND (pos_mode
, pos_rtx
);
6167 /* Preffer ZERO_EXTENSION, since it gives more information to
6169 if (rtx_cost (temp1
, SET
) < rtx_cost (temp
, SET
))
6174 else if (pos_rtx
!= 0
6175 && GET_MODE_SIZE (pos_mode
) < GET_MODE_SIZE (GET_MODE (pos_rtx
)))
6176 pos_rtx
= gen_lowpart_for_combine (pos_mode
, pos_rtx
);
6178 /* Make POS_RTX unless we already have it and it is correct. If we don't
6179 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6181 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
6182 pos_rtx
= orig_pos_rtx
;
6184 else if (pos_rtx
== 0)
6185 pos_rtx
= GEN_INT (pos
);
6187 /* Make the required operation. See if we can use existing rtx. */
6188 new = gen_rtx_combine (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
6189 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
6191 new = gen_lowpart_for_combine (mode
, new);
6196 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6197 with any other operations in X. Return X without that shift if so. */
6200 extract_left_shift (x
, count
)
6204 enum rtx_code code
= GET_CODE (x
);
6205 enum machine_mode mode
= GET_MODE (x
);
6211 /* This is the shift itself. If it is wide enough, we will return
6212 either the value being shifted if the shift count is equal to
6213 COUNT or a shift for the difference. */
6214 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6215 && INTVAL (XEXP (x
, 1)) >= count
)
6216 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
6217 INTVAL (XEXP (x
, 1)) - count
);
6221 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6222 return gen_unary (code
, mode
, mode
, tem
);
6226 case PLUS
: case IOR
: case XOR
: case AND
:
6227 /* If we can safely shift this constant and we find the inner shift,
6228 make a new operation. */
6229 if (GET_CODE (XEXP (x
,1)) == CONST_INT
6230 && (INTVAL (XEXP (x
, 1)) & ((((HOST_WIDE_INT
) 1 << count
)) - 1)) == 0
6231 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
6232 return gen_binary (code
, mode
, tem
,
6233 GEN_INT (INTVAL (XEXP (x
, 1)) >> count
));
6244 /* Look at the expression rooted at X. Look for expressions
6245 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6246 Form these expressions.
6248 Return the new rtx, usually just X.
6250 Also, for machines like the Vax that don't have logical shift insns,
6251 try to convert logical to arithmetic shift operations in cases where
6252 they are equivalent. This undoes the canonicalizations to logical
6253 shifts done elsewhere.
6255 We try, as much as possible, to re-use rtl expressions to save memory.
6257 IN_CODE says what kind of expression we are processing. Normally, it is
6258 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6259 being kludges), it is MEM. When processing the arguments of a comparison
6260 or a COMPARE against zero, it is COMPARE. */
6263 make_compound_operation (x
, in_code
)
6265 enum rtx_code in_code
;
6267 enum rtx_code code
= GET_CODE (x
);
6268 enum machine_mode mode
= GET_MODE (x
);
6269 int mode_width
= GET_MODE_BITSIZE (mode
);
6271 enum rtx_code next_code
;
6277 /* Select the code to be used in recursive calls. Once we are inside an
6278 address, we stay there. If we have a comparison, set to COMPARE,
6279 but once inside, go back to our default of SET. */
6281 next_code
= (code
== MEM
|| code
== PLUS
|| code
== MINUS
? MEM
6282 : ((code
== COMPARE
|| GET_RTX_CLASS (code
) == '<')
6283 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
6284 : in_code
== COMPARE
? SET
: in_code
);
6286 /* Process depending on the code of this operation. If NEW is set
6287 non-zero, it will be returned. */
6292 /* Convert shifts by constants into multiplications if inside
6294 if (in_code
== MEM
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6295 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6296 && INTVAL (XEXP (x
, 1)) >= 0)
6298 new = make_compound_operation (XEXP (x
, 0), next_code
);
6299 new = gen_rtx_combine (MULT
, mode
, new,
6300 GEN_INT ((HOST_WIDE_INT
) 1
6301 << INTVAL (XEXP (x
, 1))));
6306 /* If the second operand is not a constant, we can't do anything
6308 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
6311 /* If the constant is a power of two minus one and the first operand
6312 is a logical right shift, make an extraction. */
6313 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6314 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6316 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6317 new = make_extraction (mode
, new, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
6318 0, in_code
== COMPARE
);
6321 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6322 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
6323 && subreg_lowpart_p (XEXP (x
, 0))
6324 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
6325 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6327 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x
, 0)), 0),
6329 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x
, 0))), new, 0,
6330 XEXP (SUBREG_REG (XEXP (x
, 0)), 1), i
, 1,
6331 0, in_code
== COMPARE
);
6333 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6334 else if ((GET_CODE (XEXP (x
, 0)) == XOR
6335 || GET_CODE (XEXP (x
, 0)) == IOR
)
6336 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
6337 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
6338 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6340 /* Apply the distributive law, and then try to make extractions. */
6341 new = gen_rtx_combine (GET_CODE (XEXP (x
, 0)), mode
,
6342 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
6344 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
6346 new = make_compound_operation (new, in_code
);
6349 /* If we are have (and (rotate X C) M) and C is larger than the number
6350 of bits in M, this is an extraction. */
6352 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
6353 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6354 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0
6355 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
6357 new = make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
6358 new = make_extraction (mode
, new,
6359 (GET_MODE_BITSIZE (mode
)
6360 - INTVAL (XEXP (XEXP (x
, 0), 1))),
6361 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6364 /* On machines without logical shifts, if the operand of the AND is
6365 a logical shift and our mask turns off all the propagated sign
6366 bits, we can replace the logical shift with an arithmetic shift. */
6367 else if (ashr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
6368 && (lshr_optab
->handlers
[(int) mode
].insn_code
6369 == CODE_FOR_nothing
)
6370 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6371 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6372 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6373 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6374 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
6376 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
6378 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
6379 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
6381 gen_rtx_combine (ASHIFTRT
, mode
,
6382 make_compound_operation (XEXP (XEXP (x
, 0), 0),
6384 XEXP (XEXP (x
, 0), 1)));
6387 /* If the constant is one less than a power of two, this might be
6388 representable by an extraction even if no shift is present.
6389 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6390 we are in a COMPARE. */
6391 else if ((i
= exact_log2 (INTVAL (XEXP (x
, 1)) + 1)) >= 0)
6392 new = make_extraction (mode
,
6393 make_compound_operation (XEXP (x
, 0),
6395 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
6397 /* If we are in a comparison and this is an AND with a power of two,
6398 convert this into the appropriate bit extract. */
6399 else if (in_code
== COMPARE
6400 && (i
= exact_log2 (INTVAL (XEXP (x
, 1)))) >= 0)
6401 new = make_extraction (mode
,
6402 make_compound_operation (XEXP (x
, 0),
6404 i
, NULL_RTX
, 1, 1, 0, 1);
6409 /* If the sign bit is known to be zero, replace this with an
6410 arithmetic shift. */
6411 if (ashr_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
6412 && lshr_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
6413 && mode_width
<= HOST_BITS_PER_WIDE_INT
6414 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
6416 new = gen_rtx_combine (ASHIFTRT
, mode
,
6417 make_compound_operation (XEXP (x
, 0),
6423 /* ... fall through ... */
6429 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6430 this is a SIGN_EXTRACT. */
6431 if (GET_CODE (rhs
) == CONST_INT
6432 && GET_CODE (lhs
) == ASHIFT
6433 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
6434 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1)))
6436 new = make_compound_operation (XEXP (lhs
, 0), next_code
);
6437 new = make_extraction (mode
, new,
6438 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
6439 NULL_RTX
, mode_width
- INTVAL (rhs
),
6440 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6443 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6444 If so, try to merge the shifts into a SIGN_EXTEND. We could
6445 also do this for some cases of SIGN_EXTRACT, but it doesn't
6446 seem worth the effort; the case checked for occurs on Alpha. */
6448 if (GET_RTX_CLASS (GET_CODE (lhs
)) != 'o'
6449 && ! (GET_CODE (lhs
) == SUBREG
6450 && (GET_RTX_CLASS (GET_CODE (SUBREG_REG (lhs
))) == 'o'))
6451 && GET_CODE (rhs
) == CONST_INT
6452 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
6453 && (new = extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
6454 new = make_extraction (mode
, make_compound_operation (new, next_code
),
6455 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
6456 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
6461 /* Call ourselves recursively on the inner expression. If we are
6462 narrowing the object and it has a different RTL code from
6463 what it originally did, do this SUBREG as a force_to_mode. */
6465 tem
= make_compound_operation (SUBREG_REG (x
), in_code
);
6466 if (GET_CODE (tem
) != GET_CODE (SUBREG_REG (x
))
6467 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (tem
))
6468 && subreg_lowpart_p (x
))
6470 rtx newer
= force_to_mode (tem
, mode
,
6471 GET_MODE_MASK (mode
), NULL_RTX
, 0);
6473 /* If we have something other than a SUBREG, we might have
6474 done an expansion, so rerun outselves. */
6475 if (GET_CODE (newer
) != SUBREG
)
6476 newer
= make_compound_operation (newer
, in_code
);
6481 /* If this is a paradoxical subreg, and the new code is a sign or
6482 zero extension, omit the subreg and widen the extension. If it
6483 is a regular subreg, we can still get rid of the subreg by not
6484 widening so much, or in fact removing the extension entirely. */
6485 if ((GET_CODE (tem
) == SIGN_EXTEND
6486 || GET_CODE (tem
) == ZERO_EXTEND
)
6487 && subreg_lowpart_p (x
))
6489 if (GET_MODE_SIZE (mode
) > GET_MODE_SIZE (GET_MODE (tem
))
6490 || (GET_MODE_SIZE (mode
) >
6491 GET_MODE_SIZE (GET_MODE (XEXP (tem
, 0)))))
6492 tem
= gen_rtx_combine (GET_CODE (tem
), mode
, XEXP (tem
, 0));
6494 tem
= gen_lowpart_for_combine (mode
, XEXP (tem
, 0));
6505 x
= gen_lowpart_for_combine (mode
, new);
6506 code
= GET_CODE (x
);
6509 /* Now recursively process each operand of this operation. */
6510 fmt
= GET_RTX_FORMAT (code
);
6511 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
6514 new = make_compound_operation (XEXP (x
, i
), next_code
);
6515 SUBST (XEXP (x
, i
), new);
6521 /* Given M see if it is a value that would select a field of bits
6522 within an item, but not the entire word. Return -1 if not.
6523 Otherwise, return the starting position of the field, where 0 is the
6526 *PLEN is set to the length of the field. */
6529 get_pos_from_mask (m
, plen
)
6530 unsigned HOST_WIDE_INT m
;
6533 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6534 int pos
= exact_log2 (m
& - m
);
6539 /* Now shift off the low-order zero bits and see if we have a power of
6541 *plen
= exact_log2 ((m
>> pos
) + 1);
6549 /* See if X can be simplified knowing that we will only refer to it in
6550 MODE and will only refer to those bits that are nonzero in MASK.
6551 If other bits are being computed or if masking operations are done
6552 that select a superset of the bits in MASK, they can sometimes be
6555 Return a possibly simplified expression, but always convert X to
6556 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6558 Also, if REG is non-zero and X is a register equal in value to REG,
6561 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6562 are all off in X. This is used when X will be complemented, by either
6563 NOT, NEG, or XOR. */
6566 force_to_mode (x
, mode
, mask
, reg
, just_select
)
6568 enum machine_mode mode
;
6569 unsigned HOST_WIDE_INT mask
;
6573 enum rtx_code code
= GET_CODE (x
);
6574 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
6575 enum machine_mode op_mode
;
6576 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
6579 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6580 code below will do the wrong thing since the mode of such an
6581 expression is VOIDmode.
6583 Also do nothing if X is a CLOBBER; this can happen if X was
6584 the return value from a call to gen_lowpart_for_combine. */
6585 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
6588 /* We want to perform the operation is its present mode unless we know
6589 that the operation is valid in MODE, in which case we do the operation
6591 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
6592 && code_to_optab
[(int) code
] != 0
6593 && (code_to_optab
[(int) code
]->handlers
[(int) mode
].insn_code
6594 != CODE_FOR_nothing
))
6595 ? mode
: GET_MODE (x
));
6597 /* It is not valid to do a right-shift in a narrower mode
6598 than the one it came in with. */
6599 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
6600 && GET_MODE_BITSIZE (mode
) < GET_MODE_BITSIZE (GET_MODE (x
)))
6601 op_mode
= GET_MODE (x
);
6603 /* Truncate MASK to fit OP_MODE. */
6605 mask
&= GET_MODE_MASK (op_mode
);
6607 /* When we have an arithmetic operation, or a shift whose count we
6608 do not know, we need to assume that all bit the up to the highest-order
6609 bit in MASK will be needed. This is how we form such a mask. */
6611 fuller_mask
= (GET_MODE_BITSIZE (op_mode
) >= HOST_BITS_PER_WIDE_INT
6612 ? GET_MODE_MASK (op_mode
)
6613 : (((unsigned HOST_WIDE_INT
) 1 << (floor_log2 (mask
) + 1))
6616 fuller_mask
= ~ (HOST_WIDE_INT
) 0;
6618 /* Determine what bits of X are guaranteed to be (non)zero. */
6619 nonzero
= nonzero_bits (x
, mode
);
6621 /* If none of the bits in X are needed, return a zero. */
6622 if (! just_select
&& (nonzero
& mask
) == 0)
6625 /* If X is a CONST_INT, return a new one. Do this here since the
6626 test below will fail. */
6627 if (GET_CODE (x
) == CONST_INT
)
6629 HOST_WIDE_INT cval
= INTVAL (x
) & mask
;
6630 int width
= GET_MODE_BITSIZE (mode
);
6632 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6633 number, sign extend it. */
6634 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6635 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6636 cval
|= (HOST_WIDE_INT
) -1 << width
;
6638 return GEN_INT (cval
);
6641 /* If X is narrower than MODE and we want all the bits in X's mode, just
6642 get X in the proper mode. */
6643 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
6644 && (GET_MODE_MASK (GET_MODE (x
)) & ~ mask
) == 0)
6645 return gen_lowpart_for_combine (mode
, x
);
6647 /* If we aren't changing the mode, X is not a SUBREG, and all zero bits in
6648 MASK are already known to be zero in X, we need not do anything. */
6649 if (GET_MODE (x
) == mode
&& code
!= SUBREG
&& (~ mask
& nonzero
) == 0)
6655 /* If X is a (clobber (const_int)), return it since we know we are
6656 generating something that won't match. */
6660 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6661 spanned the boundary of the MEM. If we are now masking so it is
6662 within that boundary, we don't need the USE any more. */
6663 if (! BITS_BIG_ENDIAN
6664 && (mask
& ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
6665 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6672 x
= expand_compound_operation (x
);
6673 if (GET_CODE (x
) != code
)
6674 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6678 if (reg
!= 0 && (rtx_equal_p (get_last_value (reg
), x
)
6679 || rtx_equal_p (reg
, get_last_value (x
))))
6684 if (subreg_lowpart_p (x
)
6685 /* We can ignore the effect of this SUBREG if it narrows the mode or
6686 if the constant masks to zero all the bits the mode doesn't
6688 && ((GET_MODE_SIZE (GET_MODE (x
))
6689 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
6691 & GET_MODE_MASK (GET_MODE (x
))
6692 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
6693 return force_to_mode (SUBREG_REG (x
), mode
, mask
, reg
, next_select
);
6697 /* If this is an AND with a constant, convert it into an AND
6698 whose constant is the AND of that constant with MASK. If it
6699 remains an AND of MASK, delete it since it is redundant. */
6701 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
6703 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
6704 mask
& INTVAL (XEXP (x
, 1)));
6706 /* If X is still an AND, see if it is an AND with a mask that
6707 is just some low-order bits. If so, and it is MASK, we don't
6710 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6711 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) == mask
)
6714 /* If it remains an AND, try making another AND with the bits
6715 in the mode mask that aren't in MASK turned on. If the
6716 constant in the AND is wide enough, this might make a
6717 cheaper constant. */
6719 if (GET_CODE (x
) == AND
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
6720 && GET_MODE_MASK (GET_MODE (x
)) != mask
6721 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
)
6723 HOST_WIDE_INT cval
= (INTVAL (XEXP (x
, 1))
6724 | (GET_MODE_MASK (GET_MODE (x
)) & ~ mask
));
6725 int width
= GET_MODE_BITSIZE (GET_MODE (x
));
6728 /* If MODE is narrower that HOST_WIDE_INT and CVAL is a negative
6729 number, sign extend it. */
6730 if (width
> 0 && width
< HOST_BITS_PER_WIDE_INT
6731 && (cval
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6732 cval
|= (HOST_WIDE_INT
) -1 << width
;
6734 y
= gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0), GEN_INT (cval
));
6735 if (rtx_cost (y
, SET
) < rtx_cost (x
, SET
))
6745 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6746 low-order bits (as in an alignment operation) and FOO is already
6747 aligned to that boundary, mask C1 to that boundary as well.
6748 This may eliminate that PLUS and, later, the AND. */
6751 int width
= GET_MODE_BITSIZE (mode
);
6752 unsigned HOST_WIDE_INT smask
= mask
;
6754 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6755 number, sign extend it. */
6757 if (width
< HOST_BITS_PER_WIDE_INT
6758 && (smask
& ((HOST_WIDE_INT
) 1 << (width
- 1))) != 0)
6759 smask
|= (HOST_WIDE_INT
) -1 << width
;
6761 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6762 && exact_log2 (- smask
) >= 0)
6766 && (XEXP (x
, 0) == stack_pointer_rtx
6767 || XEXP (x
, 0) == frame_pointer_rtx
))
6769 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
6770 unsigned HOST_WIDE_INT sp_mask
= GET_MODE_MASK (mode
);
6772 sp_mask
&= ~ (sp_alignment
- 1);
6773 if ((sp_mask
& ~ smask
) == 0
6774 && ((INTVAL (XEXP (x
, 1)) - STACK_BIAS
) & ~ smask
) != 0)
6775 return force_to_mode (plus_constant (XEXP (x
, 0),
6776 ((INTVAL (XEXP (x
, 1)) -
6777 STACK_BIAS
) & smask
)
6779 mode
, smask
, reg
, next_select
);
6782 if ((nonzero_bits (XEXP (x
, 0), mode
) & ~ smask
) == 0
6783 && (INTVAL (XEXP (x
, 1)) & ~ smask
) != 0)
6784 return force_to_mode (plus_constant (XEXP (x
, 0),
6785 (INTVAL (XEXP (x
, 1))
6787 mode
, smask
, reg
, next_select
);
6791 /* ... fall through ... */
6795 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6796 most significant bit in MASK since carries from those bits will
6797 affect the bits we are interested in. */
6803 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6804 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6805 operation which may be a bitfield extraction. Ensure that the
6806 constant we form is not wider than the mode of X. */
6808 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
6809 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
6810 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
6811 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
6812 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6813 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
6814 + floor_log2 (INTVAL (XEXP (x
, 1))))
6815 < GET_MODE_BITSIZE (GET_MODE (x
)))
6816 && (INTVAL (XEXP (x
, 1))
6817 & ~ nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
6819 temp
= GEN_INT ((INTVAL (XEXP (x
, 1)) & mask
)
6820 << INTVAL (XEXP (XEXP (x
, 0), 1)));
6821 temp
= gen_binary (GET_CODE (x
), GET_MODE (x
),
6822 XEXP (XEXP (x
, 0), 0), temp
);
6823 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
6824 XEXP (XEXP (x
, 0), 1));
6825 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6829 /* For most binary operations, just propagate into the operation and
6830 change the mode if we have an operation of that mode. */
6832 op0
= gen_lowpart_for_combine (op_mode
,
6833 force_to_mode (XEXP (x
, 0), mode
, mask
,
6835 op1
= gen_lowpart_for_combine (op_mode
,
6836 force_to_mode (XEXP (x
, 1), mode
, mask
,
6839 /* If OP1 is a CONST_INT and X is an IOR or XOR, clear bits outside
6840 MASK since OP1 might have been sign-extended but we never want
6841 to turn on extra bits, since combine might have previously relied
6842 on them being off. */
6843 if (GET_CODE (op1
) == CONST_INT
&& (code
== IOR
|| code
== XOR
)
6844 && (INTVAL (op1
) & mask
) != 0)
6845 op1
= GEN_INT (INTVAL (op1
) & mask
);
6847 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
6848 x
= gen_binary (code
, op_mode
, op0
, op1
);
6852 /* For left shifts, do the same, but just for the first operand.
6853 However, we cannot do anything with shifts where we cannot
6854 guarantee that the counts are smaller than the size of the mode
6855 because such a count will have a different meaning in a
6858 if (! (GET_CODE (XEXP (x
, 1)) == CONST_INT
6859 && INTVAL (XEXP (x
, 1)) >= 0
6860 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (mode
))
6861 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
6862 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
6863 < (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
))))
6866 /* If the shift count is a constant and we can do arithmetic in
6867 the mode of the shift, refine which bits we need. Otherwise, use the
6868 conservative form of the mask. */
6869 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6870 && INTVAL (XEXP (x
, 1)) >= 0
6871 && INTVAL (XEXP (x
, 1)) < GET_MODE_BITSIZE (op_mode
)
6872 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6873 mask
>>= INTVAL (XEXP (x
, 1));
6877 op0
= gen_lowpart_for_combine (op_mode
,
6878 force_to_mode (XEXP (x
, 0), op_mode
,
6879 mask
, reg
, next_select
));
6881 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
6882 x
= gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
6886 /* Here we can only do something if the shift count is a constant,
6887 this shift constant is valid for the host, and we can do arithmetic
6890 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
6891 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
6892 && GET_MODE_BITSIZE (op_mode
) <= HOST_BITS_PER_WIDE_INT
)
6894 rtx inner
= XEXP (x
, 0);
6895 unsigned HOST_WIDE_INT inner_mask
;
6897 /* Select the mask of the bits we need for the shift operand. */
6898 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
6900 /* We can only change the mode of the shift if we can do arithmetic
6901 in the mode of the shift and INNER_MASK is no wider than the
6902 width of OP_MODE. */
6903 if (GET_MODE_BITSIZE (op_mode
) > HOST_BITS_PER_WIDE_INT
6904 || (inner_mask
& ~ GET_MODE_MASK (op_mode
)) != 0)
6905 op_mode
= GET_MODE (x
);
6907 inner
= force_to_mode (inner
, op_mode
, inner_mask
, reg
, next_select
);
6909 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
6910 x
= gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
6913 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6914 shift and AND produces only copies of the sign bit (C2 is one less
6915 than a power of two), we can do this with just a shift. */
6917 if (GET_CODE (x
) == LSHIFTRT
6918 && GET_CODE (XEXP (x
, 1)) == CONST_INT
6919 && ((INTVAL (XEXP (x
, 1))
6920 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
6921 >= GET_MODE_BITSIZE (GET_MODE (x
)))
6922 && exact_log2 (mask
+ 1) >= 0
6923 && (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
6924 >= exact_log2 (mask
+ 1)))
6925 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
6926 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x
))
6927 - exact_log2 (mask
+ 1)));
6932 /* If we are just looking for the sign bit, we don't need this shift at
6933 all, even if it has a variable count. */
6934 if (GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
6935 && (mask
== ((unsigned HOST_WIDE_INT
) 1
6936 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
6937 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
6939 /* If this is a shift by a constant, get a mask that contains those bits
6940 that are not copies of the sign bit. We then have two cases: If
6941 MASK only includes those bits, this can be a logical shift, which may
6942 allow simplifications. If MASK is a single-bit field not within
6943 those bits, we are requesting a copy of the sign bit and hence can
6944 shift the sign bit to the appropriate location. */
6946 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) >= 0
6947 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
6951 /* If the considered data is wider then HOST_WIDE_INT, we can't
6952 represent a mask for all its bits in a single scalar.
6953 But we only care about the lower bits, so calculate these. */
6955 if (GET_MODE_BITSIZE (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
6957 nonzero
= ~ (HOST_WIDE_INT
) 0;
6959 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6960 is the number of bits a full-width mask would have set.
6961 We need only shift if these are fewer than nonzero can
6962 hold. If not, we must keep all bits set in nonzero. */
6964 if (GET_MODE_BITSIZE (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
6965 < HOST_BITS_PER_WIDE_INT
)
6966 nonzero
>>= INTVAL (XEXP (x
, 1))
6967 + HOST_BITS_PER_WIDE_INT
6968 - GET_MODE_BITSIZE (GET_MODE (x
)) ;
6972 nonzero
= GET_MODE_MASK (GET_MODE (x
));
6973 nonzero
>>= INTVAL (XEXP (x
, 1));
6976 if ((mask
& ~ nonzero
) == 0
6977 || (i
= exact_log2 (mask
)) >= 0)
6979 x
= simplify_shift_const
6980 (x
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
6981 i
< 0 ? INTVAL (XEXP (x
, 1))
6982 : GET_MODE_BITSIZE (GET_MODE (x
)) - 1 - i
);
6984 if (GET_CODE (x
) != ASHIFTRT
)
6985 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
6989 /* If MASK is 1, convert this to a LSHIFTRT. This can be done
6990 even if the shift count isn't a constant. */
6992 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0), XEXP (x
, 1));
6996 /* If this is a zero- or sign-extension operation that just affects bits
6997 we don't care about, remove it. Be sure the call above returned
6998 something that is still a shift. */
7000 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
7001 && GET_CODE (XEXP (x
, 1)) == CONST_INT
7002 && INTVAL (XEXP (x
, 1)) >= 0
7003 && (INTVAL (XEXP (x
, 1))
7004 <= GET_MODE_BITSIZE (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
7005 && GET_CODE (XEXP (x
, 0)) == ASHIFT
7006 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7007 && INTVAL (XEXP (XEXP (x
, 0), 1)) == INTVAL (XEXP (x
, 1)))
7008 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
7015 /* If the shift count is constant and we can do computations
7016 in the mode of X, compute where the bits we care about are.
7017 Otherwise, we can't do anything. Don't change the mode of
7018 the shift or propagate MODE into the shift, though. */
7019 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
7020 && INTVAL (XEXP (x
, 1)) >= 0)
7022 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
7023 GET_MODE (x
), GEN_INT (mask
),
7025 if (temp
&& GET_CODE(temp
) == CONST_INT
)
7027 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
7028 INTVAL (temp
), reg
, next_select
));
7033 /* If we just want the low-order bit, the NEG isn't needed since it
7034 won't change the low-order bit. */
7036 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, just_select
);
7038 /* We need any bits less significant than the most significant bit in
7039 MASK since carries from those bits will affect the bits we are
7045 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7046 same as the XOR case above. Ensure that the constant we form is not
7047 wider than the mode of X. */
7049 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7050 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
7051 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7052 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
7053 < GET_MODE_BITSIZE (GET_MODE (x
)))
7054 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
7056 temp
= GEN_INT (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)));
7057 temp
= gen_binary (XOR
, GET_MODE (x
), XEXP (XEXP (x
, 0), 0), temp
);
7058 x
= gen_binary (LSHIFTRT
, GET_MODE (x
), temp
, XEXP (XEXP (x
, 0), 1));
7060 return force_to_mode (x
, mode
, mask
, reg
, next_select
);
7063 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7064 use the full mask inside the NOT. */
7068 op0
= gen_lowpart_for_combine (op_mode
,
7069 force_to_mode (XEXP (x
, 0), mode
, mask
,
7071 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
7072 x
= gen_unary (code
, op_mode
, op_mode
, op0
);
7076 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7077 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7078 which is equal to STORE_FLAG_VALUE. */
7079 if ((mask
& ~ STORE_FLAG_VALUE
) == 0 && XEXP (x
, 1) == const0_rtx
7080 && exact_log2 (nonzero_bits (XEXP (x
, 0), mode
)) >= 0
7081 && nonzero_bits (XEXP (x
, 0), mode
) == STORE_FLAG_VALUE
)
7082 return force_to_mode (XEXP (x
, 0), mode
, mask
, reg
, next_select
);
7087 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7088 written in a narrower mode. We play it safe and do not do so. */
7091 gen_lowpart_for_combine (GET_MODE (x
),
7092 force_to_mode (XEXP (x
, 1), mode
,
7093 mask
, reg
, next_select
)));
7095 gen_lowpart_for_combine (GET_MODE (x
),
7096 force_to_mode (XEXP (x
, 2), mode
,
7097 mask
, reg
,next_select
)));
7104 /* Ensure we return a value of the proper mode. */
7105 return gen_lowpart_for_combine (mode
, x
);
7108 /* Return nonzero if X is an expression that has one of two values depending on
7109 whether some other value is zero or nonzero. In that case, we return the
7110 value that is being tested, *PTRUE is set to the value if the rtx being
7111 returned has a nonzero value, and *PFALSE is set to the other alternative.
7113 If we return zero, we set *PTRUE and *PFALSE to X. */
7116 if_then_else_cond (x
, ptrue
, pfalse
)
7118 rtx
*ptrue
, *pfalse
;
7120 enum machine_mode mode
= GET_MODE (x
);
7121 enum rtx_code code
= GET_CODE (x
);
7122 int size
= GET_MODE_BITSIZE (mode
);
7123 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
7124 unsigned HOST_WIDE_INT nz
;
7126 /* If we are comparing a value against zero, we are done. */
7127 if ((code
== NE
|| code
== EQ
)
7128 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 0)
7130 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
7131 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
7135 /* If this is a unary operation whose operand has one of two values, apply
7136 our opcode to compute those values. */
7137 else if (GET_RTX_CLASS (code
) == '1'
7138 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
7140 *ptrue
= gen_unary (code
, mode
, GET_MODE (XEXP (x
, 0)), true0
);
7141 *pfalse
= gen_unary (code
, mode
, GET_MODE (XEXP (x
, 0)), false0
);
7145 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7146 make can't possibly match and would suppress other optimizations. */
7147 else if (code
== COMPARE
)
7150 /* If this is a binary operation, see if either side has only one of two
7151 values. If either one does or if both do and they are conditional on
7152 the same value, compute the new true and false values. */
7153 else if (GET_RTX_CLASS (code
) == 'c' || GET_RTX_CLASS (code
) == '2'
7154 || GET_RTX_CLASS (code
) == '<')
7156 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
7157 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
7159 if ((cond0
!= 0 || cond1
!= 0)
7160 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
7162 /* If if_then_else_cond returned zero, then true/false are the
7163 same rtl. We must copy one of them to prevent invalid rtl
7166 true0
= copy_rtx (true0
);
7167 else if (cond1
== 0)
7168 true1
= copy_rtx (true1
);
7170 *ptrue
= gen_binary (code
, mode
, true0
, true1
);
7171 *pfalse
= gen_binary (code
, mode
, false0
, false1
);
7172 return cond0
? cond0
: cond1
;
7175 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7176 operands is zero when the other is non-zero, and vice-versa,
7177 and STORE_FLAG_VALUE is 1 or -1. */
7179 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7180 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
7182 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7184 rtx op0
= XEXP (XEXP (x
, 0), 1);
7185 rtx op1
= XEXP (XEXP (x
, 1), 1);
7187 cond0
= XEXP (XEXP (x
, 0), 0);
7188 cond1
= XEXP (XEXP (x
, 1), 0);
7190 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7191 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7192 && reversible_comparison_p (cond1
)
7193 && ((GET_CODE (cond0
) == reverse_condition (GET_CODE (cond1
))
7194 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7195 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7196 || ((swap_condition (GET_CODE (cond0
))
7197 == reverse_condition (GET_CODE (cond1
)))
7198 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7199 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7200 && ! side_effects_p (x
))
7202 *ptrue
= gen_binary (MULT
, mode
, op0
, const_true_rtx
);
7203 *pfalse
= gen_binary (MULT
, mode
,
7205 ? gen_unary (NEG
, mode
, mode
, op1
) : op1
),
7211 /* Similarly for MULT, AND and UMIN, execpt that for these the result
7213 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
7214 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
7215 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
7217 cond0
= XEXP (XEXP (x
, 0), 0);
7218 cond1
= XEXP (XEXP (x
, 1), 0);
7220 if (GET_RTX_CLASS (GET_CODE (cond0
)) == '<'
7221 && GET_RTX_CLASS (GET_CODE (cond1
)) == '<'
7222 && reversible_comparison_p (cond1
)
7223 && ((GET_CODE (cond0
) == reverse_condition (GET_CODE (cond1
))
7224 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
7225 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
7226 || ((swap_condition (GET_CODE (cond0
))
7227 == reverse_condition (GET_CODE (cond1
)))
7228 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
7229 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
7230 && ! side_effects_p (x
))
7232 *ptrue
= *pfalse
= const0_rtx
;
7238 else if (code
== IF_THEN_ELSE
)
7240 /* If we have IF_THEN_ELSE already, extract the condition and
7241 canonicalize it if it is NE or EQ. */
7242 cond0
= XEXP (x
, 0);
7243 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
7244 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
7245 return XEXP (cond0
, 0);
7246 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
7248 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
7249 return XEXP (cond0
, 0);
7255 /* If X is a normal SUBREG with both inner and outer modes integral,
7256 we can narrow both the true and false values of the inner expression,
7257 if there is a condition. */
7258 else if (code
== SUBREG
&& GET_MODE_CLASS (mode
) == MODE_INT
7259 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_INT
7260 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
)))
7261 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
7264 if ((GET_CODE (SUBREG_REG (x
)) == REG
7265 || GET_CODE (SUBREG_REG (x
)) == MEM
7266 || CONSTANT_P (SUBREG_REG (x
)))
7267 && GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))) > UNITS_PER_WORD
7268 && (WORDS_BIG_ENDIAN
|| SUBREG_WORD (x
) != 0))
7270 true0
= operand_subword (true0
, SUBREG_WORD (x
), 0, mode
);
7271 false0
= operand_subword (false0
, SUBREG_WORD (x
), 0, mode
);
7273 *ptrue
= force_to_mode (true0
, mode
, GET_MODE_MASK (mode
), NULL_RTX
, 0);
7275 = force_to_mode (false0
, mode
, GET_MODE_MASK (mode
), NULL_RTX
, 0);
7280 /* If X is a constant, this isn't special and will cause confusions
7281 if we treat it as such. Likewise if it is equivalent to a constant. */
7282 else if (CONSTANT_P (x
)
7283 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
7286 /* If X is known to be either 0 or -1, those are the true and
7287 false values when testing X. */
7288 else if (num_sign_bit_copies (x
, mode
) == size
)
7290 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
7294 /* Likewise for 0 or a single bit. */
7295 else if (exact_log2 (nz
= nonzero_bits (x
, mode
)) >= 0)
7297 *ptrue
= GEN_INT (nz
), *pfalse
= const0_rtx
;
7301 /* Otherwise fail; show no condition with true and false values the same. */
7302 *ptrue
= *pfalse
= x
;
7306 /* Return the value of expression X given the fact that condition COND
7307 is known to be true when applied to REG as its first operand and VAL
7308 as its second. X is known to not be shared and so can be modified in
7311 We only handle the simplest cases, and specifically those cases that
7312 arise with IF_THEN_ELSE expressions. */
7315 known_cond (x
, cond
, reg
, val
)
7320 enum rtx_code code
= GET_CODE (x
);
7325 if (side_effects_p (x
))
7328 if (cond
== EQ
&& rtx_equal_p (x
, reg
))
7331 /* If X is (abs REG) and we know something about REG's relationship
7332 with zero, we may be able to simplify this. */
7334 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
7337 case GE
: case GT
: case EQ
:
7340 return gen_unary (NEG
, GET_MODE (XEXP (x
, 0)), GET_MODE (XEXP (x
, 0)),
7346 /* The only other cases we handle are MIN, MAX, and comparisons if the
7347 operands are the same as REG and VAL. */
7349 else if (GET_RTX_CLASS (code
) == '<' || GET_RTX_CLASS (code
) == 'c')
7351 if (rtx_equal_p (XEXP (x
, 0), val
))
7352 cond
= swap_condition (cond
), temp
= val
, val
= reg
, reg
= temp
;
7354 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
7356 if (GET_RTX_CLASS (code
) == '<')
7358 if (comparison_dominates_p (cond
, code
))
7359 return const_true_rtx
;
7361 code
= reverse_condition (code
);
7363 && comparison_dominates_p (cond
, code
))
7368 else if (code
== SMAX
|| code
== SMIN
7369 || code
== UMIN
|| code
== UMAX
)
7371 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
7373 if (code
== SMAX
|| code
== UMAX
)
7374 cond
= reverse_condition (cond
);
7379 return unsignedp
? x
: XEXP (x
, 1);
7381 return unsignedp
? x
: XEXP (x
, 0);
7383 return unsignedp
? XEXP (x
, 1) : x
;
7385 return unsignedp
? XEXP (x
, 0) : x
;
7393 fmt
= GET_RTX_FORMAT (code
);
7394 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
7397 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
7398 else if (fmt
[i
] == 'E')
7399 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
7400 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
7407 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7408 assignment as a field assignment. */
7411 rtx_equal_for_field_assignment_p (x
, y
)
7415 if (x
== y
|| rtx_equal_p (x
, y
))
7418 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
7421 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7422 Note that all SUBREGs of MEM are paradoxical; otherwise they
7423 would have been rewritten. */
7424 if (GET_CODE (x
) == MEM
&& GET_CODE (y
) == SUBREG
7425 && GET_CODE (SUBREG_REG (y
)) == MEM
7426 && rtx_equal_p (SUBREG_REG (y
),
7427 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (y
)), x
)))
7430 if (GET_CODE (y
) == MEM
&& GET_CODE (x
) == SUBREG
7431 && GET_CODE (SUBREG_REG (x
)) == MEM
7432 && rtx_equal_p (SUBREG_REG (x
),
7433 gen_lowpart_for_combine (GET_MODE (SUBREG_REG (x
)), y
)))
7436 /* We used to see if get_last_value of X and Y were the same but that's
7437 not correct. In one direction, we'll cause the assignment to have
7438 the wrong destination and in the case, we'll import a register into this
7439 insn that might have already have been dead. So fail if none of the
7440 above cases are true. */
7444 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7445 Return that assignment if so.
7447 We only handle the most common cases. */
7450 make_field_assignment (x
)
7453 rtx dest
= SET_DEST (x
);
7454 rtx src
= SET_SRC (x
);
7460 enum machine_mode mode
;
7462 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7463 a clear of a one-bit field. We will have changed it to
7464 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7467 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
7468 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == CONST_INT
7469 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
7470 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7472 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7475 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7479 else if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
7480 && subreg_lowpart_p (XEXP (src
, 0))
7481 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
7482 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
7483 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
7484 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
7485 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7487 assign
= make_extraction (VOIDmode
, dest
, 0,
7488 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
7491 return gen_rtx_SET (VOIDmode
, assign
, const0_rtx
);
7495 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7497 else if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
7498 && XEXP (XEXP (src
, 0), 0) == const1_rtx
7499 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
7501 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
7504 return gen_rtx_SET (VOIDmode
, assign
, const1_rtx
);
7508 /* The other case we handle is assignments into a constant-position
7509 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7510 a mask that has all one bits except for a group of zero bits and
7511 OTHER is known to have zeros where C1 has ones, this is such an
7512 assignment. Compute the position and length from C1. Shift OTHER
7513 to the appropriate position, force it to the required mode, and
7514 make the extraction. Check for the AND in both operands. */
7516 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
7519 rhs
= expand_compound_operation (XEXP (src
, 0));
7520 lhs
= expand_compound_operation (XEXP (src
, 1));
7522 if (GET_CODE (rhs
) == AND
7523 && GET_CODE (XEXP (rhs
, 1)) == CONST_INT
7524 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
7525 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
7526 else if (GET_CODE (lhs
) == AND
7527 && GET_CODE (XEXP (lhs
, 1)) == CONST_INT
7528 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
7529 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
7533 pos
= get_pos_from_mask ((~ c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
7534 if (pos
< 0 || pos
+ len
> GET_MODE_BITSIZE (GET_MODE (dest
))
7535 || GET_MODE_BITSIZE (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
7536 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
7539 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
7543 /* The mode to use for the source is the mode of the assignment, or of
7544 what is inside a possible STRICT_LOW_PART. */
7545 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
7546 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
7548 /* Shift OTHER right POS places and make it the source, restricting it
7549 to the proper length and mode. */
7551 src
= force_to_mode (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7552 GET_MODE (src
), other
, pos
),
7554 GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
7555 ? GET_MODE_MASK (mode
)
7556 : ((unsigned HOST_WIDE_INT
) 1 << len
) - 1,
7559 return gen_rtx_combine (SET
, VOIDmode
, assign
, src
);
7562 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7566 apply_distributive_law (x
)
7569 enum rtx_code code
= GET_CODE (x
);
7570 rtx lhs
, rhs
, other
;
7572 enum rtx_code inner_code
;
7574 /* Distributivity is not true for floating point.
7575 It can change the value. So don't do it.
7576 -- rms and moshier@world.std.com. */
7577 if (FLOAT_MODE_P (GET_MODE (x
)))
7580 /* The outer operation can only be one of the following: */
7581 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
7582 && code
!= PLUS
&& code
!= MINUS
)
7585 lhs
= XEXP (x
, 0), rhs
= XEXP (x
, 1);
7587 /* If either operand is a primitive we can't do anything, so get out
7589 if (GET_RTX_CLASS (GET_CODE (lhs
)) == 'o'
7590 || GET_RTX_CLASS (GET_CODE (rhs
)) == 'o')
7593 lhs
= expand_compound_operation (lhs
);
7594 rhs
= expand_compound_operation (rhs
);
7595 inner_code
= GET_CODE (lhs
);
7596 if (inner_code
!= GET_CODE (rhs
))
7599 /* See if the inner and outer operations distribute. */
7606 /* These all distribute except over PLUS. */
7607 if (code
== PLUS
|| code
== MINUS
)
7612 if (code
!= PLUS
&& code
!= MINUS
)
7617 /* This is also a multiply, so it distributes over everything. */
7621 /* Non-paradoxical SUBREGs distributes over all operations, provided
7622 the inner modes and word numbers are the same, this is an extraction
7623 of a low-order part, we don't convert an fp operation to int or
7624 vice versa, and we would not be converting a single-word
7625 operation into a multi-word operation. The latter test is not
7626 required, but it prevents generating unneeded multi-word operations.
7627 Some of the previous tests are redundant given the latter test, but
7628 are retained because they are required for correctness.
7630 We produce the result slightly differently in this case. */
7632 if (GET_MODE (SUBREG_REG (lhs
)) != GET_MODE (SUBREG_REG (rhs
))
7633 || SUBREG_WORD (lhs
) != SUBREG_WORD (rhs
)
7634 || ! subreg_lowpart_p (lhs
)
7635 || (GET_MODE_CLASS (GET_MODE (lhs
))
7636 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs
))))
7637 || (GET_MODE_SIZE (GET_MODE (lhs
))
7638 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))))
7639 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs
))) > UNITS_PER_WORD
)
7642 tem
= gen_binary (code
, GET_MODE (SUBREG_REG (lhs
)),
7643 SUBREG_REG (lhs
), SUBREG_REG (rhs
));
7644 return gen_lowpart_for_combine (GET_MODE (x
), tem
);
7650 /* Set LHS and RHS to the inner operands (A and B in the example
7651 above) and set OTHER to the common operand (C in the example).
7652 These is only one way to do this unless the inner operation is
7654 if (GET_RTX_CLASS (inner_code
) == 'c'
7655 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
7656 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
7657 else if (GET_RTX_CLASS (inner_code
) == 'c'
7658 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
7659 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
7660 else if (GET_RTX_CLASS (inner_code
) == 'c'
7661 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
7662 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
7663 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
7664 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
7668 /* Form the new inner operation, seeing if it simplifies first. */
7669 tem
= gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
7671 /* There is one exception to the general way of distributing:
7672 (a ^ b) | (a ^ c) -> (~a) & (b ^ c) */
7673 if (code
== XOR
&& inner_code
== IOR
)
7676 other
= gen_unary (NOT
, GET_MODE (x
), GET_MODE (x
), other
);
7679 /* We may be able to continuing distributing the result, so call
7680 ourselves recursively on the inner operation before forming the
7681 outer operation, which we return. */
7682 return gen_binary (inner_code
, GET_MODE (x
),
7683 apply_distributive_law (tem
), other
);
7686 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7689 Return an equivalent form, if different from X. Otherwise, return X. If
7690 X is zero, we are to always construct the equivalent form. */
7693 simplify_and_const_int (x
, mode
, varop
, constop
)
7695 enum machine_mode mode
;
7697 unsigned HOST_WIDE_INT constop
;
7699 unsigned HOST_WIDE_INT nonzero
;
7702 /* Simplify VAROP knowing that we will be only looking at some of the
7704 varop
= force_to_mode (varop
, mode
, constop
, NULL_RTX
, 0);
7706 /* If VAROP is a CLOBBER, we will fail so return it; if it is a
7707 CONST_INT, we are done. */
7708 if (GET_CODE (varop
) == CLOBBER
|| GET_CODE (varop
) == CONST_INT
)
7711 /* See what bits may be nonzero in VAROP. Unlike the general case of
7712 a call to nonzero_bits, here we don't care about bits outside
7715 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
7716 nonzero
= trunc_int_for_mode (nonzero
, mode
);
7718 /* Turn off all bits in the constant that are known to already be zero.
7719 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7720 which is tested below. */
7724 /* If we don't have any bits left, return zero. */
7728 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7729 a power of two, we can replace this with a ASHIFT. */
7730 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
7731 && (i
= exact_log2 (constop
)) >= 0)
7732 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
7734 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7735 or XOR, then try to apply the distributive law. This may eliminate
7736 operations if either branch can be simplified because of the AND.
7737 It may also make some cases more complex, but those cases probably
7738 won't match a pattern either with or without this. */
7740 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
7742 gen_lowpart_for_combine
7744 apply_distributive_law
7745 (gen_binary (GET_CODE (varop
), GET_MODE (varop
),
7746 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7747 XEXP (varop
, 0), constop
),
7748 simplify_and_const_int (NULL_RTX
, GET_MODE (varop
),
7749 XEXP (varop
, 1), constop
))));
7751 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7752 if we already had one (just check for the simplest cases). */
7753 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
7754 && GET_MODE (XEXP (x
, 0)) == mode
7755 && SUBREG_REG (XEXP (x
, 0)) == varop
)
7756 varop
= XEXP (x
, 0);
7758 varop
= gen_lowpart_for_combine (mode
, varop
);
7760 /* If we can't make the SUBREG, try to return what we were given. */
7761 if (GET_CODE (varop
) == CLOBBER
)
7762 return x
? x
: varop
;
7764 /* If we are only masking insignificant bits, return VAROP. */
7765 if (constop
== nonzero
)
7768 /* Otherwise, return an AND. See how much, if any, of X we can use. */
7769 else if (x
== 0 || GET_CODE (x
) != AND
|| GET_MODE (x
) != mode
)
7770 x
= gen_binary (AND
, mode
, varop
, GEN_INT (constop
));
7774 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
7775 || (unsigned HOST_WIDE_INT
) INTVAL (XEXP (x
, 1)) != constop
)
7776 SUBST (XEXP (x
, 1), GEN_INT (constop
));
7778 SUBST (XEXP (x
, 0), varop
);
7784 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
7785 We don't let nonzero_bits recur into num_sign_bit_copies, because that
7786 is less useful. We can't allow both, because that results in exponential
7787 run time recursion. There is a nullstone testcase that triggered
7788 this. This macro avoids accidental uses of num_sign_bit_copies. */
7789 #define num_sign_bit_copies()
7791 /* Given an expression, X, compute which bits in X can be non-zero.
7792 We don't care about bits outside of those defined in MODE.
7794 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7795 a shift, AND, or zero_extract, we can do better. */
7797 static unsigned HOST_WIDE_INT
7798 nonzero_bits (x
, mode
)
7800 enum machine_mode mode
;
7802 unsigned HOST_WIDE_INT nonzero
= GET_MODE_MASK (mode
);
7803 unsigned HOST_WIDE_INT inner_nz
;
7805 int mode_width
= GET_MODE_BITSIZE (mode
);
7808 /* For floating-point values, assume all bits are needed. */
7809 if (FLOAT_MODE_P (GET_MODE (x
)) || FLOAT_MODE_P (mode
))
7812 /* If X is wider than MODE, use its mode instead. */
7813 if (GET_MODE_BITSIZE (GET_MODE (x
)) > mode_width
)
7815 mode
= GET_MODE (x
);
7816 nonzero
= GET_MODE_MASK (mode
);
7817 mode_width
= GET_MODE_BITSIZE (mode
);
7820 if (mode_width
> HOST_BITS_PER_WIDE_INT
)
7821 /* Our only callers in this case look for single bit values. So
7822 just return the mode mask. Those tests will then be false. */
7825 #ifndef WORD_REGISTER_OPERATIONS
7826 /* If MODE is wider than X, but both are a single word for both the host
7827 and target machines, we can compute this from which bits of the
7828 object might be nonzero in its own mode, taking into account the fact
7829 that on many CISC machines, accessing an object in a wider mode
7830 causes the high-order bits to become undefined. So they are
7831 not known to be zero. */
7833 if (GET_MODE (x
) != VOIDmode
&& GET_MODE (x
) != mode
7834 && GET_MODE_BITSIZE (GET_MODE (x
)) <= BITS_PER_WORD
7835 && GET_MODE_BITSIZE (GET_MODE (x
)) <= HOST_BITS_PER_WIDE_INT
7836 && GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (GET_MODE (x
)))
7838 nonzero
&= nonzero_bits (x
, GET_MODE (x
));
7839 nonzero
|= GET_MODE_MASK (mode
) & ~ GET_MODE_MASK (GET_MODE (x
));
7844 code
= GET_CODE (x
);
7848 #ifdef POINTERS_EXTEND_UNSIGNED
7849 /* If pointers extend unsigned and this is a pointer in Pmode, say that
7850 all the bits above ptr_mode are known to be zero. */
7851 if (POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
7852 && REGNO_POINTER_FLAG (REGNO (x
)))
7853 nonzero
&= GET_MODE_MASK (ptr_mode
);
7856 #ifdef STACK_BOUNDARY
7857 /* If this is the stack pointer, we may know something about its
7858 alignment. If PUSH_ROUNDING is defined, it is possible for the
7859 stack to be momentarily aligned only to that amount, so we pick
7860 the least alignment. */
7862 /* We can't check for arg_pointer_rtx here, because it is not
7863 guaranteed to have as much alignment as the stack pointer.
7864 In particular, in the Irix6 n64 ABI, the stack has 128 bit
7865 alignment but the argument pointer has only 64 bit alignment. */
7867 if ((x
== frame_pointer_rtx
7868 || x
== stack_pointer_rtx
7869 || x
== hard_frame_pointer_rtx
7870 || (REGNO (x
) >= FIRST_VIRTUAL_REGISTER
7871 && REGNO (x
) <= LAST_VIRTUAL_REGISTER
))
7877 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
7879 #ifdef PUSH_ROUNDING
7880 if (REGNO (x
) == STACK_POINTER_REGNUM
)
7881 sp_alignment
= MIN (PUSH_ROUNDING (1), sp_alignment
);
7884 /* We must return here, otherwise we may get a worse result from
7885 one of the choices below. There is nothing useful below as
7886 far as the stack pointer is concerned. */
7887 return nonzero
&= ~ (sp_alignment
- 1);
7891 /* If X is a register whose nonzero bits value is current, use it.
7892 Otherwise, if X is a register whose value we can find, use that
7893 value. Otherwise, use the previously-computed global nonzero bits
7894 for this register. */
7896 if (reg_last_set_value
[REGNO (x
)] != 0
7897 && reg_last_set_mode
[REGNO (x
)] == mode
7898 && (reg_last_set_label
[REGNO (x
)] == label_tick
7899 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
7900 && REG_N_SETS (REGNO (x
)) == 1
7901 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
7903 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
7904 return reg_last_set_nonzero_bits
[REGNO (x
)];
7906 tem
= get_last_value (x
);
7910 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7911 /* If X is narrower than MODE and TEM is a non-negative
7912 constant that would appear negative in the mode of X,
7913 sign-extend it for use in reg_nonzero_bits because some
7914 machines (maybe most) will actually do the sign-extension
7915 and this is the conservative approach.
7917 ??? For 2.5, try to tighten up the MD files in this regard
7918 instead of this kludge. */
7920 if (GET_MODE_BITSIZE (GET_MODE (x
)) < mode_width
7921 && GET_CODE (tem
) == CONST_INT
7923 && 0 != (INTVAL (tem
)
7924 & ((HOST_WIDE_INT
) 1
7925 << (GET_MODE_BITSIZE (GET_MODE (x
)) - 1))))
7926 tem
= GEN_INT (INTVAL (tem
)
7927 | ((HOST_WIDE_INT
) (-1)
7928 << GET_MODE_BITSIZE (GET_MODE (x
))));
7930 return nonzero_bits (tem
, mode
);
7932 else if (nonzero_sign_valid
&& reg_nonzero_bits
[REGNO (x
)])
7933 return reg_nonzero_bits
[REGNO (x
)] & nonzero
;
7938 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
7939 /* If X is negative in MODE, sign-extend the value. */
7940 if (INTVAL (x
) > 0 && mode_width
< BITS_PER_WORD
7941 && 0 != (INTVAL (x
) & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))))
7942 return (INTVAL (x
) | ((HOST_WIDE_INT
) (-1) << mode_width
));
7948 #ifdef LOAD_EXTEND_OP
7949 /* In many, if not most, RISC machines, reading a byte from memory
7950 zeros the rest of the register. Noticing that fact saves a lot
7951 of extra zero-extends. */
7952 if (LOAD_EXTEND_OP (GET_MODE (x
)) == ZERO_EXTEND
)
7953 nonzero
&= GET_MODE_MASK (GET_MODE (x
));
7963 /* If this produces an integer result, we know which bits are set.
7964 Code here used to clear bits outside the mode of X, but that is
7967 if (GET_MODE_CLASS (mode
) == MODE_INT
7968 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7969 nonzero
= STORE_FLAG_VALUE
;
7974 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7975 and num_sign_bit_copies. */
7976 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
7977 == GET_MODE_BITSIZE (GET_MODE (x
)))
7981 if (GET_MODE_SIZE (GET_MODE (x
)) < mode_width
)
7982 nonzero
|= (GET_MODE_MASK (mode
) & ~ GET_MODE_MASK (GET_MODE (x
)));
7987 /* Disabled to avoid exponential mutual recursion between nonzero_bits
7988 and num_sign_bit_copies. */
7989 if (num_sign_bit_copies (XEXP (x
, 0), GET_MODE (x
))
7990 == GET_MODE_BITSIZE (GET_MODE (x
)))
7996 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
) & GET_MODE_MASK (mode
));
8000 nonzero
&= nonzero_bits (XEXP (x
, 0), mode
);
8001 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8002 nonzero
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8006 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
8007 Otherwise, show all the bits in the outer mode but not the inner
8009 inner_nz
= nonzero_bits (XEXP (x
, 0), mode
);
8010 if (GET_MODE (XEXP (x
, 0)) != VOIDmode
)
8012 inner_nz
&= GET_MODE_MASK (GET_MODE (XEXP (x
, 0)));
8014 & (((HOST_WIDE_INT
) 1
8015 << (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0))) - 1))))
8016 inner_nz
|= (GET_MODE_MASK (mode
)
8017 & ~ GET_MODE_MASK (GET_MODE (XEXP (x
, 0))));
8020 nonzero
&= inner_nz
;
8024 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8025 & nonzero_bits (XEXP (x
, 1), mode
));
8029 case UMIN
: case UMAX
: case SMIN
: case SMAX
:
8030 nonzero
&= (nonzero_bits (XEXP (x
, 0), mode
)
8031 | nonzero_bits (XEXP (x
, 1), mode
));
8034 case PLUS
: case MINUS
:
8036 case DIV
: case UDIV
:
8037 case MOD
: case UMOD
:
8038 /* We can apply the rules of arithmetic to compute the number of
8039 high- and low-order zero bits of these operations. We start by
8040 computing the width (position of the highest-order non-zero bit)
8041 and the number of low-order zero bits for each value. */
8043 unsigned HOST_WIDE_INT nz0
= nonzero_bits (XEXP (x
, 0), mode
);
8044 unsigned HOST_WIDE_INT nz1
= nonzero_bits (XEXP (x
, 1), mode
);
8045 int width0
= floor_log2 (nz0
) + 1;
8046 int width1
= floor_log2 (nz1
) + 1;
8047 int low0
= floor_log2 (nz0
& -nz0
);
8048 int low1
= floor_log2 (nz1
& -nz1
);
8049 HOST_WIDE_INT op0_maybe_minusp
8050 = (nz0
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8051 HOST_WIDE_INT op1_maybe_minusp
8052 = (nz1
& ((HOST_WIDE_INT
) 1 << (mode_width
- 1)));
8053 int result_width
= mode_width
;
8061 && (XEXP (x
, 0) == stack_pointer_rtx
8062 || XEXP (x
, 0) == frame_pointer_rtx
)
8063 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8065 int sp_alignment
= STACK_BOUNDARY
/ BITS_PER_UNIT
;
8067 nz0
= (GET_MODE_MASK (mode
) & ~ (sp_alignment
- 1));
8068 nz1
= INTVAL (XEXP (x
, 1)) - STACK_BIAS
;
8069 width0
= floor_log2 (nz0
) + 1;
8070 width1
= floor_log2 (nz1
) + 1;
8071 low0
= floor_log2 (nz0
& -nz0
);
8072 low1
= floor_log2 (nz1
& -nz1
);
8075 result_width
= MAX (width0
, width1
) + 1;
8076 result_low
= MIN (low0
, low1
);
8079 result_low
= MIN (low0
, low1
);
8082 result_width
= width0
+ width1
;
8083 result_low
= low0
+ low1
;
8086 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8087 result_width
= width0
;
8090 result_width
= width0
;
8093 if (! op0_maybe_minusp
&& ! op1_maybe_minusp
)
8094 result_width
= MIN (width0
, width1
);
8095 result_low
= MIN (low0
, low1
);
8098 result_width
= MIN (width0
, width1
);
8099 result_low
= MIN (low0
, low1
);
8105 if (result_width
< mode_width
)
8106 nonzero
&= ((HOST_WIDE_INT
) 1 << result_width
) - 1;
8109 nonzero
&= ~ (((HOST_WIDE_INT
) 1 << result_low
) - 1);
8114 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8115 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8116 nonzero
&= ((HOST_WIDE_INT
) 1 << INTVAL (XEXP (x
, 1))) - 1;
8120 /* If this is a SUBREG formed for a promoted variable that has
8121 been zero-extended, we know that at least the high-order bits
8122 are zero, though others might be too. */
8124 if (SUBREG_PROMOTED_VAR_P (x
) && SUBREG_PROMOTED_UNSIGNED_P (x
))
8125 nonzero
= (GET_MODE_MASK (GET_MODE (x
))
8126 & nonzero_bits (SUBREG_REG (x
), GET_MODE (x
)));
8128 /* If the inner mode is a single word for both the host and target
8129 machines, we can compute this from which bits of the inner
8130 object might be nonzero. */
8131 if (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) <= BITS_PER_WORD
8132 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8133 <= HOST_BITS_PER_WIDE_INT
))
8135 nonzero
&= nonzero_bits (SUBREG_REG (x
), mode
);
8137 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP)
8138 /* If this is a typical RISC machine, we only have to worry
8139 about the way loads are extended. */
8140 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
8142 & (((unsigned HOST_WIDE_INT
) 1
8143 << (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))) - 1))))
8145 : LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) != ZERO_EXTEND
)
8148 /* On many CISC machines, accessing an object in a wider mode
8149 causes the high-order bits to become undefined. So they are
8150 not known to be zero. */
8151 if (GET_MODE_SIZE (GET_MODE (x
))
8152 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8153 nonzero
|= (GET_MODE_MASK (GET_MODE (x
))
8154 & ~ GET_MODE_MASK (GET_MODE (SUBREG_REG (x
))));
8163 /* The nonzero bits are in two classes: any bits within MODE
8164 that aren't in GET_MODE (x) are always significant. The rest of the
8165 nonzero bits are those that are significant in the operand of
8166 the shift when shifted the appropriate number of bits. This
8167 shows that high-order bits are cleared by the right shift and
8168 low-order bits by left shifts. */
8169 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8170 && INTVAL (XEXP (x
, 1)) >= 0
8171 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8173 enum machine_mode inner_mode
= GET_MODE (x
);
8174 int width
= GET_MODE_BITSIZE (inner_mode
);
8175 int count
= INTVAL (XEXP (x
, 1));
8176 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (inner_mode
);
8177 unsigned HOST_WIDE_INT op_nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8178 unsigned HOST_WIDE_INT inner
= op_nonzero
& mode_mask
;
8179 unsigned HOST_WIDE_INT outer
= 0;
8181 if (mode_width
> width
)
8182 outer
= (op_nonzero
& nonzero
& ~ mode_mask
);
8184 if (code
== LSHIFTRT
)
8186 else if (code
== ASHIFTRT
)
8190 /* If the sign bit may have been nonzero before the shift, we
8191 need to mark all the places it could have been copied to
8192 by the shift as possibly nonzero. */
8193 if (inner
& ((HOST_WIDE_INT
) 1 << (width
- 1 - count
)))
8194 inner
|= (((HOST_WIDE_INT
) 1 << count
) - 1) << (width
- count
);
8196 else if (code
== ASHIFT
)
8199 inner
= ((inner
<< (count
% width
)
8200 | (inner
>> (width
- (count
% width
)))) & mode_mask
);
8202 nonzero
&= (outer
| inner
);
8207 /* This is at most the number of bits in the mode. */
8208 nonzero
= ((HOST_WIDE_INT
) 1 << (floor_log2 (mode_width
) + 1)) - 1;
8212 nonzero
&= (nonzero_bits (XEXP (x
, 1), mode
)
8213 | nonzero_bits (XEXP (x
, 2), mode
));
8223 /* See the macro definition above. */
8224 #undef num_sign_bit_copies
8226 /* Return the number of bits at the high-order end of X that are known to
8227 be equal to the sign bit. X will be used in mode MODE; if MODE is
8228 VOIDmode, X will be used in its own mode. The returned value will always
8229 be between 1 and the number of bits in MODE. */
8232 num_sign_bit_copies (x
, mode
)
8234 enum machine_mode mode
;
8236 enum rtx_code code
= GET_CODE (x
);
8238 int num0
, num1
, result
;
8239 unsigned HOST_WIDE_INT nonzero
;
8242 /* If we weren't given a mode, use the mode of X. If the mode is still
8243 VOIDmode, we don't know anything. Likewise if one of the modes is
8246 if (mode
== VOIDmode
)
8247 mode
= GET_MODE (x
);
8249 if (mode
== VOIDmode
|| FLOAT_MODE_P (mode
) || FLOAT_MODE_P (GET_MODE (x
)))
8252 bitwidth
= GET_MODE_BITSIZE (mode
);
8254 /* For a smaller object, just ignore the high bits. */
8255 if (bitwidth
< GET_MODE_BITSIZE (GET_MODE (x
)))
8256 return MAX (1, (num_sign_bit_copies (x
, GET_MODE (x
))
8257 - (GET_MODE_BITSIZE (GET_MODE (x
)) - bitwidth
)));
8259 if (GET_MODE (x
) != VOIDmode
&& bitwidth
> GET_MODE_BITSIZE (GET_MODE (x
)))
8261 #ifndef WORD_REGISTER_OPERATIONS
8262 /* If this machine does not do all register operations on the entire
8263 register and MODE is wider than the mode of X, we can say nothing
8264 at all about the high-order bits. */
8267 /* Likewise on machines that do, if the mode of the object is smaller
8268 than a word and loads of that size don't sign extend, we can say
8269 nothing about the high order bits. */
8270 if (GET_MODE_BITSIZE (GET_MODE (x
)) < BITS_PER_WORD
8271 #ifdef LOAD_EXTEND_OP
8272 && LOAD_EXTEND_OP (GET_MODE (x
)) != SIGN_EXTEND
8283 #ifdef POINTERS_EXTEND_UNSIGNED
8284 /* If pointers extend signed and this is a pointer in Pmode, say that
8285 all the bits above ptr_mode are known to be sign bit copies. */
8286 if (! POINTERS_EXTEND_UNSIGNED
&& GET_MODE (x
) == Pmode
&& mode
== Pmode
8287 && REGNO_POINTER_FLAG (REGNO (x
)))
8288 return GET_MODE_BITSIZE (Pmode
) - GET_MODE_BITSIZE (ptr_mode
) + 1;
8291 if (reg_last_set_value
[REGNO (x
)] != 0
8292 && reg_last_set_mode
[REGNO (x
)] == mode
8293 && (reg_last_set_label
[REGNO (x
)] == label_tick
8294 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
8295 && REG_N_SETS (REGNO (x
)) == 1
8296 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
,
8298 && INSN_CUID (reg_last_set
[REGNO (x
)]) < subst_low_cuid
)
8299 return reg_last_set_sign_bit_copies
[REGNO (x
)];
8301 tem
= get_last_value (x
);
8303 return num_sign_bit_copies (tem
, mode
);
8305 if (nonzero_sign_valid
&& reg_sign_bit_copies
[REGNO (x
)] != 0)
8306 return reg_sign_bit_copies
[REGNO (x
)];
8310 #ifdef LOAD_EXTEND_OP
8311 /* Some RISC machines sign-extend all loads of smaller than a word. */
8312 if (LOAD_EXTEND_OP (GET_MODE (x
)) == SIGN_EXTEND
)
8313 return MAX (1, bitwidth
- GET_MODE_BITSIZE (GET_MODE (x
)) + 1);
8318 /* If the constant is negative, take its 1's complement and remask.
8319 Then see how many zero bits we have. */
8320 nonzero
= INTVAL (x
) & GET_MODE_MASK (mode
);
8321 if (bitwidth
<= HOST_BITS_PER_WIDE_INT
8322 && (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8323 nonzero
= (~ nonzero
) & GET_MODE_MASK (mode
);
8325 return (nonzero
== 0 ? bitwidth
: bitwidth
- floor_log2 (nonzero
) - 1);
8328 /* If this is a SUBREG for a promoted object that is sign-extended
8329 and we are looking at it in a wider mode, we know that at least the
8330 high-order bits are known to be sign bit copies. */
8332 if (SUBREG_PROMOTED_VAR_P (x
) && ! SUBREG_PROMOTED_UNSIGNED_P (x
))
8333 return MAX (bitwidth
- GET_MODE_BITSIZE (GET_MODE (x
)) + 1,
8334 num_sign_bit_copies (SUBREG_REG (x
), mode
));
8336 /* For a smaller object, just ignore the high bits. */
8337 if (bitwidth
<= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
))))
8339 num0
= num_sign_bit_copies (SUBREG_REG (x
), VOIDmode
);
8340 return MAX (1, (num0
8341 - (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (x
)))
8345 #ifdef WORD_REGISTER_OPERATIONS
8346 #ifdef LOAD_EXTEND_OP
8347 /* For paradoxical SUBREGs on machines where all register operations
8348 affect the entire register, just look inside. Note that we are
8349 passing MODE to the recursive call, so the number of sign bit copies
8350 will remain relative to that mode, not the inner mode. */
8352 /* This works only if loads sign extend. Otherwise, if we get a
8353 reload for the inner part, it may be loaded from the stack, and
8354 then we lose all sign bit copies that existed before the store
8357 if ((GET_MODE_SIZE (GET_MODE (x
))
8358 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8359 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x
))) == SIGN_EXTEND
)
8360 return num_sign_bit_copies (SUBREG_REG (x
), mode
);
8366 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
8367 return MAX (1, bitwidth
- INTVAL (XEXP (x
, 1)));
8371 return (bitwidth
- GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8372 + num_sign_bit_copies (XEXP (x
, 0), VOIDmode
));
8375 /* For a smaller object, just ignore the high bits. */
8376 num0
= num_sign_bit_copies (XEXP (x
, 0), VOIDmode
);
8377 return MAX (1, (num0
- (GET_MODE_BITSIZE (GET_MODE (XEXP (x
, 0)))
8381 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8383 case ROTATE
: case ROTATERT
:
8384 /* If we are rotating left by a number of bits less than the number
8385 of sign bit copies, we can just subtract that amount from the
8387 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8388 && INTVAL (XEXP (x
, 1)) >= 0 && INTVAL (XEXP (x
, 1)) < bitwidth
)
8390 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8391 return MAX (1, num0
- (code
== ROTATE
? INTVAL (XEXP (x
, 1))
8392 : bitwidth
- INTVAL (XEXP (x
, 1))));
8397 /* In general, this subtracts one sign bit copy. But if the value
8398 is known to be positive, the number of sign bit copies is the
8399 same as that of the input. Finally, if the input has just one bit
8400 that might be nonzero, all the bits are copies of the sign bit. */
8401 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8402 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8403 return num0
> 1 ? num0
- 1 : 1;
8405 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8410 && (((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
))
8415 case IOR
: case AND
: case XOR
:
8416 case SMIN
: case SMAX
: case UMIN
: case UMAX
:
8417 /* Logical operations will preserve the number of sign-bit copies.
8418 MIN and MAX operations always return one of the operands. */
8419 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8420 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8421 return MIN (num0
, num1
);
8423 case PLUS
: case MINUS
:
8424 /* For addition and subtraction, we can have a 1-bit carry. However,
8425 if we are subtracting 1 from a positive number, there will not
8426 be such a carry. Furthermore, if the positive number is known to
8427 be 0 or 1, we know the result is either -1 or 0. */
8429 if (code
== PLUS
&& XEXP (x
, 1) == constm1_rtx
8430 && bitwidth
<= HOST_BITS_PER_WIDE_INT
)
8432 nonzero
= nonzero_bits (XEXP (x
, 0), mode
);
8433 if ((((HOST_WIDE_INT
) 1 << (bitwidth
- 1)) & nonzero
) == 0)
8434 return (nonzero
== 1 || nonzero
== 0 ? bitwidth
8435 : bitwidth
- floor_log2 (nonzero
) - 1);
8438 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8439 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8440 return MAX (1, MIN (num0
, num1
) - 1);
8443 /* The number of bits of the product is the sum of the number of
8444 bits of both terms. However, unless one of the terms if known
8445 to be positive, we must allow for an additional bit since negating
8446 a negative number can remove one sign bit copy. */
8448 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8449 num1
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8451 result
= bitwidth
- (bitwidth
- num0
) - (bitwidth
- num1
);
8453 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8454 || (((nonzero_bits (XEXP (x
, 0), mode
)
8455 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8456 && ((nonzero_bits (XEXP (x
, 1), mode
)
8457 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))))
8460 return MAX (1, result
);
8463 /* The result must be <= the first operand. If the first operand
8464 has the high bit set, we know nothing about the number of sign
8466 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8468 else if ((nonzero_bits (XEXP (x
, 0), mode
)
8469 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0)
8472 return num_sign_bit_copies (XEXP (x
, 0), mode
);
8475 /* The result must be <= the scond operand. */
8476 return num_sign_bit_copies (XEXP (x
, 1), mode
);
8479 /* Similar to unsigned division, except that we have to worry about
8480 the case where the divisor is negative, in which case we have
8482 result
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8484 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8485 || (nonzero_bits (XEXP (x
, 1), mode
)
8486 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8492 result
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8494 && (bitwidth
> HOST_BITS_PER_WIDE_INT
8495 || (nonzero_bits (XEXP (x
, 1), mode
)
8496 & ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))) != 0))
8502 /* Shifts by a constant add to the number of bits equal to the
8504 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8505 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
8506 && INTVAL (XEXP (x
, 1)) > 0)
8507 num0
= MIN (bitwidth
, num0
+ INTVAL (XEXP (x
, 1)));
8512 /* Left shifts destroy copies. */
8513 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
8514 || INTVAL (XEXP (x
, 1)) < 0
8515 || INTVAL (XEXP (x
, 1)) >= bitwidth
)
8518 num0
= num_sign_bit_copies (XEXP (x
, 0), mode
);
8519 return MAX (1, num0
- INTVAL (XEXP (x
, 1)));
8522 num0
= num_sign_bit_copies (XEXP (x
, 1), mode
);
8523 num1
= num_sign_bit_copies (XEXP (x
, 2), mode
);
8524 return MIN (num0
, num1
);
8526 case EQ
: case NE
: case GE
: case GT
: case LE
: case LT
:
8527 case GEU
: case GTU
: case LEU
: case LTU
:
8528 if (STORE_FLAG_VALUE
== -1)
8536 /* If we haven't been able to figure it out by one of the above rules,
8537 see if some of the high-order bits are known to be zero. If so,
8538 count those bits and return one less than that amount. If we can't
8539 safely compute the mask for this mode, always return BITWIDTH. */
8541 if (bitwidth
> HOST_BITS_PER_WIDE_INT
)
8544 nonzero
= nonzero_bits (x
, mode
);
8545 return (nonzero
& ((HOST_WIDE_INT
) 1 << (bitwidth
- 1))
8546 ? 1 : bitwidth
- floor_log2 (nonzero
) - 1);
8549 /* Return the number of "extended" bits there are in X, when interpreted
8550 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8551 unsigned quantities, this is the number of high-order zero bits.
8552 For signed quantities, this is the number of copies of the sign bit
8553 minus 1. In both case, this function returns the number of "spare"
8554 bits. For example, if two quantities for which this function returns
8555 at least 1 are added, the addition is known not to overflow.
8557 This function will always return 0 unless called during combine, which
8558 implies that it must be called from a define_split. */
8561 extended_count (x
, mode
, unsignedp
)
8563 enum machine_mode mode
;
8566 if (nonzero_sign_valid
== 0)
8570 ? (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
8571 && (GET_MODE_BITSIZE (mode
) - 1
8572 - floor_log2 (nonzero_bits (x
, mode
))))
8573 : num_sign_bit_copies (x
, mode
) - 1);
8576 /* This function is called from `simplify_shift_const' to merge two
8577 outer operations. Specifically, we have already found that we need
8578 to perform operation *POP0 with constant *PCONST0 at the outermost
8579 position. We would now like to also perform OP1 with constant CONST1
8580 (with *POP0 being done last).
8582 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8583 the resulting operation. *PCOMP_P is set to 1 if we would need to
8584 complement the innermost operand, otherwise it is unchanged.
8586 MODE is the mode in which the operation will be done. No bits outside
8587 the width of this mode matter. It is assumed that the width of this mode
8588 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8590 If *POP0 or OP1 are NIL, it means no operation is required. Only NEG, PLUS,
8591 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8592 result is simply *PCONST0.
8594 If the resulting operation cannot be expressed as one operation, we
8595 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8598 merge_outer_ops (pop0
, pconst0
, op1
, const1
, mode
, pcomp_p
)
8599 enum rtx_code
*pop0
;
8600 HOST_WIDE_INT
*pconst0
;
8602 HOST_WIDE_INT const1
;
8603 enum machine_mode mode
;
8606 enum rtx_code op0
= *pop0
;
8607 HOST_WIDE_INT const0
= *pconst0
;
8609 const0
&= GET_MODE_MASK (mode
);
8610 const1
&= GET_MODE_MASK (mode
);
8612 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8616 /* If OP0 or OP1 is NIL, this is easy. Similarly if they are the same or
8619 if (op1
== NIL
|| op0
== SET
)
8622 else if (op0
== NIL
)
8623 op0
= op1
, const0
= const1
;
8625 else if (op0
== op1
)
8649 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8650 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
8653 /* If the two constants aren't the same, we can't do anything. The
8654 remaining six cases can all be done. */
8655 else if (const0
!= const1
)
8663 /* (a & b) | b == b */
8665 else /* op1 == XOR */
8666 /* (a ^ b) | b == a | b */
8672 /* (a & b) ^ b == (~a) & b */
8673 op0
= AND
, *pcomp_p
= 1;
8674 else /* op1 == IOR */
8675 /* (a | b) ^ b == a & ~b */
8676 op0
= AND
, *pconst0
= ~ const0
;
8681 /* (a | b) & b == b */
8683 else /* op1 == XOR */
8684 /* (a ^ b) & b) == (~a) & b */
8691 /* Check for NO-OP cases. */
8692 const0
&= GET_MODE_MASK (mode
);
8694 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
8696 else if (const0
== 0 && op0
== AND
)
8698 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
8702 /* ??? Slightly redundant with the above mask, but not entirely.
8703 Moving this above means we'd have to sign-extend the mode mask
8704 for the final test. */
8705 const0
= trunc_int_for_mode (const0
, mode
);
8713 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8714 The result of the shift is RESULT_MODE. X, if non-zero, is an expression
8715 that we started with.
8717 The shift is normally computed in the widest mode we find in VAROP, as
8718 long as it isn't a different number of words than RESULT_MODE. Exceptions
8719 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8722 simplify_shift_const (x
, code
, result_mode
, varop
, count
)
8725 enum machine_mode result_mode
;
8729 enum rtx_code orig_code
= code
;
8730 int orig_count
= count
;
8731 enum machine_mode mode
= result_mode
;
8732 enum machine_mode shift_mode
, tmode
;
8734 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
8735 /* We form (outer_op (code varop count) (outer_const)). */
8736 enum rtx_code outer_op
= NIL
;
8737 HOST_WIDE_INT outer_const
= 0;
8739 int complement_p
= 0;
8742 /* If we were given an invalid count, don't do anything except exactly
8743 what was requested. */
8745 if (count
< 0 || count
> GET_MODE_BITSIZE (mode
))
8750 return gen_rtx_fmt_ee (code
, mode
, varop
, GEN_INT (count
));
8753 /* Unless one of the branches of the `if' in this loop does a `continue',
8754 we will `break' the loop after the `if'. */
8758 /* If we have an operand of (clobber (const_int 0)), just return that
8760 if (GET_CODE (varop
) == CLOBBER
)
8763 /* If we discovered we had to complement VAROP, leave. Making a NOT
8764 here would cause an infinite loop. */
8768 /* Convert ROTATERT to ROTATE. */
8769 if (code
== ROTATERT
)
8770 code
= ROTATE
, count
= GET_MODE_BITSIZE (result_mode
) - count
;
8772 /* We need to determine what mode we will do the shift in. If the
8773 shift is a right shift or a ROTATE, we must always do it in the mode
8774 it was originally done in. Otherwise, we can do it in MODE, the
8775 widest mode encountered. */
8777 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
8778 ? result_mode
: mode
);
8780 /* Handle cases where the count is greater than the size of the mode
8781 minus 1. For ASHIFT, use the size minus one as the count (this can
8782 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8783 take the count modulo the size. For other shifts, the result is
8786 Since these shifts are being produced by the compiler by combining
8787 multiple operations, each of which are defined, we know what the
8788 result is supposed to be. */
8790 if (count
> GET_MODE_BITSIZE (shift_mode
) - 1)
8792 if (code
== ASHIFTRT
)
8793 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8794 else if (code
== ROTATE
|| code
== ROTATERT
)
8795 count
%= GET_MODE_BITSIZE (shift_mode
);
8798 /* We can't simply return zero because there may be an
8806 /* Negative counts are invalid and should not have been made (a
8807 programmer-specified negative count should have been handled
8812 /* An arithmetic right shift of a quantity known to be -1 or 0
8814 if (code
== ASHIFTRT
8815 && (num_sign_bit_copies (varop
, shift_mode
)
8816 == GET_MODE_BITSIZE (shift_mode
)))
8822 /* If we are doing an arithmetic right shift and discarding all but
8823 the sign bit copies, this is equivalent to doing a shift by the
8824 bitsize minus one. Convert it into that shift because it will often
8825 allow other simplifications. */
8827 if (code
== ASHIFTRT
8828 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
8829 >= GET_MODE_BITSIZE (shift_mode
)))
8830 count
= GET_MODE_BITSIZE (shift_mode
) - 1;
8832 /* We simplify the tests below and elsewhere by converting
8833 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8834 `make_compound_operation' will convert it to a ASHIFTRT for
8835 those machines (such as Vax) that don't have a LSHIFTRT. */
8836 if (GET_MODE_BITSIZE (shift_mode
) <= HOST_BITS_PER_WIDE_INT
8838 && ((nonzero_bits (varop
, shift_mode
)
8839 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (shift_mode
) - 1)))
8843 switch (GET_CODE (varop
))
8849 new = expand_compound_operation (varop
);
8858 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8859 minus the width of a smaller mode, we can do this with a
8860 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8861 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8862 && ! mode_dependent_address_p (XEXP (varop
, 0))
8863 && ! MEM_VOLATILE_P (varop
)
8864 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8865 MODE_INT
, 1)) != BLKmode
)
8867 if (BYTES_BIG_ENDIAN
)
8868 new = gen_rtx_MEM (tmode
, XEXP (varop
, 0));
8870 new = gen_rtx_MEM (tmode
,
8871 plus_constant (XEXP (varop
, 0),
8872 count
/ BITS_PER_UNIT
));
8873 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (varop
);
8874 MEM_COPY_ATTRIBUTES (new, varop
);
8875 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
8876 : ZERO_EXTEND
, mode
, new);
8883 /* Similar to the case above, except that we can only do this if
8884 the resulting mode is the same as that of the underlying
8885 MEM and adjust the address depending on the *bits* endianness
8886 because of the way that bit-field extract insns are defined. */
8887 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
8888 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
8889 MODE_INT
, 1)) != BLKmode
8890 && tmode
== GET_MODE (XEXP (varop
, 0)))
8892 if (BITS_BIG_ENDIAN
)
8893 new = XEXP (varop
, 0);
8896 new = copy_rtx (XEXP (varop
, 0));
8897 SUBST (XEXP (new, 0),
8898 plus_constant (XEXP (new, 0),
8899 count
/ BITS_PER_UNIT
));
8902 varop
= gen_rtx_combine (code
== ASHIFTRT
? SIGN_EXTEND
8903 : ZERO_EXTEND
, mode
, new);
8910 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8911 the same number of words as what we've seen so far. Then store
8912 the widest mode in MODE. */
8913 if (subreg_lowpart_p (varop
)
8914 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8915 > GET_MODE_SIZE (GET_MODE (varop
)))
8916 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
8917 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
8920 varop
= SUBREG_REG (varop
);
8921 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
8922 mode
= GET_MODE (varop
);
8928 /* Some machines use MULT instead of ASHIFT because MULT
8929 is cheaper. But it is still better on those machines to
8930 merge two shifts into one. */
8931 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8932 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8934 varop
= gen_binary (ASHIFT
, GET_MODE (varop
), XEXP (varop
, 0),
8935 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
8941 /* Similar, for when divides are cheaper. */
8942 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8943 && exact_log2 (INTVAL (XEXP (varop
, 1))) >= 0)
8945 varop
= gen_binary (LSHIFTRT
, GET_MODE (varop
), XEXP (varop
, 0),
8946 GEN_INT (exact_log2 (INTVAL (XEXP (varop
, 1)))));
8952 /* If we are extracting just the sign bit of an arithmetic right
8953 shift, that shift is not needed. */
8954 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1)
8956 varop
= XEXP (varop
, 0);
8960 /* ... fall through ... */
8965 /* Here we have two nested shifts. The result is usually the
8966 AND of a new shift with a mask. We compute the result below. */
8967 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
8968 && INTVAL (XEXP (varop
, 1)) >= 0
8969 && INTVAL (XEXP (varop
, 1)) < GET_MODE_BITSIZE (GET_MODE (varop
))
8970 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
8971 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
8973 enum rtx_code first_code
= GET_CODE (varop
);
8974 int first_count
= INTVAL (XEXP (varop
, 1));
8975 unsigned HOST_WIDE_INT mask
;
8978 /* We have one common special case. We can't do any merging if
8979 the inner code is an ASHIFTRT of a smaller mode. However, if
8980 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8981 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8982 we can convert it to
8983 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8984 This simplifies certain SIGN_EXTEND operations. */
8985 if (code
== ASHIFT
&& first_code
== ASHIFTRT
8986 && (GET_MODE_BITSIZE (result_mode
)
8987 - GET_MODE_BITSIZE (GET_MODE (varop
))) == count
)
8989 /* C3 has the low-order C1 bits zero. */
8991 mask
= (GET_MODE_MASK (mode
)
8992 & ~ (((HOST_WIDE_INT
) 1 << first_count
) - 1));
8994 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
8995 XEXP (varop
, 0), mask
);
8996 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
8998 count
= first_count
;
9003 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
9004 than C1 high-order bits equal to the sign bit, we can convert
9005 this to either an ASHIFT or a ASHIFTRT depending on the
9008 We cannot do this if VAROP's mode is not SHIFT_MODE. */
9010 if (code
== ASHIFTRT
&& first_code
== ASHIFT
9011 && GET_MODE (varop
) == shift_mode
9012 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
9015 count
-= first_count
;
9017 count
= - count
, code
= ASHIFT
;
9018 varop
= XEXP (varop
, 0);
9022 /* There are some cases we can't do. If CODE is ASHIFTRT,
9023 we can only do this if FIRST_CODE is also ASHIFTRT.
9025 We can't do the case when CODE is ROTATE and FIRST_CODE is
9028 If the mode of this shift is not the mode of the outer shift,
9029 we can't do this if either shift is a right shift or ROTATE.
9031 Finally, we can't do any of these if the mode is too wide
9032 unless the codes are the same.
9034 Handle the case where the shift codes are the same
9037 if (code
== first_code
)
9039 if (GET_MODE (varop
) != result_mode
9040 && (code
== ASHIFTRT
|| code
== LSHIFTRT
9044 count
+= first_count
;
9045 varop
= XEXP (varop
, 0);
9049 if (code
== ASHIFTRT
9050 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
9051 || GET_MODE_BITSIZE (mode
) > HOST_BITS_PER_WIDE_INT
9052 || (GET_MODE (varop
) != result_mode
9053 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
9054 || first_code
== ROTATE
9055 || code
== ROTATE
)))
9058 /* To compute the mask to apply after the shift, shift the
9059 nonzero bits of the inner shift the same way the
9060 outer shift will. */
9062 mask_rtx
= GEN_INT (nonzero_bits (varop
, GET_MODE (varop
)));
9065 = simplify_binary_operation (code
, result_mode
, mask_rtx
,
9068 /* Give up if we can't compute an outer operation to use. */
9070 || GET_CODE (mask_rtx
) != CONST_INT
9071 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
9073 result_mode
, &complement_p
))
9076 /* If the shifts are in the same direction, we add the
9077 counts. Otherwise, we subtract them. */
9078 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9079 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
9080 count
+= first_count
;
9082 count
-= first_count
;
9084 /* If COUNT is positive, the new shift is usually CODE,
9085 except for the two exceptions below, in which case it is
9086 FIRST_CODE. If the count is negative, FIRST_CODE should
9089 && ((first_code
== ROTATE
&& code
== ASHIFT
)
9090 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
9093 code
= first_code
, count
= - count
;
9095 varop
= XEXP (varop
, 0);
9099 /* If we have (A << B << C) for any shift, we can convert this to
9100 (A << C << B). This wins if A is a constant. Only try this if
9101 B is not a constant. */
9103 else if (GET_CODE (varop
) == code
9104 && GET_CODE (XEXP (varop
, 1)) != CONST_INT
9106 = simplify_binary_operation (code
, mode
,
9110 varop
= gen_rtx_combine (code
, mode
, new, XEXP (varop
, 1));
9117 /* Make this fit the case below. */
9118 varop
= gen_rtx_combine (XOR
, mode
, XEXP (varop
, 0),
9119 GEN_INT (GET_MODE_MASK (mode
)));
9125 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
9126 with C the size of VAROP - 1 and the shift is logical if
9127 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9128 we have an (le X 0) operation. If we have an arithmetic shift
9129 and STORE_FLAG_VALUE is 1 or we have a logical shift with
9130 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
9132 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
9133 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
9134 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9135 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9136 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9137 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9140 varop
= gen_rtx_combine (LE
, GET_MODE (varop
), XEXP (varop
, 1),
9143 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9144 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
9149 /* If we have (shift (logical)), move the logical to the outside
9150 to allow it to possibly combine with another logical and the
9151 shift to combine with another shift. This also canonicalizes to
9152 what a ZERO_EXTRACT looks like. Also, some machines have
9153 (and (shift)) insns. */
9155 if (GET_CODE (XEXP (varop
, 1)) == CONST_INT
9156 && (new = simplify_binary_operation (code
, result_mode
,
9158 GEN_INT (count
))) != 0
9159 && GET_CODE(new) == CONST_INT
9160 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
9161 INTVAL (new), result_mode
, &complement_p
))
9163 varop
= XEXP (varop
, 0);
9167 /* If we can't do that, try to simplify the shift in each arm of the
9168 logical expression, make a new logical expression, and apply
9169 the inverse distributive law. */
9171 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9172 XEXP (varop
, 0), count
);
9173 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
9174 XEXP (varop
, 1), count
);
9176 varop
= gen_binary (GET_CODE (varop
), shift_mode
, lhs
, rhs
);
9177 varop
= apply_distributive_law (varop
);
9184 /* convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
9185 says that the sign bit can be tested, FOO has mode MODE, C is
9186 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
9187 that may be nonzero. */
9188 if (code
== LSHIFTRT
9189 && XEXP (varop
, 1) == const0_rtx
9190 && GET_MODE (XEXP (varop
, 0)) == result_mode
9191 && count
== GET_MODE_BITSIZE (result_mode
) - 1
9192 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9193 && ((STORE_FLAG_VALUE
9194 & ((HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (result_mode
) - 1))))
9195 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9196 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9197 (HOST_WIDE_INT
) 1, result_mode
,
9200 varop
= XEXP (varop
, 0);
9207 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
9208 than the number of bits in the mode is equivalent to A. */
9209 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9210 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
9212 varop
= XEXP (varop
, 0);
9217 /* NEG commutes with ASHIFT since it is multiplication. Move the
9218 NEG outside to allow shifts to combine. */
9220 && merge_outer_ops (&outer_op
, &outer_const
, NEG
,
9221 (HOST_WIDE_INT
) 0, result_mode
,
9224 varop
= XEXP (varop
, 0);
9230 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
9231 is one less than the number of bits in the mode is
9232 equivalent to (xor A 1). */
9233 if (code
== LSHIFTRT
&& count
== GET_MODE_BITSIZE (result_mode
) - 1
9234 && XEXP (varop
, 1) == constm1_rtx
9235 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
9236 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
9237 (HOST_WIDE_INT
) 1, result_mode
,
9241 varop
= XEXP (varop
, 0);
9245 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
9246 that might be nonzero in BAR are those being shifted out and those
9247 bits are known zero in FOO, we can replace the PLUS with FOO.
9248 Similarly in the other operand order. This code occurs when
9249 we are computing the size of a variable-size array. */
9251 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9252 && count
< HOST_BITS_PER_WIDE_INT
9253 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
9254 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
9255 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
9257 varop
= XEXP (varop
, 0);
9260 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
9261 && count
< HOST_BITS_PER_WIDE_INT
9262 && GET_MODE_BITSIZE (result_mode
) <= HOST_BITS_PER_WIDE_INT
9263 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9265 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
9266 & nonzero_bits (XEXP (varop
, 1),
9269 varop
= XEXP (varop
, 1);
9273 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
9275 && GET_CODE (XEXP (varop
, 1)) == CONST_INT
9276 && (new = simplify_binary_operation (ASHIFT
, result_mode
,
9278 GEN_INT (count
))) != 0
9279 && GET_CODE(new) == CONST_INT
9280 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
9281 INTVAL (new), result_mode
, &complement_p
))
9283 varop
= XEXP (varop
, 0);
9289 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
9290 with C the size of VAROP - 1 and the shift is logical if
9291 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
9292 we have a (gt X 0) operation. If the shift is arithmetic with
9293 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
9294 we have a (neg (gt X 0)) operation. */
9296 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9297 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
9298 && count
== GET_MODE_BITSIZE (GET_MODE (varop
)) - 1
9299 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
9300 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9301 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
9302 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
9305 varop
= gen_rtx_combine (GT
, GET_MODE (varop
), XEXP (varop
, 1),
9308 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
9309 varop
= gen_rtx_combine (NEG
, GET_MODE (varop
), varop
);
9316 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
9317 if the truncate does not affect the value. */
9318 if (code
== LSHIFTRT
9319 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
9320 && GET_CODE (XEXP (XEXP (varop
, 0), 1)) == CONST_INT
9321 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
9322 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop
, 0)))
9323 - GET_MODE_BITSIZE (GET_MODE (varop
)))))
9325 rtx varop_inner
= XEXP (varop
, 0);
9327 varop_inner
= gen_rtx_combine (LSHIFTRT
,
9328 GET_MODE (varop_inner
),
9329 XEXP (varop_inner
, 0),
9330 GEN_INT (count
+ INTVAL (XEXP (varop_inner
, 1))));
9331 varop
= gen_rtx_combine (TRUNCATE
, GET_MODE (varop
),
9345 /* We need to determine what mode to do the shift in. If the shift is
9346 a right shift or ROTATE, we must always do it in the mode it was
9347 originally done in. Otherwise, we can do it in MODE, the widest mode
9348 encountered. The code we care about is that of the shift that will
9349 actually be done, not the shift that was originally requested. */
9351 = (code
== ASHIFTRT
|| code
== LSHIFTRT
|| code
== ROTATE
9352 ? result_mode
: mode
);
9354 /* We have now finished analyzing the shift. The result should be
9355 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
9356 OUTER_OP is non-NIL, it is an operation that needs to be applied
9357 to the result of the shift. OUTER_CONST is the relevant constant,
9358 but we must turn off all bits turned off in the shift.
9360 If we were passed a value for X, see if we can use any pieces of
9361 it. If not, make new rtx. */
9363 if (x
&& GET_RTX_CLASS (GET_CODE (x
)) == '2'
9364 && GET_CODE (XEXP (x
, 1)) == CONST_INT
9365 && INTVAL (XEXP (x
, 1)) == count
)
9366 const_rtx
= XEXP (x
, 1);
9368 const_rtx
= GEN_INT (count
);
9370 if (x
&& GET_CODE (XEXP (x
, 0)) == SUBREG
9371 && GET_MODE (XEXP (x
, 0)) == shift_mode
9372 && SUBREG_REG (XEXP (x
, 0)) == varop
)
9373 varop
= XEXP (x
, 0);
9374 else if (GET_MODE (varop
) != shift_mode
)
9375 varop
= gen_lowpart_for_combine (shift_mode
, varop
);
9377 /* If we can't make the SUBREG, try to return what we were given. */
9378 if (GET_CODE (varop
) == CLOBBER
)
9379 return x
? x
: varop
;
9381 new = simplify_binary_operation (code
, shift_mode
, varop
, const_rtx
);
9386 if (x
== 0 || GET_CODE (x
) != code
|| GET_MODE (x
) != shift_mode
)
9387 x
= gen_rtx_combine (code
, shift_mode
, varop
, const_rtx
);
9389 SUBST (XEXP (x
, 0), varop
);
9390 SUBST (XEXP (x
, 1), const_rtx
);
9393 /* If we have an outer operation and we just made a shift, it is
9394 possible that we could have simplified the shift were it not
9395 for the outer operation. So try to do the simplification
9398 if (outer_op
!= NIL
&& GET_CODE (x
) == code
9399 && GET_CODE (XEXP (x
, 1)) == CONST_INT
)
9400 x
= simplify_shift_const (x
, code
, shift_mode
, XEXP (x
, 0),
9401 INTVAL (XEXP (x
, 1)));
9403 /* If we were doing a LSHIFTRT in a wider mode than it was originally,
9404 turn off all the bits that the shift would have turned off. */
9405 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
9406 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
9407 GET_MODE_MASK (result_mode
) >> orig_count
);
9409 /* Do the remainder of the processing in RESULT_MODE. */
9410 x
= gen_lowpart_for_combine (result_mode
, x
);
9412 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9415 x
= gen_unary (NOT
, result_mode
, result_mode
, x
);
9417 if (outer_op
!= NIL
)
9419 if (GET_MODE_BITSIZE (result_mode
) < HOST_BITS_PER_WIDE_INT
)
9420 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
9422 if (outer_op
== AND
)
9423 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
9424 else if (outer_op
== SET
)
9425 /* This means that we have determined that the result is
9426 equivalent to a constant. This should be rare. */
9427 x
= GEN_INT (outer_const
);
9428 else if (GET_RTX_CLASS (outer_op
) == '1')
9429 x
= gen_unary (outer_op
, result_mode
, result_mode
, x
);
9431 x
= gen_binary (outer_op
, result_mode
, x
, GEN_INT (outer_const
));
9437 /* Like recog, but we receive the address of a pointer to a new pattern.
9438 We try to match the rtx that the pointer points to.
9439 If that fails, we may try to modify or replace the pattern,
9440 storing the replacement into the same pointer object.
9442 Modifications include deletion or addition of CLOBBERs.
9444 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9445 the CLOBBERs are placed.
9447 The value is the final insn code from the pattern ultimately matched,
9451 recog_for_combine (pnewpat
, insn
, pnotes
)
9456 register rtx pat
= *pnewpat
;
9457 int insn_code_number
;
9458 int num_clobbers_to_add
= 0;
9462 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9463 we use to indicate that something didn't match. If we find such a
9464 thing, force rejection. */
9465 if (GET_CODE (pat
) == PARALLEL
)
9466 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
9467 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
9468 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
9471 /* Is the result of combination a valid instruction? */
9472 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9474 /* If it isn't, there is the possibility that we previously had an insn
9475 that clobbered some register as a side effect, but the combined
9476 insn doesn't need to do that. So try once more without the clobbers
9477 unless this represents an ASM insn. */
9479 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
9480 && GET_CODE (pat
) == PARALLEL
)
9484 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
9485 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
9488 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
9492 SUBST_INT (XVECLEN (pat
, 0), pos
);
9495 pat
= XVECEXP (pat
, 0, 0);
9497 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
9500 /* If we had any clobbers to add, make a new pattern than contains
9501 them. Then check to make sure that all of them are dead. */
9502 if (num_clobbers_to_add
)
9504 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
9505 gen_rtvec (GET_CODE (pat
) == PARALLEL
9507 + num_clobbers_to_add
)
9508 : num_clobbers_to_add
+ 1));
9510 if (GET_CODE (pat
) == PARALLEL
)
9511 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
9512 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
9514 XVECEXP (newpat
, 0, 0) = pat
;
9516 add_clobbers (newpat
, insn_code_number
);
9518 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
9519 i
< XVECLEN (newpat
, 0); i
++)
9521 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) == REG
9522 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
9524 notes
= gen_rtx_EXPR_LIST (REG_UNUSED
,
9525 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
9533 return insn_code_number
;
9536 /* Like gen_lowpart but for use by combine. In combine it is not possible
9537 to create any new pseudoregs. However, it is safe to create
9538 invalid memory addresses, because combine will try to recognize
9539 them and all they will do is make the combine attempt fail.
9541 If for some reason this cannot do its job, an rtx
9542 (clobber (const_int 0)) is returned.
9543 An insn containing that will not be recognized. */
9548 gen_lowpart_for_combine (mode
, x
)
9549 enum machine_mode mode
;
9554 if (GET_MODE (x
) == mode
)
9557 /* We can only support MODE being wider than a word if X is a
9558 constant integer or has a mode the same size. */
9560 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
9561 && ! ((GET_MODE (x
) == VOIDmode
9562 && (GET_CODE (x
) == CONST_INT
9563 || GET_CODE (x
) == CONST_DOUBLE
))
9564 || GET_MODE_SIZE (GET_MODE (x
)) == GET_MODE_SIZE (mode
)))
9565 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9567 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9568 won't know what to do. So we will strip off the SUBREG here and
9569 process normally. */
9570 if (GET_CODE (x
) == SUBREG
&& GET_CODE (SUBREG_REG (x
)) == MEM
)
9573 if (GET_MODE (x
) == mode
)
9577 result
= gen_lowpart_common (mode
, x
);
9579 && GET_CODE (result
) == SUBREG
9580 && GET_CODE (SUBREG_REG (result
)) == REG
9581 && REGNO (SUBREG_REG (result
)) >= FIRST_PSEUDO_REGISTER
9582 && (GET_MODE_SIZE (GET_MODE (result
))
9583 != GET_MODE_SIZE (GET_MODE (SUBREG_REG (result
)))))
9584 REG_CHANGES_SIZE (REGNO (SUBREG_REG (result
))) = 1;
9589 if (GET_CODE (x
) == MEM
)
9591 register int offset
= 0;
9594 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9596 if (MEM_VOLATILE_P (x
) || mode_dependent_address_p (XEXP (x
, 0)))
9597 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
9599 /* If we want to refer to something bigger than the original memref,
9600 generate a perverse subreg instead. That will force a reload
9601 of the original memref X. */
9602 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
))
9603 return gen_rtx_SUBREG (mode
, x
, 0);
9605 if (WORDS_BIG_ENDIAN
)
9606 offset
= (MAX (GET_MODE_SIZE (GET_MODE (x
)), UNITS_PER_WORD
)
9607 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
));
9609 if (BYTES_BIG_ENDIAN
)
9611 /* Adjust the address so that the address-after-the-data is
9613 offset
-= (MIN (UNITS_PER_WORD
, GET_MODE_SIZE (mode
))
9614 - MIN (UNITS_PER_WORD
, GET_MODE_SIZE (GET_MODE (x
))));
9616 new = gen_rtx_MEM (mode
, plus_constant (XEXP (x
, 0), offset
));
9617 RTX_UNCHANGING_P (new) = RTX_UNCHANGING_P (x
);
9618 MEM_COPY_ATTRIBUTES (new, x
);
9622 /* If X is a comparison operator, rewrite it in a new mode. This
9623 probably won't match, but may allow further simplifications. */
9624 else if (GET_RTX_CLASS (GET_CODE (x
)) == '<')
9625 return gen_rtx_combine (GET_CODE (x
), mode
, XEXP (x
, 0), XEXP (x
, 1));
9627 /* If we couldn't simplify X any other way, just enclose it in a
9628 SUBREG. Normally, this SUBREG won't match, but some patterns may
9629 include an explicit SUBREG or we may simplify it further in combine. */
9634 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (GET_MODE (x
)) > UNITS_PER_WORD
)
9635 word
= ((GET_MODE_SIZE (GET_MODE (x
))
9636 - MAX (GET_MODE_SIZE (mode
), UNITS_PER_WORD
))
9638 return gen_rtx_SUBREG (mode
, x
, word
);
9642 /* Make an rtx expression. This is a subset of gen_rtx and only supports
9643 expressions of 1, 2, or 3 operands, each of which are rtx expressions.
9645 If the identical expression was previously in the insn (in the undobuf),
9646 it will be returned. Only if it is not found will a new expression
9651 gen_rtx_combine
VPARAMS ((enum rtx_code code
, enum machine_mode mode
, ...))
9653 #ifndef ANSI_PROTOTYPES
9655 enum machine_mode mode
;
9667 #ifndef ANSI_PROTOTYPES
9668 code
= va_arg (p
, enum rtx_code
);
9669 mode
= va_arg (p
, enum machine_mode
);
9672 n_args
= GET_RTX_LENGTH (code
);
9673 fmt
= GET_RTX_FORMAT (code
);
9675 if (n_args
== 0 || n_args
> 3)
9678 /* Get each arg and verify that it is supposed to be an expression. */
9679 for (j
= 0; j
< n_args
; j
++)
9684 args
[j
] = va_arg (p
, rtx
);
9689 /* See if this is in undobuf. Be sure we don't use objects that came
9690 from another insn; this could produce circular rtl structures. */
9692 for (undo
= undobuf
.undos
; undo
!= undobuf
.previous_undos
; undo
= undo
->next
)
9694 && GET_CODE (undo
->old_contents
.r
) == code
9695 && GET_MODE (undo
->old_contents
.r
) == mode
)
9697 for (j
= 0; j
< n_args
; j
++)
9698 if (XEXP (undo
->old_contents
.r
, j
) != args
[j
])
9702 return undo
->old_contents
.r
;
9705 /* Otherwise make a new rtx. We know we have 1, 2, or 3 args.
9706 Use rtx_alloc instead of gen_rtx because it's faster on RISC. */
9707 rt
= rtx_alloc (code
);
9708 PUT_MODE (rt
, mode
);
9709 XEXP (rt
, 0) = args
[0];
9712 XEXP (rt
, 1) = args
[1];
9714 XEXP (rt
, 2) = args
[2];
9719 /* These routines make binary and unary operations by first seeing if they
9720 fold; if not, a new expression is allocated. */
9723 gen_binary (code
, mode
, op0
, op1
)
9725 enum machine_mode mode
;
9731 if (GET_RTX_CLASS (code
) == 'c'
9732 && (GET_CODE (op0
) == CONST_INT
9733 || (CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)))
9734 tem
= op0
, op0
= op1
, op1
= tem
;
9736 if (GET_RTX_CLASS (code
) == '<')
9738 enum machine_mode op_mode
= GET_MODE (op0
);
9740 /* Strip the COMPARE from (REL_OP (compare X Y) 0) to get
9741 just (REL_OP X Y). */
9742 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
9744 op1
= XEXP (op0
, 1);
9745 op0
= XEXP (op0
, 0);
9746 op_mode
= GET_MODE (op0
);
9749 if (op_mode
== VOIDmode
)
9750 op_mode
= GET_MODE (op1
);
9751 result
= simplify_relational_operation (code
, op_mode
, op0
, op1
);
9754 result
= simplify_binary_operation (code
, mode
, op0
, op1
);
9759 /* Put complex operands first and constants second. */
9760 if (GET_RTX_CLASS (code
) == 'c'
9761 && ((CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)
9762 || (GET_RTX_CLASS (GET_CODE (op0
)) == 'o'
9763 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')
9764 || (GET_CODE (op0
) == SUBREG
9765 && GET_RTX_CLASS (GET_CODE (SUBREG_REG (op0
))) == 'o'
9766 && GET_RTX_CLASS (GET_CODE (op1
)) != 'o')))
9767 return gen_rtx_combine (code
, mode
, op1
, op0
);
9769 /* If we are turning off bits already known off in OP0, we need not do
9771 else if (code
== AND
&& GET_CODE (op1
) == CONST_INT
9772 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
9773 && (nonzero_bits (op0
, mode
) & ~ INTVAL (op1
)) == 0)
9776 return gen_rtx_combine (code
, mode
, op0
, op1
);
9780 gen_unary (code
, mode
, op0_mode
, op0
)
9782 enum machine_mode mode
, op0_mode
;
9785 rtx result
= simplify_unary_operation (code
, mode
, op0
, op0_mode
);
9790 return gen_rtx_combine (code
, mode
, op0
);
9793 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9794 comparison code that will be tested.
9796 The result is a possibly different comparison code to use. *POP0 and
9797 *POP1 may be updated.
9799 It is possible that we might detect that a comparison is either always
9800 true or always false. However, we do not perform general constant
9801 folding in combine, so this knowledge isn't useful. Such tautologies
9802 should have been detected earlier. Hence we ignore all such cases. */
9804 static enum rtx_code
9805 simplify_comparison (code
, pop0
, pop1
)
9814 enum machine_mode mode
, tmode
;
9816 /* Try a few ways of applying the same transformation to both operands. */
9819 #ifndef WORD_REGISTER_OPERATIONS
9820 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9821 so check specially. */
9822 if (code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
9823 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
9824 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
9825 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
9826 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
9827 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
9828 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
9829 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
9830 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9831 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
9832 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
9833 && GET_CODE (XEXP (XEXP (op1
, 0), 1)) == CONST_INT
9834 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (op1
, 1))
9835 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op0
, 0), 1))
9836 && INTVAL (XEXP (op0
, 1)) == INTVAL (XEXP (XEXP (op1
, 0), 1))
9837 && (INTVAL (XEXP (op0
, 1))
9838 == (GET_MODE_BITSIZE (GET_MODE (op0
))
9840 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
9842 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
9843 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
9847 /* If both operands are the same constant shift, see if we can ignore the
9848 shift. We can if the shift is a rotate or if the bits shifted out of
9849 this shift are known to be zero for both inputs and if the type of
9850 comparison is compatible with the shift. */
9851 if (GET_CODE (op0
) == GET_CODE (op1
)
9852 && GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
9853 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
9854 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
9855 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
9856 || (GET_CODE (op0
) == ASHIFTRT
9857 && (code
!= GTU
&& code
!= LTU
9858 && code
!= GEU
&& code
!= GEU
)))
9859 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9860 && INTVAL (XEXP (op0
, 1)) >= 0
9861 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
9862 && XEXP (op0
, 1) == XEXP (op1
, 1))
9864 enum machine_mode mode
= GET_MODE (op0
);
9865 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9866 int shift_count
= INTVAL (XEXP (op0
, 1));
9868 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
9869 mask
&= (mask
>> shift_count
) << shift_count
;
9870 else if (GET_CODE (op0
) == ASHIFT
)
9871 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
9873 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~ mask
) == 0
9874 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~ mask
) == 0)
9875 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
9880 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9881 SUBREGs are of the same mode, and, in both cases, the AND would
9882 be redundant if the comparison was done in the narrower mode,
9883 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9884 and the operand's possibly nonzero bits are 0xffffff01; in that case
9885 if we only care about QImode, we don't need the AND). This case
9886 occurs if the output mode of an scc insn is not SImode and
9887 STORE_FLAG_VALUE == 1 (e.g., the 386).
9889 Similarly, check for a case where the AND's are ZERO_EXTEND
9890 operations from some narrower mode even though a SUBREG is not
9893 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
9894 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
9895 && GET_CODE (XEXP (op1
, 1)) == CONST_INT
)
9897 rtx inner_op0
= XEXP (op0
, 0);
9898 rtx inner_op1
= XEXP (op1
, 0);
9899 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
9900 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
9903 if (GET_CODE (inner_op0
) == SUBREG
&& GET_CODE (inner_op1
) == SUBREG
9904 && (GET_MODE_SIZE (GET_MODE (inner_op0
))
9905 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0
))))
9906 && (GET_MODE (SUBREG_REG (inner_op0
))
9907 == GET_MODE (SUBREG_REG (inner_op1
)))
9908 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0
)))
9909 <= HOST_BITS_PER_WIDE_INT
)
9910 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
9911 GET_MODE (SUBREG_REG (inner_op0
)))))
9912 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
9913 GET_MODE (SUBREG_REG (inner_op1
))))))
9915 op0
= SUBREG_REG (inner_op0
);
9916 op1
= SUBREG_REG (inner_op1
);
9918 /* The resulting comparison is always unsigned since we masked
9919 off the original sign bit. */
9920 code
= unsigned_condition (code
);
9926 for (tmode
= GET_CLASS_NARROWEST_MODE
9927 (GET_MODE_CLASS (GET_MODE (op0
)));
9928 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
9929 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
9931 op0
= gen_lowpart_for_combine (tmode
, inner_op0
);
9932 op1
= gen_lowpart_for_combine (tmode
, inner_op1
);
9933 code
= unsigned_condition (code
);
9942 /* If both operands are NOT, we can strip off the outer operation
9943 and adjust the comparison code for swapped operands; similarly for
9944 NEG, except that this must be an equality comparison. */
9945 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
9946 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
9947 && (code
== EQ
|| code
== NE
)))
9948 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
9954 /* If the first operand is a constant, swap the operands and adjust the
9955 comparison code appropriately, but don't do this if the second operand
9956 is already a constant integer. */
9957 if (CONSTANT_P (op0
) && GET_CODE (op1
) != CONST_INT
)
9959 tem
= op0
, op0
= op1
, op1
= tem
;
9960 code
= swap_condition (code
);
9963 /* We now enter a loop during which we will try to simplify the comparison.
9964 For the most part, we only are concerned with comparisons with zero,
9965 but some things may really be comparisons with zero but not start
9966 out looking that way. */
9968 while (GET_CODE (op1
) == CONST_INT
)
9970 enum machine_mode mode
= GET_MODE (op0
);
9971 int mode_width
= GET_MODE_BITSIZE (mode
);
9972 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
9973 int equality_comparison_p
;
9974 int sign_bit_comparison_p
;
9975 int unsigned_comparison_p
;
9976 HOST_WIDE_INT const_op
;
9978 /* We only want to handle integral modes. This catches VOIDmode,
9979 CCmode, and the floating-point modes. An exception is that we
9980 can handle VOIDmode if OP0 is a COMPARE or a comparison
9983 if (GET_MODE_CLASS (mode
) != MODE_INT
9984 && ! (mode
== VOIDmode
9985 && (GET_CODE (op0
) == COMPARE
9986 || GET_RTX_CLASS (GET_CODE (op0
)) == '<')))
9989 /* Get the constant we are comparing against and turn off all bits
9990 not on in our mode. */
9991 const_op
= INTVAL (op1
);
9992 if (mode_width
<= HOST_BITS_PER_WIDE_INT
)
9995 /* If we are comparing against a constant power of two and the value
9996 being compared can only have that single bit nonzero (e.g., it was
9997 `and'ed with that bit), we can replace this with a comparison
10000 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
10001 || code
== LT
|| code
== LTU
)
10002 && mode_width
<= HOST_BITS_PER_WIDE_INT
10003 && exact_log2 (const_op
) >= 0
10004 && nonzero_bits (op0
, mode
) == (unsigned HOST_WIDE_INT
) const_op
)
10006 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
10007 op1
= const0_rtx
, const_op
= 0;
10010 /* Similarly, if we are comparing a value known to be either -1 or
10011 0 with -1, change it to the opposite comparison against zero. */
10014 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
10015 || code
== GEU
|| code
== LTU
)
10016 && num_sign_bit_copies (op0
, mode
) == mode_width
)
10018 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
10019 op1
= const0_rtx
, const_op
= 0;
10022 /* Do some canonicalizations based on the comparison code. We prefer
10023 comparisons against zero and then prefer equality comparisons.
10024 If we can reduce the size of a constant, we will do that too. */
10029 /* < C is equivalent to <= (C - 1) */
10033 op1
= GEN_INT (const_op
);
10035 /* ... fall through to LE case below. */
10041 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
10045 op1
= GEN_INT (const_op
);
10049 /* If we are doing a <= 0 comparison on a value known to have
10050 a zero sign bit, we can replace this with == 0. */
10051 else if (const_op
== 0
10052 && mode_width
<= HOST_BITS_PER_WIDE_INT
10053 && (nonzero_bits (op0
, mode
)
10054 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10059 /* >= C is equivalent to > (C - 1). */
10063 op1
= GEN_INT (const_op
);
10065 /* ... fall through to GT below. */
10071 /* > C is equivalent to >= (C + 1); we do this for C < 0*/
10075 op1
= GEN_INT (const_op
);
10079 /* If we are doing a > 0 comparison on a value known to have
10080 a zero sign bit, we can replace this with != 0. */
10081 else if (const_op
== 0
10082 && mode_width
<= HOST_BITS_PER_WIDE_INT
10083 && (nonzero_bits (op0
, mode
)
10084 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)
10089 /* < C is equivalent to <= (C - 1). */
10093 op1
= GEN_INT (const_op
);
10095 /* ... fall through ... */
10098 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
10099 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10100 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10102 const_op
= 0, op1
= const0_rtx
;
10110 /* unsigned <= 0 is equivalent to == 0 */
10114 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
10115 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10116 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10118 const_op
= 0, op1
= const0_rtx
;
10124 /* >= C is equivalent to < (C - 1). */
10128 op1
= GEN_INT (const_op
);
10130 /* ... fall through ... */
10133 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
10134 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10135 && (const_op
== (HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10137 const_op
= 0, op1
= const0_rtx
;
10145 /* unsigned > 0 is equivalent to != 0 */
10149 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
10150 else if ((mode_width
<= HOST_BITS_PER_WIDE_INT
)
10151 && (const_op
== ((HOST_WIDE_INT
) 1 << (mode_width
- 1)) - 1))
10153 const_op
= 0, op1
= const0_rtx
;
10162 /* Compute some predicates to simplify code below. */
10164 equality_comparison_p
= (code
== EQ
|| code
== NE
);
10165 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
10166 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
10169 /* If this is a sign bit comparison and we can do arithmetic in
10170 MODE, say that we will only be needing the sign bit of OP0. */
10171 if (sign_bit_comparison_p
10172 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10173 op0
= force_to_mode (op0
, mode
,
10175 << (GET_MODE_BITSIZE (mode
) - 1)),
10178 /* Now try cases based on the opcode of OP0. If none of the cases
10179 does a "continue", we exit this loop immediately after the
10182 switch (GET_CODE (op0
))
10185 /* If we are extracting a single bit from a variable position in
10186 a constant that has only a single bit set and are comparing it
10187 with zero, we can convert this into an equality comparison
10188 between the position and the location of the single bit. */
10190 if (GET_CODE (XEXP (op0
, 0)) == CONST_INT
10191 && XEXP (op0
, 1) == const1_rtx
10192 && equality_comparison_p
&& const_op
== 0
10193 && (i
= exact_log2 (INTVAL (XEXP (op0
, 0)))) >= 0)
10195 if (BITS_BIG_ENDIAN
)
10198 mode
= insn_data
[(int) CODE_FOR_extzv
].operand
[1].mode
;
10199 if (mode
== VOIDmode
)
10201 i
= (GET_MODE_BITSIZE (mode
) - 1 - i
);
10203 i
= BITS_PER_WORD
- 1 - i
;
10207 op0
= XEXP (op0
, 2);
10211 /* Result is nonzero iff shift count is equal to I. */
10212 code
= reverse_condition (code
);
10216 /* ... fall through ... */
10219 tem
= expand_compound_operation (op0
);
10228 /* If testing for equality, we can take the NOT of the constant. */
10229 if (equality_comparison_p
10230 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
10232 op0
= XEXP (op0
, 0);
10237 /* If just looking at the sign bit, reverse the sense of the
10239 if (sign_bit_comparison_p
)
10241 op0
= XEXP (op0
, 0);
10242 code
= (code
== GE
? LT
: GE
);
10248 /* If testing for equality, we can take the NEG of the constant. */
10249 if (equality_comparison_p
10250 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
10252 op0
= XEXP (op0
, 0);
10257 /* The remaining cases only apply to comparisons with zero. */
10261 /* When X is ABS or is known positive,
10262 (neg X) is < 0 if and only if X != 0. */
10264 if (sign_bit_comparison_p
10265 && (GET_CODE (XEXP (op0
, 0)) == ABS
10266 || (mode_width
<= HOST_BITS_PER_WIDE_INT
10267 && (nonzero_bits (XEXP (op0
, 0), mode
)
10268 & ((HOST_WIDE_INT
) 1 << (mode_width
- 1))) == 0)))
10270 op0
= XEXP (op0
, 0);
10271 code
= (code
== LT
? NE
: EQ
);
10275 /* If we have NEG of something whose two high-order bits are the
10276 same, we know that "(-a) < 0" is equivalent to "a > 0". */
10277 if (num_sign_bit_copies (op0
, mode
) >= 2)
10279 op0
= XEXP (op0
, 0);
10280 code
= swap_condition (code
);
10286 /* If we are testing equality and our count is a constant, we
10287 can perform the inverse operation on our RHS. */
10288 if (equality_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10289 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
10290 op1
, XEXP (op0
, 1))) != 0)
10292 op0
= XEXP (op0
, 0);
10297 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
10298 a particular bit. Convert it to an AND of a constant of that
10299 bit. This will be converted into a ZERO_EXTRACT. */
10300 if (const_op
== 0 && sign_bit_comparison_p
10301 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10302 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10304 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10307 - INTVAL (XEXP (op0
, 1)))));
10308 code
= (code
== LT
? NE
: EQ
);
10312 /* ... fall through ... */
10315 /* ABS is ignorable inside an equality comparison with zero. */
10316 if (const_op
== 0 && equality_comparison_p
)
10318 op0
= XEXP (op0
, 0);
10325 /* Can simplify (compare (zero/sign_extend FOO) CONST)
10326 to (compare FOO CONST) if CONST fits in FOO's mode and we
10327 are either testing inequality or have an unsigned comparison
10328 with ZERO_EXTEND or a signed comparison with SIGN_EXTEND. */
10329 if (! unsigned_comparison_p
10330 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10331 <= HOST_BITS_PER_WIDE_INT
)
10332 && ((unsigned HOST_WIDE_INT
) const_op
10333 < (((unsigned HOST_WIDE_INT
) 1
10334 << (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0))) - 1)))))
10336 op0
= XEXP (op0
, 0);
10342 /* Check for the case where we are comparing A - C1 with C2,
10343 both constants are smaller than 1/2 the maximum positive
10344 value in MODE, and the comparison is equality or unsigned.
10345 In that case, if A is either zero-extended to MODE or has
10346 sufficient sign bits so that the high-order bit in MODE
10347 is a copy of the sign in the inner mode, we can prove that it is
10348 safe to do the operation in the wider mode. This simplifies
10349 many range checks. */
10351 if (mode_width
<= HOST_BITS_PER_WIDE_INT
10352 && subreg_lowpart_p (op0
)
10353 && GET_CODE (SUBREG_REG (op0
)) == PLUS
10354 && GET_CODE (XEXP (SUBREG_REG (op0
), 1)) == CONST_INT
10355 && INTVAL (XEXP (SUBREG_REG (op0
), 1)) < 0
10356 && (- INTVAL (XEXP (SUBREG_REG (op0
), 1))
10357 < (HOST_WIDE_INT
)(GET_MODE_MASK (mode
) / 2))
10358 && (unsigned HOST_WIDE_INT
) const_op
< GET_MODE_MASK (mode
) / 2
10359 && (0 == (nonzero_bits (XEXP (SUBREG_REG (op0
), 0),
10360 GET_MODE (SUBREG_REG (op0
)))
10361 & ~ GET_MODE_MASK (mode
))
10362 || (num_sign_bit_copies (XEXP (SUBREG_REG (op0
), 0),
10363 GET_MODE (SUBREG_REG (op0
)))
10364 > (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10365 - GET_MODE_BITSIZE (mode
)))))
10367 op0
= SUBREG_REG (op0
);
10371 /* If the inner mode is narrower and we are extracting the low part,
10372 we can treat the SUBREG as if it were a ZERO_EXTEND. */
10373 if (subreg_lowpart_p (op0
)
10374 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
10375 /* Fall through */ ;
10379 /* ... fall through ... */
10382 if ((unsigned_comparison_p
|| equality_comparison_p
)
10383 && (GET_MODE_BITSIZE (GET_MODE (XEXP (op0
, 0)))
10384 <= HOST_BITS_PER_WIDE_INT
)
10385 && ((unsigned HOST_WIDE_INT
) const_op
10386 < GET_MODE_MASK (GET_MODE (XEXP (op0
, 0)))))
10388 op0
= XEXP (op0
, 0);
10394 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
10395 this for equality comparisons due to pathological cases involving
10397 if (equality_comparison_p
10398 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10399 op1
, XEXP (op0
, 1))))
10401 op0
= XEXP (op0
, 0);
10406 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
10407 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
10408 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
10410 op0
= XEXP (XEXP (op0
, 0), 0);
10411 code
= (code
== LT
? EQ
: NE
);
10417 /* (op (minus A B) 0) -> (op A B) */
10418 if (op1
== const0_rtx
)
10420 op1
= XEXP (op0
, 1);
10421 op0
= XEXP (op0
, 0);
10425 /* (eq (minus A B) C) -> (eq A (plus B C)) or
10426 (eq B (minus A C)), whichever simplifies. We can only do
10427 this for equality comparisons due to pathological cases involving
10429 if (equality_comparison_p
10430 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
10431 XEXP (op0
, 1), op1
)))
10433 op0
= XEXP (op0
, 0);
10438 if (equality_comparison_p
10439 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
10440 XEXP (op0
, 0), op1
)))
10442 op0
= XEXP (op0
, 1);
10447 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
10448 of bits in X minus 1, is one iff X > 0. */
10449 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
10450 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10451 && INTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
10452 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10454 op0
= XEXP (op0
, 1);
10455 code
= (code
== GE
? LE
: GT
);
10461 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
10462 if C is zero or B is a constant. */
10463 if (equality_comparison_p
10464 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
10465 XEXP (op0
, 1), op1
)))
10467 op0
= XEXP (op0
, 0);
10474 case LT
: case LTU
: case LE
: case LEU
:
10475 case GT
: case GTU
: case GE
: case GEU
:
10476 /* We can't do anything if OP0 is a condition code value, rather
10477 than an actual data value. */
10480 || XEXP (op0
, 0) == cc0_rtx
10482 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
10485 /* Get the two operands being compared. */
10486 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
10487 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
10489 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
10491 /* Check for the cases where we simply want the result of the
10492 earlier test or the opposite of that result. */
10494 || (code
== EQ
&& reversible_comparison_p (op0
))
10495 || (GET_MODE_BITSIZE (GET_MODE (op0
)) <= HOST_BITS_PER_WIDE_INT
10496 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10497 && (STORE_FLAG_VALUE
10498 & (((HOST_WIDE_INT
) 1
10499 << (GET_MODE_BITSIZE (GET_MODE (op0
)) - 1))))
10501 || (code
== GE
&& reversible_comparison_p (op0
)))))
10503 code
= (code
== LT
|| code
== NE
10504 ? GET_CODE (op0
) : reverse_condition (GET_CODE (op0
)));
10505 op0
= tem
, op1
= tem1
;
10511 /* The sign bit of (ior (plus X (const_int -1)) X) is non-zero
10513 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
10514 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
10515 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
10517 op0
= XEXP (op0
, 1);
10518 code
= (code
== GE
? GT
: LE
);
10524 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10525 will be converted to a ZERO_EXTRACT later. */
10526 if (const_op
== 0 && equality_comparison_p
10527 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10528 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
10530 op0
= simplify_and_const_int
10531 (op0
, mode
, gen_rtx_combine (LSHIFTRT
, mode
,
10533 XEXP (XEXP (op0
, 0), 1)),
10534 (HOST_WIDE_INT
) 1);
10538 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10539 zero and X is a comparison and C1 and C2 describe only bits set
10540 in STORE_FLAG_VALUE, we can compare with X. */
10541 if (const_op
== 0 && equality_comparison_p
10542 && mode_width
<= HOST_BITS_PER_WIDE_INT
10543 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10544 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
10545 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10546 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
10547 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
10549 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10550 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
10551 if ((~ STORE_FLAG_VALUE
& mask
) == 0
10552 && (GET_RTX_CLASS (GET_CODE (XEXP (XEXP (op0
, 0), 0))) == '<'
10553 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
10554 && GET_RTX_CLASS (GET_CODE (tem
)) == '<')))
10556 op0
= XEXP (XEXP (op0
, 0), 0);
10561 /* If we are doing an equality comparison of an AND of a bit equal
10562 to the sign bit, replace this with a LT or GE comparison of
10563 the underlying value. */
10564 if (equality_comparison_p
10566 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10567 && mode_width
<= HOST_BITS_PER_WIDE_INT
10568 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
10569 == (unsigned HOST_WIDE_INT
) 1 << (mode_width
- 1)))
10571 op0
= XEXP (op0
, 0);
10572 code
= (code
== EQ
? GE
: LT
);
10576 /* If this AND operation is really a ZERO_EXTEND from a narrower
10577 mode, the constant fits within that mode, and this is either an
10578 equality or unsigned comparison, try to do this comparison in
10579 the narrower mode. */
10580 if ((equality_comparison_p
|| unsigned_comparison_p
)
10581 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10582 && (i
= exact_log2 ((INTVAL (XEXP (op0
, 1))
10583 & GET_MODE_MASK (mode
))
10585 && const_op
>> i
== 0
10586 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
10588 op0
= gen_lowpart_for_combine (tmode
, XEXP (op0
, 0));
10592 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1 fits
10593 in both M1 and M2 and the SUBREG is either paradoxical or
10594 represents the low part, permute the SUBREG and the AND and
10596 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
10598 #ifdef WORD_REGISTER_OPERATIONS
10600 > (GET_MODE_BITSIZE
10601 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10602 && mode_width
<= BITS_PER_WORD
)
10605 <= (GET_MODE_BITSIZE
10606 (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10607 && subreg_lowpart_p (XEXP (op0
, 0))))
10608 #ifndef WORD_REGISTER_OPERATIONS
10609 /* It is unsafe to commute the AND into the SUBREG if the SUBREG
10610 is paradoxical and WORD_REGISTER_OPERATIONS is not defined.
10611 As originally written the upper bits have a defined value
10612 due to the AND operation. However, if we commute the AND
10613 inside the SUBREG then they no longer have defined values
10614 and the meaning of the code has been changed. */
10615 && (GET_MODE_SIZE (GET_MODE (XEXP (op0
, 0)))
10616 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0)))))
10618 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10619 && mode_width
<= HOST_BITS_PER_WIDE_INT
10620 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10621 <= HOST_BITS_PER_WIDE_INT
)
10622 && (INTVAL (XEXP (op0
, 1)) & ~ mask
) == 0
10623 && 0 == (~ GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))
10624 & INTVAL (XEXP (op0
, 1)))
10625 && (unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1)) != mask
10626 && ((unsigned HOST_WIDE_INT
) INTVAL (XEXP (op0
, 1))
10627 != GET_MODE_MASK (GET_MODE (SUBREG_REG (XEXP (op0
, 0))))))
10631 = gen_lowpart_for_combine
10633 gen_binary (AND
, GET_MODE (SUBREG_REG (XEXP (op0
, 0))),
10634 SUBREG_REG (XEXP (op0
, 0)), XEXP (op0
, 1)));
10641 /* If we have (compare (ashift FOO N) (const_int C)) and
10642 the high order N bits of FOO (N+1 if an inequality comparison)
10643 are known to be zero, we can do this by comparing FOO with C
10644 shifted right N bits so long as the low-order N bits of C are
10646 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10647 && INTVAL (XEXP (op0
, 1)) >= 0
10648 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
10649 < HOST_BITS_PER_WIDE_INT
)
10651 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0)
10652 && mode_width
<= HOST_BITS_PER_WIDE_INT
10653 && (nonzero_bits (XEXP (op0
, 0), mode
)
10654 & ~ (mask
>> (INTVAL (XEXP (op0
, 1))
10655 + ! equality_comparison_p
))) == 0)
10657 /* We must perform a logical shift, not an arithmetic one,
10658 as we want the top N bits of C to be zero. */
10659 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
10661 temp
>>= INTVAL (XEXP (op0
, 1));
10662 op1
= GEN_INT (trunc_int_for_mode (temp
, mode
));
10663 op0
= XEXP (op0
, 0);
10667 /* If we are doing a sign bit comparison, it means we are testing
10668 a particular bit. Convert it to the appropriate AND. */
10669 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 1)) == CONST_INT
10670 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
10672 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10675 - INTVAL (XEXP (op0
, 1)))));
10676 code
= (code
== LT
? NE
: EQ
);
10680 /* If this an equality comparison with zero and we are shifting
10681 the low bit to the sign bit, we can convert this to an AND of the
10683 if (const_op
== 0 && equality_comparison_p
10684 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10685 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10687 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
10688 (HOST_WIDE_INT
) 1);
10694 /* If this is an equality comparison with zero, we can do this
10695 as a logical shift, which might be much simpler. */
10696 if (equality_comparison_p
&& const_op
== 0
10697 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
)
10699 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
10701 INTVAL (XEXP (op0
, 1)));
10705 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10706 do the comparison in a narrower mode. */
10707 if (! unsigned_comparison_p
10708 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10709 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
10710 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
10711 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10712 MODE_INT
, 1)) != BLKmode
10713 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10714 || ((unsigned HOST_WIDE_INT
) - const_op
10715 <= GET_MODE_MASK (tmode
))))
10717 op0
= gen_lowpart_for_combine (tmode
, XEXP (XEXP (op0
, 0), 0));
10721 /* Likewise if OP0 is a PLUS of a sign extension with a
10722 constant, which is usually represented with the PLUS
10723 between the shifts. */
10724 if (! unsigned_comparison_p
10725 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10726 && GET_CODE (XEXP (op0
, 0)) == PLUS
10727 && GET_CODE (XEXP (XEXP (op0
, 0), 1)) == CONST_INT
10728 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
10729 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
10730 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
10731 MODE_INT
, 1)) != BLKmode
10732 && ((unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (tmode
)
10733 || ((unsigned HOST_WIDE_INT
) - const_op
10734 <= GET_MODE_MASK (tmode
))))
10736 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
10737 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
10738 rtx new_const
= gen_binary (ASHIFTRT
, GET_MODE (op0
), add_const
,
10741 op0
= gen_binary (PLUS
, tmode
,
10742 gen_lowpart_for_combine (tmode
, inner
),
10747 /* ... fall through ... */
10749 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10750 the low order N bits of FOO are known to be zero, we can do this
10751 by comparing FOO with C shifted left N bits so long as no
10752 overflow occurs. */
10753 if (GET_CODE (XEXP (op0
, 1)) == CONST_INT
10754 && INTVAL (XEXP (op0
, 1)) >= 0
10755 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
10756 && mode_width
<= HOST_BITS_PER_WIDE_INT
10757 && (nonzero_bits (XEXP (op0
, 0), mode
)
10758 & (((HOST_WIDE_INT
) 1 << INTVAL (XEXP (op0
, 1))) - 1)) == 0
10760 || (floor_log2 (const_op
) + INTVAL (XEXP (op0
, 1))
10763 const_op
<<= INTVAL (XEXP (op0
, 1));
10764 op1
= GEN_INT (const_op
);
10765 op0
= XEXP (op0
, 0);
10769 /* If we are using this shift to extract just the sign bit, we
10770 can replace this with an LT or GE comparison. */
10772 && (equality_comparison_p
|| sign_bit_comparison_p
)
10773 && GET_CODE (XEXP (op0
, 1)) == CONST_INT
10774 && INTVAL (XEXP (op0
, 1)) == mode_width
- 1)
10776 op0
= XEXP (op0
, 0);
10777 code
= (code
== NE
|| code
== GT
? LT
: GE
);
10789 /* Now make any compound operations involved in this comparison. Then,
10790 check for an outmost SUBREG on OP0 that is not doing anything or is
10791 paradoxical. The latter case can only occur when it is known that the
10792 "extra" bits will be zero. Therefore, it is safe to remove the SUBREG.
10793 We can never remove a SUBREG for a non-equality comparison because the
10794 sign bit is in a different place in the underlying object. */
10796 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
10797 op1
= make_compound_operation (op1
, SET
);
10799 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10800 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10801 && (code
== NE
|| code
== EQ
)
10802 && ((GET_MODE_SIZE (GET_MODE (op0
))
10803 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
))))))
10805 op0
= SUBREG_REG (op0
);
10806 op1
= gen_lowpart_for_combine (GET_MODE (op0
), op1
);
10809 else if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
10810 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
10811 && (code
== NE
|| code
== EQ
)
10812 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)))
10813 <= HOST_BITS_PER_WIDE_INT
)
10814 && (nonzero_bits (SUBREG_REG (op0
), GET_MODE (SUBREG_REG (op0
)))
10815 & ~ GET_MODE_MASK (GET_MODE (op0
))) == 0
10816 && (tem
= gen_lowpart_for_combine (GET_MODE (SUBREG_REG (op0
)),
10818 (nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
10819 & ~ GET_MODE_MASK (GET_MODE (op0
))) == 0))
10820 op0
= SUBREG_REG (op0
), op1
= tem
;
10822 /* We now do the opposite procedure: Some machines don't have compare
10823 insns in all modes. If OP0's mode is an integer mode smaller than a
10824 word and we can't do a compare in that mode, see if there is a larger
10825 mode for which we can do the compare. There are a number of cases in
10826 which we can use the wider mode. */
10828 mode
= GET_MODE (op0
);
10829 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
10830 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
10831 && cmp_optab
->handlers
[(int) mode
].insn_code
== CODE_FOR_nothing
)
10832 for (tmode
= GET_MODE_WIDER_MODE (mode
);
10834 && GET_MODE_BITSIZE (tmode
) <= HOST_BITS_PER_WIDE_INT
);
10835 tmode
= GET_MODE_WIDER_MODE (tmode
))
10836 if (cmp_optab
->handlers
[(int) tmode
].insn_code
!= CODE_FOR_nothing
)
10838 /* If the only nonzero bits in OP0 and OP1 are those in the
10839 narrower mode and this is an equality or unsigned comparison,
10840 we can use the wider mode. Similarly for sign-extended
10841 values, in which case it is true for all comparisons. */
10842 if (((code
== EQ
|| code
== NE
10843 || code
== GEU
|| code
== GTU
|| code
== LEU
|| code
== LTU
)
10844 && (nonzero_bits (op0
, tmode
) & ~ GET_MODE_MASK (mode
)) == 0
10845 && (nonzero_bits (op1
, tmode
) & ~ GET_MODE_MASK (mode
)) == 0)
10846 || ((num_sign_bit_copies (op0
, tmode
)
10847 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))
10848 && (num_sign_bit_copies (op1
, tmode
)
10849 > GET_MODE_BITSIZE (tmode
) - GET_MODE_BITSIZE (mode
))))
10851 /* If OP0 is an AND and we don't have an AND in MODE either,
10852 make a new AND in the proper mode. */
10853 if (GET_CODE (op0
) == AND
10854 && (add_optab
->handlers
[(int) mode
].insn_code
10855 == CODE_FOR_nothing
))
10856 op0
= gen_binary (AND
, tmode
,
10857 gen_lowpart_for_combine (tmode
,
10859 gen_lowpart_for_combine (tmode
,
10862 op0
= gen_lowpart_for_combine (tmode
, op0
);
10863 op1
= gen_lowpart_for_combine (tmode
, op1
);
10867 /* If this is a test for negative, we can make an explicit
10868 test of the sign bit. */
10870 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
10871 && GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
)
10873 op0
= gen_binary (AND
, tmode
,
10874 gen_lowpart_for_combine (tmode
, op0
),
10875 GEN_INT ((HOST_WIDE_INT
) 1
10876 << (GET_MODE_BITSIZE (mode
) - 1)));
10877 code
= (code
== LT
) ? NE
: EQ
;
10882 #ifdef CANONICALIZE_COMPARISON
10883 /* If this machine only supports a subset of valid comparisons, see if we
10884 can convert an unsupported one into a supported one. */
10885 CANONICALIZE_COMPARISON (code
, op0
, op1
);
10894 /* Return 1 if we know that X, a comparison operation, is not operating
10895 on a floating-point value or is EQ or NE, meaning that we can safely
10899 reversible_comparison_p (x
)
10902 if (TARGET_FLOAT_FORMAT
!= IEEE_FLOAT_FORMAT
10904 || GET_CODE (x
) == NE
|| GET_CODE (x
) == EQ
10905 || GET_CODE (x
) == UNORDERED
|| GET_CODE (x
) == ORDERED
)
10908 switch (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))))
10911 case MODE_PARTIAL_INT
:
10912 case MODE_COMPLEX_INT
:
10916 /* If the mode of the condition codes tells us that this is safe,
10917 we need look no further. */
10918 if (REVERSIBLE_CC_MODE (GET_MODE (XEXP (x
, 0))))
10921 /* Otherwise try and find where the condition codes were last set and
10923 x
= get_last_value (XEXP (x
, 0));
10924 return (x
&& GET_CODE (x
) == COMPARE
10925 && ! FLOAT_MODE_P (GET_MODE (XEXP (x
, 0))));
10932 /* Utility function for following routine. Called when X is part of a value
10933 being stored into reg_last_set_value. Sets reg_last_set_table_tick
10934 for each register mentioned. Similar to mention_regs in cse.c */
10937 update_table_tick (x
)
10940 register enum rtx_code code
= GET_CODE (x
);
10941 register const char *fmt
= GET_RTX_FORMAT (code
);
10946 int regno
= REGNO (x
);
10947 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
10948 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
10950 for (i
= regno
; i
< endregno
; i
++)
10951 reg_last_set_table_tick
[i
] = label_tick
;
10956 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
10957 /* Note that we can't have an "E" in values stored; see
10958 get_last_value_validate. */
10960 update_table_tick (XEXP (x
, i
));
10963 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10964 are saying that the register is clobbered and we no longer know its
10965 value. If INSN is zero, don't update reg_last_set; this is only permitted
10966 with VALUE also zero and is used to invalidate the register. */
10969 record_value_for_reg (reg
, insn
, value
)
10974 int regno
= REGNO (reg
);
10975 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
10976 ? HARD_REGNO_NREGS (regno
, GET_MODE (reg
)) : 1);
10979 /* If VALUE contains REG and we have a previous value for REG, substitute
10980 the previous value. */
10981 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
10985 /* Set things up so get_last_value is allowed to see anything set up to
10987 subst_low_cuid
= INSN_CUID (insn
);
10988 tem
= get_last_value (reg
);
10990 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10991 it isn't going to be useful and will take a lot of time to process,
10992 so just use the CLOBBER. */
10996 if ((GET_RTX_CLASS (GET_CODE (tem
)) == '2'
10997 || GET_RTX_CLASS (GET_CODE (tem
)) == 'c')
10998 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
10999 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
11000 tem
= XEXP (tem
, 0);
11002 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
11006 /* For each register modified, show we don't know its value, that
11007 we don't know about its bitwise content, that its value has been
11008 updated, and that we don't know the location of the death of the
11010 for (i
= regno
; i
< endregno
; i
++)
11013 reg_last_set
[i
] = insn
;
11014 reg_last_set_value
[i
] = 0;
11015 reg_last_set_mode
[i
] = 0;
11016 reg_last_set_nonzero_bits
[i
] = 0;
11017 reg_last_set_sign_bit_copies
[i
] = 0;
11018 reg_last_death
[i
] = 0;
11021 /* Mark registers that are being referenced in this value. */
11023 update_table_tick (value
);
11025 /* Now update the status of each register being set.
11026 If someone is using this register in this block, set this register
11027 to invalid since we will get confused between the two lives in this
11028 basic block. This makes using this register always invalid. In cse, we
11029 scan the table to invalidate all entries using this register, but this
11030 is too much work for us. */
11032 for (i
= regno
; i
< endregno
; i
++)
11034 reg_last_set_label
[i
] = label_tick
;
11035 if (value
&& reg_last_set_table_tick
[i
] == label_tick
)
11036 reg_last_set_invalid
[i
] = 1;
11038 reg_last_set_invalid
[i
] = 0;
11041 /* The value being assigned might refer to X (like in "x++;"). In that
11042 case, we must replace it with (clobber (const_int 0)) to prevent
11044 if (value
&& ! get_last_value_validate (&value
, insn
,
11045 reg_last_set_label
[regno
], 0))
11047 value
= copy_rtx (value
);
11048 if (! get_last_value_validate (&value
, insn
,
11049 reg_last_set_label
[regno
], 1))
11053 /* For the main register being modified, update the value, the mode, the
11054 nonzero bits, and the number of sign bit copies. */
11056 reg_last_set_value
[regno
] = value
;
11060 subst_low_cuid
= INSN_CUID (insn
);
11061 reg_last_set_mode
[regno
] = GET_MODE (reg
);
11062 reg_last_set_nonzero_bits
[regno
] = nonzero_bits (value
, GET_MODE (reg
));
11063 reg_last_set_sign_bit_copies
[regno
]
11064 = num_sign_bit_copies (value
, GET_MODE (reg
));
11068 /* Called via note_stores from record_dead_and_set_regs to handle one
11069 SET or CLOBBER in an insn. DATA is the instruction in which the
11070 set is occurring. */
11073 record_dead_and_set_regs_1 (dest
, setter
, data
)
11077 rtx record_dead_insn
= (rtx
) data
;
11079 if (GET_CODE (dest
) == SUBREG
)
11080 dest
= SUBREG_REG (dest
);
11082 if (GET_CODE (dest
) == REG
)
11084 /* If we are setting the whole register, we know its value. Otherwise
11085 show that we don't know the value. We can handle SUBREG in
11087 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
11088 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
11089 else if (GET_CODE (setter
) == SET
11090 && GET_CODE (SET_DEST (setter
)) == SUBREG
11091 && SUBREG_REG (SET_DEST (setter
)) == dest
11092 && GET_MODE_BITSIZE (GET_MODE (dest
)) <= BITS_PER_WORD
11093 && subreg_lowpart_p (SET_DEST (setter
)))
11094 record_value_for_reg (dest
, record_dead_insn
,
11095 gen_lowpart_for_combine (GET_MODE (dest
),
11096 SET_SRC (setter
)));
11098 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
11100 else if (GET_CODE (dest
) == MEM
11101 /* Ignore pushes, they clobber nothing. */
11102 && ! push_operand (dest
, GET_MODE (dest
)))
11103 mem_last_set
= INSN_CUID (record_dead_insn
);
11106 /* Update the records of when each REG was most recently set or killed
11107 for the things done by INSN. This is the last thing done in processing
11108 INSN in the combiner loop.
11110 We update reg_last_set, reg_last_set_value, reg_last_set_mode,
11111 reg_last_set_nonzero_bits, reg_last_set_sign_bit_copies, reg_last_death,
11112 and also the similar information mem_last_set (which insn most recently
11113 modified memory) and last_call_cuid (which insn was the most recent
11114 subroutine call). */
11117 record_dead_and_set_regs (insn
)
11123 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
11125 if (REG_NOTE_KIND (link
) == REG_DEAD
11126 && GET_CODE (XEXP (link
, 0)) == REG
)
11128 int regno
= REGNO (XEXP (link
, 0));
11130 = regno
+ (regno
< FIRST_PSEUDO_REGISTER
11131 ? HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (link
, 0)))
11134 for (i
= regno
; i
< endregno
; i
++)
11135 reg_last_death
[i
] = insn
;
11137 else if (REG_NOTE_KIND (link
) == REG_INC
)
11138 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
11141 if (GET_CODE (insn
) == CALL_INSN
)
11143 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
11144 if (call_used_regs
[i
])
11146 reg_last_set_value
[i
] = 0;
11147 reg_last_set_mode
[i
] = 0;
11148 reg_last_set_nonzero_bits
[i
] = 0;
11149 reg_last_set_sign_bit_copies
[i
] = 0;
11150 reg_last_death
[i
] = 0;
11153 last_call_cuid
= mem_last_set
= INSN_CUID (insn
);
11156 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
11159 /* If a SUBREG has the promoted bit set, it is in fact a property of the
11160 register present in the SUBREG, so for each such SUBREG go back and
11161 adjust nonzero and sign bit information of the registers that are
11162 known to have some zero/sign bits set.
11164 This is needed because when combine blows the SUBREGs away, the
11165 information on zero/sign bits is lost and further combines can be
11166 missed because of that. */
11169 record_promoted_value (insn
, subreg
)
11174 int regno
= REGNO (SUBREG_REG (subreg
));
11175 enum machine_mode mode
= GET_MODE (subreg
);
11177 if (GET_MODE_BITSIZE (mode
) >= HOST_BITS_PER_WIDE_INT
)
11180 for (links
= LOG_LINKS (insn
); links
; )
11182 insn
= XEXP (links
, 0);
11183 set
= single_set (insn
);
11185 if (! set
|| GET_CODE (SET_DEST (set
)) != REG
11186 || REGNO (SET_DEST (set
)) != regno
11187 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
11189 links
= XEXP (links
, 1);
11193 if (reg_last_set
[regno
] == insn
)
11195 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
11196 reg_last_set_nonzero_bits
[regno
] &= GET_MODE_MASK (mode
);
11199 if (GET_CODE (SET_SRC (set
)) == REG
)
11201 regno
= REGNO (SET_SRC (set
));
11202 links
= LOG_LINKS (insn
);
11209 /* Scan X for promoted SUBREGs. For each one found,
11210 note what it implies to the registers used in it. */
11213 check_promoted_subreg (insn
, x
)
11217 if (GET_CODE (x
) == SUBREG
&& SUBREG_PROMOTED_VAR_P (x
)
11218 && GET_CODE (SUBREG_REG (x
)) == REG
)
11219 record_promoted_value (insn
, x
);
11222 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
11225 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
11226 switch (format
[i
])
11229 check_promoted_subreg (insn
, XEXP (x
, i
));
11233 if (XVEC (x
, i
) != 0)
11234 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11235 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
11241 /* Utility routine for the following function. Verify that all the registers
11242 mentioned in *LOC are valid when *LOC was part of a value set when
11243 label_tick == TICK. Return 0 if some are not.
11245 If REPLACE is non-zero, replace the invalid reference with
11246 (clobber (const_int 0)) and return 1. This replacement is useful because
11247 we often can get useful information about the form of a value (e.g., if
11248 it was produced by a shift that always produces -1 or 0) even though
11249 we don't know exactly what registers it was produced from. */
11252 get_last_value_validate (loc
, insn
, tick
, replace
)
11259 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
11260 int len
= GET_RTX_LENGTH (GET_CODE (x
));
11263 if (GET_CODE (x
) == REG
)
11265 int regno
= REGNO (x
);
11266 int endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11267 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11270 for (j
= regno
; j
< endregno
; j
++)
11271 if (reg_last_set_invalid
[j
]
11272 /* If this is a pseudo-register that was only set once and not
11273 live at the beginning of the function, it is always valid. */
11274 || (! (regno
>= FIRST_PSEUDO_REGISTER
11275 && REG_N_SETS (regno
) == 1
11276 && ! REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
, regno
))
11277 && reg_last_set_label
[j
] > tick
))
11280 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11286 /* If this is a memory reference, make sure that there were
11287 no stores after it that might have clobbered the value. We don't
11288 have alias info, so we assume any store invalidates it. */
11289 else if (GET_CODE (x
) == MEM
&& ! RTX_UNCHANGING_P (x
)
11290 && INSN_CUID (insn
) <= mem_last_set
)
11293 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
11297 for (i
= 0; i
< len
; i
++)
11299 && get_last_value_validate (&XEXP (x
, i
), insn
, tick
, replace
) == 0)
11300 /* Don't bother with these. They shouldn't occur anyway. */
11304 /* If we haven't found a reason for it to be invalid, it is valid. */
11308 /* Get the last value assigned to X, if known. Some registers
11309 in the value may be replaced with (clobber (const_int 0)) if their value
11310 is known longer known reliably. */
11319 /* If this is a non-paradoxical SUBREG, get the value of its operand and
11320 then convert it to the desired mode. If this is a paradoxical SUBREG,
11321 we cannot predict what values the "extra" bits might have. */
11322 if (GET_CODE (x
) == SUBREG
11323 && subreg_lowpart_p (x
)
11324 && (GET_MODE_SIZE (GET_MODE (x
))
11325 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
11326 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
11327 return gen_lowpart_for_combine (GET_MODE (x
), value
);
11329 if (GET_CODE (x
) != REG
)
11333 value
= reg_last_set_value
[regno
];
11335 /* If we don't have a value, or if it isn't for this basic block and
11336 it's either a hard register, set more than once, or it's a live
11337 at the beginning of the function, return 0.
11339 Because if it's not live at the beginnning of the function then the reg
11340 is always set before being used (is never used without being set).
11341 And, if it's set only once, and it's always set before use, then all
11342 uses must have the same last value, even if it's not from this basic
11346 || (reg_last_set_label
[regno
] != label_tick
11347 && (regno
< FIRST_PSEUDO_REGISTER
11348 || REG_N_SETS (regno
) != 1
11349 || REGNO_REG_SET_P (BASIC_BLOCK (0)->global_live_at_start
, regno
))))
11352 /* If the value was set in a later insn than the ones we are processing,
11353 we can't use it even if the register was only set once. */
11354 if (INSN_CUID (reg_last_set
[regno
]) >= subst_low_cuid
)
11357 /* If the value has all its registers valid, return it. */
11358 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11359 reg_last_set_label
[regno
], 0))
11362 /* Otherwise, make a copy and replace any invalid register with
11363 (clobber (const_int 0)). If that fails for some reason, return 0. */
11365 value
= copy_rtx (value
);
11366 if (get_last_value_validate (&value
, reg_last_set
[regno
],
11367 reg_last_set_label
[regno
], 1))
11373 /* Return nonzero if expression X refers to a REG or to memory
11374 that is set in an instruction more recent than FROM_CUID. */
11377 use_crosses_set_p (x
, from_cuid
)
11381 register const char *fmt
;
11383 register enum rtx_code code
= GET_CODE (x
);
11387 register int regno
= REGNO (x
);
11388 int endreg
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11389 ? HARD_REGNO_NREGS (regno
, GET_MODE (x
)) : 1);
11391 #ifdef PUSH_ROUNDING
11392 /* Don't allow uses of the stack pointer to be moved,
11393 because we don't know whether the move crosses a push insn. */
11394 if (regno
== STACK_POINTER_REGNUM
)
11397 for (;regno
< endreg
; regno
++)
11398 if (reg_last_set
[regno
]
11399 && INSN_CUID (reg_last_set
[regno
]) > from_cuid
)
11404 if (code
== MEM
&& mem_last_set
> from_cuid
)
11407 fmt
= GET_RTX_FORMAT (code
);
11409 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11414 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11415 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_cuid
))
11418 else if (fmt
[i
] == 'e'
11419 && use_crosses_set_p (XEXP (x
, i
), from_cuid
))
11425 /* Define three variables used for communication between the following
11428 static int reg_dead_regno
, reg_dead_endregno
;
11429 static int reg_dead_flag
;
11431 /* Function called via note_stores from reg_dead_at_p.
11433 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11434 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11437 reg_dead_at_p_1 (dest
, x
, data
)
11440 void *data ATTRIBUTE_UNUSED
;
11442 int regno
, endregno
;
11444 if (GET_CODE (dest
) != REG
)
11447 regno
= REGNO (dest
);
11448 endregno
= regno
+ (regno
< FIRST_PSEUDO_REGISTER
11449 ? HARD_REGNO_NREGS (regno
, GET_MODE (dest
)) : 1);
11451 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
11452 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
11455 /* Return non-zero if REG is known to be dead at INSN.
11457 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11458 referencing REG, it is dead. If we hit a SET referencing REG, it is
11459 live. Otherwise, see if it is live or dead at the start of the basic
11460 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11461 must be assumed to be always live. */
11464 reg_dead_at_p (reg
, insn
)
11470 /* Set variables for reg_dead_at_p_1. */
11471 reg_dead_regno
= REGNO (reg
);
11472 reg_dead_endregno
= reg_dead_regno
+ (reg_dead_regno
< FIRST_PSEUDO_REGISTER
11473 ? HARD_REGNO_NREGS (reg_dead_regno
,
11479 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. */
11480 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
11482 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11483 if (TEST_HARD_REG_BIT (newpat_used_regs
, i
))
11487 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11488 beginning of function. */
11489 for (; insn
&& GET_CODE (insn
) != CODE_LABEL
&& GET_CODE (insn
) != BARRIER
;
11490 insn
= prev_nonnote_insn (insn
))
11492 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
11494 return reg_dead_flag
== 1 ? 1 : 0;
11496 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
11500 /* Get the basic block number that we were in. */
11505 for (block
= 0; block
< n_basic_blocks
; block
++)
11506 if (insn
== BLOCK_HEAD (block
))
11509 if (block
== n_basic_blocks
)
11513 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
11514 if (REGNO_REG_SET_P (BASIC_BLOCK (block
)->global_live_at_start
, i
))
11520 /* Note hard registers in X that are used. This code is similar to
11521 that in flow.c, but much simpler since we don't care about pseudos. */
11524 mark_used_regs_combine (x
)
11527 register RTX_CODE code
= GET_CODE (x
);
11528 register int regno
;
11540 case ADDR_DIFF_VEC
:
11543 /* CC0 must die in the insn after it is set, so we don't need to take
11544 special note of it here. */
11550 /* If we are clobbering a MEM, mark any hard registers inside the
11551 address as used. */
11552 if (GET_CODE (XEXP (x
, 0)) == MEM
)
11553 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
11558 /* A hard reg in a wide mode may really be multiple registers.
11559 If so, mark all of them just like the first. */
11560 if (regno
< FIRST_PSEUDO_REGISTER
)
11562 /* None of this applies to the stack, frame or arg pointers */
11563 if (regno
== STACK_POINTER_REGNUM
11564 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11565 || regno
== HARD_FRAME_POINTER_REGNUM
11567 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11568 || (regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
11570 || regno
== FRAME_POINTER_REGNUM
)
11573 i
= HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11575 SET_HARD_REG_BIT (newpat_used_regs
, regno
+ i
);
11581 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11583 register rtx testreg
= SET_DEST (x
);
11585 while (GET_CODE (testreg
) == SUBREG
11586 || GET_CODE (testreg
) == ZERO_EXTRACT
11587 || GET_CODE (testreg
) == SIGN_EXTRACT
11588 || GET_CODE (testreg
) == STRICT_LOW_PART
)
11589 testreg
= XEXP (testreg
, 0);
11591 if (GET_CODE (testreg
) == MEM
)
11592 mark_used_regs_combine (XEXP (testreg
, 0));
11594 mark_used_regs_combine (SET_SRC (x
));
11602 /* Recursively scan the operands of this expression. */
11605 register const char *fmt
= GET_RTX_FORMAT (code
);
11607 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
11610 mark_used_regs_combine (XEXP (x
, i
));
11611 else if (fmt
[i
] == 'E')
11615 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
11616 mark_used_regs_combine (XVECEXP (x
, i
, j
));
11623 /* Remove register number REGNO from the dead registers list of INSN.
11625 Return the note used to record the death, if there was one. */
11628 remove_death (regno
, insn
)
11632 register rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
11636 REG_N_DEATHS (regno
)--;
11637 remove_note (insn
, note
);
11643 /* For each register (hardware or pseudo) used within expression X, if its
11644 death is in an instruction with cuid between FROM_CUID (inclusive) and
11645 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11646 list headed by PNOTES.
11648 That said, don't move registers killed by maybe_kill_insn.
11650 This is done when X is being merged by combination into TO_INSN. These
11651 notes will then be distributed as needed. */
11654 move_deaths (x
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
)
11656 rtx maybe_kill_insn
;
11661 register const char *fmt
;
11662 register int len
, i
;
11663 register enum rtx_code code
= GET_CODE (x
);
11667 register int regno
= REGNO (x
);
11668 register rtx where_dead
= reg_last_death
[regno
];
11669 register rtx before_dead
, after_dead
;
11671 /* Don't move the register if it gets killed in between from and to */
11672 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
11673 && !reg_referenced_p (x
, maybe_kill_insn
))
11676 /* WHERE_DEAD could be a USE insn made by combine, so first we
11677 make sure that we have insns with valid INSN_CUID values. */
11678 before_dead
= where_dead
;
11679 while (before_dead
&& INSN_UID (before_dead
) > max_uid_cuid
)
11680 before_dead
= PREV_INSN (before_dead
);
11681 after_dead
= where_dead
;
11682 while (after_dead
&& INSN_UID (after_dead
) > max_uid_cuid
)
11683 after_dead
= NEXT_INSN (after_dead
);
11685 if (before_dead
&& after_dead
11686 && INSN_CUID (before_dead
) >= from_cuid
11687 && (INSN_CUID (after_dead
) < INSN_CUID (to_insn
)
11688 || (where_dead
!= after_dead
11689 && INSN_CUID (after_dead
) == INSN_CUID (to_insn
))))
11691 rtx note
= remove_death (regno
, where_dead
);
11693 /* It is possible for the call above to return 0. This can occur
11694 when reg_last_death points to I2 or I1 that we combined with.
11695 In that case make a new note.
11697 We must also check for the case where X is a hard register
11698 and NOTE is a death note for a range of hard registers
11699 including X. In that case, we must put REG_DEAD notes for
11700 the remaining registers in place of NOTE. */
11702 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
11703 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11704 > GET_MODE_SIZE (GET_MODE (x
))))
11706 int deadregno
= REGNO (XEXP (note
, 0));
11708 = (deadregno
+ HARD_REGNO_NREGS (deadregno
,
11709 GET_MODE (XEXP (note
, 0))));
11710 int ourend
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11713 for (i
= deadregno
; i
< deadend
; i
++)
11714 if (i
< regno
|| i
>= ourend
)
11715 REG_NOTES (where_dead
)
11716 = gen_rtx_EXPR_LIST (REG_DEAD
,
11717 gen_rtx_REG (reg_raw_mode
[i
], i
),
11718 REG_NOTES (where_dead
));
11720 /* If we didn't find any note, or if we found a REG_DEAD note that
11721 covers only part of the given reg, and we have a multi-reg hard
11722 register, then to be safe we must check for REG_DEAD notes
11723 for each register other than the first. They could have
11724 their own REG_DEAD notes lying around. */
11725 else if ((note
== 0
11727 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
11728 < GET_MODE_SIZE (GET_MODE (x
)))))
11729 && regno
< FIRST_PSEUDO_REGISTER
11730 && HARD_REGNO_NREGS (regno
, GET_MODE (x
)) > 1)
11732 int ourend
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11737 offset
= HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0)));
11741 for (i
= regno
+ offset
; i
< ourend
; i
++)
11742 move_deaths (gen_rtx_REG (reg_raw_mode
[i
], i
),
11743 maybe_kill_insn
, from_cuid
, to_insn
, &oldnotes
);
11746 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
11748 XEXP (note
, 1) = *pnotes
;
11752 *pnotes
= gen_rtx_EXPR_LIST (REG_DEAD
, x
, *pnotes
);
11754 REG_N_DEATHS (regno
)++;
11760 else if (GET_CODE (x
) == SET
)
11762 rtx dest
= SET_DEST (x
);
11764 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11766 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11767 that accesses one word of a multi-word item, some
11768 piece of everything register in the expression is used by
11769 this insn, so remove any old death. */
11771 if (GET_CODE (dest
) == ZERO_EXTRACT
11772 || GET_CODE (dest
) == STRICT_LOW_PART
11773 || (GET_CODE (dest
) == SUBREG
11774 && (((GET_MODE_SIZE (GET_MODE (dest
))
11775 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
11776 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
11777 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
11779 move_deaths (dest
, maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11783 /* If this is some other SUBREG, we know it replaces the entire
11784 value, so use that as the destination. */
11785 if (GET_CODE (dest
) == SUBREG
)
11786 dest
= SUBREG_REG (dest
);
11788 /* If this is a MEM, adjust deaths of anything used in the address.
11789 For a REG (the only other possibility), the entire value is
11790 being replaced so the old value is not used in this insn. */
11792 if (GET_CODE (dest
) == MEM
)
11793 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_cuid
,
11798 else if (GET_CODE (x
) == CLOBBER
)
11801 len
= GET_RTX_LENGTH (code
);
11802 fmt
= GET_RTX_FORMAT (code
);
11804 for (i
= 0; i
< len
; i
++)
11809 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
11810 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_cuid
,
11813 else if (fmt
[i
] == 'e')
11814 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_cuid
, to_insn
, pnotes
);
11818 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11819 pattern of an insn. X must be a REG. */
11822 reg_bitfield_target_p (x
, body
)
11828 if (GET_CODE (body
) == SET
)
11830 rtx dest
= SET_DEST (body
);
11832 int regno
, tregno
, endregno
, endtregno
;
11834 if (GET_CODE (dest
) == ZERO_EXTRACT
)
11835 target
= XEXP (dest
, 0);
11836 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
11837 target
= SUBREG_REG (XEXP (dest
, 0));
11841 if (GET_CODE (target
) == SUBREG
)
11842 target
= SUBREG_REG (target
);
11844 if (GET_CODE (target
) != REG
)
11847 tregno
= REGNO (target
), regno
= REGNO (x
);
11848 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
11849 return target
== x
;
11851 endtregno
= tregno
+ HARD_REGNO_NREGS (tregno
, GET_MODE (target
));
11852 endregno
= regno
+ HARD_REGNO_NREGS (regno
, GET_MODE (x
));
11854 return endregno
> tregno
&& regno
< endtregno
;
11857 else if (GET_CODE (body
) == PARALLEL
)
11858 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
11859 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
11865 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11866 as appropriate. I3 and I2 are the insns resulting from the combination
11867 insns including FROM (I2 may be zero).
11869 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11870 not need REG_DEAD notes because they are being substituted for. This
11871 saves searching in the most common cases.
11873 Each note in the list is either ignored or placed on some insns, depending
11874 on the type of note. */
11877 distribute_notes (notes
, from_insn
, i3
, i2
, elim_i2
, elim_i1
)
11881 rtx elim_i2
, elim_i1
;
11883 rtx note
, next_note
;
11886 for (note
= notes
; note
; note
= next_note
)
11888 rtx place
= 0, place2
= 0;
11890 /* If this NOTE references a pseudo register, ensure it references
11891 the latest copy of that register. */
11892 if (XEXP (note
, 0) && GET_CODE (XEXP (note
, 0)) == REG
11893 && REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
)
11894 XEXP (note
, 0) = regno_reg_rtx
[REGNO (XEXP (note
, 0))];
11896 next_note
= XEXP (note
, 1);
11897 switch (REG_NOTE_KIND (note
))
11900 case REG_EXEC_COUNT
:
11901 /* Doesn't matter much where we put this, as long as it's somewhere.
11902 It is preferable to keep these notes on branches, which is most
11903 likely to be i3. */
11907 case REG_EH_REGION
:
11908 case REG_EH_RETHROW
:
11909 /* These notes must remain with the call. It should not be
11910 possible for both I2 and I3 to be a call. */
11911 if (GET_CODE (i3
) == CALL_INSN
)
11913 else if (i2
&& GET_CODE (i2
) == CALL_INSN
)
11920 /* Any clobbers for i3 may still exist, and so we must process
11921 REG_UNUSED notes from that insn.
11923 Any clobbers from i2 or i1 can only exist if they were added by
11924 recog_for_combine. In that case, recog_for_combine created the
11925 necessary REG_UNUSED notes. Trying to keep any original
11926 REG_UNUSED notes from these insns can cause incorrect output
11927 if it is for the same register as the original i3 dest.
11928 In that case, we will notice that the register is set in i3,
11929 and then add a REG_UNUSED note for the destination of i3, which
11930 is wrong. However, it is possible to have REG_UNUSED notes from
11931 i2 or i1 for register which were both used and clobbered, so
11932 we keep notes from i2 or i1 if they will turn into REG_DEAD
11935 /* If this register is set or clobbered in I3, put the note there
11936 unless there is one already. */
11937 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
11939 if (from_insn
!= i3
)
11942 if (! (GET_CODE (XEXP (note
, 0)) == REG
11943 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
11944 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
11947 /* Otherwise, if this register is used by I3, then this register
11948 now dies here, so we must put a REG_DEAD note here unless there
11950 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
11951 && ! (GET_CODE (XEXP (note
, 0)) == REG
11952 ? find_regno_note (i3
, REG_DEAD
, REGNO (XEXP (note
, 0)))
11953 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
11955 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
11964 /* These notes say something about results of an insn. We can
11965 only support them if they used to be on I3 in which case they
11966 remain on I3. Otherwise they are ignored.
11968 If the note refers to an expression that is not a constant, we
11969 must also ignore the note since we cannot tell whether the
11970 equivalence is still true. It might be possible to do
11971 slightly better than this (we only have a problem if I2DEST
11972 or I1DEST is present in the expression), but it doesn't
11973 seem worth the trouble. */
11975 if (from_insn
== i3
11976 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
11981 case REG_NO_CONFLICT
:
11982 /* These notes say something about how a register is used. They must
11983 be present on any use of the register in I2 or I3. */
11984 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
11987 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
11997 /* This can show up in several ways -- either directly in the
11998 pattern, or hidden off in the constant pool with (or without?)
11999 a REG_EQUAL note. */
12000 /* ??? Ignore the without-reg_equal-note problem for now. */
12001 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
12002 || ((tem
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
12003 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12004 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0)))
12008 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
12009 || ((tem
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
12010 && GET_CODE (XEXP (tem
, 0)) == LABEL_REF
12011 && XEXP (XEXP (tem
, 0), 0) == XEXP (note
, 0))))
12021 /* It is too much trouble to try to see if this note is still
12022 correct in all situations. It is better to simply delete it. */
12026 /* If the insn previously containing this note still exists,
12027 put it back where it was. Otherwise move it to the previous
12028 insn. Adjust the corresponding REG_LIBCALL note. */
12029 if (GET_CODE (from_insn
) != NOTE
)
12033 tem
= find_reg_note (XEXP (note
, 0), REG_LIBCALL
, NULL_RTX
);
12034 place
= prev_real_insn (from_insn
);
12036 XEXP (tem
, 0) = place
;
12041 /* This is handled similarly to REG_RETVAL. */
12042 if (GET_CODE (from_insn
) != NOTE
)
12046 tem
= find_reg_note (XEXP (note
, 0), REG_RETVAL
, NULL_RTX
);
12047 place
= next_real_insn (from_insn
);
12049 XEXP (tem
, 0) = place
;
12054 /* If the register is used as an input in I3, it dies there.
12055 Similarly for I2, if it is non-zero and adjacent to I3.
12057 If the register is not used as an input in either I3 or I2
12058 and it is not one of the registers we were supposed to eliminate,
12059 there are two possibilities. We might have a non-adjacent I2
12060 or we might have somehow eliminated an additional register
12061 from a computation. For example, we might have had A & B where
12062 we discover that B will always be zero. In this case we will
12063 eliminate the reference to A.
12065 In both cases, we must search to see if we can find a previous
12066 use of A and put the death note there. */
12069 && GET_CODE (from_insn
) == CALL_INSN
12070 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
12072 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
12074 else if (i2
!= 0 && next_nonnote_insn (i2
) == i3
12075 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12078 if (XEXP (note
, 0) == elim_i2
|| XEXP (note
, 0) == elim_i1
)
12083 basic_block bb
= BASIC_BLOCK (this_basic_block
);
12085 for (tem
= PREV_INSN (i3
); place
== 0; tem
= PREV_INSN (tem
))
12087 if (GET_RTX_CLASS (GET_CODE (tem
)) != 'i')
12089 if (tem
== bb
->head
)
12094 /* If the register is being set at TEM, see if that is all
12095 TEM is doing. If so, delete TEM. Otherwise, make this
12096 into a REG_UNUSED note instead. */
12097 if (reg_set_p (XEXP (note
, 0), PATTERN (tem
)))
12099 rtx set
= single_set (tem
);
12100 rtx inner_dest
= 0;
12102 rtx cc0_setter
= NULL_RTX
;
12106 for (inner_dest
= SET_DEST (set
);
12107 GET_CODE (inner_dest
) == STRICT_LOW_PART
12108 || GET_CODE (inner_dest
) == SUBREG
12109 || GET_CODE (inner_dest
) == ZERO_EXTRACT
;
12110 inner_dest
= XEXP (inner_dest
, 0))
12113 /* Verify that it was the set, and not a clobber that
12114 modified the register.
12116 CC0 targets must be careful to maintain setter/user
12117 pairs. If we cannot delete the setter due to side
12118 effects, mark the user with an UNUSED note instead
12121 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
12122 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
12124 && (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
12125 || ((cc0_setter
= prev_cc0_setter (tem
)) != NULL
12126 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))
12130 /* Move the notes and links of TEM elsewhere.
12131 This might delete other dead insns recursively.
12132 First set the pattern to something that won't use
12135 PATTERN (tem
) = pc_rtx
;
12137 distribute_notes (REG_NOTES (tem
), tem
, tem
,
12138 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12139 distribute_links (LOG_LINKS (tem
));
12141 PUT_CODE (tem
, NOTE
);
12142 NOTE_LINE_NUMBER (tem
) = NOTE_INSN_DELETED
;
12143 NOTE_SOURCE_FILE (tem
) = 0;
12146 /* Delete the setter too. */
12149 PATTERN (cc0_setter
) = pc_rtx
;
12151 distribute_notes (REG_NOTES (cc0_setter
),
12152 cc0_setter
, cc0_setter
,
12153 NULL_RTX
, NULL_RTX
, NULL_RTX
);
12154 distribute_links (LOG_LINKS (cc0_setter
));
12156 PUT_CODE (cc0_setter
, NOTE
);
12157 NOTE_LINE_NUMBER (cc0_setter
)
12158 = NOTE_INSN_DELETED
;
12159 NOTE_SOURCE_FILE (cc0_setter
) = 0;
12163 /* If the register is both set and used here, put the
12164 REG_DEAD note here, but place a REG_UNUSED note
12165 here too unless there already is one. */
12166 else if (reg_referenced_p (XEXP (note
, 0),
12171 if (! find_regno_note (tem
, REG_UNUSED
,
12172 REGNO (XEXP (note
, 0))))
12174 = gen_rtx_EXPR_LIST (REG_UNUSED
, XEXP (note
, 0),
12179 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
12181 /* If there isn't already a REG_UNUSED note, put one
12183 if (! find_regno_note (tem
, REG_UNUSED
,
12184 REGNO (XEXP (note
, 0))))
12189 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem
))
12190 || (GET_CODE (tem
) == CALL_INSN
12191 && find_reg_fusage (tem
, USE
, XEXP (note
, 0))))
12195 /* If we are doing a 3->2 combination, and we have a
12196 register which formerly died in i3 and was not used
12197 by i2, which now no longer dies in i3 and is used in
12198 i2 but does not die in i2, and place is between i2
12199 and i3, then we may need to move a link from place to
12201 if (i2
&& INSN_UID (place
) <= max_uid_cuid
12202 && INSN_CUID (place
) > INSN_CUID (i2
)
12203 && from_insn
&& INSN_CUID (from_insn
) > INSN_CUID (i2
)
12204 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
12206 rtx links
= LOG_LINKS (place
);
12207 LOG_LINKS (place
) = 0;
12208 distribute_links (links
);
12213 if (tem
== bb
->head
)
12217 /* We haven't found an insn for the death note and it
12218 is still a REG_DEAD note, but we have hit the beginning
12219 of the block. If the existing life info says the reg
12220 was dead, there's nothing left to do. Otherwise, we'll
12221 need to do a global life update after combine. */
12222 if (REG_NOTE_KIND (note
) == REG_DEAD
&& place
== 0)
12224 int regno
= REGNO (XEXP (note
, 0));
12225 if (REGNO_REG_SET_P (bb
->global_live_at_start
, regno
))
12227 SET_BIT (refresh_blocks
, this_basic_block
);
12233 /* If the register is set or already dead at PLACE, we needn't do
12234 anything with this note if it is still a REG_DEAD note.
12235 We can here if it is set at all, not if is it totally replace,
12236 which is what `dead_or_set_p' checks, so also check for it being
12239 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
12241 int regno
= REGNO (XEXP (note
, 0));
12243 if (dead_or_set_p (place
, XEXP (note
, 0))
12244 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
12246 /* Unless the register previously died in PLACE, clear
12247 reg_last_death. [I no longer understand why this is
12249 if (reg_last_death
[regno
] != place
)
12250 reg_last_death
[regno
] = 0;
12254 reg_last_death
[regno
] = place
;
12256 /* If this is a death note for a hard reg that is occupying
12257 multiple registers, ensure that we are still using all
12258 parts of the object. If we find a piece of the object
12259 that is unused, we must add a USE for that piece before
12260 PLACE and put the appropriate REG_DEAD note on it.
12262 An alternative would be to put a REG_UNUSED for the pieces
12263 on the insn that set the register, but that can't be done if
12264 it is not in the same block. It is simpler, though less
12265 efficient, to add the USE insns. */
12267 if (place
&& regno
< FIRST_PSEUDO_REGISTER
12268 && HARD_REGNO_NREGS (regno
, GET_MODE (XEXP (note
, 0))) > 1)
12271 = regno
+ HARD_REGNO_NREGS (regno
,
12272 GET_MODE (XEXP (note
, 0)));
12276 for (i
= regno
; i
< endregno
; i
++)
12277 if (! refers_to_regno_p (i
, i
+ 1, PATTERN (place
), 0)
12278 && ! find_regno_fusage (place
, USE
, i
))
12280 rtx piece
= gen_rtx_REG (reg_raw_mode
[i
], i
);
12283 /* See if we already placed a USE note for this
12284 register in front of PLACE. */
12286 GET_CODE (PREV_INSN (p
)) == INSN
12287 && GET_CODE (PATTERN (PREV_INSN (p
))) == USE
;
12289 if (rtx_equal_p (piece
,
12290 XEXP (PATTERN (PREV_INSN (p
)), 0)))
12299 = emit_insn_before (gen_rtx_USE (VOIDmode
,
12302 REG_NOTES (use_insn
)
12303 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
,
12304 REG_NOTES (use_insn
));
12310 /* Check for the case where the register dying partially
12311 overlaps the register set by this insn. */
12313 for (i
= regno
; i
< endregno
; i
++)
12314 if (dead_or_set_regno_p (place
, i
))
12322 /* Put only REG_DEAD notes for pieces that are
12323 still used and that are not already dead or set. */
12325 for (i
= regno
; i
< endregno
; i
++)
12327 rtx piece
= gen_rtx_REG (reg_raw_mode
[i
], i
);
12329 if ((reg_referenced_p (piece
, PATTERN (place
))
12330 || (GET_CODE (place
) == CALL_INSN
12331 && find_reg_fusage (place
, USE
, piece
)))
12332 && ! dead_or_set_p (place
, piece
)
12333 && ! reg_bitfield_target_p (piece
,
12336 = gen_rtx_EXPR_LIST (REG_DEAD
, piece
,
12337 REG_NOTES (place
));
12347 /* Any other notes should not be present at this point in the
12354 XEXP (note
, 1) = REG_NOTES (place
);
12355 REG_NOTES (place
) = note
;
12357 else if ((REG_NOTE_KIND (note
) == REG_DEAD
12358 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12359 && GET_CODE (XEXP (note
, 0)) == REG
)
12360 REG_N_DEATHS (REGNO (XEXP (note
, 0)))--;
12364 if ((REG_NOTE_KIND (note
) == REG_DEAD
12365 || REG_NOTE_KIND (note
) == REG_UNUSED
)
12366 && GET_CODE (XEXP (note
, 0)) == REG
)
12367 REG_N_DEATHS (REGNO (XEXP (note
, 0)))++;
12369 REG_NOTES (place2
) = gen_rtx_fmt_ee (GET_CODE (note
),
12370 REG_NOTE_KIND (note
),
12372 REG_NOTES (place2
));
12377 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12378 I3, I2, and I1 to new locations. This is also called in one case to
12379 add a link pointing at I3 when I3's destination is changed. */
12382 distribute_links (links
)
12385 rtx link
, next_link
;
12387 for (link
= links
; link
; link
= next_link
)
12393 next_link
= XEXP (link
, 1);
12395 /* If the insn that this link points to is a NOTE or isn't a single
12396 set, ignore it. In the latter case, it isn't clear what we
12397 can do other than ignore the link, since we can't tell which
12398 register it was for. Such links wouldn't be used by combine
12401 It is not possible for the destination of the target of the link to
12402 have been changed by combine. The only potential of this is if we
12403 replace I3, I2, and I1 by I3 and I2. But in that case the
12404 destination of I2 also remains unchanged. */
12406 if (GET_CODE (XEXP (link
, 0)) == NOTE
12407 || (set
= single_set (XEXP (link
, 0))) == 0)
12410 reg
= SET_DEST (set
);
12411 while (GET_CODE (reg
) == SUBREG
|| GET_CODE (reg
) == ZERO_EXTRACT
12412 || GET_CODE (reg
) == SIGN_EXTRACT
12413 || GET_CODE (reg
) == STRICT_LOW_PART
)
12414 reg
= XEXP (reg
, 0);
12416 /* A LOG_LINK is defined as being placed on the first insn that uses
12417 a register and points to the insn that sets the register. Start
12418 searching at the next insn after the target of the link and stop
12419 when we reach a set of the register or the end of the basic block.
12421 Note that this correctly handles the link that used to point from
12422 I3 to I2. Also note that not much searching is typically done here
12423 since most links don't point very far away. */
12425 for (insn
= NEXT_INSN (XEXP (link
, 0));
12426 (insn
&& (this_basic_block
== n_basic_blocks
- 1
12427 || BLOCK_HEAD (this_basic_block
+ 1) != insn
));
12428 insn
= NEXT_INSN (insn
))
12429 if (GET_RTX_CLASS (GET_CODE (insn
)) == 'i'
12430 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
12432 if (reg_referenced_p (reg
, PATTERN (insn
)))
12436 else if (GET_CODE (insn
) == CALL_INSN
12437 && find_reg_fusage (insn
, USE
, reg
))
12443 /* If we found a place to put the link, place it there unless there
12444 is already a link to the same insn as LINK at that point. */
12450 for (link2
= LOG_LINKS (place
); link2
; link2
= XEXP (link2
, 1))
12451 if (XEXP (link2
, 0) == XEXP (link
, 0))
12456 XEXP (link
, 1) = LOG_LINKS (place
);
12457 LOG_LINKS (place
) = link
;
12459 /* Set added_links_insn to the earliest insn we added a
12461 if (added_links_insn
== 0
12462 || INSN_CUID (added_links_insn
) > INSN_CUID (place
))
12463 added_links_insn
= place
;
12469 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12475 while (insn
!= 0 && INSN_UID (insn
) > max_uid_cuid
12476 && GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == USE
)
12477 insn
= NEXT_INSN (insn
);
12479 if (INSN_UID (insn
) > max_uid_cuid
)
12482 return INSN_CUID (insn
);
12486 dump_combine_stats (file
)
12491 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12492 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
12496 dump_combine_total_stats (file
)
12501 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12502 total_attempts
, total_merges
, total_extras
, total_successes
);