1 /* Code for RTL transformations to satisfy insn constraints.
2 Copyright (C) 2010, 2011, 2012
3 Free Software Foundation, Inc.
4 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
23 /* This file contains code for 3 passes: constraint pass,
24 inheritance/split pass, and pass for undoing failed inheritance and
27 The major goal of constraint pass is to transform RTL to satisfy
28 insn and address constraints by:
29 o choosing insn alternatives;
30 o generating *reload insns* (or reloads in brief) and *reload
31 pseudos* which will get necessary hard registers later;
32 o substituting pseudos with equivalent values and removing the
33 instructions that initialized those pseudos.
35 The constraint pass has biggest and most complicated code in LRA.
36 There are a lot of important details like:
37 o reuse of input reload pseudos to simplify reload pseudo
39 o some heuristics to choose insn alternative to improve the
43 The pass is mimicking former reload pass in alternative choosing
44 because the reload pass is oriented to current machine description
45 model. It might be changed if the machine description model is
48 There is special code for preventing all LRA and this pass cycling
51 On the first iteration of the pass we process every instruction and
52 choose an alternative for each one. On subsequent iterations we try
53 to avoid reprocessing instructions if we can be sure that the old
54 choice is still valid.
56 The inheritance/spilt pass is to transform code to achieve
57 ineheritance and live range splitting. It is done on backward
60 The inheritance optimization goal is to reuse values in hard
61 registers. There is analogous optimization in old reload pass. The
62 inheritance is achieved by following transformation:
64 reload_p1 <- p reload_p1 <- p
65 ... new_p <- reload_p1
67 reload_p2 <- p reload_p2 <- new_p
69 where p is spilled and not changed between the insns. Reload_p1 is
70 also called *original pseudo* and new_p is called *inheritance
73 The subsequent assignment pass will try to assign the same (or
74 another if it is not possible) hard register to new_p as to
75 reload_p1 or reload_p2.
77 If the assignment pass fails to assign a hard register to new_p,
78 this file will undo the inheritance and restore the original code.
79 This is because implementing the above sequence with a spilled
80 new_p would make the code much worse. The inheritance is done in
81 EBB scope. The above is just a simplified example to get an idea
82 of the inheritance as the inheritance is also done for non-reload
85 Splitting (transformation) is also done in EBB scope on the same
86 pass as the inheritance:
88 r <- ... or ... <- r r <- ... or ... <- r
89 ... s <- r (new insn -- save)
91 ... r <- s (new insn -- restore)
94 The *split pseudo* s is assigned to the hard register of the
95 original pseudo or hard register r.
98 o In EBBs with high register pressure for global pseudos (living
99 in at least 2 BBs) and assigned to hard registers when there
100 are more one reloads needing the hard registers;
101 o for pseudos needing save/restore code around calls.
103 If the split pseudo still has the same hard register as the
104 original pseudo after the subsequent assignment pass or the
105 original pseudo was split, the opposite transformation is done on
106 the same pass for undoing inheritance. */
112 #include "coretypes.h"
114 #include "hard-reg-set.h"
118 #include "insn-config.h"
119 #include "insn-codes.h"
122 #include "addresses.h"
124 #include "function.h"
126 #include "basic-block.h"
131 #include "rtl-error.h"
134 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current
135 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted
137 static int bb_reload_num
;
139 /* The current insn being processed and corresponding its data (basic
140 block, the insn data, the insn static data, and the mode of each
142 static rtx curr_insn
;
143 static basic_block curr_bb
;
144 static lra_insn_recog_data_t curr_id
;
145 static struct lra_static_insn_data
*curr_static_id
;
146 static enum machine_mode curr_operand_mode
[MAX_RECOG_OPERANDS
];
150 /* Start numbers for new registers and insns at the current constraints
152 static int new_regno_start
;
153 static int new_insn_uid_start
;
155 /* If LOC is nonnull, strip any outer subreg from it. */
157 strip_subreg (rtx
*loc
)
159 return loc
&& GET_CODE (*loc
) == SUBREG
? &SUBREG_REG (*loc
) : loc
;
162 /* Return hard regno of REGNO or if it is was not assigned to a hard
163 register, use a hard register from its allocno class. */
165 get_try_hard_regno (int regno
)
168 enum reg_class rclass
;
170 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
171 hard_regno
= lra_get_regno_hard_regno (regno
);
174 rclass
= lra_get_allocno_class (regno
);
175 if (rclass
== NO_REGS
)
177 return ira_class_hard_regs
[rclass
][0];
180 /* Return final hard regno (plus offset) which will be after
181 elimination. We do this for matching constraints because the final
182 hard regno could have a different class. */
184 get_final_hard_regno (int hard_regno
, int offset
)
188 hard_regno
= lra_get_elimination_hard_regno (hard_regno
);
189 return hard_regno
+ offset
;
192 /* Return hard regno of X after removing subreg and making
193 elimination. If X is not a register or subreg of register, return
194 -1. For pseudo use its assignment. */
196 get_hard_regno (rtx x
)
199 int offset
, hard_regno
;
202 if (GET_CODE (x
) == SUBREG
)
203 reg
= SUBREG_REG (x
);
206 if ((hard_regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
207 hard_regno
= lra_get_regno_hard_regno (hard_regno
);
211 if (GET_CODE (x
) == SUBREG
)
212 offset
+= subreg_regno_offset (hard_regno
, GET_MODE (reg
),
213 SUBREG_BYTE (x
), GET_MODE (x
));
214 return get_final_hard_regno (hard_regno
, offset
);
217 /* If REGNO is a hard register or has been allocated a hard register,
218 return the class of that register. If REGNO is a reload pseudo
219 created by the current constraints pass, return its allocno class.
220 Return NO_REGS otherwise. */
221 static enum reg_class
222 get_reg_class (int regno
)
226 if ((hard_regno
= regno
) >= FIRST_PSEUDO_REGISTER
)
227 hard_regno
= lra_get_regno_hard_regno (regno
);
230 hard_regno
= get_final_hard_regno (hard_regno
, 0);
231 return REGNO_REG_CLASS (hard_regno
);
233 if (regno
>= new_regno_start
)
234 return lra_get_allocno_class (regno
);
238 /* Return true if REG satisfies (or will satisfy) reg class constraint
239 CL. Use elimination first if REG is a hard register. If REG is a
240 reload pseudo created by this constraints pass, assume that it will
241 be allocated a hard register from its allocno class, but allow that
242 class to be narrowed to CL if it is currently a superset of CL.
244 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of
245 REGNO (reg), or NO_REGS if no change in its class was needed. */
247 in_class_p (rtx reg
, enum reg_class cl
, enum reg_class
*new_class
)
249 enum reg_class rclass
, common_class
;
250 enum machine_mode reg_mode
;
251 int class_size
, hard_regno
, nregs
, i
, j
;
252 int regno
= REGNO (reg
);
254 if (new_class
!= NULL
)
255 *new_class
= NO_REGS
;
256 if (regno
< FIRST_PSEUDO_REGISTER
)
259 rtx
*final_loc
= &final_reg
;
261 lra_eliminate_reg_if_possible (final_loc
);
262 return TEST_HARD_REG_BIT (reg_class_contents
[cl
], REGNO (*final_loc
));
264 reg_mode
= GET_MODE (reg
);
265 rclass
= get_reg_class (regno
);
266 if (regno
< new_regno_start
267 /* Do not allow the constraints for reload instructions to
268 influence the classes of new pseudos. These reloads are
269 typically moves that have many alternatives, and restricting
270 reload pseudos for one alternative may lead to situations
271 where other reload pseudos are no longer allocatable. */
272 || INSN_UID (curr_insn
) >= new_insn_uid_start
)
273 /* When we don't know what class will be used finally for reload
274 pseudos, we use ALL_REGS. */
275 return ((regno
>= new_regno_start
&& rclass
== ALL_REGS
)
276 || (rclass
!= NO_REGS
&& ira_class_subset_p
[rclass
][cl
]
277 && ! hard_reg_set_subset_p (reg_class_contents
[cl
],
278 lra_no_alloc_regs
)));
281 common_class
= ira_reg_class_subset
[rclass
][cl
];
282 if (new_class
!= NULL
)
283 *new_class
= common_class
;
284 if (hard_reg_set_subset_p (reg_class_contents
[common_class
],
287 /* Check that there are enough allocatable regs. */
288 class_size
= ira_class_hard_regs_num
[common_class
];
289 for (i
= 0; i
< class_size
; i
++)
291 hard_regno
= ira_class_hard_regs
[common_class
][i
];
292 nregs
= hard_regno_nregs
[hard_regno
][reg_mode
];
295 for (j
= 0; j
< nregs
; j
++)
296 if (TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
+ j
)
297 || ! TEST_HARD_REG_BIT (reg_class_contents
[common_class
],
307 /* Return true if REGNO satisfies a memory constraint. */
311 return get_reg_class (regno
) == NO_REGS
;
314 /* If we have decided to substitute X with another value, return that
315 value, otherwise return X. */
317 get_equiv_substitution (rtx x
)
322 if (! REG_P (x
) || (regno
= REGNO (x
)) < FIRST_PSEUDO_REGISTER
323 || ! ira_reg_equiv
[regno
].defined_p
324 || ! ira_reg_equiv
[regno
].profitable_p
325 || lra_get_regno_hard_regno (regno
) >= 0)
327 if ((res
= ira_reg_equiv
[regno
].memory
) != NULL_RTX
)
329 if ((res
= ira_reg_equiv
[regno
].constant
) != NULL_RTX
)
331 if ((res
= ira_reg_equiv
[regno
].invariant
) != NULL_RTX
)
336 /* Set up curr_operand_mode. */
338 init_curr_operand_mode (void)
340 int nop
= curr_static_id
->n_operands
;
341 for (int i
= 0; i
< nop
; i
++)
343 enum machine_mode mode
= GET_MODE (*curr_id
->operand_loc
[i
]);
344 if (mode
== VOIDmode
)
346 /* The .md mode for address operands is the mode of the
347 addressed value rather than the mode of the address itself. */
348 if (curr_id
->icode
>= 0 && curr_static_id
->operand
[i
].is_address
)
351 mode
= curr_static_id
->operand
[i
].mode
;
353 curr_operand_mode
[i
] = mode
;
359 /* The page contains code to reuse input reloads. */
361 /* Structure describes input reload of the current insns. */
364 /* Reloaded value. */
366 /* Reload pseudo used. */
370 /* The number of elements in the following array. */
371 static int curr_insn_input_reloads_num
;
372 /* Array containing info about input reloads. It is used to find the
373 same input reload and reuse the reload pseudo in this case. */
374 static struct input_reload curr_insn_input_reloads
[LRA_MAX_INSN_RELOADS
];
376 /* Initiate data concerning reuse of input reloads for the current
379 init_curr_insn_input_reloads (void)
381 curr_insn_input_reloads_num
= 0;
384 /* Change class of pseudo REGNO to NEW_CLASS. Print info about it
385 using TITLE. Output a new line if NL_P. */
387 change_class (int regno
, enum reg_class new_class
,
388 const char *title
, bool nl_p
)
390 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
);
391 if (lra_dump_file
!= NULL
)
392 fprintf (lra_dump_file
, "%s to class %s for r%d",
393 title
, reg_class_names
[new_class
], regno
);
394 setup_reg_classes (regno
, new_class
, NO_REGS
, new_class
);
395 if (lra_dump_file
!= NULL
&& nl_p
)
396 fprintf (lra_dump_file
, "\n");
399 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already
400 created input reload pseudo (only if TYPE is not OP_OUT). The
401 result pseudo is returned through RESULT_REG. Return TRUE if we
402 created a new pseudo, FALSE if we reused the already created input
403 reload pseudo. Use TITLE to describe new registers for debug
406 get_reload_reg (enum op_type type
, enum machine_mode mode
, rtx original
,
407 enum reg_class rclass
, const char *title
, rtx
*result_reg
)
410 enum reg_class new_class
;
415 = lra_create_new_reg_with_unique_value (mode
, original
, rclass
, title
);
418 for (i
= 0; i
< curr_insn_input_reloads_num
; i
++)
419 if (rtx_equal_p (curr_insn_input_reloads
[i
].input
, original
)
420 && in_class_p (curr_insn_input_reloads
[i
].reg
, rclass
, &new_class
))
422 lra_assert (! side_effects_p (original
));
423 *result_reg
= curr_insn_input_reloads
[i
].reg
;
424 regno
= REGNO (*result_reg
);
425 if (lra_dump_file
!= NULL
)
427 fprintf (lra_dump_file
, " Reuse r%d for reload ", regno
);
428 dump_value_slim (lra_dump_file
, original
, 1);
430 if (new_class
!= lra_get_allocno_class (regno
))
431 change_class (regno
, new_class
, ", change", false);
432 if (lra_dump_file
!= NULL
)
433 fprintf (lra_dump_file
, "\n");
436 *result_reg
= lra_create_new_reg (mode
, original
, rclass
, title
);
437 lra_assert (curr_insn_input_reloads_num
< LRA_MAX_INSN_RELOADS
);
438 curr_insn_input_reloads
[curr_insn_input_reloads_num
].input
= original
;
439 curr_insn_input_reloads
[curr_insn_input_reloads_num
++].reg
= *result_reg
;
445 /* The page contains code to extract memory address parts. */
447 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */
449 ok_for_index_p_nonstrict (rtx reg
)
451 unsigned regno
= REGNO (reg
);
453 return regno
>= FIRST_PSEUDO_REGISTER
|| REGNO_OK_FOR_INDEX_P (regno
);
456 /* A version of regno_ok_for_base_p for use here, when all pseudos
457 should count as OK. Arguments as for regno_ok_for_base_p. */
459 ok_for_base_p_nonstrict (rtx reg
, enum machine_mode mode
, addr_space_t as
,
460 enum rtx_code outer_code
, enum rtx_code index_code
)
462 unsigned regno
= REGNO (reg
);
464 if (regno
>= FIRST_PSEUDO_REGISTER
)
466 return ok_for_base_p_1 (regno
, mode
, as
, outer_code
, index_code
);
471 /* The page contains major code to choose the current insn alternative
472 and generate reloads for it. */
474 /* Return the offset from REGNO of the least significant register
477 This function is used to tell whether two registers satisfy
478 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if:
480 REGNO1 + lra_constraint_offset (REGNO1, MODE1)
481 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */
483 lra_constraint_offset (int regno
, enum machine_mode mode
)
485 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
486 if (WORDS_BIG_ENDIAN
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
487 && SCALAR_INT_MODE_P (mode
))
488 return hard_regno_nregs
[regno
][mode
] - 1;
492 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match
493 if they are the same hard reg, and has special hacks for
494 auto-increment and auto-decrement. This is specifically intended for
495 process_alt_operands to use in determining whether two operands
496 match. X is the operand whose number is the lower of the two.
498 It is supposed that X is the output operand and Y is the input
499 operand. Y_HARD_REGNO is the final hard regno of register Y or
500 register in subreg Y as we know it now. Otherwise, it is a
503 operands_match_p (rtx x
, rtx y
, int y_hard_regno
)
506 RTX_CODE code
= GET_CODE (x
);
511 if ((code
== REG
|| (code
== SUBREG
&& REG_P (SUBREG_REG (x
))))
512 && (REG_P (y
) || (GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
)))))
516 i
= get_hard_regno (x
);
520 if ((j
= y_hard_regno
) < 0)
523 i
+= lra_constraint_offset (i
, GET_MODE (x
));
524 j
+= lra_constraint_offset (j
, GET_MODE (y
));
529 /* If two operands must match, because they are really a single
530 operand of an assembler insn, then two post-increments are invalid
531 because the assembler insn would increment only once. On the
532 other hand, a post-increment matches ordinary indexing if the
533 post-increment is the output operand. */
534 if (code
== POST_DEC
|| code
== POST_INC
|| code
== POST_MODIFY
)
535 return operands_match_p (XEXP (x
, 0), y
, y_hard_regno
);
537 /* Two pre-increments are invalid because the assembler insn would
538 increment only once. On the other hand, a pre-increment matches
539 ordinary indexing if the pre-increment is the input operand. */
540 if (GET_CODE (y
) == PRE_DEC
|| GET_CODE (y
) == PRE_INC
541 || GET_CODE (y
) == PRE_MODIFY
)
542 return operands_match_p (x
, XEXP (y
, 0), -1);
546 if (code
== REG
&& GET_CODE (y
) == SUBREG
&& REG_P (SUBREG_REG (y
))
547 && x
== SUBREG_REG (y
))
549 if (GET_CODE (y
) == REG
&& code
== SUBREG
&& REG_P (SUBREG_REG (x
))
550 && SUBREG_REG (x
) == y
)
553 /* Now we have disposed of all the cases in which different rtx
555 if (code
!= GET_CODE (y
))
558 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */
559 if (GET_MODE (x
) != GET_MODE (y
))
568 return XEXP (x
, 0) == XEXP (y
, 0);
570 return XSTR (x
, 0) == XSTR (y
, 0);
576 /* Compare the elements. If any pair of corresponding elements fail
577 to match, return false for the whole things. */
579 fmt
= GET_RTX_FORMAT (code
);
580 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
586 if (XWINT (x
, i
) != XWINT (y
, i
))
591 if (XINT (x
, i
) != XINT (y
, i
))
596 val
= operands_match_p (XEXP (x
, i
), XEXP (y
, i
), -1);
605 if (XVECLEN (x
, i
) != XVECLEN (y
, i
))
607 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; --j
)
609 val
= operands_match_p (XVECEXP (x
, i
, j
), XVECEXP (y
, i
, j
), -1);
615 /* It is believed that rtx's at this level will never
616 contain anything but integers and other rtx's, except for
617 within LABEL_REFs and SYMBOL_REFs. */
625 /* True if X is a constant that can be forced into the constant pool.
626 MODE is the mode of the operand, or VOIDmode if not known. */
627 #define CONST_POOL_OK_P(MODE, X) \
628 ((MODE) != VOIDmode \
630 && GET_CODE (X) != HIGH \
631 && !targetm.cannot_force_const_mem (MODE, X))
633 /* True if C is a non-empty register class that has too few registers
634 to be safely used as a reload target class. */
635 #define SMALL_REGISTER_CLASS_P(C) \
636 (reg_class_size [(C)] == 1 \
637 || (reg_class_size [(C)] >= 1 && targetm.class_likely_spilled_p (C)))
639 /* If REG is a reload pseudo, try to make its class satisfying CL. */
641 narrow_reload_pseudo_class (rtx reg
, enum reg_class cl
)
643 enum reg_class rclass
;
645 /* Do not make more accurate class from reloads generated. They are
646 mostly moves with a lot of constraints. Making more accurate
647 class may results in very narrow class and impossibility of find
648 registers for several reloads of one insn. */
649 if (INSN_UID (curr_insn
) >= new_insn_uid_start
)
651 if (GET_CODE (reg
) == SUBREG
)
652 reg
= SUBREG_REG (reg
);
653 if (! REG_P (reg
) || (int) REGNO (reg
) < new_regno_start
)
655 if (in_class_p (reg
, cl
, &rclass
) && rclass
!= cl
)
656 change_class (REGNO (reg
), rclass
, " Change", true);
659 /* Generate reloads for matching OUT and INS (array of input operand
660 numbers with end marker -1) with reg class GOAL_CLASS. Add input
661 and output reloads correspondingly to the lists *BEFORE and
664 match_reload (signed char out
, signed char *ins
, enum reg_class goal_class
,
665 rtx
*before
, rtx
*after
)
668 rtx new_in_reg
, new_out_reg
, reg
, clobber
;
669 enum machine_mode inmode
, outmode
;
670 rtx in_rtx
= *curr_id
->operand_loc
[ins
[0]];
671 rtx out_rtx
= *curr_id
->operand_loc
[out
];
673 outmode
= curr_operand_mode
[out
];
674 inmode
= curr_operand_mode
[ins
[0]];
675 push_to_sequence (*before
);
676 if (inmode
!= outmode
)
678 if (GET_MODE_SIZE (inmode
) > GET_MODE_SIZE (outmode
))
681 = lra_create_new_reg_with_unique_value (inmode
, in_rtx
,
683 if (SCALAR_INT_MODE_P (inmode
))
684 new_out_reg
= gen_lowpart_SUBREG (outmode
, reg
);
686 new_out_reg
= gen_rtx_SUBREG (outmode
, reg
, 0);
687 /* If the input reg is dying here, we can use the same hard
688 register for REG and IN_RTX. We do it only for original
689 pseudos as reload pseudos can die although original
690 pseudos still live where reload pseudos dies. */
691 if (REG_P (in_rtx
) && (int) REGNO (in_rtx
) < lra_new_regno_start
692 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (in_rtx
)))
693 lra_reg_info
[REGNO (reg
)].val
= lra_reg_info
[REGNO (in_rtx
)].val
;
698 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
700 if (SCALAR_INT_MODE_P (outmode
))
701 new_in_reg
= gen_lowpart_SUBREG (inmode
, reg
);
703 new_in_reg
= gen_rtx_SUBREG (inmode
, reg
, 0);
704 /* NEW_IN_REG is non-paradoxical subreg. We don't want
705 NEW_OUT_REG living above. We add clobber clause for
706 this. This is just a temporary clobber. We can remove
707 it at the end of LRA work. */
708 clobber
= emit_clobber (new_out_reg
);
709 LRA_TEMP_CLOBBER_P (PATTERN (clobber
)) = 1;
710 if (GET_CODE (in_rtx
) == SUBREG
)
712 rtx subreg_reg
= SUBREG_REG (in_rtx
);
714 /* If SUBREG_REG is dying here and sub-registers IN_RTX
715 and NEW_IN_REG are similar, we can use the same hard
716 register for REG and SUBREG_REG. */
717 if (REG_P (subreg_reg
)
718 && (int) REGNO (subreg_reg
) < lra_new_regno_start
719 && GET_MODE (subreg_reg
) == outmode
720 && SUBREG_BYTE (in_rtx
) == SUBREG_BYTE (new_in_reg
)
721 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (subreg_reg
)))
722 lra_reg_info
[REGNO (reg
)].val
723 = lra_reg_info
[REGNO (subreg_reg
)].val
;
729 /* Pseudos have values -- see comments for lra_reg_info.
730 Different pseudos with the same value do not conflict even if
731 they live in the same place. When we create a pseudo we
732 assign value of original pseudo (if any) from which we
733 created the new pseudo. If we create the pseudo from the
734 input pseudo, the new pseudo will no conflict with the input
735 pseudo which is wrong when the input pseudo lives after the
736 insn and as the new pseudo value is changed by the insn
737 output. Therefore we create the new pseudo from the output.
739 We cannot reuse the current output register because we might
740 have a situation like "a <- a op b", where the constraints
741 force the second input operand ("b") to match the output
742 operand ("a"). "b" must then be copied into a new register
743 so that it doesn't clobber the current value of "a". */
745 new_in_reg
= new_out_reg
746 = lra_create_new_reg_with_unique_value (outmode
, out_rtx
,
749 /* In and out operand can be got from transformations before
750 processing insn constraints. One example of such transformations
751 is subreg reloading (see function simplify_operand_subreg). The
752 new pseudos created by the transformations might have inaccurate
753 class (ALL_REGS) and we should make their classes more
755 narrow_reload_pseudo_class (in_rtx
, goal_class
);
756 narrow_reload_pseudo_class (out_rtx
, goal_class
);
757 lra_emit_move (copy_rtx (new_in_reg
), in_rtx
);
758 *before
= get_insns ();
760 for (i
= 0; (in
= ins
[i
]) >= 0; i
++)
763 (GET_MODE (*curr_id
->operand_loc
[in
]) == VOIDmode
764 || GET_MODE (new_in_reg
) == GET_MODE (*curr_id
->operand_loc
[in
]));
765 *curr_id
->operand_loc
[in
] = new_in_reg
;
767 lra_update_dups (curr_id
, ins
);
768 if (find_reg_note (curr_insn
, REG_UNUSED
, out_rtx
) == NULL_RTX
)
771 lra_emit_move (out_rtx
, copy_rtx (new_out_reg
));
773 *after
= get_insns ();
776 *curr_id
->operand_loc
[out
] = new_out_reg
;
777 lra_update_dup (curr_id
, out
);
780 /* Return register class which is union of all reg classes in insn
781 constraint alternative string starting with P. */
782 static enum reg_class
783 reg_class_from_constraints (const char *p
)
786 enum reg_class op_class
= NO_REGS
;
789 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
796 op_class
= (reg_class_subunion
797 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
803 op_class
= reg_class_subunion
[op_class
][GENERAL_REGS
];
807 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
809 #ifdef EXTRA_CONSTRAINT_STR
810 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
812 = (reg_class_subunion
813 [op_class
][base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
820 = reg_class_subunion
[op_class
][REG_CLASS_FROM_CONSTRAINT (c
, p
)];
823 while ((p
+= len
), c
);
827 /* If OP is a register, return the class of the register as per
828 get_reg_class, otherwise return NO_REGS. */
829 static inline enum reg_class
830 get_op_class (rtx op
)
832 return REG_P (op
) ? get_reg_class (REGNO (op
)) : NO_REGS
;
835 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo
836 otherwise. If modes of MEM_PSEUDO and VAL are different, use
837 SUBREG for VAL to make them equal. */
839 emit_spill_move (bool to_p
, rtx mem_pseudo
, rtx val
)
841 if (GET_MODE (mem_pseudo
) != GET_MODE (val
))
842 val
= gen_rtx_SUBREG (GET_MODE (mem_pseudo
),
843 GET_CODE (val
) == SUBREG
? SUBREG_REG (val
) : val
,
846 ? gen_move_insn (mem_pseudo
, val
)
847 : gen_move_insn (val
, mem_pseudo
));
850 /* Process a special case insn (register move), return true if we
851 don't need to process it anymore. Return that RTL was changed
852 through CHANGE_P and macro SECONDARY_MEMORY_NEEDED says to use
853 secondary memory through SEC_MEM_P. */
855 check_and_process_move (bool *change_p
, bool *sec_mem_p
)
858 rtx set
, dest
, src
, dreg
, sreg
, old_sreg
, new_reg
, before
, scratch_reg
;
859 enum reg_class dclass
, sclass
, secondary_class
;
860 enum machine_mode sreg_mode
;
861 secondary_reload_info sri
;
863 *sec_mem_p
= *change_p
= false;
864 if ((set
= single_set (curr_insn
)) == NULL
)
866 dreg
= dest
= SET_DEST (set
);
867 sreg
= src
= SET_SRC (set
);
868 /* Quick check on the right move insn which does not need
870 if ((dclass
= get_op_class (dest
)) != NO_REGS
871 && (sclass
= get_op_class (src
)) != NO_REGS
872 /* The backend guarantees that register moves of cost 2 never
874 && targetm
.register_move_cost (GET_MODE (src
), dclass
, sclass
) == 2)
876 if (GET_CODE (dest
) == SUBREG
)
877 dreg
= SUBREG_REG (dest
);
878 if (GET_CODE (src
) == SUBREG
)
879 sreg
= SUBREG_REG (src
);
880 if (! REG_P (dreg
) || ! REG_P (sreg
))
882 sclass
= dclass
= NO_REGS
;
883 dreg
= get_equiv_substitution (dreg
);
885 dclass
= get_reg_class (REGNO (dreg
));
886 if (dclass
== ALL_REGS
)
887 /* ALL_REGS is used for new pseudos created by transformations
888 like reload of SUBREG_REG (see function
889 simplify_operand_subreg). We don't know their class yet. We
890 should figure out the class from processing the insn
891 constraints not in this fast path function. Even if ALL_REGS
892 were a right class for the pseudo, secondary_... hooks usually
893 are not define for ALL_REGS. */
895 sreg_mode
= GET_MODE (sreg
);
897 sreg
= get_equiv_substitution (sreg
);
899 sclass
= get_reg_class (REGNO (sreg
));
900 if (sclass
== ALL_REGS
)
901 /* See comments above. */
903 #ifdef SECONDARY_MEMORY_NEEDED
904 if (dclass
!= NO_REGS
&& sclass
!= NO_REGS
905 && SECONDARY_MEMORY_NEEDED (sclass
, dclass
, GET_MODE (src
)))
912 sri
.icode
= CODE_FOR_nothing
;
914 secondary_class
= NO_REGS
;
915 /* Set up hard register for a reload pseudo for hook
916 secondary_reload because some targets just ignore unassigned
917 pseudos in the hook. */
918 if (dclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (dreg
)) < 0)
920 dregno
= REGNO (dreg
);
921 reg_renumber
[dregno
] = ira_class_hard_regs
[dclass
][0];
925 if (sclass
!= NO_REGS
&& lra_get_regno_hard_regno (REGNO (sreg
)) < 0)
927 sregno
= REGNO (sreg
);
928 reg_renumber
[sregno
] = ira_class_hard_regs
[sclass
][0];
932 if (sclass
!= NO_REGS
)
934 = (enum reg_class
) targetm
.secondary_reload (false, dest
,
935 (reg_class_t
) sclass
,
936 GET_MODE (src
), &sri
);
937 if (sclass
== NO_REGS
938 || ((secondary_class
!= NO_REGS
|| sri
.icode
!= CODE_FOR_nothing
)
939 && dclass
!= NO_REGS
))
941 enum reg_class old_sclass
= secondary_class
;
942 secondary_reload_info old_sri
= sri
;
945 sri
.icode
= CODE_FOR_nothing
;
948 = (enum reg_class
) targetm
.secondary_reload (true, sreg
,
949 (reg_class_t
) dclass
,
951 /* Check the target hook consistency. */
953 ((secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
954 || (old_sclass
== NO_REGS
&& old_sri
.icode
== CODE_FOR_nothing
)
955 || (secondary_class
== old_sclass
&& sri
.icode
== old_sri
.icode
));
958 reg_renumber
[sregno
] = -1;
960 reg_renumber
[dregno
] = -1;
961 if (secondary_class
== NO_REGS
&& sri
.icode
== CODE_FOR_nothing
)
965 if (secondary_class
!= NO_REGS
)
966 new_reg
= lra_create_new_reg_with_unique_value (sreg_mode
, NULL_RTX
,
970 if (old_sreg
!= sreg
)
971 sreg
= copy_rtx (sreg
);
972 if (sri
.icode
== CODE_FOR_nothing
)
973 lra_emit_move (new_reg
, sreg
);
976 enum reg_class scratch_class
;
978 scratch_class
= (reg_class_from_constraints
979 (insn_data
[sri
.icode
].operand
[2].constraint
));
980 scratch_reg
= (lra_create_new_reg_with_unique_value
981 (insn_data
[sri
.icode
].operand
[2].mode
, NULL_RTX
,
982 scratch_class
, "scratch"));
983 emit_insn (GEN_FCN (sri
.icode
) (new_reg
!= NULL_RTX
? new_reg
: dest
,
986 before
= get_insns ();
988 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Inserting the move");
989 if (new_reg
!= NULL_RTX
)
991 if (GET_CODE (src
) == SUBREG
)
992 SUBREG_REG (src
) = new_reg
;
994 SET_SRC (set
) = new_reg
;
998 if (lra_dump_file
!= NULL
)
1000 fprintf (lra_dump_file
, "Deleting move %u\n", INSN_UID (curr_insn
));
1001 dump_insn_slim (lra_dump_file
, curr_insn
);
1003 lra_set_insn_deleted (curr_insn
);
1009 /* The following data describe the result of process_alt_operands.
1010 The data are used in curr_insn_transform to generate reloads. */
1012 /* The chosen reg classes which should be used for the corresponding
1014 static enum reg_class goal_alt
[MAX_RECOG_OPERANDS
];
1015 /* True if the operand should be the same as another operand and that
1016 other operand does not need a reload. */
1017 static bool goal_alt_match_win
[MAX_RECOG_OPERANDS
];
1018 /* True if the operand does not need a reload. */
1019 static bool goal_alt_win
[MAX_RECOG_OPERANDS
];
1020 /* True if the operand can be offsetable memory. */
1021 static bool goal_alt_offmemok
[MAX_RECOG_OPERANDS
];
1022 /* The number of an operand to which given operand can be matched to. */
1023 static int goal_alt_matches
[MAX_RECOG_OPERANDS
];
1024 /* The number of elements in the following array. */
1025 static int goal_alt_dont_inherit_ops_num
;
1026 /* Numbers of operands whose reload pseudos should not be inherited. */
1027 static int goal_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1028 /* True if the insn commutative operands should be swapped. */
1029 static bool goal_alt_swapped
;
1030 /* The chosen insn alternative. */
1031 static int goal_alt_number
;
1033 /* The following five variables are used to choose the best insn
1034 alternative. They reflect final characteristics of the best
1037 /* Number of necessary reloads and overall cost reflecting the
1038 previous value and other unpleasantness of the best alternative. */
1039 static int best_losers
, best_overall
;
1040 /* Number of small register classes used for operands of the best
1042 static int best_small_class_operands_num
;
1043 /* Overall number hard registers used for reloads. For example, on
1044 some targets we need 2 general registers to reload DFmode and only
1045 one floating point register. */
1046 static int best_reload_nregs
;
1047 /* Overall number reflecting distances of previous reloading the same
1048 value. The distances are counted from the current BB start. It is
1049 used to improve inheritance chances. */
1050 static int best_reload_sum
;
1052 /* True if the current insn should have no correspondingly input or
1054 static bool no_input_reloads_p
, no_output_reloads_p
;
1056 /* True if we swapped the commutative operands in the current
1058 static int curr_swapped
;
1060 /* Arrange for address element *LOC to be a register of class CL.
1061 Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an
1062 automodified value; handle that case by adding the required output
1063 reloads to list AFTER. Return true if the RTL was changed. */
1065 process_addr_reg (rtx
*loc
, rtx
*before
, rtx
*after
, enum reg_class cl
)
1068 enum reg_class rclass
, new_class
;
1071 enum machine_mode mode
;
1072 bool before_p
= false;
1074 loc
= strip_subreg (loc
);
1076 mode
= GET_MODE (reg
);
1079 /* Always reload memory in an address even if the target supports
1081 new_reg
= lra_create_new_reg_with_unique_value (mode
, reg
, cl
, "address");
1086 regno
= REGNO (reg
);
1087 rclass
= get_reg_class (regno
);
1088 if ((*loc
= get_equiv_substitution (reg
)) != reg
)
1090 if (lra_dump_file
!= NULL
)
1092 fprintf (lra_dump_file
,
1093 "Changing pseudo %d in address of insn %u on equiv ",
1094 REGNO (reg
), INSN_UID (curr_insn
));
1095 dump_value_slim (lra_dump_file
, *loc
, 1);
1096 fprintf (lra_dump_file
, "\n");
1098 *loc
= copy_rtx (*loc
);
1100 if (*loc
!= reg
|| ! in_class_p (reg
, cl
, &new_class
))
1103 if (get_reload_reg (after
== NULL
? OP_IN
: OP_INOUT
,
1104 mode
, reg
, cl
, "address", &new_reg
))
1107 else if (new_class
!= NO_REGS
&& rclass
!= new_class
)
1109 change_class (regno
, new_class
, " Change", true);
1117 push_to_sequence (*before
);
1118 lra_emit_move (new_reg
, reg
);
1119 *before
= get_insns ();
1126 lra_emit_move (reg
, new_reg
);
1128 *after
= get_insns ();
1134 /* Make reloads for subreg in operand NOP with internal subreg mode
1135 REG_MODE, add new reloads for further processing. Return true if
1136 any reload was generated. */
1138 simplify_operand_subreg (int nop
, enum machine_mode reg_mode
)
1142 enum machine_mode mode
;
1144 rtx operand
= *curr_id
->operand_loc
[nop
];
1146 before
= after
= NULL_RTX
;
1148 if (GET_CODE (operand
) != SUBREG
)
1151 mode
= GET_MODE (operand
);
1152 reg
= SUBREG_REG (operand
);
1153 /* If we change address for paradoxical subreg of memory, the
1154 address might violate the necessary alignment or the access might
1155 be slow. So take this into consideration. We should not worry
1156 about access beyond allocated memory for paradoxical memory
1157 subregs as we don't substitute such equiv memory (see processing
1158 equivalences in function lra_constraints) and because for spilled
1159 pseudos we allocate stack memory enough for the biggest
1160 corresponding paradoxical subreg. */
1162 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (reg
))
1163 || MEM_ALIGN (reg
) >= GET_MODE_ALIGNMENT (mode
)))
1164 || (REG_P (reg
) && REGNO (reg
) < FIRST_PSEUDO_REGISTER
))
1166 alter_subreg (curr_id
->operand_loc
[nop
], false);
1169 /* Put constant into memory when we have mixed modes. It generates
1170 a better code in most cases as it does not need a secondary
1171 reload memory. It also prevents LRA looping when LRA is using
1172 secondary reload memory again and again. */
1173 if (CONSTANT_P (reg
) && CONST_POOL_OK_P (reg_mode
, reg
)
1174 && SCALAR_INT_MODE_P (reg_mode
) != SCALAR_INT_MODE_P (mode
))
1176 SUBREG_REG (operand
) = force_const_mem (reg_mode
, reg
);
1177 alter_subreg (curr_id
->operand_loc
[nop
], false);
1180 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or
1181 if there may be a problem accessing OPERAND in the outer
1184 && REGNO (reg
) >= FIRST_PSEUDO_REGISTER
1185 && (hard_regno
= lra_get_regno_hard_regno (REGNO (reg
))) >= 0
1186 /* Don't reload paradoxical subregs because we could be looping
1187 having repeatedly final regno out of hard regs range. */
1188 && (hard_regno_nregs
[hard_regno
][GET_MODE (reg
)]
1189 >= hard_regno_nregs
[hard_regno
][mode
])
1190 && simplify_subreg_regno (hard_regno
, GET_MODE (reg
),
1191 SUBREG_BYTE (operand
), mode
) < 0)
1192 || CONSTANT_P (reg
) || GET_CODE (reg
) == PLUS
|| MEM_P (reg
))
1194 enum op_type type
= curr_static_id
->operand
[nop
].type
;
1195 /* The class will be defined later in curr_insn_transform. */
1196 enum reg_class rclass
1197 = (enum reg_class
) targetm
.preferred_reload_class (reg
, ALL_REGS
);
1199 new_reg
= lra_create_new_reg_with_unique_value (reg_mode
, reg
, rclass
,
1201 bitmap_set_bit (&lra_optional_reload_pseudos
, REGNO (new_reg
));
1203 || GET_MODE_SIZE (GET_MODE (reg
)) > GET_MODE_SIZE (mode
))
1205 push_to_sequence (before
);
1206 lra_emit_move (new_reg
, reg
);
1207 before
= get_insns ();
1213 lra_emit_move (reg
, new_reg
);
1215 after
= get_insns ();
1218 SUBREG_REG (operand
) = new_reg
;
1219 lra_process_new_insns (curr_insn
, before
, after
,
1220 "Inserting subreg reload");
1226 /* Return TRUE if X refers for a hard register from SET. */
1228 uses_hard_regs_p (rtx x
, HARD_REG_SET set
)
1230 int i
, j
, x_hard_regno
;
1231 enum machine_mode mode
;
1237 code
= GET_CODE (x
);
1238 mode
= GET_MODE (x
);
1242 code
= GET_CODE (x
);
1243 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (mode
))
1244 mode
= GET_MODE (x
);
1249 x_hard_regno
= get_hard_regno (x
);
1250 return (x_hard_regno
>= 0
1251 && overlaps_hard_reg_set_p (set
, mode
, x_hard_regno
));
1255 struct address_info ad
;
1257 decompose_mem_address (&ad
, x
);
1258 if (ad
.base_term
!= NULL
&& uses_hard_regs_p (*ad
.base_term
, set
))
1260 if (ad
.index_term
!= NULL
&& uses_hard_regs_p (*ad
.index_term
, set
))
1263 fmt
= GET_RTX_FORMAT (code
);
1264 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1268 if (uses_hard_regs_p (XEXP (x
, i
), set
))
1271 else if (fmt
[i
] == 'E')
1273 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1274 if (uses_hard_regs_p (XVECEXP (x
, i
, j
), set
))
1281 /* Return true if OP is a spilled pseudo. */
1283 spilled_pseudo_p (rtx op
)
1286 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
&& in_mem_p (REGNO (op
)));
1289 /* Return true if X is a general constant. */
1291 general_constant_p (rtx x
)
1293 return CONSTANT_P (x
) && (! flag_pic
|| LEGITIMATE_PIC_OPERAND_P (x
));
1296 /* Major function to choose the current insn alternative and what
1297 operands should be reloaded and how. If ONLY_ALTERNATIVE is not
1298 negative we should consider only this alternative. Return false if
1299 we can not choose the alternative or find how to reload the
1302 process_alt_operands (int only_alternative
)
1305 int nop
, small_class_operands_num
, overall
, nalt
;
1306 int n_alternatives
= curr_static_id
->n_alternatives
;
1307 int n_operands
= curr_static_id
->n_operands
;
1308 /* LOSERS counts the operands that don't fit this alternative and
1309 would require loading. */
1311 /* REJECT is a count of how undesirable this alternative says it is
1312 if any reloading is required. If the alternative matches exactly
1313 then REJECT is ignored, but otherwise it gets this much counted
1314 against it in addition to the reloading needed. */
1316 /* The number of elements in the following array. */
1317 int early_clobbered_regs_num
;
1318 /* Numbers of operands which are early clobber registers. */
1319 int early_clobbered_nops
[MAX_RECOG_OPERANDS
];
1320 enum reg_class curr_alt
[MAX_RECOG_OPERANDS
];
1321 HARD_REG_SET curr_alt_set
[MAX_RECOG_OPERANDS
];
1322 bool curr_alt_match_win
[MAX_RECOG_OPERANDS
];
1323 bool curr_alt_win
[MAX_RECOG_OPERANDS
];
1324 bool curr_alt_offmemok
[MAX_RECOG_OPERANDS
];
1325 int curr_alt_matches
[MAX_RECOG_OPERANDS
];
1326 /* The number of elements in the following array. */
1327 int curr_alt_dont_inherit_ops_num
;
1328 /* Numbers of operands whose reload pseudos should not be inherited. */
1329 int curr_alt_dont_inherit_ops
[MAX_RECOG_OPERANDS
];
1331 /* The register when the operand is a subreg of register, otherwise the
1333 rtx no_subreg_reg_operand
[MAX_RECOG_OPERANDS
];
1334 /* The register if the operand is a register or subreg of register,
1336 rtx operand_reg
[MAX_RECOG_OPERANDS
];
1337 int hard_regno
[MAX_RECOG_OPERANDS
];
1338 enum machine_mode biggest_mode
[MAX_RECOG_OPERANDS
];
1339 int reload_nregs
, reload_sum
;
1343 /* Calculate some data common for all alternatives to speed up the
1345 for (nop
= 0; nop
< n_operands
; nop
++)
1347 op
= no_subreg_reg_operand
[nop
] = *curr_id
->operand_loc
[nop
];
1348 /* The real hard regno of the operand after the allocation. */
1349 hard_regno
[nop
] = get_hard_regno (op
);
1351 operand_reg
[nop
] = op
;
1352 biggest_mode
[nop
] = GET_MODE (operand_reg
[nop
]);
1353 if (GET_CODE (operand_reg
[nop
]) == SUBREG
)
1355 operand_reg
[nop
] = SUBREG_REG (operand_reg
[nop
]);
1356 if (GET_MODE_SIZE (biggest_mode
[nop
])
1357 < GET_MODE_SIZE (GET_MODE (operand_reg
[nop
])))
1358 biggest_mode
[nop
] = GET_MODE (operand_reg
[nop
]);
1360 if (REG_P (operand_reg
[nop
]))
1361 no_subreg_reg_operand
[nop
] = operand_reg
[nop
];
1363 operand_reg
[nop
] = NULL_RTX
;
1366 /* The constraints are made of several alternatives. Each operand's
1367 constraint looks like foo,bar,... with commas separating the
1368 alternatives. The first alternatives for all operands go
1369 together, the second alternatives go together, etc.
1371 First loop over alternatives. */
1372 for (nalt
= 0; nalt
< n_alternatives
; nalt
++)
1374 /* Loop over operands for one constraint alternative. */
1375 #ifdef HAVE_ATTR_enabled
1376 if (curr_id
->alternative_enabled_p
!= NULL
1377 && ! curr_id
->alternative_enabled_p
[nalt
])
1381 if (only_alternative
>= 0 && nalt
!= only_alternative
)
1384 overall
= losers
= reject
= reload_nregs
= reload_sum
= 0;
1385 for (nop
= 0; nop
< n_operands
; nop
++)
1386 reject
+= (curr_static_id
1387 ->operand_alternative
[nalt
* n_operands
+ nop
].reject
);
1388 early_clobbered_regs_num
= 0;
1390 for (nop
= 0; nop
< n_operands
; nop
++)
1394 int len
, c
, m
, i
, opalt_num
, this_alternative_matches
;
1395 bool win
, did_match
, offmemok
, early_clobber_p
;
1396 /* false => this operand can be reloaded somehow for this
1399 /* true => this operand can be reloaded if the alternative
1402 /* True if a constant forced into memory would be OK for
1405 enum reg_class this_alternative
, this_costly_alternative
;
1406 HARD_REG_SET this_alternative_set
, this_costly_alternative_set
;
1407 bool this_alternative_match_win
, this_alternative_win
;
1408 bool this_alternative_offmemok
;
1409 enum machine_mode mode
;
1411 opalt_num
= nalt
* n_operands
+ nop
;
1412 if (curr_static_id
->operand_alternative
[opalt_num
].anything_ok
)
1414 /* Fast track for no constraints at all. */
1415 curr_alt
[nop
] = NO_REGS
;
1416 CLEAR_HARD_REG_SET (curr_alt_set
[nop
]);
1417 curr_alt_win
[nop
] = true;
1418 curr_alt_match_win
[nop
] = false;
1419 curr_alt_offmemok
[nop
] = false;
1420 curr_alt_matches
[nop
] = -1;
1424 op
= no_subreg_reg_operand
[nop
];
1425 mode
= curr_operand_mode
[nop
];
1427 win
= did_match
= winreg
= offmemok
= constmemok
= false;
1430 early_clobber_p
= false;
1431 p
= curr_static_id
->operand_alternative
[opalt_num
].constraint
;
1433 this_costly_alternative
= this_alternative
= NO_REGS
;
1434 /* We update set of possible hard regs besides its class
1435 because reg class might be inaccurate. For example,
1436 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM
1437 is translated in HI_REGS because classes are merged by
1438 pairs and there is no accurate intermediate class. */
1439 CLEAR_HARD_REG_SET (this_alternative_set
);
1440 CLEAR_HARD_REG_SET (this_costly_alternative_set
);
1441 this_alternative_win
= false;
1442 this_alternative_match_win
= false;
1443 this_alternative_offmemok
= false;
1444 this_alternative_matches
= -1;
1446 /* An empty constraint should be excluded by the fast
1448 lra_assert (*p
!= 0 && *p
!= ',');
1450 /* Scan this alternative's specs for this operand; set WIN
1451 if the operand fits any letter in this alternative.
1452 Otherwise, clear BADOP if this operand could fit some
1453 letter after reloads, or set WINREG if this operand could
1454 fit after reloads provided the constraint allows some
1459 switch ((c
= *p
, len
= CONSTRAINT_LEN (c
, p
)), c
)
1468 case '=': case '+': case '?': case '*': case '!':
1469 case ' ': case '\t':
1473 /* We only support one commutative marker, the first
1474 one. We already set commutative above. */
1478 early_clobber_p
= true;
1482 /* Ignore rest of this alternative. */
1486 case '0': case '1': case '2': case '3': case '4':
1487 case '5': case '6': case '7': case '8': case '9':
1492 m
= strtoul (p
, &end
, 10);
1495 lra_assert (nop
> m
);
1497 this_alternative_matches
= m
;
1498 m_hregno
= get_hard_regno (*curr_id
->operand_loc
[m
]);
1499 /* We are supposed to match a previous operand.
1500 If we do, we win if that one did. If we do
1501 not, count both of the operands as losers.
1502 (This is too conservative, since most of the
1503 time only a single reload insn will be needed
1504 to make the two operands win. As a result,
1505 this alternative may be rejected when it is
1506 actually desirable.) */
1508 if (operands_match_p (*curr_id
->operand_loc
[nop
],
1509 *curr_id
->operand_loc
[m
], m_hregno
))
1511 /* We should reject matching of an early
1512 clobber operand if the matching operand is
1513 not dying in the insn. */
1514 if (! curr_static_id
->operand
[m
].early_clobber
1515 || operand_reg
[nop
] == NULL_RTX
1516 || (find_regno_note (curr_insn
, REG_DEAD
,
1517 REGNO (operand_reg
[nop
]))
1523 /* If we are matching a non-offsettable
1524 address where an offsettable address was
1525 expected, then we must reject this
1526 combination, because we can't reload
1528 if (curr_alt_offmemok
[m
]
1529 && MEM_P (*curr_id
->operand_loc
[m
])
1530 && curr_alt
[m
] == NO_REGS
&& ! curr_alt_win
[m
])
1536 /* Operands don't match. Both operands must
1537 allow a reload register, otherwise we
1538 cannot make them match. */
1539 if (curr_alt
[m
] == NO_REGS
)
1541 /* Retroactively mark the operand we had to
1542 match as a loser, if it wasn't already and
1543 it wasn't matched to a register constraint
1544 (e.g it might be matched by memory). */
1546 && (operand_reg
[m
] == NULL_RTX
1547 || hard_regno
[m
] < 0))
1551 += (ira_reg_class_max_nregs
[curr_alt
[m
]]
1552 [GET_MODE (*curr_id
->operand_loc
[m
])]);
1555 /* We prefer no matching alternatives because
1556 it gives more freedom in RA. */
1557 if (operand_reg
[nop
] == NULL_RTX
1558 || (find_regno_note (curr_insn
, REG_DEAD
,
1559 REGNO (operand_reg
[nop
]))
1563 /* If we have to reload this operand and some
1564 previous operand also had to match the same
1565 thing as this operand, we don't know how to do
1567 if (!match_p
|| !curr_alt_win
[m
])
1569 for (i
= 0; i
< nop
; i
++)
1570 if (curr_alt_matches
[i
] == m
)
1578 /* This can be fixed with reloads if the operand
1579 we are supposed to match can be fixed with
1582 this_alternative
= curr_alt
[m
];
1583 COPY_HARD_REG_SET (this_alternative_set
, curr_alt_set
[m
]);
1584 winreg
= this_alternative
!= NO_REGS
;
1589 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1591 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1592 IOR_HARD_REG_SET (this_alternative_set
,
1593 reg_class_contents
[cl
]);
1596 this_costly_alternative
1597 = reg_class_subunion
[this_costly_alternative
][cl
];
1598 IOR_HARD_REG_SET (this_costly_alternative_set
,
1599 reg_class_contents
[cl
]);
1605 case TARGET_MEM_CONSTRAINT
:
1606 if (MEM_P (op
) || spilled_pseudo_p (op
))
1608 /* We can put constant or pseudo value into memory
1609 to satisfy the constraint. */
1610 if (CONST_POOL_OK_P (mode
, op
) || REG_P (op
))
1617 && (GET_CODE (XEXP (op
, 0)) == PRE_DEC
1618 || GET_CODE (XEXP (op
, 0)) == POST_DEC
))
1624 && (GET_CODE (XEXP (op
, 0)) == PRE_INC
1625 || GET_CODE (XEXP (op
, 0)) == POST_INC
))
1629 /* Memory op whose address is not offsettable. */
1632 && ! offsettable_nonstrict_memref_p (op
))
1636 /* Memory operand whose address is offsettable. */
1639 && offsettable_nonstrict_memref_p (op
))
1640 || spilled_pseudo_p (op
))
1642 /* We can put constant or pseudo value into memory
1643 or make memory address offsetable to satisfy the
1645 if (CONST_POOL_OK_P (mode
, op
) || MEM_P (op
) || REG_P (op
))
1653 if (GET_CODE (op
) == CONST_DOUBLE
1654 || (GET_CODE (op
) == CONST_VECTOR
1655 && (GET_MODE_CLASS (mode
) == MODE_VECTOR_FLOAT
)))
1661 if (GET_CODE (op
) == CONST_DOUBLE
1662 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op
, c
, p
))
1667 if (CONST_INT_P (op
)
1668 || (GET_CODE (op
) == CONST_DOUBLE
&& mode
== VOIDmode
))
1672 if (general_constant_p (op
))
1677 if (CONST_INT_P (op
)
1678 || (GET_CODE (op
) == CONST_DOUBLE
&& mode
== VOIDmode
))
1690 if (CONST_INT_P (op
)
1691 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op
), c
, p
))
1696 /* This constraint should be excluded by the fast
1703 || general_constant_p (op
)
1704 || spilled_pseudo_p (op
))
1706 /* Drop through into 'r' case. */
1710 = reg_class_subunion
[this_alternative
][GENERAL_REGS
];
1711 IOR_HARD_REG_SET (this_alternative_set
,
1712 reg_class_contents
[GENERAL_REGS
]);
1715 this_costly_alternative
1716 = (reg_class_subunion
1717 [this_costly_alternative
][GENERAL_REGS
]);
1718 IOR_HARD_REG_SET (this_costly_alternative_set
,
1719 reg_class_contents
[GENERAL_REGS
]);
1724 if (REG_CLASS_FROM_CONSTRAINT (c
, p
) == NO_REGS
)
1726 #ifdef EXTRA_CONSTRAINT_STR
1727 if (EXTRA_MEMORY_CONSTRAINT (c
, p
))
1729 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1731 else if (spilled_pseudo_p (op
))
1734 /* If we didn't already win, we can reload
1735 constants via force_const_mem or put the
1736 pseudo value into memory, or make other
1737 memory by reloading the address like for
1739 if (CONST_POOL_OK_P (mode
, op
)
1740 || MEM_P (op
) || REG_P (op
))
1746 if (EXTRA_ADDRESS_CONSTRAINT (c
, p
))
1748 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1751 /* If we didn't already win, we can reload
1752 the address into a base register. */
1753 cl
= base_reg_class (VOIDmode
, ADDR_SPACE_GENERIC
,
1756 = reg_class_subunion
[this_alternative
][cl
];
1757 IOR_HARD_REG_SET (this_alternative_set
,
1758 reg_class_contents
[cl
]);
1761 this_costly_alternative
1762 = (reg_class_subunion
1763 [this_costly_alternative
][cl
]);
1764 IOR_HARD_REG_SET (this_costly_alternative_set
,
1765 reg_class_contents
[cl
]);
1771 if (EXTRA_CONSTRAINT_STR (op
, c
, p
))
1777 cl
= REG_CLASS_FROM_CONSTRAINT (c
, p
);
1778 this_alternative
= reg_class_subunion
[this_alternative
][cl
];
1779 IOR_HARD_REG_SET (this_alternative_set
,
1780 reg_class_contents
[cl
]);
1783 this_costly_alternative
1784 = reg_class_subunion
[this_costly_alternative
][cl
];
1785 IOR_HARD_REG_SET (this_costly_alternative_set
,
1786 reg_class_contents
[cl
]);
1789 if (mode
== BLKmode
)
1794 if (hard_regno
[nop
] >= 0
1795 && in_hard_reg_set_p (this_alternative_set
,
1796 mode
, hard_regno
[nop
]))
1798 else if (hard_regno
[nop
] < 0
1799 && in_class_p (op
, this_alternative
, NULL
))
1804 if (c
!= ' ' && c
!= '\t')
1805 costly_p
= c
== '*';
1807 while ((p
+= len
), c
);
1809 /* Record which operands fit this alternative. */
1812 this_alternative_win
= true;
1813 if (operand_reg
[nop
] != NULL_RTX
)
1815 if (hard_regno
[nop
] >= 0)
1817 if (in_hard_reg_set_p (this_costly_alternative_set
,
1818 mode
, hard_regno
[nop
]))
1823 /* Prefer won reg to spilled pseudo under other equal
1826 if (in_class_p (operand_reg
[nop
],
1827 this_costly_alternative
, NULL
))
1830 /* We simulate the behaviour of old reload here.
1831 Although scratches need hard registers and it
1832 might result in spilling other pseudos, no reload
1833 insns are generated for the scratches. So it
1834 might cost something but probably less than old
1835 reload pass believes. */
1836 if (lra_former_scratch_p (REGNO (operand_reg
[nop
])))
1837 reject
+= LRA_LOSER_COST_FACTOR
;
1841 this_alternative_match_win
= true;
1844 int const_to_mem
= 0;
1848 = (this_alternative
== NO_REGS
1849 || (hard_reg_set_subset_p
1850 (reg_class_contents
[this_alternative
],
1851 lra_no_alloc_regs
)));
1852 /* If this operand accepts a register, and if the
1853 register class has at least one allocatable register,
1854 then this operand can be reloaded. */
1855 if (winreg
&& !no_regs_p
)
1861 this_alternative_offmemok
= offmemok
;
1862 if (this_costly_alternative
!= NO_REGS
)
1864 /* If the operand is dying, has a matching constraint,
1865 and satisfies constraints of the matched operand
1866 which failed to satisfy the own constraints, we do
1867 not need to generate a reload insn for this
1869 if (!(this_alternative_matches
>= 0
1870 && !curr_alt_win
[this_alternative_matches
]
1872 && find_regno_note (curr_insn
, REG_DEAD
, REGNO (op
))
1873 && (hard_regno
[nop
] >= 0
1874 ? in_hard_reg_set_p (this_alternative_set
,
1875 mode
, hard_regno
[nop
])
1876 : in_class_p (op
, this_alternative
, NULL
))))
1878 if (operand_reg
[nop
] != NULL_RTX
1879 /* Output operands and matched input operands are
1880 not inherited. The following conditions do not
1881 exactly describe the previous statement but they
1882 are pretty close. */
1883 && curr_static_id
->operand
[nop
].type
!= OP_OUT
1884 && (this_alternative_matches
< 0
1885 || curr_static_id
->operand
[nop
].type
!= OP_IN
))
1887 int last_reload
= (lra_reg_info
[ORIGINAL_REGNO
1891 if (last_reload
> bb_reload_num
)
1892 reload_sum
+= last_reload
- bb_reload_num
;
1894 /* If this is a constant that is reloaded into the
1895 desired class by copying it to memory first, count
1896 that as another reload. This is consistent with
1897 other code and is required to avoid choosing another
1898 alternative when the constant is moved into memory.
1899 Note that the test here is precisely the same as in
1900 the code below that calls force_const_mem. */
1901 if (CONST_POOL_OK_P (mode
, op
)
1902 && ((targetm
.preferred_reload_class
1903 (op
, this_alternative
) == NO_REGS
)
1904 || no_input_reloads_p
))
1911 /* Alternative loses if it requires a type of reload not
1912 permitted for this insn. We can always reload
1913 objects with a REG_UNUSED note. */
1914 if ((curr_static_id
->operand
[nop
].type
!= OP_IN
1915 && no_output_reloads_p
1916 && ! find_reg_note (curr_insn
, REG_UNUSED
, op
))
1917 || (curr_static_id
->operand
[nop
].type
!= OP_OUT
1918 && no_input_reloads_p
&& ! const_to_mem
))
1921 /* Check strong discouragement of reload of non-constant
1922 into class THIS_ALTERNATIVE. */
1923 if (! CONSTANT_P (op
) && ! no_regs_p
1924 && (targetm
.preferred_reload_class
1925 (op
, this_alternative
) == NO_REGS
1926 || (curr_static_id
->operand
[nop
].type
== OP_OUT
1927 && (targetm
.preferred_output_reload_class
1928 (op
, this_alternative
) == NO_REGS
))))
1929 reject
+= LRA_MAX_REJECT
;
1931 if (! ((const_to_mem
&& constmemok
)
1932 || (MEM_P (op
) && offmemok
)))
1934 /* We prefer to reload pseudos over reloading other
1935 things, since such reloads may be able to be
1936 eliminated later. So bump REJECT in other cases.
1937 Don't do this in the case where we are forcing a
1938 constant into memory and it will then win since
1939 we don't want to have a different alternative
1941 if (! (REG_P (op
) && REGNO (op
) >= FIRST_PSEUDO_REGISTER
))
1946 += ira_reg_class_max_nregs
[this_alternative
][mode
];
1949 /* We are trying to spill pseudo into memory. It is
1950 usually more costly than moving to a hard register
1951 although it might takes the same number of
1953 if (no_regs_p
&& REG_P (op
))
1956 #ifdef SECONDARY_MEMORY_NEEDED
1957 /* If reload requires moving value through secondary
1958 memory, it will need one more insn at least. */
1959 if (this_alternative
!= NO_REGS
1960 && REG_P (op
) && (cl
= get_reg_class (REGNO (op
))) != NO_REGS
1961 && ((curr_static_id
->operand
[nop
].type
!= OP_OUT
1962 && SECONDARY_MEMORY_NEEDED (cl
, this_alternative
,
1964 || (curr_static_id
->operand
[nop
].type
!= OP_IN
1965 && SECONDARY_MEMORY_NEEDED (this_alternative
, cl
,
1969 /* Input reloads can be inherited more often than output
1970 reloads can be removed, so penalize output
1972 if (!REG_P (op
) || curr_static_id
->operand
[nop
].type
!= OP_IN
)
1976 if (early_clobber_p
)
1978 /* ??? We check early clobbers after processing all operands
1979 (see loop below) and there we update the costs more.
1980 Should we update the cost (may be approximately) here
1981 because of early clobber register reloads or it is a rare
1982 or non-important thing to be worth to do it. */
1983 overall
= losers
* LRA_LOSER_COST_FACTOR
+ reject
;
1984 if ((best_losers
== 0 || losers
!= 0) && best_overall
< overall
)
1987 curr_alt
[nop
] = this_alternative
;
1988 COPY_HARD_REG_SET (curr_alt_set
[nop
], this_alternative_set
);
1989 curr_alt_win
[nop
] = this_alternative_win
;
1990 curr_alt_match_win
[nop
] = this_alternative_match_win
;
1991 curr_alt_offmemok
[nop
] = this_alternative_offmemok
;
1992 curr_alt_matches
[nop
] = this_alternative_matches
;
1994 if (this_alternative_matches
>= 0
1995 && !did_match
&& !this_alternative_win
)
1996 curr_alt_win
[this_alternative_matches
] = false;
1998 if (early_clobber_p
&& operand_reg
[nop
] != NULL_RTX
)
1999 early_clobbered_nops
[early_clobbered_regs_num
++] = nop
;
2002 curr_alt_dont_inherit_ops_num
= 0;
2003 for (nop
= 0; nop
< early_clobbered_regs_num
; nop
++)
2005 int i
, j
, clobbered_hard_regno
;
2006 HARD_REG_SET temp_set
;
2008 i
= early_clobbered_nops
[nop
];
2009 if ((! curr_alt_win
[i
] && ! curr_alt_match_win
[i
])
2010 || hard_regno
[i
] < 0)
2012 clobbered_hard_regno
= hard_regno
[i
];
2013 CLEAR_HARD_REG_SET (temp_set
);
2014 add_to_hard_reg_set (&temp_set
, biggest_mode
[i
], clobbered_hard_regno
);
2015 for (j
= 0; j
< n_operands
; j
++)
2017 /* We don't want process insides of match_operator and
2018 match_parallel because otherwise we would process
2019 their operands once again generating a wrong
2021 || curr_static_id
->operand
[j
].is_operator
)
2023 else if ((curr_alt_matches
[j
] == i
&& curr_alt_match_win
[j
])
2024 || (curr_alt_matches
[i
] == j
&& curr_alt_match_win
[i
]))
2026 else if (uses_hard_regs_p (*curr_id
->operand_loc
[j
], temp_set
))
2028 if (j
>= n_operands
)
2030 /* We need to reload early clobbered register. */
2031 for (j
= 0; j
< n_operands
; j
++)
2032 if (curr_alt_matches
[j
] == i
)
2034 curr_alt_match_win
[j
] = false;
2036 overall
+= LRA_LOSER_COST_FACTOR
;
2038 if (! curr_alt_match_win
[i
])
2039 curr_alt_dont_inherit_ops
[curr_alt_dont_inherit_ops_num
++] = i
;
2042 /* Remember pseudos used for match reloads are never
2044 lra_assert (curr_alt_matches
[i
] >= 0);
2045 curr_alt_win
[curr_alt_matches
[i
]] = false;
2047 curr_alt_win
[i
] = curr_alt_match_win
[i
] = false;
2049 overall
+= LRA_LOSER_COST_FACTOR
;
2051 small_class_operands_num
= 0;
2052 for (nop
= 0; nop
< n_operands
; nop
++)
2053 small_class_operands_num
2054 += SMALL_REGISTER_CLASS_P (curr_alt
[nop
]) ? 1 : 0;
2056 /* If this alternative can be made to work by reloading, and it
2057 needs less reloading than the others checked so far, record
2058 it as the chosen goal for reloading. */
2059 if ((best_losers
!= 0 && losers
== 0)
2060 || (((best_losers
== 0 && losers
== 0)
2061 || (best_losers
!= 0 && losers
!= 0))
2062 && (best_overall
> overall
2063 || (best_overall
== overall
2064 /* If the cost of the reloads is the same,
2065 prefer alternative which requires minimal
2066 number of small register classes for the
2067 operands. This improves chances of reloads
2068 for insn requiring small register
2070 && (small_class_operands_num
2071 < best_small_class_operands_num
2072 || (small_class_operands_num
2073 == best_small_class_operands_num
2074 && (reload_nregs
< best_reload_nregs
2075 || (reload_nregs
== best_reload_nregs
2076 && best_reload_sum
< reload_sum
))))))))
2078 for (nop
= 0; nop
< n_operands
; nop
++)
2080 goal_alt_win
[nop
] = curr_alt_win
[nop
];
2081 goal_alt_match_win
[nop
] = curr_alt_match_win
[nop
];
2082 goal_alt_matches
[nop
] = curr_alt_matches
[nop
];
2083 goal_alt
[nop
] = curr_alt
[nop
];
2084 goal_alt_offmemok
[nop
] = curr_alt_offmemok
[nop
];
2086 goal_alt_dont_inherit_ops_num
= curr_alt_dont_inherit_ops_num
;
2087 for (nop
= 0; nop
< curr_alt_dont_inherit_ops_num
; nop
++)
2088 goal_alt_dont_inherit_ops
[nop
] = curr_alt_dont_inherit_ops
[nop
];
2089 goal_alt_swapped
= curr_swapped
;
2090 best_overall
= overall
;
2091 best_losers
= losers
;
2092 best_small_class_operands_num
= small_class_operands_num
;
2093 best_reload_nregs
= reload_nregs
;
2094 best_reload_sum
= reload_sum
;
2095 goal_alt_number
= nalt
;
2098 /* Everything is satisfied. Do not process alternatives
2107 /* Return 1 if ADDR is a valid memory address for mode MODE in address
2108 space AS, and check that each pseudo has the proper kind of hard
2111 valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED
,
2112 rtx addr
, addr_space_t as
)
2114 #ifdef GO_IF_LEGITIMATE_ADDRESS
2115 lra_assert (ADDR_SPACE_GENERIC_P (as
));
2116 GO_IF_LEGITIMATE_ADDRESS (mode
, addr
, win
);
2122 return targetm
.addr_space
.legitimate_address_p (mode
, addr
, 0, as
);
2126 /* Return whether address AD is valid. */
2129 valid_address_p (struct address_info
*ad
)
2131 /* Some ports do not check displacements for eliminable registers,
2132 so we replace them temporarily with the elimination target. */
2133 rtx saved_base_reg
= NULL_RTX
;
2134 rtx saved_index_reg
= NULL_RTX
;
2135 rtx
*base_term
= strip_subreg (ad
->base_term
);
2136 rtx
*index_term
= strip_subreg (ad
->index_term
);
2137 if (base_term
!= NULL
)
2139 saved_base_reg
= *base_term
;
2140 lra_eliminate_reg_if_possible (base_term
);
2141 if (ad
->base_term2
!= NULL
)
2142 *ad
->base_term2
= *ad
->base_term
;
2144 if (index_term
!= NULL
)
2146 saved_index_reg
= *index_term
;
2147 lra_eliminate_reg_if_possible (index_term
);
2149 bool ok_p
= valid_address_p (ad
->mode
, *ad
->outer
, ad
->as
);
2150 if (saved_base_reg
!= NULL_RTX
)
2152 *base_term
= saved_base_reg
;
2153 if (ad
->base_term2
!= NULL
)
2154 *ad
->base_term2
= *ad
->base_term
;
2156 if (saved_index_reg
!= NULL_RTX
)
2157 *index_term
= saved_index_reg
;
2161 /* Make reload base reg + disp from address AD. Return the new pseudo. */
2163 base_plus_disp_to_reg (struct address_info
*ad
)
2168 lra_assert (ad
->base
== ad
->base_term
&& ad
->disp
== ad
->disp_term
);
2169 cl
= base_reg_class (ad
->mode
, ad
->as
, ad
->base_outer_code
,
2170 get_index_code (ad
));
2171 new_reg
= lra_create_new_reg (GET_MODE (*ad
->base_term
), NULL_RTX
,
2173 lra_emit_add (new_reg
, *ad
->base_term
, *ad
->disp_term
);
2177 /* Return true if we can add a displacement to address AD, even if that
2178 makes the address invalid. The fix-up code requires any new address
2179 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */
2181 can_add_disp_p (struct address_info
*ad
)
2183 return (!ad
->autoinc_p
2184 && ad
->segment
== NULL
2185 && ad
->base
== ad
->base_term
2186 && ad
->disp
== ad
->disp_term
);
2189 /* Make equiv substitution in address AD. Return true if a substitution
2192 equiv_address_substitution (struct address_info
*ad
)
2194 rtx base_reg
, new_base_reg
, index_reg
, new_index_reg
, *base_term
, *index_term
;
2195 HOST_WIDE_INT disp
, scale
;
2198 base_term
= strip_subreg (ad
->base_term
);
2199 if (base_term
== NULL
)
2200 base_reg
= new_base_reg
= NULL_RTX
;
2203 base_reg
= *base_term
;
2204 new_base_reg
= get_equiv_substitution (base_reg
);
2206 index_term
= strip_subreg (ad
->index_term
);
2207 if (index_term
== NULL
)
2208 index_reg
= new_index_reg
= NULL_RTX
;
2211 index_reg
= *index_term
;
2212 new_index_reg
= get_equiv_substitution (index_reg
);
2214 if (base_reg
== new_base_reg
&& index_reg
== new_index_reg
)
2218 if (lra_dump_file
!= NULL
)
2220 fprintf (lra_dump_file
, "Changing address in insn %d ",
2221 INSN_UID (curr_insn
));
2222 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2224 if (base_reg
!= new_base_reg
)
2226 if (REG_P (new_base_reg
))
2228 *base_term
= new_base_reg
;
2231 else if (GET_CODE (new_base_reg
) == PLUS
2232 && REG_P (XEXP (new_base_reg
, 0))
2233 && CONST_INT_P (XEXP (new_base_reg
, 1))
2234 && can_add_disp_p (ad
))
2236 disp
+= INTVAL (XEXP (new_base_reg
, 1));
2237 *base_term
= XEXP (new_base_reg
, 0);
2240 if (ad
->base_term2
!= NULL
)
2241 *ad
->base_term2
= *ad
->base_term
;
2243 if (index_reg
!= new_index_reg
)
2245 if (REG_P (new_index_reg
))
2247 *index_term
= new_index_reg
;
2250 else if (GET_CODE (new_index_reg
) == PLUS
2251 && REG_P (XEXP (new_index_reg
, 0))
2252 && CONST_INT_P (XEXP (new_index_reg
, 1))
2253 && can_add_disp_p (ad
)
2254 && (scale
= get_index_scale (ad
)))
2256 disp
+= INTVAL (XEXP (new_index_reg
, 1)) * scale
;
2257 *index_term
= XEXP (new_index_reg
, 0);
2263 if (ad
->disp
!= NULL
)
2264 *ad
->disp
= plus_constant (GET_MODE (*ad
->inner
), *ad
->disp
, disp
);
2267 *ad
->inner
= plus_constant (GET_MODE (*ad
->inner
), *ad
->inner
, disp
);
2268 update_address (ad
);
2272 if (lra_dump_file
!= NULL
)
2275 fprintf (lra_dump_file
, " -- no change\n");
2278 fprintf (lra_dump_file
, " on equiv ");
2279 dump_value_slim (lra_dump_file
, *ad
->outer
, 1);
2280 fprintf (lra_dump_file
, "\n");
2286 /* Major function to make reloads for an address in operand NOP.
2287 The supported cases are:
2289 1) an address that existed before LRA started, at which point it must
2290 have been valid. These addresses are subject to elimination and
2291 may have become invalid due to the elimination offset being out
2294 2) an address created by forcing a constant to memory (force_const_to_mem).
2295 The initial form of these addresses might not be valid, and it is this
2296 function's job to make them valid.
2298 3) a frame address formed from a register and a (possibly zero)
2299 constant offset. As above, these addresses might not be valid
2300 and this function must make them so.
2302 Add reloads to the lists *BEFORE and *AFTER. We might need to add
2303 reloads to *AFTER because of inc/dec, {pre, post} modify in the
2304 address. Return true for any RTL change. */
2306 process_address (int nop
, rtx
*before
, rtx
*after
)
2308 struct address_info ad
;
2310 rtx op
= *curr_id
->operand_loc
[nop
];
2311 const char *constraint
= curr_static_id
->operand
[nop
].constraint
;
2314 if (constraint
[0] == 'p'
2315 || EXTRA_ADDRESS_CONSTRAINT (constraint
[0], constraint
))
2316 decompose_lea_address (&ad
, curr_id
->operand_loc
[nop
]);
2317 else if (MEM_P (op
))
2318 decompose_mem_address (&ad
, op
);
2319 else if (GET_CODE (op
) == SUBREG
2320 && MEM_P (SUBREG_REG (op
)))
2321 decompose_mem_address (&ad
, SUBREG_REG (op
));
2324 change_p
= equiv_address_substitution (&ad
);
2325 if (ad
.base_term
!= NULL
2326 && (process_addr_reg
2327 (ad
.base_term
, before
,
2329 && !(REG_P (*ad
.base_term
)
2330 && find_regno_note (curr_insn
, REG_DEAD
,
2331 REGNO (*ad
.base_term
)) != NULL_RTX
)
2333 base_reg_class (ad
.mode
, ad
.as
, ad
.base_outer_code
,
2334 get_index_code (&ad
)))))
2337 if (ad
.base_term2
!= NULL
)
2338 *ad
.base_term2
= *ad
.base_term
;
2340 if (ad
.index_term
!= NULL
2341 && process_addr_reg (ad
.index_term
, before
, NULL
, INDEX_REG_CLASS
))
2344 /* There are three cases where the shape of *AD.INNER may now be invalid:
2346 1) the original address was valid, but either elimination or
2347 equiv_address_substitution applied a displacement that made
2350 2) the address is an invalid symbolic address created by
2353 3) the address is a frame address with an invalid offset.
2355 All these cases involve a displacement and a non-autoinc address,
2356 so there is no point revalidating other types. */
2357 if (ad
.disp
== NULL
|| ad
.autoinc_p
|| valid_address_p (&ad
))
2360 /* Any index existed before LRA started, so we can assume that the
2361 presence and shape of the index is valid. */
2362 push_to_sequence (*before
);
2363 gcc_assert (ad
.segment
== NULL
);
2364 gcc_assert (ad
.disp
== ad
.disp_term
);
2365 if (ad
.base
== NULL
)
2367 if (ad
.index
== NULL
)
2370 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
,
2372 rtx disp
= *ad
.disp
;
2374 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2378 rtx last
= get_last_insn ();
2380 /* disp => lo_sum (new_base, disp), case (2) above. */
2381 insn
= emit_insn (gen_rtx_SET
2383 gen_rtx_HIGH (Pmode
, copy_rtx (disp
))));
2384 code
= recog_memoized (insn
);
2387 *ad
.disp
= gen_rtx_LO_SUM (Pmode
, new_reg
, disp
);
2388 if (! valid_address_p (ad
.mode
, *ad
.outer
, ad
.as
))
2395 delete_insns_since (last
);
2400 /* disp => new_base, case (2) above. */
2401 lra_emit_move (new_reg
, disp
);
2407 /* index * scale + disp => new base + index * scale,
2409 enum reg_class cl
= base_reg_class (ad
.mode
, ad
.as
, PLUS
,
2410 GET_CODE (*ad
.index
));
2412 lra_assert (INDEX_REG_CLASS
!= NO_REGS
);
2413 new_reg
= lra_create_new_reg (Pmode
, NULL_RTX
, cl
, "disp");
2414 lra_emit_move (new_reg
, *ad
.disp
);
2415 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2416 new_reg
, *ad
.index
);
2419 else if (ad
.index
== NULL
)
2421 /* base + disp => new base, cases (1) and (3) above. */
2422 /* Another option would be to reload the displacement into an
2423 index register. However, postreload has code to optimize
2424 address reloads that have the same base and different
2425 displacements, so reloading into an index register would
2426 not necessarily be a win. */
2427 new_reg
= base_plus_disp_to_reg (&ad
);
2428 *ad
.inner
= new_reg
;
2432 /* base + scale * index + disp => new base + scale * index,
2434 new_reg
= base_plus_disp_to_reg (&ad
);
2435 *ad
.inner
= simplify_gen_binary (PLUS
, GET_MODE (new_reg
),
2436 new_reg
, *ad
.index
);
2438 *before
= get_insns ();
2443 /* Emit insns to reload VALUE into a new register. VALUE is an
2444 auto-increment or auto-decrement RTX whose operand is a register or
2445 memory location; so reloading involves incrementing that location.
2446 IN is either identical to VALUE, or some cheaper place to reload
2447 value being incremented/decremented from.
2449 INC_AMOUNT is the number to increment or decrement by (always
2450 positive and ignored for POST_MODIFY/PRE_MODIFY).
2452 Return pseudo containing the result. */
2454 emit_inc (enum reg_class new_rclass
, rtx in
, rtx value
, int inc_amount
)
2456 /* REG or MEM to be copied and incremented. */
2457 rtx incloc
= XEXP (value
, 0);
2458 /* Nonzero if increment after copying. */
2459 int post
= (GET_CODE (value
) == POST_DEC
|| GET_CODE (value
) == POST_INC
2460 || GET_CODE (value
) == POST_MODIFY
);
2465 rtx real_in
= in
== value
? incloc
: in
;
2469 if (GET_CODE (value
) == PRE_MODIFY
|| GET_CODE (value
) == POST_MODIFY
)
2471 lra_assert (GET_CODE (XEXP (value
, 1)) == PLUS
2472 || GET_CODE (XEXP (value
, 1)) == MINUS
);
2473 lra_assert (rtx_equal_p (XEXP (XEXP (value
, 1), 0), XEXP (value
, 0)));
2474 plus_p
= GET_CODE (XEXP (value
, 1)) == PLUS
;
2475 inc
= XEXP (XEXP (value
, 1), 1);
2479 if (GET_CODE (value
) == PRE_DEC
|| GET_CODE (value
) == POST_DEC
)
2480 inc_amount
= -inc_amount
;
2482 inc
= GEN_INT (inc_amount
);
2485 if (! post
&& REG_P (incloc
))
2488 result
= lra_create_new_reg (GET_MODE (value
), value
, new_rclass
,
2491 if (real_in
!= result
)
2493 /* First copy the location to the result register. */
2494 lra_assert (REG_P (result
));
2495 emit_insn (gen_move_insn (result
, real_in
));
2498 /* We suppose that there are insns to add/sub with the constant
2499 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the
2500 old reload worked with this assumption. If the assumption
2501 becomes wrong, we should use approach in function
2502 base_plus_disp_to_reg. */
2505 /* See if we can directly increment INCLOC. */
2506 last
= get_last_insn ();
2507 add_insn
= emit_insn (plus_p
2508 ? gen_add2_insn (incloc
, inc
)
2509 : gen_sub2_insn (incloc
, inc
));
2511 code
= recog_memoized (add_insn
);
2514 if (! post
&& result
!= incloc
)
2515 emit_insn (gen_move_insn (result
, incloc
));
2518 delete_insns_since (last
);
2521 /* If couldn't do the increment directly, must increment in RESULT.
2522 The way we do this depends on whether this is pre- or
2523 post-increment. For pre-increment, copy INCLOC to the reload
2524 register, increment it there, then save back. */
2527 if (real_in
!= result
)
2528 emit_insn (gen_move_insn (result
, real_in
));
2530 emit_insn (gen_add2_insn (result
, inc
));
2532 emit_insn (gen_sub2_insn (result
, inc
));
2533 if (result
!= incloc
)
2534 emit_insn (gen_move_insn (incloc
, result
));
2540 Because this might be a jump insn or a compare, and because
2541 RESULT may not be available after the insn in an input
2542 reload, we must do the incrementing before the insn being
2545 We have already copied IN to RESULT. Increment the copy in
2546 RESULT, save that back, then decrement RESULT so it has
2547 the original value. */
2549 emit_insn (gen_add2_insn (result
, inc
));
2551 emit_insn (gen_sub2_insn (result
, inc
));
2552 emit_insn (gen_move_insn (incloc
, result
));
2553 /* Restore non-modified value for the result. We prefer this
2554 way because it does not require an additional hard
2558 if (CONST_INT_P (inc
))
2559 emit_insn (gen_add2_insn (result
, GEN_INT (-INTVAL (inc
))));
2561 emit_insn (gen_sub2_insn (result
, inc
));
2564 emit_insn (gen_add2_insn (result
, inc
));
2569 /* Swap operands NOP and NOP + 1. */
2571 swap_operands (int nop
)
2573 enum machine_mode mode
= curr_operand_mode
[nop
];
2574 curr_operand_mode
[nop
] = curr_operand_mode
[nop
+ 1];
2575 curr_operand_mode
[nop
+ 1] = mode
;
2576 rtx x
= *curr_id
->operand_loc
[nop
];
2577 *curr_id
->operand_loc
[nop
] = *curr_id
->operand_loc
[nop
+ 1];
2578 *curr_id
->operand_loc
[nop
+ 1] = x
;
2579 /* Swap the duplicates too. */
2580 lra_update_dup (curr_id
, nop
);
2581 lra_update_dup (curr_id
, nop
+ 1);
2584 /* Main entry point of the constraint code: search the body of the
2585 current insn to choose the best alternative. It is mimicking insn
2586 alternative cost calculation model of former reload pass. That is
2587 because machine descriptions were written to use this model. This
2588 model can be changed in future. Make commutative operand exchange
2591 Return true if some RTL changes happened during function call. */
2593 curr_insn_transform (void)
2599 signed char goal_alt_matched
[MAX_RECOG_OPERANDS
][MAX_RECOG_OPERANDS
];
2602 /* Flag that the insn has been changed through a transformation. */
2605 #ifdef SECONDARY_MEMORY_NEEDED
2608 int max_regno_before
;
2609 int reused_alternative_num
;
2611 no_input_reloads_p
= no_output_reloads_p
= false;
2612 goal_alt_number
= -1;
2614 if (check_and_process_move (&change_p
, &sec_mem_p
))
2617 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output
2618 reloads; neither are insns that SET cc0. Insns that use CC0 are
2619 not allowed to have any input reloads. */
2620 if (JUMP_P (curr_insn
) || CALL_P (curr_insn
))
2621 no_output_reloads_p
= true;
2624 if (reg_referenced_p (cc0_rtx
, PATTERN (curr_insn
)))
2625 no_input_reloads_p
= true;
2626 if (reg_set_p (cc0_rtx
, PATTERN (curr_insn
)))
2627 no_output_reloads_p
= true;
2630 n_operands
= curr_static_id
->n_operands
;
2631 n_alternatives
= curr_static_id
->n_alternatives
;
2633 /* Just return "no reloads" if insn has no operands with
2635 if (n_operands
== 0 || n_alternatives
== 0)
2638 max_regno_before
= max_reg_num ();
2640 for (i
= 0; i
< n_operands
; i
++)
2642 goal_alt_matched
[i
][0] = -1;
2643 goal_alt_matches
[i
] = -1;
2646 commutative
= curr_static_id
->commutative
;
2648 /* Now see what we need for pseudos that didn't get hard regs or got
2649 the wrong kind of hard reg. For this, we must consider all the
2650 operands together against the register constraints. */
2652 best_losers
= best_overall
= INT_MAX
;
2653 best_small_class_operands_num
= best_reload_sum
= 0;
2655 curr_swapped
= false;
2656 goal_alt_swapped
= false;
2658 /* Make equivalence substitution and memory subreg elimination
2659 before address processing because an address legitimacy can
2660 depend on memory mode. */
2661 for (i
= 0; i
< n_operands
; i
++)
2663 rtx op
= *curr_id
->operand_loc
[i
];
2664 rtx subst
, old
= op
;
2665 bool op_change_p
= false;
2667 if (GET_CODE (old
) == SUBREG
)
2668 old
= SUBREG_REG (old
);
2669 subst
= get_equiv_substitution (old
);
2672 subst
= copy_rtx (subst
);
2673 lra_assert (REG_P (old
));
2674 if (GET_CODE (op
) == SUBREG
)
2675 SUBREG_REG (op
) = subst
;
2677 *curr_id
->operand_loc
[i
] = subst
;
2678 if (lra_dump_file
!= NULL
)
2680 fprintf (lra_dump_file
,
2681 "Changing pseudo %d in operand %i of insn %u on equiv ",
2682 REGNO (old
), i
, INSN_UID (curr_insn
));
2683 dump_value_slim (lra_dump_file
, subst
, 1);
2684 fprintf (lra_dump_file
, "\n");
2686 op_change_p
= change_p
= true;
2688 if (simplify_operand_subreg (i
, GET_MODE (old
)) || op_change_p
)
2691 lra_update_dup (curr_id
, i
);
2695 /* Reload address registers and displacements. We do it before
2696 finding an alternative because of memory constraints. */
2697 before
= after
= NULL_RTX
;
2698 for (i
= 0; i
< n_operands
; i
++)
2699 if (! curr_static_id
->operand
[i
].is_operator
2700 && process_address (i
, &before
, &after
))
2703 lra_update_dup (curr_id
, i
);
2707 /* If we've changed the instruction then any alternative that
2708 we chose previously may no longer be valid. */
2709 lra_set_used_insn_alternative (curr_insn
, -1);
2713 reused_alternative_num
= curr_id
->used_insn_alternative
;
2714 if (lra_dump_file
!= NULL
&& reused_alternative_num
>= 0)
2715 fprintf (lra_dump_file
, "Reusing alternative %d for insn #%u\n",
2716 reused_alternative_num
, INSN_UID (curr_insn
));
2718 if (process_alt_operands (reused_alternative_num
))
2721 /* If insn is commutative (it's safe to exchange a certain pair of
2722 operands) then we need to try each alternative twice, the second
2723 time matching those two operands as if we had exchanged them. To
2724 do this, really exchange them in operands.
2726 If we have just tried the alternatives the second time, return
2727 operands to normal and drop through. */
2729 if (reused_alternative_num
< 0 && commutative
>= 0)
2731 curr_swapped
= !curr_swapped
;
2734 swap_operands (commutative
);
2738 swap_operands (commutative
);
2741 /* The operands don't meet the constraints. goal_alt describes the
2742 alternative that we could reach by reloading the fewest operands.
2743 Reload so as to fit it. */
2745 if (! alt_p
&& ! sec_mem_p
)
2747 /* No alternative works with reloads?? */
2748 if (INSN_CODE (curr_insn
) >= 0)
2749 fatal_insn ("unable to generate reloads for:", curr_insn
);
2750 error_for_asm (curr_insn
,
2751 "inconsistent operand constraints in an %<asm%>");
2752 /* Avoid further trouble with this insn. */
2753 PATTERN (curr_insn
) = gen_rtx_USE (VOIDmode
, const0_rtx
);
2754 lra_invalidate_insn_data (curr_insn
);
2758 /* If the best alternative is with operands 1 and 2 swapped, swap
2759 them. Update the operand numbers of any reloads already
2762 if (goal_alt_swapped
)
2764 if (lra_dump_file
!= NULL
)
2765 fprintf (lra_dump_file
, " Commutative operand exchange in insn %u\n",
2766 INSN_UID (curr_insn
));
2768 /* Swap the duplicates too. */
2769 swap_operands (commutative
);
2773 #ifdef SECONDARY_MEMORY_NEEDED
2774 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined
2775 too conservatively. So we use the secondary memory only if there
2776 is no any alternative without reloads. */
2777 use_sec_mem_p
= false;
2779 use_sec_mem_p
= true;
2782 for (i
= 0; i
< n_operands
; i
++)
2783 if (! goal_alt_win
[i
] && ! goal_alt_match_win
[i
])
2785 use_sec_mem_p
= i
< n_operands
;
2790 rtx new_reg
, set
, src
, dest
;
2791 enum machine_mode sec_mode
;
2793 lra_assert (sec_mem_p
);
2794 set
= single_set (curr_insn
);
2795 lra_assert (set
!= NULL_RTX
&& ! side_effects_p (set
));
2796 dest
= SET_DEST (set
);
2797 src
= SET_SRC (set
);
2798 #ifdef SECONDARY_MEMORY_NEEDED_MODE
2799 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src
));
2801 sec_mode
= GET_MODE (src
);
2803 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
2804 NO_REGS
, "secondary");
2805 /* If the mode is changed, it should be wider. */
2806 lra_assert (GET_MODE_SIZE (GET_MODE (new_reg
))
2807 >= GET_MODE_SIZE (GET_MODE (src
)));
2808 after
= emit_spill_move (false, new_reg
, dest
);
2809 lra_process_new_insns (curr_insn
, NULL_RTX
, after
,
2810 "Inserting the sec. move");
2811 before
= emit_spill_move (true, new_reg
, src
);
2812 lra_process_new_insns (curr_insn
, before
, NULL_RTX
, "Changing on");
2813 lra_set_insn_deleted (curr_insn
);
2818 lra_assert (goal_alt_number
>= 0);
2819 lra_set_used_insn_alternative (curr_insn
, goal_alt_number
);
2821 if (lra_dump_file
!= NULL
)
2825 fprintf (lra_dump_file
, " Choosing alt %d in insn %u:",
2826 goal_alt_number
, INSN_UID (curr_insn
));
2827 for (i
= 0; i
< n_operands
; i
++)
2829 p
= (curr_static_id
->operand_alternative
2830 [goal_alt_number
* n_operands
+ i
].constraint
);
2833 fprintf (lra_dump_file
, " (%d) ", i
);
2834 for (; *p
!= '\0' && *p
!= ',' && *p
!= '#'; p
++)
2835 fputc (*p
, lra_dump_file
);
2837 fprintf (lra_dump_file
, "\n");
2840 /* Right now, for any pair of operands I and J that are required to
2841 match, with J < I, goal_alt_matches[I] is J. Add I to
2842 goal_alt_matched[J]. */
2844 for (i
= 0; i
< n_operands
; i
++)
2845 if ((j
= goal_alt_matches
[i
]) >= 0)
2847 for (k
= 0; goal_alt_matched
[j
][k
] >= 0; k
++)
2849 /* We allow matching one output operand and several input
2852 || (curr_static_id
->operand
[j
].type
== OP_OUT
2853 && curr_static_id
->operand
[i
].type
== OP_IN
2854 && (curr_static_id
->operand
2855 [goal_alt_matched
[j
][0]].type
== OP_IN
)));
2856 goal_alt_matched
[j
][k
] = i
;
2857 goal_alt_matched
[j
][k
+ 1] = -1;
2860 for (i
= 0; i
< n_operands
; i
++)
2861 goal_alt_win
[i
] |= goal_alt_match_win
[i
];
2863 /* Any constants that aren't allowed and can't be reloaded into
2864 registers are here changed into memory references. */
2865 for (i
= 0; i
< n_operands
; i
++)
2866 if (goal_alt_win
[i
])
2869 enum reg_class new_class
;
2870 rtx reg
= *curr_id
->operand_loc
[i
];
2872 if (GET_CODE (reg
) == SUBREG
)
2873 reg
= SUBREG_REG (reg
);
2875 if (REG_P (reg
) && (regno
= REGNO (reg
)) >= FIRST_PSEUDO_REGISTER
)
2877 bool ok_p
= in_class_p (reg
, goal_alt
[i
], &new_class
);
2879 if (new_class
!= NO_REGS
&& get_reg_class (regno
) != new_class
)
2882 change_class (regno
, new_class
, " Change", true);
2888 const char *constraint
;
2890 rtx op
= *curr_id
->operand_loc
[i
];
2891 rtx subreg
= NULL_RTX
;
2892 enum machine_mode mode
= curr_operand_mode
[i
];
2894 if (GET_CODE (op
) == SUBREG
)
2897 op
= SUBREG_REG (op
);
2898 mode
= GET_MODE (op
);
2901 if (CONST_POOL_OK_P (mode
, op
)
2902 && ((targetm
.preferred_reload_class
2903 (op
, (enum reg_class
) goal_alt
[i
]) == NO_REGS
)
2904 || no_input_reloads_p
))
2906 rtx tem
= force_const_mem (mode
, op
);
2909 if (subreg
!= NULL_RTX
)
2910 tem
= gen_rtx_SUBREG (mode
, tem
, SUBREG_BYTE (subreg
));
2912 *curr_id
->operand_loc
[i
] = tem
;
2913 lra_update_dup (curr_id
, i
);
2914 process_address (i
, &before
, &after
);
2916 /* If the alternative accepts constant pool refs directly
2917 there will be no reload needed at all. */
2918 if (subreg
!= NULL_RTX
)
2920 /* Skip alternatives before the one requested. */
2921 constraint
= (curr_static_id
->operand_alternative
2922 [goal_alt_number
* n_operands
+ i
].constraint
);
2924 (c
= *constraint
) && c
!= ',' && c
!= '#';
2925 constraint
+= CONSTRAINT_LEN (c
, constraint
))
2927 if (c
== TARGET_MEM_CONSTRAINT
|| c
== 'o')
2929 #ifdef EXTRA_CONSTRAINT_STR
2930 if (EXTRA_MEMORY_CONSTRAINT (c
, constraint
)
2931 && EXTRA_CONSTRAINT_STR (tem
, c
, constraint
))
2935 if (c
== '\0' || c
== ',' || c
== '#')
2938 goal_alt_win
[i
] = true;
2942 for (i
= 0; i
< n_operands
; i
++)
2945 rtx op
= *curr_id
->operand_loc
[i
];
2947 if (goal_alt_win
[i
])
2949 if (goal_alt
[i
] == NO_REGS
2951 /* When we assign NO_REGS it means that we will not
2952 assign a hard register to the scratch pseudo by
2953 assigment pass and the scratch pseudo will be
2954 spilled. Spilled scratch pseudos are transformed
2955 back to scratches at the LRA end. */
2956 && lra_former_scratch_operand_p (curr_insn
, i
))
2957 change_class (REGNO (op
), NO_REGS
, " Change", true);
2961 /* Operands that match previous ones have already been handled. */
2962 if (goal_alt_matches
[i
] >= 0)
2965 /* We should not have an operand with a non-offsettable address
2966 appearing where an offsettable address will do. It also may
2967 be a case when the address should be special in other words
2968 not a general one (e.g. it needs no index reg). */
2969 if (goal_alt_matched
[i
][0] == -1 && goal_alt_offmemok
[i
] && MEM_P (op
))
2971 enum reg_class rclass
;
2972 rtx
*loc
= &XEXP (op
, 0);
2973 enum rtx_code code
= GET_CODE (*loc
);
2975 push_to_sequence (before
);
2976 rclass
= base_reg_class (GET_MODE (op
), MEM_ADDR_SPACE (op
),
2978 if (GET_RTX_CLASS (code
) == RTX_AUTOINC
)
2979 new_reg
= emit_inc (rclass
, *loc
, *loc
,
2980 /* This value does not matter for MODIFY. */
2981 GET_MODE_SIZE (GET_MODE (op
)));
2982 else if (get_reload_reg (OP_IN
, Pmode
, *loc
, rclass
,
2983 "offsetable address", &new_reg
))
2984 lra_emit_move (new_reg
, *loc
);
2985 before
= get_insns ();
2988 lra_update_dup (curr_id
, i
);
2990 else if (goal_alt_matched
[i
][0] == -1)
2992 enum machine_mode mode
;
2994 int hard_regno
, byte
;
2995 enum op_type type
= curr_static_id
->operand
[i
].type
;
2997 loc
= curr_id
->operand_loc
[i
];
2998 mode
= curr_operand_mode
[i
];
2999 if (GET_CODE (*loc
) == SUBREG
)
3001 reg
= SUBREG_REG (*loc
);
3002 byte
= SUBREG_BYTE (*loc
);
3004 /* Strict_low_part requires reload the register not
3005 the sub-register. */
3006 && (curr_static_id
->operand
[i
].strict_low
3007 || (GET_MODE_SIZE (mode
)
3008 <= GET_MODE_SIZE (GET_MODE (reg
))
3010 = get_try_hard_regno (REGNO (reg
))) >= 0
3011 && (simplify_subreg_regno
3013 GET_MODE (reg
), byte
, mode
) < 0)
3014 && (goal_alt
[i
] == NO_REGS
3015 || (simplify_subreg_regno
3016 (ira_class_hard_regs
[goal_alt
[i
]][0],
3017 GET_MODE (reg
), byte
, mode
) >= 0)))))
3019 loc
= &SUBREG_REG (*loc
);
3020 mode
= GET_MODE (*loc
);
3024 if (get_reload_reg (type
, mode
, old
, goal_alt
[i
], "", &new_reg
)
3027 push_to_sequence (before
);
3028 lra_emit_move (new_reg
, old
);
3029 before
= get_insns ();
3034 && find_reg_note (curr_insn
, REG_UNUSED
, old
) == NULL_RTX
)
3037 lra_emit_move (type
== OP_INOUT
? copy_rtx (old
) : old
, new_reg
);
3039 after
= get_insns ();
3043 for (j
= 0; j
< goal_alt_dont_inherit_ops_num
; j
++)
3044 if (goal_alt_dont_inherit_ops
[j
] == i
)
3046 lra_set_regno_unique_value (REGNO (new_reg
));
3049 lra_update_dup (curr_id
, i
);
3051 else if (curr_static_id
->operand
[i
].type
== OP_IN
3052 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3059 match_reload (goal_alt_matched
[i
][0], arr
,
3060 goal_alt
[i
], &before
, &after
);
3062 else if (curr_static_id
->operand
[i
].type
== OP_OUT
3063 && (curr_static_id
->operand
[goal_alt_matched
[i
][0]].type
3065 match_reload (i
, goal_alt_matched
[i
], goal_alt
[i
], &before
, &after
);
3067 /* We must generate code in any case when function
3068 process_alt_operands decides that it is possible. */
3071 if (before
!= NULL_RTX
|| after
!= NULL_RTX
3072 || max_regno_before
!= max_reg_num ())
3076 lra_update_operator_dups (curr_id
);
3077 /* Something changes -- process the insn. */
3078 lra_update_insn_regno_info (curr_insn
);
3080 lra_process_new_insns (curr_insn
, before
, after
, "Inserting insn reload");
3084 /* Return true if X is in LIST. */
3086 in_list_p (rtx x
, rtx list
)
3088 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3089 if (XEXP (list
, 0) == x
)
3094 /* Return true if X contains an allocatable hard register (if
3095 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */
3097 contains_reg_p (rtx x
, bool hard_reg_p
, bool spilled_p
)
3103 code
= GET_CODE (x
);
3106 int regno
= REGNO (x
);
3107 HARD_REG_SET alloc_regs
;
3111 if (regno
>= FIRST_PSEUDO_REGISTER
)
3112 regno
= lra_get_regno_hard_regno (regno
);
3115 COMPL_HARD_REG_SET (alloc_regs
, lra_no_alloc_regs
);
3116 return overlaps_hard_reg_set_p (alloc_regs
, GET_MODE (x
), regno
);
3120 if (regno
< FIRST_PSEUDO_REGISTER
)
3124 return lra_get_regno_hard_regno (regno
) < 0;
3127 fmt
= GET_RTX_FORMAT (code
);
3128 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3132 if (contains_reg_p (XEXP (x
, i
), hard_reg_p
, spilled_p
))
3135 else if (fmt
[i
] == 'E')
3137 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3138 if (contains_reg_p (XVECEXP (x
, i
, j
), hard_reg_p
, spilled_p
))
3145 /* Process all regs in location *LOC and change them on equivalent
3146 substitution. Return true if any change was done. */
3148 loc_equivalence_change_p (rtx
*loc
)
3150 rtx subst
, reg
, x
= *loc
;
3151 bool result
= false;
3152 enum rtx_code code
= GET_CODE (x
);
3158 reg
= SUBREG_REG (x
);
3159 if ((subst
= get_equiv_substitution (reg
)) != reg
3160 && GET_MODE (subst
) == VOIDmode
)
3162 /* We cannot reload debug location. Simplify subreg here
3163 while we know the inner mode. */
3164 *loc
= simplify_gen_subreg (GET_MODE (x
), subst
,
3165 GET_MODE (reg
), SUBREG_BYTE (x
));
3169 if (code
== REG
&& (subst
= get_equiv_substitution (x
)) != x
)
3175 /* Scan all the operand sub-expressions. */
3176 fmt
= GET_RTX_FORMAT (code
);
3177 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3180 result
= loc_equivalence_change_p (&XEXP (x
, i
)) || result
;
3181 else if (fmt
[i
] == 'E')
3182 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3184 = loc_equivalence_change_p (&XVECEXP (x
, i
, j
)) || result
;
3189 /* Similar to loc_equivalence_change_p, but for use as
3190 simplify_replace_fn_rtx callback. */
3192 loc_equivalence_callback (rtx loc
, const_rtx
, void *)
3197 rtx subst
= get_equiv_substitution (loc
);
3204 /* Maximum number of generated reload insns per an insn. It is for
3205 preventing this pass cycling in a bug case. */
3206 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS
3208 /* The current iteration number of this LRA pass. */
3209 int lra_constraint_iter
;
3211 /* The current iteration number of this LRA pass after the last spill
3213 int lra_constraint_iter_after_spill
;
3215 /* True if we substituted equiv which needs checking register
3216 allocation correctness because the equivalent value contains
3217 allocatable hard registers or when we restore multi-register
3219 bool lra_risky_transformations_p
;
3221 /* Return true if REGNO is referenced in more than one block. */
3223 multi_block_pseudo_p (int regno
)
3225 basic_block bb
= NULL
;
3229 if (regno
< FIRST_PSEUDO_REGISTER
)
3232 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info
[regno
].insn_bitmap
, 0, uid
, bi
)
3234 bb
= BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
);
3235 else if (BLOCK_FOR_INSN (lra_insn_recog_data
[uid
]->insn
) != bb
)
3240 /* Return true if LIST contains a deleted insn. */
3242 contains_deleted_insn_p (rtx list
)
3244 for (; list
!= NULL_RTX
; list
= XEXP (list
, 1))
3245 if (NOTE_P (XEXP (list
, 0))
3246 && NOTE_KIND (XEXP (list
, 0)) == NOTE_INSN_DELETED
)
3251 /* Return true if X contains a pseudo dying in INSN. */
3253 dead_pseudo_p (rtx x
, rtx insn
)
3260 return (insn
!= NULL_RTX
3261 && find_regno_note (insn
, REG_DEAD
, REGNO (x
)) != NULL_RTX
);
3262 code
= GET_CODE (x
);
3263 fmt
= GET_RTX_FORMAT (code
);
3264 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3268 if (dead_pseudo_p (XEXP (x
, i
), insn
))
3271 else if (fmt
[i
] == 'E')
3273 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3274 if (dead_pseudo_p (XVECEXP (x
, i
, j
), insn
))
3281 /* Return true if INSN contains a dying pseudo in INSN right hand
3284 insn_rhs_dead_pseudo_p (rtx insn
)
3286 rtx set
= single_set (insn
);
3288 gcc_assert (set
!= NULL
);
3289 return dead_pseudo_p (SET_SRC (set
), insn
);
3292 /* Return true if any init insn of REGNO contains a dying pseudo in
3293 insn right hand side. */
3295 init_insn_rhs_dead_pseudo_p (int regno
)
3297 rtx insns
= ira_reg_equiv
[regno
].init_insns
;
3302 return insn_rhs_dead_pseudo_p (insns
);
3303 for (; insns
!= NULL_RTX
; insns
= XEXP (insns
, 1))
3304 if (insn_rhs_dead_pseudo_p (XEXP (insns
, 0)))
3309 /* Entry function of LRA constraint pass. Return true if the
3310 constraint pass did change the code. */
3312 lra_constraints (bool first_p
)
3315 int i
, hard_regno
, new_insns_num
;
3316 unsigned int min_len
, new_min_len
, uid
;
3317 rtx set
, x
, reg
, dest_reg
;
3318 basic_block last_bb
;
3319 bitmap_head equiv_insn_bitmap
;
3322 lra_constraint_iter
++;
3323 if (lra_dump_file
!= NULL
)
3324 fprintf (lra_dump_file
, "\n********** Local #%d: **********\n\n",
3325 lra_constraint_iter
);
3326 lra_constraint_iter_after_spill
++;
3327 if (lra_constraint_iter_after_spill
> LRA_MAX_CONSTRAINT_ITERATION_NUMBER
)
3329 ("Maximum number of LRA constraint passes is achieved (%d)\n",
3330 LRA_MAX_CONSTRAINT_ITERATION_NUMBER
);
3332 lra_risky_transformations_p
= false;
3333 new_insn_uid_start
= get_max_uid ();
3334 new_regno_start
= first_p
? lra_constraint_new_regno_start
: max_reg_num ();
3335 bitmap_initialize (&equiv_insn_bitmap
, ®_obstack
);
3336 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3337 if (lra_reg_info
[i
].nrefs
!= 0)
3339 ira_reg_equiv
[i
].profitable_p
= true;
3340 reg
= regno_reg_rtx
[i
];
3341 if ((hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3345 nregs
= hard_regno_nregs
[hard_regno
][lra_reg_info
[i
].biggest_mode
];
3346 for (j
= 0; j
< nregs
; j
++)
3347 df_set_regs_ever_live (hard_regno
+ j
, true);
3349 else if ((x
= get_equiv_substitution (reg
)) != reg
)
3351 bool pseudo_p
= contains_reg_p (x
, false, false);
3354 /* After RTL transformation, we can not guarantee that
3355 pseudo in the substitution was not reloaded which might
3356 make equivalence invalid. For example, in reverse
3363 the memory address register was reloaded before the 2nd
3365 if ((! first_p
&& pseudo_p
)
3366 /* We don't use DF for compilation speed sake. So it
3367 is problematic to update live info when we use an
3368 equivalence containing pseudos in more than one
3370 || (pseudo_p
&& multi_block_pseudo_p (i
))
3371 /* If an init insn was deleted for some reason, cancel
3372 the equiv. We could update the equiv insns after
3373 transformations including an equiv insn deletion
3374 but it is not worthy as such cases are extremely
3376 || contains_deleted_insn_p (ira_reg_equiv
[i
].init_insns
)
3377 /* If it is not a reverse equivalence, we check that a
3378 pseudo in rhs of the init insn is not dying in the
3379 insn. Otherwise, the live info at the beginning of
3380 the corresponding BB might be wrong after we
3381 removed the insn. When the equiv can be a
3382 constant, the right hand side of the init insn can
3384 || (! ((insn
= ira_reg_equiv
[i
].init_insns
) != NULL_RTX
3386 && (set
= single_set (insn
)) != NULL_RTX
3387 && REG_P (SET_DEST (set
))
3388 && (int) REGNO (SET_DEST (set
)) == i
)
3389 && init_insn_rhs_dead_pseudo_p (i
))
3390 /* Prevent access beyond equivalent memory for
3391 paradoxical subregs. */
3393 && (GET_MODE_SIZE (lra_reg_info
[i
].biggest_mode
)
3394 > GET_MODE_SIZE (GET_MODE (x
)))))
3395 ira_reg_equiv
[i
].defined_p
= false;
3396 if (contains_reg_p (x
, false, true))
3397 ira_reg_equiv
[i
].profitable_p
= false;
3398 if (get_equiv_substitution (reg
) != reg
)
3399 bitmap_ior_into (&equiv_insn_bitmap
, &lra_reg_info
[i
].insn_bitmap
);
3402 /* We should add all insns containing pseudos which should be
3403 substituted by their equivalences. */
3404 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap
, 0, uid
, bi
)
3405 lra_push_insn_by_uid (uid
);
3406 lra_eliminate (false);
3407 min_len
= lra_insn_stack_length ();
3411 while ((new_min_len
= lra_insn_stack_length ()) != 0)
3413 curr_insn
= lra_pop_insn ();
3415 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
3416 if (curr_bb
!= last_bb
)
3419 bb_reload_num
= lra_curr_reload_num
;
3421 if (min_len
> new_min_len
)
3423 min_len
= new_min_len
;
3426 if (new_insns_num
> MAX_RELOAD_INSNS_NUMBER
)
3428 ("Max. number of generated reload insns per insn is achieved (%d)\n",
3429 MAX_RELOAD_INSNS_NUMBER
);
3431 if (DEBUG_INSN_P (curr_insn
))
3433 /* We need to check equivalence in debug insn and change
3434 pseudo to the equivalent value if necessary. */
3435 curr_id
= lra_get_insn_recog_data (curr_insn
);
3436 if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
)))
3438 rtx old
= *curr_id
->operand_loc
[0];
3439 *curr_id
->operand_loc
[0]
3440 = simplify_replace_fn_rtx (old
, NULL_RTX
,
3441 loc_equivalence_callback
, NULL
);
3442 if (old
!= *curr_id
->operand_loc
[0])
3444 lra_update_insn_regno_info (curr_insn
);
3449 else if (INSN_P (curr_insn
))
3451 if ((set
= single_set (curr_insn
)) != NULL_RTX
)
3453 dest_reg
= SET_DEST (set
);
3454 /* The equivalence pseudo could be set up as SUBREG in a
3455 case when it is a call restore insn in a mode
3456 different from the pseudo mode. */
3457 if (GET_CODE (dest_reg
) == SUBREG
)
3458 dest_reg
= SUBREG_REG (dest_reg
);
3459 if ((REG_P (dest_reg
)
3460 && (x
= get_equiv_substitution (dest_reg
)) != dest_reg
3461 /* Remove insns which set up a pseudo whose value
3462 can not be changed. Such insns might be not in
3463 init_insns because we don't update equiv data
3464 during insn transformations.
3466 As an example, let suppose that a pseudo got
3467 hard register and on the 1st pass was not
3468 changed to equivalent constant. We generate an
3469 additional insn setting up the pseudo because of
3470 secondary memory movement. Then the pseudo is
3471 spilled and we use the equiv constant. In this
3472 case we should remove the additional insn and
3473 this insn is not init_insns list. */
3474 && (! MEM_P (x
) || MEM_READONLY_P (x
)
3475 || in_list_p (curr_insn
,
3477 [REGNO (dest_reg
)].init_insns
)))
3478 || (((x
= get_equiv_substitution (SET_SRC (set
)))
3480 && in_list_p (curr_insn
,
3482 [REGNO (SET_SRC (set
))].init_insns
)))
3484 /* This is equiv init insn of pseudo which did not get a
3485 hard register -- remove the insn. */
3486 if (lra_dump_file
!= NULL
)
3488 fprintf (lra_dump_file
,
3489 " Removing equiv init insn %i (freq=%d)\n",
3490 INSN_UID (curr_insn
),
3491 BLOCK_FOR_INSN (curr_insn
)->frequency
);
3492 dump_insn_slim (lra_dump_file
, curr_insn
);
3494 if (contains_reg_p (x
, true, false))
3495 lra_risky_transformations_p
= true;
3496 lra_set_insn_deleted (curr_insn
);
3500 curr_id
= lra_get_insn_recog_data (curr_insn
);
3501 curr_static_id
= curr_id
->insn_static_data
;
3502 init_curr_insn_input_reloads ();
3503 init_curr_operand_mode ();
3504 if (curr_insn_transform ())
3506 /* Check non-transformed insns too for equiv change as USE
3507 or CLOBBER don't need reloads but can contain pseudos
3508 being changed on their equivalences. */
3509 else if (bitmap_bit_p (&equiv_insn_bitmap
, INSN_UID (curr_insn
))
3510 && loc_equivalence_change_p (&PATTERN (curr_insn
)))
3512 lra_update_insn_regno_info (curr_insn
);
3517 bitmap_clear (&equiv_insn_bitmap
);
3518 /* If we used a new hard regno, changed_p should be true because the
3519 hard reg is assigned to a new pseudo. */
3520 #ifdef ENABLE_CHECKING
3523 for (i
= FIRST_PSEUDO_REGISTER
; i
< new_regno_start
; i
++)
3524 if (lra_reg_info
[i
].nrefs
!= 0
3525 && (hard_regno
= lra_get_regno_hard_regno (i
)) >= 0)
3527 int j
, nregs
= hard_regno_nregs
[hard_regno
][PSEUDO_REGNO_MODE (i
)];
3529 for (j
= 0; j
< nregs
; j
++)
3530 lra_assert (df_regs_ever_live_p (hard_regno
+ j
));
3537 /* Initiate the LRA constraint pass. It is done once per
3540 lra_constraints_init (void)
3544 /* Finalize the LRA constraint pass. It is done once per
3547 lra_constraints_finish (void)
3553 /* This page contains code to do inheritance/split
3556 /* Number of reloads passed so far in current EBB. */
3557 static int reloads_num
;
3559 /* Number of calls passed so far in current EBB. */
3560 static int calls_num
;
3562 /* Current reload pseudo check for validity of elements in
3564 static int curr_usage_insns_check
;
3566 /* Info about last usage of registers in EBB to do inheritance/split
3567 transformation. Inheritance transformation is done from a spilled
3568 pseudo and split transformations from a hard register or a pseudo
3569 assigned to a hard register. */
3572 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member
3573 value INSNS is valid. The insns is chain of optional debug insns
3574 and a finishing non-debug insn using the corresponding reg. */
3576 /* Value of global reloads_num at the last insn in INSNS. */
3578 /* Value of global reloads_nums at the last insn in INSNS. */
3580 /* It can be true only for splitting. And it means that the restore
3581 insn should be put after insn given by the following member. */
3583 /* Next insns in the current EBB which use the original reg and the
3584 original reg value is not changed between the current insn and
3585 the next insns. In order words, e.g. for inheritance, if we need
3586 to use the original reg value again in the next insns we can try
3587 to use the value in a hard register from a reload insn of the
3592 /* Map: regno -> corresponding pseudo usage insns. */
3593 static struct usage_insns
*usage_insns
;
3596 setup_next_usage_insn (int regno
, rtx insn
, int reloads_num
, bool after_p
)
3598 usage_insns
[regno
].check
= curr_usage_insns_check
;
3599 usage_insns
[regno
].insns
= insn
;
3600 usage_insns
[regno
].reloads_num
= reloads_num
;
3601 usage_insns
[regno
].calls_num
= calls_num
;
3602 usage_insns
[regno
].after_p
= after_p
;
3605 /* The function is used to form list REGNO usages which consists of
3606 optional debug insns finished by a non-debug insn using REGNO.
3607 RELOADS_NUM is current number of reload insns processed so far. */
3609 add_next_usage_insn (int regno
, rtx insn
, int reloads_num
)
3611 rtx next_usage_insns
;
3613 if (usage_insns
[regno
].check
== curr_usage_insns_check
3614 && (next_usage_insns
= usage_insns
[regno
].insns
) != NULL_RTX
3615 && DEBUG_INSN_P (insn
))
3617 /* Check that we did not add the debug insn yet. */
3618 if (next_usage_insns
!= insn
3619 && (GET_CODE (next_usage_insns
) != INSN_LIST
3620 || XEXP (next_usage_insns
, 0) != insn
))
3621 usage_insns
[regno
].insns
= gen_rtx_INSN_LIST (VOIDmode
, insn
,
3624 else if (NONDEBUG_INSN_P (insn
))
3625 setup_next_usage_insn (regno
, insn
, reloads_num
, false);
3627 usage_insns
[regno
].check
= 0;
3630 /* Replace all references to register OLD_REGNO in *LOC with pseudo
3631 register NEW_REG. Return true if any change was made. */
3633 substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
)
3636 bool result
= false;
3644 code
= GET_CODE (x
);
3645 if (code
== REG
&& (int) REGNO (x
) == old_regno
)
3647 enum machine_mode mode
= GET_MODE (*loc
);
3648 enum machine_mode inner_mode
= GET_MODE (new_reg
);
3650 if (mode
!= inner_mode
)
3652 if (GET_MODE_SIZE (mode
) >= GET_MODE_SIZE (inner_mode
)
3653 || ! SCALAR_INT_MODE_P (inner_mode
))
3654 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, 0);
3656 new_reg
= gen_lowpart_SUBREG (mode
, new_reg
);
3662 /* Scan all the operand sub-expressions. */
3663 fmt
= GET_RTX_FORMAT (code
);
3664 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
3668 if (substitute_pseudo (&XEXP (x
, i
), old_regno
, new_reg
))
3671 else if (fmt
[i
] == 'E')
3673 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3674 if (substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
, new_reg
))
3681 /* Return first non-debug insn in list USAGE_INSNS. */
3683 skip_usage_debug_insns (rtx usage_insns
)
3687 /* Skip debug insns. */
3688 for (insn
= usage_insns
;
3689 insn
!= NULL_RTX
&& GET_CODE (insn
) == INSN_LIST
;
3690 insn
= XEXP (insn
, 1))
3695 /* Return true if we need secondary memory moves for insn in
3696 USAGE_INSNS after inserting inherited pseudo of class INHER_CL
3699 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED
,
3700 rtx usage_insns ATTRIBUTE_UNUSED
)
3702 #ifndef SECONDARY_MEMORY_NEEDED
3705 rtx insn
, set
, dest
;
3708 if (inher_cl
== ALL_REGS
3709 || (insn
= skip_usage_debug_insns (usage_insns
)) == NULL_RTX
)
3711 lra_assert (INSN_P (insn
));
3712 if ((set
= single_set (insn
)) == NULL_RTX
|| ! REG_P (SET_DEST (set
)))
3714 dest
= SET_DEST (set
);
3717 lra_assert (inher_cl
!= NO_REGS
);
3718 cl
= get_reg_class (REGNO (dest
));
3719 return (cl
!= NO_REGS
&& cl
!= ALL_REGS
3720 && SECONDARY_MEMORY_NEEDED (inher_cl
, cl
, GET_MODE (dest
)));
3724 /* Registers involved in inheritance/split in the current EBB
3725 (inheritance/split pseudos and original registers). */
3726 static bitmap_head check_only_regs
;
3728 /* Do inheritance transformations for insn INSN, which defines (if
3729 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which
3730 instruction in the EBB next uses ORIGINAL_REGNO; it has the same
3731 form as the "insns" field of usage_insns. Return true if we
3732 succeed in such transformation.
3734 The transformations look like:
3737 ... p <- i (new insn)
3739 <- ... p ... <- ... i ...
3741 ... i <- p (new insn)
3742 <- ... p ... <- ... i ...
3744 <- ... p ... <- ... i ...
3745 where p is a spilled original pseudo and i is a new inheritance pseudo.
3748 The inheritance pseudo has the smallest class of two classes CL and
3749 class of ORIGINAL REGNO. */
3751 inherit_reload_reg (bool def_p
, int original_regno
,
3752 enum reg_class cl
, rtx insn
, rtx next_usage_insns
)
3754 enum reg_class rclass
= lra_get_allocno_class (original_regno
);
3755 rtx original_reg
= regno_reg_rtx
[original_regno
];
3756 rtx new_reg
, new_insns
, usage_insn
;
3758 lra_assert (! usage_insns
[original_regno
].after_p
);
3759 if (lra_dump_file
!= NULL
)
3760 fprintf (lra_dump_file
,
3761 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n");
3762 if (! ira_reg_classes_intersect_p
[cl
][rclass
])
3764 if (lra_dump_file
!= NULL
)
3766 fprintf (lra_dump_file
,
3767 " Rejecting inheritance for %d "
3768 "because of disjoint classes %s and %s\n",
3769 original_regno
, reg_class_names
[cl
],
3770 reg_class_names
[rclass
]);
3771 fprintf (lra_dump_file
,
3772 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
3776 if ((ira_class_subset_p
[cl
][rclass
] && cl
!= rclass
)
3777 /* We don't use a subset of two classes because it can be
3778 NO_REGS. This transformation is still profitable in most
3779 cases even if the classes are not intersected as register
3780 move is probably cheaper than a memory load. */
3781 || ira_class_hard_regs_num
[cl
] < ira_class_hard_regs_num
[rclass
])
3783 if (lra_dump_file
!= NULL
)
3784 fprintf (lra_dump_file
, " Use smallest class of %s and %s\n",
3785 reg_class_names
[cl
], reg_class_names
[rclass
]);
3789 if (check_secondary_memory_needed_p (cl
, next_usage_insns
))
3791 /* Reject inheritance resulting in secondary memory moves.
3792 Otherwise, there is a danger in LRA cycling. Also such
3793 transformation will be unprofitable. */
3794 if (lra_dump_file
!= NULL
)
3796 rtx insn
= skip_usage_debug_insns (next_usage_insns
);
3797 rtx set
= single_set (insn
);
3799 lra_assert (set
!= NULL_RTX
);
3801 rtx dest
= SET_DEST (set
);
3803 lra_assert (REG_P (dest
));
3804 fprintf (lra_dump_file
,
3805 " Rejecting inheritance for insn %d(%s)<-%d(%s) "
3806 "as secondary mem is needed\n",
3807 REGNO (dest
), reg_class_names
[get_reg_class (REGNO (dest
))],
3808 original_regno
, reg_class_names
[cl
]);
3809 fprintf (lra_dump_file
,
3810 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
3814 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
3815 rclass
, "inheritance");
3818 emit_move_insn (original_reg
, new_reg
);
3820 emit_move_insn (new_reg
, original_reg
);
3821 new_insns
= get_insns ();
3823 if (NEXT_INSN (new_insns
) != NULL_RTX
)
3825 if (lra_dump_file
!= NULL
)
3827 fprintf (lra_dump_file
,
3828 " Rejecting inheritance %d->%d "
3829 "as it results in 2 or more insns:\n",
3830 original_regno
, REGNO (new_reg
));
3831 dump_rtl_slim (lra_dump_file
, new_insns
, NULL_RTX
, -1, 0);
3832 fprintf (lra_dump_file
,
3833 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
3837 substitute_pseudo (&insn
, original_regno
, new_reg
);
3838 lra_update_insn_regno_info (insn
);
3840 /* We now have a new usage insn for original regno. */
3841 setup_next_usage_insn (original_regno
, new_insns
, reloads_num
, false);
3842 if (lra_dump_file
!= NULL
)
3843 fprintf (lra_dump_file
, " Original reg change %d->%d (bb%d):\n",
3844 original_regno
, REGNO (new_reg
), BLOCK_FOR_INSN (insn
)->index
);
3845 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
3846 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
3847 bitmap_set_bit (&check_only_regs
, original_regno
);
3848 bitmap_set_bit (&lra_inheritance_pseudos
, REGNO (new_reg
));
3850 lra_process_new_insns (insn
, NULL_RTX
, new_insns
,
3851 "Add original<-inheritance");
3853 lra_process_new_insns (insn
, new_insns
, NULL_RTX
,
3854 "Add inheritance<-original");
3855 while (next_usage_insns
!= NULL_RTX
)
3857 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
3859 usage_insn
= next_usage_insns
;
3860 lra_assert (NONDEBUG_INSN_P (usage_insn
));
3861 next_usage_insns
= NULL
;
3865 usage_insn
= XEXP (next_usage_insns
, 0);
3866 lra_assert (DEBUG_INSN_P (usage_insn
));
3867 next_usage_insns
= XEXP (next_usage_insns
, 1);
3869 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
3870 lra_update_insn_regno_info (usage_insn
);
3871 if (lra_dump_file
!= NULL
)
3873 fprintf (lra_dump_file
,
3874 " Inheritance reuse change %d->%d (bb%d):\n",
3875 original_regno
, REGNO (new_reg
),
3876 BLOCK_FOR_INSN (usage_insn
)->index
);
3877 dump_insn_slim (lra_dump_file
, usage_insn
);
3880 if (lra_dump_file
!= NULL
)
3881 fprintf (lra_dump_file
,
3882 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
3886 /* Return true if we need a caller save/restore for pseudo REGNO which
3887 was assigned to a hard register. */
3889 need_for_call_save_p (int regno
)
3891 lra_assert (regno
>= FIRST_PSEUDO_REGISTER
&& reg_renumber
[regno
] >= 0);
3892 return (usage_insns
[regno
].calls_num
< calls_num
3893 && (overlaps_hard_reg_set_p
3895 PSEUDO_REGNO_MODE (regno
), reg_renumber
[regno
])));
3898 /* Global registers occuring in the current EBB. */
3899 static bitmap_head ebb_global_regs
;
3901 /* Return true if we need a split for hard register REGNO or pseudo
3902 REGNO which was assigned to a hard register.
3903 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be
3904 used for reloads since the EBB end. It is an approximation of the
3905 used hard registers in the split range. The exact value would
3906 require expensive calculations. If we were aggressive with
3907 splitting because of the approximation, the split pseudo will save
3908 the same hard register assignment and will be removed in the undo
3909 pass. We still need the approximation because too aggressive
3910 splitting would result in too inaccurate cost calculation in the
3911 assignment pass because of too many generated moves which will be
3912 probably removed in the undo pass. */
3914 need_for_split_p (HARD_REG_SET potential_reload_hard_regs
, int regno
)
3916 int hard_regno
= regno
< FIRST_PSEUDO_REGISTER
? regno
: reg_renumber
[regno
];
3918 lra_assert (hard_regno
>= 0);
3919 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs
, hard_regno
)
3920 /* Don't split eliminable hard registers, otherwise we can
3921 split hard registers like hard frame pointer, which
3922 lives on BB start/end according to DF-infrastructure,
3923 when there is a pseudo assigned to the register and
3924 living in the same BB. */
3925 && (regno
>= FIRST_PSEUDO_REGISTER
3926 || ! TEST_HARD_REG_BIT (eliminable_regset
, hard_regno
))
3927 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs
, hard_regno
)
3928 /* We need at least 2 reloads to make pseudo splitting
3929 profitable. We should provide hard regno splitting in
3930 any case to solve 1st insn scheduling problem when
3931 moving hard register definition up might result in
3932 impossibility to find hard register for reload pseudo of
3933 small register class. */
3934 && (usage_insns
[regno
].reloads_num
3935 + (regno
< FIRST_PSEUDO_REGISTER
? 0 : 2) < reloads_num
)
3936 && (regno
< FIRST_PSEUDO_REGISTER
3937 /* For short living pseudos, spilling + inheritance can
3938 be considered a substitution for splitting.
3939 Therefore we do not splitting for local pseudos. It
3940 decreases also aggressiveness of splitting. The
3941 minimal number of references is chosen taking into
3942 account that for 2 references splitting has no sense
3943 as we can just spill the pseudo. */
3944 || (regno
>= FIRST_PSEUDO_REGISTER
3945 && lra_reg_info
[regno
].nrefs
> 3
3946 && bitmap_bit_p (&ebb_global_regs
, regno
))))
3947 || (regno
>= FIRST_PSEUDO_REGISTER
&& need_for_call_save_p (regno
)));
3950 /* Return class for the split pseudo created from original pseudo with
3951 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We
3952 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and
3953 results in no secondary memory movements. */
3954 static enum reg_class
3955 choose_split_class (enum reg_class allocno_class
,
3956 int hard_regno ATTRIBUTE_UNUSED
,
3957 enum machine_mode mode ATTRIBUTE_UNUSED
)
3959 #ifndef SECONDARY_MEMORY_NEEDED
3960 return allocno_class
;
3963 enum reg_class cl
, best_cl
= NO_REGS
;
3964 enum reg_class hard_reg_class ATTRIBUTE_UNUSED
3965 = REGNO_REG_CLASS (hard_regno
);
3967 if (! SECONDARY_MEMORY_NEEDED (allocno_class
, allocno_class
, mode
)
3968 && TEST_HARD_REG_BIT (reg_class_contents
[allocno_class
], hard_regno
))
3969 return allocno_class
;
3971 (cl
= reg_class_subclasses
[allocno_class
][i
]) != LIM_REG_CLASSES
;
3973 if (! SECONDARY_MEMORY_NEEDED (cl
, hard_reg_class
, mode
)
3974 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class
, cl
, mode
)
3975 && TEST_HARD_REG_BIT (reg_class_contents
[cl
], hard_regno
)
3976 && (best_cl
== NO_REGS
3977 || ira_class_hard_regs_num
[best_cl
] < ira_class_hard_regs_num
[cl
]))
3983 /* Do split transformations for insn INSN, which defines or uses
3984 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in
3985 the EBB next uses ORIGINAL_REGNO; it has the same form as the
3986 "insns" field of usage_insns.
3988 The transformations look like:
3991 ... s <- p (new insn -- save)
3993 ... p <- s (new insn -- restore)
3994 <- ... p ... <- ... p ...
3996 <- ... p ... <- ... p ...
3997 ... s <- p (new insn -- save)
3999 ... p <- s (new insn -- restore)
4000 <- ... p ... <- ... p ...
4002 where p is an original pseudo got a hard register or a hard
4003 register and s is a new split pseudo. The save is put before INSN
4004 if BEFORE_P is true. Return true if we succeed in such
4007 split_reg (bool before_p
, int original_regno
, rtx insn
, rtx next_usage_insns
)
4009 enum reg_class rclass
;
4012 rtx new_reg
, save
, restore
, usage_insn
;
4016 if (original_regno
< FIRST_PSEUDO_REGISTER
)
4018 rclass
= ira_allocno_class_translate
[REGNO_REG_CLASS (original_regno
)];
4019 hard_regno
= original_regno
;
4020 call_save_p
= false;
4024 hard_regno
= reg_renumber
[original_regno
];
4025 rclass
= lra_get_allocno_class (original_regno
);
4026 original_reg
= regno_reg_rtx
[original_regno
];
4027 call_save_p
= need_for_call_save_p (original_regno
);
4029 original_reg
= regno_reg_rtx
[original_regno
];
4030 lra_assert (hard_regno
>= 0);
4031 if (lra_dump_file
!= NULL
)
4032 fprintf (lra_dump_file
,
4033 " ((((((((((((((((((((((((((((((((((((((((((((((((\n");
4036 enum machine_mode sec_mode
;
4038 #ifdef SECONDARY_MEMORY_NEEDED_MODE
4039 sec_mode
= SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (original_reg
));
4041 sec_mode
= GET_MODE (original_reg
);
4043 new_reg
= lra_create_new_reg (sec_mode
, NULL_RTX
,
4048 rclass
= choose_split_class (rclass
, hard_regno
,
4049 GET_MODE (original_reg
));
4050 if (rclass
== NO_REGS
)
4052 if (lra_dump_file
!= NULL
)
4054 fprintf (lra_dump_file
,
4055 " Rejecting split of %d(%s): "
4056 "no good reg class for %d(%s)\n",
4058 reg_class_names
[lra_get_allocno_class (original_regno
)],
4060 reg_class_names
[REGNO_REG_CLASS (hard_regno
)]);
4063 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4067 new_reg
= lra_create_new_reg (GET_MODE (original_reg
), original_reg
,
4069 reg_renumber
[REGNO (new_reg
)] = hard_regno
;
4071 save
= emit_spill_move (true, new_reg
, original_reg
);
4072 if (NEXT_INSN (save
) != NULL_RTX
)
4074 lra_assert (! call_save_p
);
4075 if (lra_dump_file
!= NULL
)
4079 " Rejecting split %d->%d resulting in > 2 %s save insns:\n",
4080 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4081 dump_rtl_slim (lra_dump_file
, save
, NULL_RTX
, -1, 0);
4082 fprintf (lra_dump_file
,
4083 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4087 restore
= emit_spill_move (false, new_reg
, original_reg
);
4088 if (NEXT_INSN (restore
) != NULL_RTX
)
4090 lra_assert (! call_save_p
);
4091 if (lra_dump_file
!= NULL
)
4093 fprintf (lra_dump_file
,
4094 " Rejecting split %d->%d "
4095 "resulting in > 2 %s restore insns:\n",
4096 original_regno
, REGNO (new_reg
), call_save_p
? "call" : "");
4097 dump_rtl_slim (lra_dump_file
, restore
, NULL_RTX
, -1, 0);
4098 fprintf (lra_dump_file
,
4099 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4103 after_p
= usage_insns
[original_regno
].after_p
;
4104 lra_reg_info
[REGNO (new_reg
)].restore_regno
= original_regno
;
4105 bitmap_set_bit (&check_only_regs
, REGNO (new_reg
));
4106 bitmap_set_bit (&check_only_regs
, original_regno
);
4107 bitmap_set_bit (&lra_split_regs
, REGNO (new_reg
));
4110 if (GET_CODE (next_usage_insns
) != INSN_LIST
)
4112 usage_insn
= next_usage_insns
;
4115 usage_insn
= XEXP (next_usage_insns
, 0);
4116 lra_assert (DEBUG_INSN_P (usage_insn
));
4117 next_usage_insns
= XEXP (next_usage_insns
, 1);
4118 substitute_pseudo (&usage_insn
, original_regno
, new_reg
);
4119 lra_update_insn_regno_info (usage_insn
);
4120 if (lra_dump_file
!= NULL
)
4122 fprintf (lra_dump_file
, " Split reuse change %d->%d:\n",
4123 original_regno
, REGNO (new_reg
));
4124 dump_insn_slim (lra_dump_file
, usage_insn
);
4127 lra_assert (NOTE_P (usage_insn
) || NONDEBUG_INSN_P (usage_insn
));
4128 lra_assert (usage_insn
!= insn
|| (after_p
&& before_p
));
4129 lra_process_new_insns (usage_insn
, after_p
? NULL_RTX
: restore
,
4130 after_p
? restore
: NULL_RTX
,
4132 ? "Add reg<-save" : "Add reg<-split");
4133 lra_process_new_insns (insn
, before_p
? save
: NULL_RTX
,
4134 before_p
? NULL_RTX
: save
,
4136 ? "Add save<-reg" : "Add split<-reg");
4137 if (lra_dump_file
!= NULL
)
4138 fprintf (lra_dump_file
,
4139 " ))))))))))))))))))))))))))))))))))))))))))))))))\n");
4143 /* Recognize that we need a split transformation for insn INSN, which
4144 defines or uses REGNO in its insn biggest MODE (we use it only if
4145 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains
4146 hard registers which might be used for reloads since the EBB end.
4147 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla
4148 uid before starting INSN processing. Return true if we succeed in
4149 such transformation. */
4151 split_if_necessary (int regno
, enum machine_mode mode
,
4152 HARD_REG_SET potential_reload_hard_regs
,
4153 bool before_p
, rtx insn
, int max_uid
)
4157 rtx next_usage_insns
;
4159 if (regno
< FIRST_PSEUDO_REGISTER
)
4160 nregs
= hard_regno_nregs
[regno
][mode
];
4161 for (i
= 0; i
< nregs
; i
++)
4162 if (usage_insns
[regno
+ i
].check
== curr_usage_insns_check
4163 && (next_usage_insns
= usage_insns
[regno
+ i
].insns
) != NULL_RTX
4164 /* To avoid processing the register twice or more. */
4165 && ((GET_CODE (next_usage_insns
) != INSN_LIST
4166 && INSN_UID (next_usage_insns
) < max_uid
)
4167 || (GET_CODE (next_usage_insns
) == INSN_LIST
4168 && (INSN_UID (XEXP (next_usage_insns
, 0)) < max_uid
)))
4169 && need_for_split_p (potential_reload_hard_regs
, regno
+ i
)
4170 && split_reg (before_p
, regno
+ i
, insn
, next_usage_insns
))
4175 /* Check only registers living at the current program point in the
4177 static bitmap_head live_regs
;
4179 /* Update live info in EBB given by its HEAD and TAIL insns after
4180 inheritance/split transformation. The function removes dead moves
4183 update_ebb_live_info (rtx head
, rtx tail
)
4190 basic_block last_bb
, prev_bb
, curr_bb
;
4192 struct lra_insn_reg
*reg
;
4196 last_bb
= BLOCK_FOR_INSN (tail
);
4198 for (curr_insn
= tail
;
4199 curr_insn
!= PREV_INSN (head
);
4200 curr_insn
= prev_insn
)
4202 prev_insn
= PREV_INSN (curr_insn
);
4203 /* We need to process empty blocks too. They contain
4204 NOTE_INSN_BASIC_BLOCK referring for the basic block. */
4205 if (NOTE_P (curr_insn
) && NOTE_KIND (curr_insn
) != NOTE_INSN_BASIC_BLOCK
)
4207 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4208 if (curr_bb
!= prev_bb
)
4210 if (prev_bb
!= NULL
)
4212 /* Update df_get_live_in (prev_bb): */
4213 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4214 if (bitmap_bit_p (&live_regs
, j
))
4215 bitmap_set_bit (df_get_live_in (prev_bb
), j
);
4217 bitmap_clear_bit (df_get_live_in (prev_bb
), j
);
4219 if (curr_bb
!= last_bb
)
4221 /* Update df_get_live_out (curr_bb): */
4222 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs
, 0, j
, bi
)
4224 live_p
= bitmap_bit_p (&live_regs
, j
);
4226 FOR_EACH_EDGE (e
, ei
, curr_bb
->succs
)
4227 if (bitmap_bit_p (df_get_live_in (e
->dest
), j
))
4233 bitmap_set_bit (df_get_live_out (curr_bb
), j
);
4235 bitmap_clear_bit (df_get_live_out (curr_bb
), j
);
4239 bitmap_and (&live_regs
, &check_only_regs
, df_get_live_out (curr_bb
));
4241 if (! NONDEBUG_INSN_P (curr_insn
))
4243 curr_id
= lra_get_insn_recog_data (curr_insn
);
4245 if ((set
= single_set (curr_insn
)) != NULL_RTX
&& REG_P (SET_DEST (set
))
4246 && (regno
= REGNO (SET_DEST (set
))) >= FIRST_PSEUDO_REGISTER
4247 && bitmap_bit_p (&check_only_regs
, regno
)
4248 && ! bitmap_bit_p (&live_regs
, regno
))
4250 /* See which defined values die here. */
4251 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4252 if (reg
->type
== OP_OUT
&& ! reg
->subreg_p
)
4253 bitmap_clear_bit (&live_regs
, reg
->regno
);
4254 /* Mark each used value as live. */
4255 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4256 if (reg
->type
== OP_IN
4257 && bitmap_bit_p (&check_only_regs
, reg
->regno
))
4258 bitmap_set_bit (&live_regs
, reg
->regno
);
4259 /* It is quite important to remove dead move insns because it
4260 means removing dead store. We don't need to process them for
4264 if (lra_dump_file
!= NULL
)
4266 fprintf (lra_dump_file
, " Removing dead insn:\n ");
4267 dump_insn_slim (lra_dump_file
, curr_insn
);
4269 lra_set_insn_deleted (curr_insn
);
4274 /* The structure describes info to do an inheritance for the current
4275 insn. We need to collect such info first before doing the
4276 transformations because the transformations change the insn
4277 internal representation. */
4280 /* Original regno. */
4282 /* Subsequent insns which can inherit original reg value. */
4286 /* Array containing all info for doing inheritance from the current
4288 static struct to_inherit to_inherit
[LRA_MAX_INSN_RELOADS
];
4290 /* Number elements in the previous array. */
4291 static int to_inherit_num
;
4293 /* Add inheritance info REGNO and INSNS. Their meaning is described in
4294 structure to_inherit. */
4296 add_to_inherit (int regno
, rtx insns
)
4300 for (i
= 0; i
< to_inherit_num
; i
++)
4301 if (to_inherit
[i
].regno
== regno
)
4303 lra_assert (to_inherit_num
< LRA_MAX_INSN_RELOADS
);
4304 to_inherit
[to_inherit_num
].regno
= regno
;
4305 to_inherit
[to_inherit_num
++].insns
= insns
;
4308 /* Return the last non-debug insn in basic block BB, or the block begin
4311 get_last_insertion_point (basic_block bb
)
4315 FOR_BB_INSNS_REVERSE (bb
, insn
)
4316 if (NONDEBUG_INSN_P (insn
) || NOTE_INSN_BASIC_BLOCK_P (insn
))
4321 /* Set up RES by registers living on edges FROM except the edge (FROM,
4322 TO) or by registers set up in a jump insn in BB FROM. */
4324 get_live_on_other_edges (basic_block from
, basic_block to
, bitmap res
)
4327 struct lra_insn_reg
*reg
;
4331 lra_assert (to
!= NULL
);
4333 FOR_EACH_EDGE (e
, ei
, from
->succs
)
4335 bitmap_ior_into (res
, df_get_live_in (e
->dest
));
4336 last
= get_last_insertion_point (from
);
4337 if (! JUMP_P (last
))
4339 curr_id
= lra_get_insn_recog_data (last
);
4340 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4341 if (reg
->type
!= OP_IN
)
4342 bitmap_set_bit (res
, reg
->regno
);
4345 /* Used as a temporary results of some bitmap calculations. */
4346 static bitmap_head temp_bitmap
;
4348 /* Do inheritance/split transformations in EBB starting with HEAD and
4349 finishing on TAIL. We process EBB insns in the reverse order.
4350 Return true if we did any inheritance/split transformation in the
4353 We should avoid excessive splitting which results in worse code
4354 because of inaccurate cost calculations for spilling new split
4355 pseudos in such case. To achieve this we do splitting only if
4356 register pressure is high in given basic block and there are reload
4357 pseudos requiring hard registers. We could do more register
4358 pressure calculations at any given program point to avoid necessary
4359 splitting even more but it is to expensive and the current approach
4360 works well enough. */
4362 inherit_in_ebb (rtx head
, rtx tail
)
4364 int i
, src_regno
, dst_regno
, nregs
;
4365 bool change_p
, succ_p
;
4366 rtx prev_insn
, next_usage_insns
, set
, last_insn
;
4368 struct lra_insn_reg
*reg
;
4369 basic_block last_processed_bb
, curr_bb
= NULL
;
4370 HARD_REG_SET potential_reload_hard_regs
, live_hard_regs
;
4374 bool head_p
, after_p
;
4377 curr_usage_insns_check
++;
4378 reloads_num
= calls_num
= 0;
4379 bitmap_clear (&check_only_regs
);
4380 last_processed_bb
= NULL
;
4381 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
4382 CLEAR_HARD_REG_SET (live_hard_regs
);
4383 /* We don't process new insns generated in the loop. */
4384 for (curr_insn
= tail
; curr_insn
!= PREV_INSN (head
); curr_insn
= prev_insn
)
4386 prev_insn
= PREV_INSN (curr_insn
);
4387 if (BLOCK_FOR_INSN (curr_insn
) != NULL
)
4388 curr_bb
= BLOCK_FOR_INSN (curr_insn
);
4389 if (last_processed_bb
!= curr_bb
)
4391 /* We are at the end of BB. Add qualified living
4392 pseudos for potential splitting. */
4393 to_process
= df_get_live_out (curr_bb
);
4394 if (last_processed_bb
!= NULL
)
4396 /* We are somewhere in the middle of EBB. */
4397 get_live_on_other_edges (curr_bb
, last_processed_bb
,
4399 to_process
= &temp_bitmap
;
4401 last_processed_bb
= curr_bb
;
4402 last_insn
= get_last_insertion_point (curr_bb
);
4403 after_p
= (! JUMP_P (last_insn
)
4404 && (! CALL_P (last_insn
)
4405 || (find_reg_note (last_insn
,
4406 REG_NORETURN
, NULL_RTX
) == NULL_RTX
4407 && ! SIBLING_CALL_P (last_insn
))));
4408 REG_SET_TO_HARD_REG_SET (live_hard_regs
, df_get_live_out (curr_bb
));
4409 IOR_HARD_REG_SET (live_hard_regs
, eliminable_regset
);
4410 IOR_HARD_REG_SET (live_hard_regs
, lra_no_alloc_regs
);
4411 CLEAR_HARD_REG_SET (potential_reload_hard_regs
);
4412 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
4414 if ((int) j
>= lra_constraint_new_regno_start
)
4416 if (j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
4418 if (j
< FIRST_PSEUDO_REGISTER
)
4419 SET_HARD_REG_BIT (live_hard_regs
, j
);
4421 add_to_hard_reg_set (&live_hard_regs
,
4422 PSEUDO_REGNO_MODE (j
),
4424 setup_next_usage_insn (j
, last_insn
, reloads_num
, after_p
);
4428 src_regno
= dst_regno
= -1;
4429 if (NONDEBUG_INSN_P (curr_insn
)
4430 && (set
= single_set (curr_insn
)) != NULL_RTX
4431 && REG_P (SET_DEST (set
)) && REG_P (SET_SRC (set
)))
4433 src_regno
= REGNO (SET_SRC (set
));
4434 dst_regno
= REGNO (SET_DEST (set
));
4436 if (src_regno
< lra_constraint_new_regno_start
4437 && src_regno
>= FIRST_PSEUDO_REGISTER
4438 && reg_renumber
[src_regno
] < 0
4439 && dst_regno
>= lra_constraint_new_regno_start
4440 && (cl
= lra_get_allocno_class (dst_regno
)) != NO_REGS
)
4442 /* 'reload_pseudo <- original_pseudo'. */
4445 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
4446 && (next_usage_insns
= usage_insns
[src_regno
].insns
) != NULL_RTX
)
4447 succ_p
= inherit_reload_reg (false, src_regno
, cl
,
4448 curr_insn
, next_usage_insns
);
4452 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
4453 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
4454 IOR_HARD_REG_SET (potential_reload_hard_regs
,
4455 reg_class_contents
[cl
]);
4457 else if (src_regno
>= lra_constraint_new_regno_start
4458 && dst_regno
< lra_constraint_new_regno_start
4459 && dst_regno
>= FIRST_PSEUDO_REGISTER
4460 && reg_renumber
[dst_regno
] < 0
4461 && (cl
= lra_get_allocno_class (src_regno
)) != NO_REGS
4462 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
4463 && (next_usage_insns
4464 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
4467 /* 'original_pseudo <- reload_pseudo'. */
4468 if (! JUMP_P (curr_insn
)
4469 && inherit_reload_reg (true, dst_regno
, cl
,
4470 curr_insn
, next_usage_insns
))
4473 usage_insns
[dst_regno
].check
= 0;
4474 if (hard_reg_set_subset_p (reg_class_contents
[cl
], live_hard_regs
))
4475 IOR_HARD_REG_SET (potential_reload_hard_regs
,
4476 reg_class_contents
[cl
]);
4478 else if (INSN_P (curr_insn
))
4480 int max_uid
= get_max_uid ();
4482 curr_id
= lra_get_insn_recog_data (curr_insn
);
4484 /* Process insn definitions. */
4485 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4486 if (reg
->type
!= OP_IN
4487 && (dst_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
4489 if (dst_regno
>= FIRST_PSEUDO_REGISTER
&& reg
->type
== OP_OUT
4490 && reg_renumber
[dst_regno
] < 0 && ! reg
->subreg_p
4491 && usage_insns
[dst_regno
].check
== curr_usage_insns_check
4492 && (next_usage_insns
4493 = usage_insns
[dst_regno
].insns
) != NULL_RTX
)
4495 struct lra_insn_reg
*r
;
4497 for (r
= curr_id
->regs
; r
!= NULL
; r
= r
->next
)
4498 if (r
->type
!= OP_OUT
&& r
->regno
== dst_regno
)
4500 /* Don't do inheritance if the pseudo is also
4501 used in the insn. */
4503 /* We can not do inheritance right now
4504 because the current insn reg info (chain
4505 regs) can change after that. */
4506 add_to_inherit (dst_regno
, next_usage_insns
);
4508 /* We can not process one reg twice here because of
4509 usage_insns invalidation. */
4510 if ((dst_regno
< FIRST_PSEUDO_REGISTER
4511 || reg_renumber
[dst_regno
] >= 0)
4512 && ! reg
->subreg_p
&& reg
->type
== OP_OUT
)
4516 if (split_if_necessary (dst_regno
, reg
->biggest_mode
,
4517 potential_reload_hard_regs
,
4518 false, curr_insn
, max_uid
))
4520 CLEAR_HARD_REG_SET (s
);
4521 if (dst_regno
< FIRST_PSEUDO_REGISTER
)
4522 add_to_hard_reg_set (&s
, reg
->biggest_mode
, dst_regno
);
4524 add_to_hard_reg_set (&s
, PSEUDO_REGNO_MODE (dst_regno
),
4525 reg_renumber
[dst_regno
]);
4526 AND_COMPL_HARD_REG_SET (live_hard_regs
, s
);
4528 /* We should invalidate potential inheritance or
4529 splitting for the current insn usages to the next
4530 usage insns (see code below) as the output pseudo
4532 if ((dst_regno
>= FIRST_PSEUDO_REGISTER
4533 && reg_renumber
[dst_regno
] < 0)
4534 || (reg
->type
== OP_OUT
&& ! reg
->subreg_p
4535 && (dst_regno
< FIRST_PSEUDO_REGISTER
4536 || reg_renumber
[dst_regno
] >= 0)))
4539 if (dst_regno
>= FIRST_PSEUDO_REGISTER
)
4540 usage_insns
[dst_regno
].check
= 0;
4543 nregs
= hard_regno_nregs
[dst_regno
][reg
->biggest_mode
];
4544 for (i
= 0; i
< nregs
; i
++)
4545 usage_insns
[dst_regno
+ i
].check
= 0;
4549 if (! JUMP_P (curr_insn
))
4550 for (i
= 0; i
< to_inherit_num
; i
++)
4551 if (inherit_reload_reg (true, to_inherit
[i
].regno
,
4552 ALL_REGS
, curr_insn
,
4553 to_inherit
[i
].insns
))
4555 if (CALL_P (curr_insn
))
4557 rtx cheap
, pat
, dest
, restore
;
4558 int regno
, hard_regno
;
4561 if ((cheap
= find_reg_note (curr_insn
,
4562 REG_RETURNED
, NULL_RTX
)) != NULL_RTX
4563 && ((cheap
= XEXP (cheap
, 0)), true)
4564 && (regno
= REGNO (cheap
)) >= FIRST_PSEUDO_REGISTER
4565 && (hard_regno
= reg_renumber
[regno
]) >= 0
4566 /* If there are pending saves/restores, the
4567 optimization is not worth. */
4568 && usage_insns
[regno
].calls_num
== calls_num
- 1
4569 && TEST_HARD_REG_BIT (call_used_reg_set
, hard_regno
))
4571 /* Restore the pseudo from the call result as
4572 REG_RETURNED note says that the pseudo value is
4573 in the call result and the pseudo is an argument
4575 pat
= PATTERN (curr_insn
);
4576 if (GET_CODE (pat
) == PARALLEL
)
4577 pat
= XVECEXP (pat
, 0, 0);
4578 dest
= SET_DEST (pat
);
4580 emit_move_insn (cheap
, copy_rtx (dest
));
4581 restore
= get_insns ();
4583 lra_process_new_insns (curr_insn
, NULL
, restore
,
4584 "Inserting call parameter restore");
4585 /* We don't need to save/restore of the pseudo from
4587 usage_insns
[regno
].calls_num
= calls_num
;
4588 bitmap_set_bit (&check_only_regs
, regno
);
4592 /* Process insn usages. */
4593 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4594 if ((reg
->type
!= OP_OUT
4595 || (reg
->type
== OP_OUT
&& reg
->subreg_p
))
4596 && (src_regno
= reg
->regno
) < lra_constraint_new_regno_start
)
4598 if (src_regno
>= FIRST_PSEUDO_REGISTER
4599 && reg_renumber
[src_regno
] < 0 && reg
->type
== OP_IN
)
4601 if (usage_insns
[src_regno
].check
== curr_usage_insns_check
4602 && (next_usage_insns
4603 = usage_insns
[src_regno
].insns
) != NULL_RTX
4604 && NONDEBUG_INSN_P (curr_insn
))
4605 add_to_inherit (src_regno
, next_usage_insns
);
4608 add_next_usage_insn (src_regno
, curr_insn
, reloads_num
);
4610 else if (src_regno
< FIRST_PSEUDO_REGISTER
4611 || reg_renumber
[src_regno
] >= 0)
4614 rtx use_insn
= curr_insn
;
4616 before_p
= (JUMP_P (curr_insn
)
4617 || (CALL_P (curr_insn
) && reg
->type
== OP_IN
));
4618 if (NONDEBUG_INSN_P (curr_insn
)
4619 && split_if_necessary (src_regno
, reg
->biggest_mode
,
4620 potential_reload_hard_regs
,
4621 before_p
, curr_insn
, max_uid
))
4624 lra_risky_transformations_p
= true;
4627 usage_insns
[src_regno
].check
= 0;
4629 use_insn
= PREV_INSN (curr_insn
);
4631 if (NONDEBUG_INSN_P (curr_insn
))
4633 if (src_regno
< FIRST_PSEUDO_REGISTER
)
4634 add_to_hard_reg_set (&live_hard_regs
,
4635 reg
->biggest_mode
, src_regno
);
4637 add_to_hard_reg_set (&live_hard_regs
,
4638 PSEUDO_REGNO_MODE (src_regno
),
4639 reg_renumber
[src_regno
]);
4641 add_next_usage_insn (src_regno
, use_insn
, reloads_num
);
4644 for (i
= 0; i
< to_inherit_num
; i
++)
4646 src_regno
= to_inherit
[i
].regno
;
4647 if (inherit_reload_reg (false, src_regno
, ALL_REGS
,
4648 curr_insn
, to_inherit
[i
].insns
))
4651 setup_next_usage_insn (src_regno
, curr_insn
, reloads_num
, false);
4654 /* We reached the start of the current basic block. */
4655 if (prev_insn
== NULL_RTX
|| prev_insn
== PREV_INSN (head
)
4656 || BLOCK_FOR_INSN (prev_insn
) != curr_bb
)
4658 /* We reached the beginning of the current block -- do
4659 rest of spliting in the current BB. */
4660 to_process
= df_get_live_in (curr_bb
);
4661 if (BLOCK_FOR_INSN (head
) != curr_bb
)
4663 /* We are somewhere in the middle of EBB. */
4664 get_live_on_other_edges (EDGE_PRED (curr_bb
, 0)->src
,
4665 curr_bb
, &temp_bitmap
);
4666 to_process
= &temp_bitmap
;
4669 EXECUTE_IF_SET_IN_BITMAP (to_process
, 0, j
, bi
)
4671 if ((int) j
>= lra_constraint_new_regno_start
)
4673 if (((int) j
< FIRST_PSEUDO_REGISTER
|| reg_renumber
[j
] >= 0)
4674 && usage_insns
[j
].check
== curr_usage_insns_check
4675 && (next_usage_insns
= usage_insns
[j
].insns
) != NULL_RTX
)
4677 if (need_for_split_p (potential_reload_hard_regs
, j
))
4679 if (lra_dump_file
!= NULL
&& head_p
)
4681 fprintf (lra_dump_file
,
4682 " ----------------------------------\n");
4685 if (split_reg (false, j
, bb_note (curr_bb
),
4689 usage_insns
[j
].check
= 0;
4697 /* This value affects EBB forming. If probability of edge from EBB to
4698 a BB is not greater than the following value, we don't add the BB
4700 #define EBB_PROBABILITY_CUTOFF (REG_BR_PROB_BASE / 2)
4702 /* Current number of inheritance/split iteration. */
4703 int lra_inheritance_iter
;
4705 /* Entry function for inheritance/split pass. */
4707 lra_inheritance (void)
4710 basic_block bb
, start_bb
;
4713 lra_inheritance_iter
++;
4714 if (lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
4716 timevar_push (TV_LRA_INHERITANCE
);
4717 if (lra_dump_file
!= NULL
)
4718 fprintf (lra_dump_file
, "\n********** Inheritance #%d: **********\n\n",
4719 lra_inheritance_iter
);
4720 curr_usage_insns_check
= 0;
4721 usage_insns
= XNEWVEC (struct usage_insns
, lra_constraint_new_regno_start
);
4722 for (i
= 0; i
< lra_constraint_new_regno_start
; i
++)
4723 usage_insns
[i
].check
= 0;
4724 bitmap_initialize (&check_only_regs
, ®_obstack
);
4725 bitmap_initialize (&live_regs
, ®_obstack
);
4726 bitmap_initialize (&temp_bitmap
, ®_obstack
);
4727 bitmap_initialize (&ebb_global_regs
, ®_obstack
);
4731 if (lra_dump_file
!= NULL
)
4732 fprintf (lra_dump_file
, "EBB");
4733 /* Form a EBB starting with BB. */
4734 bitmap_clear (&ebb_global_regs
);
4735 bitmap_ior_into (&ebb_global_regs
, df_get_live_in (bb
));
4738 if (lra_dump_file
!= NULL
)
4739 fprintf (lra_dump_file
, " %d", bb
->index
);
4740 if (bb
->next_bb
== EXIT_BLOCK_PTR
|| LABEL_P (BB_HEAD (bb
->next_bb
)))
4742 e
= find_fallthru_edge (bb
->succs
);
4745 if (e
->probability
<= EBB_PROBABILITY_CUTOFF
)
4749 bitmap_ior_into (&ebb_global_regs
, df_get_live_out (bb
));
4750 if (lra_dump_file
!= NULL
)
4751 fprintf (lra_dump_file
, "\n");
4752 if (inherit_in_ebb (BB_HEAD (start_bb
), BB_END (bb
)))
4753 /* Remember that the EBB head and tail can change in
4755 update_ebb_live_info (BB_HEAD (start_bb
), BB_END (bb
));
4757 bitmap_clear (&ebb_global_regs
);
4758 bitmap_clear (&temp_bitmap
);
4759 bitmap_clear (&live_regs
);
4760 bitmap_clear (&check_only_regs
);
4763 timevar_pop (TV_LRA_INHERITANCE
);
4768 /* This page contains code to undo failed inheritance/split
4771 /* Current number of iteration undoing inheritance/split. */
4772 int lra_undo_inheritance_iter
;
4774 /* Fix BB live info LIVE after removing pseudos created on pass doing
4775 inheritance/split which are REMOVED_PSEUDOS. */
4777 fix_bb_live_info (bitmap live
, bitmap removed_pseudos
)
4782 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos
, 0, regno
, bi
)
4783 if (bitmap_clear_bit (live
, regno
))
4784 bitmap_set_bit (live
, lra_reg_info
[regno
].restore_regno
);
4787 /* Return regno of the (subreg of) REG. Otherwise, return a negative
4792 if (GET_CODE (reg
) == SUBREG
)
4793 reg
= SUBREG_REG (reg
);
4799 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and
4800 return true if we did any change. The undo transformations for
4801 inheritance looks like
4805 p <- i, i <- p, and i <- i3
4806 where p is original pseudo from which inheritance pseudo i was
4807 created, i and i3 are removed inheritance pseudos, i2 is another
4808 not removed inheritance pseudo. All split pseudos or other
4809 occurrences of removed inheritance pseudos are changed on the
4810 corresponding original pseudos.
4812 The function also schedules insns changed and created during
4813 inheritance/split pass for processing by the subsequent constraint
4816 remove_inheritance_pseudos (bitmap remove_pseudos
)
4819 int regno
, sregno
, prev_sregno
, dregno
, restore_regno
;
4820 rtx set
, prev_set
, prev_insn
;
4821 bool change_p
, done_p
;
4823 change_p
= ! bitmap_empty_p (remove_pseudos
);
4824 /* We can not finish the function right away if CHANGE_P is true
4825 because we need to marks insns affected by previous
4826 inheritance/split pass for processing by the subsequent
4830 fix_bb_live_info (df_get_live_in (bb
), remove_pseudos
);
4831 fix_bb_live_info (df_get_live_out (bb
), remove_pseudos
);
4832 FOR_BB_INSNS_REVERSE (bb
, curr_insn
)
4834 if (! INSN_P (curr_insn
))
4837 sregno
= dregno
= -1;
4838 if (change_p
&& NONDEBUG_INSN_P (curr_insn
)
4839 && (set
= single_set (curr_insn
)) != NULL_RTX
)
4841 dregno
= get_regno (SET_DEST (set
));
4842 sregno
= get_regno (SET_SRC (set
));
4845 if (sregno
>= 0 && dregno
>= 0)
4847 if ((bitmap_bit_p (remove_pseudos
, sregno
)
4848 && (lra_reg_info
[sregno
].restore_regno
== dregno
4849 || (bitmap_bit_p (remove_pseudos
, dregno
)
4850 && (lra_reg_info
[sregno
].restore_regno
4851 == lra_reg_info
[dregno
].restore_regno
))))
4852 || (bitmap_bit_p (remove_pseudos
, dregno
)
4853 && lra_reg_info
[dregno
].restore_regno
== sregno
))
4854 /* One of the following cases:
4855 original <- removed inheritance pseudo
4856 removed inherit pseudo <- another removed inherit pseudo
4857 removed inherit pseudo <- original pseudo
4859 removed_split_pseudo <- original_reg
4860 original_reg <- removed_split_pseudo */
4862 if (lra_dump_file
!= NULL
)
4864 fprintf (lra_dump_file
, " Removing %s:\n",
4865 bitmap_bit_p (&lra_split_regs
, sregno
)
4866 || bitmap_bit_p (&lra_split_regs
, dregno
)
4867 ? "split" : "inheritance");
4868 dump_insn_slim (lra_dump_file
, curr_insn
);
4870 lra_set_insn_deleted (curr_insn
);
4873 else if (bitmap_bit_p (remove_pseudos
, sregno
)
4874 && bitmap_bit_p (&lra_inheritance_pseudos
, sregno
))
4876 /* Search the following pattern:
4877 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2
4878 original_pseudo <- inherit_or_split_pseudo1
4879 where the 2nd insn is the current insn and
4880 inherit_or_split_pseudo2 is not removed. If it is found,
4881 change the current insn onto:
4882 original_pseudo <- inherit_or_split_pseudo2. */
4883 for (prev_insn
= PREV_INSN (curr_insn
);
4884 prev_insn
!= NULL_RTX
&& ! NONDEBUG_INSN_P (prev_insn
);
4885 prev_insn
= PREV_INSN (prev_insn
))
4887 if (prev_insn
!= NULL_RTX
&& BLOCK_FOR_INSN (prev_insn
) == bb
4888 && (prev_set
= single_set (prev_insn
)) != NULL_RTX
4889 /* There should be no subregs in insn we are
4890 searching because only the original reg might
4891 be in subreg when we changed the mode of
4892 load/store for splitting. */
4893 && REG_P (SET_DEST (prev_set
))
4894 && REG_P (SET_SRC (prev_set
))
4895 && (int) REGNO (SET_DEST (prev_set
)) == sregno
4896 && ((prev_sregno
= REGNO (SET_SRC (prev_set
)))
4897 >= FIRST_PSEUDO_REGISTER
)
4898 /* As we consider chain of inheritance or
4899 splitting described in above comment we should
4900 check that sregno and prev_sregno were
4901 inheritance/split pseudos created from the
4902 same original regno. */
4903 && (lra_reg_info
[sregno
].restore_regno
4904 == lra_reg_info
[prev_sregno
].restore_regno
)
4905 && ! bitmap_bit_p (remove_pseudos
, prev_sregno
))
4907 lra_assert (GET_MODE (SET_SRC (prev_set
))
4908 == GET_MODE (regno_reg_rtx
[sregno
]));
4909 if (GET_CODE (SET_SRC (set
)) == SUBREG
)
4910 SUBREG_REG (SET_SRC (set
)) = SET_SRC (prev_set
);
4912 SET_SRC (set
) = SET_SRC (prev_set
);
4913 lra_push_insn_and_update_insn_regno_info (curr_insn
);
4914 lra_set_used_insn_alternative_by_uid
4915 (INSN_UID (curr_insn
), -1);
4917 if (lra_dump_file
!= NULL
)
4919 fprintf (lra_dump_file
, " Change reload insn:\n");
4920 dump_insn_slim (lra_dump_file
, curr_insn
);
4927 struct lra_insn_reg
*reg
;
4928 bool restored_regs_p
= false;
4929 bool kept_regs_p
= false;
4931 curr_id
= lra_get_insn_recog_data (curr_insn
);
4932 for (reg
= curr_id
->regs
; reg
!= NULL
; reg
= reg
->next
)
4935 restore_regno
= lra_reg_info
[regno
].restore_regno
;
4936 if (restore_regno
>= 0)
4938 if (change_p
&& bitmap_bit_p (remove_pseudos
, regno
))
4940 substitute_pseudo (&curr_insn
, regno
,
4941 regno_reg_rtx
[restore_regno
]);
4942 restored_regs_p
= true;
4948 if (NONDEBUG_INSN_P (curr_insn
) && kept_regs_p
)
4950 /* The instruction has changed since the previous
4951 constraints pass. */
4952 lra_push_insn_and_update_insn_regno_info (curr_insn
);
4953 lra_set_used_insn_alternative_by_uid
4954 (INSN_UID (curr_insn
), -1);
4956 else if (restored_regs_p
)
4957 /* The instruction has been restored to the form that
4958 it had during the previous constraints pass. */
4959 lra_update_insn_regno_info (curr_insn
);
4960 if (restored_regs_p
&& lra_dump_file
!= NULL
)
4962 fprintf (lra_dump_file
, " Insn after restoring regs:\n");
4963 dump_insn_slim (lra_dump_file
, curr_insn
);
4971 /* Entry function for undoing inheritance/split transformation. Return true
4972 if we did any RTL change in this pass. */
4974 lra_undo_inheritance (void)
4977 int restore_regno
, hard_regno
;
4978 int n_all_inherit
, n_inherit
, n_all_split
, n_split
;
4979 bitmap_head remove_pseudos
;
4983 lra_undo_inheritance_iter
++;
4984 if (lra_undo_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
)
4986 if (lra_dump_file
!= NULL
)
4987 fprintf (lra_dump_file
,
4988 "\n********** Undoing inheritance #%d: **********\n\n",
4989 lra_undo_inheritance_iter
);
4990 bitmap_initialize (&remove_pseudos
, ®_obstack
);
4991 n_inherit
= n_all_inherit
= 0;
4992 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
4993 if (lra_reg_info
[regno
].restore_regno
>= 0)
4996 if (reg_renumber
[regno
] < 0)
4997 bitmap_set_bit (&remove_pseudos
, regno
);
5001 if (lra_dump_file
!= NULL
&& n_all_inherit
!= 0)
5002 fprintf (lra_dump_file
, "Inherit %d out of %d (%.2f%%)\n",
5003 n_inherit
, n_all_inherit
,
5004 (double) n_inherit
/ n_all_inherit
* 100);
5005 n_split
= n_all_split
= 0;
5006 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5007 if ((restore_regno
= lra_reg_info
[regno
].restore_regno
) >= 0)
5010 hard_regno
= (restore_regno
>= FIRST_PSEUDO_REGISTER
5011 ? reg_renumber
[restore_regno
] : restore_regno
);
5012 if (hard_regno
< 0 || reg_renumber
[regno
] == hard_regno
)
5013 bitmap_set_bit (&remove_pseudos
, regno
);
5017 if (lra_dump_file
!= NULL
)
5018 fprintf (lra_dump_file
, " Keep split r%d (orig=r%d)\n",
5019 regno
, restore_regno
);
5022 if (lra_dump_file
!= NULL
&& n_all_split
!= 0)
5023 fprintf (lra_dump_file
, "Split %d out of %d (%.2f%%)\n",
5024 n_split
, n_all_split
,
5025 (double) n_split
/ n_all_split
* 100);
5026 change_p
= remove_inheritance_pseudos (&remove_pseudos
);
5027 bitmap_clear (&remove_pseudos
);
5028 /* Clear restore_regnos. */
5029 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos
, 0, regno
, bi
)
5030 lra_reg_info
[regno
].restore_regno
= -1;
5031 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs
, 0, regno
, bi
)
5032 lra_reg_info
[regno
].restore_regno
= -1;