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[official-gcc.git] / libgcc / longlong.h
blob4fbfbaeca4134cab267905d7f9d19502d18dd2d7
1 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
2 Copyright (C) 1991-2013 Free Software Foundation, Inc.
3
4 This file is part of the GNU C Library.
5
6 The GNU C Library is free software; you can redistribute it and/or
7 modify it under the terms of the GNU Lesser General Public
8 License as published by the Free Software Foundation; either
9 version 2.1 of the License, or (at your option) any later version.
10
11 In addition to the permissions in the GNU Lesser General Public
12 License, the Free Software Foundation gives you unlimited
13 permission to link the compiled version of this file into
14 combinations with other programs, and to distribute those
15 combinations without any restriction coming from the use of this
16 file. (The Lesser General Public License restrictions do apply in
17 other respects; for example, they cover modification of the file,
18 and distribution when not linked into a combine executable.)
19
20 The GNU C Library is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 Lesser General Public License for more details.
24
25 You should have received a copy of the GNU Lesser General Public
26 License along with the GNU C Library; if not, see
27 <http://www.gnu.org/licenses/>. */
28
29 /* You have to define the following before including this file:
30
31 UWtype -- An unsigned type, default type for operations (typically a "word")
32 UHWtype -- An unsigned type, at least half the size of UWtype.
33 UDWtype -- An unsigned type, at least twice as large a UWtype
34 W_TYPE_SIZE -- size in bits of UWtype
35
36 UQItype -- Unsigned 8 bit type.
37 SItype, USItype -- Signed and unsigned 32 bit types.
38 DItype, UDItype -- Signed and unsigned 64 bit types.
39
40 On a 32 bit machine UWtype should typically be USItype;
41 on a 64 bit machine, UWtype should typically be UDItype. */
42
43 #define __BITS4 (W_TYPE_SIZE / 4)
44 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
45 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
46 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
47
48 #ifndef W_TYPE_SIZE
49 #define W_TYPE_SIZE 32
50 #define UWtype USItype
51 #define UHWtype USItype
52 #define UDWtype UDItype
53 #endif
54
55 /* Used in glibc only. */
56 #ifndef attribute_hidden
57 #define attribute_hidden
58 #endif
59
60 extern const UQItype __clz_tab[256] attribute_hidden;
61
62 /* Define auxiliary asm macros.
63
64 1) umul_ppmm(high_prod, low_prod, multiplier, multiplicand) multiplies two
65 UWtype integers MULTIPLIER and MULTIPLICAND, and generates a two UWtype
66 word product in HIGH_PROD and LOW_PROD.
67
68 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
69 UDWtype product. This is just a variant of umul_ppmm.
70
71 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
72 denominator) divides a UDWtype, composed by the UWtype integers
73 HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
74 in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
75 than DENOMINATOR for correct operation. If, in addition, the most
76 significant bit of DENOMINATOR must be 1, then the pre-processor symbol
77 UDIV_NEEDS_NORMALIZATION is defined to 1.
78
79 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
80 denominator). Like udiv_qrnnd but the numbers are signed. The quotient
81 is rounded towards 0.
82
83 5) count_leading_zeros(count, x) counts the number of zero-bits from the
84 msb to the first nonzero bit in the UWtype X. This is the number of
85 steps X needs to be shifted left to set the msb. Undefined for X == 0,
86 unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
87
88 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
89 from the least significant end.
90
91 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
92 high_addend_2, low_addend_2) adds two UWtype integers, composed by
93 HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
94 respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
95 (i.e. carry out) is not stored anywhere, and is lost.
96
97 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
98 high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
99 composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
100 LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
101 and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
102 and is lost.
103
104 If any of these macros are left undefined for a particular CPU,
105 C macros are used. */
106
107 /* The CPUs come in alphabetical order below.
108
109 Please add support for more CPUs here, or improve the current support
110 for the CPUs below!
111 (E.g. WE32100, IBM360.) */
112
113 #if defined (__GNUC__) && !defined (NO_ASM)
114
115 /* We sometimes need to clobber "cc" with gcc2, but that would not be
116 understood by gcc1. Use cpp to avoid major code duplication. */
117 #if __GNUC__ < 2
118 #define __CLOBBER_CC
119 #define __AND_CLOBBER_CC
120 #else /* __GNUC__ >= 2 */
121 #define __CLOBBER_CC : "cc"
122 #define __AND_CLOBBER_CC , "cc"
123 #endif /* __GNUC__ < 2 */
124
125 #if defined (__alpha) && W_TYPE_SIZE == 64
126 #define umul_ppmm(ph, pl, m0, m1) \
127 do { \
128 UDItype __m0 = (m0), __m1 = (m1); \
129 (ph) = __builtin_alpha_umulh (__m0, __m1); \
130 (pl) = __m0 * __m1; \
131 } while (0)
132 #define UMUL_TIME 46
133 #ifndef LONGLONG_STANDALONE
134 #define udiv_qrnnd(q, r, n1, n0, d) \
135 do { UDItype __r; \
136 (q) = __udiv_qrnnd (&__r, (n1), (n0), (d)); \
137 (r) = __r; \
138 } while (0)
139 extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
140 #define UDIV_TIME 220
141 #endif /* LONGLONG_STANDALONE */
142 #ifdef __alpha_cix__
143 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzl (X))
144 #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X))
145 #define COUNT_LEADING_ZEROS_0 64
146 #else
147 #define count_leading_zeros(COUNT,X) \
148 do { \
149 UDItype __xr = (X), __t, __a; \
150 __t = __builtin_alpha_cmpbge (0, __xr); \
151 __a = __clz_tab[__t ^ 0xff] - 1; \
152 __t = __builtin_alpha_extbl (__xr, __a); \
153 (COUNT) = 64 - (__clz_tab[__t] + __a*8); \
154 } while (0)
155 #define count_trailing_zeros(COUNT,X) \
156 do { \
157 UDItype __xr = (X), __t, __a; \
158 __t = __builtin_alpha_cmpbge (0, __xr); \
159 __t = ~__t & -~__t; \
160 __a = ((__t & 0xCC) != 0) * 2; \
161 __a += ((__t & 0xF0) != 0) * 4; \
162 __a += ((__t & 0xAA) != 0); \
163 __t = __builtin_alpha_extbl (__xr, __a); \
164 __a <<= 3; \
165 __t &= -__t; \
166 __a += ((__t & 0xCC) != 0) * 2; \
167 __a += ((__t & 0xF0) != 0) * 4; \
168 __a += ((__t & 0xAA) != 0); \
169 (COUNT) = __a; \
170 } while (0)
171 #endif /* __alpha_cix__ */
172 #endif /* __alpha */
173
174 #if defined (__arc__) && W_TYPE_SIZE == 32
175 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
176 __asm__ ("add.f %1, %4, %5\n\tadc %0, %2, %3" \
177 : "=r" ((USItype) (sh)), \
178 "=&r" ((USItype) (sl)) \
179 : "%r" ((USItype) (ah)), \
180 "rIJ" ((USItype) (bh)), \
181 "%r" ((USItype) (al)), \
182 "rIJ" ((USItype) (bl)))
183 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
184 __asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
185 : "=r" ((USItype) (sh)), \
186 "=&r" ((USItype) (sl)) \
187 : "r" ((USItype) (ah)), \
188 "rIJ" ((USItype) (bh)), \
189 "r" ((USItype) (al)), \
190 "rIJ" ((USItype) (bl)))
191
192 #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
193 #ifdef __ARC_NORM__
194 #define count_leading_zeros(count, x) \
195 do \
196 { \
197 SItype c_; \
198 \
199 __asm__ ("norm.f\t%0,%1\n\tmov.mi\t%0,-1" : "=r" (c_) : "r" (x) : "cc");\
200 (count) = c_ + 1; \
201 } \
202 while (0)
203 #define COUNT_LEADING_ZEROS_0 32
204 #endif
205 #endif
206
207 #if defined (__arm__) && (defined (__thumb2__) || !defined (__thumb__)) \
208 && W_TYPE_SIZE == 32
209 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
210 __asm__ ("adds %1, %4, %5\n\tadc %0, %2, %3" \
211 : "=r" ((USItype) (sh)), \
212 "=&r" ((USItype) (sl)) \
213 : "%r" ((USItype) (ah)), \
214 "rI" ((USItype) (bh)), \
215 "%r" ((USItype) (al)), \
216 "rI" ((USItype) (bl)) __CLOBBER_CC)
217 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
218 __asm__ ("subs %1, %4, %5\n\tsbc %0, %2, %3" \
219 : "=r" ((USItype) (sh)), \
220 "=&r" ((USItype) (sl)) \
221 : "r" ((USItype) (ah)), \
222 "rI" ((USItype) (bh)), \
223 "r" ((USItype) (al)), \
224 "rI" ((USItype) (bl)) __CLOBBER_CC)
225 # if defined(__ARM_ARCH_2__) || defined(__ARM_ARCH_2A__) \
226 || defined(__ARM_ARCH_3__)
227 # define umul_ppmm(xh, xl, a, b) \
228 do { \
229 register USItype __t0, __t1, __t2; \
230 __asm__ ("%@ Inlined umul_ppmm\n" \
231 " mov %2, %5, lsr #16\n" \
232 " mov %0, %6, lsr #16\n" \
233 " bic %3, %5, %2, lsl #16\n" \
234 " bic %4, %6, %0, lsl #16\n" \
235 " mul %1, %3, %4\n" \
236 " mul %4, %2, %4\n" \
237 " mul %3, %0, %3\n" \
238 " mul %0, %2, %0\n" \
239 " adds %3, %4, %3\n" \
240 " addcs %0, %0, #65536\n" \
241 " adds %1, %1, %3, lsl #16\n" \
242 " adc %0, %0, %3, lsr #16" \
243 : "=&r" ((USItype) (xh)), \
244 "=r" ((USItype) (xl)), \
245 "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
246 : "r" ((USItype) (a)), \
247 "r" ((USItype) (b)) __CLOBBER_CC ); \
248 } while (0)
249 # define UMUL_TIME 20
250 # else
251 # define umul_ppmm(xh, xl, a, b) \
252 do { \
253 /* Generate umull, under compiler control. */ \
254 register UDItype __t0 = (UDItype)(USItype)(a) * (USItype)(b); \
255 (xl) = (USItype)__t0; \
256 (xh) = (USItype)(__t0 >> 32); \
257 } while (0)
258 # define UMUL_TIME 3
259 # endif
260 # define UDIV_TIME 100
261 #endif /* __arm__ */
262
263 #if defined(__arm__)
264 /* Let gcc decide how best to implement count_leading_zeros. */
265 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
266 #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctz (X))
267 #define COUNT_LEADING_ZEROS_0 32
268 #endif
269
270 #if defined (__AVR__)
271
272 #if W_TYPE_SIZE == 16
273 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
274 #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctz (X))
275 #define COUNT_LEADING_ZEROS_0 16
276 #endif /* W_TYPE_SIZE == 16 */
277
278 #if W_TYPE_SIZE == 32
279 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzl (X))
280 #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzl (X))
281 #define COUNT_LEADING_ZEROS_0 32
282 #endif /* W_TYPE_SIZE == 32 */
283
284 #if W_TYPE_SIZE == 64
285 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clzll (X))
286 #define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctzll (X))
287 #define COUNT_LEADING_ZEROS_0 64
288 #endif /* W_TYPE_SIZE == 64 */
289
290 #endif /* defined (__AVR__) */
291
292 #if defined (__CRIS__) && __CRIS_arch_version >= 3
293 #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
294 #if __CRIS_arch_version >= 8
295 #define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
296 #endif
297 #endif /* __CRIS__ */
298
299 #if defined (__hppa) && W_TYPE_SIZE == 32
300 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
301 __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
302 : "=r" ((USItype) (sh)), \
303 "=&r" ((USItype) (sl)) \
304 : "%rM" ((USItype) (ah)), \
305 "rM" ((USItype) (bh)), \
306 "%rM" ((USItype) (al)), \
307 "rM" ((USItype) (bl)))
308 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
309 __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0" \
310 : "=r" ((USItype) (sh)), \
311 "=&r" ((USItype) (sl)) \
312 : "rM" ((USItype) (ah)), \
313 "rM" ((USItype) (bh)), \
314 "rM" ((USItype) (al)), \
315 "rM" ((USItype) (bl)))
316 #if defined (_PA_RISC1_1)
317 #define umul_ppmm(w1, w0, u, v) \
318 do { \
319 union \
320 { \
321 UDItype __f; \
322 struct {USItype __w1, __w0;} __w1w0; \
323 } __t; \
324 __asm__ ("xmpyu %1,%2,%0" \
325 : "=x" (__t.__f) \
326 : "x" ((USItype) (u)), \
327 "x" ((USItype) (v))); \
328 (w1) = __t.__w1w0.__w1; \
329 (w0) = __t.__w1w0.__w0; \
330 } while (0)
331 #define UMUL_TIME 8
332 #else
333 #define UMUL_TIME 30
334 #endif
335 #define UDIV_TIME 40
336 #define count_leading_zeros(count, x) \
337 do { \
338 USItype __tmp; \
339 __asm__ ( \
340 "ldi 1,%0\n" \
341 " extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
342 " extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n"\
343 " ldo 16(%0),%0 ; Yes. Perform add.\n" \
344 " extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
345 " extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n"\
346 " ldo 8(%0),%0 ; Yes. Perform add.\n" \
347 " extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
348 " extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n"\
349 " ldo 4(%0),%0 ; Yes. Perform add.\n" \
350 " extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
351 " extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n"\
352 " ldo 2(%0),%0 ; Yes. Perform add.\n" \
353 " extru %1,30,1,%1 ; Extract bit 1.\n" \
354 " sub %0,%1,%0 ; Subtract it.\n" \
355 : "=r" (count), "=r" (__tmp) : "1" (x)); \
356 } while (0)
357 #endif
358
359 #if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
360 #if !defined (__zarch__)
361 #define smul_ppmm(xh, xl, m0, m1) \
362 do { \
363 union {DItype __ll; \
364 struct {USItype __h, __l;} __i; \
365 } __x; \
366 __asm__ ("lr %N0,%1\n\tmr %0,%2" \
367 : "=&r" (__x.__ll) \
368 : "r" (m0), "r" (m1)); \
369 (xh) = __x.__i.__h; (xl) = __x.__i.__l; \
370 } while (0)
371 #define sdiv_qrnnd(q, r, n1, n0, d) \
372 do { \
373 union {DItype __ll; \
374 struct {USItype __h, __l;} __i; \
375 } __x; \
376 __x.__i.__h = n1; __x.__i.__l = n0; \
377 __asm__ ("dr %0,%2" \
378 : "=r" (__x.__ll) \
379 : "0" (__x.__ll), "r" (d)); \
380 (q) = __x.__i.__l; (r) = __x.__i.__h; \
381 } while (0)
382 #else
383 #define smul_ppmm(xh, xl, m0, m1) \
384 do { \
385 register SItype __r0 __asm__ ("0"); \
386 register SItype __r1 __asm__ ("1") = (m0); \
387 \
388 __asm__ ("mr\t%%r0,%3" \
389 : "=r" (__r0), "=r" (__r1) \
390 : "r" (__r1), "r" (m1)); \
391 (xh) = __r0; (xl) = __r1; \
392 } while (0)
393
394 #define sdiv_qrnnd(q, r, n1, n0, d) \
395 do { \
396 register SItype __r0 __asm__ ("0") = (n1); \
397 register SItype __r1 __asm__ ("1") = (n0); \
398 \
399 __asm__ ("dr\t%%r0,%4" \
400 : "=r" (__r0), "=r" (__r1) \
401 : "r" (__r0), "r" (__r1), "r" (d)); \
402 (q) = __r1; (r) = __r0; \
403 } while (0)
404 #endif /* __zarch__ */
405 #endif
406
407 #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
408 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
409 __asm__ ("add{l} {%5,%1|%1,%5}\n\tadc{l} {%3,%0|%0,%3}" \
410 : "=r" ((USItype) (sh)), \
411 "=&r" ((USItype) (sl)) \
412 : "%0" ((USItype) (ah)), \
413 "g" ((USItype) (bh)), \
414 "%1" ((USItype) (al)), \
415 "g" ((USItype) (bl)))
416 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
417 __asm__ ("sub{l} {%5,%1|%1,%5}\n\tsbb{l} {%3,%0|%0,%3}" \
418 : "=r" ((USItype) (sh)), \
419 "=&r" ((USItype) (sl)) \
420 : "0" ((USItype) (ah)), \
421 "g" ((USItype) (bh)), \
422 "1" ((USItype) (al)), \
423 "g" ((USItype) (bl)))
424 #define umul_ppmm(w1, w0, u, v) \
425 __asm__ ("mul{l} %3" \
426 : "=a" ((USItype) (w0)), \
427 "=d" ((USItype) (w1)) \
428 : "%0" ((USItype) (u)), \
429 "rm" ((USItype) (v)))
430 #define udiv_qrnnd(q, r, n1, n0, dv) \
431 __asm__ ("div{l} %4" \
432 : "=a" ((USItype) (q)), \
433 "=d" ((USItype) (r)) \
434 : "0" ((USItype) (n0)), \
435 "1" ((USItype) (n1)), \
436 "rm" ((USItype) (dv)))
437 #define count_leading_zeros(count, x) ((count) = __builtin_clz (x))
438 #define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x))
439 #define UMUL_TIME 40
440 #define UDIV_TIME 40
441 #endif /* 80x86 */
442
443 #if (defined (__x86_64__) || defined (__i386__)) && W_TYPE_SIZE == 64
444 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
445 __asm__ ("add{q} {%5,%1|%1,%5}\n\tadc{q} {%3,%0|%0,%3}" \
446 : "=r" ((UDItype) (sh)), \
447 "=&r" ((UDItype) (sl)) \
448 : "%0" ((UDItype) (ah)), \
449 "rme" ((UDItype) (bh)), \
450 "%1" ((UDItype) (al)), \
451 "rme" ((UDItype) (bl)))
452 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
453 __asm__ ("sub{q} {%5,%1|%1,%5}\n\tsbb{q} {%3,%0|%0,%3}" \
454 : "=r" ((UDItype) (sh)), \
455 "=&r" ((UDItype) (sl)) \
456 : "0" ((UDItype) (ah)), \
457 "rme" ((UDItype) (bh)), \
458 "1" ((UDItype) (al)), \
459 "rme" ((UDItype) (bl)))
460 #define umul_ppmm(w1, w0, u, v) \
461 __asm__ ("mul{q} %3" \
462 : "=a" ((UDItype) (w0)), \
463 "=d" ((UDItype) (w1)) \
464 : "%0" ((UDItype) (u)), \
465 "rm" ((UDItype) (v)))
466 #define udiv_qrnnd(q, r, n1, n0, dv) \
467 __asm__ ("div{q} %4" \
468 : "=a" ((UDItype) (q)), \
469 "=d" ((UDItype) (r)) \
470 : "0" ((UDItype) (n0)), \
471 "1" ((UDItype) (n1)), \
472 "rm" ((UDItype) (dv)))
473 #define count_leading_zeros(count, x) ((count) = __builtin_clzll (x))
474 #define count_trailing_zeros(count, x) ((count) = __builtin_ctzll (x))
475 #define UMUL_TIME 40
476 #define UDIV_TIME 40
477 #endif /* x86_64 */
478
479 #if defined (__i960__) && W_TYPE_SIZE == 32
480 #define umul_ppmm(w1, w0, u, v) \
481 ({union {UDItype __ll; \
482 struct {USItype __l, __h;} __i; \
483 } __xx; \
484 __asm__ ("emul %2,%1,%0" \
485 : "=d" (__xx.__ll) \
486 : "%dI" ((USItype) (u)), \
487 "dI" ((USItype) (v))); \
488 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
489 #define __umulsidi3(u, v) \
490 ({UDItype __w; \
491 __asm__ ("emul %2,%1,%0" \
492 : "=d" (__w) \
493 : "%dI" ((USItype) (u)), \
494 "dI" ((USItype) (v))); \
495 __w; })
496 #endif /* __i960__ */
497
498 #if defined (__ia64) && W_TYPE_SIZE == 64
499 /* This form encourages gcc (pre-release 3.4 at least) to emit predicated
500 "sub r=r,r" and "sub r=r,r,1", giving a 2 cycle latency. The generic
501 code using "al<bl" arithmetically comes out making an actual 0 or 1 in a
502 register, which takes an extra cycle. */
503 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
504 do { \
505 UWtype __x; \
506 __x = (al) - (bl); \
507 if ((al) < (bl)) \
508 (sh) = (ah) - (bh) - 1; \
509 else \
510 (sh) = (ah) - (bh); \
511 (sl) = __x; \
512 } while (0)
513
514 /* Do both product parts in assembly, since that gives better code with
515 all gcc versions. Some callers will just use the upper part, and in
516 that situation we waste an instruction, but not any cycles. */
517 #define umul_ppmm(ph, pl, m0, m1) \
518 __asm__ ("xma.hu %0 = %2, %3, f0\n\txma.l %1 = %2, %3, f0" \
519 : "=&f" (ph), "=f" (pl) \
520 : "f" (m0), "f" (m1))
521 #define count_leading_zeros(count, x) \
522 do { \
523 UWtype _x = (x), _y, _a, _c; \
524 __asm__ ("mux1 %0 = %1, @rev" : "=r" (_y) : "r" (_x)); \
525 __asm__ ("czx1.l %0 = %1" : "=r" (_a) : "r" (-_y | _y)); \
526 _c = (_a - 1) << 3; \
527 _x >>= _c; \
528 if (_x >= 1 << 4) \
529 _x >>= 4, _c += 4; \
530 if (_x >= 1 << 2) \
531 _x >>= 2, _c += 2; \
532 _c += _x >> 1; \
533 (count) = W_TYPE_SIZE - 1 - _c; \
534 } while (0)
535 /* similar to what gcc does for __builtin_ffs, but 0 based rather than 1
536 based, and we don't need a special case for x==0 here */
537 #define count_trailing_zeros(count, x) \
538 do { \
539 UWtype __ctz_x = (x); \
540 __asm__ ("popcnt %0 = %1" \
541 : "=r" (count) \
542 : "r" ((__ctz_x-1) & ~__ctz_x)); \
543 } while (0)
544 #define UMUL_TIME 14
545 #endif
546
547 #if defined (__M32R__) && W_TYPE_SIZE == 32
548 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
549 /* The cmp clears the condition bit. */ \
550 __asm__ ("cmp %0,%0\n\taddx %1,%5\n\taddx %0,%3" \
551 : "=r" ((USItype) (sh)), \
552 "=&r" ((USItype) (sl)) \
553 : "0" ((USItype) (ah)), \
554 "r" ((USItype) (bh)), \
555 "1" ((USItype) (al)), \
556 "r" ((USItype) (bl)) \
557 : "cbit")
558 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
559 /* The cmp clears the condition bit. */ \
560 __asm__ ("cmp %0,%0\n\tsubx %1,%5\n\tsubx %0,%3" \
561 : "=r" ((USItype) (sh)), \
562 "=&r" ((USItype) (sl)) \
563 : "0" ((USItype) (ah)), \
564 "r" ((USItype) (bh)), \
565 "1" ((USItype) (al)), \
566 "r" ((USItype) (bl)) \
567 : "cbit")
568 #endif /* __M32R__ */
569
570 #if defined (__mc68000__) && W_TYPE_SIZE == 32
571 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
572 __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0" \
573 : "=d" ((USItype) (sh)), \
574 "=&d" ((USItype) (sl)) \
575 : "%0" ((USItype) (ah)), \
576 "d" ((USItype) (bh)), \
577 "%1" ((USItype) (al)), \
578 "g" ((USItype) (bl)))
579 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
580 __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0" \
581 : "=d" ((USItype) (sh)), \
582 "=&d" ((USItype) (sl)) \
583 : "0" ((USItype) (ah)), \
584 "d" ((USItype) (bh)), \
585 "1" ((USItype) (al)), \
586 "g" ((USItype) (bl)))
587
588 /* The '020, '030, '040, '060 and CPU32 have 32x32->64 and 64/32->32q-32r. */
589 #if (defined (__mc68020__) && !defined (__mc68060__))
590 #define umul_ppmm(w1, w0, u, v) \
591 __asm__ ("mulu%.l %3,%1:%0" \
592 : "=d" ((USItype) (w0)), \
593 "=d" ((USItype) (w1)) \
594 : "%0" ((USItype) (u)), \
595 "dmi" ((USItype) (v)))
596 #define UMUL_TIME 45
597 #define udiv_qrnnd(q, r, n1, n0, d) \
598 __asm__ ("divu%.l %4,%1:%0" \
599 : "=d" ((USItype) (q)), \
600 "=d" ((USItype) (r)) \
601 : "0" ((USItype) (n0)), \
602 "1" ((USItype) (n1)), \
603 "dmi" ((USItype) (d)))
604 #define UDIV_TIME 90
605 #define sdiv_qrnnd(q, r, n1, n0, d) \
606 __asm__ ("divs%.l %4,%1:%0" \
607 : "=d" ((USItype) (q)), \
608 "=d" ((USItype) (r)) \
609 : "0" ((USItype) (n0)), \
610 "1" ((USItype) (n1)), \
611 "dmi" ((USItype) (d)))
612
613 #elif defined (__mcoldfire__) /* not mc68020 */
614
615 #define umul_ppmm(xh, xl, a, b) \
616 __asm__ ("| Inlined umul_ppmm\n" \
617 " move%.l %2,%/d0\n" \
618 " move%.l %3,%/d1\n" \
619 " move%.l %/d0,%/d2\n" \
620 " swap %/d0\n" \
621 " move%.l %/d1,%/d3\n" \
622 " swap %/d1\n" \
623 " move%.w %/d2,%/d4\n" \
624 " mulu %/d3,%/d4\n" \
625 " mulu %/d1,%/d2\n" \
626 " mulu %/d0,%/d3\n" \
627 " mulu %/d0,%/d1\n" \
628 " move%.l %/d4,%/d0\n" \
629 " clr%.w %/d0\n" \
630 " swap %/d0\n" \
631 " add%.l %/d0,%/d2\n" \
632 " add%.l %/d3,%/d2\n" \
633 " jcc 1f\n" \
634 " add%.l %#65536,%/d1\n" \
635 "1: swap %/d2\n" \
636 " moveq %#0,%/d0\n" \
637 " move%.w %/d2,%/d0\n" \
638 " move%.w %/d4,%/d2\n" \
639 " move%.l %/d2,%1\n" \
640 " add%.l %/d1,%/d0\n" \
641 " move%.l %/d0,%0" \
642 : "=g" ((USItype) (xh)), \
643 "=g" ((USItype) (xl)) \
644 : "g" ((USItype) (a)), \
645 "g" ((USItype) (b)) \
646 : "d0", "d1", "d2", "d3", "d4")
647 #define UMUL_TIME 100
648 #define UDIV_TIME 400
649 #else /* not ColdFire */
650 /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
651 #define umul_ppmm(xh, xl, a, b) \
652 __asm__ ("| Inlined umul_ppmm\n" \
653 " move%.l %2,%/d0\n" \
654 " move%.l %3,%/d1\n" \
655 " move%.l %/d0,%/d2\n" \
656 " swap %/d0\n" \
657 " move%.l %/d1,%/d3\n" \
658 " swap %/d1\n" \
659 " move%.w %/d2,%/d4\n" \
660 " mulu %/d3,%/d4\n" \
661 " mulu %/d1,%/d2\n" \
662 " mulu %/d0,%/d3\n" \
663 " mulu %/d0,%/d1\n" \
664 " move%.l %/d4,%/d0\n" \
665 " eor%.w %/d0,%/d0\n" \
666 " swap %/d0\n" \
667 " add%.l %/d0,%/d2\n" \
668 " add%.l %/d3,%/d2\n" \
669 " jcc 1f\n" \
670 " add%.l %#65536,%/d1\n" \
671 "1: swap %/d2\n" \
672 " moveq %#0,%/d0\n" \
673 " move%.w %/d2,%/d0\n" \
674 " move%.w %/d4,%/d2\n" \
675 " move%.l %/d2,%1\n" \
676 " add%.l %/d1,%/d0\n" \
677 " move%.l %/d0,%0" \
678 : "=g" ((USItype) (xh)), \
679 "=g" ((USItype) (xl)) \
680 : "g" ((USItype) (a)), \
681 "g" ((USItype) (b)) \
682 : "d0", "d1", "d2", "d3", "d4")
683 #define UMUL_TIME 100
684 #define UDIV_TIME 400
685
686 #endif /* not mc68020 */
687
688 /* The '020, '030, '040 and '060 have bitfield insns.
689 cpu32 disguises as a 68020, but lacks them. */
690 #if defined (__mc68020__) && !defined (__mcpu32__)
691 #define count_leading_zeros(count, x) \
692 __asm__ ("bfffo %1{%b2:%b2},%0" \
693 : "=d" ((USItype) (count)) \
694 : "od" ((USItype) (x)), "n" (0))
695 /* Some ColdFire architectures have a ff1 instruction supported via
696 __builtin_clz. */
697 #elif defined (__mcfisaaplus__) || defined (__mcfisac__)
698 #define count_leading_zeros(count,x) ((count) = __builtin_clz (x))
699 #define COUNT_LEADING_ZEROS_0 32
700 #endif
701 #endif /* mc68000 */
702
703 #if defined (__m88000__) && W_TYPE_SIZE == 32
704 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
705 __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3" \
706 : "=r" ((USItype) (sh)), \
707 "=&r" ((USItype) (sl)) \
708 : "%rJ" ((USItype) (ah)), \
709 "rJ" ((USItype) (bh)), \
710 "%rJ" ((USItype) (al)), \
711 "rJ" ((USItype) (bl)))
712 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
713 __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3" \
714 : "=r" ((USItype) (sh)), \
715 "=&r" ((USItype) (sl)) \
716 : "rJ" ((USItype) (ah)), \
717 "rJ" ((USItype) (bh)), \
718 "rJ" ((USItype) (al)), \
719 "rJ" ((USItype) (bl)))
720 #define count_leading_zeros(count, x) \
721 do { \
722 USItype __cbtmp; \
723 __asm__ ("ff1 %0,%1" \
724 : "=r" (__cbtmp) \
725 : "r" ((USItype) (x))); \
726 (count) = __cbtmp ^ 31; \
727 } while (0)
728 #define COUNT_LEADING_ZEROS_0 63 /* sic */
729 #if defined (__mc88110__)
730 #define umul_ppmm(wh, wl, u, v) \
731 do { \
732 union {UDItype __ll; \
733 struct {USItype __h, __l;} __i; \
734 } __xx; \
735 __asm__ ("mulu.d %0,%1,%2" \
736 : "=r" (__xx.__ll) \
737 : "r" ((USItype) (u)), \
738 "r" ((USItype) (v))); \
739 (wh) = __xx.__i.__h; \
740 (wl) = __xx.__i.__l; \
741 } while (0)
742 #define udiv_qrnnd(q, r, n1, n0, d) \
743 ({union {UDItype __ll; \
744 struct {USItype __h, __l;} __i; \
745 } __xx; \
746 USItype __q; \
747 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
748 __asm__ ("divu.d %0,%1,%2" \
749 : "=r" (__q) \
750 : "r" (__xx.__ll), \
751 "r" ((USItype) (d))); \
752 (r) = (n0) - __q * (d); (q) = __q; })
753 #define UMUL_TIME 5
754 #define UDIV_TIME 25
755 #else
756 #define UMUL_TIME 17
757 #define UDIV_TIME 150
758 #endif /* __mc88110__ */
759 #endif /* __m88000__ */
760
761 #if defined (__mn10300__)
762 # if defined (__AM33__)
763 # define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
764 # define umul_ppmm(w1, w0, u, v) \
765 asm("mulu %3,%2,%1,%0" : "=r"(w0), "=r"(w1) : "r"(u), "r"(v))
766 # define smul_ppmm(w1, w0, u, v) \
767 asm("mul %3,%2,%1,%0" : "=r"(w0), "=r"(w1) : "r"(u), "r"(v))
768 # else
769 # define umul_ppmm(w1, w0, u, v) \
770 asm("nop; nop; mulu %3,%0" : "=d"(w0), "=z"(w1) : "%0"(u), "d"(v))
771 # define smul_ppmm(w1, w0, u, v) \
772 asm("nop; nop; mul %3,%0" : "=d"(w0), "=z"(w1) : "%0"(u), "d"(v))
773 # endif
774 # define add_ssaaaa(sh, sl, ah, al, bh, bl) \
775 do { \
776 DWunion __s, __a, __b; \
777 __a.s.low = (al); __a.s.high = (ah); \
778 __b.s.low = (bl); __b.s.high = (bh); \
779 __s.ll = __a.ll + __b.ll; \
780 (sl) = __s.s.low; (sh) = __s.s.high; \
781 } while (0)
782 # define sub_ddmmss(sh, sl, ah, al, bh, bl) \
783 do { \
784 DWunion __s, __a, __b; \
785 __a.s.low = (al); __a.s.high = (ah); \
786 __b.s.low = (bl); __b.s.high = (bh); \
787 __s.ll = __a.ll - __b.ll; \
788 (sl) = __s.s.low; (sh) = __s.s.high; \
789 } while (0)
790 # define udiv_qrnnd(q, r, nh, nl, d) \
791 asm("divu %2,%0" : "=D"(q), "=z"(r) : "D"(d), "0"(nl), "1"(nh))
792 # define sdiv_qrnnd(q, r, nh, nl, d) \
793 asm("div %2,%0" : "=D"(q), "=z"(r) : "D"(d), "0"(nl), "1"(nh))
794 # define UMUL_TIME 3
795 # define UDIV_TIME 38
796 #endif
797
798 #if defined (__mips__) && W_TYPE_SIZE == 32
799 #define umul_ppmm(w1, w0, u, v) \
800 do { \
801 UDItype __x = (UDItype) (USItype) (u) * (USItype) (v); \
802 (w1) = (USItype) (__x >> 32); \
803 (w0) = (USItype) (__x); \
804 } while (0)
805 #define UMUL_TIME 10
806 #define UDIV_TIME 100
807
808 #if (__mips == 32 || __mips == 64) && ! __mips16
809 #define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
810 #define COUNT_LEADING_ZEROS_0 32
811 #endif
812 #endif /* __mips__ */
813
814 #if defined (__ns32000__) && W_TYPE_SIZE == 32
815 #define umul_ppmm(w1, w0, u, v) \
816 ({union {UDItype __ll; \
817 struct {USItype __l, __h;} __i; \
818 } __xx; \
819 __asm__ ("meid %2,%0" \
820 : "=g" (__xx.__ll) \
821 : "%0" ((USItype) (u)), \
822 "g" ((USItype) (v))); \
823 (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
824 #define __umulsidi3(u, v) \
825 ({UDItype __w; \
826 __asm__ ("meid %2,%0" \
827 : "=g" (__w) \
828 : "%0" ((USItype) (u)), \
829 "g" ((USItype) (v))); \
830 __w; })
831 #define udiv_qrnnd(q, r, n1, n0, d) \
832 ({union {UDItype __ll; \
833 struct {USItype __l, __h;} __i; \
834 } __xx; \
835 __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
836 __asm__ ("deid %2,%0" \
837 : "=g" (__xx.__ll) \
838 : "0" (__xx.__ll), \
839 "g" ((USItype) (d))); \
840 (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
841 #define count_trailing_zeros(count,x) \
842 do { \
843 __asm__ ("ffsd %2,%0" \
844 : "=r" ((USItype) (count)) \
845 : "0" ((USItype) 0), \
846 "r" ((USItype) (x))); \
847 } while (0)
848 #endif /* __ns32000__ */
849
850 /* FIXME: We should test _IBMR2 here when we add assembly support for the
851 system vendor compilers.
852 FIXME: What's needed for gcc PowerPC VxWorks? __vxworks__ is not good
853 enough, since that hits ARM and m68k too. */
854 #if (defined (_ARCH_PPC) /* AIX */ \
855 || defined (__powerpc__) /* gcc */ \
856 || defined (__POWERPC__) /* BEOS */ \
857 || defined (__ppc__) /* Darwin */ \
858 || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
859 || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
860 && CPU_FAMILY == PPC) \
861 ) && W_TYPE_SIZE == 32
862 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
863 do { \
864 if (__builtin_constant_p (bh) && (bh) == 0) \
865 __asm__ ("add%I4c %1,%3,%4\n\taddze %0,%2" \
866 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
867 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
868 __asm__ ("add%I4c %1,%3,%4\n\taddme %0,%2" \
869 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
870 else \
871 __asm__ ("add%I5c %1,%4,%5\n\tadde %0,%2,%3" \
872 : "=r" (sh), "=&r" (sl) \
873 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
874 } while (0)
875 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
876 do { \
877 if (__builtin_constant_p (ah) && (ah) == 0) \
878 __asm__ ("subf%I3c %1,%4,%3\n\tsubfze %0,%2" \
879 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
880 else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0) \
881 __asm__ ("subf%I3c %1,%4,%3\n\tsubfme %0,%2" \
882 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
883 else if (__builtin_constant_p (bh) && (bh) == 0) \
884 __asm__ ("subf%I3c %1,%4,%3\n\taddme %0,%2" \
885 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
886 else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0) \
887 __asm__ ("subf%I3c %1,%4,%3\n\taddze %0,%2" \
888 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
889 else \
890 __asm__ ("subf%I4c %1,%5,%4\n\tsubfe %0,%3,%2" \
891 : "=r" (sh), "=&r" (sl) \
892 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
893 } while (0)
894 #define count_leading_zeros(count, x) \
895 __asm__ ("cntlzw %0,%1" : "=r" (count) : "r" (x))
896 #define COUNT_LEADING_ZEROS_0 32
897 #if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
898 || defined (__ppc__) \
899 || (defined (PPC) && ! defined (CPU_FAMILY)) /* gcc 2.7.x GNU&SysV */ \
900 || (defined (PPC) && defined (CPU_FAMILY) /* VxWorks */ \
901 && CPU_FAMILY == PPC)
902 #define umul_ppmm(ph, pl, m0, m1) \
903 do { \
904 USItype __m0 = (m0), __m1 = (m1); \
905 __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
906 (pl) = __m0 * __m1; \
907 } while (0)
908 #define UMUL_TIME 15
909 #define smul_ppmm(ph, pl, m0, m1) \
910 do { \
911 SItype __m0 = (m0), __m1 = (m1); \
912 __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
913 (pl) = __m0 * __m1; \
914 } while (0)
915 #define SMUL_TIME 14
916 #define UDIV_TIME 120
917 #endif
918 #endif /* 32-bit POWER architecture variants. */
919
920 /* We should test _IBMR2 here when we add assembly support for the system
921 vendor compilers. */
922 #if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
923 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
924 do { \
925 if (__builtin_constant_p (bh) && (bh) == 0) \
926 __asm__ ("add%I4c %1,%3,%4\n\taddze %0,%2" \
927 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
928 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
929 __asm__ ("add%I4c %1,%3,%4\n\taddme %0,%2" \
930 : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
931 else \
932 __asm__ ("add%I5c %1,%4,%5\n\tadde %0,%2,%3" \
933 : "=r" (sh), "=&r" (sl) \
934 : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl)); \
935 } while (0)
936 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
937 do { \
938 if (__builtin_constant_p (ah) && (ah) == 0) \
939 __asm__ ("subf%I3c %1,%4,%3\n\tsubfze %0,%2" \
940 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
941 else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0) \
942 __asm__ ("subf%I3c %1,%4,%3\n\tsubfme %0,%2" \
943 : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
944 else if (__builtin_constant_p (bh) && (bh) == 0) \
945 __asm__ ("subf%I3c %1,%4,%3\n\taddme %0,%2" \
946 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
947 else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0) \
948 __asm__ ("subf%I3c %1,%4,%3\n\taddze %0,%2" \
949 : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
950 else \
951 __asm__ ("subf%I4c %1,%5,%4\n\tsubfe %0,%3,%2" \
952 : "=r" (sh), "=&r" (sl) \
953 : "r" (ah), "r" (bh), "rI" (al), "r" (bl)); \
954 } while (0)
955 #define count_leading_zeros(count, x) \
956 __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
957 #define COUNT_LEADING_ZEROS_0 64
958 #define umul_ppmm(ph, pl, m0, m1) \
959 do { \
960 UDItype __m0 = (m0), __m1 = (m1); \
961 __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
962 (pl) = __m0 * __m1; \
963 } while (0)
964 #define UMUL_TIME 15
965 #define smul_ppmm(ph, pl, m0, m1) \
966 do { \
967 DItype __m0 = (m0), __m1 = (m1); \
968 __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1)); \
969 (pl) = __m0 * __m1; \
970 } while (0)
971 #define SMUL_TIME 14 /* ??? */
972 #define UDIV_TIME 120 /* ??? */
973 #endif /* 64-bit PowerPC. */
974
975 #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
976 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
977 __asm__ ("a %1,%5\n\tae %0,%3" \
978 : "=r" ((USItype) (sh)), \
979 "=&r" ((USItype) (sl)) \
980 : "%0" ((USItype) (ah)), \
981 "r" ((USItype) (bh)), \
982 "%1" ((USItype) (al)), \
983 "r" ((USItype) (bl)))
984 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
985 __asm__ ("s %1,%5\n\tse %0,%3" \
986 : "=r" ((USItype) (sh)), \
987 "=&r" ((USItype) (sl)) \
988 : "0" ((USItype) (ah)), \
989 "r" ((USItype) (bh)), \
990 "1" ((USItype) (al)), \
991 "r" ((USItype) (bl)))
992 #define umul_ppmm(ph, pl, m0, m1) \
993 do { \
994 USItype __m0 = (m0), __m1 = (m1); \
995 __asm__ ( \
996 "s r2,r2\n" \
997 " mts r10,%2\n" \
998 " m r2,%3\n" \
999 " m r2,%3\n" \
1000 " m r2,%3\n" \
1001 " m r2,%3\n" \
1002 " m r2,%3\n" \
1003 " m r2,%3\n" \
1004 " m r2,%3\n" \
1005 " m r2,%3\n" \
1006 " m r2,%3\n" \
1007 " m r2,%3\n" \
1008 " m r2,%3\n" \
1009 " m r2,%3\n" \
1010 " m r2,%3\n" \
1011 " m r2,%3\n" \
1012 " m r2,%3\n" \
1013 " m r2,%3\n" \
1014 " cas %0,r2,r0\n" \
1015 " mfs r10,%1" \
1016 : "=r" ((USItype) (ph)), \
1017 "=r" ((USItype) (pl)) \
1018 : "%r" (__m0), \
1019 "r" (__m1) \
1020 : "r2"); \
1021 (ph) += ((((SItype) __m0 >> 31) & __m1) \
1022 + (((SItype) __m1 >> 31) & __m0)); \
1023 } while (0)
1024 #define UMUL_TIME 20
1025 #define UDIV_TIME 200
1026 #define count_leading_zeros(count, x) \
1027 do { \
1028 if ((x) >= 0x10000) \
1029 __asm__ ("clz %0,%1" \
1030 : "=r" ((USItype) (count)) \
1031 : "r" ((USItype) (x) >> 16)); \
1032 else \
1033 { \
1034 __asm__ ("clz %0,%1" \
1035 : "=r" ((USItype) (count)) \
1036 : "r" ((USItype) (x))); \
1037 (count) += 16; \
1038 } \
1039 } while (0)
1040 #endif
1041
1042 #if defined(__sh__) && !__SHMEDIA__ && W_TYPE_SIZE == 32
1043 #ifndef __sh1__
1044 #define umul_ppmm(w1, w0, u, v) \
1045 __asm__ ( \
1046 "dmulu.l %2,%3\n\tsts%M1 macl,%1\n\tsts%M0 mach,%0" \
1047 : "=r<" ((USItype)(w1)), \
1048 "=r<" ((USItype)(w0)) \
1049 : "r" ((USItype)(u)), \
1050 "r" ((USItype)(v)) \
1051 : "macl", "mach")
1052 #define UMUL_TIME 5
1053 #endif
1054
1055 /* This is the same algorithm as __udiv_qrnnd_c. */
1056 #define UDIV_NEEDS_NORMALIZATION 1
1057
1058 #define udiv_qrnnd(q, r, n1, n0, d) \
1059 do { \
1060 extern UWtype __udiv_qrnnd_16 (UWtype, UWtype) \
1061 __attribute__ ((visibility ("hidden"))); \
1062 /* r0: rn r1: qn */ /* r0: n1 r4: n0 r5: d r6: d1 */ /* r2: __m */ \
1063 __asm__ ( \
1064 "mov%M4 %4,r5\n" \
1065 " swap.w %3,r4\n" \
1066 " swap.w r5,r6\n" \
1067 " jsr @%5\n" \
1068 " shll16 r6\n" \
1069 " swap.w r4,r4\n" \
1070 " jsr @%5\n" \
1071 " swap.w r1,%0\n" \
1072 " or r1,%0" \
1073 : "=r" (q), "=&z" (r) \
1074 : "1" (n1), "r" (n0), "rm" (d), "r" (&__udiv_qrnnd_16) \
1075 : "r1", "r2", "r4", "r5", "r6", "pr", "t"); \
1076 } while (0)
1077
1078 #define UDIV_TIME 80
1079
1080 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1081 __asm__ ("clrt;subc %5,%1; subc %4,%0" \
1082 : "=r" (sh), "=r" (sl) \
1083 : "0" (ah), "1" (al), "r" (bh), "r" (bl) : "t")
1084
1085 #endif /* __sh__ */
1086
1087 #if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
1088 #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
1089 #define count_leading_zeros(count, x) \
1090 do \
1091 { \
1092 UDItype x_ = (USItype)(x); \
1093 SItype c_; \
1094 \
1095 __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_)); \
1096 (count) = c_ - 31; \
1097 } \
1098 while (0)
1099 #define COUNT_LEADING_ZEROS_0 32
1100 #endif
1101
1102 #if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
1103 && W_TYPE_SIZE == 32
1104 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1105 __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0" \
1106 : "=r" ((USItype) (sh)), \
1107 "=&r" ((USItype) (sl)) \
1108 : "%rJ" ((USItype) (ah)), \
1109 "rI" ((USItype) (bh)), \
1110 "%rJ" ((USItype) (al)), \
1111 "rI" ((USItype) (bl)) \
1112 __CLOBBER_CC)
1113 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1114 __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0" \
1115 : "=r" ((USItype) (sh)), \
1116 "=&r" ((USItype) (sl)) \
1117 : "rJ" ((USItype) (ah)), \
1118 "rI" ((USItype) (bh)), \
1119 "rJ" ((USItype) (al)), \
1120 "rI" ((USItype) (bl)) \
1121 __CLOBBER_CC)
1122 #if defined (__sparc_v9__)
1123 #define umul_ppmm(w1, w0, u, v) \
1124 do { \
1125 register USItype __g1 asm ("g1"); \
1126 __asm__ ("umul\t%2,%3,%1\n\t" \
1127 "srlx\t%1, 32, %0" \
1128 : "=r" ((USItype) (w1)), \
1129 "=r" (__g1) \
1130 : "r" ((USItype) (u)), \
1131 "r" ((USItype) (v))); \
1132 (w0) = __g1; \
1133 } while (0)
1134 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
1135 __asm__ ("mov\t%2,%%y\n\t" \
1136 "udiv\t%3,%4,%0\n\t" \
1137 "umul\t%0,%4,%1\n\t" \
1138 "sub\t%3,%1,%1" \
1139 : "=&r" ((USItype) (__q)), \
1140 "=&r" ((USItype) (__r)) \
1141 : "r" ((USItype) (__n1)), \
1142 "r" ((USItype) (__n0)), \
1143 "r" ((USItype) (__d)))
1144 #else
1145 #if defined (__sparc_v8__)
1146 #define umul_ppmm(w1, w0, u, v) \
1147 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
1148 : "=r" ((USItype) (w1)), \
1149 "=r" ((USItype) (w0)) \
1150 : "r" ((USItype) (u)), \
1151 "r" ((USItype) (v)))
1152 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
1153 __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
1154 : "=&r" ((USItype) (__q)), \
1155 "=&r" ((USItype) (__r)) \
1156 : "r" ((USItype) (__n1)), \
1157 "r" ((USItype) (__n0)), \
1158 "r" ((USItype) (__d)))
1159 #else
1160 #if defined (__sparclite__)
1161 /* This has hardware multiply but not divide. It also has two additional
1162 instructions scan (ffs from high bit) and divscc. */
1163 #define umul_ppmm(w1, w0, u, v) \
1164 __asm__ ("umul %2,%3,%1;rd %%y,%0" \
1165 : "=r" ((USItype) (w1)), \
1166 "=r" ((USItype) (w0)) \
1167 : "r" ((USItype) (u)), \
1168 "r" ((USItype) (v)))
1169 #define udiv_qrnnd(q, r, n1, n0, d) \
1170 __asm__ ("! Inlined udiv_qrnnd\n" \
1171 " wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
1172 " tst %%g0\n" \
1173 " divscc %3,%4,%%g1\n" \
1174 " divscc %%g1,%4,%%g1\n" \
1175 " divscc %%g1,%4,%%g1\n" \
1176 " divscc %%g1,%4,%%g1\n" \
1177 " divscc %%g1,%4,%%g1\n" \
1178 " divscc %%g1,%4,%%g1\n" \
1179 " divscc %%g1,%4,%%g1\n" \
1180 " divscc %%g1,%4,%%g1\n" \
1181 " divscc %%g1,%4,%%g1\n" \
1182 " divscc %%g1,%4,%%g1\n" \
1183 " divscc %%g1,%4,%%g1\n" \
1184 " divscc %%g1,%4,%%g1\n" \
1185 " divscc %%g1,%4,%%g1\n" \
1186 " divscc %%g1,%4,%%g1\n" \
1187 " divscc %%g1,%4,%%g1\n" \
1188 " divscc %%g1,%4,%%g1\n" \
1189 " divscc %%g1,%4,%%g1\n" \
1190 " divscc %%g1,%4,%%g1\n" \
1191 " divscc %%g1,%4,%%g1\n" \
1192 " divscc %%g1,%4,%%g1\n" \
1193 " divscc %%g1,%4,%%g1\n" \
1194 " divscc %%g1,%4,%%g1\n" \
1195 " divscc %%g1,%4,%%g1\n" \
1196 " divscc %%g1,%4,%%g1\n" \
1197 " divscc %%g1,%4,%%g1\n" \
1198 " divscc %%g1,%4,%%g1\n" \
1199 " divscc %%g1,%4,%%g1\n" \
1200 " divscc %%g1,%4,%%g1\n" \
1201 " divscc %%g1,%4,%%g1\n" \
1202 " divscc %%g1,%4,%%g1\n" \
1203 " divscc %%g1,%4,%%g1\n" \
1204 " divscc %%g1,%4,%0\n" \
1205 " rd %%y,%1\n" \
1206 " bl,a 1f\n" \
1207 " add %1,%4,%1\n" \
1208 "1: ! End of inline udiv_qrnnd" \
1209 : "=r" ((USItype) (q)), \
1210 "=r" ((USItype) (r)) \
1211 : "r" ((USItype) (n1)), \
1212 "r" ((USItype) (n0)), \
1213 "rI" ((USItype) (d)) \
1214 : "g1" __AND_CLOBBER_CC)
1215 #define UDIV_TIME 37
1216 #define count_leading_zeros(count, x) \
1217 do { \
1218 __asm__ ("scan %1,1,%0" \
1219 : "=r" ((USItype) (count)) \
1220 : "r" ((USItype) (x))); \
1221 } while (0)
1222 /* Early sparclites return 63 for an argument of 0, but they warn that future
1223 implementations might change this. Therefore, leave COUNT_LEADING_ZEROS_0
1224 undefined. */
1225 #else
1226 /* SPARC without integer multiplication and divide instructions.
1227 (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
1228 #define umul_ppmm(w1, w0, u, v) \
1229 __asm__ ("! Inlined umul_ppmm\n" \
1230 " wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n"\
1231 " sra %3,31,%%o5 ! Don't move this insn\n" \
1232 " and %2,%%o5,%%o5 ! Don't move this insn\n" \
1233 " andcc %%g0,0,%%g1 ! Don't move this insn\n" \
1234 " mulscc %%g1,%3,%%g1\n" \
1235 " mulscc %%g1,%3,%%g1\n" \
1236 " mulscc %%g1,%3,%%g1\n" \
1237 " mulscc %%g1,%3,%%g1\n" \
1238 " mulscc %%g1,%3,%%g1\n" \
1239 " mulscc %%g1,%3,%%g1\n" \
1240 " mulscc %%g1,%3,%%g1\n" \
1241 " mulscc %%g1,%3,%%g1\n" \
1242 " mulscc %%g1,%3,%%g1\n" \
1243 " mulscc %%g1,%3,%%g1\n" \
1244 " mulscc %%g1,%3,%%g1\n" \
1245 " mulscc %%g1,%3,%%g1\n" \
1246 " mulscc %%g1,%3,%%g1\n" \
1247 " mulscc %%g1,%3,%%g1\n" \
1248 " mulscc %%g1,%3,%%g1\n" \
1249 " mulscc %%g1,%3,%%g1\n" \
1250 " mulscc %%g1,%3,%%g1\n" \
1251 " mulscc %%g1,%3,%%g1\n" \
1252 " mulscc %%g1,%3,%%g1\n" \
1253 " mulscc %%g1,%3,%%g1\n" \
1254 " mulscc %%g1,%3,%%g1\n" \
1255 " mulscc %%g1,%3,%%g1\n" \
1256 " mulscc %%g1,%3,%%g1\n" \
1257 " mulscc %%g1,%3,%%g1\n" \
1258 " mulscc %%g1,%3,%%g1\n" \
1259 " mulscc %%g1,%3,%%g1\n" \
1260 " mulscc %%g1,%3,%%g1\n" \
1261 " mulscc %%g1,%3,%%g1\n" \
1262 " mulscc %%g1,%3,%%g1\n" \
1263 " mulscc %%g1,%3,%%g1\n" \
1264 " mulscc %%g1,%3,%%g1\n" \
1265 " mulscc %%g1,%3,%%g1\n" \
1266 " mulscc %%g1,0,%%g1\n" \
1267 " add %%g1,%%o5,%0\n" \
1268 " rd %%y,%1" \
1269 : "=r" ((USItype) (w1)), \
1270 "=r" ((USItype) (w0)) \
1271 : "%rI" ((USItype) (u)), \
1272 "r" ((USItype) (v)) \
1273 : "g1", "o5" __AND_CLOBBER_CC)
1274 #define UMUL_TIME 39 /* 39 instructions */
1275 /* It's quite necessary to add this much assembler for the sparc.
1276 The default udiv_qrnnd (in C) is more than 10 times slower! */
1277 #define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
1278 __asm__ ("! Inlined udiv_qrnnd\n" \
1279 " mov 32,%%g1\n" \
1280 " subcc %1,%2,%%g0\n" \
1281 "1: bcs 5f\n" \
1282 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1283 " sub %1,%2,%1 ! this kills msb of n\n" \
1284 " addx %1,%1,%1 ! so this can't give carry\n" \
1285 " subcc %%g1,1,%%g1\n" \
1286 "2: bne 1b\n" \
1287 " subcc %1,%2,%%g0\n" \
1288 " bcs 3f\n" \
1289 " addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1290 " b 3f\n" \
1291 " sub %1,%2,%1 ! this kills msb of n\n" \
1292 "4: sub %1,%2,%1\n" \
1293 "5: addxcc %1,%1,%1\n" \
1294 " bcc 2b\n" \
1295 " subcc %%g1,1,%%g1\n" \
1296 "! Got carry from n. Subtract next step to cancel this carry.\n" \
1297 " bne 4b\n" \
1298 " addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
1299 " sub %1,%2,%1\n" \
1300 "3: xnor %0,0,%0\n" \
1301 " ! End of inline udiv_qrnnd" \
1302 : "=&r" ((USItype) (__q)), \
1303 "=&r" ((USItype) (__r)) \
1304 : "r" ((USItype) (__d)), \
1305 "1" ((USItype) (__n1)), \
1306 "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
1307 #define UDIV_TIME (3+7*32) /* 7 instructions/iteration. 32 iterations. */
1308 #endif /* __sparclite__ */
1309 #endif /* __sparc_v8__ */
1310 #endif /* __sparc_v9__ */
1311 #endif /* sparc32 */
1312
1313 #if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
1314 && W_TYPE_SIZE == 64
1315 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1316 do { \
1317 UDItype __carry = 0; \
1318 __asm__ ("addcc\t%r5,%6,%1\n\t" \
1319 "add\t%r3,%4,%0\n\t" \
1320 "movcs\t%%xcc, 1, %2\n\t" \
1321 "add\t%0, %2, %0" \
1322 : "=r" ((UDItype)(sh)), \
1323 "=&r" ((UDItype)(sl)), \
1324 "+r" (__carry) \
1325 : "%rJ" ((UDItype)(ah)), \
1326 "rI" ((UDItype)(bh)), \
1327 "%rJ" ((UDItype)(al)), \
1328 "rI" ((UDItype)(bl)) \
1329 __CLOBBER_CC); \
1330 } while (0)
1331
1332 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1333 do { \
1334 UDItype __carry = 0; \
1335 __asm__ ("subcc\t%r5,%6,%1\n\t" \
1336 "sub\t%r3,%4,%0\n\t" \
1337 "movcs\t%%xcc, 1, %2\n\t" \
1338 "sub\t%0, %2, %0" \
1339 : "=r" ((UDItype)(sh)), \
1340 "=&r" ((UDItype)(sl)), \
1341 "+r" (__carry) \
1342 : "%rJ" ((UDItype)(ah)), \
1343 "rI" ((UDItype)(bh)), \
1344 "%rJ" ((UDItype)(al)), \
1345 "rI" ((UDItype)(bl)) \
1346 __CLOBBER_CC); \
1347 } while (0)
1348
1349 #define umul_ppmm(wh, wl, u, v) \
1350 do { \
1351 UDItype tmp1, tmp2, tmp3, tmp4; \
1352 __asm__ __volatile__ ( \
1353 "srl %7,0,%3\n\t" \
1354 "mulx %3,%6,%1\n\t" \
1355 "srlx %6,32,%2\n\t" \
1356 "mulx %2,%3,%4\n\t" \
1357 "sllx %4,32,%5\n\t" \
1358 "srl %6,0,%3\n\t" \
1359 "sub %1,%5,%5\n\t" \
1360 "srlx %5,32,%5\n\t" \
1361 "addcc %4,%5,%4\n\t" \
1362 "srlx %7,32,%5\n\t" \
1363 "mulx %3,%5,%3\n\t" \
1364 "mulx %2,%5,%5\n\t" \
1365 "sethi %%hi(0x80000000),%2\n\t" \
1366 "addcc %4,%3,%4\n\t" \
1367 "srlx %4,32,%4\n\t" \
1368 "add %2,%2,%2\n\t" \
1369 "movcc %%xcc,%%g0,%2\n\t" \
1370 "addcc %5,%4,%5\n\t" \
1371 "sllx %3,32,%3\n\t" \
1372 "add %1,%3,%1\n\t" \
1373 "add %5,%2,%0" \
1374 : "=r" ((UDItype)(wh)), \
1375 "=&r" ((UDItype)(wl)), \
1376 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
1377 : "r" ((UDItype)(u)), \
1378 "r" ((UDItype)(v)) \
1379 __CLOBBER_CC); \
1380 } while (0)
1381 #define UMUL_TIME 96
1382 #define UDIV_TIME 230
1383 #endif /* sparc64 */
1384
1385 #if defined (__vax__) && W_TYPE_SIZE == 32
1386 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1387 __asm__ ("addl2 %5,%1\n\tadwc %3,%0" \
1388 : "=g" ((USItype) (sh)), \
1389 "=&g" ((USItype) (sl)) \
1390 : "%0" ((USItype) (ah)), \
1391 "g" ((USItype) (bh)), \
1392 "%1" ((USItype) (al)), \
1393 "g" ((USItype) (bl)))
1394 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1395 __asm__ ("subl2 %5,%1\n\tsbwc %3,%0" \
1396 : "=g" ((USItype) (sh)), \
1397 "=&g" ((USItype) (sl)) \
1398 : "0" ((USItype) (ah)), \
1399 "g" ((USItype) (bh)), \
1400 "1" ((USItype) (al)), \
1401 "g" ((USItype) (bl)))
1402 #define umul_ppmm(xh, xl, m0, m1) \
1403 do { \
1404 union { \
1405 UDItype __ll; \
1406 struct {USItype __l, __h;} __i; \
1407 } __xx; \
1408 USItype __m0 = (m0), __m1 = (m1); \
1409 __asm__ ("emul %1,%2,$0,%0" \
1410 : "=r" (__xx.__ll) \
1411 : "g" (__m0), \
1412 "g" (__m1)); \
1413 (xh) = __xx.__i.__h; \
1414 (xl) = __xx.__i.__l; \
1415 (xh) += ((((SItype) __m0 >> 31) & __m1) \
1416 + (((SItype) __m1 >> 31) & __m0)); \
1417 } while (0)
1418 #define sdiv_qrnnd(q, r, n1, n0, d) \
1419 do { \
1420 union {DItype __ll; \
1421 struct {SItype __l, __h;} __i; \
1422 } __xx; \
1423 __xx.__i.__h = n1; __xx.__i.__l = n0; \
1424 __asm__ ("ediv %3,%2,%0,%1" \
1425 : "=g" (q), "=g" (r) \
1426 : "g" (__xx.__ll), "g" (d)); \
1427 } while (0)
1428 #endif /* __vax__ */
1429
1430 #ifdef _TMS320C6X
1431 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1432 do \
1433 { \
1434 UDItype __ll; \
1435 __asm__ ("addu .l1 %1, %2, %0" \
1436 : "=a" (__ll) : "a" (al), "a" (bl)); \
1437 (sl) = (USItype)__ll; \
1438 (sh) = ((USItype)(__ll >> 32)) + (ah) + (bh); \
1439 } \
1440 while (0)
1441
1442 #ifdef _TMS320C6400_PLUS
1443 #define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
1444 #define umul_ppmm(w1, w0, u, v) \
1445 do { \
1446 UDItype __x = (UDItype) (USItype) (u) * (USItype) (v); \
1447 (w1) = (USItype) (__x >> 32); \
1448 (w0) = (USItype) (__x); \
1449 } while (0)
1450 #endif /* _TMS320C6400_PLUS */
1451
1452 #define count_leading_zeros(count, x) ((count) = __builtin_clz (x))
1453 #ifdef _TMS320C6400
1454 #define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x))
1455 #endif
1456 #define UMUL_TIME 4
1457 #define UDIV_TIME 40
1458 #endif /* _TMS320C6X */
1459
1460 #if defined (__xtensa__) && W_TYPE_SIZE == 32
1461 /* This code is not Xtensa-configuration-specific, so rely on the compiler
1462 to expand builtin functions depending on what configuration features
1463 are available. This avoids library calls when the operation can be
1464 performed in-line. */
1465 #define umul_ppmm(w1, w0, u, v) \
1466 do { \
1467 DWunion __w; \
1468 __w.ll = __builtin_umulsidi3 (u, v); \
1469 w1 = __w.s.high; \
1470 w0 = __w.s.low; \
1471 } while (0)
1472 #define __umulsidi3(u, v) __builtin_umulsidi3 (u, v)
1473 #define count_leading_zeros(COUNT, X) ((COUNT) = __builtin_clz (X))
1474 #define count_trailing_zeros(COUNT, X) ((COUNT) = __builtin_ctz (X))
1475 #endif /* __xtensa__ */
1476
1477 #if defined xstormy16
1478 extern UHItype __stormy16_count_leading_zeros (UHItype);
1479 #define count_leading_zeros(count, x) \
1480 do \
1481 { \
1482 UHItype size; \
1483 \
1484 /* We assume that W_TYPE_SIZE is a multiple of 16... */ \
1485 for ((count) = 0, size = W_TYPE_SIZE; size; size -= 16) \
1486 { \
1487 UHItype c; \
1488 \
1489 c = __clzhi2 ((x) >> (size - 16)); \
1490 (count) += c; \
1491 if (c != 16) \
1492 break; \
1493 } \
1494 } \
1495 while (0)
1496 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
1497 #endif
1498
1499 #if defined (__z8000__) && W_TYPE_SIZE == 16
1500 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1501 __asm__ ("add %H1,%H5\n\tadc %H0,%H3" \
1502 : "=r" ((unsigned int)(sh)), \
1503 "=&r" ((unsigned int)(sl)) \
1504 : "%0" ((unsigned int)(ah)), \
1505 "r" ((unsigned int)(bh)), \
1506 "%1" ((unsigned int)(al)), \
1507 "rQR" ((unsigned int)(bl)))
1508 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1509 __asm__ ("sub %H1,%H5\n\tsbc %H0,%H3" \
1510 : "=r" ((unsigned int)(sh)), \
1511 "=&r" ((unsigned int)(sl)) \
1512 : "0" ((unsigned int)(ah)), \
1513 "r" ((unsigned int)(bh)), \
1514 "1" ((unsigned int)(al)), \
1515 "rQR" ((unsigned int)(bl)))
1516 #define umul_ppmm(xh, xl, m0, m1) \
1517 do { \
1518 union {long int __ll; \
1519 struct {unsigned int __h, __l;} __i; \
1520 } __xx; \
1521 unsigned int __m0 = (m0), __m1 = (m1); \
1522 __asm__ ("mult %S0,%H3" \
1523 : "=r" (__xx.__i.__h), \
1524 "=r" (__xx.__i.__l) \
1525 : "%1" (__m0), \
1526 "rQR" (__m1)); \
1527 (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1528 (xh) += ((((signed int) __m0 >> 15) & __m1) \
1529 + (((signed int) __m1 >> 15) & __m0)); \
1530 } while (0)
1531 #endif /* __z8000__ */
1532
1533 #endif /* __GNUC__ */
1534
1535 /* If this machine has no inline assembler, use C macros. */
1536
1537 #if !defined (add_ssaaaa)
1538 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1539 do { \
1540 UWtype __x; \
1541 __x = (al) + (bl); \
1542 (sh) = (ah) + (bh) + (__x < (al)); \
1543 (sl) = __x; \
1544 } while (0)
1545 #endif
1546
1547 #if !defined (sub_ddmmss)
1548 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1549 do { \
1550 UWtype __x; \
1551 __x = (al) - (bl); \
1552 (sh) = (ah) - (bh) - (__x > (al)); \
1553 (sl) = __x; \
1554 } while (0)
1555 #endif
1556
1557 /* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
1558 smul_ppmm. */
1559 #if !defined (umul_ppmm) && defined (smul_ppmm)
1560 #define umul_ppmm(w1, w0, u, v) \
1561 do { \
1562 UWtype __w1; \
1563 UWtype __xm0 = (u), __xm1 = (v); \
1564 smul_ppmm (__w1, w0, __xm0, __xm1); \
1565 (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1) \
1566 + (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0); \
1567 } while (0)
1568 #endif
1569
1570 /* If we still don't have umul_ppmm, define it using plain C. */
1571 #if !defined (umul_ppmm)
1572 #define umul_ppmm(w1, w0, u, v) \
1573 do { \
1574 UWtype __x0, __x1, __x2, __x3; \
1575 UHWtype __ul, __vl, __uh, __vh; \
1576 \
1577 __ul = __ll_lowpart (u); \
1578 __uh = __ll_highpart (u); \
1579 __vl = __ll_lowpart (v); \
1580 __vh = __ll_highpart (v); \
1581 \
1582 __x0 = (UWtype) __ul * __vl; \
1583 __x1 = (UWtype) __ul * __vh; \
1584 __x2 = (UWtype) __uh * __vl; \
1585 __x3 = (UWtype) __uh * __vh; \
1586 \
1587 __x1 += __ll_highpart (__x0);/* this can't give carry */ \
1588 __x1 += __x2; /* but this indeed can */ \
1589 if (__x1 < __x2) /* did we get it? */ \
1590 __x3 += __ll_B; /* yes, add it in the proper pos. */ \
1591 \
1592 (w1) = __x3 + __ll_highpart (__x1); \
1593 (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
1594 } while (0)
1595 #endif
1596
1597 #if !defined (__umulsidi3)
1598 #define __umulsidi3(u, v) \
1599 ({DWunion __w; \
1600 umul_ppmm (__w.s.high, __w.s.low, u, v); \
1601 __w.ll; })
1602 #endif
1603
1604 /* Define this unconditionally, so it can be used for debugging. */
1605 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1606 do { \
1607 UWtype __d1, __d0, __q1, __q0; \
1608 UWtype __r1, __r0, __m; \
1609 __d1 = __ll_highpart (d); \
1610 __d0 = __ll_lowpart (d); \
1611 \
1612 __r1 = (n1) % __d1; \
1613 __q1 = (n1) / __d1; \
1614 __m = (UWtype) __q1 * __d0; \
1615 __r1 = __r1 * __ll_B | __ll_highpart (n0); \
1616 if (__r1 < __m) \
1617 { \
1618 __q1--, __r1 += (d); \
1619 if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
1620 if (__r1 < __m) \
1621 __q1--, __r1 += (d); \
1622 } \
1623 __r1 -= __m; \
1624 \
1625 __r0 = __r1 % __d1; \
1626 __q0 = __r1 / __d1; \
1627 __m = (UWtype) __q0 * __d0; \
1628 __r0 = __r0 * __ll_B | __ll_lowpart (n0); \
1629 if (__r0 < __m) \
1630 { \
1631 __q0--, __r0 += (d); \
1632 if (__r0 >= (d)) \
1633 if (__r0 < __m) \
1634 __q0--, __r0 += (d); \
1635 } \
1636 __r0 -= __m; \
1637 \
1638 (q) = (UWtype) __q1 * __ll_B | __q0; \
1639 (r) = __r0; \
1640 } while (0)
1641
1642 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1643 __udiv_w_sdiv (defined in libgcc or elsewhere). */
1644 #if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
1645 #define udiv_qrnnd(q, r, nh, nl, d) \
1646 do { \
1647 USItype __r; \
1648 (q) = __udiv_w_sdiv (&__r, nh, nl, d); \
1649 (r) = __r; \
1650 } while (0)
1651 #endif
1652
1653 /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c. */
1654 #if !defined (udiv_qrnnd)
1655 #define UDIV_NEEDS_NORMALIZATION 1
1656 #define udiv_qrnnd __udiv_qrnnd_c
1657 #endif
1658
1659 #if !defined (count_leading_zeros)
1660 #define count_leading_zeros(count, x) \
1661 do { \
1662 UWtype __xr = (x); \
1663 UWtype __a; \
1664 \
1665 if (W_TYPE_SIZE <= 32) \
1666 { \
1667 __a = __xr < ((UWtype)1<<2*__BITS4) \
1668 ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4) \
1669 : (__xr < ((UWtype)1<<3*__BITS4) ? 2*__BITS4 : 3*__BITS4); \
1670 } \
1671 else \
1672 { \
1673 for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8) \
1674 if (((__xr >> __a) & 0xff) != 0) \
1675 break; \
1676 } \
1677 \
1678 (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a); \
1679 } while (0)
1680 #define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
1681 #endif
1682
1683 #if !defined (count_trailing_zeros)
1684 /* Define count_trailing_zeros using count_leading_zeros. The latter might be
1685 defined in asm, but if it is not, the C version above is good enough. */
1686 #define count_trailing_zeros(count, x) \
1687 do { \
1688 UWtype __ctz_x = (x); \
1689 UWtype __ctz_c; \
1690 count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x); \
1691 (count) = W_TYPE_SIZE - 1 - __ctz_c; \
1692 } while (0)
1693 #endif
1694
1695 #ifndef UDIV_NEEDS_NORMALIZATION
1696 #define UDIV_NEEDS_NORMALIZATION 0
1697 #endif
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