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1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
108 #ifndef CHECK_STACK_LIMIT
109 #define CHECK_STACK_LIMIT (-1)
110 #endif
112 /* Return index of given mode in mult and division cost tables. */
113 #define MODE_INDEX(mode) \
114 ((mode) == QImode ? 0 \
115 : (mode) == HImode ? 1 \
116 : (mode) == SImode ? 2 \
117 : (mode) == DImode ? 3 \
118 : 4)
120 /* Processor costs (relative to an add) */
121 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
122 #define COSTS_N_BYTES(N) ((N) * 2)
124 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
133 const
156 in QImode, HImode and SImode.
157 Relative to reg-reg move (2). */
161 in SFmode, DFmode and XFmode */
163 in SFmode, DFmode and XFmode */
166 in SImode and DImode */
168 in SImode and DImode */
171 in SImode, DImode and TImode */
173 in SImode, DImode and TImode */
186 ix86_size_memcpy,
187 ix86_size_memset,
199 };
201 /* Processor costs (relative to an add) */
204 DUMMY_STRINGOP_ALGS};
207 DUMMY_STRINGOP_ALGS};
209 static const
232 in QImode, HImode and SImode.
233 Relative to reg-reg move (2). */
237 in SFmode, DFmode and XFmode */
239 in SFmode, DFmode and XFmode */
242 in SImode and DImode */
244 in SImode and DImode */
247 in SImode, DImode and TImode */
249 in SImode, DImode and TImode */
262 i386_memcpy,
263 i386_memset,
275 };
279 DUMMY_STRINGOP_ALGS};
282 DUMMY_STRINGOP_ALGS};
284 static const
307 in QImode, HImode and SImode.
308 Relative to reg-reg move (2). */
312 in SFmode, DFmode and XFmode */
314 in SFmode, DFmode and XFmode */
317 in SImode and DImode */
319 in SImode and DImode */
322 in SImode, DImode and TImode */
324 in SImode, DImode and TImode */
327 shared for code and data, so 4kB is
328 not really precise. */
339 i486_memcpy,
340 i486_memset,
352 };
356 DUMMY_STRINGOP_ALGS};
359 DUMMY_STRINGOP_ALGS};
361 static const
384 in QImode, HImode and SImode.
385 Relative to reg-reg move (2). */
389 in SFmode, DFmode and XFmode */
391 in SFmode, DFmode and XFmode */
394 in SImode and DImode */
396 in SImode and DImode */
399 in SImode, DImode and TImode */
401 in SImode, DImode and TImode */
414 pentium_memcpy,
415 pentium_memset,
427 };
429 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
430 (we ensure the alignment). For small blocks inline loop is still a
431 noticeable win, for bigger blocks either rep movsl or rep movsb is
432 way to go. Rep movsb has apparently more expensive startup time in CPU,
433 but after 4K the difference is down in the noise. */
438 DUMMY_STRINGOP_ALGS};
443 DUMMY_STRINGOP_ALGS};
444 static const
467 in QImode, HImode and SImode.
468 Relative to reg-reg move (2). */
472 in SFmode, DFmode and XFmode */
474 in SFmode, DFmode and XFmode */
477 in SImode and DImode */
479 in SImode and DImode */
482 in SImode, DImode and TImode */
484 in SImode, DImode and TImode */
497 pentiumpro_memcpy,
498 pentiumpro_memset,
510 };
514 DUMMY_STRINGOP_ALGS};
517 DUMMY_STRINGOP_ALGS};
518 static const
541 in QImode, HImode and SImode.
542 Relative to reg-reg move (2). */
546 in SFmode, DFmode and XFmode */
548 in SFmode, DFmode and XFmode */
552 in SImode and DImode */
554 in SImode and DImode */
557 in SImode, DImode and TImode */
559 in SImode, DImode and TImode */
572 geode_memcpy,
573 geode_memset,
585 };
589 DUMMY_STRINGOP_ALGS};
592 DUMMY_STRINGOP_ALGS};
593 static const
616 in QImode, HImode and SImode.
617 Relative to reg-reg move (2). */
621 in SFmode, DFmode and XFmode */
623 in SFmode, DFmode and XFmode */
626 in SImode and DImode */
628 in SImode and DImode */
631 in SImode, DImode and TImode */
633 in SImode, DImode and TImode */
637 have integrated l2 cache, but
638 optimizing for k6 is not important
639 enough to worry about that. */
649 k6_memcpy,
650 k6_memset,
662 };
664 /* For some reason, Athlon deals better with REP prefix (relative to loops)
665 compared to K8. Alignment becomes important after 8 bytes for memcpy and
666 128 bytes for memset. */
669 DUMMY_STRINGOP_ALGS};
672 DUMMY_STRINGOP_ALGS};
673 static const
696 in QImode, HImode and SImode.
697 Relative to reg-reg move (2). */
701 in SFmode, DFmode and XFmode */
703 in SFmode, DFmode and XFmode */
706 in SImode and DImode */
708 in SImode and DImode */
711 in SImode, DImode and TImode */
713 in SImode, DImode and TImode */
726 athlon_memcpy,
727 athlon_memset,
739 };
741 /* K8 has optimized REP instruction for medium sized blocks, but for very
742 small blocks it is better to use loop. For large blocks, libcall can
743 do nontemporary accesses and beat inline considerably. */
754 static const
777 in QImode, HImode and SImode.
778 Relative to reg-reg move (2). */
782 in SFmode, DFmode and XFmode */
784 in SFmode, DFmode and XFmode */
787 in SImode and DImode */
789 in SImode and DImode */
792 in SImode, DImode and TImode */
794 in SImode, DImode and TImode */
799 /* New AMD processors never drop prefetches; if they cannot be performed
800 immediately, they are queued. We set number of simultaneous prefetches
801 to a large constant to reflect this (it probably is not a good idea not
802 to limit number of prefetches at all, as their execution also takes some
803 time). */
813 k8_memcpy,
814 k8_memset,
826 };
828 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
829 very small blocks it is better to use loop. For large blocks, libcall can
830 do nontemporary accesses and beat inline considerably. */
863 in QImode, HImode and SImode.
864 Relative to reg-reg move (2). */
868 in SFmode, DFmode and XFmode */
870 in SFmode, DFmode and XFmode */
873 in SImode and DImode */
875 in SImode and DImode */
878 in SImode, DImode and TImode */
880 in SImode, DImode and TImode */
882 /* On K8:
883 MOVD reg64, xmmreg Double FSTORE 4
884 MOVD reg32, xmmreg Double FSTORE 4
885 On AMDFAM10:
886 MOVD reg64, xmmreg Double FADD 3
887 1/1 1/1
888 MOVD reg32, xmmreg Double FADD 3
889 1/1 1/1 */
893 /* New AMD processors never drop prefetches; if they cannot be performed
894 immediately, they are queued. We set number of simultaneous prefetches
895 to a large constant to reflect this (it probably is not a good idea not
896 to limit number of prefetches at all, as their execution also takes some
897 time). */
907 amdfam10_memcpy,
908 amdfam10_memset,
920 };
922 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
923 very small blocks it is better to use loop. For large blocks, libcall
924 can do nontemporary accesses and beat inline considerably. */
958 in QImode, HImode and SImode.
959 Relative to reg-reg move (2). */
963 in SFmode, DFmode and XFmode */
965 in SFmode, DFmode and XFmode */
968 in SImode and DImode */
970 in SImode and DImode */
973 in SImode, DImode and TImode */
975 in SImode, DImode and TImode */
977 /* On K8:
978 MOVD reg64, xmmreg Double FSTORE 4
979 MOVD reg32, xmmreg Double FSTORE 4
980 On AMDFAM10:
981 MOVD reg64, xmmreg Double FADD 3
982 1/1 1/1
983 MOVD reg32, xmmreg Double FADD 3
984 1/1 1/1 */
988 /* New AMD processors never drop prefetches; if they cannot be performed
989 immediately, they are queued. We set number of simultaneous prefetches
990 to a large constant to reflect this (it probably is not a good idea not
991 to limit number of prefetches at all, as their execution also takes some
992 time). */
1002 bdver1_memcpy,
1003 bdver1_memset,
1015 };
1017 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1018 very small blocks it is better to use loop. For large blocks, libcall
1019 can do nontemporary accesses and beat inline considerably. */
1054 in QImode, HImode and SImode.
1055 Relative to reg-reg move (2). */
1059 in SFmode, DFmode and XFmode */
1061 in SFmode, DFmode and XFmode */
1064 in SImode and DImode */
1066 in SImode and DImode */
1069 in SImode, DImode and TImode */
1071 in SImode, DImode and TImode */
1073 /* On K8:
1074 MOVD reg64, xmmreg Double FSTORE 4
1075 MOVD reg32, xmmreg Double FSTORE 4
1076 On AMDFAM10:
1077 MOVD reg64, xmmreg Double FADD 3
1078 1/1 1/1
1079 MOVD reg32, xmmreg Double FADD 3
1080 1/1 1/1 */
1084 /* New AMD processors never drop prefetches; if they cannot be performed
1085 immediately, they are queued. We set number of simultaneous prefetches
1086 to a large constant to reflect this (it probably is not a good idea not
1087 to limit number of prefetches at all, as their execution also takes some
1088 time). */
1098 bdver2_memcpy,
1099 bdver2_memset,
1111 };
1114 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1115 very small blocks it is better to use loop. For large blocks, libcall
1116 can do nontemporary accesses and beat inline considerably. */
1149 in QImode, HImode and SImode.
1150 Relative to reg-reg move (2). */
1154 in SFmode, DFmode and XFmode */
1156 in SFmode, DFmode and XFmode */
1159 in SImode and DImode */
1161 in SImode and DImode */
1164 in SImode, DImode and TImode */
1166 in SImode, DImode and TImode */
1171 /* New AMD processors never drop prefetches; if they cannot be performed
1172 immediately, they are queued. We set number of simultaneous prefetches
1173 to a large constant to reflect this (it probably is not a good idea not
1174 to limit number of prefetches at all, as their execution also takes some
1175 time). */
1185 bdver3_memcpy,
1186 bdver3_memset,
1198 };
1200 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1201 very small blocks it is better to use loop. For large blocks, libcall
1202 can do nontemporary accesses and beat inline considerably. */
1235 in QImode, HImode and SImode.
1236 Relative to reg-reg move (2). */
1240 in SFmode, DFmode and XFmode */
1242 in SFmode, DFmode and XFmode */
1245 in SImode and DImode */
1247 in SImode and DImode */
1250 in SImode, DImode and TImode */
1252 in SImode, DImode and TImode */
1257 /* New AMD processors never drop prefetches; if they cannot be performed
1258 immediately, they are queued. We set number of simultaneous prefetches
1259 to a large constant to reflect this (it probably is not a good idea not
1260 to limit number of prefetches at all, as their execution also takes some
1261 time). */
1271 bdver4_memcpy,
1272 bdver4_memset,
1284 };
1286 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1287 very small blocks it is better to use loop. For large blocks, libcall can
1288 do nontemporary accesses and beat inline considerably. */
1321 in QImode, HImode and SImode.
1322 Relative to reg-reg move (2). */
1326 in SFmode, DFmode and XFmode */
1328 in SFmode, DFmode and XFmode */
1331 in SImode and DImode */
1333 in SImode and DImode */
1336 in SImode, DImode and TImode */
1338 in SImode, DImode and TImode */
1340 /* On K8:
1341 MOVD reg64, xmmreg Double FSTORE 4
1342 MOVD reg32, xmmreg Double FSTORE 4
1343 On AMDFAM10:
1344 MOVD reg64, xmmreg Double FADD 3
1345 1/1 1/1
1346 MOVD reg32, xmmreg Double FADD 3
1347 1/1 1/1 */
1360 btver1_memcpy,
1361 btver1_memset,
1373 };
1407 in QImode, HImode and SImode.
1408 Relative to reg-reg move (2). */
1412 in SFmode, DFmode and XFmode */
1414 in SFmode, DFmode and XFmode */
1417 in SImode and DImode */
1419 in SImode and DImode */
1422 in SImode, DImode and TImode */
1424 in SImode, DImode and TImode */
1426 /* On K8:
1427 MOVD reg64, xmmreg Double FSTORE 4
1428 MOVD reg32, xmmreg Double FSTORE 4
1429 On AMDFAM10:
1430 MOVD reg64, xmmreg Double FADD 3
1431 1/1 1/1
1432 MOVD reg32, xmmreg Double FADD 3
1433 1/1 1/1 */
1445 btver2_memcpy,
1446 btver2_memset,
1458 };
1462 DUMMY_STRINGOP_ALGS};
1466 DUMMY_STRINGOP_ALGS};
1468 static const
1491 in QImode, HImode and SImode.
1492 Relative to reg-reg move (2). */
1496 in SFmode, DFmode and XFmode */
1498 in SFmode, DFmode and XFmode */
1501 in SImode and DImode */
1503 in SImode and DImode */
1506 in SImode, DImode and TImode */
1508 in SImode, DImode and TImode */
1521 pentium4_memcpy,
1522 pentium4_memset,
1534 };
1547 static const
1570 in QImode, HImode and SImode.
1571 Relative to reg-reg move (2). */
1575 in SFmode, DFmode and XFmode */
1577 in SFmode, DFmode and XFmode */
1580 in SImode and DImode */
1582 in SImode and DImode */
1585 in SImode, DImode and TImode */
1587 in SImode, DImode and TImode */
1600 nocona_memcpy,
1601 nocona_memset,
1613 };
1624 static const
1647 in QImode, HImode and SImode.
1648 Relative to reg-reg move (2). */
1652 in SFmode, DFmode and XFmode */
1654 in SFmode, DFmode and XFmode */
1657 in SImode and DImode */
1659 in SImode and DImode */
1662 in SImode, DImode and TImode */
1664 in SImode, DImode and TImode */
1677 atom_memcpy,
1678 atom_memset,
1690 };
1701 static const
1724 in QImode, HImode and SImode.
1725 Relative to reg-reg move (2). */
1729 in SFmode, DFmode and XFmode */
1731 in SFmode, DFmode and XFmode */
1734 in SImode and DImode */
1736 in SImode and DImode */
1739 in SImode, DImode and TImode */
1741 in SImode, DImode and TImode */
1754 slm_memcpy,
1755 slm_memset,
1767 };
1778 static const
1801 in QImode, HImode and SImode.
1802 Relative to reg-reg move (2). */
1806 in SFmode, DFmode and XFmode */
1808 in SFmode, DFmode and XFmode */
1811 in SImode and DImode */
1813 in SImode and DImode */
1816 in SImode, DImode and TImode */
1818 in SImode, DImode and TImode */
1831 intel_memcpy,
1832 intel_memset,
1844 };
1846 /* Generic should produce code tuned for Core-i7 (and newer chips)
1847 and btver1 (and newer chips). */
1859 static const
1862 /* On all chips taken into consideration lea is 2 cycles and more. With
1863 this cost however our current implementation of synth_mult results in
1864 use of unnecessary temporary registers causing regression on several
1865 SPECfp benchmarks. */
1886 in QImode, HImode and SImode.
1887 Relative to reg-reg move (2). */
1891 in SFmode, DFmode and XFmode */
1893 in SFmode, DFmode and XFmode */
1896 in SImode and DImode */
1898 in SImode and DImode */
1901 in SImode, DImode and TImode */
1903 in SImode, DImode and TImode */
1909 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1910 value is increased to perhaps more appropriate value of 5. */
1918 generic_memcpy,
1919 generic_memset,
1931 };
1933 /* core_cost should produce code tuned for Core familly of CPUs. */
1946 static const
1949 /* On all chips taken into consideration lea is 2 cycles and more. With
1950 this cost however our current implementation of synth_mult results in
1951 use of unnecessary temporary registers causing regression on several
1952 SPECfp benchmarks. */
1973 in QImode, HImode and SImode.
1974 Relative to reg-reg move (2). */
1978 in SFmode, DFmode and XFmode */
1980 in SFmode, DFmode and XFmode */
1983 in SImode and DImode */
1985 in SImode and DImode */
1988 in SImode, DImode and TImode */
1990 in SImode, DImode and TImode */
1996 /* FIXME perhaps more appropriate value is 5. */
2004 core_memcpy,
2005 core_memset,
2017 };
2020 /* Set by -mtune. */
2023 /* Set by -mtune or -Os. */
2026 /* Processor feature/optimization bitmasks. */
2027 #define m_386 (1<<PROCESSOR_I386)
2028 #define m_486 (1<<PROCESSOR_I486)
2029 #define m_PENT (1<<PROCESSOR_PENTIUM)
2030 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2031 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2032 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2033 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2034 #define m_CORE2 (1<<PROCESSOR_CORE2)
2035 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2036 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2037 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2038 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2039 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2040 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2041 #define m_KNL (1<<PROCESSOR_KNL)
2042 #define m_INTEL (1<<PROCESSOR_INTEL)
2044 #define m_GEODE (1<<PROCESSOR_GEODE)
2045 #define m_K6 (1<<PROCESSOR_K6)
2046 #define m_K6_GEODE (m_K6 | m_GEODE)
2047 #define m_K8 (1<<PROCESSOR_K8)
2048 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2049 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2050 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2051 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2052 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2053 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2054 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2055 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2056 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2057 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2058 #define m_BTVER (m_BTVER1 | m_BTVER2)
2059 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2061 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2064 #undef DEF_TUNE
2065 #define DEF_TUNE(tune, name, selector) name,
2067 #undef DEF_TUNE
2068 };
2070 /* Feature tests against the various tunings. */
2073 /* Feature tests against the various tunings used to create ix86_tune_features
2074 based on the processor mask. */
2076 #undef DEF_TUNE
2077 #define DEF_TUNE(tune, name, selector) selector,
2079 #undef DEF_TUNE
2080 };
2082 /* Feature tests against the various architecture variations. */
2085 /* Feature tests against the various architecture variations, used to create
2086 ix86_arch_features based on the processor mask. */
2088 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2091 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2094 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2097 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2100 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2102 };
2104 /* In case the average insn count for single function invocation is
2105 lower than this constant, emit fast (but longer) prologue and
2106 epilogue code. */
2107 #define FAST_PROLOGUE_INSN_COUNT 20
2109 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2114 /* Array of the smallest class containing reg number REGNO, indexed by
2115 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2118 {
2119 /* ax, dx, cx, bx */
2121 /* si, di, bp, sp */
2123 /* FP registers */
2126 /* arg pointer */
2127 NON_Q_REGS,
2128 /* flags, fpsr, fpcr, frame */
2130 /* SSE registers */
2133 /* MMX registers */
2136 /* REX registers */
2139 /* SSE REX registers */
2142 /* AVX-512 SSE registers */
2147 /* Mask registers. */
2150 /* MPX bound registers */
2152 };
2154 /* The "default" register map used in 32bit mode. */
2157 {
2169 };
2171 /* The "default" register map used in 64bit mode. */
2174 {
2186 };
2188 /* Define the register numbers to be used in Dwarf debugging information.
2189 The SVR4 reference port C compiler uses the following register numbers
2190 in its Dwarf output code:
2191 0 for %eax (gcc regno = 0)
2192 1 for %ecx (gcc regno = 2)
2193 2 for %edx (gcc regno = 1)
2194 3 for %ebx (gcc regno = 3)
2195 4 for %esp (gcc regno = 7)
2196 5 for %ebp (gcc regno = 6)
2197 6 for %esi (gcc regno = 4)
2198 7 for %edi (gcc regno = 5)
2199 The following three DWARF register numbers are never generated by
2200 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2201 believes these numbers have these meanings.
2202 8 for %eip (no gcc equivalent)
2203 9 for %eflags (gcc regno = 17)
2204 10 for %trapno (no gcc equivalent)
2205 It is not at all clear how we should number the FP stack registers
2206 for the x86 architecture. If the version of SDB on x86/svr4 were
2207 a bit less brain dead with respect to floating-point then we would
2208 have a precedent to follow with respect to DWARF register numbers
2209 for x86 FP registers, but the SDB on x86/svr4 is so completely
2210 broken with respect to FP registers that it is hardly worth thinking
2211 of it as something to strive for compatibility with.
2212 The version of x86/svr4 SDB I have at the moment does (partially)
2213 seem to believe that DWARF register number 11 is associated with
2214 the x86 register %st(0), but that's about all. Higher DWARF
2215 register numbers don't seem to be associated with anything in
2216 particular, and even for DWARF regno 11, SDB only seems to under-
2217 stand that it should say that a variable lives in %st(0) (when
2218 asked via an `=' command) if we said it was in DWARF regno 11,
2219 but SDB still prints garbage when asked for the value of the
2220 variable in question (via a `/' command).
2221 (Also note that the labels SDB prints for various FP stack regs
2222 when doing an `x' command are all wrong.)
2223 Note that these problems generally don't affect the native SVR4
2224 C compiler because it doesn't allow the use of -O with -g and
2225 because when it is *not* optimizing, it allocates a memory
2226 location for each floating-point variable, and the memory
2227 location is what gets described in the DWARF AT_location
2228 attribute for the variable in question.
2229 Regardless of the severe mental illness of the x86/svr4 SDB, we
2230 do something sensible here and we use the following DWARF
2231 register numbers. Note that these are all stack-top-relative
2232 numbers.
2233 11 for %st(0) (gcc regno = 8)
2234 12 for %st(1) (gcc regno = 9)
2235 13 for %st(2) (gcc regno = 10)
2236 14 for %st(3) (gcc regno = 11)
2237 15 for %st(4) (gcc regno = 12)
2238 16 for %st(5) (gcc regno = 13)
2239 17 for %st(6) (gcc regno = 14)
2240 18 for %st(7) (gcc regno = 15)
2241 */
2243 {
2255 };
2257 /* Define parameter passing and return registers. */
2260 {
2262 };
2265 {
2267 };
2270 {
2272 };
2274 /* Additional registers that are clobbered by SYSV calls. */
2277 {
2282 };
2284 /* Define the structure for the machine field in struct function. */
2289 rtx rtl;
2291 };
2293 /* Structure describing stack frame layout.
2294 Stack grows downward:
2296 [arguments]
2297 <- ARG_POINTER
2298 saved pc
2300 saved static chain if ix86_static_chain_on_stack
2302 saved frame pointer if frame_pointer_needed
2303 <- HARD_FRAME_POINTER
2304 [saved regs]
2305 <- regs_save_offset
2306 [padding0]
2308 [saved SSE regs]
2309 <- sse_regs_save_offset
2310 [padding1] |
2311 | <- FRAME_POINTER
2312 [va_arg registers] |
2313 |
2314 [frame] |
2315 |
2316 [padding2] | = to_allocate
2317 <- STACK_POINTER
2318 */
2319 struct ix86_frame
2320 {
2327 /* The offsets relative to ARG_POINTER. */
2328 HOST_WIDE_INT frame_pointer_offset;
2329 HOST_WIDE_INT hard_frame_pointer_offset;
2330 HOST_WIDE_INT stack_pointer_offset;
2331 HOST_WIDE_INT hfp_save_offset;
2332 HOST_WIDE_INT reg_save_offset;
2333 HOST_WIDE_INT sse_reg_save_offset;
2335 /* When save_regs_using_mov is set, emit prologue using
2336 move instead of push instructions. */
2338 };
2340 /* Which cpu are we scheduling for. */
2343 /* Which cpu are we optimizing for. */
2346 /* Which instruction set architecture to use. */
2349 /* True if processor has SSE prefetch instruction. */
2352 /* -mstackrealign option */
2370 /* Preferred alignment for stack boundary in bits. */
2373 /* Alignment for incoming stack boundary in bits specified at
2374 command line. */
2377 /* Default alignment for incoming stack boundary in bits. */
2380 /* Alignment for incoming stack boundary in bits. */
2383 /* Calling abi specific va_list type nodes. */
2387 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2391 /* Fence to use after loop using movnt. */
2392 tree x86_mfence;
2394 /* Register class used for passing given 64bit part of the argument.
2395 These represent classes as documented by the PS ABI, with the exception
2396 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2397 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2399 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2400 whenever possible (upper half does contain padding). */
2401 enum x86_64_reg_class
2402 {
2403 X86_64_NO_CLASS,
2404 X86_64_INTEGER_CLASS,
2405 X86_64_INTEGERSI_CLASS,
2406 X86_64_SSE_CLASS,
2407 X86_64_SSESF_CLASS,
2408 X86_64_SSEDF_CLASS,
2409 X86_64_SSEUP_CLASS,
2410 X86_64_X87_CLASS,
2411 X86_64_X87UP_CLASS,
2412 X86_64_COMPLEX_X87_CLASS,
2413 X86_64_MEMORY_CLASS
2414 };
2416 #define MAX_CLASSES 8
2418 /* Table of constants used by fldpi, fldln2, etc.... */
2422 \f
2427 const_tree);
2439 enum ix86_function_specific_strings
2440 {
2441 IX86_FUNCTION_SPECIFIC_ARCH,
2442 IX86_FUNCTION_SPECIFIC_TUNE,
2443 IX86_FUNCTION_SPECIFIC_MAX
2444 };
2466 \f
2467 #ifndef SUBTARGET32_DEFAULT_CPU
2469 #endif
2471 /* Whether -mtune= or -march= were specified */
2475 /* Vectorization library interface and handlers. */
2481 /* Processor target table, indexed by processor number */
2482 struct ptt
2483 {
2491 };
2493 /* This table must be in sync with enum processor_type in i386.h. */
2495 {
2522 };
2523 \f
2524 static unsigned int
2526 {
2529 /* vzeroupper instructions are inserted immediately after reload to
2530 account for possible spills from 256bit registers. The pass
2531 reuses mode switching infrastructure by re-running mode insertion
2532 pass, so disable entities that have already been processed. */
2538 /* Call optimize_mode_switching. */
2541 }
2546 {
2556 };
2559 {
2563 {}
2565 /* opt_pass methods: */
2567 {
2571 }
2574 {
2576 }
2582 rtl_opt_pass *
2584 {
2586 }
2588 /* Return true if a red-zone is in use. */
2592 {
2594 }
2595 \f
2596 /* Return a string that documents the current -m options. The caller is
2597 responsible for freeing the string. */
2603 {
2604 struct ix86_target_opts
2605 {
2608 };
2610 /* This table is ordered so that options like -msse4.2 that imply
2611 preceding options while match those first. */
2613 {
2667 };
2669 /* Flag options. */
2671 {
2700 };
2717 /* Add -march= option. */
2719 {
2722 }
2724 /* Add -mtune= option. */
2726 {
2729 }
2731 /* Add -m32/-m64/-mx32. */
2733 {
2736 else
2738 isa &= ~ (OPTION_MASK_ISA_64BIT
2739 | OPTION_MASK_ABI_64
2741 }
2742 else
2746 /* Pick out the options in isa options. */
2748 {
2750 {
2753 }
2754 }
2757 {
2760 isa);
2761 }
2763 /* Add flag options. */
2765 {
2767 {
2770 }
2771 }
2774 {
2777 }
2779 /* Add -fpmath= option. */
2781 {
2784 {
2799 }
2800 }
2802 /* Any options? */
2808 /* Size the string. */
2812 {
2817 }
2819 /* Build the string. */
2824 {
2831 {
2833 line_len++;
2836 {
2840 }
2841 }
2845 {
2849 }
2850 }
2856 }
2858 /* Return true, if profiling code should be emitted before
2859 prologue. Otherwise it returns false.
2860 Note: For x86 with "hotfix" it is sorried. */
2861 static bool
2863 {
2865 }
2867 /* Function that is callable from the debugger to print the current
2868 options. */
2869 void ATTRIBUTE_UNUSED
2871 {
2877 {
2880 }
2881 else
2885 }
2888 #define DEF_ENUM
2889 #define DEF_ALG(alg, name) #name,
2891 #undef DEF_ENUM
2892 #undef DEF_ALG
2893 };
2895 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2896 The string is of the following form (or comma separated list of it):
2898 strategy_alg:max_size:[align|noalign]
2900 where the full size range for the strategy is either [0, max_size] or
2901 [min_size, max_size], in which min_size is the max_size + 1 of the
2902 preceding range. The last size range must have max_size == -1.
2904 Examples:
2906 1.
2907 -mmemcpy-strategy=libcall:-1:noalign
2909 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2912 2.
2913 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2915 This is to tell the compiler to use the following strategy for memset
2916 1) when the expected size is between [1, 16], use rep_8byte strategy;
2917 2) when the size is between [17, 2048], use vector_loop;
2918 3) when the size is > 2048, use libcall. */
2920 struct stringop_size_range
2921 {
2923 stringop_alg alg;
2925 };
2927 static void
2929 {
2937 else
2942 do
2943 {
2953 {
2957 }
2960 {
2964 }
2971 {
2973 alg_name,
2976 }
2980 {
2981 /* rep; movq isn't available in 32-bit code. */
2984 alg_name,
2987 }
2995 else
2996 {
3000 }
3001 n++;
3003 }
3007 {
3012 }
3015 {
3019 }
3021 /* Now override the default algs array. */
3023 {
3029 }
3030 }
3032 \f
3033 /* parse -mtune-ctrl= option. When DUMP is true,
3034 print the features that are explicitly set. */
3036 static void
3038 {
3046 do
3047 {
3054 {
3055 curr_feature_string++;
3057 }
3059 {
3061 {
3067 }
3068 }
3073 }
3076 }
3078 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3079 processor type. */
3081 static void
3083 {
3088 {
3091 else
3093 }
3096 {
3101 }
3104 }
3107 /* Default align_* from the processor table. */
3109 static void
3111 {
3113 {
3116 }
3118 {
3121 }
3123 {
3125 }
3126 }
3128 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE hook. */
3130 static void
3132 {
3134 }
3136 /* Override various settings based on options. If MAIN_ARGS_P, the
3137 options are from the command line, otherwise they are from
3138 attributes. */
3140 static void
3144 {
3152 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3153 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3154 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3155 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3156 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3157 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3158 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3159 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3160 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3161 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3162 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3163 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3164 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3165 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3166 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3167 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3168 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3169 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3170 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3171 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3172 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3173 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3174 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3175 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3176 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3177 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3178 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3179 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3180 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3181 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3182 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3183 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3184 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3185 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3186 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3187 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3188 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3189 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3190 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3191 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3192 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3193 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3194 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3195 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3196 #define PTA_MPX (HOST_WIDE_INT_1 << 44)
3197 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3198 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3199 #define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
3200 #define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
3201 #define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
3202 #define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
3203 #define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
3204 #define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
3205 #define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 53)
3206 #define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 54)
3207 #define PTA_CLWB (HOST_WIDE_INT_1 << 55)
3208 #define PTA_PCOMMIT (HOST_WIDE_INT_1 << 56)
3209 #define PTA_MWAITX (HOST_WIDE_INT_1 << 57)
3211 #define PTA_CORE2 \
3212 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3213 | PTA_CX16 | PTA_FXSR)
3214 #define PTA_NEHALEM \
3215 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3216 #define PTA_WESTMERE \
3217 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3218 #define PTA_SANDYBRIDGE \
3219 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3220 #define PTA_IVYBRIDGE \
3221 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3222 #define PTA_HASWELL \
3223 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3224 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3225 #define PTA_BROADWELL \
3226 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3227 #define PTA_KNL \
3228 (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
3229 #define PTA_BONNELL \
3230 (PTA_CORE2 | PTA_MOVBE)
3231 #define PTA_SILVERMONT \
3232 (PTA_WESTMERE | PTA_MOVBE)
3234 /* if this reaches 64, need to widen struct pta flags below */
3236 static struct pta
3237 {
3242 }
3244 {
3278 PTA_SANDYBRIDGE},
3280 PTA_SANDYBRIDGE},
3282 PTA_IVYBRIDGE},
3284 PTA_IVYBRIDGE},
3376 PTA_64BIT
3378 };
3380 /* -mrecip options. */
3381 static struct
3382 {
3385 }
3387 {
3394 };
3398 /* Set up prefix/suffix so the error messages refer to either the command
3399 line argument, or the attribute(target). */
3401 {
3405 }
3406 else
3407 {
3411 }
3413 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3414 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3417 #ifdef TARGET_BI_ARCH
3418 else
3419 {
3420 #if TARGET_BI_ARCH == 1
3421 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3422 is on and OPTION_MASK_ABI_X32 is off. We turn off
3423 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3424 -mx32. */
3427 #else
3428 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3429 on and OPTION_MASK_ABI_64 is off. We turn off
3430 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3431 -m64 or OPTION_MASK_CODE16 is turned on by -m16. */
3435 #endif
3436 }
3437 #endif
3440 {
3441 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3442 OPTION_MASK_ABI_64 for TARGET_X32. */
3445 }
3448 | OPTION_MASK_ABI_X32
3451 {
3452 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3453 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3456 }
3458 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3459 SUBTARGET_OVERRIDE_OPTIONS;
3460 #endif
3462 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3463 SUBSUBTARGET_OVERRIDE_OPTIONS;
3464 #endif
3466 /* -fPIC is the default for x86_64. */
3470 /* Need to check -mtune=generic first. */
3472 {
3473 /* As special support for cross compilers we read -mtune=native
3474 as -mtune=generic. With native compilers we won't see the
3475 -mtune=native, as it was changed by the driver. */
3477 {
3479 }
3484 }
3485 else
3486 {
3490 {
3491 opts->x_ix86_tune_string
3494 }
3496 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3497 or defaulted. We need to use a sensible tune option. */
3499 {
3501 }
3502 }
3506 {
3507 /* rep; movq isn't available in 32-bit code. */
3510 }
3513 opts->x_ix86_arch_string
3516 else
3520 {
3528 }
3529 else
3536 /* For targets using ms ABI enable ms-extensions, if not
3537 explicit turned off. For non-ms ABI we turn off this
3538 option. */
3543 {
3545 {
3589 {
3592 }
3600 }
3601 }
3602 else
3603 {
3604 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3605 use of rip-relative addressing. This eliminates fixups that
3606 would otherwise be needed if this object is to be placed in a
3607 DLL, and is essentially just as efficient as direct addressing. */
3613 else
3615 }
3617 {
3620 }
3628 {
3631 /* Default cpu tuning to the architecture. */
3812 }
3836 {
3840 {
3842 {
3844 {
3852 }
3853 else
3856 }
3857 }
3858 /* Intel CPUs have always interpreted SSE prefetch instructions as
3859 NOPs; so, we can enable SSE prefetch instructions even when
3860 -mtune (rather than -march) points us to a processor that has them.
3861 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3862 higher processors. */
3867 }
3875 #ifndef USE_IX86_FRAME_POINTER
3876 #define USE_IX86_FRAME_POINTER 0
3877 #endif
3879 #ifndef USE_X86_64_FRAME_POINTER
3880 #define USE_X86_64_FRAME_POINTER 0
3881 #endif
3883 /* Set the default values for switches whose default depends on TARGET_64BIT
3884 in case they weren't overwritten by command line options. */
3886 {
3894 opts->x_flag_unwind_tables
3898 }
3899 else
3900 {
3902 opts->x_flag_omit_frame_pointer
3908 }
3911 /* TODO: ix86_cost should be chosen at instruction or function granuality
3912 so for cold code we use size_cost even in !optimize_size compilation. */
3915 else
3918 /* Arrange to set up i386_stack_locals for all functions. */
3921 /* Validate -mregparm= value. */
3923 {
3927 {
3931 }
3932 }
3936 /* Default align_* from the processor table. */
3939 /* Provide default for -mbranch-cost= value. */
3944 {
3945 opts->x_target_flags
3948 /* Enable by default the SSE and MMX builtins. Do allow the user to
3949 explicitly disable any of these. In particular, disabling SSE and
3950 MMX for kernel code is extremely useful. */
3952 opts->x_ix86_isa_flags
3959 }
3960 else
3961 {
3962 opts->x_target_flags
3966 opts->x_ix86_isa_flags
3969 /* i386 ABI does not specify red zone. It still makes sense to use it
3970 when programmer takes care to stack from being destroyed. */
3973 }
3975 /* Keep nonleaf frame pointers. */
3981 /* If we're doing fast math, we don't care about comparison order
3982 wrt NaNs. This lets us use a shorter comparison sequence. */
3986 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3987 since the insns won't need emulation. */
3991 /* Likewise, if the target doesn't have a 387, or we've specified
3992 software floating point, don't use 387 inline intrinsics. */
3996 /* Turn on MMX builtins for -msse. */
3998 opts->x_ix86_isa_flags
4001 /* Enable SSE prefetch. */
4006 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
4009 opts->x_ix86_isa_flags
4012 /* Enable popcnt instruction for -msse4.2 or -mabm. */
4015 opts->x_ix86_isa_flags
4018 /* Enable lzcnt instruction for -mabm. */
4020 opts->x_ix86_isa_flags
4023 /* Validate -mpreferred-stack-boundary= value or default it to
4024 PREFERRED_STACK_BOUNDARY_DEFAULT. */
4027 {
4034 {
4038 else
4041 }
4042 else
4043 ix86_preferred_stack_boundary
4045 }
4047 /* Set the default value for -mstackrealign. */
4053 /* Validate -mincoming-stack-boundary= value or default it to
4054 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
4057 {
4064 else
4065 {
4066 ix86_user_incoming_stack_boundary
4068 ix86_incoming_stack_boundary
4070 }
4071 }
4073 #ifndef NO_PROFILE_COUNTERS
4076 #endif
4080 /* Accept -msseregparm only if at least SSE support is enabled. */
4086 {
4088 {
4090 {
4093 }
4096 {
4099 }
4100 }
4101 }
4102 /* For all chips supporting SSE2, -mfpmath=sse performs better than
4103 fpmath=387. The second is however default at many targets since the
4104 extra 80bit precision of temporaries is considered to be part of ABI.
4105 Overwrite the default at least for -ffast-math.
4106 TODO: -mfpmath=both seems to produce same performing code with bit
4107 smaller binaries. It is however not clear if register allocation is
4108 ready for this setting.
4109 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
4110 codegen. We may switch to 387 with -ffast-math for size optimized
4111 functions. */
4115 else
4118 /* If the i387 is disabled, then do not return values in it. */
4122 /* Use external vectorized library in vectorizing intrinsics. */
4125 {
4136 }
4142 /* If stack probes are required, the space used for large function
4143 arguments on the stack must also be probed, so enable
4144 -maccumulate-outgoing-args so this happens in the prologue. */
4147 {
4152 }
4154 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4155 {
4161 }
4163 /* When scheduling description is not available, disable scheduler pass
4164 so it won't slow down the compilation and make x87 code slower. */
4185 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4187 && HAVE_prefetch
4193 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4194 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4199 {
4202 {
4204 ix86_gen_tls_local_dynamic_base_64
4206 }
4207 else
4208 {
4210 ix86_gen_tls_local_dynamic_base_64
4212 }
4213 }
4214 else
4218 {
4229 }
4230 else
4231 {
4242 }
4244 #ifdef USE_IX86_CLD
4245 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4248 #endif
4251 {
4256 }
4258 {
4262 }
4264 {
4265 #if defined(PROFILE_BEFORE_PROLOGUE)
4267 #else
4269 #endif
4270 }
4280 /* Enable 128-bit AVX instruction generation
4281 for the auto-vectorizer. */
4287 {
4294 {
4297 {
4299 q++;
4300 }
4301 else
4306 else
4307 {
4310 {
4313 }
4316 {
4320 }
4321 }
4326 else
4328 }
4329 }
4336 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4337 for 64-bit Bionic. */
4342 ? MASK_LONG_DOUBLE_128
4345 /* Only one of them can be active. */
4349 /* Save the initial options in case the user does function specific
4350 options. */
4352 target_option_default_node = target_option_current_node
4355 /* Handle stack protector */
4357 opts->x_ix86_stack_protector_guard
4360 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4362 {
4366 }
4369 {
4373 }
4374 }
4376 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4378 static void
4380 {
4382 struct register_pass_info insert_vzeroupper_info
4385 };
4390 /* This needs to be done at start up. It's convenient to do it here. */
4392 }
4394 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
4397 {
4401 }
4403 /* Update register usage after having seen the compiler flags. */
4405 static void
4407 {
4410 /* For 32-bit targets, squash the REX registers. */
4412 {
4419 }
4421 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4429 {
4430 /* Set/reset conditionally defined registers from
4431 CALL_USED_REGISTERS initializer. */
4435 /* Calculate registers of CLOBBERED_REGS register set
4436 as call used registers from GENERAL_REGS register set. */
4440 }
4442 /* If MMX is disabled, squash the registers. */
4448 /* If SSE is disabled, squash the registers. */
4454 /* If the FPU is disabled, squash the registers. */
4460 /* If AVX512F is disabled, squash the registers. */
4462 {
4468 }
4470 /* If MPX is disabled, squash the registers. */
4474 }
4476 \f
4477 /* Save the current options */
4479 static void
4482 {
4518 /* The fields are char but the variables are not; make sure the
4519 values fit in the fields. */
4524 }
4526 /* Restore the current options */
4528 static void
4531 {
4537 /* We don't change -fPIC. */
4575 /* TODO: ix86_cost should be chosen at instruction or function granuality
4576 so for cold code we use size_cost even in !optimize_size compilation. */
4579 else
4582 /* Recreate the arch feature tests if the arch changed */
4584 {
4589 }
4591 /* Recreate the tune optimization tests */
4594 }
4596 /* Adjust target options after streaming them in. This is mainly about
4597 reconciling them with global options. */
4599 static void
4601 {
4602 /* flag_pic is a global option, but ix86_cmodel is target saved option
4603 partly computed from flag_pic. If flag_pic is on, adjust x_ix86_cmodel
4604 for PIC, or error out. */
4607 {
4626 }
4627 else
4629 {
4644 }
4645 }
4647 /* Print the current options */
4649 static void
4652 {
4670 {
4673 }
4674 }
4676 \f
4677 /* Inner function to process the attribute((target(...))), take an argument and
4678 set the current options from the argument. If we have a list, recursively go
4679 over the list. */
4681 static bool
4686 {
4690 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4691 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4692 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4693 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4694 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4696 enum ix86_opt_type
4697 {
4698 ix86_opt_unknown,
4699 ix86_opt_yes,
4700 ix86_opt_no,
4701 ix86_opt_str,
4702 ix86_opt_enum,
4703 ix86_opt_isa
4704 };
4706 static const struct
4707 {
4714 /* isa options */
4768 /* enum options */
4771 /* string options */
4775 /* flag options */
4777 OPT_mcld,
4778 MASK_CLD),
4781 OPT_mfancy_math_387,
4782 MASK_NO_FANCY_MATH_387),
4785 OPT_mieee_fp,
4786 MASK_IEEE_FP),
4789 OPT_minline_all_stringops,
4790 MASK_INLINE_ALL_STRINGOPS),
4793 OPT_minline_stringops_dynamically,
4794 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4797 OPT_mno_align_stringops,
4798 MASK_NO_ALIGN_STRINGOPS),
4801 OPT_mrecip,
4802 MASK_RECIP),
4804 };
4806 /* If this is a list, recurse to get the options. */
4808 {
4815 enum_opts_set))
4819 }
4822 {
4825 }
4827 /* Handle multiple arguments separated by commas. */
4831 {
4845 {
4849 }
4850 else
4851 {
4854 }
4856 /* Recognize no-xxx. */
4858 {
4862 }
4863 else
4866 /* Find the option. */
4870 {
4878 {
4883 }
4884 }
4886 /* Process the option. */
4888 {
4891 }
4894 {
4900 }
4903 {
4909 else
4911 }
4914 {
4916 {
4919 }
4920 else
4922 }
4925 {
4933 global_dc);
4934 else
4935 {
4938 }
4939 }
4941 else
4943 }
4946 }
4948 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4950 tree
4954 {
4969 /* Process each of the options on the chain. */
4974 /* If the changed options are different from the default, rerun
4975 ix86_option_override_internal, and then save the options away.
4976 The string options are are attribute options, and will be undone
4977 when we copy the save structure. */
4983 {
4984 /* If we are using the default tune= or arch=, undo the string assigned,
4985 and use the default. */
4996 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
5001 {
5004 }
5006 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
5009 /* Add any builtin functions with the new isa if any. */
5012 /* Save the current options unless we are validating options for
5013 #pragma. */
5020 /* Free up memory allocated to hold the strings */
5023 }
5026 }
5028 /* Hook to validate attribute((target("string"))). */
5030 static bool
5033 tree args,
5035 {
5040 /* attribute((target("default"))) does nothing, beyond
5041 affecting multi-versioning. */
5050 /* Get the optimization options of the current function. */
5056 /* Init func_options. */
5064 /* Initialize func_options to the default before its target options can
5065 be set. */
5078 {
5083 }
5086 }
5088 \f
5089 /* Hook to determine if one function can safely inline another. */
5091 static bool
5093 {
5098 /* If callee has no option attributes, then it is ok to inline. */
5102 /* If caller has no option attributes, but callee does then it is not ok to
5103 inline. */
5107 else
5108 {
5112 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
5113 can inline a SSE2 function but a SSE2 function can't inline a SSE4
5114 function. */
5119 /* See if we have the same non-isa options. */
5123 /* See if arch, tune, etc. are the same. */
5136 else
5138 }
5141 }
5143 \f
5144 /* Remember the last target of ix86_set_current_function. */
5147 /* Set targets globals to the default (or current #pragma GCC target
5148 if active). Invalidate ix86_previous_fndecl cache. */
5150 void
5152 {
5159 else
5162 }
5164 /* Establish appropriate back-end context for processing the function
5165 FNDECL. The argument might be NULL to indicate processing at top
5166 level, outside of any function scope. */
5167 static void
5169 {
5170 /* Only change the context if the function changes. This hook is called
5171 several times in the course of compiling a function, and we don't want to
5172 slow things down too much or call target_reinit when it isn't safe. */
5176 tree old_tree;
5181 else
5185 {
5189 }
5196 {
5202 else
5204 }
5206 }
5208 \f
5209 /* Return true if this goes in large data/bss. */
5211 static bool
5213 {
5217 /* Functions are never large data. */
5221 /* Automatic variables are never large data. */
5226 {
5232 }
5233 else
5234 {
5237 /* If this is an incomplete type with size 0, then we can't put it
5238 in data because it might be too big when completed. Also,
5239 int_size_in_bytes returns -1 if size can vary or is larger than
5240 an integer in which case also it is safer to assume that it goes in
5241 large data. */
5244 }
5247 }
5249 /* Switch to the appropriate section for output of DECL.
5250 DECL is either a `VAR_DECL' node or a constant of some sort.
5251 RELOC indicates whether forming the initial value of DECL requires
5252 link-time relocations. */
5257 {
5259 {
5263 {
5297 /* We don't split these for medium model. Place them into
5298 default sections and hope for best. */
5300 }
5302 {
5303 /* We might get called with string constants, but get_named_section
5304 doesn't like them as they are not DECLs. Also, we need to set
5305 flags in that case. */
5309 }
5310 }
5312 }
5314 /* Select a set of attributes for section NAME based on the properties
5315 of DECL and whether or not RELOC indicates that DECL's initializer
5316 might contain runtime relocations. */
5318 static unsigned int ATTRIBUTE_UNUSED
5320 {
5334 }
5336 /* Build up a unique section name, expressed as a
5337 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5338 RELOC indicates whether the initial value of EXP requires
5339 link-time relocations. */
5341 static void ATTRIBUTE_UNUSED
5343 {
5345 {
5347 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5351 {
5375 /* We don't split these for medium model. Place them into
5376 default sections and hope for best. */
5378 }
5380 {
5387 /* If we're using one_only, then there needs to be a .gnu.linkonce
5388 prefix to the section name. */
5395 }
5396 }
5398 }
5400 #ifdef COMMON_ASM_OP
5401 /* This says how to output assembler code to declare an
5402 uninitialized external linkage data object.
5404 For medium model x86-64 we need to use .largecomm opcode for
5405 large objects. */
5406 void
5410 {
5414 else
5419 }
5420 #endif
5422 /* Utility function for targets to use in implementing
5423 ASM_OUTPUT_ALIGNED_BSS. */
5425 void
5428 {
5432 else
5435 #ifdef ASM_DECLARE_OBJECT_NAME
5438 #else
5439 /* Standard thing is just output label for the object. */
5443 }
5444 \f
5445 /* Decide whether we must probe the stack before any space allocation
5446 on this target. It's essentially TARGET_STACK_PROBE except when
5447 -fstack-check causes the stack to be already probed differently. */
5449 bool
5451 {
5452 /* Do not probe the stack twice if static stack checking is enabled. */
5457 }
5458 \f
5459 /* Decide whether we can make a sibling call to a function. DECL is the
5460 declaration of the function being targeted by the call and EXP is the
5461 CALL_EXPR representing the call. */
5463 static bool
5465 {
5469 /* If we are generating position-independent code, we cannot sibcall
5470 optimize direct calls to global functions, as the PLT requires
5471 %ebx be live. (Darwin does not have a PLT.) */
5473 && !TARGET_64BIT
5474 && flag_pic
5475 && flag_plt
5479 /* If we need to align the outgoing stack, then sibcalling would
5480 unalign the stack, which may break the called function. */
5486 {
5489 }
5490 else
5491 {
5492 /* We're looking at the CALL_EXPR, we need the type of the function. */
5497 }
5499 /* Check that the return value locations are the same. Like
5500 if we are returning floats on the 80387 register stack, we cannot
5501 make a sibcall from a function that doesn't return a float to a
5502 function that does or, conversely, from a function that does return
5503 a float to a function that doesn't; the necessary stack adjustment
5504 would not be executed. This is also the place we notice
5505 differences in the return value ABI. Note that it is ok for one
5506 of the functions to have void return type as long as the return
5507 value of the other is passed in a register. */
5512 {
5515 }
5517 ;
5522 {
5523 /* The SYSV ABI has more call-clobbered registers;
5524 disallow sibcalls from MS to SYSV. */
5528 }
5529 else
5530 {
5531 /* If this call is indirect, we'll need to be able to use a
5532 call-clobbered register for the address of the target function.
5533 Make sure that all such registers are not used for passing
5534 parameters. Note that DLLIMPORT functions are indirect. */
5537 {
5539 {
5540 /* ??? Need to count the actual number of registers to be used,
5541 not the possible number of registers. Fix later. */
5543 }
5544 }
5545 }
5547 /* Otherwise okay. That also includes certain types of indirect calls. */
5549 }
5551 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5552 and "sseregparm" calling convention attributes;
5553 arguments as in struct attribute_spec.handler. */
5555 static tree
5557 tree args,
5560 {
5565 {
5567 name);
5570 }
5572 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5574 {
5575 tree cst;
5578 {
5580 }
5583 {
5585 }
5589 {
5592 name);
5594 }
5596 {
5600 }
5603 }
5606 {
5607 /* Do not warn when emulating the MS ABI. */
5612 name);
5615 }
5617 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5619 {
5621 {
5623 }
5625 {
5627 }
5629 {
5631 }
5633 {
5635 }
5636 }
5638 /* Can combine stdcall with fastcall (redundant), regparm and
5639 sseregparm. */
5641 {
5643 {
5645 }
5647 {
5649 }
5651 {
5653 }
5654 }
5656 /* Can combine cdecl with regparm and sseregparm. */
5658 {
5660 {
5662 }
5664 {
5666 }
5668 {
5670 }
5671 }
5673 {
5676 name);
5678 {
5680 }
5682 {
5684 }
5686 {
5688 }
5689 }
5691 /* Can combine sseregparm with all attributes. */
5694 }
5696 /* The transactional memory builtins are implicitly regparm or fastcall
5697 depending on the ABI. Override the generic do-nothing attribute that
5698 these builtins were declared with, and replace it with one of the two
5699 attributes that we expect elsewhere. */
5701 static tree
5704 {
5705 tree alt;
5707 /* In no case do we want to add the placeholder attribute. */
5710 /* The 64-bit ABI is unchanged for transactional memory. */
5714 /* ??? Is there a better way to validate 32-bit windows? We have
5715 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5718 else
5719 {
5722 }
5726 }
5728 /* This function determines from TYPE the calling-convention. */
5730 unsigned int
5732 {
5735 tree attrs;
5742 {
5752 /* Regparam isn't allowed for thiscall and fastcall. */
5754 {
5759 }
5763 }
5770 || is_stdarg
5776 }
5778 /* Return 0 if the attributes for two types are incompatible, 1 if they
5779 are compatible, and 2 if they are nearly compatible (which causes a
5780 warning to be generated). */
5782 static int
5784 {
5800 }
5801 \f
5802 /* Return the regparm value for a function with the indicated TYPE and DECL.
5803 DECL may be NULL when calling function indirectly
5804 or considering a libcall. */
5806 static int
5808 {
5809 tree attr;
5820 {
5823 {
5826 }
5827 }
5833 /* Use register calling convention for local functions when possible. */
5836 {
5841 /* Caller and callee must agree on the calling convention, so
5842 checking here just optimize means that with
5843 __attribute__((optimize (...))) caller could use regparm convention
5844 and callee not, or vice versa. Instead look at whether the callee
5845 is optimized or not. */
5848 {
5851 {
5854 /* Make sure no regparm register is taken by a
5855 fixed register variable. */
5857 local_regparm++)
5861 /* We don't want to use regparm(3) for nested functions as
5862 these use a static chain pointer in the third argument. */
5866 /* Save a register for the split stack. */
5870 /* Each fixed register usage increases register pressure,
5871 so less registers should be used for argument passing.
5872 This functionality can be overriden by an explicit
5873 regparm value. */
5876 globals++;
5878 local_regparm
5883 }
5884 }
5885 }
5888 }
5890 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5891 DFmode (2) arguments in SSE registers for a function with the
5892 indicated TYPE and DECL. DECL may be NULL when calling function
5893 indirectly or considering a libcall. Return -1 if any FP parameter
5894 should be rejected by error. This is used in siutation we imply SSE
5895 calling convetion but the function is called from another function with
5896 SSE disabled. Otherwise return 0. */
5898 static int
5900 {
5903 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5904 by the sseregparm attribute. */
5907 {
5909 {
5911 {
5915 else
5918 }
5920 }
5923 }
5932 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5933 (and DFmode for SSE2) arguments in SSE registers. */
5935 /* TARGET_SSE_MATH */
5939 {
5942 {
5943 /* Refuse to produce wrong code when local function with SSE enabled
5944 is called from SSE disabled function.
5945 FIXME: We need a way to detect these cases cross-ltrans partition
5946 and avoid using SSE calling conventions on local functions called
5947 from function with SSE disabled. For now at least delay the
5948 warning until we know we are going to produce wrong code.
5949 See PR66047 */
5954 }
5955 }
5958 }
5960 /* Return true if EAX is live at the start of the function. Used by
5961 ix86_expand_prologue to determine if we need special help before
5962 calling allocate_stack_worker. */
5964 static bool
5966 {
5967 /* Cheat. Don't bother working forward from ix86_function_regparm
5968 to the function type to whether an actual argument is located in
5969 eax. Instead just look at cfg info, which is still close enough
5970 to correct at this point. This gives false positives for broken
5971 functions that might use uninitialized data that happens to be
5972 allocated in eax, but who cares? */
5974 }
5976 static bool
5978 {
5979 tree attr;
5982 {
5988 /* For 32-bit MS-ABI the default is to keep aggregate
5989 return pointer. */
5992 }
5994 }
5996 /* Value is the number of bytes of arguments automatically
5997 popped when returning from a subroutine call.
5998 FUNDECL is the declaration node of the function (as a tree),
5999 FUNTYPE is the data type of the function (as a tree),
6000 or for a library call it is an identifier node for the subroutine name.
6001 SIZE is the number of bytes of arguments passed on the stack.
6003 On the 80386, the RTD insn may be used to pop them if the number
6004 of args is fixed, but if the number is variable then the caller
6005 must pop them all. RTD can't be used for library calls now
6006 because the library is compiled with the Unix compiler.
6007 Use of RTD is a selectable option, since it is incompatible with
6008 standard Unix calling sequences. If the option is not selected,
6009 the caller must always pop the args.
6011 The attribute stdcall is equivalent to RTD on a per module basis. */
6013 static int
6015 {
6018 /* None of the 64-bit ABIs pop arguments. */
6029 /* Lose any fake structure return argument if it is passed on the stack. */
6032 {
6036 }
6039 }
6041 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
6043 static bool
6045 {
6046 /* Check operand constraints in case hard registers were propagated
6047 into insn pattern. This check prevents combine pass from
6048 generating insn patterns with invalid hard register operands.
6049 These invalid insns can eventually confuse reload to error out
6050 with a spill failure. See also PRs 46829 and 46843. */
6052 {
6061 {
6069 /* For pre-AVX disallow unaligned loads/stores where the
6070 instructions don't support it. */
6074 {
6078 }
6080 /* A unary operator may be accepted by the predicate, but it
6081 is irrelevant for matching constraints. */
6086 {
6094 }
6101 /* Operand has no constraints, anything is OK. */
6106 {
6111 && operands_match_p
6115 {
6118 }
6119 }
6123 }
6124 }
6127 }
6128 \f
6129 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
6131 static unsigned HOST_WIDE_INT
6133 {
6137 }
6138 \f
6139 /* Argument support functions. */
6141 /* Return true when register may be used to pass function parameters. */
6142 bool
6144 {
6153 {
6157 else
6163 }
6169 /* TODO: The function should depend on current function ABI but
6170 builtins.c would need updating then. Therefore we use the
6171 default ABI. */
6174 /* RAX is used as hidden argument to va_arg functions. */
6180 else
6188 }
6190 /* Return if we do not know how to pass TYPE solely in registers. */
6192 static bool
6194 {
6198 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
6199 The layout_type routine is crafty and tries to trick us into passing
6200 currently unsupported vector types on the stack by using TImode. */
6203 }
6205 /* It returns the size, in bytes, of the area reserved for arguments passed
6206 in registers for the function represented by fndecl dependent to the used
6207 abi format. */
6208 int
6210 {
6214 else
6219 }
6221 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
6222 call abi used. */
6223 enum calling_abi
6225 {
6227 {
6230 {
6232 {
6234 {
6237 {
6240 }
6241 }
6243 }
6244 }
6248 }
6250 }
6252 /* We add this as a workaround in order to use libc_has_function
6253 hook in i386.md. */
6254 bool
6256 {
6258 }
6260 static bool
6262 {
6264 {
6268 else
6270 }
6272 }
6274 static enum calling_abi
6276 {
6280 }
6282 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6283 call abi used. */
6284 enum calling_abi
6286 {
6290 }
6292 /* Write the extra assembler code needed to declare a function properly. */
6294 void
6296 tree decl)
6297 {
6301 {
6307 }
6309 #ifdef SUBTARGET_ASM_UNWIND_INIT
6311 #endif
6315 /* Output magic byte marker, if hot-patch attribute is set. */
6317 {
6319 {
6320 /* leaq [%rsp + 0], %rsp */
6323 }
6324 else
6325 {
6326 /* movl.s %edi, %edi
6327 push %ebp
6328 movl.s %esp, %ebp */
6331 }
6332 }
6333 }
6335 /* regclass.c */
6338 /* Implementation of call abi switching target hook. Specific to FNDECL
6339 the specific call register sets are set. See also
6340 ix86_conditional_register_usage for more details. */
6341 void
6343 {
6346 else
6348 }
6350 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6351 expensive re-initialization of init_regs each time we switch function context
6352 since this is needed only during RTL expansion. */
6353 static void
6355 {
6359 }
6361 /* Return 1 if pseudo register should be created and used to hold
6362 GOT address for PIC code. */
6363 bool
6365 {
6372 }
6374 /* Initialize large model PIC register. */
6376 static void
6378 {
6380 rtx tmp_reg;
6389 label));
6393 }
6395 /* Create and initialize PIC register if required. */
6396 static void
6398 {
6399 edge entry_edge;
6408 {
6411 else
6413 }
6414 else
6415 {
6416 /* If there is future mcount call in the function it is more profitable
6417 to emit SET_GOT into ABI defined REAL_PIC_OFFSET_TABLE_REGNUM. */
6426 }
6434 }
6436 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6437 for a call to a function whose data type is FNTYPE.
6438 For a library call, FNTYPE is 0. */
6440 void
6444 tree fndecl,
6446 {
6453 {
6456 {
6460 }
6461 else
6463 }
6464 else
6469 /* Set up the number of registers to use for passing arguments. */
6472 {
6474 ? X86_64_REGPARM_MAX
6476 }
6478 {
6481 {
6483 ? X86_64_SSE_REGPARM_MAX
6485 }
6486 }
6494 /* Because type might mismatch in between caller and callee, we need to
6495 use actual type of function for local calls.
6496 FIXME: cgraph_analyze can be told to actually record if function uses
6497 va_start so for local functions maybe_vaarg can be made aggressive
6498 helping K&R code.
6499 FIXME: once typesytem is fixed, we won't need this code anymore. */
6513 {
6514 /* If there are variable arguments, then we won't pass anything
6515 in registers in 32-bit mode. */
6517 {
6526 }
6528 /* Use ecx and edx registers if function has fastcall attribute,
6529 else look for regparm information. */
6531 {
6534 {
6537 }
6539 {
6542 }
6543 else
6545 }
6547 /* Set up the number of SSE registers used for passing SFmode
6548 and DFmode arguments. Warn for mismatching ABI. */
6550 }
6551 }
6553 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6554 But in the case of vector types, it is some vector mode.
6556 When we have only some of our vector isa extensions enabled, then there
6557 are some modes for which vector_mode_supported_p is false. For these
6558 modes, the generic vector support in gcc will choose some non-vector mode
6559 in order to implement the type. By computing the natural mode, we'll
6560 select the proper ABI location for the operand and not depend on whatever
6561 the middle-end decides to do with these vector types.
6563 The midde-end can't deal with the vector types > 16 bytes. In this
6564 case, we return the original mode and warn ABI change if CUM isn't
6565 NULL.
6567 If INT_RETURN is true, warn ABI change if the vector mode isn't
6568 available for function return value. */
6570 static machine_mode
6573 {
6577 {
6580 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6582 {
6587 else
6590 /* Get the mode which has this inner mode and number of units. */
6594 {
6596 {
6601 {
6605 }
6607 {
6611 }
6614 }
6616 {
6621 {
6625 }
6627 {
6631 }
6634 }
6637 {
6642 {
6646 }
6648 {
6652 }
6653 }
6655 {
6660 {
6664 }
6666 {
6670 }
6671 }
6673 }
6676 }
6677 }
6680 }
6682 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6683 this may not agree with the mode that the type system has chosen for the
6684 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6685 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6687 static rtx
6690 {
6691 rtx tmp;
6695 else
6696 {
6700 }
6703 }
6705 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6706 of this code is to classify each 8bytes of incoming argument by the register
6707 class and assign registers accordingly. */
6709 /* Return the union class of CLASS1 and CLASS2.
6710 See the x86-64 PS ABI for details. */
6712 static enum x86_64_reg_class
6714 {
6715 /* Rule #1: If both classes are equal, this is the resulting class. */
6719 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6720 the other class. */
6726 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6730 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6738 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6739 MEMORY is used. */
6748 /* Rule #6: Otherwise class SSE is used. */
6750 }
6752 /* Classify the argument of type TYPE and mode MODE.
6753 CLASSES will be filled by the register class used to pass each word
6754 of the operand. The number of words is returned. In case the parameter
6755 should be passed in memory, 0 is returned. As a special case for zero
6756 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6758 BIT_OFFSET is used internally for handling records and specifies offset
6759 of the offset in bits modulo 512 to avoid overflow cases.
6761 See the x86-64 PS ABI for details.
6762 */
6764 static int
6767 {
6768 HOST_WIDE_INT bytes =
6770 int words
6773 /* Variable sized entities are always passed/returned in memory. */
6782 {
6784 tree field;
6787 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6794 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6795 signalize memory class, so handle it as special case. */
6797 {
6800 }
6802 /* Classify each field of record and merge classes. */
6804 {
6806 /* And now merge the fields of structure. */
6808 {
6810 {
6816 /* Bitfields are always classified as integer. Handle them
6817 early, since later code would consider them to be
6818 misaligned integers. */
6820 {
6829 }
6830 else
6831 {
6836 /* Flexible array member is ignored. */
6843 {
6847 {
6850 "the ABI of passing struct with"
6851 " a flexible array member has"
6853 }
6855 }
6857 subclasses,
6867 }
6868 }
6869 }
6873 /* Arrays are handled as small records. */
6874 {
6881 /* The partial classes are now full classes. */
6892 }
6895 /* Unions are similar to RECORD_TYPE but offset is always 0.
6896 */
6898 {
6900 {
6908 bit_offset);
6913 }
6914 }
6919 }
6922 {
6923 /* When size > 16 bytes, if the first one isn't
6924 X86_64_SSE_CLASS or any other ones aren't
6925 X86_64_SSEUP_CLASS, everything should be passed in
6926 memory. */
6933 }
6935 /* Final merger cleanup. */
6937 {
6938 /* If one class is MEMORY, everything should be passed in
6939 memory. */
6943 /* The X86_64_SSEUP_CLASS should be always preceded by
6944 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6948 {
6949 /* The first one should never be X86_64_SSEUP_CLASS. */
6952 }
6954 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6955 everything should be passed in memory. */
6958 {
6961 /* The first one should never be X86_64_X87UP_CLASS. */
6964 {
6967 "the ABI of passing union with long double"
6969 }
6971 }
6972 }
6974 }
6976 /* Compute alignment needed. We align all types to natural boundaries with
6977 exception of XFmode that is aligned to 64bits. */
6979 {
6988 /* Misaligned fields are always returned in memory. */
6991 }
6993 /* for V1xx modes, just use the base mode */
6998 /* Classification of atomic types. */
7000 {
7016 {
7019 /* Analyze last 128 bits only. */
7023 {
7026 }
7028 {
7031 }
7033 {
7037 }
7039 {
7042 }
7043 else
7045 }
7052 /* OImode shouldn't be used directly. */
7059 else
7077 else
7078 {
7082 {
7085 "the ABI of passing structure with complex float"
7087 }
7090 }
7099 /* This modes is larger than 16 bytes. */
7157 else
7161 }
7162 }
7164 /* Examine the argument and return set number of register required in each
7165 class. Return true iff parameter should be passed in memory. */
7167 static bool
7170 {
7181 {
7202 }
7205 }
7207 /* Construct container for the argument used by GCC interface. See
7208 FUNCTION_ARG for the detailed description. */
7210 static rtx
7214 {
7215 /* The following variables hold the static issued_error state. */
7220 machine_mode tmpmode;
7229 rtx ret;
7240 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
7241 some less clueful developer tries to use floating-point anyway. */
7243 {
7245 {
7247 {
7250 }
7251 }
7253 {
7256 }
7258 }
7260 /* Likewise, error if the ABI requires us to return values in the
7261 x87 registers and the user specified -mno-80387. */
7267 {
7269 {
7272 }
7274 }
7276 /* First construct simple cases. Avoid SCmode, since we want to use
7277 single register to pass this type. */
7280 {
7295 /* Zero sized array, struct or class. */
7299 }
7338 /* Otherwise figure out the entries of the PARALLEL. */
7340 {
7344 {
7349 /* Merge TImodes on aligned occasions here too. */
7351 tmpmode
7355 else
7357 /* We've requested 24 bytes we
7358 don't have mode for. Use DImode. */
7365 intreg++;
7373 sse_regno++;
7381 sse_regno++;
7386 {
7392 {
7394 i++;
7395 }
7396 else
7421 }
7427 sse_regno++;
7431 }
7432 }
7434 /* Empty aligned struct, union or class. */
7442 }
7444 /* Update the data in CUM to advance over an argument of mode MODE
7445 and data type TYPE. (TYPE is null for libcalls where that information
7446 may not be available.)
7448 Return a number of integer regsiters advanced over. */
7450 static int
7453 HOST_WIDE_INT words)
7454 {
7459 {
7466 /* FALLTHRU */
7478 {
7481 }
7485 /* OImode shouldn't be used directly. */
7498 /* FALLTHRU */
7520 {
7525 {
7528 }
7529 }
7539 {
7544 {
7547 }
7548 }
7550 }
7552 {
7558 }
7561 }
7563 static int
7566 {
7569 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7576 {
7582 }
7583 else
7584 {
7589 }
7590 }
7592 static int
7594 HOST_WIDE_INT words)
7595 {
7596 /* Otherwise, this should be passed indirect. */
7601 {
7605 }
7607 }
7609 /* Update the data in CUM to advance over an argument of mode MODE and
7610 data type TYPE. (TYPE is null for libcalls where that information
7611 may not be available.) */
7613 static void
7616 {
7623 else
7632 {
7633 /* If we pass bounds in BT then just update remained bounds count. */
7635 {
7638 }
7640 /* Update remained number of bounds to force. */
7647 }
7649 /* The first arg not going to Bounds Tables resets this counter. */
7651 /* For unnamed args we always pass bounds to avoid bounds mess when
7652 passed and received types do not match. If bounds do not follow
7653 unnamed arg, still pretend required number of bounds were passed. */
7655 {
7658 }
7661 {
7666 else
7668 }
7669 else
7672 /* For stdarg we expect bounds to be passed for each value passed
7673 in register. */
7676 /* For pointers passed in memory we expect bounds passed in Bounds
7677 Table. */
7680 }
7682 /* Define where to put the arguments to a function.
7683 Value is zero to push the argument on the stack,
7684 or a hard register in which to store the argument.
7686 MODE is the argument's machine mode.
7687 TYPE is the data type of the argument (as a tree).
7688 This is null for libcalls where that information may
7689 not be available.
7690 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7691 the preceding args and about the function being called.
7692 NAMED is nonzero if this argument is a named parameter
7693 (otherwise it is an extra parameter matching an ellipsis). */
7695 static rtx
7699 {
7701 /* Avoid the AL settings for the Unix64 ABI. */
7706 {
7713 /* FALLTHRU */
7719 {
7722 /* Fastcall allocates the first two DWORD (SImode) or
7723 smaller arguments to ECX and EDX if it isn't an
7724 aggregate type . */
7726 {
7732 /* ECX not EAX is the first allocated register. */
7735 }
7737 }
7750 /* FALLTHRU */
7752 /* In 32bit, we pass TImode in xmm registers. */
7760 {
7764 }
7769 /* OImode and XImode shouldn't be used directly. */
7785 {
7789 }
7799 {
7803 }
7805 }
7807 {
7813 }
7816 }
7818 static rtx
7821 {
7822 /* Handle a hidden AL argument containing number of registers
7823 for varargs x86-64 functions. */
7827 ? X86_64_SSE_REGPARM_MAX
7832 {
7848 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7852 }
7858 }
7860 static rtx
7863 HOST_WIDE_INT bytes)
7864 {
7867 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7868 We use value of -2 to specify that current function call is MSABI. */
7872 /* If we've run out of registers, it goes on the stack. */
7878 /* Only floating point modes are passed in anything but integer regs. */
7880 {
7883 else
7884 {
7887 /* Unnamed floating parameters are passed in both the
7888 SSE and integer registers. */
7894 }
7895 }
7896 /* Handle aggregated types passed in register. */
7898 {
7903 }
7906 }
7908 /* Return where to put the arguments to a function.
7909 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7911 MODE is the argument's machine mode. TYPE is the data type of the
7912 argument. It is null for libcalls where that information may not be
7913 available. CUM gives information about the preceding args and about
7914 the function being called. NAMED is nonzero if this argument is a
7915 named parameter (otherwise it is an extra parameter matching an
7916 ellipsis). */
7918 static rtx
7921 {
7925 rtx arg;
7927 /* All pointer bounds argumntas are handled separately here. */
7930 {
7931 /* Return NULL if bounds are forced to go in Bounds Table. */
7934 /* Return the next available bound reg if any. */
7937 /* Return the next special slot number otherwise. */
7938 else
7942 }
7946 else
7950 /* To simplify the code below, represent vector types with a vector mode
7951 even if MMX/SSE are not active. */
7956 {
7961 else
7963 }
7964 else
7968 }
7970 /* A C expression that indicates when an argument must be passed by
7971 reference. If nonzero for an argument, a copy of that argument is
7972 made in memory and a pointer to the argument is passed instead of
7973 the argument itself. The pointer is passed in whatever way is
7974 appropriate for passing a pointer to that type. */
7976 static bool
7979 {
7982 /* Bounds are never passed by reference. */
7988 {
7991 /* See Windows x64 Software Convention. */
7993 {
7997 {
7998 /* Arrays are passed by reference. */
8003 {
8004 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
8005 are passed by reference. */
8007 }
8008 }
8010 /* __m128 is passed by reference. */
8012 }
8015 }
8018 }
8020 /* Return true when TYPE should be 128bit aligned for 32bit argument
8021 passing ABI. XXX: This function is obsolete and is only used for
8022 checking psABI compatibility with previous versions of GCC. */
8024 static bool
8026 {
8038 {
8039 /* Walk the aggregates recursively. */
8041 {
8045 {
8046 tree field;
8048 /* Walk all the structure fields. */
8050 {
8054 }
8056 }
8059 /* Just for use if some languages passes arrays by value. */
8066 }
8067 }
8069 }
8071 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
8072 XXX: This function is obsolete and is only used for checking psABI
8073 compatibility with previous versions of GCC. */
8075 static unsigned int
8078 {
8079 /* In 32bit, only _Decimal128 and __float128 are aligned to their
8080 natural boundaries. */
8082 {
8083 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
8084 make an exception for SSE modes since these require 128bit
8085 alignment.
8087 The handling here differs from field_alignment. ICC aligns MMX
8088 arguments to 4 byte boundaries, while structure fields are aligned
8089 to 8 byte boundaries. */
8091 {
8094 }
8095 else
8096 {
8099 }
8100 }
8104 }
8106 /* Return true when TYPE should be 128bit aligned for 32bit argument
8107 passing ABI. */
8109 static bool
8111 {
8121 {
8122 /* Walk the aggregates recursively. */
8124 {
8128 {
8129 tree field;
8131 /* Walk all the structure fields. */
8133 field;
8135 {
8139 }
8141 }
8144 /* Just for use if some languages passes arrays by value. */
8151 }
8152 }
8153 else
8157 }
8159 /* Gives the alignment boundary, in bits, of an argument with the
8160 specified mode and type. */
8162 static unsigned int
8164 {
8167 {
8168 /* Since the main variant type is used for call, we convert it to
8169 the main variant type. */
8172 }
8173 else
8177 else
8178 {
8183 {
8184 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
8186 {
8189 }
8195 }
8198 && !warned
8200 saved_align))
8201 {
8204 "The ABI for passing parameters with %d-byte"
8207 }
8208 }
8211 }
8213 /* Return true if N is a possible register number of function value. */
8215 static bool
8217 {
8219 {
8232 /* Complex values are returned in %st(0)/%st(1) pair. */
8235 /* TODO: The function should depend on current function ABI but
8236 builtins.c would need updating then. Therefore we use the
8237 default ABI. */
8242 /* Complex values are returned in %xmm0/%xmm1 pair. */
8251 }
8254 }
8256 /* Define how to find the value returned by a function.
8257 VALTYPE is the data type of the value (as a tree).
8258 If the precise function being called is known, FUNC is its FUNCTION_DECL;
8259 otherwise, FUNC is 0. */
8261 static rtx
8264 {
8267 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
8268 we normally prevent this case when mmx is not available. However
8269 some ABIs may require the result to be returned like DImode. */
8273 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
8274 we prevent this case when sse is not available. However some ABIs
8275 may require the result to be returned like integer TImode. */
8280 /* 32-byte vector modes in %ymm0. */
8284 /* 64-byte vector modes in %zmm0. */
8288 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
8291 else
8292 /* Most things go in %eax. */
8295 /* Override FP return register with %xmm0 for local functions when
8296 SSE math is enabled or for functions with sseregparm attribute. */
8298 {
8301 {
8306 }
8310 }
8312 /* OImode shouldn't be used directly. */
8316 }
8318 static rtx
8320 const_tree valtype)
8321 {
8322 rtx ret;
8324 /* Handle libcalls, which don't provide a type node. */
8326 {
8330 {
8349 }
8352 }
8354 {
8355 /* Pointers are always returned in word_mode. */
8357 }
8363 /* For zero sized structures, construct_container returns NULL, but we
8364 need to keep rest of compiler happy by returning meaningful value. */
8369 }
8371 static rtx
8373 const_tree valtype)
8374 {
8378 {
8380 {
8399 }
8400 }
8402 }
8404 static rtx
8407 {
8422 else
8424 }
8426 static rtx
8428 {
8434 }
8436 /* Return an RTX representing a place where a function returns
8437 or recieves pointer bounds or NULL if no bounds are returned.
8439 VALTYPE is a data type of a value returned by the function.
8441 FN_DECL_OR_TYPE is a tree node representing FUNCTION_DECL
8442 or FUNCTION_TYPE of the function.
8444 If OUTGOING is false, return a place in which the caller will
8445 see the return value. Otherwise, return a place where a
8446 function returns a value. */
8448 static rtx
8450 const_tree fntype_or_decl ATTRIBUTE_UNUSED,
8452 {
8458 {
8459 bitmap slots;
8461 bitmap_iterator bi;
8469 {
8474 }
8480 }
8481 else
8485 }
8487 /* Pointer function arguments and return values are promoted to
8488 word_mode. */
8490 static machine_mode
8494 {
8496 {
8499 }
8501 for_return);
8502 }
8504 /* Return true if a structure, union or array with MODE containing FIELD
8505 should be accessed using BLKmode. */
8507 static bool
8509 {
8510 /* Union with XFmode must be in BLKmode. */
8514 }
8516 rtx
8518 {
8520 }
8522 /* Return true iff type is returned in memory. */
8524 static bool
8526 {
8527 #ifdef SUBTARGET_RETURN_IN_MEMORY
8529 #else
8531 HOST_WIDE_INT size;
8537 {
8539 {
8542 /* __m128 is returned in xmm0. */
8551 /* Otherwise, the size must be exactly in [1248]. */
8553 }
8554 else
8555 {
8560 }
8561 }
8562 else
8563 {
8573 {
8574 /* User-created vectors small enough to fit in EAX. */
8578 /* Unless ABI prescibes otherwise,
8579 MMX/3dNow values are returned in MM0 if available. */
8584 /* SSE values are returned in XMM0 if available. */
8588 /* AVX values are returned in YMM0 if available. */
8592 /* AVX512F values are returned in ZMM0 if available. */
8595 }
8603 /* OImode shouldn't be used directly. */
8607 }
8608 #endif
8609 }
8611 \f
8612 /* Create the va_list data type. */
8614 /* Returns the calling convention specific va_list date type.
8615 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8617 static tree
8619 {
8622 /* For i386 we use plain pointer to argument area. */
8632 unsigned_type_node);
8635 unsigned_type_node);
8638 ptr_type_node);
8641 ptr_type_node);
8660 /* The correct type is an array type of one element. */
8662 }
8664 /* Setup the builtin va_list data type and for 64-bit the additional
8665 calling convention specific va_list data types. */
8667 static tree
8669 {
8672 /* Initialize abi specific va_list builtin types. */
8674 {
8675 tree t;
8677 {
8682 }
8683 else
8684 {
8689 }
8691 {
8696 }
8697 else
8698 {
8703 }
8704 }
8707 }
8709 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8711 static void
8713 {
8715 alias_set_type set;
8718 /* GPR size of varargs save area. */
8721 else
8724 /* FPR size of varargs save area. We don't need it if we don't pass
8725 anything in SSE registers. */
8728 else
8742 {
8750 }
8753 {
8754 machine_mode smode;
8756 rtx test;
8758 /* Now emit code to save SSE registers. The AX parameter contains number
8759 of SSE parameter registers used to call this function, though all we
8760 actually check here is the zero/non-zero status. */
8765 label));
8767 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8768 we used movdqa (i.e. TImode) instead? Perhaps even better would
8769 be if we could determine the real mode of the data, via a hook
8770 into pass_stdarg. Ignore all that for now. */
8780 {
8789 }
8792 }
8793 }
8795 static void
8797 {
8801 /* Reset to zero, as there might be a sysv vaarg used
8802 before. */
8807 {
8818 }
8819 }
8821 static void
8824 {
8826 CUMULATIVE_ARGS next_cum;
8827 tree fntype;
8829 /* This argument doesn't appear to be used anymore. Which is good,
8830 because the old code here didn't suppress rtl generation. */
8838 /* For varargs, we do not want to skip the dummy va_dcl argument.
8839 For stdargs, we do want to skip the last named argument. */
8847 else
8849 }
8851 static void
8854 tree type,
8857 {
8859 CUMULATIVE_ARGS next_cum;
8860 tree fntype;
8861 rtx save_area;
8866 /* Do nothing if we use plain pointer to argument area. */
8872 /* For varargs, we do not want to skip the dummy va_dcl argument.
8873 For stdargs, we do want to skip the last named argument. */
8887 {
8892 rtx bounds;
8896 else
8897 {
8898 rtx ldx_addr =
8905 }
8911 bnd_reg++;
8912 }
8913 }
8916 /* Checks if TYPE is of kind va_list char *. */
8918 static bool
8920 {
8921 tree canonic;
8923 /* For 32-bit it is always true. */
8929 }
8931 /* Implement va_start. */
8933 static void
8935 {
8939 tree type;
8940 rtx ovf_rtx;
8944 {
8947 /* When we are splitting the stack, we can't refer to the stack
8948 arguments using internal_arg_pointer, because they may be on
8949 the old stack. The split stack prologue will arrange to
8950 leave a pointer to the old stack arguments in a scratch
8951 register, which we here copy to a pseudo-register. The split
8952 stack prologue can't set the pseudo-register directly because
8953 it (the prologue) runs before any registers have been saved. */
8957 {
8958 rtx reg;
8972 }
8973 }
8975 /* Only 64bit target needs something special. */
8977 {
8980 else
8981 {
8991 /* Store zero bounds for va_list. */
8995 next));
8997 }
8999 }
9008 /* The following should be folded into the MEM_REF offset. */
9018 /* Count number of gp and fp argument registers used. */
9024 {
9030 }
9033 {
9039 }
9041 /* Find the overflow area. */
9045 else
9051 /* Store zero bounds for overflow area pointer. */
9060 {
9061 /* Find the register save area.
9062 Prologue of the function save it right above stack frame. */
9068 /* Store zero bounds for save area pointer. */
9075 }
9076 }
9078 /* Implement va_arg. */
9080 static tree
9083 {
9090 rtx container;
9092 tree ptrtype;
9093 machine_mode nat_mode;
9096 /* Only 64bit target needs something special. */
9120 {
9133 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
9135 {
9138 }
9146 }
9148 /* Pull the value out of the saved registers. */
9153 {
9167 /* In case we are passing structure, verify that it is consecutive block
9168 on the register save area. If not we need to do moves. */
9170 {
9171 /* Verify that all registers are strictly consecutive */
9173 {
9177 {
9182 }
9183 }
9184 else
9185 {
9189 {
9194 }
9195 }
9196 }
9198 {
9201 }
9202 else
9203 {
9206 }
9208 /* First ensure that we fit completely in registers. */
9210 {
9217 }
9219 {
9227 }
9229 /* Compute index to start of area used for integer regs. */
9231 {
9232 /* int_addr = gpr + sav; */
9235 }
9237 {
9238 /* sse_addr = fpr + sav; */
9241 }
9243 {
9247 /* addr = &temp; */
9252 {
9256 tree piece_type;
9257 tree addr_type;
9258 tree daddr_type;
9267 {
9272 }
9276 else
9283 {
9286 }
9287 else
9288 {
9291 }
9298 {
9303 }
9304 else
9305 {
9306 tree copy
9311 }
9313 }
9314 }
9317 {
9321 }
9324 {
9328 }
9333 }
9335 /* ... otherwise out of the overflow area. */
9337 /* When we align parameter on stack for caller, if the parameter
9338 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
9339 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
9340 here with caller. */
9345 /* Care for on-stack alignment if needed. */
9348 else
9349 {
9354 }
9371 }
9372 \f
9373 /* Return true if OPNUM's MEM should be matched
9374 in movabs* patterns. */
9376 bool
9378 {
9390 }
9391 \f
9392 /* Initialize the table of extra 80387 mathematical constants. */
9394 static void
9396 {
9398 {
9404 };
9408 {
9410 /* Ensure each constant is rounded to XFmode precision. */
9413 }
9416 }
9418 /* Return non-zero if the constant is something that
9419 can be loaded with a special instruction. */
9421 int
9423 {
9426 REAL_VALUE_TYPE r;
9438 /* For XFmode constants, try to find a special 80387 instruction when
9439 optimizing for size or on those CPUs that benefit from them. */
9442 {
9451 }
9453 /* Load of the constant -0.0 or -1.0 will be split as
9454 fldz;fchs or fld1;fchs sequence. */
9461 }
9463 /* Return the opcode of the special instruction to be used to load
9464 the constant X. */
9468 {
9470 {
9490 }
9491 }
9493 /* Return the CONST_DOUBLE representing the 80387 constant that is
9494 loaded by the specified special instruction. The argument IDX
9495 matches the return value from standard_80387_constant_p. */
9497 rtx
9499 {
9506 {
9517 }
9520 XFmode);
9521 }
9523 /* Return 1 if X is all 0s and 2 if x is all 1s
9524 in supported SSE/AVX vector mode. */
9526 int
9528 {
9529 machine_mode mode;
9540 {
9561 }
9564 }
9566 /* Return the opcode of the special instruction to be used to load
9567 the constant X. */
9571 {
9573 {
9576 {
9603 }
9613 else
9618 }
9620 }
9622 /* Returns true if OP contains a symbol reference */
9624 bool
9626 {
9635 {
9637 {
9643 }
9647 }
9650 }
9652 /* Return true if it is appropriate to emit `ret' instructions in the
9653 body of a function. Do this only if the epilogue is simple, needing a
9654 couple of insns. Prior to reloading, we can't tell how many registers
9655 must be saved, so return false then. Return false if there is no frame
9656 marker to de-allocate. */
9658 bool
9660 {
9666 /* Don't allow more than 32k pop, since that's all we can do
9667 with one instruction. */
9674 }
9675 \f
9676 /* Value should be nonzero if functions must have frame pointers.
9677 Zero means the frame pointer need not be set up (and parms may
9678 be accessed via the stack pointer) in functions that seem suitable. */
9680 static bool
9682 {
9683 /* If we accessed previous frames, then the generated code expects
9684 to be able to access the saved ebp value in our frame. */
9688 /* Several x86 os'es need a frame pointer for other reasons,
9689 usually pertaining to setjmp. */
9693 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9697 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9698 allocation is 4GB. */
9702 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9703 turns off the frame pointer by default. Turn it back on now if
9704 we've not got a leaf function. */
9714 }
9716 /* Record that the current function accesses previous call frames. */
9718 void
9720 {
9722 }
9723 \f
9724 #ifndef USE_HIDDEN_LINKONCE
9725 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9726 # define USE_HIDDEN_LINKONCE 1
9727 # else
9728 # define USE_HIDDEN_LINKONCE 0
9729 # endif
9730 #endif
9734 /* Fills in the label name that should be used for a pc thunk for
9735 the given register. */
9737 static void
9739 {
9744 else
9746 }
9749 /* This function generates code for -fpic that loads %ebx with
9750 the return address of the caller and then returns. */
9752 static void
9754 {
9759 {
9761 tree decl;
9777 #if TARGET_MACHO
9779 {
9788 }
9789 else
9790 #endif
9792 {
9803 }
9804 else
9805 {
9808 }
9814 /* Make sure unwind info is emitted for the thunk if needed. */
9817 /* Pad stack IP move with 4 instructions (two NOPs count
9818 as one instruction). */
9820 {
9825 }
9836 }
9840 }
9842 /* Emit code for the SET_GOT patterns. */
9846 {
9852 {
9853 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9858 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9859 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9860 an unadorned address. */
9865 }
9870 {
9872 /* We don't need a pic base, we're not producing pic. */
9879 }
9880 else
9881 {
9890 #if TARGET_MACHO
9891 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9892 This is what will be referenced by the Mach-O PIC subsystem. */
9896 /* When we are restoring the pic base at the site of a nonlocal label,
9897 and we decided to emit the pic base above, we will still output a
9898 local label used for calculating the correction offset (even though
9899 the offset will be 0 in that case). */
9903 #endif
9904 }
9910 }
9912 /* Generate an "push" pattern for input ARG. */
9914 static rtx
9916 {
9928 stack_pointer_rtx)),
9929 arg);
9930 }
9932 /* Generate an "pop" pattern for input ARG. */
9934 static rtx
9936 {
9943 stack_pointer_rtx)));
9944 }
9946 /* Return >= 0 if there is an unused call-clobbered register available
9947 for the entire function. */
9949 static unsigned int
9951 {
9958 {
9960 /* Can't use the same register for both PIC and DRAP. */
9963 else
9968 }
9971 }
9973 /* Return TRUE if we need to save REGNO. */
9975 static bool
9977 {
9980 {
9982 {
9983 /* REAL_PIC_OFFSET_TABLE_REGNUM used by call to
9984 _mcount in prologue. */
9987 }
9994 }
9997 {
10000 {
10006 }
10007 }
10018 }
10020 /* Return number of saved general prupose registers. */
10022 static int
10024 {
10030 nregs ++;
10032 }
10034 /* Return number of saved SSE registrers. */
10036 static int
10038 {
10046 nregs ++;
10048 }
10050 /* Given FROM and TO register numbers, say whether this elimination is
10051 allowed. If stack alignment is needed, we can only replace argument
10052 pointer with hard frame pointer, or replace frame pointer with stack
10053 pointer. Otherwise, frame pointer elimination is automatically
10054 handled and all other eliminations are valid. */
10056 static bool
10058 {
10064 else
10066 }
10068 /* Return the offset between two registers, one to be eliminated, and the other
10069 its replacement, at the start of a routine. */
10071 HOST_WIDE_INT
10073 {
10082 else
10083 {
10091 }
10092 }
10094 /* In a dynamically-aligned function, we can't know the offset from
10095 stack pointer to frame pointer, so we must ensure that setjmp
10096 eliminates fp against the hard fp (%ebp) rather than trying to
10097 index from %esp up to the top of the frame across a gap that is
10098 of unknown (at compile-time) size. */
10099 static rtx
10101 {
10103 }
10105 /* When using -fsplit-stack, the allocation routines set a field in
10106 the TCB to the bottom of the stack plus this much space, measured
10107 in bytes. */
10109 #define SPLIT_STACK_AVAILABLE 256
10111 /* Fill structure ix86_frame about frame of currently computed function. */
10113 static void
10115 {
10117 HOST_WIDE_INT offset;
10120 HOST_WIDE_INT to_allocate;
10125 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
10126 function prologues and leaf. */
10130 {
10133 }
10134 /* preferred_stack_boundary is never updated for call
10135 expanded from tls descriptor. Update it here. We don't update it in
10136 expand stage because according to the comments before
10137 ix86_current_function_calls_tls_descriptor, tls calls may be optimized
10138 away. */
10141 {
10145 }
10154 /* For SEH we have to limit the amount of code movement into the prologue.
10155 At present we do this via a BLOCKAGE, at which point there's very little
10156 scheduling that can be done, which means that there's very little point
10157 in doing anything except PUSHs. */
10161 /* During reload iteration the amount of registers saved can change.
10162 Recompute the value as needed. Do not recompute when amount of registers
10163 didn't change as reload does multiple calls to the function and does not
10164 expect the decision to change within single iteration. */
10167 {
10173 /* The fast prologue uses move instead of push to save registers. This
10174 is significantly longer, but also executes faster as modern hardware
10175 can execute the moves in parallel, but can't do that for push/pop.
10177 Be careful about choosing what prologue to emit: When function takes
10178 many instructions to execute we may use slow version as well as in
10179 case function is known to be outside hot spot (this is known with
10180 feedback only). Weight the size of function by number of registers
10181 to save as it is cheap to use one or two push instructions but very
10182 slow to use many of them. */
10186 || (flag_branch_probabilities
10189 else
10192 }
10194 frame->save_regs_using_mov
10196 /* If static stack checking is enabled and done with probes,
10197 the registers need to be saved before allocating the frame. */
10200 /* Skip return address. */
10203 /* Skip pushed static chain. */
10207 /* Skip saved base pointer. */
10212 /* The traditional frame pointer location is at the top of the frame. */
10215 /* Register save area */
10219 /* On SEH target, registers are pushed just before the frame pointer
10220 location. */
10224 /* Align and set SSE register save area. */
10226 {
10227 /* The only ABI that has saved SSE registers (Win64) also has a
10228 16-byte aligned default stack, and thus we don't need to be
10229 within the re-aligned local stack frame to save them. */
10233 }
10236 /* The re-aligned stack starts here. Values before this point are not
10237 directly comparable with values below this point. In order to make
10238 sure that no value happens to be the same before and after, force
10239 the alignment computation below to add a non-zero value. */
10243 /* Va-arg area */
10247 /* Align start of frame for local function. */
10256 /* Frame pointer points here. */
10261 /* Add outgoing arguments area. Can be skipped if we eliminated
10262 all the function calls as dead code.
10263 Skipping is however impossible when function calls alloca. Alloca
10264 expander assumes that last crtl->outgoing_args_size
10265 of stack frame are unused. */
10269 {
10272 }
10273 else
10276 /* Align stack boundary. Only needed if we're calling another function
10277 or using alloca. */
10282 /* We've reached end of stack frame. */
10285 /* Size prologue needs to allocate. */
10296 {
10302 }
10303 else
10307 /* The SEH frame pointer location is near the bottom of the frame.
10308 This is enforced by the fact that the difference between the
10309 stack pointer and the frame pointer is limited to 240 bytes in
10310 the unwind data structure. */
10312 {
10313 HOST_WIDE_INT diff;
10315 /* If we can leave the frame pointer where it is, do so. Also, returns
10316 the establisher frame for __builtin_frame_address (0). */
10321 {
10322 /* Ideally we'd determine what portion of the local stack frame
10323 (within the constraint of the lowest 240) is most heavily used.
10324 But without that complication, simply bias the frame pointer
10325 by 128 bytes so as to maximize the amount of the local stack
10326 frame that is addressable with 8-bit offsets. */
10328 }
10329 }
10330 }
10332 /* This is semi-inlined memory_address_length, but simplified
10333 since we know that we're always dealing with reg+offset, and
10334 to avoid having to create and discard all that rtl. */
10338 {
10342 {
10343 /* EBP and R13 cannot be encoded without an offset. */
10345 }
10349 /* ESP and R12 must be encoded with a SIB byte. */
10351 len++;
10354 }
10356 /* Return an RTX that points to CFA_OFFSET within the stack frame.
10357 The valid base registers are taken from CFUN->MACHINE->FS. */
10359 static rtx
10361 {
10367 {
10368 /* Choose the base register most likely to allow the most scheduling
10369 opportunities. Generally FP is valid throughout the function,
10370 while DRAP must be reloaded within the epilogue. But choose either
10371 over the SP due to increased encoding size. */
10374 {
10377 }
10379 {
10382 }
10384 {
10387 }
10388 }
10389 else
10390 {
10391 HOST_WIDE_INT toffset;
10394 /* Choose the base register with the smallest address encoding.
10395 With a tie, choose FP > DRAP > SP. */
10397 {
10401 }
10403 {
10407 {
10411 }
10412 }
10414 {
10418 {
10422 }
10423 }
10424 }
10428 }
10430 /* Emit code to save registers in the prologue. */
10432 static void
10434 {
10440 {
10443 }
10444 }
10446 /* Emit a single register save at CFA - CFA_OFFSET. */
10448 static void
10450 HOST_WIDE_INT cfa_offset)
10451 {
10459 /* For SSE saves, we need to indicate the 128-bit alignment. */
10470 /* When saving registers into a re-aligned local stack frame, avoid
10471 any tricky guessing by dwarf2out. */
10473 {
10477 {
10478 /* A bit of a hack. We force the DRAP register to be saved in
10479 the re-aligned stack frame, which provides us with a copy
10480 of the CFA that will last past the prologue. Install it. */
10486 }
10487 else
10488 {
10489 /* The frame pointer is a stable reference within the
10490 aligned frame. Use it. */
10496 }
10497 }
10499 /* The memory may not be relative to the current CFA register,
10500 which means that we may need to generate a new pattern for
10501 use by the unwind info. */
10503 {
10508 }
10509 }
10511 /* Emit code to save registers using MOV insns.
10512 First register is stored at CFA - CFA_OFFSET. */
10513 static void
10515 {
10520 {
10523 }
10524 }
10526 /* Emit code to save SSE registers using MOV insns.
10527 First register is stored at CFA - CFA_OFFSET. */
10528 static void
10530 {
10535 {
10538 }
10539 }
10543 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
10544 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
10545 Don't add the note if the previously saved value will be left untouched
10546 within stack red-zone till return, as unwinders can find the same value
10547 in the register and on the stack. */
10549 static void
10551 {
10557 {
10560 }
10561 else
10562 queued_cfa_restores
10564 }
10566 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
10568 static void
10570 {
10571 rtx last;
10575 ;
10580 }
10582 /* Expand prologue or epilogue stack adjustment.
10583 The pattern exist to put a dependency on all ebp-based memory accesses.
10584 STYLE should be negative if instructions should be marked as frame related,
10585 zero if %r11 register is live and cannot be freely used and positive
10586 otherwise. */
10588 static void
10591 {
10593 rtx insn;
10600 else
10601 {
10602 rtx tmp;
10603 /* r11 is used by indirect sibcall return as well, set before the
10604 epilogue and used after the epilogue. */
10607 else
10608 {
10612 }
10618 }
10625 {
10626 rtx r;
10636 }
10638 {
10641 {
10645 }
10646 }
10649 {
10654 {
10657 }
10659 {
10662 }
10663 else
10664 {
10665 /* Else there are two possibilities: SP itself, which we set
10666 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10667 taken care of this by hand along the eh_return path. */
10670 }
10674 }
10675 }
10677 /* Find an available register to be used as dynamic realign argument
10678 pointer regsiter. Such a register will be written in prologue and
10679 used in begin of body, so it must not be
10680 1. parameter passing register.
10681 2. GOT pointer.
10682 We reuse static-chain register if it is available. Otherwise, we
10683 use DI for i386 and R13 for x86-64. We chose R13 since it has
10684 shorter encoding.
10686 Return: the regno of chosen register. */
10688 static unsigned int
10690 {
10694 {
10695 /* Use R13 for nested function or function need static chain.
10696 Since function with tail call may use any caller-saved
10697 registers in epilogue, DRAP must not use caller-saved
10698 register in such case. */
10703 }
10704 else
10705 {
10706 /* Use DI for nested function or function need static chain.
10707 Since function with tail call may use any caller-saved
10708 registers in epilogue, DRAP must not use caller-saved
10709 register in such case. */
10713 /* Reuse static chain register if it isn't used for parameter
10714 passing. */
10716 {
10720 }
10722 }
10723 }
10725 /* Return minimum incoming stack alignment. */
10727 static unsigned int
10729 {
10732 /* Prefer the one specified at command line. */
10735 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10736 if -mstackrealign is used, it isn't used for sibcall check and
10737 estimated stack alignment is 128bit. */
10739 && !TARGET_64BIT
10740 && ix86_force_align_arg_pointer
10743 else
10746 /* Incoming stack alignment can be changed on individual functions
10747 via force_align_arg_pointer attribute. We use the smallest
10748 incoming stack boundary. */
10754 /* The incoming stack frame has to be aligned at least at
10755 parm_stack_boundary. */
10759 /* Stack at entrance of main is aligned by runtime. We use the
10760 smallest incoming stack boundary. */
10768 }
10770 /* Update incoming stack boundary and estimated stack alignment. */
10772 static void
10774 {
10775 ix86_incoming_stack_boundary
10778 /* x86_64 vararg needs 16byte stack alignment for register save
10779 area. */
10784 }
10786 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10787 needed or an rtx for DRAP otherwise. */
10789 static rtx
10791 {
10796 {
10797 /* Assign DRAP to vDRAP and returns vDRAP */
10799 rtx drap_vreg;
10800 rtx arg_ptr;
10813 {
10816 }
10818 }
10819 else
10821 }
10823 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10825 static rtx
10827 {
10829 }
10832 rtx reg;
10834 };
10836 /* Return a short-lived scratch register for use on function entry.
10837 In 32-bit mode, it is valid only after the registers are saved
10838 in the prologue. This register must be released by means of
10839 release_scratch_register_on_entry once it is dead. */
10841 static void
10843 {
10849 {
10850 /* We always use R11 in 64-bit mode. */
10852 }
10853 else
10854 {
10856 bool fastcall_p
10858 bool thiscall_p
10862 int drap_regno
10865 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10866 for the static chain register. */
10870 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10871 for the static chain register. */
10876 /* ecx is the static chain register. */
10878 && !static_chain_p
10883 /* esi is the static chain register. */
10889 else
10890 {
10893 }
10894 }
10898 {
10901 }
10902 }
10904 /* Release a scratch register obtained from the preceding function. */
10906 static void
10908 {
10910 {
10914 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10920 }
10921 }
10923 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10925 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10927 static void
10929 {
10930 /* We skip the probe for the first interval + a small dope of 4 words and
10931 probe that many bytes past the specified size to maintain a protection
10932 area at the botton of the stack. */
10936 /* See if we have a constant small number of probes to generate. If so,
10937 that's the easy case. The run-time loop is made up of 11 insns in the
10938 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10939 for n # of intervals. */
10941 {
10945 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10946 values of N from 1 until it exceeds SIZE. If only one probe is
10947 needed, this will not generate any code. Then adjust and probe
10948 to PROBE_INTERVAL + SIZE. */
10950 {
10952 {
10955 }
10956 else
10963 }
10967 else
10975 /* Adjust back to account for the additional first interval. */
10979 }
10981 /* Otherwise, do the same as above, but in a loop. Note that we must be
10982 extra careful with variables wrapping around because we might be at
10983 the very top (or the very bottom) of the address space and we have
10984 to be able to handle this case properly; in particular, we use an
10985 equality test for the loop condition. */
10986 else
10987 {
10988 HOST_WIDE_INT rounded_size;
10994 /* Step 1: round SIZE to the previous multiple of the interval. */
10999 /* Step 2: compute initial and final value of the loop counter. */
11001 /* SP = SP_0 + PROBE_INTERVAL. */
11006 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
11010 stack_pointer_rtx)));
11013 /* Step 3: the loop
11015 while (SP != LAST_ADDR)
11016 {
11017 SP = SP + PROBE_INTERVAL
11018 probe at SP
11019 }
11021 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
11022 values of N from 1 until it is equal to ROUNDED_SIZE. */
11027 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
11028 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
11031 {
11036 }
11038 /* Adjust back to account for the additional first interval. */
11044 }
11048 /* Even if the stack pointer isn't the CFA register, we need to correctly
11049 describe the adjustments made to it, in particular differentiate the
11050 frame-related ones from the frame-unrelated ones. */
11052 {
11065 }
11067 /* Make sure nothing is scheduled before we are done. */
11069 }
11071 /* Adjust the stack pointer up to REG while probing it. */
11075 {
11085 /* Jump to END_LAB if SP == LAST_ADDR. */
11093 /* SP = SP + PROBE_INTERVAL. */
11097 /* Probe at SP. */
11108 }
11110 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
11111 inclusive. These are offsets from the current stack pointer. */
11113 static void
11115 {
11116 /* See if we have a constant small number of probes to generate. If so,
11117 that's the easy case. The run-time loop is made up of 7 insns in the
11118 generic case while the compile-time loop is made up of n insns for n #
11119 of intervals. */
11121 {
11122 HOST_WIDE_INT i;
11124 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
11125 it exceeds SIZE. If only one probe is needed, this will not
11126 generate any code. Then probe at FIRST + SIZE. */
11133 }
11135 /* Otherwise, do the same as above, but in a loop. Note that we must be
11136 extra careful with variables wrapping around because we might be at
11137 the very top (or the very bottom) of the address space and we have
11138 to be able to handle this case properly; in particular, we use an
11139 equality test for the loop condition. */
11140 else
11141 {
11148 /* Step 1: round SIZE to the previous multiple of the interval. */
11153 /* Step 2: compute initial and final value of the loop counter. */
11155 /* TEST_OFFSET = FIRST. */
11158 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
11162 /* Step 3: the loop
11164 while (TEST_ADDR != LAST_ADDR)
11165 {
11166 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11167 probe at TEST_ADDR
11168 }
11170 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11171 until it is equal to ROUNDED_SIZE. */
11176 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11177 that SIZE is equal to ROUNDED_SIZE. */
11182 stack_pointer_rtx,
11187 }
11189 /* Make sure nothing is scheduled before we are done. */
11191 }
11193 /* Probe a range of stack addresses from REG to END, inclusive. These are
11194 offsets from the current stack pointer. */
11198 {
11208 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11216 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11220 /* Probe at TEST_ADDR. */
11233 }
11235 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
11236 to be generated in correct form. */
11237 static void
11239 {
11240 /* Check if stack realign is really needed after reload, and
11241 stores result in cfun */
11242 unsigned int incoming_stack_boundary
11251 {
11252 /* After stack_realign_needed is finalized, we can't no longer
11253 change it. */
11256 }
11258 /* If the only reason for frame_pointer_needed is that we conservatively
11259 assumed stack realignment might be needed, but in the end nothing that
11260 needed the stack alignment had been spilled, clear frame_pointer_needed
11261 and say we don't need stack realignment. */
11263 && frame_pointer_needed
11265 && flag_omit_frame_pointer
11267 && !ix86_current_function_calls_tls_descriptor
11276 {
11278 basic_block bb;
11285 HARD_FRAME_POINTER_REGNUM);
11287 {
11292 set_up_by_prologue))
11293 {
11297 }
11298 }
11300 /* If drap has been set, but it actually isn't live at the start
11301 of the function, there is no reason to set it up. */
11303 {
11306 {
11309 }
11310 }
11311 else
11326 }
11330 }
11332 /* Delete SET_GOT right after entry block if it is allocated to reg. */
11334 static void
11336 {
11342 {
11345 {
11351 }
11352 }
11353 }
11355 /* Expand the prologue into a bunch of separate insns. */
11357 void
11359 {
11363 HOST_WIDE_INT allocate;
11369 /* DRAP should not coexist with stack_realign_fp */
11374 /* Initialize CFA state for before the prologue. */
11378 /* Track SP offset to the CFA. We continue tracking this after we've
11379 swapped the CFA register away from SP. In the case of re-alignment
11380 this is fudged; we're interested to offsets within the local frame. */
11387 {
11388 /* We should have already generated an error for any use of
11389 ms_hook on a nested function. */
11392 /* Check if profiling is active and we shall use profiling before
11393 prologue variant. If so sorry. */
11398 /* In ix86_asm_output_function_label we emitted:
11399 8b ff movl.s %edi,%edi
11400 55 push %ebp
11401 8b ec movl.s %esp,%ebp
11403 This matches the hookable function prologue in Win32 API
11404 functions in Microsoft Windows XP Service Pack 2 and newer.
11405 Wine uses this to enable Windows apps to hook the Win32 API
11406 functions provided by Wine.
11408 What that means is that we've already set up the frame pointer. */
11412 {
11415 /* We've decided to use the frame pointer already set up.
11416 Describe this to the unwinder by pretending that both
11417 push and mov insns happen right here.
11419 Putting the unwind info here at the end of the ms_hook
11420 is done so that we can make absolutely certain we get
11421 the required byte sequence at the start of the function,
11422 rather than relying on an assembler that can produce
11423 the exact encoding required.
11425 However it does mean (in the unpatched case) that we have
11426 a 1 insn window where the asynchronous unwind info is
11427 incorrect. However, if we placed the unwind info at
11428 its correct location we would have incorrect unwind info
11429 in the patched case. Which is probably all moot since
11430 I don't expect Wine generates dwarf2 unwind info for the
11431 system libraries that use this feature. */
11437 stack_pointer_rtx);
11445 /* Note that gen_push incremented m->fs.cfa_offset, even
11446 though we didn't emit the push insn here. */
11450 }
11451 else
11452 {
11453 /* The frame pointer is not needed so pop %ebp again.
11454 This leaves us with a pristine state. */
11456 }
11457 }
11459 /* The first insn of a function that accepts its static chain on the
11460 stack is to push the register that would be filled in by a direct
11461 call. This insn will be skipped by the trampoline. */
11463 {
11467 /* We don't want to interpret this push insn as a register save,
11468 only as a stack adjustment. The real copy of the register as
11469 a save will be done later, if needed. */
11474 }
11476 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
11477 of DRAP is needed and stack realignment is really needed after reload */
11479 {
11482 /* Only need to push parameter pointer reg if it is caller saved. */
11484 {
11485 /* Push arg pointer reg */
11488 }
11490 /* Grab the argument pointer. */
11497 /* Align the stack. */
11499 stack_pointer_rtx,
11503 /* Replicate the return address on the stack so that return
11504 address can be reached via (argp - 1) slot. This is needed
11505 to implement macro RETURN_ADDR_RTX and intrinsic function
11506 expand_builtin_return_addr etc. */
11512 /* For the purposes of frame and register save area addressing,
11513 we've started over with a new frame. */
11516 }
11522 {
11523 /* Note: AT&T enter does NOT have reversed args. Enter is probably
11524 slower on all targets. Also sdb doesn't like it. */
11528 /* Push registers now, before setting the frame pointer
11529 on SEH target. */
11531 && TARGET_SEH
11533 {
11537 }
11540 {
11548 }
11549 }
11552 {
11553 /* If saving registers via PUSH, do so now. */
11555 {
11559 }
11561 /* When using red zone we may start register saving before allocating
11562 the stack frame saving one cycle of the prologue. However, avoid
11563 doing this if we have to probe the stack; at least on x86_64 the
11564 stack probe can turn into a call that clobbers a red zone location. */
11566 && (! TARGET_STACK_PROBE
11568 {
11571 }
11572 }
11575 {
11579 /* The computation of the size of the re-aligned stack frame means
11580 that we must allocate the size of the register save area before
11581 performing the actual alignment. Otherwise we cannot guarantee
11582 that there's enough storage above the realignment point. */
11589 /* Align the stack. */
11591 stack_pointer_rtx,
11594 /* For the purposes of register save area addressing, the stack
11595 pointer is no longer valid. As for the value of sp_offset,
11596 see ix86_compute_frame_layout, which we need to match in order
11597 to pass verification of stack_pointer_offset at the end. */
11600 }
11605 {
11606 /* We start to count from ARG_POINTER. */
11609 /* If it was realigned, take into account the fake frame. */
11611 {
11618 /* This over-estimates by 1 minimal-stack-alignment-unit but
11619 mitigates that by counting in the new return address slot. */
11620 current_function_dynamic_stack_size
11622 }
11625 }
11627 /* On SEH target with very large frame size, allocate an area to save
11628 SSE registers (as the very large allocation won't be described). */
11632 {
11633 HOST_WIDE_INT sse_size =
11638 /* No need to do stack checking as the area will be immediately
11639 written. */
11646 }
11648 /* The stack has already been decremented by the instruction calling us
11649 so probe if the size is non-negative to preserve the protection area. */
11651 {
11652 /* We expect the registers to be saved when probes are used. */
11656 {
11659 {
11662 }
11663 }
11664 else
11665 {
11672 {
11674 {
11677 }
11678 else
11680 }
11681 else
11682 {
11684 {
11688 }
11689 else
11691 }
11692 }
11693 }
11696 ;
11699 {
11703 }
11704 else
11705 {
11717 {
11720 /* Note that SEH directives need to continue tracking the stack
11721 pointer even after the frame pointer has been set up. */
11723 {
11731 }
11732 }
11735 {
11740 {
11748 }
11749 }
11754 /* Use the fact that AX still contains ALLOCATE. */
11756 ? gen_pro_epilogue_adjust_stack_di_sub
11763 {
11771 }
11774 /* Use stack_pointer_rtx for relative addressing so that code
11775 works for realigned stack, too. */
11777 {
11784 }
11786 {
11791 }
11792 }
11795 /* If we havn't already set up the frame pointer, do so now. */
11797 {
11809 }
11816 /* For the mcount profiling on 32 bit PIC mode we need to emit SET_GOT
11817 in PROLOGUE. */
11819 {
11825 /* Deleting already emmitted SET_GOT if exist and allocated to
11826 REAL_PIC_OFFSET_TABLE_REGNUM. */
11828 }
11831 {
11832 /* vDRAP is setup but after reload it turns out stack realign
11833 isn't necessary, here we will emit prologue to setup DRAP
11834 without stack realign adjustment */
11837 }
11839 /* Prevent instructions from being scheduled into register save push
11840 sequence when access to the redzone area is done through frame pointer.
11841 The offset between the frame pointer and the stack pointer is calculated
11842 relative to the value of the stack pointer at the end of the function
11843 prologue, and moving instructions that access redzone area via frame
11844 pointer inside push sequence violates this assumption. */
11848 /* Emit cld instruction if stringops are used in the function. */
11852 /* SEH requires that the prologue end within 256 bytes of the start of
11853 the function. Prevent instruction schedules that would extend that.
11854 Further, prevent alloca modifications to the stack pointer from being
11855 combined with prologue modifications. */
11858 }
11860 /* Emit code to restore REG using a POP insn. */
11862 static void
11864 {
11873 {
11874 /* Previously we'd represented the CFA as an expression
11875 like *(%ebp - 8). We've just popped that value from
11876 the stack, which means we need to reset the CFA to
11877 the drap register. This will remain until we restore
11878 the stack pointer. */
11882 /* This means that the DRAP register is valid for addressing too. */
11885 }
11888 {
11895 }
11897 /* When the frame pointer is the CFA, and we pop it, we are
11898 swapping back to the stack pointer as the CFA. This happens
11899 for stack frames that don't allocate other data, so we assume
11900 the stack pointer is now pointing at the return address, i.e.
11901 the function entry state, which makes the offset be 1 word. */
11903 {
11906 {
11914 }
11915 }
11916 }
11918 /* Emit code to restore saved registers using POP insns. */
11920 static void
11922 {
11928 }
11930 /* Emit code and notes for the LEAVE instruction. */
11932 static void
11934 {
11946 {
11954 }
11957 }
11959 /* Emit code to restore saved registers using MOV insns.
11960 First register is restored from CFA - CFA_OFFSET. */
11961 static void
11964 {
11970 {
11972 rtx mem;
11980 {
11981 /* Previously we'd represented the CFA as an expression
11982 like *(%ebp - 8). We've just popped that value from
11983 the stack, which means we need to reset the CFA to
11984 the drap register. This will remain until we restore
11985 the stack pointer. */
11989 /* This means that the DRAP register is valid for addressing. */
11991 }
11992 else
11996 }
11997 }
11999 /* Emit code to restore saved registers using MOV insns.
12000 First register is restored from CFA - CFA_OFFSET. */
12001 static void
12004 {
12009 {
12011 rtx mem;
12021 }
12022 }
12024 /* Restore function stack, frame, and registers. */
12026 void
12028 {
12044 /* The FP must be valid if the frame pointer is present. */
12049 /* We must have *some* valid pointer to the stack frame. */
12052 /* The DRAP is never valid at this point. */
12055 /* See the comment about red zone and frame
12056 pointer usage in ix86_expand_prologue. */
12063 /* Determine the CFA offset of the end of the red-zone. */
12066 {
12067 /* The red-zone begins below the return address. */
12070 /* When the register save area is in the aligned portion of
12071 the stack, determine the maximum runtime displacement that
12072 matches up with the aligned frame. */
12076 }
12078 /* Special care must be taken for the normal return case of a function
12079 using eh_return: the eax and edx registers are marked as saved, but
12080 not restored along this path. Adjust the save location to match. */
12084 /* EH_RETURN requires the use of moves to function properly. */
12087 /* SEH requires the use of pops to identify the epilogue. */
12090 /* If we're only restoring one register and sp is not valid then
12091 using a move instruction to restore the register since it's
12092 less work than reloading sp and popping the register. */
12105 && TARGET_USE_LEAVE
12109 else
12113 {
12114 /* Ensure that the entire register save area is addressable via
12115 the stack pointer, if we will restore via sp. */
12120 {
12124 style,
12126 }
12127 }
12129 /* If there are any SSE registers to restore, then we have to do it
12130 via moves, since there's obviously no pop for SSE regs. */
12136 {
12137 rtx t;
12142 /* eh_return epilogues need %ecx added to the stack pointer. */
12144 {
12148 /* Stack align doesn't work with eh_return. */
12150 /* Neither does regparm nested functions. */
12154 {
12162 /* Note that we use SA as a temporary CFA, as the return
12163 address is at the proper place relative to it. We
12164 pretend this happens at the FP restore insn because
12165 prior to this insn the FP would be stored at the wrong
12166 offset relative to SA, and after this insn we have no
12167 other reasonable register to use for the CFA. We don't
12168 bother resetting the CFA to the SP for the duration of
12169 the return insn. */
12182 }
12183 else
12184 {
12192 {
12196 UNITS_PER_WORD));
12198 }
12199 }
12202 }
12203 }
12204 else
12205 {
12206 /* SEH requires that the function end with (1) a stack adjustment
12207 if necessary, (2) a sequence of pops, and (3) a return or
12208 jump instruction. Prevent insns from the function body from
12209 being scheduled into this sequence. */
12211 {
12212 /* Prevent a catch region from being adjacent to the standard
12213 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
12214 several other flags that would be interesting to test are
12215 not yet set up. */
12218 else
12220 }
12222 /* First step is to deallocate the stack frame so that we can
12223 pop the registers. Also do it on SEH target for very large
12224 frame as the emitted instructions aren't allowed by the ABI in
12225 epilogues. */
12227 || (TARGET_SEH
12230 {
12235 }
12237 {
12241 style,
12243 }
12246 }
12248 /* If we used a stack pointer and haven't already got rid of it,
12249 then do so now. */
12251 {
12252 /* If the stack pointer is valid and pointing at the frame
12253 pointer store address, then we only need a pop. */
12256 /* Leave results in shorter dependency chains on CPUs that are
12257 able to grok it fast. */
12262 else
12263 {
12265 hard_frame_pointer_rtx,
12268 }
12269 }
12272 {
12300 }
12302 /* At this point the stack pointer must be valid, and we must have
12303 restored all of the registers. We may not have deallocated the
12304 entire stack frame. We've delayed this until now because it may
12305 be possible to merge the local stack deallocation with the
12306 deallocation forced by ix86_static_chain_on_stack. */
12311 {
12315 }
12316 else
12319 /* Sibcall epilogues don't want a return instruction. */
12321 {
12324 }
12327 {
12330 /* i386 can only pop 64K bytes. If asked to pop more, pop return
12331 address, do explicit add, and jump indirectly to the caller. */
12334 {
12338 /* There is no "pascal" calling convention in any 64bit ABI. */
12354 }
12355 else
12357 }
12358 else
12361 /* Restore the state back to the state from the prologue,
12362 so that it's correct for the next epilogue. */
12364 }
12366 /* Reset from the function's potential modifications. */
12368 static void
12370 {
12374 #if TARGET_MACHO
12375 /* Mach-O doesn't support labels at the end of objects, so if
12376 it looks like we might want one, insert a NOP. */
12377 {
12383 {
12384 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
12385 notes only, instead set their CODE_LABEL_NUMBER to -1,
12386 otherwise there would be code generation differences
12387 in between -g and -g0. */
12391 }
12401 }
12402 #endif
12404 }
12406 /* Return a scratch register to use in the split stack prologue. The
12407 split stack prologue is used for -fsplit-stack. It is the first
12408 instructions in the function, even before the regular prologue.
12409 The scratch register can be any caller-saved register which is not
12410 used for parameters or for the static chain. */
12412 static unsigned int
12414 {
12417 else
12418 {
12431 {
12433 {
12437 }
12439 }
12441 {
12445 }
12447 {
12450 else
12451 {
12453 {
12457 }
12459 }
12460 }
12461 else
12462 {
12463 /* FIXME: We could make this work by pushing a register
12464 around the addition and comparison. */
12467 }
12468 }
12469 }
12471 /* A SYMBOL_REF for the function which allocates new stackspace for
12472 -fsplit-stack. */
12476 /* A SYMBOL_REF for the more stack function when using the large
12477 model. */
12481 /* Handle -fsplit-stack. These are the first instructions in the
12482 function, even before the regular prologue. */
12484 void
12486 {
12488 HOST_WIDE_INT allocate;
12494 rtx fn;
12502 /* This is the label we will branch to if we have enough stack
12503 space. We expect the basic block reordering pass to reverse this
12504 branch if optimizing, so that we branch in the unlikely case. */
12507 /* We need to compare the stack pointer minus the frame size with
12508 the stack boundary in the TCB. The stack boundary always gives
12509 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
12510 can compare directly. Otherwise we need to do an addition. */
12513 UNSPEC_STACK_CHECK);
12518 else
12519 {
12521 rtx offset;
12523 /* We need a scratch register to hold the stack pointer minus
12524 the required frame size. Since this is the very start of the
12525 function, the scratch register can be any caller-saved
12526 register which is not used for parameters. */
12533 {
12534 /* We don't use ix86_gen_add3 in this case because it will
12535 want to split to lea, but when not optimizing the insn
12536 will not be split after this point. */
12539 offset)));
12540 }
12541 else
12542 {
12545 stack_pointer_rtx));
12546 }
12548 }
12554 /* Mark the jump as very likely to be taken. */
12559 {
12562 }
12565 /* Get more stack space. We pass in the desired stack space and the
12566 size of the arguments to copy to the new stack. In 32-bit mode
12567 we push the parameters; __morestack will return on a new stack
12568 anyhow. In 64-bit mode we pass the parameters in r10 and
12569 r11. */
12574 {
12580 /* If this function uses a static chain, it will be in %r10.
12581 Preserve it across the call to __morestack. */
12583 {
12584 rtx rax;
12589 }
12593 {
12594 HOST_WIDE_INT argval;
12597 /* When using the large model we need to load the address
12598 into a register, and we've run out of registers. So we
12599 switch to a different calling convention, and we call a
12600 different function: __morestack_large. We pass the
12601 argument size in the upper 32 bits of r10 and pass the
12602 frame size in the lower 32 bits. */
12607 {
12608 split_stack_fn_large =
12611 }
12613 {
12615 rtx x;
12624 UNSPEC_GOT);
12630 }
12631 else
12638 }
12639 else
12640 {
12644 }
12647 }
12648 else
12649 {
12652 }
12658 /* In order to make call/return prediction work right, we now need
12659 to execute a return instruction. See
12660 libgcc/config/i386/morestack.S for the details on how this works.
12662 For flow purposes gcc must not see this as a return
12663 instruction--we need control flow to continue at the subsequent
12664 label. Therefore, we use an unspec. */
12668 /* If we are in 64-bit mode and this function uses a static chain,
12669 we saved %r10 in %rax before calling _morestack. */
12674 /* If this function calls va_start, we need to store a pointer to
12675 the arguments on the old stack, because they may not have been
12676 all copied to the new stack. At this point the old stack can be
12677 found at the frame pointer value used by __morestack, because
12678 __morestack has set that up before calling back to us. Here we
12679 store that pointer in a scratch register, and in
12680 ix86_expand_prologue we store the scratch register in a stack
12681 slot. */
12683 {
12685 rtx frame_reg;
12692 /* 64-bit:
12693 fp -> old fp value
12694 return address within this function
12695 return address of caller of this function
12696 stack arguments
12697 So we add three words to get to the stack arguments.
12699 32-bit:
12700 fp -> old fp value
12701 return address within this function
12702 first argument to __morestack
12703 second argument to __morestack
12704 return address of caller of this function
12705 stack arguments
12706 So we add five words to get to the stack arguments.
12707 */
12718 }
12723 /* If this function calls va_start, we now have to set the scratch
12724 register for the case where we do not call __morestack. In this
12725 case we need to set it based on the stack pointer. */
12727 {
12734 }
12735 }
12737 /* We may have to tell the dataflow pass that the split stack prologue
12738 is initializing a scratch register. */
12740 static void
12742 {
12744 {
12747 }
12748 }
12749 \f
12750 /* Extract the parts of an RTL expression that is a valid memory address
12751 for an instruction. Return 0 if the structure of the address is
12752 grossly off. Return -1 if the address contains ASHIFT, so it is not
12753 strictly valid, but still used for computing length of lea instruction. */
12755 int
12757 {
12762 rtx tmp;
12766 /* Allow zero-extended SImode addresses,
12767 they will be emitted with addr32 prefix. */
12769 {
12772 {
12776 }
12779 {
12786 }
12787 }
12789 /* Allow SImode subregs of DImode addresses,
12790 they will be emitted with addr32 prefix. */
12792 {
12795 {
12799 }
12800 }
12805 {
12808 else
12810 }
12812 {
12817 do
12818 {
12823 }
12830 {
12833 {
12858 /* FALLTHRU */
12862 && TARGET_TLS_DIRECT_SEG_REFS
12865 else
12872 /* FALLTHRU */
12879 else
12894 }
12895 }
12896 }
12898 {
12901 }
12903 {
12904 /* We're called for lea too, which implements ashift on occasion. */
12914 }
12915 else
12919 {
12921 ;
12924 ;
12925 else
12927 }
12929 /* Extract the integral value of scale. */
12931 {
12935 }
12940 /* Avoid useless 0 displacement. */
12944 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12949 {
12952 }
12954 /* Special case: %ebp cannot be encoded as a base without a displacement.
12955 Similarly %r13. */
12957 && base_reg
12966 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12967 Avoid this by transforming to [%esi+0].
12968 Reload calls address legitimization without cfun defined, so we need
12969 to test cfun for being non-NULL. */
12975 /* Special case: encode reg+reg instead of reg*2. */
12979 /* Special case: scaling cannot be encoded without base or displacement. */
12990 }
12991 \f
12992 /* Return cost of the memory address x.
12993 For i386, it is better to use a complex address than let gcc copy
12994 the address into a reg and make a new pseudo. But not if the address
12995 requires to two regs - that would mean more pseudos with longer
12996 lifetimes. */
12997 static int
12999 {
13011 /* Attempt to minimize number of registers in the address by increasing
13012 address cost for each used register. We don't increase address cost
13013 for "pic_offset_table_rtx". When a memopt with "pic_offset_table_rtx"
13014 is not invariant itself it most likely means that base or index is not
13015 invariant. Therefore only "pic_offset_table_rtx" could be hoisted out,
13016 which is not profitable for x86. */
13020 || !pic_offset_table_rtx
13023 cost++;
13028 || !pic_offset_table_rtx
13031 cost++;
13033 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
13034 since it's predecode logic can't detect the length of instructions
13035 and it degenerates to vector decoded. Increase cost of such
13036 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
13037 to split such addresses or even refuse such addresses at all.
13039 Following addressing modes are affected:
13040 [base+scale*index]
13041 [scale*index+disp]
13042 [base+index]
13044 The first and last case may be avoidable by explicitly coding the zero in
13045 memory address, but I don't have AMD-K6 machine handy to check this
13046 theory. */
13055 }
13056 \f
13057 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
13058 this is used for to form addresses to local data when -fPIC is in
13059 use. */
13061 static bool
13063 {
13066 }
13068 /* Determine if a given RTX is a valid constant. We already know this
13069 satisfies CONSTANT_P. */
13071 static bool
13073 {
13074 /* Pointer bounds constants are not valid. */
13079 {
13084 {
13088 }
13093 /* Only some unspecs are valid as "constants". */
13096 {
13112 }
13114 /* We must have drilled down to a symbol. */
13119 /* FALLTHRU */
13122 /* TLS symbols are never valid. */
13126 /* DLLIMPORT symbols are never valid. */
13131 #if TARGET_MACHO
13132 /* mdynamic-no-pic */
13135 #endif
13149 }
13151 /* Otherwise we handle everything else in the move patterns. */
13153 }
13155 /* Determine if it's legal to put X into the constant pool. This
13156 is not possible for the address of thread-local symbols, which
13157 is checked above. */
13159 static bool
13161 {
13162 /* We can always put integral constants and vectors in memory. */
13164 {
13173 }
13175 }
13177 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
13178 otherwise zero. */
13180 static bool
13182 {
13188 }
13191 /* Nonzero if the constant value X is a legitimate general operand
13192 when generating PIC code. It is given that flag_pic is on and
13193 that X satisfies CONSTANT_P. */
13195 bool
13197 {
13198 rtx inner;
13201 {
13208 /* Only some unspecs are valid as "constants". */
13211 {
13224 }
13225 /* FALLTHRU */
13233 }
13234 }
13236 /* Determine if a given CONST RTX is a valid memory displacement
13237 in PIC mode. */
13239 bool
13241 {
13244 /* In 64bit mode we can allow direct addresses of symbols and labels
13245 when they are not dynamic symbols. */
13247 {
13251 {
13275 /* FALLTHRU */
13278 /* TLS references should always be enclosed in UNSPEC.
13279 The dllimported symbol needs always to be resolved. */
13285 {
13293 /* Function-symbols need to be resolved only for
13294 large-model.
13295 For the small-model we don't need to resolve anything
13296 here. */
13301 /* Non-external symbols don't need to be resolved for
13302 large, and medium-model. */
13307 }
13310 || (HAVE_LD_PIE_COPYRELOC
13311 && flag_pie
13320 }
13321 }
13327 {
13328 /* We are unsafe to allow PLUS expressions. This limit allowed distance
13329 of GOT tables. We should not need these anyway. */
13341 }
13345 {
13350 }
13359 {
13363 /* We need to check for both symbols and labels because VxWorks loads
13364 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
13365 details. */
13369 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
13370 While ABI specify also 32bit relocation but we don't produce it in
13371 small PIC model at all. */
13393 }
13396 }
13398 /* Determine if op is suitable RTX for an address register.
13399 Return naked register if a register or a register subreg is
13400 found, otherwise return NULL_RTX. */
13402 static rtx
13404 {
13407 /* Only SImode or DImode registers can form the address. */
13414 {
13422 /* Don't allow SUBREGs that span more than a word. It can
13423 lead to spill failures when the register is one word out
13424 of a two word structure. */
13428 /* Allow only SUBREGs of non-eliminable hard registers. */
13431 }
13433 /* Op is not a register. */
13435 }
13437 /* Recognizes RTL expressions that are valid memory addresses for an
13438 instruction. The MODE argument is the machine mode for the MEM
13439 expression that wants to use this address.
13441 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
13442 convert common non-canonical forms to canonical form so that they will
13443 be recognized. */
13445 static bool
13447 {
13450 HOST_WIDE_INT scale;
13454 /* Decomposition failed. */
13463 /* Validate base register. */
13465 {
13473 /* Base is not valid. */
13475 }
13477 /* Validate index register. */
13479 {
13487 /* Index is not valid. */
13489 }
13491 /* Index and base should have the same mode. */
13496 /* Address override works only on the (%reg) part of %fs:(%reg). */
13502 /* Validate scale factor. */
13504 {
13506 /* Scale without index. */
13510 /* Scale is not a valid multiplier. */
13512 }
13514 /* Validate displacement. */
13516 {
13521 {
13522 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
13523 used. While ABI specify also 32bit relocations, we don't produce
13524 them at all and use IP relative instead. */
13531 /* 64bit address unspec. */
13551 /* Invalid address unspec. */
13553 }
13556 && (flag_pic
13557 || (TARGET_MACHO
13558 #if TARGET_MACHO
13559 && MACHOPIC_INDIRECT
13561 #endif
13562 )))
13563 {
13565 is_legitimate_pic:
13567 {
13568 /* foo@dtpoff(%rX) is ok. */
13575 /* Non-constant pic memory reference. */
13577 }
13580 /* Displacement is an invalid pic construct. */
13582 #if TARGET_MACHO
13585 /* displacment must be referenced via non_lazy_pointer */
13587 #endif
13589 /* This code used to verify that a symbolic pic displacement
13590 includes the pic_offset_table_rtx register.
13592 While this is good idea, unfortunately these constructs may
13593 be created by "adds using lea" optimization for incorrect
13594 code like:
13596 int a;
13597 int foo(int i)
13598 {
13599 return *(&a+i);
13600 }
13602 This code is nonsensical, but results in addressing
13603 GOT table with pic_offset_table_rtx base. We can't
13604 just refuse it easily, since it gets matched by
13605 "addsi3" pattern, that later gets split to lea in the
13606 case output register differs from input. While this
13607 can be handled by separate addsi pattern for this case
13608 that never results in lea, this seems to be easier and
13609 correct fix for crash to disable this test. */
13610 }
13617 /* Displacement is not constant. */
13621 /* Displacement is out of range. */
13623 /* In x32 mode, constant addresses are sign extended to 64bit, so
13624 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13629 }
13631 /* Everything looks valid. */
13633 }
13635 /* Determine if a given RTX is a valid constant address. */
13637 bool
13639 {
13641 }
13642 \f
13643 /* Return a unique alias set for the GOT. */
13645 static alias_set_type
13647 {
13652 }
13654 /* Return a legitimate reference for ORIG (an address) using the
13655 register REG. If REG is 0, a new pseudo is generated.
13657 There are two types of references that must be handled:
13659 1. Global data references must load the address from the GOT, via
13660 the PIC reg. An insn is emitted to do this load, and the reg is
13661 returned.
13663 2. Static data references, constant pool addresses, and code labels
13664 compute the address as an offset from the GOT, whose base is in
13665 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13666 differentiate them from global data objects. The returned
13667 address is the PIC reg + an unspec constant.
13669 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13670 reg also appears in the address. */
13672 static rtx
13674 {
13678 #if TARGET_MACHO
13680 {
13683 /* Use the generic Mach-O PIC machinery. */
13685 }
13686 #endif
13689 {
13693 }
13699 {
13700 rtx tmpreg;
13701 /* This symbol may be referenced via a displacement from the PIC
13702 base address (@GOTOFF). */
13707 {
13709 UNSPEC_GOTOFF);
13711 }
13712 else
13717 else
13722 {
13726 }
13727 else
13729 }
13731 {
13732 /* This symbol may be referenced via a displacement from the PIC
13733 base address (@GOTOFF). */
13738 {
13740 UNSPEC_GOTOFF);
13742 }
13743 else
13749 {
13752 }
13753 }
13755 /* We can't use @GOTOFF for text labels on VxWorks;
13756 see gotoff_operand. */
13758 {
13763 /* For x64 PE-COFF there is no GOT table. So we use address
13764 directly. */
13766 {
13774 }
13776 {
13784 /* Use directly gen_movsi, otherwise the address is loaded
13785 into register for CSE. We don't want to CSE this addresses,
13786 instead we CSE addresses from the GOT table, so skip this. */
13789 }
13790 else
13791 {
13792 /* This symbol must be referenced via a load from the
13793 Global Offset Table (@GOT). */
13807 }
13808 }
13809 else
13810 {
13813 {
13815 {
13818 }
13819 else
13821 }
13823 {
13826 /* We must match stuff we generate before. Assume the only
13827 unspecs that can get here are ours. Not that we could do
13828 anything with them anyway.... */
13834 }
13836 {
13839 /* Check first to see if this is a constant offset from a @GOTOFF
13840 symbol reference. */
13843 {
13845 {
13847 UNSPEC_GOTOFF);
13853 {
13856 }
13857 }
13858 else
13859 {
13862 {
13866 }
13867 }
13868 }
13869 else
13870 {
13873 new_rtx
13877 {
13880 {
13883 new_rtx
13885 }
13886 else
13888 }
13889 else
13890 {
13891 /* For %rip addressing, we have to use just disp32, not
13892 base nor index. */
13899 {
13902 }
13904 }
13905 }
13906 }
13907 }
13909 }
13910 \f
13911 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13913 static rtx
13915 {
13919 {
13924 }
13930 }
13932 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13936 static rtx
13938 {
13940 {
13946 }
13949 {
13951 UNSPEC_PLTOFF);
13954 }
13957 }
13959 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13963 rtx
13965 {
13967 {
13968 ix86_tls_module_base_symbol
13973 }
13976 }
13978 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13979 false if we expect this to be used for a memory address and true if
13980 we expect to load the address into a register. */
13982 static rtx
13984 {
13990 /* Fall back to global dynamic model if tool chain cannot support local
13991 dynamic. */
13998 {
14003 {
14006 else
14007 {
14010 }
14011 }
14014 {
14017 else
14027 }
14028 else
14029 {
14033 {
14038 emit_call_insn
14048 }
14049 else
14051 }
14058 {
14061 else
14062 {
14065 }
14066 }
14069 {
14074 else
14080 }
14081 else
14082 {
14086 {
14089 rtx eqv;
14092 emit_call_insn
14097 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
14098 share the LD_BASE result with other LD model accesses. */
14100 UNSPEC_TLS_LD_BASE);
14104 }
14105 else
14107 }
14115 {
14122 }
14127 {
14129 {
14130 /* The Sun linker took the AMD64 TLS spec literally
14131 and can only handle %rax as destination of the
14132 initial executable code sequence. */
14137 }
14139 /* Generate DImode references to avoid %fs:(%reg32)
14140 problems and linker IE->LE relaxation bug. */
14144 }
14146 {
14149 }
14151 {
14155 }
14156 else
14157 {
14160 }
14170 {
14175 }
14176 else
14177 {
14181 }
14191 {
14195 }
14196 else
14197 {
14201 }
14206 }
14209 }
14211 /* Create or return the unique __imp_DECL dllimport symbol corresponding
14212 to symbol DECL if BEIMPORT is true. Otherwise create or return the
14213 unique refptr-DECL symbol corresponding to symbol DECL. */
14216 {
14220 {
14222 }
14224 static int
14226 {
14228 }
14229 };
14233 static tree
14235 {
14241 tree to;
14242 rtx rtl;
14269 else
14282 {
14284 #ifdef SUB_TARGET_RECORD_STUB
14286 #endif
14287 }
14296 }
14298 /* Expand SYMBOL into its corresponding far-addresse symbol.
14299 WANT_REG is true if we require the result be a register. */
14301 static rtx
14303 {
14304 tree imp_decl;
14305 rtx x;
14314 }
14316 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
14317 true if we require the result be a register. */
14319 static rtx
14321 {
14322 tree imp_decl;
14323 rtx x;
14332 }
14334 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
14335 is true if we require the result be a register. */
14337 static rtx
14339 {
14344 {
14351 {
14354 }
14355 }
14371 {
14374 }
14376 }
14378 /* Try machine-dependent ways of modifying an illegitimate address
14379 to be legitimate. If we find one, return the new, valid address.
14380 This macro is used in only one place: `memory_address' in explow.c.
14382 OLDX is the address as it was before break_out_memory_refs was called.
14383 In some cases it is useful to look at this to decide what needs to be done.
14385 It is always safe for this macro to do nothing. It exists to recognize
14386 opportunities to optimize the output.
14388 For the 80386, we handle X+REG by loading X into a register R and
14389 using R+REG. R will go in a general reg and indexing will be used.
14390 However, if REG is a broken-out memory address or multiplication,
14391 nothing needs to be done because REG can certainly go in a general reg.
14393 When -fpic is used, special handling is needed for symbolic references.
14394 See comments by legitimize_pic_address in i386.c for details. */
14396 static rtx
14398 {
14409 {
14413 }
14416 {
14420 }
14425 #if TARGET_MACHO
14428 #endif
14430 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
14434 {
14439 }
14442 {
14443 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
14448 {
14454 }
14459 {
14465 }
14467 /* Put multiply first if it isn't already. */
14469 {
14472 }
14474 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
14475 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
14476 created by virtual register instantiation, register elimination, and
14477 similar optimizations. */
14479 {
14485 }
14487 /* Canonicalize
14488 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
14489 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
14494 {
14495 rtx constant;
14499 {
14502 }
14504 {
14507 }
14508 else
14512 {
14519 }
14520 }
14526 {
14529 }
14532 {
14535 }
14543 {
14546 }
14552 {
14556 {
14559 }
14563 }
14566 {
14570 {
14573 }
14577 }
14578 }
14581 }
14582 \f
14583 /* Print an integer constant expression in assembler syntax. Addition
14584 and subtraction are the only arithmetic that may appear in these
14585 expressions. FILE is the stdio stream to write to, X is the rtx, and
14586 CODE is the operand print code from the output string. */
14588 static void
14590 {
14594 {
14603 else
14604 {
14607 /* Mark the decl as referenced so that cgraph will
14608 output the function. */
14612 #if TARGET_MACHO
14616 #endif
14618 }
14626 /* FALLTHRU */
14637 /* This used to output parentheses around the expression,
14638 but that does not work on the 386 (either ATT or BSD assembler). */
14643 /* We can't handle floating point constants;
14644 TARGET_PRINT_OPERAND must handle them. */
14649 /* Some assemblers need integer constants to appear first. */
14651 {
14655 }
14656 else
14657 {
14662 }
14677 {
14681 }
14686 {
14705 /* FIXME: This might be @TPOFF in Sun ld too. */
14714 else
14724 else
14730 #if TARGET_MACHO
14735 #endif
14739 }
14744 }
14745 }
14747 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14748 We need to emit DTP-relative relocations. */
14750 static void ATTRIBUTE_UNUSED
14752 {
14757 {
14765 }
14766 }
14768 /* Return true if X is a representation of the PIC register. This copes
14769 with calls from ix86_find_base_term, where the register might have
14770 been replaced by a cselib value. */
14772 static bool
14774 {
14781 {
14789 }
14790 else
14792 }
14794 /* Helper function for ix86_delegitimize_address.
14795 Attempt to delegitimize TLS local-exec accesses. */
14797 static rtx
14799 {
14824 {
14829 }
14835 }
14837 /* In the name of slightly smaller debug output, and to cater to
14838 general assembler lossage, recognize PIC+GOTOFF and turn it back
14839 into a direct symbol reference.
14841 On Darwin, this is necessary to avoid a crash, because Darwin
14842 has a different PIC label for each routine but the DWARF debugging
14843 information is not associated with any particular routine, so it's
14844 necessary to remove references to the PIC label from RTL stored by
14845 the DWARF output code. */
14847 static rtx
14849 {
14851 /* addend is NULL or some rtx if x is something+GOTOFF where
14852 something doesn't include the PIC register. */
14854 /* reg_addend is NULL or a multiple of some register. */
14856 /* const_addend is NULL or a const_int. */
14858 /* This is the result, or NULL. */
14867 {
14874 {
14880 }
14887 {
14890 {
14895 }
14897 }
14902 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14903 and -mcmodel=medium -fpic. */
14904 }
14911 /* %ebx + GOT/GOTOFF */
14912 ;
14914 {
14915 /* %ebx + %reg * scale + GOT/GOTOFF */
14921 else
14922 {
14925 }
14926 }
14927 else
14933 {
14936 }
14957 {
14958 /* If the rest of original X doesn't involve the PIC register, add
14959 addend and subtract pic_offset_table_rtx. This can happen e.g.
14960 for code like:
14961 leal (%ebx, %ecx, 4), %ecx
14962 ...
14963 movl foo@GOTOFF(%ecx), %edx
14964 in which case we return (%ecx - %ebx) + foo
14965 or (%ecx - _GLOBAL_OFFSET_TABLE_) + foo if pseudo_pic_reg
14966 and reload has completed. */
14970 pic_offset_table_rtx),
14971 result);
14973 {
14977 }
14978 else
14980 }
14982 {
14986 }
14988 }
14990 /* If X is a machine specific address (i.e. a symbol or label being
14991 referenced as a displacement from the GOT implemented using an
14992 UNSPEC), then return the base term. Otherwise return X. */
14994 rtx
14996 {
14997 rtx term;
15000 {
15013 }
15016 }
15017 \f
15018 static void
15021 {
15025 {
15028 }
15033 {
15036 {
15055 }
15059 {
15078 }
15085 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
15086 Those same assemblers have the same but opposite lossage on cmov. */
15089 else
15094 {
15107 }
15114 else
15119 {
15132 }
15139 else
15149 else
15160 }
15162 }
15164 /* Print the name of register X to FILE based on its machine mode and number.
15165 If CODE is 'w', pretend the mode is HImode.
15166 If CODE is 'b', pretend the mode is QImode.
15167 If CODE is 'k', pretend the mode is SImode.
15168 If CODE is 'q', pretend the mode is DImode.
15169 If CODE is 'x', pretend the mode is V4SFmode.
15170 If CODE is 't', pretend the mode is V8SFmode.
15171 If CODE is 'g', pretend the mode is V16SFmode.
15172 If CODE is 'h', pretend the reg is the 'high' byte register.
15173 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
15174 If CODE is 'd', duplicate the operand for AVX instruction.
15175 */
15177 void
15179 {
15189 {
15193 }
15196 {
15199 }
15217 else
15231 {
15239 normal:
15255 {
15260 }
15264 }
15268 /* Irritatingly, AMD extended registers use
15269 different naming convention: "r%d[bwd]" */
15271 {
15274 {
15288 /* no suffix */
15293 }
15295 }
15298 {
15301 else
15303 }
15304 }
15306 /* Meaning of CODE:
15307 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
15308 C -- print opcode suffix for set/cmov insn.
15309 c -- like C, but print reversed condition
15310 F,f -- likewise, but for floating-point.
15311 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
15312 otherwise nothing
15313 R -- print embeded rounding and sae.
15314 r -- print only sae.
15315 z -- print the opcode suffix for the size of the current operand.
15316 Z -- likewise, with special suffixes for x87 instructions.
15317 * -- print a star (in certain assembler syntax)
15318 A -- print an absolute memory reference.
15319 E -- print address with DImode register names if TARGET_64BIT.
15320 w -- print the operand as if it's a "word" (HImode) even if it isn't.
15321 s -- print a shift double count, followed by the assemblers argument
15322 delimiter.
15323 b -- print the QImode name of the register for the indicated operand.
15324 %b0 would print %al if operands[0] is reg 0.
15325 w -- likewise, print the HImode name of the register.
15326 k -- likewise, print the SImode name of the register.
15327 q -- likewise, print the DImode name of the register.
15328 x -- likewise, print the V4SFmode name of the register.
15329 t -- likewise, print the V8SFmode name of the register.
15330 g -- likewise, print the V16SFmode name of the register.
15331 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
15332 y -- print "st(0)" instead of "st" as a register.
15333 d -- print duplicated register operand for AVX instruction.
15334 D -- print condition for SSE cmp instruction.
15335 P -- if PIC, print an @PLT suffix.
15336 p -- print raw symbol name.
15337 X -- don't print any sort of PIC '@' suffix for a symbol.
15338 & -- print some in-use local-dynamic symbol name.
15339 H -- print a memory address offset by 8; used for sse high-parts
15340 Y -- print condition for XOP pcom* instruction.
15341 + -- print a branch hint as 'cs' or 'ds' prefix
15342 ; -- print a semicolon (after prefixes due to bug in older gas).
15343 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
15344 @ -- print a segment register of thread base pointer load
15345 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
15346 ! -- print MPX prefix for jxx/call/ret instructions if required.
15347 */
15349 void
15351 {
15353 {
15355 {
15358 {
15364 /* Intel syntax. For absolute addresses, registers should not
15365 be surrounded by braces. */
15367 {
15372 }
15377 }
15383 /* Wrap address in an UNSPEC to declare special handling. */
15421 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15426 {
15440 output_operand_lossage
15443 }
15446 #endif
15451 {
15452 /* Opcodes don't get size suffixes if using Intel opcodes. */
15457 {
15475 output_operand_lossage
15478 }
15479 }
15482 warning
15484 /* FALLTHRU */
15487 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
15492 {
15494 {
15496 #ifdef HAVE_AS_IX86_FILDS
15498 #endif
15506 #ifdef HAVE_AS_IX86_FILDQ
15508 #else
15510 #endif
15515 }
15516 }
15518 {
15519 /* 387 opcodes don't get size suffixes
15520 if the operands are registers. */
15525 {
15541 }
15542 }
15543 else
15544 {
15545 output_operand_lossage
15548 }
15550 output_operand_lossage
15571 {
15574 }
15579 {
15630 }
15634 /* Little bit of braindamage here. The SSE compare instructions
15635 does use completely different names for the comparisons that the
15636 fp conditional moves. */
15638 {
15641 {
15644 }
15650 {
15653 }
15659 {
15662 }
15671 {
15674 }
15680 {
15683 }
15689 {
15692 }
15703 }
15708 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15711 #endif
15716 {
15720 }
15724 file);
15729 {
15733 }
15734 /* It doesn't actually matter what mode we use here, as we're
15735 only going to use this for printing. */
15737 /* Output 'qword ptr' for intel assembler dialect. */
15746 #ifdef HAVE_AS_IX86_HLE
15748 #else
15750 #endif
15752 #ifdef HAVE_AS_IX86_HLE
15754 #else
15756 #endif
15757 /* We do not want to print value of the operand. */
15786 {
15801 }
15814 {
15819 else
15822 }
15825 {
15826 rtx x;
15835 {
15840 {
15842 bool cputaken
15845 /* Emit hints only in the case default branch prediction
15846 heuristics would fail. */
15848 {
15849 /* We use 3e (DS) prefix for taken branches and
15850 2e (CS) prefix for not taken branches. */
15853 else
15855 }
15856 }
15857 }
15859 }
15862 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15864 #endif
15871 /* The kernel uses a different segment register for performance
15872 reasons; a system call would not have to trash the userspace
15873 segment register, which would be expensive. */
15876 else
15896 }
15897 }
15903 {
15904 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15907 {
15910 {
15919 else
15926 }
15928 /* Check for explicit size override (codes 'b', 'w', 'k',
15929 'q' and 'x') */
15943 }
15946 /* Avoid (%rip) for call operands. */
15952 else
15954 }
15957 {
15958 REAL_VALUE_TYPE r;
15966 /* Sign extend 32bit SFmode immediate to 8 bytes. */
15970 else
15972 }
15975 {
15976 REAL_VALUE_TYPE r;
15985 }
15987 /* These float cases don't actually occur as immediate operands. */
15989 {
15994 }
15996 else
15997 {
15998 /* We have patterns that allow zero sets of memory, for instance.
15999 In 64-bit mode, we should probably support all 8-byte vectors,
16000 since we can in fact encode that into an immediate. */
16002 {
16005 }
16008 {
16010 {
16013 }
16016 {
16019 else
16021 }
16022 }
16027 else
16029 }
16030 }
16032 static bool
16034 {
16037 }
16038 \f
16039 /* Print a memory operand whose address is ADDR. */
16041 static void
16043 {
16052 {
16059 }
16061 {
16065 }
16067 {
16071 {
16074 }
16077 }
16079 {
16084 }
16085 else
16096 {
16107 }
16109 /* Use one byte shorter RIP relative addressing for 64bit mode. */
16111 {
16123 }
16125 {
16126 /* Displacement only requires special attention. */
16129 {
16133 }
16136 else
16138 }
16139 else
16140 {
16141 /* Print SImode register names to force addr32 prefix. */
16143 {
16144 #ifdef ENABLE_CHECKING
16147 {
16158 }
16159 #endif
16162 }
16164 && TARGET_X32
16165 && disp
16168 {
16169 /* X32 runs in 64-bit mode, where displacement, DISP, in
16170 address DISP(%r64), is encoded as 32-bit immediate sign-
16171 extended from 32-bit to 64-bit. For -0x40000300(%r64),
16172 address is %r64 + 0xffffffffbffffd00. When %r64 <
16173 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
16174 which is invalid for x32. The correct address is %r64
16175 - 0x40000300 == 0xf7ffdd64. To properly encode
16176 -0x40000300(%r64) for x32, we zero-extend negative
16177 displacement by forcing addr32 prefix which truncates
16178 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
16179 zero-extend all negative displacements, including -1(%rsp).
16180 However, for small negative displacements, sign-extension
16181 won't cause overflow. We only zero-extend negative
16182 displacements if they < -16*1024*1024, which is also used
16183 to check legitimate address displacements for PIC. */
16185 }
16188 {
16190 {
16195 else
16197 }
16203 {
16208 }
16210 }
16211 else
16212 {
16216 {
16217 /* Pull out the offset of a symbol; print any symbol itself. */
16221 {
16225 }
16233 else
16235 }
16239 {
16242 {
16246 }
16247 }
16250 else
16254 {
16259 }
16261 }
16262 }
16263 }
16265 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
16267 static bool
16269 {
16270 rtx op;
16277 {
16280 /* FIXME: This might be @TPOFF in Sun ld. */
16291 else
16303 else
16310 #if TARGET_MACHO
16316 #endif
16319 {
16324 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
16326 #else
16328 #endif
16331 }
16336 }
16339 }
16340 \f
16341 /* Split one or more double-mode RTL references into pairs of half-mode
16342 references. The RTL can be REG, offsettable MEM, integer constant, or
16343 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
16344 split and "num" is its length. lo_half and hi_half are output arrays
16345 that parallel "operands". */
16347 void
16350 {
16351 machine_mode half_mode;
16355 {
16364 }
16369 {
16372 /* simplify_subreg refuse to split volatile memory addresses,
16373 but we still have to handle it. */
16375 {
16378 }
16379 else
16380 {
16387 }
16388 }
16389 }
16390 \f
16391 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
16392 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
16393 is the expression of the binary operation. The output may either be
16394 emitted here, or returned to the caller, like all output_* functions.
16396 There is no guarantee that the operands are the same mode, as they
16397 might be within FLOAT or FLOAT_EXTEND expressions. */
16399 #ifndef SYSV386_COMPAT
16400 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
16401 wants to fix the assemblers because that causes incompatibility
16402 with gcc. No-one wants to fix gcc because that causes
16403 incompatibility with assemblers... You can use the option of
16404 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
16405 #define SYSV386_COMPAT 1
16406 #endif
16410 {
16416 #ifdef ENABLE_CHECKING
16417 /* Even if we do not want to check the inputs, this documents input
16418 constraints. Which helps in understanding the following code. */
16428 else
16430 #endif
16433 {
16438 else
16447 else
16456 else
16465 else
16472 }
16475 {
16477 {
16481 else
16483 }
16484 else
16485 {
16489 else
16491 }
16493 }
16497 {
16503 /* know operands[0] == operands[1]. */
16506 {
16509 }
16512 {
16514 /* How is it that we are storing to a dead operand[2]?
16515 Well, presumably operands[1] is dead too. We can't
16516 store the result to st(0) as st(0) gets popped on this
16517 instruction. Instead store to operands[2] (which I
16518 think has to be st(1)). st(1) will be popped later.
16519 gcc <= 2.8.1 didn't have this check and generated
16520 assembly code that the Unixware assembler rejected. */
16522 else
16525 }
16529 else
16536 {
16539 }
16542 {
16545 }
16548 {
16549 #if SYSV386_COMPAT
16550 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
16551 derived assemblers, confusingly reverse the direction of
16552 the operation for fsub{r} and fdiv{r} when the
16553 destination register is not st(0). The Intel assembler
16554 doesn't have this brain damage. Read !SYSV386_COMPAT to
16555 figure out what the hardware really does. */
16558 else
16560 #else
16562 /* As above for fmul/fadd, we can't store to st(0). */
16564 else
16566 #endif
16568 }
16571 {
16572 #if SYSV386_COMPAT
16575 else
16577 #else
16580 else
16582 #endif
16584 }
16587 {
16590 else
16593 }
16595 {
16596 #if SYSV386_COMPAT
16598 #else
16600 #endif
16601 }
16602 else
16603 {
16604 #if SYSV386_COMPAT
16606 #else
16608 #endif
16609 }
16614 }
16618 }
16620 /* Check if a 256bit AVX register is referenced inside of EXP. */
16622 static bool
16624 {
16630 }
16632 /* Return needed mode for entity in optimize_mode_switching pass. */
16634 static int
16636 {
16638 {
16639 rtx link;
16641 /* Needed mode is set to AVX_U128_CLEAN if there are
16642 no 256bit modes used in function arguments. */
16644 link;
16646 {
16648 {
16653 }
16654 }
16657 }
16659 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16660 changes state only when a 256bit register is written to, but we need
16661 to prevent the compiler from moving optimal insertion point above
16662 eventual read from 256bit register. */
16669 }
16671 /* Return mode that i387 must be switched into
16672 prior to the execution of insn. */
16674 static int
16676 {
16679 /* The mode UNINITIALIZED is used to store control word after a
16680 function call or ASM pattern. The mode ANY specify that function
16681 has no requirements on the control word and make no changes in the
16682 bits we are interested in. */
16696 {
16719 }
16722 }
16724 /* Return mode that entity must be switched into
16725 prior to the execution of insn. */
16727 static int
16729 {
16731 {
16741 }
16743 }
16745 /* Check if a 256bit AVX register is referenced in stores. */
16747 static void
16749 {
16751 {
16754 }
16755 }
16757 /* Calculate mode of upper 128bit AVX registers after the insn. */
16759 static int
16761 {
16768 /* We know that state is clean after CALL insn if there are no
16769 256bit registers used in the function return register. */
16771 {
16776 }
16778 /* Otherwise, return current mode. Remember that if insn
16779 references AVX 256bit registers, the mode was already changed
16780 to DIRTY from MODE_NEEDED. */
16782 }
16784 /* Return the mode that an insn results in. */
16786 static int
16788 {
16790 {
16800 }
16801 }
16803 static int
16805 {
16806 tree arg;
16808 /* Entry mode is set to AVX_U128_DIRTY if there are
16809 256bit modes used in function arguments. */
16812 {
16817 }
16820 }
16822 /* Return a mode that ENTITY is assumed to be
16823 switched to at function entry. */
16825 static int
16827 {
16829 {
16839 }
16840 }
16842 static int
16844 {
16847 /* Exit mode is set to AVX_U128_DIRTY if there are
16848 256bit modes used in the function return register. */
16853 }
16855 /* Return a mode that ENTITY is assumed to be
16856 switched to at function exit. */
16858 static int
16860 {
16862 {
16872 }
16873 }
16875 static int
16877 {
16879 }
16881 /* Output code to initialize control word copies used by trunc?f?i and
16882 rounding patterns. CURRENT_MODE is set to current control word,
16883 while NEW_MODE is set to new control word. */
16885 static void
16887 {
16889 rtx new_mode;
16900 {
16902 {
16904 /* round toward zero (truncate) */
16910 /* round down toward -oo */
16917 /* round up toward +oo */
16924 /* mask precision exception for nearbyint() */
16931 }
16932 }
16933 else
16934 {
16936 {
16938 /* round toward zero (truncate) */
16944 /* round down toward -oo */
16950 /* round up toward +oo */
16956 /* mask precision exception for nearbyint() */
16963 }
16964 }
16970 }
16972 /* Emit vzeroupper. */
16974 void
16976 {
16979 /* Cancel automatic vzeroupper insertion if there are
16980 live call-saved SSE registers at the insertion point. */
16992 }
16994 /* Generate one or more insns to set ENTITY to MODE. */
16996 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
16997 is the set of hard registers live at the point where the insn(s)
16998 are to be inserted. */
17000 static void
17002 HARD_REG_SET regs_live)
17003 {
17005 {
17020 }
17021 }
17023 /* Output code for INSN to convert a float to a signed int. OPERANDS
17024 are the insn operands. The output may be [HSD]Imode and the input
17025 operand may be [SDX]Fmode. */
17029 {
17034 /* Jump through a hoop or two for DImode, since the hardware has no
17035 non-popping instruction. We used to do this a different way, but
17036 that was somewhat fragile and broke with post-reload splitters. */
17046 else
17047 {
17052 else
17056 }
17059 }
17061 /* Output code for x87 ffreep insn. The OPNO argument, which may only
17062 have the values zero or one, indicates the ffreep insn's operand
17063 from the OPERANDS array. */
17067 {
17069 #ifdef HAVE_AS_IX86_FFREEP
17071 #else
17072 {
17082 }
17083 #endif
17086 }
17089 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
17090 should be used. UNORDERED_P is true when fucom should be used. */
17094 {
17100 {
17103 }
17104 else
17105 {
17108 }
17111 {
17115 else
17117 else
17120 else
17122 }
17129 {
17131 {
17134 }
17135 else
17137 }
17140 && stack_top_dies
17143 {
17144 /* If both the top of the 387 stack dies, and the other operand
17145 is also a stack register that dies, then this must be a
17146 `fcompp' float compare */
17149 {
17150 /* There is no double popping fcomi variant. Fortunately,
17151 eflags is immune from the fstp's cc clobbering. */
17154 else
17157 }
17158 else
17159 {
17162 else
17164 }
17165 }
17166 else
17167 {
17168 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
17171 {
17179 NULL,
17180 NULL,
17187 NULL,
17188 NULL,
17189 NULL,
17190 NULL
17191 };
17206 }
17207 }
17209 void
17211 {
17214 #ifdef ASM_QUAD
17217 #else
17219 #endif
17222 }
17224 void
17226 {
17229 #ifdef ASM_QUAD
17232 #else
17234 #endif
17235 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
17241 #if TARGET_MACHO
17243 {
17247 }
17248 #endif
17249 else
17252 }
17253 \f
17254 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
17255 for the target. */
17257 void
17259 {
17260 rtx tmp;
17262 /* We play register width games, which are only valid after reload. */
17265 /* Avoid HImode and its attendant prefix byte. */
17271 {
17274 }
17277 }
17279 /* X is an unchanging MEM. If it is a constant pool reference, return
17280 the constant pool rtx, else NULL. */
17282 rtx
17284 {
17291 }
17293 void
17295 {
17303 {
17304 rtx tmp;
17308 {
17314 }
17317 }
17321 {
17324 rtx tmp;
17329 else
17333 {
17340 }
17341 }
17345 {
17347 {
17348 #if TARGET_MACHO
17349 /* dynamic-no-pic */
17351 {
17358 }
17360 {
17364 }
17367 else
17368 {
17376 }
17377 /* dynamic-no-pic */
17378 #endif
17379 }
17380 else
17381 {
17385 {
17391 }
17392 }
17393 }
17394 else
17395 {
17406 /* Force large constants in 64bit compilation into register
17407 to get them CSEed. */
17418 {
17419 /* If we are loading a floating point constant to a register,
17420 force the value to memory now, since we'll get better code
17421 out the back end. */
17425 {
17430 }
17431 }
17432 }
17435 }
17437 void
17439 {
17446 /* Force constants other than zero into memory. We do not know how
17447 the instructions used to build constants modify the upper 64 bits
17448 of the register, once we have that information we may be able
17449 to handle some of them more efficiently. */
17458 /* We need to check memory alignment for SSE mode since attribute
17459 can make operands unaligned. */
17464 {
17467 /* ix86_expand_vector_move_misalign() does not like constants ... */
17473 /* ... nor both arguments in memory. */
17481 }
17483 /* Make operand1 a register if it isn't already. */
17487 {
17490 }
17493 }
17495 /* Split 32-byte AVX unaligned load and store if needed. */
17497 static void
17499 {
17500 rtx m;
17504 machine_mode mode;
17507 {
17528 }
17531 {
17534 {
17541 }
17542 /* Normal *mov<mode>_internal pattern will handle
17543 unaligned loads just fine if misaligned_operand
17544 is true, and without the UNSPEC it can be combined
17545 with arithmetic instructions. */
17548 else
17550 }
17552 {
17555 {
17560 }
17561 else
17563 }
17564 else
17566 }
17568 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17569 straight to ix86_expand_vector_move. */
17570 /* Code generation for scalar reg-reg moves of single and double precision data:
17571 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17572 movaps reg, reg
17573 else
17574 movss reg, reg
17575 if (x86_sse_partial_reg_dependency == true)
17576 movapd reg, reg
17577 else
17578 movsd reg, reg
17580 Code generation for scalar loads of double precision data:
17581 if (x86_sse_split_regs == true)
17582 movlpd mem, reg (gas syntax)
17583 else
17584 movsd mem, reg
17586 Code generation for unaligned packed loads of single precision data
17587 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17588 if (x86_sse_unaligned_move_optimal)
17589 movups mem, reg
17591 if (x86_sse_partial_reg_dependency == true)
17592 {
17593 xorps reg, reg
17594 movlps mem, reg
17595 movhps mem+8, reg
17596 }
17597 else
17598 {
17599 movlps mem, reg
17600 movhps mem+8, reg
17601 }
17603 Code generation for unaligned packed loads of double precision data
17604 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17605 if (x86_sse_unaligned_move_optimal)
17606 movupd mem, reg
17608 if (x86_sse_split_regs == true)
17609 {
17610 movlpd mem, reg
17611 movhpd mem+8, reg
17612 }
17613 else
17614 {
17615 movsd mem, reg
17616 movhpd mem+8, reg
17617 }
17618 */
17620 void
17622 {
17631 {
17633 {
17637 {
17639 {
17642 }
17643 else
17645 }
17647 /* FALLTHRU */
17651 {
17666 }
17672 else
17680 }
17683 }
17687 {
17689 {
17693 {
17695 {
17698 }
17699 else
17701 }
17703 /* FALLTHRU */
17713 }
17716 }
17719 {
17720 /* Normal *mov<mode>_internal pattern will handle
17721 unaligned loads just fine if misaligned_operand
17722 is true, and without the UNSPEC it can be combined
17723 with arithmetic instructions. */
17729 /* ??? If we have typed data, then it would appear that using
17730 movdqu is the only way to get unaligned data loaded with
17731 integer type. */
17733 {
17735 {
17738 }
17740 /* We will eventually emit movups based on insn attributes. */
17744 }
17746 {
17747 rtx zero;
17750 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17751 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17753 {
17754 /* We will eventually emit movups based on insn attributes. */
17757 }
17759 /* When SSE registers are split into halves, we can avoid
17760 writing to the top half twice. */
17762 {
17765 }
17766 else
17767 {
17768 /* ??? Not sure about the best option for the Intel chips.
17769 The following would seem to satisfy; the register is
17770 entirely cleared, breaking the dependency chain. We
17771 then store to the upper half, with a dependency depth
17772 of one. A rumor has it that Intel recommends two movsd
17773 followed by an unpacklpd, but this is unconfirmed. And
17774 given that the dependency depth of the unpacklpd would
17775 still be one, I'm not sure why this would be better. */
17777 }
17783 }
17784 else
17785 {
17786 rtx t;
17789 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17790 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17792 {
17794 {
17797 }
17804 }
17808 else
17813 else
17822 }
17823 }
17825 {
17827 {
17830 /* We will eventually emit movups based on insn attributes. */
17832 }
17834 {
17836 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17837 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17839 /* We will eventually emit movups based on insn attributes. */
17841 else
17842 {
17847 }
17848 }
17849 else
17850 {
17855 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17856 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17858 {
17861 }
17862 else
17863 {
17868 }
17869 }
17870 }
17871 else
17873 }
17875 /* Helper function of ix86_fixup_binary_operands to canonicalize
17876 operand order. Returns true if the operands should be swapped. */
17878 static bool
17880 rtx operands[])
17881 {
17886 /* If the operation is not commutative, we can't do anything. */
17890 /* Highest priority is that src1 should match dst. */
17896 /* Next highest priority is that immediate constants come second. */
17902 /* Lowest priority is that memory references should come second. */
17909 }
17912 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17913 destination to use for the operation. If different from the true
17914 destination in operands[0], a copy operation will be required. */
17916 rtx
17918 rtx operands[])
17919 {
17924 /* Canonicalize operand order. */
17926 {
17927 /* It is invalid to swap operands of different modes. */
17931 }
17933 /* Both source operands cannot be in memory. */
17935 {
17936 /* Optimization: Only read from memory once. */
17938 {
17941 }
17944 else
17946 }
17948 /* If the destination is memory, and we do not have matching source
17949 operands, do things in registers. */
17953 /* Source 1 cannot be a constant. */
17957 /* Source 1 cannot be a non-matching memory. */
17961 /* Improve address combine. */
17970 }
17972 /* Similarly, but assume that the destination has already been
17973 set up properly. */
17975 void
17978 {
17981 }
17983 /* Attempt to expand a binary operator. Make the expansion closer to the
17984 actual machine, then just general_operand, which will allow 3 separate
17985 memory references (one output, two input) in a single insn. */
17987 void
17989 rtx operands[])
17990 {
17997 /* Emit the instruction. */
18004 {
18005 /* This is going to be an LEA; avoid splitting it later. */
18007 }
18008 else
18009 {
18012 }
18014 /* Fix up the destination if needed. */
18017 }
18019 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
18020 the given OPERANDS. */
18022 void
18024 rtx operands[])
18025 {
18028 {
18031 }
18033 {
18036 }
18037 /* Optimize (__m128i) d | (__m128i) e and similar code
18038 when d and e are float vectors into float vector logical
18039 insn. In C/C++ without using intrinsics there is no other way
18040 to express vector logical operation on float vectors than
18041 to cast them temporarily to integer vectors. */
18043 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
18052 {
18053 rtx dst;
18055 {
18064 {
18067 }
18068 else
18069 {
18074 }
18085 }
18086 }
18095 }
18097 /* Return TRUE or FALSE depending on whether the binary operator meets the
18098 appropriate constraints. */
18100 bool
18103 {
18108 /* Both source operands cannot be in memory. */
18112 /* Canonicalize operand order for commutative operators. */
18116 /* If the destination is memory, we must have a matching source operand. */
18120 /* Source 1 cannot be a constant. */
18124 /* Source 1 cannot be a non-matching memory. */
18126 /* Support "andhi/andsi/anddi" as a zero-extending move. */
18134 }
18136 /* Attempt to expand a unary operator. Make the expansion closer to the
18137 actual machine, then just general_operand, which will allow 2 separate
18138 memory references (one output, one input) in a single insn. */
18140 void
18142 rtx operands[])
18143 {
18150 /* If the destination is memory, and we do not have matching source
18151 operands, do things in registers. */
18153 {
18156 else
18158 }
18160 /* When source operand is memory, destination must match. */
18164 /* Emit the instruction. */
18170 else
18171 {
18174 }
18176 /* Fix up the destination if needed. */
18179 }
18181 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
18182 divisor are within the range [0-255]. */
18184 void
18187 {
18196 {
18209 }
18216 /* Use 8bit unsigned divimod if dividend and divisor are within
18217 the range [0-255]. */
18226 pc_rtx);
18231 /* Generate original signed/unsigned divimod. */
18236 /* Branch to the end. */
18240 /* Generate 8bit unsigned divide. */
18242 /* Don't use operands[0] for result of 8bit divide since not all
18243 registers support QImode ZERO_EXTRACT. */
18250 {
18253 }
18254 else
18255 {
18258 }
18260 /* Extract remainder from AH. */
18264 else
18265 {
18266 /* Need a new scratch register since the old one has result
18267 of 8bit divide. */
18271 }
18274 /* Zero extend quotient from AL. */
18280 }
18282 #define LEA_MAX_STALL (3)
18283 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
18285 /* Increase given DISTANCE in half-cycles according to
18286 dependencies between PREV and NEXT instructions.
18287 Add 1 half-cycle if there is no dependency and
18288 go to next cycle if there is some dependecy. */
18290 static unsigned int
18292 {
18308 }
18310 /* Function checks if instruction INSN defines register number
18311 REGNO1 or REGNO2. */
18313 static bool
18316 {
18317 df_ref def;
18327 }
18329 /* Function checks if instruction INSN uses register number
18330 REGNO as a part of address expression. */
18332 static bool
18334 {
18335 df_ref use;
18342 }
18344 /* Search backward for non-agu definition of register number REGNO1
18345 or register number REGNO2 in basic block starting from instruction
18346 START up to head of basic block or instruction INSN.
18348 Function puts true value into *FOUND var if definition was found
18349 and false otherwise.
18351 Distance in half-cycles between START and found instruction or head
18352 of BB is added to DISTANCE and returned. */
18354 static int
18358 {
18368 {
18370 {
18373 {
18376 {
18379 }
18380 }
18383 }
18388 }
18391 }
18393 /* Search backward for non-agu definition of register number REGNO1
18394 or register number REGNO2 in INSN's basic block until
18395 1. Pass LEA_SEARCH_THRESHOLD instructions, or
18396 2. Reach neighbour BBs boundary, or
18397 3. Reach agu definition.
18398 Returns the distance between the non-agu definition point and INSN.
18399 If no definition point, returns -1. */
18401 static int
18404 {
18415 {
18416 edge e;
18417 edge_iterator ei;
18422 {
18425 }
18431 else
18432 {
18437 {
18438 int bb_dist
18444 {
18451 }
18452 }
18455 }
18456 }
18458 /* get_attr_type may modify recog data. We want to make sure
18459 that recog data is valid for instruction INSN, on which
18460 distance_non_agu_define is called. INSN is unchanged here. */
18467 }
18469 /* Return the distance in half-cycles between INSN and the next
18470 insn that uses register number REGNO in memory address added
18471 to DISTANCE. Return -1 if REGNO0 is set.
18473 Put true value into *FOUND if register usage was found and
18474 false otherwise.
18475 Put true value into *REDEFINED if register redefinition was
18476 found and false otherwise. */
18478 static int
18482 {
18491 {
18494 /* If insn and start belong to the same bb, set prev to insn,
18495 so the call to increase_distance will increase the distance
18496 between insns by 1. */
18498 }
18503 {
18505 {
18508 {
18509 /* Return DISTANCE if OP0 is used in memory
18510 address in NEXT. */
18513 }
18516 {
18517 /* Return -1 if OP0 is set in NEXT. */
18520 }
18523 }
18529 }
18532 }
18534 /* Return the distance between INSN and the next insn that uses
18535 register number REGNO0 in memory address. Return -1 if no such
18536 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18538 static int
18540 {
18552 {
18553 edge e;
18554 edge_iterator ei;
18559 {
18562 }
18568 else
18569 {
18575 {
18576 int bb_dist
18581 {
18588 }
18589 }
18592 }
18593 }
18599 }
18601 /* Define this macro to tune LEA priority vs ADD, it take effect when
18602 there is a dilemma of choicing LEA or ADD
18603 Negative value: ADD is more preferred than LEA
18604 Zero: Netrual
18605 Positive value: LEA is more preferred than ADD*/
18606 #define IX86_LEA_PRIORITY 0
18608 /* Return true if usage of lea INSN has performance advantage
18609 over a sequence of instructions. Instructions sequence has
18610 SPLIT_COST cycles higher latency than lea latency. */
18612 static bool
18615 {
18618 /* For Silvermont if using a 2-source or 3-source LEA for
18619 non-destructive destination purposes, or due to wanting
18620 ability to use SCALE, the use of LEA is justified. */
18622 {
18630 }
18636 {
18637 /* If there is no non AGU operand definition, no AGU
18638 operand usage and split cost is 0 then both lea
18639 and non lea variants have same priority. Currently
18640 we prefer lea for 64 bit code and non lea on 32 bit
18641 code. */
18644 else
18646 }
18648 /* With longer definitions distance lea is more preferable.
18649 Here we change it to take into account splitting cost and
18650 lea priority. */
18653 /* If there is no use in memory addess then we just check
18654 that split cost exceeds AGU stall. */
18658 /* If this insn has both backward non-agu dependence and forward
18659 agu dependence, the one with short distance takes effect. */
18661 }
18663 /* Return true if it is legal to clobber flags by INSN and
18664 false otherwise. */
18666 static bool
18668 {
18670 df_ref use;
18671 bitmap live;
18674 {
18676 {
18683 }
18689 }
18693 }
18695 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18696 move and add to avoid AGU stalls. */
18698 bool
18700 {
18703 /* Check if we need to optimize. */
18707 /* Check it is correct to split here. */
18715 /* We need to split only adds with non destructive
18716 destination operand. */
18719 else
18721 }
18723 /* Return true if we should emit lea instruction instead of mov
18724 instruction. */
18726 bool
18728 {
18731 /* Check if we need to optimize. */
18735 /* Use lea for reg to reg moves only. */
18743 }
18745 /* Return true if we need to split lea into a sequence of
18746 instructions to avoid AGU stalls. */
18748 bool
18750 {
18756 /* Check we need to optimize. */
18760 /* The "at least two components" test below might not catch simple
18761 move or zero extension insns if parts.base is non-NULL and parts.disp
18762 is const0_rtx as the only components in the address, e.g. if the
18763 register is %rbp or %r13. As this test is much cheaper and moves or
18764 zero extensions are the common case, do this check first. */
18770 /* Check if it is OK to split here. */
18777 /* There should be at least two components in the address. */
18782 /* We should not split into add if non legitimate pic
18783 operand is used as displacement. */
18798 /* Compute how many cycles we will add to execution time
18799 if split lea into a sequence of instructions. */
18801 {
18802 /* Have to use mov instruction if non desctructive
18803 destination form is used. */
18807 /* Have to add index to base if both exist. */
18811 /* Have to use shift and adds if scale is 2 or greater. */
18813 {
18818 else
18820 }
18822 /* Have to use add instruction with immediate if
18823 disp is non zero. */
18827 /* Subtract the price of lea. */
18829 }
18833 }
18835 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18836 matches destination. RTX includes clobber of FLAGS_REG. */
18838 static void
18841 {
18848 }
18850 /* Return true if regno1 def is nearest to the insn. */
18852 static bool
18854 {
18861 {
18863 {
18866 }
18872 }
18874 /* None of the regs is defined in the bb. */
18876 }
18878 /* Split lea instructions into a sequence of instructions
18879 which are executed on ALU to avoid AGU stalls.
18880 It is assumed that it is allowed to clobber flags register
18881 at lea position. */
18883 void
18885 {
18901 {
18904 }
18907 {
18910 }
18916 {
18917 /* Case r1 = r1 + ... */
18919 {
18920 /* If we have a case r1 = r1 + C * r2 then we
18921 should use multiplication which is very
18922 expensive. Assume cost model is wrong if we
18923 have such case here. */
18928 }
18929 else
18930 {
18931 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18935 /* Use shift for scaling. */
18944 }
18945 }
18947 {
18950 }
18951 else
18952 {
18954 {
18957 }
18959 {
18962 }
18963 else
18964 {
18969 else
18970 {
18971 rtx tmp1;
18973 /* Find better operand for SET instruction, depending
18974 on which definition is farther from the insn. */
18977 else
18987 }
18990 }
18994 }
18995 }
18997 /* Return true if it is ok to optimize an ADD operation to LEA
18998 operation to avoid flag register consumation. For most processors,
18999 ADD is faster than LEA. For the processors like BONNELL, if the
19000 destination register of LEA holds an actual address which will be
19001 used soon, LEA is better and otherwise ADD is better. */
19003 bool
19005 {
19010 /* If a = b + c, (a!=b && a!=c), must use lea form. */
19018 }
19020 /* Return true if destination reg of SET_BODY is shift count of
19021 USE_BODY. */
19023 static bool
19025 {
19026 rtx set_dest;
19027 rtx shift_rtx;
19030 /* Retrieve destination of SET_BODY. */
19032 {
19041 use_body))
19046 }
19048 /* Retrieve shift count of USE_BODY. */
19050 {
19062 }
19070 {
19073 /* Return true if shift count is dest of SET_BODY. */
19075 {
19076 /* Add check since it can be invoked before register
19077 allocation in pre-reload schedule. */
19083 }
19084 }
19087 }
19089 /* Return true if destination reg of SET_INSN is shift count of
19090 USE_INSN. */
19092 bool
19094 {
19097 }
19099 /* Return TRUE or FALSE depending on whether the unary operator meets the
19100 appropriate constraints. */
19102 bool
19104 machine_mode,
19106 {
19107 /* If one of operands is memory, source and destination must match. */
19113 }
19115 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
19116 are ok, keeping in mind the possible movddup alternative. */
19118 bool
19120 {
19126 }
19128 /* Post-reload splitter for converting an SF or DFmode value in an
19129 SSE register into an unsigned SImode. */
19131 void
19133 {
19134 machine_mode vecmode;
19144 /* Load up the value into the low element. We must ensure that the other
19145 elements are valid floats -- zero is the easiest such value. */
19147 {
19150 else
19152 }
19153 else
19154 {
19159 else
19161 }
19181 else
19186 }
19188 /* Convert an unsigned DImode value into a DFmode, using only SSE.
19189 Expects the 64-bit DImode to be supplied in a pair of integral
19190 registers. Requires SSE2; will use SSE3 if available. For x86_32,
19191 -mfpmath=sse, !optimize_size only. */
19193 void
19195 {
19199 rtx x;
19205 {
19208 }
19209 else
19210 {
19214 }
19222 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
19225 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
19226 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
19227 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
19228 (0x1.0p84 + double(fp_value_hi_xmm)).
19229 Note these exponents differ by 32. */
19233 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
19234 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
19243 /* Add the upper and lower DFmode values together. */
19246 else
19247 {
19251 }
19254 }
19256 /* Not used, but eases macroization of patterns. */
19257 void
19259 {
19261 }
19263 /* Convert an unsigned SImode value into a DFmode. Only currently used
19264 for SSE, but applicable anywhere. */
19266 void
19268 {
19269 REAL_VALUE_TYPE TWO31r;
19284 }
19286 /* Convert a signed DImode value into a DFmode. Only used for SSE in
19287 32-bit mode; otherwise we have a direct convert instruction. */
19289 void
19291 {
19292 REAL_VALUE_TYPE TWO32r;
19310 }
19312 /* Convert an unsigned SImode value into a SFmode, using only SSE.
19313 For x86_32, -mfpmath=sse, !optimize_size only. */
19314 void
19316 {
19317 REAL_VALUE_TYPE ONE16r;
19336 }
19338 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
19339 a vector of unsigned ints VAL to vector of floats TARGET. */
19341 void
19343 {
19345 REAL_VALUE_TYPE TWO16r;
19352 else
19357 OPTAB_DIRECT);
19368 OPTAB_DIRECT);
19370 OPTAB_DIRECT);
19373 }
19375 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
19376 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
19377 This is done by doing just signed conversion if < 0x1p31, and otherwise by
19378 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
19380 rtx
19382 {
19383 REAL_VALUE_TYPE TWO31r;
19398 {
19404 }
19413 OPTAB_DIRECT);
19414 else
19415 {
19421 OPTAB_DIRECT);
19422 }
19425 }
19427 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
19428 then replicate the value for all elements of the vector
19429 register. */
19431 rtx
19433 {
19435 rtvec v;
19436 machine_mode scalar_mode;
19439 {
19472 }
19473 }
19475 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
19476 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
19477 for an SSE register. If VECT is true, then replicate the mask for
19478 all elements of the vector register. If INVERT is true, then create
19479 a mask excluding the sign bit. */
19481 rtx
19483 {
19485 wide_int w;
19489 {
19520 }
19527 /* Force this value into the low part of a fp vector constant. */
19536 }
19538 /* Generate code for floating point ABS or NEG. */
19540 void
19542 rtx operands[])
19543 {
19554 {
19560 }
19562 /* NEG and ABS performed with SSE use bitwise mask operations.
19563 Create the appropriate mask now. */
19566 else
19576 {
19578 rtvec par;
19583 else
19584 {
19587 }
19589 }
19590 else
19592 }
19594 /* Expand a copysign operation. Special case operand 0 being a constant. */
19596 void
19598 {
19612 else
19616 {
19623 {
19626 else
19627 {
19631 }
19632 }
19642 else
19646 }
19647 else
19648 {
19658 else
19662 }
19663 }
19665 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19666 be a constant, and so has already been expanded into a vector constant. */
19668 void
19670 {
19686 {
19689 }
19690 }
19692 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19693 so we have to do two masks. */
19695 void
19697 {
19712 {
19713 /* Shouldn't happen often (it's useless, obviously), but when it does
19714 we'd generate incorrect code if we continue below. */
19717 }
19720 {
19731 }
19732 else
19733 {
19735 {
19737 }
19739 {
19743 }
19747 {
19750 }
19752 {
19757 }
19759 }
19763 }
19765 /* Return TRUE or FALSE depending on whether the first SET in INSN
19766 has source and destination with matching CC modes, and that the
19767 CC mode is at least as constrained as REQ_MODE. */
19769 bool
19771 {
19772 rtx set;
19773 machine_mode set_mode;
19783 {
19793 /* FALLTHRU */
19797 /* FALLTHRU */
19801 /* FALLTHRU */
19816 }
19819 }
19821 /* Generate insn patterns to do an integer compare of OPERANDS. */
19823 static rtx
19825 {
19826 machine_mode cmpmode;
19832 /* This is very simple, but making the interface the same as in the
19833 FP case makes the rest of the code easier. */
19837 /* Return the test that should be put into the flags user, i.e.
19838 the bcc, scc, or cmov instruction. */
19840 }
19842 /* Figure out whether to use ordered or unordered fp comparisons.
19843 Return the appropriate mode to use. */
19845 machine_mode
19847 {
19848 /* ??? In order to make all comparisons reversible, we do all comparisons
19849 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19850 all forms trapping and nontrapping comparisons, we can make inequality
19851 comparisons trapping again, since it results in better code when using
19852 FCOM based compares. */
19854 }
19856 machine_mode
19858 {
19862 {
19865 }
19868 {
19869 /* Only zero flag is needed. */
19873 /* Codes needing carry flag. */
19876 /* Detect overflow checks. They need just the carry flag. */
19880 else
19885 /* Codes possibly doable only with sign flag when
19886 comparing against zero. */
19891 else
19892 /* For other cases Carry flag is not required. */
19894 /* Codes doable only with sign flag when comparing
19895 against zero, but we miss jump instruction for it
19896 so we need to use relational tests against overflow
19897 that thus needs to be zero. */
19902 else
19904 /* strcmp pattern do (use flags) and combine may ask us for proper
19905 mode. */
19910 }
19911 }
19913 /* Return the fixed registers used for condition codes. */
19915 static bool
19917 {
19921 }
19923 /* If two condition code modes are compatible, return a condition code
19924 mode which is compatible with both. Otherwise, return
19925 VOIDmode. */
19927 static machine_mode
19929 {
19946 {
19961 {
19976 }
19980 /* These are only compatible with themselves, which we already
19981 checked above. */
19983 }
19984 }
19987 /* Return a comparison we can do and that it is equivalent to
19988 swap_condition (code) apart possibly from orderedness.
19989 But, never change orderedness if TARGET_IEEE_FP, returning
19990 UNKNOWN in that case if necessary. */
19992 static enum rtx_code
19994 {
19996 {
20007 }
20008 }
20010 /* Return cost of comparison CODE using the best strategy for performance.
20011 All following functions do use number of instructions as a cost metrics.
20012 In future this should be tweaked to compute bytes for optimize_size and
20013 take into account performance of various instructions on various CPUs. */
20015 static int
20017 {
20020 /* The cost of code using bit-twiddling on %ah. */
20022 {
20045 }
20048 {
20055 }
20056 }
20058 /* Return strategy to use for floating-point. We assume that fcomi is always
20059 preferrable where available, since that is also true when looking at size
20060 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
20062 enum ix86_fpcmp_strategy
20064 {
20065 /* Do fcomi/sahf based test when profitable. */
20074 }
20076 /* Swap, force into registers, or otherwise massage the two operands
20077 to a fp comparison. The operands are updated in place; the new
20078 comparison code is returned. */
20080 static enum rtx_code
20082 {
20088 /* All of the unordered compare instructions only work on registers.
20089 The same is true of the fcomi compare instructions. The XFmode
20090 compare instructions require registers except when comparing
20091 against zero or when converting operand 1 from fixed point to
20092 floating point. */
20101 {
20104 }
20105 else
20106 {
20107 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
20108 things around if they appear profitable, otherwise force op0
20109 into a register. */
20115 {
20118 {
20121 }
20122 }
20128 {
20133 {
20136 }
20137 else
20139 }
20140 }
20142 /* Try to rearrange the comparison to make it cheaper. */
20146 {
20151 }
20156 }
20158 /* Convert comparison codes we use to represent FP comparison to integer
20159 code that will result in proper branch. Return UNKNOWN if no such code
20160 is available. */
20162 enum rtx_code
20164 {
20166 {
20189 }
20190 }
20192 /* Generate insn patterns to do a floating point compare of OPERANDS. */
20194 static rtx
20196 {
20203 /* Do fcomi/sahf based test when profitable. */
20205 {
20225 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
20232 /* In the unordered case, we have to check C2 for NaN's, which
20233 doesn't happen to work out to anything nice combination-wise.
20234 So do some bit twiddling on the value we've got in AH to come
20235 up with an appropriate set of condition codes. */
20239 {
20243 {
20246 }
20247 else
20248 {
20254 }
20259 {
20264 }
20265 else
20266 {
20269 }
20274 {
20277 }
20278 else
20279 {
20283 }
20288 {
20294 }
20295 else
20296 {
20299 }
20304 {
20309 }
20310 else
20311 {
20314 }
20319 {
20324 }
20325 else
20326 {
20329 }
20343 }
20348 }
20350 /* Return the test that should be put into the flags user, i.e.
20351 the bcc, scc, or cmov instruction. */
20354 const0_rtx);
20355 }
20357 static rtx
20359 {
20360 rtx ret;
20366 {
20369 }
20370 else
20374 }
20376 void
20378 {
20380 rtx tmp;
20383 {
20390 simple:
20394 pc_rtx);
20402 /* Expand DImode branch into multiple compare+branch. */
20403 {
20407 machine_mode submode;
20410 {
20413 }
20420 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
20421 avoid two branches. This costs one extra insn, so disable when
20422 optimizing for size. */
20427 {
20445 }
20447 /* Otherwise, if we are doing less-than or greater-or-equal-than,
20448 op1 is a constant and the low word is zero, then we can just
20449 examine the high word. Similarly for low word -1 and
20450 less-or-equal-than or greater-than. */
20454 {
20457 {
20460 }
20464 {
20467 }
20471 }
20473 /* Otherwise, we need two or three jumps. */
20482 {
20496 }
20498 /*
20499 * a < b =>
20500 * if (hi(a) < hi(b)) goto true;
20501 * if (hi(a) > hi(b)) goto false;
20502 * if (lo(a) < lo(b)) goto true;
20503 * false:
20504 */
20516 }
20521 }
20522 }
20524 /* Split branch based on floating point condition. */
20525 void
20528 {
20529 rtx condition;
20530 rtx i;
20533 {
20536 }
20539 tmp);
20547 }
20549 void
20551 {
20552 rtx ret;
20559 }
20561 /* Expand comparison setting or clearing carry flag. Return true when
20562 successful and set pop for the operation. */
20563 static bool
20565 {
20566 machine_mode mode =
20569 /* Do not handle double-mode compares that go through special path. */
20574 {
20575 rtx compare_op;
20580 /* Shortcut: following common codes never translate
20581 into carry flag compares. */
20586 /* These comparisons require zero flag; swap operands so they won't. */
20589 {
20592 }
20594 /* Try to expand the comparison and verify that we end up with
20595 carry flag based comparison. This fails to be true only when
20596 we decide to expand comparison using arithmetic that is not
20597 too common scenario. */
20606 else
20615 }
20621 {
20626 /* Convert a==0 into (unsigned)a<1. */
20635 /* Convert a>b into b<a or a>=b-1. */
20639 {
20641 /* Bail out on overflow. We still can swap operands but that
20642 would force loading of the constant into register. */
20647 }
20648 else
20649 {
20652 }
20655 /* Convert a>=0 into (unsigned)a<0x80000000. */
20673 }
20674 /* Swapping operands may cause constant to appear as first operand. */
20676 {
20680 }
20684 }
20686 bool
20688 {
20691 rtx compare_op;
20713 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20714 HImode insns, we'd be swallowed in word prefix ops. */
20720 {
20724 HOST_WIDE_INT diff;
20727 /* Sign bit compares are better done using shifts than we do by using
20728 sbb. */
20731 {
20732 /* Detect overlap between destination and compare sources. */
20736 {
20737 rtx flags;
20746 {
20748 compare_code
20750 }
20752 /* To simplify rest of code, restrict to the GEU case. */
20754 {
20758 }
20759 else
20760 {
20763 reverse_condition_maybe_unordered
20765 else
20768 }
20777 else
20780 }
20781 else
20782 {
20785 else
20786 {
20789 }
20791 }
20794 {
20795 /*
20796 * cmpl op0,op1
20797 * sbbl dest,dest
20798 * [addl dest, ct]
20799 *
20800 * Size 5 - 8.
20801 */
20806 }
20808 {
20809 /*
20810 * cmpl op0,op1
20811 * sbbl dest,dest
20812 * orl $ct, dest
20813 *
20814 * Size 8.
20815 */
20819 }
20821 {
20822 /*
20823 * cmpl op0,op1
20824 * sbbl dest,dest
20825 * notl dest
20826 * [addl dest, cf]
20827 *
20828 * Size 8 - 11.
20829 */
20835 }
20836 else
20837 {
20838 /*
20839 * cmpl op0,op1
20840 * sbbl dest,dest
20841 * [notl dest]
20842 * andl cf - ct, dest
20843 * [addl dest, ct]
20844 *
20845 * Size 8 - 11.
20846 */
20849 {
20853 }
20863 }
20869 }
20872 {
20877 {
20880 /* We may be reversing unordered compare to normal compare, that
20881 is not valid in general (we may convert non-trapping condition
20882 to trapping one), however on i386 we currently emit all
20883 comparisons unordered. */
20885 }
20886 else
20889 {
20893 }
20894 }
20899 {
20904 {
20909 }
20910 }
20912 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20916 {
20917 /* If lea code below could be used, only optimize
20918 if it results in a 2 insn sequence. */
20924 {
20925 /*
20926 * notl op1 (if necessary)
20927 * sarl $31, op1
20928 * orl cf, op1
20929 */
20931 {
20935 }
20946 }
20947 }
20955 {
20956 /*
20957 * xorl dest,dest
20958 * cmpl op1,op2
20959 * setcc dest
20960 * lea cf(dest*(ct-cf)),dest
20961 *
20962 * Size 14.
20963 *
20964 * This also catches the degenerate setcc-only case.
20965 */
20967 rtx tmp;
20973 /* On x86_64 the lea instruction operates on Pmode, so we need
20974 to get arithmetics done in proper mode to match. */
20977 else
20978 {
20979 rtx out1;
20982 nops++;
20984 {
20986 nops++;
20987 }
20988 }
20990 {
20992 nops++;
20993 }
20995 {
20998 else
21000 }
21005 }
21007 /*
21008 * General case: Jumpful:
21009 * xorl dest,dest cmpl op1, op2
21010 * cmpl op1, op2 movl ct, dest
21011 * setcc dest jcc 1f
21012 * decl dest movl cf, dest
21013 * andl (cf-ct),dest 1:
21014 * addl ct,dest
21015 *
21016 * Size 20. Size 14.
21017 *
21018 * This is reasonably steep, but branch mispredict costs are
21019 * high on modern cpus, so consider failing only if optimizing
21020 * for space.
21021 */
21026 {
21028 {
21033 {
21036 /* We may be reversing unordered compare to normal compare,
21037 that is not valid in general (we may convert non-trapping
21038 condition to trapping one), however on i386 we currently
21039 emit all comparisons unordered. */
21041 }
21042 else
21043 {
21047 }
21050 {
21054 }
21055 }
21058 {
21059 /* notl op1 (if needed)
21060 sarl $31, op1
21061 andl (cf-ct), op1
21062 addl ct, op1
21064 For x < 0 (resp. x <= -1) there will be no notl,
21065 so if possible swap the constants to get rid of the
21066 complement.
21067 True/false will be -1/0 while code below (store flag
21068 followed by decrement) is 0/-1, so the constants need
21069 to be exchanged once more. */
21072 {
21075 }
21076 else
21080 }
21081 else
21082 {
21086 constm1_rtx,
21088 }
21100 }
21101 }
21104 {
21105 /* Try a few things more with specific constants and a variable. */
21107 optab op;
21113 /* If one of the two operands is an interesting constant, load a
21114 constant with the above and mask it in with a logical operation. */
21117 {
21123 else
21125 }
21127 {
21133 else
21135 }
21136 else
21143 /* Recurse to get the constant loaded. */
21147 /* Mask in the interesting variable. */
21149 OPTAB_WIDEN);
21154 }
21156 /*
21157 * For comparison with above,
21158 *
21159 * movl cf,dest
21160 * movl ct,tmp
21161 * cmpl op1,op2
21162 * cmovcc tmp,dest
21163 *
21164 * Size 15.
21165 */
21187 }
21189 /* Swap, force into registers, or otherwise massage the two operands
21190 to an sse comparison with a mask result. Thus we differ a bit from
21191 ix86_prepare_fp_compare_args which expects to produce a flags result.
21193 The DEST operand exists to help determine whether to commute commutative
21194 operators. The POP0/POP1 operands are updated in place. The new
21195 comparison code is returned, or UNKNOWN if not implementable. */
21197 static enum rtx_code
21200 {
21202 {
21205 /* AVX supports all the needed comparisons. */
21208 /* We have no LTGT as an operator. We could implement it with
21209 NE & ORDERED, but this requires an extra temporary. It's
21210 not clear that it's worth it. */
21217 /* These are supported directly. */
21224 /* AVX has 3 operand comparisons, no need to swap anything. */
21227 /* For commutative operators, try to canonicalize the destination
21228 operand to be first in the comparison - this helps reload to
21229 avoid extra moves. */
21232 /* FALLTHRU */
21238 /* These are not supported directly before AVX, and furthermore
21239 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
21240 comparison operands to transform into something that is
21241 supported. */
21248 }
21251 }
21253 /* Detect conditional moves that exactly match min/max operational
21254 semantics. Note that this is IEEE safe, as long as we don't
21255 interchange the operands.
21257 Returns FALSE if this conditional move doesn't match a MIN/MAX,
21258 and TRUE if the operation is successful and instructions are emitted. */
21260 static bool
21263 {
21264 machine_mode mode;
21266 rtx tmp;
21269 ;
21272 else
21279 else
21284 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
21285 but MODE may be a vector mode and thus not appropriate. */
21287 {
21289 rtvec v;
21294 }
21295 else
21296 {
21299 }
21303 }
21305 /* Expand an sse vector comparison. Return the register with the result. */
21307 static rtx
21310 {
21314 /* In general case result of comparison can differ from operands' type. */
21315 machine_mode cmp_mode;
21317 /* In AVX512F the result of comparison is an integer mask. */
21319 rtx x;
21322 {
21327 }
21328 else
21341 /* Compare patterns for int modes are unspec in AVX512F only. */
21343 {
21347 {
21364 }
21367 {
21370 }
21371 }
21375 {
21378 }
21379 else
21383 }
21385 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
21386 operations. This is used for both scalar and vector conditional moves. */
21388 static void
21390 {
21394 /* In AVX512F the result of comparison is an integer mask. */
21402 {
21404 }
21407 {
21411 }
21414 {
21419 }
21422 {
21426 }
21429 {
21436 op_true,
21437 op_false)));
21438 }
21439 else
21440 {
21450 {
21464 {
21471 }
21486 {
21493 }
21517 }
21520 {
21524 }
21525 else
21526 {
21532 else
21544 }
21545 }
21546 }
21548 /* Expand a floating-point conditional move. Return true if successful. */
21550 bool
21552 {
21560 {
21561 machine_mode cmode;
21563 /* Since we've no cmove for sse registers, don't force bad register
21564 allocation just to gain access to it. Deny movcc when the
21565 comparison mode doesn't match the move mode. */
21584 }
21591 /* The floating point conditional move instructions don't directly
21592 support conditions resulting from a signed integer comparison. */
21596 {
21601 }
21608 }
21610 /* Expand a floating-point vector conditional move; a vcond operation
21611 rather than a movcc operation. */
21613 bool
21615 {
21617 rtx cmp;
21622 {
21623 rtx temp;
21625 {
21642 }
21644 OPTAB_DIRECT);
21647 }
21657 }
21659 /* Expand a signed/unsigned integral vector conditional move. */
21661 bool
21663 {
21673 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21674 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21683 {
21687 {
21693 }
21696 {
21702 }
21703 }
21712 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21716 ;
21717 else
21718 {
21719 /* Canonicalize the comparison to EQ, GT, GTU. */
21721 {
21738 /* FALLTHRU */
21748 }
21750 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21752 {
21754 {
21756 /* SSE4.1 supports EQ. */
21763 /* SSE4.2 supports GT/GTU. */
21770 }
21771 }
21773 /* Unsigned parallel compare is not supported by the hardware.
21774 Play some tricks to turn this into a signed comparison
21775 against 0. */
21777 {
21781 {
21788 {
21793 {
21802 }
21803 /* Subtract (-(INT MAX) - 1) from both operands to make
21804 them signed. */
21815 }
21824 /* Perform a parallel unsigned saturating subtraction. */
21836 }
21837 }
21838 }
21840 /* Allow the comparison to be done in one mode, but the movcc to
21841 happen in another mode. */
21843 {
21846 }
21847 else
21848 {
21854 }
21859 }
21861 /* AVX512F does support 64-byte integer vector operations,
21862 thus the longest vector we are faced with is V64QImode. */
21863 #define MAX_VECT_LEN 64
21865 struct expand_vec_perm_d
21866 {
21869 machine_mode vmode;
21873 };
21875 static bool
21878 {
21879 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21880 expander, so args are either in d, or in op0, op1 etc. */
21886 {
21917 {
21920 }
21924 {
21927 }
21931 {
21934 }
21950 {
21953 }
21957 {
21960 }
21964 {
21967 }
21971 }
21976 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21977 expander, so args are either in d, or in op0, op1 etc. */
21979 {
21987 }
21991 }
21993 /* Expand a variable vector permutation. */
21995 void
21997 {
22008 /* Number of elements in the vector. */
22017 {
22019 {
22020 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
22021 an constant shuffle operand. With a tiny bit of effort we can
22022 use VPERMD instead. A re-interpretation stall for V4DFmode is
22023 unfortunate but there's no avoiding it.
22024 Similarly for V16HImode we don't have instructions for variable
22025 shuffling, while for V32QImode we can use after preparing suitable
22026 masks vpshufb; vpshufb; vpermq; vpor. */
22029 {
22033 }
22034 else
22035 {
22039 }
22042 /* Replicate the low bits of the V4DImode mask into V8SImode:
22043 mask = { A B C D }
22044 t1 = { A A B B C C D D }. */
22052 else
22055 /* Multiply the shuffle indicies by two. */
22057 OPTAB_DIRECT);
22059 /* Add one to the odd shuffle indicies:
22060 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
22062 {
22065 }
22069 OPTAB_DIRECT);
22071 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
22076 }
22079 {
22081 /* The VPERMD and VPERMPS instructions already properly ignore
22082 the high bits of the shuffle elements. No need for us to
22083 perform an AND ourselves. */
22085 {
22090 }
22091 else
22092 {
22098 }
22105 else
22106 {
22112 }
22116 /* By combining the two 128-bit input vectors into one 256-bit
22117 input vector, we can use VPERMD and VPERMPS for the full
22118 two-operand shuffle. */
22150 /* From mask create two adjusted masks, which contain the same
22151 bits as mask in the low 7 bits of each vector element.
22152 The first mask will have the most significant bit clear
22153 if it requests element from the same 128-bit lane
22154 and MSB set if it requests element from the other 128-bit lane.
22155 The second mask will have the opposite values of the MSB,
22156 and additionally will have its 128-bit lanes swapped.
22157 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
22158 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
22159 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
22160 stands for other 12 bytes. */
22161 /* The bit whether element is from the same lane or the other
22162 lane is bit 4, so shift it up by 3 to the MSB position. */
22166 /* Clear MSB bits from the mask just in case it had them set. */
22168 /* After this t1 will have MSB set for elements from other lane. */
22170 /* Clear bits other than MSB. */
22172 /* Or in the lower bits from mask into t3. */
22174 /* And invert MSB bits in t1, so MSB is set for elements from the same
22175 lane. */
22177 /* Swap 128-bit lanes in t3. */
22182 /* And or in the lower bits from mask into t1. */
22185 {
22186 /* Each of these shuffles will put 0s in places where
22187 element from the other 128-bit lane is needed, otherwise
22188 will shuffle in the requested value. */
22192 /* For t3 the 128-bit lanes are swapped again. */
22197 /* And oring both together leads to the result. */
22204 }
22207 /* Similarly to the above one_operand_shuffle code,
22208 just for repeated twice for each operand. merge_two:
22209 code will merge the two results together. */
22233 }
22234 }
22237 {
22238 /* The XOP VPPERM insn supports three inputs. By ignoring the
22239 one_operand_shuffle special case, we avoid creating another
22240 set of constant vectors in memory. */
22243 /* mask = mask & {2*w-1, ...} */
22245 }
22246 else
22247 {
22248 /* mask = mask & {w-1, ...} */
22250 }
22258 /* For non-QImode operations, convert the word permutation control
22259 into a byte permutation control. */
22261 {
22266 /* Convert mask to vector of chars. */
22269 /* Replicate each of the input bytes into byte positions:
22270 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
22271 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
22272 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
22279 else
22282 /* Convert it into the byte positions by doing
22283 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
22289 }
22291 /* The actual shuffle operations all operate on V16QImode. */
22296 {
22303 }
22305 {
22312 }
22313 else
22314 {
22318 /* Shuffle the two input vectors independently. */
22324 merge_two:
22325 /* Then merge them together. The key is whether any given control
22326 element contained a bit set that indicates the second word. */
22330 {
22331 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
22332 more shuffle to convert the V2DI input mask into a V4SI
22333 input mask. At which point the masking that expand_int_vcond
22334 will work as desired. */
22342 }
22364 }
22365 }
22367 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
22368 true if we should do zero extension, else sign extension. HIGH_P is
22369 true if we want the N/2 high elements, else the low elements. */
22371 void
22373 {
22375 rtx tmp;
22378 {
22384 {
22388 else
22391 extract
22397 else
22400 extract
22406 else
22409 extract
22415 else
22418 extract
22424 else
22427 extract
22433 else
22436 extract
22442 else
22448 else
22454 else
22459 }
22462 {
22465 }
22467 {
22468 /* Shift higher 8 bytes to lower 8 bytes. */
22473 }
22474 else
22478 }
22479 else
22480 {
22484 {
22488 else
22494 else
22500 else
22505 }
22509 else
22516 }
22517 }
22519 /* Expand conditional increment or decrement using adb/sbb instructions.
22520 The default case using setcc followed by the conditional move can be
22521 done by generic code. */
22522 bool
22524 {
22526 rtx flags;
22528 rtx compare_op;
22531 machine_mode mode;
22546 {
22549 }
22552 {
22556 reverse_condition_maybe_unordered
22558 else
22560 }
22564 /* Construct either adc or sbb insn. */
22566 {
22568 {
22583 }
22584 }
22585 else
22586 {
22588 {
22603 }
22604 }
22608 }
22611 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22612 but works for floating pointer parameters and nonoffsetable memories.
22613 For pushes, it returns just stack offsets; the values will be saved
22614 in the right order. Maximally three parts are generated. */
22616 static int
22618 {
22623 else
22629 /* Optimize constant pool reference to immediates. This is used by fp
22630 moves, that force all constants to memory to allow combining. */
22632 {
22636 }
22639 {
22640 /* The only non-offsetable memories we handle are pushes. */
22649 }
22652 {
22654 /* Caution: if we looked through a constant pool memory above,
22655 the operand may actually have a different mode now. That's
22656 ok, since we want to pun this all the way back to an integer. */
22660 }
22663 {
22666 else
22667 {
22671 {
22675 }
22677 {
22682 }
22684 {
22685 REAL_VALUE_TYPE r;
22690 {
22697 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22698 long double may not be 80-bit. */
22707 }
22710 }
22711 else
22713 }
22714 }
22715 else
22716 {
22720 {
22723 {
22727 }
22729 {
22733 }
22735 {
22736 REAL_VALUE_TYPE r;
22742 /* real_to_target puts 32-bit pieces in each long. */
22744 gen_int_mode
22747 DImode);
22751 else
22753 gen_int_mode
22756 DImode);
22757 }
22758 else
22760 }
22761 }
22764 }
22766 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22767 Return false when normal moves are needed; true when all required
22768 insns have been emitted. Operands 2-4 contain the input values
22769 int the correct order; operands 5-7 contain the output values. */
22771 void
22773 {
22781 /* The DFmode expanders may ask us to move double.
22782 For 64bit target this is single move. By hiding the fact
22783 here we simplify i386.md splitters. */
22785 {
22786 /* Optimize constant pool reference to immediates. This is used by
22787 fp moves, that force all constants to memory to allow combining. */
22794 {
22797 }
22798 else
22803 }
22805 /* The only non-offsettable memory we handle is push. */
22808 else
22815 /* When emitting push, take care for source operands on the stack. */
22818 {
22821 /* Compensate for the stack decrement by 4. */
22826 /* src_base refers to the stack pointer and is
22827 automatically decreased by emitted push. */
22831 }
22833 /* We need to do copy in the right order in case an address register
22834 of the source overlaps the destination. */
22836 {
22837 rtx tmp;
22840 {
22844 collisions++;
22845 }
22847 /* Collision in the middle part can be handled by reordering. */
22849 {
22852 }
22856 {
22858 {
22861 }
22862 else
22863 {
22866 }
22867 }
22869 /* If there are more collisions, we can't handle it by reordering.
22870 Do an lea to the last part and use only one colliding move. */
22872 {
22879 /* Handle the case when the last part isn't valid for lea.
22880 Happens in 64-bit mode storing the 12-byte XFmode. */
22886 {
22891 {
22892 /* It is not valid to use %gs: or %fs: in
22893 lea though, so we need to remove it from the
22894 address used for lea and add it to each individual
22895 memory loads instead. */
22899 {
22901 {
22907 {
22911 }
22912 }
22916 }
22918 }
22919 }
22925 {
22930 }
22931 }
22932 }
22935 {
22937 {
22939 {
22944 }
22946 {
22949 }
22950 }
22951 else
22952 {
22953 /* In 64bit mode we don't have 32bit push available. In case this is
22954 register, it is OK - we will just use larger counterpart. We also
22955 retype memory - these comes from attempt to avoid REX prefix on
22956 moving of second half of TFmode value. */
22958 {
22960 {
22971 }
22975 }
22976 }
22980 }
22982 /* Choose correct order to not overwrite the source before it is copied. */
22992 {
22994 {
22997 }
22998 }
22999 else
23000 {
23002 {
23005 }
23006 }
23008 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
23010 {
23019 }
23025 }
23027 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
23028 left shift by a constant, either using a single shift or
23029 a sequence of add instructions. */
23031 static void
23033 {
23039 {
23043 }
23044 else
23045 {
23048 }
23049 }
23051 void
23053 {
23062 {
23067 {
23073 }
23074 else
23075 {
23083 }
23085 }
23092 {
23093 /* Assuming we've chosen a QImode capable registers, then 1 << N
23094 can be done with two 32/64-bit shifts, no branches, no cmoves. */
23096 {
23112 }
23114 /* Otherwise, we can get the same results by manually performing
23115 a bit extract operation on bit 5/6, and then performing the two
23116 shifts. The two methods of getting 0/1 into low/high are exactly
23117 the same size. Avoiding the shift in the bit extract case helps
23118 pentium4 a bit; no one else seems to care much either way. */
23119 else
23120 {
23121 machine_mode half_mode;
23125 HOST_WIDE_INT bits;
23126 rtx x;
23129 {
23135 }
23136 else
23137 {
23143 }
23147 else
23155 }
23160 }
23163 {
23164 /* For -1 << N, we can avoid the shld instruction, because we
23165 know that we're shifting 0...31/63 ones into a -1. */
23169 else
23171 }
23172 else
23173 {
23181 }
23186 {
23192 }
23193 else
23194 {
23199 }
23200 }
23202 void
23204 {
23214 {
23219 {
23225 }
23227 {
23236 }
23237 else
23238 {
23246 }
23247 }
23248 else
23249 {
23261 {
23269 scratch));
23270 }
23271 else
23272 {
23277 }
23278 }
23279 }
23281 void
23283 {
23293 {
23298 {
23305 }
23306 else
23307 {
23315 }
23316 }
23317 else
23318 {
23330 {
23336 scratch));
23337 }
23338 else
23339 {
23344 }
23345 }
23346 }
23348 /* Predict just emitted jump instruction to be taken with probability PROB. */
23349 static void
23351 {
23355 }
23357 /* Helper function for the string operations below. Dest VARIABLE whether
23358 it is aligned to VALUE bytes. If true, jump to the label. */
23361 {
23366 else
23372 else
23375 }
23377 /* Adjust COUNTER by the VALUE. */
23378 static void
23380 {
23385 }
23387 /* Zero extend possibly SImode EXP to Pmode register. */
23388 rtx
23390 {
23392 }
23394 /* Divide COUNTREG by SCALE. */
23395 static rtx
23397 {
23398 rtx sc;
23410 }
23412 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
23413 DImode for constant loop counts. */
23415 static machine_mode
23417 {
23425 }
23427 /* Copy the address to a Pmode register. This is used for x32 to
23428 truncate DImode TLS address to a SImode register. */
23430 static rtx
23432 {
23433 rtx reg;
23435 {
23439 }
23440 else
23441 {
23446 }
23447 }
23449 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
23450 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
23451 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
23452 memory by VALUE (supposed to be in MODE).
23454 The size is rounded down to whole number of chunk size moved at once.
23455 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
23458 static void
23463 {
23470 rtx size;
23479 /* Those two should combine. */
23481 {
23485 }
23492 /* This assert could be relaxed - in this case we'll need to compute
23493 smallest power of two, containing in PIECE_SIZE_N and pass it to
23494 offset_address. */
23500 {
23504 /* When unrolling for chips that reorder memory reads and writes,
23505 we can save registers by using single temporary.
23506 Also using 4 temporaries is overkill in 32bit mode. */
23508 {
23510 {
23512 {
23513 destmem =
23515 srcmem =
23517 }
23519 }
23520 }
23521 else
23522 {
23526 {
23529 {
23530 srcmem =
23532 }
23534 }
23536 {
23538 {
23539 destmem =
23541 }
23543 }
23544 }
23545 }
23546 else
23548 {
23550 destmem =
23553 }
23563 {
23569 else
23571 }
23572 else
23580 {
23585 }
23587 }
23589 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
23590 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
23591 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
23592 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
23593 ORIG_VALUE is the original value passed to memset to fill the memory with.
23594 Other arguments have same meaning as for previous function. */
23596 static void
23599 rtx count,
23601 {
23602 rtx destexp;
23603 rtx srcexp;
23604 rtx countreg;
23605 HOST_WIDE_INT rounded_count;
23607 /* If possible, it is shorter to use rep movs.
23608 TODO: Maybe it is better to move this logic to decide_alg. */
23619 {
23623 }
23624 else
23627 {
23632 }
23637 {
23640 }
23641 else
23642 {
23646 {
23650 }
23651 else
23654 {
23659 }
23660 else
23661 {
23664 }
23667 }
23668 }
23670 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23671 DESTMEM.
23672 SRC is passed by pointer to be updated on return.
23673 Return value is updated DST. */
23674 static rtx
23676 HOST_WIDE_INT size_to_move)
23677 {
23680 machine_mode move_mode;
23683 /* Find the widest mode in which we could perform moves.
23684 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23685 it until move of such size is supported. */
23690 {
23694 }
23696 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23697 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23699 {
23704 {
23708 }
23709 }
23715 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23719 {
23720 /* We move from memory to memory, so we'll need to do it via
23721 a temporary register. */
23732 piece_size);
23734 piece_size);
23735 }
23737 /* Update DST and SRC rtx. */
23740 }
23742 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23743 static void
23746 {
23749 {
23754 /* For now MAX_SIZE should be a power of 2. This assert could be
23755 relaxed, but it'll require a bit more complicated epilogue
23756 expanding. */
23759 {
23762 }
23764 }
23766 {
23772 }
23774 /* When there are stringops, we can cheaply increase dest and src pointers.
23775 Otherwise we save code size by maintaining offset (zero is readily
23776 available from preceding rep operation) and using x86 addressing modes.
23777 */
23779 {
23781 {
23788 }
23790 {
23797 }
23799 {
23806 }
23807 }
23808 else
23809 {
23811 rtx tmp;
23814 {
23825 }
23827 {
23840 }
23842 {
23851 }
23852 }
23853 }
23855 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23856 with value PROMOTED_VAL.
23857 SRC is passed by pointer to be updated on return.
23858 Return value is updated DST. */
23859 static rtx
23861 HOST_WIDE_INT size_to_move)
23862 {
23865 machine_mode move_mode;
23868 /* Find the widest mode in which we could perform moves.
23869 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23870 it until move of such size is supported. */
23875 {
23878 }
23885 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23889 {
23891 {
23894 piece_size);
23896 }
23904 piece_size);
23905 }
23907 /* Update DST rtx. */
23909 }
23910 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23911 static void
23914 {
23915 count =
23921 }
23923 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23924 static void
23927 {
23928 rtx dest;
23931 {
23936 /* For now MAX_SIZE should be a power of 2. This assert could be
23937 relaxed, but it'll require a bit more complicated epilogue
23938 expanding. */
23941 {
23943 {
23946 else
23948 }
23949 }
23951 }
23953 {
23956 }
23958 {
23961 {
23966 }
23967 else
23968 {
23977 }
23980 }
23982 {
23985 {
23988 }
23989 else
23990 {
23995 }
23998 }
24000 {
24006 }
24008 {
24014 }
24016 {
24022 }
24023 }
24025 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
24026 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
24027 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
24028 ignored.
24029 Return value is updated DESTMEM. */
24030 static rtx
24035 {
24038 {
24040 {
24043 {
24046 else
24048 }
24049 else
24055 }
24056 }
24058 }
24060 /* Test if COUNT&SIZE is nonzero and if so, expand movme
24061 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
24062 and jump to DONE_LABEL. */
24063 static void
24069 {
24072 rtx modesize;
24075 /* If we do not have vector value to copy, we must reduce size. */
24077 {
24079 {
24084 }
24085 else
24087 }
24088 else
24089 {
24090 /* Choose appropriate vector mode. */
24096 }
24101 {
24104 else
24105 {
24108 }
24110 }
24116 {
24120 }
24122 {
24125 else
24126 {
24129 }
24131 }
24137 }
24139 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
24140 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
24141 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
24142 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
24143 DONE_LABEL is a label after the whole copying sequence. The label is created
24144 on demand if *DONE_LABEL is NULL.
24145 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
24146 bounds after the initial copies.
24148 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
24149 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
24150 we will dispatch to a library call for large blocks.
24152 In pseudocode we do:
24154 if (COUNT < SIZE)
24155 {
24156 Assume that SIZE is 4. Bigger sizes are handled analogously
24157 if (COUNT & 4)
24158 {
24159 copy 4 bytes from SRCPTR to DESTPTR
24160 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
24161 goto done_label
24162 }
24163 if (!COUNT)
24164 goto done_label;
24165 copy 1 byte from SRCPTR to DESTPTR
24166 if (COUNT & 2)
24167 {
24168 copy 2 bytes from SRCPTR to DESTPTR
24169 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
24170 }
24171 }
24172 else
24173 {
24174 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
24175 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
24177 OLD_DESPTR = DESTPTR;
24178 Align DESTPTR up to DESIRED_ALIGN
24179 SRCPTR += DESTPTR - OLD_DESTPTR
24180 COUNT -= DEST_PTR - OLD_DESTPTR
24181 if (DYNAMIC_CHECK)
24182 Round COUNT down to multiple of SIZE
24183 << optional caller supplied zero size guard is here >>
24184 << optional caller suppplied dynamic check is here >>
24185 << caller supplied main copy loop is here >>
24186 }
24187 done_label:
24188 */
24189 static void
24192 machine_mode mode,
24202 {
24205 rtx modesize;
24207 rtx mode_value;
24209 /* Chose proper value to copy. */
24212 else
24216 /* See if block is big or small, handle small blocks. */
24218 {
24229 /* Handle sizes > 3. */
24236 /* Nothing to copy? Jump to DONE_LABEL if so */
24240 /* Do a byte copy. */
24244 else
24245 {
24248 }
24250 /* Handle sizes 2 and 3. */
24257 else
24258 {
24263 }
24269 }
24270 else
24274 /* Start memcpy for COUNT >= SIZE. */
24276 {
24279 }
24281 /* Copy first desired_align bytes. */
24287 {
24290 else
24291 {
24294 }
24297 }
24300 /* Copy last SIZE bytes. */
24307 else
24308 {
24314 }
24316 {
24320 else
24321 {
24324 }
24325 }
24327 /* Align destination. */
24329 {
24333 /* Align destptr up, place it to new register. */
24342 /* See how many bytes we skipped. */
24346 /* Adjust srcptr and count. */
24352 /* We copied at most size + prolog_size. */
24355 else
24358 /* Our loops always round down the bock size, but for dispatch to library
24359 we need precise value. */
24363 }
24364 else
24365 {
24367 /* Decrease count, so we won't end up copying last word twice. */
24371 else
24375 }
24376 }
24379 /* This function is like the previous one, except here we know how many bytes
24380 need to be copied. That allows us to update alignment not only of DST, which
24381 is returned, but also of SRC, which is passed as a pointer for that
24382 reason. */
24383 static rtx
24388 {
24396 {
24400 }
24405 {
24407 {
24409 {
24412 else
24414 }
24415 else
24418 }
24419 }
24426 {
24432 {
24435 {
24439 }
24444 }
24448 }
24451 }
24453 /* Return true if ALG can be used in current context.
24454 Assume we expand memset if MEMSET is true. */
24455 static bool
24457 {
24462 /* Algorithms using the rep prefix want at least edi and ecx;
24463 additionally, memset wants eax and memcpy wants esi. Don't
24464 consider such algorithms if the user has appropriated those
24465 registers for their own purposes. */
24472 }
24474 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
24475 static enum stringop_alg
24479 {
24490 /* Even if the string operation call is cold, we still might spend a lot
24491 of time processing large blocks. */
24497 else
24503 else
24506 /* See maximal size for user defined algorithm. */
24508 {
24515 }
24517 /* If expected size is not known but max size is small enough
24518 so inline version is a win, set expected size into
24519 the range. */
24524 /* If user specified the algorithm, honnor it if possible. */
24528 /* rep; movq or rep; movl is the smallest variant. */
24530 {
24535 else
24538 }
24539 /* Very tiny blocks are best handled via the loop, REP is expensive to
24540 setup. */
24544 {
24548 {
24549 /* We get here if the algorithms that were not libcall-based
24550 were rep-prefix based and we are unable to use rep prefixes
24551 based on global register usage. Break out of the loop and
24552 use the heuristic below. */
24556 {
24560 {
24563 }
24564 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
24565 last non-libcall inline algorithm. */
24567 {
24568 /* When the current size is best to be copied by a libcall,
24569 but we are still forced to inline, run the heuristic below
24570 that will pick code for medium sized blocks. */
24572 {
24575 }
24578 }
24580 {
24583 }
24584 }
24585 }
24586 }
24587 /* When asked to inline the call anyway, try to pick meaningful choice.
24588 We look for maximal size of block that is faster to copy by hand and
24589 take blocks of at most of that size guessing that average size will
24590 be roughly half of the block.
24592 If this turns out to be bad, we might simply specify the preferred
24593 choice in ix86_costs. */
24597 {
24600 /* If there aren't any usable algorithms, then recursing on
24601 smaller sizes isn't going to find anything. Just return the
24602 simple byte-at-a-time copy loop. */
24604 {
24605 /* Pick something reasonable. */
24609 }
24617 else
24620 }
24623 }
24625 /* Decide on alignment. We know that the operand is already aligned to ALIGN
24626 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
24627 static int
24631 machine_mode move_mode)
24632 {
24643 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
24644 copying whole cacheline at once. */
24657 }
24660 /* Helper function for memcpy. For QImode value 0xXY produce
24661 0xXYXYXYXY of wide specified by MODE. This is essentially
24662 a * 0x10101010, but we can do slightly better than
24663 synth_mult by unwinding the sequence by hand on CPUs with
24664 slow multiply. */
24665 static rtx
24667 {
24669 rtx tmp;
24676 {
24684 }
24693 nops--;
24698 {
24702 OPTAB_DIRECT);
24703 }
24704 else
24705 {
24711 else
24713 else
24714 {
24717 reg =
24719 }
24729 }
24730 }
24732 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24733 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24734 alignment from ALIGN to DESIRED_ALIGN. */
24735 static rtx
24738 {
24739 rtx promoted_val;
24748 else
24752 }
24754 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24755 operations when profitable. The code depends upon architecture, block size
24756 and alignment, but always has one of the following overall structures:
24758 Aligned move sequence:
24760 1) Prologue guard: Conditional that jumps up to epilogues for small
24761 blocks that can be handled by epilogue alone. This is faster
24762 but also needed for correctness, since prologue assume the block
24763 is larger than the desired alignment.
24765 Optional dynamic check for size and libcall for large
24766 blocks is emitted here too, with -minline-stringops-dynamically.
24768 2) Prologue: copy first few bytes in order to get destination
24769 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24770 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24771 copied. We emit either a jump tree on power of two sized
24772 blocks, or a byte loop.
24774 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24775 with specified algorithm.
24777 4) Epilogue: code copying tail of the block that is too small to be
24778 handled by main body (or up to size guarded by prologue guard).
24780 Misaligned move sequence
24782 1) missaligned move prologue/epilogue containing:
24783 a) Prologue handling small memory blocks and jumping to done_label
24784 (skipped if blocks are known to be large enough)
24785 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24786 needed by single possibly misaligned move
24787 (skipped if alignment is not needed)
24788 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24790 2) Zero size guard dispatching to done_label, if needed
24792 3) dispatch to library call, if needed,
24794 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24795 with specified algorithm. */
24796 bool
24802 {
24803 rtx destreg;
24806 rtx tmp;
24822 /* TODO: Once value ranges are available, fill in proper data. */
24830 /* i386 can do misaligned access on reasonably increased cost. */
24834 /* ALIGN is the minimum of destination and source alignment, but we care here
24835 just about destination alignment. */
24841 {
24844 /* When COUNT is 0, there is nothing to do. */
24847 }
24848 else
24849 {
24858 }
24860 /* Make sure we don't need to care about overflow later on. */
24864 /* Step 0: Decide on preferred algorithm, desired alignment and
24865 size of chunks to be copied by main loop. */
24867 issetmem,
24874 /* For now vector-version of memset is generated only for memory zeroing, as
24875 creating of promoted vector value is very cheap in this case. */
24888 {
24907 /* Find the widest supported mode. */
24913 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24914 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24916 {
24921 }
24933 }
24941 /* Step 1: Prologue guard. */
24943 /* Alignment code needs count to be in register. */
24945 {
24948 {
24949 align_bytes
24953 else
24955 }
24958 }
24961 /* Misaligned move sequences handle both prologue and epilogue at once.
24962 Default code generation results in a smaller code for large alignments
24963 and also avoids redundant job when sizes are known precisely. */
24964 misaligned_prologue_used
24965 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
24971 /* Do the cheap promotion to allow better CSE across the
24972 main loop and epilogue (ie one load of the big constant in the
24973 front of all code.
24974 For now the misaligned move sequences do not have fast path
24975 without broadcasting. */
24977 {
24979 {
24985 }
24986 else
24987 {
24990 }
24991 }
24992 /* Misaligned move sequences handles both prologues and epilogues at once.
24993 Default code generation results in smaller code for large alignments and
24994 also avoids redundant job when sizes are known precisely. */
24996 {
24997 /* Misaligned move prologue handled small blocks by itself. */
24998 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
25003 desired_align < align
25012 {
25013 /* It is possible that we copied enough so the main loop will not
25014 execute. */
25024 else
25026 }
25027 }
25028 /* Ensure that alignment prologue won't copy past end of block. */
25030 {
25032 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
25033 Make sure it is power of 2. */
25036 /* To improve performance of small blocks, we jump around the VAL
25037 promoting mode. This mean that if the promoted VAL is not constant,
25038 we might not use it in the epilogue and have to use byte
25039 loop variant. */
25044 {
25045 /* If main algorithm works on QImode, no epilogue is needed.
25046 For small sizes just don't align anything. */
25049 else
25051 }
25054 {
25061 else
25063 }
25064 }
25066 /* Emit code to decide on runtime whether library call or inline should be
25067 used. */
25069 {
25071 {
25073 {
25077 }
25078 }
25079 else
25080 {
25090 else
25094 }
25095 }
25097 /* Step 2: Alignment prologue. */
25098 /* Do the expensive promotion once we branched off the small blocks. */
25104 {
25106 {
25107 /* Except for the first move in prologue, we no longer know
25108 constant offset in aliasing info. It don't seems to worth
25109 the pain to maintain it for the first move, so throw away
25110 the info early. */
25117 issetmem);
25118 /* At most desired_align - align bytes are copied. */
25121 else
25123 }
25124 else
25125 {
25126 /* If we know how many bytes need to be stored before dst is
25127 sufficiently aligned, maintain aliasing info accurately. */
25129 srcreg,
25130 promoted_val,
25131 vec_promoted_val,
25132 desired_align,
25133 align_bytes,
25134 issetmem);
25141 }
25143 && !min_size
25148 {
25149 /* It is possible that we copied enough so the main loop will not
25150 execute. */
25160 else
25162 }
25163 }
25165 {
25172 }
25176 /* Step 3: Main loop. */
25179 {
25202 }
25203 /* Adjust properly the offset of src and dest memory for aliasing. */
25205 {
25211 }
25212 else
25213 {
25217 }
25219 /* Step 4: Epilogue to copy the remaining bytes. */
25220 epilogue:
25222 {
25223 /* When the main loop is done, COUNT_EXP might hold original count,
25224 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
25225 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
25226 bytes. Compensate if needed. */
25229 {
25230 tmp =
25233 OPTAB_DIRECT);
25236 }
25239 }
25242 {
25245 epilogue_size_needed);
25246 else
25247 {
25251 epilogue_size_needed);
25252 else
25254 epilogue_size_needed);
25255 }
25256 }
25260 }
25263 /* Expand the appropriate insns for doing strlen if not just doing
25264 repnz; scasb
25266 out = result, initialized with the start address
25267 align_rtx = alignment of the address.
25268 scratch = scratch register, initialized with the startaddress when
25269 not aligned, otherwise undefined
25271 This is just the body. It needs the initializations mentioned above and
25272 some address computing at the end. These things are done in i386.md. */
25274 static void
25276 {
25278 rtx tmp;
25283 rtx mem;
25286 rtx cmp;
25292 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
25294 /* Is there a known alignment and is it less than 4? */
25296 {
25299 /* Is there a known alignment and is it not 2? */
25301 {
25305 /* Leave just the 3 lower bits. */
25315 }
25316 else
25317 {
25318 /* Since the alignment is 2, we have to check 2 or 0 bytes;
25319 check if is aligned to 4 - byte. */
25326 }
25330 /* Now compare the bytes. */
25332 /* Compare the first n unaligned byte on a byte per byte basis. */
25336 /* Increment the address. */
25339 /* Not needed with an alignment of 2 */
25341 {
25345 end_0_label);
25350 }
25353 end_0_label);
25356 }
25358 /* Generate loop to check 4 bytes at a time. It is not a good idea to
25359 align this loop. It gives only huge programs, but does not help to
25360 speed up. */
25367 /* This formula yields a nonzero result iff one of the bytes is zero.
25368 This saves three branches inside loop and many cycles. */
25376 align_4_label);
25379 {
25385 /* If zero is not in the first two bytes, move two bytes forward. */
25391 reg,
25392 tmpreg)));
25393 /* Emit lea manually to avoid clobbering of flags. */
25400 reg2,
25401 out)));
25402 }
25403 else
25404 {
25406 /* Is zero in the first two bytes? */
25413 pc_rtx);
25417 /* Not in the first two. Move two bytes forward. */
25423 }
25425 /* Avoid branch in fixing the byte. */
25433 }
25435 /* Expand strlen. */
25437 bool
25439 {
25442 /* The generic case of strlen expander is long. Avoid it's
25443 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
25446 && !TARGET_INLINE_ALL_STRINGOPS
25456 {
25457 /* Well it seems that some optimizer does not combine a call like
25458 foo(strlen(bar), strlen(bar));
25459 when the move and the subtraction is done here. It does calculate
25460 the length just once when these instructions are done inside of
25461 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
25462 often used and I use one fewer register for the lifetime of
25463 output_strlen_unroll() this is better. */
25469 /* strlensi_unroll_1 returns the address of the zero at the end of
25470 the string, like memchr(), so compute the length by subtracting
25471 the start address. */
25473 }
25474 else
25475 {
25476 rtx unspec;
25478 /* Can't use this if the user has appropriated eax, ecx, or edi. */
25491 /* If .md starts supporting :P, this can be done in .md. */
25497 }
25499 }
25501 /* For given symbol (function) construct code to compute address of it's PLT
25502 entry in large x86-64 PIC model. */
25503 static rtx
25505 {
25518 }
25520 rtx
25522 rtx callarg2,
25524 {
25534 {
25535 #if TARGET_MACHO
25538 #endif
25539 }
25540 else
25541 {
25542 /* Static functions and indirect calls don't need the pic register. Also,
25543 check if PLT was explicitly avoided via no-plt or "noplt" attribute, making
25544 it an indirect call. */
25546 && (!TARGET_64BIT
25551 && flag_plt
25555 {
25559 pic_offset_table_rtx);
25560 }
25561 }
25563 /* Skip setting up RAX register for -mskip-rax-setup when there are no
25564 parameters passed in vector registers. */
25569 {
25573 }
25576 && !TARGET_PECOFF
25584 {
25587 }
25592 {
25593 /* We should add bounds as destination register in case
25594 pointer with bounds may be returned. */
25596 {
25600 {
25605 }
25606 else
25607 {
25611 }
25612 }
25615 }
25619 {
25623 }
25627 {
25628 int const cregs_size
25633 {
25638 }
25639 }
25648 }
25650 /* Return true if the function being called was marked with attribute "noplt"
25651 or using -fno-plt and we are compiling for non-PIC and x86_64. We need to
25652 handle the non-PIC case in the backend because there is no easy interface
25653 for the front-end to force non-PLT calls to use the GOT. This is currently
25654 used only with 64-bit ELF targets to call the function marked "noplt"
25655 indirectly. */
25657 static bool
25659 {
25673 }
25675 /* Output the assembly for a call instruction. */
25679 {
25685 {
25690 /* SEH epilogue detection requires the indirect branch case
25691 to include REX.W. */
25694 else
25699 }
25701 /* SEH unwinding can require an extra nop to be emitted in several
25702 circumstances. Determine if we have one of those. */
25704 {
25708 {
25709 /* If we get to another real insn, we don't need the nop. */
25713 /* If we get to the epilogue note, prevent a catch region from
25714 being adjacent to the standard epilogue sequence. If non-
25715 call-exceptions, we'll have done this during epilogue emission. */
25717 && !flag_non_call_exceptions
25719 {
25722 }
25723 }
25725 /* If we didn't find a real insn following the call, prevent the
25726 unwinder from looking into the next function. */
25729 }
25735 else
25744 }
25745 \f
25746 /* Clear stack slot assignments remembered from previous functions.
25747 This is called from INIT_EXPANDERS once before RTL is emitted for each
25748 function. */
25752 {
25760 }
25762 /* Return a MEM corresponding to a stack slot with mode MODE.
25763 Allocate a new slot if necessary.
25765 The RTL for a function can have several slots available: N is
25766 which slot to use. */
25768 rtx
25770 {
25787 }
25789 static void
25791 {
25797 }
25798 \f
25799 /* Check whether x86 address PARTS is a pc-relative address. */
25801 static bool
25803 {
25811 {
25813 {
25830 }
25831 }
25833 }
25835 /* Calculate the length of the memory address in the instruction encoding.
25836 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25837 or other prefixes. We never generate addr32 prefix for LEA insn. */
25839 int
25841 {
25858 /* If this is not LEA instruction, add the length of addr32 prefix. */
25863 len++;
25877 /* Rule of thumb:
25878 - esp as the base always wants an index,
25879 - ebp as the base always wants a displacement,
25880 - r12 as the base always wants an index,
25881 - r13 as the base always wants a displacement. */
25883 /* Register Indirect. */
25885 {
25886 /* esp (for its index) and ebp (for its displacement) need
25887 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25888 code. */
25895 len++;
25896 }
25898 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25899 is not disp32, but disp32(%rip), so for disp32
25900 SIB byte is needed, unless print_operand_address
25901 optimizes it into disp32(%rip) or (%rip) is implied
25902 by UNSPEC. */
25904 {
25907 len++;
25908 }
25909 else
25910 {
25911 /* Find the length of the displacement constant. */
25913 {
25916 else
25918 }
25919 /* ebp always wants a displacement. Similarly r13. */
25921 len++;
25923 /* An index requires the two-byte modrm form.... */
25925 /* ...like esp (or r12), which always wants an index. */
25929 len++;
25930 }
25933 }
25935 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25936 is set, expect that insn have 8bit immediate alternative. */
25937 int
25939 {
25945 {
25950 {
25953 {
25965 }
25967 {
25970 }
25971 }
25973 {
25983 /* Immediates for DImode instructions are encoded
25984 as 32bit sign extended values. */
25990 }
25991 }
25993 }
25995 /* Compute default value for "length_address" attribute. */
25996 int
25998 {
26002 {
26013 }
26018 {
26021 {
26026 constraints++;
26029 ;
26030 /* Skip ignored operands. */
26033 }
26035 }
26037 }
26039 /* Compute default value for "length_vex" attribute. It includes
26040 2 or 3 byte VEX prefix and 1 opcode byte. */
26042 int
26045 {
26048 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
26049 byte VEX prefix. */
26053 /* We can always use 2 byte VEX prefix in 32bit. */
26061 {
26062 /* REX.W bit uses 3 byte VEX prefix. */
26066 }
26067 else
26068 {
26069 /* REX.X or REX.B bits use 3 byte VEX prefix. */
26073 }
26076 }
26077 \f
26078 /* Return the maximum number of instructions a cpu can issue. */
26080 static int
26082 {
26084 {
26116 }
26117 }
26119 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
26120 by DEP_INSN and nothing set by DEP_INSN. */
26122 static bool
26124 {
26127 /* Simplify the test for uninteresting insns. */
26135 {
26138 }
26143 {
26146 }
26147 else
26153 /* This test is true if the dependent insn reads the flags but
26154 not any other potentially set register. */
26162 }
26164 /* Return true iff USE_INSN has a memory address with operands set by
26165 SET_INSN. */
26167 bool
26169 {
26174 {
26177 }
26179 }
26181 /* Helper function for exact_store_load_dependency.
26182 Return true if addr is found in insn. */
26183 static bool
26185 {
26192 {
26198 CASE_CONST_ANY:
26207 }
26211 {
26213 {
26223 }
26224 }
26226 }
26228 /* Return true if there exists exact dependency for store & load, i.e.
26229 the same memory address is used in them. */
26230 static bool
26232 {
26246 }
26248 static int
26250 {
26256 /* Anti and output dependencies have zero cost on all CPUs. */
26262 /* If we can't recognize the insns, we can't really do anything. */
26270 {
26272 /* Address Generation Interlock adds a cycle of latency. */
26274 {
26285 }
26289 /* ??? Compares pair with jump/setcc. */
26293 /* Floating point stores require value to be ready one cycle earlier. */
26301 /* INT->FP conversion is expensive. */
26305 /* There is one cycle extra latency between an FP op and a store. */
26315 /* Show ability of reorder buffer to hide latency of load by executing
26316 in parallel with previous instruction in case
26317 previous instruction is not needed to compute the address. */
26320 {
26321 /* Claim moves to take one cycle, as core can issue one load
26322 at time and the next load can start cycle later. */
26327 cost--;
26328 }
26332 /* The esp dependency is resolved before
26333 the instruction is really finished. */
26338 /* INT->FP conversion is expensive. */
26344 /* Show ability of reorder buffer to hide latency of load by executing
26345 in parallel with previous instruction in case
26346 previous instruction is not needed to compute the address. */
26349 {
26350 /* Claim moves to take one cycle, as core can issue one load
26351 at time and the next load can start cycle later. */
26357 else
26359 }
26370 /* Stack engine allows to execute push&pop instructions in parall. */
26374 /* FALLTHRU */
26380 /* Show ability of reorder buffer to hide latency of load by executing
26381 in parallel with previous instruction in case
26382 previous instruction is not needed to compute the address. */
26385 {
26389 /* Because of the difference between the length of integer and
26390 floating unit pipeline preparation stages, the memory operands
26391 for floating point are cheaper.
26393 ??? For Athlon it the difference is most probably 2. */
26396 else
26401 else
26403 }
26410 /* Stack engine allows to execute push&pop instructions in parall. */
26417 /* Show ability of reorder buffer to hide latency of load by executing
26418 in parallel with previous instruction in case
26419 previous instruction is not needed to compute the address. */
26422 {
26425 else
26427 }
26436 /* Increase cost of integer loads. */
26439 {
26442 {
26445 else
26446 {
26447 /* Increase cost of ld/st for short int types only
26448 because of store forwarding issue. */
26452 {
26453 /* Increase cost of store/load insn if exact
26454 dependence exists and it is load insn. */
26459 }
26460 }
26461 }
26462 }
26466 }
26469 }
26471 /* How many alternative schedules to try. This should be as wide as the
26472 scheduling freedom in the DFA, but no wider. Making this value too
26473 large results extra work for the scheduler. */
26475 static int
26477 {
26479 {
26491 /* We use lookahead value 4 for BD both before and after reload
26492 schedules. Plan is to have value 8 included for O3. */
26503 /* Generally, we want haifa-sched:max_issue() to look ahead as far
26504 as many instructions can be executed on a cycle, i.e.,
26505 issue_rate. I wonder why tuning for many CPUs does not do this. */
26508 /* Don't use lookahead for pre-reload schedule to save compile time. */
26513 }
26514 }
26516 /* Return true if target platform supports macro-fusion. */
26518 static bool
26520 {
26522 }
26524 /* Check whether current microarchitecture support macro fusion
26525 for insn pair "CONDGEN + CONDJMP". Refer to
26526 "Intel Architectures Optimization Reference Manual". */
26528 static bool
26530 {
26551 {
26556 {
26560 else
26562 }
26563 }
26570 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
26571 supported. */
26578 /* No fusion for RIP-relative address. */
26585 ix86_address parts;
26591 }
26596 /* Check whether conditional jump use Sign or Overflow Flags. */
26604 /* Return true for TYPE_TEST and TYPE_ICMP. */
26609 /* The following is the case that macro-fusion for alu + jmp. */
26613 /* No fusion for alu op with memory destination operand. */
26618 /* Macro-fusion for inc/dec + unsigned conditional jump is not
26619 supported. */
26628 }
26630 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
26631 execution. It is applied if
26632 (1) IMUL instruction is on the top of list;
26633 (2) There exists the only producer of independent IMUL instruction in
26634 ready list.
26635 Return index of IMUL producer if it was found and -1 otherwise. */
26636 static int
26638 {
26641 sd_iterator_def sd_it;
26642 dep_t dep;
26649 /* Check that IMUL instruction is on the top of ready list. */
26658 /* Search for producer of independent IMUL instruction. */
26660 {
26664 /* Skip IMUL instruction. */
26674 {
26675 rtx con;
26686 {
26687 sd_iterator_def sd_it1;
26688 dep_t dep1;
26689 /* Check if there is no other dependee for IMUL. */
26692 {
26693 rtx pro;
26699 }
26702 }
26703 }
26706 }
26708 }
26710 /* Try to find the best candidate on the top of ready list if two insns
26711 have the same priority - candidate is best if its dependees were
26712 scheduled earlier. Applied for Silvermont only.
26713 Return true if top 2 insns must be interchanged. */
26714 static bool
26716 {
26719 rtx set;
26720 sd_iterator_def sd_it;
26721 dep_t dep;
26724 #define INSN_TICK(INSN) (HID (INSN)->tick)
26745 {
26748 /* Determine winner more precise. */
26750 {
26751 rtx pro;
26757 }
26759 {
26760 rtx pro;
26766 }
26769 {
26770 /* Determine winner - load must win. */
26776 }
26778 }
26780 #undef INSN_TICK
26781 }
26783 /* Perform possible reodering of ready list for Atom/Silvermont only.
26784 Return issue rate. */
26785 static int
26788 {
26795 /* Set up issue rate. */
26798 /* Do reodering for BONNELL/SILVERMONT only. */
26802 /* Nothing to do if ready list contains only 1 instruction. */
26806 /* Do reodering for post-reload scheduler only. */
26811 {
26816 /* Put IMUL producer (ready[index]) at the top of ready list. */
26822 }
26824 /* Skip selective scheduling since HID is not populated in it. */
26828 {
26832 /* Swap 2 top elements of ready list. */
26836 }
26838 }
26840 static bool
26843 /* Returns true if lhs of insn is HW function argument register and set up
26844 is_spilled to true if it is likely spilled HW register. */
26845 static bool
26847 {
26848 rtx dst;
26852 /* Call instructions are not movable, ignore it. */
26863 {
26864 /* Is it likely spilled HW register? */
26869 }
26871 }
26873 /* Add output dependencies for chain of function adjacent arguments if only
26874 there is a move to likely spilled HW register. Return first argument
26875 if at least one dependence was added or NULL otherwise. */
26878 {
26886 /* Find nearest to call argument passing instruction. */
26888 {
26897 }
26901 {
26908 {
26911 }
26913 {
26914 /* Add output depdendence between two function arguments if chain
26915 of output arguments contains likely spilled HW registers. */
26919 }
26920 else
26922 }
26926 }
26928 /* Add output or anti dependency from insn to first_arg to restrict its code
26929 motion. */
26930 static void
26932 {
26933 rtx set;
26934 rtx tmp;
26936 /* Add anti dependencies for bounds stores. */
26941 {
26944 }
26951 {
26952 /* Add output dependency to the first function argument. */
26955 }
26956 /* Add anti dependency. */
26958 }
26960 /* Avoid cross block motion of function argument through adding dependency
26961 from the first non-jump instruction in bb. */
26962 static void
26964 {
26968 {
26970 {
26973 {
26976 }
26977 }
26981 }
26982 }
26984 /* Hook for pre-reload schedule - avoid motion of function arguments
26985 passed in likely spilled HW registers. */
26986 static void
26988 {
26997 {
27000 {
27001 /* Add dependee for first argument to predecessors if only
27002 region contains more than one block. */
27006 /* Skip trivial regions and region head blocks that can have
27007 predecessors outside of region. */
27009 {
27010 edge e;
27011 edge_iterator ei;
27013 /* Regions are SCCs with the exception of selective
27014 scheduling with pipelining of outer blocks enabled.
27015 So also check that immediate predecessors of a non-head
27016 block are in the same region. */
27018 {
27019 /* Avoid creating of loop-carried dependencies through
27020 using topological ordering in the region. */
27024 }
27025 }
27029 }
27030 }
27033 }
27035 /* Hook for pre-reload schedule - set priority of moves from likely spilled
27036 HW registers to maximum, to schedule them at soon as possible. These are
27037 moves from function argument registers at the top of the function entry
27038 and moves from function return value registers after call. */
27039 static int
27041 {
27042 rtx set;
27052 {
27059 }
27062 }
27064 /* Model decoder of Core 2/i7.
27065 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
27066 track the instruction fetch block boundaries and make sure that long
27067 (9+ bytes) instructions are assigned to D0. */
27069 /* Maximum length of an insn that can be handled by
27070 a secondary decoder unit. '8' for Core 2/i7. */
27073 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
27074 '16' for Core 2/i7. */
27077 /* Maximum number of instructions decoder can handle per cycle.
27078 '6' for Core 2/i7. */
27082 ix86_first_cycle_multipass_data_t;
27084 const_ix86_first_cycle_multipass_data_t;
27086 /* A variable to store target state across calls to max_issue within
27087 one cycle. */
27091 /* Initialize DATA. */
27092 static void
27094 {
27095 ix86_first_cycle_multipass_data_t data
27102 }
27104 /* Advancing the cycle; reset ifetch block counts. */
27105 static void
27107 {
27114 }
27118 /* Filter out insns from ready_try that the core will not be able to issue
27119 on current cycle due to decoder. */
27120 static void
27121 core2i7_first_cycle_multipass_filter_ready_try
27124 {
27126 {
27137 (!first_cycle_insn_p
27139 /* ... or it would not fit into the ifetch block ... */
27141 /* ... or the decoder is full already ... */
27143 /* ... mask the insn out. */
27144 {
27149 }
27150 }
27151 }
27153 /* Prepare for a new round of multipass lookahead scheduling. */
27154 static void
27158 {
27159 ix86_first_cycle_multipass_data_t data
27161 const_ix86_first_cycle_multipass_data_t prev_data
27164 /* Restore the state from the end of the previous round. */
27168 /* Filter instructions that cannot be issued on current cycle due to
27169 decoder restrictions. */
27171 first_cycle_insn_p);
27172 }
27174 /* INSN is being issued in current solution. Account for its impact on
27175 the decoder model. */
27176 static void
27180 {
27181 ix86_first_cycle_multipass_data_t data
27183 const_ix86_first_cycle_multipass_data_t prev_data
27193 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
27195 {
27198 }
27200 {
27204 }
27207 /* Filter out insns from ready_try that the core will not be able to issue
27208 on current cycle due to decoder. */
27211 }
27213 /* Revert the effect on ready_try. */
27214 static void
27218 {
27219 const_ix86_first_cycle_multipass_data_t data
27222 sbitmap_iterator sbi;
27226 {
27228 }
27229 }
27231 /* Save the result of multipass lookahead scheduling for the next round. */
27232 static void
27234 {
27235 const_ix86_first_cycle_multipass_data_t data
27237 ix86_first_cycle_multipass_data_t next_data
27241 {
27244 }
27245 }
27247 /* Deallocate target data. */
27248 static void
27250 {
27251 ix86_first_cycle_multipass_data_t data
27255 {
27259 }
27260 }
27262 /* Prepare for scheduling pass. */
27263 static void
27265 {
27266 /* Install scheduling hooks for current CPU. Some of these hooks are used
27267 in time-critical parts of the scheduler, so we only set them up when
27268 they are actually used. */
27270 {
27275 /* Do not perform multipass scheduling for pre-reload schedule
27276 to save compile time. */
27278 {
27294 /* Set decoder parameters. */
27299 }
27300 /* ... Fall through ... */
27310 }
27311 }
27313 \f
27314 /* Compute the alignment given to a constant that is being placed in memory.
27315 EXP is the constant and ALIGN is the alignment that the object would
27316 ordinarily have.
27317 The value of this function is used instead of that alignment to align
27318 the object. */
27320 int
27322 {
27325 {
27330 }
27336 }
27338 /* Compute the alignment for a static variable.
27339 TYPE is the data type, and ALIGN is the alignment that
27340 the object would ordinarily have. The value of this function is used
27341 instead of that alignment to align the object. */
27343 int
27345 {
27346 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
27347 for symbols from other compilation units or symbols that don't need
27348 to bind locally. In order to preserve some ABI compatibility with
27349 those compilers, ensure we don't decrease alignment from what we
27350 used to assume. */
27354 /* A data structure, equal or greater than the size of a cache line
27355 (64 bytes in the Pentium 4 and other recent Intel processors, including
27356 processors based on Intel Core microarchitecture) should be aligned
27357 so that its base address is a multiple of a cache line size. */
27359 int max_align
27366 {
27370 }
27376 {
27383 }
27385 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27386 to 16byte boundary. */
27388 {
27395 }
27401 {
27406 }
27408 {
27415 }
27420 {
27425 }
27428 {
27433 }
27436 }
27438 /* Compute the alignment for a local variable or a stack slot. EXP is
27439 the data type or decl itself, MODE is the widest mode available and
27440 ALIGN is the alignment that the object would ordinarily have. The
27441 value of this macro is used instead of that alignment to align the
27442 object. */
27444 unsigned int
27447 {
27451 {
27454 }
27455 else
27456 {
27459 }
27461 /* Don't do dynamic stack realignment for long long objects with
27462 -mpreferred-stack-boundary=2. */
27471 /* If TYPE is NULL, we are allocating a stack slot for caller-save
27472 register in MODE. We will return the largest alignment of XF
27473 and DF. */
27475 {
27479 }
27481 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27482 to 16byte boundary. Exact wording is:
27484 An array uses the same alignment as its elements, except that a local or
27485 global array variable of length at least 16 bytes or
27486 a C99 variable-length array variable always has alignment of at least 16 bytes.
27488 This was added to allow use of aligned SSE instructions at arrays. This
27489 rule is meant for static storage (where compiler can not do the analysis
27490 by itself). We follow it for automatic variables only when convenient.
27491 We fully control everything in the function compiled and functions from
27492 other unit can not rely on the alignment.
27494 Exclude va_list type. It is the common case of local array where
27495 we can not benefit from the alignment.
27497 TODO: Probably one should optimize for size only when var is not escaping. */
27500 {
27510 }
27512 {
27517 }
27519 {
27525 }
27530 {
27535 }
27538 {
27544 }
27546 }
27548 /* Compute the minimum required alignment for dynamic stack realignment
27549 purposes for a local variable, parameter or a stack slot. EXP is
27550 the data type or decl itself, MODE is its mode and ALIGN is the
27551 alignment that the object would ordinarily have. */
27553 unsigned int
27556 {
27560 {
27563 }
27564 else
27565 {
27568 }
27573 /* Don't do dynamic stack realignment for long long objects with
27574 -mpreferred-stack-boundary=2. */
27581 }
27582 \f
27583 /* Find a location for the static chain incoming to a nested function.
27584 This is a register, unless all free registers are used by arguments. */
27586 static rtx
27588 {
27591 /* While this function won't be called by the middle-end when a static
27592 chain isn't needed, it's also used throughout the backend so it's
27593 easiest to keep this check centralized. */
27598 {
27599 /* We always use R10 in 64-bit mode. */
27601 }
27602 else
27603 {
27607 /* By default in 32-bit mode we use ECX to pass the static chain. */
27611 {
27614 }
27615 else
27616 {
27619 }
27623 {
27624 /* Fastcall functions use ecx/edx for arguments, which leaves
27625 us with EAX for the static chain.
27626 Thiscall functions use ecx for arguments, which also
27627 leaves us with EAX for the static chain. */
27629 }
27631 {
27632 /* Thiscall functions use ecx for arguments, which leaves
27633 us with EAX and EDX for the static chain.
27634 We are using for abi-compatibility EAX. */
27636 }
27638 {
27639 /* For regparm 3, we have no free call-clobbered registers in
27640 which to store the static chain. In order to implement this,
27641 we have the trampoline push the static chain to the stack.
27642 However, we can't push a value below the return address when
27643 we call the nested function directly, so we have to use an
27644 alternate entry point. For this we use ESI, and have the
27645 alternate entry point push ESI, so that things appear the
27646 same once we're executing the nested function. */
27648 {
27654 }
27656 }
27657 }
27660 }
27662 /* Emit RTL insns to initialize the variable parts of a trampoline.
27663 FNDECL is the decl of the target address; M_TRAMP is a MEM for
27664 the trampoline, and CHAIN_VALUE is an RTX for the static chain
27665 to be passed to the target function. */
27667 static void
27669 {
27677 {
27680 /* Load the function address to r11. Try to load address using
27681 the shorter movl instead of movabs. We may want to support
27682 movq for kernel mode, but kernel does not use trampolines at
27683 the moment. FNADDR is a 32bit address and may not be in
27684 DImode when ptr_mode == SImode. Always use movl in this
27685 case. */
27688 {
27697 }
27698 else
27699 {
27706 }
27708 /* Load static chain using movabs to r10. Use the shorter movl
27709 instead of movabs when ptr_mode == SImode. */
27711 {
27714 }
27715 else
27716 {
27719 }
27728 /* Jump to r11; the last (unused) byte is a nop, only there to
27729 pad the write out to a single 32-bit store. */
27733 }
27734 else
27735 {
27738 /* Depending on the static chain location, either load a register
27739 with a constant, or push the constant to the stack. All of the
27740 instructions are the same size. */
27743 {
27745 {
27752 }
27753 }
27754 else
27769 /* Compute offset from the end of the jmp to the target function.
27770 In the case in which the trampoline stores the static chain on
27771 the stack, we need to skip the first insn which pushes the
27772 (call-saved) register static chain; this push is 1 byte. */
27779 }
27783 #ifdef HAVE_ENABLE_EXECUTE_STACK
27784 #ifdef CHECK_EXECUTE_STACK_ENABLED
27786 #endif
27789 #endif
27790 }
27791 \f
27792 /* The following file contains several enumerations and data structures
27793 built from the definitions in i386-builtin-types.def. */
27797 /* Table for the ix86 builtin non-function types. */
27800 /* Retrieve an element from the above table, building some of
27801 the types lazily. */
27803 static tree
27805 {
27817 {
27818 machine_mode mode;
27825 }
27826 else
27827 {
27833 else
27841 }
27845 }
27847 /* Table for the ix86 builtin function types. */
27850 /* Retrieve an element from the above table, building some of
27851 the types lazily. */
27853 static tree
27855 {
27856 tree type;
27865 {
27873 {
27876 }
27879 }
27880 else
27881 {
27887 }
27891 }
27894 /* Codes for all the SSE/MMX builtins. */
27895 enum ix86_builtins
27896 {
27897 IX86_BUILTIN_ADDPS,
27898 IX86_BUILTIN_ADDSS,
27899 IX86_BUILTIN_DIVPS,
27900 IX86_BUILTIN_DIVSS,
27901 IX86_BUILTIN_MULPS,
27902 IX86_BUILTIN_MULSS,
27903 IX86_BUILTIN_SUBPS,
27904 IX86_BUILTIN_SUBSS,
27906 IX86_BUILTIN_CMPEQPS,
27907 IX86_BUILTIN_CMPLTPS,
27908 IX86_BUILTIN_CMPLEPS,
27909 IX86_BUILTIN_CMPGTPS,
27910 IX86_BUILTIN_CMPGEPS,
27911 IX86_BUILTIN_CMPNEQPS,
27912 IX86_BUILTIN_CMPNLTPS,
27913 IX86_BUILTIN_CMPNLEPS,
27914 IX86_BUILTIN_CMPNGTPS,
27915 IX86_BUILTIN_CMPNGEPS,
27916 IX86_BUILTIN_CMPORDPS,
27917 IX86_BUILTIN_CMPUNORDPS,
27918 IX86_BUILTIN_CMPEQSS,
27919 IX86_BUILTIN_CMPLTSS,
27920 IX86_BUILTIN_CMPLESS,
27921 IX86_BUILTIN_CMPNEQSS,
27922 IX86_BUILTIN_CMPNLTSS,
27923 IX86_BUILTIN_CMPNLESS,
27924 IX86_BUILTIN_CMPORDSS,
27925 IX86_BUILTIN_CMPUNORDSS,
27927 IX86_BUILTIN_COMIEQSS,
27928 IX86_BUILTIN_COMILTSS,
27929 IX86_BUILTIN_COMILESS,
27930 IX86_BUILTIN_COMIGTSS,
27931 IX86_BUILTIN_COMIGESS,
27932 IX86_BUILTIN_COMINEQSS,
27933 IX86_BUILTIN_UCOMIEQSS,
27934 IX86_BUILTIN_UCOMILTSS,
27935 IX86_BUILTIN_UCOMILESS,
27936 IX86_BUILTIN_UCOMIGTSS,
27937 IX86_BUILTIN_UCOMIGESS,
27938 IX86_BUILTIN_UCOMINEQSS,
27940 IX86_BUILTIN_CVTPI2PS,
27941 IX86_BUILTIN_CVTPS2PI,
27942 IX86_BUILTIN_CVTSI2SS,
27943 IX86_BUILTIN_CVTSI642SS,
27944 IX86_BUILTIN_CVTSS2SI,
27945 IX86_BUILTIN_CVTSS2SI64,
27946 IX86_BUILTIN_CVTTPS2PI,
27947 IX86_BUILTIN_CVTTSS2SI,
27948 IX86_BUILTIN_CVTTSS2SI64,
27950 IX86_BUILTIN_MAXPS,
27951 IX86_BUILTIN_MAXSS,
27952 IX86_BUILTIN_MINPS,
27953 IX86_BUILTIN_MINSS,
27955 IX86_BUILTIN_LOADUPS,
27956 IX86_BUILTIN_STOREUPS,
27957 IX86_BUILTIN_MOVSS,
27959 IX86_BUILTIN_MOVHLPS,
27960 IX86_BUILTIN_MOVLHPS,
27961 IX86_BUILTIN_LOADHPS,
27962 IX86_BUILTIN_LOADLPS,
27963 IX86_BUILTIN_STOREHPS,
27964 IX86_BUILTIN_STORELPS,
27966 IX86_BUILTIN_MASKMOVQ,
27967 IX86_BUILTIN_MOVMSKPS,
27968 IX86_BUILTIN_PMOVMSKB,
27970 IX86_BUILTIN_MOVNTPS,
27971 IX86_BUILTIN_MOVNTQ,
27973 IX86_BUILTIN_LOADDQU,
27974 IX86_BUILTIN_STOREDQU,
27976 IX86_BUILTIN_PACKSSWB,
27977 IX86_BUILTIN_PACKSSDW,
27978 IX86_BUILTIN_PACKUSWB,
27980 IX86_BUILTIN_PADDB,
27981 IX86_BUILTIN_PADDW,
27982 IX86_BUILTIN_PADDD,
27983 IX86_BUILTIN_PADDQ,
27984 IX86_BUILTIN_PADDSB,
27985 IX86_BUILTIN_PADDSW,
27986 IX86_BUILTIN_PADDUSB,
27987 IX86_BUILTIN_PADDUSW,
27988 IX86_BUILTIN_PSUBB,
27989 IX86_BUILTIN_PSUBW,
27990 IX86_BUILTIN_PSUBD,
27991 IX86_BUILTIN_PSUBQ,
27992 IX86_BUILTIN_PSUBSB,
27993 IX86_BUILTIN_PSUBSW,
27994 IX86_BUILTIN_PSUBUSB,
27995 IX86_BUILTIN_PSUBUSW,
27997 IX86_BUILTIN_PAND,
27998 IX86_BUILTIN_PANDN,
27999 IX86_BUILTIN_POR,
28000 IX86_BUILTIN_PXOR,
28002 IX86_BUILTIN_PAVGB,
28003 IX86_BUILTIN_PAVGW,
28005 IX86_BUILTIN_PCMPEQB,
28006 IX86_BUILTIN_PCMPEQW,
28007 IX86_BUILTIN_PCMPEQD,
28008 IX86_BUILTIN_PCMPGTB,
28009 IX86_BUILTIN_PCMPGTW,
28010 IX86_BUILTIN_PCMPGTD,
28012 IX86_BUILTIN_PMADDWD,
28014 IX86_BUILTIN_PMAXSW,
28015 IX86_BUILTIN_PMAXUB,
28016 IX86_BUILTIN_PMINSW,
28017 IX86_BUILTIN_PMINUB,
28019 IX86_BUILTIN_PMULHUW,
28020 IX86_BUILTIN_PMULHW,
28021 IX86_BUILTIN_PMULLW,
28023 IX86_BUILTIN_PSADBW,
28024 IX86_BUILTIN_PSHUFW,
28026 IX86_BUILTIN_PSLLW,
28027 IX86_BUILTIN_PSLLD,
28028 IX86_BUILTIN_PSLLQ,
28029 IX86_BUILTIN_PSRAW,
28030 IX86_BUILTIN_PSRAD,
28031 IX86_BUILTIN_PSRLW,
28032 IX86_BUILTIN_PSRLD,
28033 IX86_BUILTIN_PSRLQ,
28034 IX86_BUILTIN_PSLLWI,
28035 IX86_BUILTIN_PSLLDI,
28036 IX86_BUILTIN_PSLLQI,
28037 IX86_BUILTIN_PSRAWI,
28038 IX86_BUILTIN_PSRADI,
28039 IX86_BUILTIN_PSRLWI,
28040 IX86_BUILTIN_PSRLDI,
28041 IX86_BUILTIN_PSRLQI,
28043 IX86_BUILTIN_PUNPCKHBW,
28044 IX86_BUILTIN_PUNPCKHWD,
28045 IX86_BUILTIN_PUNPCKHDQ,
28046 IX86_BUILTIN_PUNPCKLBW,
28047 IX86_BUILTIN_PUNPCKLWD,
28048 IX86_BUILTIN_PUNPCKLDQ,
28050 IX86_BUILTIN_SHUFPS,
28052 IX86_BUILTIN_RCPPS,
28053 IX86_BUILTIN_RCPSS,
28054 IX86_BUILTIN_RSQRTPS,
28055 IX86_BUILTIN_RSQRTPS_NR,
28056 IX86_BUILTIN_RSQRTSS,
28057 IX86_BUILTIN_RSQRTF,
28058 IX86_BUILTIN_SQRTPS,
28059 IX86_BUILTIN_SQRTPS_NR,
28060 IX86_BUILTIN_SQRTSS,
28062 IX86_BUILTIN_UNPCKHPS,
28063 IX86_BUILTIN_UNPCKLPS,
28065 IX86_BUILTIN_ANDPS,
28066 IX86_BUILTIN_ANDNPS,
28067 IX86_BUILTIN_ORPS,
28068 IX86_BUILTIN_XORPS,
28070 IX86_BUILTIN_EMMS,
28071 IX86_BUILTIN_LDMXCSR,
28072 IX86_BUILTIN_STMXCSR,
28073 IX86_BUILTIN_SFENCE,
28075 IX86_BUILTIN_FXSAVE,
28076 IX86_BUILTIN_FXRSTOR,
28077 IX86_BUILTIN_FXSAVE64,
28078 IX86_BUILTIN_FXRSTOR64,
28080 IX86_BUILTIN_XSAVE,
28081 IX86_BUILTIN_XRSTOR,
28082 IX86_BUILTIN_XSAVE64,
28083 IX86_BUILTIN_XRSTOR64,
28085 IX86_BUILTIN_XSAVEOPT,
28086 IX86_BUILTIN_XSAVEOPT64,
28088 IX86_BUILTIN_XSAVEC,
28089 IX86_BUILTIN_XSAVEC64,
28091 IX86_BUILTIN_XSAVES,
28092 IX86_BUILTIN_XRSTORS,
28093 IX86_BUILTIN_XSAVES64,
28094 IX86_BUILTIN_XRSTORS64,
28096 /* 3DNow! Original */
28097 IX86_BUILTIN_FEMMS,
28098 IX86_BUILTIN_PAVGUSB,
28099 IX86_BUILTIN_PF2ID,
28100 IX86_BUILTIN_PFACC,
28101 IX86_BUILTIN_PFADD,
28102 IX86_BUILTIN_PFCMPEQ,
28103 IX86_BUILTIN_PFCMPGE,
28104 IX86_BUILTIN_PFCMPGT,
28105 IX86_BUILTIN_PFMAX,
28106 IX86_BUILTIN_PFMIN,
28107 IX86_BUILTIN_PFMUL,
28108 IX86_BUILTIN_PFRCP,
28109 IX86_BUILTIN_PFRCPIT1,
28110 IX86_BUILTIN_PFRCPIT2,
28111 IX86_BUILTIN_PFRSQIT1,
28112 IX86_BUILTIN_PFRSQRT,
28113 IX86_BUILTIN_PFSUB,
28114 IX86_BUILTIN_PFSUBR,
28115 IX86_BUILTIN_PI2FD,
28116 IX86_BUILTIN_PMULHRW,
28118 /* 3DNow! Athlon Extensions */
28119 IX86_BUILTIN_PF2IW,
28120 IX86_BUILTIN_PFNACC,
28121 IX86_BUILTIN_PFPNACC,
28122 IX86_BUILTIN_PI2FW,
28123 IX86_BUILTIN_PSWAPDSI,
28124 IX86_BUILTIN_PSWAPDSF,
28126 /* SSE2 */
28127 IX86_BUILTIN_ADDPD,
28128 IX86_BUILTIN_ADDSD,
28129 IX86_BUILTIN_DIVPD,
28130 IX86_BUILTIN_DIVSD,
28131 IX86_BUILTIN_MULPD,
28132 IX86_BUILTIN_MULSD,
28133 IX86_BUILTIN_SUBPD,
28134 IX86_BUILTIN_SUBSD,
28136 IX86_BUILTIN_CMPEQPD,
28137 IX86_BUILTIN_CMPLTPD,
28138 IX86_BUILTIN_CMPLEPD,
28139 IX86_BUILTIN_CMPGTPD,
28140 IX86_BUILTIN_CMPGEPD,
28141 IX86_BUILTIN_CMPNEQPD,
28142 IX86_BUILTIN_CMPNLTPD,
28143 IX86_BUILTIN_CMPNLEPD,
28144 IX86_BUILTIN_CMPNGTPD,
28145 IX86_BUILTIN_CMPNGEPD,
28146 IX86_BUILTIN_CMPORDPD,
28147 IX86_BUILTIN_CMPUNORDPD,
28148 IX86_BUILTIN_CMPEQSD,
28149 IX86_BUILTIN_CMPLTSD,
28150 IX86_BUILTIN_CMPLESD,
28151 IX86_BUILTIN_CMPNEQSD,
28152 IX86_BUILTIN_CMPNLTSD,
28153 IX86_BUILTIN_CMPNLESD,
28154 IX86_BUILTIN_CMPORDSD,
28155 IX86_BUILTIN_CMPUNORDSD,
28157 IX86_BUILTIN_COMIEQSD,
28158 IX86_BUILTIN_COMILTSD,
28159 IX86_BUILTIN_COMILESD,
28160 IX86_BUILTIN_COMIGTSD,
28161 IX86_BUILTIN_COMIGESD,
28162 IX86_BUILTIN_COMINEQSD,
28163 IX86_BUILTIN_UCOMIEQSD,
28164 IX86_BUILTIN_UCOMILTSD,
28165 IX86_BUILTIN_UCOMILESD,
28166 IX86_BUILTIN_UCOMIGTSD,
28167 IX86_BUILTIN_UCOMIGESD,
28168 IX86_BUILTIN_UCOMINEQSD,
28170 IX86_BUILTIN_MAXPD,
28171 IX86_BUILTIN_MAXSD,
28172 IX86_BUILTIN_MINPD,
28173 IX86_BUILTIN_MINSD,
28175 IX86_BUILTIN_ANDPD,
28176 IX86_BUILTIN_ANDNPD,
28177 IX86_BUILTIN_ORPD,
28178 IX86_BUILTIN_XORPD,
28180 IX86_BUILTIN_SQRTPD,
28181 IX86_BUILTIN_SQRTSD,
28183 IX86_BUILTIN_UNPCKHPD,
28184 IX86_BUILTIN_UNPCKLPD,
28186 IX86_BUILTIN_SHUFPD,
28188 IX86_BUILTIN_LOADUPD,
28189 IX86_BUILTIN_STOREUPD,
28190 IX86_BUILTIN_MOVSD,
28192 IX86_BUILTIN_LOADHPD,
28193 IX86_BUILTIN_LOADLPD,
28195 IX86_BUILTIN_CVTDQ2PD,
28196 IX86_BUILTIN_CVTDQ2PS,
28198 IX86_BUILTIN_CVTPD2DQ,
28199 IX86_BUILTIN_CVTPD2PI,
28200 IX86_BUILTIN_CVTPD2PS,
28201 IX86_BUILTIN_CVTTPD2DQ,
28202 IX86_BUILTIN_CVTTPD2PI,
28204 IX86_BUILTIN_CVTPI2PD,
28205 IX86_BUILTIN_CVTSI2SD,
28206 IX86_BUILTIN_CVTSI642SD,
28208 IX86_BUILTIN_CVTSD2SI,
28209 IX86_BUILTIN_CVTSD2SI64,
28210 IX86_BUILTIN_CVTSD2SS,
28211 IX86_BUILTIN_CVTSS2SD,
28212 IX86_BUILTIN_CVTTSD2SI,
28213 IX86_BUILTIN_CVTTSD2SI64,
28215 IX86_BUILTIN_CVTPS2DQ,
28216 IX86_BUILTIN_CVTPS2PD,
28217 IX86_BUILTIN_CVTTPS2DQ,
28219 IX86_BUILTIN_MOVNTI,
28220 IX86_BUILTIN_MOVNTI64,
28221 IX86_BUILTIN_MOVNTPD,
28222 IX86_BUILTIN_MOVNTDQ,
28224 IX86_BUILTIN_MOVQ128,
28226 /* SSE2 MMX */
28227 IX86_BUILTIN_MASKMOVDQU,
28228 IX86_BUILTIN_MOVMSKPD,
28229 IX86_BUILTIN_PMOVMSKB128,
28231 IX86_BUILTIN_PACKSSWB128,
28232 IX86_BUILTIN_PACKSSDW128,
28233 IX86_BUILTIN_PACKUSWB128,
28235 IX86_BUILTIN_PADDB128,
28236 IX86_BUILTIN_PADDW128,
28237 IX86_BUILTIN_PADDD128,
28238 IX86_BUILTIN_PADDQ128,
28239 IX86_BUILTIN_PADDSB128,
28240 IX86_BUILTIN_PADDSW128,
28241 IX86_BUILTIN_PADDUSB128,
28242 IX86_BUILTIN_PADDUSW128,
28243 IX86_BUILTIN_PSUBB128,
28244 IX86_BUILTIN_PSUBW128,
28245 IX86_BUILTIN_PSUBD128,
28246 IX86_BUILTIN_PSUBQ128,
28247 IX86_BUILTIN_PSUBSB128,
28248 IX86_BUILTIN_PSUBSW128,
28249 IX86_BUILTIN_PSUBUSB128,
28250 IX86_BUILTIN_PSUBUSW128,
28252 IX86_BUILTIN_PAND128,
28253 IX86_BUILTIN_PANDN128,
28254 IX86_BUILTIN_POR128,
28255 IX86_BUILTIN_PXOR128,
28257 IX86_BUILTIN_PAVGB128,
28258 IX86_BUILTIN_PAVGW128,
28260 IX86_BUILTIN_PCMPEQB128,
28261 IX86_BUILTIN_PCMPEQW128,
28262 IX86_BUILTIN_PCMPEQD128,
28263 IX86_BUILTIN_PCMPGTB128,
28264 IX86_BUILTIN_PCMPGTW128,
28265 IX86_BUILTIN_PCMPGTD128,
28267 IX86_BUILTIN_PMADDWD128,
28269 IX86_BUILTIN_PMAXSW128,
28270 IX86_BUILTIN_PMAXUB128,
28271 IX86_BUILTIN_PMINSW128,
28272 IX86_BUILTIN_PMINUB128,
28274 IX86_BUILTIN_PMULUDQ,
28275 IX86_BUILTIN_PMULUDQ128,
28276 IX86_BUILTIN_PMULHUW128,
28277 IX86_BUILTIN_PMULHW128,
28278 IX86_BUILTIN_PMULLW128,
28280 IX86_BUILTIN_PSADBW128,
28281 IX86_BUILTIN_PSHUFHW,
28282 IX86_BUILTIN_PSHUFLW,
28283 IX86_BUILTIN_PSHUFD,
28285 IX86_BUILTIN_PSLLDQI128,
28286 IX86_BUILTIN_PSLLWI128,
28287 IX86_BUILTIN_PSLLDI128,
28288 IX86_BUILTIN_PSLLQI128,
28289 IX86_BUILTIN_PSRAWI128,
28290 IX86_BUILTIN_PSRADI128,
28291 IX86_BUILTIN_PSRLDQI128,
28292 IX86_BUILTIN_PSRLWI128,
28293 IX86_BUILTIN_PSRLDI128,
28294 IX86_BUILTIN_PSRLQI128,
28296 IX86_BUILTIN_PSLLDQ128,
28297 IX86_BUILTIN_PSLLW128,
28298 IX86_BUILTIN_PSLLD128,
28299 IX86_BUILTIN_PSLLQ128,
28300 IX86_BUILTIN_PSRAW128,
28301 IX86_BUILTIN_PSRAD128,
28302 IX86_BUILTIN_PSRLW128,
28303 IX86_BUILTIN_PSRLD128,
28304 IX86_BUILTIN_PSRLQ128,
28306 IX86_BUILTIN_PUNPCKHBW128,
28307 IX86_BUILTIN_PUNPCKHWD128,
28308 IX86_BUILTIN_PUNPCKHDQ128,
28309 IX86_BUILTIN_PUNPCKHQDQ128,
28310 IX86_BUILTIN_PUNPCKLBW128,
28311 IX86_BUILTIN_PUNPCKLWD128,
28312 IX86_BUILTIN_PUNPCKLDQ128,
28313 IX86_BUILTIN_PUNPCKLQDQ128,
28315 IX86_BUILTIN_CLFLUSH,
28316 IX86_BUILTIN_MFENCE,
28317 IX86_BUILTIN_LFENCE,
28318 IX86_BUILTIN_PAUSE,
28320 IX86_BUILTIN_FNSTENV,
28321 IX86_BUILTIN_FLDENV,
28322 IX86_BUILTIN_FNSTSW,
28323 IX86_BUILTIN_FNCLEX,
28325 IX86_BUILTIN_BSRSI,
28326 IX86_BUILTIN_BSRDI,
28327 IX86_BUILTIN_RDPMC,
28328 IX86_BUILTIN_RDTSC,
28329 IX86_BUILTIN_RDTSCP,
28330 IX86_BUILTIN_ROLQI,
28331 IX86_BUILTIN_ROLHI,
28332 IX86_BUILTIN_RORQI,
28333 IX86_BUILTIN_RORHI,
28335 /* SSE3. */
28336 IX86_BUILTIN_ADDSUBPS,
28337 IX86_BUILTIN_HADDPS,
28338 IX86_BUILTIN_HSUBPS,
28339 IX86_BUILTIN_MOVSHDUP,
28340 IX86_BUILTIN_MOVSLDUP,
28341 IX86_BUILTIN_ADDSUBPD,
28342 IX86_BUILTIN_HADDPD,
28343 IX86_BUILTIN_HSUBPD,
28344 IX86_BUILTIN_LDDQU,
28346 IX86_BUILTIN_MONITOR,
28347 IX86_BUILTIN_MWAIT,
28349 /* SSSE3. */
28350 IX86_BUILTIN_PHADDW,
28351 IX86_BUILTIN_PHADDD,
28352 IX86_BUILTIN_PHADDSW,
28353 IX86_BUILTIN_PHSUBW,
28354 IX86_BUILTIN_PHSUBD,
28355 IX86_BUILTIN_PHSUBSW,
28356 IX86_BUILTIN_PMADDUBSW,
28357 IX86_BUILTIN_PMULHRSW,
28358 IX86_BUILTIN_PSHUFB,
28359 IX86_BUILTIN_PSIGNB,
28360 IX86_BUILTIN_PSIGNW,
28361 IX86_BUILTIN_PSIGND,
28362 IX86_BUILTIN_PALIGNR,
28363 IX86_BUILTIN_PABSB,
28364 IX86_BUILTIN_PABSW,
28365 IX86_BUILTIN_PABSD,
28367 IX86_BUILTIN_PHADDW128,
28368 IX86_BUILTIN_PHADDD128,
28369 IX86_BUILTIN_PHADDSW128,
28370 IX86_BUILTIN_PHSUBW128,
28371 IX86_BUILTIN_PHSUBD128,
28372 IX86_BUILTIN_PHSUBSW128,
28373 IX86_BUILTIN_PMADDUBSW128,
28374 IX86_BUILTIN_PMULHRSW128,
28375 IX86_BUILTIN_PSHUFB128,
28376 IX86_BUILTIN_PSIGNB128,
28377 IX86_BUILTIN_PSIGNW128,
28378 IX86_BUILTIN_PSIGND128,
28379 IX86_BUILTIN_PALIGNR128,
28380 IX86_BUILTIN_PABSB128,
28381 IX86_BUILTIN_PABSW128,
28382 IX86_BUILTIN_PABSD128,
28384 /* AMDFAM10 - SSE4A New Instructions. */
28385 IX86_BUILTIN_MOVNTSD,
28386 IX86_BUILTIN_MOVNTSS,
28387 IX86_BUILTIN_EXTRQI,
28388 IX86_BUILTIN_EXTRQ,
28389 IX86_BUILTIN_INSERTQI,
28390 IX86_BUILTIN_INSERTQ,
28392 /* SSE4.1. */
28393 IX86_BUILTIN_BLENDPD,
28394 IX86_BUILTIN_BLENDPS,
28395 IX86_BUILTIN_BLENDVPD,
28396 IX86_BUILTIN_BLENDVPS,
28397 IX86_BUILTIN_PBLENDVB128,
28398 IX86_BUILTIN_PBLENDW128,
28400 IX86_BUILTIN_DPPD,
28401 IX86_BUILTIN_DPPS,
28403 IX86_BUILTIN_INSERTPS128,
28405 IX86_BUILTIN_MOVNTDQA,
28406 IX86_BUILTIN_MPSADBW128,
28407 IX86_BUILTIN_PACKUSDW128,
28408 IX86_BUILTIN_PCMPEQQ,
28409 IX86_BUILTIN_PHMINPOSUW128,
28411 IX86_BUILTIN_PMAXSB128,
28412 IX86_BUILTIN_PMAXSD128,
28413 IX86_BUILTIN_PMAXUD128,
28414 IX86_BUILTIN_PMAXUW128,
28416 IX86_BUILTIN_PMINSB128,
28417 IX86_BUILTIN_PMINSD128,
28418 IX86_BUILTIN_PMINUD128,
28419 IX86_BUILTIN_PMINUW128,
28421 IX86_BUILTIN_PMOVSXBW128,
28422 IX86_BUILTIN_PMOVSXBD128,
28423 IX86_BUILTIN_PMOVSXBQ128,
28424 IX86_BUILTIN_PMOVSXWD128,
28425 IX86_BUILTIN_PMOVSXWQ128,
28426 IX86_BUILTIN_PMOVSXDQ128,
28428 IX86_BUILTIN_PMOVZXBW128,
28429 IX86_BUILTIN_PMOVZXBD128,
28430 IX86_BUILTIN_PMOVZXBQ128,
28431 IX86_BUILTIN_PMOVZXWD128,
28432 IX86_BUILTIN_PMOVZXWQ128,
28433 IX86_BUILTIN_PMOVZXDQ128,
28435 IX86_BUILTIN_PMULDQ128,
28436 IX86_BUILTIN_PMULLD128,
28438 IX86_BUILTIN_ROUNDSD,
28439 IX86_BUILTIN_ROUNDSS,
28441 IX86_BUILTIN_ROUNDPD,
28442 IX86_BUILTIN_ROUNDPS,
28444 IX86_BUILTIN_FLOORPD,
28445 IX86_BUILTIN_CEILPD,
28446 IX86_BUILTIN_TRUNCPD,
28447 IX86_BUILTIN_RINTPD,
28448 IX86_BUILTIN_ROUNDPD_AZ,
28450 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
28451 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
28452 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
28454 IX86_BUILTIN_FLOORPS,
28455 IX86_BUILTIN_CEILPS,
28456 IX86_BUILTIN_TRUNCPS,
28457 IX86_BUILTIN_RINTPS,
28458 IX86_BUILTIN_ROUNDPS_AZ,
28460 IX86_BUILTIN_FLOORPS_SFIX,
28461 IX86_BUILTIN_CEILPS_SFIX,
28462 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
28464 IX86_BUILTIN_PTESTZ,
28465 IX86_BUILTIN_PTESTC,
28466 IX86_BUILTIN_PTESTNZC,
28468 IX86_BUILTIN_VEC_INIT_V2SI,
28469 IX86_BUILTIN_VEC_INIT_V4HI,
28470 IX86_BUILTIN_VEC_INIT_V8QI,
28471 IX86_BUILTIN_VEC_EXT_V2DF,
28472 IX86_BUILTIN_VEC_EXT_V2DI,
28473 IX86_BUILTIN_VEC_EXT_V4SF,
28474 IX86_BUILTIN_VEC_EXT_V4SI,
28475 IX86_BUILTIN_VEC_EXT_V8HI,
28476 IX86_BUILTIN_VEC_EXT_V2SI,
28477 IX86_BUILTIN_VEC_EXT_V4HI,
28478 IX86_BUILTIN_VEC_EXT_V16QI,
28479 IX86_BUILTIN_VEC_SET_V2DI,
28480 IX86_BUILTIN_VEC_SET_V4SF,
28481 IX86_BUILTIN_VEC_SET_V4SI,
28482 IX86_BUILTIN_VEC_SET_V8HI,
28483 IX86_BUILTIN_VEC_SET_V4HI,
28484 IX86_BUILTIN_VEC_SET_V16QI,
28486 IX86_BUILTIN_VEC_PACK_SFIX,
28487 IX86_BUILTIN_VEC_PACK_SFIX256,
28489 /* SSE4.2. */
28490 IX86_BUILTIN_CRC32QI,
28491 IX86_BUILTIN_CRC32HI,
28492 IX86_BUILTIN_CRC32SI,
28493 IX86_BUILTIN_CRC32DI,
28495 IX86_BUILTIN_PCMPESTRI128,
28496 IX86_BUILTIN_PCMPESTRM128,
28497 IX86_BUILTIN_PCMPESTRA128,
28498 IX86_BUILTIN_PCMPESTRC128,
28499 IX86_BUILTIN_PCMPESTRO128,
28500 IX86_BUILTIN_PCMPESTRS128,
28501 IX86_BUILTIN_PCMPESTRZ128,
28502 IX86_BUILTIN_PCMPISTRI128,
28503 IX86_BUILTIN_PCMPISTRM128,
28504 IX86_BUILTIN_PCMPISTRA128,
28505 IX86_BUILTIN_PCMPISTRC128,
28506 IX86_BUILTIN_PCMPISTRO128,
28507 IX86_BUILTIN_PCMPISTRS128,
28508 IX86_BUILTIN_PCMPISTRZ128,
28510 IX86_BUILTIN_PCMPGTQ,
28512 /* AES instructions */
28513 IX86_BUILTIN_AESENC128,
28514 IX86_BUILTIN_AESENCLAST128,
28515 IX86_BUILTIN_AESDEC128,
28516 IX86_BUILTIN_AESDECLAST128,
28517 IX86_BUILTIN_AESIMC128,
28518 IX86_BUILTIN_AESKEYGENASSIST128,
28520 /* PCLMUL instruction */
28521 IX86_BUILTIN_PCLMULQDQ128,
28523 /* AVX */
28524 IX86_BUILTIN_ADDPD256,
28525 IX86_BUILTIN_ADDPS256,
28526 IX86_BUILTIN_ADDSUBPD256,
28527 IX86_BUILTIN_ADDSUBPS256,
28528 IX86_BUILTIN_ANDPD256,
28529 IX86_BUILTIN_ANDPS256,
28530 IX86_BUILTIN_ANDNPD256,
28531 IX86_BUILTIN_ANDNPS256,
28532 IX86_BUILTIN_BLENDPD256,
28533 IX86_BUILTIN_BLENDPS256,
28534 IX86_BUILTIN_BLENDVPD256,
28535 IX86_BUILTIN_BLENDVPS256,
28536 IX86_BUILTIN_DIVPD256,
28537 IX86_BUILTIN_DIVPS256,
28538 IX86_BUILTIN_DPPS256,
28539 IX86_BUILTIN_HADDPD256,
28540 IX86_BUILTIN_HADDPS256,
28541 IX86_BUILTIN_HSUBPD256,
28542 IX86_BUILTIN_HSUBPS256,
28543 IX86_BUILTIN_MAXPD256,
28544 IX86_BUILTIN_MAXPS256,
28545 IX86_BUILTIN_MINPD256,
28546 IX86_BUILTIN_MINPS256,
28547 IX86_BUILTIN_MULPD256,
28548 IX86_BUILTIN_MULPS256,
28549 IX86_BUILTIN_ORPD256,
28550 IX86_BUILTIN_ORPS256,
28551 IX86_BUILTIN_SHUFPD256,
28552 IX86_BUILTIN_SHUFPS256,
28553 IX86_BUILTIN_SUBPD256,
28554 IX86_BUILTIN_SUBPS256,
28555 IX86_BUILTIN_XORPD256,
28556 IX86_BUILTIN_XORPS256,
28557 IX86_BUILTIN_CMPSD,
28558 IX86_BUILTIN_CMPSS,
28559 IX86_BUILTIN_CMPPD,
28560 IX86_BUILTIN_CMPPS,
28561 IX86_BUILTIN_CMPPD256,
28562 IX86_BUILTIN_CMPPS256,
28563 IX86_BUILTIN_CVTDQ2PD256,
28564 IX86_BUILTIN_CVTDQ2PS256,
28565 IX86_BUILTIN_CVTPD2PS256,
28566 IX86_BUILTIN_CVTPS2DQ256,
28567 IX86_BUILTIN_CVTPS2PD256,
28568 IX86_BUILTIN_CVTTPD2DQ256,
28569 IX86_BUILTIN_CVTPD2DQ256,
28570 IX86_BUILTIN_CVTTPS2DQ256,
28571 IX86_BUILTIN_EXTRACTF128PD256,
28572 IX86_BUILTIN_EXTRACTF128PS256,
28573 IX86_BUILTIN_EXTRACTF128SI256,
28574 IX86_BUILTIN_VZEROALL,
28575 IX86_BUILTIN_VZEROUPPER,
28576 IX86_BUILTIN_VPERMILVARPD,
28577 IX86_BUILTIN_VPERMILVARPS,
28578 IX86_BUILTIN_VPERMILVARPD256,
28579 IX86_BUILTIN_VPERMILVARPS256,
28580 IX86_BUILTIN_VPERMILPD,
28581 IX86_BUILTIN_VPERMILPS,
28582 IX86_BUILTIN_VPERMILPD256,
28583 IX86_BUILTIN_VPERMILPS256,
28584 IX86_BUILTIN_VPERMIL2PD,
28585 IX86_BUILTIN_VPERMIL2PS,
28586 IX86_BUILTIN_VPERMIL2PD256,
28587 IX86_BUILTIN_VPERMIL2PS256,
28588 IX86_BUILTIN_VPERM2F128PD256,
28589 IX86_BUILTIN_VPERM2F128PS256,
28590 IX86_BUILTIN_VPERM2F128SI256,
28591 IX86_BUILTIN_VBROADCASTSS,
28592 IX86_BUILTIN_VBROADCASTSD256,
28593 IX86_BUILTIN_VBROADCASTSS256,
28594 IX86_BUILTIN_VBROADCASTPD256,
28595 IX86_BUILTIN_VBROADCASTPS256,
28596 IX86_BUILTIN_VINSERTF128PD256,
28597 IX86_BUILTIN_VINSERTF128PS256,
28598 IX86_BUILTIN_VINSERTF128SI256,
28599 IX86_BUILTIN_LOADUPD256,
28600 IX86_BUILTIN_LOADUPS256,
28601 IX86_BUILTIN_STOREUPD256,
28602 IX86_BUILTIN_STOREUPS256,
28603 IX86_BUILTIN_LDDQU256,
28604 IX86_BUILTIN_MOVNTDQ256,
28605 IX86_BUILTIN_MOVNTPD256,
28606 IX86_BUILTIN_MOVNTPS256,
28607 IX86_BUILTIN_LOADDQU256,
28608 IX86_BUILTIN_STOREDQU256,
28609 IX86_BUILTIN_MASKLOADPD,
28610 IX86_BUILTIN_MASKLOADPS,
28611 IX86_BUILTIN_MASKSTOREPD,
28612 IX86_BUILTIN_MASKSTOREPS,
28613 IX86_BUILTIN_MASKLOADPD256,
28614 IX86_BUILTIN_MASKLOADPS256,
28615 IX86_BUILTIN_MASKSTOREPD256,
28616 IX86_BUILTIN_MASKSTOREPS256,
28617 IX86_BUILTIN_MOVSHDUP256,
28618 IX86_BUILTIN_MOVSLDUP256,
28619 IX86_BUILTIN_MOVDDUP256,
28621 IX86_BUILTIN_SQRTPD256,
28622 IX86_BUILTIN_SQRTPS256,
28623 IX86_BUILTIN_SQRTPS_NR256,
28624 IX86_BUILTIN_RSQRTPS256,
28625 IX86_BUILTIN_RSQRTPS_NR256,
28627 IX86_BUILTIN_RCPPS256,
28629 IX86_BUILTIN_ROUNDPD256,
28630 IX86_BUILTIN_ROUNDPS256,
28632 IX86_BUILTIN_FLOORPD256,
28633 IX86_BUILTIN_CEILPD256,
28634 IX86_BUILTIN_TRUNCPD256,
28635 IX86_BUILTIN_RINTPD256,
28636 IX86_BUILTIN_ROUNDPD_AZ256,
28638 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
28639 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
28640 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
28642 IX86_BUILTIN_FLOORPS256,
28643 IX86_BUILTIN_CEILPS256,
28644 IX86_BUILTIN_TRUNCPS256,
28645 IX86_BUILTIN_RINTPS256,
28646 IX86_BUILTIN_ROUNDPS_AZ256,
28648 IX86_BUILTIN_FLOORPS_SFIX256,
28649 IX86_BUILTIN_CEILPS_SFIX256,
28650 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
28652 IX86_BUILTIN_UNPCKHPD256,
28653 IX86_BUILTIN_UNPCKLPD256,
28654 IX86_BUILTIN_UNPCKHPS256,
28655 IX86_BUILTIN_UNPCKLPS256,
28657 IX86_BUILTIN_SI256_SI,
28658 IX86_BUILTIN_PS256_PS,
28659 IX86_BUILTIN_PD256_PD,
28660 IX86_BUILTIN_SI_SI256,
28661 IX86_BUILTIN_PS_PS256,
28662 IX86_BUILTIN_PD_PD256,
28664 IX86_BUILTIN_VTESTZPD,
28665 IX86_BUILTIN_VTESTCPD,
28666 IX86_BUILTIN_VTESTNZCPD,
28667 IX86_BUILTIN_VTESTZPS,
28668 IX86_BUILTIN_VTESTCPS,
28669 IX86_BUILTIN_VTESTNZCPS,
28670 IX86_BUILTIN_VTESTZPD256,
28671 IX86_BUILTIN_VTESTCPD256,
28672 IX86_BUILTIN_VTESTNZCPD256,
28673 IX86_BUILTIN_VTESTZPS256,
28674 IX86_BUILTIN_VTESTCPS256,
28675 IX86_BUILTIN_VTESTNZCPS256,
28676 IX86_BUILTIN_PTESTZ256,
28677 IX86_BUILTIN_PTESTC256,
28678 IX86_BUILTIN_PTESTNZC256,
28680 IX86_BUILTIN_MOVMSKPD256,
28681 IX86_BUILTIN_MOVMSKPS256,
28683 /* AVX2 */
28684 IX86_BUILTIN_MPSADBW256,
28685 IX86_BUILTIN_PABSB256,
28686 IX86_BUILTIN_PABSW256,
28687 IX86_BUILTIN_PABSD256,
28688 IX86_BUILTIN_PACKSSDW256,
28689 IX86_BUILTIN_PACKSSWB256,
28690 IX86_BUILTIN_PACKUSDW256,
28691 IX86_BUILTIN_PACKUSWB256,
28692 IX86_BUILTIN_PADDB256,
28693 IX86_BUILTIN_PADDW256,
28694 IX86_BUILTIN_PADDD256,
28695 IX86_BUILTIN_PADDQ256,
28696 IX86_BUILTIN_PADDSB256,
28697 IX86_BUILTIN_PADDSW256,
28698 IX86_BUILTIN_PADDUSB256,
28699 IX86_BUILTIN_PADDUSW256,
28700 IX86_BUILTIN_PALIGNR256,
28701 IX86_BUILTIN_AND256I,
28702 IX86_BUILTIN_ANDNOT256I,
28703 IX86_BUILTIN_PAVGB256,
28704 IX86_BUILTIN_PAVGW256,
28705 IX86_BUILTIN_PBLENDVB256,
28706 IX86_BUILTIN_PBLENDVW256,
28707 IX86_BUILTIN_PCMPEQB256,
28708 IX86_BUILTIN_PCMPEQW256,
28709 IX86_BUILTIN_PCMPEQD256,
28710 IX86_BUILTIN_PCMPEQQ256,
28711 IX86_BUILTIN_PCMPGTB256,
28712 IX86_BUILTIN_PCMPGTW256,
28713 IX86_BUILTIN_PCMPGTD256,
28714 IX86_BUILTIN_PCMPGTQ256,
28715 IX86_BUILTIN_PHADDW256,
28716 IX86_BUILTIN_PHADDD256,
28717 IX86_BUILTIN_PHADDSW256,
28718 IX86_BUILTIN_PHSUBW256,
28719 IX86_BUILTIN_PHSUBD256,
28720 IX86_BUILTIN_PHSUBSW256,
28721 IX86_BUILTIN_PMADDUBSW256,
28722 IX86_BUILTIN_PMADDWD256,
28723 IX86_BUILTIN_PMAXSB256,
28724 IX86_BUILTIN_PMAXSW256,
28725 IX86_BUILTIN_PMAXSD256,
28726 IX86_BUILTIN_PMAXUB256,
28727 IX86_BUILTIN_PMAXUW256,
28728 IX86_BUILTIN_PMAXUD256,
28729 IX86_BUILTIN_PMINSB256,
28730 IX86_BUILTIN_PMINSW256,
28731 IX86_BUILTIN_PMINSD256,
28732 IX86_BUILTIN_PMINUB256,
28733 IX86_BUILTIN_PMINUW256,
28734 IX86_BUILTIN_PMINUD256,
28735 IX86_BUILTIN_PMOVMSKB256,
28736 IX86_BUILTIN_PMOVSXBW256,
28737 IX86_BUILTIN_PMOVSXBD256,
28738 IX86_BUILTIN_PMOVSXBQ256,
28739 IX86_BUILTIN_PMOVSXWD256,
28740 IX86_BUILTIN_PMOVSXWQ256,
28741 IX86_BUILTIN_PMOVSXDQ256,
28742 IX86_BUILTIN_PMOVZXBW256,
28743 IX86_BUILTIN_PMOVZXBD256,
28744 IX86_BUILTIN_PMOVZXBQ256,
28745 IX86_BUILTIN_PMOVZXWD256,
28746 IX86_BUILTIN_PMOVZXWQ256,
28747 IX86_BUILTIN_PMOVZXDQ256,
28748 IX86_BUILTIN_PMULDQ256,
28749 IX86_BUILTIN_PMULHRSW256,
28750 IX86_BUILTIN_PMULHUW256,
28751 IX86_BUILTIN_PMULHW256,
28752 IX86_BUILTIN_PMULLW256,
28753 IX86_BUILTIN_PMULLD256,
28754 IX86_BUILTIN_PMULUDQ256,
28755 IX86_BUILTIN_POR256,
28756 IX86_BUILTIN_PSADBW256,
28757 IX86_BUILTIN_PSHUFB256,
28758 IX86_BUILTIN_PSHUFD256,
28759 IX86_BUILTIN_PSHUFHW256,
28760 IX86_BUILTIN_PSHUFLW256,
28761 IX86_BUILTIN_PSIGNB256,
28762 IX86_BUILTIN_PSIGNW256,
28763 IX86_BUILTIN_PSIGND256,
28764 IX86_BUILTIN_PSLLDQI256,
28765 IX86_BUILTIN_PSLLWI256,
28766 IX86_BUILTIN_PSLLW256,
28767 IX86_BUILTIN_PSLLDI256,
28768 IX86_BUILTIN_PSLLD256,
28769 IX86_BUILTIN_PSLLQI256,
28770 IX86_BUILTIN_PSLLQ256,
28771 IX86_BUILTIN_PSRAWI256,
28772 IX86_BUILTIN_PSRAW256,
28773 IX86_BUILTIN_PSRADI256,
28774 IX86_BUILTIN_PSRAD256,
28775 IX86_BUILTIN_PSRLDQI256,
28776 IX86_BUILTIN_PSRLWI256,
28777 IX86_BUILTIN_PSRLW256,
28778 IX86_BUILTIN_PSRLDI256,
28779 IX86_BUILTIN_PSRLD256,
28780 IX86_BUILTIN_PSRLQI256,
28781 IX86_BUILTIN_PSRLQ256,
28782 IX86_BUILTIN_PSUBB256,
28783 IX86_BUILTIN_PSUBW256,
28784 IX86_BUILTIN_PSUBD256,
28785 IX86_BUILTIN_PSUBQ256,
28786 IX86_BUILTIN_PSUBSB256,
28787 IX86_BUILTIN_PSUBSW256,
28788 IX86_BUILTIN_PSUBUSB256,
28789 IX86_BUILTIN_PSUBUSW256,
28790 IX86_BUILTIN_PUNPCKHBW256,
28791 IX86_BUILTIN_PUNPCKHWD256,
28792 IX86_BUILTIN_PUNPCKHDQ256,
28793 IX86_BUILTIN_PUNPCKHQDQ256,
28794 IX86_BUILTIN_PUNPCKLBW256,
28795 IX86_BUILTIN_PUNPCKLWD256,
28796 IX86_BUILTIN_PUNPCKLDQ256,
28797 IX86_BUILTIN_PUNPCKLQDQ256,
28798 IX86_BUILTIN_PXOR256,
28799 IX86_BUILTIN_MOVNTDQA256,
28800 IX86_BUILTIN_VBROADCASTSS_PS,
28801 IX86_BUILTIN_VBROADCASTSS_PS256,
28802 IX86_BUILTIN_VBROADCASTSD_PD256,
28803 IX86_BUILTIN_VBROADCASTSI256,
28804 IX86_BUILTIN_PBLENDD256,
28805 IX86_BUILTIN_PBLENDD128,
28806 IX86_BUILTIN_PBROADCASTB256,
28807 IX86_BUILTIN_PBROADCASTW256,
28808 IX86_BUILTIN_PBROADCASTD256,
28809 IX86_BUILTIN_PBROADCASTQ256,
28810 IX86_BUILTIN_PBROADCASTB128,
28811 IX86_BUILTIN_PBROADCASTW128,
28812 IX86_BUILTIN_PBROADCASTD128,
28813 IX86_BUILTIN_PBROADCASTQ128,
28814 IX86_BUILTIN_VPERMVARSI256,
28815 IX86_BUILTIN_VPERMDF256,
28816 IX86_BUILTIN_VPERMVARSF256,
28817 IX86_BUILTIN_VPERMDI256,
28818 IX86_BUILTIN_VPERMTI256,
28819 IX86_BUILTIN_VEXTRACT128I256,
28820 IX86_BUILTIN_VINSERT128I256,
28821 IX86_BUILTIN_MASKLOADD,
28822 IX86_BUILTIN_MASKLOADQ,
28823 IX86_BUILTIN_MASKLOADD256,
28824 IX86_BUILTIN_MASKLOADQ256,
28825 IX86_BUILTIN_MASKSTORED,
28826 IX86_BUILTIN_MASKSTOREQ,
28827 IX86_BUILTIN_MASKSTORED256,
28828 IX86_BUILTIN_MASKSTOREQ256,
28829 IX86_BUILTIN_PSLLVV4DI,
28830 IX86_BUILTIN_PSLLVV2DI,
28831 IX86_BUILTIN_PSLLVV8SI,
28832 IX86_BUILTIN_PSLLVV4SI,
28833 IX86_BUILTIN_PSRAVV8SI,
28834 IX86_BUILTIN_PSRAVV4SI,
28835 IX86_BUILTIN_PSRLVV4DI,
28836 IX86_BUILTIN_PSRLVV2DI,
28837 IX86_BUILTIN_PSRLVV8SI,
28838 IX86_BUILTIN_PSRLVV4SI,
28840 IX86_BUILTIN_GATHERSIV2DF,
28841 IX86_BUILTIN_GATHERSIV4DF,
28842 IX86_BUILTIN_GATHERDIV2DF,
28843 IX86_BUILTIN_GATHERDIV4DF,
28844 IX86_BUILTIN_GATHERSIV4SF,
28845 IX86_BUILTIN_GATHERSIV8SF,
28846 IX86_BUILTIN_GATHERDIV4SF,
28847 IX86_BUILTIN_GATHERDIV8SF,
28848 IX86_BUILTIN_GATHERSIV2DI,
28849 IX86_BUILTIN_GATHERSIV4DI,
28850 IX86_BUILTIN_GATHERDIV2DI,
28851 IX86_BUILTIN_GATHERDIV4DI,
28852 IX86_BUILTIN_GATHERSIV4SI,
28853 IX86_BUILTIN_GATHERSIV8SI,
28854 IX86_BUILTIN_GATHERDIV4SI,
28855 IX86_BUILTIN_GATHERDIV8SI,
28857 /* AVX512F */
28858 IX86_BUILTIN_SI512_SI256,
28859 IX86_BUILTIN_PD512_PD256,
28860 IX86_BUILTIN_PS512_PS256,
28861 IX86_BUILTIN_SI512_SI,
28862 IX86_BUILTIN_PD512_PD,
28863 IX86_BUILTIN_PS512_PS,
28864 IX86_BUILTIN_ADDPD512,
28865 IX86_BUILTIN_ADDPS512,
28866 IX86_BUILTIN_ADDSD_ROUND,
28867 IX86_BUILTIN_ADDSS_ROUND,
28868 IX86_BUILTIN_ALIGND512,
28869 IX86_BUILTIN_ALIGNQ512,
28870 IX86_BUILTIN_BLENDMD512,
28871 IX86_BUILTIN_BLENDMPD512,
28872 IX86_BUILTIN_BLENDMPS512,
28873 IX86_BUILTIN_BLENDMQ512,
28874 IX86_BUILTIN_BROADCASTF32X4_512,
28875 IX86_BUILTIN_BROADCASTF64X4_512,
28876 IX86_BUILTIN_BROADCASTI32X4_512,
28877 IX86_BUILTIN_BROADCASTI64X4_512,
28878 IX86_BUILTIN_BROADCASTSD512,
28879 IX86_BUILTIN_BROADCASTSS512,
28880 IX86_BUILTIN_CMPD512,
28881 IX86_BUILTIN_CMPPD512,
28882 IX86_BUILTIN_CMPPS512,
28883 IX86_BUILTIN_CMPQ512,
28884 IX86_BUILTIN_CMPSD_MASK,
28885 IX86_BUILTIN_CMPSS_MASK,
28886 IX86_BUILTIN_COMIDF,
28887 IX86_BUILTIN_COMISF,
28888 IX86_BUILTIN_COMPRESSPD512,
28889 IX86_BUILTIN_COMPRESSPDSTORE512,
28890 IX86_BUILTIN_COMPRESSPS512,
28891 IX86_BUILTIN_COMPRESSPSSTORE512,
28892 IX86_BUILTIN_CVTDQ2PD512,
28893 IX86_BUILTIN_CVTDQ2PS512,
28894 IX86_BUILTIN_CVTPD2DQ512,
28895 IX86_BUILTIN_CVTPD2PS512,
28896 IX86_BUILTIN_CVTPD2UDQ512,
28897 IX86_BUILTIN_CVTPH2PS512,
28898 IX86_BUILTIN_CVTPS2DQ512,
28899 IX86_BUILTIN_CVTPS2PD512,
28900 IX86_BUILTIN_CVTPS2PH512,
28901 IX86_BUILTIN_CVTPS2UDQ512,
28902 IX86_BUILTIN_CVTSD2SS_ROUND,
28903 IX86_BUILTIN_CVTSI2SD64,
28904 IX86_BUILTIN_CVTSI2SS32,
28905 IX86_BUILTIN_CVTSI2SS64,
28906 IX86_BUILTIN_CVTSS2SD_ROUND,
28907 IX86_BUILTIN_CVTTPD2DQ512,
28908 IX86_BUILTIN_CVTTPD2UDQ512,
28909 IX86_BUILTIN_CVTTPS2DQ512,
28910 IX86_BUILTIN_CVTTPS2UDQ512,
28911 IX86_BUILTIN_CVTUDQ2PD512,
28912 IX86_BUILTIN_CVTUDQ2PS512,
28913 IX86_BUILTIN_CVTUSI2SD32,
28914 IX86_BUILTIN_CVTUSI2SD64,
28915 IX86_BUILTIN_CVTUSI2SS32,
28916 IX86_BUILTIN_CVTUSI2SS64,
28917 IX86_BUILTIN_DIVPD512,
28918 IX86_BUILTIN_DIVPS512,
28919 IX86_BUILTIN_DIVSD_ROUND,
28920 IX86_BUILTIN_DIVSS_ROUND,
28921 IX86_BUILTIN_EXPANDPD512,
28922 IX86_BUILTIN_EXPANDPD512Z,
28923 IX86_BUILTIN_EXPANDPDLOAD512,
28924 IX86_BUILTIN_EXPANDPDLOAD512Z,
28925 IX86_BUILTIN_EXPANDPS512,
28926 IX86_BUILTIN_EXPANDPS512Z,
28927 IX86_BUILTIN_EXPANDPSLOAD512,
28928 IX86_BUILTIN_EXPANDPSLOAD512Z,
28929 IX86_BUILTIN_EXTRACTF32X4,
28930 IX86_BUILTIN_EXTRACTF64X4,
28931 IX86_BUILTIN_EXTRACTI32X4,
28932 IX86_BUILTIN_EXTRACTI64X4,
28933 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28934 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28935 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28936 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28937 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28938 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28939 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28940 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28941 IX86_BUILTIN_GETEXPPD512,
28942 IX86_BUILTIN_GETEXPPS512,
28943 IX86_BUILTIN_GETEXPSD128,
28944 IX86_BUILTIN_GETEXPSS128,
28945 IX86_BUILTIN_GETMANTPD512,
28946 IX86_BUILTIN_GETMANTPS512,
28947 IX86_BUILTIN_GETMANTSD128,
28948 IX86_BUILTIN_GETMANTSS128,
28949 IX86_BUILTIN_INSERTF32X4,
28950 IX86_BUILTIN_INSERTF64X4,
28951 IX86_BUILTIN_INSERTI32X4,
28952 IX86_BUILTIN_INSERTI64X4,
28953 IX86_BUILTIN_LOADAPD512,
28954 IX86_BUILTIN_LOADAPS512,
28955 IX86_BUILTIN_LOADDQUDI512,
28956 IX86_BUILTIN_LOADDQUSI512,
28957 IX86_BUILTIN_LOADUPD512,
28958 IX86_BUILTIN_LOADUPS512,
28959 IX86_BUILTIN_MAXPD512,
28960 IX86_BUILTIN_MAXPS512,
28961 IX86_BUILTIN_MAXSD_ROUND,
28962 IX86_BUILTIN_MAXSS_ROUND,
28963 IX86_BUILTIN_MINPD512,
28964 IX86_BUILTIN_MINPS512,
28965 IX86_BUILTIN_MINSD_ROUND,
28966 IX86_BUILTIN_MINSS_ROUND,
28967 IX86_BUILTIN_MOVAPD512,
28968 IX86_BUILTIN_MOVAPS512,
28969 IX86_BUILTIN_MOVDDUP512,
28970 IX86_BUILTIN_MOVDQA32LOAD512,
28971 IX86_BUILTIN_MOVDQA32STORE512,
28972 IX86_BUILTIN_MOVDQA32_512,
28973 IX86_BUILTIN_MOVDQA64LOAD512,
28974 IX86_BUILTIN_MOVDQA64STORE512,
28975 IX86_BUILTIN_MOVDQA64_512,
28976 IX86_BUILTIN_MOVNTDQ512,
28977 IX86_BUILTIN_MOVNTDQA512,
28978 IX86_BUILTIN_MOVNTPD512,
28979 IX86_BUILTIN_MOVNTPS512,
28980 IX86_BUILTIN_MOVSHDUP512,
28981 IX86_BUILTIN_MOVSLDUP512,
28982 IX86_BUILTIN_MULPD512,
28983 IX86_BUILTIN_MULPS512,
28984 IX86_BUILTIN_MULSD_ROUND,
28985 IX86_BUILTIN_MULSS_ROUND,
28986 IX86_BUILTIN_PABSD512,
28987 IX86_BUILTIN_PABSQ512,
28988 IX86_BUILTIN_PADDD512,
28989 IX86_BUILTIN_PADDQ512,
28990 IX86_BUILTIN_PANDD512,
28991 IX86_BUILTIN_PANDND512,
28992 IX86_BUILTIN_PANDNQ512,
28993 IX86_BUILTIN_PANDQ512,
28994 IX86_BUILTIN_PBROADCASTD512,
28995 IX86_BUILTIN_PBROADCASTD512_GPR,
28996 IX86_BUILTIN_PBROADCASTMB512,
28997 IX86_BUILTIN_PBROADCASTMW512,
28998 IX86_BUILTIN_PBROADCASTQ512,
28999 IX86_BUILTIN_PBROADCASTQ512_GPR,
29000 IX86_BUILTIN_PCMPEQD512_MASK,
29001 IX86_BUILTIN_PCMPEQQ512_MASK,
29002 IX86_BUILTIN_PCMPGTD512_MASK,
29003 IX86_BUILTIN_PCMPGTQ512_MASK,
29004 IX86_BUILTIN_PCOMPRESSD512,
29005 IX86_BUILTIN_PCOMPRESSDSTORE512,
29006 IX86_BUILTIN_PCOMPRESSQ512,
29007 IX86_BUILTIN_PCOMPRESSQSTORE512,
29008 IX86_BUILTIN_PEXPANDD512,
29009 IX86_BUILTIN_PEXPANDD512Z,
29010 IX86_BUILTIN_PEXPANDDLOAD512,
29011 IX86_BUILTIN_PEXPANDDLOAD512Z,
29012 IX86_BUILTIN_PEXPANDQ512,
29013 IX86_BUILTIN_PEXPANDQ512Z,
29014 IX86_BUILTIN_PEXPANDQLOAD512,
29015 IX86_BUILTIN_PEXPANDQLOAD512Z,
29016 IX86_BUILTIN_PMAXSD512,
29017 IX86_BUILTIN_PMAXSQ512,
29018 IX86_BUILTIN_PMAXUD512,
29019 IX86_BUILTIN_PMAXUQ512,
29020 IX86_BUILTIN_PMINSD512,
29021 IX86_BUILTIN_PMINSQ512,
29022 IX86_BUILTIN_PMINUD512,
29023 IX86_BUILTIN_PMINUQ512,
29024 IX86_BUILTIN_PMOVDB512,
29025 IX86_BUILTIN_PMOVDB512_MEM,
29026 IX86_BUILTIN_PMOVDW512,
29027 IX86_BUILTIN_PMOVDW512_MEM,
29028 IX86_BUILTIN_PMOVQB512,
29029 IX86_BUILTIN_PMOVQB512_MEM,
29030 IX86_BUILTIN_PMOVQD512,
29031 IX86_BUILTIN_PMOVQD512_MEM,
29032 IX86_BUILTIN_PMOVQW512,
29033 IX86_BUILTIN_PMOVQW512_MEM,
29034 IX86_BUILTIN_PMOVSDB512,
29035 IX86_BUILTIN_PMOVSDB512_MEM,
29036 IX86_BUILTIN_PMOVSDW512,
29037 IX86_BUILTIN_PMOVSDW512_MEM,
29038 IX86_BUILTIN_PMOVSQB512,
29039 IX86_BUILTIN_PMOVSQB512_MEM,
29040 IX86_BUILTIN_PMOVSQD512,
29041 IX86_BUILTIN_PMOVSQD512_MEM,
29042 IX86_BUILTIN_PMOVSQW512,
29043 IX86_BUILTIN_PMOVSQW512_MEM,
29044 IX86_BUILTIN_PMOVSXBD512,
29045 IX86_BUILTIN_PMOVSXBQ512,
29046 IX86_BUILTIN_PMOVSXDQ512,
29047 IX86_BUILTIN_PMOVSXWD512,
29048 IX86_BUILTIN_PMOVSXWQ512,
29049 IX86_BUILTIN_PMOVUSDB512,
29050 IX86_BUILTIN_PMOVUSDB512_MEM,
29051 IX86_BUILTIN_PMOVUSDW512,
29052 IX86_BUILTIN_PMOVUSDW512_MEM,
29053 IX86_BUILTIN_PMOVUSQB512,
29054 IX86_BUILTIN_PMOVUSQB512_MEM,
29055 IX86_BUILTIN_PMOVUSQD512,
29056 IX86_BUILTIN_PMOVUSQD512_MEM,
29057 IX86_BUILTIN_PMOVUSQW512,
29058 IX86_BUILTIN_PMOVUSQW512_MEM,
29059 IX86_BUILTIN_PMOVZXBD512,
29060 IX86_BUILTIN_PMOVZXBQ512,
29061 IX86_BUILTIN_PMOVZXDQ512,
29062 IX86_BUILTIN_PMOVZXWD512,
29063 IX86_BUILTIN_PMOVZXWQ512,
29064 IX86_BUILTIN_PMULDQ512,
29065 IX86_BUILTIN_PMULLD512,
29066 IX86_BUILTIN_PMULUDQ512,
29067 IX86_BUILTIN_PORD512,
29068 IX86_BUILTIN_PORQ512,
29069 IX86_BUILTIN_PROLD512,
29070 IX86_BUILTIN_PROLQ512,
29071 IX86_BUILTIN_PROLVD512,
29072 IX86_BUILTIN_PROLVQ512,
29073 IX86_BUILTIN_PRORD512,
29074 IX86_BUILTIN_PRORQ512,
29075 IX86_BUILTIN_PRORVD512,
29076 IX86_BUILTIN_PRORVQ512,
29077 IX86_BUILTIN_PSHUFD512,
29078 IX86_BUILTIN_PSLLD512,
29079 IX86_BUILTIN_PSLLDI512,
29080 IX86_BUILTIN_PSLLQ512,
29081 IX86_BUILTIN_PSLLQI512,
29082 IX86_BUILTIN_PSLLVV16SI,
29083 IX86_BUILTIN_PSLLVV8DI,
29084 IX86_BUILTIN_PSRAD512,
29085 IX86_BUILTIN_PSRADI512,
29086 IX86_BUILTIN_PSRAQ512,
29087 IX86_BUILTIN_PSRAQI512,
29088 IX86_BUILTIN_PSRAVV16SI,
29089 IX86_BUILTIN_PSRAVV8DI,
29090 IX86_BUILTIN_PSRLD512,
29091 IX86_BUILTIN_PSRLDI512,
29092 IX86_BUILTIN_PSRLQ512,
29093 IX86_BUILTIN_PSRLQI512,
29094 IX86_BUILTIN_PSRLVV16SI,
29095 IX86_BUILTIN_PSRLVV8DI,
29096 IX86_BUILTIN_PSUBD512,
29097 IX86_BUILTIN_PSUBQ512,
29098 IX86_BUILTIN_PTESTMD512,
29099 IX86_BUILTIN_PTESTMQ512,
29100 IX86_BUILTIN_PTESTNMD512,
29101 IX86_BUILTIN_PTESTNMQ512,
29102 IX86_BUILTIN_PUNPCKHDQ512,
29103 IX86_BUILTIN_PUNPCKHQDQ512,
29104 IX86_BUILTIN_PUNPCKLDQ512,
29105 IX86_BUILTIN_PUNPCKLQDQ512,
29106 IX86_BUILTIN_PXORD512,
29107 IX86_BUILTIN_PXORQ512,
29108 IX86_BUILTIN_RCP14PD512,
29109 IX86_BUILTIN_RCP14PS512,
29110 IX86_BUILTIN_RCP14SD,
29111 IX86_BUILTIN_RCP14SS,
29112 IX86_BUILTIN_RNDSCALEPD,
29113 IX86_BUILTIN_RNDSCALEPS,
29114 IX86_BUILTIN_RNDSCALESD,
29115 IX86_BUILTIN_RNDSCALESS,
29116 IX86_BUILTIN_RSQRT14PD512,
29117 IX86_BUILTIN_RSQRT14PS512,
29118 IX86_BUILTIN_RSQRT14SD,
29119 IX86_BUILTIN_RSQRT14SS,
29120 IX86_BUILTIN_SCALEFPD512,
29121 IX86_BUILTIN_SCALEFPS512,
29122 IX86_BUILTIN_SCALEFSD,
29123 IX86_BUILTIN_SCALEFSS,
29124 IX86_BUILTIN_SHUFPD512,
29125 IX86_BUILTIN_SHUFPS512,
29126 IX86_BUILTIN_SHUF_F32x4,
29127 IX86_BUILTIN_SHUF_F64x2,
29128 IX86_BUILTIN_SHUF_I32x4,
29129 IX86_BUILTIN_SHUF_I64x2,
29130 IX86_BUILTIN_SQRTPD512,
29131 IX86_BUILTIN_SQRTPD512_MASK,
29132 IX86_BUILTIN_SQRTPS512_MASK,
29133 IX86_BUILTIN_SQRTPS_NR512,
29134 IX86_BUILTIN_SQRTSD_ROUND,
29135 IX86_BUILTIN_SQRTSS_ROUND,
29136 IX86_BUILTIN_STOREAPD512,
29137 IX86_BUILTIN_STOREAPS512,
29138 IX86_BUILTIN_STOREDQUDI512,
29139 IX86_BUILTIN_STOREDQUSI512,
29140 IX86_BUILTIN_STOREUPD512,
29141 IX86_BUILTIN_STOREUPS512,
29142 IX86_BUILTIN_SUBPD512,
29143 IX86_BUILTIN_SUBPS512,
29144 IX86_BUILTIN_SUBSD_ROUND,
29145 IX86_BUILTIN_SUBSS_ROUND,
29146 IX86_BUILTIN_UCMPD512,
29147 IX86_BUILTIN_UCMPQ512,
29148 IX86_BUILTIN_UNPCKHPD512,
29149 IX86_BUILTIN_UNPCKHPS512,
29150 IX86_BUILTIN_UNPCKLPD512,
29151 IX86_BUILTIN_UNPCKLPS512,
29152 IX86_BUILTIN_VCVTSD2SI32,
29153 IX86_BUILTIN_VCVTSD2SI64,
29154 IX86_BUILTIN_VCVTSD2USI32,
29155 IX86_BUILTIN_VCVTSD2USI64,
29156 IX86_BUILTIN_VCVTSS2SI32,
29157 IX86_BUILTIN_VCVTSS2SI64,
29158 IX86_BUILTIN_VCVTSS2USI32,
29159 IX86_BUILTIN_VCVTSS2USI64,
29160 IX86_BUILTIN_VCVTTSD2SI32,
29161 IX86_BUILTIN_VCVTTSD2SI64,
29162 IX86_BUILTIN_VCVTTSD2USI32,
29163 IX86_BUILTIN_VCVTTSD2USI64,
29164 IX86_BUILTIN_VCVTTSS2SI32,
29165 IX86_BUILTIN_VCVTTSS2SI64,
29166 IX86_BUILTIN_VCVTTSS2USI32,
29167 IX86_BUILTIN_VCVTTSS2USI64,
29168 IX86_BUILTIN_VFMADDPD512_MASK,
29169 IX86_BUILTIN_VFMADDPD512_MASK3,
29170 IX86_BUILTIN_VFMADDPD512_MASKZ,
29171 IX86_BUILTIN_VFMADDPS512_MASK,
29172 IX86_BUILTIN_VFMADDPS512_MASK3,
29173 IX86_BUILTIN_VFMADDPS512_MASKZ,
29174 IX86_BUILTIN_VFMADDSD3_ROUND,
29175 IX86_BUILTIN_VFMADDSS3_ROUND,
29176 IX86_BUILTIN_VFMADDSUBPD512_MASK,
29177 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
29178 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
29179 IX86_BUILTIN_VFMADDSUBPS512_MASK,
29180 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
29181 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
29182 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
29183 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
29184 IX86_BUILTIN_VFMSUBPD512_MASK3,
29185 IX86_BUILTIN_VFMSUBPS512_MASK3,
29186 IX86_BUILTIN_VFMSUBSD3_MASK3,
29187 IX86_BUILTIN_VFMSUBSS3_MASK3,
29188 IX86_BUILTIN_VFNMADDPD512_MASK,
29189 IX86_BUILTIN_VFNMADDPS512_MASK,
29190 IX86_BUILTIN_VFNMSUBPD512_MASK,
29191 IX86_BUILTIN_VFNMSUBPD512_MASK3,
29192 IX86_BUILTIN_VFNMSUBPS512_MASK,
29193 IX86_BUILTIN_VFNMSUBPS512_MASK3,
29194 IX86_BUILTIN_VPCLZCNTD512,
29195 IX86_BUILTIN_VPCLZCNTQ512,
29196 IX86_BUILTIN_VPCONFLICTD512,
29197 IX86_BUILTIN_VPCONFLICTQ512,
29198 IX86_BUILTIN_VPERMDF512,
29199 IX86_BUILTIN_VPERMDI512,
29200 IX86_BUILTIN_VPERMI2VARD512,
29201 IX86_BUILTIN_VPERMI2VARPD512,
29202 IX86_BUILTIN_VPERMI2VARPS512,
29203 IX86_BUILTIN_VPERMI2VARQ512,
29204 IX86_BUILTIN_VPERMILPD512,
29205 IX86_BUILTIN_VPERMILPS512,
29206 IX86_BUILTIN_VPERMILVARPD512,
29207 IX86_BUILTIN_VPERMILVARPS512,
29208 IX86_BUILTIN_VPERMT2VARD512,
29209 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
29210 IX86_BUILTIN_VPERMT2VARPD512,
29211 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
29212 IX86_BUILTIN_VPERMT2VARPS512,
29213 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
29214 IX86_BUILTIN_VPERMT2VARQ512,
29215 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
29216 IX86_BUILTIN_VPERMVARDF512,
29217 IX86_BUILTIN_VPERMVARDI512,
29218 IX86_BUILTIN_VPERMVARSF512,
29219 IX86_BUILTIN_VPERMVARSI512,
29220 IX86_BUILTIN_VTERNLOGD512_MASK,
29221 IX86_BUILTIN_VTERNLOGD512_MASKZ,
29222 IX86_BUILTIN_VTERNLOGQ512_MASK,
29223 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
29225 /* Mask arithmetic operations */
29226 IX86_BUILTIN_KAND16,
29227 IX86_BUILTIN_KANDN16,
29228 IX86_BUILTIN_KNOT16,
29229 IX86_BUILTIN_KOR16,
29230 IX86_BUILTIN_KORTESTC16,
29231 IX86_BUILTIN_KORTESTZ16,
29232 IX86_BUILTIN_KUNPCKBW,
29233 IX86_BUILTIN_KXNOR16,
29234 IX86_BUILTIN_KXOR16,
29235 IX86_BUILTIN_KMOV16,
29237 /* AVX512VL. */
29238 IX86_BUILTIN_PMOVUSQD256_MEM,
29239 IX86_BUILTIN_PMOVUSQD128_MEM,
29240 IX86_BUILTIN_PMOVSQD256_MEM,
29241 IX86_BUILTIN_PMOVSQD128_MEM,
29242 IX86_BUILTIN_PMOVQD256_MEM,
29243 IX86_BUILTIN_PMOVQD128_MEM,
29244 IX86_BUILTIN_PMOVUSQW256_MEM,
29245 IX86_BUILTIN_PMOVUSQW128_MEM,
29246 IX86_BUILTIN_PMOVSQW256_MEM,
29247 IX86_BUILTIN_PMOVSQW128_MEM,
29248 IX86_BUILTIN_PMOVQW256_MEM,
29249 IX86_BUILTIN_PMOVQW128_MEM,
29250 IX86_BUILTIN_PMOVUSQB256_MEM,
29251 IX86_BUILTIN_PMOVUSQB128_MEM,
29252 IX86_BUILTIN_PMOVSQB256_MEM,
29253 IX86_BUILTIN_PMOVSQB128_MEM,
29254 IX86_BUILTIN_PMOVQB256_MEM,
29255 IX86_BUILTIN_PMOVQB128_MEM,
29256 IX86_BUILTIN_PMOVUSDW256_MEM,
29257 IX86_BUILTIN_PMOVUSDW128_MEM,
29258 IX86_BUILTIN_PMOVSDW256_MEM,
29259 IX86_BUILTIN_PMOVSDW128_MEM,
29260 IX86_BUILTIN_PMOVDW256_MEM,
29261 IX86_BUILTIN_PMOVDW128_MEM,
29262 IX86_BUILTIN_PMOVUSDB256_MEM,
29263 IX86_BUILTIN_PMOVUSDB128_MEM,
29264 IX86_BUILTIN_PMOVSDB256_MEM,
29265 IX86_BUILTIN_PMOVSDB128_MEM,
29266 IX86_BUILTIN_PMOVDB256_MEM,
29267 IX86_BUILTIN_PMOVDB128_MEM,
29268 IX86_BUILTIN_MOVDQA64LOAD256_MASK,
29269 IX86_BUILTIN_MOVDQA64LOAD128_MASK,
29270 IX86_BUILTIN_MOVDQA32LOAD256_MASK,
29271 IX86_BUILTIN_MOVDQA32LOAD128_MASK,
29272 IX86_BUILTIN_MOVDQA64STORE256_MASK,
29273 IX86_BUILTIN_MOVDQA64STORE128_MASK,
29274 IX86_BUILTIN_MOVDQA32STORE256_MASK,
29275 IX86_BUILTIN_MOVDQA32STORE128_MASK,
29276 IX86_BUILTIN_LOADAPD256_MASK,
29277 IX86_BUILTIN_LOADAPD128_MASK,
29278 IX86_BUILTIN_LOADAPS256_MASK,
29279 IX86_BUILTIN_LOADAPS128_MASK,
29280 IX86_BUILTIN_STOREAPD256_MASK,
29281 IX86_BUILTIN_STOREAPD128_MASK,
29282 IX86_BUILTIN_STOREAPS256_MASK,
29283 IX86_BUILTIN_STOREAPS128_MASK,
29284 IX86_BUILTIN_LOADUPD256_MASK,
29285 IX86_BUILTIN_LOADUPD128_MASK,
29286 IX86_BUILTIN_LOADUPS256_MASK,
29287 IX86_BUILTIN_LOADUPS128_MASK,
29288 IX86_BUILTIN_STOREUPD256_MASK,
29289 IX86_BUILTIN_STOREUPD128_MASK,
29290 IX86_BUILTIN_STOREUPS256_MASK,
29291 IX86_BUILTIN_STOREUPS128_MASK,
29292 IX86_BUILTIN_LOADDQUDI256_MASK,
29293 IX86_BUILTIN_LOADDQUDI128_MASK,
29294 IX86_BUILTIN_LOADDQUSI256_MASK,
29295 IX86_BUILTIN_LOADDQUSI128_MASK,
29296 IX86_BUILTIN_LOADDQUHI256_MASK,
29297 IX86_BUILTIN_LOADDQUHI128_MASK,
29298 IX86_BUILTIN_LOADDQUQI256_MASK,
29299 IX86_BUILTIN_LOADDQUQI128_MASK,
29300 IX86_BUILTIN_STOREDQUDI256_MASK,
29301 IX86_BUILTIN_STOREDQUDI128_MASK,
29302 IX86_BUILTIN_STOREDQUSI256_MASK,
29303 IX86_BUILTIN_STOREDQUSI128_MASK,
29304 IX86_BUILTIN_STOREDQUHI256_MASK,
29305 IX86_BUILTIN_STOREDQUHI128_MASK,
29306 IX86_BUILTIN_STOREDQUQI256_MASK,
29307 IX86_BUILTIN_STOREDQUQI128_MASK,
29308 IX86_BUILTIN_COMPRESSPDSTORE256,
29309 IX86_BUILTIN_COMPRESSPDSTORE128,
29310 IX86_BUILTIN_COMPRESSPSSTORE256,
29311 IX86_BUILTIN_COMPRESSPSSTORE128,
29312 IX86_BUILTIN_PCOMPRESSQSTORE256,
29313 IX86_BUILTIN_PCOMPRESSQSTORE128,
29314 IX86_BUILTIN_PCOMPRESSDSTORE256,
29315 IX86_BUILTIN_PCOMPRESSDSTORE128,
29316 IX86_BUILTIN_EXPANDPDLOAD256,
29317 IX86_BUILTIN_EXPANDPDLOAD128,
29318 IX86_BUILTIN_EXPANDPSLOAD256,
29319 IX86_BUILTIN_EXPANDPSLOAD128,
29320 IX86_BUILTIN_PEXPANDQLOAD256,
29321 IX86_BUILTIN_PEXPANDQLOAD128,
29322 IX86_BUILTIN_PEXPANDDLOAD256,
29323 IX86_BUILTIN_PEXPANDDLOAD128,
29324 IX86_BUILTIN_EXPANDPDLOAD256Z,
29325 IX86_BUILTIN_EXPANDPDLOAD128Z,
29326 IX86_BUILTIN_EXPANDPSLOAD256Z,
29327 IX86_BUILTIN_EXPANDPSLOAD128Z,
29328 IX86_BUILTIN_PEXPANDQLOAD256Z,
29329 IX86_BUILTIN_PEXPANDQLOAD128Z,
29330 IX86_BUILTIN_PEXPANDDLOAD256Z,
29331 IX86_BUILTIN_PEXPANDDLOAD128Z,
29332 IX86_BUILTIN_PALIGNR256_MASK,
29333 IX86_BUILTIN_PALIGNR128_MASK,
29334 IX86_BUILTIN_MOVDQA64_256_MASK,
29335 IX86_BUILTIN_MOVDQA64_128_MASK,
29336 IX86_BUILTIN_MOVDQA32_256_MASK,
29337 IX86_BUILTIN_MOVDQA32_128_MASK,
29338 IX86_BUILTIN_MOVAPD256_MASK,
29339 IX86_BUILTIN_MOVAPD128_MASK,
29340 IX86_BUILTIN_MOVAPS256_MASK,
29341 IX86_BUILTIN_MOVAPS128_MASK,
29342 IX86_BUILTIN_MOVDQUHI256_MASK,
29343 IX86_BUILTIN_MOVDQUHI128_MASK,
29344 IX86_BUILTIN_MOVDQUQI256_MASK,
29345 IX86_BUILTIN_MOVDQUQI128_MASK,
29346 IX86_BUILTIN_MINPS128_MASK,
29347 IX86_BUILTIN_MAXPS128_MASK,
29348 IX86_BUILTIN_MINPD128_MASK,
29349 IX86_BUILTIN_MAXPD128_MASK,
29350 IX86_BUILTIN_MAXPD256_MASK,
29351 IX86_BUILTIN_MAXPS256_MASK,
29352 IX86_BUILTIN_MINPD256_MASK,
29353 IX86_BUILTIN_MINPS256_MASK,
29354 IX86_BUILTIN_MULPS128_MASK,
29355 IX86_BUILTIN_DIVPS128_MASK,
29356 IX86_BUILTIN_MULPD128_MASK,
29357 IX86_BUILTIN_DIVPD128_MASK,
29358 IX86_BUILTIN_DIVPD256_MASK,
29359 IX86_BUILTIN_DIVPS256_MASK,
29360 IX86_BUILTIN_MULPD256_MASK,
29361 IX86_BUILTIN_MULPS256_MASK,
29362 IX86_BUILTIN_ADDPD128_MASK,
29363 IX86_BUILTIN_ADDPD256_MASK,
29364 IX86_BUILTIN_ADDPS128_MASK,
29365 IX86_BUILTIN_ADDPS256_MASK,
29366 IX86_BUILTIN_SUBPD128_MASK,
29367 IX86_BUILTIN_SUBPD256_MASK,
29368 IX86_BUILTIN_SUBPS128_MASK,
29369 IX86_BUILTIN_SUBPS256_MASK,
29370 IX86_BUILTIN_XORPD256_MASK,
29371 IX86_BUILTIN_XORPD128_MASK,
29372 IX86_BUILTIN_XORPS256_MASK,
29373 IX86_BUILTIN_XORPS128_MASK,
29374 IX86_BUILTIN_ORPD256_MASK,
29375 IX86_BUILTIN_ORPD128_MASK,
29376 IX86_BUILTIN_ORPS256_MASK,
29377 IX86_BUILTIN_ORPS128_MASK,
29378 IX86_BUILTIN_BROADCASTF32x2_256,
29379 IX86_BUILTIN_BROADCASTI32x2_256,
29380 IX86_BUILTIN_BROADCASTI32x2_128,
29381 IX86_BUILTIN_BROADCASTF64X2_256,
29382 IX86_BUILTIN_BROADCASTI64X2_256,
29383 IX86_BUILTIN_BROADCASTF32X4_256,
29384 IX86_BUILTIN_BROADCASTI32X4_256,
29385 IX86_BUILTIN_EXTRACTF32X4_256,
29386 IX86_BUILTIN_EXTRACTI32X4_256,
29387 IX86_BUILTIN_DBPSADBW256,
29388 IX86_BUILTIN_DBPSADBW128,
29389 IX86_BUILTIN_CVTTPD2QQ256,
29390 IX86_BUILTIN_CVTTPD2QQ128,
29391 IX86_BUILTIN_CVTTPD2UQQ256,
29392 IX86_BUILTIN_CVTTPD2UQQ128,
29393 IX86_BUILTIN_CVTPD2QQ256,
29394 IX86_BUILTIN_CVTPD2QQ128,
29395 IX86_BUILTIN_CVTPD2UQQ256,
29396 IX86_BUILTIN_CVTPD2UQQ128,
29397 IX86_BUILTIN_CVTPD2UDQ256_MASK,
29398 IX86_BUILTIN_CVTPD2UDQ128_MASK,
29399 IX86_BUILTIN_CVTTPS2QQ256,
29400 IX86_BUILTIN_CVTTPS2QQ128,
29401 IX86_BUILTIN_CVTTPS2UQQ256,
29402 IX86_BUILTIN_CVTTPS2UQQ128,
29403 IX86_BUILTIN_CVTTPS2DQ256_MASK,
29404 IX86_BUILTIN_CVTTPS2DQ128_MASK,
29405 IX86_BUILTIN_CVTTPS2UDQ256,
29406 IX86_BUILTIN_CVTTPS2UDQ128,
29407 IX86_BUILTIN_CVTTPD2DQ256_MASK,
29408 IX86_BUILTIN_CVTTPD2DQ128_MASK,
29409 IX86_BUILTIN_CVTTPD2UDQ256_MASK,
29410 IX86_BUILTIN_CVTTPD2UDQ128_MASK,
29411 IX86_BUILTIN_CVTPD2DQ256_MASK,
29412 IX86_BUILTIN_CVTPD2DQ128_MASK,
29413 IX86_BUILTIN_CVTDQ2PD256_MASK,
29414 IX86_BUILTIN_CVTDQ2PD128_MASK,
29415 IX86_BUILTIN_CVTUDQ2PD256_MASK,
29416 IX86_BUILTIN_CVTUDQ2PD128_MASK,
29417 IX86_BUILTIN_CVTDQ2PS256_MASK,
29418 IX86_BUILTIN_CVTDQ2PS128_MASK,
29419 IX86_BUILTIN_CVTUDQ2PS256_MASK,
29420 IX86_BUILTIN_CVTUDQ2PS128_MASK,
29421 IX86_BUILTIN_CVTPS2PD256_MASK,
29422 IX86_BUILTIN_CVTPS2PD128_MASK,
29423 IX86_BUILTIN_PBROADCASTB256_MASK,
29424 IX86_BUILTIN_PBROADCASTB256_GPR_MASK,
29425 IX86_BUILTIN_PBROADCASTB128_MASK,
29426 IX86_BUILTIN_PBROADCASTB128_GPR_MASK,
29427 IX86_BUILTIN_PBROADCASTW256_MASK,
29428 IX86_BUILTIN_PBROADCASTW256_GPR_MASK,
29429 IX86_BUILTIN_PBROADCASTW128_MASK,
29430 IX86_BUILTIN_PBROADCASTW128_GPR_MASK,
29431 IX86_BUILTIN_PBROADCASTD256_MASK,
29432 IX86_BUILTIN_PBROADCASTD256_GPR_MASK,
29433 IX86_BUILTIN_PBROADCASTD128_MASK,
29434 IX86_BUILTIN_PBROADCASTD128_GPR_MASK,
29435 IX86_BUILTIN_PBROADCASTQ256_MASK,
29436 IX86_BUILTIN_PBROADCASTQ256_GPR_MASK,
29437 IX86_BUILTIN_PBROADCASTQ128_MASK,
29438 IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
29439 IX86_BUILTIN_BROADCASTSS256,
29440 IX86_BUILTIN_BROADCASTSS128,
29441 IX86_BUILTIN_BROADCASTSD256,
29442 IX86_BUILTIN_EXTRACTF64X2_256,
29443 IX86_BUILTIN_EXTRACTI64X2_256,
29444 IX86_BUILTIN_INSERTF32X4_256,
29445 IX86_BUILTIN_INSERTI32X4_256,
29446 IX86_BUILTIN_PMOVSXBW256_MASK,
29447 IX86_BUILTIN_PMOVSXBW128_MASK,
29448 IX86_BUILTIN_PMOVSXBD256_MASK,
29449 IX86_BUILTIN_PMOVSXBD128_MASK,
29450 IX86_BUILTIN_PMOVSXBQ256_MASK,
29451 IX86_BUILTIN_PMOVSXBQ128_MASK,
29452 IX86_BUILTIN_PMOVSXWD256_MASK,
29453 IX86_BUILTIN_PMOVSXWD128_MASK,
29454 IX86_BUILTIN_PMOVSXWQ256_MASK,
29455 IX86_BUILTIN_PMOVSXWQ128_MASK,
29456 IX86_BUILTIN_PMOVSXDQ256_MASK,
29457 IX86_BUILTIN_PMOVSXDQ128_MASK,
29458 IX86_BUILTIN_PMOVZXBW256_MASK,
29459 IX86_BUILTIN_PMOVZXBW128_MASK,
29460 IX86_BUILTIN_PMOVZXBD256_MASK,
29461 IX86_BUILTIN_PMOVZXBD128_MASK,
29462 IX86_BUILTIN_PMOVZXBQ256_MASK,
29463 IX86_BUILTIN_PMOVZXBQ128_MASK,
29464 IX86_BUILTIN_PMOVZXWD256_MASK,
29465 IX86_BUILTIN_PMOVZXWD128_MASK,
29466 IX86_BUILTIN_PMOVZXWQ256_MASK,
29467 IX86_BUILTIN_PMOVZXWQ128_MASK,
29468 IX86_BUILTIN_PMOVZXDQ256_MASK,
29469 IX86_BUILTIN_PMOVZXDQ128_MASK,
29470 IX86_BUILTIN_REDUCEPD256_MASK,
29471 IX86_BUILTIN_REDUCEPD128_MASK,
29472 IX86_BUILTIN_REDUCEPS256_MASK,
29473 IX86_BUILTIN_REDUCEPS128_MASK,
29474 IX86_BUILTIN_REDUCESD_MASK,
29475 IX86_BUILTIN_REDUCESS_MASK,
29476 IX86_BUILTIN_VPERMVARHI256_MASK,
29477 IX86_BUILTIN_VPERMVARHI128_MASK,
29478 IX86_BUILTIN_VPERMT2VARHI256,
29479 IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
29480 IX86_BUILTIN_VPERMT2VARHI128,
29481 IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
29482 IX86_BUILTIN_VPERMI2VARHI256,
29483 IX86_BUILTIN_VPERMI2VARHI128,
29484 IX86_BUILTIN_RCP14PD256,
29485 IX86_BUILTIN_RCP14PD128,
29486 IX86_BUILTIN_RCP14PS256,
29487 IX86_BUILTIN_RCP14PS128,
29488 IX86_BUILTIN_RSQRT14PD256_MASK,
29489 IX86_BUILTIN_RSQRT14PD128_MASK,
29490 IX86_BUILTIN_RSQRT14PS256_MASK,
29491 IX86_BUILTIN_RSQRT14PS128_MASK,
29492 IX86_BUILTIN_SQRTPD256_MASK,
29493 IX86_BUILTIN_SQRTPD128_MASK,
29494 IX86_BUILTIN_SQRTPS256_MASK,
29495 IX86_BUILTIN_SQRTPS128_MASK,
29496 IX86_BUILTIN_PADDB128_MASK,
29497 IX86_BUILTIN_PADDW128_MASK,
29498 IX86_BUILTIN_PADDD128_MASK,
29499 IX86_BUILTIN_PADDQ128_MASK,
29500 IX86_BUILTIN_PSUBB128_MASK,
29501 IX86_BUILTIN_PSUBW128_MASK,
29502 IX86_BUILTIN_PSUBD128_MASK,
29503 IX86_BUILTIN_PSUBQ128_MASK,
29504 IX86_BUILTIN_PADDSB128_MASK,
29505 IX86_BUILTIN_PADDSW128_MASK,
29506 IX86_BUILTIN_PSUBSB128_MASK,
29507 IX86_BUILTIN_PSUBSW128_MASK,
29508 IX86_BUILTIN_PADDUSB128_MASK,
29509 IX86_BUILTIN_PADDUSW128_MASK,
29510 IX86_BUILTIN_PSUBUSB128_MASK,
29511 IX86_BUILTIN_PSUBUSW128_MASK,
29512 IX86_BUILTIN_PADDB256_MASK,
29513 IX86_BUILTIN_PADDW256_MASK,
29514 IX86_BUILTIN_PADDD256_MASK,
29515 IX86_BUILTIN_PADDQ256_MASK,
29516 IX86_BUILTIN_PADDSB256_MASK,
29517 IX86_BUILTIN_PADDSW256_MASK,
29518 IX86_BUILTIN_PADDUSB256_MASK,
29519 IX86_BUILTIN_PADDUSW256_MASK,
29520 IX86_BUILTIN_PSUBB256_MASK,
29521 IX86_BUILTIN_PSUBW256_MASK,
29522 IX86_BUILTIN_PSUBD256_MASK,
29523 IX86_BUILTIN_PSUBQ256_MASK,
29524 IX86_BUILTIN_PSUBSB256_MASK,
29525 IX86_BUILTIN_PSUBSW256_MASK,
29526 IX86_BUILTIN_PSUBUSB256_MASK,
29527 IX86_BUILTIN_PSUBUSW256_MASK,
29528 IX86_BUILTIN_SHUF_F64x2_256,
29529 IX86_BUILTIN_SHUF_I64x2_256,
29530 IX86_BUILTIN_SHUF_I32x4_256,
29531 IX86_BUILTIN_SHUF_F32x4_256,
29532 IX86_BUILTIN_PMOVWB128,
29533 IX86_BUILTIN_PMOVWB256,
29534 IX86_BUILTIN_PMOVSWB128,
29535 IX86_BUILTIN_PMOVSWB256,
29536 IX86_BUILTIN_PMOVUSWB128,
29537 IX86_BUILTIN_PMOVUSWB256,
29538 IX86_BUILTIN_PMOVDB128,
29539 IX86_BUILTIN_PMOVDB256,
29540 IX86_BUILTIN_PMOVSDB128,
29541 IX86_BUILTIN_PMOVSDB256,
29542 IX86_BUILTIN_PMOVUSDB128,
29543 IX86_BUILTIN_PMOVUSDB256,
29544 IX86_BUILTIN_PMOVDW128,
29545 IX86_BUILTIN_PMOVDW256,
29546 IX86_BUILTIN_PMOVSDW128,
29547 IX86_BUILTIN_PMOVSDW256,
29548 IX86_BUILTIN_PMOVUSDW128,
29549 IX86_BUILTIN_PMOVUSDW256,
29550 IX86_BUILTIN_PMOVQB128,
29551 IX86_BUILTIN_PMOVQB256,
29552 IX86_BUILTIN_PMOVSQB128,
29553 IX86_BUILTIN_PMOVSQB256,
29554 IX86_BUILTIN_PMOVUSQB128,
29555 IX86_BUILTIN_PMOVUSQB256,
29556 IX86_BUILTIN_PMOVQW128,
29557 IX86_BUILTIN_PMOVQW256,
29558 IX86_BUILTIN_PMOVSQW128,
29559 IX86_BUILTIN_PMOVSQW256,
29560 IX86_BUILTIN_PMOVUSQW128,
29561 IX86_BUILTIN_PMOVUSQW256,
29562 IX86_BUILTIN_PMOVQD128,
29563 IX86_BUILTIN_PMOVQD256,
29564 IX86_BUILTIN_PMOVSQD128,
29565 IX86_BUILTIN_PMOVSQD256,
29566 IX86_BUILTIN_PMOVUSQD128,
29567 IX86_BUILTIN_PMOVUSQD256,
29568 IX86_BUILTIN_RANGEPD256,
29569 IX86_BUILTIN_RANGEPD128,
29570 IX86_BUILTIN_RANGEPS256,
29571 IX86_BUILTIN_RANGEPS128,
29572 IX86_BUILTIN_GETEXPPS256,
29573 IX86_BUILTIN_GETEXPPD256,
29574 IX86_BUILTIN_GETEXPPS128,
29575 IX86_BUILTIN_GETEXPPD128,
29576 IX86_BUILTIN_FIXUPIMMPD256_MASK,
29577 IX86_BUILTIN_FIXUPIMMPD256_MASKZ,
29578 IX86_BUILTIN_FIXUPIMMPS256_MASK,
29579 IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
29580 IX86_BUILTIN_FIXUPIMMPD128_MASK,
29581 IX86_BUILTIN_FIXUPIMMPD128_MASKZ,
29582 IX86_BUILTIN_FIXUPIMMPS128_MASK,
29583 IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
29584 IX86_BUILTIN_PABSQ256,
29585 IX86_BUILTIN_PABSQ128,
29586 IX86_BUILTIN_PABSD256_MASK,
29587 IX86_BUILTIN_PABSD128_MASK,
29588 IX86_BUILTIN_PMULHRSW256_MASK,
29589 IX86_BUILTIN_PMULHRSW128_MASK,
29590 IX86_BUILTIN_PMULHUW128_MASK,
29591 IX86_BUILTIN_PMULHUW256_MASK,
29592 IX86_BUILTIN_PMULHW256_MASK,
29593 IX86_BUILTIN_PMULHW128_MASK,
29594 IX86_BUILTIN_PMULLW256_MASK,
29595 IX86_BUILTIN_PMULLW128_MASK,
29596 IX86_BUILTIN_PMULLQ256,
29597 IX86_BUILTIN_PMULLQ128,
29598 IX86_BUILTIN_ANDPD256_MASK,
29599 IX86_BUILTIN_ANDPD128_MASK,
29600 IX86_BUILTIN_ANDPS256_MASK,
29601 IX86_BUILTIN_ANDPS128_MASK,
29602 IX86_BUILTIN_ANDNPD256_MASK,
29603 IX86_BUILTIN_ANDNPD128_MASK,
29604 IX86_BUILTIN_ANDNPS256_MASK,
29605 IX86_BUILTIN_ANDNPS128_MASK,
29606 IX86_BUILTIN_PSLLWI128_MASK,
29607 IX86_BUILTIN_PSLLDI128_MASK,
29608 IX86_BUILTIN_PSLLQI128_MASK,
29609 IX86_BUILTIN_PSLLW128_MASK,
29610 IX86_BUILTIN_PSLLD128_MASK,
29611 IX86_BUILTIN_PSLLQ128_MASK,
29612 IX86_BUILTIN_PSLLWI256_MASK ,
29613 IX86_BUILTIN_PSLLW256_MASK,
29614 IX86_BUILTIN_PSLLDI256_MASK,
29615 IX86_BUILTIN_PSLLD256_MASK,
29616 IX86_BUILTIN_PSLLQI256_MASK,
29617 IX86_BUILTIN_PSLLQ256_MASK,
29618 IX86_BUILTIN_PSRADI128_MASK,
29619 IX86_BUILTIN_PSRAD128_MASK,
29620 IX86_BUILTIN_PSRADI256_MASK,
29621 IX86_BUILTIN_PSRAD256_MASK,
29622 IX86_BUILTIN_PSRAQI128_MASK,
29623 IX86_BUILTIN_PSRAQ128_MASK,
29624 IX86_BUILTIN_PSRAQI256_MASK,
29625 IX86_BUILTIN_PSRAQ256_MASK,
29626 IX86_BUILTIN_PANDD256,
29627 IX86_BUILTIN_PANDD128,
29628 IX86_BUILTIN_PSRLDI128_MASK,
29629 IX86_BUILTIN_PSRLD128_MASK,
29630 IX86_BUILTIN_PSRLDI256_MASK,
29631 IX86_BUILTIN_PSRLD256_MASK,
29632 IX86_BUILTIN_PSRLQI128_MASK,
29633 IX86_BUILTIN_PSRLQ128_MASK,
29634 IX86_BUILTIN_PSRLQI256_MASK,
29635 IX86_BUILTIN_PSRLQ256_MASK,
29636 IX86_BUILTIN_PANDQ256,
29637 IX86_BUILTIN_PANDQ128,
29638 IX86_BUILTIN_PANDND256,
29639 IX86_BUILTIN_PANDND128,
29640 IX86_BUILTIN_PANDNQ256,
29641 IX86_BUILTIN_PANDNQ128,
29642 IX86_BUILTIN_PORD256,
29643 IX86_BUILTIN_PORD128,
29644 IX86_BUILTIN_PORQ256,
29645 IX86_BUILTIN_PORQ128,
29646 IX86_BUILTIN_PXORD256,
29647 IX86_BUILTIN_PXORD128,
29648 IX86_BUILTIN_PXORQ256,
29649 IX86_BUILTIN_PXORQ128,
29650 IX86_BUILTIN_PACKSSWB256_MASK,
29651 IX86_BUILTIN_PACKSSWB128_MASK,
29652 IX86_BUILTIN_PACKUSWB256_MASK,
29653 IX86_BUILTIN_PACKUSWB128_MASK,
29654 IX86_BUILTIN_RNDSCALEPS256,
29655 IX86_BUILTIN_RNDSCALEPD256,
29656 IX86_BUILTIN_RNDSCALEPS128,
29657 IX86_BUILTIN_RNDSCALEPD128,
29658 IX86_BUILTIN_VTERNLOGQ256_MASK,
29659 IX86_BUILTIN_VTERNLOGQ256_MASKZ,
29660 IX86_BUILTIN_VTERNLOGD256_MASK,
29661 IX86_BUILTIN_VTERNLOGD256_MASKZ,
29662 IX86_BUILTIN_VTERNLOGQ128_MASK,
29663 IX86_BUILTIN_VTERNLOGQ128_MASKZ,
29664 IX86_BUILTIN_VTERNLOGD128_MASK,
29665 IX86_BUILTIN_VTERNLOGD128_MASKZ,
29666 IX86_BUILTIN_SCALEFPD256,
29667 IX86_BUILTIN_SCALEFPS256,
29668 IX86_BUILTIN_SCALEFPD128,
29669 IX86_BUILTIN_SCALEFPS128,
29670 IX86_BUILTIN_VFMADDPD256_MASK,
29671 IX86_BUILTIN_VFMADDPD256_MASK3,
29672 IX86_BUILTIN_VFMADDPD256_MASKZ,
29673 IX86_BUILTIN_VFMADDPD128_MASK,
29674 IX86_BUILTIN_VFMADDPD128_MASK3,
29675 IX86_BUILTIN_VFMADDPD128_MASKZ,
29676 IX86_BUILTIN_VFMADDPS256_MASK,
29677 IX86_BUILTIN_VFMADDPS256_MASK3,
29678 IX86_BUILTIN_VFMADDPS256_MASKZ,
29679 IX86_BUILTIN_VFMADDPS128_MASK,
29680 IX86_BUILTIN_VFMADDPS128_MASK3,
29681 IX86_BUILTIN_VFMADDPS128_MASKZ,
29682 IX86_BUILTIN_VFMSUBPD256_MASK3,
29683 IX86_BUILTIN_VFMSUBPD128_MASK3,
29684 IX86_BUILTIN_VFMSUBPS256_MASK3,
29685 IX86_BUILTIN_VFMSUBPS128_MASK3,
29686 IX86_BUILTIN_VFNMADDPD256_MASK,
29687 IX86_BUILTIN_VFNMADDPD128_MASK,
29688 IX86_BUILTIN_VFNMADDPS256_MASK,
29689 IX86_BUILTIN_VFNMADDPS128_MASK,
29690 IX86_BUILTIN_VFNMSUBPD256_MASK,
29691 IX86_BUILTIN_VFNMSUBPD256_MASK3,
29692 IX86_BUILTIN_VFNMSUBPD128_MASK,
29693 IX86_BUILTIN_VFNMSUBPD128_MASK3,
29694 IX86_BUILTIN_VFNMSUBPS256_MASK,
29695 IX86_BUILTIN_VFNMSUBPS256_MASK3,
29696 IX86_BUILTIN_VFNMSUBPS128_MASK,
29697 IX86_BUILTIN_VFNMSUBPS128_MASK3,
29698 IX86_BUILTIN_VFMADDSUBPD256_MASK,
29699 IX86_BUILTIN_VFMADDSUBPD256_MASK3,
29700 IX86_BUILTIN_VFMADDSUBPD256_MASKZ,
29701 IX86_BUILTIN_VFMADDSUBPD128_MASK,
29702 IX86_BUILTIN_VFMADDSUBPD128_MASK3,
29703 IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
29704 IX86_BUILTIN_VFMADDSUBPS256_MASK,
29705 IX86_BUILTIN_VFMADDSUBPS256_MASK3,
29706 IX86_BUILTIN_VFMADDSUBPS256_MASKZ,
29707 IX86_BUILTIN_VFMADDSUBPS128_MASK,
29708 IX86_BUILTIN_VFMADDSUBPS128_MASK3,
29709 IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
29710 IX86_BUILTIN_VFMSUBADDPD256_MASK3,
29711 IX86_BUILTIN_VFMSUBADDPD128_MASK3,
29712 IX86_BUILTIN_VFMSUBADDPS256_MASK3,
29713 IX86_BUILTIN_VFMSUBADDPS128_MASK3,
29714 IX86_BUILTIN_INSERTF64X2_256,
29715 IX86_BUILTIN_INSERTI64X2_256,
29716 IX86_BUILTIN_PSRAVV16HI,
29717 IX86_BUILTIN_PSRAVV8HI,
29718 IX86_BUILTIN_PMADDUBSW256_MASK,
29719 IX86_BUILTIN_PMADDUBSW128_MASK,
29720 IX86_BUILTIN_PMADDWD256_MASK,
29721 IX86_BUILTIN_PMADDWD128_MASK,
29722 IX86_BUILTIN_PSRLVV16HI,
29723 IX86_BUILTIN_PSRLVV8HI,
29724 IX86_BUILTIN_CVTPS2DQ256_MASK,
29725 IX86_BUILTIN_CVTPS2DQ128_MASK,
29726 IX86_BUILTIN_CVTPS2UDQ256,
29727 IX86_BUILTIN_CVTPS2UDQ128,
29728 IX86_BUILTIN_CVTPS2QQ256,
29729 IX86_BUILTIN_CVTPS2QQ128,
29730 IX86_BUILTIN_CVTPS2UQQ256,
29731 IX86_BUILTIN_CVTPS2UQQ128,
29732 IX86_BUILTIN_GETMANTPS256,
29733 IX86_BUILTIN_GETMANTPS128,
29734 IX86_BUILTIN_GETMANTPD256,
29735 IX86_BUILTIN_GETMANTPD128,
29736 IX86_BUILTIN_MOVDDUP256_MASK,
29737 IX86_BUILTIN_MOVDDUP128_MASK,
29738 IX86_BUILTIN_MOVSHDUP256_MASK,
29739 IX86_BUILTIN_MOVSHDUP128_MASK,
29740 IX86_BUILTIN_MOVSLDUP256_MASK,
29741 IX86_BUILTIN_MOVSLDUP128_MASK,
29742 IX86_BUILTIN_CVTQQ2PS256,
29743 IX86_BUILTIN_CVTQQ2PS128,
29744 IX86_BUILTIN_CVTUQQ2PS256,
29745 IX86_BUILTIN_CVTUQQ2PS128,
29746 IX86_BUILTIN_CVTQQ2PD256,
29747 IX86_BUILTIN_CVTQQ2PD128,
29748 IX86_BUILTIN_CVTUQQ2PD256,
29749 IX86_BUILTIN_CVTUQQ2PD128,
29750 IX86_BUILTIN_VPERMT2VARQ256,
29751 IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
29752 IX86_BUILTIN_VPERMT2VARD256,
29753 IX86_BUILTIN_VPERMT2VARD256_MASKZ,
29754 IX86_BUILTIN_VPERMI2VARQ256,
29755 IX86_BUILTIN_VPERMI2VARD256,
29756 IX86_BUILTIN_VPERMT2VARPD256,
29757 IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
29758 IX86_BUILTIN_VPERMT2VARPS256,
29759 IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
29760 IX86_BUILTIN_VPERMI2VARPD256,
29761 IX86_BUILTIN_VPERMI2VARPS256,
29762 IX86_BUILTIN_VPERMT2VARQ128,
29763 IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
29764 IX86_BUILTIN_VPERMT2VARD128,
29765 IX86_BUILTIN_VPERMT2VARD128_MASKZ,
29766 IX86_BUILTIN_VPERMI2VARQ128,
29767 IX86_BUILTIN_VPERMI2VARD128,
29768 IX86_BUILTIN_VPERMT2VARPD128,
29769 IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
29770 IX86_BUILTIN_VPERMT2VARPS128,
29771 IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
29772 IX86_BUILTIN_VPERMI2VARPD128,
29773 IX86_BUILTIN_VPERMI2VARPS128,
29774 IX86_BUILTIN_PSHUFB256_MASK,
29775 IX86_BUILTIN_PSHUFB128_MASK,
29776 IX86_BUILTIN_PSHUFHW256_MASK,
29777 IX86_BUILTIN_PSHUFHW128_MASK,
29778 IX86_BUILTIN_PSHUFLW256_MASK,
29779 IX86_BUILTIN_PSHUFLW128_MASK,
29780 IX86_BUILTIN_PSHUFD256_MASK,
29781 IX86_BUILTIN_PSHUFD128_MASK,
29782 IX86_BUILTIN_SHUFPD256_MASK,
29783 IX86_BUILTIN_SHUFPD128_MASK,
29784 IX86_BUILTIN_SHUFPS256_MASK,
29785 IX86_BUILTIN_SHUFPS128_MASK,
29786 IX86_BUILTIN_PROLVQ256,
29787 IX86_BUILTIN_PROLVQ128,
29788 IX86_BUILTIN_PROLQ256,
29789 IX86_BUILTIN_PROLQ128,
29790 IX86_BUILTIN_PRORVQ256,
29791 IX86_BUILTIN_PRORVQ128,
29792 IX86_BUILTIN_PRORQ256,
29793 IX86_BUILTIN_PRORQ128,
29794 IX86_BUILTIN_PSRAVQ128,
29795 IX86_BUILTIN_PSRAVQ256,
29796 IX86_BUILTIN_PSLLVV4DI_MASK,
29797 IX86_BUILTIN_PSLLVV2DI_MASK,
29798 IX86_BUILTIN_PSLLVV8SI_MASK,
29799 IX86_BUILTIN_PSLLVV4SI_MASK,
29800 IX86_BUILTIN_PSRAVV8SI_MASK,
29801 IX86_BUILTIN_PSRAVV4SI_MASK,
29802 IX86_BUILTIN_PSRLVV4DI_MASK,
29803 IX86_BUILTIN_PSRLVV2DI_MASK,
29804 IX86_BUILTIN_PSRLVV8SI_MASK,
29805 IX86_BUILTIN_PSRLVV4SI_MASK,
29806 IX86_BUILTIN_PSRAWI256_MASK,
29807 IX86_BUILTIN_PSRAW256_MASK,
29808 IX86_BUILTIN_PSRAWI128_MASK,
29809 IX86_BUILTIN_PSRAW128_MASK,
29810 IX86_BUILTIN_PSRLWI256_MASK,
29811 IX86_BUILTIN_PSRLW256_MASK,
29812 IX86_BUILTIN_PSRLWI128_MASK,
29813 IX86_BUILTIN_PSRLW128_MASK,
29814 IX86_BUILTIN_PRORVD256,
29815 IX86_BUILTIN_PROLVD256,
29816 IX86_BUILTIN_PRORD256,
29817 IX86_BUILTIN_PROLD256,
29818 IX86_BUILTIN_PRORVD128,
29819 IX86_BUILTIN_PROLVD128,
29820 IX86_BUILTIN_PRORD128,
29821 IX86_BUILTIN_PROLD128,
29822 IX86_BUILTIN_FPCLASSPD256,
29823 IX86_BUILTIN_FPCLASSPD128,
29824 IX86_BUILTIN_FPCLASSSD,
29825 IX86_BUILTIN_FPCLASSPS256,
29826 IX86_BUILTIN_FPCLASSPS128,
29827 IX86_BUILTIN_FPCLASSSS,
29828 IX86_BUILTIN_CVTB2MASK128,
29829 IX86_BUILTIN_CVTB2MASK256,
29830 IX86_BUILTIN_CVTW2MASK128,
29831 IX86_BUILTIN_CVTW2MASK256,
29832 IX86_BUILTIN_CVTD2MASK128,
29833 IX86_BUILTIN_CVTD2MASK256,
29834 IX86_BUILTIN_CVTQ2MASK128,
29835 IX86_BUILTIN_CVTQ2MASK256,
29836 IX86_BUILTIN_CVTMASK2B128,
29837 IX86_BUILTIN_CVTMASK2B256,
29838 IX86_BUILTIN_CVTMASK2W128,
29839 IX86_BUILTIN_CVTMASK2W256,
29840 IX86_BUILTIN_CVTMASK2D128,
29841 IX86_BUILTIN_CVTMASK2D256,
29842 IX86_BUILTIN_CVTMASK2Q128,
29843 IX86_BUILTIN_CVTMASK2Q256,
29844 IX86_BUILTIN_PCMPEQB128_MASK,
29845 IX86_BUILTIN_PCMPEQB256_MASK,
29846 IX86_BUILTIN_PCMPEQW128_MASK,
29847 IX86_BUILTIN_PCMPEQW256_MASK,
29848 IX86_BUILTIN_PCMPEQD128_MASK,
29849 IX86_BUILTIN_PCMPEQD256_MASK,
29850 IX86_BUILTIN_PCMPEQQ128_MASK,
29851 IX86_BUILTIN_PCMPEQQ256_MASK,
29852 IX86_BUILTIN_PCMPGTB128_MASK,
29853 IX86_BUILTIN_PCMPGTB256_MASK,
29854 IX86_BUILTIN_PCMPGTW128_MASK,
29855 IX86_BUILTIN_PCMPGTW256_MASK,
29856 IX86_BUILTIN_PCMPGTD128_MASK,
29857 IX86_BUILTIN_PCMPGTD256_MASK,
29858 IX86_BUILTIN_PCMPGTQ128_MASK,
29859 IX86_BUILTIN_PCMPGTQ256_MASK,
29860 IX86_BUILTIN_PTESTMB128,
29861 IX86_BUILTIN_PTESTMB256,
29862 IX86_BUILTIN_PTESTMW128,
29863 IX86_BUILTIN_PTESTMW256,
29864 IX86_BUILTIN_PTESTMD128,
29865 IX86_BUILTIN_PTESTMD256,
29866 IX86_BUILTIN_PTESTMQ128,
29867 IX86_BUILTIN_PTESTMQ256,
29868 IX86_BUILTIN_PTESTNMB128,
29869 IX86_BUILTIN_PTESTNMB256,
29870 IX86_BUILTIN_PTESTNMW128,
29871 IX86_BUILTIN_PTESTNMW256,
29872 IX86_BUILTIN_PTESTNMD128,
29873 IX86_BUILTIN_PTESTNMD256,
29874 IX86_BUILTIN_PTESTNMQ128,
29875 IX86_BUILTIN_PTESTNMQ256,
29876 IX86_BUILTIN_PBROADCASTMB128,
29877 IX86_BUILTIN_PBROADCASTMB256,
29878 IX86_BUILTIN_PBROADCASTMW128,
29879 IX86_BUILTIN_PBROADCASTMW256,
29880 IX86_BUILTIN_COMPRESSPD256,
29881 IX86_BUILTIN_COMPRESSPD128,
29882 IX86_BUILTIN_COMPRESSPS256,
29883 IX86_BUILTIN_COMPRESSPS128,
29884 IX86_BUILTIN_PCOMPRESSQ256,
29885 IX86_BUILTIN_PCOMPRESSQ128,
29886 IX86_BUILTIN_PCOMPRESSD256,
29887 IX86_BUILTIN_PCOMPRESSD128,
29888 IX86_BUILTIN_EXPANDPD256,
29889 IX86_BUILTIN_EXPANDPD128,
29890 IX86_BUILTIN_EXPANDPS256,
29891 IX86_BUILTIN_EXPANDPS128,
29892 IX86_BUILTIN_PEXPANDQ256,
29893 IX86_BUILTIN_PEXPANDQ128,
29894 IX86_BUILTIN_PEXPANDD256,
29895 IX86_BUILTIN_PEXPANDD128,
29896 IX86_BUILTIN_EXPANDPD256Z,
29897 IX86_BUILTIN_EXPANDPD128Z,
29898 IX86_BUILTIN_EXPANDPS256Z,
29899 IX86_BUILTIN_EXPANDPS128Z,
29900 IX86_BUILTIN_PEXPANDQ256Z,
29901 IX86_BUILTIN_PEXPANDQ128Z,
29902 IX86_BUILTIN_PEXPANDD256Z,
29903 IX86_BUILTIN_PEXPANDD128Z,
29904 IX86_BUILTIN_PMAXSD256_MASK,
29905 IX86_BUILTIN_PMINSD256_MASK,
29906 IX86_BUILTIN_PMAXUD256_MASK,
29907 IX86_BUILTIN_PMINUD256_MASK,
29908 IX86_BUILTIN_PMAXSD128_MASK,
29909 IX86_BUILTIN_PMINSD128_MASK,
29910 IX86_BUILTIN_PMAXUD128_MASK,
29911 IX86_BUILTIN_PMINUD128_MASK,
29912 IX86_BUILTIN_PMAXSQ256_MASK,
29913 IX86_BUILTIN_PMINSQ256_MASK,
29914 IX86_BUILTIN_PMAXUQ256_MASK,
29915 IX86_BUILTIN_PMINUQ256_MASK,
29916 IX86_BUILTIN_PMAXSQ128_MASK,
29917 IX86_BUILTIN_PMINSQ128_MASK,
29918 IX86_BUILTIN_PMAXUQ128_MASK,
29919 IX86_BUILTIN_PMINUQ128_MASK,
29920 IX86_BUILTIN_PMINSB256_MASK,
29921 IX86_BUILTIN_PMINUB256_MASK,
29922 IX86_BUILTIN_PMAXSB256_MASK,
29923 IX86_BUILTIN_PMAXUB256_MASK,
29924 IX86_BUILTIN_PMINSB128_MASK,
29925 IX86_BUILTIN_PMINUB128_MASK,
29926 IX86_BUILTIN_PMAXSB128_MASK,
29927 IX86_BUILTIN_PMAXUB128_MASK,
29928 IX86_BUILTIN_PMINSW256_MASK,
29929 IX86_BUILTIN_PMINUW256_MASK,
29930 IX86_BUILTIN_PMAXSW256_MASK,
29931 IX86_BUILTIN_PMAXUW256_MASK,
29932 IX86_BUILTIN_PMINSW128_MASK,
29933 IX86_BUILTIN_PMINUW128_MASK,
29934 IX86_BUILTIN_PMAXSW128_MASK,
29935 IX86_BUILTIN_PMAXUW128_MASK,
29936 IX86_BUILTIN_VPCONFLICTQ256,
29937 IX86_BUILTIN_VPCONFLICTD256,
29938 IX86_BUILTIN_VPCLZCNTQ256,
29939 IX86_BUILTIN_VPCLZCNTD256,
29940 IX86_BUILTIN_UNPCKHPD256_MASK,
29941 IX86_BUILTIN_UNPCKHPD128_MASK,
29942 IX86_BUILTIN_UNPCKHPS256_MASK,
29943 IX86_BUILTIN_UNPCKHPS128_MASK,
29944 IX86_BUILTIN_UNPCKLPD256_MASK,
29945 IX86_BUILTIN_UNPCKLPD128_MASK,
29946 IX86_BUILTIN_UNPCKLPS256_MASK,
29947 IX86_BUILTIN_VPCONFLICTQ128,
29948 IX86_BUILTIN_VPCONFLICTD128,
29949 IX86_BUILTIN_VPCLZCNTQ128,
29950 IX86_BUILTIN_VPCLZCNTD128,
29951 IX86_BUILTIN_UNPCKLPS128_MASK,
29952 IX86_BUILTIN_ALIGND256,
29953 IX86_BUILTIN_ALIGNQ256,
29954 IX86_BUILTIN_ALIGND128,
29955 IX86_BUILTIN_ALIGNQ128,
29956 IX86_BUILTIN_CVTPS2PH256_MASK,
29957 IX86_BUILTIN_CVTPS2PH_MASK,
29958 IX86_BUILTIN_CVTPH2PS_MASK,
29959 IX86_BUILTIN_CVTPH2PS256_MASK,
29960 IX86_BUILTIN_PUNPCKHDQ128_MASK,
29961 IX86_BUILTIN_PUNPCKHDQ256_MASK,
29962 IX86_BUILTIN_PUNPCKHQDQ128_MASK,
29963 IX86_BUILTIN_PUNPCKHQDQ256_MASK,
29964 IX86_BUILTIN_PUNPCKLDQ128_MASK,
29965 IX86_BUILTIN_PUNPCKLDQ256_MASK,
29966 IX86_BUILTIN_PUNPCKLQDQ128_MASK,
29967 IX86_BUILTIN_PUNPCKLQDQ256_MASK,
29968 IX86_BUILTIN_PUNPCKHBW128_MASK,
29969 IX86_BUILTIN_PUNPCKHBW256_MASK,
29970 IX86_BUILTIN_PUNPCKHWD128_MASK,
29971 IX86_BUILTIN_PUNPCKHWD256_MASK,
29972 IX86_BUILTIN_PUNPCKLBW128_MASK,
29973 IX86_BUILTIN_PUNPCKLBW256_MASK,
29974 IX86_BUILTIN_PUNPCKLWD128_MASK,
29975 IX86_BUILTIN_PUNPCKLWD256_MASK,
29976 IX86_BUILTIN_PSLLVV16HI,
29977 IX86_BUILTIN_PSLLVV8HI,
29978 IX86_BUILTIN_PACKSSDW256_MASK,
29979 IX86_BUILTIN_PACKSSDW128_MASK,
29980 IX86_BUILTIN_PACKUSDW256_MASK,
29981 IX86_BUILTIN_PACKUSDW128_MASK,
29982 IX86_BUILTIN_PAVGB256_MASK,
29983 IX86_BUILTIN_PAVGW256_MASK,
29984 IX86_BUILTIN_PAVGB128_MASK,
29985 IX86_BUILTIN_PAVGW128_MASK,
29986 IX86_BUILTIN_VPERMVARSF256_MASK,
29987 IX86_BUILTIN_VPERMVARDF256_MASK,
29988 IX86_BUILTIN_VPERMDF256_MASK,
29989 IX86_BUILTIN_PABSB256_MASK,
29990 IX86_BUILTIN_PABSB128_MASK,
29991 IX86_BUILTIN_PABSW256_MASK,
29992 IX86_BUILTIN_PABSW128_MASK,
29993 IX86_BUILTIN_VPERMILVARPD_MASK,
29994 IX86_BUILTIN_VPERMILVARPS_MASK,
29995 IX86_BUILTIN_VPERMILVARPD256_MASK,
29996 IX86_BUILTIN_VPERMILVARPS256_MASK,
29997 IX86_BUILTIN_VPERMILPD_MASK,
29998 IX86_BUILTIN_VPERMILPS_MASK,
29999 IX86_BUILTIN_VPERMILPD256_MASK,
30000 IX86_BUILTIN_VPERMILPS256_MASK,
30001 IX86_BUILTIN_BLENDMQ256,
30002 IX86_BUILTIN_BLENDMD256,
30003 IX86_BUILTIN_BLENDMPD256,
30004 IX86_BUILTIN_BLENDMPS256,
30005 IX86_BUILTIN_BLENDMQ128,
30006 IX86_BUILTIN_BLENDMD128,
30007 IX86_BUILTIN_BLENDMPD128,
30008 IX86_BUILTIN_BLENDMPS128,
30009 IX86_BUILTIN_BLENDMW256,
30010 IX86_BUILTIN_BLENDMB256,
30011 IX86_BUILTIN_BLENDMW128,
30012 IX86_BUILTIN_BLENDMB128,
30013 IX86_BUILTIN_PMULLD256_MASK,
30014 IX86_BUILTIN_PMULLD128_MASK,
30015 IX86_BUILTIN_PMULUDQ256_MASK,
30016 IX86_BUILTIN_PMULDQ256_MASK,
30017 IX86_BUILTIN_PMULDQ128_MASK,
30018 IX86_BUILTIN_PMULUDQ128_MASK,
30019 IX86_BUILTIN_CVTPD2PS256_MASK,
30020 IX86_BUILTIN_CVTPD2PS_MASK,
30021 IX86_BUILTIN_VPERMVARSI256_MASK,
30022 IX86_BUILTIN_VPERMVARDI256_MASK,
30023 IX86_BUILTIN_VPERMDI256_MASK,
30024 IX86_BUILTIN_CMPQ256,
30025 IX86_BUILTIN_CMPD256,
30026 IX86_BUILTIN_UCMPQ256,
30027 IX86_BUILTIN_UCMPD256,
30028 IX86_BUILTIN_CMPB256,
30029 IX86_BUILTIN_CMPW256,
30030 IX86_BUILTIN_UCMPB256,
30031 IX86_BUILTIN_UCMPW256,
30032 IX86_BUILTIN_CMPPD256_MASK,
30033 IX86_BUILTIN_CMPPS256_MASK,
30034 IX86_BUILTIN_CMPQ128,
30035 IX86_BUILTIN_CMPD128,
30036 IX86_BUILTIN_UCMPQ128,
30037 IX86_BUILTIN_UCMPD128,
30038 IX86_BUILTIN_CMPB128,
30039 IX86_BUILTIN_CMPW128,
30040 IX86_BUILTIN_UCMPB128,
30041 IX86_BUILTIN_UCMPW128,
30042 IX86_BUILTIN_CMPPD128_MASK,
30043 IX86_BUILTIN_CMPPS128_MASK,
30045 IX86_BUILTIN_GATHER3SIV8SF,
30046 IX86_BUILTIN_GATHER3SIV4SF,
30047 IX86_BUILTIN_GATHER3SIV4DF,
30048 IX86_BUILTIN_GATHER3SIV2DF,
30049 IX86_BUILTIN_GATHER3DIV8SF,
30050 IX86_BUILTIN_GATHER3DIV4SF,
30051 IX86_BUILTIN_GATHER3DIV4DF,
30052 IX86_BUILTIN_GATHER3DIV2DF,
30053 IX86_BUILTIN_GATHER3SIV8SI,
30054 IX86_BUILTIN_GATHER3SIV4SI,
30055 IX86_BUILTIN_GATHER3SIV4DI,
30056 IX86_BUILTIN_GATHER3SIV2DI,
30057 IX86_BUILTIN_GATHER3DIV8SI,
30058 IX86_BUILTIN_GATHER3DIV4SI,
30059 IX86_BUILTIN_GATHER3DIV4DI,
30060 IX86_BUILTIN_GATHER3DIV2DI,
30061 IX86_BUILTIN_SCATTERSIV8SF,
30062 IX86_BUILTIN_SCATTERSIV4SF,
30063 IX86_BUILTIN_SCATTERSIV4DF,
30064 IX86_BUILTIN_SCATTERSIV2DF,
30065 IX86_BUILTIN_SCATTERDIV8SF,
30066 IX86_BUILTIN_SCATTERDIV4SF,
30067 IX86_BUILTIN_SCATTERDIV4DF,
30068 IX86_BUILTIN_SCATTERDIV2DF,
30069 IX86_BUILTIN_SCATTERSIV8SI,
30070 IX86_BUILTIN_SCATTERSIV4SI,
30071 IX86_BUILTIN_SCATTERSIV4DI,
30072 IX86_BUILTIN_SCATTERSIV2DI,
30073 IX86_BUILTIN_SCATTERDIV8SI,
30074 IX86_BUILTIN_SCATTERDIV4SI,
30075 IX86_BUILTIN_SCATTERDIV4DI,
30076 IX86_BUILTIN_SCATTERDIV2DI,
30078 /* AVX512DQ. */
30079 IX86_BUILTIN_RANGESD128,
30080 IX86_BUILTIN_RANGESS128,
30081 IX86_BUILTIN_KUNPCKWD,
30082 IX86_BUILTIN_KUNPCKDQ,
30083 IX86_BUILTIN_BROADCASTF32x2_512,
30084 IX86_BUILTIN_BROADCASTI32x2_512,
30085 IX86_BUILTIN_BROADCASTF64X2_512,
30086 IX86_BUILTIN_BROADCASTI64X2_512,
30087 IX86_BUILTIN_BROADCASTF32X8_512,
30088 IX86_BUILTIN_BROADCASTI32X8_512,
30089 IX86_BUILTIN_EXTRACTF64X2_512,
30090 IX86_BUILTIN_EXTRACTF32X8,
30091 IX86_BUILTIN_EXTRACTI64X2_512,
30092 IX86_BUILTIN_EXTRACTI32X8,
30093 IX86_BUILTIN_REDUCEPD512_MASK,
30094 IX86_BUILTIN_REDUCEPS512_MASK,
30095 IX86_BUILTIN_PMULLQ512,
30096 IX86_BUILTIN_XORPD512,
30097 IX86_BUILTIN_XORPS512,
30098 IX86_BUILTIN_ORPD512,
30099 IX86_BUILTIN_ORPS512,
30100 IX86_BUILTIN_ANDPD512,
30101 IX86_BUILTIN_ANDPS512,
30102 IX86_BUILTIN_ANDNPD512,
30103 IX86_BUILTIN_ANDNPS512,
30104 IX86_BUILTIN_INSERTF32X8,
30105 IX86_BUILTIN_INSERTI32X8,
30106 IX86_BUILTIN_INSERTF64X2_512,
30107 IX86_BUILTIN_INSERTI64X2_512,
30108 IX86_BUILTIN_FPCLASSPD512,
30109 IX86_BUILTIN_FPCLASSPS512,
30110 IX86_BUILTIN_CVTD2MASK512,
30111 IX86_BUILTIN_CVTQ2MASK512,
30112 IX86_BUILTIN_CVTMASK2D512,
30113 IX86_BUILTIN_CVTMASK2Q512,
30114 IX86_BUILTIN_CVTPD2QQ512,
30115 IX86_BUILTIN_CVTPS2QQ512,
30116 IX86_BUILTIN_CVTPD2UQQ512,
30117 IX86_BUILTIN_CVTPS2UQQ512,
30118 IX86_BUILTIN_CVTQQ2PS512,
30119 IX86_BUILTIN_CVTUQQ2PS512,
30120 IX86_BUILTIN_CVTQQ2PD512,
30121 IX86_BUILTIN_CVTUQQ2PD512,
30122 IX86_BUILTIN_CVTTPS2QQ512,
30123 IX86_BUILTIN_CVTTPS2UQQ512,
30124 IX86_BUILTIN_CVTTPD2QQ512,
30125 IX86_BUILTIN_CVTTPD2UQQ512,
30126 IX86_BUILTIN_RANGEPS512,
30127 IX86_BUILTIN_RANGEPD512,
30129 /* AVX512BW. */
30130 IX86_BUILTIN_PACKUSDW512,
30131 IX86_BUILTIN_PACKSSDW512,
30132 IX86_BUILTIN_LOADDQUHI512_MASK,
30133 IX86_BUILTIN_LOADDQUQI512_MASK,
30134 IX86_BUILTIN_PSLLDQ512,
30135 IX86_BUILTIN_PSRLDQ512,
30136 IX86_BUILTIN_STOREDQUHI512_MASK,
30137 IX86_BUILTIN_STOREDQUQI512_MASK,
30138 IX86_BUILTIN_PALIGNR512,
30139 IX86_BUILTIN_PALIGNR512_MASK,
30140 IX86_BUILTIN_MOVDQUHI512_MASK,
30141 IX86_BUILTIN_MOVDQUQI512_MASK,
30142 IX86_BUILTIN_PSADBW512,
30143 IX86_BUILTIN_DBPSADBW512,
30144 IX86_BUILTIN_PBROADCASTB512,
30145 IX86_BUILTIN_PBROADCASTB512_GPR,
30146 IX86_BUILTIN_PBROADCASTW512,
30147 IX86_BUILTIN_PBROADCASTW512_GPR,
30148 IX86_BUILTIN_PMOVSXBW512_MASK,
30149 IX86_BUILTIN_PMOVZXBW512_MASK,
30150 IX86_BUILTIN_VPERMVARHI512_MASK,
30151 IX86_BUILTIN_VPERMT2VARHI512,
30152 IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
30153 IX86_BUILTIN_VPERMI2VARHI512,
30154 IX86_BUILTIN_PAVGB512,
30155 IX86_BUILTIN_PAVGW512,
30156 IX86_BUILTIN_PADDB512,
30157 IX86_BUILTIN_PSUBB512,
30158 IX86_BUILTIN_PSUBSB512,
30159 IX86_BUILTIN_PADDSB512,
30160 IX86_BUILTIN_PSUBUSB512,
30161 IX86_BUILTIN_PADDUSB512,
30162 IX86_BUILTIN_PSUBW512,
30163 IX86_BUILTIN_PADDW512,
30164 IX86_BUILTIN_PSUBSW512,
30165 IX86_BUILTIN_PADDSW512,
30166 IX86_BUILTIN_PSUBUSW512,
30167 IX86_BUILTIN_PADDUSW512,
30168 IX86_BUILTIN_PMAXUW512,
30169 IX86_BUILTIN_PMAXSW512,
30170 IX86_BUILTIN_PMINUW512,
30171 IX86_BUILTIN_PMINSW512,
30172 IX86_BUILTIN_PMAXUB512,
30173 IX86_BUILTIN_PMAXSB512,
30174 IX86_BUILTIN_PMINUB512,
30175 IX86_BUILTIN_PMINSB512,
30176 IX86_BUILTIN_PMOVWB512,
30177 IX86_BUILTIN_PMOVSWB512,
30178 IX86_BUILTIN_PMOVUSWB512,
30179 IX86_BUILTIN_PMULHRSW512_MASK,
30180 IX86_BUILTIN_PMULHUW512_MASK,
30181 IX86_BUILTIN_PMULHW512_MASK,
30182 IX86_BUILTIN_PMULLW512_MASK,
30183 IX86_BUILTIN_PSLLWI512_MASK,
30184 IX86_BUILTIN_PSLLW512_MASK,
30185 IX86_BUILTIN_PACKSSWB512,
30186 IX86_BUILTIN_PACKUSWB512,
30187 IX86_BUILTIN_PSRAVV32HI,
30188 IX86_BUILTIN_PMADDUBSW512_MASK,
30189 IX86_BUILTIN_PMADDWD512_MASK,
30190 IX86_BUILTIN_PSRLVV32HI,
30191 IX86_BUILTIN_PUNPCKHBW512,
30192 IX86_BUILTIN_PUNPCKHWD512,
30193 IX86_BUILTIN_PUNPCKLBW512,
30194 IX86_BUILTIN_PUNPCKLWD512,
30195 IX86_BUILTIN_PSHUFB512,
30196 IX86_BUILTIN_PSHUFHW512,
30197 IX86_BUILTIN_PSHUFLW512,
30198 IX86_BUILTIN_PSRAWI512,
30199 IX86_BUILTIN_PSRAW512,
30200 IX86_BUILTIN_PSRLWI512,
30201 IX86_BUILTIN_PSRLW512,
30202 IX86_BUILTIN_CVTB2MASK512,
30203 IX86_BUILTIN_CVTW2MASK512,
30204 IX86_BUILTIN_CVTMASK2B512,
30205 IX86_BUILTIN_CVTMASK2W512,
30206 IX86_BUILTIN_PCMPEQB512_MASK,
30207 IX86_BUILTIN_PCMPEQW512_MASK,
30208 IX86_BUILTIN_PCMPGTB512_MASK,
30209 IX86_BUILTIN_PCMPGTW512_MASK,
30210 IX86_BUILTIN_PTESTMB512,
30211 IX86_BUILTIN_PTESTMW512,
30212 IX86_BUILTIN_PTESTNMB512,
30213 IX86_BUILTIN_PTESTNMW512,
30214 IX86_BUILTIN_PSLLVV32HI,
30215 IX86_BUILTIN_PABSB512,
30216 IX86_BUILTIN_PABSW512,
30217 IX86_BUILTIN_BLENDMW512,
30218 IX86_BUILTIN_BLENDMB512,
30219 IX86_BUILTIN_CMPB512,
30220 IX86_BUILTIN_CMPW512,
30221 IX86_BUILTIN_UCMPB512,
30222 IX86_BUILTIN_UCMPW512,
30224 /* Alternate 4 and 8 element gather/scatter for the vectorizer
30225 where all operands are 32-byte or 64-byte wide respectively. */
30226 IX86_BUILTIN_GATHERALTSIV4DF,
30227 IX86_BUILTIN_GATHERALTDIV8SF,
30228 IX86_BUILTIN_GATHERALTSIV4DI,
30229 IX86_BUILTIN_GATHERALTDIV8SI,
30230 IX86_BUILTIN_GATHER3ALTDIV16SF,
30231 IX86_BUILTIN_GATHER3ALTDIV16SI,
30232 IX86_BUILTIN_GATHER3ALTSIV4DF,
30233 IX86_BUILTIN_GATHER3ALTDIV8SF,
30234 IX86_BUILTIN_GATHER3ALTSIV4DI,
30235 IX86_BUILTIN_GATHER3ALTDIV8SI,
30236 IX86_BUILTIN_GATHER3ALTSIV8DF,
30237 IX86_BUILTIN_GATHER3ALTSIV8DI,
30238 IX86_BUILTIN_GATHER3DIV16SF,
30239 IX86_BUILTIN_GATHER3DIV16SI,
30240 IX86_BUILTIN_GATHER3DIV8DF,
30241 IX86_BUILTIN_GATHER3DIV8DI,
30242 IX86_BUILTIN_GATHER3SIV16SF,
30243 IX86_BUILTIN_GATHER3SIV16SI,
30244 IX86_BUILTIN_GATHER3SIV8DF,
30245 IX86_BUILTIN_GATHER3SIV8DI,
30246 IX86_BUILTIN_SCATTERDIV16SF,
30247 IX86_BUILTIN_SCATTERDIV16SI,
30248 IX86_BUILTIN_SCATTERDIV8DF,
30249 IX86_BUILTIN_SCATTERDIV8DI,
30250 IX86_BUILTIN_SCATTERSIV16SF,
30251 IX86_BUILTIN_SCATTERSIV16SI,
30252 IX86_BUILTIN_SCATTERSIV8DF,
30253 IX86_BUILTIN_SCATTERSIV8DI,
30255 /* AVX512PF */
30256 IX86_BUILTIN_GATHERPFQPD,
30257 IX86_BUILTIN_GATHERPFDPS,
30258 IX86_BUILTIN_GATHERPFDPD,
30259 IX86_BUILTIN_GATHERPFQPS,
30260 IX86_BUILTIN_SCATTERPFDPD,
30261 IX86_BUILTIN_SCATTERPFDPS,
30262 IX86_BUILTIN_SCATTERPFQPD,
30263 IX86_BUILTIN_SCATTERPFQPS,
30265 /* AVX-512ER */
30266 IX86_BUILTIN_EXP2PD_MASK,
30267 IX86_BUILTIN_EXP2PS_MASK,
30268 IX86_BUILTIN_EXP2PS,
30269 IX86_BUILTIN_RCP28PD,
30270 IX86_BUILTIN_RCP28PS,
30271 IX86_BUILTIN_RCP28SD,
30272 IX86_BUILTIN_RCP28SS,
30273 IX86_BUILTIN_RSQRT28PD,
30274 IX86_BUILTIN_RSQRT28PS,
30275 IX86_BUILTIN_RSQRT28SD,
30276 IX86_BUILTIN_RSQRT28SS,
30278 /* AVX-512IFMA */
30279 IX86_BUILTIN_VPMADD52LUQ512,
30280 IX86_BUILTIN_VPMADD52HUQ512,
30281 IX86_BUILTIN_VPMADD52LUQ256,
30282 IX86_BUILTIN_VPMADD52HUQ256,
30283 IX86_BUILTIN_VPMADD52LUQ128,
30284 IX86_BUILTIN_VPMADD52HUQ128,
30285 IX86_BUILTIN_VPMADD52LUQ512_MASKZ,
30286 IX86_BUILTIN_VPMADD52HUQ512_MASKZ,
30287 IX86_BUILTIN_VPMADD52LUQ256_MASKZ,
30288 IX86_BUILTIN_VPMADD52HUQ256_MASKZ,
30289 IX86_BUILTIN_VPMADD52LUQ128_MASKZ,
30290 IX86_BUILTIN_VPMADD52HUQ128_MASKZ,
30292 /* AVX-512VBMI */
30293 IX86_BUILTIN_VPMULTISHIFTQB512,
30294 IX86_BUILTIN_VPMULTISHIFTQB256,
30295 IX86_BUILTIN_VPMULTISHIFTQB128,
30296 IX86_BUILTIN_VPERMVARQI512_MASK,
30297 IX86_BUILTIN_VPERMT2VARQI512,
30298 IX86_BUILTIN_VPERMT2VARQI512_MASKZ,
30299 IX86_BUILTIN_VPERMI2VARQI512,
30300 IX86_BUILTIN_VPERMVARQI256_MASK,
30301 IX86_BUILTIN_VPERMVARQI128_MASK,
30302 IX86_BUILTIN_VPERMT2VARQI256,
30303 IX86_BUILTIN_VPERMT2VARQI256_MASKZ,
30304 IX86_BUILTIN_VPERMT2VARQI128,
30305 IX86_BUILTIN_VPERMT2VARQI128_MASKZ,
30306 IX86_BUILTIN_VPERMI2VARQI256,
30307 IX86_BUILTIN_VPERMI2VARQI128,
30309 /* SHA builtins. */
30310 IX86_BUILTIN_SHA1MSG1,
30311 IX86_BUILTIN_SHA1MSG2,
30312 IX86_BUILTIN_SHA1NEXTE,
30313 IX86_BUILTIN_SHA1RNDS4,
30314 IX86_BUILTIN_SHA256MSG1,
30315 IX86_BUILTIN_SHA256MSG2,
30316 IX86_BUILTIN_SHA256RNDS2,
30318 /* CLWB instructions. */
30319 IX86_BUILTIN_CLWB,
30321 /* PCOMMIT instructions. */
30322 IX86_BUILTIN_PCOMMIT,
30324 /* CLFLUSHOPT instructions. */
30325 IX86_BUILTIN_CLFLUSHOPT,
30327 /* TFmode support builtins. */
30328 IX86_BUILTIN_INFQ,
30329 IX86_BUILTIN_HUGE_VALQ,
30330 IX86_BUILTIN_FABSQ,
30331 IX86_BUILTIN_COPYSIGNQ,
30333 /* Vectorizer support builtins. */
30334 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
30335 IX86_BUILTIN_CPYSGNPS,
30336 IX86_BUILTIN_CPYSGNPD,
30337 IX86_BUILTIN_CPYSGNPS256,
30338 IX86_BUILTIN_CPYSGNPS512,
30339 IX86_BUILTIN_CPYSGNPD256,
30340 IX86_BUILTIN_CPYSGNPD512,
30341 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
30342 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
30345 /* FMA4 instructions. */
30346 IX86_BUILTIN_VFMADDSS,
30347 IX86_BUILTIN_VFMADDSD,
30348 IX86_BUILTIN_VFMADDPS,
30349 IX86_BUILTIN_VFMADDPD,
30350 IX86_BUILTIN_VFMADDPS256,
30351 IX86_BUILTIN_VFMADDPD256,
30352 IX86_BUILTIN_VFMADDSUBPS,
30353 IX86_BUILTIN_VFMADDSUBPD,
30354 IX86_BUILTIN_VFMADDSUBPS256,
30355 IX86_BUILTIN_VFMADDSUBPD256,
30357 /* FMA3 instructions. */
30358 IX86_BUILTIN_VFMADDSS3,
30359 IX86_BUILTIN_VFMADDSD3,
30361 /* XOP instructions. */
30362 IX86_BUILTIN_VPCMOV,
30363 IX86_BUILTIN_VPCMOV_V2DI,
30364 IX86_BUILTIN_VPCMOV_V4SI,
30365 IX86_BUILTIN_VPCMOV_V8HI,
30366 IX86_BUILTIN_VPCMOV_V16QI,
30367 IX86_BUILTIN_VPCMOV_V4SF,
30368 IX86_BUILTIN_VPCMOV_V2DF,
30369 IX86_BUILTIN_VPCMOV256,
30370 IX86_BUILTIN_VPCMOV_V4DI256,
30371 IX86_BUILTIN_VPCMOV_V8SI256,
30372 IX86_BUILTIN_VPCMOV_V16HI256,
30373 IX86_BUILTIN_VPCMOV_V32QI256,
30374 IX86_BUILTIN_VPCMOV_V8SF256,
30375 IX86_BUILTIN_VPCMOV_V4DF256,
30377 IX86_BUILTIN_VPPERM,
30379 IX86_BUILTIN_VPMACSSWW,
30380 IX86_BUILTIN_VPMACSWW,
30381 IX86_BUILTIN_VPMACSSWD,
30382 IX86_BUILTIN_VPMACSWD,
30383 IX86_BUILTIN_VPMACSSDD,
30384 IX86_BUILTIN_VPMACSDD,
30385 IX86_BUILTIN_VPMACSSDQL,
30386 IX86_BUILTIN_VPMACSSDQH,
30387 IX86_BUILTIN_VPMACSDQL,
30388 IX86_BUILTIN_VPMACSDQH,
30389 IX86_BUILTIN_VPMADCSSWD,
30390 IX86_BUILTIN_VPMADCSWD,
30392 IX86_BUILTIN_VPHADDBW,
30393 IX86_BUILTIN_VPHADDBD,
30394 IX86_BUILTIN_VPHADDBQ,
30395 IX86_BUILTIN_VPHADDWD,
30396 IX86_BUILTIN_VPHADDWQ,
30397 IX86_BUILTIN_VPHADDDQ,
30398 IX86_BUILTIN_VPHADDUBW,
30399 IX86_BUILTIN_VPHADDUBD,
30400 IX86_BUILTIN_VPHADDUBQ,
30401 IX86_BUILTIN_VPHADDUWD,
30402 IX86_BUILTIN_VPHADDUWQ,
30403 IX86_BUILTIN_VPHADDUDQ,
30404 IX86_BUILTIN_VPHSUBBW,
30405 IX86_BUILTIN_VPHSUBWD,
30406 IX86_BUILTIN_VPHSUBDQ,
30408 IX86_BUILTIN_VPROTB,
30409 IX86_BUILTIN_VPROTW,
30410 IX86_BUILTIN_VPROTD,
30411 IX86_BUILTIN_VPROTQ,
30412 IX86_BUILTIN_VPROTB_IMM,
30413 IX86_BUILTIN_VPROTW_IMM,
30414 IX86_BUILTIN_VPROTD_IMM,
30415 IX86_BUILTIN_VPROTQ_IMM,
30417 IX86_BUILTIN_VPSHLB,
30418 IX86_BUILTIN_VPSHLW,
30419 IX86_BUILTIN_VPSHLD,
30420 IX86_BUILTIN_VPSHLQ,
30421 IX86_BUILTIN_VPSHAB,
30422 IX86_BUILTIN_VPSHAW,
30423 IX86_BUILTIN_VPSHAD,
30424 IX86_BUILTIN_VPSHAQ,
30426 IX86_BUILTIN_VFRCZSS,
30427 IX86_BUILTIN_VFRCZSD,
30428 IX86_BUILTIN_VFRCZPS,
30429 IX86_BUILTIN_VFRCZPD,
30430 IX86_BUILTIN_VFRCZPS256,
30431 IX86_BUILTIN_VFRCZPD256,
30433 IX86_BUILTIN_VPCOMEQUB,
30434 IX86_BUILTIN_VPCOMNEUB,
30435 IX86_BUILTIN_VPCOMLTUB,
30436 IX86_BUILTIN_VPCOMLEUB,
30437 IX86_BUILTIN_VPCOMGTUB,
30438 IX86_BUILTIN_VPCOMGEUB,
30439 IX86_BUILTIN_VPCOMFALSEUB,
30440 IX86_BUILTIN_VPCOMTRUEUB,
30442 IX86_BUILTIN_VPCOMEQUW,
30443 IX86_BUILTIN_VPCOMNEUW,
30444 IX86_BUILTIN_VPCOMLTUW,
30445 IX86_BUILTIN_VPCOMLEUW,
30446 IX86_BUILTIN_VPCOMGTUW,
30447 IX86_BUILTIN_VPCOMGEUW,
30448 IX86_BUILTIN_VPCOMFALSEUW,
30449 IX86_BUILTIN_VPCOMTRUEUW,
30451 IX86_BUILTIN_VPCOMEQUD,
30452 IX86_BUILTIN_VPCOMNEUD,
30453 IX86_BUILTIN_VPCOMLTUD,
30454 IX86_BUILTIN_VPCOMLEUD,
30455 IX86_BUILTIN_VPCOMGTUD,
30456 IX86_BUILTIN_VPCOMGEUD,
30457 IX86_BUILTIN_VPCOMFALSEUD,
30458 IX86_BUILTIN_VPCOMTRUEUD,
30460 IX86_BUILTIN_VPCOMEQUQ,
30461 IX86_BUILTIN_VPCOMNEUQ,
30462 IX86_BUILTIN_VPCOMLTUQ,
30463 IX86_BUILTIN_VPCOMLEUQ,
30464 IX86_BUILTIN_VPCOMGTUQ,
30465 IX86_BUILTIN_VPCOMGEUQ,
30466 IX86_BUILTIN_VPCOMFALSEUQ,
30467 IX86_BUILTIN_VPCOMTRUEUQ,
30469 IX86_BUILTIN_VPCOMEQB,
30470 IX86_BUILTIN_VPCOMNEB,
30471 IX86_BUILTIN_VPCOMLTB,
30472 IX86_BUILTIN_VPCOMLEB,
30473 IX86_BUILTIN_VPCOMGTB,
30474 IX86_BUILTIN_VPCOMGEB,
30475 IX86_BUILTIN_VPCOMFALSEB,
30476 IX86_BUILTIN_VPCOMTRUEB,
30478 IX86_BUILTIN_VPCOMEQW,
30479 IX86_BUILTIN_VPCOMNEW,
30480 IX86_BUILTIN_VPCOMLTW,
30481 IX86_BUILTIN_VPCOMLEW,
30482 IX86_BUILTIN_VPCOMGTW,
30483 IX86_BUILTIN_VPCOMGEW,
30484 IX86_BUILTIN_VPCOMFALSEW,
30485 IX86_BUILTIN_VPCOMTRUEW,
30487 IX86_BUILTIN_VPCOMEQD,
30488 IX86_BUILTIN_VPCOMNED,
30489 IX86_BUILTIN_VPCOMLTD,
30490 IX86_BUILTIN_VPCOMLED,
30491 IX86_BUILTIN_VPCOMGTD,
30492 IX86_BUILTIN_VPCOMGED,
30493 IX86_BUILTIN_VPCOMFALSED,
30494 IX86_BUILTIN_VPCOMTRUED,
30496 IX86_BUILTIN_VPCOMEQQ,
30497 IX86_BUILTIN_VPCOMNEQ,
30498 IX86_BUILTIN_VPCOMLTQ,
30499 IX86_BUILTIN_VPCOMLEQ,
30500 IX86_BUILTIN_VPCOMGTQ,
30501 IX86_BUILTIN_VPCOMGEQ,
30502 IX86_BUILTIN_VPCOMFALSEQ,
30503 IX86_BUILTIN_VPCOMTRUEQ,
30505 /* LWP instructions. */
30506 IX86_BUILTIN_LLWPCB,
30507 IX86_BUILTIN_SLWPCB,
30508 IX86_BUILTIN_LWPVAL32,
30509 IX86_BUILTIN_LWPVAL64,
30510 IX86_BUILTIN_LWPINS32,
30511 IX86_BUILTIN_LWPINS64,
30513 IX86_BUILTIN_CLZS,
30515 /* RTM */
30516 IX86_BUILTIN_XBEGIN,
30517 IX86_BUILTIN_XEND,
30518 IX86_BUILTIN_XABORT,
30519 IX86_BUILTIN_XTEST,
30521 /* MPX */
30522 IX86_BUILTIN_BNDMK,
30523 IX86_BUILTIN_BNDSTX,
30524 IX86_BUILTIN_BNDLDX,
30525 IX86_BUILTIN_BNDCL,
30526 IX86_BUILTIN_BNDCU,
30527 IX86_BUILTIN_BNDRET,
30528 IX86_BUILTIN_BNDNARROW,
30529 IX86_BUILTIN_BNDINT,
30530 IX86_BUILTIN_SIZEOF,
30531 IX86_BUILTIN_BNDLOWER,
30532 IX86_BUILTIN_BNDUPPER,
30534 /* BMI instructions. */
30535 IX86_BUILTIN_BEXTR32,
30536 IX86_BUILTIN_BEXTR64,
30537 IX86_BUILTIN_CTZS,
30539 /* TBM instructions. */
30540 IX86_BUILTIN_BEXTRI32,
30541 IX86_BUILTIN_BEXTRI64,
30543 /* BMI2 instructions. */
30544 IX86_BUILTIN_BZHI32,
30545 IX86_BUILTIN_BZHI64,
30546 IX86_BUILTIN_PDEP32,
30547 IX86_BUILTIN_PDEP64,
30548 IX86_BUILTIN_PEXT32,
30549 IX86_BUILTIN_PEXT64,
30551 /* ADX instructions. */
30552 IX86_BUILTIN_ADDCARRYX32,
30553 IX86_BUILTIN_ADDCARRYX64,
30555 /* SBB instructions. */
30556 IX86_BUILTIN_SBB32,
30557 IX86_BUILTIN_SBB64,
30559 /* FSGSBASE instructions. */
30560 IX86_BUILTIN_RDFSBASE32,
30561 IX86_BUILTIN_RDFSBASE64,
30562 IX86_BUILTIN_RDGSBASE32,
30563 IX86_BUILTIN_RDGSBASE64,
30564 IX86_BUILTIN_WRFSBASE32,
30565 IX86_BUILTIN_WRFSBASE64,
30566 IX86_BUILTIN_WRGSBASE32,
30567 IX86_BUILTIN_WRGSBASE64,
30569 /* RDRND instructions. */
30570 IX86_BUILTIN_RDRAND16_STEP,
30571 IX86_BUILTIN_RDRAND32_STEP,
30572 IX86_BUILTIN_RDRAND64_STEP,
30574 /* RDSEED instructions. */
30575 IX86_BUILTIN_RDSEED16_STEP,
30576 IX86_BUILTIN_RDSEED32_STEP,
30577 IX86_BUILTIN_RDSEED64_STEP,
30579 /* F16C instructions. */
30580 IX86_BUILTIN_CVTPH2PS,
30581 IX86_BUILTIN_CVTPH2PS256,
30582 IX86_BUILTIN_CVTPS2PH,
30583 IX86_BUILTIN_CVTPS2PH256,
30585 /* MONITORX and MWAITX instrucions. */
30586 IX86_BUILTIN_MONITORX,
30587 IX86_BUILTIN_MWAITX,
30589 /* CFString built-in for darwin */
30590 IX86_BUILTIN_CFSTRING,
30592 /* Builtins to get CPU type and supported features. */
30593 IX86_BUILTIN_CPU_INIT,
30594 IX86_BUILTIN_CPU_IS,
30595 IX86_BUILTIN_CPU_SUPPORTS,
30597 /* Read/write FLAGS register built-ins. */
30598 IX86_BUILTIN_READ_FLAGS,
30599 IX86_BUILTIN_WRITE_FLAGS,
30601 IX86_BUILTIN_MAX
30602 };
30604 /* Table for the ix86 builtin decls. */
30607 /* Table of all of the builtin functions that are possible with different ISA's
30608 but are waiting to be built until a function is declared to use that
30609 ISA. */
30618 };
30622 /* Bits that can still enable any inclusion of a builtin. */
30625 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
30626 of which isa_flags to use in the ix86_builtins_isa array. Stores the
30627 function decl in the ix86_builtins array. Returns the function decl or
30628 NULL_TREE, if the builtin was not added.
30630 If the front end has a special hook for builtin functions, delay adding
30631 builtin functions that aren't in the current ISA until the ISA is changed
30632 with function specific optimization. Doing so, can save about 300K for the
30633 default compiler. When the builtin is expanded, check at that time whether
30634 it is valid.
30636 If the front end doesn't have a special hook, record all builtins, even if
30637 it isn't an instruction set in the current ISA in case the user uses
30638 function specific options for a different ISA, so that we don't get scope
30639 errors if a builtin is added in the middle of a function scope. */
30645 {
30649 {
30658 {
30664 }
30665 else
30666 {
30667 /* Just a MASK where set_and_not_built_p == true can potentially
30668 include a builtin. */
30677 }
30678 }
30681 }
30683 /* Like def_builtin, but also marks the function decl "const". */
30688 {
30692 else
30696 }
30698 /* Add any new builtin functions for a given ISA that may not have been
30699 declared. This saves a bit of space compared to adding all of the
30700 declarations to the tree, even if we didn't use them. */
30702 static void
30704 {
30708 /* Bits in ISA value can be removed from potential isa values. */
30716 {
30719 {
30722 /* Don't define the builtin again. */
30728 NULL_TREE);
30735 NULL_TREE);
30738 }
30739 }
30742 }
30744 /* Bits for builtin_description.flag. */
30746 /* Set when we don't support the comparison natively, and should
30747 swap_comparison in order to support it. */
30748 #define BUILTIN_DESC_SWAP_OPERANDS 1
30750 struct builtin_description
30751 {
30758 };
30761 {
30762 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
30763 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
30764 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
30765 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
30766 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
30767 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
30768 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
30769 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
30770 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
30771 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
30772 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
30773 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
30774 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
30775 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
30776 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
30777 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
30778 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
30779 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
30780 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
30781 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
30782 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
30783 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
30784 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
30785 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
30786 };
30789 {
30790 /* SSE4.2 */
30791 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
30792 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
30793 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
30794 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
30795 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
30796 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
30797 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
30798 };
30801 {
30802 /* SSE4.2 */
30803 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
30804 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
30805 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
30806 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
30807 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
30808 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
30809 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
30810 };
30812 /* Special builtins with variable number of arguments. */
30814 {
30815 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
30816 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
30817 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
30819 /* 80387 (for use internally for atomic compound assignment). */
30820 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
30821 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
30822 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) USHORT_FTYPE_VOID },
30823 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
30825 /* MMX */
30826 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30828 /* 3DNow! */
30829 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30831 /* FXSR, XSAVE, XSAVEOPT, XSAVEC and XSAVES. */
30832 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
30833 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
30834 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30835 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30836 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30837 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xsaves", IX86_BUILTIN_XSAVES, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30838 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xrstors", IX86_BUILTIN_XRSTORS, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30839 { OPTION_MASK_ISA_XSAVEC, CODE_FOR_nothing, "__builtin_ia32_xsavec", IX86_BUILTIN_XSAVEC, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30841 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30842 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30843 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30844 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30845 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30846 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaves64", IX86_BUILTIN_XSAVES64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30847 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30848 { OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30850 /* SSE */
30851 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30852 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30853 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30855 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30856 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30857 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30858 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30860 /* SSE or 3DNow!A */
30861 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30862 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
30864 /* SSE2 */
30865 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30866 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30867 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30868 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
30869 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30870 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
30871 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
30872 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
30873 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
30874 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30876 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30877 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30879 /* SSE3 */
30880 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30882 /* SSE4.1 */
30883 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
30885 /* SSE4A */
30886 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30887 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30889 /* AVX */
30890 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
30891 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
30893 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30894 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30895 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30896 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
30897 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
30899 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30900 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30901 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30902 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30903 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30904 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
30905 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30907 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
30908 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30909 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30911 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
30912 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
30913 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
30914 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
30915 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
30916 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
30917 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
30918 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
30920 /* AVX2 */
30921 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
30922 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
30923 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
30924 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
30925 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
30926 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
30927 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
30928 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
30929 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
30931 /* AVX512F */
30932 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30933 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30934 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30935 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30936 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30937 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30938 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30939 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30940 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30941 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30943 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30944 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30945 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30946 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30947 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30949 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30950 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30952 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
30953 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
30954 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
30955 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
30956 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30957 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30958 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30959 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30960 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30961 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30962 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30963 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30964 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30965 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30966 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30967 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30968 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30969 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30970 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30971 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30972 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30973 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30974 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30975 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30976 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30977 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30978 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30980 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
30981 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
30982 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
30983 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
30984 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
30985 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
30987 /* FSGSBASE */
30988 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30989 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30990 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30991 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30992 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30993 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30994 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30995 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30997 /* RTM */
30998 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30999 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
31000 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
31002 /* AVX512BW */
31003 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_loaddquhi512_mask", IX86_BUILTIN_LOADDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_SI },
31004 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_loaddquqi512_mask", IX86_BUILTIN_LOADDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_DI },
31005 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv32hi_mask, "__builtin_ia32_storedquhi512_mask", IX86_BUILTIN_STOREDQUHI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV32HI_V32HI_SI },
31006 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_DI },
31008 /* AVX512VL */
31009 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_HI },
31010 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_loaddquhi128_mask", IX86_BUILTIN_LOADDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_QI },
31011 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_loaddquqi256_mask", IX86_BUILTIN_LOADDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_SI },
31012 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_loaddquqi128_mask", IX86_BUILTIN_LOADDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_HI },
31013 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64load256_mask", IX86_BUILTIN_MOVDQA64LOAD256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31014 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64load128_mask", IX86_BUILTIN_MOVDQA64LOAD128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31015 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32load256_mask", IX86_BUILTIN_MOVDQA32LOAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31016 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32load128_mask", IX86_BUILTIN_MOVDQA32LOAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31017 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4di_mask, "__builtin_ia32_movdqa64store256_mask", IX86_BUILTIN_MOVDQA64STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
31018 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2di_mask, "__builtin_ia32_movdqa64store128_mask", IX86_BUILTIN_MOVDQA64STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
31019 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8si_mask, "__builtin_ia32_movdqa32store256_mask", IX86_BUILTIN_MOVDQA32STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
31020 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4si_mask, "__builtin_ia32_movdqa32store128_mask", IX86_BUILTIN_MOVDQA32STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
31021 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_loadapd256_mask", IX86_BUILTIN_LOADAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31022 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_loadapd128_mask", IX86_BUILTIN_LOADAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31023 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_loadaps256_mask", IX86_BUILTIN_LOADAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31024 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_loadaps128_mask", IX86_BUILTIN_LOADAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31025 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4df_mask, "__builtin_ia32_storeapd256_mask", IX86_BUILTIN_STOREAPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
31026 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2df_mask, "__builtin_ia32_storeapd128_mask", IX86_BUILTIN_STOREAPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
31027 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8sf_mask, "__builtin_ia32_storeaps256_mask", IX86_BUILTIN_STOREAPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
31028 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4sf_mask, "__builtin_ia32_storeaps128_mask", IX86_BUILTIN_STOREAPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
31029 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadupd256_mask, "__builtin_ia32_loadupd256_mask", IX86_BUILTIN_LOADUPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31030 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loadupd_mask, "__builtin_ia32_loadupd128_mask", IX86_BUILTIN_LOADUPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31031 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadups256_mask, "__builtin_ia32_loadups256_mask", IX86_BUILTIN_LOADUPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31032 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_loadups_mask, "__builtin_ia32_loadups128_mask", IX86_BUILTIN_LOADUPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31033 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd256_mask, "__builtin_ia32_storeupd256_mask", IX86_BUILTIN_STOREUPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
31034 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd_mask, "__builtin_ia32_storeupd128_mask", IX86_BUILTIN_STOREUPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
31035 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups256_mask, "__builtin_ia32_storeups256_mask", IX86_BUILTIN_STOREUPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
31036 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups_mask, "__builtin_ia32_storeups128_mask", IX86_BUILTIN_STOREUPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
31037 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv4di_mask, "__builtin_ia32_loaddqudi256_mask", IX86_BUILTIN_LOADDQUDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31038 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv2di_mask, "__builtin_ia32_loaddqudi128_mask", IX86_BUILTIN_LOADDQUDI128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31039 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv8si_mask, "__builtin_ia32_loaddqusi256_mask", IX86_BUILTIN_LOADDQUSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31040 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv4si_mask, "__builtin_ia32_loaddqusi128_mask", IX86_BUILTIN_LOADDQUSI128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31041 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4di_mask, "__builtin_ia32_storedqudi256_mask", IX86_BUILTIN_STOREDQUDI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
31042 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv2di_mask, "__builtin_ia32_storedqudi128_mask", IX86_BUILTIN_STOREDQUDI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
31043 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8si_mask, "__builtin_ia32_storedqusi256_mask", IX86_BUILTIN_STOREDQUSI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
31044 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4si_mask, "__builtin_ia32_storedqusi128_mask", IX86_BUILTIN_STOREDQUSI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
31045 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16hi_mask, "__builtin_ia32_storedquhi256_mask", IX86_BUILTIN_STOREDQUHI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16HI_HI },
31046 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8hi_mask, "__builtin_ia32_storedquhi128_mask", IX86_BUILTIN_STOREDQUHI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8HI_QI },
31047 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv32qi_mask, "__builtin_ia32_storedquqi256_mask", IX86_BUILTIN_STOREDQUQI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV32QI_V32QI_SI },
31048 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16qi_mask, "__builtin_ia32_storedquqi128_mask", IX86_BUILTIN_STOREDQUQI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16QI_HI },
31049 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4df_mask, "__builtin_ia32_compressstoredf256_mask", IX86_BUILTIN_COMPRESSPDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
31050 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2df_mask, "__builtin_ia32_compressstoredf128_mask", IX86_BUILTIN_COMPRESSPDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
31051 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8sf_mask, "__builtin_ia32_compressstoresf256_mask", IX86_BUILTIN_COMPRESSPSSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
31052 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4sf_mask, "__builtin_ia32_compressstoresf128_mask", IX86_BUILTIN_COMPRESSPSSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
31053 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4di_mask, "__builtin_ia32_compressstoredi256_mask", IX86_BUILTIN_PCOMPRESSQSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
31054 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2di_mask, "__builtin_ia32_compressstoredi128_mask", IX86_BUILTIN_PCOMPRESSQSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
31055 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8si_mask, "__builtin_ia32_compressstoresi256_mask", IX86_BUILTIN_PCOMPRESSDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
31056 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4si_mask, "__builtin_ia32_compressstoresi128_mask", IX86_BUILTIN_PCOMPRESSDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
31057 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expandloaddf256_mask", IX86_BUILTIN_EXPANDPDLOAD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31058 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expandloaddf128_mask", IX86_BUILTIN_EXPANDPDLOAD128, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31059 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandloadsf256_mask", IX86_BUILTIN_EXPANDPSLOAD256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31060 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandloadsf128_mask", IX86_BUILTIN_EXPANDPSLOAD128, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31061 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expandloaddi256_mask", IX86_BUILTIN_PEXPANDQLOAD256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31062 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expandloaddi128_mask", IX86_BUILTIN_PEXPANDQLOAD128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31063 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandloadsi256_mask", IX86_BUILTIN_PEXPANDDLOAD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31064 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandloadsi128_mask", IX86_BUILTIN_PEXPANDDLOAD128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31065 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expandloaddf256_maskz", IX86_BUILTIN_EXPANDPDLOAD256Z, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31066 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expandloaddf128_maskz", IX86_BUILTIN_EXPANDPDLOAD128Z, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31067 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandloadsf256_maskz", IX86_BUILTIN_EXPANDPSLOAD256Z, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31068 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandloadsf128_maskz", IX86_BUILTIN_EXPANDPSLOAD128Z, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31069 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expandloaddi256_maskz", IX86_BUILTIN_PEXPANDQLOAD256Z, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31070 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expandloaddi128_maskz", IX86_BUILTIN_PEXPANDQLOAD128Z, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31071 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandloadsi256_maskz", IX86_BUILTIN_PEXPANDDLOAD256Z, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31072 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandloadsi128_maskz", IX86_BUILTIN_PEXPANDDLOAD128Z, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31073 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask_store, "__builtin_ia32_pmovqd256mem_mask", IX86_BUILTIN_PMOVQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
31074 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask_store, "__builtin_ia32_pmovqd128mem_mask", IX86_BUILTIN_PMOVQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
31075 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask_store, "__builtin_ia32_pmovsqd256mem_mask", IX86_BUILTIN_PMOVSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
31076 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask_store, "__builtin_ia32_pmovsqd128mem_mask", IX86_BUILTIN_PMOVSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
31077 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask_store, "__builtin_ia32_pmovusqd256mem_mask", IX86_BUILTIN_PMOVUSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
31078 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask_store, "__builtin_ia32_pmovusqd128mem_mask", IX86_BUILTIN_PMOVUSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
31079 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovqw256mem_mask", IX86_BUILTIN_PMOVQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
31080 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovqw128mem_mask", IX86_BUILTIN_PMOVQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
31081 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovsqw256mem_mask", IX86_BUILTIN_PMOVSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
31082 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovsqw128mem_mask", IX86_BUILTIN_PMOVSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
31083 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovusqw256mem_mask", IX86_BUILTIN_PMOVUSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
31084 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovusqw128mem_mask", IX86_BUILTIN_PMOVUSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
31085 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovqb256mem_mask", IX86_BUILTIN_PMOVQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
31086 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovqb128mem_mask", IX86_BUILTIN_PMOVQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
31087 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovsqb256mem_mask", IX86_BUILTIN_PMOVSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
31088 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovsqb128mem_mask", IX86_BUILTIN_PMOVSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
31089 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovusqb256mem_mask", IX86_BUILTIN_PMOVUSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
31090 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovusqb128mem_mask", IX86_BUILTIN_PMOVUSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
31091 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovdb256mem_mask", IX86_BUILTIN_PMOVDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
31092 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovdb128mem_mask", IX86_BUILTIN_PMOVDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
31093 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovsdb256mem_mask", IX86_BUILTIN_PMOVSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
31094 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovsdb128mem_mask", IX86_BUILTIN_PMOVSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
31095 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovusdb256mem_mask", IX86_BUILTIN_PMOVUSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
31096 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovusdb128mem_mask", IX86_BUILTIN_PMOVUSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
31097 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovdw256mem_mask", IX86_BUILTIN_PMOVDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
31098 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovdw128mem_mask", IX86_BUILTIN_PMOVDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
31099 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovsdw256mem_mask", IX86_BUILTIN_PMOVSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
31100 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
31101 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
31102 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
31104 /* PCOMMIT. */
31105 { OPTION_MASK_ISA_PCOMMIT, CODE_FOR_pcommit, "__builtin_ia32_pcommit", IX86_BUILTIN_PCOMMIT, UNKNOWN, (int) VOID_FTYPE_VOID },
31106 };
31108 /* Builtins with variable number of arguments. */
31110 {
31111 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
31112 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
31113 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
31114 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
31115 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
31116 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
31117 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
31119 /* MMX */
31120 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31121 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31122 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31123 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31124 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31125 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31127 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31128 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31129 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31130 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31131 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31132 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31133 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31134 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31136 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31137 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31139 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31140 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31141 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31142 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31144 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31145 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31146 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31147 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31148 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31149 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31151 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31152 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31153 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31154 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31155 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
31156 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
31158 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31159 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
31160 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31162 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
31164 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31165 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31166 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31167 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31168 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31169 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31171 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31172 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31173 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31174 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31175 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31176 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31178 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31179 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31180 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31181 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31183 /* 3DNow! */
31184 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31185 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31186 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31187 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31189 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31190 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31191 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31192 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31193 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31194 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31195 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31196 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31197 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31198 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31199 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31200 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31201 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31202 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31203 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31205 /* 3DNow!A */
31206 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31207 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31208 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31209 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31210 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31211 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31213 /* SSE */
31214 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
31215 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31216 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31217 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31218 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31219 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31220 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31221 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31222 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31223 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31224 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31225 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31227 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31229 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31230 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31231 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31232 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31233 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31234 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31235 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31236 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31238 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31239 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31240 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31241 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31242 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31243 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31244 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31245 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31246 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31247 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31248 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
31249 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31250 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31251 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31252 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31253 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31254 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31255 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31256 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31257 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31259 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31260 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31261 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31262 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31264 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31265 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31266 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31267 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31269 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31271 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31272 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31273 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31274 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31275 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31277 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
31278 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
31279 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
31281 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
31283 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31284 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31285 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31287 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
31288 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
31290 /* SSE MMX or 3Dnow!A */
31291 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31292 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31293 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31295 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31296 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31297 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31298 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31300 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
31301 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
31303 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
31305 /* SSE2 */
31306 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31308 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
31309 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
31310 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31311 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
31312 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
31314 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31315 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31316 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
31317 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31318 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31320 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
31322 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31323 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31324 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31325 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31327 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31328 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
31329 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31331 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31332 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31333 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31334 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31335 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31336 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31337 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31338 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31340 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31341 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31342 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31343 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31344 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
31345 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31346 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31347 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31348 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31349 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31350 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31351 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31352 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31353 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31354 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31355 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31356 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31357 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31358 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31359 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31361 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31362 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31363 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31364 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31366 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31367 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31368 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31369 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31371 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31373 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31374 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31375 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31377 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31379 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31380 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31381 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31382 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31383 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31384 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31385 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31386 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31388 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31389 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31390 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31391 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31392 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31393 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31394 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31395 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31397 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31398 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
31400 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31401 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31402 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31403 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31405 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31406 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31408 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31409 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31410 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31411 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31412 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31413 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31415 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31416 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31417 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31418 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31420 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31421 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31422 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31423 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31424 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31425 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31426 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31427 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31429 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31430 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31431 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31433 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31434 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
31436 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
31437 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31439 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
31441 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
31442 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
31443 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
31444 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
31446 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31447 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31448 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31449 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31450 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31451 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31452 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31454 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31455 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31456 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31457 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31458 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31459 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31460 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31462 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31463 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31464 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31465 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31467 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
31468 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31469 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31471 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
31473 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31475 /* SSE2 MMX */
31476 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31477 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31479 /* SSE3 */
31480 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
31481 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31483 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31484 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31485 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31486 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31487 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31488 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31490 /* SSSE3 */
31491 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31492 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
31493 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31494 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
31495 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31496 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31498 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31499 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31500 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31501 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31502 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31503 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31504 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31505 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31506 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31507 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31508 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31509 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31510 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
31511 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
31512 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31513 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31514 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31515 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31516 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31517 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31518 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31519 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31520 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31521 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31523 /* SSSE3. */
31524 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
31525 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
31527 /* SSE4.1 */
31528 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31529 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31530 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
31531 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
31532 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31533 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31534 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31535 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
31536 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
31537 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
31539 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31540 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31541 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31542 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31543 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31544 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31545 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31546 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31547 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31548 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31549 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31550 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31551 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31553 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31554 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31555 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31556 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31557 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31558 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31559 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31560 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31561 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31562 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31563 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31564 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31566 /* SSE4.1 */
31567 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31568 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31569 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31570 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31572 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
31573 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
31574 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
31575 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
31577 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31578 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31580 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31581 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31583 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
31584 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
31585 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
31586 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
31588 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
31589 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
31591 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31592 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31594 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31595 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31596 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31598 /* SSE4.2 */
31599 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31600 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
31601 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
31602 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31603 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31605 /* SSE4A */
31606 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
31607 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
31608 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
31609 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31611 /* AES */
31612 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
31613 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31615 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31616 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31617 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31618 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31620 /* PCLMUL */
31621 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
31623 /* AVX */
31624 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31625 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31626 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31627 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31628 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31629 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31630 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31631 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31632 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31633 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31634 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31635 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31636 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31637 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31638 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31639 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31640 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31641 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31642 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31643 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31644 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31645 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31646 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31647 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31648 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31649 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31651 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
31652 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
31653 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
31654 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31656 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31657 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31658 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
31659 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
31660 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31661 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31662 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31663 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31664 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31665 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31666 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31667 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31668 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31669 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
31670 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
31671 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
31672 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
31673 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
31674 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
31675 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31676 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
31677 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31678 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31679 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31680 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31681 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31682 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31683 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31684 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31685 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31686 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31687 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
31688 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
31689 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
31691 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31692 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31693 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31695 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31696 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31697 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31698 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31699 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31701 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31703 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31704 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31706 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
31707 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
31708 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
31709 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
31711 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31712 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31714 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31715 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31717 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
31718 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
31719 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
31720 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
31722 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
31723 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
31725 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31726 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31728 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31729 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31730 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31731 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31733 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31734 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31735 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31736 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
31737 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
31738 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
31740 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31741 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31742 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31743 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31744 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31745 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31746 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31747 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31748 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31749 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31750 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31751 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31752 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31753 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31754 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31756 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
31757 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
31759 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31760 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31762 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31764 /* AVX2 */
31765 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
31766 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
31767 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
31768 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
31769 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31770 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31771 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31772 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31773 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31774 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31775 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31776 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31777 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31778 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31779 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31780 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31781 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
31782 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31783 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31784 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31785 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31786 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
31787 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
31788 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31789 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31790 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31791 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31792 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31793 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31794 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31795 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31796 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31797 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31798 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31799 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31800 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31801 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31802 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31803 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
31804 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31805 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31806 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31807 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31808 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31809 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31810 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31811 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31812 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31813 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31814 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31815 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31816 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
31817 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31818 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31819 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31820 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31821 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31822 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31823 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31824 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31825 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31826 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31827 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31828 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31829 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31830 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31831 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31832 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31833 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31834 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31835 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31836 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31837 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31838 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31839 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
31840 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31841 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31842 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31843 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31844 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31845 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31846 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31847 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31848 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31849 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31850 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31851 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31852 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31853 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31854 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31855 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31856 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31857 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31858 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31859 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31860 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31861 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31862 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31863 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31864 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31865 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31866 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31867 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31868 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31869 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31870 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31871 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31872 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31873 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31874 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31875 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31876 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31877 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31878 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31879 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31880 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31881 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31882 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31883 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31884 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
31885 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31886 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
31887 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
31888 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31889 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31890 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31891 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31892 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31893 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31894 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31895 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31896 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31897 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
31898 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
31899 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vextractf128v4di, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
31900 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vinsertf128v4di, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
31901 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31902 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31903 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31904 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31905 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31906 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31907 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31908 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31909 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31910 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31912 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31914 /* BMI */
31915 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31916 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31917 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31919 /* TBM */
31920 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31921 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31923 /* F16C */
31924 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
31925 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
31926 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
31927 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
31929 /* BMI2 */
31930 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31931 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31932 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31933 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31934 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31935 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31937 /* AVX512F */
31938 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_256si, "__builtin_ia32_si512_256si", IX86_BUILTIN_SI512_SI256, UNKNOWN, (int) V16SI_FTYPE_V8SI },
31939 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_256ps, "__builtin_ia32_ps512_256ps", IX86_BUILTIN_PS512_PS256, UNKNOWN, (int) V16SF_FTYPE_V8SF },
31940 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_256pd, "__builtin_ia32_pd512_256pd", IX86_BUILTIN_PD512_PD256, UNKNOWN, (int) V8DF_FTYPE_V4DF },
31941 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_si, "__builtin_ia32_si512_si", IX86_BUILTIN_SI512_SI, UNKNOWN, (int) V16SI_FTYPE_V4SI },
31942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_ps, "__builtin_ia32_ps512_ps", IX86_BUILTIN_PS512_PS, UNKNOWN, (int) V16SF_FTYPE_V4SF },
31943 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_pd, "__builtin_ia32_pd512_pd", IX86_BUILTIN_PD512_PD, UNKNOWN, (int) V8DF_FTYPE_V2DF },
31944 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
31945 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
31946 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31947 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31949 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31950 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
31952 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31953 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
31954 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
31955 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31956 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
31957 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
31958 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31959 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31960 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31961 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
31962 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31963 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
31964 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31965 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31966 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31967 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31968 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
31969 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
31970 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
31971 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
31972 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
31973 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
31974 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
31975 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
31976 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31977 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31978 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31979 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31980 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31981 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31982 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31983 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31984 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31985 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31986 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31987 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31988 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31989 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31990 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31991 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31992 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
31993 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
31994 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
31995 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
31996 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
31997 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31998 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
31999 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
32000 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32001 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32002 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32003 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32004 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32005 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32006 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32007 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32008 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32009 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32010 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32011 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32012 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32013 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32014 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32015 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
32016 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
32017 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
32018 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
32019 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
32020 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
32021 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
32022 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
32023 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
32024 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
32025 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
32026 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
32027 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
32028 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
32029 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
32030 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
32031 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
32032 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
32033 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
32034 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
32035 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
32036 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
32037 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
32038 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
32039 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
32040 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
32041 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32042 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
32043 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32044 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32045 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32046 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32047 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32048 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32049 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32050 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32051 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32052 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32053 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32054 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
32055 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32056 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
32057 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32058 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32059 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32060 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
32061 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32062 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
32063 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32064 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32065 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32066 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
32067 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32068 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
32069 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32070 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32071 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32072 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32073 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32074 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
32075 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32076 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
32077 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32078 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32079 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32080 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32081 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32082 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32083 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32084 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32085 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32086 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
32087 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
32088 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32089 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32090 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
32091 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
32092 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
32093 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
32094 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
32095 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
32096 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
32097 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
32098 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
32099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
32100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32104 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32105 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32106 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32107 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
32116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
32121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
32122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
32123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
32124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32125 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32129 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32130 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
32131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
32132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
32133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
32135 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
32136 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
32137 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
32138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32139 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32140 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
32141 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32142 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32144 /* Mask arithmetic operations */
32145 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32146 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32147 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
32148 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32149 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32150 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32151 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
32152 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32153 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32154 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
32156 /* SHA */
32157 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32158 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32159 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32160 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
32161 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32162 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32163 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
32165 /* AVX512VL. */
32166 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT },
32167 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT },
32168 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64_256_mask", IX86_BUILTIN_MOVDQA64_256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32169 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64_128_mask", IX86_BUILTIN_MOVDQA64_128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32170 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32_256_mask", IX86_BUILTIN_MOVDQA32_256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32171 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32_128_mask", IX86_BUILTIN_MOVDQA32_128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32172 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_movapd256_mask", IX86_BUILTIN_MOVAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32173 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_movapd128_mask", IX86_BUILTIN_MOVAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32174 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_movaps256_mask", IX86_BUILTIN_MOVAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32175 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_movaps128_mask", IX86_BUILTIN_MOVAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32176 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_movdquhi256_mask", IX86_BUILTIN_MOVDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32177 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_movdquhi128_mask", IX86_BUILTIN_MOVDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32178 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_movdquqi256_mask", IX86_BUILTIN_MOVDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32179 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_movdquqi128_mask", IX86_BUILTIN_MOVDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32180 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4sf3_mask, "__builtin_ia32_minps_mask", IX86_BUILTIN_MINPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32181 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4sf3_mask, "__builtin_ia32_maxps_mask", IX86_BUILTIN_MAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32182 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2df3_mask, "__builtin_ia32_minpd_mask", IX86_BUILTIN_MINPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32183 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2df3_mask, "__builtin_ia32_maxpd_mask", IX86_BUILTIN_MAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32184 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4df3_mask, "__builtin_ia32_maxpd256_mask", IX86_BUILTIN_MAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32185 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8sf3_mask, "__builtin_ia32_maxps256_mask", IX86_BUILTIN_MAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32186 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4df3_mask, "__builtin_ia32_minpd256_mask", IX86_BUILTIN_MINPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32187 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8sf3_mask, "__builtin_ia32_minps256_mask", IX86_BUILTIN_MINPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32188 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4sf3_mask, "__builtin_ia32_mulps_mask", IX86_BUILTIN_MULPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32189 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_divv4sf3_mask, "__builtin_ia32_divps_mask", IX86_BUILTIN_DIVPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32190 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv2df3_mask, "__builtin_ia32_mulpd_mask", IX86_BUILTIN_MULPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32191 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_divv2df3_mask, "__builtin_ia32_divpd_mask", IX86_BUILTIN_DIVPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32192 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv4df3_mask, "__builtin_ia32_divpd256_mask", IX86_BUILTIN_DIVPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32193 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv8sf3_mask, "__builtin_ia32_divps256_mask", IX86_BUILTIN_DIVPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32194 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4df3_mask, "__builtin_ia32_mulpd256_mask", IX86_BUILTIN_MULPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32195 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8sf3_mask, "__builtin_ia32_mulps256_mask", IX86_BUILTIN_MULPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32196 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2df3_mask, "__builtin_ia32_addpd128_mask", IX86_BUILTIN_ADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32197 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4df3_mask, "__builtin_ia32_addpd256_mask", IX86_BUILTIN_ADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32198 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4sf3_mask, "__builtin_ia32_addps128_mask", IX86_BUILTIN_ADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32199 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8sf3_mask, "__builtin_ia32_addps256_mask", IX86_BUILTIN_ADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32200 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2df3_mask, "__builtin_ia32_subpd128_mask", IX86_BUILTIN_SUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32201 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4df3_mask, "__builtin_ia32_subpd256_mask", IX86_BUILTIN_SUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32202 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4sf3_mask, "__builtin_ia32_subps128_mask", IX86_BUILTIN_SUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32203 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8sf3_mask, "__builtin_ia32_subps256_mask", IX86_BUILTIN_SUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32204 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4df3_mask, "__builtin_ia32_xorpd256_mask", IX86_BUILTIN_XORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32205 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2df3_mask, "__builtin_ia32_xorpd128_mask", IX86_BUILTIN_XORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32206 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8sf3_mask, "__builtin_ia32_xorps256_mask", IX86_BUILTIN_XORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32207 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4sf3_mask, "__builtin_ia32_xorps128_mask", IX86_BUILTIN_XORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32208 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4df3_mask, "__builtin_ia32_orpd256_mask", IX86_BUILTIN_ORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32209 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2df3_mask, "__builtin_ia32_orpd128_mask", IX86_BUILTIN_ORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32210 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8sf3_mask, "__builtin_ia32_orps256_mask", IX86_BUILTIN_ORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32211 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4sf3_mask, "__builtin_ia32_orps128_mask", IX86_BUILTIN_ORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32212 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8sf_mask, "__builtin_ia32_broadcastf32x2_256_mask", IX86_BUILTIN_BROADCASTF32x2_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32213 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8si_mask, "__builtin_ia32_broadcasti32x2_256_mask", IX86_BUILTIN_BROADCASTI32x2_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32214 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4si_mask, "__builtin_ia32_broadcasti32x2_128_mask", IX86_BUILTIN_BROADCASTI32x2_128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32215 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4df_mask_1, "__builtin_ia32_broadcastf64x2_256_mask", IX86_BUILTIN_BROADCASTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32216 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4di_mask_1, "__builtin_ia32_broadcasti64x2_256_mask", IX86_BUILTIN_BROADCASTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32217 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8sf_mask_1, "__builtin_ia32_broadcastf32x4_256_mask", IX86_BUILTIN_BROADCASTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32218 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8si_mask_1, "__builtin_ia32_broadcasti32x4_256_mask", IX86_BUILTIN_BROADCASTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32219 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_QI },
32220 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_QI },
32221 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv16hi_mask, "__builtin_ia32_dbpsadbw256_mask", IX86_BUILTIN_DBPSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI },
32222 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI },
32223 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32224 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32225 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32226 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32227 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32228 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32229 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32230 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2uqq128_mask", IX86_BUILTIN_CVTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32231 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin_ia32_cvtpd2udq256_mask", IX86_BUILTIN_CVTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32232 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32233 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32234 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32235 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32236 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32237 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32238 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32239 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32240 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2udq128_mask", IX86_BUILTIN_CVTTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32241 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2dq256_mask", IX86_BUILTIN_CVTTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32242 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvttpd2dq_mask, "__builtin_ia32_cvttpd2dq128_mask", IX86_BUILTIN_CVTTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32243 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2udq256_mask", IX86_BUILTIN_CVTTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32244 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2si2_mask, "__builtin_ia32_cvttpd2udq128_mask", IX86_BUILTIN_CVTTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32245 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2dq256_mask, "__builtin_ia32_cvtpd2dq256_mask", IX86_BUILTIN_CVTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32246 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2dq_mask, "__builtin_ia32_cvtpd2dq128_mask", IX86_BUILTIN_CVTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32247 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4df2_mask, "__builtin_ia32_cvtdq2pd256_mask", IX86_BUILTIN_CVTDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32248 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtdq2pd_mask, "__builtin_ia32_cvtdq2pd128_mask", IX86_BUILTIN_CVTDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32249 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4df2_mask, "__builtin_ia32_cvtudq2pd256_mask", IX86_BUILTIN_CVTUDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32250 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2siv2df2_mask, "__builtin_ia32_cvtudq2pd128_mask", IX86_BUILTIN_CVTUDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32251 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv8siv8sf2_mask, "__builtin_ia32_cvtdq2ps256_mask", IX86_BUILTIN_CVTDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32252 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4sf2_mask, "__builtin_ia32_cvtdq2ps128_mask", IX86_BUILTIN_CVTDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32253 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv8siv8sf2_mask, "__builtin_ia32_cvtudq2ps256_mask", IX86_BUILTIN_CVTUDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32254 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4sf2_mask, "__builtin_ia32_cvtudq2ps128_mask", IX86_BUILTIN_CVTUDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32255 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtps2pd256_mask, "__builtin_ia32_cvtps2pd256_mask", IX86_BUILTIN_CVTPS2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_QI },
32256 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtps2pd_mask, "__builtin_ia32_cvtps2pd128_mask", IX86_BUILTIN_CVTPS2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SF_V2DF_QI },
32257 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv32qi_mask, "__builtin_ia32_pbroadcastb256_mask", IX86_BUILTIN_PBROADCASTB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_SI },
32258 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv32qi_mask, "__builtin_ia32_pbroadcastb256_gpr_mask", IX86_BUILTIN_PBROADCASTB256_GPR_MASK, UNKNOWN, (int) V32QI_FTYPE_QI_V32QI_SI },
32259 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16qi_mask, "__builtin_ia32_pbroadcastb128_mask", IX86_BUILTIN_PBROADCASTB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32260 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16qi_mask, "__builtin_ia32_pbroadcastb128_gpr_mask", IX86_BUILTIN_PBROADCASTB128_GPR_MASK, UNKNOWN, (int) V16QI_FTYPE_QI_V16QI_HI },
32261 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16hi_mask, "__builtin_ia32_pbroadcastw256_mask", IX86_BUILTIN_PBROADCASTW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8HI_V16HI_HI },
32262 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16hi_mask, "__builtin_ia32_pbroadcastw256_gpr_mask", IX86_BUILTIN_PBROADCASTW256_GPR_MASK, UNKNOWN, (int) V16HI_FTYPE_HI_V16HI_HI },
32263 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8hi_mask, "__builtin_ia32_pbroadcastw128_mask", IX86_BUILTIN_PBROADCASTW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32264 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8hi_mask, "__builtin_ia32_pbroadcastw128_gpr_mask", IX86_BUILTIN_PBROADCASTW128_GPR_MASK, UNKNOWN, (int) V8HI_FTYPE_HI_V8HI_QI },
32265 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8si_mask, "__builtin_ia32_pbroadcastd256_mask", IX86_BUILTIN_PBROADCASTD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32266 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8si_mask, "__builtin_ia32_pbroadcastd256_gpr_mask", IX86_BUILTIN_PBROADCASTD256_GPR_MASK, UNKNOWN, (int) V8SI_FTYPE_SI_V8SI_QI },
32267 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4si_mask, "__builtin_ia32_pbroadcastd128_mask", IX86_BUILTIN_PBROADCASTD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32268 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4si_mask, "__builtin_ia32_pbroadcastd128_gpr_mask", IX86_BUILTIN_PBROADCASTD128_GPR_MASK, UNKNOWN, (int) V4SI_FTYPE_SI_V4SI_QI },
32269 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4di_mask, "__builtin_ia32_pbroadcastq256_mask", IX86_BUILTIN_PBROADCASTQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32270 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4di_mask, "__builtin_ia32_pbroadcastq256_gpr_mask", IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
32271 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv2di_mask, "__builtin_ia32_pbroadcastq128_mask", IX86_BUILTIN_PBROADCASTQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32272 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv2di_mask, "__builtin_ia32_pbroadcastq128_gpr_mask", IX86_BUILTIN_PBROADCASTQ128_GPR_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
32273 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8sf_mask, "__builtin_ia32_broadcastss256_mask", IX86_BUILTIN_BROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32274 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4sf_mask, "__builtin_ia32_broadcastss128_mask", IX86_BUILTIN_BROADCASTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32275 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4df_mask, "__builtin_ia32_broadcastsd256_mask", IX86_BUILTIN_BROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32276 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4df, "__builtin_ia32_extractf64x2_256_mask", IX86_BUILTIN_EXTRACTF64X2_256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT_V2DF_QI },
32277 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4di, "__builtin_ia32_extracti64x2_256_mask", IX86_BUILTIN_EXTRACTI64X2_256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT_V2DI_QI },
32278 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8sf, "__builtin_ia32_insertf32x4_256_mask", IX86_BUILTIN_INSERTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI },
32279 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8si, "__builtin_ia32_inserti32x4_256_mask", IX86_BUILTIN_INSERTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI },
32280 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv16qiv16hi2_mask, "__builtin_ia32_pmovsxbw256_mask", IX86_BUILTIN_PMOVSXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32281 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv8qiv8hi2_mask, "__builtin_ia32_pmovsxbw128_mask", IX86_BUILTIN_PMOVSXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32282 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8qiv8si2_mask, "__builtin_ia32_pmovsxbd256_mask", IX86_BUILTIN_PMOVSXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32283 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4qiv4si2_mask, "__builtin_ia32_pmovsxbd128_mask", IX86_BUILTIN_PMOVSXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32284 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4qiv4di2_mask, "__builtin_ia32_pmovsxbq256_mask", IX86_BUILTIN_PMOVSXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32285 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2qiv2di2_mask, "__builtin_ia32_pmovsxbq128_mask", IX86_BUILTIN_PMOVSXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32286 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8hiv8si2_mask, "__builtin_ia32_pmovsxwd256_mask", IX86_BUILTIN_PMOVSXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32287 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4hiv4si2_mask, "__builtin_ia32_pmovsxwd128_mask", IX86_BUILTIN_PMOVSXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32288 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4hiv4di2_mask, "__builtin_ia32_pmovsxwq256_mask", IX86_BUILTIN_PMOVSXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32289 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2hiv2di2_mask, "__builtin_ia32_pmovsxwq128_mask", IX86_BUILTIN_PMOVSXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32290 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4siv4di2_mask, "__builtin_ia32_pmovsxdq256_mask", IX86_BUILTIN_PMOVSXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32291 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2siv2di2_mask, "__builtin_ia32_pmovsxdq128_mask", IX86_BUILTIN_PMOVSXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32292 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv16qiv16hi2_mask, "__builtin_ia32_pmovzxbw256_mask", IX86_BUILTIN_PMOVZXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32293 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv8qiv8hi2_mask, "__builtin_ia32_pmovzxbw128_mask", IX86_BUILTIN_PMOVZXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32294 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8qiv8si2_mask, "__builtin_ia32_pmovzxbd256_mask", IX86_BUILTIN_PMOVZXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32295 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4qiv4si2_mask, "__builtin_ia32_pmovzxbd128_mask", IX86_BUILTIN_PMOVZXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32296 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4qiv4di2_mask, "__builtin_ia32_pmovzxbq256_mask", IX86_BUILTIN_PMOVZXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32297 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2qiv2di2_mask, "__builtin_ia32_pmovzxbq128_mask", IX86_BUILTIN_PMOVZXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32298 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8hiv8si2_mask, "__builtin_ia32_pmovzxwd256_mask", IX86_BUILTIN_PMOVZXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32299 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4hiv4si2_mask, "__builtin_ia32_pmovzxwd128_mask", IX86_BUILTIN_PMOVZXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32300 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4hiv4di2_mask, "__builtin_ia32_pmovzxwq256_mask", IX86_BUILTIN_PMOVZXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32301 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2hiv2di2_mask, "__builtin_ia32_pmovzxwq128_mask", IX86_BUILTIN_PMOVZXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32302 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4siv4di2_mask, "__builtin_ia32_pmovzxdq256_mask", IX86_BUILTIN_PMOVZXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32303 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2siv2di2_mask, "__builtin_ia32_pmovzxdq128_mask", IX86_BUILTIN_PMOVZXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32304 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4df_mask, "__builtin_ia32_reducepd256_mask", IX86_BUILTIN_REDUCEPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32305 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv2df_mask, "__builtin_ia32_reducepd128_mask", IX86_BUILTIN_REDUCEPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32306 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv8sf_mask, "__builtin_ia32_reduceps256_mask", IX86_BUILTIN_REDUCEPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32307 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4sf_mask, "__builtin_ia32_reduceps128_mask", IX86_BUILTIN_REDUCEPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32308 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv2df, "__builtin_ia32_reducesd", IX86_BUILTIN_REDUCESD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32309 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv4sf, "__builtin_ia32_reducess", IX86_BUILTIN_REDUCESS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32310 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32311 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32312 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32313 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32314 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32315 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32316 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32317 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32318 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32319 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v2df_mask, "__builtin_ia32_rcp14pd128_mask", IX86_BUILTIN_RCP14PD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32320 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v8sf_mask, "__builtin_ia32_rcp14ps256_mask", IX86_BUILTIN_RCP14PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32321 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4sf_mask, "__builtin_ia32_rcp14ps128_mask", IX86_BUILTIN_RCP14PS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32322 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4df_mask, "__builtin_ia32_rsqrt14pd256_mask", IX86_BUILTIN_RSQRT14PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32323 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v2df_mask, "__builtin_ia32_rsqrt14pd128_mask", IX86_BUILTIN_RSQRT14PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32324 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v8sf_mask, "__builtin_ia32_rsqrt14ps256_mask", IX86_BUILTIN_RSQRT14PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32325 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4sf_mask, "__builtin_ia32_rsqrt14ps128_mask", IX86_BUILTIN_RSQRT14PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32326 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv4df2_mask, "__builtin_ia32_sqrtpd256_mask", IX86_BUILTIN_SQRTPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32327 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sqrtv2df2_mask, "__builtin_ia32_sqrtpd128_mask", IX86_BUILTIN_SQRTPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32328 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv8sf2_mask, "__builtin_ia32_sqrtps256_mask", IX86_BUILTIN_SQRTPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32329 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_sqrtv4sf2_mask, "__builtin_ia32_sqrtps128_mask", IX86_BUILTIN_SQRTPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32330 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16qi3_mask, "__builtin_ia32_paddb128_mask", IX86_BUILTIN_PADDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32331 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8hi3_mask, "__builtin_ia32_paddw128_mask", IX86_BUILTIN_PADDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32332 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4si3_mask, "__builtin_ia32_paddd128_mask", IX86_BUILTIN_PADDD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32333 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2di3_mask, "__builtin_ia32_paddq128_mask", IX86_BUILTIN_PADDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32334 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16qi3_mask, "__builtin_ia32_psubb128_mask", IX86_BUILTIN_PSUBB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32335 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8hi3_mask, "__builtin_ia32_psubw128_mask", IX86_BUILTIN_PSUBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32336 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4si3_mask, "__builtin_ia32_psubd128_mask", IX86_BUILTIN_PSUBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32337 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2di3_mask, "__builtin_ia32_psubq128_mask", IX86_BUILTIN_PSUBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32338 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv16qi3_mask, "__builtin_ia32_paddsb128_mask", IX86_BUILTIN_PADDSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32339 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv8hi3_mask, "__builtin_ia32_paddsw128_mask", IX86_BUILTIN_PADDSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32340 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv16qi3_mask, "__builtin_ia32_psubsb128_mask", IX86_BUILTIN_PSUBSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32341 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv8hi3_mask, "__builtin_ia32_psubsw128_mask", IX86_BUILTIN_PSUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32342 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv16qi3_mask, "__builtin_ia32_paddusb128_mask", IX86_BUILTIN_PADDUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32343 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv8hi3_mask, "__builtin_ia32_paddusw128_mask", IX86_BUILTIN_PADDUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32344 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv16qi3_mask, "__builtin_ia32_psubusb128_mask", IX86_BUILTIN_PSUBUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32345 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv8hi3_mask, "__builtin_ia32_psubusw128_mask", IX86_BUILTIN_PSUBUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32346 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv32qi3_mask, "__builtin_ia32_paddb256_mask", IX86_BUILTIN_PADDB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32347 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16hi3_mask, "__builtin_ia32_paddw256_mask", IX86_BUILTIN_PADDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32348 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8si3_mask, "__builtin_ia32_paddd256_mask", IX86_BUILTIN_PADDD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32349 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4di3_mask, "__builtin_ia32_paddq256_mask", IX86_BUILTIN_PADDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32350 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv32qi3_mask, "__builtin_ia32_paddsb256_mask", IX86_BUILTIN_PADDSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32351 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv16hi3_mask, "__builtin_ia32_paddsw256_mask", IX86_BUILTIN_PADDSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32352 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv32qi3_mask, "__builtin_ia32_paddusb256_mask", IX86_BUILTIN_PADDUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32353 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv16hi3_mask, "__builtin_ia32_paddusw256_mask", IX86_BUILTIN_PADDUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32354 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv32qi3_mask, "__builtin_ia32_psubb256_mask", IX86_BUILTIN_PSUBB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32355 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16hi3_mask, "__builtin_ia32_psubw256_mask", IX86_BUILTIN_PSUBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32356 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8si3_mask, "__builtin_ia32_psubd256_mask", IX86_BUILTIN_PSUBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32357 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4di3_mask, "__builtin_ia32_psubq256_mask", IX86_BUILTIN_PSUBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32358 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv32qi3_mask, "__builtin_ia32_psubsb256_mask", IX86_BUILTIN_PSUBSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32359 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv16hi3_mask, "__builtin_ia32_psubsw256_mask", IX86_BUILTIN_PSUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32360 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv32qi3_mask, "__builtin_ia32_psubusb256_mask", IX86_BUILTIN_PSUBUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32361 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv16hi3_mask, "__builtin_ia32_psubusw256_mask", IX86_BUILTIN_PSUBUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32362 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_256_mask", IX86_BUILTIN_SHUF_F64x2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32363 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_256_mask", IX86_BUILTIN_SHUF_I64x2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32364 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_256_mask", IX86_BUILTIN_SHUF_I32x4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32365 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_256_mask", IX86_BUILTIN_SHUF_F32x4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32366 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovwb128_mask", IX86_BUILTIN_PMOVWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32367 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovwb256_mask", IX86_BUILTIN_PMOVWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32368 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovswb128_mask", IX86_BUILTIN_PMOVSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32369 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovswb256_mask", IX86_BUILTIN_PMOVSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32370 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovuswb128_mask", IX86_BUILTIN_PMOVUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32371 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovuswb256_mask", IX86_BUILTIN_PMOVUSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32372 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask, "__builtin_ia32_pmovdb128_mask", IX86_BUILTIN_PMOVDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32373 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask, "__builtin_ia32_pmovdb256_mask", IX86_BUILTIN_PMOVDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32374 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask, "__builtin_ia32_pmovsdb128_mask", IX86_BUILTIN_PMOVSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32375 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask, "__builtin_ia32_pmovsdb256_mask", IX86_BUILTIN_PMOVSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32376 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask, "__builtin_ia32_pmovusdb128_mask", IX86_BUILTIN_PMOVUSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32377 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask, "__builtin_ia32_pmovusdb256_mask", IX86_BUILTIN_PMOVUSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32378 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask, "__builtin_ia32_pmovdw128_mask", IX86_BUILTIN_PMOVDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32379 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask, "__builtin_ia32_pmovdw256_mask", IX86_BUILTIN_PMOVDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32380 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask, "__builtin_ia32_pmovsdw128_mask", IX86_BUILTIN_PMOVSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32381 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask, "__builtin_ia32_pmovsdw256_mask", IX86_BUILTIN_PMOVSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32382 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask, "__builtin_ia32_pmovusdw128_mask", IX86_BUILTIN_PMOVUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32383 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask, "__builtin_ia32_pmovusdw256_mask", IX86_BUILTIN_PMOVUSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32384 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask, "__builtin_ia32_pmovqb128_mask", IX86_BUILTIN_PMOVQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32385 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask, "__builtin_ia32_pmovqb256_mask", IX86_BUILTIN_PMOVQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32386 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask, "__builtin_ia32_pmovsqb128_mask", IX86_BUILTIN_PMOVSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32387 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask, "__builtin_ia32_pmovsqb256_mask", IX86_BUILTIN_PMOVSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32388 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask, "__builtin_ia32_pmovusqb128_mask", IX86_BUILTIN_PMOVUSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32389 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask, "__builtin_ia32_pmovusqb256_mask", IX86_BUILTIN_PMOVUSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32390 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask, "__builtin_ia32_pmovqw128_mask", IX86_BUILTIN_PMOVQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32391 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask, "__builtin_ia32_pmovqw256_mask", IX86_BUILTIN_PMOVQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32392 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask, "__builtin_ia32_pmovsqw128_mask", IX86_BUILTIN_PMOVSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32393 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask, "__builtin_ia32_pmovsqw256_mask", IX86_BUILTIN_PMOVSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32394 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask, "__builtin_ia32_pmovusqw128_mask", IX86_BUILTIN_PMOVUSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32395 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask, "__builtin_ia32_pmovusqw256_mask", IX86_BUILTIN_PMOVUSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32396 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask, "__builtin_ia32_pmovqd128_mask", IX86_BUILTIN_PMOVQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32397 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask, "__builtin_ia32_pmovqd256_mask", IX86_BUILTIN_PMOVQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32398 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask, "__builtin_ia32_pmovsqd128_mask", IX86_BUILTIN_PMOVSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32399 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask, "__builtin_ia32_pmovsqd256_mask", IX86_BUILTIN_PMOVSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32400 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask, "__builtin_ia32_pmovusqd128_mask", IX86_BUILTIN_PMOVUSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32401 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask, "__builtin_ia32_pmovusqd256_mask", IX86_BUILTIN_PMOVUSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32402 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4df_mask, "__builtin_ia32_rangepd256_mask", IX86_BUILTIN_RANGEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32403 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv2df_mask, "__builtin_ia32_rangepd128_mask", IX86_BUILTIN_RANGEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32404 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv8sf_mask, "__builtin_ia32_rangeps256_mask", IX86_BUILTIN_RANGEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32405 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4sf_mask, "__builtin_ia32_rangeps128_mask", IX86_BUILTIN_RANGEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32406 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv8sf_mask, "__builtin_ia32_getexpps256_mask", IX86_BUILTIN_GETEXPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32407 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4df_mask, "__builtin_ia32_getexppd256_mask", IX86_BUILTIN_GETEXPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32408 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4sf_mask, "__builtin_ia32_getexpps128_mask", IX86_BUILTIN_GETEXPPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32409 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv2df_mask, "__builtin_ia32_getexppd128_mask", IX86_BUILTIN_GETEXPPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32410 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_mask, "__builtin_ia32_fixupimmpd256_mask", IX86_BUILTIN_FIXUPIMMPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32411 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_maskz, "__builtin_ia32_fixupimmpd256_maskz", IX86_BUILTIN_FIXUPIMMPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32412 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_mask, "__builtin_ia32_fixupimmps256_mask", IX86_BUILTIN_FIXUPIMMPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32413 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_maskz, "__builtin_ia32_fixupimmps256_maskz", IX86_BUILTIN_FIXUPIMMPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32414 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_mask, "__builtin_ia32_fixupimmpd128_mask", IX86_BUILTIN_FIXUPIMMPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32415 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_maskz, "__builtin_ia32_fixupimmpd128_maskz", IX86_BUILTIN_FIXUPIMMPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32416 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_mask, "__builtin_ia32_fixupimmps128_mask", IX86_BUILTIN_FIXUPIMMPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32417 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_maskz, "__builtin_ia32_fixupimmps128_maskz", IX86_BUILTIN_FIXUPIMMPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32418 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4di2_mask, "__builtin_ia32_pabsq256_mask", IX86_BUILTIN_PABSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32419 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv2di2_mask, "__builtin_ia32_pabsq128_mask", IX86_BUILTIN_PABSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32420 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8si2_mask, "__builtin_ia32_pabsd256_mask", IX86_BUILTIN_PABSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32421 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4si2_mask, "__builtin_ia32_pabsd128_mask", IX86_BUILTIN_PABSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32422 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pmulhrswv16hi3_mask , "__builtin_ia32_pmulhrsw256_mask", IX86_BUILTIN_PMULHRSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32423 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pmulhrswv8hi3_mask, "__builtin_ia32_pmulhrsw128_mask", IX86_BUILTIN_PMULHRSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32424 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv8hi3_highpart_mask, "__builtin_ia32_pmulhuw128_mask", IX86_BUILTIN_PMULHUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32425 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv16hi3_highpart_mask, "__builtin_ia32_pmulhuw256_mask" , IX86_BUILTIN_PMULHUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32426 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv16hi3_highpart_mask, "__builtin_ia32_pmulhw256_mask" , IX86_BUILTIN_PMULHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32427 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv8hi3_highpart_mask, "__builtin_ia32_pmulhw128_mask", IX86_BUILTIN_PMULHW128_MASK, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32428 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv16hi3_mask, "__builtin_ia32_pmullw256_mask" , IX86_BUILTIN_PMULLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32429 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8hi3_mask, "__builtin_ia32_pmullw128_mask", IX86_BUILTIN_PMULLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32430 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv4di3_mask, "__builtin_ia32_pmullq256_mask", IX86_BUILTIN_PMULLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32431 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv2di3_mask, "__builtin_ia32_pmullq128_mask", IX86_BUILTIN_PMULLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32432 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4df3_mask, "__builtin_ia32_andpd256_mask", IX86_BUILTIN_ANDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32433 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2df3_mask, "__builtin_ia32_andpd128_mask", IX86_BUILTIN_ANDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32434 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8sf3_mask, "__builtin_ia32_andps256_mask", IX86_BUILTIN_ANDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32435 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4sf3_mask, "__builtin_ia32_andps128_mask", IX86_BUILTIN_ANDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32436 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv4df3_mask, "__builtin_ia32_andnpd256_mask", IX86_BUILTIN_ANDNPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32437 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2df3_mask, "__builtin_ia32_andnpd128_mask", IX86_BUILTIN_ANDNPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32438 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv8sf3_mask, "__builtin_ia32_andnps256_mask", IX86_BUILTIN_ANDNPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32439 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_andnotv4sf3_mask, "__builtin_ia32_andnps128_mask", IX86_BUILTIN_ANDNPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32440 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllwi128_mask", IX86_BUILTIN_PSLLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32441 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslldi128_mask", IX86_BUILTIN_PSLLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32442 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllqi128_mask", IX86_BUILTIN_PSLLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32443 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllw128_mask", IX86_BUILTIN_PSLLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32444 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslld128_mask", IX86_BUILTIN_PSLLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32445 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllq128_mask", IX86_BUILTIN_PSLLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32446 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllwi256_mask", IX86_BUILTIN_PSLLWI256_MASK , UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32447 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllw256_mask", IX86_BUILTIN_PSLLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32448 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslldi256_mask", IX86_BUILTIN_PSLLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32449 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslld256_mask", IX86_BUILTIN_PSLLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32450 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllqi256_mask", IX86_BUILTIN_PSLLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32451 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllq256_mask", IX86_BUILTIN_PSLLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32452 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psradi128_mask", IX86_BUILTIN_PSRADI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32453 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psrad128_mask", IX86_BUILTIN_PSRAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32454 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psradi256_mask", IX86_BUILTIN_PSRADI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32455 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psrad256_mask", IX86_BUILTIN_PSRAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32456 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraqi128_mask", IX86_BUILTIN_PSRAQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32457 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraq128_mask", IX86_BUILTIN_PSRAQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32458 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraqi256_mask", IX86_BUILTIN_PSRAQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32459 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraq256_mask", IX86_BUILTIN_PSRAQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32460 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8si3_mask, "__builtin_ia32_pandd256_mask", IX86_BUILTIN_PANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32461 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4si3_mask, "__builtin_ia32_pandd128_mask", IX86_BUILTIN_PANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32462 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrldi128_mask", IX86_BUILTIN_PSRLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32463 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrld128_mask", IX86_BUILTIN_PSRLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32464 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrldi256_mask", IX86_BUILTIN_PSRLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32465 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrld256_mask", IX86_BUILTIN_PSRLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32466 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlqi128_mask", IX86_BUILTIN_PSRLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32467 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlq128_mask", IX86_BUILTIN_PSRLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32468 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlqi256_mask", IX86_BUILTIN_PSRLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32469 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlq256_mask", IX86_BUILTIN_PSRLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32470 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4di3_mask, "__builtin_ia32_pandq256_mask", IX86_BUILTIN_PANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32471 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2di3_mask, "__builtin_ia32_pandq128_mask", IX86_BUILTIN_PANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32472 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv8si3_mask, "__builtin_ia32_pandnd256_mask", IX86_BUILTIN_PANDND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32473 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv4si3_mask, "__builtin_ia32_pandnd128_mask", IX86_BUILTIN_PANDND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32474 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv4di3_mask, "__builtin_ia32_pandnq256_mask", IX86_BUILTIN_PANDNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32475 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2di3_mask, "__builtin_ia32_pandnq128_mask", IX86_BUILTIN_PANDNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32476 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8si3_mask, "__builtin_ia32_pord256_mask", IX86_BUILTIN_PORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32477 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4si3_mask, "__builtin_ia32_pord128_mask", IX86_BUILTIN_PORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32478 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4di3_mask, "__builtin_ia32_porq256_mask", IX86_BUILTIN_PORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32479 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2di3_mask, "__builtin_ia32_porq128_mask", IX86_BUILTIN_PORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32480 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8si3_mask, "__builtin_ia32_pxord256_mask", IX86_BUILTIN_PXORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32481 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4si3_mask, "__builtin_ia32_pxord128_mask", IX86_BUILTIN_PXORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32482 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4di3_mask, "__builtin_ia32_pxorq256_mask", IX86_BUILTIN_PXORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32483 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2di3_mask, "__builtin_ia32_pxorq128_mask", IX86_BUILTIN_PXORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32484 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packsswb_mask, "__builtin_ia32_packsswb256_mask", IX86_BUILTIN_PACKSSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32485 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packsswb_mask, "__builtin_ia32_packsswb128_mask", IX86_BUILTIN_PACKSSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32486 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packuswb_mask, "__builtin_ia32_packuswb256_mask", IX86_BUILTIN_PACKUSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32487 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packuswb_mask, "__builtin_ia32_packuswb128_mask", IX86_BUILTIN_PACKUSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32488 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev8sf_mask, "__builtin_ia32_rndscaleps_256_mask", IX86_BUILTIN_RNDSCALEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32489 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4df_mask, "__builtin_ia32_rndscalepd_256_mask", IX86_BUILTIN_RNDSCALEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32490 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4sf_mask, "__builtin_ia32_rndscaleps_128_mask", IX86_BUILTIN_RNDSCALEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32491 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev2df_mask, "__builtin_ia32_rndscalepd_128_mask", IX86_BUILTIN_RNDSCALEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32492 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_mask, "__builtin_ia32_pternlogq256_mask", IX86_BUILTIN_VTERNLOGQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32493 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_maskz, "__builtin_ia32_pternlogq256_maskz", IX86_BUILTIN_VTERNLOGQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32494 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_mask, "__builtin_ia32_pternlogd256_mask", IX86_BUILTIN_VTERNLOGD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32495 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_maskz, "__builtin_ia32_pternlogd256_maskz", IX86_BUILTIN_VTERNLOGD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32496 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_mask, "__builtin_ia32_pternlogq128_mask", IX86_BUILTIN_VTERNLOGQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32497 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_maskz, "__builtin_ia32_pternlogq128_maskz", IX86_BUILTIN_VTERNLOGQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32498 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_mask, "__builtin_ia32_pternlogd128_mask", IX86_BUILTIN_VTERNLOGD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32499 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_maskz, "__builtin_ia32_pternlogd128_maskz", IX86_BUILTIN_VTERNLOGD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32500 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4df_mask, "__builtin_ia32_scalefpd256_mask", IX86_BUILTIN_SCALEFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32501 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv8sf_mask, "__builtin_ia32_scalefps256_mask", IX86_BUILTIN_SCALEFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32502 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv2df_mask, "__builtin_ia32_scalefpd128_mask", IX86_BUILTIN_SCALEFPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32503 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4sf_mask, "__builtin_ia32_scalefps128_mask", IX86_BUILTIN_SCALEFPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32504 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask, "__builtin_ia32_vfmaddpd256_mask", IX86_BUILTIN_VFMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32505 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask3, "__builtin_ia32_vfmaddpd256_mask3", IX86_BUILTIN_VFMADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32506 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_maskz, "__builtin_ia32_vfmaddpd256_maskz", IX86_BUILTIN_VFMADDPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32507 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask, "__builtin_ia32_vfmaddpd128_mask", IX86_BUILTIN_VFMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32508 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask3, "__builtin_ia32_vfmaddpd128_mask3", IX86_BUILTIN_VFMADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32509 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_maskz, "__builtin_ia32_vfmaddpd128_maskz", IX86_BUILTIN_VFMADDPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32510 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask, "__builtin_ia32_vfmaddps256_mask", IX86_BUILTIN_VFMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32511 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask3, "__builtin_ia32_vfmaddps256_mask3", IX86_BUILTIN_VFMADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32512 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_maskz, "__builtin_ia32_vfmaddps256_maskz", IX86_BUILTIN_VFMADDPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32513 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask, "__builtin_ia32_vfmaddps128_mask", IX86_BUILTIN_VFMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32514 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask3, "__builtin_ia32_vfmaddps128_mask3", IX86_BUILTIN_VFMADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32515 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_maskz, "__builtin_ia32_vfmaddps128_maskz", IX86_BUILTIN_VFMADDPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32516 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4df_mask3, "__builtin_ia32_vfmsubpd256_mask3", IX86_BUILTIN_VFMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32517 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v2df_mask3, "__builtin_ia32_vfmsubpd128_mask3", IX86_BUILTIN_VFMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32518 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v8sf_mask3, "__builtin_ia32_vfmsubps256_mask3", IX86_BUILTIN_VFMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32519 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4sf_mask3, "__builtin_ia32_vfmsubps128_mask3", IX86_BUILTIN_VFMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32520 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4df_mask, "__builtin_ia32_vfnmaddpd256_mask", IX86_BUILTIN_VFNMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32521 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v2df_mask, "__builtin_ia32_vfnmaddpd128_mask", IX86_BUILTIN_VFNMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32522 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v8sf_mask, "__builtin_ia32_vfnmaddps256_mask", IX86_BUILTIN_VFNMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32523 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4sf_mask, "__builtin_ia32_vfnmaddps128_mask", IX86_BUILTIN_VFNMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32524 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask, "__builtin_ia32_vfnmsubpd256_mask", IX86_BUILTIN_VFNMSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32525 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask3, "__builtin_ia32_vfnmsubpd256_mask3", IX86_BUILTIN_VFNMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32526 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask, "__builtin_ia32_vfnmsubpd128_mask", IX86_BUILTIN_VFNMSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32527 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask3, "__builtin_ia32_vfnmsubpd128_mask3", IX86_BUILTIN_VFNMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32528 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask, "__builtin_ia32_vfnmsubps256_mask", IX86_BUILTIN_VFNMSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32529 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask3, "__builtin_ia32_vfnmsubps256_mask3", IX86_BUILTIN_VFNMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32530 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask, "__builtin_ia32_vfnmsubps128_mask", IX86_BUILTIN_VFNMSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32531 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask3, "__builtin_ia32_vfnmsubps128_mask3", IX86_BUILTIN_VFNMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32532 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask, "__builtin_ia32_vfmaddsubpd256_mask", IX86_BUILTIN_VFMADDSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32533 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask3, "__builtin_ia32_vfmaddsubpd256_mask3", IX86_BUILTIN_VFMADDSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32534 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_maskz, "__builtin_ia32_vfmaddsubpd256_maskz", IX86_BUILTIN_VFMADDSUBPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32535 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask, "__builtin_ia32_vfmaddsubpd128_mask", IX86_BUILTIN_VFMADDSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32536 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask3, "__builtin_ia32_vfmaddsubpd128_mask3", IX86_BUILTIN_VFMADDSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32537 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_maskz, "__builtin_ia32_vfmaddsubpd128_maskz", IX86_BUILTIN_VFMADDSUBPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32538 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask, "__builtin_ia32_vfmaddsubps256_mask", IX86_BUILTIN_VFMADDSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32539 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask3, "__builtin_ia32_vfmaddsubps256_mask3", IX86_BUILTIN_VFMADDSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32540 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_maskz, "__builtin_ia32_vfmaddsubps256_maskz", IX86_BUILTIN_VFMADDSUBPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32541 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask, "__builtin_ia32_vfmaddsubps128_mask", IX86_BUILTIN_VFMADDSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32542 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask3, "__builtin_ia32_vfmaddsubps128_mask3", IX86_BUILTIN_VFMADDSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32543 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_maskz, "__builtin_ia32_vfmaddsubps128_maskz", IX86_BUILTIN_VFMADDSUBPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32544 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4df_mask3, "__builtin_ia32_vfmsubaddpd256_mask3", IX86_BUILTIN_VFMSUBADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32545 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v2df_mask3, "__builtin_ia32_vfmsubaddpd128_mask3", IX86_BUILTIN_VFMSUBADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32546 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3, "__builtin_ia32_vfmsubaddps256_mask3", IX86_BUILTIN_VFMSUBADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32547 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4sf_mask3, "__builtin_ia32_vfmsubaddps128_mask3", IX86_BUILTIN_VFMSUBADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32548 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4df, "__builtin_ia32_insertf64x2_256_mask", IX86_BUILTIN_INSERTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI },
32549 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4di, "__builtin_ia32_inserti64x2_256_mask", IX86_BUILTIN_INSERTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI },
32550 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv16hi_mask, "__builtin_ia32_psrav16hi_mask", IX86_BUILTIN_PSRAVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32551 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv8hi_mask, "__builtin_ia32_psrav8hi_mask", IX86_BUILTIN_PSRAVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32552 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v16hi_mask, "__builtin_ia32_pmaddubsw256_mask", IX86_BUILTIN_PMADDUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_V16HI_HI },
32553 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v8hi_mask, "__builtin_ia32_pmaddubsw128_mask", IX86_BUILTIN_PMADDUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_V8HI_QI },
32554 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v16hi_mask, "__builtin_ia32_pmaddwd256_mask", IX86_BUILTIN_PMADDWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI_V8SI_QI },
32555 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v8hi_mask, "__builtin_ia32_pmaddwd128_mask", IX86_BUILTIN_PMADDWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI_V4SI_QI },
32556 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv16hi_mask, "__builtin_ia32_psrlv16hi_mask", IX86_BUILTIN_PSRLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32557 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv8hi_mask, "__builtin_ia32_psrlv8hi_mask", IX86_BUILTIN_PSRLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32558 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_fix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2dq256_mask", IX86_BUILTIN_CVTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32559 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_fix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2dq128_mask", IX86_BUILTIN_CVTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32560 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2udq256_mask", IX86_BUILTIN_CVTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32561 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2udq128_mask", IX86_BUILTIN_CVTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32562 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv4di_mask, "__builtin_ia32_cvtps2qq256_mask", IX86_BUILTIN_CVTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32563 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv2di_mask, "__builtin_ia32_cvtps2qq128_mask", IX86_BUILTIN_CVTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32564 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv4di_mask, "__builtin_ia32_cvtps2uqq256_mask", IX86_BUILTIN_CVTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32565 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv2di_mask, "__builtin_ia32_cvtps2uqq128_mask", IX86_BUILTIN_CVTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32566 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv8sf_mask, "__builtin_ia32_getmantps256_mask", IX86_BUILTIN_GETMANTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32567 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4sf_mask, "__builtin_ia32_getmantps128_mask", IX86_BUILTIN_GETMANTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32568 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4df_mask, "__builtin_ia32_getmantpd256_mask", IX86_BUILTIN_GETMANTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32569 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv2df_mask, "__builtin_ia32_getmantpd128_mask", IX86_BUILTIN_GETMANTPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32570 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movddup256_mask, "__builtin_ia32_movddup256_mask", IX86_BUILTIN_MOVDDUP256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32571 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_dupv2df_mask, "__builtin_ia32_movddup128_mask", IX86_BUILTIN_MOVDDUP128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32572 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movshdup256_mask, "__builtin_ia32_movshdup256_mask", IX86_BUILTIN_MOVSHDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32573 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movshdup_mask, "__builtin_ia32_movshdup128_mask", IX86_BUILTIN_MOVSHDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32574 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_movsldup256_mask", IX86_BUILTIN_MOVSLDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32575 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32576 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32577 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32578 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32579 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32580 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32581 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32582 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32583 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32584 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32585 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32586 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32587 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_maskz, "__builtin_ia32_vpermt2vard256_maskz", IX86_BUILTIN_VPERMT2VARD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32588 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4di3_mask, "__builtin_ia32_vpermi2varq256_mask", IX86_BUILTIN_VPERMI2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32589 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8si3_mask, "__builtin_ia32_vpermi2vard256_mask", IX86_BUILTIN_VPERMI2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32590 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_mask, "__builtin_ia32_vpermt2varpd256_mask", IX86_BUILTIN_VPERMT2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32591 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_maskz, "__builtin_ia32_vpermt2varpd256_maskz", IX86_BUILTIN_VPERMT2VARPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32592 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_mask, "__builtin_ia32_vpermt2varps256_mask", IX86_BUILTIN_VPERMT2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32593 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_maskz, "__builtin_ia32_vpermt2varps256_maskz", IX86_BUILTIN_VPERMT2VARPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32594 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4df3_mask, "__builtin_ia32_vpermi2varpd256_mask", IX86_BUILTIN_VPERMI2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32595 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8sf3_mask, "__builtin_ia32_vpermi2varps256_mask", IX86_BUILTIN_VPERMI2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32596 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_mask, "__builtin_ia32_vpermt2varq128_mask", IX86_BUILTIN_VPERMT2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32597 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_maskz, "__builtin_ia32_vpermt2varq128_maskz", IX86_BUILTIN_VPERMT2VARQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32598 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_mask, "__builtin_ia32_vpermt2vard128_mask", IX86_BUILTIN_VPERMT2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32599 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_maskz, "__builtin_ia32_vpermt2vard128_maskz", IX86_BUILTIN_VPERMT2VARD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32600 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2di3_mask, "__builtin_ia32_vpermi2varq128_mask", IX86_BUILTIN_VPERMI2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32601 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4si3_mask, "__builtin_ia32_vpermi2vard128_mask", IX86_BUILTIN_VPERMI2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32602 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_mask, "__builtin_ia32_vpermt2varpd128_mask", IX86_BUILTIN_VPERMT2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32603 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_maskz, "__builtin_ia32_vpermt2varpd128_maskz", IX86_BUILTIN_VPERMT2VARPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32604 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_mask, "__builtin_ia32_vpermt2varps128_mask", IX86_BUILTIN_VPERMT2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32605 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_maskz, "__builtin_ia32_vpermt2varps128_maskz", IX86_BUILTIN_VPERMT2VARPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32606 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2df3_mask, "__builtin_ia32_vpermi2varpd128_mask", IX86_BUILTIN_VPERMI2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32607 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4sf3_mask, "__builtin_ia32_vpermi2varps128_mask", IX86_BUILTIN_VPERMI2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32608 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pshufbv32qi3_mask, "__builtin_ia32_pshufb256_mask", IX86_BUILTIN_PSHUFB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32609 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pshufbv16qi3_mask, "__builtin_ia32_pshufb128_mask", IX86_BUILTIN_PSHUFB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32610 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhwv3_mask, "__builtin_ia32_pshufhw256_mask", IX86_BUILTIN_PSHUFHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32611 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhw_mask, "__builtin_ia32_pshufhw128_mask", IX86_BUILTIN_PSHUFHW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32612 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflwv3_mask, "__builtin_ia32_pshuflw256_mask", IX86_BUILTIN_PSHUFLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32613 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflw_mask, "__builtin_ia32_pshuflw128_mask", IX86_BUILTIN_PSHUFLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32614 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufdv3_mask, "__builtin_ia32_pshufd256_mask", IX86_BUILTIN_PSHUFD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32615 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufd_mask, "__builtin_ia32_pshufd128_mask", IX86_BUILTIN_PSHUFD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32616 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufpd256_mask, "__builtin_ia32_shufpd256_mask", IX86_BUILTIN_SHUFPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32617 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_shufpd_mask, "__builtin_ia32_shufpd128_mask", IX86_BUILTIN_SHUFPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32618 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufps256_mask, "__builtin_ia32_shufps256_mask", IX86_BUILTIN_SHUFPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32619 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_shufps_mask, "__builtin_ia32_shufps128_mask", IX86_BUILTIN_SHUFPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32620 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4di_mask, "__builtin_ia32_prolvq256_mask", IX86_BUILTIN_PROLVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32621 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv2di_mask, "__builtin_ia32_prolvq128_mask", IX86_BUILTIN_PROLVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32622 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4di_mask, "__builtin_ia32_prolq256_mask", IX86_BUILTIN_PROLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32623 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv2di_mask, "__builtin_ia32_prolq128_mask", IX86_BUILTIN_PROLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32624 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4di_mask, "__builtin_ia32_prorvq256_mask", IX86_BUILTIN_PRORVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32625 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv2di_mask, "__builtin_ia32_prorvq128_mask", IX86_BUILTIN_PRORVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32626 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4di_mask, "__builtin_ia32_prorq256_mask", IX86_BUILTIN_PRORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32627 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv2di_mask, "__builtin_ia32_prorq128_mask", IX86_BUILTIN_PRORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32628 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv2di_mask, "__builtin_ia32_psravq128_mask", IX86_BUILTIN_PSRAVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32629 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4di_mask, "__builtin_ia32_psravq256_mask", IX86_BUILTIN_PSRAVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32630 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4di_mask, "__builtin_ia32_psllv4di_mask", IX86_BUILTIN_PSLLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32631 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv2di_mask, "__builtin_ia32_psllv2di_mask", IX86_BUILTIN_PSLLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32632 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv8si_mask, "__builtin_ia32_psllv8si_mask", IX86_BUILTIN_PSLLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32633 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4si_mask, "__builtin_ia32_psllv4si_mask", IX86_BUILTIN_PSLLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32634 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv8si_mask, "__builtin_ia32_psrav8si_mask", IX86_BUILTIN_PSRAVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32635 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4si_mask, "__builtin_ia32_psrav4si_mask", IX86_BUILTIN_PSRAVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32636 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4di_mask, "__builtin_ia32_psrlv4di_mask", IX86_BUILTIN_PSRLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32637 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv2di_mask, "__builtin_ia32_psrlv2di_mask", IX86_BUILTIN_PSRLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32638 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv8si_mask, "__builtin_ia32_psrlv8si_mask", IX86_BUILTIN_PSRLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32639 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4si_mask, "__builtin_ia32_psrlv4si_mask", IX86_BUILTIN_PSRLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32640 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psrawi256_mask", IX86_BUILTIN_PSRAWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32641 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psraw256_mask", IX86_BUILTIN_PSRAW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32642 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psrawi128_mask", IX86_BUILTIN_PSRAWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32643 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psraw128_mask", IX86_BUILTIN_PSRAW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32644 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlwi256_mask", IX86_BUILTIN_PSRLWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32645 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlw256_mask", IX86_BUILTIN_PSRLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32646 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlwi128_mask", IX86_BUILTIN_PSRLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32647 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlw128_mask", IX86_BUILTIN_PSRLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32648 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv8si_mask, "__builtin_ia32_prorvd256_mask", IX86_BUILTIN_PRORVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32649 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv8si_mask, "__builtin_ia32_prolvd256_mask", IX86_BUILTIN_PROLVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32650 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv8si_mask, "__builtin_ia32_prord256_mask", IX86_BUILTIN_PRORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32651 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv8si_mask, "__builtin_ia32_prold256_mask", IX86_BUILTIN_PROLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32652 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4si_mask, "__builtin_ia32_prorvd128_mask", IX86_BUILTIN_PRORVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32653 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4si_mask, "__builtin_ia32_prolvd128_mask", IX86_BUILTIN_PROLVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32654 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_ia32_prord128_mask", IX86_BUILTIN_PRORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32655 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32656 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_QI },
32657 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_QI },
32658 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT },
32659 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_QI },
32660 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_QI },
32661 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT },
32662 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) HI_FTYPE_V16QI },
32663 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) SI_FTYPE_V32QI },
32664 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) QI_FTYPE_V8HI },
32665 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv16hi, "__builtin_ia32_cvtw2mask256", IX86_BUILTIN_CVTW2MASK256, UNKNOWN, (int) HI_FTYPE_V16HI },
32666 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv4si, "__builtin_ia32_cvtd2mask128", IX86_BUILTIN_CVTD2MASK128, UNKNOWN, (int) QI_FTYPE_V4SI },
32667 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv8si, "__builtin_ia32_cvtd2mask256", IX86_BUILTIN_CVTD2MASK256, UNKNOWN, (int) QI_FTYPE_V8SI },
32668 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv2di, "__builtin_ia32_cvtq2mask128", IX86_BUILTIN_CVTQ2MASK128, UNKNOWN, (int) QI_FTYPE_V2DI },
32669 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv4di, "__builtin_ia32_cvtq2mask256", IX86_BUILTIN_CVTQ2MASK256, UNKNOWN, (int) QI_FTYPE_V4DI },
32670 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv16qi, "__builtin_ia32_cvtmask2b128", IX86_BUILTIN_CVTMASK2B128, UNKNOWN, (int) V16QI_FTYPE_HI },
32671 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv32qi, "__builtin_ia32_cvtmask2b256", IX86_BUILTIN_CVTMASK2B256, UNKNOWN, (int) V32QI_FTYPE_SI },
32672 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv8hi, "__builtin_ia32_cvtmask2w128", IX86_BUILTIN_CVTMASK2W128, UNKNOWN, (int) V8HI_FTYPE_QI },
32673 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv16hi, "__builtin_ia32_cvtmask2w256", IX86_BUILTIN_CVTMASK2W256, UNKNOWN, (int) V16HI_FTYPE_HI },
32674 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv4si, "__builtin_ia32_cvtmask2d128", IX86_BUILTIN_CVTMASK2D128, UNKNOWN, (int) V4SI_FTYPE_QI },
32675 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv8si, "__builtin_ia32_cvtmask2d256", IX86_BUILTIN_CVTMASK2D256, UNKNOWN, (int) V8SI_FTYPE_QI },
32676 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv2di, "__builtin_ia32_cvtmask2q128", IX86_BUILTIN_CVTMASK2Q128, UNKNOWN, (int) V2DI_FTYPE_QI },
32677 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv4di, "__builtin_ia32_cvtmask2q256", IX86_BUILTIN_CVTMASK2Q256, UNKNOWN, (int) V4DI_FTYPE_QI },
32678 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16qi3_mask, "__builtin_ia32_pcmpeqb128_mask", IX86_BUILTIN_PCMPEQB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32679 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv32qi3_mask, "__builtin_ia32_pcmpeqb256_mask", IX86_BUILTIN_PCMPEQB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32680 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8hi3_mask, "__builtin_ia32_pcmpeqw128_mask", IX86_BUILTIN_PCMPEQW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32681 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16hi3_mask, "__builtin_ia32_pcmpeqw256_mask", IX86_BUILTIN_PCMPEQW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32682 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4si3_mask, "__builtin_ia32_pcmpeqd128_mask", IX86_BUILTIN_PCMPEQD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32683 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8si3_mask, "__builtin_ia32_pcmpeqd256_mask", IX86_BUILTIN_PCMPEQD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32684 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv2di3_mask, "__builtin_ia32_pcmpeqq128_mask", IX86_BUILTIN_PCMPEQQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32685 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4di3_mask, "__builtin_ia32_pcmpeqq256_mask", IX86_BUILTIN_PCMPEQQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32686 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16qi3_mask, "__builtin_ia32_pcmpgtb128_mask", IX86_BUILTIN_PCMPGTB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32687 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv32qi3_mask, "__builtin_ia32_pcmpgtb256_mask", IX86_BUILTIN_PCMPGTB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32688 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8hi3_mask, "__builtin_ia32_pcmpgtw128_mask", IX86_BUILTIN_PCMPGTW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32689 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16hi3_mask, "__builtin_ia32_pcmpgtw256_mask", IX86_BUILTIN_PCMPGTW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32690 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4si3_mask, "__builtin_ia32_pcmpgtd128_mask", IX86_BUILTIN_PCMPGTD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32691 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8si3_mask, "__builtin_ia32_pcmpgtd256_mask", IX86_BUILTIN_PCMPGTD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32692 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv2di3_mask, "__builtin_ia32_pcmpgtq128_mask", IX86_BUILTIN_PCMPGTQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32693 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4di3_mask, "__builtin_ia32_pcmpgtq256_mask", IX86_BUILTIN_PCMPGTQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32694 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16qi3_mask, "__builtin_ia32_ptestmb128", IX86_BUILTIN_PTESTMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32695 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv32qi3_mask, "__builtin_ia32_ptestmb256", IX86_BUILTIN_PTESTMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32696 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8hi3_mask, "__builtin_ia32_ptestmw128", IX86_BUILTIN_PTESTMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32697 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16hi3_mask, "__builtin_ia32_ptestmw256", IX86_BUILTIN_PTESTMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32698 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4si3_mask, "__builtin_ia32_ptestmd128", IX86_BUILTIN_PTESTMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32699 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8si3_mask, "__builtin_ia32_ptestmd256", IX86_BUILTIN_PTESTMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32700 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv2di3_mask, "__builtin_ia32_ptestmq128", IX86_BUILTIN_PTESTMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32701 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4di3_mask, "__builtin_ia32_ptestmq256", IX86_BUILTIN_PTESTMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32702 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16qi3_mask, "__builtin_ia32_ptestnmb128", IX86_BUILTIN_PTESTNMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32703 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv32qi3_mask, "__builtin_ia32_ptestnmb256", IX86_BUILTIN_PTESTNMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32704 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8hi3_mask, "__builtin_ia32_ptestnmw128", IX86_BUILTIN_PTESTNMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32705 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16hi3_mask, "__builtin_ia32_ptestnmw256", IX86_BUILTIN_PTESTNMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32706 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4si3_mask, "__builtin_ia32_ptestnmd128", IX86_BUILTIN_PTESTNMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32707 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8si3_mask, "__builtin_ia32_ptestnmd256", IX86_BUILTIN_PTESTNMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32708 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv2di3_mask, "__builtin_ia32_ptestnmq128", IX86_BUILTIN_PTESTNMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32709 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4di3_mask, "__builtin_ia32_ptestnmq256", IX86_BUILTIN_PTESTNMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32710 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv2di, "__builtin_ia32_broadcastmb128", IX86_BUILTIN_PBROADCASTMB128, UNKNOWN, (int) V2DI_FTYPE_QI },
32711 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv4di, "__builtin_ia32_broadcastmb256", IX86_BUILTIN_PBROADCASTMB256, UNKNOWN, (int) V4DI_FTYPE_QI },
32712 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv4si, "__builtin_ia32_broadcastmw128", IX86_BUILTIN_PBROADCASTMW128, UNKNOWN, (int) V4SI_FTYPE_HI },
32713 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv8si, "__builtin_ia32_broadcastmw256", IX86_BUILTIN_PBROADCASTMW256, UNKNOWN, (int) V8SI_FTYPE_HI },
32714 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4df_mask, "__builtin_ia32_compressdf256_mask", IX86_BUILTIN_COMPRESSPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32715 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2df_mask, "__builtin_ia32_compressdf128_mask", IX86_BUILTIN_COMPRESSPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32716 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8sf_mask, "__builtin_ia32_compresssf256_mask", IX86_BUILTIN_COMPRESSPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32717 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4sf_mask, "__builtin_ia32_compresssf128_mask", IX86_BUILTIN_COMPRESSPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32718 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4di_mask, "__builtin_ia32_compressdi256_mask", IX86_BUILTIN_PCOMPRESSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32719 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2di_mask, "__builtin_ia32_compressdi128_mask", IX86_BUILTIN_PCOMPRESSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32720 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8si_mask, "__builtin_ia32_compresssi256_mask", IX86_BUILTIN_PCOMPRESSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32721 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4si_mask, "__builtin_ia32_compresssi128_mask", IX86_BUILTIN_PCOMPRESSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32722 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expanddf256_mask", IX86_BUILTIN_EXPANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32723 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expanddf128_mask", IX86_BUILTIN_EXPANDPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32724 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandsf256_mask", IX86_BUILTIN_EXPANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32725 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandsf128_mask", IX86_BUILTIN_EXPANDPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32726 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expanddi256_mask", IX86_BUILTIN_PEXPANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32727 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expanddi128_mask", IX86_BUILTIN_PEXPANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32728 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandsi256_mask", IX86_BUILTIN_PEXPANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32729 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandsi128_mask", IX86_BUILTIN_PEXPANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32730 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expanddf256_maskz", IX86_BUILTIN_EXPANDPD256Z, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32731 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expanddf128_maskz", IX86_BUILTIN_EXPANDPD128Z, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32732 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandsf256_maskz", IX86_BUILTIN_EXPANDPS256Z, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32733 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandsf128_maskz", IX86_BUILTIN_EXPANDPS128Z, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32734 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expanddi256_maskz", IX86_BUILTIN_PEXPANDQ256Z, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32735 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expanddi128_maskz", IX86_BUILTIN_PEXPANDQ128Z, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32736 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandsi256_maskz", IX86_BUILTIN_PEXPANDD256Z, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32737 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandsi128_maskz", IX86_BUILTIN_PEXPANDD128Z, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32738 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8si3_mask, "__builtin_ia32_pmaxsd256_mask", IX86_BUILTIN_PMAXSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32739 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8si3_mask, "__builtin_ia32_pminsd256_mask", IX86_BUILTIN_PMINSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32740 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8si3_mask, "__builtin_ia32_pmaxud256_mask", IX86_BUILTIN_PMAXUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32741 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8si3_mask, "__builtin_ia32_pminud256_mask", IX86_BUILTIN_PMINUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32742 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4si3_mask, "__builtin_ia32_pmaxsd128_mask", IX86_BUILTIN_PMAXSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32743 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4si3_mask, "__builtin_ia32_pminsd128_mask", IX86_BUILTIN_PMINSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32744 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4si3_mask, "__builtin_ia32_pmaxud128_mask", IX86_BUILTIN_PMAXUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32745 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4si3_mask, "__builtin_ia32_pminud128_mask", IX86_BUILTIN_PMINUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32746 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4di3_mask, "__builtin_ia32_pmaxsq256_mask", IX86_BUILTIN_PMAXSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32747 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4di3_mask, "__builtin_ia32_pminsq256_mask", IX86_BUILTIN_PMINSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32748 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4di3_mask, "__builtin_ia32_pmaxuq256_mask", IX86_BUILTIN_PMAXUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32749 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4di3_mask, "__builtin_ia32_pminuq256_mask", IX86_BUILTIN_PMINUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32750 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2di3_mask, "__builtin_ia32_pmaxsq128_mask", IX86_BUILTIN_PMAXSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32751 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2di3_mask, "__builtin_ia32_pminsq128_mask", IX86_BUILTIN_PMINSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32752 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv2di3_mask, "__builtin_ia32_pmaxuq128_mask", IX86_BUILTIN_PMAXUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32753 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv2di3_mask, "__builtin_ia32_pminuq128_mask", IX86_BUILTIN_PMINUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32754 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv32qi3_mask, "__builtin_ia32_pminsb256_mask", IX86_BUILTIN_PMINSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32755 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv32qi3_mask, "__builtin_ia32_pminub256_mask", IX86_BUILTIN_PMINUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32756 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv32qi3_mask, "__builtin_ia32_pmaxsb256_mask", IX86_BUILTIN_PMAXSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32757 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv32qi3_mask, "__builtin_ia32_pmaxub256_mask", IX86_BUILTIN_PMAXUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32758 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16qi3_mask, "__builtin_ia32_pminsb128_mask", IX86_BUILTIN_PMINSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32759 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16qi3_mask, "__builtin_ia32_pminub128_mask", IX86_BUILTIN_PMINUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32760 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16qi3_mask, "__builtin_ia32_pmaxsb128_mask", IX86_BUILTIN_PMAXSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32761 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16qi3_mask, "__builtin_ia32_pmaxub128_mask", IX86_BUILTIN_PMAXUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32762 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16hi3_mask, "__builtin_ia32_pminsw256_mask", IX86_BUILTIN_PMINSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32763 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16hi3_mask, "__builtin_ia32_pminuw256_mask", IX86_BUILTIN_PMINUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32764 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16hi3_mask, "__builtin_ia32_pmaxsw256_mask", IX86_BUILTIN_PMAXSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32765 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16hi3_mask, "__builtin_ia32_pmaxuw256_mask", IX86_BUILTIN_PMAXUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32766 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8hi3_mask, "__builtin_ia32_pminsw128_mask", IX86_BUILTIN_PMINSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32767 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8hi3_mask, "__builtin_ia32_pminuw128_mask", IX86_BUILTIN_PMINUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32768 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8hi3_mask, "__builtin_ia32_pmaxsw128_mask", IX86_BUILTIN_PMAXSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32769 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8hi3_mask, "__builtin_ia32_pmaxuw128_mask", IX86_BUILTIN_PMAXUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32770 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4di_mask, "__builtin_ia32_vpconflictdi_256_mask", IX86_BUILTIN_VPCONFLICTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32771 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv8si_mask, "__builtin_ia32_vpconflictsi_256_mask", IX86_BUILTIN_VPCONFLICTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32772 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4di2_mask, "__builtin_ia32_vplzcntq_256_mask", IX86_BUILTIN_VPCLZCNTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32773 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv8si2_mask, "__builtin_ia32_vplzcntd_256_mask", IX86_BUILTIN_VPCLZCNTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32774 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhpd256_mask, "__builtin_ia32_unpckhpd256_mask", IX86_BUILTIN_UNPCKHPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32775 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpckhpd128_mask, "__builtin_ia32_unpckhpd128_mask", IX86_BUILTIN_UNPCKHPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32776 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhps256_mask, "__builtin_ia32_unpckhps256_mask", IX86_BUILTIN_UNPCKHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32777 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4sf_mask, "__builtin_ia32_unpckhps128_mask", IX86_BUILTIN_UNPCKHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32778 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklpd256_mask, "__builtin_ia32_unpcklpd256_mask", IX86_BUILTIN_UNPCKLPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32779 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpcklpd128_mask, "__builtin_ia32_unpcklpd128_mask", IX86_BUILTIN_UNPCKLPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32780 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklps256_mask, "__builtin_ia32_unpcklps256_mask", IX86_BUILTIN_UNPCKLPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32781 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv2di_mask, "__builtin_ia32_vpconflictdi_128_mask", IX86_BUILTIN_VPCONFLICTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32782 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4si_mask, "__builtin_ia32_vpconflictsi_128_mask", IX86_BUILTIN_VPCONFLICTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32783 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv2di2_mask, "__builtin_ia32_vplzcntq_128_mask", IX86_BUILTIN_VPCLZCNTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32784 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4si2_mask, "__builtin_ia32_vplzcntd_128_mask", IX86_BUILTIN_VPCLZCNTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32785 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_unpcklps128_mask, "__builtin_ia32_unpcklps128_mask", IX86_BUILTIN_UNPCKLPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32786 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv8si_mask, "__builtin_ia32_alignd256_mask", IX86_BUILTIN_ALIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32787 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4di_mask, "__builtin_ia32_alignq256_mask", IX86_BUILTIN_ALIGNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32788 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4si_mask, "__builtin_ia32_alignd128_mask", IX86_BUILTIN_ALIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI },
32789 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv2di_mask, "__builtin_ia32_alignq128_mask", IX86_BUILTIN_ALIGNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI },
32790 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph256_mask, "__builtin_ia32_vcvtps2ph256_mask", IX86_BUILTIN_CVTPS2PH256_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT_V8HI_QI },
32791 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph_mask, "__builtin_ia32_vcvtps2ph_mask", IX86_BUILTIN_CVTPS2PH_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT_V8HI_QI },
32792 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps_mask, "__builtin_ia32_vcvtph2ps_mask", IX86_BUILTIN_CVTPH2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V8HI_V4SF_QI },
32793 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps256_mask, "__builtin_ia32_vcvtph2ps256_mask", IX86_BUILTIN_CVTPH2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8HI_V8SF_QI },
32794 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4si_mask, "__builtin_ia32_punpckhdq128_mask", IX86_BUILTIN_PUNPCKHDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32795 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv8si_mask, "__builtin_ia32_punpckhdq256_mask", IX86_BUILTIN_PUNPCKHDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32796 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv2di_mask, "__builtin_ia32_punpckhqdq128_mask", IX86_BUILTIN_PUNPCKHQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32797 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv4di_mask, "__builtin_ia32_punpckhqdq256_mask", IX86_BUILTIN_PUNPCKHQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32798 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv4si_mask, "__builtin_ia32_punpckldq128_mask", IX86_BUILTIN_PUNPCKLDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32799 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv8si_mask, "__builtin_ia32_punpckldq256_mask", IX86_BUILTIN_PUNPCKLDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32800 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv2di_mask, "__builtin_ia32_punpcklqdq128_mask", IX86_BUILTIN_PUNPCKLQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32801 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv4di_mask, "__builtin_ia32_punpcklqdq256_mask", IX86_BUILTIN_PUNPCKLQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32802 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv16qi_mask, "__builtin_ia32_punpckhbw128_mask", IX86_BUILTIN_PUNPCKHBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32803 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv32qi_mask, "__builtin_ia32_punpckhbw256_mask", IX86_BUILTIN_PUNPCKHBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32804 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv8hi_mask, "__builtin_ia32_punpckhwd128_mask", IX86_BUILTIN_PUNPCKHWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32805 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv16hi_mask, "__builtin_ia32_punpckhwd256_mask", IX86_BUILTIN_PUNPCKHWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32806 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv16qi_mask, "__builtin_ia32_punpcklbw128_mask", IX86_BUILTIN_PUNPCKLBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32807 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv32qi_mask, "__builtin_ia32_punpcklbw256_mask", IX86_BUILTIN_PUNPCKLBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32808 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv8hi_mask, "__builtin_ia32_punpcklwd128_mask", IX86_BUILTIN_PUNPCKLWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32809 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv16hi_mask, "__builtin_ia32_punpcklwd256_mask", IX86_BUILTIN_PUNPCKLWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32810 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv16hi_mask, "__builtin_ia32_psllv16hi_mask", IX86_BUILTIN_PSLLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32811 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv8hi_mask, "__builtin_ia32_psllv8hi_mask", IX86_BUILTIN_PSLLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32812 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packssdw_mask, "__builtin_ia32_packssdw256_mask", IX86_BUILTIN_PACKSSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32813 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packssdw_mask, "__builtin_ia32_packssdw128_mask", IX86_BUILTIN_PACKSSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32814 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packusdw_mask, "__builtin_ia32_packusdw256_mask", IX86_BUILTIN_PACKUSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32815 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_packusdw_mask, "__builtin_ia32_packusdw128_mask", IX86_BUILTIN_PACKUSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32816 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv32qi3_mask, "__builtin_ia32_pavgb256_mask", IX86_BUILTIN_PAVGB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32817 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv16hi3_mask, "__builtin_ia32_pavgw256_mask", IX86_BUILTIN_PAVGW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32818 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv16qi3_mask, "__builtin_ia32_pavgb128_mask", IX86_BUILTIN_PAVGB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32819 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv8hi3_mask, "__builtin_ia32_pavgw128_mask", IX86_BUILTIN_PAVGW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32820 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8sf_mask, "__builtin_ia32_permvarsf256_mask", IX86_BUILTIN_VPERMVARSF256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32821 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4df_mask, "__builtin_ia32_permvardf256_mask", IX86_BUILTIN_VPERMVARDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32822 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4df_mask, "__builtin_ia32_permdf256_mask", IX86_BUILTIN_VPERMDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32823 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv32qi2_mask, "__builtin_ia32_pabsb256_mask", IX86_BUILTIN_PABSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32824 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16qi2_mask, "__builtin_ia32_pabsb128_mask", IX86_BUILTIN_PABSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32825 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16hi2_mask, "__builtin_ia32_pabsw256_mask", IX86_BUILTIN_PABSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32826 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8hi2_mask, "__builtin_ia32_pabsw128_mask", IX86_BUILTIN_PABSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32827 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv2df3_mask, "__builtin_ia32_vpermilvarpd_mask", IX86_BUILTIN_VPERMILVARPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32828 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4sf3_mask, "__builtin_ia32_vpermilvarps_mask", IX86_BUILTIN_VPERMILVARPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32829 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4df3_mask, "__builtin_ia32_vpermilvarpd256_mask", IX86_BUILTIN_VPERMILVARPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32830 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv8sf3_mask, "__builtin_ia32_vpermilvarps256_mask", IX86_BUILTIN_VPERMILVARPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32831 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv2df_mask, "__builtin_ia32_vpermilpd_mask", IX86_BUILTIN_VPERMILPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32832 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4sf_mask, "__builtin_ia32_vpermilps_mask", IX86_BUILTIN_VPERMILPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32833 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4df_mask, "__builtin_ia32_vpermilpd256_mask", IX86_BUILTIN_VPERMILPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32834 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv8sf_mask, "__builtin_ia32_vpermilps256_mask", IX86_BUILTIN_VPERMILPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32835 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4di, "__builtin_ia32_blendmq_256_mask", IX86_BUILTIN_BLENDMQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32836 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8si, "__builtin_ia32_blendmd_256_mask", IX86_BUILTIN_BLENDMD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32837 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4df, "__builtin_ia32_blendmpd_256_mask", IX86_BUILTIN_BLENDMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32838 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8sf, "__builtin_ia32_blendmps_256_mask", IX86_BUILTIN_BLENDMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32839 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2di, "__builtin_ia32_blendmq_128_mask", IX86_BUILTIN_BLENDMQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32840 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4si, "__builtin_ia32_blendmd_128_mask", IX86_BUILTIN_BLENDMD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32841 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2df, "__builtin_ia32_blendmpd_128_mask", IX86_BUILTIN_BLENDMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32842 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4sf, "__builtin_ia32_blendmps_128_mask", IX86_BUILTIN_BLENDMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32843 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16hi, "__builtin_ia32_blendmw_256_mask", IX86_BUILTIN_BLENDMW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32844 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv32qi, "__builtin_ia32_blendmb_256_mask", IX86_BUILTIN_BLENDMB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32845 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8hi, "__builtin_ia32_blendmw_128_mask", IX86_BUILTIN_BLENDMW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32846 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16qi, "__builtin_ia32_blendmb_128_mask", IX86_BUILTIN_BLENDMB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32847 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8si3_mask, "__builtin_ia32_pmulld256_mask", IX86_BUILTIN_PMULLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32848 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4si3_mask, "__builtin_ia32_pmulld128_mask", IX86_BUILTIN_PMULLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32849 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v8si_mask, "__builtin_ia32_pmuludq256_mask", IX86_BUILTIN_PMULUDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32850 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_smult_even_v8si_mask, "__builtin_ia32_pmuldq256_mask", IX86_BUILTIN_PMULDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32851 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_mulv2siv2di3_mask, "__builtin_ia32_pmuldq128_mask", IX86_BUILTIN_PMULDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32852 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v4si_mask, "__builtin_ia32_pmuludq128_mask", IX86_BUILTIN_PMULUDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32853 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2ps256_mask, "__builtin_ia32_cvtpd2ps256_mask", IX86_BUILTIN_CVTPD2PS256_MASK, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_QI },
32854 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2ps_mask, "__builtin_ia32_cvtpd2ps_mask", IX86_BUILTIN_CVTPD2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V2DF_V4SF_QI },
32855 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8si_mask, "__builtin_ia32_permvarsi256_mask", IX86_BUILTIN_VPERMVARSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32856 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4di_mask, "__builtin_ia32_permvardi256_mask", IX86_BUILTIN_VPERMVARDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32857 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4di_mask, "__builtin_ia32_permdi256_mask", IX86_BUILTIN_VPERMDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32858 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4di3_mask, "__builtin_ia32_cmpq256_mask", IX86_BUILTIN_CMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32859 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8si3_mask, "__builtin_ia32_cmpd256_mask", IX86_BUILTIN_CMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32860 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4di3_mask, "__builtin_ia32_ucmpq256_mask", IX86_BUILTIN_UCMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32861 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8si3_mask, "__builtin_ia32_ucmpd256_mask", IX86_BUILTIN_UCMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32862 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv32qi3_mask, "__builtin_ia32_cmpb256_mask", IX86_BUILTIN_CMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32863 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16hi3_mask, "__builtin_ia32_cmpw256_mask", IX86_BUILTIN_CMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32864 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv32qi3_mask, "__builtin_ia32_ucmpb256_mask", IX86_BUILTIN_UCMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32865 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16hi3_mask, "__builtin_ia32_ucmpw256_mask", IX86_BUILTIN_UCMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32866 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4df3_mask, "__builtin_ia32_cmppd256_mask", IX86_BUILTIN_CMPPD256_MASK, UNKNOWN, (int) QI_FTYPE_V4DF_V4DF_INT_QI },
32867 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8sf3_mask, "__builtin_ia32_cmpps256_mask", IX86_BUILTIN_CMPPS256_MASK, UNKNOWN, (int) QI_FTYPE_V8SF_V8SF_INT_QI },
32868 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2di3_mask, "__builtin_ia32_cmpq128_mask", IX86_BUILTIN_CMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32869 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4si3_mask, "__builtin_ia32_cmpd128_mask", IX86_BUILTIN_CMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32870 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv2di3_mask, "__builtin_ia32_ucmpq128_mask", IX86_BUILTIN_UCMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32871 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4si3_mask, "__builtin_ia32_ucmpd128_mask", IX86_BUILTIN_UCMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32872 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16qi3_mask, "__builtin_ia32_cmpb128_mask", IX86_BUILTIN_CMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32873 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8hi3_mask, "__builtin_ia32_cmpw128_mask", IX86_BUILTIN_CMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32874 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16qi3_mask, "__builtin_ia32_ucmpb128_mask", IX86_BUILTIN_UCMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32875 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8hi3_mask, "__builtin_ia32_ucmpw128_mask", IX86_BUILTIN_UCMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32876 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2df3_mask, "__builtin_ia32_cmppd128_mask", IX86_BUILTIN_CMPPD128_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI },
32877 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4sf3_mask, "__builtin_ia32_cmpps128_mask", IX86_BUILTIN_CMPPS128_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI },
32879 /* AVX512DQ. */
32880 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x2_512_mask", IX86_BUILTIN_BROADCASTF32x2_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
32881 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask, "__builtin_ia32_broadcasti32x2_512_mask", IX86_BUILTIN_BROADCASTI32x2_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
32882 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8df_mask_1, "__builtin_ia32_broadcastf64x2_512_mask", IX86_BUILTIN_BROADCASTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
32883 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8di_mask_1, "__builtin_ia32_broadcasti64x2_512_mask", IX86_BUILTIN_BROADCASTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
32884 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask_1, "__builtin_ia32_broadcastf32x8_512_mask", IX86_BUILTIN_BROADCASTF32X8_512, UNKNOWN, (int) V16SF_FTYPE_V8SF_V16SF_HI },
32885 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask_1, "__builtin_ia32_broadcasti32x8_512_mask", IX86_BUILTIN_BROADCASTI32X8_512, UNKNOWN, (int) V16SI_FTYPE_V8SI_V16SI_HI },
32886 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf64x2_mask, "__builtin_ia32_extractf64x2_512_mask", IX86_BUILTIN_EXTRACTF64X2_512, UNKNOWN, (int) V2DF_FTYPE_V8DF_INT_V2DF_QI },
32887 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf32x8_mask, "__builtin_ia32_extractf32x8_mask", IX86_BUILTIN_EXTRACTF32X8, UNKNOWN, (int) V8SF_FTYPE_V16SF_INT_V8SF_QI },
32888 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti64x2_mask, "__builtin_ia32_extracti64x2_512_mask", IX86_BUILTIN_EXTRACTI64X2_512, UNKNOWN, (int) V2DI_FTYPE_V8DI_INT_V2DI_QI },
32889 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti32x8_mask, "__builtin_ia32_extracti32x8_mask", IX86_BUILTIN_EXTRACTI32X8, UNKNOWN, (int) V8SI_FTYPE_V16SI_INT_V8SI_QI },
32890 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv8df_mask, "__builtin_ia32_reducepd512_mask", IX86_BUILTIN_REDUCEPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32891 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv16sf_mask, "__builtin_ia32_reduceps512_mask", IX86_BUILTIN_REDUCEPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
32892 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_mulv8di3_mask, "__builtin_ia32_pmullq512_mask", IX86_BUILTIN_PMULLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32893 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv8df3_mask, "__builtin_ia32_xorpd512_mask", IX86_BUILTIN_XORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32894 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv16sf3_mask, "__builtin_ia32_xorps512_mask", IX86_BUILTIN_XORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32895 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv8df3_mask, "__builtin_ia32_orpd512_mask", IX86_BUILTIN_ORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32896 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv16sf3_mask, "__builtin_ia32_orps512_mask", IX86_BUILTIN_ORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32897 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv8df3_mask, "__builtin_ia32_andpd512_mask", IX86_BUILTIN_ANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32898 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv16sf3_mask, "__builtin_ia32_andps512_mask", IX86_BUILTIN_ANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32899 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv8df3_mask, "__builtin_ia32_andnpd512_mask", IX86_BUILTIN_ANDNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI},
32900 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv16sf3_mask, "__builtin_ia32_andnps512_mask", IX86_BUILTIN_ANDNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32901 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf32x8_mask, "__builtin_ia32_insertf32x8_mask", IX86_BUILTIN_INSERTF32X8, UNKNOWN, (int) V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI },
32902 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti32x8_mask, "__builtin_ia32_inserti32x8_mask", IX86_BUILTIN_INSERTI32X8, UNKNOWN, (int) V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI },
32903 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf64x2_mask, "__builtin_ia32_insertf64x2_512_mask", IX86_BUILTIN_INSERTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI },
32904 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti64x2_mask, "__builtin_ia32_inserti64x2_512_mask", IX86_BUILTIN_INSERTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI },
32905 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv8df_mask, "__builtin_ia32_fpclasspd512_mask", IX86_BUILTIN_FPCLASSPD512, UNKNOWN, (int) QI_FTYPE_V8DF_INT_QI },
32906 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv16sf_mask, "__builtin_ia32_fpclassps512_mask", IX86_BUILTIN_FPCLASSPS512, UNKNOWN, (int) HI_FTYPE_V16SF_INT_HI },
32907 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtd2maskv16si, "__builtin_ia32_cvtd2mask512", IX86_BUILTIN_CVTD2MASK512, UNKNOWN, (int) HI_FTYPE_V16SI },
32908 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtq2maskv8di, "__builtin_ia32_cvtq2mask512", IX86_BUILTIN_CVTQ2MASK512, UNKNOWN, (int) QI_FTYPE_V8DI },
32909 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2dv16si, "__builtin_ia32_cvtmask2d512", IX86_BUILTIN_CVTMASK2D512, UNKNOWN, (int) V16SI_FTYPE_HI },
32910 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2qv8di, "__builtin_ia32_cvtmask2q512", IX86_BUILTIN_CVTMASK2Q512, UNKNOWN, (int) V8DI_FTYPE_QI },
32912 /* AVX512BW. */
32913 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpcksi, "__builtin_ia32_kunpcksi", IX86_BUILTIN_KUNPCKWD, UNKNOWN, (int) SI_FTYPE_SI_SI },
32914 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpckdi, "__builtin_ia32_kunpckdi", IX86_BUILTIN_KUNPCKDQ, UNKNOWN, (int) DI_FTYPE_DI_DI },
32915 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packusdw_mask, "__builtin_ia32_packusdw512_mask", IX86_BUILTIN_PACKUSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32916 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlv4ti3, "__builtin_ia32_pslldq512", IX86_BUILTIN_PSLLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32917 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrv4ti3, "__builtin_ia32_psrldq512", IX86_BUILTIN_PSRLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32918 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packssdw_mask, "__builtin_ia32_packssdw512_mask", IX86_BUILTIN_PACKSSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32919 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv4ti, "__builtin_ia32_palignr512", IX86_BUILTIN_PALIGNR512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_CONVERT },
32920 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv64qi_mask, "__builtin_ia32_palignr512_mask", IX86_BUILTIN_PALIGNR512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT },
32921 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_movdquhi512_mask", IX86_BUILTIN_MOVDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32922 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_movdquqi512_mask", IX86_BUILTIN_MOVDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32923 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_psadbw, "__builtin_ia32_psadbw512", IX86_BUILTIN_PSADBW512, UNKNOWN, (int) V8DI_FTYPE_V64QI_V64QI },
32924 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_dbpsadbwv32hi_mask, "__builtin_ia32_dbpsadbw512_mask", IX86_BUILTIN_DBPSADBW512, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI },
32925 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv64qi_mask, "__builtin_ia32_pbroadcastb512_mask", IX86_BUILTIN_PBROADCASTB512, UNKNOWN, (int) V64QI_FTYPE_V16QI_V64QI_DI },
32926 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv64qi_mask, "__builtin_ia32_pbroadcastb512_gpr_mask", IX86_BUILTIN_PBROADCASTB512_GPR, UNKNOWN, (int) V64QI_FTYPE_QI_V64QI_DI },
32927 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv32hi_mask, "__builtin_ia32_pbroadcastw512_mask", IX86_BUILTIN_PBROADCASTW512, UNKNOWN, (int) V32HI_FTYPE_V8HI_V32HI_SI },
32928 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv32hi_mask, "__builtin_ia32_pbroadcastw512_gpr_mask", IX86_BUILTIN_PBROADCASTW512_GPR, UNKNOWN, (int) V32HI_FTYPE_HI_V32HI_SI },
32929 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sign_extendv32qiv32hi2_mask, "__builtin_ia32_pmovsxbw512_mask", IX86_BUILTIN_PMOVSXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32930 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_zero_extendv32qiv32hi2_mask, "__builtin_ia32_pmovzxbw512_mask", IX86_BUILTIN_PMOVZXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32931 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_permvarv32hi_mask, "__builtin_ia32_permvarhi512_mask", IX86_BUILTIN_VPERMVARHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32932 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_mask, "__builtin_ia32_vpermt2varhi512_mask", IX86_BUILTIN_VPERMT2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32933 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_maskz, "__builtin_ia32_vpermt2varhi512_maskz", IX86_BUILTIN_VPERMT2VARHI512_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32934 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermi2varv32hi3_mask, "__builtin_ia32_vpermi2varhi512_mask", IX86_BUILTIN_VPERMI2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32935 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv64qi3_mask, "__builtin_ia32_pavgb512_mask", IX86_BUILTIN_PAVGB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32936 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv32hi3_mask, "__builtin_ia32_pavgw512_mask", IX86_BUILTIN_PAVGW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32937 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv64qi3_mask, "__builtin_ia32_paddb512_mask", IX86_BUILTIN_PADDB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32938 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv64qi3_mask, "__builtin_ia32_psubb512_mask", IX86_BUILTIN_PSUBB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32939 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv64qi3_mask, "__builtin_ia32_psubsb512_mask", IX86_BUILTIN_PSUBSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32940 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv64qi3_mask, "__builtin_ia32_paddsb512_mask", IX86_BUILTIN_PADDSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32941 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv64qi3_mask, "__builtin_ia32_psubusb512_mask", IX86_BUILTIN_PSUBUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32942 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv64qi3_mask, "__builtin_ia32_paddusb512_mask", IX86_BUILTIN_PADDUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32943 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv32hi3_mask, "__builtin_ia32_psubw512_mask", IX86_BUILTIN_PSUBW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32944 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv32hi3_mask, "__builtin_ia32_paddw512_mask", IX86_BUILTIN_PADDW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32945 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv32hi3_mask, "__builtin_ia32_psubsw512_mask", IX86_BUILTIN_PSUBSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32946 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv32hi3_mask, "__builtin_ia32_paddsw512_mask", IX86_BUILTIN_PADDSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32947 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv32hi3_mask, "__builtin_ia32_psubusw512_mask", IX86_BUILTIN_PSUBUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32948 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv32hi3_mask, "__builtin_ia32_paddusw512_mask", IX86_BUILTIN_PADDUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32949 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv32hi3_mask, "__builtin_ia32_pmaxuw512_mask", IX86_BUILTIN_PMAXUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32950 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv32hi3_mask, "__builtin_ia32_pmaxsw512_mask", IX86_BUILTIN_PMAXSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32951 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv32hi3_mask, "__builtin_ia32_pminuw512_mask", IX86_BUILTIN_PMINUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32952 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv32hi3_mask, "__builtin_ia32_pminsw512_mask", IX86_BUILTIN_PMINSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32953 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv64qi3_mask, "__builtin_ia32_pmaxub512_mask", IX86_BUILTIN_PMAXUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32954 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv64qi3_mask, "__builtin_ia32_pmaxsb512_mask", IX86_BUILTIN_PMAXSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32955 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv64qi3_mask, "__builtin_ia32_pminub512_mask", IX86_BUILTIN_PMINUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32956 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv64qi3_mask, "__builtin_ia32_pminsb512_mask", IX86_BUILTIN_PMINSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32957 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovwb512_mask", IX86_BUILTIN_PMOVWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32958 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ss_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovswb512_mask", IX86_BUILTIN_PMOVSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32959 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_us_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovuswb512_mask", IX86_BUILTIN_PMOVUSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32960 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_umulhrswv32hi3_mask, "__builtin_ia32_pmulhrsw512_mask", IX86_BUILTIN_PMULHRSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32961 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umulv32hi3_highpart_mask, "__builtin_ia32_pmulhuw512_mask" , IX86_BUILTIN_PMULHUW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32962 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smulv32hi3_highpart_mask, "__builtin_ia32_pmulhw512_mask" , IX86_BUILTIN_PMULHW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32963 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_mulv32hi3_mask, "__builtin_ia32_pmullw512_mask", IX86_BUILTIN_PMULLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32964 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllwi512_mask", IX86_BUILTIN_PSLLWI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32965 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllw512_mask", IX86_BUILTIN_PSLLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32966 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packsswb_mask, "__builtin_ia32_packsswb512_mask", IX86_BUILTIN_PACKSSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32967 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packuswb_mask, "__builtin_ia32_packuswb512_mask", IX86_BUILTIN_PACKUSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32968 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashrvv32hi_mask, "__builtin_ia32_psrav32hi_mask", IX86_BUILTIN_PSRAVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32969 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddubsw512v32hi_mask, "__builtin_ia32_pmaddubsw512_mask", IX86_BUILTIN_PMADDUBSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_V32HI_SI },
32970 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddwd512v32hi_mask, "__builtin_ia32_pmaddwd512_mask", IX86_BUILTIN_PMADDWD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V32HI_V32HI_V16SI_HI },
32971 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrvv32hi_mask, "__builtin_ia32_psrlv32hi_mask", IX86_BUILTIN_PSRLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32972 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv64qi_mask, "__builtin_ia32_punpckhbw512_mask", IX86_BUILTIN_PUNPCKHBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32973 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv32hi_mask, "__builtin_ia32_punpckhwd512_mask", IX86_BUILTIN_PUNPCKHWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32974 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv64qi_mask, "__builtin_ia32_punpcklbw512_mask", IX86_BUILTIN_PUNPCKLBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32975 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv32hi_mask, "__builtin_ia32_punpcklwd512_mask", IX86_BUILTIN_PUNPCKLWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32976 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufbv64qi3_mask, "__builtin_ia32_pshufb512_mask", IX86_BUILTIN_PSHUFB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32977 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufhwv32hi_mask, "__builtin_ia32_pshufhw512_mask", IX86_BUILTIN_PSHUFHW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32978 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshuflwv32hi_mask, "__builtin_ia32_pshuflw512_mask", IX86_BUILTIN_PSHUFLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32979 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psrawi512_mask", IX86_BUILTIN_PSRAWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32980 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psraw512_mask", IX86_BUILTIN_PSRAW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32981 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlwi512_mask", IX86_BUILTIN_PSRLWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32982 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlw512_mask", IX86_BUILTIN_PSRLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32983 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtb2maskv64qi, "__builtin_ia32_cvtb2mask512", IX86_BUILTIN_CVTB2MASK512, UNKNOWN, (int) DI_FTYPE_V64QI },
32984 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtw2maskv32hi, "__builtin_ia32_cvtw2mask512", IX86_BUILTIN_CVTW2MASK512, UNKNOWN, (int) SI_FTYPE_V32HI },
32985 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2bv64qi, "__builtin_ia32_cvtmask2b512", IX86_BUILTIN_CVTMASK2B512, UNKNOWN, (int) V64QI_FTYPE_DI },
32986 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2wv32hi, "__builtin_ia32_cvtmask2w512", IX86_BUILTIN_CVTMASK2W512, UNKNOWN, (int) V32HI_FTYPE_SI },
32987 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv64qi3_mask, "__builtin_ia32_pcmpeqb512_mask", IX86_BUILTIN_PCMPEQB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32988 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv32hi3_mask, "__builtin_ia32_pcmpeqw512_mask", IX86_BUILTIN_PCMPEQW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32989 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv64qi3_mask, "__builtin_ia32_pcmpgtb512_mask", IX86_BUILTIN_PCMPGTB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32990 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv32hi3_mask, "__builtin_ia32_pcmpgtw512_mask", IX86_BUILTIN_PCMPGTW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32991 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv64qi3_mask, "__builtin_ia32_ptestmb512", IX86_BUILTIN_PTESTMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32992 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv32hi3_mask, "__builtin_ia32_ptestmw512", IX86_BUILTIN_PTESTMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32993 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv64qi3_mask, "__builtin_ia32_ptestnmb512", IX86_BUILTIN_PTESTNMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32994 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv32hi3_mask, "__builtin_ia32_ptestnmw512", IX86_BUILTIN_PTESTNMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32995 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlvv32hi_mask, "__builtin_ia32_psllv32hi_mask", IX86_BUILTIN_PSLLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32996 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv64qi2_mask, "__builtin_ia32_pabsb512_mask", IX86_BUILTIN_PABSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32997 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv32hi2_mask, "__builtin_ia32_pabsw512_mask", IX86_BUILTIN_PABSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32998 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv32hi, "__builtin_ia32_blendmw_512_mask", IX86_BUILTIN_BLENDMW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32999 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv64qi, "__builtin_ia32_blendmb_512_mask", IX86_BUILTIN_BLENDMB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
33000 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv64qi3_mask, "__builtin_ia32_cmpb512_mask", IX86_BUILTIN_CMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
33001 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
33002 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
33003 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
33005 /* AVX512IFMA */
33006 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_mask, "__builtin_ia32_vpmadd52luq512_mask", IX86_BUILTIN_VPMADD52LUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33007 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_maskz, "__builtin_ia32_vpmadd52luq512_maskz", IX86_BUILTIN_VPMADD52LUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33008 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_mask, "__builtin_ia32_vpmadd52huq512_mask", IX86_BUILTIN_VPMADD52HUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33009 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_maskz, "__builtin_ia32_vpmadd52huq512_maskz", IX86_BUILTIN_VPMADD52HUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33010 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_mask, "__builtin_ia32_vpmadd52luq256_mask", IX86_BUILTIN_VPMADD52LUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33011 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_maskz, "__builtin_ia32_vpmadd52luq256_maskz", IX86_BUILTIN_VPMADD52LUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33012 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_mask, "__builtin_ia32_vpmadd52huq256_mask", IX86_BUILTIN_VPMADD52HUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33013 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_maskz, "__builtin_ia32_vpmadd52huq256_maskz", IX86_BUILTIN_VPMADD52HUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33014 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_mask, "__builtin_ia32_vpmadd52luq128_mask", IX86_BUILTIN_VPMADD52LUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33015 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_maskz, "__builtin_ia32_vpmadd52luq128_maskz", IX86_BUILTIN_VPMADD52LUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33016 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_mask, "__builtin_ia32_vpmadd52huq128_mask", IX86_BUILTIN_VPMADD52HUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33017 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_maskz, "__builtin_ia32_vpmadd52huq128_maskz", IX86_BUILTIN_VPMADD52HUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33019 /* AVX512VBMI */
33020 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_vpmultishiftqbv64qi_mask, "__builtin_ia32_vpmultishiftqb512_mask", IX86_BUILTIN_VPMULTISHIFTQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33021 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv32qi_mask, "__builtin_ia32_vpmultishiftqb256_mask", IX86_BUILTIN_VPMULTISHIFTQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33022 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv16qi_mask, "__builtin_ia32_vpmultishiftqb128_mask", IX86_BUILTIN_VPMULTISHIFTQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33023 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_permvarv64qi_mask, "__builtin_ia32_permvarqi512_mask", IX86_BUILTIN_VPERMVARQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33024 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_mask, "__builtin_ia32_vpermt2varqi512_mask", IX86_BUILTIN_VPERMT2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33025 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_maskz, "__builtin_ia32_vpermt2varqi512_maskz", IX86_BUILTIN_VPERMT2VARQI512_MASKZ, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33026 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermi2varv64qi3_mask, "__builtin_ia32_vpermi2varqi512_mask", IX86_BUILTIN_VPERMI2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33027 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv32qi_mask, "__builtin_ia32_permvarqi256_mask", IX86_BUILTIN_VPERMVARQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33028 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16qi_mask, "__builtin_ia32_permvarqi128_mask", IX86_BUILTIN_VPERMVARQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33029 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_mask, "__builtin_ia32_vpermt2varqi256_mask", IX86_BUILTIN_VPERMT2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33030 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_maskz, "__builtin_ia32_vpermt2varqi256_maskz", IX86_BUILTIN_VPERMT2VARQI256_MASKZ, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33031 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_mask, "__builtin_ia32_vpermt2varqi128_mask", IX86_BUILTIN_VPERMT2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33032 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_maskz, "__builtin_ia32_vpermt2varqi128_maskz", IX86_BUILTIN_VPERMT2VARQI128_MASKZ, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33033 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv32qi3_mask, "__builtin_ia32_vpermi2varqi256_mask", IX86_BUILTIN_VPERMI2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33034 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16qi3_mask, "__builtin_ia32_vpermi2varqi128_mask", IX86_BUILTIN_VPERMI2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33035 };
33037 /* Builtins with rounding support. */
33039 {
33040 /* AVX512F */
33041 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33042 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33043 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33044 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33045 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
33046 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
33047 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
33048 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
33049 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
33050 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
33051 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
33052 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33053 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
33054 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33055 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
33056 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33057 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
33058 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33059 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
33060 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
33061 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
33062 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
33063 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
33064 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33065 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33066 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33067 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33068 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
33069 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
33070 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
33071 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
33072 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33073 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33074 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33075 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33076 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
33077 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
33078 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
33079 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
33080 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
33081 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
33082 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
33083 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
33084 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33085 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33086 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33087 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33088 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
33089 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
33090 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33091 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33092 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33093 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33094 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33095 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33096 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33097 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33098 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
33105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
33106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
33121 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33123 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33125 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33127 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
33129 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33130 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33131 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33133 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33134 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33135 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33136 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33137 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33139 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33140 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33141 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33142 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
33143 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
33144 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33145 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33146 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33147 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33148 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33149 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33150 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33151 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33152 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33153 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33154 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33155 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33156 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33157 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33158 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33159 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33161 /* AVX512ER */
33162 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33163 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33164 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33165 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33166 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33167 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33168 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33169 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33170 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33171 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33173 /* AVX512DQ. */
33174 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv2df_round, "__builtin_ia32_rangesd128_round", IX86_BUILTIN_RANGESD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33175 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv4sf_round, "__builtin_ia32_rangess128_round", IX86_BUILTIN_RANGESS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33176 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2qq512_mask", IX86_BUILTIN_CVTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33177 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__builtin_ia32_cvtps2qq512_mask", IX86_BUILTIN_CVTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33178 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33179 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33180 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33181 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33182 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33183 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33184 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33185 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33186 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33187 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33188 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT },
33189 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT },
33190 };
33192 /* Bultins for MPX. */
33194 {
33195 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndstx", IX86_BUILTIN_BNDSTX, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND_PCVOID },
33196 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcl", IX86_BUILTIN_BNDCL, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33197 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcu", IX86_BUILTIN_BNDCU, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33198 };
33200 /* Const builtins for MPX. */
33202 {
33203 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndmk", IX86_BUILTIN_BNDMK, UNKNOWN, (int) BND_FTYPE_PCVOID_ULONG },
33204 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndldx", IX86_BUILTIN_BNDLDX, UNKNOWN, (int) BND_FTYPE_PCVOID_PCVOID },
33205 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_narrow_bounds", IX86_BUILTIN_BNDNARROW, UNKNOWN, (int) PVOID_FTYPE_PCVOID_BND_ULONG },
33206 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndint", IX86_BUILTIN_BNDINT, UNKNOWN, (int) BND_FTYPE_BND_BND },
33207 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_sizeof", IX86_BUILTIN_SIZEOF, UNKNOWN, (int) ULONG_FTYPE_VOID },
33208 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndlower", IX86_BUILTIN_BNDLOWER, UNKNOWN, (int) PVOID_FTYPE_BND },
33209 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndupper", IX86_BUILTIN_BNDUPPER, UNKNOWN, (int) PVOID_FTYPE_BND },
33210 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndret", IX86_BUILTIN_BNDRET, UNKNOWN, (int) BND_FTYPE_PCVOID },
33211 };
33213 /* FMA4 and XOP. */
33214 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
33215 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
33216 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
33217 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
33218 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
33219 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
33220 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
33221 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
33222 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
33223 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
33224 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
33225 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
33226 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
33227 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
33228 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
33229 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
33230 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
33231 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
33232 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
33233 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
33234 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
33235 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
33236 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
33237 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
33238 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
33239 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
33240 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
33241 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
33242 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
33243 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
33244 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
33245 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
33246 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
33247 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
33248 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
33249 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
33250 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
33251 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
33252 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
33253 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
33254 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
33255 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
33256 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
33257 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
33258 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
33259 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
33260 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
33261 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
33262 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
33263 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
33264 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
33265 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
33268 {
33309 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
33310 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
33311 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
33312 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
33313 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
33314 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
33315 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
33317 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33318 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33319 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
33320 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
33321 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
33322 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
33323 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
33325 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
33327 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33328 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33329 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33330 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33331 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33332 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33333 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33334 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33335 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33336 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33337 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33338 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33340 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33341 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
33342 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
33343 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
33344 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
33345 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
33346 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
33347 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
33348 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33349 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
33350 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
33351 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
33352 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33353 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
33354 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
33355 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
33357 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
33358 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
33359 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
33360 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
33361 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
33362 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
33364 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33365 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33366 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33367 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33368 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33369 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33370 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33371 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33372 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33373 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33374 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33375 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33376 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33377 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33378 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33380 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
33381 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33382 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33383 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
33384 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
33385 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
33386 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
33388 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
33389 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33390 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33391 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
33392 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
33393 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
33394 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
33396 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
33397 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33398 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33399 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
33400 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
33401 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
33402 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
33404 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33405 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33406 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33407 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
33408 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
33409 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
33410 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
33412 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
33413 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33414 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33415 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
33416 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
33417 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
33418 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
33420 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
33421 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33422 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33423 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
33424 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
33425 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
33426 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
33428 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
33429 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33430 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33431 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
33432 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
33433 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
33434 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
33436 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33437 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33438 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33439 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
33440 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
33441 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
33442 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
33444 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33445 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33446 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33447 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33448 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33449 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33450 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33451 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33453 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33454 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33455 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33456 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33457 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33458 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33459 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33460 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33462 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
33463 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
33464 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
33465 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
33467 };
33468 \f
33469 /* TM vector builtins. */
33471 /* Reuse the existing x86-specific `struct builtin_description' cause
33472 we're lazy. Add casts to make them fit. */
33474 {
33475 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33476 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33477 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33478 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33479 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33480 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33481 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33483 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33484 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33485 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33486 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33487 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33488 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33489 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33491 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33492 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33493 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33494 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33495 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33496 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33497 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33499 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
33500 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
33501 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
33502 };
33504 /* TM callbacks. */
33506 /* Return the builtin decl needed to load a vector of TYPE. */
33508 static tree
33510 {
33512 {
33514 {
33521 }
33522 }
33524 }
33526 /* Return the builtin decl needed to store a vector of TYPE. */
33528 static tree
33530 {
33532 {
33534 {
33541 }
33542 }
33544 }
33545 \f
33546 /* Initialize the transactional memory vector load/store builtins. */
33548 static void
33550 {
33554 tree decl;
33561 /* If there are no builtins defined, we must be compiling in a
33562 language without trans-mem support. */
33566 /* Use whatever attributes a normal TM load has. */
33570 /* Use whatever attributes a normal TM store has. */
33574 /* Use whatever attributes a normal TM log has. */
33582 {
33586 {
33594 {
33597 }
33599 {
33602 }
33603 else
33604 {
33607 }
33609 /* The builtin without the prefix for
33610 calling it directly. */
33612 attrs);
33613 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
33614 set the TYPE_ATTRIBUTES. */
33618 }
33619 }
33620 }
33622 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
33623 in the current target ISA to allow the user to compile particular modules
33624 with different target specific options that differ from the command line
33625 options. */
33626 static void
33628 {
33633 /* Add all special builtins with variable number of operands. */
33637 {
33643 }
33645 /* Add all builtins with variable number of operands. */
33649 {
33655 }
33657 /* Add all builtins with rounding. */
33661 {
33667 }
33669 /* pcmpestr[im] insns. */
33673 {
33676 else
33679 }
33681 /* pcmpistr[im] insns. */
33685 {
33688 else
33691 }
33693 /* comi/ucomi insns. */
33695 {
33698 else
33701 }
33703 /* SSE */
33709 /* SSE or 3DNow!A */
33712 IX86_BUILTIN_MASKMOVQ);
33714 /* SSE2 */
33723 /* SSE3. */
33729 /* AES */
33743 /* PCLMUL */
33747 /* RDRND */
33754 IX86_BUILTIN_RDRAND64_STEP);
33756 /* AVX2 */
33758 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
33759 IX86_BUILTIN_GATHERSIV2DF);
33762 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
33763 IX86_BUILTIN_GATHERSIV4DF);
33766 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
33767 IX86_BUILTIN_GATHERDIV2DF);
33770 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
33771 IX86_BUILTIN_GATHERDIV4DF);
33774 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
33775 IX86_BUILTIN_GATHERSIV4SF);
33778 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
33779 IX86_BUILTIN_GATHERSIV8SF);
33782 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
33783 IX86_BUILTIN_GATHERDIV4SF);
33786 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
33787 IX86_BUILTIN_GATHERDIV8SF);
33790 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
33791 IX86_BUILTIN_GATHERSIV2DI);
33794 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
33795 IX86_BUILTIN_GATHERSIV4DI);
33798 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
33799 IX86_BUILTIN_GATHERDIV2DI);
33802 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
33803 IX86_BUILTIN_GATHERDIV4DI);
33806 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
33807 IX86_BUILTIN_GATHERSIV4SI);
33810 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
33811 IX86_BUILTIN_GATHERSIV8SI);
33814 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
33815 IX86_BUILTIN_GATHERDIV4SI);
33818 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
33819 IX86_BUILTIN_GATHERDIV8SI);
33822 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
33823 IX86_BUILTIN_GATHERALTSIV4DF);
33826 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
33827 IX86_BUILTIN_GATHERALTDIV8SF);
33830 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
33831 IX86_BUILTIN_GATHERALTSIV4DI);
33834 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
33835 IX86_BUILTIN_GATHERALTDIV8SI);
33837 /* AVX512F */
33839 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
33840 IX86_BUILTIN_GATHER3SIV16SF);
33843 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
33844 IX86_BUILTIN_GATHER3SIV8DF);
33847 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
33848 IX86_BUILTIN_GATHER3DIV16SF);
33851 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
33852 IX86_BUILTIN_GATHER3DIV8DF);
33855 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
33856 IX86_BUILTIN_GATHER3SIV16SI);
33859 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
33860 IX86_BUILTIN_GATHER3SIV8DI);
33863 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
33864 IX86_BUILTIN_GATHER3DIV16SI);
33867 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
33868 IX86_BUILTIN_GATHER3DIV8DI);
33871 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
33872 IX86_BUILTIN_GATHER3ALTSIV8DF);
33875 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
33876 IX86_BUILTIN_GATHER3ALTDIV16SF);
33879 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
33880 IX86_BUILTIN_GATHER3ALTSIV8DI);
33883 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
33884 IX86_BUILTIN_GATHER3ALTDIV16SI);
33887 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
33888 IX86_BUILTIN_SCATTERSIV16SF);
33891 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
33892 IX86_BUILTIN_SCATTERSIV8DF);
33895 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
33896 IX86_BUILTIN_SCATTERDIV16SF);
33899 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
33900 IX86_BUILTIN_SCATTERDIV8DF);
33903 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
33904 IX86_BUILTIN_SCATTERSIV16SI);
33907 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
33908 IX86_BUILTIN_SCATTERSIV8DI);
33911 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
33912 IX86_BUILTIN_SCATTERDIV16SI);
33915 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
33916 IX86_BUILTIN_SCATTERDIV8DI);
33918 /* AVX512VL */
33920 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_QI_INT,
33921 IX86_BUILTIN_GATHER3SIV2DF);
33924 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_QI_INT,
33925 IX86_BUILTIN_GATHER3SIV4DF);
33928 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_QI_INT,
33929 IX86_BUILTIN_GATHER3DIV2DF);
33932 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_QI_INT,
33933 IX86_BUILTIN_GATHER3DIV4DF);
33936 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_QI_INT,
33937 IX86_BUILTIN_GATHER3SIV4SF);
33940 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_QI_INT,
33941 IX86_BUILTIN_GATHER3SIV8SF);
33944 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_QI_INT,
33945 IX86_BUILTIN_GATHER3DIV4SF);
33948 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_QI_INT,
33949 IX86_BUILTIN_GATHER3DIV8SF);
33952 V2DI_FTYPE_V2DI_PCINT64_V4SI_QI_INT,
33953 IX86_BUILTIN_GATHER3SIV2DI);
33956 V4DI_FTYPE_V4DI_PCINT64_V4SI_QI_INT,
33957 IX86_BUILTIN_GATHER3SIV4DI);
33960 V2DI_FTYPE_V2DI_PCINT64_V2DI_QI_INT,
33961 IX86_BUILTIN_GATHER3DIV2DI);
33964 V4DI_FTYPE_V4DI_PCINT64_V4DI_QI_INT,
33965 IX86_BUILTIN_GATHER3DIV4DI);
33968 V4SI_FTYPE_V4SI_PCINT_V4SI_QI_INT,
33969 IX86_BUILTIN_GATHER3SIV4SI);
33972 V8SI_FTYPE_V8SI_PCINT_V8SI_QI_INT,
33973 IX86_BUILTIN_GATHER3SIV8SI);
33976 V4SI_FTYPE_V4SI_PCINT_V2DI_QI_INT,
33977 IX86_BUILTIN_GATHER3DIV4SI);
33980 V4SI_FTYPE_V4SI_PCINT_V4DI_QI_INT,
33981 IX86_BUILTIN_GATHER3DIV8SI);
33984 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
33985 IX86_BUILTIN_GATHER3ALTSIV4DF);
33988 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
33989 IX86_BUILTIN_GATHER3ALTDIV8SF);
33992 V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
33993 IX86_BUILTIN_GATHER3ALTSIV4DI);
33996 V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
33997 IX86_BUILTIN_GATHER3ALTDIV8SI);
34000 VOID_FTYPE_PFLOAT_QI_V8SI_V8SF_INT,
34001 IX86_BUILTIN_SCATTERSIV8SF);
34004 VOID_FTYPE_PFLOAT_QI_V4SI_V4SF_INT,
34005 IX86_BUILTIN_SCATTERSIV4SF);
34008 VOID_FTYPE_PDOUBLE_QI_V4SI_V4DF_INT,
34009 IX86_BUILTIN_SCATTERSIV4DF);
34012 VOID_FTYPE_PDOUBLE_QI_V4SI_V2DF_INT,
34013 IX86_BUILTIN_SCATTERSIV2DF);
34016 VOID_FTYPE_PFLOAT_QI_V4DI_V4SF_INT,
34017 IX86_BUILTIN_SCATTERDIV8SF);
34020 VOID_FTYPE_PFLOAT_QI_V2DI_V4SF_INT,
34021 IX86_BUILTIN_SCATTERDIV4SF);
34024 VOID_FTYPE_PDOUBLE_QI_V4DI_V4DF_INT,
34025 IX86_BUILTIN_SCATTERDIV4DF);
34028 VOID_FTYPE_PDOUBLE_QI_V2DI_V2DF_INT,
34029 IX86_BUILTIN_SCATTERDIV2DF);
34032 VOID_FTYPE_PINT_QI_V8SI_V8SI_INT,
34033 IX86_BUILTIN_SCATTERSIV8SI);
34036 VOID_FTYPE_PINT_QI_V4SI_V4SI_INT,
34037 IX86_BUILTIN_SCATTERSIV4SI);
34040 VOID_FTYPE_PLONGLONG_QI_V4SI_V4DI_INT,
34041 IX86_BUILTIN_SCATTERSIV4DI);
34044 VOID_FTYPE_PLONGLONG_QI_V4SI_V2DI_INT,
34045 IX86_BUILTIN_SCATTERSIV2DI);
34048 VOID_FTYPE_PINT_QI_V4DI_V4SI_INT,
34049 IX86_BUILTIN_SCATTERDIV8SI);
34052 VOID_FTYPE_PINT_QI_V2DI_V4SI_INT,
34053 IX86_BUILTIN_SCATTERDIV4SI);
34056 VOID_FTYPE_PLONGLONG_QI_V4DI_V4DI_INT,
34057 IX86_BUILTIN_SCATTERDIV4DI);
34060 VOID_FTYPE_PLONGLONG_QI_V2DI_V2DI_INT,
34061 IX86_BUILTIN_SCATTERDIV2DI);
34063 /* AVX512PF */
34065 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
34066 IX86_BUILTIN_GATHERPFDPD);
34068 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
34069 IX86_BUILTIN_GATHERPFDPS);
34071 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
34072 IX86_BUILTIN_GATHERPFQPD);
34074 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
34075 IX86_BUILTIN_GATHERPFQPS);
34077 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
34078 IX86_BUILTIN_SCATTERPFDPD);
34080 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
34081 IX86_BUILTIN_SCATTERPFDPS);
34083 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
34084 IX86_BUILTIN_SCATTERPFQPD);
34086 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
34087 IX86_BUILTIN_SCATTERPFQPS);
34089 /* SHA */
34105 /* RTM. */
34109 /* MMX access to the vec_init patterns. */
34114 V4HI_FTYPE_HI_HI_HI_HI,
34115 IX86_BUILTIN_VEC_INIT_V4HI);
34118 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
34119 IX86_BUILTIN_VEC_INIT_V8QI);
34121 /* Access to the vec_extract patterns. */
34143 /* Access to the vec_set patterns. */
34164 /* RDSEED */
34173 /* ADCX */
34178 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34179 IX86_BUILTIN_ADDCARRYX64);
34181 /* SBB */
34186 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34187 IX86_BUILTIN_SBB64);
34189 /* Read/write FLAGS. */
34199 /* CLFLUSHOPT. */
34203 /* CLWB. */
34207 /* MONITORX and MWAITX. */
34213 /* Add FMA4 multi-arg argument instructions */
34215 {
34221 }
34222 }
34224 static void
34226 {
34229 tree decl;
34235 {
34242 /* With no leaf and nothrow flags for MPX builtins
34243 abnormal edges may follow its call when setjmp
34244 presents in the function. Since we may have a lot
34245 of MPX builtins calls it causes lots of useless
34246 edges and enormous PHI nodes. To avoid this we mark
34247 MPX builtins as leaf and nothrow. */
34249 {
34251 NULL_TREE);
34253 }
34254 else
34255 {
34258 }
34259 }
34264 {
34272 {
34274 NULL_TREE);
34276 }
34277 else
34278 {
34281 }
34282 }
34283 }
34285 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
34286 to return a pointer to VERSION_DECL if the outcome of the expression
34287 formed by PREDICATE_CHAIN is true. This function will be called during
34288 version dispatch to decide which function version to execute. It returns
34289 the basic block at the end, to which more conditions can be added. */
34291 static basic_block
34294 {
34295 gimple return_stmt;
34297 gimple convert_stmt;
34298 gimple call_cond_stmt;
34299 gimple if_else_stmt;
34305 gimple_seq gseq;
34322 {
34330 }
34333 {
34348 else
34349 {
34350 gimple assign_stmt;
34351 /* Use MIN_EXPR to check if any integer is zero?.
34352 and_expr_var = min_expr <cond_var, and_expr_var> */
34360 }
34361 }
34364 integer_zero_node,
34394 }
34396 /* This parses the attribute arguments to target in DECL and determines
34397 the right builtin to use to match the platform specification.
34398 It returns the priority value for this version decl. If PREDICATE_LIST
34399 is not NULL, it stores the list of cpu features that need to be checked
34400 before dispatching this function. */
34402 static unsigned int
34404 {
34405 tree attrs;
34407 tree target_node;
34414 /* Priority of i386 features, greater value is higher priority. This is
34415 used to decide the order in which function dispatch must happen. For
34416 instance, a version specialized for SSE4.2 should be checked for dispatch
34417 before a version for SSE3, as SSE4.2 implies SSE3. */
34418 enum feature_priority
34419 {
34421 P_MMX,
34422 P_SSE,
34423 P_SSE2,
34424 P_SSE3,
34425 P_SSSE3,
34426 P_PROC_SSSE3,
34427 P_SSE4_A,
34428 P_PROC_SSE4_A,
34429 P_SSE4_1,
34430 P_SSE4_2,
34431 P_PROC_SSE4_2,
34432 P_POPCNT,
34433 P_AVX,
34434 P_PROC_AVX,
34435 P_BMI,
34436 P_PROC_BMI,
34437 P_FMA4,
34438 P_XOP,
34439 P_PROC_XOP,
34440 P_FMA,
34441 P_PROC_FMA,
34442 P_BMI2,
34443 P_AVX2,
34444 P_PROC_AVX2,
34445 P_AVX512F,
34446 P_PROC_AVX512F
34447 };
34451 /* These are the target attribute strings for which a dispatcher is
34452 available, from fold_builtin_cpu. */
34454 static struct _feature_list
34455 {
34458 }
34460 {
34478 };
34481 static unsigned int NUM_FEATURES
34497 /* Return priority zero for default function. */
34501 /* Handle arch= if specified. For priority, set it to be 1 more than
34502 the best instruction set the processor can handle. For instance, if
34503 there is a version for atom and a version for ssse3 (the highest ISA
34504 priority for atom), the atom version must be checked for dispatch
34505 before the ssse3 version. */
34507 {
34517 {
34519 {
34527 else
34528 /* We translate "arch=corei7" and "arch=nehalem" to
34529 "corei7" so that it will be mapped to M_INTEL_COREI7
34530 as cpu type to cover all M_INTEL_COREI7_XXXs. */
34537 else
34544 else
34588 }
34589 }
34594 {
34598 }
34601 {
34603 /* For a C string literal the length includes the trailing NULL. */
34606 predicate_chain);
34607 }
34608 }
34610 /* Process feature name. */
34617 {
34618 /* Do not process "arch=" */
34620 {
34623 }
34625 {
34627 {
34629 {
34634 predicate_chain);
34635 }
34636 /* Find the maximum priority feature. */
34641 }
34642 }
34644 {
34648 }
34650 }
34654 {
34657 attrs_str);
34659 }
34661 {
34664 }
34667 }
34669 /* This compares the priority of target features in function DECL1
34670 and DECL2. It returns positive value if DECL1 is higher priority,
34671 negative value if DECL2 is higher priority and 0 if they are the
34672 same. */
34674 static int
34676 {
34681 }
34683 /* V1 and V2 point to function versions with different priorities
34684 based on the target ISA. This function compares their priorities. */
34686 static int
34688 {
34690 {
34691 tree version_decl;
34692 tree predicate_chain;
34699 }
34701 /* This function generates the dispatch function for
34702 multi-versioned functions. DISPATCH_DECL is the function which will
34703 contain the dispatch logic. FNDECLS are the function choices for
34704 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
34705 in DISPATCH_DECL in which the dispatch code is generated. */
34707 static int
34711 {
34712 tree default_decl;
34713 gimple ifunc_cpu_init_stmt;
34714 gimple_seq gseq;
34716 tree ele;
34722 struct _function_version_info
34723 {
34724 tree version_decl;
34725 tree predicate_chain;
34733 /*fndecls_p is actually a vector. */
34736 /* At least one more version other than the default. */
34743 /* The first version in the vector is the default decl. */
34749 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
34750 constructors, so explicity call __builtin_cpu_init here. */
34761 {
34765 /* Get attribute string, parse it and find the right predicate decl.
34766 The predicate function could be a lengthy combination of many
34767 features, like arch-type and various isa-variants. */
34778 actual_versions++;
34779 }
34781 /* Sort the versions according to descending order of dispatch priority. The
34782 priority is based on the ISA. This is not a perfect solution. There
34783 could still be ambiguity. If more than one function version is suitable
34784 to execute, which one should be dispatched? In future, allow the user
34785 to specify a dispatch priority next to the version. */
34795 /* dispatch default version at the end. */
34801 }
34803 /* Comparator function to be used in qsort routine to sort attribute
34804 specification strings to "target". */
34806 static int
34808 {
34812 }
34814 /* ARGLIST is the argument to target attribute. This function tokenizes
34815 the comma separated arguments, sorts them and returns a string which
34816 is a unique identifier for the comma separated arguments. It also
34817 replaces non-identifier characters "=,-" with "_". */
34821 {
34822 tree arg;
34831 {
34836 argnum++;
34839 argnum++;
34840 }
34845 {
34851 }
34853 /* Replace "=,-" with "_". */
34866 {
34868 i++;
34870 }
34877 {
34882 }
34887 }
34889 /* This function changes the assembler name for functions that are
34890 versions. If DECL is a function version and has a "target"
34891 attribute, it appends the attribute string to its assembler name. */
34893 static tree
34895 {
34896 tree version_attr;
34904 "Function versions cannot be marked as gnu_inline,"
34913 /* target attribute string cannot be NULL. */
34917 version_string
34928 /* Allow assembler name to be modified if already set. */
34936 }
34938 /* This function returns true if FN1 and FN2 are versions of the same function,
34939 that is, the target strings of the function decls are different. This assumes
34940 that FN1 and FN2 have the same signature. */
34942 static bool
34944 {
34956 /* At least one function decl should have the target attribute specified. */
34960 /* Diagnose missing target attribute if one of the decls is already
34961 multi-versioned. */
34963 {
34965 {
34967 {
34970 }
34973 fn2);
34976 /* Prevent diagnosing of the same error multiple times. */
34981 }
34983 }
34988 /* The sorted target strings must be different for fn1 and fn2
34989 to be versions. */
34992 else
34999 }
35001 static tree
35003 {
35004 /* For function version, add the target suffix to the assembler name. */
35008 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
35010 #endif
35013 }
35015 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
35016 is true, append the full path name of the source file. */
35020 {
35028 /* Get a unique name that can be used globally without any chances
35029 of collision at link time. */
35039 /* Use '.' to concatenate names as it is demangler friendly. */
35042 suffix);
35043 else
35047 }
35049 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
35051 /* Make a dispatcher declaration for the multi-versioned function DECL.
35052 Calls to DECL function will be replaced with calls to the dispatcher
35053 by the front-end. Return the decl created. */
35055 static tree
35057 {
35058 tree func_decl;
35078 /* Mark this func as external, the resolver will flip it again if
35079 it gets generated. */
35081 /* This will be of type IFUNCs have to be externally visible. */
35085 }
35087 #endif
35089 /* Returns true if decl is multi-versioned and DECL is the default function,
35090 that is it is not tagged with target specific optimization. */
35092 static bool
35094 {
35103 }
35105 /* Make a dispatcher declaration for the multi-versioned function DECL.
35106 Calls to DECL function will be replaced with calls to the dispatcher
35107 by the front-end. Returns the decl of the dispatcher function. */
35109 static tree
35111 {
35133 /* Find the default version and make it the first node. */
35135 /* Go to the beginning of the chain. */
35140 {
35145 }
35147 /* If there is no default node, just return NULL. */
35151 /* Make default info the first node. */
35153 {
35160 }
35164 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
35166 {
35171 /* Right now, the dispatching is done via ifunc. */
35177 dispatcher_version_info
35182 /* Set the dispatcher for all the versions. */
35185 {
35188 }
35189 }
35190 else
35191 #endif
35192 {
35194 "multiversioning needs ifunc which is not supported "
35196 }
35199 }
35201 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
35202 it to CHAIN. */
35204 static tree
35206 {
35207 tree attr_name;
35208 tree attr_arg_name;
35209 tree attr_args;
35210 tree attr;
35217 }
35219 /* Make the resolver function decl to dispatch the versions of
35220 a multi-versioned function, DEFAULT_DECL. Create an
35221 empty basic block in the resolver and store the pointer in
35222 EMPTY_BB. Return the decl of the resolver function. */
35224 static tree
35228 {
35233 /* IFUNC's have to be globally visible. So, if the default_decl is
35234 not, then the name of the IFUNC should be made unique. */
35238 /* Append the filename to the resolver function if the versions are
35239 not externally visible. This is because the resolver function has
35240 to be externally visible for the loader to find it. So, appending
35241 the filename will prevent conflicts with a resolver function from
35242 another module which is based on the same version name. */
35245 /* The resolver function should return a (void *). */
35256 /* IFUNC resolvers have to be externally visible. */
35260 /* Resolver is not external, body is generated. */
35270 {
35271 /* In this case, each translation unit with a call to this
35272 versioned function will put out a resolver. Ensure it
35273 is comdat to keep just one copy. */
35276 }
35277 /* Build result decl and add to function_decl. */
35293 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
35297 /* Create the alias for dispatch to resolver here. */
35298 /*cgraph_create_function_alias (dispatch_decl, decl);*/
35302 }
35304 /* Generate the dispatching code body to dispatch multi-versioned function
35305 DECL. The target hook is called to process the "target" attributes and
35306 provide the code to dispatch the right function at run-time. NODE points
35307 to the dispatcher decl whose body will be created. */
35309 static tree
35311 {
35312 tree resolver_decl;
35313 basic_block empty_bb;
35314 tree default_ver_decl;
35330 /* The first version in the chain corresponds to the default version. */
35333 /* node is going to be an alias, so remove the finalized bit. */
35347 {
35349 /* Check for virtual functions here again, as by this time it should
35350 have been determined if this function needs a vtable index or
35351 not. This happens for methods in derived classes that override
35352 virtual methods in base classes but are not explicitly marked as
35353 virtual. */
35358 }
35364 }
35365 /* This builds the processor_model struct type defined in
35366 libgcc/config/i386/cpuinfo.c */
35368 static tree
35370 {
35377 /* The first 3 fields are unsigned int. */
35379 {
35385 }
35387 /* The last field is an array of unsigned integers of size one. */
35398 }
35400 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
35402 static tree
35404 {
35405 tree new_decl;
35408 VAR_DECL,
35410 type);
35423 }
35425 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
35426 into an integer defined in libgcc/config/i386/cpuinfo.c */
35428 static tree
35430 {
35436 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
35437 enum processor_features
35438 {
35440 F_MMX,
35441 F_POPCNT,
35442 F_SSE,
35443 F_SSE2,
35444 F_SSE3,
35445 F_SSSE3,
35446 F_SSE4_1,
35447 F_SSE4_2,
35448 F_AVX,
35449 F_AVX2,
35450 F_SSE4_A,
35451 F_FMA4,
35452 F_XOP,
35453 F_FMA,
35454 F_AVX512F,
35455 F_BMI,
35456 F_BMI2,
35457 F_MAX
35458 };
35460 /* These are the values for vendor types and cpu types and subtypes
35461 in cpuinfo.c. Cpu types and subtypes should be subtracted by
35462 the corresponding start value. */
35463 enum processor_model
35464 {
35466 M_AMD,
35467 M_CPU_TYPE_START,
35468 M_INTEL_BONNELL,
35469 M_INTEL_CORE2,
35470 M_INTEL_COREI7,
35471 M_AMDFAM10H,
35472 M_AMDFAM15H,
35473 M_INTEL_SILVERMONT,
35474 M_INTEL_KNL,
35475 M_AMD_BTVER1,
35476 M_AMD_BTVER2,
35477 M_CPU_SUBTYPE_START,
35478 M_INTEL_COREI7_NEHALEM,
35479 M_INTEL_COREI7_WESTMERE,
35480 M_INTEL_COREI7_SANDYBRIDGE,
35481 M_AMDFAM10H_BARCELONA,
35482 M_AMDFAM10H_SHANGHAI,
35483 M_AMDFAM10H_ISTANBUL,
35484 M_AMDFAM15H_BDVER1,
35485 M_AMDFAM15H_BDVER2,
35486 M_AMDFAM15H_BDVER3,
35487 M_AMDFAM15H_BDVER4,
35488 M_INTEL_COREI7_IVYBRIDGE,
35489 M_INTEL_COREI7_HASWELL,
35490 M_INTEL_COREI7_BROADWELL
35491 };
35493 static struct _arch_names_table
35494 {
35497 }
35499 {
35526 };
35528 static struct _isa_names_table
35529 {
35532 }
35534 {
35553 };
35567 {
35568 /* *args must be a expr that can contain other EXPRS leading to a
35569 STRING_CST. */
35571 {
35574 }
35576 }
35581 {
35582 tree ref;
35583 tree field;
35584 tree final;
35587 unsigned int NUM_ARCH_NAMES
35596 {
35600 }
35605 /* CPU types are stored in the next field. */
35608 {
35611 }
35613 /* CPU subtypes are stored in the next field. */
35615 {
35618 }
35620 /* Get the appropriate field in __cpu_model. */
35624 /* Check the value. */
35628 }
35630 {
35631 tree ref;
35632 tree array_elt;
35633 tree field;
35634 tree final;
35637 unsigned int NUM_ISA_NAMES
35646 {
35650 }
35653 /* Get the last field, which is __cpu_features. */
35657 /* Get the appropriate field: __cpu_model.__cpu_features */
35661 /* Access the 0th element of __cpu_features array. */
35666 /* Return __cpu_model.__cpu_features[0] & field_val */
35670 }
35672 }
35674 static tree
35677 {
35679 {
35684 {
35687 }
35688 }
35690 #ifdef SUBTARGET_FOLD_BUILTIN
35692 #endif
35695 }
35697 /* Make builtins to detect cpu type and features supported. NAME is
35698 the builtin name, CODE is the builtin code, and FTYPE is the function
35699 type of the builtin. */
35701 static void
35704 {
35705 tree decl;
35706 tree type;
35714 }
35716 /* Make builtins to get CPU type and features supported. The created
35717 builtins are :
35719 __builtin_cpu_init (), to detect cpu type and features,
35720 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
35721 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
35722 */
35724 static void
35726 {
35733 }
35735 /* Internal method for ix86_init_builtins. */
35737 static void
35739 {
35751 sysv_va_ref =
35754 fnvoid_va_end_ms =
35756 fnvoid_va_start_ms =
35758 fnvoid_va_end_sysv =
35760 fnvoid_va_start_sysv =
35762 NULL_TREE);
35763 fnvoid_va_copy_ms =
35765 NULL_TREE);
35766 fnvoid_va_copy_sysv =
35782 }
35784 static void
35786 {
35789 /* The __float80 type. */
35792 {
35793 /* The __float80 type. */
35798 }
35801 /* The __float128 type. */
35807 /* This macro is built by i386-builtin-types.awk. */
35808 DEFINE_BUILTIN_PRIMITIVE_TYPES;
35809 }
35811 static void
35813 {
35814 tree t;
35818 /* Builtins to get CPU type and features. */
35821 /* TFmode support builtins. */
35827 /* We will expand them to normal call if SSE isn't available since
35828 they are used by libgcc. */
35848 #ifdef SUBTARGET_INIT_BUILTINS
35849 SUBTARGET_INIT_BUILTINS;
35850 #endif
35851 }
35853 /* Return the ix86 builtin for CODE. */
35855 static tree
35857 {
35862 }
35864 /* Errors in the source file can cause expand_expr to return const0_rtx
35865 where we expect a vector. To avoid crashing, use one of the vector
35866 clear instructions. */
35867 static rtx
35869 {
35873 }
35875 /* Fixup modeless constants to fit required mode. */
35876 static rtx
35878 {
35882 }
35884 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
35886 static rtx
35888 {
35889 rtx pat;
35909 {
35913 }
35927 }
35929 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
35931 static rtx
35935 {
35936 rtx pat;
35944 rtx op;
35945 machine_mode mode;
35951 {
36031 }
36041 {
36048 {
36050 {
36053 {
36071 xop_rotl:
36073 {
36076 gcc_checking_assert
36078 }
36079 else
36080 {
36081 gcc_checking_assert
36092 }
36096 }
36097 }
36098 }
36099 else
36100 {
36101 non_constant:
36105 /* If we aren't optimizing, only allow one memory operand to be
36106 generated. */
36108 num_memory++;
36116 }
36120 }
36123 {
36134 else
36135 {
36141 }
36154 }
36161 }
36163 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
36164 insns with vec_merge. */
36166 static rtx
36168 rtx target)
36169 {
36170 rtx pat;
36197 }
36199 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
36201 static rtx
36204 {
36205 rtx pat;
36210 rtx op2;
36221 /* Swap operands if we have a comparison that isn't available in
36222 hardware. */
36244 }
36246 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
36248 static rtx
36250 rtx target)
36251 {
36252 rtx pat;
36266 /* Swap operands if we have a comparison that isn't available in
36267 hardware. */
36289 const0_rtx)));
36292 }
36294 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
36296 static rtx
36298 rtx target)
36299 {
36300 rtx pat;
36325 }
36327 static rtx
36330 {
36331 rtx pat;
36336 rtx op2;
36363 }
36365 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
36367 static rtx
36369 rtx target)
36370 {
36371 rtx pat;
36403 const0_rtx)));
36406 }
36408 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
36410 static rtx
36413 {
36414 rtx pat;
36452 {
36455 }
36458 {
36467 }
36469 {
36478 }
36479 else
36480 {
36487 }
36495 {
36500 emit_insn
36504 FLAGS_REG),
36505 const0_rtx)));
36507 }
36508 else
36510 }
36513 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
36515 static rtx
36518 {
36519 rtx pat;
36547 {
36550 }
36553 {
36562 }
36564 {
36573 }
36574 else
36575 {
36582 }
36590 {
36595 emit_insn
36599 FLAGS_REG),
36600 const0_rtx)));
36602 }
36603 else
36605 }
36607 /* Subroutine of ix86_expand_builtin to take care of insns with
36608 variable number of operands. */
36610 static rtx
36613 {
36619 struct
36620 {
36621 rtx op;
36622 machine_mode mode;
36633 {
37343 }
37348 {
37351 }
37354 {
37361 }
37362 else
37363 {
37366 }
37369 {
37376 {
37377 /* SIMD shift insns take either an 8-bit immediate or
37378 register as count. But builtin functions take int as
37379 count. If count doesn't match, we put it in register. */
37381 {
37385 }
37386 }
37389 {
37392 {
37501 {
37505 {
37508 }
37514 }
37516 }
37517 }
37518 else
37519 {
37523 /* If we aren't optimizing, only allow one memory operand to
37524 be generated. */
37526 num_memory++;
37531 {
37534 }
37535 else
37536 {
37539 }
37540 }
37544 }
37547 {
37572 }
37579 }
37581 /* Transform pattern of following layout:
37582 (parallel [
37583 set (A B)
37584 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
37585 ])
37586 into:
37587 (set (A B))
37589 Or:
37590 (parallel [ A B
37591 ...
37592 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
37593 ...
37594 ])
37595 into:
37596 (parallel [ A B ... ]) */
37598 static rtx
37600 {
37607 {
37616 }
37617 else
37618 {
37624 {
37629 }
37631 /* No more than 1 occurence was removed. */
37635 }
37636 }
37638 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
37639 with rounding. */
37640 static rtx
37643 {
37660 /* See avxintrin.h for values. */
37662 {
37666 };
37668 {
37673 };
37676 {
37679 }
37681 {
37684 }
37687 {
37690 }
37713 ? CODE_FOR_sse_ucomi_round
37720 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
37722 {
37728 }
37729 else
37730 {
37733 }
37738 set_dst,
37739 const0_rtx)));
37742 }
37744 static rtx
37747 {
37748 rtx pat;
37750 struct
37751 {
37752 rtx op;
37753 machine_mode mode;
37762 {
37845 }
37855 {
37862 {
37864 {
37866 {
37882 }
37883 }
37884 }
37886 {
37888 {
37891 }
37893 /* If there is no rounding use normal version of the pattern. */
37896 }
37897 else
37898 {
37905 {
37908 }
37909 else
37910 {
37913 }
37914 }
37918 }
37921 {
37946 }
37956 }
37958 /* Subroutine of ix86_expand_builtin to take care of special insns
37959 with variable number of operands. */
37961 static rtx
37964 {
37965 tree arg;
37969 struct
37970 {
37971 rtx op;
37972 machine_mode mode;
37981 {
38021 {
38029 }
38048 /* Reserve memory operand for target. */
38051 {
38052 /* These builtins and instructions require the memory
38053 to be properly aligned. */
38072 }
38101 {
38102 /* These builtins and instructions require the memory
38103 to be properly aligned. */
38120 }
38121 /* FALLTHRU */
38159 /* Reserve memory operand for target. */
38186 {
38187 /* These builtins and instructions require the memory
38188 to be properly aligned. */
38211 }
38224 }
38229 {
38234 {
38237 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
38238 on it. Try to improve it using get_pointer_alignment,
38239 and if the special builtin is one that requires strict
38240 mode alignment, also from it's GET_MODE_ALIGNMENT.
38241 Failure to do so could lead to ix86_legitimate_combined_insn
38242 rejecting all changes to such insns. */
38248 }
38249 else
38252 }
38253 else
38254 {
38261 }
38264 {
38273 {
38275 {
38281 else
38284 }
38285 }
38286 else
38287 {
38289 {
38290 /* This must be the memory operand. */
38293 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
38294 on it. Try to improve it using get_pointer_alignment,
38295 and if the special builtin is one that requires strict
38296 mode alignment, also from it's GET_MODE_ALIGNMENT.
38297 Failure to do so could lead to ix86_legitimate_combined_insn
38298 rejecting all changes to such insns. */
38304 }
38305 else
38306 {
38307 /* This must be register. */
38315 else
38316 {
38319 }
38320 }
38321 }
38325 }
38328 {
38343 }
38349 }
38351 /* Return the integer constant in ARG. Constrain it to be in the range
38352 of the subparts of VEC_TYPE; issue an error if not. */
38354 static int
38356 {
38361 {
38364 }
38367 }
38369 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38370 ix86_expand_vector_init. We DO have language-level syntax for this, in
38371 the form of (type){ init-list }. Except that since we can't place emms
38372 instructions from inside the compiler, we can't allow the use of MMX
38373 registers unless the user explicitly asks for it. So we do *not* define
38374 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
38375 we have builtins invoked by mmintrin.h that gives us license to emit
38376 these sorts of instructions. */
38378 static rtx
38380 {
38390 {
38393 }
38400 }
38402 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38403 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
38404 had a language-level syntax for referencing vector elements. */
38406 static rtx
38408 {
38412 rtx op0;
38432 }
38434 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38435 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
38436 a language-level syntax for referencing vector elements. */
38438 static rtx
38440 {
38464 /* OP0 is the source of these builtin functions and shouldn't be
38465 modified. Create a copy, use it and return it as target. */
38471 }
38473 /* Emit conditional move of SRC to DST with condition
38474 OP1 CODE OP2. */
38475 static void
38477 {
38478 rtx t;
38481 {
38485 }
38486 else
38487 {
38493 }
38494 }
38496 /* Choose max of DST and SRC and put it to DST. */
38497 static void
38499 {
38501 }
38503 /* Expand an expression EXP that calls a built-in function,
38504 with result going to TARGET if that's convenient
38505 (and in mode MODE if that's convenient).
38506 SUBTARGET may be used as the target for computing one of EXP's operands.
38507 IGNORE is nonzero if the value is to be ignored. */
38509 static rtx
38512 {
38522 /* For CPU builtins that can be folded, fold first and expand the fold. */
38524 {
38526 {
38527 /* Make it call __cpu_indicator_init in libgcc. */
38533 }
38536 {
38541 }
38542 }
38544 /* Determine whether the builtin function is available under the current ISA.
38545 Originally the builtin was not created if it wasn't applicable to the
38546 current ISA based on the command line switches. With function specific
38547 options, we need to check in the context of the function making the call
38548 whether it is supported. */
38551 {
38557 else
38558 {
38562 }
38564 }
38567 {
38585 /* Builtin arg1 is size of block but instruction op1 should
38586 be (size - 1). */
38677 /* If no bounds were specified for returned value,
38678 then use INIT bounds. It usually happens when
38679 some built-in function is expanded. */
38681 {
38690 }
38696 {
38699 /* Return value and lb. */
38701 /* Bounds. */
38703 /* Size. */
38710 /* Size was passed but we need to use (size - 1) as for bndmk. */
38714 /* Add LB to size and inverse to get UB. */
38724 /* We need to move bounds to memory before any computations. */
38727 else
38728 {
38731 }
38733 /* Generate mem expression to be used for access to LB and UB. */
38739 /* Compute LB. */
38744 /* Compute UB. UB is stored in 1's complement form. Therefore
38745 we also use max here. */
38754 }
38757 {
38775 /* Put first bounds to temporaries. */
38779 {
38783 }
38784 else
38785 {
38789 }
38791 /* Put second bounds to temporaries. */
38795 {
38799 }
38800 else
38801 {
38805 }
38807 /* Compute LB. */
38811 /* Compute UB. UB is stored in 1's complement form. Therefore
38812 we also use max here. */
38819 }
38822 {
38823 tree name;
38824 rtx symbol;
38842 }
38845 {
38856 /* We need to move bounds to memory first. */
38859 else
38860 {
38863 }
38865 /* Generate mem expression to access LB and load it. */
38870 }
38873 {
38884 /* We need to move bounds to memory first. */
38887 else
38888 {
38891 }
38893 /* Generate mem expression to access UB. */
38896 /* We need to inverse all bits of UB. */
38903 }
38908 ? CODE_FOR_mmx_maskmovq
38910 /* Note the arg order is different from the operand order. */
39051 {
39052 REAL_VALUE_TYPE inf;
39053 rtx tmp;
39065 }
39075 {
39081 insn = (TARGET_64BIT
39085 }
39087 {
39088 insn = (TARGET_64BIT
39092 }
39093 else
39094 {
39097 insn = (TARGET_64BIT
39105 {
39108 }
39110 }
39113 {
39114 /* mode is VOIDmode if __builtin_rd* has been called
39115 without lhs. */
39119 }
39122 {
39127 }
39140 {
39161 }
39167 {
39170 }
39196 {
39199 }
39205 {
39209 {
39248 }
39253 }
39254 else
39255 {
39257 {
39278 }
39280 }
39310 ? CODE_FOR_tbm_bextri_si
39313 {
39316 }
39317 else
39318 {
39327 }
39343 rdrand_step:
39350 {
39353 }
39359 /* Emit SImode conditional move. */
39361 {
39364 }
39367 else
39375 const0_rtx);
39394 rdseed_step:
39401 {
39404 }
39410 const0_rtx);
39439 addcarryx:
39447 /* Generate CF from input operand. */
39452 /* Gen ADCX instruction to compute X+Y+CF. */
39467 /* Store the result. */
39470 {
39473 }
39476 /* Return current CF value. */
39518 kortest:
39532 /* Emit kortest. */
39534 /* And use setcc to return result from flags. */
39792 gather_gen:
39793 rtx half;
39806 /* Note the arg order is different from the operand order. */
39817 else
39821 {
39845 else
39852 {
39857 }
39866 else
39873 {
39878 }
39882 }
39884 /* Force memory operand only with base register here. But we
39885 don't want to do it on memory operand for other builtin
39886 functions. */
39899 {
39902 }
39903 else
39904 {
39907 }
39909 {
39912 }
39914 /* Optimize. If mask is known to have all high bits set,
39915 replace op0 with pc_rtx to signal that the instruction
39916 overwrites the whole destination and doesn't use its
39917 previous contents. */
39919 {
39921 {
39924 }
39926 {
39929 {
39933 negative++;
39936 negative++;
39937 }
39940 }
39943 {
39944 /* Recognize also when mask is like:
39945 __v2df src = _mm_setzero_pd ();
39946 __v2df mask = _mm_cmpeq_pd (src, src);
39947 or
39948 __v8sf src = _mm256_setzero_ps ();
39949 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
39950 as that is a cheaper way to load all ones into
39951 a register than having to load a constant from
39952 memory. */
39955 {
39960 {
39967 /* FALLTHRU */
39977 }
39978 }
39979 }
39980 }
39988 {
40014 }
40017 scatter_gen:
40033 /* Force memory operand only with base register here. But we
40034 don't want to do it on memory operand for other builtin
40035 functions. */
40044 {
40047 }
40048 else
40049 {
40052 }
40061 {
40064 }
40073 vec_prefetch_gen:
40093 {
40096 }
40098 {
40101 }
40106 /* Force memory operand only with base register here. But we
40107 don't want to do it on memory operand for other builtin
40108 functions. */
40115 {
40118 }
40121 {
40124 }
40140 {
40143 }
40149 }
40162 {
40166 /* Emit a normal call if SSE isn't available. */
40170 }
40199 }
40201 /* This returns the target-specific builtin with code CODE if
40202 current_function_decl has visibility on this builtin, which is checked
40203 using isa flags. Returns NULL_TREE otherwise. */
40206 {
40210 /* Determine the isa flags of current_function_decl. */
40222 else
40224 }
40226 /* Return function decl for target specific builtin
40227 for given MPX builtin passed i FCODE. */
40228 static tree
40230 {
40232 {
40268 }
40271 }
40273 /* Helper function for ix86_load_bounds and ix86_store_bounds.
40275 Return an address to be used to load/store bounds for pointer
40276 passed in SLOT.
40278 SLOT_NO is an integer constant holding number of a target
40279 dependent special slot to be used in case SLOT is not a memory.
40281 SPECIAL_BASE is a pointer to be used as a base of fake address
40282 to access special slots in Bounds Table. SPECIAL_BASE[-1],
40283 SPECIAL_BASE[-2] etc. will be used as fake pointer locations. */
40285 static rtx
40287 {
40290 /* NULL slot means we pass bounds for pointer not passed to the
40291 function at all. Register slot means we pass pointer in a
40292 register. In both these cases bounds are passed via Bounds
40293 Table. Since we do not have actual pointer stored in memory,
40294 we have to use fake addresses to access Bounds Table. We
40295 start with (special_base - sizeof (void*)) and decrease this
40296 address by pointer size to get addresses for other slots. */
40298 {
40302 }
40303 /* If pointer is passed in a memory then its address is used to
40304 access Bounds Table. */
40306 {
40310 }
40311 else
40315 }
40317 /* Expand pass uses this hook to load bounds for function parameter
40318 PTR passed in SLOT in case its bounds are not passed in a register.
40320 If SLOT is a memory, then bounds are loaded as for regular pointer
40321 loaded from memory. PTR may be NULL in case SLOT is a memory.
40322 In such case value of PTR (if required) may be loaded from SLOT.
40324 If SLOT is NULL or a register then SLOT_NO is an integer constant
40325 holding number of the target dependent special slot which should be
40326 used to obtain bounds.
40328 Return loaded bounds. */
40330 static rtx
40332 {
40334 rtx addr;
40336 /* Get address to be used to access Bounds Table. Special slots start
40337 at the location of return address of the current function. */
40340 /* Load pointer value from a memory if we don't have it. */
40342 {
40345 }
40352 }
40354 /* Expand pass uses this hook to store BOUNDS for call argument PTR
40355 passed in SLOT in case BOUNDS are not passed in a register.
40357 If SLOT is a memory, then BOUNDS are stored as for regular pointer
40358 stored in memory. PTR may be NULL in case SLOT is a memory.
40359 In such case value of PTR (if required) may be loaded from SLOT.
40361 If SLOT is NULL or a register then SLOT_NO is an integer constant
40362 holding number of the target dependent special slot which should be
40363 used to store BOUNDS. */
40365 static void
40367 {
40368 rtx addr;
40370 /* Get address to be used to access Bounds Table. Special slots start
40371 at the location of return address of a called function. */
40374 /* Load pointer value from a memory if we don't have it. */
40376 {
40379 }
40388 }
40390 /* Load and return bounds returned by function in SLOT. */
40392 static rtx
40394 {
40395 rtx res;
40402 }
40404 /* Store BOUNDS returned by function into SLOT. */
40406 static void
40408 {
40411 }
40413 /* Returns a function decl for a vectorized version of the builtin function
40414 with builtin function code FN and the result vector type TYPE, or NULL_TREE
40415 if it is not available. */
40417 static tree
40419 tree type_in)
40420 {
40436 {
40439 {
40446 }
40451 {
40454 }
40459 {
40466 }
40472 /* The round insn does not trap on denormals. */
40477 {
40484 }
40490 /* The round insn does not trap on denormals. */
40495 {
40500 }
40506 /* The round insn does not trap on denormals. */
40511 {
40518 }
40524 /* The round insn does not trap on denormals. */
40529 {
40534 }
40541 {
40546 }
40553 {
40558 }
40564 /* The round insn does not trap on denormals. */
40569 {
40576 }
40582 /* The round insn does not trap on denormals. */
40587 {
40592 }
40597 {
40604 }
40609 {
40616 }
40620 /* The round insn does not trap on denormals. */
40625 {
40630 }
40634 /* The round insn does not trap on denormals. */
40639 {
40644 }
40648 /* The round insn does not trap on denormals. */
40653 {
40658 }
40662 /* The round insn does not trap on denormals. */
40667 {
40672 }
40676 /* The round insn does not trap on denormals. */
40681 {
40686 }
40690 /* The round insn does not trap on denormals. */
40695 {
40700 }
40704 /* The round insn does not trap on denormals. */
40709 {
40714 }
40718 /* The round insn does not trap on denormals. */
40723 {
40728 }
40732 /* The round insn does not trap on denormals. */
40737 {
40742 }
40746 /* The round insn does not trap on denormals. */
40751 {
40756 }
40761 {
40766 }
40771 {
40776 }
40781 }
40783 /* Dispatch to a handler for a vectorization library. */
40786 type_in);
40789 }
40791 /* Handler for an SVML-style interface to
40792 a library with vectorized intrinsics. */
40794 static tree
40796 {
40804 /* The SVML is suitable for unsafe math only. */
40817 {
40864 }
40873 {
40876 }
40877 else
40880 /* Convert to uppercase. */
40885 args;
40887 arity++;
40891 else
40894 /* Build a function declaration for the vectorized function. */
40903 }
40905 /* Handler for an ACML-style interface to
40906 a library with vectorized intrinsics. */
40908 static tree
40910 {
40918 /* The ACML is 64bits only and suitable for unsafe math only as
40919 it does not correctly support parts of IEEE with the required
40920 precision such as denormals. */
40934 {
40964 }
40971 args;
40973 arity++;
40977 else
40980 /* Build a function declaration for the vectorized function. */
40989 }
40991 /* Returns a decl of a function that implements gather load with
40992 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
40993 Return NULL_TREE if it is not available. */
40995 static tree
40998 {
41014 /* v*gather* insn sign extends index to pointer mode. */
41026 {
41030 else
41036 else
41042 else
41048 else
41054 else
41060 else
41066 else
41072 else
41078 else
41084 else
41090 else
41096 else
41101 }
41104 }
41106 /* Returns a code for a target-specific builtin that implements
41107 reciprocal of the function, or NULL_TREE if not available. */
41109 static tree
41111 {
41118 /* Machine dependent builtins. */
41120 {
41121 /* Vectorized version of sqrt to rsqrt conversion. */
41130 }
41131 else
41132 /* Normal builtins. */
41134 {
41135 /* Sqrt to rsqrt conversion. */
41141 }
41142 }
41143 \f
41144 /* Helper for avx_vpermilps256_operand et al. This is also used by
41145 the expansion functions to turn the parallel back into a mask.
41146 The return value is 0 for no match and the imm8+1 for a match. */
41148 int
41150 {
41158 /* Validate that all of the elements are constants, and not totally
41159 out of range. Copy the data into an integral array to make the
41160 subsequent checks easier. */
41162 {
41172 }
41175 {
41177 /* In the 512-bit DFmode case, we can only move elements within
41178 a 128-bit lane. First fill the second part of the mask,
41179 then fallthru. */
41181 {
41185 }
41187 {
41191 }
41192 /* FALLTHRU */
41195 /* In the 256-bit DFmode case, we can only move elements within
41196 a 128-bit lane. */
41198 {
41202 }
41204 {
41208 }
41212 /* In 512 bit SFmode case, permutation in the upper 256 bits
41213 must mirror the permutation in the lower 256-bits. */
41217 /* FALLTHRU */
41220 /* In 256 bit SFmode case, we have full freedom of
41221 movement within the low 128-bit lane, but the high 128-bit
41222 lane must mirror the exact same pattern. */
41227 /* FALLTHRU */
41231 /* In the 128-bit case, we've full freedom in the placement of
41232 the elements from the source operand. */
41239 }
41241 /* Make sure success has a non-zero value by adding one. */
41243 }
41245 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
41246 the expansion functions to turn the parallel back into a mask.
41247 The return value is 0 for no match and the imm8+1 for a match. */
41249 int
41251 {
41259 /* Validate that all of the elements are constants, and not totally
41260 out of range. Copy the data into an integral array to make the
41261 subsequent checks easier. */
41263 {
41273 }
41275 /* Validate that the halves of the permute are halves. */
41283 /* Reconstruct the mask. */
41285 {
41291 }
41293 /* Make sure success has a non-zero value by adding one. */
41295 }
41296 \f
41297 /* Return a register priority for hard reg REGNO. */
41298 static int
41300 {
41301 /* ebp and r13 as the base always wants a displacement, r12 as the
41302 base always wants an index. So discourage their usage in an
41303 address. */
41308 /* New x86-64 int registers result in bigger code size. Discourage
41309 them. */
41312 /* New x86-64 SSE registers result in bigger code size. Discourage
41313 them. */
41316 /* Usage of AX register results in smaller code. Prefer it. */
41320 }
41322 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
41324 Put float CONST_DOUBLE in the constant pool instead of fp regs.
41325 QImode must go into class Q_REGS.
41326 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
41327 movdf to do mem-to-mem moves through integer regs. */
41329 static reg_class_t
41331 {
41334 /* We're only allowed to return a subclass of CLASS. Many of the
41335 following checks fail for NO_REGS, so eliminate that early. */
41339 /* All classes can load zeros. */
41343 /* Force constants into memory if we are loading a (nonzero) constant into
41344 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
41345 instructions to load from a constant. */
41352 /* Prefer SSE regs only, if we can use them for math. */
41356 /* Floating-point constants need more complex checks. */
41358 {
41359 /* General regs can load everything. */
41363 /* Floats can load 0 and 1 plus some others. Note that we eliminated
41364 zero above. We only want to wind up preferring 80387 registers if
41365 we plan on doing computation with them. */
41368 {
41369 /* Limit class to non-sse. */
41378 }
41381 }
41383 /* Generally when we see PLUS here, it's the function invariant
41384 (plus soft-fp const_int). Which can only be computed into general
41385 regs. */
41389 /* QImode constants are easy to load, but non-constant QImode data
41390 must go into Q_REGS. */
41392 {
41398 }
41401 }
41403 /* Discourage putting floating-point values in SSE registers unless
41404 SSE math is being used, and likewise for the 387 registers. */
41405 static reg_class_t
41407 {
41410 /* Restrict the output reload class to the register bank that we are doing
41411 math on. If we would like not to return a subset of CLASS, reject this
41412 alternative: if reload cannot do this, it will still use its choice. */
41418 {
41423 else
41425 }
41428 }
41430 static reg_class_t
41433 {
41434 /* Double-word spills from general registers to non-offsettable memory
41435 references (zero-extended addresses) require special handling. */
41441 {
41443 ? CODE_FOR_reload_noff_load
41445 /* Add the cost of moving address to a temporary. */
41449 }
41451 /* QImode spills from non-QI registers require
41452 intermediate register on 32bit targets. */
41458 {
41463 else
41469 /* Return Q_REGS if the operand is in memory. */
41472 }
41474 /* This condition handles corner case where an expression involving
41475 pointers gets vectorized. We're trying to use the address of a
41476 stack slot as a vector initializer.
41478 (set (reg:V2DI 74 [ vect_cst_.2 ])
41479 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
41481 Eventually frame gets turned into sp+offset like this:
41483 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41484 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41485 (const_int 392 [0x188]))))
41487 That later gets turned into:
41489 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41490 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41491 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
41493 We'll have the following reload recorded:
41495 Reload 0: reload_in (DI) =
41496 (plus:DI (reg/f:DI 7 sp)
41497 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
41498 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41499 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
41500 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
41501 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41502 reload_reg_rtx: (reg:V2DI 22 xmm1)
41504 Which isn't going to work since SSE instructions can't handle scalar
41505 additions. Returning GENERAL_REGS forces the addition into integer
41506 register and reload can handle subsequent reloads without problems. */
41514 }
41516 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
41518 static bool
41520 {
41522 {
41538 }
41541 }
41543 /* If we are copying between general and FP registers, we need a memory
41544 location. The same is true for SSE and MMX registers.
41546 To optimize register_move_cost performance, allow inline variant.
41548 The macro can't work reliably when one of the CLASSES is class containing
41549 registers from multiple units (SSE, MMX, integer). We avoid this by never
41550 combining those units in single alternative in the machine description.
41551 Ensure that this constraint holds to avoid unexpected surprises.
41553 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
41554 enforce these sanity checks. */
41559 {
41568 {
41571 }
41576 /* Between mask and general, we have moves no larger than word size. */
41581 /* ??? This is a lie. We do have moves between mmx/general, and for
41582 mmx/sse2. But by saying we need secondary memory we discourage the
41583 register allocator from using the mmx registers unless needed. */
41588 {
41589 /* SSE1 doesn't have any direct moves from other classes. */
41593 /* If the target says that inter-unit moves are more expensive
41594 than moving through memory, then don't generate them. */
41599 /* Between SSE and general, we have moves no larger than word size. */
41602 }
41605 }
41607 bool
41610 {
41612 }
41614 /* Implement the TARGET_CLASS_MAX_NREGS hook.
41616 On the 80386, this is the size of MODE in words,
41617 except in the FP regs, where a single reg is always enough. */
41619 static unsigned char
41621 {
41623 {
41628 else
41630 }
41631 else
41632 {
41635 else
41637 }
41638 }
41640 /* Return true if the registers in CLASS cannot represent the change from
41641 modes FROM to TO. */
41643 bool
41646 {
41650 /* x87 registers can't do subreg at all, as all values are reformatted
41651 to extended precision. */
41656 {
41657 /* Vector registers do not support QI or HImode loads. If we don't
41658 disallow a change to these modes, reload will assume it's ok to
41659 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
41660 the vec_dupv4hi pattern. */
41663 }
41666 }
41668 /* Return the cost of moving data of mode M between a
41669 register and memory. A value of 2 is the default; this cost is
41670 relative to those in `REGISTER_MOVE_COST'.
41672 This function is used extensively by register_move_cost that is used to
41673 build tables at startup. Make it inline in this case.
41674 When IN is 2, return maximum of in and out move cost.
41676 If moving between registers and memory is more expensive than
41677 between two registers, you should define this macro to express the
41678 relative cost.
41680 Model also increased moving costs of QImode registers in non
41681 Q_REGS classes.
41682 */
41686 {
41689 {
41692 {
41704 }
41708 }
41710 {
41713 {
41725 }
41729 }
41731 {
41734 {
41743 }
41747 }
41749 {
41752 {
41758 else
41763 }
41764 else
41765 {
41770 else
41772 }
41779 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
41786 else
41790 }
41791 }
41793 static int
41796 {
41798 }
41801 /* Return the cost of moving data from a register in class CLASS1 to
41802 one in class CLASS2.
41804 It is not required that the cost always equal 2 when FROM is the same as TO;
41805 on some machines it is expensive to move between registers if they are not
41806 general registers. */
41808 static int
41810 reg_class_t class2_i)
41811 {
41815 /* In case we require secondary memory, compute cost of the store followed
41816 by load. In order to avoid bad register allocation choices, we need
41817 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
41820 {
41826 /* In case of copying from general_purpose_register we may emit multiple
41827 stores followed by single load causing memory size mismatch stall.
41828 Count this as arbitrarily high cost of 20. */
41833 /* In the case of FP/MMX moves, the registers actually overlap, and we
41834 have to switch modes in order to treat them differently. */
41840 }
41842 /* Moves between SSE/MMX and integer unit are expensive. */
41846 /* ??? By keeping returned value relatively high, we limit the number
41847 of moves between integer and MMX/SSE registers for all targets.
41848 Additionally, high value prevents problem with x86_modes_tieable_p(),
41849 where integer modes in MMX/SSE registers are not tieable
41850 because of missing QImode and HImode moves to, from or between
41851 MMX/SSE registers. */
41861 }
41863 /* Return TRUE if hard register REGNO can hold a value of machine-mode
41864 MODE. */
41866 bool
41868 {
41869 /* Flags and only flags can only hold CCmode values. */
41880 || (TARGET_AVX512BW
41885 {
41886 /* We implement the move patterns for all vector modes into and
41887 out of SSE registers, even when no operation instructions
41888 are available. */
41890 /* For AVX-512 we allow, regardless of regno:
41891 - XI mode
41892 - any of 512-bit wide vector mode
41893 - any scalar mode. */
41900 /* TODO check for QI/HI scalars. */
41901 /* AVX512VL allows sse regs16+ for 128/256 bit modes. */
41909 /* xmm16-xmm31 are only available for AVX-512. */
41913 /* OImode and AVX modes are available only when AVX is enabled. */
41920 }
41922 {
41923 /* We implement the move patterns for 3DNOW modes even in MMX mode,
41924 so if the register is available at all, then we can move data of
41925 the given mode into or out of it. */
41928 }
41931 {
41932 /* Take care for QImode values - they can be in non-QI regs,
41933 but then they do cause partial register stalls. */
41938 /* LRA checks if the hard register is OK for the given mode.
41939 QImode values can live in non-QI regs, so we allow all
41940 registers here. */
41944 }
41945 /* We handle both integer and floats in the general purpose registers. */
41952 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
41953 on to use that value in smaller contexts, this can easily force a
41954 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
41955 supporting DImode, allow it. */
41960 }
41962 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
41963 tieable integer mode. */
41965 static bool
41967 {
41969 {
41982 }
41983 }
41985 /* Return true if MODE1 is accessible in a register that can hold MODE2
41986 without copying. That is, all register classes that can hold MODE2
41987 can also hold MODE1. */
41989 bool
41991 {
41999 /* MODE2 being XFmode implies fp stack or general regs, which means we
42000 can tie any smaller floating point modes to it. Note that we do not
42001 tie this with TFmode. */
42005 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
42006 that we can tie it with SFmode. */
42010 /* If MODE2 is only appropriate for an SSE register, then tie with
42011 any other mode acceptable to SSE registers. */
42021 /* If MODE2 is appropriate for an MMX register, then tie
42022 with any other mode acceptable to MMX registers. */
42029 }
42031 /* Return the cost of moving between two registers of mode MODE. */
42033 static int
42035 {
42039 {
42071 }
42073 /* Return the cost of moving between two registers of mode MODE,
42074 assuming that the move will be in pieces of at most UNITS bytes. */
42076 }
42078 /* Compute a (partial) cost for rtx X. Return true if the complete
42079 cost has been computed, and false if subexpressions should be
42080 scanned. In either case, *TOTAL contains the cost result. */
42082 static bool
42085 {
42086 rtx mask;
42093 {
42097 {
42100 }
42112 && !(TARGET_64BIT
42116 /* Use 0 cost for CONST to improve its propagation. */
42119 else
42129 {
42139 }
42141 {
42144 {
42153 }
42154 }
42155 /* Fall back to (MEM (SYMBOL_REF)), since that's where
42156 it'll probably end up. Add a penalty for size. */
42163 /* The zero extensions is often completely free on x86_64, so make
42164 it as cheap as possible. */
42170 else
42182 {
42185 {
42188 }
42191 {
42194 }
42195 }
42196 /* FALLTHRU */
42203 {
42204 /* ??? Should be SSE vector operation cost. */
42205 /* At least for published AMD latencies, this really is the same
42206 as the latency for a simple fpu operation like fabs. */
42207 /* V*QImode is emulated with 1-11 insns. */
42209 {
42212 {
42213 /* For XOP we use vpshab, which requires a broadcast of the
42214 value to the variable shift insn. For constants this
42215 means a V16Q const in mem; even when we can perform the
42216 shift with one insn set the cost to prefer paddb. */
42218 {
42223 }
42225 }
42229 }
42230 else
42232 }
42234 {
42236 {
42239 else
42241 }
42242 else
42243 {
42246 else
42248 }
42249 }
42250 else
42251 {
42256 {
42257 /* Return the cost after shift-and truncation. */
42260 }
42261 else
42263 }
42267 {
42268 rtx sub;
42273 /* ??? SSE scalar/vector cost should be used here. */
42274 /* ??? Bald assumption that fma has the same cost as fmul. */
42278 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
42289 }
42293 {
42294 /* ??? SSE scalar cost should be used here. */
42297 }
42299 {
42302 }
42304 {
42305 /* ??? SSE vector cost should be used here. */
42308 }
42310 {
42311 /* V*QImode is emulated with 7-13 insns. */
42313 {
42320 }
42321 /* V*DImode is emulated with 5-8 insns. */
42323 {
42326 else
42328 }
42329 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
42330 insns, including two PMULUDQ. */
42333 else
42336 }
42337 else
42338 {
42343 {
42346 nbits++;
42347 }
42348 else
42349 /* This is arbitrary. */
42352 /* Compute costs correctly for widening multiplication. */
42356 {
42363 {
42367 else
42369 }
42373 }
42381 }
42388 /* ??? SSE cost should be used here. */
42393 /* ??? SSE vector cost should be used here. */
42395 else
42402 {
42407 {
42410 {
42418 }
42419 }
42422 {
42425 {
42431 }
42432 }
42434 {
42442 }
42443 }
42444 /* FALLTHRU */
42448 {
42449 /* ??? SSE cost should be used here. */
42452 }
42454 {
42457 }
42459 {
42460 /* ??? SSE vector cost should be used here. */
42463 }
42464 /* FALLTHRU */
42471 {
42478 }
42479 /* FALLTHRU */
42483 {
42484 /* ??? SSE cost should be used here. */
42487 }
42489 {
42492 }
42494 {
42495 /* ??? SSE vector cost should be used here. */
42498 }
42499 /* FALLTHRU */
42503 {
42504 /* ??? Should be SSE vector operation cost. */
42505 /* At least for published AMD latencies, this really is the same
42506 as the latency for a simple fpu operation like fabs. */
42508 }
42511 else
42520 {
42521 /* This kind of construct is implemented using test[bwl].
42522 Treat it as if we had an AND. */
42527 }
42529 /* The embedded comparison operand is completely free. */
42543 /* ??? SSE cost should be used here. */
42548 /* ??? SSE vector cost should be used here. */
42554 /* ??? SSE cost should be used here. */
42559 /* ??? SSE vector cost should be used here. */
42571 /* ??? Assume all of these vector manipulation patterns are
42572 recognizable. In which case they all pretty much have the
42573 same cost. */
42578 /* This is masked instruction, assume the same cost,
42579 as nonmasked variant. */
42582 else
42588 }
42589 }
42591 #if TARGET_MACHO
42595 /* Given a symbol name and its associated stub, write out the
42596 definition of the stub. */
42598 void
42600 {
42605 /* For 64-bit we shouldn't get here. */
42608 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
42625 else
42632 {
42634 }
42636 {
42637 /* PIC stub. */
42638 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42644 }
42645 else
42648 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
42649 it needs no stub-binding-helper. */
42656 {
42659 }
42660 else
42665 /* N.B. Keep the correspondence of these
42666 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
42667 old-pic/new-pic/non-pic stubs; altering this will break
42668 compatibility with existing dylibs. */
42670 {
42671 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42673 }
42674 else
42675 /* 16-byte -mdynamic-no-pic stub. */
42681 }
42684 /* Order the registers for register allocator. */
42686 void
42688 {
42692 /* First allocate the local general purpose registers. */
42697 /* Global general purpose registers. */
42702 /* x87 registers come first in case we are doing FP math
42703 using them. */
42708 /* SSE registers. */
42714 /* Extended REX SSE registers. */
42718 /* Mask register. */
42722 /* MPX bound registers. */
42726 /* x87 registers. */
42734 /* Initialize the rest of array as we do not allocate some registers
42735 at all. */
42738 }
42740 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
42741 in struct attribute_spec handler. */
42742 static tree
42744 tree args,
42747 {
42752 {
42754 name);
42757 }
42759 {
42761 name);
42764 }
42766 {
42767 tree cst;
42771 {
42774 name);
42776 }
42779 {
42782 name);
42784 }
42787 }
42790 }
42792 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
42793 struct attribute_spec.handler. */
42794 static tree
42797 {
42802 {
42804 name);
42807 }
42809 /* Can combine regparm with all attributes but fastcall. */
42811 {
42813 {
42815 }
42818 }
42820 {
42822 {
42824 }
42827 }
42830 }
42832 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
42833 struct attribute_spec.handler. */
42834 static tree
42837 {
42840 {
42843 }
42844 else
42848 {
42850 name);
42852 }
42858 {
42860 name);
42862 }
42865 }
42867 static tree
42870 {
42872 {
42874 name);
42876 }
42878 }
42880 static bool
42882 {
42886 }
42888 /* Returns an expression indicating where the this parameter is
42889 located on entry to the FUNCTION. */
42891 static rtx
42893 {
42899 {
42904 else
42907 }
42912 {
42919 {
42924 }
42925 else
42926 {
42929 {
42935 }
42936 }
42938 }
42942 }
42944 /* Determine whether x86_output_mi_thunk can succeed. */
42946 static bool
42948 const_tree function)
42949 {
42950 /* 64-bit can handle anything. */
42954 /* For 32-bit, everything's fine if we have one free register. */
42958 /* Need a free register for vcall_offset. */
42962 /* Need a free register for GOT references. */
42966 /* Otherwise ok. */
42968 }
42970 /* Output the assembler code for a thunk function. THUNK_DECL is the
42971 declaration for the thunk function itself, FUNCTION is the decl for
42972 the target function. DELTA is an immediate constant offset to be
42973 added to THIS. If VCALL_OFFSET is nonzero, the word at
42974 *(*this + vcall_offset) should be added to THIS. */
42976 static void
42979 {
42987 else
42988 {
42994 else
42996 }
43000 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
43001 pull it in now and let DELTA benefit. */
43005 {
43006 /* Put the this parameter into %eax. */
43009 }
43010 else
43013 /* Adjust the this parameter by a fixed constant. */
43015 {
43020 {
43022 {
43026 }
43027 }
43030 }
43032 /* Adjust the this parameter by a value stored in the vtable. */
43034 {
43044 /* Adjust the this parameter. */
43048 {
43052 }
43059 vcall_mem));
43060 else
43062 }
43064 /* If necessary, drop THIS back to its stack slot. */
43070 {
43073 ;
43074 else
43075 {
43079 }
43080 }
43081 else
43082 {
43084 ;
43085 #if TARGET_MACHO
43087 {
43090 }
43092 else
43093 {
43101 }
43102 }
43104 /* Our sibling call patterns do not allow memories, because we have no
43105 predicate that can distinguish between frame and non-frame memory.
43106 For our purposes here, we can get away with (ab)using a jump pattern,
43107 because we're going to do no optimization. */
43109 {
43111 {
43117 }
43118 else
43120 }
43121 else
43122 {
43124 {
43125 // CM_LARGE_PIC always uses pseudo PIC register which is
43126 // uninitialized. Since FUNCTION is local and calling it
43127 // doesn't go through PLT, we use scratch register %r11 as
43128 // PIC register and initialize it here.
43133 }
43136 {
43142 }
43148 }
43151 /* Emit just enough of rest_of_compilation to get the insns emitted.
43152 Note that use_thunk calls assemble_start_function et al. */
43158 }
43160 static void
43162 {
43166 #if TARGET_MACHO
43168 #endif
43175 }
43177 int
43179 {
43180 machine_mode mode;
43191 }
43193 /* Print call to TARGET to FILE. */
43195 static void
43197 {
43200 else
43202 }
43204 /* Output assembler code to FILE to increment profiler label # LABELNO
43205 for profiling a function entry. */
43206 void
43208 {
43212 {
43213 #ifndef NO_PROFILE_COUNTERS
43215 #endif
43219 else
43221 }
43223 {
43224 #ifndef NO_PROFILE_COUNTERS
43227 #endif
43229 }
43230 else
43231 {
43232 #ifndef NO_PROFILE_COUNTERS
43235 #endif
43237 }
43240 {
43244 }
43245 }
43247 /* We don't have exact information about the insn sizes, but we may assume
43248 quite safely that we are informed about all 1 byte insns and memory
43249 address sizes. This is enough to eliminate unnecessary padding in
43250 99% of cases. */
43252 static int
43254 {
43260 /* Discard alignments we've emit and jump instructions. */
43265 /* Important case - calls are always 5 bytes.
43266 It is common to have many calls in the row. */
43275 /* For normal instructions we rely on get_attr_length being exact,
43276 with a few exceptions. */
43278 {
43282 {
43292 /* Otherwise trust get_attr_length. */
43294 }
43299 }
43302 else
43304 }
43306 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43308 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
43309 window. */
43311 static void
43313 {
43318 /* Look for all minimal intervals of instructions containing 4 jumps.
43319 The intervals are bounded by START and INSN. NBYTES is the total
43320 size of instructions in the interval including INSN and not including
43321 START. When the NBYTES is smaller than 16 bytes, it is possible
43322 that the end of START and INSN ends up in the same 16byte page.
43324 The smallest offset in the page INSN can start is the case where START
43325 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
43326 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
43328 Don't consider asm goto as jump, while it can contain a jump, it doesn't
43329 have to, control transfer to label(s) can be performed through other
43330 means, and also we estimate minimum length of all asm stmts as 0. */
43332 {
43336 {
43342 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
43343 already in the current 16 byte page, because otherwise
43344 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
43345 bytes to reach 16 byte boundary. */
43353 {
43355 {
43360 else
43363 }
43364 }
43366 }
43375 njumps++;
43376 else
43380 {
43385 else
43388 }
43395 {
43402 }
43403 }
43404 }
43405 #endif
43407 /* AMD Athlon works faster
43408 when RET is not destination of conditional jump or directly preceded
43409 by other jump instruction. We avoid the penalty by inserting NOP just
43410 before the RET instructions in such cases. */
43411 static void
43413 {
43414 edge e;
43415 edge_iterator ei;
43418 {
43431 {
43432 edge e;
43433 edge_iterator ei;
43438 {
43441 }
43442 }
43444 {
43450 /* Empty functions get branch mispredict even when
43451 the jump destination is not visible to us. */
43454 }
43456 {
43459 }
43460 }
43461 }
43463 /* Count the minimum number of instructions in BB. Return 4 if the
43464 number of instructions >= 4. */
43466 static int
43468 {
43472 /* Count number of instructions in this block. Return 4 if the number
43473 of instructions >= 4. */
43475 {
43476 /* Only happen in exit blocks. */
43484 {
43485 insn_count++;
43488 }
43489 }
43492 }
43495 /* Count the minimum number of instructions in code path in BB.
43496 Return 4 if the number of instructions >= 4. */
43498 static int
43500 {
43501 edge e;
43502 edge_iterator ei;
43505 /* Only bother counting instructions along paths with no
43506 more than 2 basic blocks between entry and exit. Given
43507 that BB has an edge to exit, determine if a predecessor
43508 of BB has an edge from entry. If so, compute the number
43509 of instructions in the predecessor block. If there
43510 happen to be multiple such blocks, compute the minimum. */
43513 {
43514 edge prev_e;
43515 edge_iterator prev_ei;
43518 {
43521 }
43523 {
43525 {
43530 }
43531 }
43532 }
43538 }
43540 /* Pad short function to 4 instructions. */
43542 static void
43544 {
43545 edge e;
43546 edge_iterator ei;
43549 {
43552 {
43555 /* Pad short function. */
43557 {
43560 /* Find epilogue. */
43569 /* Two NOPs count as one instruction. */
43572 }
43573 }
43574 }
43575 }
43577 /* Fix up a Windows system unwinder issue. If an EH region falls through into
43578 the epilogue, the Windows system unwinder will apply epilogue logic and
43579 produce incorrect offsets. This can be avoided by adding a nop between
43580 the last insn that can throw and the first insn of the epilogue. */
43582 static void
43584 {
43585 edge e;
43586 edge_iterator ei;
43589 {
43592 /* Find the beginning of the epilogue. */
43599 /* We only care about preceding insns that can throw. */
43604 /* Do not separate calls from their debug information. */
43610 else
43614 }
43615 }
43617 /* Implement machine specific optimizations. We implement padding of returns
43618 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
43619 static void
43621 {
43622 /* We are freeing block_for_insn in the toplev to keep compatibility
43623 with old MDEP_REORGS that are not CFG based. Recompute it now. */
43630 {
43635 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43638 #endif
43639 }
43640 }
43642 /* Return nonzero when QImode register that must be represented via REX prefix
43643 is used. */
43644 bool
43646 {
43654 }
43656 /* Return true when INSN mentions register that must be encoded using REX
43657 prefix. */
43658 bool
43660 {
43663 {
43668 }
43670 }
43672 /* If profitable, negate (without causing overflow) integer constant
43673 of mode MODE at location LOC. Return true in this case. */
43674 bool
43676 {
43677 HOST_WIDE_INT val;
43683 {
43685 /* DImode x86_64 constants must fit in 32 bits. */
43698 }
43700 /* Avoid overflows. */
43706 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
43707 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
43710 {
43713 }
43716 }
43718 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
43719 optabs would emit if we didn't have TFmode patterns. */
43721 void
43723 {
43758 }
43759 \f
43765 /* Get a vector mode of the same size as the original but with elements
43766 twice as wide. This is only guaranteed to apply to integral vectors. */
43770 {
43771 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
43776 }
43778 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
43779 fill target with val via vec_duplicate. */
43781 static bool
43783 {
43786 rtx dup;
43788 /* First attempt to recognize VAL as-is. */
43792 {
43794 /* If that fails, force VAL into a register. */
43805 }
43807 }
43809 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43810 with all elements equal to VAR. Return true if successful. */
43812 static bool
43815 {
43819 {
43824 /* FALLTHRU */
43844 {
43845 rtx x;
43852 }
43865 {
43869 permute:
43877 /* Extend to SImode using a paradoxical SUBREG. */
43881 /* Insert the SImode value as low element of a V4SImode vector. */
43890 }
43901 widen:
43902 /* Replicate the value once into the next wider mode and recurse. */
43903 {
43905 rtx x;
43922 }
43928 else
43929 {
43938 }
43945 else
43946 {
43955 }
43960 }
43961 }
43963 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43964 whose ONE_VAR element is VAR, and other elements are zero. Return true
43965 if successful. */
43967 static bool
43970 {
43971 machine_mode vsimode;
43972 rtx new_target;
43977 {
43979 /* For SSE4.1, we normally use vector set. But if the second
43980 element is zero and inter-unit moves are OK, we use movq
43981 instead. */
43983 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
44005 /* Use ix86_expand_vector_set in 64bit mode only. */
44010 }
44013 {
44018 }
44021 {
44026 /* FALLTHRU */
44041 else
44048 {
44049 /* We need to shuffle the value to the correct position, so
44050 create a new pseudo to store the intermediate result. */
44052 /* With SSE2, we can use the integer shuffle insns. */
44054 {
44056 const1_rtx,
44063 }
44065 /* Otherwise convert the intermediate result to V4SFmode and
44066 use the SSE1 shuffle instructions. */
44068 {
44071 }
44072 else
44076 const1_rtx,
44085 }
44100 widen:
44104 /* Zero extend the variable element to SImode and recurse. */
44117 }
44118 }
44120 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
44121 consisting of the values in VALS. It is known that all elements
44122 except ONE_VAR are constants. Return true if successful. */
44124 static bool
44127 {
44129 machine_mode wmode;
44137 {
44142 /* For the two element vectors, it's just as easy to use
44143 the general case. */
44147 /* Use ix86_expand_vector_set in 64bit mode only. */
44169 widen:
44170 /* There's no way to set one QImode entry easily. Combine
44171 the variable value with its adjacent constant value, and
44172 promote to an HImode set. */
44175 {
44180 }
44181 else
44182 {
44185 }
44199 }
44204 }
44206 /* A subroutine of ix86_expand_vector_init_general. Use vector
44207 concatenate to handle the most general case: all values variable,
44208 and none identical. */
44210 static void
44213 {
44216 rtvec v;
44220 {
44223 {
44268 }
44280 {
44295 }
44300 {
44319 }
44324 {
44337 }
44340 half:
44341 /* FIXME: We process inputs backward to help RA. PR 36222. */
44345 {
44350 }
44354 {
44358 {
44362 }
44365 {
44369 }
44372 }
44374 {
44377 {
44381 }
44384 }
44385 else
44391 }
44392 }
44394 /* A subroutine of ix86_expand_vector_init_general. Use vector
44395 interleave to handle the most general case: all values variable,
44396 and none identical. */
44398 static void
44401 {
44410 {
44431 }
44434 {
44435 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
44439 /* Insert the SImode value as low element of V4SImode vector. */
44443 op0),
44445 const1_rtx);
44448 /* Cast the V4SImode vector back to a vector in orignal mode. */
44452 /* Load even elements into the second position. */
44456 const1_rtx));
44458 /* Cast vector to FIRST_IMODE vector. */
44461 }
44463 /* Interleave low FIRST_IMODE vectors. */
44465 {
44469 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
44472 }
44474 /* Interleave low SECOND_IMODE vectors. */
44476 {
44479 {
44484 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
44485 vector. */
44488 }
44491 /* FALLTHRU */
44498 /* Cast the SECOND_IMODE vector back to a vector on original
44499 mode. */
44505 }
44506 }
44508 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
44509 all values variable, and none identical. */
44511 static void
44514 {
44521 {
44526 /* FALLTHRU */
44554 half:
44577 quarter:
44603 /* FALLTHRU */
44609 /* Don't use ix86_expand_vector_init_interleave if we can't
44610 move from GPR to SSE register directly. */
44626 }
44628 {
44630 machine_mode inner_mode;
44640 {
44644 {
44650 else
44651 {
44656 }
44657 }
44660 }
44665 {
44671 }
44673 {
44679 }
44680 else
44682 }
44683 }
44685 /* Initialize vector TARGET via VALS. Suppress the use of MMX
44686 instructions unless MMX_OK is true. */
44688 void
44690 {
44697 rtx x;
44700 {
44710 }
44712 /* Constants are best loaded from the constant pool. */
44714 {
44717 }
44719 /* If all values are identical, broadcast the value. */
44725 /* Values where only one field is non-constant are best loaded from
44726 the pool and overwritten via move later. */
44728 {
44732 one_var))
44737 }
44740 }
44742 void
44744 {
44747 machine_mode half_mode;
44749 rtx tmp;
44751 = {
44758 };
44760 = {
44767 };
44773 {
44777 {
44782 else
44786 }
44798 else
44804 {
44807 /* For the two element vectors, we implement a VEC_CONCAT with
44808 the extraction of the other element. */
44815 else
44820 }
44829 {
44835 /* tmp = target = A B C D */
44837 /* target = A A B B */
44839 /* target = X A B B */
44841 /* target = A X C D */
44848 /* tmp = target = A B C D */
44850 /* tmp = X B C D */
44852 /* target = A B X D */
44859 /* tmp = target = A B C D */
44861 /* tmp = X B C D */
44863 /* target = A B X D */
44871 }
44879 /* Element 0 handled by vec_merge below. */
44881 {
44884 }
44887 {
44888 /* With SSE2, use integer shuffles to swap element 0 and ELT,
44889 store into element 0, then shuffle them back. */
44906 }
44907 else
44908 {
44909 /* For SSE1, we have to reuse the V4SF code. */
44913 }
44966 half:
44967 /* Compute offset. */
44973 /* Extract the half. */
44977 /* Put val in tmp at elt. */
44980 /* Put it back. */
44986 {
44989 }
44994 {
44997 }
45002 {
45005 }
45010 {
45013 }
45018 {
45021 }
45026 {
45029 }
45034 }
45037 {
45043 }
45045 {
45049 }
45050 else
45051 {
45060 }
45061 }
45063 void
45065 {
45069 rtx tmp;
45072 {
45077 /* FALLTHRU */
45090 {
45110 }
45122 {
45124 {
45144 }
45148 }
45149 else
45150 {
45151 /* For SSE1, we have to reuse the V4SF code. */
45155 }
45171 {
45175 else
45179 }
45184 {
45188 else
45192 }
45197 {
45201 else
45205 }
45210 {
45214 else
45218 }
45223 {
45227 else
45231 }
45236 {
45240 else
45244 }
45249 {
45253 else
45257 }
45262 {
45266 else
45270 }
45277 else
45286 else
45295 else
45304 else
45310 /* ??? Could extract the appropriate HImode element and shift. */
45313 }
45316 {
45320 /* Let the rtl optimizers know about the zero extension performed. */
45322 {
45325 }
45328 }
45329 else
45330 {
45337 }
45338 }
45340 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
45341 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
45342 The upper bits of DEST are undefined, though they shouldn't cause
45343 exceptions (some bits from src or all zeros are ok). */
45345 static void
45347 {
45350 {
45354 else
45372 else
45379 else
45387 {
45392 const1_rtx);
45393 }
45394 else
45395 {
45399 }
45421 else
45443 }
45447 }
45449 /* Expand a vector reduction. FN is the binary pattern to reduce;
45450 DEST is the destination; IN is the input vector. */
45452 void
45454 {
45459 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
45463 {
45466 }
45471 {
45476 else
45480 }
45481 }
45482 \f
45483 /* Target hook for scalar_mode_supported_p. */
45484 static bool
45486 {
45491 else
45493 }
45495 /* Implements target hook vector_mode_supported_p. */
45496 static bool
45498 {
45512 }
45514 /* Implement target hook libgcc_floating_mode_supported_p. */
45515 static bool
45517 {
45519 {
45526 #ifdef IX86_NO_LIBGCC_TFMODE
45528 #elif defined IX86_MAYBE_NO_LIBGCC_TFMODE
45530 #else
45532 #endif
45536 }
45537 }
45539 /* Target hook for c_mode_for_suffix. */
45540 static machine_mode
45542 {
45549 }
45551 /* Worker function for TARGET_MD_ASM_ADJUST.
45553 We do this in the new i386 backend to maintain source compatibility
45554 with the old cc0-based compiler. */
45560 {
45568 }
45570 /* Implements target vector targetm.asm.encode_section_info. */
45572 static void ATTRIBUTE_UNUSED
45574 {
45579 }
45581 /* Worker function for REVERSE_CONDITION. */
45583 enum rtx_code
45585 {
45589 }
45591 /* Output code to perform an x87 FP register move, from OPERANDS[1]
45592 to OPERANDS[0]. */
45596 {
45598 {
45601 {
45605 }
45609 }
45611 {
45615 else
45616 {
45617 /* There is no non-popping store to memory for XFmode.
45618 So if we need one, follow the store with a load. */
45621 else
45623 }
45624 }
45625 else
45627 }
45629 /* Output code to perform a conditional jump to LABEL, if C2 flag in
45630 FP status register is set. */
45632 void
45634 {
45636 rtx temp;
45641 {
45646 }
45647 else
45648 {
45653 }
45657 pc_rtx);
45662 }
45664 /* Output code to perform a log1p XFmode calculation. */
45667 {
45673 rtx test;
45679 XFmode));
45693 }
45695 /* Emit code for round calculation. */
45697 {
45704 rtx insn;
45709 {
45721 }
45724 {
45745 }
45753 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
45755 /* scratch = fxam(op1) */
45758 UNSPEC_FXAM)));
45759 /* e1 = fabs(op1) */
45762 /* e2 = e1 + 0.5 */
45766 /* res = floor(e2) */
45768 {
45772 }
45773 else
45777 {
45780 {
45787 UNSPEC_TRUNC_NOOP)));
45788 }
45804 }
45806 /* flags = signbit(a) */
45809 /* if (flags) then res = -res */
45813 pc_rtx);
45824 }
45826 /* Output code to perform a Newton-Rhapson approximation of a single precision
45827 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
45830 {
45838 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
45842 /* x0 = rcp(b) estimate */
45845 UNSPEC_RCP14)));
45846 else
45848 UNSPEC_RCP)));
45850 /* e0 = x0 * b */
45853 /* e0 = x0 * e0 */
45856 /* e1 = x0 + x0 */
45859 /* x1 = e1 - e0 */
45862 /* res = a * x1 */
45864 }
45866 /* Output code to perform a Newton-Rhapson approximation of a
45867 single precision floating point [reciprocal] square root. */
45871 {
45873 REAL_VALUE_TYPE r;
45890 {
45893 /* There is no 512-bit rsqrt. There is however rsqrt14. */
45896 }
45898 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
45899 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
45903 /* x0 = rsqrt(a) estimate */
45905 unspec)));
45907 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
45909 {
45917 /* Handle masked compare. */
45919 {
45921 /* Imm value 0x4 corresponds to not-equal comparison. */
45924 }
45925 else
45926 {
45930 }
45931 }
45933 /* e0 = x0 * a */
45935 /* e1 = e0 * x0 */
45938 /* e2 = e1 - 3. */
45944 /* e3 = -.5 * x0 */
45946 else
45947 /* e3 = -.5 * e0 */
45949 /* ret = e2 * e3 */
45951 }
45953 #ifdef TARGET_SOLARIS
45954 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
45956 static void
45958 tree decl)
45959 {
45960 /* With Binutils 2.15, the "@unwind" marker must be specified on
45961 every occurrence of the ".eh_frame" section, not just the first
45962 one. */
45965 {
45969 }
45971 #ifndef USE_GAS
45973 {
45976 }
45977 #endif
45980 }
45983 /* Return the mangling of TYPE if it is an extended fundamental type. */
45987 {
45995 {
45997 /* __float128 is "g". */
46000 /* "long double" or __float80 is "e". */
46004 }
46005 }
46007 /* For 32-bit code we can save PIC register setup by using
46008 __stack_chk_fail_local hidden function instead of calling
46009 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
46010 register, so it is better to call __stack_chk_fail directly. */
46012 static tree ATTRIBUTE_UNUSED
46014 {
46015 return TARGET_64BIT
46018 }
46020 /* Select a format to encode pointers in exception handling data. CODE
46021 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
46022 true if the symbol may be affected by dynamic relocations.
46024 ??? All x86 object file formats are capable of representing this.
46025 After all, the relocation needed is the same as for the call insn.
46026 Whether or not a particular assembler allows us to enter such, I
46027 guess we'll have to see. */
46028 int
46030 {
46032 {
46039 }
46044 }
46045 \f
46046 /* Expand copysign from SIGN to the positive value ABS_VALUE
46047 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
46048 the sign-bit. */
46049 static void
46051 {
46055 {
46056 machine_mode vmode;
46062 else
46067 {
46068 /* We need to generate a scalar mode mask in this case. */
46073 }
46074 }
46075 else
46079 }
46081 /* Expand fabs (OP0) and return a new rtx that holds the result. The
46082 mask for masking out the sign-bit is stored in *SMASK, if that is
46083 non-null. */
46084 static rtx
46086 {
46095 else
46099 {
46100 /* We need to generate a scalar mode mask in this case. */
46105 }
46112 }
46114 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
46115 swapping the operands if SWAP_OPERANDS is true. The expanded
46116 code is a forward jump to a newly created label in case the
46117 comparison is true. The generated label rtx is returned. */
46121 {
46124 rtx tmp;
46139 }
46141 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
46142 using comparison code CODE. Operands are swapped for the comparison if
46143 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
46144 static rtx
46147 {
46160 }
46162 /* Generate and return a rtx of mode MODE for 2**n where n is the number
46163 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
46164 static rtx
46166 {
46167 REAL_VALUE_TYPE TWO52r;
46168 rtx TWO52;
46175 }
46177 /* Expand SSE sequence for computing lround from OP1 storing
46178 into OP0. */
46179 void
46181 {
46182 /* C code for the stuff we're doing below:
46183 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
46184 return (long)tmp;
46185 */
46189 rtx adj;
46191 /* load nextafter (0.5, 0.0) */
46196 /* adj = copysign (0.5, op1) */
46200 /* adj = op1 + adj */
46203 /* op0 = (imode)adj */
46205 }
46207 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
46208 into OPERAND0. */
46209 void
46211 {
46212 /* C code for the stuff we're doing below (for do_floor):
46213 xi = (long)op1;
46214 xi -= (double)xi > op1 ? 1 : 0;
46215 return xi;
46216 */
46222 /* reg = (long)op1 */
46226 /* freg = (double)reg */
46230 /* ireg = (freg > op1) ? ireg - 1 : ireg */
46241 }
46243 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
46244 result in OPERAND0. */
46245 void
46247 {
46248 /* C code for the stuff we're doing below:
46249 xa = fabs (operand1);
46250 if (!isless (xa, 2**52))
46251 return operand1;
46252 xa = xa + 2**52 - 2**52;
46253 return copysign (xa, operand1);
46254 */
46262 /* xa = abs (operand1) */
46265 /* if (!isless (xa, TWO52)) goto label; */
46278 }
46280 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46281 into OPERAND0. */
46282 void
46284 {
46285 /* C code for the stuff we expand below.
46286 double xa = fabs (x), x2;
46287 if (!isless (xa, TWO52))
46288 return x;
46289 xa = xa + TWO52 - TWO52;
46290 x2 = copysign (xa, x);
46291 Compensate. Floor:
46292 if (x2 > x)
46293 x2 -= 1;
46294 Compensate. Ceil:
46295 if (x2 < x)
46296 x2 -= -1;
46297 return x2;
46298 */
46305 /* Temporary for holding the result, initialized to the input
46306 operand to ease control flow. */
46310 /* xa = abs (operand1) */
46313 /* if (!isless (xa, TWO52)) goto label; */
46316 /* xa = xa + TWO52 - TWO52; */
46320 /* xa = copysign (xa, operand1) */
46323 /* generate 1.0 or -1.0 */
46328 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46331 /* We always need to subtract here to preserve signed zero. */
46340 }
46342 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46343 into OPERAND0. */
46344 void
46346 {
46347 /* C code for the stuff we expand below.
46348 double xa = fabs (x), x2;
46349 if (!isless (xa, TWO52))
46350 return x;
46351 x2 = (double)(long)x;
46352 Compensate. Floor:
46353 if (x2 > x)
46354 x2 -= 1;
46355 Compensate. Ceil:
46356 if (x2 < x)
46357 x2 += 1;
46358 if (HONOR_SIGNED_ZEROS (mode))
46359 return copysign (x2, x);
46360 return x2;
46361 */
46368 /* Temporary for holding the result, initialized to the input
46369 operand to ease control flow. */
46373 /* xa = abs (operand1) */
46376 /* if (!isless (xa, TWO52)) goto label; */
46379 /* xa = (double)(long)x */
46384 /* generate 1.0 */
46387 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46401 }
46403 /* Expand SSE sequence for computing round from OPERAND1 storing
46404 into OPERAND0. Sequence that works without relying on DImode truncation
46405 via cvttsd2siq that is only available on 64bit targets. */
46406 void
46408 {
46409 /* C code for the stuff we expand below.
46410 double xa = fabs (x), xa2, x2;
46411 if (!isless (xa, TWO52))
46412 return x;
46413 Using the absolute value and copying back sign makes
46414 -0.0 -> -0.0 correct.
46415 xa2 = xa + TWO52 - TWO52;
46416 Compensate.
46417 dxa = xa2 - xa;
46418 if (dxa <= -0.5)
46419 xa2 += 1;
46420 else if (dxa > 0.5)
46421 xa2 -= 1;
46422 x2 = copysign (xa2, x);
46423 return x2;
46424 */
46431 /* Temporary for holding the result, initialized to the input
46432 operand to ease control flow. */
46436 /* xa = abs (operand1) */
46439 /* if (!isless (xa, TWO52)) goto label; */
46442 /* xa2 = xa + TWO52 - TWO52; */
46446 /* dxa = xa2 - xa; */
46449 /* generate 0.5, 1.0 and -0.5 */
46455 /* Compensate. */
46457 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
46461 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
46466 /* res = copysign (xa2, operand1) */
46473 }
46475 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46476 into OPERAND0. */
46477 void
46479 {
46480 /* C code for SSE variant we expand below.
46481 double xa = fabs (x), x2;
46482 if (!isless (xa, TWO52))
46483 return x;
46484 x2 = (double)(long)x;
46485 if (HONOR_SIGNED_ZEROS (mode))
46486 return copysign (x2, x);
46487 return x2;
46488 */
46495 /* Temporary for holding the result, initialized to the input
46496 operand to ease control flow. */
46500 /* xa = abs (operand1) */
46503 /* if (!isless (xa, TWO52)) goto label; */
46506 /* x = (double)(long)x */
46518 }
46520 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46521 into OPERAND0. */
46522 void
46524 {
46529 /* C code for SSE variant we expand below.
46530 double xa = fabs (x), x2;
46531 if (!isless (xa, TWO52))
46532 return x;
46533 xa2 = xa + TWO52 - TWO52;
46534 Compensate:
46535 if (xa2 > xa)
46536 xa2 -= 1.0;
46537 x2 = copysign (xa2, x);
46538 return x2;
46539 */
46543 /* Temporary for holding the result, initialized to the input
46544 operand to ease control flow. */
46548 /* xa = abs (operand1) */
46551 /* if (!isless (xa, TWO52)) goto label; */
46554 /* res = xa + TWO52 - TWO52; */
46559 /* generate 1.0 */
46562 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
46569 /* res = copysign (res, operand1) */
46576 }
46578 /* Expand SSE sequence for computing round from OPERAND1 storing
46579 into OPERAND0. */
46580 void
46582 {
46583 /* C code for the stuff we're doing below:
46584 double xa = fabs (x);
46585 if (!isless (xa, TWO52))
46586 return x;
46587 xa = (double)(long)(xa + nextafter (0.5, 0.0));
46588 return copysign (xa, x);
46589 */
46596 /* Temporary for holding the result, initialized to the input
46597 operand to ease control flow. */
46605 /* load nextafter (0.5, 0.0) */
46610 /* xa = xa + 0.5 */
46614 /* xa = (double)(int64_t)xa */
46619 /* res = copysign (xa, operand1) */
46626 }
46628 /* Expand SSE sequence for computing round
46629 from OP1 storing into OP0 using sse4 round insn. */
46630 void
46632 {
46641 {
46652 }
46654 /* round (a) = trunc (a + copysign (0.5, a)) */
46656 /* load nextafter (0.5, 0.0) */
46662 /* e1 = copysign (0.5, op1) */
46666 /* e2 = op1 + e1 */
46669 /* res = trunc (e2) */
46674 }
46675 \f
46677 /* Table of valid machine attributes. */
46679 {
46680 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
46681 affects_type_identity } */
46682 /* Stdcall attribute says callee is responsible for popping arguments
46683 if they are not variable. */
46686 /* Fastcall attribute says callee is responsible for popping arguments
46687 if they are not variable. */
46690 /* Thiscall attribute says callee is responsible for popping arguments
46691 if they are not variable. */
46694 /* Cdecl attribute says the callee is a normal C declaration */
46697 /* Regparm attribute specifies how many integer arguments are to be
46698 passed in registers. */
46701 /* Sseregparm attribute says we are using x86_64 calling conventions
46702 for FP arguments. */
46705 /* The transactional memory builtins are implicitly regparm or fastcall
46706 depending on the ABI. Override the generic do-nothing attribute that
46707 these builtins were declared with. */
46710 /* force_align_arg_pointer says this function realigns the stack at entry. */
46713 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46718 #endif
46723 #ifdef SUBTARGET_ATTRIBUTE_TABLE
46724 SUBTARGET_ATTRIBUTE_TABLE,
46725 #endif
46726 /* ms_abi and sysv_abi calling convention function attributes. */
46733 /* End element. */
46735 };
46737 /* Implement targetm.vectorize.builtin_vectorization_cost. */
46738 static int
46741 {
46745 {
46790 }
46791 }
46793 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
46794 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
46795 insn every time. */
46799 /* Initialize vselect_insn. */
46801 static void
46803 {
46805 rtx x;
46816 }
46818 /* Construct (set target (vec_select op0 (parallel perm))) and
46819 return true if that's a valid instruction in the active ISA. */
46821 static bool
46824 {
46850 }
46852 /* Similar, but generate a vec_concat from op0 and op1 as well. */
46854 static bool
46858 {
46859 machine_mode v2mode;
46860 rtx x;
46875 }
46877 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46878 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
46880 static bool
46882 {
46891 && (TARGET_AVX512BW
46893 ;
46895 ;
46897 ;
46899 ;
46900 else
46903 /* This is a blend, not a permute. Elements must stay in their
46904 respective lanes. */
46906 {
46910 }
46915 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
46916 decision should be extracted elsewhere, so that we only try that
46917 sequence once all budget==3 options have been tried. */
46924 {
46954 /* See if bytes move in pairs so we can use pblendw with
46955 an immediate argument, rather than pblendvb with a vector
46956 argument. */
46959 {
46960 use_pblendvb:
46964 finish_pblendvb:
46970 else
46975 }
46980 /* FALLTHRU */
46982 do_subreg:
46989 /* See if bytes move in pairs. If not, vpblendvb must be used. */
46993 /* See if bytes move in quadruplets. If yes, vpblendd
46994 with immediate can be used. */
46999 {
47000 /* See if bytes move the same in both lanes. If yes,
47001 vpblendw with immediate can be used. */
47006 /* Use vpblendw. */
47011 }
47013 /* Use vpblendd. */
47020 /* See if words move in pairs. If yes, vpblendd can be used. */
47025 {
47026 /* See if words move the same in both lanes. If not,
47027 vpblendvb must be used. */
47030 {
47031 /* Use vpblendvb. */
47041 }
47043 /* Use vpblendw. */
47047 }
47049 /* Use vpblendd. */
47056 /* Use vpblendd. */
47064 }
47067 {
47084 }
47088 else
47091 /* This matches five different patterns with the different modes. */
47099 }
47101 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47102 in terms of the variable form of vpermilps.
47104 Note that we will have already failed the immediate input vpermilps,
47105 which requires that the high and low part shuffle be identical; the
47106 variable form doesn't require that. */
47108 static bool
47110 {
47117 /* We can only permute within the 128-bit lane. */
47119 {
47123 }
47129 {
47132 /* Within each 128-bit lane, the elements of op0 are numbered
47133 from 0 and the elements of op1 are numbered from 4. */
47140 }
47147 }
47149 /* Return true if permutation D can be performed as VMODE permutation
47150 instead. */
47152 static bool
47154 {
47169 else
47175 }
47177 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47178 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
47180 static bool
47182 {
47191 {
47193 {
47196 {
47200 /* Use vperm2i128 insn. The pattern uses
47201 V4DImode instead of V2TImode. */
47214 }
47216 }
47217 }
47218 else
47219 {
47221 {
47224 }
47226 {
47230 /* V4DImode should be already handled through
47231 expand_vselect by vpermq instruction. */
47238 {
47239 /* First see if vpermq can be used for
47240 V8SImode/V16HImode/V32QImode. */
47242 {
47250 {
47254 }
47256 }
47258 /* Next see if vpermd can be used. */
47261 }
47262 /* Or if vpermps can be used. */
47267 {
47268 /* vpshufb only works intra lanes, it is not
47269 possible to shuffle bytes in between the lanes. */
47273 }
47274 }
47276 {
47280 /* If vpermq didn't work, vpshufb won't work either. */
47288 {
47289 /* First see if vpermq can be used for
47290 V16SImode/V32HImode/V64QImode. */
47292 {
47300 {
47304 }
47306 }
47308 /* Next see if vpermd can be used. */
47311 }
47312 /* Or if vpermps can be used. */
47316 {
47317 /* vpshufb only works intra lanes, it is not
47318 possible to shuffle bytes in between the lanes. */
47322 }
47323 }
47324 else
47326 }
47337 else
47338 {
47346 else
47350 {
47354 }
47355 }
47366 {
47381 else
47383 }
47384 else
47385 {
47388 }
47393 }
47395 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
47396 in a single instruction. */
47398 static bool
47400 {
47404 /* Check plain VEC_SELECT first, because AVX has instructions that could
47405 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
47406 input where SEL+CONCAT may not. */
47408 {
47414 {
47420 }
47423 {
47427 }
47429 {
47430 /* Use vpbroadcast{b,w,d}. */
47433 {
47476 /* For other modes prefer other shuffles this function creates. */
47478 }
47480 {
47484 }
47485 }
47490 /* There are plenty of patterns in sse.md that are written for
47491 SEL+CONCAT and are not replicated for a single op. Perhaps
47492 that should be changed, to avoid the nastiness here. */
47494 /* Recognize interleave style patterns, which means incrementing
47495 every other permutation operand. */
47497 {
47500 }
47505 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
47507 {
47509 {
47514 }
47519 }
47520 }
47522 /* Finally, try the fully general two operand permute. */
47527 /* Recognize interleave style patterns with reversed operands. */
47529 {
47531 {
47535 else
47538 }
47543 }
47545 /* Try the SSE4.1 blend variable merge instructions. */
47549 /* Try one of the AVX vpermil variable permutations. */
47553 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
47554 vpshufb, vpermd, vpermps or vpermq variable permutation. */
47558 /* Try the AVX2 vpalignr instruction. */
47562 /* Try the AVX512F vpermi2 instructions. */
47567 }
47569 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47570 in terms of a pair of pshuflw + pshufhw instructions. */
47572 static bool
47574 {
47582 /* The two permutations only operate in 64-bit lanes. */
47593 /* Emit the pshuflw. */
47600 /* Emit the pshufhw. */
47608 }
47610 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47611 the permutation using the SSSE3 palignr instruction. This succeeds
47612 when all of the elements in PERM fit within one vector and we merely
47613 need to shift them down so that a single vector permutation has a
47614 chance to succeed. If SINGLE_INSN_ONLY_P, succeed if only
47615 the vpalignr instruction itself can perform the requested permutation. */
47617 static bool
47619 {
47626 /* Even with AVX, palignr only operates on 128-bit vectors,
47627 in AVX2 palignr operates on both 128-bit lanes. */
47637 {
47641 {
47644 }
47653 }
47656 {
47665 }
47667 /* Given that we have SSSE3, we know we'll be able to implement the
47668 single operand permutation after the palignr with pshufb for
47669 128-bit vectors. If SINGLE_INSN_ONLY_P, in_order has to be computed
47670 first. */
47676 {
47681 }
47685 {
47691 else
47696 }
47702 /* For AVX2, test whether we can permute the result in one instruction. */
47704 {
47709 }
47713 {
47717 }
47718 else
47719 {
47724 shift));
47725 }
47729 /* Test for the degenerate case where the alignment by itself
47730 produces the desired permutation. */
47732 {
47735 }
47741 }
47743 /* A subroutine of ix86_expand_vec_perm_const_1. Try to simplify
47744 the permutation using the SSE4_1 pblendv instruction. Potentially
47745 reduces permutation from 2 pshufb and or to 1 pshufb and pblendv. */
47747 static bool
47749 {
47755 /* Use the same checks as in expand_vec_perm_blend. */
47759 ;
47761 ;
47763 ;
47764 else
47767 /* Figure out where permutation elements stay not in their
47768 respective lanes. */
47770 {
47774 }
47775 /* We can pblend the part where elements stay not in their
47776 respective lanes only when these elements are all in one
47777 half of a permutation.
47778 {0 1 8 3 4 5 9 7} is ok as 8, 9 are at not at their respective
47779 lanes, but both 8 and 9 >= 8
47780 {0 1 8 3 4 5 2 7} is not ok as 2 and 8 are not at their
47781 respective lanes and 8 >= 8, but 2 not. */
47787 /* First we apply one operand permutation to the part where
47788 elements stay not in their respective lanes. */
47792 else
47804 else
47809 /* Next we put permuted elements into their positions. */
47813 else
47823 }
47827 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47828 a two vector permutation into a single vector permutation by using
47829 an interleave operation to merge the vectors. */
47831 static bool
47833 {
47842 {
47845 }
47847 {
47850 /* For 32-byte modes allow even d->one_operand_p.
47851 The lack of cross-lane shuffling in some instructions
47852 might prevent a single insn shuffle. */
47855 /* If expand_vec_perm_interleave3 can expand this into
47856 a 3 insn sequence, give up and let it be expanded as
47857 3 insn sequence. While that is one insn longer,
47858 it doesn't need a memory operand and in the common
47859 case that both interleave low and high permutations
47860 with the same operands are adjacent needs 4 insns
47861 for both after CSE. */
47864 }
47865 else
47868 /* Examine from whence the elements come. */
47877 {
47880 /* Split the two input vectors into 4 halves. */
47886 /* If the elements from the low halves use interleave low, and similarly
47887 for interleave high. If the elements are from mis-matched halves, we
47888 can use shufps for V4SF/V4SI or do a DImode shuffle. */
47890 {
47891 /* punpckl* */
47893 {
47898 }
47901 }
47903 {
47904 /* punpckh* */
47906 {
47911 }
47914 }
47916 {
47917 /* shufps */
47919 {
47924 }
47926 {
47927 /* shufpd */
47932 }
47933 }
47935 {
47936 /* shufps */
47938 {
47943 }
47945 {
47946 /* shufpd */
47951 }
47952 }
47953 else
47955 }
47956 else
47957 {
47962 /* Split the two input vectors into 8 quarters. */
47968 {
47971 }
47974 {
47978 }
47980 {
47983 }
47986 {
47988 {
47989 /* Attempt to increase the likelihood that dfinal
47990 shuffle will be intra-lane. */
47992 }
47994 /* vperm2f128 or vperm2i128. */
47996 {
48001 }
48006 {
48010 {
48013 }
48014 }
48015 }
48020 {
48021 /* vpunpckl* */
48023 {
48032 }
48033 }
48036 {
48037 /* vpunpckh* */
48039 {
48048 }
48049 }
48050 else
48052 }
48054 /* Use the remapping array set up above to move the elements from their
48055 swizzled locations into their final destinations. */
48058 {
48061 /* If same_halves is true, both halves of the remapped vector are the
48062 same. Avoid cross-lane accesses if possible. */
48064 {
48067 }
48068 else
48070 }
48072 {
48075 }
48079 /* Test if the final remap can be done with a single insn. For V4SFmode or
48080 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
48093 {
48096 }
48103 }
48105 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48106 a single vector cross-lane permutation into vpermq followed
48107 by any of the single insn permutations. */
48109 static bool
48111 {
48125 {
48128 }
48131 {
48136 }
48149 {
48156 }
48163 {
48168 ;
48171 else
48173 }
48182 }
48184 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
48185 a vector permutation using two instructions, vperm2f128 resp.
48186 vperm2i128 followed by any single in-lane permutation. */
48188 static bool
48190 {
48204 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
48205 immediate. For perm < 16 the second permutation uses
48206 d->op0 as first operand, for perm >= 16 it uses d->op1
48207 as first operand. The second operand is the result of
48208 vperm2[fi]128. */
48210 {
48211 /* Ignore permutations which do not move anything cross-lane. */
48213 {
48214 /* The second shuffle for e.g. V4DFmode has
48215 0123 and ABCD operands.
48216 Ignore AB23, as 23 is already in the second lane
48217 of the first operand. */
48219 /* And 01CD, as 01 is in the first lane of the first
48220 operand. */
48222 /* And 4567, as then the vperm2[fi]128 doesn't change
48223 anything on the original 4567 second operand. */
48225 }
48226 else
48227 {
48228 /* The second shuffle for e.g. V4DFmode has
48229 4567 and ABCD operands.
48230 Ignore AB67, as 67 is already in the second lane
48231 of the first operand. */
48233 /* And 45CD, as 45 is in the first lane of the first
48234 operand. */
48236 /* And 0123, as then the vperm2[fi]128 doesn't change
48237 anything on the original 0123 first operand. */
48239 }
48242 {
48248 else
48250 }
48253 {
48257 }
48258 else
48262 {
48266 /* Found a usable second shuffle. dfirst will be
48267 vperm2f128 on d->op0 and d->op1. */
48279 /* And dsecond is some single insn shuffle, taking
48280 d->op0 and result of vperm2f128 (if perm < 16) or
48281 d->op1 and result of vperm2f128 (otherwise). */
48290 }
48292 /* For one operand, the only useful vperm2f128 permutation is 0x01
48293 aka lanes swap. */
48296 }
48299 }
48301 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48302 a two vector permutation using 2 intra-lane interleave insns
48303 and cross-lane shuffle for 32-byte vectors. */
48305 static bool
48307 {
48314 ;
48316 ;
48317 else
48332 {
48336 else
48342 else
48348 else
48354 else
48360 else
48366 else
48371 }
48375 }
48377 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
48378 a single vector permutation using a single intra-lane vector
48379 permutation, vperm2f128 swapping the lanes and vblend* insn blending
48380 the non-swapped and swapped vectors together. */
48382 static bool
48384 {
48392 || TARGET_AVX2
48401 {
48408 }
48443 }
48445 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
48446 permutation using two vperm2f128, followed by a vshufpd insn blending
48447 the two vectors together. */
48449 static bool
48451 {
48494 }
48496 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
48497 permutation with two pshufb insns and an ior. We should have already
48498 failed all two instruction sequences. */
48500 static bool
48502 {
48516 /* Generate two permutation masks. If the required element is within
48517 the given vector it is shuffled into the proper lane. If the required
48518 element is in the other vector, force a zero into the lane by setting
48519 bit 7 in the permutation mask. */
48522 {
48529 {
48532 }
48533 }
48557 }
48559 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
48560 with two vpshufb insns, vpermq and vpor. We should have already failed
48561 all two or three instruction sequences. */
48563 static bool
48565 {
48580 /* Generate two permutation masks. If the required element is within
48581 the same lane, it is shuffled in. If the required element from the
48582 other lane, force a zero by setting bit 7 in the permutation mask.
48583 In the other mask the mask has non-negative elements if element
48584 is requested from the other lane, but also moved to the other lane,
48585 so that the result of vpshufb can have the two V2TImode halves
48586 swapped. */
48589 {
48594 {
48597 }
48598 }
48607 /* Swap the 128-byte lanes of h into hp. */
48611 const1_rtx));
48628 }
48630 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48631 and extract-odd permutations of two V32QImode and V16QImode operand
48632 with two vpshufb insns, vpor and vpermq. We should have already
48633 failed all two or three instruction sequences. */
48635 static bool
48637 {
48656 /* Generate two permutation masks. In the first permutation mask
48657 the first quarter will contain indexes for the first half
48658 of the op0, the second quarter will contain bit 7 set, third quarter
48659 will contain indexes for the second half of the op0 and the
48660 last quarter bit 7 set. In the second permutation mask
48661 the first quarter will contain bit 7 set, the second quarter
48662 indexes for the first half of the op1, the third quarter bit 7 set
48663 and last quarter indexes for the second half of the op1.
48664 I.e. the first mask e.g. for V32QImode extract even will be:
48665 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
48666 (all values masked with 0xf except for -128) and second mask
48667 for extract even will be
48668 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
48671 {
48677 {
48680 }
48681 }
48700 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
48708 }
48710 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48711 and extract-odd permutations of two V16QI, V8HI, V16HI or V32QI operands
48712 with two "and" and "pack" or two "shift" and "pack" insns. We should
48713 have already failed all two instruction sequences. */
48715 static bool
48717 {
48721 machine_mode half_mode;
48730 {
48732 /* Required for "pack". */
48743 /* No check as all instructions are SSE2. */
48774 /* Only V8HI, V16QI, V16HI and V32QI modes are more profitable than
48775 general shuffles. */
48777 }
48779 /* Check that permutation is even or odd. */
48794 {
48801 }
48802 else
48803 {
48810 }
48811 /* In AVX2 for 256 bit case we need to permute pack result. */
48813 {
48819 const0_rtx,
48820 const2_rtx,
48821 const1_rtx,
48824 }
48825 else
48829 }
48831 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
48832 and extract-odd permutations. */
48834 static bool
48836 {
48840 {
48847 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48851 /* Now an unpck[lh]pd will produce the result required. */
48854 else
48860 {
48869 /* Shuffle within the 128-bit lanes to produce:
48870 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
48874 /* Shuffle the lanes around to produce:
48875 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
48879 /* Shuffle within the 128-bit lanes to produce:
48880 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
48883 /* Shuffle within the 128-bit lanes to produce:
48884 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
48887 /* Shuffle the lanes around to produce:
48888 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
48891 }
48898 /* These are always directly implementable by expand_vec_perm_1. */
48906 else
48907 {
48910 /* We need 2*log2(N)-1 operations to achieve odd/even
48911 with interleave. */
48920 else
48923 }
48935 {
48940 else
48945 {
48950 }
48952 }
48960 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48964 /* Now an vpunpck[lh]qdq will produce the result required. */
48967 else
48974 {
48979 else
48984 {
48989 }
48991 }
49002 /* Shuffle the lanes around into
49003 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
49011 /* Swap the 2nd and 3rd position in each lane into
49012 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
49018 /* Now an vpunpck[lh]qdq will produce
49019 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
49023 else
49032 }
49035 }
49037 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
49038 extract-even and extract-odd permutations. */
49040 static bool
49042 {
49054 }
49056 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
49057 permutations. We assume that expand_vec_perm_1 has already failed. */
49059 static bool
49061 {
49069 {
49072 /* These are special-cased in sse.md so that we can optionally
49073 use the vbroadcast instruction. They expand to two insns
49074 if the input happens to be in a register. */
49081 /* These are always implementable using standard shuffle patterns. */
49086 /* These can be implemented via interleave. We save one insn by
49087 stopping once we have promoted to V4SImode and then use pshufd. */
49090 do
49091 {
49092 rtx dest;
49098 {
49102 }
49109 }
49125 /* For AVX2 broadcasts of the first element vpbroadcast* or
49126 vpermq should be used by expand_vec_perm_1. */
49132 }
49133 }
49135 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
49136 broadcast permutations. */
49138 static bool
49140 {
49152 }
49154 /* Implement arbitrary permutations of two V64QImode operands
49155 will 2 vpermi2w, 2 vpshufb and one vpor instruction. */
49156 static bool
49158 {
49168 machine_mode vmode;
49174 {
49181 }
49183 /* Prepare permutations such that the first one takes care of
49184 putting the even bytes into the right positions or one higher
49185 positions (ds[0]) and the second one takes care of
49186 putting the odd bytes into the right positions or one below
49187 (ds[1]). */
49190 {
49193 {
49196 }
49197 else
49198 {
49201 }
49202 }
49224 }
49226 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
49227 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
49228 all the shorter instruction sequences. */
49230 static bool
49232 {
49248 /* Generate 4 permutation masks. If the required element is within
49249 the same lane, it is shuffled in. If the required element from the
49250 other lane, force a zero by setting bit 7 in the permutation mask.
49251 In the other mask the mask has non-negative elements if element
49252 is requested from the other lane, but also moved to the other lane,
49253 so that the result of vpshufb can have the two V2TImode halves
49254 swapped. */
49257 {
49262 }
49268 {
49276 }
49279 {
49281 {
49284 }
49291 }
49293 /* Swap the 128-byte lanes of h[X]. */
49295 {
49301 const1_rtx));
49303 }
49306 {
49308 {
49311 }
49317 }
49320 {
49322 {
49326 }
49329 }
49339 }
49341 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
49342 With all of the interface bits taken care of, perform the expansion
49343 in D and return true on success. */
49345 static bool
49347 {
49348 /* Try a single instruction expansion. */
49352 /* Try sequences of two instructions. */
49375 /* Try sequences of three instructions. */
49392 /* Try sequences of four instructions. */
49403 /* ??? Look for narrow permutations whose element orderings would
49404 allow the promotion to a wider mode. */
49406 /* ??? Look for sequences of interleave or a wider permute that place
49407 the data into the correct lanes for a half-vector shuffle like
49408 pshuf[lh]w or vpermilps. */
49410 /* ??? Look for sequences of interleave that produce the desired results.
49411 The combinatorics of punpck[lh] get pretty ugly... */
49416 /* Even longer sequences. */
49421 }
49423 /* If a permutation only uses one operand, make it clear. Returns true
49424 if the permutation references both operands. */
49426 static bool
49428 {
49436 {
49442 {
49445 }
49446 /* The elements of PERM do not suggest that only the first operand
49447 is used, but both operands are identical. Allow easier matching
49448 of the permutation by folding the permutation into the single
49449 input vector. */
49450 /* FALLTHRU */
49461 }
49464 }
49466 bool
49468 {
49473 rtx sel;
49490 {
49495 }
49502 /* If the selector says both arguments are needed, but the operands are the
49503 same, the above tried to expand with one_operand_p and flattened selector.
49504 If that didn't work, retry without one_operand_p; we succeeded with that
49505 during testing. */
49507 {
49511 }
49514 }
49516 /* Implement targetm.vectorize.vec_perm_const_ok. */
49518 static bool
49521 {
49530 /* Given sufficient ISA support we can just return true here
49531 for selected vector modes. */
49533 {
49539 /* All implementable with a single vpermi2 insn. */
49544 /* All implementable with a single vpermi2 insn. */
49549 /* Implementable with 2 vpermi2, 2 vpshufb and 1 or insn. */
49557 /* All implementable with a single vpermi2 insn. */
49562 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49567 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49574 /* All implementable with a single vpperm insn. */
49577 /* All implementable with 2 pshufb + 1 ior. */
49583 /* All implementable with shufpd or unpck[lh]pd. */
49587 }
49589 /* Extract the values from the vector CST into the permutation
49590 array in D. */
49593 {
49597 }
49599 /* For all elements from second vector, fold the elements to first. */
49604 /* Check whether the mask can be applied to the vector type. */
49607 /* Implementable with shufps or pshufd. */
49611 /* Otherwise we have to go through the motions and see if we can
49612 figure out how to generate the requested permutation. */
49623 }
49625 void
49627 {
49642 /* We'll either be able to implement the permutation directly... */
49646 /* ... or we use the special-case patterns. */
49648 }
49650 static void
49652 {
49667 {
49670 }
49672 /* Note that for AVX this isn't one instruction. */
49675 }
49678 /* Expand a vector operation CODE for a V*QImode in terms of the
49679 same operation on V*HImode. */
49681 void
49683 {
49685 machine_mode himode;
49695 {
49713 }
49717 {
49719 /* Unpack data such that we've got a source byte in each low byte of
49720 each word. We don't care what goes into the high byte of each word.
49721 Rather than trying to get zero in there, most convenient is to let
49722 it be a copy of the low byte. */
49727 /* FALLTHRU */
49739 /* FALLTHRU */
49749 }
49751 /* Perform the operation. */
49758 /* Merge the data back into the right place. */
49768 {
49769 /* For SSE2, we used an full interleave, so the desired
49770 results are in the even elements. */
49773 }
49774 else
49775 {
49776 /* For AVX, the interleave used above was not cross-lane. So the
49777 extraction is evens but with the second and third quarter swapped.
49778 Happily, that is even one insn shorter than even extraction. */
49781 }
49788 }
49790 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
49791 if op is CONST_VECTOR with all odd elements equal to their
49792 preceding element. */
49794 static bool
49796 {
49806 }
49808 void
49811 {
49814 rtx x;
49822 /* We only play even/odd games with vectors of SImode. */
49825 /* If we're looking for the odd results, shift those members down to
49826 the even slots. For some cpus this is faster than a PSHUFD. */
49828 {
49829 /* For XOP use vpmacsdqh, but only for smult, as it is only
49830 signed. */
49832 {
49836 }
49847 }
49850 {
49853 else
49855 }
49857 {
49860 else
49862 }
49867 else
49868 {
49871 /* The easiest way to implement this without PMULDQ is to go through
49872 the motions as if we are performing a full 64-bit multiply. With
49873 the exception that we need to do less shuffling of the elements. */
49875 /* Compute the sign-extension, aka highparts, of the two operands. */
49881 /* Multiply LO(A) * HI(B), and vice-versa. */
49887 /* Multiply LO(A) * LO(B). */
49891 /* Combine and shift the highparts into place. */
49896 /* Combine high and low parts. */
49899 }
49901 }
49903 void
49906 {
49912 {
49917 {
49918 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
49919 shuffle the elements once so that all elements are in the right
49920 place for immediate use: { A C B D }. */
49925 }
49926 else
49927 {
49928 /* Put the elements into place for the multiply. */
49932 }
49937 /* Shuffle the elements between the lanes. After this we
49938 have { A B E F | C D G H } for each operand. */
49948 /* Shuffle the elements within the lanes. After this we
49949 have { A A B B | C C D D } or { E E F F | G G H H }. */
49990 }
49991 }
49993 void
49995 {
50005 /* Move the results in element 2 down to element 1; we don't care
50006 what goes in elements 2 and 3. Then we can merge the parts
50007 back together with an interleave.
50009 Note that two other sequences were tried:
50010 (1) Use interleaves at the start instead of psrldq, which allows
50011 us to use a single shufps to merge things back at the end.
50012 (2) Use shufps here to combine the two vectors, then pshufd to
50013 put the elements in the correct order.
50014 In both cases the cost of the reformatting stall was too high
50015 and the overall sequence slower. */
50026 }
50028 void
50030 {
50041 {
50042 /* op1: A,B,C,D, op2: E,F,G,H */
50051 /* t1: B,A,D,C */
50058 /* t2: (B*E),(A*F),(D*G),(C*H) */
50061 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
50064 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
50067 /* Multiply lower parts and add all */
50074 }
50075 else
50076 {
50077 machine_mode nmode;
50081 {
50084 }
50086 {
50089 }
50091 {
50094 }
50095 else
50099 /* Multiply low parts. */
50103 /* Shift input vectors right 32 bits so we can multiply high parts. */
50108 /* Multiply high parts by low parts. */
50114 /* Combine and shift the highparts back. */
50118 /* Combine high and low parts. */
50120 }
50124 }
50126 /* Return 1 if control tansfer instruction INSN
50127 should be encoded with bnd prefix.
50128 If insn is NULL then return 1 when control
50129 transfer instructions should be prefixed with
50130 bnd by default for current function. */
50132 bool
50134 {
50135 /* For call insns check special flag. */
50137 {
50141 }
50143 /* All other insns are prefixed only if function is instrumented. */
50145 }
50147 /* Calculate integer abs() using only SSE2 instructions. */
50149 void
50151 {
50156 {
50157 /* For 32-bit signed integer X, the best way to calculate the absolute
50158 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
50170 /* For 16-bit signed integer X, the best way to calculate the absolute
50171 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
50179 /* For 8-bit signed integer X, the best way to calculate the absolute
50180 value of X is min ((unsigned char) X, (unsigned char) (-X)),
50181 as SSE2 provides the PMINUB insn. */
50191 }
50195 }
50197 /* Expand an insert into a vector register through pinsr insn.
50198 Return true if successful. */
50200 bool
50202 {
50210 {
50213 }
50219 {
50224 {
50231 {
50263 }
50277 }
50281 }
50282 }
50283 \f
50284 /* This function returns the calling abi specific va_list type node.
50285 It returns the FNDECL specific va_list type. */
50287 static tree
50289 {
50296 else
50298 }
50300 /* Returns the canonical va_list type specified by TYPE. If there
50301 is no valid TYPE provided, it return NULL_TREE. */
50303 static tree
50305 {
50308 /* Resolve references and pointers to va_list type. */
50317 {
50322 {
50323 /* If va_list is an array type, the argument may have decayed
50324 to a pointer type, e.g. by being passed to another function.
50325 In that case, unwrap both types so that we can compare the
50326 underlying records. */
50329 {
50332 }
50333 }
50340 {
50341 /* If va_list is an array type, the argument may have decayed
50342 to a pointer type, e.g. by being passed to another function.
50343 In that case, unwrap both types so that we can compare the
50344 underlying records. */
50347 {
50350 }
50351 }
50358 {
50359 /* If va_list is an array type, the argument may have decayed
50360 to a pointer type, e.g. by being passed to another function.
50361 In that case, unwrap both types so that we can compare the
50362 underlying records. */
50365 {
50368 }
50369 }
50373 }
50375 }
50377 /* Iterate through the target-specific builtin types for va_list.
50378 IDX denotes the iterator, *PTREE is set to the result type of
50379 the va_list builtin, and *PNAME to its internal type.
50380 Returns zero if there is no element for this index, otherwise
50381 IDX should be increased upon the next call.
50382 Note, do not iterate a base builtin's name like __builtin_va_list.
50383 Used from c_common_nodes_and_builtins. */
50385 static int
50387 {
50389 {
50391 {
50404 }
50405 }
50408 }
50410 #undef TARGET_SCHED_DISPATCH
50411 #define TARGET_SCHED_DISPATCH has_dispatch
50412 #undef TARGET_SCHED_DISPATCH_DO
50413 #define TARGET_SCHED_DISPATCH_DO do_dispatch
50414 #undef TARGET_SCHED_REASSOCIATION_WIDTH
50415 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
50416 #undef TARGET_SCHED_REORDER
50417 #define TARGET_SCHED_REORDER ix86_sched_reorder
50418 #undef TARGET_SCHED_ADJUST_PRIORITY
50419 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
50420 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
50421 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
50422 ix86_dependencies_evaluation_hook
50424 /* The size of the dispatch window is the total number of bytes of
50425 object code allowed in a window. */
50426 #define DISPATCH_WINDOW_SIZE 16
50428 /* Number of dispatch windows considered for scheduling. */
50429 #define MAX_DISPATCH_WINDOWS 3
50431 /* Maximum number of instructions in a window. */
50432 #define MAX_INSN 4
50434 /* Maximum number of immediate operands in a window. */
50435 #define MAX_IMM 4
50437 /* Maximum number of immediate bits allowed in a window. */
50438 #define MAX_IMM_SIZE 128
50440 /* Maximum number of 32 bit immediates allowed in a window. */
50441 #define MAX_IMM_32 4
50443 /* Maximum number of 64 bit immediates allowed in a window. */
50444 #define MAX_IMM_64 2
50446 /* Maximum total of loads or prefetches allowed in a window. */
50447 #define MAX_LOAD 2
50449 /* Maximum total of stores allowed in a window. */
50450 #define MAX_STORE 1
50452 #undef BIG
50453 #define BIG 100
50456 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
50459 disp_load,
50460 disp_store,
50461 disp_load_store,
50462 disp_prefetch,
50463 disp_imm,
50464 disp_imm_32,
50465 disp_imm_64,
50466 disp_branch,
50467 disp_cmp,
50468 disp_jcc,
50469 disp_last
50470 };
50472 /* Number of allowable groups in a dispatch window. It is an array
50473 indexed by dispatch_group enum. 100 is used as a big number,
50474 because the number of these kind of operations does not have any
50475 effect in dispatch window, but we need them for other reasons in
50476 the table. */
50479 };
50485 };
50487 /* Instruction path. */
50493 last_path
50494 };
50496 /* sched_insn_info defines a window to the instructions scheduled in
50497 the basic block. It contains a pointer to the insn_info table and
50498 the instruction scheduled.
50500 Windows are allocated for each basic block and are linked
50501 together. */
50503 rtx insn;
50510 /* Linked list of dispatch windows. This is a two way list of
50511 dispatch windows of a basic block. It contains information about
50512 the number of uops in the window and the total number of
50513 instructions and of bytes in the object code for this dispatch
50514 window. */
50532 /* Immediate valuse used in an insn. */
50534 {
50543 /* Get dispatch group of insn. */
50545 static enum dispatch_group
50547 {
50563 }
50565 /* Return true if insn is a compare instruction. */
50567 static bool
50569 {
50577 }
50579 /* Return true if a dispatch violation encountered. */
50581 static bool
50583 {
50587 }
50589 /* Return true if insn is a branch instruction. */
50591 static bool
50593 {
50595 }
50597 /* Return true if insn is a prefetch instruction. */
50599 static bool
50601 {
50603 }
50605 /* This function initializes a dispatch window and the list container holding a
50606 pointer to the window. */
50608 static void
50610 {
50616 else
50634 {
50640 }
50642 }
50644 /* This function allocates and initializes a dispatch window and the
50645 list container holding a pointer to the window. */
50649 {
50654 }
50656 /* This routine initializes the dispatch scheduling information. It
50657 initiates building dispatch scheduler tables and constructs the
50658 first dispatch window. */
50660 static void
50662 {
50663 /* Allocate a dispatch list and a window. */
50668 }
50670 /* This function returns true if a branch is detected. End of a basic block
50671 does not have to be a branch, but here we assume only branches end a
50672 window. */
50674 static bool
50676 {
50678 }
50680 /* This function is called when the end of a window processing is reached. */
50682 static void
50684 {
50687 {
50692 }
50694 }
50696 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
50697 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
50698 for 48 bytes of instructions. Note that these windows are not dispatch
50699 windows that their sizes are DISPATCH_WINDOW_SIZE. */
50703 {
50705 {
50710 }
50716 }
50718 /* Compute number of immediate operands of an instruction. */
50720 static void
50722 {
50729 {
50736 else
50748 {
50751 }
50756 }
50757 }
50759 /* Return total size of immediate operands of an instruction along with number
50760 of corresponding immediate-operands. It initializes its parameters to zero
50761 befor calling FIND_CONSTANT.
50762 INSN is the input instruction. IMM is the total of immediates.
50763 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
50764 bit immediates. */
50766 static int
50768 {
50776 }
50778 /* This function indicates if an operand of an instruction is an
50779 immediate. */
50781 static bool
50783 {
50792 }
50794 /* Return single or double path for instructions. */
50796 static enum insn_path
50798 {
50808 }
50810 /* Return insn dispatch group. */
50812 static enum dispatch_group
50814 {
50832 }
50834 /* Count number of GROUP restricted instructions in a dispatch
50835 window WINDOW_LIST. */
50837 static int
50839 {
50850 {
50869 }
50882 }
50884 /* This function returns true if insn satisfies dispatch rules on the
50885 last window scheduled. */
50887 static bool
50889 {
50897 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
50898 instructions should be given the lowest priority in the
50899 scheduling process in Haifa scheduler to make sure they will be
50900 scheduled in the same dispatch window as the reference to them. */
50904 /* Check nonrestricted. */
50908 /* Get last dispatch window. */
50913 {
50918 /* Window 1 is full. Go for next window. */
50920 }
50927 /* See if it fits in the first window. */
50929 {
50930 /* The first widow should have only single and double path
50931 uops. */
50937 }
50939 }
50941 /* Add an instruction INSN with NUM_UOPS micro-operations to the
50942 dispatch window WINDOW_LIST. */
50944 static void
50946 {
50964 /* Initialize window with new instruction. */
50985 {
50988 }
50989 }
50991 /* Adds a scheduled instruction, INSN, to the current dispatch window.
50992 If the total bytes of instructions or the number of instructions in
50993 the window exceed allowable, it allocates a new window. */
50995 static void
50997 {
51020 /* Get the last dispatch window. */
51028 else
51031 /* If current window is full, get a new window.
51032 Window number zero is full, if MAX_INSN uops are scheduled in it.
51033 Window number one is full, if window zero's bytes plus window
51034 one's bytes is 32, or if the bytes of the new instruction added
51035 to the total makes it greater than 48, or it has already MAX_INSN
51036 instructions in it. */
51045 {
51048 }
51051 {
51055 {
51058 }
51059 }
51061 {
51066 {
51069 }
51072 }
51073 else
51077 {
51078 /* End of basic block is reached do end-basic-block process. */
51081 }
51082 }
51084 /* Print the dispatch window, WINDOW_NUM, to FILE. */
51086 DEBUG_FUNCTION static void
51088 {
51094 else
51108 {
51111 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
51117 }
51118 }
51120 /* Print to stdout a dispatch window. */
51122 DEBUG_FUNCTION void
51124 {
51126 }
51128 /* Print INSN dispatch information to FILE. */
51130 DEBUG_FUNCTION static void
51132 {
51155 }
51157 /* Print to STDERR the status of the ready list with respect to
51158 dispatch windows. */
51160 DEBUG_FUNCTION void
51162 {
51170 }
51172 /* This routine is the driver of the dispatch scheduler. */
51174 static void
51176 {
51181 }
51183 /* Return TRUE if Dispatch Scheduling is supported. */
51185 static bool
51187 {
51191 {
51207 }
51210 }
51212 /* Implementation of reassociation_width target hook used by
51213 reassoc phase to identify parallelism level in reassociated
51214 tree. Statements tree_code is passed in OPC. Arguments type
51215 is passed in MODE.
51217 Currently parallel reassociation is enabled for Atom
51218 processors only and we set reassociation width to be 2
51219 because Atom may issue up to 2 instructions per cycle.
51221 Return value should be fixed if parallel reassociation is
51222 enabled for other processors. */
51224 static int
51226 {
51227 /* Vector part. */
51229 {
51232 else
51234 }
51236 /* Scalar part. */
51241 else
51243 }
51245 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
51246 place emms and femms instructions. */
51248 static machine_mode
51250 {
51255 {
51274 else
51286 /* FALLTHRU */
51290 }
51291 }
51293 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
51294 vectors. If AVX512F is enabled then try vectorizing with 512bit,
51295 256bit and 128bit vectors. */
51297 static unsigned int
51299 {
51302 }
51304 \f
51306 /* Return class of registers which could be used for pseudo of MODE
51307 and of class RCLASS for spilling instead of memory. Return NO_REGS
51308 if it is not possible or non-profitable. */
51309 static reg_class_t
51311 {
51317 }
51319 /* Implement targetm.vectorize.init_cost. */
51323 {
51327 }
51329 /* Implement targetm.vectorize.add_stmt_cost. */
51331 static unsigned
51335 {
51342 /* Statements in an inner loop relative to the loop being
51343 vectorized are weighted more heavily. The value here is
51344 arbitrary and could potentially be improved with analysis. */
51350 /* We need to multiply all vector stmt cost by 1.7 (estimated cost)
51351 for Silvermont as it has out of order integer pipeline and can execute
51352 2 scalar instruction per tick, but has in order SIMD pipeline. */
51355 {
51359 }
51364 }
51366 /* Implement targetm.vectorize.finish_cost. */
51368 static void
51371 {
51376 }
51378 /* Implement targetm.vectorize.destroy_cost_data. */
51380 static void
51382 {
51384 }
51386 /* Validate target specific memory model bits in VAL. */
51388 static unsigned HOST_WIDE_INT
51390 {
51397 {
51401 }
51404 {
51408 }
51410 {
51414 }
51416 }
51418 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
51419 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
51420 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
51421 or number of vecsize_mangle variants that should be emitted. */
51423 static int
51427 {
51434 {
51438 }
51443 {
51450 /* case SCmode: */
51451 /* case DCmode: */
51457 }
51459 tree t;
51463 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
51465 {
51472 /* case SCmode: */
51473 /* case DCmode: */
51479 }
51482 {
51483 /* Parse here processor clause. If not present, default to 'b'. */
51485 }
51487 {
51488 /* If the function isn't exported, we can pick up just one ISA
51489 for the clones. */
51494 else
51497 }
51498 else
51499 {
51502 }
51504 {
51517 }
51519 {
51522 else
51527 }
51529 }
51531 /* Add target attribute to SIMD clone NODE if needed. */
51533 static void
51535 {
51539 {
51554 }
51564 }
51566 /* If SIMD clone NODE can't be used in a vectorized loop
51567 in current function, return -1, otherwise return a badness of using it
51568 (0 if it is most desirable from vecsize_mangle point of view, 1
51569 slightly less desirable, etc.). */
51571 static int
51573 {
51575 {
51593 }
51594 }
51596 /* This function adjusts the unroll factor based on
51597 the hardware capabilities. For ex, bdver3 has
51598 a loop buffer which makes unrolling of smaller
51599 loops less important. This function decides the
51600 unroll factor using number of memory references
51601 (value 32 is used) as a heuristic. */
51603 static unsigned
51605 {
51614 /* Count the number of memory references within the loop body.
51615 This value determines the unrolling factor for bdver3 and bdver4
51616 architectures. */
51625 {
51630 else
51632 }
51639 }
51642 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
51644 static bool
51646 {
51647 /* For x87 floating point with standard excess precision handling,
51648 there is no adddf3 pattern (since x87 floating point only has
51649 XFmode operations) so the default hook implementation gets this
51650 wrong. */
51652 }
51654 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
51656 static void
51658 {
51663 {
51678 hold_fnclex);
51691 }
51693 {
51702 mxcsr_orig_var,
51712 ldmxcsr_hold_call);
51715 else
51720 ldmxcsr_clear_call);
51721 else
51725 stxmcsr_update_call);
51727 {
51733 exceptions_assign);
51734 }
51735 else
51740 ldmxcsr_update_call);
51741 }
51742 tree atomic_feraiseexcept
51747 atomic_feraiseexcept_call);
51748 }
51750 /* Return mode to be used for bounds or VOIDmode
51751 if bounds are not supported. */
51753 static enum machine_mode
51755 {
51756 /* Do not support pointer checker if MPX
51757 is not enabled. */
51759 {
51764 }
51767 }
51769 /* Return constant used to statically initialize constant bounds.
51771 This function is used to create special bound values. For now
51772 only INIT bounds and NONE bounds are expected. More special
51773 values may be added later. */
51775 static tree
51777 {
51783 /* This function is supposed to be used to create INIT and
51784 NONE bounds only. */
51789 }
51791 /* Generate a list of statements STMTS to initialize pointer bounds
51792 variable VAR with bounds LB and UB. Return the number of generated
51793 statements. */
51795 static int
51797 {
51815 }
51817 #if !TARGET_MACHO && !TARGET_DLLIMPORT_DECL_ATTRIBUTES
51818 /* For i386, common symbol is local only for non-PIE binaries. For
51819 x86-64, common symbol is local only for non-PIE binaries or linker
51820 supports copy reloc in PIE binaries. */
51822 static bool
51824 {
51826 (!flag_pic
51827 || (TARGET_64BIT
51829 }
51830 #endif
51832 /* If MEM is in the form of [base+offset], extract the two parts
51833 of address and set to BASE and OFFSET, otherwise return false. */
51835 static bool
51837 {
51838 rtx addr;
51848 {
51852 }
51858 {
51862 }
51865 }
51867 /* Given OPERANDS of consecutive load/store, check if we can merge
51868 them into move multiple. LOAD is true if they are load instructions.
51869 MODE is the mode of memory operands. */
51871 bool
51874 {
51879 {
51884 }
51885 else
51886 {
51891 }
51898 /* Check if the addresses are in the form of [base+offset]. */
51904 /* Check if the bases are the same. */
51911 /* Check if mem_1 is adjacent to mem_2 and mem_1 has lower address. */
51916 }
51918 /* Initialize the GCC target structure. */
51919 #undef TARGET_RETURN_IN_MEMORY
51920 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
51922 #undef TARGET_LEGITIMIZE_ADDRESS
51923 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
51925 #undef TARGET_ATTRIBUTE_TABLE
51926 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
51927 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
51928 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
51929 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
51930 # undef TARGET_MERGE_DECL_ATTRIBUTES
51931 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
51932 #endif
51934 #undef TARGET_COMP_TYPE_ATTRIBUTES
51935 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
51937 #undef TARGET_INIT_BUILTINS
51938 #define TARGET_INIT_BUILTINS ix86_init_builtins
51939 #undef TARGET_BUILTIN_DECL
51940 #define TARGET_BUILTIN_DECL ix86_builtin_decl
51941 #undef TARGET_EXPAND_BUILTIN
51942 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
51944 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
51945 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
51946 ix86_builtin_vectorized_function
51948 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
51949 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
51951 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
51952 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
51954 #undef TARGET_VECTORIZE_BUILTIN_GATHER
51955 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
51957 #undef TARGET_BUILTIN_RECIPROCAL
51958 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
51960 #undef TARGET_ASM_FUNCTION_EPILOGUE
51961 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
51963 #undef TARGET_ENCODE_SECTION_INFO
51964 #ifndef SUBTARGET_ENCODE_SECTION_INFO
51965 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
51966 #else
51967 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
51968 #endif
51970 #undef TARGET_ASM_OPEN_PAREN
51972 #undef TARGET_ASM_CLOSE_PAREN
51975 #undef TARGET_ASM_BYTE_OP
51976 #define TARGET_ASM_BYTE_OP ASM_BYTE
51978 #undef TARGET_ASM_ALIGNED_HI_OP
51979 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
51980 #undef TARGET_ASM_ALIGNED_SI_OP
51981 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
51982 #ifdef ASM_QUAD
51983 #undef TARGET_ASM_ALIGNED_DI_OP
51984 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
51985 #endif
51987 #undef TARGET_PROFILE_BEFORE_PROLOGUE
51988 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
51990 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
51991 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
51993 #undef TARGET_ASM_UNALIGNED_HI_OP
51994 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
51995 #undef TARGET_ASM_UNALIGNED_SI_OP
51996 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
51997 #undef TARGET_ASM_UNALIGNED_DI_OP
51998 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
52000 #undef TARGET_PRINT_OPERAND
52001 #define TARGET_PRINT_OPERAND ix86_print_operand
52002 #undef TARGET_PRINT_OPERAND_ADDRESS
52003 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
52004 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
52005 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
52006 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
52007 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
52009 #undef TARGET_SCHED_INIT_GLOBAL
52010 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
52011 #undef TARGET_SCHED_ADJUST_COST
52012 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
52013 #undef TARGET_SCHED_ISSUE_RATE
52014 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
52015 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
52016 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
52017 ia32_multipass_dfa_lookahead
52018 #undef TARGET_SCHED_MACRO_FUSION_P
52019 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
52020 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
52021 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
52023 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
52024 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
52026 #undef TARGET_MEMMODEL_CHECK
52027 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
52029 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
52030 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
52032 #ifdef HAVE_AS_TLS
52033 #undef TARGET_HAVE_TLS
52034 #define TARGET_HAVE_TLS true
52035 #endif
52036 #undef TARGET_CANNOT_FORCE_CONST_MEM
52037 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
52038 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
52039 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
52041 #undef TARGET_DELEGITIMIZE_ADDRESS
52042 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
52044 #undef TARGET_MS_BITFIELD_LAYOUT_P
52045 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
52047 #if TARGET_MACHO
52048 #undef TARGET_BINDS_LOCAL_P
52049 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
52050 #else
52051 #undef TARGET_BINDS_LOCAL_P
52052 #define TARGET_BINDS_LOCAL_P ix86_binds_local_p
52053 #endif
52054 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
52055 #undef TARGET_BINDS_LOCAL_P
52056 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
52057 #endif
52059 #undef TARGET_ASM_OUTPUT_MI_THUNK
52060 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
52061 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
52062 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
52064 #undef TARGET_ASM_FILE_START
52065 #define TARGET_ASM_FILE_START x86_file_start
52067 #undef TARGET_OPTION_OVERRIDE
52068 #define TARGET_OPTION_OVERRIDE ix86_option_override
52070 #undef TARGET_REGISTER_MOVE_COST
52071 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
52072 #undef TARGET_MEMORY_MOVE_COST
52073 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
52074 #undef TARGET_RTX_COSTS
52075 #define TARGET_RTX_COSTS ix86_rtx_costs
52076 #undef TARGET_ADDRESS_COST
52077 #define TARGET_ADDRESS_COST ix86_address_cost
52079 #undef TARGET_FIXED_CONDITION_CODE_REGS
52080 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
52081 #undef TARGET_CC_MODES_COMPATIBLE
52082 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
52084 #undef TARGET_MACHINE_DEPENDENT_REORG
52085 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
52087 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
52088 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
52090 #undef TARGET_BUILD_BUILTIN_VA_LIST
52091 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
52093 #undef TARGET_FOLD_BUILTIN
52094 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
52096 #undef TARGET_COMPARE_VERSION_PRIORITY
52097 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
52099 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
52100 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
52101 ix86_generate_version_dispatcher_body
52103 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
52104 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
52105 ix86_get_function_versions_dispatcher
52107 #undef TARGET_ENUM_VA_LIST_P
52108 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
52110 #undef TARGET_FN_ABI_VA_LIST
52111 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
52113 #undef TARGET_CANONICAL_VA_LIST_TYPE
52114 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
52116 #undef TARGET_EXPAND_BUILTIN_VA_START
52117 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
52119 #undef TARGET_MD_ASM_ADJUST
52120 #define TARGET_MD_ASM_ADJUST ix86_md_asm_adjust
52122 #undef TARGET_PROMOTE_PROTOTYPES
52123 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
52124 #undef TARGET_SETUP_INCOMING_VARARGS
52125 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
52126 #undef TARGET_MUST_PASS_IN_STACK
52127 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
52128 #undef TARGET_FUNCTION_ARG_ADVANCE
52129 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
52130 #undef TARGET_FUNCTION_ARG
52131 #define TARGET_FUNCTION_ARG ix86_function_arg
52132 #undef TARGET_INIT_PIC_REG
52133 #define TARGET_INIT_PIC_REG ix86_init_pic_reg
52134 #undef TARGET_USE_PSEUDO_PIC_REG
52135 #define TARGET_USE_PSEUDO_PIC_REG ix86_use_pseudo_pic_reg
52136 #undef TARGET_FUNCTION_ARG_BOUNDARY
52137 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
52138 #undef TARGET_PASS_BY_REFERENCE
52139 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
52140 #undef TARGET_INTERNAL_ARG_POINTER
52141 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
52142 #undef TARGET_UPDATE_STACK_BOUNDARY
52143 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
52144 #undef TARGET_GET_DRAP_RTX
52145 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
52146 #undef TARGET_STRICT_ARGUMENT_NAMING
52147 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
52148 #undef TARGET_STATIC_CHAIN
52149 #define TARGET_STATIC_CHAIN ix86_static_chain
52150 #undef TARGET_TRAMPOLINE_INIT
52151 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
52152 #undef TARGET_RETURN_POPS_ARGS
52153 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
52155 #undef TARGET_LEGITIMATE_COMBINED_INSN
52156 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
52158 #undef TARGET_ASAN_SHADOW_OFFSET
52159 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
52161 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
52162 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
52164 #undef TARGET_SCALAR_MODE_SUPPORTED_P
52165 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
52167 #undef TARGET_VECTOR_MODE_SUPPORTED_P
52168 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
52170 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
52171 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
52172 ix86_libgcc_floating_mode_supported_p
52174 #undef TARGET_C_MODE_FOR_SUFFIX
52175 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
52177 #ifdef HAVE_AS_TLS
52178 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
52179 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
52180 #endif
52182 #ifdef SUBTARGET_INSERT_ATTRIBUTES
52183 #undef TARGET_INSERT_ATTRIBUTES
52184 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
52185 #endif
52187 #undef TARGET_MANGLE_TYPE
52188 #define TARGET_MANGLE_TYPE ix86_mangle_type
52190 #if !TARGET_MACHO
52191 #undef TARGET_STACK_PROTECT_FAIL
52192 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
52193 #endif
52195 #undef TARGET_FUNCTION_VALUE
52196 #define TARGET_FUNCTION_VALUE ix86_function_value
52198 #undef TARGET_FUNCTION_VALUE_REGNO_P
52199 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
52201 #undef TARGET_PROMOTE_FUNCTION_MODE
52202 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
52204 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
52205 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ix86_override_options_after_change
52207 #undef TARGET_MEMBER_TYPE_FORCES_BLK
52208 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
52210 #undef TARGET_INSTANTIATE_DECLS
52211 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
52213 #undef TARGET_SECONDARY_RELOAD
52214 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
52216 #undef TARGET_CLASS_MAX_NREGS
52217 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
52219 #undef TARGET_PREFERRED_RELOAD_CLASS
52220 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
52221 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
52222 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
52223 #undef TARGET_CLASS_LIKELY_SPILLED_P
52224 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
52226 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
52227 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
52228 ix86_builtin_vectorization_cost
52229 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
52230 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
52231 ix86_vectorize_vec_perm_const_ok
52232 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
52233 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
52234 ix86_preferred_simd_mode
52235 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
52236 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
52237 ix86_autovectorize_vector_sizes
52238 #undef TARGET_VECTORIZE_INIT_COST
52239 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
52240 #undef TARGET_VECTORIZE_ADD_STMT_COST
52241 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
52242 #undef TARGET_VECTORIZE_FINISH_COST
52243 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
52244 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
52245 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
52247 #undef TARGET_SET_CURRENT_FUNCTION
52248 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
52250 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
52251 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
52253 #undef TARGET_OPTION_SAVE
52254 #define TARGET_OPTION_SAVE ix86_function_specific_save
52256 #undef TARGET_OPTION_RESTORE
52257 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
52259 #undef TARGET_OPTION_POST_STREAM_IN
52260 #define TARGET_OPTION_POST_STREAM_IN ix86_function_specific_post_stream_in
52262 #undef TARGET_OPTION_PRINT
52263 #define TARGET_OPTION_PRINT ix86_function_specific_print
52265 #undef TARGET_OPTION_FUNCTION_VERSIONS
52266 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
52268 #undef TARGET_CAN_INLINE_P
52269 #define TARGET_CAN_INLINE_P ix86_can_inline_p
52271 #undef TARGET_EXPAND_TO_RTL_HOOK
52272 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
52274 #undef TARGET_LEGITIMATE_ADDRESS_P
52275 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
52277 #undef TARGET_LRA_P
52278 #define TARGET_LRA_P hook_bool_void_true
52280 #undef TARGET_REGISTER_PRIORITY
52281 #define TARGET_REGISTER_PRIORITY ix86_register_priority
52283 #undef TARGET_REGISTER_USAGE_LEVELING_P
52284 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
52286 #undef TARGET_LEGITIMATE_CONSTANT_P
52287 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
52289 #undef TARGET_FRAME_POINTER_REQUIRED
52290 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
52292 #undef TARGET_CAN_ELIMINATE
52293 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
52295 #undef TARGET_EXTRA_LIVE_ON_ENTRY
52296 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
52298 #undef TARGET_ASM_CODE_END
52299 #define TARGET_ASM_CODE_END ix86_code_end
52301 #undef TARGET_CONDITIONAL_REGISTER_USAGE
52302 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
52304 #if TARGET_MACHO
52305 #undef TARGET_INIT_LIBFUNCS
52306 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
52307 #endif
52309 #undef TARGET_LOOP_UNROLL_ADJUST
52310 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
52312 #undef TARGET_SPILL_CLASS
52313 #define TARGET_SPILL_CLASS ix86_spill_class
52315 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
52316 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
52317 ix86_simd_clone_compute_vecsize_and_simdlen
52319 #undef TARGET_SIMD_CLONE_ADJUST
52320 #define TARGET_SIMD_CLONE_ADJUST \
52321 ix86_simd_clone_adjust
52323 #undef TARGET_SIMD_CLONE_USABLE
52324 #define TARGET_SIMD_CLONE_USABLE \
52325 ix86_simd_clone_usable
52327 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
52328 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
52329 ix86_float_exceptions_rounding_supported_p
52331 #undef TARGET_MODE_EMIT
52332 #define TARGET_MODE_EMIT ix86_emit_mode_set
52334 #undef TARGET_MODE_NEEDED
52335 #define TARGET_MODE_NEEDED ix86_mode_needed
52337 #undef TARGET_MODE_AFTER
52338 #define TARGET_MODE_AFTER ix86_mode_after
52340 #undef TARGET_MODE_ENTRY
52341 #define TARGET_MODE_ENTRY ix86_mode_entry
52343 #undef TARGET_MODE_EXIT
52344 #define TARGET_MODE_EXIT ix86_mode_exit
52346 #undef TARGET_MODE_PRIORITY
52347 #define TARGET_MODE_PRIORITY ix86_mode_priority
52349 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
52350 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
52352 #undef TARGET_LOAD_BOUNDS_FOR_ARG
52353 #define TARGET_LOAD_BOUNDS_FOR_ARG ix86_load_bounds
52355 #undef TARGET_STORE_BOUNDS_FOR_ARG
52356 #define TARGET_STORE_BOUNDS_FOR_ARG ix86_store_bounds
52358 #undef TARGET_LOAD_RETURNED_BOUNDS
52359 #define TARGET_LOAD_RETURNED_BOUNDS ix86_load_returned_bounds
52361 #undef TARGET_STORE_RETURNED_BOUNDS
52362 #define TARGET_STORE_RETURNED_BOUNDS ix86_store_returned_bounds
52364 #undef TARGET_CHKP_BOUND_MODE
52365 #define TARGET_CHKP_BOUND_MODE ix86_mpx_bound_mode
52367 #undef TARGET_BUILTIN_CHKP_FUNCTION
52368 #define TARGET_BUILTIN_CHKP_FUNCTION ix86_builtin_mpx_function
52370 #undef TARGET_CHKP_FUNCTION_VALUE_BOUNDS
52371 #define TARGET_CHKP_FUNCTION_VALUE_BOUNDS ix86_function_value_bounds
52373 #undef TARGET_CHKP_MAKE_BOUNDS_CONSTANT
52374 #define TARGET_CHKP_MAKE_BOUNDS_CONSTANT ix86_make_bounds_constant
52376 #undef TARGET_CHKP_INITIALIZE_BOUNDS
52377 #define TARGET_CHKP_INITIALIZE_BOUNDS ix86_initialize_bounds
52379 #undef TARGET_SETUP_INCOMING_VARARG_BOUNDS
52380 #define TARGET_SETUP_INCOMING_VARARG_BOUNDS ix86_setup_incoming_vararg_bounds
52382 #undef TARGET_OFFLOAD_OPTIONS
52383 #define TARGET_OFFLOAD_OPTIONS \
52384 ix86_offload_options
52386 #undef TARGET_ABSOLUTE_BIGGEST_ALIGNMENT
52387 #define TARGET_ABSOLUTE_BIGGEST_ALIGNMENT 512
52390 \f