| blob | f3802d7379a22b6eb9790cac3566ea2b32f477f6 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
99 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
125 /* Number of attempts to combine instructions in this function. */
129 /* Number of attempts that got as far as substitution in this function. */
133 /* Number of instructions combined with added SETs in this function. */
137 /* Number of instructions combined in this function. */
141 /* Totals over entire compilation. */
145 /* combine_instructions may try to replace the right hand side of the
146 second instruction with the value of an associated REG_EQUAL note
147 before throwing it at try_combine. That is problematic when there
148 is a REG_DEAD note for a register used in the old right hand side
149 and can cause distribute_notes to do wrong things. This is the
150 second instruction if it has been so modified, null otherwise. */
154 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
158 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
161 \f
163 /* Record last point of death of (hard or pseudo) register n. */
166 /* Record last point of modification of (hard or pseudo) register n. */
169 /* The next group of fields allows the recording of the last value assigned
170 to (hard or pseudo) register n. We use this information to see if an
171 operation being processed is redundant given a prior operation performed
172 on the register. For example, an `and' with a constant is redundant if
173 all the zero bits are already known to be turned off.
175 We use an approach similar to that used by cse, but change it in the
176 following ways:
178 (1) We do not want to reinitialize at each label.
179 (2) It is useful, but not critical, to know the actual value assigned
180 to a register. Often just its form is helpful.
182 Therefore, we maintain the following fields:
184 last_set_value the last value assigned
185 last_set_label records the value of label_tick when the
186 register was assigned
187 last_set_table_tick records the value of label_tick when a
188 value using the register is assigned
189 last_set_invalid set to nonzero when it is not valid
190 to use the value of this register in some
191 register's value
193 To understand the usage of these tables, it is important to understand
194 the distinction between the value in last_set_value being valid and
195 the register being validly contained in some other expression in the
196 table.
198 (The next two parameters are out of date).
200 reg_stat[i].last_set_value is valid if it is nonzero, and either
201 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
203 Register I may validly appear in any expression returned for the value
204 of another register if reg_n_sets[i] is 1. It may also appear in the
205 value for register J if reg_stat[j].last_set_invalid is zero, or
206 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
208 If an expression is found in the table containing a register which may
209 not validly appear in an expression, the register is replaced by
210 something that won't match, (clobber (const_int 0)). */
212 /* Record last value assigned to (hard or pseudo) register n. */
214 rtx last_set_value;
216 /* Record the value of label_tick when an expression involving register n
217 is placed in last_set_value. */
221 /* Record the value of label_tick when the value for register n is placed in
222 last_set_value. */
226 /* These fields are maintained in parallel with last_set_value and are
227 used to store the mode in which the register was last set, the bits
228 that were known to be zero when it was last set, and the number of
229 sign bits copies it was known to have when it was last set. */
235 /* Set nonzero if references to register n in expressions should not be
236 used. last_set_invalid is set nonzero when this register is being
237 assigned to and last_set_table_tick == label_tick. */
241 /* Some registers that are set more than once and used in more than one
242 basic block are nevertheless always set in similar ways. For example,
243 a QImode register may be loaded from memory in two places on a machine
244 where byte loads zero extend.
246 We record in the following fields if a register has some leading bits
247 that are always equal to the sign bit, and what we know about the
248 nonzero bits of a register, specifically which bits are known to be
249 zero.
251 If an entry is zero, it means that we don't know anything special. */
257 /* Record the value of the label_tick when the last truncation
258 happened. The field truncated_to_mode is only valid if
259 truncation_label == label_tick. */
263 /* Record the last truncation seen for this register. If truncation
264 is not a nop to this mode we might be able to save an explicit
265 truncation if we know that value already contains a truncated
266 value. */
274 /* One plus the highest pseudo for which we track REG_N_SETS.
275 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
276 but during combine_split_insns new pseudos can be created. As we don't have
277 updated DF information in that case, it is hard to initialize the array
278 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
279 so instead of growing the arrays, just assume all newly created pseudos
280 during combine might be set multiple times. */
284 /* Record the luid of the last insn that invalidated memory
285 (anything that writes memory, and subroutine calls, but not pushes). */
289 /* Record the luid of the last CALL_INSN
290 so we can tell whether a potential combination crosses any calls. */
294 /* When `subst' is called, this is the insn that is being modified
295 (by combining in a previous insn). The PATTERN of this insn
296 is still the old pattern partially modified and it should not be
297 looked at, but this may be used to examine the successors of the insn
298 to judge whether a simplification is valid. */
302 /* This is the lowest LUID that `subst' is currently dealing with.
303 get_last_value will not return a value if the register was set at or
304 after this LUID. If not for this mechanism, we could get confused if
305 I2 or I1 in try_combine were an insn that used the old value of a register
306 to obtain a new value. In that case, we might erroneously get the
307 new value of the register when we wanted the old one. */
311 /* This contains any hard registers that are used in newpat; reg_dead_at_p
312 must consider all these registers to be always live. */
316 /* This is an insn to which a LOG_LINKS entry has been added. If this
317 insn is the earlier than I2 or I3, combine should rescan starting at
318 that location. */
322 /* Basic block in which we are performing combines. */
326 \f
327 /* Length of the currently allocated uid_insn_cost array. */
331 /* The following array records the insn_rtx_cost for every insn
332 in the instruction stream. */
336 /* The following array records the LOG_LINKS for every insn in the
337 instruction stream as struct insn_link pointers. */
343 };
347 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
348 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
350 #define FOR_EACH_LOG_LINK(L, INSN) \
351 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
353 /* Links for LOG_LINKS are allocated from this obstack. */
357 /* Allocate a link. */
361 {
369 }
371 /* Incremented for each basic block. */
375 /* Reset to label_tick for each extended basic block in scanning order. */
379 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
380 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
384 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
385 be safely used. It is zero while computing them and after combine has
386 completed. This former test prevents propagating values based on
387 previously set values, which can be incorrect if a variable is modified
388 in a loop. */
392 \f
393 /* Record one modification to rtl structure
394 to be undone by storing old_contents into *where. */
398 struct undo
399 {
404 };
406 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
407 num_undo says how many are currently recorded.
409 other_insn is nonzero if we have modified some other insn in the process
410 of working on subst_insn. It must be verified too. */
412 struct undobuf
413 {
417 };
421 /* Number of times the pseudo being substituted for
422 was found and replaced. */
427 machine_mode,
431 machine_mode,
503 \f
505 /* It is not safe to use ordinary gen_lowpart in combine.
506 See comments in gen_lowpart_for_combine. */
507 #undef RTL_HOOKS_GEN_LOWPART
508 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
510 /* Our implementation of gen_lowpart never emits a new pseudo. */
511 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
512 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
514 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
515 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
517 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
518 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
520 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
521 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
525 \f
526 /* Convenience wrapper for the canonicalize_comparison target hook.
527 Target hooks cannot use enum rtx_code. */
531 {
535 }
537 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
538 PATTERN can not be split. Otherwise, it returns an insn sequence.
539 This is a wrapper around split_insns which ensures that the
540 reg_stat vector is made larger if the splitter creates a new
541 register. */
545 {
554 }
556 /* This is used by find_single_use to locate an rtx in LOC that
557 contains exactly one use of DEST, which is typically either a REG
558 or CC0. It returns a pointer to the innermost rtx expression
559 containing DEST. Appearances of DEST that are being used to
560 totally replace it are not counted. */
564 {
573 {
577 CASE_CONST_ANY:
582 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
583 of a REG that occupies all of the REG, the insn uses DEST if
584 it is mentioned in the destination or the source. Otherwise, we
585 need just check the source. */
605 }
607 /* If it wasn't one of the common cases above, check each expression and
608 vector of this code. Look for a unique usage of DEST. */
612 {
614 {
619 else
625 /* Duplicate usage. */
627 }
629 {
633 {
639 else
646 }
647 }
648 }
651 }
654 /* See if DEST, produced in INSN, is used only a single time in the
655 sequel. If so, return a pointer to the innermost rtx expression in which
656 it is used.
658 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
660 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
661 care about REG_DEAD notes or LOG_LINKS.
663 Otherwise, we find the single use by finding an insn that has a
664 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
665 only referenced once in that insn, we know that it must be the first
666 and last insn referencing DEST. */
670 {
671 basic_block bb;
677 {
687 }
697 {
703 {
708 }
709 }
712 }
713 \f
714 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
715 insn. The substitution can be undone by undo_all. If INTO is already
716 set to NEWVAL, do not record this change. Because computing NEWVAL might
717 also call SUBST, we have to compute it before we put anything into
718 the undo table. */
720 static void
722 {
729 /* We'd like to catch as many invalid transformations here as
730 possible. Unfortunately, there are way too many mode changes
731 that are perfectly valid, so we'd waste too much effort for
732 little gain doing the checks here. Focus on catching invalid
733 transformations involving integer constants. */
736 {
737 /* Sanity check that we're replacing oldval with a CONST_INT
738 that is a valid sign-extension for the original mode. */
742 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
743 CONST_INT is not valid, because after the replacement, the
744 original mode would be gone. Unfortunately, we can't tell
745 when do_SUBST is called to replace the operand thereof, so we
746 perform this test on oldval instead, checking whether an
747 invalid replacement took place before we got here. */
752 }
756 else
765 }
767 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
769 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
770 for the value of a HOST_WIDE_INT value (including CONST_INT) is
771 not safe. */
773 static void
775 {
784 else
793 }
795 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
797 /* Similar to SUBST, but just substitute the mode. This is used when
798 changing the mode of a pseudo-register, so that any other
799 references to the entry in the regno_reg_rtx array will change as
800 well. */
802 static void
804 {
813 else
822 }
824 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
826 #if !HAVE_cc0
827 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
829 static void
831 {
840 else
849 }
851 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
852 #endif
853 \f
854 /* Subroutine of try_combine. Determine whether the replacement patterns
855 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
856 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
857 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
858 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
859 of all the instructions can be estimated and the replacements are more
860 expensive than the original sequence. */
862 static bool
865 {
870 /* Lookup the original insn_rtx_costs. */
875 {
878 {
882 }
883 else
884 {
888 }
889 }
890 else
891 {
894 }
896 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
897 correct that. */
902 /* Calculate the replacement insn_rtx_costs. */
905 {
909 }
910 else
911 {
914 }
917 {
923 {
926 }
927 else
929 }
931 /* Disallow this combination if both new_cost and old_cost are greater than
932 zero, and new_cost is greater than old cost. */
936 {
955 else
957 }
962 /* Update the uid_insn_cost array with the replacement costs. */
966 {
970 }
973 }
976 /* Delete any insns that copy a register to itself. */
978 static void
980 {
982 basic_block bb;
985 {
987 {
990 {
995 }
996 }
997 }
998 }
1000 \f
1001 /* Return false if we do not want to (or cannot) combine DEF. */
1002 static bool
1004 {
1005 /* Do not consider if it is pre/post modification in MEM. */
1011 /* Do not combine frame pointer adjustments. */
1014 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1017 #endif
1023 }
1025 /* Return false if we do not want to (or cannot) combine USE. */
1026 static bool
1028 {
1029 /* Do not consider the usage of the stack pointer by function call. */
1034 }
1036 /* Fill in log links field for all insns. */
1038 static void
1040 {
1041 basic_block bb;
1048 /* Pass through each block from the end, recording the uses of each
1049 register and establishing log links when def is encountered.
1050 Note that we do not clear next_use array in order to save time,
1051 so we have to test whether the use is in the same basic block as def.
1053 There are a few cases below when we do not consider the definition or
1054 usage -- these are taken from original flow.c did. Don't ask me why it is
1055 done this way; I don't know and if it works, I don't want to know. */
1058 {
1060 {
1064 /* Log links are created only once. */
1068 {
1084 /* flow.c claimed:
1086 We don't build a LOG_LINK for hard registers contained
1087 in ASM_OPERANDs. If these registers get replaced,
1088 we might wind up changing the semantics of the insn,
1089 even if reload can make what appear to be valid
1090 assignments later. */
1095 /* Don't add duplicate links between instructions. */
1104 }
1109 }
1110 }
1113 }
1115 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1116 true if we found a LOG_LINK that proves that A feeds B. This only works
1117 if there are no instructions between A and B which could have a link
1118 depending on A, since in that case we would not record a link for B.
1119 We also check the implicit dependency created by a cc0 setter/user
1120 pair. */
1122 static bool
1124 {
1132 }
1133 \f
1134 /* Main entry point for combiner. F is the first insn of the function.
1135 NREGS is the first unused pseudo-reg number.
1137 Return nonzero if the combiner has turned an indirect jump
1138 instruction into a direct jump. */
1139 static int
1141 {
1143 #if HAVE_cc0
1145 #endif
1148 basic_block last_bb;
1168 /* Allocate array for insn info. */
1176 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1177 problems when, for example, we have j <<= 1 in a loop. */
1182 /* Scan all SETs and see if we can deduce anything about what
1183 bits are known to be zero for some registers and how many copies
1184 of the sign bit are known to exist for those registers.
1186 Also set any known values so that we can use it while searching
1187 for what bits are known to be set. */
1190 /* Allow the entry block and the first block to fall into the same EBB.
1191 Conceptually the incoming promotions are assigned to the entry block. */
1196 {
1201 label_tick++;
1209 {
1210 #ifdef AUTO_INC_DEC
1211 rtx links;
1212 #endif
1218 insn);
1221 #ifdef AUTO_INC_DEC
1225 insn);
1226 #endif
1228 /* Record the current insn_rtx_cost of this instruction. */
1231 optimize_this_for_speed_p);
1235 }
1236 }
1240 /* Now scan all the insns in forward order. */
1248 {
1254 label_tick++;
1264 {
1278 /* See if we know about function return values before this
1279 insn based upon SUBREG flags. */
1282 /* See if we can find hardregs and subreg of pseudos in
1283 narrower modes. This could help turning TRUNCATEs
1284 into SUBREGs. */
1287 /* Try this insn with each insn it links back to. */
1293 {
1296 }
1298 /* Try each sequence of three linked insns ending with this one. */
1302 {
1305 /* If the linked insn has been replaced by a note, then there
1306 is no point in pursuing this chain any further. */
1314 {
1317 }
1318 }
1320 #if HAVE_cc0
1321 /* Try to combine a jump insn that uses CC0
1322 with a preceding insn that sets CC0, and maybe with its
1323 logical predecessor as well.
1324 This is how we make decrement-and-branch insns.
1325 We need this special code because data flow connections
1326 via CC0 do not get entered in LOG_LINKS. */
1332 {
1343 }
1345 /* Do the same for an insn that explicitly references CC0. */
1352 {
1363 }
1365 /* Finally, see if any of the insns that this insn links to
1366 explicitly references CC0. If so, try this insn, that insn,
1367 and its predecessor if it sets CC0. */
1379 #endif
1381 /* Try combining an insn with two different insns whose results it
1382 uses. */
1392 {
1395 }
1397 /* Try four-instruction combinations. */
1400 {
1404 /* If the linked insn has been replaced by a note, then there
1405 is no point in pursuing this chain any further. */
1410 {
1414 /* I0 -> I1 -> I2 -> I3. */
1420 {
1423 }
1424 /* I0, I1 -> I2, I2 -> I3. */
1431 {
1434 }
1435 }
1438 {
1442 /* I0 -> I2; I1, I2 -> I3. */
1448 {
1451 }
1452 /* I0 -> I1; I1, I2 -> I3. */
1458 {
1461 }
1462 }
1463 }
1465 /* Try this insn with each REG_EQUAL note it links back to. */
1467 {
1473 /* Avoid using a register that may already been marked
1474 dead by an earlier instruction. */
1479 {
1480 /* Temporarily replace the set's source with the
1481 contents of the REG_EQUAL note. The insn will
1482 be deleted or recognized by try_combine. */
1490 last_combined_insn);
1493 {
1496 }
1498 }
1499 }
1504 retry:
1505 ;
1506 }
1507 }
1514 /* Clean up. */
1520 {
1523 {
1526 }
1528 }
1538 /* Make recognizer allow volatile MEMs again. */
1542 }
1544 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1546 static void
1548 {
1554 }
1555 \f
1556 /* Set up any promoted values for incoming argument registers. */
1558 static void
1560 {
1561 tree arg;
1566 {
1571 /* Only continue if the incoming argument is in a register. */
1575 /* Determine, if possible, whether all call sites of the current
1576 function lie within the current compilation unit. (This does
1577 take into account the exporting of a function via taking its
1578 address, and so forth.) */
1581 /* The mode and signedness of the argument before any promotions happen
1582 (equal to the mode of the pseudo holding it at that stage). */
1586 /* The mode and signedness of the argument after any source language and
1587 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1591 /* The mode and signedness of the argument as it is actually passed,
1592 see assign_parm_setup_reg in function.c. */
1596 /* The mode of the register in which the argument is being passed. */
1599 /* Eliminate sign extensions in the callee when:
1600 (a) A mode promotion has occurred; */
1603 /* (b) The mode of the register is the same as the mode of
1604 the argument as it is passed; */
1607 /* (c) There's no language level extension; */
1609 ;
1610 /* (c.1) All callers are from the current compilation unit. If that's
1611 the case we don't have to rely on an ABI, we only have to know
1612 what we're generating right now, and we know that we will do the
1613 mode1 to mode2 promotion with the given sign. */
1616 /* (c.2) The combination of the two promotions is useful. This is
1617 true when the signs match, or if the first promotion is unsigned.
1618 In the later case, (sign_extend (zero_extend x)) is the same as
1619 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1625 /* Record that the value was promoted from mode1 to mode3,
1626 so that any sign extension at the head of the current
1627 function may be eliminated. */
1631 }
1632 }
1634 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1635 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1636 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1637 because some machines (maybe most) will actually do the sign-extension and
1638 this is the conservative approach.
1640 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1641 kludge. */
1643 static rtx
1645 {
1653 }
1654 #endif
1656 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1657 and SET. */
1659 static void
1661 rtx x)
1662 {
1671 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1675 #endif
1677 /* Don't call nonzero_bits if it cannot change anything. */
1679 {
1684 }
1686 /* Don't call num_sign_bit_copies if it cannot change anything. */
1688 {
1691 {
1695 }
1698 }
1699 }
1701 /* Called via note_stores. If X is a pseudo that is narrower than
1702 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1704 If we are setting only a portion of X and we can't figure out what
1705 portion, assume all bits will be used since we don't know what will
1706 be happening.
1708 Similarly, set how many bits of X are known to be copies of the sign bit
1709 at all locations in the function. This is the smallest number implied
1710 by any set of X. */
1712 static void
1714 {
1719 /* If this register is undefined at the start of the file, we can't
1720 say what its contents were. */
1721 && ! REGNO_REG_SET_P
1724 {
1728 {
1732 }
1734 /* If this register is being initialized using itself, and the
1735 register is uninitialized in this basic block, and there are
1736 no LOG_LINKS which set the register, then part of the
1737 register is uninitialized. In that case we can't assume
1738 anything about the number of nonzero bits.
1740 ??? We could do better if we checked this in
1741 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1742 could avoid making assumptions about the insn which initially
1743 sets the register, while still using the information in other
1744 insns. We would have to be careful to check every insn
1745 involved in the combination. */
1751 {
1758 {
1762 }
1763 }
1765 /* If this is a complex assignment, see if we can convert it into a
1766 simple assignment. */
1769 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1770 set what we know about X. */
1776 else
1777 {
1780 }
1781 }
1782 }
1783 \f
1784 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1785 optionally insns that were previously combined into I3 or that will be
1786 combined into the merger of INSN and I3. The order is PRED, PRED2,
1787 INSN, SUCC, SUCC2, I3.
1789 Return 0 if the combination is not allowed for any reason.
1791 If the combination is allowed, *PDEST will be set to the single
1792 destination of INSN and *PSRC to the single source, and this function
1793 will return 1. */
1795 static int
1799 {
1804 #ifdef AUTO_INC_DEC
1805 rtx link;
1806 #endif
1811 {
1813 {
1818 }
1823 }
1827 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1828 or a PARALLEL consisting of such a SET and CLOBBERs.
1830 If INSN has CLOBBER parallel parts, ignore them for our processing.
1831 By definition, these happen during the execution of the insn. When it
1832 is merged with another insn, all bets are off. If they are, in fact,
1833 needed and aren't also supplied in I3, they may be added by
1834 recog_for_combine. Otherwise, it won't match.
1836 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1837 note.
1839 Get the source and destination of INSN. If more than one, can't
1840 combine. */
1846 {
1848 {
1852 {
1853 /* This is important to combine floating point insns
1854 for the SH4 port. */
1856 /* Combining an isolated USE doesn't make sense.
1857 We depend here on combinable_i3pat to reject them. */
1858 /* The code below this loop only verifies that the inputs of
1859 the SET in INSN do not change. We call reg_set_between_p
1860 to verify that the REG in the USE does not change between
1861 I3 and INSN.
1862 If the USE in INSN was for a pseudo register, the matching
1863 insn pattern will likely match any register; combining this
1864 with any other USE would only be safe if we knew that the
1865 used registers have identical values, or if there was
1866 something to tell them apart, e.g. different modes. For
1867 now, we forgo such complicated tests and simply disallow
1868 combining of USES of pseudo registers with any other USE. */
1871 {
1876 do
1877 {
1887 }
1889 }
1892 /* We can ignore CLOBBERs. */
1897 /* Ignore SETs whose result isn't used but not those that
1898 have side-effects. */
1904 /* If we have already found a SET, this is a second one and
1905 so we cannot combine with this insn. */
1913 /* Anything else means we can't combine. */
1915 }
1916 }
1919 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1920 so don't do anything with it. */
1923 }
1924 else
1930 /* The simplification in expand_field_assignment may call back to
1931 get_last_value, so set safe guard here. */
1937 /* Do not eliminate user-specified register if it is in an
1938 asm input because we may break the register asm usage defined
1939 in GCC manual if allow to do so.
1940 Be aware that this may cover more cases than we expect but this
1941 should be harmless. */
1946 /* Don't eliminate a store in the stack pointer. */
1948 /* Don't combine with an insn that sets a register to itself if it has
1949 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1951 /* Can't merge an ASM_OPERANDS. */
1953 /* Can't merge a function call. */
1955 /* Don't eliminate a function call argument. */
1961 /* Don't substitute into an incremented register. */
1965 /* Don't substitute into a non-local goto, this confuses CFG. */
1967 /* Make sure that DEST is not used after SUCC but before I3. */
1968 || (!all_adjacent
1969 && ((succ2
1973 /* Make sure that the value that is to be substituted for the register
1974 does not use any registers whose values alter in between. However,
1975 If the insns are adjacent, a use can't cross a set even though we
1976 think it might (this can happen for a sequence of insns each setting
1977 the same destination; last_set of that register might point to
1978 a NOTE). If INSN has a REG_EQUIV note, the register is always
1979 equivalent to the memory so the substitution is valid even if there
1980 are intervening stores. Also, don't move a volatile asm or
1981 UNSPEC_VOLATILE across any other insns. */
1982 || (! all_adjacent
1988 /* Don't combine across a CALL_INSN, because that would possibly
1989 change whether the life span of some REGs crosses calls or not,
1990 and it is a pain to update that information.
1991 Exception: if source is a constant, moving it later can't hurt.
1992 Accept that as a special case. */
1996 /* DEST must either be a REG or CC0. */
1998 {
1999 /* If register alignment is being enforced for multi-word items in all
2000 cases except for parameters, it is possible to have a register copy
2001 insn referencing a hard register that is not allowed to contain the
2002 mode being copied and which would not be valid as an operand of most
2003 insns. Eliminate this problem by not combining with such an insn.
2005 Also, on some machines we don't want to extend the life of a hard
2006 register. */
2011 /* Don't extend the life of a hard register unless it is
2012 user variable (if we have few registers) or it can't
2013 fit into the desired register (meaning something special
2014 is going on).
2015 Also avoid substituting a return register into I3, because
2016 reload can't handle a conflict with constraints of other
2017 inputs. */
2021 }
2029 {
2032 /* If the clobber represents an earlyclobber operand, we must not
2033 substitute an expression containing the clobbered register.
2034 As we do not analyze the constraint strings here, we have to
2035 make the conservative assumption. However, if the register is
2036 a fixed hard reg, the clobber cannot represent any operand;
2037 we leave it up to the machine description to either accept or
2038 reject use-and-clobber patterns. */
2044 }
2046 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2047 or not), reject, unless nothing volatile comes between it and I3 */
2050 {
2051 /* Make sure neither succ nor succ2 contains a volatile reference. */
2056 /* We'll check insns between INSN and I3 below. */
2057 }
2059 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2060 to be an explicit register variable, and was chosen for a reason. */
2066 /* If INSN contains volatile references (specifically volatile MEMs),
2067 we cannot combine across any other volatile references.
2068 Even if INSN doesn't contain volatile references, any intervening
2069 volatile insn might affect machine state. */
2072 ? volatile_refs_p
2079 /* If INSN contains an autoincrement or autodecrement, make sure that
2080 register is not used between there and I3, and not already used in
2081 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2082 Also insist that I3 not be a jump; if it were one
2083 and the incremented register were spilled, we would lose. */
2085 #ifdef AUTO_INC_DEC
2100 #endif
2102 /* Don't combine an insn that follows a CC0-setting insn.
2103 An insn that uses CC0 must not be separated from the one that sets it.
2104 We do, however, allow I2 to follow a CC0-setting insn if that insn
2105 is passed as I1; in that case it will be deleted also.
2106 We also allow combining in this case if all the insns are adjacent
2107 because that would leave the two CC0 insns adjacent as well.
2108 It would be more logical to test whether CC0 occurs inside I1 or I2,
2109 but that would be much slower, and this ought to be equivalent. */
2112 {
2117 }
2119 /* If we get here, we have passed all the tests and the combination is
2120 to be allowed. */
2126 }
2127 \f
2128 /* LOC is the location within I3 that contains its pattern or the component
2129 of a PARALLEL of the pattern. We validate that it is valid for combining.
2131 One problem is if I3 modifies its output, as opposed to replacing it
2132 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2133 doing so would produce an insn that is not equivalent to the original insns.
2135 Consider:
2137 (set (reg:DI 101) (reg:DI 100))
2138 (set (subreg:SI (reg:DI 101) 0) <foo>)
2140 This is NOT equivalent to:
2142 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2143 (set (reg:DI 101) (reg:DI 100))])
2145 Not only does this modify 100 (in which case it might still be valid
2146 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2148 We can also run into a problem if I2 sets a register that I1
2149 uses and I1 gets directly substituted into I3 (not via I2). In that
2150 case, we would be getting the wrong value of I2DEST into I3, so we
2151 must reject the combination. This case occurs when I2 and I1 both
2152 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2153 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2154 of a SET must prevent combination from occurring. The same situation
2155 can occur for I0, in which case I0_NOT_IN_SRC is set.
2157 Before doing the above check, we first try to expand a field assignment
2158 into a set of logical operations.
2160 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2161 we place a register that is both set and used within I3. If more than one
2162 such register is detected, we fail.
2164 Return 1 if the combination is valid, zero otherwise. */
2166 static int
2169 {
2173 {
2178 rtx subdest;
2185 /* Check for the case where I3 modifies its output, as discussed
2186 above. We don't want to prevent pseudos from being combined
2187 into the address of a MEM, so only prevent the combination if
2188 i1 or i2 set the same MEM. */
2198 /* This is the same test done in can_combine_p except we can't test
2199 all_adjacent; we don't have to, since this instruction will stay
2200 in place, thus we are not considering increasing the lifetime of
2201 INNER_DEST.
2203 Also, if this insn sets a function argument, combining it with
2204 something that might need a spill could clobber a previous
2205 function argument; the all_adjacent test in can_combine_p also
2206 checks this; here, we do a more specific test for this case. */
2216 /* If DEST is used in I3, it is being killed in this insn, so
2217 record that for later. We have to consider paradoxical
2218 subregs here, since they kill the whole register, but we
2219 ignore partial subregs, STRICT_LOW_PART, etc.
2220 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2221 STACK_POINTER_REGNUM, since these are always considered to be
2222 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2232 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2234 #endif
2239 {
2244 }
2245 }
2248 {
2255 }
2258 }
2259 \f
2260 /* Return 1 if X is an arithmetic expression that contains a multiplication
2261 and division. We don't count multiplications by powers of two here. */
2263 static int
2265 {
2267 {
2283 }
2284 }
2285 \f
2286 /* Determine whether INSN can be used in a combination. Return nonzero if
2287 not. This is used in try_combine to detect early some cases where we
2288 can't perform combinations. */
2290 static int
2292 {
2293 rtx set;
2296 /* If this isn't really an insn, we can't do anything.
2297 This can occur when flow deletes an insn that it has merged into an
2298 auto-increment address. */
2302 /* Never combine loads and stores involving hard regs that are likely
2303 to be spilled. The register allocator can usually handle such
2304 reg-reg moves by tying. If we allow the combiner to make
2305 substitutions of likely-spilled regs, reload might die.
2306 As an exception, we allow combinations involving fixed regs; these are
2307 not available to the register allocator so there's no risk involved. */
2328 }
2330 struct likely_spilled_retval_info
2331 {
2334 };
2336 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2337 hard registers that are known to be written to / clobbered in full. */
2338 static void
2340 {
2357 else
2360 }
2362 /* Return nonzero iff part of the return value is live during INSN, and
2363 it is likely spilled. This can happen when more than one insn is needed
2364 to copy the return value, e.g. when we consider to combine into the
2365 second copy insn for a complex value. */
2367 static int
2369 {
2371 rtx reg;
2374 /* We assume here that no machine mode needs more than
2375 32 hard registers when the value overlaps with a register
2376 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2391 /* Disregard parts of the return value that are set later. */
2400 /* Check if any of the (probably) live return value registers is
2401 likely spilled. */
2402 nregs --;
2403 do
2404 {
2410 }
2412 /* Adjust INSN after we made a change to its destination.
2414 Changing the destination can invalidate notes that say something about
2415 the results of the insn and a LOG_LINK pointing to the insn. */
2417 static void
2419 {
2420 /* For notes, be conservative and simply remove them. */
2423 /* The new insn will have a destination that was previously the destination
2424 of an insn just above it. Call distribute_links to make a LOG_LINK from
2425 the next use of that destination. */
2441 }
2443 /* Return TRUE if combine can reuse reg X in mode MODE.
2444 ADDED_SETS is nonzero if the original set is still required. */
2445 static bool
2447 {
2454 /* Allow hard registers if the new mode is legal, and occupies no more
2455 registers than the old mode. */
2460 /* Or a pseudo that is only used once. */
2463 && !added_sets
2465 }
2468 /* Check whether X, the destination of a set, refers to part of
2469 the register specified by REG. */
2471 static bool
2473 {
2474 /* Check that reg is an integer mode register. */
2485 }
2487 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2488 Note that the INSN should be deleted *after* removing dead edges, so
2489 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2490 but not for a (set (pc) (label_ref FOO)). */
2492 static void
2494 {
2502 {
2507 /* Remove barriers from the footer if there are any. */
2510 {
2513 else
2517 }
2520 }
2521 }
2523 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2524 by an arbitrary number of CLOBBERs. */
2525 static bool
2527 {
2545 }
2547 #if !HAVE_cc0
2548 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2549 CLOBBERs), can be split into individual SETs in that order, without
2550 changing semantics. */
2551 static bool
2553 {
2561 {
2570 }
2573 }
2574 #endif
2576 /* Try to combine the insns I0, I1 and I2 into I3.
2577 Here I0, I1 and I2 appear earlier than I3.
2578 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2579 I3.
2581 If we are combining more than two insns and the resulting insn is not
2582 recognized, try splitting it into two insns. If that happens, I2 and I3
2583 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2584 Otherwise, I0, I1 and I2 are pseudo-deleted.
2586 Return 0 if the combination does not work. Then nothing is changed.
2587 If we did the combination, return the insn at which combine should
2588 resume scanning.
2590 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2591 new direct jump instruction.
2593 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2594 been I3 passed to an earlier try_combine within the same basic
2595 block. */
2600 {
2601 /* New patterns for I3 and I2, respectively. */
2605 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2606 dead. */
2608 /* Total number of SETs to put into I3. */
2610 /* Nonzero if I2's or I1's body now appears in I3. */
2612 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2614 /* Contains I3 if the destination of I3 is used in its source, which means
2615 that the old life of I3 is being killed. If that usage is placed into
2616 I2 and not in I3, a REG_DEAD note must be made. */
2618 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2620 /* Copy of SET_SRC of I1 and I0, if needed. */
2622 /* Set if I2DEST was reused as a scratch register. */
2624 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2626 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2631 /* Notes that must be added to REG_NOTES in I3 and I2. */
2633 /* Notes that we substituted I3 into I2 instead of the normal case. */
2635 /* Notes that I1, I2 or I3 is a MULT operation. */
2642 rtx temp_expr;
2645 rtx new_other_notes;
2648 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2649 never be). */
2653 /* Only try four-insn combinations when there's high likelihood of
2654 success. Look for simple insns, such as loads of constants or
2655 binary operations involving a constant. */
2657 {
2667 {
2670 rtx src;
2675 {
2678 }
2680 ngood++;
2683 nshift++;
2684 }
2686 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2687 are likely manipulating its value. Ideally we'll be able to combine
2688 all four insns into a bitfield insertion of some kind.
2690 Note the source in I0 might be inside a sign/zero extension and the
2691 memory modes in I0 and I3 might be different. So extract the address
2692 from the destination of I3 and search for it in the source of I0.
2694 In the event that there's a match but the source/dest do not actually
2695 refer to the same memory, the worst that happens is we try some
2696 combinations that we wouldn't have otherwise. */
2698 /* Ensure the source of SET0 is a MEM, possibly buried inside
2699 an extension. */
2705 /* Ensure the destination of SET3 is a MEM. */
2707 /* Would it be better to extract the base address for the MEM
2708 in SET3 and look for that? I don't have cases where it matters
2709 but I could envision such cases. */
2715 }
2717 /* Exit early if one of the insns involved can't be used for
2718 combinations. */
2729 combine_attempts++;
2732 /* Reset the hard register usage information. */
2736 {
2743 else
2746 }
2748 /* If multiple insns feed into one of I2 or I3, they can be in any
2749 order. To simplify the code below, reorder them in sequence. */
2759 /* First check for one important special case that the code below will
2760 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2761 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2762 we may be able to replace that destination with the destination of I3.
2763 This occurs in the common code where we compute both a quotient and
2764 remainder into a structure, in which case we want to do the computation
2765 directly into the structure to avoid register-register copies.
2767 Note that this case handles both multiple sets in I2 and also cases
2768 where I2 has a number of CLOBBERs inside the PARALLEL.
2770 We make very conservative checks below and only try to handle the
2771 most common cases of this. For example, we only handle the case
2772 where I2 and I3 are adjacent to avoid making difficult register
2773 usage tests. */
2781 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2782 below would need to check what is inside (and reg_overlap_mentioned_p
2783 doesn't support those codes anyway). Don't allow those destinations;
2784 the resulting insn isn't likely to be recognized anyway. */
2790 {
2793 /* Make sure that the destination of I3,
2794 which we are going to substitute into one output of I2,
2795 is not used within another output of I2. We must avoid making this:
2796 (parallel [(set (mem (reg 69)) ...)
2797 (set (reg 69) ...)])
2798 which is not well-defined as to order of actions.
2799 (Besides, reload can't handle output reloads for this.)
2801 The problem can also happen if the dest of I3 is a memory ref,
2802 if another dest in I2 is an indirect memory ref. */
2810 /* Make sure this PARALLEL is not an asm. We do not allow combining
2811 that usually (see can_combine_p), so do not here either. */
2821 {
2822 combine_merges++;
2832 /* Replace the dest in I2 with our dest and make the resulting
2833 insn the new pattern for I3. Then skip to where we validate
2834 the pattern. Everything was set up above. */
2839 }
2840 }
2842 /* If I2 is setting a pseudo to a constant and I3 is setting some
2843 sub-part of it to another constant, merge them by making a new
2844 constant. */
2851 {
2857 {
2860 {
2866 }
2867 }
2868 else
2869 {
2874 }
2877 {
2878 /* If this is the low part, we're done. */
2880 ;
2881 /* Handle the case where inner is twice the size of outer. */
2885 /* Otherwise give up for now. */
2886 else
2888 }
2891 {
2895 wide_int o
2900 combine_merges++;
2907 /* Replace the source in I2 with the new constant and make the
2908 resulting insn the new pattern for I3. Then skip to where we
2909 validate the pattern. Everything was set up above. */
2915 /* The dest of I3 has been replaced with the dest of I2. */
2918 }
2919 }
2921 #if !HAVE_cc0
2922 /* If we have no I1 and I2 looks like:
2923 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2924 (set Y OP)])
2925 make up a dummy I1 that is
2926 (set Y OP)
2927 and change I2 to be
2928 (set (reg:CC X) (compare:CC Y (const_int 0)))
2930 (We can ignore any trailing CLOBBERs.)
2932 This undoes a previous combination and allows us to match a branch-and-
2933 decrement insn. */
2945 {
2946 /* We make I1 with the same INSN_UID as I2. This gives it
2947 the same DF_INSN_LUID for value tracking. Our fake I1 will
2948 never appear in the insn stream so giving it the same INSN_UID
2949 as I2 will not cause a problem. */
2962 }
2964 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2965 make those two SETs separate I1 and I2 insns, and make an I0 that is
2966 the original I1. */
2972 {
2973 /* If there is no I1, there is no I0 either. */
2976 /* We make I1 with the same INSN_UID as I2. This gives it
2977 the same DF_INSN_LUID for value tracking. Our fake I1 will
2978 never appear in the insn stream so giving it the same INSN_UID
2979 as I2 will not cause a problem. */
2987 }
2988 #endif
2990 /* Verify that I2 and I1 are valid for combining. */
2996 {
2999 }
3001 /* Record whether I2DEST is used in I2SRC and similarly for the other
3002 cases. Knowing this will help in register status updating below. */
3013 /* For the earlier insns, determine which of the subsequent ones they
3014 feed. */
3021 /* Ensure that I3's pattern can be the destination of combines. */
3027 {
3030 }
3032 /* See if any of the insns is a MULT operation. Unless one is, we will
3033 reject a combination that is, since it must be slower. Be conservative
3034 here. */
3042 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3043 We used to do this EXCEPT in one case: I3 has a post-inc in an
3044 output operand. However, that exception can give rise to insns like
3045 mov r3,(r3)+
3046 which is a famous insn on the PDP-11 where the value of r3 used as the
3047 source was model-dependent. Avoid this sort of thing. */
3049 #if 0
3055 /* It's not the exception. */
3056 #endif
3057 #ifdef AUTO_INC_DEC
3058 {
3059 rtx link;
3065 {
3068 }
3069 }
3070 #endif
3072 /* See if the SETs in I1 or I2 need to be kept around in the merged
3073 instruction: whenever the value set there is still needed past I3.
3074 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3076 For the SET in I1, we have two cases: if I1 and I2 independently feed
3077 into I3, the set in I1 needs to be kept around unless I1DEST dies
3078 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3079 in I1 needs to be kept around unless I1DEST dies or is set in either
3080 I2 or I3. The same considerations apply to I0. */
3087 else
3095 else
3098 /* We are about to copy insns for the case where they need to be kept
3099 around. Check that they can be copied in the merged instruction. */
3105 {
3108 }
3110 /* If the set in I2 needs to be kept around, we must make a copy of
3111 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3112 PATTERN (I2), we are only substituting for the original I1DEST, not into
3113 an already-substituted copy. This also prevents making self-referential
3114 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3115 I2DEST. */
3118 {
3121 else
3123 }
3126 {
3129 else
3131 }
3134 {
3137 else
3139 }
3141 combine_merges++;
3143 /* Substitute in the latest insn for the regs set by the earlier ones. */
3149 /* Many machines that don't use CC0 have insns that can both perform an
3150 arithmetic operation and set the condition code. These operations will
3151 be represented as a PARALLEL with the first element of the vector
3152 being a COMPARE of an arithmetic operation with the constant zero.
3153 The second element of the vector will set some pseudo to the result
3154 of the same arithmetic operation. If we simplify the COMPARE, we won't
3155 match such a pattern and so will generate an extra insn. Here we test
3156 for this case, where both the comparison and the operation result are
3157 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3158 I2SRC. Later we will make the PARALLEL that contains I2. */
3164 {
3165 rtx newpat_dest;
3179 {
3184 }
3186 /* Do the rest only if op1 is const0_rtx, which may be the
3187 result of simplification. */
3189 {
3190 /* If a single use of the CC is found, prepare to modify it
3191 when SELECT_CC_MODE returns a new CC-class mode, or when
3192 the above simplify_compare_const() returned a new comparison
3193 operator. undobuf.other_insn is assigned the CC use insn
3194 when modifying it. */
3196 {
3197 #ifdef SELECT_CC_MODE
3198 machine_mode new_mode
3203 {
3208 else
3209 {
3212 }
3213 }
3214 #endif
3215 /* Cases for modifying the CC-using comparison. */
3217 /* ??? Do we need to verify the zero rtx? */
3219 {
3220 /* Replace cc_use_loc with entire new RTX. */
3225 }
3227 {
3228 /* Just replace the CC reg with a new mode. */
3231 }
3232 }
3234 /* Now we modify the current newpat:
3235 First, SET_DEST(newpat) is updated if the CC mode has been
3236 altered. For targets without SELECT_CC_MODE, this should be
3237 optimized away. */
3240 /* This is always done to propagate i2src into newpat. */
3243 /* Create new version of i2pat if needed; the below PARALLEL
3244 creation needs this to work correctly. */
3248 }
3249 }
3252 {
3253 /* It is possible that the source of I2 or I1 may be performing
3254 an unneeded operation, such as a ZERO_EXTEND of something
3255 that is known to have the high part zero. Handle that case
3256 by letting subst look at the inner insns.
3258 Another way to do this would be to have a function that tries
3259 to simplify a single insn instead of merging two or more
3260 insns. We don't do this because of the potential of infinite
3261 loops and because of the potential extra memory required.
3262 However, doing it the way we are is a bit of a kludge and
3263 doesn't catch all cases.
3265 But only do this if -fexpensive-optimizations since it slows
3266 things down and doesn't usually win.
3268 This is not done in the COMPARE case above because the
3269 unmodified I2PAT is used in the PARALLEL and so a pattern
3270 with a modified I2SRC would not match. */
3273 {
3274 /* Pass pc_rtx so no substitutions are done, just
3275 simplifications. */
3277 {
3280 }
3284 }
3289 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3290 copy of I2SRC each time we substitute it, in order to avoid creating
3291 self-referential RTL when we will be substituting I1SRC for I1DEST
3292 later. Likewise if I0 feeds into I2, either directly or indirectly
3293 through I1, and I0DEST is in I0SRC. */
3300 /* Record whether I2's body now appears within I3's body. */
3302 }
3304 /* If we already got a failure, don't try to do more. Otherwise, try to
3305 substitute I1 if we have it. */
3308 {
3309 /* Check that an autoincrement side-effect on I1 has not been lost.
3310 This happens if I1DEST is mentioned in I2 and dies there, and
3311 has disappeared from the new pattern. */
3313 && i1_feeds_i2_n
3316 /* Before we can do this substitution, we must redo the test done
3317 above (see detailed comments there) that ensures I1DEST isn't
3318 mentioned in any SETs in NEWPAT that are field assignments. */
3321 {
3324 }
3329 /* If the following substitution will modify I1SRC, make a copy of it
3330 for the case where it is substituted for I1DEST in I2PAT later. */
3334 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3335 copy of I1SRC each time we substitute it, in order to avoid creating
3336 self-referential RTL when we will be substituting I0SRC for I0DEST
3337 later. */
3342 /* Record whether I1's body now appears within I3's body. */
3344 }
3346 /* Likewise for I0 if we have it. */
3349 {
3356 {
3359 }
3361 /* If the following substitution will modify I0SRC, make a copy of it
3362 for the case where it is substituted for I0DEST in I1PAT later. */
3365 /* And a copy for I0DEST in I2PAT substitution. */
3374 }
3376 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3377 to count all the ways that I2SRC and I1SRC can be used. */
3388 /* Fail if we tried to make a new register. */
3390 /* Fail if we couldn't do something and have a CLOBBER. */
3392 /* Fail if this new pattern is a MULT and we didn't have one before
3393 at the outer level. */
3396 {
3399 }
3401 /* If the actions of the earlier insns must be kept
3402 in addition to substituting them into the latest one,
3403 we must make a new PARALLEL for the latest insn
3404 to hold additional the SETs. */
3407 {
3409 combine_extras++;
3412 {
3418 }
3419 else
3420 {
3425 }
3431 {
3437 }
3439 {
3448 }
3449 }
3451 validate_replacement:
3453 /* Note which hard regs this insn has as inputs. */
3456 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3457 consider splitting this pattern, we might need these clobbers. */
3460 {
3466 }
3468 /* We have recognized nothing yet. */
3471 /* See if this is a PARALLEL of two SETs where one SET's destination is
3472 a register that is unused and this isn't marked as an instruction that
3473 might trap in an EH region. In that case, we just need the other SET.
3474 We prefer this over the PARALLEL.
3476 This can occur when simplifying a divmod insn. We *must* test for this
3477 case here because the code below that splits two independent SETs doesn't
3478 handle this case correctly when it updates the register status.
3480 It's pointless doing this if we originally had two sets, one from
3481 i3, and one from i2. Combining then splitting the parallel results
3482 in the original i2 again plus an invalid insn (which we delete).
3483 The net effect is only to move instructions around, which makes
3484 debug info less accurate. */
3489 {
3500 {
3503 }
3512 {
3518 }
3522 }
3524 /* Is the result of combination a valid instruction? */
3528 /* If we were combining three insns and the result is a simple SET
3529 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3530 insns. There are two ways to do this. It can be split using a
3531 machine-specific method (like when you have an addition of a large
3532 constant) or by combine in the function find_split_point. */
3536 {
3540 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3541 use I2DEST as a scratch register will help. In the latter case,
3542 convert I2DEST to the mode of the source of NEWPAT if we can. */
3546 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3547 inputs of NEWPAT. */
3549 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3550 possible to try that as a scratch reg. This would require adding
3551 more code to make it work though. */
3554 {
3557 /* First try to split using the original register as a
3558 scratch register. */
3562 i2dest)));
3565 /* If that didn't work, try changing the mode of I2DEST if
3566 we can. */
3571 {
3573 rtx ni2dest;
3577 else
3578 {
3581 }
3583 parallel = (gen_rtx_PARALLEL
3587 ni2dest))));
3592 {
3600 }
3601 }
3604 }
3606 /* If recog_for_combine has discarded clobbers, try to use them
3607 again for the split. */
3609 {
3612 }
3615 {
3620 }
3624 {
3634 /* If I2 or I3 has multiple SETs, we won't know how to track
3635 register status, so don't use these insns. If I2's destination
3636 is used between I2 and I3, we also can't use these insns. */
3646 /* It is possible that both insns now set the destination of I3.
3647 If so, we must show an extra use of it. */
3650 {
3669 }
3670 }
3672 /* If we can split it and use I2DEST, go ahead and see if that
3673 helps things be recognized. Verify that none of the registers
3674 are set between I2 and I3. */
3678 /* We need I2DEST in the proper mode. If it is a hard register
3679 or the only use of a pseudo, we can change its mode.
3680 Make sure we don't change a hard register to have a mode that
3681 isn't valid for it, or change the number of registers. */
3688 /* We can't overwrite I2DEST if its value is still used by
3689 NEWPAT. */
3691 {
3700 /* *SPLIT may be part of I2SRC, so make sure we have the
3701 original expression around for later debug processing.
3702 We should not need I2SRC any more in other cases. */
3705 else
3708 /* Get NEWDEST as a register in the proper mode. We have already
3709 validated that we can do this. */
3711 {
3714 else
3715 {
3718 }
3719 }
3721 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3722 an ASHIFT. This can occur if it was inside a PLUS and hence
3723 appeared to be a memory address. This is a kludge. */
3728 {
3731 /* Update split_code because we may not have a multiply
3732 anymore. */
3734 }
3736 /* Similarly for (plus (mult FOO (const_int pow2))). */
3742 {
3746 /* Update split_code because we may not have a multiply
3747 anymore. */
3749 }
3751 #ifdef INSN_SCHEDULING
3752 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3753 be written as a ZERO_EXTEND. */
3755 {
3756 #ifdef LOAD_EXTEND_OP
3757 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3758 what it really is. */
3763 else
3764 #endif
3767 }
3768 #endif
3770 /* Attempt to split binary operators using arithmetic identities. */
3774 {
3781 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3783 {
3788 }
3789 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3796 {
3802 /* Split both "((X op Y) op X) op Y" and
3803 "((X op Y) op Y) op X" as "T op T" where T is
3804 "X op Y". */
3807 {
3812 }
3813 /* Split "((X op X) op Y) op Y)" as "T op T" where
3814 T is "X op Y". */
3816 {
3822 }
3823 }
3824 }
3827 {
3830 }
3834 /* recog_for_combine might have added CLOBBERs to newi2pat.
3835 Make sure NEWPAT does not depend on the clobbered regs. */
3839 {
3842 {
3845 }
3846 }
3848 /* If the split point was a MULT and we didn't have one before,
3849 don't use one now. */
3852 }
3853 }
3855 /* Check for a case where we loaded from memory in a narrow mode and
3856 then sign extended it, but we need both registers. In that case,
3857 we have a PARALLEL with both loads from the same memory location.
3858 We can split this into a load from memory followed by a register-register
3859 copy. This saves at least one insn, more if register allocation can
3860 eliminate the copy.
3862 We cannot do this if the destination of the first assignment is a
3863 condition code register or cc0. We eliminate this case by making sure
3864 the SET_DEST and SET_SRC have the same mode.
3866 We cannot do this if the destination of the second assignment is
3867 a register that we have already assumed is zero-extended. Similarly
3868 for a SUBREG of such a register. */
3903 {
3904 rtx ni2dest;
3918 }
3920 /* Similarly, check for a case where we have a PARALLEL of two independent
3921 SETs but we started with three insns. In this case, we can do the sets
3922 as two separate insns. This case occurs when some SET allows two
3923 other insns to combine, but the destination of that SET is still live.
3925 Also do this if we started with two insns and (at least) one of the
3926 resulting sets is a noop; this noop will be deleted later. */
3945 {
3949 /* Normally, it doesn't matter which of the two is done first,
3950 but the one that references cc0 can't be the second, and
3951 one which uses any regs/memory set in between i2 and i3 can't
3952 be first. The PARALLEL might also have been pre-existing in i3,
3953 so we need to make sure that we won't wrongly hoist a SET to i2
3954 that would conflict with a death note present in there. */
3962 /* If I3 is a jump, ensure that set0 is a jump so that
3963 we do not create invalid RTL. */
3965 )
3966 {
3969 }
3977 /* If I3 is a jump, ensure that set1 is a jump so that
3978 we do not create invalid RTL. */
3980 )
3981 {
3984 }
3985 else
3986 {
3989 }
3994 {
3995 /* recog_for_combine might have added CLOBBERs to newi2pat.
3996 Make sure NEWPAT does not depend on the clobbered regs. */
3998 {
4001 {
4004 {
4007 }
4008 }
4009 }
4012 }
4013 }
4015 /* If it still isn't recognized, fail and change things back the way they
4016 were. */
4018 /* Is the result a reasonable ASM_OPERANDS? */
4020 {
4023 }
4025 /* If we had to change another insn, make sure it is valid also. */
4027 {
4035 {
4038 }
4039 }
4041 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4042 they are adjacent to each other or not. */
4044 {
4048 {
4051 }
4052 }
4054 /* Only allow this combination if insn_rtx_costs reports that the
4055 replacement instructions are cheaper than the originals. */
4057 {
4060 }
4063 {
4068 {
4073 /* Temporarily revert mode back. */
4077 {
4078 /* If we used i2dest as a scratch register with a
4079 different mode, substitute it for the original
4080 i2src while its original mode is temporarily
4081 restored, and then clear i2scratch so that we don't
4082 do it again later. */
4084 this_basic_block);
4086 /* Put back the new mode. */
4088 }
4089 else
4090 {
4095 {
4098 }
4099 else
4100 {
4107 }
4109 /* We're dealing with a reg that changed mode but not
4110 meaning, so we want to turn it into a subreg for
4111 the new mode. However, because of REG sharing and
4112 because its mode had already changed, we have to do
4113 it in two steps. First, replace any debug uses of
4114 reg, with its original mode temporarily restored,
4115 with this copy we have created; then, replace the
4116 copy with the SUBREG of the original shared reg,
4117 once again changed to the new mode. */
4119 this_basic_block);
4123 this_basic_block);
4124 }
4125 }
4126 }
4128 /* If we will be able to accept this, we have made a
4129 change to the destination of I3. This requires us to
4130 do a few adjustments. */
4133 {
4136 }
4138 /* We now know that we can do this combination. Merge the insns and
4139 update the status of registers and LOG_LINKS. */
4142 {
4147 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4148 ensure that they are still valid. Then add any non-duplicate
4149 notes added by recog_for_combine. */
4151 {
4161 }
4165 NULL_RTX);
4166 }
4169 {
4172 rtx ni2dest;
4174 /* I3 now uses what used to be its destination and which is now
4175 I2's destination. This requires us to do a few adjustments. */
4179 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4180 so we still will.
4182 However, some later insn might be using I2's dest and have
4183 a LOG_LINK pointing at I3. We must remove this link.
4184 The simplest way to remove the link is to point it at I1,
4185 which we know will be a NOTE. */
4187 /* newi2pat is usually a SET here; however, recog_for_combine might
4188 have added some clobbers. */
4191 else
4198 {
4200 {
4206 }
4207 }
4208 }
4210 {
4215 /* Compute which registers we expect to eliminate. newi2pat may be setting
4216 either i3dest or i2dest, so we must check it. */
4219 || !i2dest_killed
4221 /* For i1, we need to compute both local elimination and global
4222 elimination information with respect to newi2pat because i1dest
4223 may be the same as i3dest, in which case newi2pat may be setting
4224 i1dest. Global information is used when distributing REG_DEAD
4225 note for i2 and i3, in which case it does matter if newi2pat sets
4226 i1dest or not.
4228 Local information is used when distributing REG_DEAD note for i1,
4229 in which case it doesn't matter if newi2pat sets i1dest or not.
4230 See PR62151, if we have four insns combination:
4231 i0: r0 <- i0src
4232 i1: r1 <- i1src (using r0)
4233 REG_DEAD (r0)
4234 i2: r0 <- i2src (using r1)
4235 i3: r3 <- i3src (using r0)
4236 ix: using r0
4237 From i1's point of view, r0 is eliminated, no matter if it is set
4238 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4239 should be discarded.
4241 Note local information only affects cases in forms like "I1->I2->I3",
4242 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4243 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4244 i0dest anyway. */
4246 || !i1dest_killed
4251 /* Same case as i1. */
4258 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4259 clear them. */
4267 /* Ensure that we do not have something that should not be shared but
4268 occurs multiple times in the new insns. Check this by first
4269 resetting all the `used' flags and then copying anything is shared. */
4293 {
4300 {
4301 /* I2SRC must still be meaningful at this point. Some splitting
4302 operations can invalidate I2SRC, but those operations do not
4303 apply to calls. */
4306 }
4314 }
4319 /* We had one special case above where I2 had more than one set and
4320 we replaced a destination of one of those sets with the destination
4321 of I3. In that case, we have to update LOG_LINKS of insns later
4322 in this basic block. Note that this (expensive) case is rare.
4324 Also, in this case, we must pretend that all REG_NOTEs for I2
4325 actually came from I3, so that REG_UNUSED notes from I2 will be
4326 properly handled. */
4329 {
4338 temp_insn
4348 {
4353 }
4354 else
4357 }
4365 {
4368 this_basic_block);
4371 }
4372 else
4373 {
4376 this_basic_block);
4378 }
4381 {
4386 this_basic_block);
4388 }
4391 {
4396 this_basic_block);
4398 }
4400 /* Get death notes for everything that is now used in either I3 or
4401 I2 and used to die in a previous insn. If we built two new
4402 patterns, move from I1 to I2 then I2 to I3 so that we get the
4403 proper movement on registers that I2 modifies. */
4409 else
4415 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4432 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4433 know these are REG_UNUSED and want them to go to the desired insn,
4434 so we always pass it as i3. */
4438 NULL_RTX);
4442 NULL_RTX);
4444 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4445 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4446 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4447 in that case, it might delete I2. Similarly for I2 and I1.
4448 Show an additional death due to the REG_DEAD note we make here. If
4449 we discard it in distribute_notes, we will decrement it again. */
4452 {
4457 else
4460 }
4463 {
4468 else
4471 }
4474 {
4479 else
4482 }
4485 {
4490 else
4493 }
4501 {
4506 /* The insn that used to set this register doesn't exist, and
4507 this life of the register may not exist either. See if one of
4508 I3's links points to an insn that sets I2DEST. If it does,
4509 that is now the last known value for I2DEST. If we don't update
4510 this and I2 set the register to a value that depended on its old
4511 contents, we will get confused. If this insn is used, thing
4512 will be set correctly in combine_instructions. */
4520 /* If the reg formerly set in I2 died only once and that was in I3,
4521 zero its use count so it won't make `reload' do any work. */
4524 && ! i2dest_in_i2src
4527 }
4530 {
4543 && ! i1dest_in_i1src
4546 }
4549 {
4562 && ! i0dest_in_i0src
4565 }
4567 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4568 been made to this insn. The order is important, because newi2pat
4569 can affect nonzero_bits of newpat. */
4573 }
4576 {
4578 {
4581 }
4583 }
4586 {
4588 {
4591 }
4593 }
4596 {
4598 {
4601 }
4603 }
4606 {
4608 {
4611 }
4613 }
4616 {
4618 {
4621 }
4623 }
4625 /* Set new_direct_jump_p if a new return or simple jump instruction
4626 has been created. Adjust the CFG accordingly. */
4628 {
4632 }
4637 {
4640 }
4642 /* A noop might also need cleaning up of CFG, if it comes from the
4643 simplification of a jump. */
4648 {
4651 }
4658 {
4661 }
4663 combine_successes++;
4670 else
4672 }
4673 \f
4674 /* Get a marker for undoing to the current state. */
4678 {
4680 }
4682 /* Undo the modifications up to the marker. */
4684 static void
4686 {
4690 {
4695 {
4710 }
4714 }
4717 }
4719 /* Undo all the modifications recorded in undobuf. */
4721 static void
4723 {
4725 }
4727 /* We've committed to accepting the changes we made. Move all
4728 of the undos to the free list. */
4730 static void
4732 {
4736 {
4740 }
4742 }
4743 \f
4744 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4745 where we have an arithmetic expression and return that point. LOC will
4746 be inside INSN.
4748 try_combine will call this function to see if an insn can be split into
4749 two insns. */
4753 {
4762 /* First special-case some codes. */
4764 {
4766 #ifdef INSN_SCHEDULING
4767 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4768 point. */
4771 #endif
4775 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4776 using LO_SUM and HIGH. */
4779 {
4787 }
4789 /* If we have a PLUS whose second operand is a constant and the
4790 address is not valid, perhaps will can split it up using
4791 the machine-specific way to split large constants. We use
4792 the first pseudo-reg (one of the virtual regs) as a placeholder;
4793 it will not remain in the result. */
4798 {
4801 subst_insn);
4803 /* This should have produced two insns, each of which sets our
4804 placeholder. If the source of the second is a valid address,
4805 we can make put both sources together and make a split point
4806 in the middle. */
4819 && memory_address_addr_space_p
4822 {
4826 /* Replace the placeholder in SRC2 with SRC1. If we can
4827 find where in SRC2 it was placed, that can become our
4828 split point and we can replace this address with SRC2.
4829 Just try two obvious places. */
4840 {
4843 }
4844 }
4846 /* If that didn't work, perhaps the first operand is complex and
4847 needs to be computed separately, so make a split point there.
4848 This will occur on machines that just support REG + CONST
4849 and have a constant moved through some previous computation. */
4855 }
4857 /* If we have a PLUS whose first operand is complex, try computing it
4858 separately by making a split there. */
4869 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4870 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4871 we need to put the operand into a register. So split at that
4872 point. */
4882 /* See if we can split SET_SRC as it stands. */
4887 /* See if we can split SET_DEST as it stands. */
4892 /* See if this is a bitfield assignment with everything constant. If
4893 so, this is an IOR of an AND, so split it into that. */
4903 {
4909 unsigned HOST_WIDE_INT mask
4911 rtx or_mask;
4920 else
4921 {
4927 or_mask));
4928 }
4935 }
4937 /* Otherwise, see if this is an operation that we can split into two.
4938 If so, try to split that. */
4942 {
4944 /* If we are AND'ing with a large constant that is only a single
4945 bit and the result is only being used in a context where we
4946 need to know if it is zero or nonzero, replace it with a bit
4947 extraction. This will avoid the large constant, which might
4948 have taken more than one insn to make. If the constant were
4949 not a valid argument to the AND but took only one insn to make,
4950 this is no worse, but if it took more than one insn, it will
4951 be better. */
4961 {
4966 {
4969 }
4970 }
4974 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4975 is known to be on, this can be converted into a NEG of a shift. */
4981 {
4993 }
4999 /* We can't optimize if either mode is a partial integer
5000 mode as we don't know how many bits are significant
5001 in those modes. */
5015 {
5023 }
5028 }
5032 {
5035 /* For unsigned, we have a choice of a shift followed by an
5036 AND or two shifts. Use two shifts for field sizes where the
5037 constant might be too large. We assume here that we can
5038 always at least get 8-bit constants in an AND insn, which is
5039 true for every current RISC. */
5042 {
5043 unsigned HOST_WIDE_INT mask
5047 gen_rtx_LSHIFTRT
5055 }
5056 else
5057 {
5059 gen_rtx_fmt_ee
5070 }
5071 }
5073 /* See if this is a simple operation with a constant as the second
5074 operand. It might be that this constant is out of range and hence
5075 could be used as a split point. */
5083 /* Finally, see if this is a simple operation with its first operand
5084 not in a register. The operation might require this operand in a
5085 register, so return it as a split point. We can always do this
5086 because if the first operand were another operation, we would have
5087 already found it as a split point. */
5096 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5097 it is better to write this as (not (ior A B)) so we can split it.
5098 Similarly for IOR. */
5100 {
5108 }
5110 /* Many RISC machines have a large set of logical insns. If the
5111 second operand is a NOT, put it first so we will try to split the
5112 other operand first. */
5114 {
5118 }
5123 /* Canonicalization can produce (minus A (mult B C)), where C is a
5124 constant. It may be better to try splitting (plus (mult B -C) A)
5125 instead if this isn't a multiply by a power of two. */
5129 {
5137 mode)),
5140 }
5142 /* Split at a multiply-accumulate instruction. However if this is
5143 the SET_SRC, we likely do not have such an instruction and it's
5144 worthless to try this split. */
5153 }
5155 /* Otherwise, select our actions depending on our rtx class. */
5157 {
5163 /* ... fall through ... */
5171 /* ... fall through ... */
5173 /* Some machines have (and (shift ...) ...) insns. If X is not
5174 an AND, but XEXP (X, 0) is, use it as our split point. */
5184 /* Otherwise, we don't have a split point. */
5186 }
5187 }
5188 \f
5189 /* Throughout X, replace FROM with TO, and return the result.
5190 The result is TO if X is FROM;
5191 otherwise the result is X, but its contents may have been modified.
5192 If they were modified, a record was made in undobuf so that
5193 undo_all will (among other things) return X to its original state.
5195 If the number of changes necessary is too much to record to undo,
5196 the excess changes are not made, so the result is invalid.
5197 The changes already made can still be undone.
5198 undobuf.num_undo is incremented for such changes, so by testing that
5199 the caller can tell whether the result is valid.
5201 `n_occurrences' is incremented each time FROM is replaced.
5203 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5205 IN_COND is nonzero if we are at the top level of a condition.
5207 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5208 by copying if `n_occurrences' is nonzero. */
5210 static rtx
5212 {
5217 rtx new_rtx;
5219 /* Two expressions are equal if they are identical copies of a shared
5220 RTX or if they are both registers with the same register number
5221 and mode. */
5223 #define COMBINE_RTX_EQUAL_P(X,Y) \
5224 ((X) == (Y) \
5225 || (REG_P (X) && REG_P (Y) \
5226 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5228 /* Do not substitute into clobbers of regs -- this will never result in
5229 valid RTL. */
5234 {
5235 n_occurrences++;
5237 }
5239 /* If X and FROM are the same register but different modes, they
5240 will not have been seen as equal above. However, the log links code
5241 will make a LOG_LINKS entry for that case. If we do nothing, we
5242 will try to rerecognize our original insn and, when it succeeds,
5243 we will delete the feeding insn, which is incorrect.
5245 So force this insn not to match in this (rare) case. */
5250 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5251 of which may contain things that can be combined. */
5255 /* It is possible to have a subexpression appear twice in the insn.
5256 Suppose that FROM is a register that appears within TO.
5257 Then, after that subexpression has been scanned once by `subst',
5258 the second time it is scanned, TO may be found. If we were
5259 to scan TO here, we would find FROM within it and create a
5260 self-referent rtl structure which is completely wrong. */
5264 /* Parallel asm_operands need special attention because all of the
5265 inputs are shared across the arms. Furthermore, unsharing the
5266 rtl results in recognition failures. Failure to handle this case
5267 specially can result in circular rtl.
5269 Solve this by doing a normal pass across the first entry of the
5270 parallel, and only processing the SET_DESTs of the subsequent
5271 entries. Ug. */
5276 {
5279 /* If this substitution failed, this whole thing fails. */
5287 {
5293 {
5296 /* If this substitution failed, this whole thing fails. */
5302 }
5303 }
5304 }
5305 else
5306 {
5310 /* We don't need to process a SET_DEST that is a register, CC0,
5311 or PC, so set up to skip this common case. All other cases
5312 where we want to suppress replacing something inside a
5313 SET_SRC are handled via the IN_DEST operand. */
5320 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5321 constant. */
5326 {
5328 {
5331 {
5333 {
5336 n_occurrences++;
5337 }
5338 else
5339 {
5341 unique_copy);
5343 /* If this substitution failed, this whole thing
5344 fails. */
5348 }
5351 }
5352 }
5354 {
5355 /* If this is a register being set, ignore it. */
5362 ;
5365 {
5366 /* In general, don't install a subreg involving two
5367 modes not tieable. It can worsen register
5368 allocation, and can even make invalid reload
5369 insns, since the reg inside may need to be copied
5370 from in the outside mode, and that may be invalid
5371 if it is an fp reg copied in integer mode.
5373 We allow two exceptions to this: It is valid if
5374 it is inside another SUBREG and the mode of that
5375 SUBREG and the mode of the inside of TO is
5376 tieable and it is valid if X is a SET that copies
5377 FROM to CC0. */
5385 #if HAVE_cc0
5387 #endif
5388 )
5400 n_occurrences++;
5401 }
5402 else
5403 /* If we are in a SET_DEST, suppress most cases unless we
5404 have gone inside a MEM, in which case we want to
5405 simplify the address. We assume here that things that
5406 are actually part of the destination have their inner
5407 parts in the first expression. This is true for SUBREG,
5408 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5409 things aside from REG and MEM that should appear in a
5410 SET_DEST. */
5412 (((in_dest
5418 unique_copy);
5420 /* If we found that we will have to reject this combination,
5421 indicate that by returning the CLOBBER ourselves, rather than
5422 an expression containing it. This will speed things up as
5423 well as prevent accidents where two CLOBBERs are considered
5424 to be equal, thus producing an incorrect simplification. */
5430 {
5438 }
5441 {
5445 }
5446 else
5448 }
5449 }
5450 }
5452 /* Check if we are loading something from the constant pool via float
5453 extension; in this case we would undo compress_float_constant
5454 optimization and degenerate constant load to an immediate value. */
5458 {
5462 }
5464 /* Try to simplify X. If the simplification changed the code, it is likely
5465 that further simplification will help, so loop, but limit the number
5466 of repetitions that will be performed. */
5469 {
5470 /* If X is sufficiently simple, don't bother trying to do anything
5471 with it. */
5480 /* We no longer know the original mode of operand 0 since we
5481 have changed the form of X) */
5483 }
5486 }
5487 \f
5488 /* Simplify X, a piece of RTL. We just operate on the expression at the
5489 outer level; call `subst' to simplify recursively. Return the new
5490 expression.
5492 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5493 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5494 of a condition. */
5496 static rtx
5499 {
5502 rtx temp;
5505 /* If this is a commutative operation, put a constant last and a complex
5506 expression first. We don't need to do this for comparisons here. */
5509 {
5513 }
5515 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5516 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5517 things. Check for cases where both arms are testing the same
5518 condition.
5520 Don't do anything if all operands are very simple. */
5533 {
5538 /* If everything is a comparison, what we have is highly unlikely
5539 to be simpler, so don't use it. */
5542 {
5549 /* Simplify the alternative arms; this may collapse the true and
5550 false arms to store-flag values. Be careful to use copy_rtx
5551 here since true_rtx or false_rtx might share RTL with x as a
5552 result of the if_then_else_cond call above. */
5556 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5557 is unlikely to be simpler. */
5560 {
5563 /* Restarting if we generate a store-flag expression will cause
5564 us to loop. Just drop through in this case. */
5566 /* If the result values are STORE_FLAG_VALUE and zero, we can
5567 just make the comparison operation. */
5578 /* Likewise, we can make the negate of a comparison operation
5579 if the result values are - STORE_FLAG_VALUE and zero. */
5587 mode);
5598 mode);
5599 else
5602 mode,
5603 VOIDmode,
5604 cond,
5605 cop1),
5610 }
5611 }
5612 }
5614 /* Try to fold this expression in case we have constants that weren't
5615 present before. */
5618 {
5626 {
5629 {
5633 }
5636 }
5649 }
5652 {
5657 }
5659 /* First see if we can apply the inverse distributive law. */
5662 {
5666 }
5668 /* If CODE is an associative operation not otherwise handled, see if we
5669 can associate some operands. This can win if they are constants or
5670 if they are logically related (i.e. (a & b) & a). */
5676 {
5678 {
5682 rtx inner;
5684 /* Make sure we pass the constant operand if any as the second
5685 one if this is a commutative operation. */
5693 /* For commutative operations, try the other pair if that one
5694 didn't simplify. */
5696 {
5701 }
5705 }
5706 }
5708 /* A little bit of algebraic simplification here. */
5710 {
5712 /* Ensure that our address has any ASHIFTs converted to MULT in case
5713 address-recognizing predicates are called later. */
5722 /* See if this can be moved to simplify_subreg. */
5725 /* Don't call gen_lowpart if the inner mode
5726 is VOIDmode and we cannot simplify it, as SUBREG without
5727 inner mode is invalid. */
5734 {
5735 rtx temp;
5741 /* If op is known to have all lower bits zero, the result is zero. */
5751 }
5753 /* Don't change the mode of the MEM if that would change the meaning
5754 of the address. */
5761 /* Note that we cannot do any narrowing for non-constants since
5762 we might have been counting on using the fact that some bits were
5763 zero. We now do this in the SET. */
5770 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5771 replaced by (lshiftrt X C). This will convert
5772 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5780 /* If X has only a single bit that might be nonzero, say, bit I, convert
5781 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5782 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5783 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5784 or a SUBREG of one since we'd be making the expression more
5785 complex if it was just a register. */
5791 {
5792 rtx temp1 = simplify_shift_const
5798 /* If all we did was surround TEMP with the two shifts, we
5799 haven't improved anything, so don't use it. Otherwise,
5800 we are better off with TEMP1. */
5805 }
5809 /* We can't handle truncation to a partial integer mode here
5810 because we don't know the real bitsize of the partial
5811 integer mode. */
5820 /* We can truncate a constant value and return it. */
5824 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5825 whose value is a comparison can be replaced with a subreg if
5826 STORE_FLAG_VALUE permits. */
5835 /* (const (const X)) can become (const X). Do it this way rather than
5836 returning the inner CONST since CONST can be shared with a
5837 REG_EQUAL note. */
5843 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5844 can add in an offset. find_split_point will split this address up
5845 again if it doesn't match. */
5852 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5853 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5854 bit-field and can be replaced by either a sign_extend or a
5855 sign_extract. The `and' may be a zero_extend and the two
5856 <c>, -<c> constants may be reversed. */
5871 return simplify_shift_const
5878 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5879 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5880 the bitsize of the mode - 1. This allows simplification of
5881 "a = (b & 8) == 0;" */
5893 /* If we are adding two things that have no bits in common, convert
5894 the addition into an IOR. This will often be further simplified,
5895 for example in cases like ((a & 1) + (a & 2)), which can
5896 become a & 3. */
5901 {
5902 /* Try to simplify the expression further. */
5906 /* If we could, great. If not, do not go ahead with the IOR
5907 replacement, since PLUS appears in many special purpose
5908 address arithmetic instructions. */
5916 }
5920 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5921 (and <foo> (const_int pow2-1)) */
5931 /* If we have (mult (plus A B) C), apply the distributive law and then
5932 the inverse distributive law to see if things simplify. This
5933 occurs mostly in addresses, often when unrolling loops. */
5936 {
5940 }
5942 /* Try simplify a*(b/c) as (a*b)/c. */
5945 {
5951 }
5955 /* If this is a divide by a power of two, treat it as a shift if
5956 its first operand is a shift. */
5974 /* If the first operand is a condition code, we can't do anything
5975 with it. */
5979 {
5987 /* Simplify our comparison, if possible. */
5990 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5991 if only the low-order bit is possibly nonzero in X (such as when
5992 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5993 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5994 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5995 (plus X 1).
5997 Remove any ZERO_EXTRACT we made when thinking this was a
5998 comparison. It may now be simpler to use, e.g., an AND. If a
5999 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6000 the call to make_compound_operation in the SET case.
6002 Don't apply these optimizations if the caller would
6003 prefer a comparison rather than a value.
6004 E.g., for the condition in an IF_THEN_ELSE most targets need
6005 an explicit comparison. */
6008 ;
6024 {
6028 mode);
6029 }
6036 {
6040 const1_rtx);
6041 }
6049 {
6052 }
6054 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6055 those above. */
6057 ;
6073 {
6077 mode);
6078 }
6086 {
6090 mode);
6091 }
6093 /* If X is 0/1, (eq X 0) is X-1. */
6099 {
6102 }
6104 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6105 one bit that might be nonzero, we can convert (ne x 0) to
6106 (ashift x c) where C puts the bit in the sign bit. Remove any
6107 AND with STORE_FLAG_VALUE when we are done, since we are only
6108 going to test the sign bit. */
6115 {
6121 else
6123 }
6125 /* If the code changed, return a whole new comparison.
6126 We also need to avoid using SUBST in cases where
6127 simplify_comparison has widened a comparison with a CONST_INT,
6128 since in that case the wider CONST_INT may fail the sanity
6129 checks in do_SUBST. */
6136 /* Otherwise, keep this operation, but maybe change its operands.
6137 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6140 }
6150 /* If we are processing SET_DEST, we are done. */
6168 /* If this is a shift by a constant amount, simplify it. */
6184 }
6187 }
6188 \f
6189 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6191 static rtx
6193 {
6200 rtx temp;
6203 rtx reversed;
6205 /* Simplify storing of the truth value. */
6210 /* Also when the truth value has to be reversed. */
6216 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6217 in it is being compared against certain values. Get the true and false
6218 comparisons and see if that says anything about the value of each arm. */
6224 {
6225 HOST_WIDE_INT nzb;
6231 /* If FALSE_CODE is EQ, swap the codes and arms. */
6234 {
6237 }
6239 /* If we are comparing against zero and the expression being tested has
6240 only a single bit that might be nonzero, that is its value when it is
6241 not equal to zero. Similarly if it is known to be -1 or 0. */
6245 {
6248 }
6252 {
6255 }
6257 /* Now simplify an arm if we know the value of the register in the
6258 branch and it is used in the arm. Be careful due to the potential
6259 of locally-shared RTL. */
6276 }
6278 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6279 reversed, do so to avoid needing two sets of patterns for
6280 subtract-and-branch insns. Similarly if we have a constant in the true
6281 arm, the false arm is the same as the first operand of the comparison, or
6282 the false arm is more complicated than the true arm. */
6295 {
6304 /* It is possible that the conditional has been simplified out. */
6307 }
6309 /* If the two arms are identical, we don't need the comparison. */
6314 /* Convert a == b ? b : a to "a". */
6326 /* Look for cases where we have (abs x) or (neg (abs X)). */
6329 && comparison_p
6336 {
6342 return
6345 mode);
6348 }
6350 /* Look for MIN or MAX. */
6353 && comparison_p
6358 {
6373 }
6375 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6376 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6377 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6378 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6379 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6380 neither 1 or -1, but it isn't worth checking for. */
6383 && comparison_p
6386 {
6402 /* If an identity-zero op is commutative, check whether there
6403 would be a match if we swapped the operands. */
6423 {
6427 }
6439 {
6443 }
6459 {
6463 }
6475 {
6479 }
6482 {
6488 const_true_rtx));
6496 }
6497 }
6499 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6500 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6501 negation of a single bit, we can convert this operation to a shift. We
6502 can actually do this more generally, but it doesn't seem worth it. */
6511 return
6515 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6525 }
6526 \f
6527 /* Simplify X, a SET expression. Return the new expression. */
6529 static rtx
6531 {
6534 machine_mode mode
6539 /* (set (pc) (return)) gets written as (return). */
6543 /* Now that we know for sure which bits of SRC we are using, see if we can
6544 simplify the expression for the object knowing that we only need the
6545 low-order bits. */
6548 {
6551 }
6553 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6554 the comparison result and try to simplify it unless we already have used
6555 undobuf.other_insn. */
6563 {
6572 {
6575 {
6578 }
6579 }
6580 else
6588 {
6592 }
6593 else
6594 {
6599 /* Attempt to simplify CC user. */
6601 {
6605 }
6607 /* Convert X into a no-op move. */
6611 }
6613 /* Simplify our comparison, if possible. */
6616 #ifdef SELECT_CC_MODE
6617 /* If this machine has CC modes other than CCmode, check to see if we
6618 need to use a different CC mode here. */
6627 else
6630 /* If the mode changed, we have to change SET_DEST, the mode in the
6631 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6632 a hard register, just build new versions with the proper mode. If it
6633 is a pseudo, we lose unless it is only time we set the pseudo, in
6634 which case we can safely change its mode. */
6636 {
6638 {
6640 rtx new_dest;
6644 else
6645 {
6648 }
6655 }
6656 }
6659 /* If the code changed, we have to build a new comparison in
6660 undobuf.other_insn. */
6662 {
6671 /* If the only change we made was to change an EQ into an NE or
6672 vice versa, OP0 has only one bit that might be nonzero, and OP1
6673 is zero, check if changing the user of the condition code will
6674 produce a valid insn. If it won't, we can keep the original code
6675 in that insn by surrounding our operation with an XOR. */
6682 {
6687 {
6694 }
6695 }
6696 }
6701 /* Don't generate a compare of a CC with 0, just use that CC. */
6703 {
6706 }
6707 /* Otherwise, if we didn't previously have the same COMPARE we
6708 want, create it from scratch. */
6711 {
6714 }
6715 }
6716 else
6717 {
6718 /* Get SET_SRC in a form where we have placed back any
6719 compound expressions. Then do the checks below. */
6722 }
6724 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6725 and X being a REG or (subreg (reg)), we may be able to convert this to
6726 (set (subreg:m2 x) (op)).
6728 We can always do this if M1 is narrower than M2 because that means that
6729 we only care about the low bits of the result.
6731 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6732 perform a narrower operation than requested since the high-order bits will
6733 be undefined. On machine where it is defined, this transformation is safe
6734 as long as M1 and M2 have the same number of words. */
6742 #ifndef WORD_REGISTER_OPERATIONS
6745 #endif
6746 #ifdef CANNOT_CHANGE_MODE_CLASS
6751 #endif
6755 {
6758 dest));
6762 }
6764 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6765 in SRC. */
6771 {
6775 /* Here we make sure that we don't have a sign bit on. */
6778 {
6781 }
6782 }
6784 #ifdef LOAD_EXTEND_OP
6785 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6786 would require a paradoxical subreg. Replace the subreg with a
6787 zero_extend to avoid the reload that would otherwise be required. */
6795 {
6801 }
6802 #endif
6804 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6805 are comparing an item known to be 0 or -1 against 0, use a logical
6806 operation instead. Check for one of the arms being an IOR of the other
6807 arm with some value. We compute three terms to be IOR'ed together. In
6808 practice, at most two will be nonzero. Then we do the IOR's. */
6816 && (!HAVE_conditional_move
6822 {
6848 false_rtx);
6854 term3));
6857 }
6859 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6860 whole thing fail. */
6865 else
6866 /* Convert this into a field assignment operation, if possible. */
6868 }
6869 \f
6870 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6871 result. */
6873 static rtx
6875 {
6881 {
6883 /* We can call simplify_and_const_int only if we don't lose
6884 any (sign) bits when converting INTVAL (op1) to
6885 "unsigned HOST_WIDE_INT". */
6889 {
6896 }
6898 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6899 apply the distributive law and then the inverse distributive
6900 law to see if things simplify. */
6902 {
6906 }
6908 {
6912 }
6916 /* If we have (ior (and A B) C), apply the distributive law and then
6917 the inverse distributive law to see if things simplify. */
6920 {
6924 }
6927 {
6931 }
6936 }
6939 }
6940 \f
6941 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6942 operations" because they can be replaced with two more basic operations.
6943 ZERO_EXTEND is also considered "compound" because it can be replaced with
6944 an AND operation, which is simpler, though only one operation.
6946 The function expand_compound_operation is called with an rtx expression
6947 and will convert it to the appropriate shifts and AND operations,
6948 simplifying at each stage.
6950 The function make_compound_operation is called to convert an expression
6951 consisting of shifts and ANDs into the equivalent compound expression.
6952 It is the inverse of this function, loosely speaking. */
6954 static rtx
6956 {
6960 rtx tem;
6963 {
6967 /* We can't necessarily use a const_int for a multiword mode;
6968 it depends on implicitly extending the value.
6969 Since we don't know the right way to extend it,
6970 we can't tell whether the implicit way is right.
6972 Even for a mode that is no wider than a const_int,
6973 we can't win, because we need to sign extend one of its bits through
6974 the rest of it, and we don't know which bit. */
6978 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6979 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6980 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6981 reloaded. If not for that, MEM's would very rarely be safe.
6983 Reject MODEs bigger than a word, because we might not be able
6984 to reference a two-register group starting with an arbitrary register
6985 (and currently gen_lowpart might crash for a SUBREG). */
6990 /* Reject MODEs that aren't scalar integers because turning vector
6991 or complex modes into shifts causes problems. */
6997 /* If the inner object has VOIDmode (the only way this can happen
6998 is if it is an ASM_OPERANDS), we can't do anything since we don't
6999 know how much masking to do. */
7008 /* ... fall through ... */
7011 /* If the operand is a CLOBBER, just return it. */
7020 /* Reject MODEs that aren't scalar integers because turning vector
7021 or complex modes into shifts causes problems. */
7029 /* This should stay within the object being extracted, fail otherwise. */
7040 }
7041 /* Convert sign extension to zero extension, if we know that the high
7042 bit is not set, as this is easier to optimize. It will be converted
7043 back to cheaper alternative in make_extraction. */
7051 {
7055 /* Make sure this is a profitable operation. */
7062 else
7064 }
7066 /* We can optimize some special cases of ZERO_EXTEND. */
7068 {
7069 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7070 know that the last value didn't have any inappropriate bits
7071 set. */
7079 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7088 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7089 is a comparison and STORE_FLAG_VALUE permits. This is like
7090 the first case, but it works even when GET_MODE (x) is larger
7091 than HOST_WIDE_INT. */
7100 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7110 }
7112 /* If we reach here, we want to return a pair of shifts. The inner
7113 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7114 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7115 logical depending on the value of UNSIGNEDP.
7117 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7118 converted into an AND of a shift.
7120 We must check for the case where the left shift would have a negative
7121 count. This can happen in a case like (x >> 31) & 255 on machines
7122 that can't shift by a constant. On those machines, we would first
7123 combine the shift with the AND to produce a variable-position
7124 extraction. Then the constant of 31 would be substituted in
7125 to produce such a position. */
7129 {
7138 }
7145 else
7146 /* Any other cases we can't handle. */
7149 /* If we couldn't do this for some reason, return the original
7150 expression. */
7155 }
7156 \f
7157 /* X is a SET which contains an assignment of one object into
7158 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7159 or certain SUBREGS). If possible, convert it into a series of
7160 logical operations.
7162 We half-heartedly support variable positions, but do not at all
7163 support variable lengths. */
7165 static const_rtx
7167 {
7168 rtx inner;
7172 machine_mode compute_mode;
7174 /* Loop until we find something we can't simplify. */
7176 {
7179 {
7183 }
7186 {
7191 /* A constant position should stay within the width of INNER. */
7197 {
7205 /* If position is ADJUST - X, new position is X. */
7207 else
7208 {
7213 pos);
7214 }
7215 }
7216 }
7218 /* A SUBREG between two modes that occupy the same numbers of words
7219 can be done by moving the SUBREG to the source. */
7221 /* We need SUBREGs to compute nonzero_bits properly. */
7222 && nonzero_sign_valid
7227 {
7229 gen_lowpart
7233 }
7234 else
7242 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7244 {
7245 machine_mode imode;
7247 /* Don't do anything for vector or complex integral types. */
7251 /* Try to find an integral mode to pun with. */
7258 }
7260 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7264 /* Now compute the equivalent expression. Make a copy of INNER
7265 for the SET_DEST in case it is a MEM into which we will substitute;
7266 we don't want shared RTL in that case. */
7268 compute_mode);
7272 compute_mode,
7274 compute_mode),
7275 inner);
7280 mask),
7281 pos);
7286 }
7289 }
7290 \f
7291 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7292 it is an RTX that represents the (variable) starting position; otherwise,
7293 POS is the (constant) starting bit position. Both are counted from the LSB.
7295 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7297 IN_DEST is nonzero if this is a reference in the destination of a SET.
7298 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7299 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7300 be used.
7302 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7303 ZERO_EXTRACT should be built even for bits starting at bit 0.
7305 MODE is the desired mode of the result (if IN_DEST == 0).
7307 The result is an RTX for the extraction or NULL_RTX if the target
7308 can't handle it. */
7310 static rtx
7314 {
7315 /* This mode describes the size of the storage area
7316 to fetch the overall value from. Within that, we
7317 ignore the POS lowest bits, etc. */
7319 machine_mode inner_mode;
7320 machine_mode wanted_inner_mode;
7327 HOST_WIDE_INT orig_pos;
7333 {
7334 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7335 consider just the QI as the memory to extract from.
7336 The subreg adds or removes high bits; its mode is
7337 irrelevant to the meaning of this extraction,
7338 since POS and LEN count from the lsb. */
7342 }
7347 {
7348 /* We're extracting the least significant bits of an rtx
7349 (ashift X (const_int C)), where LEN > C. Extract the
7350 least significant (LEN - C) bits of X, giving an rtx
7351 whose mode is MODE, then shift it left C times. */
7357 }
7363 /* See if this can be done without an extraction. We never can if the
7364 width of the field is not the same as that of some integer mode. For
7365 registers, we can only avoid the extraction if the position is at the
7366 low-order bit and this is either not in the destination or we have the
7367 appropriate STRICT_LOW_PART operation available.
7369 For MEM, we can avoid an extract if the field starts on an appropriate
7370 boundary and we can change the mode of the memory reference. */
7379 && (! in_dest
7383 && (pos
7386 /* We can't do this if we are widening INNER_MODE (it
7387 may not be aligned, for one thing). */
7393 {
7394 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7395 field. If the original and current mode are the same, we need not
7396 adjust the offset. Otherwise, we do if bytes big endian.
7398 If INNER is not a MEM, get a piece consisting of just the field
7399 of interest (in this case POS % BITS_PER_WORD must be 0). */
7402 {
7403 HOST_WIDE_INT offset;
7405 /* POS counts from lsb, but make OFFSET count in memory order. */
7408 else
7412 }
7414 {
7416 {
7417 /* We can't call gen_lowpart in a DEST since we
7418 always want a SUBREG (see below) and it would sometimes
7419 return a new hard register. */
7421 {
7436 /* Avoid creating invalid subregs, for example when
7437 simplifying (x>>32)&255. */
7442 }
7443 else
7445 }
7446 else
7448 }
7449 else
7451 len >= HOST_BITS_PER_WIDE_INT
7456 /* If this extraction is going into the destination of a SET,
7457 make a STRICT_LOW_PART unless we made a MEM. */
7472 /* If we know that no extraneous bits are set, and that the high
7473 bit is not set, convert the extraction to the cheaper of
7474 sign and zero extension, that are equivalent in these cases. */
7480 {
7484 /* Prefer ZERO_EXTENSION, since it gives more information to
7485 backends. */
7490 }
7492 /* Otherwise, sign- or zero-extend unless we already are in the
7493 proper mode. */
7497 }
7499 /* Unless this is a COMPARE or we have a funny memory reference,
7500 don't do anything with zero-extending field extracts starting at
7501 the low-order bit since they are simple AND operations. */
7506 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7507 if the position is not a constant and the length is not 1. In all
7508 other cases, we would only be going outside our object in cases when
7509 an original shift would have been undefined. */
7518 /* If INNER is not from memory, we want it to have the mode of a register
7519 extraction pattern's structure operand, or word_mode if there is no
7520 such pattern. The same applies to extraction_mode and pos_mode
7521 and their respective operands.
7523 For memory, assume that the desired extraction_mode and pos_mode
7524 are the same as for a register operation, since at present we don't
7525 have named patterns for aligned memory structures. */
7529 {
7533 }
7535 /* Never narrow an object, since that might not be safe. */
7543 else
7544 {
7545 /* Be careful not to go beyond the extracted object and maintain the
7546 natural alignment of the memory. */
7550 {
7553 }
7554 }
7559 {
7560 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7561 BITS_BIG_ENDIAN style. If position is constant, compute new
7562 position. Otherwise, build subtraction.
7563 Note that POS is relative to the mode of the original argument.
7564 If it's a MEM we need to recompute POS relative to that.
7565 However, if we're extracting from (or inserting into) a register,
7566 we want to recompute POS relative to wanted_inner_mode. */
7573 else
7574 pos_rtx
7577 pos_rtx);
7578 /* POS may be less than 0 now, but we check for that below.
7579 Note that it can only be less than 0 if !MEM_P (inner). */
7580 }
7582 /* If INNER has a wider mode, and this is a constant extraction, try to
7583 make it smaller and adjust the byte to point to the byte containing
7584 the value. */
7587 && ! pos_rtx
7592 {
7595 /* The computations below will be correct if the machine is big
7596 endian in both bits and bytes or little endian in bits and bytes.
7597 If it is mixed, we must adjust. */
7599 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7600 adjust OFFSET to compensate. */
7605 /* We can now move to the desired byte. */
7616 }
7618 /* If INNER is not memory, get it into the proper mode. If we are changing
7619 its mode, POS must be a constant and smaller than the size of the new
7620 mode. */
7622 {
7623 /* On the LHS, don't create paradoxical subregs implicitely truncating
7624 the register unless TRULY_NOOP_TRUNCATION. */
7627 wanted_inner_mode))
7639 pos_rtx
7645 }
7647 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7648 have to zero extend. Otherwise, we can just use a SUBREG. */
7651 {
7655 /* If we know that no extraneous bits are set, and that the high
7656 bit is not set, convert extraction to cheaper one - either
7657 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7658 cases. */
7666 {
7670 /* Prefer ZERO_EXTENSION, since it gives more information to
7671 backends. */
7675 }
7677 }
7679 /* Make POS_RTX unless we already have it and it is correct. If we don't
7680 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7681 be a CONST_INT. */
7688 /* Make the required operation. See if we can use existing rtx. */
7695 }
7696 \f
7697 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7698 with any other operations in X. Return X without that shift if so. */
7700 static rtx
7702 {
7705 rtx tem;
7708 {
7710 /* This is the shift itself. If it is wide enough, we will return
7711 either the value being shifted if the shift count is equal to
7712 COUNT or a shift for the difference. */
7726 /* If we can safely shift this constant and we find the inner shift,
7727 make a new operation. */
7732 {
7736 }
7741 }
7744 }
7745 \f
7746 /* Look at the expression rooted at X. Look for expressions
7747 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7748 Form these expressions.
7750 Return the new rtx, usually just X.
7752 Also, for machines like the VAX that don't have logical shift insns,
7753 try to convert logical to arithmetic shift operations in cases where
7754 they are equivalent. This undoes the canonicalizations to logical
7755 shifts done elsewhere.
7757 We try, as much as possible, to re-use rtl expressions to save memory.
7759 IN_CODE says what kind of expression we are processing. Normally, it is
7760 SET. In a memory address it is MEM. When processing the arguments of
7761 a comparison or a COMPARE against zero, it is COMPARE. */
7763 rtx
7765 {
7773 rtx tem;
7776 /* Select the code to be used in recursive calls. Once we are inside an
7777 address, we stay there. If we have a comparison, set to COMPARE,
7778 but once inside, go back to our default of SET. */
7785 /* Process depending on the code of this operation. If NEW is set
7786 nonzero, it will be returned. */
7789 {
7791 /* Convert shifts by constants into multiplications if inside
7792 an address. */
7797 {
7803 {
7806 }
7809 }
7819 {
7823 }
7826 {
7830 mode));
7832 }
7833 else
7834 {
7838 }
7849 {
7853 }
7856 {
7860 mode));
7862 }
7863 else
7864 {
7868 }
7872 /* If the second operand is not a constant, we can't do anything
7873 with it. */
7877 /* If the constant is a power of two minus one and the first operand
7878 is a logical right shift, make an extraction. */
7881 {
7885 }
7887 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7892 {
7894 next_code);
7898 }
7899 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7905 {
7906 /* Apply the distributive law, and then try to make extractions. */
7913 }
7915 /* If we are have (and (rotate X C) M) and C is larger than the number
7916 of bits in M, this is an extraction. */
7922 {
7928 }
7930 /* On machines without logical shifts, if the operand of the AND is
7931 a logical shift and our mask turns off all the propagated sign
7932 bits, we can replace the logical shift with an arithmetic shift. */
7940 {
7947 make_compound_operation
7950 }
7952 /* If the constant is one less than a power of two, this might be
7953 representable by an extraction even if no shift is present.
7954 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7955 we are in a COMPARE. */
7959 next_code),
7962 /* If we are in a comparison and this is an AND with a power of two,
7963 convert this into the appropriate bit extract. */
7968 next_code),
7974 /* If the sign bit is known to be zero, replace this with an
7975 arithmetic shift. */
7980 {
7983 next_code),
7986 }
7988 /* ... fall through ... */
7994 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7995 this is a SIGN_EXTRACT. */
8002 {
8009 }
8011 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8012 If so, try to merge the shifts into a SIGN_EXTEND. We could
8013 also do this for some cases of SIGN_EXTRACT, but it doesn't
8014 seem worth the effort; the case checked for occurs on Alpha. */
8030 /* Call ourselves recursively on the inner expression. If we are
8031 narrowing the object and it has a different RTL code from
8032 what it originally did, do this SUBREG as a force_to_mode. */
8033 {
8037 /* If in_code is COMPARE, it isn't always safe to pass it through
8038 to the recursive make_compound_operation call. */
8042 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8043 is (const_int 0), rather than
8044 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8054 simplified
8062 {
8063 rtx newer
8066 /* If we have something other than a SUBREG, we might have
8067 done an expansion, so rerun ourselves. */
8071 /* force_to_mode can expand compounds. If it just re-expanded the
8072 compound, use gen_lowpart to convert to the desired mode. */
8074 /* Likewise if it re-expanded the compound only partially.
8075 This happens for SUBREG of ZERO_EXTRACT if they extract
8076 the same number of bits. */
8085 }
8089 }
8094 }
8097 {
8100 }
8102 /* Now recursively process each operand of this operation. We need to
8103 handle ZERO_EXTEND specially so that we don't lose track of the
8104 inner mode. */
8106 {
8114 }
8119 {
8122 }
8125 {
8128 }
8130 maybe_swap:
8131 /* If this is a commutative operation, the changes to the operands
8132 may have made it noncanonical. */
8135 {
8139 }
8142 }
8143 \f
8144 /* Given M see if it is a value that would select a field of bits
8145 within an item, but not the entire word. Return -1 if not.
8146 Otherwise, return the starting position of the field, where 0 is the
8147 low-order bit.
8149 *PLEN is set to the length of the field. */
8151 static int
8153 {
8154 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8159 /* Now shift off the low-order zero bits and see if we have a
8160 power of two minus 1. */
8168 }
8169 \f
8170 /* If X refers to a register that equals REG in value, replace these
8171 references with REG. */
8172 static rtx
8174 {
8182 {
8218 {
8222 else
8224 }
8226 /* fall through */
8233 {
8236 {
8238 {
8241 }
8243 }
8244 }
8246 {
8249 {
8252 {
8254 {
8257 }
8259 }
8260 }
8261 }
8264 }
8267 }
8269 /* Return X converted to MODE. If the value is already truncated to
8270 MODE we can just return a subreg even though in the general case we
8271 would need an explicit truncation. */
8273 static rtx
8275 {
8280 {
8281 /* Bit-cast X into an integer mode. */
8286 }
8289 }
8291 /* See if X can be simplified knowing that we will only refer to it in
8292 MODE and will only refer to those bits that are nonzero in MASK.
8293 If other bits are being computed or if masking operations are done
8294 that select a superset of the bits in MASK, they can sometimes be
8295 ignored.
8297 Return a possibly simplified expression, but always convert X to
8298 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8300 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8301 are all off in X. This is used when X will be complemented, by either
8302 NOT, NEG, or XOR. */
8304 static rtx
8307 {
8310 machine_mode op_mode;
8314 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8315 code below will do the wrong thing since the mode of such an
8316 expression is VOIDmode.
8318 Also do nothing if X is a CLOBBER; this can happen if X was
8319 the return value from a call to gen_lowpart. */
8323 /* We want to perform the operation in its present mode unless we know
8324 that the operation is valid in MODE, in which case we do the operation
8325 in MODE. */
8330 /* It is not valid to do a right-shift in a narrower mode
8331 than the one it came in with. */
8336 /* Truncate MASK to fit OP_MODE. */
8340 /* When we have an arithmetic operation, or a shift whose count we
8341 do not know, we need to assume that all bits up to the highest-order
8342 bit in MASK will be needed. This is how we form such a mask. */
8345 else
8349 /* Determine what bits of X are guaranteed to be (non)zero. */
8352 /* If none of the bits in X are needed, return a zero. */
8356 /* If X is a CONST_INT, return a new one. Do this here since the
8357 test below will fail. */
8359 {
8362 else
8363 {
8366 }
8367 }
8369 /* If X is narrower than MODE and we want all the bits in X's mode, just
8370 get X in the proper mode. */
8375 /* We can ignore the effect of a SUBREG if it narrows the mode or
8376 if the constant masks to zero all the bits the mode doesn't have. */
8386 /* The arithmetic simplifications here only work for scalar integer modes. */
8391 {
8393 /* If X is a (clobber (const_int)), return it since we know we are
8394 generating something that won't match. */
8407 /* Similarly for a truncate. */
8411 /* If this is an AND with a constant, convert it into an AND
8412 whose constant is the AND of that constant with MASK. If it
8413 remains an AND of MASK, delete it since it is redundant. */
8416 {
8420 /* If X is still an AND, see if it is an AND with a mask that
8421 is just some low-order bits. If so, and it is MASK, we don't
8422 need it. */
8429 /* If it remains an AND, try making another AND with the bits
8430 in the mode mask that aren't in MASK turned on. If the
8431 constant in the AND is wide enough, this might make a
8432 cheaper constant. */
8437 {
8438 unsigned HOST_WIDE_INT cval
8441 rtx y;
8448 }
8451 }
8456 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8457 low-order bits (as in an alignment operation) and FOO is already
8458 aligned to that boundary, mask C1 to that boundary as well.
8459 This may eliminate that PLUS and, later, the AND. */
8461 {
8465 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8466 number, sign extend it. */
8479 }
8481 /* ... fall through ... */
8484 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8485 most significant bit in MASK since carries from those bits will
8486 affect the bits we are interested in. */
8491 /* If X is (minus C Y) where C's least set bit is larger than any bit
8492 in the mask, then we may replace with (neg Y). */
8495 {
8499 }
8501 /* Similarly, if C contains every bit in the fuller_mask, then we may
8502 replace with (not Y). */
8505 {
8509 }
8516 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8517 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8518 operation which may be a bitfield extraction. Ensure that the
8519 constant we form is not wider than the mode of X. */
8531 {
8540 }
8542 binop:
8543 /* For most binary operations, just propagate into the operation and
8544 change the mode if we have an operation of that mode. */
8549 /* If we ended up truncating both operands, truncate the result of the
8550 operation instead. */
8553 {
8556 }
8566 /* For left shifts, do the same, but just for the first operand.
8567 However, we cannot do anything with shifts where we cannot
8568 guarantee that the counts are smaller than the size of the mode
8569 because such a count will have a different meaning in a
8570 wider mode. */
8580 /* If the shift count is a constant and we can do arithmetic in
8581 the mode of the shift, refine which bits we need. Otherwise, use the
8582 conservative form of the mask. */
8588 else
8600 /* Here we can only do something if the shift count is a constant,
8601 this shift constant is valid for the host, and we can do arithmetic
8602 in OP_MODE. */
8608 {
8612 /* Select the mask of the bits we need for the shift operand. */
8615 /* We can only change the mode of the shift if we can do arithmetic
8616 in the mode of the shift and INNER_MASK is no wider than the
8617 width of X's mode. */
8625 }
8627 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8628 shift and AND produces only copies of the sign bit (C2 is one less
8629 than a power of two), we can do this with just a shift. */
8633 /* The shift puts one of the sign bit copies in the least significant
8634 bit. */
8639 /* Number of bits left after the shift must be more than the mask
8640 needs. */
8643 /* Must be more sign bit copies than the mask needs. */
8653 /* If we are just looking for the sign bit, we don't need this shift at
8654 all, even if it has a variable count. */
8658 /* If this is a shift by a constant, get a mask that contains those bits
8659 that are not copies of the sign bit. We then have two cases: If
8660 MASK only includes those bits, this can be a logical shift, which may
8661 allow simplifications. If MASK is a single-bit field not within
8662 those bits, we are requesting a copy of the sign bit and hence can
8663 shift the sign bit to the appropriate location. */
8667 {
8670 /* If the considered data is wider than HOST_WIDE_INT, we can't
8671 represent a mask for all its bits in a single scalar.
8672 But we only care about the lower bits, so calculate these. */
8675 {
8678 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8679 is the number of bits a full-width mask would have set.
8680 We need only shift if these are fewer than nonzero can
8681 hold. If not, we must keep all bits set in nonzero. */
8686 + HOST_BITS_PER_WIDE_INT
8688 }
8689 else
8690 {
8693 }
8696 {
8701 }
8704 {
8705 x = simplify_shift_const
8711 }
8712 }
8714 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8715 even if the shift count isn't a constant. */
8720 shiftrt:
8722 /* If this is a zero- or sign-extension operation that just affects bits
8723 we don't care about, remove it. Be sure the call above returned
8724 something that is still a shift. */
8734 next_select);
8740 /* If the shift count is constant and we can do computations
8741 in the mode of X, compute where the bits we care about are.
8742 Otherwise, we can't do anything. Don't change the mode of
8743 the shift or propagate MODE into the shift, though. */
8746 {
8756 }
8760 /* If we just want the low-order bit, the NEG isn't needed since it
8761 won't change the low-order bit. */
8765 /* We need any bits less significant than the most significant bit in
8766 MASK since carries from those bits will affect the bits we are
8767 interested in. */
8772 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8773 same as the XOR case above. Ensure that the constant we form is not
8774 wider than the mode of X. */
8782 {
8791 }
8793 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8794 use the full mask inside the NOT. */
8797 unop:
8800 next_select));
8806 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8807 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8808 which is equal to STORE_FLAG_VALUE. */
8820 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8821 written in a narrower mode. We play it safe and do not do so. */
8837 }
8839 /* Ensure we return a value of the proper mode. */
8841 }
8842 \f
8843 /* Return nonzero if X is an expression that has one of two values depending on
8844 whether some other value is zero or nonzero. In that case, we return the
8845 value that is being tested, *PTRUE is set to the value if the rtx being
8846 returned has a nonzero value, and *PFALSE is set to the other alternative.
8848 If we return zero, we set *PTRUE and *PFALSE to X. */
8850 static rtx
8852 {
8858 /* If we are comparing a value against zero, we are done. */
8861 {
8865 }
8867 /* If this is a unary operation whose operand has one of two values, apply
8868 our opcode to compute those values. */
8871 {
8876 }
8878 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8879 make can't possibly match and would suppress other optimizations. */
8881 ;
8883 /* If this is a binary operation, see if either side has only one of two
8884 values. If either one does or if both do and they are conditional on
8885 the same value, compute the new true and false values. */
8887 {
8893 {
8894 /* If if_then_else_cond returned zero, then true/false are the
8895 same rtl. We must copy one of them to prevent invalid rtl
8896 sharing. */
8903 {
8908 }
8909 else
8910 {
8913 }
8916 }
8918 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8919 operands is zero when the other is nonzero, and vice-versa,
8920 and STORE_FLAG_VALUE is 1 or -1. */
8926 {
8943 {
8950 const_true_rtx);
8952 }
8953 }
8955 /* Similarly for MULT, AND and UMIN, except that for these the result
8956 is always zero. */
8960 {
8974 {
8977 }
8978 }
8979 }
8982 {
8983 /* If we have IF_THEN_ELSE already, extract the condition and
8984 canonicalize it if it is NE or EQ. */
8990 {
8993 }
8994 else
8996 }
8998 /* If X is a SUBREG, we can narrow both the true and false values
8999 if the inner expression, if there is a condition. */
9003 {
9009 {
9013 }
9014 }
9016 /* If X is a constant, this isn't special and will cause confusions
9017 if we treat it as such. Likewise if it is equivalent to a constant. */
9020 ;
9022 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9023 will be least confusing to the rest of the compiler. */
9025 {
9028 }
9030 /* If X is known to be either 0 or -1, those are the true and
9031 false values when testing X. */
9035 {
9038 }
9040 /* Likewise for 0 or a single bit. */
9043 {
9046 }
9048 /* Otherwise fail; show no condition with true and false values the same. */
9051 }
9052 \f
9053 /* Return the value of expression X given the fact that condition COND
9054 is known to be true when applied to REG as its first operand and VAL
9055 as its second. X is known to not be shared and so can be modified in
9056 place.
9058 We only handle the simplest cases, and specifically those cases that
9059 arise with IF_THEN_ELSE expressions. */
9061 static rtx
9063 {
9071 /* If either operand of the condition is a floating point value,
9072 then we have to avoid collapsing an EQ comparison. */
9082 /* If X is (abs REG) and we know something about REG's relationship
9083 with zero, we may be able to simplify this. */
9087 {
9096 }
9098 /* The only other cases we handle are MIN, MAX, and comparisons if the
9099 operands are the same as REG and VAL. */
9102 {
9104 {
9107 }
9110 {
9112 {
9120 else
9122 }
9125 {
9128 /* Do not reverse the condition when it is NE or EQ.
9129 This is because we cannot conclude anything about
9130 the value of 'SMAX (x, y)' when x is not equal to y,
9131 but we can when x equals y. */
9137 {
9148 }
9149 }
9150 }
9151 }
9153 {
9158 {
9159 /* We must simplify subreg here, before we lose track of the
9160 original inner_mode. */
9165 else
9167 }
9170 }
9171 /* We don't have to handle SIGN_EXTEND here, because even in the
9172 case of replacing something with a modeless CONST_INT, a
9173 CONST_INT is already (supposed to be) a valid sign extension for
9174 its narrower mode, which implies it's already properly
9175 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9176 story is different. */
9178 {
9183 {
9184 /* We must simplify the zero_extend here, before we lose
9185 track of the original inner_mode. */
9190 else
9192 }
9195 }
9199 {
9206 }
9209 }
9210 \f
9211 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9212 assignment as a field assignment. */
9214 static int
9216 {
9218 {
9223 /* For big endian, adjust the memory offset. */
9228 else
9230 }
9238 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9239 Note that all SUBREGs of MEM are paradoxical; otherwise they
9240 would have been rewritten. */
9253 /* We used to see if get_last_value of X and Y were the same but that's
9254 not correct. In one direction, we'll cause the assignment to have
9255 the wrong destination and in the case, we'll import a register into this
9256 insn that might have already have been dead. So fail if none of the
9257 above cases are true. */
9259 }
9260 \f
9261 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9262 Return that assignment if so.
9264 We only handle the most common cases. */
9266 static rtx
9268 {
9271 rtx assign;
9273 HOST_WIDE_INT c1;
9274 HOST_WIDE_INT pos;
9276 rtx other;
9277 machine_mode mode;
9279 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9280 a clear of a one-bit field. We will have changed it to
9281 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9282 for a SUBREG. */
9288 {
9294 }
9304 {
9311 }
9313 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9314 one-bit field. */
9318 {
9324 }
9326 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9327 SRC is an AND with all bits of that field set, then we can discard
9328 the AND. */
9333 {
9340 else
9343 /* Complete overlap. We can remove the source AND. */
9347 /* Partial overlap. We can reduce the source AND. */
9349 {
9354 }
9355 }
9357 /* The other case we handle is assignments into a constant-position
9358 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9359 a mask that has all one bits except for a group of zero bits and
9360 OTHER is known to have zeros where C1 has ones, this is such an
9361 assignment. Compute the position and length from C1. Shift OTHER
9362 to the appropriate position, force it to the required mode, and
9363 make the extraction. Check for the AND in both operands. */
9365 /* One or more SUBREGs might obscure the constant-position field
9366 assignment. The first one we are likely to encounter is an outer
9367 narrowing SUBREG, which we can just strip for the purposes of
9368 identifying the constant-field assignment. */
9382 /* The second SUBREG that might get in the way is a paradoxical
9383 SUBREG around the first operand of the AND. We want to
9384 pretend the operand is as wide as the destination here. We
9385 do this by adjusting the MEM to wider mode for the sole
9386 purpose of the call to rtx_equal_for_field_assignment_p. Also
9387 note this trick only works for MEMs. */
9399 /* The second SUBREG that might get in the way is a paradoxical
9400 SUBREG around the first operand of the AND. We want to
9401 pretend the operand is as wide as the destination here. We
9402 do this by adjusting the MEM to wider mode for the sole
9403 purpose of the call to rtx_equal_for_field_assignment_p. Also
9404 note this trick only works for MEMs. */
9412 else
9425 /* The mode to use for the source is the mode of the assignment, or of
9426 what is inside a possible STRICT_LOW_PART. */
9430 /* Shift OTHER right POS places and make it the source, restricting it
9431 to the proper length and mode. */
9436 dest);
9443 /* If SRC is masked by an AND that does not make a difference in
9444 the value being stored, strip it. */
9455 }
9456 \f
9457 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9458 if so. */
9460 static rtx
9462 {
9466 rtx tem;
9468 /* Distributivity is not true for floating point as it can change the
9469 value. So we don't do it unless -funsafe-math-optimizations. */
9474 /* The outer operation can only be one of the following: */
9482 /* If either operand is a primitive we can't do anything, so get out
9483 fast. */
9493 /* See if the inner and outer operations distribute. */
9495 {
9500 /* These all distribute except over PLUS. */
9511 /* This is also a multiply, so it distributes over everything. */
9514 /* This used to handle SUBREG, but this turned out to be counter-
9515 productive, since (subreg (op ...)) usually is not handled by
9516 insn patterns, and this "optimization" therefore transformed
9517 recognizable patterns into unrecognizable ones. Therefore the
9518 SUBREG case was removed from here.
9520 It is possible that distributing SUBREG over arithmetic operations
9521 leads to an intermediate result than can then be optimized further,
9522 e.g. by moving the outer SUBREG to the other side of a SET as done
9523 in simplify_set. This seems to have been the original intent of
9524 handling SUBREGs here.
9526 However, with current GCC this does not appear to actually happen,
9527 at least on major platforms. If some case is found where removing
9528 the SUBREG case here prevents follow-on optimizations, distributing
9529 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9533 }
9535 /* Set LHS and RHS to the inner operands (A and B in the example
9536 above) and set OTHER to the common operand (C in the example).
9537 There is only one way to do this unless the inner operation is
9538 commutative. */
9550 else
9553 /* Form the new inner operation, seeing if it simplifies first. */
9556 /* There is one exception to the general way of distributing:
9557 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9559 {
9562 }
9564 /* We may be able to continuing distributing the result, so call
9565 ourselves recursively on the inner operation before forming the
9566 outer operation, which we return. */
9569 }
9571 /* See if X is of the form (* (+ A B) C), and if so convert to
9572 (+ (* A C) (* B C)) and try to simplify.
9574 Most of the time, this results in no change. However, if some of
9575 the operands are the same or inverses of each other, simplifications
9576 will result.
9578 For example, (and (ior A B) (not B)) can occur as the result of
9579 expanding a bit field assignment. When we apply the distributive
9580 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9581 which then simplifies to (and (A (not B))).
9583 Note that no checks happen on the validity of applying the inverse
9584 distributive law. This is pointless since we can do it in the
9585 few places where this routine is called.
9587 N is the index of the term that is decomposed (the arithmetic operation,
9588 i.e. (+ A B) in the first example above). !N is the index of the term that
9589 is distributed, i.e. of C in the first example above. */
9590 static rtx
9592 {
9593 machine_mode mode;
9597 /* Distributivity is not true for floating point as it can change the
9598 value. So we don't do it unless -funsafe-math-optimizations. */
9615 /* Special case (and (xor B C) (not A)), which is equivalent to
9616 (xor (ior A B) (ior A C)) */
9618 {
9621 }
9624 {
9625 /* Distribute the second term. */
9628 }
9629 else
9630 {
9631 /* Distribute the first term. */
9634 }
9644 }
9645 \f
9646 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9647 in MODE. Return an equivalent form, if different from (and VAROP
9648 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9650 static rtx
9653 {
9656 rtx orig_varop;
9664 /* Simplify VAROP knowing that we will be only looking at some of the
9665 bits in it.
9667 Note by passing in CONSTOP, we guarantee that the bits not set in
9668 CONSTOP are not significant and will never be examined. We must
9669 ensure that is the case by explicitly masking out those bits
9670 before returning. */
9673 /* If VAROP is a CLOBBER, we will fail so return it. */
9677 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9678 to VAROP and return the new constant. */
9682 /* See what bits may be nonzero in VAROP. Unlike the general case of
9683 a call to nonzero_bits, here we don't care about bits outside
9684 MODE. */
9688 /* Turn off all bits in the constant that are known to already be zero.
9689 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9690 which is tested below. */
9694 /* If we don't have any bits left, return zero. */
9698 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9699 a power of two, we can replace this with an ASHIFT. */
9704 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9705 or XOR, then try to apply the distributive law. This may eliminate
9706 operations if either branch can be simplified because of the AND.
9707 It may also make some cases more complex, but those cases probably
9708 won't match a pattern either with or without this. */
9711 return
9712 gen_lowpart
9714 apply_distributive_law
9719 constop),
9723 constop))));
9725 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9726 the AND and see if one of the operands simplifies to zero. If so, we
9727 may eliminate it. */
9731 {
9740 }
9742 /* Make a SUBREG if necessary. If we can't make it, fail. */
9747 /* If we are only masking insignificant bits, return VAROP. */
9754 /* Otherwise, return an AND. */
9756 }
9759 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9760 in MODE.
9762 Return an equivalent form, if different from X. Otherwise, return X. If
9763 X is zero, we are to always construct the equivalent form. */
9765 static rtx
9768 {
9779 }
9780 \f
9781 /* Given a REG, X, compute which bits in X can be nonzero.
9782 We don't care about bits outside of those defined in MODE.
9784 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9785 a shift, AND, or zero_extract, we can do better. */
9787 static rtx
9789 const_rtx known_x ATTRIBUTE_UNUSED,
9790 machine_mode known_mode ATTRIBUTE_UNUSED,
9793 {
9794 rtx tem;
9797 /* If X is a register whose nonzero bits value is current, use it.
9798 Otherwise, if X is a register whose value we can find, use that
9799 value. Otherwise, use the previously-computed global nonzero bits
9800 for this register. */
9814 && !REGNO_REG_SET_P
9817 {
9821 /* We don't know anything about the upper bits. */
9826 }
9831 {
9832 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9835 #endif
9837 }
9839 {
9843 /* We don't know anything about the upper bits. */
9847 }
9850 }
9852 /* Return the number of bits at the high-order end of X that are known to
9853 be equal to the sign bit. X will be used in mode MODE; if MODE is
9854 VOIDmode, X will be used in its own mode. The returned value will always
9855 be between 1 and the number of bits in MODE. */
9857 static rtx
9859 const_rtx known_x ATTRIBUTE_UNUSED,
9860 machine_mode known_mode
9861 ATTRIBUTE_UNUSED,
9864 {
9865 rtx tem;
9878 && !REGNO_REG_SET_P
9881 {
9884 }
9895 }
9896 \f
9897 /* Return the number of "extended" bits there are in X, when interpreted
9898 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9899 unsigned quantities, this is the number of high-order zero bits.
9900 For signed quantities, this is the number of copies of the sign bit
9901 minus 1. In both case, this function returns the number of "spare"
9902 bits. For example, if two quantities for which this function returns
9903 at least 1 are added, the addition is known not to overflow.
9905 This function will always return 0 unless called during combine, which
9906 implies that it must be called from a define_split. */
9908 unsigned int
9910 {
9920 }
9922 /* This function is called from `simplify_shift_const' to merge two
9923 outer operations. Specifically, we have already found that we need
9924 to perform operation *POP0 with constant *PCONST0 at the outermost
9925 position. We would now like to also perform OP1 with constant CONST1
9926 (with *POP0 being done last).
9928 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9929 the resulting operation. *PCOMP_P is set to 1 if we would need to
9930 complement the innermost operand, otherwise it is unchanged.
9932 MODE is the mode in which the operation will be done. No bits outside
9933 the width of this mode matter. It is assumed that the width of this mode
9934 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9936 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9937 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9938 result is simply *PCONST0.
9940 If the resulting operation cannot be expressed as one operation, we
9941 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9943 static int
9944 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
9945 {
9952 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9956 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9957 if OP0 is SET. */
9966 {
9968 {
9986 }
9987 }
9989 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9993 /* If the two constants aren't the same, we can't do anything. The
9994 remaining six cases can all be done. */
9998 else
10000 {
10003 /* (a & b) | b == b */
10006 /* (a ^ b) | b == a | b */
10007 {;}
10012 /* (a & b) ^ b == (~a) & b */
10015 /* (a | b) ^ b == a & ~b */
10021 /* (a | b) & b == b */
10024 /* (a ^ b) & b) == (~a) & b */
10029 }
10031 /* Check for NO-OP cases. */
10044 /* ??? Slightly redundant with the above mask, but not entirely.
10045 Moving this above means we'd have to sign-extend the mode mask
10046 for the final test. */
10051 }
10052 \f
10053 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10054 the shift in. The original shift operation CODE is performed on OP in
10055 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10056 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10057 result of the shift is subject to operation OUTER_CODE with operand
10058 OUTER_CONST. */
10060 static machine_mode
10064 {
10069 /* In general we can't perform in wider mode for right shift and rotate. */
10071 {
10073 /* We can still widen if the bits brought in from the left are identical
10074 to the sign bit of ORIG_MODE. */
10082 /* Similarly here but with zero bits. */
10087 /* We can also widen if the bits brought in will be masked off. This
10088 operation is performed in ORIG_MODE. */
10090 {
10096 }
10097 /* fall through */
10107 }
10108 }
10110 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10111 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10112 if we cannot simplify it. Otherwise, return a simplified value.
10114 The shift is normally computed in the widest mode we find in VAROP, as
10115 long as it isn't a different number of words than RESULT_MODE. Exceptions
10116 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10118 static rtx
10121 {
10127 unsigned int mode_words
10129 /* We form (outer_op (code varop count) (outer_const)). */
10135 /* Make sure and truncate the "natural" shift on the way in. We don't
10136 want to do this inside the loop as it makes it more difficult to
10137 combine shifts. */
10141 /* If we were given an invalid count, don't do anything except exactly
10142 what was requested. */
10149 /* Unless one of the branches of the `if' in this loop does a `continue',
10150 we will `break' the loop after the `if'. */
10153 {
10154 /* If we have an operand of (clobber (const_int 0)), fail. */
10158 /* Convert ROTATERT to ROTATE. */
10160 {
10165 else
10167 }
10172 /* Handle cases where the count is greater than the size of the mode
10173 minus 1. For ASHIFT, use the size minus one as the count (this can
10174 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10175 take the count modulo the size. For other shifts, the result is
10176 zero.
10178 Since these shifts are being produced by the compiler by combining
10179 multiple operations, each of which are defined, we know what the
10180 result is supposed to be. */
10183 {
10188 else
10189 {
10190 /* We can't simply return zero because there may be an
10191 outer op. */
10195 }
10196 }
10198 /* If we discovered we had to complement VAROP, leave. Making a NOT
10199 here would cause an infinite loop. */
10203 /* An arithmetic right shift of a quantity known to be -1 or 0
10204 is a no-op. */
10208 {
10211 }
10213 /* If we are doing an arithmetic right shift and discarding all but
10214 the sign bit copies, this is equivalent to doing a shift by the
10215 bitsize minus one. Convert it into that shift because it will often
10216 allow other simplifications. */
10223 /* We simplify the tests below and elsewhere by converting
10224 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10225 `make_compound_operation' will convert it to an ASHIFTRT for
10226 those machines (such as VAX) that don't have an LSHIFTRT. */
10243 {
10250 {
10253 }
10257 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10258 minus the width of a smaller mode, we can do this with a
10259 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10266 {
10275 }
10279 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10280 the same number of words as what we've seen so far. Then store
10281 the widest mode in MODE. */
10287 == mode_words
10290 {
10295 }
10299 /* Some machines use MULT instead of ASHIFT because MULT
10300 is cheaper. But it is still better on those machines to
10301 merge two shifts into one. */
10304 {
10305 varop
10311 }
10315 /* Similar, for when divides are cheaper. */
10318 {
10319 varop
10325 }
10329 /* If we are extracting just the sign bit of an arithmetic
10330 right shift, that shift is not needed. However, the sign
10331 bit of a wider mode may be different from what would be
10332 interpreted as the sign bit in a narrower mode, so, if
10333 the result is narrower, don't discard the shift. */
10338 {
10341 }
10343 /* ... fall through ... */
10348 /* Here we have two nested shifts. The result is usually the
10349 AND of a new shift with a mask. We compute the result below. */
10356 {
10360 rtx mask_rtx;
10362 /* We have one common special case. We can't do any merging if
10363 the inner code is an ASHIFTRT of a smaller mode. However, if
10364 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10365 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10366 we can convert it to
10367 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10368 This simplifies certain SIGN_EXTEND operations. */
10372 {
10373 /* C3 has the low-order C1 bits zero. */
10385 }
10387 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10388 than C1 high-order bits equal to the sign bit, we can convert
10389 this to either an ASHIFT or an ASHIFTRT depending on the
10390 two counts.
10392 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10398 {
10402 {
10405 }
10408 }
10410 /* There are some cases we can't do. If CODE is ASHIFTRT,
10411 we can only do this if FIRST_CODE is also ASHIFTRT.
10413 We can't do the case when CODE is ROTATE and FIRST_CODE is
10414 ASHIFTRT.
10416 If the mode of this shift is not the mode of the outer shift,
10417 we can't do this if either shift is a right shift or ROTATE.
10419 Finally, we can't do any of these if the mode is too wide
10420 unless the codes are the same.
10422 Handle the case where the shift codes are the same
10423 first. */
10426 {
10435 }
10446 /* To compute the mask to apply after the shift, shift the
10447 nonzero bits of the inner shift the same way the
10448 outer shift will. */
10451 result_mode);
10453 mask_rtx
10457 /* Give up if we can't compute an outer operation to use. */
10465 /* If the shifts are in the same direction, we add the
10466 counts. Otherwise, we subtract them. */
10470 else
10473 /* If COUNT is positive, the new shift is usually CODE,
10474 except for the two exceptions below, in which case it is
10475 FIRST_CODE. If the count is negative, FIRST_CODE should
10476 always be used */
10486 }
10488 /* If we have (A << B << C) for any shift, we can convert this to
10489 (A << C << B). This wins if A is a constant. Only try this if
10490 B is not a constant. */
10495 {
10502 }
10509 /* Make this fit the case below. */
10516 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10517 with C the size of VAROP - 1 and the shift is logical if
10518 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10519 we have an (le X 0) operation. If we have an arithmetic shift
10520 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10521 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10529 {
10532 const0_rtx);
10538 }
10540 /* If we have (shift (logical)), move the logical to the outside
10541 to allow it to possibly combine with another logical and the
10542 shift to combine with another shift. This also canonicalizes to
10543 what a ZERO_EXTRACT looks like. Also, some machines have
10544 (and (shift)) insns. */
10547 /* We can't do this if we have (ashiftrt (xor)) and the
10548 constant has its sign bit set in shift_mode with shift_mode
10549 wider than result_mode. */
10553 shift_mode))
10561 {
10564 }
10566 /* If we can't do that, try to simplify the shift in each arm of the
10567 logical expression, make a new logical expression, and apply
10568 the inverse distributive law. This also can't be done for
10569 (ashiftrt (xor)) where we've widened the shift and the constant
10570 changes the sign bit. */
10575 shift_mode)))
10576 {
10588 }
10592 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10593 says that the sign bit can be tested, FOO has mode MODE, C is
10594 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10595 that may be nonzero. */
10605 {
10609 }
10613 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10614 than the number of bits in the mode is equivalent to A. */
10618 {
10622 }
10624 /* NEG commutes with ASHIFT since it is multiplication. Move the
10625 NEG outside to allow shifts to combine. */
10629 {
10632 }
10636 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10637 is one less than the number of bits in the mode is
10638 equivalent to (xor A 1). */
10645 {
10649 }
10651 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10652 that might be nonzero in BAR are those being shifted out and those
10653 bits are known zero in FOO, we can replace the PLUS with FOO.
10654 Similarly in the other operand order. This code occurs when
10655 we are computing the size of a variable-size array. */
10662 {
10665 }
10673 result_mode)))
10674 {
10677 }
10679 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10689 {
10692 }
10694 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10695 signbit', and attempt to change the PLUS to an XOR and move it to
10696 the outer operation as is done above in the AND/IOR/XOR case
10697 leg for shift(logical). See details in logical handling above
10698 for reasoning in doing so. */
10709 {
10712 }
10717 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10718 with C the size of VAROP - 1 and the shift is logical if
10719 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10720 we have a (gt X 0) operation. If the shift is arithmetic with
10721 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10722 we have a (neg (gt X 0)) operation. */
10731 {
10734 const0_rtx);
10740 }
10744 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10745 if the truncate does not affect the value. */
10752 {
10755 varop_inner
10758 GEN_INT
10763 }
10768 }
10771 }
10776 /* We have now finished analyzing the shift. The result should be
10777 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10778 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10779 to the result of the shift. OUTER_CONST is the relevant constant,
10780 but we must turn off all bits turned off in the shift. */
10788 /* Make a SUBREG if necessary. If we can't make it, fail. */
10793 /* If we have an outer operation and we just made a shift, it is
10794 possible that we could have simplified the shift were it not
10795 for the outer operation. So try to do the simplification
10796 recursively. */
10800 else
10806 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10807 turn off all the bits that the shift would have turned off. */
10812 /* Do the remainder of the processing in RESULT_MODE. */
10815 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10816 operation. */
10821 {
10829 {
10830 /* This means that we have determined that the result is
10831 equivalent to a constant. This should be rare. */
10834 }
10837 else
10840 }
10843 }
10845 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10846 The result of the shift is RESULT_MODE. If we cannot simplify it,
10847 return X or, if it is NULL, synthesize the expression with
10848 simplify_gen_binary. Otherwise, return a simplified value.
10850 The shift is normally computed in the widest mode we find in VAROP, as
10851 long as it isn't a different number of words than RESULT_MODE. Exceptions
10852 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10854 static rtx
10857 {
10867 }
10869 \f
10870 /* A subroutine of recog_for_combine. See there for arguments and
10871 return value. */
10873 static int
10875 {
10877 rtx pat_without_clobbers;
10885 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10886 we use to indicate that something didn't match. If we find such a
10887 thing, force rejection. */
10901 {
10904 else
10907 }
10909 /* If it isn't, there is the possibility that we previously had an insn
10910 that clobbered some register as a side effect, but the combined
10911 insn doesn't need to do that. So try once more without the clobbers
10912 unless this represents an ASM insn. */
10916 {
10921 {
10924 pos++;
10925 }
10935 {
10938 else
10941 }
10942 }
10949 /* Recognize all noop sets, these will be killed by followup pass. */
10953 /* If we had any clobbers to add, make a new pattern than contains
10954 them. Then check to make sure that all of them are dead. */
10956 {
10966 else
10973 {
10978 {
10982 }
10983 }
10985 }
10989 {
10996 /* Allow targets to reject combined insn. */
10998 {
11001 dump_file);
11003 /* Callers expect recog_for_combine to strip
11004 clobbers from the pattern on failure. */
11009 }
11014 }
11020 }
11022 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11023 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11024 Return whether anything was so changed. */
11026 static bool
11028 {
11033 {
11042 {
11050 }
11055 {
11058 }
11059 else
11064 mask--;
11070 }
11073 }
11075 /* Like recog, but we receive the address of a pointer to a new pattern.
11076 We try to match the rtx that the pointer points to.
11077 If that fails, we may try to modify or replace the pattern,
11078 storing the replacement into the same pointer object.
11080 Modifications include deletion or addition of CLOBBERs. If the
11081 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11082 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11083 (and undo if that fails).
11085 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11086 the CLOBBERs are placed.
11088 The value is the final insn code from the pattern ultimately matched,
11089 or -1. */
11091 static int
11093 {
11105 {
11108 {
11112 }
11113 }
11116 {
11121 }
11124 }
11125 \f
11126 /* Like gen_lowpart_general but for use by combine. In combine it
11127 is not possible to create any new pseudoregs. However, it is
11128 safe to create invalid memory addresses, because combine will
11129 try to recognize them and all they will do is make the combine
11130 attempt fail.
11132 If for some reason this cannot do its job, an rtx
11133 (clobber (const_int 0)) is returned.
11134 An insn containing that will not be recognized. */
11136 static rtx
11138 {
11142 rtx result;
11147 /* We can only support MODE being wider than a word if X is a
11148 constant integer or has a mode the same size. */
11153 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11154 won't know what to do. So we will strip off the SUBREG here and
11155 process normally. */
11157 {
11160 /* For use in case we fall down into the address adjustments
11161 further below, we need to adjust the known mode and size of
11162 x; imode and isize, since we just adjusted x. */
11169 }
11177 {
11180 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11181 address. */
11186 /* If we want to refer to something bigger than the original memref,
11187 generate a paradoxical subreg instead. That will force a reload
11188 of the original memref X. */
11195 /* Adjust the address so that the address-after-the-data is
11196 unchanged. */
11201 }
11203 /* If X is a comparison operator, rewrite it in a new mode. This
11204 probably won't match, but may allow further simplifications. */
11208 /* If we couldn't simplify X any other way, just enclose it in a
11209 SUBREG. Normally, this SUBREG won't match, but some patterns may
11210 include an explicit SUBREG or we may simplify it further in combine. */
11211 else
11212 {
11214 rtx res;
11218 {
11223 }
11227 }
11229 fail:
11231 }
11232 \f
11233 /* Try to simplify a comparison between OP0 and a constant OP1,
11234 where CODE is the comparison code that will be tested, into a
11235 (CODE OP0 const0_rtx) form.
11237 The result is a possibly different comparison code to use.
11238 *POP1 may be updated. */
11240 static enum rtx_code
11243 {
11247 /* Get the constant we are comparing against and turn off all bits
11248 not on in our mode. */
11252 /* If we are comparing against a constant power of two and the value
11253 being compared can only have that single bit nonzero (e.g., it was
11254 `and'ed with that bit), we can replace this with a comparison
11255 with zero. */
11263 {
11266 }
11268 /* Similarly, if we are comparing a value known to be either -1 or
11269 0 with -1, change it to the opposite comparison against zero. */
11274 {
11277 }
11279 /* Do some canonicalizations based on the comparison code. We prefer
11280 comparisons against zero and then prefer equality comparisons.
11281 If we can reduce the size of a constant, we will do that too. */
11283 {
11285 /* < C is equivalent to <= (C - 1) */
11287 {
11290 /* ... fall through to LE case below. */
11291 }
11292 else
11296 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11298 {
11301 }
11303 /* If we are doing a <= 0 comparison on a value known to have
11304 a zero sign bit, we can replace this with == 0. */
11314 /* >= C is equivalent to > (C - 1). */
11316 {
11319 /* ... fall through to GT below. */
11320 }
11321 else
11325 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11327 {
11330 }
11332 /* If we are doing a > 0 comparison on a value known to have
11333 a zero sign bit, we can replace this with != 0. */
11343 /* < C is equivalent to <= (C - 1). */
11345 {
11348 /* ... fall through ... */
11349 }
11350 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11354 {
11358 }
11359 else
11363 /* unsigned <= 0 is equivalent to == 0 */
11366 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11370 {
11373 }
11377 /* >= C is equivalent to > (C - 1). */
11379 {
11382 /* ... fall through ... */
11383 }
11385 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11389 {
11393 }
11394 else
11398 /* unsigned > 0 is equivalent to != 0 */
11401 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11405 {
11408 }
11413 }
11417 }
11418 \f
11419 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11420 comparison code that will be tested.
11422 The result is a possibly different comparison code to use. *POP0 and
11423 *POP1 may be updated.
11425 It is possible that we might detect that a comparison is either always
11426 true or always false. However, we do not perform general constant
11427 folding in combine, so this knowledge isn't useful. Such tautologies
11428 should have been detected earlier. Hence we ignore all such cases. */
11430 static enum rtx_code
11432 {
11439 /* Try a few ways of applying the same transformation to both operands. */
11441 {
11442 #ifndef WORD_REGISTER_OPERATIONS
11443 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11444 so check specially. */
11459 - (GET_MODE_PRECISION
11461 {
11464 }
11465 #endif
11467 /* If both operands are the same constant shift, see if we can ignore the
11468 shift. We can if the shift is a rotate or if the bits shifted out of
11469 this shift are known to be zero for both inputs and if the type of
11470 comparison is compatible with the shift. */
11483 {
11496 else
11498 }
11500 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11501 SUBREGs are of the same mode, and, in both cases, the AND would
11502 be redundant if the comparison was done in the narrower mode,
11503 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11504 and the operand's possibly nonzero bits are 0xffffff01; in that case
11505 if we only care about QImode, we don't need the AND). This case
11506 occurs if the output mode of an scc insn is not SImode and
11507 STORE_FLAG_VALUE == 1 (e.g., the 386).
11509 Similarly, check for a case where the AND's are ZERO_EXTEND
11510 operations from some narrower mode even though a SUBREG is not
11511 present. */
11516 {
11533 {
11537 /* The resulting comparison is always unsigned since we masked
11538 off the original sign bit. */
11542 }
11549 {
11555 }
11559 }
11561 /* If both operands are NOT, we can strip off the outer operation
11562 and adjust the comparison code for swapped operands; similarly for
11563 NEG, except that this must be an equality comparison. */
11569 else
11571 }
11573 /* If the first operand is a constant, swap the operands and adjust the
11574 comparison code appropriately, but don't do this if the second operand
11575 is already a constant integer. */
11577 {
11580 }
11582 /* We now enter a loop during which we will try to simplify the comparison.
11583 For the most part, we only are concerned with comparisons with zero,
11584 but some things may really be comparisons with zero but not start
11585 out looking that way. */
11588 {
11595 HOST_WIDE_INT const_op;
11597 /* We only want to handle integral modes. This catches VOIDmode,
11598 CCmode, and the floating-point modes. An exception is that we
11599 can handle VOIDmode if OP0 is a COMPARE or a comparison
11600 operation. */
11607 /* Try to simplify the compare to constant, possibly changing the
11608 comparison op, and/or changing op1 to zero. */
11612 /* Compute some predicates to simplify code below. */
11619 /* If this is a sign bit comparison and we can do arithmetic in
11620 MODE, say that we will only be needing the sign bit of OP0. */
11627 /* Now try cases based on the opcode of OP0. If none of the cases
11628 does a "continue", we exit this loop immediately after the
11629 switch. */
11632 {
11634 /* If we are extracting a single bit from a variable position in
11635 a constant that has only a single bit set and are comparing it
11636 with zero, we can convert this into an equality comparison
11637 between the position and the location of the single bit. */
11638 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11639 have already reduced the shift count modulo the word size. */
11645 {
11653 /* Result is nonzero iff shift count is equal to I. */
11656 }
11658 /* ... fall through ... */
11663 {
11666 }
11670 /* If testing for equality, we can take the NOT of the constant. */
11673 {
11677 }
11679 /* If just looking at the sign bit, reverse the sense of the
11680 comparison. */
11682 {
11686 }
11690 /* If testing for equality, we can take the NEG of the constant. */
11693 {
11697 }
11699 /* The remaining cases only apply to comparisons with zero. */
11703 /* When X is ABS or is known positive,
11704 (neg X) is < 0 if and only if X != 0. */
11712 {
11716 }
11718 /* If we have NEG of something whose two high-order bits are the
11719 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11721 {
11725 }
11729 /* If we are testing equality and our count is a constant, we
11730 can perform the inverse operation on our RHS. */
11734 {
11738 }
11740 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11741 a particular bit. Convert it to an AND of a constant of that
11742 bit. This will be converted into a ZERO_EXTRACT. */
11746 {
11753 }
11755 /* Fall through. */
11758 /* ABS is ignorable inside an equality comparison with zero. */
11760 {
11763 }
11767 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11768 (compare FOO CONST) if CONST fits in FOO's mode and we
11769 are either testing inequality or have an unsigned
11770 comparison with ZERO_EXTEND or a signed comparison with
11771 SIGN_EXTEND. But don't do it if we don't have a compare
11772 insn of the given mode, since we'd have to revert it
11773 later on, and then we wouldn't know whether to sign- or
11774 zero-extend. */
11777 && ! unsigned_comparison_p
11781 {
11784 }
11788 /* Check for the case where we are comparing A - C1 with C2, that is
11790 (subreg:MODE (plus (A) (-C1))) op (C2)
11792 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11793 comparison in the wider mode. One of the following two conditions
11794 must be true in order for this to be valid:
11796 1. The mode extension results in the same bit pattern being added
11797 on both sides and the comparison is equality or unsigned. As
11798 C2 has been truncated to fit in MODE, the pattern can only be
11799 all 0s or all 1s.
11801 2. The mode extension results in the sign bit being copied on
11802 each side.
11804 The difficulty here is that we have predicates for A but not for
11805 (A - C1) so we need to check that C1 is within proper bounds so
11806 as to perturbate A as little as possible. */
11813 {
11822 /* (A - C1) zero-extends if it is positive and sign-extends
11823 if it is negative, C2 both zero- and sign-extends. */
11827 /* (A - C1) sign-extends if it is positive and 1-extends
11828 if it is negative, C2 both sign- and 1-extends. */
11835 /* (A - C1) always sign-extends, like C2. */
11839 {
11842 }
11843 }
11845 /* If the inner mode is narrower and we are extracting the low part,
11846 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11850 else
11853 /* ... fall through ... */
11863 {
11866 }
11870 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11871 this for equality comparisons due to pathological cases involving
11872 overflows. */
11876 {
11880 }
11882 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11885 {
11889 }
11893 /* We used to optimize signed comparisons against zero, but that
11894 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11895 arrive here as equality comparisons, or (GEU, LTU) are
11896 optimized away. No need to special-case them. */
11898 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11899 (eq B (minus A C)), whichever simplifies. We can only do
11900 this for equality comparisons due to pathological cases involving
11901 overflows. */
11905 {
11909 }
11914 {
11918 }
11920 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11921 of bits in X minus 1, is one iff X > 0. */
11926 {
11930 }
11934 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11935 if C is zero or B is a constant. */
11939 {
11943 }
11951 /* We can't do anything if OP0 is a condition code value, rather
11952 than an actual data value. */
11958 /* Get the two operands being compared. */
11961 else
11964 /* Check for the cases where we simply want the result of the
11965 earlier test or the opposite of that result. */
11969 {
11973 else
11977 {
11982 }
11983 }
11987 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11988 iff X <= 0. */
11992 {
11996 }
12000 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12001 will be converted to a ZERO_EXTRACT later. */
12005 {
12010 }
12012 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12013 zero and X is a comparison and C1 and C2 describe only bits set
12014 in STORE_FLAG_VALUE, we can compare with X. */
12022 {
12029 {
12032 }
12033 }
12035 /* If we are doing an equality comparison of an AND of a bit equal
12036 to the sign bit, replace this with a LT or GE comparison of
12037 the underlying value. */
12044 {
12048 }
12050 /* If this AND operation is really a ZERO_EXTEND from a narrower
12051 mode, the constant fits within that mode, and this is either an
12052 equality or unsigned comparison, try to do this comparison in
12053 the narrower mode.
12055 Note that in:
12057 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12058 -> (ne:DI (reg:SI 4) (const_int 0))
12060 unless TRULY_NOOP_TRUNCATION allows it or the register is
12061 known to hold a value of the required mode the
12062 transformation is invalid. */
12073 {
12076 }
12078 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
12079 fits in both M1 and M2 and the SUBREG is either paradoxical
12080 or represents the low part, permute the SUBREG and the AND
12081 and try again. */
12083 {
12086 /* Require an integral mode, to avoid creating something like
12087 (AND:SF ...). */
12089 /* It is unsafe to commute the AND into the SUBREG if the
12090 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12091 not defined. As originally written the upper bits
12092 have a defined value due to the AND operation.
12093 However, if we commute the AND inside the SUBREG then
12094 they no longer have defined values and the meaning of
12095 the code has been changed. */
12097 #ifdef WORD_REGISTER_OPERATIONS
12100 #endif
12110 {
12116 }
12117 }
12119 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12123 {
12128 }
12130 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12131 (eq (and (lshiftrt X) 1) 0).
12132 Also handle the case where (not X) is expressed using xor. */
12136 {
12148 {
12149 op0
12154 }
12155 }
12159 /* If we have (compare (ashift FOO N) (const_int C)) and
12160 the high order N bits of FOO (N+1 if an inequality comparison)
12161 are known to be zero, we can do this by comparing FOO with C
12162 shifted right N bits so long as the low-order N bits of C are
12163 zero. */
12175 {
12176 /* We must perform a logical shift, not an arithmetic one,
12177 as we want the top N bits of C to be zero. */
12184 }
12186 /* If we are doing a sign bit comparison, it means we are testing
12187 a particular bit. Convert it to the appropriate AND. */
12190 {
12197 }
12199 /* If this an equality comparison with zero and we are shifting
12200 the low bit to the sign bit, we can convert this to an AND of the
12201 low-order bit. */
12205 {
12208 }
12212 /* If this is an equality comparison with zero, we can do this
12213 as a logical shift, which might be much simpler. */
12216 {
12221 }
12223 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12224 do the comparison in a narrower mode. */
12234 {
12237 }
12239 /* Likewise if OP0 is a PLUS of a sign extension with a
12240 constant, which is usually represented with the PLUS
12241 between the shifts. */
12253 {
12261 new_const);
12263 }
12265 /* ... fall through ... */
12267 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12268 the low order N bits of FOO are known to be zero, we can do this
12269 by comparing FOO with C shifted left N bits so long as no
12270 overflow occurs. Even if the low order N bits of FOO aren't known
12271 to be zero, if the comparison is >= or < we can use the same
12272 optimization and for > or <= by setting all the low
12273 order N bits in the comparison constant. */
12284 {
12285 unsigned HOST_WIDE_INT low_bits
12290 {
12291 /* If the shift was logical, then we must make the condition
12292 unsigned. */
12300 const_op
12305 }
12306 }
12308 /* If we are using this shift to extract just the sign bit, we
12309 can replace this with an LT or GE comparison. */
12314 {
12318 }
12323 }
12326 }
12328 /* Now make any compound operations involved in this comparison. Then,
12329 check for an outmost SUBREG on OP0 that is not doing anything or is
12330 paradoxical. The latter transformation must only be performed when
12331 it is known that the "extra" bits will be the same in op0 and op1 or
12332 that they don't matter. There are three cases to consider:
12334 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12335 care bits and we can assume they have any convenient value. So
12336 making the transformation is safe.
12338 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12339 In this case the upper bits of op0 are undefined. We should not make
12340 the simplification in that case as we do not know the contents of
12341 those bits.
12343 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12344 UNKNOWN. In that case we know those bits are zeros or ones. We must
12345 also be sure that they are the same as the upper bits of op1.
12347 We can never remove a SUBREG for a non-equality comparison because
12348 the sign bit is in a different place in the underlying object. */
12357 {
12359 {
12360 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12361 implemented. */
12363 {
12366 }
12367 }
12373 {
12379 }
12380 }
12382 /* We now do the opposite procedure: Some machines don't have compare
12383 insns in all modes. If OP0's mode is an integer mode smaller than a
12384 word and we can't do a compare in that mode, see if there is a larger
12385 mode for which we can do the compare. There are a number of cases in
12386 which we can use the wider mode. */
12396 {
12399 /* If this is a test for negative, we can make an explicit
12400 test of the sign bit. Test this first so we can use
12401 a paradoxical subreg to extend OP0. */
12405 {
12406 unsigned HOST_WIDE_INT sign
12413 }
12415 /* If the only nonzero bits in OP0 and OP1 are those in the
12416 narrower mode and this is an equality or unsigned comparison,
12417 we can use the wider mode. Similarly for sign-extended
12418 values, in which case it is true for all comparisons. */
12435 {
12436 /* If OP0 is an AND and we don't have an AND in MODE either,
12437 make a new AND in the proper mode. */
12445 else
12446 {
12448 {
12451 }
12452 else
12453 {
12456 }
12458 }
12459 }
12460 }
12462 /* We may have changed the comparison operands. Re-canonicalize. */
12464 {
12467 }
12469 /* If this machine only supports a subset of valid comparisons, see if we
12470 can convert an unsupported one into a supported one. */
12477 }
12478 \f
12479 /* Utility function for record_value_for_reg. Count number of
12480 rtxs in X. */
12481 static int
12483 {
12490 {
12510 }
12521 }
12522 \f
12523 /* Utility function for following routine. Called when X is part of a value
12524 being stored into last_set_value. Sets last_set_table_tick
12525 for each register mentioned. Similar to mention_regs in cse.c */
12527 static void
12529 {
12535 {
12541 {
12544 }
12547 }
12551 {
12552 /* Check for identical subexpressions. If x contains
12553 identical subexpression we only have to traverse one of
12554 them. */
12556 {
12557 /* Note that at this point x1 has already been
12558 processed. */
12562 /* If x0 and x1 are identical then there is no need to
12563 process x0. */
12567 /* If x0 is identical to a subexpression of x1 then while
12568 processing x1, x0 has already been processed. Thus we
12569 are done with x. */
12574 /* If x1 is identical to a subexpression of x0 then we
12575 still have to process the rest of x0. */
12578 {
12581 }
12582 }
12585 }
12589 }
12591 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12592 are saying that the register is clobbered and we no longer know its
12593 value. If INSN is zero, don't update reg_stat[].last_set; this is
12594 only permitted with VALUE also zero and is used to invalidate the
12595 register. */
12597 static void
12599 {
12605 /* If VALUE contains REG and we have a previous value for REG, substitute
12606 the previous value. */
12608 {
12609 rtx tem;
12611 /* Set things up so get_last_value is allowed to see anything set up to
12612 our insn. */
12616 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12617 it isn't going to be useful and will take a lot of time to process,
12618 so just use the CLOBBER. */
12621 {
12627 {
12628 /* If there are two or more occurrences of REG in VALUE,
12629 prevent the value from growing too much. */
12632 }
12635 }
12636 }
12638 /* For each register modified, show we don't know its value, that
12639 we don't know about its bitwise content, that its value has been
12640 updated, and that we don't know the location of the death of the
12641 register. */
12643 {
12655 }
12657 /* Mark registers that are being referenced in this value. */
12661 /* Now update the status of each register being set.
12662 If someone is using this register in this block, set this register
12663 to invalid since we will get confused between the two lives in this
12664 basic block. This makes using this register always invalid. In cse, we
12665 scan the table to invalidate all entries using this register, but this
12666 is too much work for us. */
12669 {
12675 else
12677 }
12679 /* The value being assigned might refer to X (like in "x++;"). In that
12680 case, we must replace it with (clobber (const_int 0)) to prevent
12681 infinite loops. */
12684 {
12688 }
12690 /* For the main register being modified, update the value, the mode, the
12691 nonzero bits, and the number of sign bit copies. */
12696 {
12704 rsp->last_set_sign_bit_copies
12706 }
12707 }
12709 /* Called via note_stores from record_dead_and_set_regs to handle one
12710 SET or CLOBBER in an insn. DATA is the instruction in which the
12711 set is occurring. */
12713 static void
12715 {
12722 {
12726 }
12729 {
12730 /* If we are setting the whole register, we know its value. Otherwise
12731 show that we don't know the value. We can handle SUBREG in
12732 some cases. */
12743 else
12745 }
12747 /* Ignore pushes, they clobber nothing. */
12750 }
12752 /* Update the records of when each REG was most recently set or killed
12753 for the things done by INSN. This is the last thing done in processing
12754 INSN in the combiner loop.
12756 We update reg_stat[], in particular fields last_set, last_set_value,
12757 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12758 last_death, and also the similar information mem_last_set (which insn
12759 most recently modified memory) and last_call_luid (which insn was the
12760 most recent subroutine call). */
12762 static void
12764 {
12765 rtx link;
12769 {
12772 {
12777 {
12782 }
12783 }
12786 }
12789 {
12790 hard_reg_set_iterator hrsi;
12792 {
12804 }
12808 /* We can't combine into a call pattern. Remember, though, that
12809 the return value register is set at this LUID. We could
12810 still replace a register with the return value from the
12811 wrong subroutine call! */
12813 }
12814 else
12816 }
12818 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12819 register present in the SUBREG, so for each such SUBREG go back and
12820 adjust nonzero and sign bit information of the registers that are
12821 known to have some zero/sign bits set.
12823 This is needed because when combine blows the SUBREGs away, the
12824 information on zero/sign bits is lost and further combines can be
12825 missed because of that. */
12827 static void
12829 {
12831 rtx set;
12839 {
12848 {
12851 }
12855 {
12858 }
12861 {
12864 }
12865 else
12867 }
12868 }
12870 /* Check if X, a register, is known to contain a value already
12871 truncated to MODE. In this case we can use a subreg to refer to
12872 the truncated value even though in the generic case we would need
12873 an explicit truncation. */
12875 static bool
12877 {
12889 }
12891 /* If X is a hard reg or a subreg record the mode that the register is
12892 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12893 to turn a truncate into a subreg using this information. Return true
12894 if traversing X is complete. */
12896 static bool
12898 {
12899 machine_mode truncated_mode;
12903 {
12914 }
12915 /* ??? For hard-regs we now record everything. We might be able to
12916 optimize this using last_set_mode. */
12919 else
12927 {
12930 }
12933 }
12935 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12936 the modes they are used in. This can help truning TRUNCATEs into
12937 SUBREGs. */
12939 static void
12941 {
12946 }
12948 /* Scan X for promoted SUBREGs. For each one found,
12949 note what it implies to the registers used in it. */
12951 static void
12953 {
12958 else
12959 {
12965 {
12975 }
12976 }
12977 }
12978 \f
12979 /* Verify that all the registers and memory references mentioned in *LOC are
12980 still valid. *LOC was part of a value set in INSN when label_tick was
12981 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12982 the invalid references with (clobber (const_int 0)) and return 1. This
12983 replacement is useful because we often can get useful information about
12984 the form of a value (e.g., if it was produced by a shift that always
12985 produces -1 or 0) even though we don't know exactly what registers it
12986 was produced from. */
12988 static int
12990 {
12997 {
13003 {
13006 /* If this is a pseudo-register that was only set once and not
13007 live at the beginning of the function, it is always valid. */
13011 && (!REGNO_REG_SET_P
13013 regno)))
13015 {
13019 }
13020 }
13023 }
13024 /* If this is a memory reference, make sure that there were no stores after
13025 it that might have clobbered the value. We don't have alias info, so we
13026 assume any store invalidates it. Moreover, we only have local UIDs, so
13027 we also assume that there were stores in the intervening basic blocks. */
13030 {
13034 }
13037 {
13039 {
13040 /* Check for identical subexpressions. If x contains
13041 identical subexpression we only have to traverse one of
13042 them. */
13044 {
13045 /* Note that at this point x0 has already been checked
13046 and found valid. */
13050 /* If x0 and x1 are identical then x is also valid. */
13054 /* If x1 is identical to a subexpression of x0 then
13055 while checking x0, x1 has already been checked. Thus
13056 it is valid and so as x. */
13061 /* If x0 is identical to a subexpression of x1 then x is
13062 valid iff the rest of x1 is valid. */
13065 return
13069 }
13074 }
13080 }
13082 /* If we haven't found a reason for it to be invalid, it is valid. */
13084 }
13086 /* Get the last value assigned to X, if known. Some registers
13087 in the value may be replaced with (clobber (const_int 0)) if their value
13088 is known longer known reliably. */
13090 static rtx
13092 {
13094 rtx value;
13097 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13098 then convert it to the desired mode. If this is a paradoxical SUBREG,
13099 we cannot predict what values the "extra" bits might have. */
13113 /* If we don't have a value, or if it isn't for this basic block and
13114 it's either a hard register, set more than once, or it's a live
13115 at the beginning of the function, return 0.
13117 Because if it's not live at the beginning of the function then the reg
13118 is always set before being used (is never used without being set).
13119 And, if it's set only once, and it's always set before use, then all
13120 uses must have the same last value, even if it's not from this basic
13121 block. */
13128 || REGNO_REG_SET_P
13132 /* If the value was set in a later insn than the ones we are processing,
13133 we can't use it even if the register was only set once. */
13138 /* If the value has all its registers valid, return it. */
13142 /* Otherwise, make a copy and replace any invalid register with
13143 (clobber (const_int 0)). If that fails for some reason, return 0. */
13150 }
13151 \f
13152 /* Return nonzero if expression X refers to a REG or to memory
13153 that is set in an instruction more recent than FROM_LUID. */
13155 static int
13157 {
13163 {
13167 #ifdef PUSH_ROUNDING
13168 /* Don't allow uses of the stack pointer to be moved,
13169 because we don't know whether the move crosses a push insn. */
13172 #endif
13174 {
13180 }
13182 }
13190 {
13192 {
13197 }
13201 }
13203 }
13204 \f
13205 /* Define three variables used for communication between the following
13206 routines. */
13211 /* Function called via note_stores from reg_dead_at_p.
13213 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13214 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13216 static void
13218 {
13228 }
13230 /* Return nonzero if REG is known to be dead at INSN.
13232 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13233 referencing REG, it is dead. If we hit a SET referencing REG, it is
13234 live. Otherwise, see if it is live or dead at the start of the basic
13235 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13236 must be assumed to be always live. */
13238 static int
13240 {
13241 basic_block block;
13244 /* Set variables for reg_dead_at_p_1. */
13250 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13251 we allow the machine description to decide whether use-and-clobber
13252 patterns are OK. */
13254 {
13258 }
13260 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13261 beginning of basic block. */
13264 {
13266 {
13276 }
13282 }
13284 /* Look at live-in sets for the basic block that we were in. */
13290 }
13291 \f
13292 /* Note hard registers in X that are used. */
13294 static void
13296 {
13302 {
13306 CASE_CONST_ANY:
13311 /* CC0 must die in the insn after it is set, so we don't need to take
13312 special note of it here. */
13317 /* If we are clobbering a MEM, mark any hard registers inside the
13318 address as used. */
13325 /* A hard reg in a wide mode may really be multiple registers.
13326 If so, mark all of them just like the first. */
13328 {
13329 /* None of this applies to the stack, frame or arg pointers. */
13331 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
13333 #endif
13340 }
13344 {
13345 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13346 the address. */
13358 }
13363 }
13365 /* Recursively scan the operands of this expression. */
13367 {
13371 {
13375 {
13380 }
13381 }
13382 }
13383 }
13384 \f
13385 /* Remove register number REGNO from the dead registers list of INSN.
13387 Return the note used to record the death, if there was one. */
13389 rtx
13391 {
13398 }
13400 /* For each register (hardware or pseudo) used within expression X, if its
13401 death is in an instruction with luid between FROM_LUID (inclusive) and
13402 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13403 list headed by PNOTES.
13405 That said, don't move registers killed by maybe_kill_insn.
13407 This is done when X is being merged by combination into TO_INSN. These
13408 notes will then be distributed as needed. */
13410 static void
13413 {
13419 {
13423 /* Don't move the register if it gets killed in between from and to. */
13432 {
13435 /* It is possible for the call above to return 0. This can occur
13436 when last_death points to I2 or I1 that we combined with.
13437 In that case make a new note.
13439 We must also check for the case where X is a hard register
13440 and NOTE is a death note for a range of hard registers
13441 including X. In that case, we must put REG_DEAD notes for
13442 the remaining registers in place of NOTE. */
13447 {
13456 }
13458 /* If we didn't find any note, or if we found a REG_DEAD note that
13459 covers only part of the given reg, and we have a multi-reg hard
13460 register, then to be safe we must check for REG_DEAD notes
13461 for each register other than the first. They could have
13462 their own REG_DEAD notes lying around. */
13469 {
13476 else
13482 }
13485 {
13488 }
13489 else
13491 }
13494 }
13497 {
13502 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13503 that accesses one word of a multi-word item, some
13504 piece of everything register in the expression is used by
13505 this insn, so remove any old death. */
13506 /* ??? So why do we test for equality of the sizes? */
13515 {
13518 }
13520 /* If this is some other SUBREG, we know it replaces the entire
13521 value, so use that as the destination. */
13525 /* If this is a MEM, adjust deaths of anything used in the address.
13526 For a REG (the only other possibility), the entire value is
13527 being replaced so the old value is not used in this insn. */
13533 }
13542 {
13544 {
13549 }
13552 }
13553 }
13554 \f
13555 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13556 pattern of an insn. X must be a REG. */
13558 static int
13560 {
13564 {
13566 rtx target;
13573 else
13590 }
13598 }
13599 \f
13600 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13601 as appropriate. I3 and I2 are the insns resulting from the combination
13602 insns including FROM (I2 may be zero).
13604 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13605 not need REG_DEAD notes because they are being substituted for. This
13606 saves searching in the most common cases.
13608 Each note in the list is either ignored or placed on some insns, depending
13609 on the type of note. */
13611 static void
13614 {
13616 rtx tem_note;
13620 {
13625 {
13628 /* Doesn't matter much where we put this, as long as it's somewhere.
13629 It is preferable to keep these notes on branches, which is most
13630 likely to be i3. */
13637 else
13638 {
13641 }
13645 /* These notes must remain with the call or trapping instruction. */
13650 else
13651 {
13657 /* ??? Otherwise assume we've combined things such that we
13658 can now prove that the instructions can't trap. Drop the
13659 note in this case. */
13660 }
13664 /* ??? How to distribute between i3-i1. Assume i3 contains the
13665 entire adjustment. Assert i3 contains at least some adjust. */
13667 {
13669 /* fixup_args_size_notes looks at REG_NORETURN note,
13670 so ensure the note is placed there first. */
13672 {
13676 {
13682 }
13683 }
13685 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13686 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13689 && !ACCUMULATE_OUTGOING_ARGS
13691 }
13698 /* These notes must remain with the call. It should not be
13699 possible for both I2 and I3 to be a call. */
13702 else
13703 {
13706 }
13710 /* Any clobbers for i3 may still exist, and so we must process
13711 REG_UNUSED notes from that insn.
13713 Any clobbers from i2 or i1 can only exist if they were added by
13714 recog_for_combine. In that case, recog_for_combine created the
13715 necessary REG_UNUSED notes. Trying to keep any original
13716 REG_UNUSED notes from these insns can cause incorrect output
13717 if it is for the same register as the original i3 dest.
13718 In that case, we will notice that the register is set in i3,
13719 and then add a REG_UNUSED note for the destination of i3, which
13720 is wrong. However, it is possible to have REG_UNUSED notes from
13721 i2 or i1 for register which were both used and clobbered, so
13722 we keep notes from i2 or i1 if they will turn into REG_DEAD
13723 notes. */
13725 /* If this register is set or clobbered in I3, put the note there
13726 unless there is one already. */
13728 {
13736 }
13737 /* Otherwise, if this register is used by I3, then this register
13738 now dies here, so we must put a REG_DEAD note here unless there
13739 is one already. */
13745 {
13748 }
13754 /* These notes say something about results of an insn. We can
13755 only support them if they used to be on I3 in which case they
13756 remain on I3. Otherwise they are ignored.
13758 If the note refers to an expression that is not a constant, we
13759 must also ignore the note since we cannot tell whether the
13760 equivalence is still true. It might be possible to do
13761 slightly better than this (we only have a problem if I2DEST
13762 or I1DEST is present in the expression), but it doesn't
13763 seem worth the trouble. */
13771 /* These notes say something about how a register is used. They must
13772 be present on any use of the register in I2 or I3. */
13777 {
13780 else
13782 }
13787 /* This can show up in several ways -- either directly in the
13788 pattern, or hidden off in the constant pool with (or without?)
13789 a REG_EQUAL note. */
13790 /* ??? Ignore the without-reg_equal-note problem for now. */
13802 {
13805 else
13807 }
13809 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13810 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13811 there. */
13816 {
13823 }
13829 {
13837 }
13841 /* This note says something about the value of a register prior
13842 to the execution of an insn. It is too much trouble to see
13843 if the note is still correct in all situations. It is better
13844 to simply delete it. */
13848 /* If we replaced the right hand side of FROM_INSN with a
13849 REG_EQUAL note, the original use of the dying register
13850 will not have been combined into I3 and I2. In such cases,
13851 FROM_INSN is guaranteed to be the first of the combined
13852 instructions, so we simply need to search back before
13853 FROM_INSN for the previous use or set of this register,
13854 then alter the notes there appropriately.
13856 If the register is used as an input in I3, it dies there.
13857 Similarly for I2, if it is nonzero and adjacent to I3.
13859 If the register is not used as an input in either I3 or I2
13860 and it is not one of the registers we were supposed to eliminate,
13861 there are two possibilities. We might have a non-adjacent I2
13862 or we might have somehow eliminated an additional register
13863 from a computation. For example, we might have had A & B where
13864 we discover that B will always be zero. In this case we will
13865 eliminate the reference to A.
13867 In both cases, we must search to see if we can find a previous
13868 use of A and put the death note there. */
13874 else
13875 {
13886 && !(i2mod
13888 i2mod_old_rhs)))
13893 /* If the new I2 sets the same register that is marked dead
13894 in the note, the note now should not be put on I2, as the
13895 note refers to a previous incarnation of the reg. */
13898 }
13901 {
13905 {
13907 {
13911 }
13913 /* If the register is being set at TEM_INSN, see if that is all
13914 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13915 into a REG_UNUSED note instead. Don't delete sets to
13916 global register vars. */
13920 {
13931 ;
13933 /* Verify that it was the set, and not a clobber that
13934 modified the register.
13936 CC0 targets must be careful to maintain setter/user
13937 pairs. If we cannot delete the setter due to side
13938 effects, mark the user with an UNUSED note instead
13939 of deleting it. */
13943 #if HAVE_cc0
13947 #endif
13948 )
13949 {
13950 /* Move the notes and links of TEM_INSN elsewhere.
13951 This might delete other dead insns recursively.
13952 First set the pattern to something that won't use
13953 any register. */
13967 /* Delete the setter too. */
13969 {
13982 }
13983 }
13984 else
13985 {
13988 /* If there isn't already a REG_UNUSED note, put one
13989 here. Do not place a REG_DEAD note, even if
13990 the register is also used here; that would not
13991 match the algorithm used in lifetime analysis
13992 and can cause the consistency check in the
13993 scheduler to fail. */
13998 }
13999 }
14003 {
14006 /* If we are doing a 3->2 combination, and we have a
14007 register which formerly died in i3 and was not used
14008 by i2, which now no longer dies in i3 and is used in
14009 i2 but does not die in i2, and place is between i2
14010 and i3, then we may need to move a link from place to
14011 i2. */
14013 && from_insn
14016 {
14020 }
14022 }
14026 }
14028 }
14030 /* If the register is set or already dead at PLACE, we needn't do
14031 anything with this note if it is still a REG_DEAD note.
14032 We check here if it is set at all, not if is it totally replaced,
14033 which is what `dead_or_set_p' checks, so also check for it being
14034 set partially. */
14037 {
14043 {
14044 /* Unless the register previously died in PLACE, clear
14045 last_death. [I no longer understand why this is
14046 being done.] */
14050 }
14051 else
14054 /* If this is a death note for a hard reg that is occupying
14055 multiple registers, ensure that we are still using all
14056 parts of the object. If we find a piece of the object
14057 that is unused, we must arrange for an appropriate REG_DEAD
14058 note to be added for it. However, we can't just emit a USE
14059 and tag the note to it, since the register might actually
14060 be dead; so we recourse, and the recursive call then finds
14061 the previous insn that used this register. */
14064 {
14073 {
14076 }
14079 {
14080 /* Put only REG_DEAD notes for pieces that are
14081 not already dead or set. */
14085 {
14092 {
14094 NULL_RTX);
14098 NULL_RTX);
14099 }
14104 {
14106 {
14110 }
14114 {
14117 }
14118 }
14119 }
14122 }
14123 }
14124 }
14128 /* Any other notes should not be present at this point in the
14129 compilation. */
14131 }
14134 {
14137 }
14141 }
14142 }
14143 \f
14144 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14145 I3, I2, and I1 to new locations. This is also called to add a link
14146 pointing at I3 when I3's destination is changed. */
14148 static void
14150 {
14154 {
14161 /* If the insn that this link points to is a NOTE, ignore it. */
14170 {
14173 {
14189 }
14192 }
14193 else
14203 /* A LOG_LINK is defined as being placed on the first insn that uses
14204 a register and points to the insn that sets the register. Start
14205 searching at the next insn after the target of the link and stop
14206 when we reach a set of the register or the end of the basic block.
14208 Note that this correctly handles the link that used to point from
14209 I3 to I2. Also note that not much searching is typically done here
14210 since most links don't point very far away. */
14219 {
14223 }
14226 {
14229 }
14233 /* If we found a place to put the link, place it there unless there
14234 is already a link to the same insn as LINK at that point. */
14237 {
14245 {
14249 /* Set added_links_insn to the earliest insn we added a
14250 link to. */
14254 }
14255 }
14256 }
14257 }
14258 \f
14259 /* Check for any register or memory mentioned in EQUIV that is not
14260 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14261 of EXPR where some registers may have been replaced by constants. */
14263 static bool
14265 {
14268 {
14273 }
14275 }
14276 \f
14277 DEBUG_FUNCTION void
14279 {
14280 fprintf
14282 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14284 }
14286 void
14288 {
14289 fprintf
14291 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14293 }
14294 \f
14295 /* Try combining insns through substitution. */
14296 static unsigned int
14298 {
14308 rebuild_jump_labels_after_combine
14311 /* Combining insns may have turned an indirect jump into a
14312 direct jump. Rebuild the JUMP_LABEL fields of jumping
14313 instructions. */
14315 {
14320 }
14324 }
14329 {
14339 };
14342 {
14346 {}
14348 /* opt_pass methods: */
14351 {
14353 }
14359 rtl_opt_pass *
14361 {
14363 }