| blob | 484a34fe443837fba813bb7ca432a7a45f9ae0d8 |
1 ;;- Machine description for Renesas / SuperH SH.
2 ;; Copyright (C) 1993-2023 Free Software Foundation, Inc.
3 ;; Contributed by Steve Chamberlain (sac@cygnus.com).
4 ;; Improved by Jim Wilson (wilson@cygnus.com).
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; any later version.
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
23 ;; ??? Should prepend a * to all pattern names which are not used.
24 ;; This will make the compiler smaller, and rebuilds after changes faster.
26 ;; ??? Should be enhanced to include support for many more GNU superoptimizer
27 ;; sequences. Especially the sequences for arithmetic right shifts.
29 ;; ??? Should check all DImode patterns for consistency and usefulness.
31 ;; ??? The MAC.W and MAC.L instructions are not supported. There is no
32 ;; way to generate them.
34 ;; BSR is not generated by the compiler proper, but when relaxing, it
35 ;; generates .uses pseudo-ops that allow linker relaxation to create
36 ;; BSR. This is actually implemented in bfd/{coff,elf32}-sh.c
38 ;; Special constraints for SH machine description:
39 ;;
40 ;; t -- T
41 ;; x -- mac
42 ;; l -- pr
43 ;; z -- r0
44 ;;
45 ;; Special formats used for outputting SH instructions:
46 ;;
47 ;; %. -- print a .s if insn needs delay slot
48 ;; %@ -- print rte/rts if is/isn't an interrupt function
49 ;; %# -- output a nop if there is nothing to put in the delay slot
50 ;; %O -- print a constant without the #
51 ;; %R -- print the lsw reg of a double
52 ;; %S -- print the msw reg of a double
53 ;; %T -- print next word of a double REG or MEM
54 ;;
55 ;; Special predicates:
56 ;;
57 ;; arith_operand -- operand is valid source for arithmetic op
58 ;; arith_reg_operand -- operand is valid register for arithmetic op
59 ;; general_movdst_operand -- operand is valid move destination
60 ;; general_movsrc_operand -- operand is valid move source
61 ;; logical_operand -- operand is valid source for logical op
63 ;; -------------------------------------------------------------------------
64 ;; Constants
65 ;; -------------------------------------------------------------------------
67 (define_constants [
68 (AP_REG 145)
69 (PR_REG 146)
70 (T_REG 147)
71 (GBR_REG 144)
72 (MACH_REG 148)
73 (MACL_REG 149)
74 (FPUL_REG 150)
75 (RAP_REG 152)
77 (FPSCR_REG 151)
79 ;; Virtual FPSCR - bits that are used by FP ops.
80 (FPSCR_MODES_REG 154)
82 ;; Virtual FPSCR - bits that are updated by FP ops.
83 (FPSCR_STAT_REG 155)
85 (PIC_REG 12)
86 (FP_REG 14)
87 (SP_REG 15)
89 (R0_REG 0)
90 (R1_REG 1)
91 (R2_REG 2)
92 (R3_REG 3)
93 (R4_REG 4)
94 (R5_REG 5)
95 (R6_REG 6)
96 (R7_REG 7)
97 (R8_REG 8)
98 (R9_REG 9)
99 (R10_REG 10)
100 (R20_REG 20)
101 (R21_REG 21)
102 (R22_REG 22)
103 (R23_REG 23)
105 (DR0_REG 64)
106 (DR2_REG 66)
107 (DR4_REG 68)
109 (XD0_REG 136)
111 (FPSCR_PR 524288) ;; 1 << 19
112 (FPSCR_SZ 1048576) ;; 1 << 20
113 (FPSCR_FR 2097152) ;; 1 << 21
114 ])
116 (define_c_enum "unspec" [
117 ;; These are used with unspec.
118 UNSPEC_MOVA
119 UNSPEC_CASESI
120 UNSPEC_BBR
121 UNSPEC_SFUNC
122 UNSPEC_PIC
123 UNSPEC_GOT
124 UNSPEC_GOTOFF
125 UNSPEC_PLT
126 UNSPEC_CALLER
127 UNSPEC_GOTPLT
128 UNSPEC_PCREL
129 UNSPEC_ICACHE
130 UNSPEC_FCOSA
131 UNSPEC_FSRRA
132 UNSPEC_FSINA
133 UNSPEC_ALLOCO
134 UNSPEC_TLSGD
135 UNSPEC_TLSLDM
136 UNSPEC_TLSIE
137 UNSPEC_DTPOFF
138 UNSPEC_GOTTPOFF
139 UNSPEC_TPOFF
140 UNSPEC_RA
141 UNSPEC_THUNK
142 UNSPEC_CHKADD
143 UNSPEC_SP_SET
144 UNSPEC_SP_TEST
145 UNSPEC_MOVUA
146 ;; (unspec [TARGET ANCHOR] UNSPEC_SYMOFF) == TARGET - ANCHOR.
147 UNSPEC_SYMOFF
148 ;; (unspec [OFFSET ANCHOR] UNSPEC_PCREL_SYMOFF) == OFFSET - (ANCHOR - .).
149 UNSPEC_PCREL_SYMOFF
150 ;; For FDPIC
151 UNSPEC_GOTFUNCDESC
152 UNSPEC_GOTOFFFUNCDESC
153 ;; Misc builtins
154 UNSPEC_BUILTIN_STRLEN
155 ])
157 (define_c_enum "unspecv" [
158 ;; These are used with unspec_volatile.
159 UNSPECV_BLOCKAGE
160 UNSPECV_ALIGN
161 UNSPECV_CONST2
162 UNSPECV_CONST4
163 UNSPECV_CONST8
164 UNSPECV_WINDOW_END
165 UNSPECV_CONST_END
166 UNSPECV_EH_RETURN
167 UNSPECV_GBR
168 UNSPECV_SP_SWITCH_B
169 UNSPECV_SP_SWITCH_E
171 UNSPECV_FPSCR_MODES
172 UNSPECV_FPSCR_STAT
173 ])
175 ;; -------------------------------------------------------------------------
176 ;; Attributes
177 ;; -------------------------------------------------------------------------
179 ;; Target CPU.
181 (define_attr "cpu"
182 "sh1,sh2,sh2e,sh2a,sh3,sh3e,sh4,sh4a"
183 (const (symbol_ref "sh_cpu_attr")))
185 (define_attr "endian" "big,little"
186 (const (if_then_else (symbol_ref "TARGET_LITTLE_ENDIAN")
187 (const_string "little") (const_string "big"))))
189 ;; Indicate if the default fpu mode is single precision.
190 (define_attr "fpu_single" "yes,no"
191 (const (if_then_else (symbol_ref "TARGET_FPU_SINGLE")
192 (const_string "yes") (const_string "no"))))
194 (define_attr "fmovd" "yes,no"
195 (const (if_then_else (symbol_ref "TARGET_FMOVD")
196 (const_string "yes") (const_string "no"))))
197 ;; pipeline model
198 (define_attr "pipe_model" "sh1,sh4"
199 (const
200 (cond [(symbol_ref "TARGET_SUPERSCALAR") (const_string "sh4")]
201 (const_string "sh1"))))
203 ;; cbranch conditional branch instructions
204 ;; jump unconditional jumps
205 ;; arith ordinary arithmetic
206 ;; arith3 a compound insn that behaves similarly to a sequence of
207 ;; three insns of type arith
208 ;; arith3b like above, but might end with a redirected branch
209 ;; load from memory
210 ;; load_si Likewise, SImode variant for general register.
211 ;; fload Likewise, but load to fp register.
212 ;; store to memory
213 ;; fstore floating point register to memory
214 ;; move general purpose register to register
215 ;; movi8 8-bit immediate to general purpose register
216 ;; mt_group other sh4 mt instructions
217 ;; fmove register to register, floating point
218 ;; smpy word precision integer multiply
219 ;; dmpy longword or doublelongword precision integer multiply
220 ;; return rts
221 ;; pload load of pr reg, which can't be put into delay slot of rts
222 ;; prset copy register to pr reg, ditto
223 ;; pstore store of pr reg, which can't be put into delay slot of jsr
224 ;; prget copy pr to register, ditto
225 ;; pcload pc relative load of constant value
226 ;; pcfload Likewise, but load to fp register.
227 ;; pcload_si Likewise, SImode variant for general register.
228 ;; rte return from exception
229 ;; sfunc special function call with known used registers
230 ;; call function call
231 ;; fp floating point
232 ;; fpscr_toggle toggle a bit in the fpscr
233 ;; fdiv floating point divide (or square root)
234 ;; gp_fpul move from general purpose register to fpul
235 ;; fpul_gp move from fpul to general purpose register
236 ;; mac_gp move from mac[lh] to general purpose register
237 ;; gp_mac move from general purpose register to mac[lh]
238 ;; mac_mem move from mac[lh] to memory
239 ;; mem_mac move from memory to mac[lh]
240 ;; dfp_arith,dfp_mul, fp_cmp,dfp_cmp,dfp_conv
241 ;; ftrc_s fix_truncsfsi2_i4
242 ;; dfdiv double precision floating point divide (or square root)
243 ;; cwb ic_invalidate_line_i
244 ;; movua SH4a unaligned load
245 ;; fsrra square root reciprocal approximate
246 ;; fsca sine and cosine approximate
247 ;; tls_load load TLS related address
248 ;; nil no-op move, will be deleted.
250 (define_attr "type"
251 "mt_group,cbranch,jump,jump_ind,arith,arith3,arith3b,dyn_shift,load,load_si,
252 fload,store,fstore,move,movi8,fmove,smpy,dmpy,return,pload,prset,pstore,
253 prget,pcload,pcload_si,pcfload,rte,sfunc,call,fp,fpscr_toggle,fdiv,ftrc_s,
254 dfp_arith,dfp_mul,fp_cmp,dfp_cmp,dfp_conv,dfdiv,gp_fpul,fpul_gp,mac_gp,
255 gp_mac,mac_mem,mem_mac,mem_fpscr,gp_fpscr,cwb,movua,fsrra,fsca,tls_load,
256 nil,other"
257 (const_string "other"))
259 ;; We define a new attribute namely "insn_class".We use
260 ;; this for the DFA based pipeline description.
261 ;;
262 ;; mt_group SH4 "mt" group instructions.
263 ;;
264 ;; ex_group SH4 "ex" group instructions.
265 ;;
266 ;; ls_group SH4 "ls" group instructions.
267 ;;
268 (define_attr "insn_class"
269 "mt_group,ex_group,ls_group,br_group,fe_group,co_group,none"
270 (cond [(eq_attr "type" "move,mt_group") (const_string "mt_group")
271 (eq_attr "type" "movi8,arith,dyn_shift") (const_string "ex_group")
272 (eq_attr "type" "fmove,load,pcload,load_si,pcload_si,fload,pcfload,
273 store,fstore,gp_fpul,fpul_gp") (const_string "ls_group")
274 (eq_attr "type" "cbranch,jump") (const_string "br_group")
275 (eq_attr "type" "fp,fp_cmp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
276 (const_string "fe_group")
277 (eq_attr "type" "jump_ind,smpy,dmpy,mac_gp,return,pload,prset,pstore,
278 prget,rte,sfunc,call,dfp_cmp,mem_fpscr,gp_fpscr,cwb,
279 gp_mac,mac_mem,mem_mac") (const_string "co_group")]
280 (const_string "none")))
282 ;; nil are zero instructions, and arith3 / arith3b are multiple instructions,
283 ;; so these do not belong in an insn group, although they are modeled
284 ;; with their own define_insn_reservations.
286 ;; Indicate what precision must be selected in fpscr for this insn, if any.
287 (define_attr "fp_mode" "single,double,none" (const_string "none"))
289 ;; Indicate if the fpu mode is set by this instruction
290 ;; "unknown" must have the value as "none" in fp_mode, and means
291 ;; that the instruction/abi has left the processor in an unknown
292 ;; state.
293 ;; "none" means that nothing has changed and no mode is set.
294 ;; This attribute is only used for the Renesas ABI.
295 (define_attr "fp_set" "single,double,unknown,none" (const_string "none"))
297 ; If a conditional branch destination is within -252..258 bytes away
298 ; from the instruction it can be 2 bytes long. Something in the
299 ; range -4090..4100 bytes can be 6 bytes long. All other conditional
300 ; branches are initially assumed to be 16 bytes long.
301 ; In machine_dependent_reorg, we split all branches that are longer than
302 ; 2 bytes.
304 ;; The maximum range used for SImode constant pool entries is 1018. A final
305 ;; instruction can add 8 bytes while only being 4 bytes in size, thus we
306 ;; can have a total of 1022 bytes in the pool. Add 4 bytes for a branch
307 ;; instruction around the pool table, 2 bytes of alignment before the table,
308 ;; and 30 bytes of alignment after the table. That gives a maximum total
309 ;; pool size of 1058 bytes.
310 ;; Worst case code/pool content size ratio is 1:2 (using asms).
311 ;; Thus, in the worst case, there is one instruction in front of a maximum
312 ;; sized pool, and then there are 1052 bytes of pool for every 508 bytes of
313 ;; code. For the last n bytes of code, there are 2n + 36 bytes of pool.
314 ;; If we have a forward branch, the initial table will be put after the
315 ;; unconditional branch.
316 ;;
317 ;; ??? We could do much better by keeping track of the actual pcloads within
318 ;; the branch range and in the pcload range in front of the branch range.
320 ;; ??? This looks ugly because genattrtab won't allow if_then_else or cond
321 ;; inside an le.
322 (define_attr "short_cbranch_p" "no,yes"
323 (cond [(match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
324 (const_string "no")
325 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 506))
326 (const_string "yes")
327 (match_test "NEXT_INSN (PREV_INSN (insn)) != insn")
328 (const_string "no")
329 (leu (plus (minus (match_dup 0) (pc)) (const_int 252)) (const_int 508))
330 (const_string "yes")
331 ] (const_string "no")))
333 (define_attr "med_branch_p" "no,yes"
334 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 990))
335 (const_int 1988))
336 (const_string "yes")
337 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
338 (const_string "no")
339 (leu (plus (minus (match_dup 0) (pc)) (const_int 4092))
340 (const_int 8186))
341 (const_string "yes")
342 ] (const_string "no")))
344 (define_attr "med_cbranch_p" "no,yes"
345 (cond [(leu (plus (minus (match_dup 0) (pc)) (const_int 988))
346 (const_int 1986))
347 (const_string "yes")
348 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
349 (const_string "no")
350 (leu (plus (minus (match_dup 0) (pc)) (const_int 4090))
351 (const_int 8184))
352 (const_string "yes")
353 ] (const_string "no")))
355 (define_attr "braf_branch_p" "no,yes"
356 (cond [(match_test "! TARGET_SH2")
357 (const_string "no")
358 (leu (plus (minus (match_dup 0) (pc)) (const_int 10330))
359 (const_int 20660))
360 (const_string "yes")
361 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
362 (const_string "no")
363 (leu (plus (minus (match_dup 0) (pc)) (const_int 32764))
364 (const_int 65530))
365 (const_string "yes")
366 ] (const_string "no")))
368 (define_attr "braf_cbranch_p" "no,yes"
369 (cond [(match_test "! TARGET_SH2")
370 (const_string "no")
371 (leu (plus (minus (match_dup 0) (pc)) (const_int 10328))
372 (const_int 20658))
373 (const_string "yes")
374 (match_test "mdep_reorg_phase <= SH_FIXUP_PCLOAD")
375 (const_string "no")
376 (leu (plus (minus (match_dup 0) (pc)) (const_int 32762))
377 (const_int 65528))
378 (const_string "yes")
379 ] (const_string "no")))
381 ;; An unconditional jump in the range -4092..4098 can be 2 bytes long.
382 ;; For wider ranges, we need a combination of a code and a data part.
383 ;; If we can get a scratch register for a long range jump, the code
384 ;; part can be 4 bytes long; otherwise, it must be 8 bytes long.
385 ;; If the jump is in the range -32764..32770, the data part can be 2 bytes
386 ;; long; otherwise, it must be 6 bytes long.
388 ;; All other instructions are two bytes long by default.
390 ;; ??? This should use something like *branch_p (minus (match_dup 0) (pc)),
391 ;; but getattrtab doesn't understand this.
392 (define_attr "length" ""
393 (cond [(eq_attr "type" "cbranch")
394 (cond [(eq_attr "short_cbranch_p" "yes")
395 (const_int 2)
396 (eq_attr "med_cbranch_p" "yes")
397 (const_int 6)
398 (eq_attr "braf_cbranch_p" "yes")
399 (const_int 12)
400 ;; ??? using pc is not computed transitively.
401 (ne (match_dup 0) (match_dup 0))
402 (const_int 14)
403 (match_test "flag_pic")
404 (const_int 24)
405 ] (const_int 16))
406 (eq_attr "type" "jump")
407 (cond [(eq_attr "med_branch_p" "yes")
408 (const_int 2)
409 (and (match_test "prev_nonnote_insn (insn)")
410 (and (eq (symbol_ref "GET_CODE (prev_nonnote_insn (insn))")
411 (symbol_ref "INSN"))
412 (eq (symbol_ref "INSN_CODE (prev_nonnote_insn (insn))")
413 (symbol_ref "code_for_indirect_jump_scratch"))))
414 (cond [(eq_attr "braf_branch_p" "yes")
415 (const_int 6)
416 (not (match_test "flag_pic"))
417 (const_int 10)
418 (match_test "TARGET_SH2")
419 (const_int 10)] (const_int 18))
420 (eq_attr "braf_branch_p" "yes")
421 (const_int 10)
422 ;; ??? using pc is not computed transitively.
423 (ne (match_dup 0) (match_dup 0))
424 (const_int 12)
425 (match_test "flag_pic")
426 (const_int 22)
427 ] (const_int 14))
428 ] (const_int 2)))
430 ;; DFA descriptions for the pipelines
432 (include "sh1.md")
433 (include "sh4.md")
435 (include "iterators.md")
436 (include "predicates.md")
437 (include "constraints.md")
439 ;; Definitions for filling delay slots
441 (define_attr "needs_delay_slot" "yes,no" (const_string "no"))
443 (define_attr "banked" "yes,no"
444 (cond [(match_test "sh_loads_bankedreg_p (insn)")
445 (const_string "yes")]
446 (const_string "no")))
448 ;; ??? This should be (nil) instead of (const_int 0)
449 (define_attr "hit_stack" "yes,no"
450 (cond [(not (match_test "find_regno_note (insn, REG_INC, SP_REG)"))
451 (const_string "no")]
452 (const_string "yes")))
454 (define_attr "interrupt_function" "no,yes"
455 (const (symbol_ref "current_function_interrupt")))
457 (define_attr "in_delay_slot" "yes,no"
458 (cond [(eq_attr "type" "cbranch") (const_string "no")
459 (eq_attr "type" "pcload,pcload_si") (const_string "no")
460 (eq_attr "type" "fpscr_toggle") (const_string "no")
461 (eq_attr "needs_delay_slot" "yes") (const_string "no")
462 (eq_attr "length" "2") (const_string "yes")
463 ] (const_string "no")))
465 (define_attr "cond_delay_slot" "yes,no"
466 (cond [(eq_attr "in_delay_slot" "yes") (const_string "yes")
467 ] (const_string "no")))
469 (define_attr "is_sfunc" ""
470 (if_then_else (eq_attr "type" "sfunc") (const_int 1) (const_int 0)))
472 ;; SH4 Double-precision computation with double-precision result -
473 ;; the two halves are ready at different times.
474 (define_attr "dfp_comp" "yes,no"
475 (cond [(eq_attr "type" "dfp_arith,dfp_mul,dfp_conv,dfdiv") (const_string "yes")]
476 (const_string "no")))
478 ;; Insns for which the latency of a preceding fp insn is decreased by one.
479 (define_attr "late_fp_use" "yes,no" (const_string "no"))
480 ;; And feeding insns for which this relevant.
481 (define_attr "any_fp_comp" "yes,no"
482 (cond [(eq_attr "type" "fp,fdiv,ftrc_s,dfp_arith,dfp_mul,dfp_conv,dfdiv")
483 (const_string "yes")]
484 (const_string "no")))
486 (define_attr "any_int_load" "yes,no"
487 (cond [(eq_attr "type" "load,load_si,pcload,pcload_si")
488 (const_string "yes")]
489 (const_string "no")))
491 (define_attr "highpart" "user, ignore, extend, depend, must_split"
492 (const_string "user"))
494 (define_delay
495 (eq_attr "needs_delay_slot" "yes")
496 [(eq_attr "in_delay_slot" "yes") (nil) (nil)])
498 ;; Since a normal return (rts) implicitly uses the PR register,
499 ;; we can't allow PR register loads in an rts delay slot.
500 ;; On the SH1* and SH2*, the rte instruction reads the return pc from the
501 ;; stack, and thus we can't put a pop instruction in its delay slot.
502 ;; On the SH3* and SH4*, the rte instruction does not use the stack, so a
503 ;; pop instruction can go in the delay slot, unless it references a banked
504 ;; register (the register bank is switched by rte).
505 (define_delay
506 (eq_attr "type" "return")
507 [(and (eq_attr "in_delay_slot" "yes")
508 (ior (and (eq_attr "interrupt_function" "no")
509 (eq_attr "type" "!pload,prset"))
510 (and (eq_attr "interrupt_function" "yes")
511 (ior (match_test "TARGET_SH3") (eq_attr "hit_stack" "no"))
512 (eq_attr "banked" "no"))))
513 (nil) (nil)])
515 ;; Since a call implicitly uses the PR register, we can't allow
516 ;; a PR register store in a jsr delay slot.
518 (define_delay
519 (ior (eq_attr "type" "call") (eq_attr "type" "sfunc"))
520 [(and (eq_attr "in_delay_slot" "yes")
521 (eq_attr "type" "!pstore,prget")) (nil) (nil)])
523 ;; Conditional branches with delay slots are available starting with SH2.
524 ;; If zero displacement conditional branches are fast, disable the delay
525 ;; slot if the branch jumps over only one 2-byte insn.
526 (define_delay
527 (and (eq_attr "type" "cbranch")
528 (match_test "TARGET_SH2")
529 (not (and (match_test "TARGET_ZDCBRANCH")
530 (match_test "sh_cbranch_distance (insn, 4) == 2"))))
531 [(eq_attr "cond_delay_slot" "yes") (nil) (nil)])
532 \f
533 ;; -------------------------------------------------------------------------
534 ;; SImode signed integer comparisons
535 ;; -------------------------------------------------------------------------
537 ;; Patterns to generate the tst instruction which are usually formed by
538 ;; the combine pass.
539 ;; The canonical form here being used is (eq (and (op) (op)) 0).
540 ;; For some bit patterns, such as contiguous bits, we also must accept
541 ;; zero_extract forms. Single bit tests are also handled via zero_extract
542 ;; patterns in the 'bit field extract patterns' section. All variants
543 ;; are eventually converted to the 'tstsi_t' insn.
544 ;; As long as pseudos can be created (before RA), 'tstsi_t' will also accept
545 ;; constants that won't fit into 8 bits. After having captured the constant
546 ;; we can decide better whether/how to load it into a register and do other
547 ;; post-combine optimizations such as bypassing sign/zero extensions.
548 (define_insn_and_split "tstsi_t"
549 [(set (reg:SI T_REG)
550 (eq:SI (and:SI (match_operand:SI 0 "arith_reg_operand" "%z,r")
551 (match_operand:SI 1 "arith_or_int_operand" "K08,?r"))
552 (const_int 0)))]
553 "TARGET_SH1
554 && (can_create_pseudo_p () || arith_reg_operand (operands[1], SImode)
555 || satisfies_constraint_K08 (operands[1]))"
556 "tst %1,%0"
557 "TARGET_SH1 && can_create_pseudo_p () && CONST_INT_P (operands[1])
558 && !sh_in_recog_treg_set_expr ()"
559 [(const_int 0)]
560 {
561 gcc_assert (CONST_INT_P (operands[1]));
563 HOST_WIDE_INT op1val = INTVAL (operands[1]);
564 rtx reg = operands[0];
565 if (SUBREG_P (reg))
566 reg = SUBREG_REG (reg);
567 gcc_assert (REG_P (reg));
568 bool op0_dead_after_this =
569 sh_reg_dead_or_unused_after_insn (curr_insn, REGNO (reg));
571 if (optimize)
572 {
573 if (dump_file)
574 fprintf (dump_file,
575 "tstsi_t: trying to optimize const_int 0x%08x\n",
576 (uint32_t)op1val);
578 /* See if we can convert a test with a reg and a constant into
579 something simpler, if the reg is known to be zero or sign
580 extended. */
581 sh_extending_set_of_reg eop0 = sh_find_extending_set_of_reg (operands[0],
582 curr_insn);
583 if (eop0.ext_code != UNKNOWN)
584 {
585 /* Adjust the constant, trying to eliminate bits that are not
586 contributing to the result. */
587 if (eop0.from_mode == QImode)
588 op1val = (op1val
589 | (eop0.ext_code == SIGN_EXTEND && (op1val & 0xFFFFFF80)
590 ? 0x80 : 0)) & 0xFF;
591 else if (eop0.from_mode == HImode)
592 op1val = (op1val
593 | (eop0.ext_code == SIGN_EXTEND && (op1val & 0xFFFF8000)
594 ? 0x8000 : 0)) & 0xFFFF;
596 if (dump_file)
597 fprintf (dump_file, "tstsi_t: using effective const_int: 0x%08x\n",
598 (uint32_t)op1val);
600 /* Try to bypass the sign/zero extension first if op0 dies after
601 this insn. */
602 if (op0_dead_after_this && eop0.can_use_as_unextended_reg ())
603 {
604 if (dump_file)
605 fprintf (dump_file, "tstsi_t: bypassing sign/zero extension\n");
607 operands[0] = eop0.use_as_unextended_reg (curr_insn);
608 }
609 else if ((eop0.from_mode == QImode && op1val == 0xFF)
610 || (eop0.from_mode == HImode && op1val == 0xFFFF))
611 {
612 if (dump_file)
613 fprintf (dump_file, "tstsi_t: converting to cmpeqsi_t\n");
614 emit_insn (gen_cmpeqsi_t (eop0.use_as_extended_reg (curr_insn),
615 const0_rtx));
616 DONE;
617 }
618 else if (eop0.ext_code == SIGN_EXTEND
619 && ((eop0.from_mode == QImode && op1val == 0x80)
620 || (eop0.from_mode == HImode && op1val == 0x8000)))
621 {
622 if (dump_file)
623 fprintf (dump_file, "tstsi_t: converting to cmpgesi_t\n");
624 emit_insn (gen_cmpgesi_t (eop0.use_as_extended_reg (curr_insn),
625 const0_rtx));
626 DONE;
627 }
628 else if (!CONST_OK_FOR_K08 (op1val))
629 {
630 if (dump_file)
631 fprintf (dump_file, "tstsi_t: converting const_int to signed "
632 "value\n");
634 /* If here we haven't done anything yet. Convert the constant
635 to a signed value to reduce the constant pool size. */
636 operands[0] = eop0.use_as_extended_reg (curr_insn);
638 if (eop0.from_mode == QImode)
639 op1val |= (op1val & 0x80) ? 0xFFFFFFFFFFFFFF00LL : 0;
640 else if (eop0.from_mode == HImode)
641 op1val |= (op1val & 0x8000) ? 0xFFFFFFFFFFFF0000LL : 0;
642 }
643 else
644 operands[0] = eop0.use_as_extended_reg (curr_insn);
645 }
646 }
648 if (dump_file)
649 fprintf (dump_file, "tstsi_t: using const_int 0x%08x\n",
650 (uint32_t)op1val);
652 /* Try to fit the constant into 8 bits by shuffling the value in the
653 register operand.
654 Doing that usually results in smaller code as the constants in the
655 pools are avoided (32 bit constant = load + constant = 6 bytes).
656 However, if the constant load (LS insn) can be hoisted insn dependencies
657 can be avoided and chances for parallel execution increase. The common
658 usage pattern is:
659 - load reg from mem
660 - test bits
661 - conditional branch
663 FIXME: For now we do that only when optimizing for size until there is
664 a better heuristic.
666 FIXME: If there are multiple tst insns in the block with the same
667 constant, avoid the #imm variant to avoid R0 loads. Use the 'tst Rn,Rm'
668 variant instead and load the constant into a reg. For that we'd need
669 to do some analysis. */
671 if (CONST_OK_FOR_K08 (op1val))
672 {
673 /* Do nothing. */
674 }
675 else if ((op1val & 0xFFFF) == 0
676 && CONST_OK_FOR_K08 (op1val >> 16) && optimize_size)
677 {
678 /* Use a swap.w insn to do a shift + reg copy (to R0) in one insn. */
679 op1val = op1val >> 16;
680 rtx r = gen_reg_rtx (SImode);
681 emit_insn (gen_rotlsi3_16 (r, operands[0]));
682 operands[0] = r;
683 }
684 else if ((op1val & 0xFF) == 0
685 && CONST_OK_FOR_K08 (op1val >> 8) && optimize_size)
686 {
687 /* Use a swap.b insn to do a shift + reg copy (to R0) in one insn. */
688 op1val = op1val >> 8;
689 rtx r = gen_reg_rtx (SImode);
690 emit_insn (gen_swapbsi2 (r, operands[0]));
691 operands[0] = r;
692 }
693 else if ((op1val & 3) == 0
694 && CONST_OK_FOR_K08 (op1val >> 2) && optimize_size)
695 {
696 op1val = op1val >> 2;
697 rtx r = gen_reg_rtx (SImode);
698 emit_insn (gen_lshrsi3_k (r, operands[0], GEN_INT (2)));
699 operands[0] = r;
700 }
701 else if ((op1val & 1) == 0
702 && CONST_OK_FOR_K08 (op1val >> 1) && optimize_size)
703 {
704 op1val = op1val >> 1;
705 rtx r = gen_reg_rtx (SImode);
706 emit_insn (gen_shlr (r, operands[0]));
707 operands[0] = r;
708 }
710 operands[1] = GEN_INT (op1val);
712 if (!satisfies_constraint_K08 (operands[1]))
713 operands[1] = force_reg (SImode, operands[1]);
715 emit_insn (gen_tstsi_t (operands[0], operands[1]));
716 DONE;
717 }
718 [(set_attr "type" "mt_group")])
720 ;; This pattern is used by combine when testing QI/HImode subregs with a
721 ;; negative constant. Ignore high bits by masking them out in the constant.
722 (define_insn_and_split "*tst<mode>_t"
723 [(set (reg:SI T_REG)
724 (eq:SI (subreg:SI
725 (and:QIHI (match_operand:QIHI 0 "arith_reg_operand")
726 (match_operand 1 "const_int_operand")) 0)
727 (const_int 0)))]
728 "TARGET_SH1 && can_create_pseudo_p ()"
729 "#"
730 "&& 1"
731 [(set (reg:SI T_REG)
732 (eq:SI (and:SI (match_dup 0) (match_dup 1)) (const_int 0)))]
733 {
734 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
735 operands[1] = GEN_INT (INTVAL (operands[1])
736 & (<MODE>mode == HImode ? 0xFFFF : 0xFF));
737 })
739 ;; This pattern might be risky because it also tests the upper bits and not
740 ;; only the subreg. We have to check whether the operands have been sign
741 ;; or zero extended. In the worst case, a zero extension has to be inserted
742 ;; to mask out the unwanted bits.
743 (define_insn_and_split "*tst<mode>_t_subregs"
744 [(set (reg:SI T_REG)
745 (eq:SI
746 (subreg:QIHI
747 (and:SI (match_operand:SI 0 "arith_reg_operand")
748 (match_operand:SI 1 "arith_reg_operand")) <lowpart_le>)
749 (const_int 0)))]
750 "TARGET_SH1 && TARGET_LITTLE_ENDIAN && can_create_pseudo_p ()"
751 "#"
752 "&& !sh_in_recog_treg_set_expr ()"
753 [(const_int 0)]
754 {
755 sh_split_tst_subregs (curr_insn, <MODE>mode, <lowpart_le>, operands);
756 DONE;
757 })
759 (define_insn_and_split "*tst<mode>_t_subregs"
760 [(set (reg:SI T_REG)
761 (eq:SI
762 (subreg:QIHI
763 (and:SI (match_operand:SI 0 "arith_reg_operand")
764 (match_operand:SI 1 "arith_reg_operand")) <lowpart_be>)
765 (const_int 0)))]
766 "TARGET_SH1 && TARGET_BIG_ENDIAN && can_create_pseudo_p ()"
767 "#"
768 "&& !sh_in_recog_treg_set_expr ()"
769 [(const_int 0)]
770 {
771 sh_split_tst_subregs (curr_insn, <MODE>mode, <lowpart_be>, operands);
772 DONE;
773 })
775 ;; Extract contiguous bits and compare them against zero.
776 ;; Notice that this will not be used for single bits. Special single bit
777 ;; extraction patterns are in the 'bit field extract patterns' section.
778 (define_insn_and_split "*tst<mode>_t_zero_extract"
779 [(set (reg:SI T_REG)
780 (eq:SI (zero_extract:SI (match_operand:QIHISI 0 "arith_reg_operand")
781 (match_operand 1 "const_int_operand")
782 (match_operand 2 "const_int_operand"))
783 (const_int 0)))]
784 "TARGET_SH1 && can_create_pseudo_p ()"
785 "#"
786 "&& 1"
787 [(set (reg:SI T_REG)
788 (eq:SI (and:SI (match_dup 0) (match_dup 1)) (const_int 0)))]
789 {
790 operands[1] = GEN_INT (ZERO_EXTRACT_ANDMASK (operands[1], operands[2]));
791 if (GET_MODE (operands[0]) != SImode)
792 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
793 })
795 ;; Convert '(reg << shift) & mask' into 'reg & (mask >> shift)'.
796 ;; The shifted-out bits in the mask will always be zero, since the
797 ;; shifted-in bits in the reg will also be always zero.
798 (define_insn_and_split "*tstsi_t_shift_mask"
799 [(set (reg:SI T_REG)
800 (eq:SI (and:SI (ashift:SI (match_operand:SI 0 "arith_reg_operand")
801 (match_operand 1 "const_int_operand"))
802 (match_operand 2 "const_int_operand"))
803 (const_int 0)))]
804 "TARGET_SH1 && can_create_pseudo_p ()"
805 "#"
806 "&& 1"
807 [(set (reg:SI T_REG)
808 (eq:SI (and:SI (match_dup 0) (match_dup 2)) (const_int 0)))]
809 {
810 operands[2] = GEN_INT (INTVAL (operands[2]) >> INTVAL (operands[1]));
811 })
813 (define_insn "cmpeqsi_t"
814 [(set (reg:SI T_REG)
815 (eq:SI (match_operand:SI 0 "arith_reg_operand" "r,z,r")
816 (match_operand:SI 1 "arith_operand" "N,rI08,r")))]
817 "TARGET_SH1"
818 "@
819 tst %0,%0
820 cmp/eq %1,%0
821 cmp/eq %1,%0"
822 [(set_attr "type" "mt_group")])
824 ;; Sometimes combine fails to form the (eq (and (op) (op)) 0) tst insn.
825 ;; Try to fix that in the split1 pass by looking for the previous set
826 ;; of the tested op. Also see if there is a preceeding sign/zero
827 ;; extension that can be avoided.
828 (define_split
829 [(set (reg:SI T_REG)
830 (eq:SI (match_operand:SI 0 "arith_reg_operand") (const_int 0)))]
831 "TARGET_SH1 && can_create_pseudo_p () && optimize
832 && !sh_in_recog_treg_set_expr ()"
833 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))]
834 {
835 if (dump_file)
836 fprintf (dump_file, "cmpeqsi_t: trying to optimize const_int 0\n");
838 /* If the tested reg is not dead after this insn, it's probably used by
839 something else after the comparison. It's probably better to leave
840 it as it is. */
841 rtx reg = operands[0];
842 if (SUBREG_P (reg))
843 reg = SUBREG_REG (reg);
844 gcc_assert (REG_P (reg));
845 if (find_regno_note (curr_insn, REG_DEAD, REGNO (reg)) != NULL_RTX)
846 FAIL;
848 /* FIXME: Maybe also search the predecessor basic blocks to catch
849 more cases. */
850 set_of_reg op = sh_find_set_of_reg (operands[0], curr_insn,
851 prev_nonnote_nondebug_insn_bb);
853 if (op.set_src != NULL && GET_CODE (op.set_src) == AND
854 && !sh_insn_operands_modified_between_p (op.insn, op.insn, curr_insn))
855 {
856 if (dump_file)
857 fprintf (dump_file, "cmpeqsi_t: found preceeding and in insn %d\n",
858 INSN_UID (op.insn));
860 if (!(arith_reg_operand (XEXP (op.set_src, 0), SImode)
861 && (arith_reg_operand (XEXP (op.set_src, 1), SImode)
862 || CONST_INT_P (XEXP (op.set_src, 1)))))
863 FAIL;
865 /* Assume that the operands of the andsi insn are compatible with the
866 operands of the tstsi_t insn, which is generally the case. */
867 if (dump_file)
868 fprintf (dump_file, "cmpeqsi_t: replacing with tstsi_t\n");
869 emit_insn (gen_tstsi_t (copy_rtx (XEXP (op.set_src, 0)),
870 copy_rtx (XEXP (op.set_src, 1))));
871 DONE;
872 }
874 /* Converting HImode into tests against 0xFFFF tends to increase the code
875 size, as it will create constant pool entries. Disable it for now. */
876 const bool enable_himode = false;
878 /* FIXME: try to keep the (eq (reg) (const_int 0)). Even if the zero
879 extended reg is used after this insn, if we know that _before_ the zero
880 extension the value was loaded via sign extending mem load, we can just
881 use the value of the mem load directly. */
882 sh_extending_set_of_reg eop = sh_find_extending_set_of_reg (operands[0],
883 curr_insn);
885 if (eop.ext_code != UNKNOWN
886 && (eop.from_mode == QImode || (eop.from_mode == HImode && enable_himode))
887 && eop.can_use_as_unextended_reg ()
888 && !reg_used_between_p (operands[0], eop.insn, curr_insn))
889 {
890 /* Bypass the sign/zero extension and test against the bit mask, but
891 only if it's the only use of the sign/zero extracted value.
892 Otherwise we'd be introducing new constants in the pool. */
893 if (dump_file)
894 fprintf (dump_file, "cmpeqsi_t: bypassing sign/zero extension in "
895 "insn %d and using tstsi_t\n", INSN_UID (op.insn));
897 emit_insn (gen_tstsi_t (
898 eop.use_as_unextended_reg (curr_insn),
899 GEN_INT (eop.from_mode == QImode ? 0xFF : 0xFFFF)));
900 DONE;
901 }
903 if (dump_file)
904 fprintf (dump_file, "cmpeqsi_t: nothing optimized\n");
905 FAIL;
906 })
908 (define_insn "cmpgtsi_t"
909 [(set (reg:SI T_REG)
910 (gt:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
911 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))]
912 "TARGET_SH1"
913 "@
914 cmp/pl %0
915 cmp/gt %1,%0"
916 [(set_attr "type" "mt_group")])
918 (define_insn "cmpgesi_t"
919 [(set (reg:SI T_REG)
920 (ge:SI (match_operand:SI 0 "arith_reg_operand" "r,r")
921 (match_operand:SI 1 "arith_reg_or_0_operand" "N,r")))]
922 "TARGET_SH1"
923 "@
924 cmp/pz %0
925 cmp/ge %1,%0"
926 [(set_attr "type" "mt_group")])
928 ;; Recombine a cmp/pz followed by a nott into a shll.
929 ;; On non-SH2A recombine a cmp/pz followed by a movrt into shll-movt.
930 ;; On SH2A cmp/pz-movrt is slightly better, as it does not mutate the input.
931 (define_split
932 [(set (reg:SI T_REG)
933 (ge:SI (match_operand:SI 0 "arith_reg_operand") (const_int 0)))]
935 "TARGET_SH1 && can_create_pseudo_p () && optimize
936 && !sh_in_recog_treg_set_expr ()"
937 [(const_int 0)]
938 {
939 if (dump_file)
940 fprintf (dump_file, "cmpgesi_t: trying to optimize for const_int 0\n");
942 rtx_insn* i = next_nonnote_nondebug_insn_bb (curr_insn);
944 if (dump_file)
945 {
946 fprintf (dump_file, "cmpgesi_t: following insn is \n");
947 print_rtl_single (dump_file, i);
948 fprintf (dump_file, "\n");
949 }
951 if (sh_is_nott_insn (i))
952 {
953 if (dump_file)
954 fprintf (dump_file,
955 "cmpgesi_t: replacing (cmp/pz, nott) with (shll)\n");
956 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
957 set_insn_deleted (i);
958 DONE;
959 }
961 /* On non-SH2A negc is used as movrt replacement, which sets T = 1.
962 Thus we can remove it only if T is marked as dead afterwards. */
963 if (rtx dest_reg = !TARGET_SH2A
964 && sh_reg_dead_or_unused_after_insn (i, T_REG)
965 ? sh_movrt_set_dest (i) : NULL)
966 {
967 if (dump_file)
968 fprintf (dump_file,
969 "cmpgesi_t: replacing (cmp/pz, movrt) with (shll, movt)\n");
970 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
971 add_reg_note (emit_insn (gen_movt (dest_reg, get_t_reg_rtx ())),
972 REG_DEAD, get_t_reg_rtx ());
973 set_insn_deleted (i);
974 DONE;
975 }
977 if (dump_file)
978 fprintf (dump_file, "cmpgesi_t: nothing optimized\n");
980 FAIL;
981 })
983 ;; FIXME: This is actually wrong. There is no way to literally move a
984 ;; general reg to t reg. Luckily, it seems that this pattern will be only
985 ;; used when the general reg is known be either '0' or '1' during combine.
986 ;; What we actually need is reg != 0 -> T, but we have only reg == 0 -> T.
987 ;; Due to interactions with other patterns, combine fails to pick the latter
988 ;; and invert the dependent logic.
989 (define_insn "*negtstsi"
990 [(set (reg:SI T_REG) (match_operand:SI 0 "arith_reg_operand" "r"))]
991 "TARGET_SH1 && !sh_in_recog_treg_set_expr ()"
992 "cmp/pl %0"
993 [(set_attr "type" "mt_group")])
995 ;; Some integer sign comparison patterns can be realized with the div0s insn.
996 ;; div0s Rm,Rn T = (Rm >> 31) ^ (Rn >> 31)
997 ;;
998 ;; The 'cmp_div0s' pattern is our canonical form, into which all the other
999 ;; variations are converted. The negative forms will split into a trailing
1000 ;; nott sequence, which will be eliminated either by the
1001 ;; 'any_treg_expr_to_reg' pattern, or by the 'sh_treg_combine' pass.
1002 (define_insn "cmp_div0s"
1003 [(set (reg:SI T_REG)
1004 (lshiftrt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand" "%r")
1005 (match_operand:SI 1 "arith_reg_operand" "r"))
1006 (const_int 31)))]
1007 "TARGET_SH1"
1008 "div0s %0,%1"
1009 [(set_attr "type" "arith")])
1011 (define_insn_and_split "*cmp_div0s_1"
1012 [(set (reg:SI T_REG)
1013 (xor:SI (ge:SI (match_operand:SI 0 "arith_reg_operand")
1014 (const_int 0))
1015 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1016 (const_int 0))))]
1017 "TARGET_SH1 && can_create_pseudo_p ()"
1018 "#"
1019 "&& 1"
1020 [(set (reg:SI T_REG)
1021 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))])
1023 (define_insn_and_split "*cmp_div0s_2"
1024 [(set (reg:SI T_REG)
1025 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
1026 (const_int 31))
1027 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1028 (const_int 0))))]
1029 "TARGET_SH1 && can_create_pseudo_p ()"
1030 "#"
1031 "&& 1"
1032 [(set (reg:SI T_REG)
1033 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))])
1035 (define_insn_and_split "*cmp_div0s_3"
1036 [(set (reg:SI T_REG)
1037 (eq:SI (ge:SI (match_operand:SI 0 "arith_reg_operand")
1038 (const_int 0))
1039 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1040 (const_int 0))))]
1041 "TARGET_SH1 && can_create_pseudo_p ()"
1042 "#"
1043 "&& 1"
1044 [(set (reg:SI T_REG)
1045 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1046 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1048 (define_insn_and_split "*cmp_div0s_4"
1049 [(set (reg:SI T_REG)
1050 (ge:SI (xor:SI (match_operand:SI 0 "arith_reg_operand")
1051 (match_operand:SI 1 "arith_reg_operand"))
1052 (const_int 0)))]
1053 "TARGET_SH1 && can_create_pseudo_p ()"
1054 "#"
1055 "&& 1"
1056 [(set (reg:SI T_REG)
1057 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1058 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1060 (define_insn_and_split "*cmp_div0s_5"
1061 [(set (reg:SI T_REG)
1062 (xor:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
1063 (const_int 31))
1064 (ge:SI (match_operand:SI 1 "arith_reg_operand")
1065 (const_int 0))))]
1066 "TARGET_SH1 && can_create_pseudo_p ()"
1067 "#"
1068 "&& 1"
1069 [(set (reg:SI T_REG)
1070 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1071 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1073 (define_insn_and_split "*cmp_div0s_6"
1074 [(set (reg:SI T_REG)
1075 (eq:SI (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
1076 (const_int 31))
1077 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
1078 (const_int 31))))]
1079 "TARGET_SH1 && can_create_pseudo_p ()"
1080 "#"
1081 "&& 1"
1082 [(set (reg:SI T_REG)
1083 (lshiftrt:SI (xor:SI (match_dup 0) (match_dup 1)) (const_int 31)))
1084 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1086 ;; In some cases, it might be shorter to get a tested bit into bit 31 and
1087 ;; use div0s. Otherwise it's usually better to just leave the xor and tst
1088 ;; sequence. The only thing we can try to do here is avoiding the large
1089 ;; tst constant.
1090 (define_insn_and_split "*cmp_div0s_7"
1091 [(set (reg:SI T_REG)
1092 (zero_extract:SI (xor:SI (match_operand:SI 0 "arith_reg_operand")
1093 (match_operand:SI 1 "arith_reg_operand"))
1094 (const_int 1)
1095 (match_operand 2 "const_int_operand")))]
1096 "TARGET_SH1 && can_create_pseudo_p ()
1097 && (INTVAL (operands[2]) == 7 || INTVAL (operands[2]) == 15
1098 || INTVAL (operands[2]) == 23 || INTVAL (operands[2]) == 29
1099 || INTVAL (operands[2]) == 30 || INTVAL (operands[2]) == 31)"
1100 "#"
1101 "&& 1"
1102 [(const_int 0)]
1103 {
1104 const int bitpos = INTVAL (operands[2]);
1106 rtx op0 = gen_reg_rtx (SImode);
1107 rtx op1 = gen_reg_rtx (SImode);
1109 if (bitpos == 23 || bitpos == 30 || bitpos == 29)
1110 {
1111 emit_insn (gen_ashlsi3 (op0, operands[0], GEN_INT (31 - bitpos)));
1112 emit_insn (gen_ashlsi3 (op1, operands[1], GEN_INT (31 - bitpos)));
1113 }
1114 else if (bitpos == 15)
1115 {
1116 emit_insn (gen_extendhisi2 (op0, gen_lowpart (HImode, operands[0])));
1117 emit_insn (gen_extendhisi2 (op1, gen_lowpart (HImode, operands[1])));
1118 }
1119 else if (bitpos == 7)
1120 {
1121 emit_insn (gen_extendqisi2 (op0, gen_lowpart (QImode, operands[0])));
1122 emit_insn (gen_extendqisi2 (op1, gen_lowpart (QImode, operands[1])));
1123 }
1124 else if (bitpos == 31)
1125 {
1126 op0 = operands[0];
1127 op1 = operands[1];
1128 }
1129 else
1130 gcc_unreachable ();
1132 emit_insn (gen_cmp_div0s (op0, op1));
1133 DONE;
1134 })
1136 ;; For bits 0..7 using a xor and tst #imm,r0 sequence seems to be better.
1137 ;; Thus allow the following patterns only for higher bit positions where
1138 ;; we it's more likely to save the large tst constant.
1139 (define_insn_and_split "*cmp_div0s_8"
1140 [(set (reg:SI T_REG)
1141 (eq:SI (zero_extract:SI (match_operand:SI 0 "arith_reg_operand")
1142 (const_int 1)
1143 (match_operand 2 "const_int_operand"))
1144 (zero_extract:SI (match_operand:SI 1 "arith_reg_operand")
1145 (const_int 1)
1146 (match_dup 2))))]
1147 "TARGET_SH1 && can_create_pseudo_p ()
1148 && (INTVAL (operands[2]) == 15
1149 || INTVAL (operands[2]) == 23 || INTVAL (operands[2]) == 29
1150 || INTVAL (operands[2]) == 30 || INTVAL (operands[2]) == 31)"
1151 "#"
1152 "&& 1"
1153 [(set (reg:SI T_REG)
1154 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
1155 (const_int 1) (match_dup 2)))
1156 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1158 (define_insn_and_split "*cmp_div0s_9"
1159 [(set (reg:SI T_REG)
1160 (zero_extract:SI (xor:SI (xor:SI (match_operand:SI 0 "arith_reg_operand")
1161 (match_operand:SI 1 "arith_reg_operand"))
1162 (match_operand 2 "const_int_operand"))
1163 (const_int 1)
1164 (match_operand 3 "const_int_operand")))]
1165 "TARGET_SH1 && can_create_pseudo_p ()
1166 && (INTVAL (operands[2]) & 0xFFFFFFFF) == (1U << INTVAL (operands[3]))
1167 && (INTVAL (operands[3]) == 15
1168 || INTVAL (operands[3]) == 23 || INTVAL (operands[3]) == 29
1169 || INTVAL (operands[3]) == 30 || INTVAL (operands[3]) == 31)"
1170 "#"
1171 "&& 1"
1172 [(set (reg:SI T_REG)
1173 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
1174 (const_int 1) (match_dup 3)))
1175 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))])
1177 ;; -------------------------------------------------------------------------
1178 ;; SImode compare and branch
1179 ;; -------------------------------------------------------------------------
1181 (define_expand "cbranchsi4"
1182 [(set (pc)
1183 (if_then_else (match_operator 0 "comparison_operator"
1184 [(match_operand:SI 1 "arith_operand" "")
1185 (match_operand:SI 2 "arith_operand" "")])
1186 (label_ref (match_operand 3 "" ""))
1187 (pc)))
1188 (clobber (reg:SI T_REG))]
1189 "can_create_pseudo_p ()"
1190 {
1191 expand_cbranchsi4 (operands, LAST_AND_UNUSED_RTX_CODE);
1192 DONE;
1193 })
1195 ;; Combine patterns to invert compare and branch operations for which we
1196 ;; don't have actual comparison insns. These patterns are used in cases
1197 ;; which appear after the initial cbranchsi expansion, which also does
1198 ;; some condition inversion.
1199 (define_split
1200 [(set (pc)
1201 (if_then_else (ne (match_operand:SI 0 "arith_reg_operand" "")
1202 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1203 (label_ref (match_operand 2))
1204 (pc)))
1205 (clobber (reg:SI T_REG))]
1206 "TARGET_SH1"
1207 [(set (reg:SI T_REG) (eq:SI (match_dup 0) (match_dup 1)))
1208 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1209 (label_ref (match_dup 2))
1210 (pc)))])
1212 ;; FIXME: These don't seem to have any effect on the generated cbranch code
1213 ;; anymore, but only on some register allocation choices.
1214 (define_split
1215 [(set (pc)
1216 (if_then_else (le (match_operand:SI 0 "arith_reg_operand" "")
1217 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1218 (label_ref (match_operand 2))
1219 (pc)))
1220 (clobber (reg:SI T_REG))]
1221 "TARGET_SH1"
1222 [(set (reg:SI T_REG) (gt:SI (match_dup 0) (match_dup 1)))
1223 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1224 (label_ref (match_dup 2))
1225 (pc)))])
1227 (define_split
1228 [(set (pc)
1229 (if_then_else (lt (match_operand:SI 0 "arith_reg_operand" "")
1230 (match_operand:SI 1 "arith_reg_or_0_operand" ""))
1231 (label_ref (match_operand 2))
1232 (pc)))
1233 (clobber (reg:SI T_REG))]
1234 "TARGET_SH1"
1235 [(set (reg:SI T_REG) (ge:SI (match_dup 0) (match_dup 1)))
1236 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1237 (label_ref (match_dup 2))
1238 (pc)))])
1240 (define_split
1241 [(set (pc)
1242 (if_then_else (leu (match_operand:SI 0 "arith_reg_operand" "")
1243 (match_operand:SI 1 "arith_reg_operand" ""))
1244 (label_ref (match_operand 2))
1245 (pc)))
1246 (clobber (reg:SI T_REG))]
1247 "TARGET_SH1"
1248 [(set (reg:SI T_REG) (gtu:SI (match_dup 0) (match_dup 1)))
1249 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1250 (label_ref (match_dup 2))
1251 (pc)))])
1253 (define_split
1254 [(set (pc)
1255 (if_then_else (ltu (match_operand:SI 0 "arith_reg_operand" "")
1256 (match_operand:SI 1 "arith_reg_operand" ""))
1257 (label_ref (match_operand 2))
1258 (pc)))
1259 (clobber (reg:SI T_REG))]
1260 "TARGET_SH1"
1261 [(set (reg:SI T_REG) (geu:SI (match_dup 0) (match_dup 1)))
1262 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1263 (label_ref (match_dup 2))
1264 (pc)))])
1266 ;; -------------------------------------------------------------------------
1267 ;; SImode unsigned integer comparisons
1268 ;; -------------------------------------------------------------------------
1270 ;; Usually comparisons of 'unsigned int >= 0' are optimized away completely.
1271 ;; However, especially when optimizations are off (e.g. -O0) such comparisons
1272 ;; might remain and we have to handle them. If the '>= 0' case wasn't
1273 ;; handled here, something else would just load a '0' into the second operand
1274 ;; and do the comparison. We can do slightly better by just setting the
1275 ;; T bit to '1'.
1276 (define_insn_and_split "cmpgeusi_t"
1277 [(set (reg:SI T_REG)
1278 (geu:SI (match_operand:SI 0 "arith_reg_operand" "r")
1279 (match_operand:SI 1 "arith_reg_or_0_operand" "r")))]
1280 "TARGET_SH1"
1281 "cmp/hs %1,%0"
1282 "&& satisfies_constraint_Z (operands[1])"
1283 [(set (reg:SI T_REG) (const_int 1))]
1284 ""
1285 [(set_attr "type" "mt_group")])
1287 (define_insn "cmpgtusi_t"
1288 [(set (reg:SI T_REG)
1289 (gtu:SI (match_operand:SI 0 "arith_reg_operand" "r")
1290 (match_operand:SI 1 "arith_reg_operand" "r")))]
1291 "TARGET_SH1"
1292 "cmp/hi %1,%0"
1293 [(set_attr "type" "mt_group")])
1294 \f
1295 ;; -------------------------------------------------------------------------
1296 ;; DImode compare and branch
1297 ;; -------------------------------------------------------------------------
1299 ;; arith3 patterns don't work well with the sh4-300 branch prediction mechanism.
1300 ;; Therefore, we aim to have a set of three branches that go straight to the
1301 ;; destination, i.e. only one of them is taken at any one time.
1302 ;; This mechanism should also be slightly better for the sh4-200.
1304 (define_expand "cbranchdi4"
1305 [(set (pc)
1306 (if_then_else (match_operator 0 "comparison_operator"
1307 [(match_operand:DI 1 "arith_operand")
1308 (match_operand:DI 2 "arith_operand")])
1309 (label_ref (match_operand 3))
1310 (pc)))
1311 (clobber (reg:SI T_REG))]
1312 "TARGET_SH2 && can_create_pseudo_p ()"
1313 {
1314 if (!expand_cbranchdi4 (operands, GET_CODE (operands[0])))
1315 FAIL;
1316 DONE;
1317 })
1319 ;; -------------------------------------------------------------------------
1320 ;; DImode signed integer comparisons
1321 ;; -------------------------------------------------------------------------
1323 (define_insn ""
1324 [(set (reg:SI T_REG)
1325 (eq:SI (and:DI (match_operand:DI 0 "arith_reg_operand" "r")
1326 (match_operand:DI 1 "arith_operand" "r"))
1327 (const_int 0)))]
1328 "TARGET_SH1"
1329 {
1330 return output_branchy_insn (EQ, "tst\t%S1,%S0;bf\t%l9;tst\t%R1,%R0",
1331 insn, operands);
1332 }
1333 [(set_attr "length" "6")
1334 (set_attr "type" "arith3b")])
1336 (define_insn "cmpeqdi_t"
1337 [(set (reg:SI T_REG)
1338 (eq:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1339 (match_operand:DI 1 "arith_reg_or_0_operand" "N,r")))]
1340 "TARGET_SH1"
1341 {
1342 static const char* alt[] =
1343 {
1344 "tst %S0,%S0" "\n"
1345 " bf 0f" "\n"
1346 " tst %R0,%R0" "\n"
1347 "0:",
1349 "cmp/eq %S1,%S0" "\n"
1350 " bf 0f" "\n"
1351 " cmp/eq %R1,%R0" "\n"
1352 "0:"
1353 };
1354 return alt[which_alternative];
1355 }
1356 [(set_attr "length" "6")
1357 (set_attr "type" "arith3b")])
1359 (define_split
1360 [(set (reg:SI T_REG)
1361 (eq:SI (match_operand:DI 0 "arith_reg_operand" "")
1362 (match_operand:DI 1 "arith_reg_or_0_operand" "")))]
1363 ;; If we applied this split when not optimizing, it would only be
1364 ;; applied during the machine-dependent reorg, when no new basic blocks
1365 ;; may be created.
1366 "TARGET_SH1 && reload_completed && optimize"
1367 [(set (reg:SI T_REG) (eq:SI (match_dup 2) (match_dup 3)))
1368 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
1369 (label_ref (match_dup 6))
1370 (pc)))
1371 (set (reg:SI T_REG) (eq:SI (match_dup 4) (match_dup 5)))
1372 (match_dup 6)]
1373 {
1374 operands[2] = gen_highpart (SImode, operands[0]);
1375 operands[3] = operands[1] == const0_rtx
1376 ? const0_rtx
1377 : gen_highpart (SImode, operands[1]);
1378 operands[4] = gen_lowpart (SImode, operands[0]);
1379 operands[5] = gen_lowpart (SImode, operands[1]);
1380 operands[6] = gen_label_rtx ();
1381 })
1383 (define_insn "cmpgtdi_t"
1384 [(set (reg:SI T_REG)
1385 (gt:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1386 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
1387 "TARGET_SH2"
1388 {
1389 static const char* alt[] =
1390 {
1391 "cmp/eq %S1,%S0" "\n"
1392 " bf{.|/}s 0f" "\n"
1393 " cmp/gt %S1,%S0" "\n"
1394 " cmp/hi %R1,%R0" "\n"
1395 "0:",
1397 "tst %S0,%S0" "\n"
1398 " bf{.|/}s 0f" "\n"
1399 " cmp/pl %S0" "\n"
1400 " cmp/hi %S0,%R0" "\n"
1401 "0:"
1402 };
1403 return alt[which_alternative];
1404 }
1405 [(set_attr "length" "8")
1406 (set_attr "type" "arith3")])
1408 (define_insn "cmpgedi_t"
1409 [(set (reg:SI T_REG)
1410 (ge:SI (match_operand:DI 0 "arith_reg_operand" "r,r")
1411 (match_operand:DI 1 "arith_reg_or_0_operand" "r,N")))]
1412 "TARGET_SH2"
1413 {
1414 static const char* alt[] =
1415 {
1416 "cmp/eq %S1,%S0" "\n"
1417 " bf{.|/}s 0f" "\n"
1418 " cmp/ge %S1,%S0" "\n"
1419 " cmp/hs %R1,%R0" "\n"
1420 "0:",
1422 "cmp/pz %S0"
1423 };
1424 return alt[which_alternative];
1425 }
1426 [(set_attr "length" "8,2")
1427 (set_attr "type" "arith3,mt_group")])
1428 \f
1429 ;; -------------------------------------------------------------------------
1430 ;; DImode unsigned integer comparisons
1431 ;; -------------------------------------------------------------------------
1433 (define_insn "cmpgeudi_t"
1434 [(set (reg:SI T_REG)
1435 (geu:SI (match_operand:DI 0 "arith_reg_operand" "r")
1436 (match_operand:DI 1 "arith_reg_operand" "r")))]
1437 "TARGET_SH2"
1438 {
1439 return "cmp/eq %S1,%S0" "\n"
1440 " bf{.|/}s 0f" "\n"
1441 " cmp/hs %S1,%S0" "\n"
1442 " cmp/hs %R1,%R0" "\n"
1443 "0:";
1444 }
1445 [(set_attr "length" "8")
1446 (set_attr "type" "arith3")])
1448 (define_insn "cmpgtudi_t"
1449 [(set (reg:SI T_REG)
1450 (gtu:SI (match_operand:DI 0 "arith_reg_operand" "r")
1451 (match_operand:DI 1 "arith_reg_operand" "r")))]
1452 "TARGET_SH2"
1453 {
1454 return "cmp/eq %S1,%S0" "\n"
1455 " bf{.|/}s 0f" "\n"
1456 " cmp/hi %S1,%S0" "\n"
1457 " cmp/hi %R1,%R0" "\n"
1458 "0:";
1459 }
1460 [(set_attr "length" "8")
1461 (set_attr "type" "arith3")])
1463 ;; -------------------------------------------------------------------------
1464 ;; Conditional move instructions
1465 ;; -------------------------------------------------------------------------
1467 (define_insn "*movsicc_t_false"
1468 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1469 (if_then_else (eq (reg:SI T_REG) (const_int 0))
1470 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1471 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1472 "TARGET_PRETEND_CMOVE
1473 && (arith_reg_operand (operands[1], SImode)
1474 || (immediate_operand (operands[1], SImode)
1475 && satisfies_constraint_I08 (operands[1])))"
1476 {
1477 return "bt 0f" "\n"
1478 " mov %1,%0" "\n"
1479 "0:";
1480 }
1481 [(set_attr "type" "mt_group,arith") ;; poor approximation
1482 (set_attr "length" "4")])
1484 (define_insn "*movsicc_t_true"
1485 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1486 (if_then_else (ne (reg:SI T_REG) (const_int 0))
1487 (match_operand:SI 1 "general_movsrc_operand" "r,I08")
1488 (match_operand:SI 2 "arith_reg_operand" "0,0")))]
1489 "TARGET_PRETEND_CMOVE
1490 && (arith_reg_operand (operands[1], SImode)
1491 || (immediate_operand (operands[1], SImode)
1492 && satisfies_constraint_I08 (operands[1])))"
1493 {
1494 return "bf 0f" "\n"
1495 " mov %1,%0" "\n"
1496 "0:";
1497 }
1498 [(set_attr "type" "mt_group,arith") ;; poor approximation
1499 (set_attr "length" "4")])
1501 (define_expand "movsicc"
1502 [(set (match_operand:SI 0 "arith_reg_dest" "")
1503 (if_then_else:SI (match_operand 1 "comparison_operator" "")
1504 (match_operand:SI 2 "arith_reg_or_0_operand" "")
1505 (match_operand:SI 3 "arith_reg_operand" "")))]
1506 "TARGET_PRETEND_CMOVE"
1507 {
1508 rtx_code code = GET_CODE (operands[1]);
1509 rtx_code new_code = code;
1510 rtx op0 = XEXP (operands[1], 0);
1511 rtx op1 = XEXP (operands[1], 1);
1513 if (! currently_expanding_to_rtl)
1514 FAIL;
1516 switch (code)
1517 {
1518 case LT: case LE: case LEU: case LTU:
1519 if (GET_MODE_CLASS (GET_MODE (op0)) != MODE_INT)
1520 break;
1521 /* FALLTHRU */
1522 case NE:
1523 new_code = reverse_condition (code);
1524 break;
1525 case EQ: case GT: case GE: case GEU: case GTU:
1526 break;
1527 default:
1528 FAIL;
1529 }
1531 sh_emit_scc_to_t (new_code, op0, op1);
1532 operands[1] = gen_rtx_fmt_ee (new_code == code ? NE : EQ, VOIDmode,
1533 gen_rtx_REG (SImode, T_REG), const0_rtx);
1534 })
1536 ;; -------------------------------------------------------------------------
1537 ;; Addition instructions
1538 ;; -------------------------------------------------------------------------
1540 (define_insn_and_split "adddi3"
1541 [(set (match_operand:DI 0 "arith_reg_dest")
1542 (plus:DI (match_operand:DI 1 "arith_reg_operand")
1543 (match_operand:DI 2 "arith_reg_operand")))
1544 (clobber (reg:SI T_REG))]
1545 "TARGET_SH1"
1546 "#"
1547 "&& can_create_pseudo_p ()"
1548 [(const_int 0)]
1549 {
1550 emit_insn (gen_clrt ());
1551 emit_insn (gen_addc (gen_lowpart (SImode, operands[0]),
1552 gen_lowpart (SImode, operands[1]),
1553 gen_lowpart (SImode, operands[2])));
1554 emit_insn (gen_addc (gen_highpart (SImode, operands[0]),
1555 gen_highpart (SImode, operands[1]),
1556 gen_highpart (SImode, operands[2])));
1557 DONE;
1558 })
1560 (define_insn "addc"
1561 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1562 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0")
1563 (match_operand:SI 2 "arith_reg_operand" "r"))
1564 (reg:SI T_REG)))
1565 (set (reg:SI T_REG)
1566 (ltu:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 1)))]
1567 "TARGET_SH1"
1568 "addc %2,%0"
1569 [(set_attr "type" "arith")])
1571 ;; A simplified version of the addc insn, where the exact value of the
1572 ;; T bit doesn't matter. This is easier for combine to pick up.
1573 ;; We allow a reg or 0 for one of the operands in order to be able to
1574 ;; do 'reg + T' sequences.
1575 (define_insn_and_split "*addc"
1576 [(set (match_operand:SI 0 "arith_reg_dest")
1577 (plus:SI (plus:SI (match_operand:SI 1 "arith_reg_operand")
1578 (match_operand:SI 2 "arith_reg_or_0_operand"))
1579 (match_operand 3 "treg_set_expr")))
1580 (clobber (reg:SI T_REG))]
1581 "TARGET_SH1 && can_create_pseudo_p ()"
1582 "#"
1583 "&& 1"
1584 [(const_int 0)]
1585 {
1586 sh_treg_insns ti = sh_split_treg_set_expr (operands[3], curr_insn);
1587 if (ti.has_trailing_nott ())
1588 {
1589 if (operands[2] == const0_rtx)
1590 {
1591 /* op1 + 0 + (1 - T) = op1 + 1 - T = op1 - (-1) - T */
1592 remove_insn (ti.trailing_nott ());
1593 emit_insn (gen_subc (operands[0], operands[1],
1594 force_reg (SImode, GEN_INT (-1))));
1595 DONE;
1596 }
1597 else if (!TARGET_SH2A)
1598 {
1599 /* op1 + op2 + (1 - T) = op1 - (0 - op2 - 1) - T = op1 - ~op2 - T
1600 On SH2A keep the nott insn, because nott-addc sequence doesn't
1601 mutate the inputs. */
1602 remove_insn (ti.trailing_nott ());
1603 rtx tmp = gen_reg_rtx (SImode);
1604 emit_insn (gen_one_cmplsi2 (tmp, operands[2]));
1605 emit_insn (gen_subc (operands[0], operands[1], tmp));
1606 DONE;
1607 }
1608 }
1610 emit_insn (gen_addc (operands[0], operands[1],
1611 force_reg (SImode, operands[2])));
1612 DONE;
1613 })
1615 (define_insn_and_split "*addc"
1616 [(set (match_operand:SI 0 "arith_reg_dest")
1617 (plus:SI (plus:SI (match_operand 1 "treg_set_expr")
1618 (match_operand:SI 2 "arith_reg_operand"))
1619 (match_operand:SI 3 "arith_reg_operand")))
1620 (clobber (reg:SI T_REG))]
1621 "TARGET_SH1 && can_create_pseudo_p ()"
1622 "#"
1623 "&& 1"
1624 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 3))
1625 (match_dup 1)))
1626 (clobber (reg:SI T_REG))])])
1628 (define_insn_and_split "*addc"
1629 [(set (match_operand:SI 0 "arith_reg_dest")
1630 (plus:SI (match_operand 1 "treg_set_expr")
1631 (plus:SI (match_operand:SI 2 "arith_reg_operand")
1632 (match_operand:SI 3 "arith_reg_operand"))))
1633 (clobber (reg:SI T_REG))]
1634 "TARGET_SH1 && can_create_pseudo_p ()"
1635 "#"
1636 "&& 1"
1637 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 3))
1638 (match_dup 1)))
1639 (clobber (reg:SI T_REG))])])
1641 ;; Sometimes combine will try to do 'reg + (0-reg) + 1' if the *addc pattern
1642 ;; matched. Split this up into a simple sub add sequence, as this will save
1643 ;; us one sett insn.
1644 (define_insn_and_split "*minus_plus_one"
1645 [(set (match_operand:SI 0 "arith_reg_dest" "")
1646 (plus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
1647 (match_operand:SI 2 "arith_reg_operand" ""))
1648 (const_int 1)))]
1649 "TARGET_SH1"
1650 "#"
1651 "&& 1"
1652 [(set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))
1653 (set (match_dup 0) (plus:SI (match_dup 0) (const_int 1)))])
1656 ;; The tree optimiziers canonicalize
1657 ;; reg + (reg & 1)
1658 ;; into
1659 ;; (reg + 1) & -2
1660 ;;
1661 ;; On SH2A an add-bclr sequence will be used to handle this.
1662 ;; On non-SH2A re-emit the add-and sequence to improve register utilization.
1663 (define_insn_and_split "*round_int_even"
1664 [(set (match_operand:SI 0 "arith_reg_dest")
1665 (and:SI (plus:SI (match_operand:SI 1 "arith_reg_operand")
1666 (const_int 1))
1667 (const_int -2)))]
1668 "TARGET_SH1 && !TARGET_SH2A && can_create_pseudo_p ()
1669 && !reg_overlap_mentioned_p (operands[0], operands[1])"
1670 "#"
1671 "&& 1"
1672 [(set (match_dup 0) (const_int -2))
1673 (set (match_dup 2) (plus:SI (match_dup 1) (const_int 1)))
1674 (set (match_dup 0) (and:SI (match_dup 0) (match_dup 2)))]
1675 {
1676 operands[2] = gen_reg_rtx (SImode);
1677 })
1679 ;; If the *round_int_even pattern is combined with another plus,
1680 ;; convert it into an addc pattern to emit an shlr-addc sequence.
1681 ;; This split is taken by combine on non-SH2A and SH2A.
1682 (define_split
1683 [(set (match_operand:SI 0 "arith_reg_dest")
1684 (plus:SI (and:SI (plus:SI (match_operand:SI 1 "arith_reg_operand")
1685 (const_int 1))
1686 (const_int -2))
1687 (match_operand:SI 2 "arith_reg_operand")))]
1688 "TARGET_SH1 && can_create_pseudo_p ()"
1689 [(parallel [(set (match_dup 0)
1690 (plus:SI (plus:SI (match_dup 1) (match_dup 2))
1691 (and:SI (match_dup 1) (const_int 1))))
1692 (clobber (reg:SI T_REG))])])
1694 ;; Split 'reg + T' into 'reg + 0 + T' to utilize the addc insn.
1695 ;; If the 0 constant can be CSE-ed, this becomes a one instruction
1696 ;; operation, as opposed to sequences such as
1697 ;; movt r2
1698 ;; add r2,r3
1699 ;;
1700 ;; Even if the constant is not CSE-ed, a sequence such as
1701 ;; mov #0,r2
1702 ;; addc r2,r3
1703 ;; can be scheduled much better since the load of the constant can be
1704 ;; done earlier, before any comparison insns that store the result in
1705 ;; the T bit.
1706 ;; However, avoid things like 'reg + 1', which would expand into a
1707 ;; 3 insn sequence, instead of add #imm8.
1708 (define_insn_and_split "*addc_t_r"
1709 [(set (match_operand:SI 0 "arith_reg_dest")
1710 (plus:SI (match_operand 1 "treg_set_expr_not_const01")
1711 (match_operand:SI 2 "arith_reg_operand")))
1712 (clobber (reg:SI T_REG))]
1713 "TARGET_SH1 && can_create_pseudo_p ()"
1714 "#"
1715 "&& 1"
1716 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (const_int 0))
1717 (match_dup 1)))
1718 (clobber (reg:SI T_REG))])])
1720 (define_insn_and_split "*addc_r_t"
1721 [(set (match_operand:SI 0 "arith_reg_dest")
1722 (plus:SI (match_operand:SI 1 "arith_reg_operand")
1723 (match_operand 2 "treg_set_expr_not_const01")))
1724 (clobber (reg:SI T_REG))]
1725 "TARGET_SH1 && can_create_pseudo_p ()"
1726 "#"
1727 "&& 1"
1728 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (const_int 0))
1729 (match_dup 2)))
1730 (clobber (reg:SI T_REG))])])
1732 ;; Convert '2 * reg + T' into 'reg + reg + T'.
1733 (define_insn_and_split "*addc_2r_t"
1734 [(set (match_operand:SI 0 "arith_reg_dest")
1735 (plus:SI (match_operand 1 "treg_set_expr")
1736 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
1737 (const_int 1))))
1738 (clobber (reg:SI T_REG))]
1739 "TARGET_SH1 && can_create_pseudo_p ()"
1740 "#"
1741 "&& 1"
1742 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 2))
1743 (match_dup 1)))
1744 (clobber (reg:SI T_REG))])])
1746 (define_insn_and_split "*addc_2r_t"
1747 [(set (match_operand:SI 0 "arith_reg_dest")
1748 (plus:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
1749 (const_int 1))
1750 (match_operand 2 "treg_set_expr")))
1751 (clobber (reg:SI T_REG))]
1752 "TARGET_SH1 && can_create_pseudo_p ()"
1753 "#"
1754 "&& 1"
1755 [(parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 1) (match_dup 1))
1756 (match_dup 2)))
1757 (clobber (reg:SI T_REG))])])
1759 ;; Convert '(op2 + T) - op3' into 'op2 + (-op3) + T'
1760 (define_insn_and_split "*addc_negreg_t"
1761 [(set (match_operand:SI 0 "arith_reg_dest")
1762 (minus:SI (plus:SI (match_operand 1 "treg_set_expr")
1763 (match_operand:SI 2 "arith_reg_operand"))
1764 (match_operand:SI 3 "arith_reg_operand")))
1765 (clobber (reg:SI T_REG))]
1766 "TARGET_SH1 && can_create_pseudo_p ()"
1767 "#"
1768 "&& 1"
1769 [(set (match_dup 4) (neg:SI (match_dup 3)))
1770 (parallel [(set (match_dup 0) (plus:SI (plus:SI (match_dup 2) (match_dup 4))
1771 (match_dup 1)))
1772 (clobber (reg:SI T_REG))])]
1773 {
1774 operands[4] = gen_reg_rtx (SImode);
1775 })
1777 (define_expand "addsi3"
1778 [(set (match_operand:SI 0 "arith_reg_dest")
1779 (plus:SI (match_operand:SI 1 "arith_reg_operand")
1780 (match_operand:SI 2 "arith_or_int_operand")))]
1781 ""
1782 {
1783 if (!arith_operand (operands[2], SImode))
1784 {
1785 if (!sh_lra_p () || reg_overlap_mentioned_p (operands[0], operands[1]))
1786 {
1787 emit_insn (gen_addsi3_scr (operands[0], operands[1], operands[2]));
1788 DONE;
1789 }
1790 }
1791 })
1793 ;; The *addsi3_compact is made an insn_and_split and accepts actually
1794 ;; impossible constraints to make LRA's register elimination work well on SH.
1795 ;; The problem is that LRA expects something like
1796 ;; (set rA (plus rB (const_int N)))
1797 ;; to work. We can do that, but we have to split out an additional reg-reg
1798 ;; copy or constant load before the actual add insn.
1799 ;; Use u constraint for that case to avoid the invalid value in the stack
1800 ;; pointer.
1801 ;; This also results in better code when LRA is not used. However, we have
1802 ;; to use different sets of patterns and the order of these patterns is
1803 ;; important.
1804 ;; In some cases the constant zero might end up in operands[2] of the
1805 ;; patterns. We have to accept that and convert it into a reg-reg move.
1806 (define_insn_and_split "*addsi3_compact_lra"
1807 [(set (match_operand:SI 0 "arith_reg_dest" "=r,&u")
1808 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0,r")
1809 (match_operand:SI 2 "arith_or_int_operand" "rI08,rn")))]
1810 "TARGET_SH1 && sh_lra_p ()
1811 && (! reg_overlap_mentioned_p (operands[0], operands[1])
1812 || arith_operand (operands[2], SImode))"
1813 "@
1814 add %2,%0
1815 #"
1816 "&& reload_completed
1817 && ! reg_overlap_mentioned_p (operands[0], operands[1])"
1818 [(set (match_dup 0) (match_dup 2))
1819 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
1820 {
1821 /* Prefer 'mov r0,r1; add #imm8,r1' over 'mov #imm8,r1; add r0,r1' */
1822 if (satisfies_constraint_I08 (operands[2]))
1823 std::swap (operands[1], operands[2]);
1824 }
1825 [(set_attr "type" "arith")])
1827 (define_insn_and_split "addsi3_scr"
1828 [(set (match_operand:SI 0 "arith_reg_dest" "=r,&u,&u")
1829 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0,r,r")
1830 (match_operand:SI 2 "arith_or_int_operand" "rI08,r,n")))
1831 (clobber (match_scratch:SI 3 "=X,X,&u"))]
1832 "TARGET_SH1"
1833 "@
1834 add %2,%0
1835 #
1836 #"
1837 "&& reload_completed"
1838 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1839 {
1840 if (operands[2] == const0_rtx)
1841 {
1842 emit_move_insn (operands[0], operands[1]);
1843 DONE;
1844 }
1846 if (CONST_INT_P (operands[2]) && !satisfies_constraint_I08 (operands[2]))
1847 {
1848 if (reg_overlap_mentioned_p (operands[0], operands[1]))
1849 {
1850 emit_move_insn (operands[3], operands[2]);
1851 emit_move_insn (operands[0], operands[1]);
1852 operands[2] = operands[3];
1853 }
1854 else
1855 {
1856 emit_move_insn (operands[0], operands[2]);
1857 operands[2] = operands[1];
1858 }
1859 }
1860 else if (!reg_overlap_mentioned_p (operands[0], operands[1]))
1861 {
1862 if (!reg_overlap_mentioned_p (operands[0], operands[2]))
1863 emit_move_insn (operands[0], operands[1]);
1864 else
1865 operands[2] = operands[1];
1866 }
1867 }
1868 [(set_attr "type" "arith")])
1870 ;; Old reload might generate add insns directly (not through the expander) for
1871 ;; address register calculations when reloading, in which case it won't try
1872 ;; the addsi_scr pattern. Because reload will sometimes try to validate
1873 ;; the generated insns and their constraints, this pattern must be
1874 ;; recognizable during and after reload. However, when reload generates
1875 ;; address register calculations for the stack pointer, we don't allow this
1876 ;; pattern. This will make reload prefer using indexed @(reg + reg) address
1877 ;; modes when the displacement of a @(disp + reg) doesn't fit.
1878 (define_insn_and_split "*addsi3"
1879 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1880 (plus:SI (match_operand:SI 1 "arith_reg_operand" "r")
1881 (match_operand:SI 2 "arith_or_int_operand" "rn")))]
1882 "TARGET_SH1 && !sh_lra_p ()
1883 && (reload_completed || reload_in_progress)
1884 && !reg_overlap_mentioned_p (operands[0], operands[1])
1885 && (!reload_in_progress
1886 || ((!REG_P (operands[1]) || REGNO (operands[1]) != SP_REG)
1887 && (!REG_P (operands[2]) || REGNO (operands[2]) != SP_REG)))"
1888 "#"
1889 "&& 1"
1890 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
1891 {
1892 if (operands[2] == const0_rtx)
1893 {
1894 emit_move_insn (operands[0], operands[1]);
1895 DONE;
1896 }
1898 if (CONST_INT_P (operands[2]))
1899 {
1900 if (satisfies_constraint_I08 (operands[2]))
1901 emit_move_insn (operands[0], operands[1]);
1902 else
1903 {
1904 emit_move_insn (operands[0], operands[2]);
1905 operands[2] = operands[1];
1906 }
1907 }
1908 else if (!reg_overlap_mentioned_p (operands[0], operands[2]))
1909 emit_move_insn (operands[0], operands[1]);
1910 else
1911 operands[2] = operands[1];
1912 })
1914 (define_insn_and_split "*addsi3"
1915 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
1916 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%0,r")
1917 (match_operand:SI 2 "arith_operand" "rI08,Z")))]
1918 "TARGET_SH1 && !sh_lra_p ()"
1919 "@
1920 add %2,%0
1921 #"
1922 "&& operands[2] == const0_rtx"
1923 [(set (match_dup 0) (match_dup 1))]
1924 {
1925 }
1926 [(set_attr "type" "arith")])
1928 ;; -------------------------------------------------------------------------
1929 ;; Subtraction instructions
1930 ;; -------------------------------------------------------------------------
1932 (define_insn_and_split "subdi3"
1933 [(set (match_operand:DI 0 "arith_reg_dest")
1934 (minus:DI (match_operand:DI 1 "arith_reg_operand")
1935 (match_operand:DI 2 "arith_reg_operand")))
1936 (clobber (reg:SI T_REG))]
1937 "TARGET_SH1"
1938 "#"
1939 "&& can_create_pseudo_p ()"
1940 [(const_int 0)]
1941 {
1942 emit_insn (gen_clrt ());
1943 emit_insn (gen_subc (gen_lowpart (SImode, operands[0]),
1944 gen_lowpart (SImode, operands[1]),
1945 gen_lowpart (SImode, operands[2])));
1946 emit_insn (gen_subc (gen_highpart (SImode, operands[0]),
1947 gen_highpart (SImode, operands[1]),
1948 gen_highpart (SImode, operands[2])));
1949 DONE;
1950 })
1952 (define_insn "subc"
1953 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
1954 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
1955 (match_operand:SI 2 "arith_reg_operand" "r"))
1956 (reg:SI T_REG)))
1957 (set (reg:SI T_REG)
1958 (gtu:SI (minus:SI (minus:SI (match_dup 1) (match_dup 2))
1959 (reg:SI T_REG))
1960 (match_dup 1)))]
1961 "TARGET_SH1"
1962 "subc %2,%0"
1963 [(set_attr "type" "arith")])
1965 ;; A simplified version of the subc insn, where the exact value of the
1966 ;; T bit doesn't matter. This is easier for combine to pick up.
1967 ;; We allow a reg or 0 for one of the operands in order to be able to
1968 ;; do 'reg - T' sequences. Reload will load the constant 0 into the reg
1969 ;; as needed.
1970 (define_insn_and_split "*subc"
1971 [(set (match_operand:SI 0 "arith_reg_dest")
1972 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand")
1973 (match_operand:SI 2 "arith_reg_or_0_operand"))
1974 (match_operand 3 "treg_set_expr")))
1975 (clobber (reg:SI T_REG))]
1976 "TARGET_SH1 && can_create_pseudo_p ()"
1977 "#"
1978 "&& 1"
1979 [(const_int 0)]
1980 {
1981 sh_treg_insns ti = sh_split_treg_set_expr (operands[3], curr_insn);
1982 if (ti.has_trailing_nott ())
1983 {
1984 if (operands[2] == const0_rtx)
1985 {
1986 /* op1 - (1 - T) = op1 - 1 + T = op1 + (-1) + T */
1987 remove_insn (ti.trailing_nott ());
1988 emit_insn (gen_addc (operands[0], operands[1],
1989 force_reg (SImode, GEN_INT (-1))));
1990 DONE;
1991 }
1992 else if (!TARGET_SH2A)
1993 {
1994 /* op1 - op2 - (1 - T) = op1 + (0 - op2 - 1) + T = op1 + ~op2 + T
1995 On SH2A keep the nott insn, because nott-subc sequence doesn't
1996 mutate the inputs. */
1997 remove_insn (ti.trailing_nott ());
1998 rtx tmp = gen_reg_rtx (SImode);
1999 emit_insn (gen_one_cmplsi2 (tmp, operands[2]));
2000 emit_insn (gen_addc (operands[0], operands[1], tmp));
2001 DONE;
2002 }
2003 }
2005 emit_insn (gen_subc (operands[0], operands[1],
2006 force_reg (SImode, operands[2])));
2007 DONE;
2008 })
2010 ;; Convert reg - T - reg = reg - reg - T
2011 (define_insn_and_split "*subc"
2012 [(set (match_operand:SI 0 "arith_reg_dest")
2013 (minus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand")
2014 (match_operand 2 "treg_set_expr"))
2015 (match_operand:SI 3 "arith_reg_operand")))
2016 (clobber (reg:SI T_REG))]
2017 "TARGET_SH1 && can_create_pseudo_p ()"
2018 "#"
2019 "&& 1"
2020 [(parallel [(set (match_dup 0)
2021 (minus:SI (minus:SI (match_dup 1) (match_dup 3))
2022 (match_dup 2)))
2023 (clobber (reg:SI T_REG))])])
2025 ;; Split reg - reg - 1 into a sett subc sequence, as it can be scheduled
2026 ;; better, if the sett insn can be done early.
2027 ;; Notice that combine turns 'a - b - 1' into 'a + (~b)'.
2028 (define_insn_and_split "*subc"
2029 [(set (match_operand:SI 0 "arith_reg_dest" "")
2030 (plus:SI (not:SI (match_operand:SI 1 "arith_reg_operand" ""))
2031 (match_operand:SI 2 "arith_reg_operand" "")))
2032 (clobber (reg:SI T_REG))]
2033 "TARGET_SH1 && can_create_pseudo_p ()"
2034 "#"
2035 "&& 1"
2036 [(parallel [(set (match_dup 0)
2037 (minus:SI (minus:SI (match_dup 2) (match_dup 1))
2038 (const_int 1)))
2039 (clobber (reg:SI T_REG))])])
2041 ;; Split 'reg - T' into 'reg - 0 - T' to utilize the subc insn.
2042 ;; If the 0 constant can be CSE-ed, this becomes a one instruction
2043 ;; operation, as opposed to sequences such as
2044 ;; movt r2
2045 ;; sub r2,r3
2046 ;;
2047 ;; Even if the constant is not CSE-ed, a sequence such as
2048 ;; mov #0,r2
2049 ;; subc r2,r3
2050 ;; can be scheduled much better since the load of the constant can be
2051 ;; done earlier, before any comparison insns that store the result in
2052 ;; the T bit.
2053 ;; However, avoid things like 'reg - 1', which would expand into a
2054 ;; 3 insn sequence, instead of add #imm8.
2055 (define_insn_and_split "*subc"
2056 [(set (match_operand:SI 0 "arith_reg_dest" "")
2057 (minus:SI (match_operand:SI 1 "arith_reg_operand" "")
2058 (match_operand 2 "treg_set_expr_not_const01")))
2059 (clobber (reg:SI T_REG))]
2060 "TARGET_SH1 && can_create_pseudo_p ()"
2061 "#"
2062 "&& 1"
2063 [(parallel [(set (match_dup 0)
2064 (minus:SI (minus:SI (match_dup 1) (const_int 0))
2065 (match_dup 2)))
2066 (clobber (reg:SI T_REG))])])
2068 ;; Convert
2069 ;; (1 - T) - op2 = 1 - op2 - T
2070 (define_insn_and_split "*subc_negt_reg"
2071 [(set (match_operand:SI 0 "arith_reg_dest")
2072 (minus:SI (match_operand 1 "treg_set_expr_not_const01")
2073 (match_operand:SI 2 "arith_reg_operand")))
2074 (clobber (reg:SI T_REG))]
2075 "TARGET_SH1 && can_create_pseudo_p ()"
2076 "#"
2077 "&& 1"
2078 [(const_int 0)]
2079 {
2080 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
2081 if (ti.remove_trailing_nott ())
2082 {
2083 /* (1 - T) - op2 = 1 - op2 - T */
2084 emit_insn (gen_subc (operands[0],
2085 force_reg (SImode, GEN_INT (1)), operands[2]));
2086 }
2087 else
2088 {
2089 /* T - op2: use movt,sub sequence. */
2090 rtx tmp = gen_reg_rtx (SImode);
2091 emit_insn (gen_movt (tmp, get_t_reg_rtx ()));
2092 emit_insn (gen_subsi3 (operands[0], tmp, operands[2]));
2093 }
2094 DONE;
2095 })
2097 ;; Convert
2098 ;; op1 - (1 - T) + op3 = op1 - 1 + T + op3
2099 ;; (op1 - T) + op3 = op1 - (-op3) - T
2100 (define_insn_and_split "*subc_negreg_t"
2101 [(set (match_operand:SI 0 "arith_reg_dest")
2102 (plus:SI (minus:SI (match_operand:SI 1 "arith_reg_operand")
2103 (match_operand 2 "treg_set_expr"))
2104 (match_operand:SI 3 "arith_reg_operand")))
2105 (clobber (reg:SI T_REG))]
2106 "TARGET_SH1 && can_create_pseudo_p ()"
2107 "#"
2108 "&& 1"
2109 [(const_int 0)]
2110 {
2111 sh_treg_insns ti = sh_split_treg_set_expr (operands[2], curr_insn);
2112 if (ti.remove_trailing_nott ())
2113 {
2114 /* op1 - (1 - T) + op3 = (op1 - 1) + op3 + T */
2115 rtx tmp = gen_reg_rtx (SImode);
2116 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (-1)));
2117 emit_insn (gen_addc (operands[0], tmp, operands[3]));
2118 }
2119 else
2120 {
2121 /* (op1 - T) + op3' = 'op1 - (-op3) - T */
2122 rtx tmp = gen_reg_rtx (SImode);
2123 emit_insn (gen_negsi2 (tmp, operands[3]));
2124 emit_insn (gen_subc (operands[0], operands[1], tmp));
2125 }
2126 DONE;
2127 })
2129 (define_insn "*subsi3_internal"
2130 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2131 (minus:SI (match_operand:SI 1 "arith_reg_operand" "0")
2132 (match_operand:SI 2 "arith_reg_operand" "r")))]
2133 "TARGET_SH1"
2134 "sub %2,%0"
2135 [(set_attr "type" "arith")])
2137 ;; Convert
2138 ;; constant - reg
2139 ;; to
2140 ;; neg reg
2141 ;; add reg, #const
2142 ;; since this will sometimes save one instruction.
2143 ;; Otherwise we might get a sequence like
2144 ;; mov #const, rY
2145 ;; sub rY, rX
2146 ;; mov rX, rY
2147 ;; if the source and dest regs are the same.
2148 (define_expand "subsi3"
2149 [(set (match_operand:SI 0 "arith_reg_operand" "")
2150 (minus:SI (match_operand:SI 1 "arith_operand" "")
2151 (match_operand:SI 2 "arith_reg_operand" "")))]
2152 ""
2153 {
2154 if (CONST_INT_P (operands[1]))
2155 {
2156 emit_insn (gen_negsi2 (operands[0], operands[2]));
2157 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
2158 DONE;
2159 }
2160 })
2161 \f
2162 ;; -------------------------------------------------------------------------
2163 ;; Division instructions
2164 ;; -------------------------------------------------------------------------
2166 ;; We take advantage of the library routines which don't clobber as many
2167 ;; registers as a normal function call would.
2169 ;; The INSN_REFERENCES_ARE_DELAYED in sh.h is problematic because it
2170 ;; also has an effect on the register that holds the address of the sfunc.
2171 ;; To make this work, we have an extra dummy insn that shows the use
2172 ;; of this register for reorg.
2174 (define_insn "use_sfunc_addr"
2175 [(set (reg:SI PR_REG)
2176 (unspec:SI [(match_operand:SI 0 "register_operand" "r")] UNSPEC_SFUNC))]
2177 "TARGET_SH1 && check_use_sfunc_addr (insn, operands[0])"
2178 ""
2179 [(set_attr "length" "0")])
2181 (define_insn "udivsi3_sh2a"
2182 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2183 (udiv:SI (match_operand:SI 1 "arith_reg_operand" "0")
2184 (match_operand:SI 2 "arith_reg_operand" "z")))]
2185 "TARGET_SH2A"
2186 "divu %2,%1"
2187 [(set_attr "type" "arith")
2188 (set_attr "in_delay_slot" "no")])
2190 ;; We must use a pseudo-reg forced to reg 0 in the SET_DEST rather than
2191 ;; hard register 0. If we used hard register 0, then the next instruction
2192 ;; would be a move from hard register 0 to a pseudo-reg. If the pseudo-reg
2193 ;; gets allocated to a stack slot that needs its address reloaded, then
2194 ;; there is nothing to prevent reload from using r0 to reload the address.
2195 ;; This reload would clobber the value in r0 we are trying to store.
2196 ;; If we let reload allocate r0, then this problem can never happen.
2197 (define_insn "udivsi3_i1"
2198 [(set (match_operand:SI 0 "register_operand" "=z,z")
2199 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2200 (clobber (reg:SI T_REG))
2201 (clobber (reg:SI PR_REG))
2202 (clobber (reg:SI R1_REG))
2203 (clobber (reg:SI R4_REG))
2204 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2205 (use (match_operand 2 "" "Z,Ccl"))]
2206 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
2207 "@
2208 jsr @%1%#
2209 bsrf %1\n%O2:%#"
2210 [(set_attr "type" "sfunc")
2211 (set_attr "needs_delay_slot" "yes")])
2213 (define_insn "udivsi3_i4"
2214 [(set (match_operand:SI 0 "register_operand" "=y,y")
2215 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2216 (clobber (reg:SI T_REG))
2217 (clobber (reg:SI PR_REG))
2218 (clobber (reg:DF DR0_REG))
2219 (clobber (reg:DF DR2_REG))
2220 (clobber (reg:DF DR4_REG))
2221 (clobber (reg:SI R0_REG))
2222 (clobber (reg:SI R1_REG))
2223 (clobber (reg:SI R4_REG))
2224 (clobber (reg:SI R5_REG))
2225 (clobber (reg:SI FPSCR_STAT_REG))
2226 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2227 (use (match_operand 2 "" "Z,Ccl"))
2228 (use (reg:SI FPSCR_MODES_REG))]
2229 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
2230 "@
2231 jsr @%1%#
2232 bsrf %1\n%O2:%#"
2233 [(set_attr "type" "sfunc")
2234 (set_attr "fp_mode" "double")
2235 (set_attr "needs_delay_slot" "yes")])
2237 (define_insn "udivsi3_i4_single"
2238 [(set (match_operand:SI 0 "register_operand" "=y,y")
2239 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2240 (clobber (reg:SI T_REG))
2241 (clobber (reg:SI PR_REG))
2242 (clobber (reg:DF DR0_REG))
2243 (clobber (reg:DF DR2_REG))
2244 (clobber (reg:DF DR4_REG))
2245 (clobber (reg:SI R0_REG))
2246 (clobber (reg:SI R1_REG))
2247 (clobber (reg:SI R4_REG))
2248 (clobber (reg:SI R5_REG))
2249 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2250 (use (match_operand 2 "" "Z,Ccl"))]
2251 "TARGET_FPU_ANY && TARGET_FPU_SINGLE"
2252 "@
2253 jsr @%1%#
2254 bsrf %1\n%O2:%#"
2255 [(set_attr "type" "sfunc")
2256 (set_attr "needs_delay_slot" "yes")])
2258 (define_insn "udivsi3_i4_int"
2259 [(set (match_operand:SI 0 "register_operand" "=z")
2260 (udiv:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2261 (clobber (reg:SI T_REG))
2262 (clobber (reg:SI R1_REG))
2263 (clobber (reg:SI PR_REG))
2264 (clobber (reg:SI MACH_REG))
2265 (clobber (reg:SI MACL_REG))
2266 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2267 "TARGET_SH1"
2268 "jsr @%1%#"
2269 [(set_attr "type" "sfunc")
2270 (set_attr "needs_delay_slot" "yes")])
2273 (define_expand "udivsi3"
2274 [(set (match_operand:SI 0 "register_operand")
2275 (udiv:SI (match_operand:SI 1 "general_operand")
2276 (match_operand:SI 2 "general_operand")))]
2277 ""
2278 {
2279 rtx last;
2280 rtx func_ptr = gen_reg_rtx (Pmode);
2282 /* Emit the move of the address to a pseudo outside of the libcall. */
2283 if (TARGET_DIVIDE_CALL_TABLE)
2284 {
2285 /* libgcc2:__udivmoddi4 is not supposed to use an actual division, since
2286 that causes problems when the divide code is supposed to come from a
2287 separate library. Division by zero is undefined, so dividing 1 can be
2288 implemented by comparing with the divisor. */
2289 if (operands[1] == const1_rtx && currently_expanding_to_rtl)
2290 {
2291 rtx test = gen_rtx_GEU (VOIDmode, operands[1], operands[2]);
2292 emit_insn (gen_cstoresi4 (operands[0], test,
2293 operands[1], operands[2]));
2294 DONE;
2295 }
2296 else if (operands[2] == const0_rtx)
2297 {
2298 emit_move_insn (operands[0], operands[2]);
2299 DONE;
2300 }
2301 function_symbol (func_ptr, "__udivsi3_i4i", SFUNC_GOT);
2302 last = gen_udivsi3_i4_int (operands[0], func_ptr);
2303 }
2304 else if (TARGET_DIVIDE_CALL_FP)
2305 {
2306 rtx lab = function_symbol (func_ptr, "__udivsi3_i4", SFUNC_STATIC).lab;
2307 if (TARGET_FPU_SINGLE)
2308 last = gen_udivsi3_i4_single (operands[0], func_ptr, lab);
2309 else
2310 last = gen_udivsi3_i4 (operands[0], func_ptr, lab);
2311 }
2312 else if (TARGET_SH2A)
2313 {
2314 operands[1] = force_reg (SImode, operands[1]);
2315 operands[2] = force_reg (SImode, operands[2]);
2316 emit_insn (gen_udivsi3_sh2a (operands[0], operands[1], operands[2]));
2317 DONE;
2318 }
2319 else
2320 {
2321 rtx lab = function_symbol (func_ptr, "__udivsi3", SFUNC_STATIC).lab;
2322 last = gen_udivsi3_i1 (operands[0], func_ptr, lab);
2323 }
2324 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2325 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
2326 emit_insn (last);
2327 DONE;
2328 })
2330 (define_insn "divsi3_sh2a"
2331 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2332 (div:SI (match_operand:SI 1 "arith_reg_operand" "0")
2333 (match_operand:SI 2 "arith_reg_operand" "z")))]
2334 "TARGET_SH2A"
2335 "divs %2,%1"
2336 [(set_attr "type" "arith")
2337 (set_attr "in_delay_slot" "no")])
2339 (define_insn "divsi3_i1"
2340 [(set (match_operand:SI 0 "register_operand" "=z")
2341 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2342 (clobber (reg:SI T_REG))
2343 (clobber (reg:SI PR_REG))
2344 (clobber (reg:SI R1_REG))
2345 (clobber (reg:SI R2_REG))
2346 (clobber (reg:SI R3_REG))
2347 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2348 "TARGET_SH1 && TARGET_DIVIDE_CALL_DIV1"
2349 "jsr @%1%#"
2350 [(set_attr "type" "sfunc")
2351 (set_attr "needs_delay_slot" "yes")])
2353 (define_insn "divsi3_i4"
2354 [(set (match_operand:SI 0 "register_operand" "=y,y")
2355 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2356 (clobber (reg:SI PR_REG))
2357 (clobber (reg:DF DR0_REG))
2358 (clobber (reg:DF DR2_REG))
2359 (clobber (reg:SI FPSCR_STAT_REG))
2360 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2361 (use (match_operand 2 "" "Z,Ccl"))
2362 (use (reg:SI FPSCR_MODES_REG))]
2363 "TARGET_FPU_DOUBLE && ! TARGET_FPU_SINGLE"
2364 "@
2365 jsr @%1%#
2366 bsrf %1\n%O2:%#"
2367 [(set_attr "type" "sfunc")
2368 (set_attr "fp_mode" "double")
2369 (set_attr "needs_delay_slot" "yes")])
2371 (define_insn "divsi3_i4_single"
2372 [(set (match_operand:SI 0 "register_operand" "=y,y")
2373 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2374 (clobber (reg:SI PR_REG))
2375 (clobber (reg:DF DR0_REG))
2376 (clobber (reg:DF DR2_REG))
2377 (clobber (reg:SI R2_REG))
2378 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
2379 (use (match_operand 2 "" "Z,Ccl"))]
2380 "TARGET_FPU_ANY && TARGET_FPU_SINGLE"
2381 "@
2382 jsr @%1%#
2383 bsrf %1\n%O2:%#"
2384 [(set_attr "type" "sfunc")
2385 (set_attr "needs_delay_slot" "yes")])
2387 (define_insn "divsi3_i4_int"
2388 [(set (match_operand:SI 0 "register_operand" "=z")
2389 (div:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2390 (clobber (reg:SI T_REG))
2391 (clobber (reg:SI PR_REG))
2392 (clobber (reg:SI R1_REG))
2393 (clobber (reg:SI MACH_REG))
2394 (clobber (reg:SI MACL_REG))
2395 (use (match_operand:SI 1 "arith_reg_operand" "r"))]
2396 "TARGET_SH1"
2397 "jsr @%1%#"
2398 [(set_attr "type" "sfunc")
2399 (set_attr "needs_delay_slot" "yes")])
2401 (define_expand "divsi3"
2402 [(set (match_operand:SI 0 "register_operand")
2403 (div:SI (match_operand:SI 1 "general_operand")
2404 (match_operand:SI 2 "general_operand")))]
2405 ""
2406 {
2407 rtx last;
2408 rtx func_ptr = gen_reg_rtx (Pmode);
2410 /* Emit the move of the address to a pseudo outside of the libcall. */
2411 if (TARGET_DIVIDE_CALL_TABLE)
2412 {
2413 function_symbol (func_ptr, sh_divsi3_libfunc, SFUNC_GOT);
2414 last = gen_divsi3_i4_int (operands[0], func_ptr);
2415 }
2416 else if (TARGET_DIVIDE_CALL_FP)
2417 {
2418 rtx lab = function_symbol (func_ptr, sh_divsi3_libfunc,
2419 SFUNC_STATIC).lab;
2420 if (TARGET_FPU_SINGLE)
2421 last = gen_divsi3_i4_single (operands[0], func_ptr, lab);
2422 else
2423 last = gen_divsi3_i4 (operands[0], func_ptr, lab);
2424 }
2425 else if (TARGET_SH2A)
2426 {
2427 operands[1] = force_reg (SImode, operands[1]);
2428 operands[2] = force_reg (SImode, operands[2]);
2429 emit_insn (gen_divsi3_sh2a (operands[0], operands[1], operands[2]));
2430 DONE;
2431 }
2432 else
2433 {
2434 function_symbol (func_ptr, sh_divsi3_libfunc, SFUNC_GOT);
2435 last = gen_divsi3_i1 (operands[0], func_ptr);
2436 }
2437 emit_move_insn (gen_rtx_REG (SImode, 4), operands[1]);
2438 emit_move_insn (gen_rtx_REG (SImode, 5), operands[2]);
2439 emit_insn (last);
2440 DONE;
2441 })
2443 \f
2444 ;; -------------------------------------------------------------------------
2445 ;; Multiplication instructions
2446 ;; -------------------------------------------------------------------------
2448 (define_insn_and_split "mulhisi3"
2449 [(set (match_operand:SI 0 "arith_reg_dest")
2450 (mult:SI (sign_extend:SI (match_operand:HI 1 "arith_reg_operand"))
2451 (sign_extend:SI (match_operand:HI 2 "arith_reg_operand"))))
2452 (clobber (reg:SI MACL_REG))]
2453 "TARGET_SH1 && can_create_pseudo_p ()"
2454 "#"
2455 "&& 1"
2456 [(set (reg:SI MACL_REG) (mult:SI (sign_extend:SI (match_dup 1))
2457 (sign_extend:SI (match_dup 2))))
2458 (set (match_dup 0) (reg:SI MACL_REG))])
2460 (define_insn_and_split "umulhisi3"
2461 [(set (match_operand:SI 0 "arith_reg_dest")
2462 (mult:SI (zero_extend:SI (match_operand:HI 1 "arith_reg_operand"))
2463 (zero_extend:SI (match_operand:HI 2 "arith_reg_operand"))))
2464 (clobber (reg:SI MACL_REG))]
2465 "TARGET_SH1 && can_create_pseudo_p ()"
2466 "#"
2467 "&& 1"
2468 [(set (reg:SI MACL_REG) (mult:SI (zero_extend:SI (match_dup 1))
2469 (zero_extend:SI (match_dup 2))))
2470 (set (match_dup 0) (reg:SI MACL_REG))])
2472 (define_insn "umulhisi3_i"
2473 [(set (reg:SI MACL_REG)
2474 (mult:SI (zero_extend:SI
2475 (match_operand:HI 0 "arith_reg_operand" "r"))
2476 (zero_extend:SI
2477 (match_operand:HI 1 "arith_reg_operand" "r"))))]
2478 "TARGET_SH1"
2479 "mulu.w %1,%0"
2480 [(set_attr "type" "smpy")])
2482 (define_insn "mulhisi3_i"
2483 [(set (reg:SI MACL_REG)
2484 (mult:SI (sign_extend:SI
2485 (match_operand:HI 0 "arith_reg_operand" "r"))
2486 (sign_extend:SI
2487 (match_operand:HI 1 "arith_reg_operand" "r"))))]
2488 "TARGET_SH1"
2489 "muls.w %1,%0"
2490 [(set_attr "type" "smpy")])
2493 ;; mulsi3 on the SH2 can be done in one instruction, on the SH1 we generate
2494 ;; a call to a routine which clobbers known registers.
2495 (define_insn "mulsi3_call"
2496 [(set (match_operand:SI 1 "register_operand" "=z")
2497 (mult:SI (reg:SI R4_REG) (reg:SI R5_REG)))
2498 (clobber (reg:SI MACL_REG))
2499 (clobber (reg:SI T_REG))
2500 (clobber (reg:SI PR_REG))
2501 (clobber (reg:SI R3_REG))
2502 (clobber (reg:SI R2_REG))
2503 (clobber (reg:SI R1_REG))
2504 (use (match_operand:SI 0 "arith_reg_operand" "r"))]
2505 "TARGET_SH1"
2506 "jsr @%0%#"
2507 [(set_attr "type" "sfunc")
2508 (set_attr "needs_delay_slot" "yes")])
2510 (define_insn "mul_r"
2511 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2512 (mult:SI (match_operand:SI 1 "arith_reg_operand" "0")
2513 (match_operand:SI 2 "arith_reg_operand" "z")))]
2514 "TARGET_SH2A"
2515 "mulr %2,%0"
2516 [(set_attr "type" "dmpy")])
2518 (define_insn "mul_l"
2519 [(set (reg:SI MACL_REG)
2520 (mult:SI (match_operand:SI 0 "arith_reg_operand" "r")
2521 (match_operand:SI 1 "arith_reg_operand" "r")))]
2522 "TARGET_SH2"
2523 "mul.l %1,%0"
2524 [(set_attr "type" "dmpy")])
2526 (define_insn_and_split "mulsi3_i"
2527 [(set (match_operand:SI 0 "arith_reg_dest")
2528 (mult:SI (match_operand:SI 1 "arith_reg_operand")
2529 (match_operand:SI 2 "arith_reg_operand")))
2530 (clobber (reg:SI MACL_REG))]
2531 "TARGET_SH2 && can_create_pseudo_p ()"
2532 "#"
2533 "&& 1"
2534 [(set (reg:SI MACL_REG) (mult:SI (match_dup 1) (match_dup 2)))
2535 (set (match_dup 0) (reg:SI MACL_REG))])
2537 (define_expand "mulsi3"
2538 [(set (match_operand:SI 0 "arith_reg_dest")
2539 (mult:SI (match_operand:SI 1 "arith_reg_operand")
2540 (match_operand:SI 2 "arith_reg_operand")))]
2541 "TARGET_SH1"
2542 {
2543 if (!TARGET_SH2)
2544 {
2545 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
2546 emit_move_insn (gen_rtx_REG (SImode, R5_REG), operands[2]);
2548 rtx sym = function_symbol (NULL, "__mulsi3", SFUNC_STATIC).sym;
2550 emit_insn (gen_mulsi3_call (force_reg (SImode, sym), operands[0]));
2551 }
2552 else
2553 {
2554 /* FIXME: For some reason, expanding the mul_l insn and the macl store
2555 insn early gives slightly better code. In particular it prevents
2556 the decrement-test loop type to be used in some cases which saves
2557 one multiplication in the loop setup code.
2559 emit_insn (gen_mulsi3_i (operands[0], operands[1], operands[2]));
2560 */
2562 emit_insn (gen_mul_l (operands[1], operands[2]));
2563 emit_move_insn (operands[0], gen_rtx_REG (SImode, MACL_REG));
2564 }
2565 DONE;
2566 })
2568 (define_insn "mulsidi3_i"
2569 [(set (reg:SI MACH_REG)
2570 (truncate:SI
2571 (lshiftrt:DI
2572 (mult:DI
2573 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2574 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2575 (const_int 32))))
2576 (set (reg:SI MACL_REG)
2577 (mult:SI (match_dup 0)
2578 (match_dup 1)))]
2579 "TARGET_SH2"
2580 "dmuls.l %1,%0"
2581 [(set_attr "type" "dmpy")])
2583 (define_expand "mulsidi3"
2584 [(set (match_operand:DI 0 "arith_reg_dest")
2585 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2586 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand"))))]
2587 "TARGET_SH2"
2588 {
2589 emit_insn (gen_mulsidi3_compact (operands[0], operands[1], operands[2]));
2590 DONE;
2591 })
2593 (define_insn_and_split "mulsidi3_compact"
2594 [(set (match_operand:DI 0 "arith_reg_dest")
2595 (mult:DI (sign_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2596 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand"))))
2597 (clobber (reg:SI MACH_REG))
2598 (clobber (reg:SI MACL_REG))]
2599 "TARGET_SH2 && can_create_pseudo_p ()"
2600 "#"
2601 "&& 1"
2602 [(const_int 0)]
2603 {
2604 rtx low_dst = gen_lowpart (SImode, operands[0]);
2605 rtx high_dst = gen_highpart (SImode, operands[0]);
2607 emit_insn (gen_mulsidi3_i (operands[1], operands[2]));
2609 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
2610 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
2611 /* We need something to tag the possible REG_EQUAL notes on to. */
2612 emit_move_insn (operands[0], operands[0]);
2613 DONE;
2614 })
2616 (define_insn "umulsidi3_i"
2617 [(set (reg:SI MACH_REG)
2618 (truncate:SI
2619 (lshiftrt:DI
2620 (mult:DI
2621 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2622 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2623 (const_int 32))))
2624 (set (reg:SI MACL_REG)
2625 (mult:SI (match_dup 0)
2626 (match_dup 1)))]
2627 "TARGET_SH2"
2628 "dmulu.l %1,%0"
2629 [(set_attr "type" "dmpy")])
2631 (define_expand "umulsidi3"
2632 [(set (match_operand:DI 0 "arith_reg_dest")
2633 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2634 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand"))))]
2635 "TARGET_SH2"
2636 {
2637 emit_insn (gen_umulsidi3_compact (operands[0], operands[1], operands[2]));
2638 DONE;
2639 })
2641 (define_insn_and_split "umulsidi3_compact"
2642 [(set (match_operand:DI 0 "arith_reg_dest")
2643 (mult:DI (zero_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2644 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand"))))
2645 (clobber (reg:SI MACH_REG))
2646 (clobber (reg:SI MACL_REG))]
2647 "TARGET_SH2 && can_create_pseudo_p ()"
2648 "#"
2649 "&& 1"
2650 [(const_int 0)]
2651 {
2652 rtx low_dst = gen_lowpart (SImode, operands[0]);
2653 rtx high_dst = gen_highpart (SImode, operands[0]);
2655 emit_insn (gen_umulsidi3_i (operands[1], operands[2]));
2657 emit_move_insn (low_dst, gen_rtx_REG (SImode, MACL_REG));
2658 emit_move_insn (high_dst, gen_rtx_REG (SImode, MACH_REG));
2659 /* We need something to tag the possible REG_EQUAL notes on to. */
2660 emit_move_insn (operands[0], operands[0]);
2661 DONE;
2662 })
2664 (define_insn "smulsi3_highpart_i"
2665 [(set (reg:SI MACH_REG)
2666 (truncate:SI
2667 (lshiftrt:DI
2668 (mult:DI
2669 (sign_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2670 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2671 (const_int 32))))
2672 (clobber (reg:SI MACL_REG))]
2673 "TARGET_SH2"
2674 "dmuls.l %1,%0"
2675 [(set_attr "type" "dmpy")])
2677 (define_insn_and_split "smulsi3_highpart"
2678 [(set (match_operand:SI 0 "arith_reg_dest")
2679 (truncate:SI
2680 (lshiftrt:DI
2681 (mult:DI
2682 (sign_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2683 (sign_extend:DI (match_operand:SI 2 "arith_reg_operand")))
2684 (const_int 32))))
2685 (clobber (reg:SI MACL_REG))
2686 (clobber (reg:SI MACH_REG))]
2687 "TARGET_SH2 && can_create_pseudo_p ()"
2688 "#"
2689 "&& 1"
2690 [(const_int 0)]
2691 {
2692 emit_insn (gen_smulsi3_highpart_i (operands[1], operands[2]));
2693 emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
2694 })
2696 (define_insn "umulsi3_highpart_i"
2697 [(set (reg:SI MACH_REG)
2698 (truncate:SI
2699 (lshiftrt:DI
2700 (mult:DI
2701 (zero_extend:DI (match_operand:SI 0 "arith_reg_operand" "r"))
2702 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand" "r")))
2703 (const_int 32))))
2704 (clobber (reg:SI MACL_REG))]
2705 "TARGET_SH2"
2706 "dmulu.l %1,%0"
2707 [(set_attr "type" "dmpy")])
2709 (define_insn_and_split "umulsi3_highpart"
2710 [(set (match_operand:SI 0 "arith_reg_dest")
2711 (truncate:SI
2712 (lshiftrt:DI
2713 (mult:DI
2714 (zero_extend:DI (match_operand:SI 1 "arith_reg_operand"))
2715 (zero_extend:DI (match_operand:SI 2 "arith_reg_operand")))
2716 (const_int 32))))
2717 (clobber (reg:SI MACL_REG))]
2718 "TARGET_SH2 && can_create_pseudo_p ()"
2719 "#"
2720 "&& 1"
2721 [(const_int 0)]
2722 {
2723 emit_insn (gen_umulsi3_highpart_i (operands[1], operands[2]));
2724 emit_move_insn (operands[0], gen_rtx_REG (SImode, MACH_REG));
2725 })
2727 ;; -------------------------------------------------------------------------
2728 ;; Logical operations
2729 ;; -------------------------------------------------------------------------
2731 (define_expand "andsi3"
2732 [(set (match_operand:SI 0 "arith_reg_dest")
2733 (and:SI (match_operand:SI 1 "arith_reg_operand")
2734 (match_operand:SI 2 "logical_and_operand")))]
2735 ""
2736 {
2737 /* If it is possible to turn the and insn into a zero extension
2738 already, redundant zero extensions will be folded, which results
2739 in better code.
2740 Ideally the splitter of *andsi_compact would be enough, if redundant
2741 zero extensions were detected after the combine pass, which does not
2742 happen at the moment. */
2744 if (satisfies_constraint_Jmb (operands[2]))
2745 {
2746 emit_insn (gen_zero_extendqisi2 (operands[0],
2747 gen_lowpart (QImode, operands[1])));
2748 DONE;
2749 }
2750 else if (satisfies_constraint_Jmw (operands[2]))
2751 {
2752 emit_insn (gen_zero_extendhisi2 (operands[0],
2753 gen_lowpart (HImode, operands[1])));
2754 DONE;
2755 }
2756 })
2758 (define_insn_and_split "*andsi_compact"
2759 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r,z,r")
2760 (and:SI (match_operand:SI 1 "arith_reg_operand" "%r,r,0,0")
2761 (match_operand:SI 2 "logical_and_operand" "Jmb,Jmw,K08,r")))]
2762 "TARGET_SH1"
2763 "@
2764 extu.b %1,%0
2765 extu.w %1,%0
2766 and %2,%0
2767 and %2,%0"
2768 "&& 1"
2769 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))]
2770 {
2771 if (satisfies_constraint_Jmb (operands[2]))
2772 operands[1] = gen_lowpart (QImode, operands[1]);
2773 else if (satisfies_constraint_Jmw (operands[2]))
2774 operands[1] = gen_lowpart (HImode, operands[1]);
2775 else
2776 FAIL;
2777 }
2778 [(set_attr "type" "arith")])
2780 (define_insn "*andsi3_bclr"
2781 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2782 (and:SI (match_operand:SI 1 "arith_reg_operand" "%0")
2783 (match_operand:SI 2 "const_int_operand" "Psz")))]
2784 "TARGET_SH2A && satisfies_constraint_Psz (operands[2])"
2785 "bclr %W2,%0"
2786 [(set_attr "type" "arith")])
2788 (define_expand "iorsi3"
2789 [(set (match_operand:SI 0 "arith_reg_dest")
2790 (ior:SI (match_operand:SI 1 "arith_reg_operand")
2791 (match_operand:SI 2 "logical_operand")))])
2793 (define_insn "*iorsi3_compact"
2794 [(set (match_operand:SI 0 "arith_reg_dest" "=r,z")
2795 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
2796 (match_operand:SI 2 "logical_operand" "r,K08")))]
2797 "TARGET_SH1
2798 && !(TARGET_SH2A && satisfies_constraint_Pso (operands[2]))"
2799 "or %2,%0"
2800 [(set_attr "type" "arith")])
2802 (define_insn "*iorsi3_bset"
2803 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2804 (ior:SI (match_operand:SI 1 "arith_reg_operand" "%0")
2805 (match_operand:SI 2 "const_int_operand" "Pso")))]
2806 "TARGET_SH2A && satisfies_constraint_Pso (operands[2])"
2807 "bset %V2,%0"
2808 [(set_attr "type" "arith")])
2810 (define_insn "xorsi3"
2811 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
2812 (xor:SI (match_operand:SI 1 "arith_reg_operand" "%0,0")
2813 (match_operand:SI 2 "logical_operand" "K08,r")))]
2814 "TARGET_SH1"
2815 "xor %2,%0"
2816 [(set_attr "type" "arith")])
2818 ;; The *logical_op_t pattern helps combine eliminating sign/zero extensions
2819 ;; of results where one of the inputs is a T bit store. Notice that this
2820 ;; pattern must not match during reload. If reload picks this pattern it
2821 ;; will be impossible to split it afterwards.
2822 (define_insn_and_split "*logical_op_t"
2823 [(set (match_operand:SI 0 "arith_reg_dest")
2824 (match_operator:SI 3 "logical_operator"
2825 [(match_operand:SI 1 "arith_reg_operand")
2826 (match_operand:SI 2 "t_reg_operand")]))]
2827 "TARGET_SH1 && can_create_pseudo_p ()"
2828 "#"
2829 "&& 1"
2830 [(set (match_dup 4) (reg:SI T_REG))
2831 (set (match_dup 0) (match_dup 3))]
2832 {
2833 operands[4] = gen_reg_rtx (SImode);
2834 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
2835 operands[1], operands[4]);
2836 })
2838 ;; -------------------------------------------------------------------------
2839 ;; Shifts and rotates
2840 ;; -------------------------------------------------------------------------
2842 ;; Let combine see that we can get the MSB and LSB into the T bit
2843 ;; via shll and shlr. This allows it to plug it into insns that can have
2844 ;; the T bit as an input (e.g. addc).
2845 ;; On SH2A use bld #0,Rn instead of shlr to avoid mutating the input.
2846 (define_insn_and_split "*reg_lsb_t"
2847 [(set (reg:SI T_REG)
2848 (and:SI (match_operand:SI 0 "arith_reg_operand")
2849 (const_int 1)))]
2850 "TARGET_SH1 && can_create_pseudo_p ()"
2851 "#"
2852 "&& 1"
2853 [(const_int 0)]
2854 {
2855 emit_insn (TARGET_SH2A ? gen_bldsi_reg (operands[0], const0_rtx)
2856 : gen_shlr (gen_reg_rtx (SImode), operands[0]));
2857 })
2859 (define_insn_and_split "*reg_msb_t"
2860 [(set (reg:SI T_REG)
2861 (lshiftrt:SI (match_operand:SI 0 "arith_reg_operand")
2862 (const_int 31)))]
2863 "TARGET_SH1 && can_create_pseudo_p ()"
2864 "#"
2865 "&& 1"
2866 [(const_int 0)]
2867 {
2868 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
2869 })
2871 (define_expand "rotrsi3"
2872 [(set (match_operand:SI 0 "arith_reg_dest")
2873 (rotatert:SI (match_operand:SI 1 "arith_reg_operand")
2874 (match_operand:SI 2 "const_int_operand")))]
2875 "TARGET_SH1"
2876 {
2877 HOST_WIDE_INT ival = INTVAL (operands[2]);
2878 if (ival == 1)
2879 {
2880 emit_insn (gen_rotrsi3_1 (operands[0], operands[1]));
2881 DONE;
2882 }
2884 FAIL;
2885 })
2887 (define_insn "rotrsi3_1"
2888 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2889 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
2890 (const_int 1)))
2891 (set (reg:SI T_REG)
2892 (and:SI (match_dup 1) (const_int 1)))]
2893 "TARGET_SH1"
2894 "rotr %0"
2895 [(set_attr "type" "arith")])
2897 ;; A slimplified version of rotr for combine.
2898 (define_insn "*rotrsi3_1"
2899 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2900 (rotatert:SI (match_operand:SI 1 "arith_reg_operand" "0")
2901 (const_int 1)))
2902 (clobber (reg:SI T_REG))]
2903 "TARGET_SH1"
2904 "rotr %0"
2905 [(set_attr "type" "arith")])
2907 (define_insn "rotlsi3_1"
2908 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2909 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
2910 (const_int 1)))
2911 (set (reg:SI T_REG)
2912 (lshiftrt:SI (match_dup 1) (const_int 31)))]
2913 "TARGET_SH1"
2914 "rotl %0"
2915 [(set_attr "type" "arith")])
2917 ;; A simplified version of rotl for combine.
2918 (define_insn "*rotlsi3_1"
2919 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2920 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
2921 (const_int 1)))
2922 (clobber (reg:SI T_REG))]
2923 "TARGET_SH1"
2924 "rotl %0"
2925 [(set_attr "type" "arith")])
2927 (define_insn "rotlsi3_31"
2928 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2929 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "0")
2930 (const_int 31)))
2931 (clobber (reg:SI T_REG))]
2932 "TARGET_SH1"
2933 "rotr %0"
2934 [(set_attr "type" "arith")])
2936 (define_insn "rotlsi3_16"
2937 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
2938 (rotate:SI (match_operand:SI 1 "arith_reg_operand" "r")
2939 (const_int 16)))]
2940 "TARGET_SH1"
2941 "swap.w %1,%0"
2942 [(set_attr "type" "arith")])
2944 (define_expand "rotlsi3"
2945 [(set (match_operand:SI 0 "arith_reg_dest")
2946 (rotate:SI (match_operand:SI 1 "arith_reg_operand")
2947 (match_operand:SI 2 "const_int_operand")))]
2948 "TARGET_SH1"
2949 {
2950 static const char rot_tab[] = {
2951 000, 000, 000, 000, 000, 000, 010, 001,
2952 001, 001, 011, 013, 003, 003, 003, 003,
2953 003, 003, 003, 003, 003, 013, 012, 002,
2954 002, 002, 010, 000, 000, 000, 000, 000,
2955 };
2957 int count = INTVAL (operands[2]);
2958 int choice = rot_tab[count];
2959 if (choice & 010 && SH_DYNAMIC_SHIFT_COST <= 1)
2960 FAIL;
2961 choice &= 7;
2962 switch (choice)
2963 {
2964 case 0:
2965 emit_move_insn (operands[0], operands[1]);
2966 count -= (count & 16) * 2;
2967 break;
2968 case 3:
2969 emit_insn (gen_rotlsi3_16 (operands[0], operands[1]));
2970 count -= 16;
2971 break;
2972 case 1:
2973 case 2:
2974 {
2975 rtx parts[2];
2976 parts[0] = gen_reg_rtx (SImode);
2977 parts[1] = gen_reg_rtx (SImode);
2978 emit_insn (gen_rotlsi3_16 (parts[2-choice], operands[1]));
2979 emit_move_insn (parts[choice-1], operands[1]);
2980 emit_insn (gen_ashlsi3 (parts[0], parts[0], GEN_INT (8)));
2981 emit_insn (gen_lshrsi3 (parts[1], parts[1], GEN_INT (8)));
2982 emit_insn (gen_iorsi3 (operands[0], parts[0], parts[1]));
2983 count = (count & ~16) - 8;
2984 }
2985 }
2987 for (; count > 0; count--)
2988 emit_insn (gen_rotlsi3_1 (operands[0], operands[0]));
2989 for (; count < 0; count++)
2990 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
2992 DONE;
2993 })
2995 (define_insn "rotlhi3_8"
2996 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
2997 (rotate:HI (match_operand:HI 1 "arith_reg_operand" "r")
2998 (const_int 8)))]
2999 "TARGET_SH1"
3000 "swap.b %1,%0"
3001 [(set_attr "type" "arith")])
3003 (define_expand "rotlhi3"
3004 [(set (match_operand:HI 0 "arith_reg_operand")
3005 (rotate:HI (match_operand:HI 1 "arith_reg_operand")
3006 (match_operand:HI 2 "const_int_operand")))]
3007 "TARGET_SH1"
3008 {
3009 if (INTVAL (operands[2]) != 8)
3010 FAIL;
3011 })
3013 ;; The rotcr and rotcl insns are used primarily in DImode shifts by one.
3014 ;; They can also be used to implement things like
3015 ;; bool t = a == b;
3016 ;; int x0 = (y >> 1) | (t << 31); // rotcr
3017 ;; int x1 = (y << 1) | t; // rotcl
3018 (define_insn "rotcr"
3019 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3020 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3021 (const_int 1))
3022 (ashift:SI (match_operand:SI 2 "t_reg_operand")
3023 (const_int 31))))
3024 (set (reg:SI T_REG)
3025 (and:SI (match_dup 1) (const_int 1)))]
3026 "TARGET_SH1"
3027 "rotcr %0"
3028 [(set_attr "type" "arith")])
3030 (define_insn "rotcl"
3031 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3032 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
3033 (const_int 1))
3034 (match_operand:SI 2 "t_reg_operand")))
3035 (set (reg:SI T_REG)
3036 (lshiftrt:SI (match_dup 1) (const_int 31)))]
3037 "TARGET_SH1"
3038 "rotcl %0"
3039 [(set_attr "type" "arith")])
3041 ;; Simplified rotcr version for combine, which allows arbitrary shift
3042 ;; amounts for the reg. If the shift amount is '1' rotcr can be used
3043 ;; directly. Otherwise we have to insert a shift in between.
3044 (define_insn_and_split "*rotcr"
3045 [(set (match_operand:SI 0 "arith_reg_dest")
3046 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_or_0_operand")
3047 (match_operand:SI 2 "const_int_operand"))
3048 (ashift:SI (match_operand 3 "arith_reg_or_treg_set_expr")
3049 (const_int 31))))
3050 (clobber (reg:SI T_REG))]
3051 "TARGET_SH1 && can_create_pseudo_p ()"
3052 "#"
3053 "&& 1"
3054 [(const_int 0)]
3055 {
3056 rtx_insn *prev_set_t_insn = NULL;
3058 if (!arith_reg_operand (operands[3], SImode))
3059 {
3060 sh_treg_insns ti = sh_split_treg_set_expr (operands[3], curr_insn);
3061 if (!ti.was_treg_operand ())
3062 prev_set_t_insn = ti.first_insn ();
3064 operands[3] = get_t_reg_rtx ();
3066 if (TARGET_SH2A && ti.has_trailing_nott () && operands[1] == const0_rtx)
3067 {
3068 /* Convert to a movrt, rotr sequence. */
3069 remove_insn (ti.trailing_nott ());
3070 rtx tmp = gen_reg_rtx (SImode);
3071 emit_insn (gen_movnegt (tmp, get_t_reg_rtx ()));
3072 emit_insn (gen_rotrsi3_1 (operands[0], tmp));
3073 DONE;
3074 }
3075 }
3077 if (operands[1] == const0_rtx)
3078 {
3079 operands[1] = gen_reg_rtx (SImode);
3080 emit_insn (gen_movt (operands[1], get_t_reg_rtx ()));
3081 }
3083 if (INTVAL (operands[2]) > 1)
3084 {
3085 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1);
3086 rtx tmp_t_reg = NULL_RTX;
3088 /* If we're going to emit a shift sequence that clobbers the T_REG,
3089 try to find the previous insn that sets the T_REG and emit the
3090 shift insn before that insn, to remove the T_REG dependency.
3091 If the insn that sets the T_REG cannot be found, store the T_REG
3092 in a temporary reg and restore it after the shift. */
3093 if (sh_lshrsi_clobbers_t_reg_p (shift_count)
3094 && ! sh_dynamicalize_shift_p (shift_count))
3095 {
3096 if (prev_set_t_insn == NULL)
3097 prev_set_t_insn = prev_nonnote_nondebug_insn_bb (curr_insn);
3099 /* Skip the nott insn, which was probably inserted by the splitter
3100 of *rotcr_neg_t. Don't use one of the recog functions
3101 here during insn splitting, since that causes problems in later
3102 passes. */
3103 if (prev_set_t_insn != NULL_RTX)
3104 {
3105 rtx pat = PATTERN (prev_set_t_insn);
3106 if (GET_CODE (pat) == SET
3107 && t_reg_operand (XEXP (pat, 0), SImode)
3108 && negt_reg_operand (XEXP (pat, 1), SImode))
3109 prev_set_t_insn = prev_nonnote_nondebug_insn_bb
3110 (prev_set_t_insn);
3111 }
3113 if (! (prev_set_t_insn != NULL_RTX
3114 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn)
3115 && ! reg_referenced_p (get_t_reg_rtx (),
3116 PATTERN (prev_set_t_insn))))
3117 {
3118 prev_set_t_insn = NULL;
3119 tmp_t_reg = gen_reg_rtx (SImode);
3120 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ()));
3121 }
3122 }
3124 rtx shift_result = gen_reg_rtx (SImode);
3125 rtx shift_insn = gen_lshrsi3 (shift_result, operands[1], shift_count);
3126 operands[1] = shift_result;
3128 /* Emit the shift insn before the insn that sets T_REG, if possible. */
3129 if (prev_set_t_insn != NULL_RTX)
3130 emit_insn_before (shift_insn, prev_set_t_insn);
3131 else
3132 emit_insn (shift_insn);
3134 /* Restore T_REG if it has been saved before. */
3135 if (tmp_t_reg != NULL_RTX)
3136 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx));
3137 }
3139 /* For the rotcr insn to work, operands[3] must be in T_REG.
3140 If it is not we can get it there by shifting it right one bit.
3141 In this case T_REG is not an input for this insn, thus we don't have to
3142 pay attention as of where to insert the shlr insn. */
3143 if (! t_reg_operand (operands[3], SImode))
3144 {
3145 /* We don't care about the shifted result here, only the T_REG. */
3146 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3]));
3147 operands[3] = get_t_reg_rtx ();
3148 }
3150 emit_insn (gen_rotcr (operands[0], operands[1], operands[3]));
3151 DONE;
3152 })
3154 ;; If combine tries the same as above but with swapped operands, split
3155 ;; it so that it will try the pattern above.
3156 (define_split
3157 [(set (match_operand:SI 0 "arith_reg_dest")
3158 (ior:SI (ashift:SI (match_operand 1 "arith_reg_or_treg_set_expr")
3159 (const_int 31))
3160 (lshiftrt:SI (match_operand:SI 2 "arith_reg_or_0_operand")
3161 (match_operand:SI 3 "const_int_operand"))))]
3162 "TARGET_SH1 && can_create_pseudo_p ()"
3163 [(parallel [(set (match_dup 0)
3164 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3))
3165 (ashift:SI (match_dup 1) (const_int 31))))
3166 (clobber (reg:SI T_REG))])])
3168 ;; Basically the same as the rotcr pattern above, but for rotcl.
3169 ;; FIXME: Fold copy pasted split code for rotcr and rotcl.
3170 (define_insn_and_split "*rotcl"
3171 [(set (match_operand:SI 0 "arith_reg_dest")
3172 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3173 (match_operand:SI 2 "const_int_operand"))
3174 (and:SI (match_operand:SI 3 "arith_reg_or_t_reg_operand")
3175 (const_int 1))))
3176 (clobber (reg:SI T_REG))]
3177 "TARGET_SH1"
3178 "#"
3179 "&& can_create_pseudo_p ()"
3180 [(const_int 0)]
3181 {
3182 gcc_assert (INTVAL (operands[2]) > 0);
3184 if (INTVAL (operands[2]) > 1)
3185 {
3186 const rtx shift_count = GEN_INT (INTVAL (operands[2]) - 1);
3187 rtx_insn *prev_set_t_insn = NULL;
3188 rtx tmp_t_reg = NULL_RTX;
3190 /* If we're going to emit a shift sequence that clobbers the T_REG,
3191 try to find the previous insn that sets the T_REG and emit the
3192 shift insn before that insn, to remove the T_REG dependency.
3193 If the insn that sets the T_REG cannot be found, store the T_REG
3194 in a temporary reg and restore it after the shift. */
3195 if (sh_ashlsi_clobbers_t_reg_p (shift_count)
3196 && ! sh_dynamicalize_shift_p (shift_count))
3197 {
3198 prev_set_t_insn = prev_nonnote_nondebug_insn_bb (curr_insn);
3200 /* Skip the nott insn, which was probably inserted by the splitter
3201 of *rotcl_neg_t. Don't use one of the recog functions
3202 here during insn splitting, since that causes problems in later
3203 passes. */
3204 if (prev_set_t_insn != NULL_RTX)
3205 {
3206 rtx pat = PATTERN (prev_set_t_insn);
3207 if (GET_CODE (pat) == SET
3208 && t_reg_operand (XEXP (pat, 0), SImode)
3209 && negt_reg_operand (XEXP (pat, 1), SImode))
3210 prev_set_t_insn = prev_nonnote_nondebug_insn_bb
3211 (prev_set_t_insn);
3212 }
3214 if (! (prev_set_t_insn != NULL_RTX
3215 && reg_set_p (get_t_reg_rtx (), prev_set_t_insn)
3216 && ! reg_referenced_p (get_t_reg_rtx (),
3217 PATTERN (prev_set_t_insn))))
3218 {
3219 prev_set_t_insn = NULL;
3220 tmp_t_reg = gen_reg_rtx (SImode);
3221 emit_insn (gen_move_insn (tmp_t_reg, get_t_reg_rtx ()));
3222 }
3223 }
3225 rtx shift_result = gen_reg_rtx (SImode);
3226 rtx shift_insn = gen_ashlsi3 (shift_result, operands[1], shift_count);
3227 operands[1] = shift_result;
3229 /* Emit the shift insn before the insn that sets T_REG, if possible. */
3230 if (prev_set_t_insn != NULL_RTX)
3231 emit_insn_before (shift_insn, prev_set_t_insn);
3232 else
3233 emit_insn (shift_insn);
3235 /* Restore T_REG if it has been saved before. */
3236 if (tmp_t_reg != NULL_RTX)
3237 emit_insn (gen_cmpgtsi_t (tmp_t_reg, const0_rtx));
3238 }
3240 /* For the rotcl insn to work, operands[3] must be in T_REG.
3241 If it is not we can get it there by shifting it right one bit.
3242 In this case T_REG is not an input for this insn, thus we don't have to
3243 pay attention as of where to insert the shlr insn. */
3244 if (! t_reg_operand (operands[3], SImode))
3245 {
3246 /* We don't care about the shifted result here, only the T_REG. */
3247 emit_insn (gen_shlr (gen_reg_rtx (SImode), operands[3]));
3248 operands[3] = get_t_reg_rtx ();
3249 }
3251 emit_insn (gen_rotcl (operands[0], operands[1], operands[3]));
3252 DONE;
3253 })
3255 ;; rotcl combine pattern variations
3256 (define_insn_and_split "*rotcl"
3257 [(set (match_operand:SI 0 "arith_reg_dest")
3258 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3259 (match_operand:SI 2 "const_int_operand"))
3260 (match_operand 3 "treg_set_expr")))
3261 (clobber (reg:SI T_REG))]
3262 "TARGET_SH1"
3263 "#"
3264 "&& can_create_pseudo_p ()"
3265 [(parallel [(set (match_dup 0)
3266 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
3267 (and:SI (match_dup 3) (const_int 1))))
3268 (clobber (reg:SI T_REG))])]
3269 {
3270 sh_split_treg_set_expr (operands[3], curr_insn);
3271 operands[3] = get_t_reg_rtx ();
3272 })
3274 (define_insn_and_split "*rotcl"
3275 [(set (match_operand:SI 0 "arith_reg_dest")
3276 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_or_t_reg_operand")
3277 (const_int 1))
3278 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
3279 (match_operand:SI 3 "const_int_operand"))))
3280 (clobber (reg:SI T_REG))]
3281 "TARGET_SH1"
3282 "#"
3283 "&& can_create_pseudo_p ()"
3284 [(parallel [(set (match_dup 0)
3285 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
3286 (and:SI (match_dup 1) (const_int 1))))
3287 (clobber (reg:SI T_REG))])])
3289 (define_insn_and_split "*rotcl"
3290 [(set (match_operand:SI 0 "arith_reg_dest")
3291 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3292 (match_operand:SI 2 "const_int_operand"))
3293 (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand")
3294 (const_int 31))))
3295 (clobber (reg:SI T_REG))]
3296 "TARGET_SH1"
3297 "#"
3298 "&& can_create_pseudo_p ()"
3299 [(parallel [(set (match_dup 0)
3300 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
3301 (and:SI (reg:SI T_REG) (const_int 1))))
3302 (clobber (reg:SI T_REG))])]
3303 {
3304 /* We don't care about the result of the left shift, only the T_REG. */
3305 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3]));
3306 })
3308 (define_insn_and_split "*rotcl"
3309 [(set (match_operand:SI 0 "arith_reg_dest")
3310 (ior:SI (lshiftrt:SI (match_operand:SI 3 "arith_reg_operand")
3311 (const_int 31))
3312 (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3313 (match_operand:SI 2 "const_int_operand"))))
3314 (clobber (reg:SI T_REG))]
3315 "TARGET_SH1"
3316 "#"
3317 "&& can_create_pseudo_p ()"
3318 [(parallel [(set (match_dup 0)
3319 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
3320 (and:SI (reg:SI T_REG) (const_int 1))))
3321 (clobber (reg:SI T_REG))])]
3322 {
3323 /* We don't care about the result of the left shift, only the T_REG. */
3324 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[3]));
3325 })
3327 (define_insn_and_split "*rotcl"
3328 [(set (match_operand:SI 0 "arith_reg_dest")
3329 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand")
3330 (match_operand 2 "const_int_operand"))
3331 (zero_extract:SI (match_operand:SI 3 "arith_reg_operand")
3332 (const_int 1)
3333 (match_operand 4 "const_int_operand"))))
3334 (clobber (reg:SI T_REG))]
3335 "TARGET_SH1"
3336 "#"
3337 "&& can_create_pseudo_p ()"
3338 [(parallel [(set (match_dup 0)
3339 (ior:SI (ashift:SI (match_dup 1) (match_dup 2))
3340 (and:SI (match_dup 5) (const_int 1))))
3341 (clobber (reg:SI T_REG))])]
3342 {
3343 if (TARGET_SH2A && satisfies_constraint_K03 (operands[4]))
3344 {
3345 /* On SH2A we can use the bld insn to zero extract a single bit
3346 into the T bit. */
3347 operands[5] = get_t_reg_rtx ();
3348 emit_insn (gen_bldsi_reg (operands[3], operands[4]));
3349 }
3350 else
3351 {
3352 /* If we can't use the bld insn we have to emit a tst + nott sequence
3353 to get the extracted bit into the T bit.
3354 This will probably be worse than pre-shifting the operand. */
3355 operands[5] = gen_reg_rtx (SImode);
3356 emit_insn (gen_lshrsi3 (operands[5], operands[3], operands[4]));
3357 }
3358 })
3360 ;; rotcr combine bridge pattern which will make combine try out more
3361 ;; complex patterns.
3362 (define_insn_and_split "*rotcr"
3363 [(set (match_operand:SI 0 "arith_reg_dest")
3364 (ashift:SI (match_operand 1 "treg_set_expr") (const_int 31)))]
3365 "TARGET_SH1 && can_create_pseudo_p ()"
3366 "#"
3367 "&& 1"
3368 [(parallel [(set (match_dup 0)
3369 (ior:SI (lshiftrt:SI (const_int 0) (const_int 1))
3370 (ashift:SI (match_dup 1) (const_int 31))))
3371 (clobber (reg:SI T_REG))])])
3373 (define_insn_and_split "*rotcr"
3374 [(set (match_operand:SI 0 "arith_reg_dest")
3375 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
3376 (const_int -2147483648)) ;; 0xffffffff80000000
3377 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
3378 (const_int 1))))
3379 (clobber (reg:SI T_REG))]
3380 "TARGET_SH1"
3381 "#"
3382 "&& can_create_pseudo_p ()"
3383 [(const_int 0)]
3384 {
3385 rtx tmp = gen_reg_rtx (SImode);
3386 emit_insn (gen_shll (tmp, operands[1]));
3387 emit_insn (gen_rotcr (operands[0], operands[2], get_t_reg_rtx ()));
3388 DONE;
3389 })
3391 (define_insn_and_split "*rotcr"
3392 [(set (match_operand:SI 0 "arith_reg_dest")
3393 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
3394 (const_int 1))
3395 (const_int -2147483648))) ;; 0xffffffff80000000
3396 (clobber (reg:SI T_REG))]
3397 "TARGET_SH1"
3398 "#"
3399 "&& can_create_pseudo_p ()"
3400 [(const_int 0)]
3401 {
3402 emit_insn (gen_sett ());
3403 emit_insn (gen_rotcr (operands[0], operands[1], get_t_reg_rtx ()));
3404 DONE;
3405 })
3407 ;; rotcr combine patterns for rotating in the negated T_REG value.
3408 (define_insn_and_split "*rotcr_neg_t"
3409 [(set (match_operand:SI 0 "arith_reg_dest")
3410 (ior:SI (match_operand:SI 1 "negt_reg_shl31_operand")
3411 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand")
3412 (match_operand:SI 3 "const_int_operand"))))
3413 (clobber (reg:SI T_REG))]
3414 "TARGET_SH1"
3415 "#"
3416 "&& can_create_pseudo_p ()"
3417 [(parallel [(set (match_dup 0)
3418 (ior:SI (lshiftrt:SI (match_dup 2) (match_dup 3))
3419 (ashift:SI (reg:SI T_REG) (const_int 31))))
3420 (clobber (reg:SI T_REG))])]
3421 {
3422 emit_insn (gen_nott (get_t_reg_rtx ()));
3423 })
3425 (define_insn_and_split "*rotcr_neg_t"
3426 [(set (match_operand:SI 0 "arith_reg_dest")
3427 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
3428 (match_operand:SI 2 "const_int_operand"))
3429 (match_operand:SI 3 "negt_reg_shl31_operand")))
3430 (clobber (reg:SI T_REG))]
3431 "TARGET_SH1"
3432 "#"
3433 "&& can_create_pseudo_p ()"
3434 [(parallel [(set (match_dup 0)
3435 (ior:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
3436 (ashift:SI (reg:SI T_REG) (const_int 31))))
3437 (clobber (reg:SI T_REG))])]
3438 {
3439 emit_insn (gen_nott (get_t_reg_rtx ()));
3440 })
3442 ;; rotcl combine patterns for rotating in the negated T_REG value.
3443 ;; For some strange reason these have to be specified as splits which combine
3444 ;; will pick up. If they are specified as insn_and_split like the
3445 ;; *rotcr_neg_t patterns above, combine would recognize them successfully
3446 ;; but not emit them on non-SH2A targets.
3447 (define_split
3448 [(set (match_operand:SI 0 "arith_reg_dest")
3449 (ior:SI (match_operand:SI 1 "negt_reg_operand")
3450 (ashift:SI (match_operand:SI 2 "arith_reg_operand")
3451 (match_operand:SI 3 "const_int_operand"))))]
3452 "TARGET_SH1"
3453 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))
3454 (parallel [(set (match_dup 0)
3455 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
3456 (and:SI (reg:SI T_REG) (const_int 1))))
3457 (clobber (reg:SI T_REG))])])
3459 (define_split
3460 [(set (match_operand:SI 0 "arith_reg_dest")
3461 (ior:SI (ashift:SI (match_operand:SI 2 "arith_reg_operand")
3462 (match_operand:SI 3 "const_int_operand"))
3463 (match_operand:SI 1 "negt_reg_operand")))]
3464 "TARGET_SH1"
3465 [(set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))
3466 (parallel [(set (match_dup 0)
3467 (ior:SI (ashift:SI (match_dup 2) (match_dup 3))
3468 (and:SI (reg:SI T_REG) (const_int 1))))
3469 (clobber (reg:SI T_REG))])])
3471 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3472 ;; SImode shift left
3474 (define_expand "ashlsi3"
3475 [(set (match_operand:SI 0 "arith_reg_operand" "")
3476 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "")
3477 (match_operand:SI 2 "shift_count_operand" "")))]
3478 ""
3479 {
3480 if (TARGET_DYNSHIFT
3481 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2]))
3482 {
3483 /* Don't force the constant into a reg yet. Some other optimizations
3484 might not see through the reg that holds the shift count. */
3485 }
3487 /* If the ashlsi3_* insn is going to clobber the T_REG it must be
3488 expanded here. */
3489 if (CONST_INT_P (operands[2])
3490 && sh_ashlsi_clobbers_t_reg_p (operands[2])
3491 && ! sh_dynamicalize_shift_p (operands[2]))
3492 {
3493 emit_insn (gen_ashlsi3_n_clobbers_t (operands[0], operands[1],
3494 operands[2]));
3495 DONE;
3496 }
3498 /* Expand a library call for the dynamic shift. */
3499 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT)
3500 {
3501 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
3502 rtx funcaddr = gen_reg_rtx (Pmode);
3503 rtx lab = function_symbol (funcaddr, "__ashlsi3_r0", SFUNC_STATIC).lab;
3504 emit_insn (gen_ashlsi3_d_call (operands[0], operands[2], funcaddr, lab));
3506 DONE;
3507 }
3508 })
3510 (define_insn "ashlsi3_k"
3511 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
3512 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0,0")
3513 (match_operand:SI 2 "p27_shift_count_operand" "M,P27")))]
3514 "TARGET_SH1"
3515 "@
3516 add %0,%0
3517 shll%O2 %0"
3518 [(set_attr "type" "arith")])
3520 (define_insn_and_split "ashlsi3_d"
3521 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3522 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
3523 (match_operand:SI 2 "shift_count_operand" "r")))]
3524 "TARGET_DYNSHIFT"
3525 "shld %2,%0"
3526 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2])
3527 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])"
3528 [(const_int 0)]
3529 {
3530 if (satisfies_constraint_P27 (operands[2]))
3531 {
3532 emit_insn (gen_ashlsi3_k (operands[0], operands[1], operands[2]));
3533 DONE;
3534 }
3535 else if (! satisfies_constraint_P27 (operands[2]))
3536 {
3537 /* This must happen before reload, otherwise the constant will be moved
3538 into a register due to the "r" constraint, after which this split
3539 cannot be done anymore.
3540 Unfortunately the move insn will not always be eliminated.
3541 Also, here we must not create a shift sequence that clobbers the
3542 T_REG. */
3543 emit_move_insn (operands[0], operands[1]);
3544 gen_shifty_op (ASHIFT, operands);
3545 DONE;
3546 }
3548 FAIL;
3549 }
3550 [(set_attr "type" "dyn_shift")])
3552 ;; If dynamic shifts are not available use a library function.
3553 ;; By specifying the pattern we reduce the number of call clobbered regs.
3554 ;; In order to make combine understand the truncation of the shift amount
3555 ;; operand we have to allow it to use pseudo regs for the shift operands.
3556 (define_insn "ashlsi3_d_call"
3557 [(set (match_operand:SI 0 "arith_reg_dest" "=z,z")
3558 (ashift:SI (reg:SI R4_REG)
3559 (and:SI (match_operand:SI 1 "arith_reg_operand" "z,z")
3560 (const_int 31))))
3561 (use (match_operand:SI 2 "arith_reg_operand" "r,r"))
3562 (use (match_operand 3 "" "Z,Ccl"))
3563 (clobber (reg:SI T_REG))
3564 (clobber (reg:SI PR_REG))]
3565 "TARGET_SH1 && !TARGET_DYNSHIFT"
3566 "@
3567 jsr @%2%#
3568 bsrf %2\n%O3:%#"
3569 [(set_attr "type" "sfunc")
3570 (set_attr "needs_delay_slot" "yes")])
3572 (define_insn_and_split "ashlsi3_n"
3573 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3574 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
3575 (match_operand:SI 2 "not_p27_shift_count_operand" "")))]
3576 "TARGET_SH1 && ! sh_ashlsi_clobbers_t_reg_p (operands[2])"
3577 "#"
3578 "&& (reload_completed
3579 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
3580 [(const_int 0)]
3581 {
3582 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
3583 {
3584 /* If this pattern was picked and dynamic shifts are supported, switch
3585 to dynamic shift pattern before reload. */
3586 operands[2] = force_reg (SImode, operands[2]);
3587 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
3588 }
3589 else
3590 gen_shifty_op (ASHIFT, operands);
3592 DONE;
3593 })
3595 (define_insn_and_split "ashlsi3_n_clobbers_t"
3596 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3597 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0")
3598 (match_operand:SI 2 "not_p27_shift_count_operand" "")))
3599 (clobber (reg:SI T_REG))]
3600 "TARGET_SH1 && sh_ashlsi_clobbers_t_reg_p (operands[2])"
3601 "#"
3602 "&& (reload_completed || INTVAL (operands[2]) == 31
3603 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
3604 [(const_int 0)]
3605 {
3606 if (INTVAL (operands[2]) == 31)
3607 {
3608 /* If the shift amount is 31 we split into a different sequence before
3609 reload so that it gets a chance to allocate R0 for the sequence.
3610 If it fails to do so (due to pressure on R0), it will take one insn
3611 more for the and. */
3612 emit_insn (gen_andsi3 (operands[0], operands[1], const1_rtx));
3613 emit_insn (gen_rotlsi3_31 (operands[0], operands[0]));
3614 }
3615 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
3616 {
3617 /* If this pattern was picked and dynamic shifts are supported, switch
3618 to dynamic shift pattern before reload. */
3619 operands[2] = force_reg (SImode, operands[2]);
3620 emit_insn (gen_ashlsi3_d (operands[0], operands[1], operands[2]));
3621 }
3622 else
3623 gen_shifty_op (ASHIFT, operands);
3625 DONE;
3626 })
3628 (define_insn "shll"
3629 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3630 (ashift:SI (match_operand:SI 1 "arith_reg_operand" "0") (const_int 1)))
3631 (set (reg:SI T_REG)
3632 (lt:SI (match_dup 1) (const_int 0)))]
3633 "TARGET_SH1"
3634 "shll %0"
3635 [(set_attr "type" "arith")])
3637 (define_insn "*ashlsi_c_void"
3638 [(set (reg:SI T_REG)
3639 (lt:SI (match_operand:SI 0 "arith_reg_operand" "r") (const_int 0)))
3640 (clobber (match_scratch:SI 1 "=0"))]
3641 "TARGET_SH1 && cse_not_expected"
3642 "shll %0"
3643 [(set_attr "type" "arith")])
3645 (define_peephole2
3646 [(set (match_operand:SI 0 "arith_reg_dest" "") (const_int 0))
3647 (set (reg:SI T_REG)
3648 (gt:SI (match_dup 0) (match_operand:SI 1 "arith_reg_operand" "")))]
3649 "TARGET_SH1
3650 && peep2_reg_dead_p (2, operands[0])
3651 && peep2_reg_dead_p (2, operands[1])"
3652 [(const_int 0)]
3653 {
3654 emit_insn (gen_shll (operands[1], operands[1]));
3655 DONE;
3656 })
3658 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3659 ;; HImode shift left
3661 (define_expand "ashlhi3"
3662 [(parallel [(set (match_operand:HI 0 "arith_reg_operand" "")
3663 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "")
3664 (match_operand:SI 2 "nonmemory_operand" "")))
3665 (clobber (reg:SI T_REG))])]
3666 "TARGET_SH1"
3667 {
3668 if (!CONST_INT_P (operands[2]))
3669 FAIL;
3670 /* It may be possible to call gen_ashlhi3 directly with more generic
3671 operands. Make sure operands[1] is a HImode register here. */
3672 if (!arith_reg_operand (operands[1], HImode))
3673 operands[1] = copy_to_mode_reg (HImode, operands[1]);
3674 })
3676 (define_insn "ashlhi3_k"
3677 [(set (match_operand:HI 0 "arith_reg_dest" "=r,r")
3678 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0,0")
3679 (match_operand:HI 2 "const_int_operand" "M,P27")))]
3680 "TARGET_SH1 && satisfies_constraint_P27 (operands[2])"
3681 "@
3682 add %0,%0
3683 shll%O2 %0"
3684 [(set_attr "type" "arith")])
3686 (define_insn_and_split "*ashlhi3_n"
3687 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
3688 (ashift:HI (match_operand:HI 1 "arith_reg_operand" "0")
3689 (match_operand:HI 2 "const_int_operand" "n")))
3690 (clobber (reg:SI T_REG))]
3691 "TARGET_SH1"
3692 "#"
3693 "&& reload_completed"
3694 [(use (reg:SI R0_REG))]
3695 {
3696 gen_shifty_hi_op (ASHIFT, operands);
3697 DONE;
3698 })
3700 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3701 ;; DImode shift left
3703 (define_expand "ashldi3"
3704 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
3705 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "")
3706 (match_operand:DI 2 "immediate_operand" "")))
3707 (clobber (reg:SI T_REG))])]
3708 ""
3709 {
3710 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 1)
3711 {
3712 emit_insn (gen_ashldi3_k (operands[0], operands[1]));
3713 DONE;
3714 }
3715 else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 32)
3716 {
3717 emit_insn (gen_ashldi3_std (operands[0], operands[1], operands[2]));
3718 DONE;
3719 }
3720 else
3721 FAIL;
3722 })
3724 ;; Expander for DImode shift left with SImode operations.
3725 (define_expand "ashldi3_std"
3726 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3727 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "r")
3728 (match_operand:DI 2 "const_int_operand" "n")))]
3729 "TARGET_SH1 && INTVAL (operands[2]) < 32"
3730 {
3731 rtx low_src = gen_lowpart (SImode, operands[1]);
3732 rtx high_src = gen_highpart (SImode, operands[1]);
3733 rtx dst = gen_reg_rtx (DImode);
3734 rtx low_dst = gen_lowpart (SImode, dst);
3735 rtx high_dst = gen_highpart (SImode, dst);
3736 rtx tmp0 = gen_reg_rtx (SImode);
3737 rtx tmp1 = gen_reg_rtx (SImode);
3739 emit_insn (gen_lshrsi3 (tmp0, low_src, GEN_INT (32 - INTVAL (operands[2]))));
3740 emit_insn (gen_ashlsi3 (low_dst, low_src, operands[2]));
3741 emit_insn (gen_ashlsi3 (tmp1, high_src, operands[2]));
3742 emit_insn (gen_iorsi3 (high_dst, tmp0, tmp1));
3743 emit_move_insn (operands[0], dst);
3744 DONE;
3745 })
3747 (define_insn_and_split "ashldi3_k"
3748 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3749 (ashift:DI (match_operand:DI 1 "arith_reg_operand" "0")
3750 (const_int 1)))
3751 (clobber (reg:SI T_REG))]
3752 "TARGET_SH1"
3753 "#"
3754 "&& reload_completed"
3755 [(const_int 0)]
3756 {
3757 rtx high = gen_highpart (SImode, operands[0]);
3758 rtx low = gen_lowpart (SImode, operands[0]);
3759 emit_insn (gen_shll (low, low));
3760 emit_insn (gen_rotcl (high, high, get_t_reg_rtx ()));
3761 DONE;
3762 })
3764 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3765 ;; SImode arithmetic shift right
3766 ;;
3767 ;; We can't do HImode right shifts correctly unless we start out with an
3768 ;; explicit zero / sign extension; doing that would result in worse overall
3769 ;; code, so just let the machine independent code widen the mode.
3770 ;; That's why we don't have ashrhi3_k / lshrhi3_k / lshrhi3_m / lshrhi3 .
3772 (define_expand "ashrsi3"
3773 [(parallel [(set (match_operand:SI 0 "arith_reg_dest" "")
3774 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
3775 (match_operand:SI 2 "nonmemory_operand" "")))
3776 (clobber (reg:SI T_REG))])]
3777 ""
3778 {
3779 if (expand_ashiftrt (operands))
3780 DONE;
3781 else
3782 FAIL;
3783 })
3785 (define_insn "shar"
3786 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3787 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3788 (const_int 1)))
3789 (set (reg:SI T_REG)
3790 (and:SI (match_dup 1) (const_int 1)))]
3791 "TARGET_SH1"
3792 "shar %0"
3793 [(set_attr "type" "arith")])
3795 (define_insn "ashrsi3_k"
3796 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3797 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3798 (match_operand:SI 2 "const_int_operand" "M")))
3799 (clobber (reg:SI T_REG))]
3800 "TARGET_SH1 && INTVAL (operands[2]) == 1"
3801 "shar %0"
3802 [(set_attr "type" "arith")])
3804 (define_insn_and_split "ashrsi2_16"
3805 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3806 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "r")
3807 (const_int 16)))]
3808 "TARGET_SH1"
3809 "#"
3810 "&& 1"
3811 [(set (match_dup 0) (rotate:SI (match_dup 1) (const_int 16)))
3812 (set (match_dup 0) (sign_extend:SI (match_dup 2)))]
3813 {
3814 operands[2] = gen_lowpart (HImode, operands[0]);
3815 })
3817 (define_insn_and_split "ashrsi2_31"
3818 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3819 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3820 (const_int 31)))
3821 (clobber (reg:SI T_REG))]
3822 "TARGET_SH1"
3823 "#"
3824 "&& 1"
3825 [(const_int 0)]
3826 {
3827 emit_insn (gen_shll (operands[0], operands[1]));
3828 emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ()));
3829 DONE;
3830 })
3832 ;; If the shift amount is changed by combine it will try to plug the
3833 ;; use on the symbol of the library function and the PR clobber.
3834 (define_insn_and_split "*ashrsi2_31"
3835 [(set (match_operand:SI 0 "arith_reg_dest")
3836 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand")
3837 (const_int 31)))
3838 (clobber (reg:SI T_REG))
3839 (clobber (reg:SI PR_REG))
3840 (use (match_operand:SI 2 "symbol_ref_operand"))]
3841 "TARGET_SH1"
3842 "#"
3843 "&& 1"
3844 [(parallel [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))
3845 (clobber (reg:SI T_REG))])])
3847 (define_insn "ashrsi3_d"
3848 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3849 (ashiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3850 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r"))))]
3851 "TARGET_DYNSHIFT"
3852 "shad %2,%0"
3853 [(set_attr "type" "dyn_shift")])
3855 (define_insn "ashrsi3_n"
3856 [(set (reg:SI R4_REG)
3857 (ashiftrt:SI (reg:SI R4_REG)
3858 (match_operand:SI 0 "const_int_operand" "i,i")))
3859 (clobber (reg:SI T_REG))
3860 (clobber (reg:SI PR_REG))
3861 (use (match_operand:SI 1 "arith_reg_operand" "r,r"))
3862 (use (match_operand 2 "" "Z,Ccl"))]
3863 "TARGET_SH1"
3864 "@
3865 jsr @%1%#
3866 bsrf %1\n%O2:%#"
3867 [(set_attr "type" "sfunc")
3868 (set_attr "needs_delay_slot" "yes")])
3870 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3871 ;; DImode arithmetic shift right
3873 (define_expand "ashrdi3"
3874 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
3875 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
3876 (match_operand:DI 2 "immediate_operand" "")))
3877 (clobber (reg:SI T_REG))])]
3878 ""
3879 {
3880 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
3881 FAIL;
3882 })
3884 (define_insn_and_split "ashrdi3_k"
3885 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
3886 (ashiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
3887 (const_int 1)))
3888 (clobber (reg:SI T_REG))]
3889 "TARGET_SH1"
3890 "#"
3891 "&& reload_completed"
3892 [(const_int 0)]
3893 {
3894 rtx high = gen_highpart (SImode, operands[0]);
3895 rtx low = gen_lowpart (SImode, operands[0]);
3896 emit_insn (gen_shar (high, high));
3897 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ()));
3898 DONE;
3899 })
3901 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3902 ;; SImode logical shift right
3904 (define_expand "lshrsi3"
3905 [(set (match_operand:SI 0 "arith_reg_dest" "")
3906 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "")
3907 (match_operand:SI 2 "shift_count_operand" "")))]
3908 ""
3909 {
3910 /* If a dynamic shift is supposed to be used, expand the lshrsi3_d insn
3911 here, otherwise the pattern will never match due to the shift amount reg
3912 negation. */
3913 if (TARGET_DYNSHIFT
3914 && CONST_INT_P (operands[2]) && sh_dynamicalize_shift_p (operands[2]))
3915 {
3916 /* Don't force the constant into a reg yet. Some other optimizations
3917 might not see through the reg that holds the shift count. */
3918 if (sh_lshrsi_clobbers_t_reg_p (operands[2]))
3919 emit_insn (gen_lshrsi3_n_clobbers_t (operands[0], operands[1], operands[2]));
3920 else
3921 emit_insn (gen_lshrsi3_n (operands[0], operands[1], operands[2]));
3922 DONE;
3923 }
3925 if (TARGET_DYNSHIFT && ! CONST_INT_P (operands[2]))
3926 {
3927 rtx neg_count = gen_reg_rtx (SImode);
3928 emit_insn (gen_negsi2 (neg_count, operands[2]));
3929 emit_insn (gen_lshrsi3_d (operands[0], operands[1], neg_count));
3930 DONE;
3931 }
3933 /* If the lshrsi3_* insn is going to clobber the T_REG it must be
3934 expanded here. */
3935 if (CONST_INT_P (operands[2])
3936 && sh_lshrsi_clobbers_t_reg_p (operands[2])
3937 && ! sh_dynamicalize_shift_p (operands[2]))
3938 {
3939 emit_insn (gen_lshrsi3_n_clobbers_t (operands[0], operands[1],
3940 operands[2]));
3941 DONE;
3942 }
3944 /* Expand a library call for the dynamic shift. */
3945 if (!CONST_INT_P (operands[2]) && !TARGET_DYNSHIFT)
3946 {
3947 emit_move_insn (gen_rtx_REG (SImode, R4_REG), operands[1]);
3948 rtx funcaddr = gen_reg_rtx (Pmode);
3949 rtx lab = function_symbol (funcaddr, "__lshrsi3_r0", SFUNC_STATIC).lab;
3950 emit_insn (gen_lshrsi3_d_call (operands[0], operands[2], funcaddr, lab));
3951 DONE;
3952 }
3953 })
3955 (define_insn "lshrsi3_k"
3956 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3957 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3958 (match_operand:SI 2 "p27_rshift_count_operand" "P27")))]
3959 "TARGET_SH1"
3960 "shlr%O2 %0"
3961 [(set_attr "type" "arith")])
3963 (define_insn_and_split "lshrsi3_d"
3964 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
3965 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
3966 (neg:SI (match_operand:SI 2 "shift_count_operand" "r"))))]
3967 "TARGET_DYNSHIFT"
3968 "shld %2,%0"
3969 "&& CONST_INT_P (operands[2]) && ! sh_dynamicalize_shift_p (operands[2])
3970 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])"
3971 [(const_int 0)]
3972 {
3973 /* The shift count const_int is a negative value for all dynamic
3974 right shift insns. */
3975 operands[2] = GEN_INT (- INTVAL (operands[2]));
3977 if (satisfies_constraint_P27 (operands[2]))
3978 {
3979 /* This will not be done for a shift amount of 1, because it would
3980 clobber the T_REG. */
3981 emit_insn (gen_lshrsi3_k (operands[0], operands[1], operands[2]));
3982 DONE;
3983 }
3984 else if (! satisfies_constraint_P27 (operands[2]))
3985 {
3986 /* This must happen before reload, otherwise the constant will be moved
3987 into a register due to the "r" constraint, after which this split
3988 cannot be done anymore.
3989 Unfortunately the move insn will not always be eliminated.
3990 Also, here we must not create a shift sequence that clobbers the
3991 T_REG. */
3992 emit_move_insn (operands[0], operands[1]);
3993 gen_shifty_op (LSHIFTRT, operands);
3994 DONE;
3995 }
3997 FAIL;
3998 }
3999 [(set_attr "type" "dyn_shift")])
4001 ;; If dynamic shifts are not available use a library function.
4002 ;; By specifying the pattern we reduce the number of call clobbered regs.
4003 ;; In order to make combine understand the truncation of the shift amount
4004 ;; operand we have to allow it to use pseudo regs for the shift operands.
4005 (define_insn "lshrsi3_d_call"
4006 [(set (match_operand:SI 0 "arith_reg_dest" "=z,z")
4007 (lshiftrt:SI (reg:SI R4_REG)
4008 (and:SI (match_operand:SI 1 "arith_reg_operand" "z,z")
4009 (const_int 31))))
4010 (use (match_operand:SI 2 "arith_reg_operand" "r,r"))
4011 (use (match_operand 3 "" "Z,Ccl"))
4012 (clobber (reg:SI T_REG))
4013 (clobber (reg:SI PR_REG))]
4014 "TARGET_SH1 && !TARGET_DYNSHIFT"
4015 "@
4016 jsr @%2%#
4017 bsrf %2\n%O3:%#"
4018 [(set_attr "type" "sfunc")
4019 (set_attr "needs_delay_slot" "yes")])
4021 (define_insn_and_split "lshrsi3_n"
4022 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4023 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4024 (match_operand:SI 2 "not_p27_rshift_count_operand")))]
4025 "TARGET_SH1 && ! sh_lshrsi_clobbers_t_reg_p (operands[2])"
4026 "#"
4027 "&& (reload_completed
4028 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
4029 [(const_int 0)]
4030 {
4031 if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
4032 {
4033 /* If this pattern was picked and dynamic shifts are supported, switch
4034 to dynamic shift pattern before reload. */
4035 operands[2] = GEN_INT (- INTVAL (operands[2]));
4036 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2]));
4037 }
4038 else
4039 gen_shifty_op (LSHIFTRT, operands);
4041 DONE;
4042 })
4044 ;; The lshrsi3_n_clobbers_t pattern also works as a simplified version of
4045 ;; the shlr pattern.
4046 (define_insn_and_split "lshrsi3_n_clobbers_t"
4047 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4048 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4049 (match_operand:SI 2 "not_p27_rshift_count_operand")))
4050 (clobber (reg:SI T_REG))]
4051 "TARGET_SH1 && sh_lshrsi_clobbers_t_reg_p (operands[2])"
4052 "#"
4053 "&& (reload_completed || INTVAL (operands[2]) == 31
4054 || (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ()))"
4055 [(const_int 0)]
4056 {
4057 if (INTVAL (operands[2]) == 31)
4058 {
4059 emit_insn (gen_shll (operands[0], operands[1]));
4060 emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
4061 }
4062 else if (sh_dynamicalize_shift_p (operands[2]) && can_create_pseudo_p ())
4063 {
4064 /* If this pattern was picked and dynamic shifts are supported, switch
4065 to dynamic shift pattern before reload. */
4066 operands[2] = GEN_INT (- INTVAL (operands[2]));
4067 emit_insn (gen_lshrsi3_d (operands[0], operands[1], operands[2]));
4068 }
4069 else
4070 gen_shifty_op (LSHIFTRT, operands);
4072 DONE;
4073 })
4075 (define_insn "shlr"
4076 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4077 (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4078 (const_int 1)))
4079 (set (reg:SI T_REG)
4080 (and:SI (match_dup 1) (const_int 1)))]
4081 "TARGET_SH1"
4082 "shlr %0"
4083 [(set_attr "type" "arith")])
4085 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4086 ;; DImode logical shift right
4088 (define_expand "lshrdi3"
4089 [(parallel [(set (match_operand:DI 0 "arith_reg_operand" "")
4090 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "")
4091 (match_operand:DI 2 "immediate_operand" "")))
4092 (clobber (reg:SI T_REG))])]
4093 ""
4094 {
4095 if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 1)
4096 FAIL;
4097 })
4099 (define_insn_and_split "lshrdi3_k"
4100 [(set (match_operand:DI 0 "arith_reg_dest" "=r")
4101 (lshiftrt:DI (match_operand:DI 1 "arith_reg_operand" "0")
4102 (const_int 1)))
4103 (clobber (reg:SI T_REG))]
4104 "TARGET_SH1"
4105 "#"
4106 "&& reload_completed"
4107 [(const_int 0)]
4108 {
4109 rtx high = gen_highpart (SImode, operands[0]);
4110 rtx low = gen_lowpart (SImode, operands[0]);
4111 emit_insn (gen_shlr (high, high));
4112 emit_insn (gen_rotcr (low, low, get_t_reg_rtx ()));
4113 DONE;
4114 })
4116 ;; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4117 ;; Combined left/right shifts
4119 (define_split
4120 [(set (match_operand:SI 0 "register_operand" "")
4121 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4122 (match_operand:SI 2 "const_int_operand" ""))
4123 (match_operand:SI 3 "const_int_operand" "")))]
4124 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
4125 [(use (reg:SI R0_REG))]
4126 {
4127 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1]))
4128 FAIL;
4129 DONE;
4130 })
4132 (define_split
4133 [(set (match_operand:SI 0 "register_operand" "")
4134 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "")
4135 (match_operand:SI 2 "const_int_operand" ""))
4136 (match_operand:SI 3 "const_int_operand" "")))
4137 (clobber (reg:SI T_REG))]
4138 "TARGET_SH1 && reload_completed && (unsigned)INTVAL (operands[2]) < 32"
4139 [(use (reg:SI R0_REG))]
4140 {
4141 if (gen_shl_and (operands[0], operands[2], operands[3], operands[1]))
4142 FAIL;
4143 DONE;
4144 })
4146 (define_insn ""
4147 [(set (match_operand:SI 0 "register_operand" "=r")
4148 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
4149 (match_operand:SI 2 "const_int_operand" "n"))
4150 (match_operand:SI 3 "const_int_operand" "n")))
4151 (clobber (reg:SI T_REG))]
4152 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 1"
4153 "#"
4154 [(set (attr "length")
4155 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
4156 (const_string "4")
4157 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
4158 (const_string "6")
4159 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
4160 (const_string "8")
4161 (eq (symbol_ref "shl_and_length (insn)") (const_int 5))
4162 (const_string "10")
4163 (eq (symbol_ref "shl_and_length (insn)") (const_int 6))
4164 (const_string "12")
4165 (eq (symbol_ref "shl_and_length (insn)") (const_int 7))
4166 (const_string "14")
4167 (eq (symbol_ref "shl_and_length (insn)") (const_int 8))
4168 (const_string "16")]
4169 (const_string "18")))
4170 (set_attr "type" "arith")])
4172 (define_insn ""
4173 [(set (match_operand:SI 0 "register_operand" "=z")
4174 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "0")
4175 (match_operand:SI 2 "const_int_operand" "n"))
4176 (match_operand:SI 3 "const_int_operand" "n")))
4177 (clobber (reg:SI T_REG))]
4178 "TARGET_SH1 && shl_and_kind (operands[2], operands[3], 0) == 2"
4179 "#"
4180 [(set (attr "length")
4181 (cond [(eq (symbol_ref "shl_and_length (insn)") (const_int 2))
4182 (const_string "4")
4183 (eq (symbol_ref "shl_and_length (insn)") (const_int 3))
4184 (const_string "6")
4185 (eq (symbol_ref "shl_and_length (insn)") (const_int 4))
4186 (const_string "8")]
4187 (const_string "10")))
4188 (set_attr "type" "arith")])
4190 ;; shift left / and combination with a scratch register: The combine pass
4191 ;; does not accept the individual instructions, even though they are
4192 ;; cheap. But it needs a precise description so that it is usable after
4193 ;; reload.
4194 (define_insn "and_shl_scratch"
4195 [(set (match_operand:SI 0 "register_operand" "=r,&r")
4196 (lshiftrt:SI
4197 (ashift:SI
4198 (and:SI
4199 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0")
4200 (match_operand:SI 2 "const_int_operand" "N,n"))
4201 (match_operand:SI 3 "" "0,r"))
4202 (match_operand:SI 4 "const_int_operand" "n,n"))
4203 (match_operand:SI 5 "const_int_operand" "n,n")))
4204 (clobber (reg:SI T_REG))]
4205 "TARGET_SH1"
4206 "#"
4207 [(set (attr "length")
4208 (cond [(eq (symbol_ref "shl_and_scr_length (insn)") (const_int 2))
4209 (const_string "4")
4210 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 3))
4211 (const_string "6")
4212 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 4))
4213 (const_string "8")
4214 (eq (symbol_ref "shl_and_scr_length (insn)") (const_int 5))
4215 (const_string "10")]
4216 (const_string "12")))
4217 (set_attr "type" "arith")])
4219 (define_split
4220 [(set (match_operand:SI 0 "register_operand" "")
4221 (lshiftrt:SI
4222 (ashift:SI
4223 (and:SI
4224 (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
4225 (match_operand:SI 2 "const_int_operand" ""))
4226 (match_operand:SI 3 "register_operand" ""))
4227 (match_operand:SI 4 "const_int_operand" ""))
4228 (match_operand:SI 5 "const_int_operand" "")))
4229 (clobber (reg:SI T_REG))]
4230 "TARGET_SH1"
4231 [(use (reg:SI R0_REG))]
4232 {
4233 rtx and_source = operands[rtx_equal_p (operands[0], operands[1]) ? 3 : 1];
4235 if (INTVAL (operands[2]))
4236 {
4237 gen_shifty_op (LSHIFTRT, operands);
4238 }
4239 emit_insn (gen_andsi3 (operands[0], operands[0], and_source));
4240 operands[2] = operands[4];
4241 gen_shifty_op (ASHIFT, operands);
4242 if (INTVAL (operands[5]))
4243 {
4244 operands[2] = operands[5];
4245 gen_shifty_op (LSHIFTRT, operands);
4246 }
4247 DONE;
4248 })
4250 ;; signed left/right shift combination.
4251 (define_split
4252 [(set (match_operand:SI 0 "register_operand" "")
4253 (sign_extract:SI
4254 (ashift:SI (match_operand:SI 1 "register_operand" "")
4255 (match_operand:SI 2 "const_int_operand" ""))
4256 (match_operand:SI 3 "const_int_operand" "")
4257 (const_int 0)))
4258 (clobber (reg:SI T_REG))]
4259 "TARGET_SH1"
4260 [(use (reg:SI R0_REG))]
4261 {
4262 if (gen_shl_sext (operands[0], operands[2], operands[3], operands[1]))
4263 FAIL;
4264 DONE;
4265 })
4267 (define_insn "shl_sext_ext"
4268 [(set (match_operand:SI 0 "register_operand" "=r")
4269 (sign_extract:SI
4270 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4271 (match_operand:SI 2 "const_int_operand" "n"))
4272 (match_operand:SI 3 "const_int_operand" "n")
4273 (const_int 0)))
4274 (clobber (reg:SI T_REG))]
4275 "TARGET_SH1 && (unsigned)shl_sext_kind (operands[2], operands[3], 0) - 1 < 5"
4276 "#"
4277 [(set (attr "length")
4278 (cond [(match_test "shl_sext_length (insn)")
4279 (const_string "2")
4280 (eq (symbol_ref "shl_sext_length (insn)") (const_int 2))
4281 (const_string "4")
4282 (eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
4283 (const_string "6")
4284 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
4285 (const_string "8")
4286 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
4287 (const_string "10")
4288 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
4289 (const_string "12")
4290 (eq (symbol_ref "shl_sext_length (insn)") (const_int 7))
4291 (const_string "14")
4292 (eq (symbol_ref "shl_sext_length (insn)") (const_int 8))
4293 (const_string "16")]
4294 (const_string "18")))
4295 (set_attr "type" "arith")])
4297 (define_insn "shl_sext_sub"
4298 [(set (match_operand:SI 0 "register_operand" "=z")
4299 (sign_extract:SI
4300 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4301 (match_operand:SI 2 "const_int_operand" "n"))
4302 (match_operand:SI 3 "const_int_operand" "n")
4303 (const_int 0)))
4304 (clobber (reg:SI T_REG))]
4305 "TARGET_SH1 && (shl_sext_kind (operands[2], operands[3], 0) & ~1) == 6"
4306 "#"
4307 [(set (attr "length")
4308 (cond [(eq (symbol_ref "shl_sext_length (insn)") (const_int 3))
4309 (const_string "6")
4310 (eq (symbol_ref "shl_sext_length (insn)") (const_int 4))
4311 (const_string "8")
4312 (eq (symbol_ref "shl_sext_length (insn)") (const_int 5))
4313 (const_string "10")
4314 (eq (symbol_ref "shl_sext_length (insn)") (const_int 6))
4315 (const_string "12")]
4316 (const_string "14")))
4317 (set_attr "type" "arith")])
4319 ;; The xtrct_left and xtrct_right patterns are used in expansions of DImode
4320 ;; shifts by 16, and allow the xtrct instruction to be generated from C
4321 ;; source.
4322 (define_insn "xtrct_left"
4323 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4324 (ior:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
4325 (const_int 16))
4326 (lshiftrt:SI (match_operand:SI 2 "arith_reg_operand" "0")
4327 (const_int 16))))]
4328 "TARGET_SH1"
4329 "xtrct %1,%0"
4330 [(set_attr "type" "arith")])
4332 (define_insn "xtrct_right"
4333 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4334 (ior:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand" "0")
4335 (const_int 16))
4336 (ashift:SI (match_operand:SI 2 "arith_reg_operand" "r")
4337 (const_int 16))))]
4338 "TARGET_SH1"
4339 "xtrct %2,%0"
4340 [(set_attr "type" "arith")])
4342 ;; -------------------------------------------------------------------------
4343 ;; Unary arithmetic
4344 ;; -------------------------------------------------------------------------
4346 (define_insn "negc"
4347 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4348 (neg:SI (plus:SI (reg:SI T_REG)
4349 (match_operand:SI 1 "arith_reg_operand" "r"))))
4350 (set (reg:SI T_REG)
4351 (ne:SI (ior:SI (reg:SI T_REG) (match_dup 1))
4352 (const_int 0)))]
4353 "TARGET_SH1"
4354 "negc %1,%0"
4355 [(set_attr "type" "arith")])
4357 ;; A simplified version of the negc insn, where the exact value of the
4358 ;; T bit doesn't matter. This is easier for combine to pick up.
4359 ;; Notice that '0 - x - 1' is the same as '~x', thus we don't specify
4360 ;; extra patterns for this case.
4361 (define_insn_and_split "*negc"
4362 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4363 (minus:SI (neg:SI (match_operand:SI 1 "arith_reg_operand" "r"))
4364 (match_operand 2 "treg_set_expr")))
4365 (clobber (reg:SI T_REG))]
4366 "TARGET_SH1 && can_create_pseudo_p ()"
4367 "#"
4368 "&& 1"
4369 [(const_int 0)]
4370 {
4371 sh_split_treg_set_expr (operands[2], curr_insn);
4372 emit_insn (gen_negc (operands[0], operands[1]));
4373 DONE;
4374 });
4376 ;; Don't split into individual negc insns immediately so that neg:DI (abs:DI)
4377 ;; can be combined.
4378 (define_insn_and_split "negdi2"
4379 [(set (match_operand:DI 0 "arith_reg_dest")
4380 (neg:DI (match_operand:DI 1 "arith_reg_operand")))
4381 (clobber (reg:SI T_REG))]
4382 "TARGET_SH1"
4383 "#"
4384 "&& can_create_pseudo_p ()"
4385 [(const_int 0)]
4386 {
4387 emit_insn (gen_clrt ());
4388 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]),
4389 gen_lowpart (SImode, operands[1])));
4390 emit_insn (gen_negc (gen_highpart (SImode, operands[0]),
4391 gen_highpart (SImode, operands[1])));
4392 DONE;
4393 })
4395 (define_insn "negsi2"
4396 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4397 (neg:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
4398 "TARGET_SH1"
4399 "neg %1,%0"
4400 [(set_attr "type" "arith")])
4402 (define_insn_and_split "one_cmplsi2"
4403 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4404 (not:SI (match_operand:SI 1 "arith_reg_operand" "r")))]
4405 "TARGET_SH1"
4406 "not %1,%0"
4407 "&& can_create_pseudo_p ()"
4408 [(set (reg:SI T_REG) (ge:SI (match_dup 1) (const_int 0)))
4409 (set (match_dup 0) (reg:SI T_REG))]
4410 {
4411 /* PR 54685
4412 If the result of 'unsigned int <= 0x7FFFFFFF' ends up as the following
4413 sequence:
4415 (set (reg0) (not:SI (reg0) (reg1)))
4416 (parallel [(set (reg2) (lshiftrt:SI (reg0) (const_int 31)))
4417 (clobber (reg:SI T_REG))])
4419 ... match and combine the sequence manually in the split pass after the
4420 combine pass. Notice that combine does try the target pattern of this
4421 split, but if the pattern is added it interferes with other patterns, in
4422 particular with the div0s comparisons.
4423 This could also be done with a peephole but doing it here before register
4424 allocation can save one temporary.
4425 When we're here, the not:SI pattern obviously has been matched already
4426 and we only have to see whether the following insn is the left shift. */
4428 rtx_insn *i = next_nonnote_nondebug_insn_bb (curr_insn);
4429 if (i == NULL_RTX || !NONJUMP_INSN_P (i))
4430 FAIL;
4432 rtx p = PATTERN (i);
4433 if (GET_CODE (p) != PARALLEL || XVECLEN (p, 0) != 2)
4434 FAIL;
4436 rtx p0 = XVECEXP (p, 0, 0);
4437 rtx p1 = XVECEXP (p, 0, 1);
4439 if (/* (set (reg2) (lshiftrt:SI (reg0) (const_int 31))) */
4440 GET_CODE (p0) == SET
4441 && GET_CODE (XEXP (p0, 1)) == LSHIFTRT
4442 && REG_P (XEXP (XEXP (p0, 1), 0))
4443 && REGNO (XEXP (XEXP (p0, 1), 0)) == REGNO (operands[0])
4444 && CONST_INT_P (XEXP (XEXP (p0, 1), 1))
4445 && INTVAL (XEXP (XEXP (p0, 1), 1)) == 31
4447 /* (clobber (reg:SI T_REG)) */
4448 && GET_CODE (p1) == CLOBBER && REG_P (XEXP (p1, 0))
4449 && REGNO (XEXP (p1, 0)) == T_REG)
4450 {
4451 operands[0] = XEXP (p0, 0);
4452 set_insn_deleted (i);
4453 }
4454 else
4455 FAIL;
4456 }
4457 [(set_attr "type" "arith")])
4459 (define_insn_and_split "abs<mode>2"
4460 [(set (match_operand:SIDI 0 "arith_reg_dest")
4461 (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand")))
4462 (clobber (reg:SI T_REG))]
4463 "TARGET_SH1"
4464 "#"
4465 "&& can_create_pseudo_p ()"
4466 [(const_int 0)]
4467 {
4468 if (<MODE>mode == SImode)
4469 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
4470 else
4471 {
4472 rtx high_src = gen_highpart (SImode, operands[1]);
4473 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
4474 }
4476 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1],
4477 const1_rtx));
4478 DONE;
4479 })
4481 (define_insn_and_split "*negabs<mode>2"
4482 [(set (match_operand:SIDI 0 "arith_reg_dest")
4483 (neg:SIDI (abs:SIDI (match_operand:SIDI 1 "arith_reg_operand"))))
4484 (clobber (reg:SI T_REG))]
4485 "TARGET_SH1"
4486 "#"
4487 "&& can_create_pseudo_p ()"
4488 [(const_int 0)]
4489 {
4490 if (<MODE>mode == SImode)
4491 emit_insn (gen_cmpgesi_t (operands[1], const0_rtx));
4492 else
4493 {
4494 rtx high_src = gen_highpart (SImode, operands[1]);
4495 emit_insn (gen_cmpgesi_t (high_src, const0_rtx));
4496 }
4498 emit_insn (gen_neg<mode>_cond (operands[0], operands[1], operands[1],
4499 const0_rtx));
4500 DONE;
4501 })
4503 ;; The SH4 202 can do zero-offset branches without pipeline stalls.
4504 ;; This can be used as some kind of conditional execution, which is useful
4505 ;; for abs.
4506 ;; Actually the instruction scheduling should decide whether to use a
4507 ;; zero-offset branch or not for any generic case involving a single
4508 ;; instruction on SH4 202.
4509 (define_insn_and_split "negsi_cond"
4510 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4511 (if_then_else
4512 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand" "M,N"))
4513 (match_operand:SI 1 "arith_reg_operand" "0,0")
4514 (neg:SI (match_operand:SI 2 "arith_reg_operand" "r,r"))))]
4515 "TARGET_SH1 && TARGET_ZDCBRANCH"
4516 {
4517 static const char* alt[] =
4518 {
4519 "bt 0f" "\n"
4520 " neg %2,%0" "\n"
4521 "0:",
4523 "bf 0f" "\n"
4524 " neg %2,%0" "\n"
4525 "0:"
4526 };
4527 return alt[which_alternative];
4528 }
4529 "TARGET_SH1 && ! TARGET_ZDCBRANCH"
4530 [(const_int 0)]
4531 {
4532 rtx_code_label *skip_neg_label = gen_label_rtx ();
4534 emit_move_insn (operands[0], operands[1]);
4536 emit_jump_insn (INTVAL (operands[3])
4537 ? gen_branch_true (skip_neg_label)
4538 : gen_branch_false (skip_neg_label));
4540 emit_label_after (skip_neg_label,
4541 emit_insn (gen_negsi2 (operands[0], operands[1])));
4542 DONE;
4543 }
4544 [(set_attr "type" "arith") ;; poor approximation
4545 (set_attr "length" "4")])
4547 (define_insn_and_split "negdi_cond"
4548 [(set (match_operand:DI 0 "arith_reg_dest")
4549 (if_then_else
4550 (eq:SI (reg:SI T_REG) (match_operand:SI 3 "const_int_operand"))
4551 (match_operand:DI 1 "arith_reg_operand")
4552 (neg:DI (match_operand:DI 2 "arith_reg_operand"))))
4553 (clobber (reg:SI T_REG))]
4554 "TARGET_SH1"
4555 "#"
4556 "&& can_create_pseudo_p ()"
4557 [(const_int 0)]
4558 {
4559 rtx_code_label *skip_neg_label = gen_label_rtx ();
4561 emit_move_insn (operands[0], operands[1]);
4563 emit_jump_insn (INTVAL (operands[3])
4564 ? gen_branch_true (skip_neg_label)
4565 : gen_branch_false (skip_neg_label));
4567 if (!INTVAL (operands[3]))
4568 emit_insn (gen_clrt ());
4570 emit_insn (gen_negc (gen_lowpart (SImode, operands[0]),
4571 gen_lowpart (SImode, operands[1])));
4572 emit_label_after (skip_neg_label,
4573 emit_insn (gen_negc (gen_highpart (SImode, operands[0]),
4574 gen_highpart (SImode, operands[1]))));
4575 DONE;
4576 })
4578 (define_expand "bswapsi2"
4579 [(set (match_operand:SI 0 "arith_reg_dest" "")
4580 (bswap:SI (match_operand:SI 1 "arith_reg_operand" "")))]
4581 "TARGET_SH1"
4582 {
4583 if (! can_create_pseudo_p ())
4584 FAIL;
4585 else
4586 {
4587 rtx tmp0 = gen_reg_rtx (SImode);
4588 rtx tmp1 = gen_reg_rtx (SImode);
4590 emit_insn (gen_swapbsi2 (tmp0, operands[1]));
4591 emit_insn (gen_rotlsi3_16 (tmp1, tmp0));
4592 emit_insn (gen_swapbsi2 (operands[0], tmp1));
4593 DONE;
4594 }
4595 })
4597 (define_insn "swapbsi2"
4598 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4599 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "r")
4600 (const_int -65536)) ;; 0xFFFF0000
4601 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
4602 (const_int 65280))
4603 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
4604 (const_int 255)))))]
4605 "TARGET_SH1"
4606 "swap.b %1,%0"
4607 [(set_attr "type" "arith")])
4609 ;; The *swapbisi2_and_shl8 pattern helps the combine pass simplifying
4610 ;; partial byte swap expressions such as...
4611 ;; ((x & 0xFF) << 8) | ((x >> 8) & 0xFF).
4612 ;; ...which are currently not handled by the tree optimizers.
4613 ;; The combine pass will not initially try to combine the full expression,
4614 ;; but only some sub-expressions. In such a case the *swapbisi2_and_shl8
4615 ;; pattern acts as an intermediate pattern that will eventually lead combine
4616 ;; to the swapbsi2 pattern above.
4617 ;; As a side effect this also improves code that does (x & 0xFF) << 8
4618 ;; or (x << 8) & 0xFF00.
4619 (define_insn_and_split "*swapbisi2_and_shl8"
4620 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4621 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
4622 (const_int 8))
4623 (const_int 65280))
4624 (match_operand:SI 2 "arith_reg_operand" "r")))]
4625 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
4626 "#"
4627 "&& can_create_pseudo_p ()"
4628 [(const_int 0)]
4629 {
4630 rtx tmp0 = gen_reg_rtx (SImode);
4631 rtx tmp1 = gen_reg_rtx (SImode);
4633 emit_insn (gen_zero_extendqisi2 (tmp0, gen_lowpart (QImode, operands[1])));
4634 emit_insn (gen_swapbsi2 (tmp1, tmp0));
4635 emit_insn (gen_iorsi3 (operands[0], tmp1, operands[2]));
4636 DONE;
4637 })
4639 ;; The *swapbhisi2 pattern is, like the *swapbisi2_and_shl8 pattern, another
4640 ;; intermediate pattern that will help the combine pass arriving at swapbsi2.
4641 (define_insn_and_split "*swapbhisi2"
4642 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4643 (ior:SI (and:SI (ashift:SI (match_operand:SI 1 "arith_reg_operand" "r")
4644 (const_int 8))
4645 (const_int 65280))
4646 (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))))]
4647 "TARGET_SH1 && ! reload_in_progress && ! reload_completed"
4648 "#"
4649 "&& can_create_pseudo_p ()"
4650 [(const_int 0)]
4651 {
4652 rtx tmp = gen_reg_rtx (SImode);
4654 emit_insn (gen_zero_extendhisi2 (tmp, gen_lowpart (HImode, operands[1])));
4655 emit_insn (gen_swapbsi2 (operands[0], tmp));
4656 DONE;
4657 })
4659 ;; In some cases the swapbsi2 pattern might leave a sequence such as...
4660 ;; swap.b r4,r4
4661 ;; mov r4,r0
4662 ;;
4663 ;; which can be simplified to...
4664 ;; swap.b r4,r0
4665 (define_peephole2
4666 [(set (match_operand:SI 0 "arith_reg_dest" "")
4667 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "")
4668 (const_int -65536)) ;; 0xFFFF0000
4669 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
4670 (const_int 65280))
4671 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
4672 (const_int 255)))))
4673 (set (match_operand:SI 2 "arith_reg_dest" "")
4674 (match_dup 0))]
4675 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
4676 [(set (match_dup 2)
4677 (ior:SI (and:SI (match_operand:SI 1 "arith_reg_operand" "")
4678 (const_int -65536)) ;; 0xFFFF0000
4679 (ior:SI (and:SI (ashift:SI (match_dup 1) (const_int 8))
4680 (const_int 65280))
4681 (and:SI (ashiftrt:SI (match_dup 1) (const_int 8))
4682 (const_int 255)))))])
4683 \f
4684 ;; -------------------------------------------------------------------------
4685 ;; Zero extension instructions
4686 ;; -------------------------------------------------------------------------
4688 (define_expand "zero_extend<mode>si2"
4689 [(set (match_operand:SI 0 "arith_reg_dest")
4690 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand")))])
4692 (define_insn_and_split "*zero_extend<mode>si2_compact"
4693 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4694 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
4695 "TARGET_SH1"
4696 "extu.<bw> %1,%0"
4697 "&& can_create_pseudo_p ()"
4698 [(set (match_dup 0) (match_dup 2))]
4699 {
4700 /* Sometimes combine fails to combine a T bit or negated T bit store to a
4701 reg with a following zero extension. In the split pass after combine,
4702 try to figure out how the extended reg was set. If it originated from
4703 the T bit we can replace the zero extension with a reg move, which will
4704 be eliminated. Notice that this also helps the *cbranch_t splitter when
4705 it tries to post-combine tests and conditional branches, as it does not
4706 check for zero extensions. */
4707 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
4708 if (operands[2] == NULL_RTX)
4709 FAIL;
4710 }
4711 [(set_attr "type" "arith")])
4713 (define_insn "zero_extendqihi2"
4714 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4715 (zero_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
4716 "TARGET_SH1"
4717 "extu.b %1,%0"
4718 [(set_attr "type" "arith")])
4720 ;; SH2A supports two zero extending load instructions: movu.b and movu.w.
4721 ;; They could also be used for simple memory addresses like @Rn by setting
4722 ;; the displacement value to zero. However, doing so too early results in
4723 ;; missed opportunities for other optimizations such as post-inc or index
4724 ;; addressing loads.
4725 ;; We don't allow the zero extending loads to match during RTL expansion,
4726 ;; as this would pessimize other optimization opportunities such as bit
4727 ;; extractions of unsigned mems, where the zero extraction is irrelevant.
4728 ;; If the zero extracting mem loads are emitted early it will be more
4729 ;; difficult to change them back to sign extending loads (which are preferred).
4730 ;; The combine pass will also try to combine mem loads and zero extends,
4731 ;; which is prevented by 'sh_legitimate_combined_insn'.
4732 (define_insn "*zero_extend<mode>si2_disp_mem"
4733 [(set (match_operand:SI 0 "arith_reg_dest" "=r,r")
4734 (zero_extend:SI
4735 (match_operand:QIHI 1 "zero_extend_movu_operand" "Sdd,Sra")))]
4736 "TARGET_SH2A"
4737 "@
4738 movu.<bw> %1,%0
4739 movu.<bw> @(0,%t1),%0"
4740 [(set_attr "type" "load")
4741 (set_attr "length" "4")])
4743 ;; Convert the zero extending loads in sequences such as:
4744 ;; movu.b @(1,r5),r0 movu.w @(2,r5),r0
4745 ;; mov.b r0,@(1,r4) mov.b r0,@(1,r4)
4746 ;;
4747 ;; back to sign extending loads like:
4748 ;; mov.b @(1,r5),r0 mov.w @(2,r5),r0
4749 ;; mov.b r0,@(1,r4) mov.b r0,@(1,r4)
4750 ;;
4751 ;; if the extension type is irrelevant. The sign extending mov.{b|w} insn
4752 ;; is only 2 bytes in size if the displacement is {K04|K05}.
4753 ;; If the displacement is greater it doesn't matter, so we convert anyways.
4754 (define_peephole2
4755 [(set (match_operand:SI 0 "arith_reg_dest" "")
4756 (zero_extend:SI (match_operand 1 "displacement_mem_operand" "")))
4757 (set (match_operand 2 "nonimmediate_operand" "")
4758 (match_operand 3 "arith_reg_operand" ""))]
4759 "TARGET_SH2A
4760 && REGNO (operands[0]) == REGNO (operands[3])
4761 && peep2_reg_dead_p (2, operands[0])
4762 && GET_MODE_SIZE (GET_MODE (operands[2]))
4763 <= GET_MODE_SIZE (GET_MODE (operands[1]))"
4764 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
4765 (set (match_dup 2) (match_dup 3))])
4767 ;; Fold sequences such as
4768 ;; mov.b @r3,r7
4769 ;; extu.b r7,r7
4770 ;; into
4771 ;; movu.b @(0,r3),r7
4772 ;; This does not reduce the code size but the number of instructions is
4773 ;; halved, which results in faster code.
4774 (define_peephole2
4775 [(set (match_operand:SI 0 "arith_reg_dest" "")
4776 (sign_extend:SI (match_operand 1 "simple_mem_operand" "")))
4777 (set (match_operand:SI 2 "arith_reg_dest" "")
4778 (zero_extend:SI (match_operand 3 "arith_reg_operand" "")))]
4779 "TARGET_SH2A
4780 && GET_MODE (operands[1]) == GET_MODE (operands[3])
4781 && (GET_MODE (operands[1]) == QImode || GET_MODE (operands[1]) == HImode)
4782 && REGNO (operands[0]) == REGNO (operands[3])
4783 && (REGNO (operands[2]) == REGNO (operands[0])
4784 || peep2_reg_dead_p (2, operands[0]))"
4785 [(set (match_dup 2) (zero_extend:SI (match_dup 4)))]
4786 {
4787 operands[4]
4788 = replace_equiv_address (operands[1],
4789 gen_rtx_PLUS (SImode, XEXP (operands[1], 0),
4790 const0_rtx));
4791 })
4793 ;; -------------------------------------------------------------------------
4794 ;; Sign extension instructions
4795 ;; -------------------------------------------------------------------------
4797 ;; ??? This should be a define expand.
4798 ;; ??? Or perhaps it should be dropped?
4800 ;; convert_move generates good code for SH[1-4].
4802 (define_expand "extend<mode>si2"
4803 [(set (match_operand:SI 0 "arith_reg_dest")
4804 (sign_extend:SI (match_operand:QIHI 1 "general_extend_operand")))])
4806 (define_insn_and_split "*extend<mode>si2_compact_reg"
4807 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4808 (sign_extend:SI (match_operand:QIHI 1 "arith_reg_operand" "r")))]
4809 "TARGET_SH1"
4810 "exts.<bw> %1,%0"
4811 "&& can_create_pseudo_p ()"
4812 [(set (match_dup 0) (match_dup 2))]
4813 {
4814 /* Sometimes combine fails to combine a T bit or negated T bit store to a
4815 reg with a following sign extension. In the split pass after combine,
4816 try to figure the extended reg was set. If it originated from the T
4817 bit we can replace the sign extension with a reg move, which will be
4818 eliminated. */
4819 operands[2] = sh_try_omit_signzero_extend (operands[1], curr_insn);
4820 if (operands[2] == NULL_RTX)
4821 FAIL;
4822 }
4823 [(set_attr "type" "arith")])
4825 ;; FIXME: Fold non-SH2A and SH2A alternatives with "enabled" attribute.
4826 ;; See movqi insns.
4827 (define_insn "*extend<mode>si2_compact_mem_disp"
4828 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r")
4829 (sign_extend:SI
4830 (mem:QIHI
4831 (plus:SI
4832 (match_operand:SI 1 "arith_reg_operand" "%r,r")
4833 (match_operand:SI 2 "const_int_operand" "<disp04>,N")))))]
4834 "TARGET_SH1 && ! TARGET_SH2A
4835 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
4836 "@
4837 mov.<bw> @(%O2,%1),%0
4838 mov.<bw> @%1,%0"
4839 [(set_attr "type" "load")])
4841 (define_insn "*extend<mode>si2_compact_mem_disp"
4842 [(set (match_operand:SI 0 "arith_reg_dest" "=z,r,r")
4843 (sign_extend:SI
4844 (mem:QIHI
4845 (plus:SI
4846 (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
4847 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>")))))]
4848 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
4849 "@
4850 mov.<bw> @(%O2,%1),%0
4851 mov.<bw> @%1,%0
4852 mov.<bw> @(%O2,%1),%0"
4853 [(set_attr "type" "load")
4854 (set_attr "length" "2,2,4")])
4856 ;; The pre-dec and post-inc mems must be captured by the '<' and '>'
4857 ;; constraints, otherwise wrong code might get generated.
4858 (define_insn "*extend<mode>si2_predec"
4859 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
4860 (sign_extend:SI (match_operand:QIHI 1 "pre_dec_mem" "<")))]
4861 "TARGET_SH2A"
4862 "mov.<bw> %1,%0"
4863 [(set_attr "type" "load")])
4865 ;; The *_snd patterns will take care of other QImode/HImode addressing
4866 ;; modes than displacement addressing. They must be defined _after_ the
4867 ;; displacement addressing patterns. Otherwise the displacement addressing
4868 ;; patterns will not be picked.
4869 (define_insn "*extend<mode>si2_compact_snd"
4870 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
4871 (sign_extend:SI
4872 (match_operand:QIHI 1 "movsrc_no_disp_mem_operand" "Snd")))]
4873 "TARGET_SH1"
4874 "mov.<bw> %1,%0"
4875 [(set_attr "type" "load")])
4877 (define_expand "extendqihi2"
4878 [(set (match_operand:HI 0 "arith_reg_dest")
4879 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand")))]
4880 "TARGET_SH1")
4882 (define_insn "*extendqihi2_compact_reg"
4883 [(set (match_operand:HI 0 "arith_reg_dest" "=r")
4884 (sign_extend:HI (match_operand:QI 1 "arith_reg_operand" "r")))]
4885 "TARGET_SH1"
4886 "exts.b %1,%0"
4887 [(set_attr "type" "arith")])
4889 ;; -------------------------------------------------------------------------
4890 ;; Move instructions
4891 ;; -------------------------------------------------------------------------
4893 (define_expand "push"
4894 [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
4895 (match_operand:SI 0 "register_operand"))])
4897 (define_expand "pop"
4898 [(set (match_operand:SI 0 "register_operand")
4899 (mem:SI (post_inc:SI (reg:SI SP_REG))))])
4901 (define_expand "push_e"
4902 [(parallel [(set (mem:SF (pre_dec:SI (reg:SI SP_REG)))
4903 (match_operand:SF 0 "" ""))
4904 (use (reg:SI FPSCR_MODES_REG))
4905 (clobber (scratch:SI))])])
4907 (define_insn "push_fpul"
4908 [(set (mem:SF (pre_dec:SI (reg:SI SP_REG))) (reg:SF FPUL_REG))]
4909 "TARGET_SH2E"
4910 "sts.l fpul,@-r15"
4911 [(set_attr "type" "fstore")
4912 (set_attr "late_fp_use" "yes")
4913 (set_attr "hit_stack" "yes")])
4915 ;; DFmode pushes for sh4 require a lot of what is defined for movdf_i4,
4916 ;; so use that.
4917 (define_expand "push_4"
4918 [(parallel [(set (mem:DF (pre_dec:SI (reg:SI SP_REG)))
4919 (match_operand:DF 0 "" ""))
4920 (use (reg:SI FPSCR_MODES_REG))
4921 (clobber (scratch:SI))])])
4923 (define_expand "pop_e"
4924 [(parallel [(set (match_operand:SF 0 "" "")
4925 (mem:SF (post_inc:SI (reg:SI SP_REG))))
4926 (use (reg:SI FPSCR_MODES_REG))
4927 (clobber (scratch:SI))])])
4929 (define_insn "pop_fpul"
4930 [(set (reg:SF FPUL_REG) (mem:SF (post_inc:SI (reg:SI SP_REG))))]
4931 "TARGET_SH2E"
4932 "lds.l @r15+,fpul"
4933 [(set_attr "type" "load")
4934 (set_attr "hit_stack" "yes")])
4936 (define_expand "pop_4"
4937 [(parallel [(set (match_operand:DF 0 "" "")
4938 (mem:DF (post_inc:SI (reg:SI SP_REG))))
4939 (use (reg:SI FPSCR_MODES_REG))
4940 (clobber (scratch:SI))])])
4942 (define_expand "push_fpscr"
4943 [(const_int 0)]
4944 "TARGET_SH2E"
4945 {
4946 add_reg_note (
4947 emit_insn (
4948 gen_sts_fpscr (
4949 gen_frame_mem (SImode, gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)))),
4950 REG_INC, stack_pointer_rtx);
4951 DONE;
4952 })
4954 (define_expand "pop_fpscr"
4955 [(const_int 0)]
4956 "TARGET_SH2E"
4957 {
4958 add_reg_note (
4959 emit_insn (
4960 gen_lds_fpscr (
4961 gen_frame_mem (SImode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx)))),
4962 REG_INC, stack_pointer_rtx);
4963 DONE;
4964 })
4966 ;; The clrt and sett patterns can happen as the result of optimization and
4967 ;; insn expansion.
4968 ;; Comparisons might get simplified to a move of zero or 1 into the T reg.
4969 ;; In this case they might not disappear completely, because the T reg is
4970 ;; a fixed hard reg.
4971 ;; When DImode operations that use the T reg as carry/borrow are split into
4972 ;; individual SImode operations, the T reg is usually cleared before the
4973 ;; first SImode insn.
4974 (define_insn "clrt"
4975 [(set (reg:SI T_REG) (const_int 0))]
4976 "TARGET_SH1"
4977 "clrt"
4978 [(set_attr "type" "mt_group")])
4980 (define_insn "sett"
4981 [(set (reg:SI T_REG) (const_int 1))]
4982 "TARGET_SH1"
4983 "sett"
4984 [(set_attr "type" "mt_group")])
4986 ;; Use the combine pass to transform sequences such as
4987 ;; mov r5,r0
4988 ;; add #1,r0
4989 ;; shll2 r0
4990 ;; mov.l @(r0,r4),r0
4991 ;; into
4992 ;; shll2 r5
4993 ;; add r4,r5
4994 ;; mov.l @(4,r5),r0
4995 ;;
4996 ;; See also PR 39423.
4997 ;; Notice that these patterns have a T_REG clobber, because the shift
4998 ;; sequence that will be split out might clobber the T_REG. Ideally, the
4999 ;; clobber would be added conditionally, depending on the result of
5000 ;; sh_ashlsi_clobbers_t_reg_p. When splitting out the shifts we must go
5001 ;; through the ashlsi3 expander in order to get the right shift insn --
5002 ;; a T_REG clobbering or non-clobbering shift sequence or dynamic shift.
5003 ;; FIXME: Combine never tries this kind of patterns for DImode.
5004 (define_insn_and_split "*movsi_index_disp_load"
5005 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
5006 (match_operand:SI 1 "mem_index_disp_operand" "m"))
5007 (clobber (reg:SI T_REG))]
5008 "TARGET_SH1"
5009 "#"
5010 "&& can_create_pseudo_p ()"
5011 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
5012 (set (match_dup 0) (match_dup 7))]
5013 {
5014 rtx mem = operands[1];
5015 rtx plus0_rtx = XEXP (mem, 0);
5016 rtx plus1_rtx = XEXP (plus0_rtx, 0);
5017 rtx mult_rtx = XEXP (plus1_rtx, 0);
5019 operands[1] = XEXP (mult_rtx, 0);
5020 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
5021 operands[3] = XEXP (plus1_rtx, 1);
5022 operands[4] = XEXP (plus0_rtx, 1);
5023 operands[5] = gen_reg_rtx (SImode);
5024 operands[6] = gen_reg_rtx (SImode);
5025 operands[7] =
5026 replace_equiv_address (mem,
5027 gen_rtx_PLUS (SImode, operands[6], operands[4]));
5029 emit_insn (gen_ashlsi3 (operands[5], operands[1], operands[2]));
5030 })
5032 (define_insn_and_split "*movhi_index_disp_load"
5033 [(set (match_operand:SI 0 "arith_reg_dest")
5034 (SZ_EXTEND:SI (match_operand:HI 1 "mem_index_disp_operand")))
5035 (clobber (reg:SI T_REG))]
5036 "TARGET_SH1"
5037 "#"
5038 "&& can_create_pseudo_p ()"
5039 [(const_int 0)]
5040 {
5041 rtx mem = operands[1];
5042 rtx plus0_rtx = XEXP (mem, 0);
5043 rtx plus1_rtx = XEXP (plus0_rtx, 0);
5044 rtx mult_rtx = XEXP (plus1_rtx, 0);
5046 rtx op_1 = XEXP (mult_rtx, 0);
5047 rtx op_2 = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
5048 rtx op_3 = XEXP (plus1_rtx, 1);
5049 rtx op_4 = XEXP (plus0_rtx, 1);
5050 rtx op_5 = gen_reg_rtx (SImode);
5051 rtx op_6 = gen_reg_rtx (SImode);
5052 rtx op_7 = replace_equiv_address (mem, gen_rtx_PLUS (SImode, op_6, op_4));
5054 emit_insn (gen_ashlsi3 (op_5, op_1, op_2));
5055 emit_insn (gen_addsi3 (op_6, op_5, op_3));
5057 if (<CODE> == SIGN_EXTEND)
5058 {
5059 emit_insn (gen_extendhisi2 (operands[0], op_7));
5060 DONE;
5061 }
5062 else if (<CODE> == ZERO_EXTEND)
5063 {
5064 /* On SH2A the movu.w insn can be used for zero extending loads. */
5065 if (TARGET_SH2A)
5066 emit_insn (gen_zero_extendhisi2 (operands[0], op_7));
5067 else
5068 {
5069 emit_insn (gen_extendhisi2 (operands[0], op_7));
5070 emit_insn (gen_zero_extendhisi2 (operands[0],
5071 gen_lowpart (HImode, operands[0])));
5072 }
5073 DONE;
5074 }
5075 else
5076 FAIL;
5077 })
5079 (define_insn_and_split "*mov<mode>_index_disp_store"
5080 [(set (match_operand:HISI 0 "mem_index_disp_operand" "=m")
5081 (match_operand:HISI 1 "arith_reg_operand" "r"))
5082 (clobber (reg:SI T_REG))]
5083 "TARGET_SH1"
5084 "#"
5085 "&& can_create_pseudo_p ()"
5086 [(set (match_dup 6) (plus:SI (match_dup 5) (match_dup 3)))
5087 (set (match_dup 7) (match_dup 1))]
5088 {
5089 rtx mem = operands[0];
5090 rtx plus0_rtx = XEXP (mem, 0);
5091 rtx plus1_rtx = XEXP (plus0_rtx, 0);
5092 rtx mult_rtx = XEXP (plus1_rtx, 0);
5094 operands[0] = XEXP (mult_rtx, 0);
5095 operands[2] = GEN_INT (exact_log2 (INTVAL (XEXP (mult_rtx, 1))));
5096 operands[3] = XEXP (plus1_rtx, 1);
5097 operands[4] = XEXP (plus0_rtx, 1);
5098 operands[5] = gen_reg_rtx (SImode);
5099 operands[6] = gen_reg_rtx (SImode);
5100 operands[7] =
5101 replace_equiv_address (mem,
5102 gen_rtx_PLUS (SImode, operands[6], operands[4]));
5104 emit_insn (gen_ashlsi3 (operands[5], operands[0], operands[2]));
5105 })
5107 ;; t/r must come after r/r, lest reload will try to reload stuff like
5108 ;; (set (subreg:SI (mem:QI (plus:SI (reg:SI SP_REG) (const_int 12)) 0) 0)
5109 ;; (made from (set (subreg:SI (reg:QI ###) 0) ) into T.
5110 ;; Notice that although this pattern allows movi20 and movi20s on non-SH2A,
5111 ;; those alternatives will not be taken, as they will be converted into
5112 ;; PC-relative loads.
5113 (define_insn "movsi_i"
5114 [(set (match_operand:SI 0 "general_movdst_operand"
5115 "=r,r, r, r, r, r,r,r,m,<,<,x,l,x,l,r")
5116 (match_operand:SI 1 "general_movsrc_operand"
5117 " Q,r,I08,I20,I28,mr,x,l,r,x,l,r,r,>,>,i"))]
5118 "TARGET_SH1 && !TARGET_FPU_ANY
5119 && (register_operand (operands[0], SImode)
5120 || register_operand (operands[1], SImode))"
5121 "@
5122 mov.l %1,%0
5123 mov %1,%0
5124 mov %1,%0
5125 movi20 %1,%0
5126 movi20s %1,%0
5127 mov.l %1,%0
5128 sts %1,%0
5129 sts %1,%0
5130 mov.l %1,%0
5131 sts.l %1,%0
5132 sts.l %1,%0
5133 lds %1,%0
5134 lds %1,%0
5135 lds.l %1,%0
5136 lds.l %1,%0
5137 fake %1,%0"
5138 [(set_attr "type" "pcload_si,move,movi8,move,move,load_si,mac_gp,prget,store,
5139 mac_mem,pstore,gp_mac,prset,mem_mac,pload,pcload_si")
5140 (set_attr_alternative "length"
5141 [(const_int 2)
5142 (const_int 2)
5143 (const_int 2)
5144 (const_int 4)
5145 (const_int 4)
5146 (if_then_else (match_operand 1 "long_displacement_mem_operand")
5147 (const_int 4) (const_int 2))
5148 (const_int 2)
5149 (const_int 2)
5150 (if_then_else (match_operand 0 "long_displacement_mem_operand")
5151 (const_int 4) (const_int 2))
5152 (const_int 2)
5153 (const_int 2)
5154 (const_int 2)
5155 (const_int 2)
5156 (const_int 2)
5157 (const_int 2)
5158 (const_int 2)])])
5160 ;; t/r must come after r/r, lest reload will try to reload stuff like
5161 ;; (subreg:SI (reg:SF FR14_REG) 0) into T (compiling stdlib/strtod.c -m3e -O2)
5162 ;; ??? This allows moves from macl to fpul to be recognized, but these moves
5163 ;; will require a reload.
5164 ;; ??? We can't include f/f because we need the proper FPSCR setting when
5165 ;; TARGET_FMOVD is in effect, and mode switching is done before reload.
5166 ;; Notice that although this pattern allows movi20 and movi20s on non-SH2A,
5167 ;; those alternatives will not be taken, as they will be converted into
5168 ;; PC-relative loads.
5169 (define_insn "movsi_ie"
5170 [(set (match_operand:SI 0 "general_movdst_operand"
5171 "=r,r, r, r, r, r,r,r,mr,<,<,x,l,x,l,y,<,r,y,r,*f, y,*f,y")
5172 (match_operand:SI 1 "general_movsrc_operand"
5173 " Q,r,I08,I20,I28,mr,x,l, r,x,l,r,r,>,>,>,y,i,r,y, y,*f,*f,y"))]
5174 "TARGET_SH1 && TARGET_FPU_ANY
5175 && ((register_operand (operands[0], SImode)
5176 && !fpscr_operand (operands[0], SImode))
5177 || (register_operand (operands[1], SImode)
5178 && !fpscr_operand (operands[1], SImode)))"
5179 "@
5180 mov.l %1,%0
5181 mov %1,%0
5182 mov %1,%0
5183 movi20 %1,%0
5184 movi20s %1,%0
5185 mov.l %1,%0
5186 sts %1,%0
5187 sts %1,%0
5188 mov.l %1,%0
5189 sts.l %1,%0
5190 sts.l %1,%0
5191 lds %1,%0
5192 lds %1,%0
5193 lds.l %1,%0
5194 lds.l %1,%0
5195 lds.l %1,%0
5196 sts.l %1,%0
5197 fake %1,%0
5198 lds %1,%0
5199 sts %1,%0
5200 fsts fpul,%0
5201 flds %1,fpul
5202 fmov %1,%0
5203 ! move optimized away"
5204 [(set_attr "type" "pcload_si,move,movi8,move,move,load_si,mac_gp,prget,store,
5205 mac_mem,pstore,gp_mac,prset,mem_mac,pload,load,fstore,
5206 pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
5207 (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
5208 (set_attr_alternative "length"
5209 [(const_int 2)
5210 (const_int 2)
5211 (const_int 2)
5212 (const_int 4)
5213 (const_int 4)
5214 (if_then_else (match_operand 1 "long_displacement_mem_operand")
5215 (const_int 4) (const_int 2))
5216 (const_int 2)
5217 (const_int 2)
5218 (if_then_else (match_operand 0 "long_displacement_mem_operand")
5219 (const_int 4) (const_int 2))
5220 (const_int 2)
5221 (const_int 2)
5222 (const_int 2)
5223 (const_int 2)
5224 (const_int 2)
5225 (const_int 2)
5226 (const_int 2)
5227 (const_int 2)
5228 (const_int 2)
5229 (const_int 2)
5230 (const_int 2)
5231 (const_int 2)
5232 (const_int 2)
5233 (const_int 2)
5234 (const_int 0)])])
5236 ;; Notice that although this pattern allows movi20 and movi20s on non-SH2A,
5237 ;; those alternatives will not be taken, as they will be converted into
5238 ;; PC-relative loads.
5239 (define_insn "movsi_i_lowpart"
5240 [(set (strict_low_part
5241 (match_operand:SI 0 "general_movdst_operand"
5242 "+r,r, r, r, r, r,r,r,m,r"))
5243 (match_operand:SI 1 "general_movsrc_operand"
5244 " Q,r,I08,I20,I28,mr,x,l,r,i"))]
5245 "TARGET_SH1
5246 && (register_operand (operands[0], SImode)
5247 || register_operand (operands[1], SImode))"
5248 "@
5249 mov.l %1,%0
5250 mov %1,%0
5251 mov %1,%0
5252 movi20 %1,%0
5253 movi20s %1,%0
5254 mov.l %1,%0
5255 sts %1,%0
5256 sts %1,%0
5257 mov.l %1,%0
5258 fake %1,%0"
5259 [(set_attr "type" "pcload,move,movi8,move,move,load,mac_gp,prget,store,
5260 pcload")
5261 (set_attr_alternative "length"
5262 [(const_int 2)
5263 (const_int 2)
5264 (const_int 2)
5265 (const_int 4)
5266 (const_int 4)
5267 (if_then_else (match_operand 1 "long_displacement_mem_operand")
5268 (const_int 4) (const_int 2))
5269 (const_int 2)
5270 (const_int 2)
5271 (if_then_else (match_operand 0 "long_displacement_mem_operand")
5272 (const_int 4) (const_int 2))
5273 (const_int 2)])])
5275 (define_insn_and_split "load_ra"
5276 [(set (match_operand:SI 0 "general_movdst_operand" "")
5277 (unspec:SI [(match_operand:SI 1 "register_operand" "")] UNSPEC_RA))]
5278 "TARGET_SH1"
5279 "#"
5280 "&& ! currently_expanding_to_rtl"
5281 [(set (match_dup 0) (match_dup 1))])
5283 (define_expand "movsi"
5284 [(set (match_operand:SI 0 "general_movdst_operand" "")
5285 (match_operand:SI 1 "general_movsrc_operand" ""))]
5286 ""
5287 {
5288 prepare_move_operands (operands, SImode);
5289 })
5291 (define_expand "ic_invalidate_line"
5292 [(parallel [(unspec_volatile [(match_operand:SI 0 "register_operand")
5293 (match_dup 1)] UNSPEC_ICACHE)
5294 (clobber (scratch:SI))])]
5295 "TARGET_HARD_SH4"
5296 {
5297 emit_insn (gen_ic_invalidate_line_sh4a (operands[0]));
5298 DONE;
5299 })
5301 ;; The address %0 is assumed to be 4-aligned at least. Thus, by ORing
5302 ;; 0xf0000008, we get the low-oder bits *1*00 (binary), which fits
5303 ;; the requirement *1*00 for associative address writes. The alignment of
5304 ;; %0 implies that its least significant bit is cleared,
5305 ;; thus we clear the V bit of a matching entry if there is one.
5306 (define_insn "ic_invalidate_line_i"
5307 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
5308 (match_operand:SI 1 "register_operand" "r")]
5309 UNSPEC_ICACHE)
5310 (clobber (match_scratch:SI 2 "=&r"))]
5311 "TARGET_HARD_SH4"
5312 {
5313 return "ocbwb @%0" "\n"
5314 " extu.w %0,%2" "\n"
5315 " or %1,%2" "\n"
5316 " mov.l %0,@%2";
5317 }
5318 [(set_attr "length" "8")
5319 (set_attr "type" "cwb")])
5321 (define_insn "ic_invalidate_line_sh4a"
5322 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
5323 UNSPEC_ICACHE)]
5324 "TARGET_SH4A || TARGET_SH4_300"
5325 {
5326 return "ocbwb @%0" "\n"
5327 " synco" "\n"
5328 " icbi @%0";
5329 }
5330 [(set_attr "length" "6")
5331 (set_attr "type" "cwb")])
5333 (define_expand "mov<mode>"
5334 [(set (match_operand:QIHI 0 "general_movdst_operand")
5335 (match_operand:QIHI 1 "general_movsrc_operand"))]
5336 ""
5337 {
5338 if (can_create_pseudo_p () && CONST_INT_P (operands[1])
5339 && REG_P (operands[0]) && REGNO (operands[0]) != R0_REG)
5340 {
5341 rtx reg = gen_reg_rtx(SImode);
5342 emit_move_insn (reg, operands[1]);
5343 operands[1] = gen_lowpart (<MODE>mode, reg);
5344 }
5346 prepare_move_operands (operands, <MODE>mode);
5347 })
5349 ;; The pre-dec and post-inc mems must be captured by the '<' and '>'
5350 ;; constraints, otherwise wrong code might get generated.
5351 (define_insn "*mov<mode>_load_predec"
5352 [(set (match_operand:QIHISI 0 "arith_reg_dest" "=z")
5353 (match_operand:QIHISI 1 "pre_dec_mem" "<"))]
5354 "TARGET_SH2A"
5355 "mov.<bwl> %1,%0"
5356 [(set_attr "type" "load")])
5358 (define_insn "*mov<mode>_store_postinc"
5359 [(set (match_operand:QIHISI 0 "post_inc_mem" "=>")
5360 (match_operand:QIHISI 1 "arith_reg_operand" "z"))]
5361 "TARGET_SH2A"
5362 "mov.<bwl> %1,%0"
5363 [(set_attr "type" "store")])
5365 ;; Specifying the displacement addressing load / store patterns separately
5366 ;; before the generic movqi / movhi pattern allows controlling the order
5367 ;; in which load / store insns are selected in a more fine grained way.
5368 ;; FIXME: The non-SH2A and SH2A variants should be combined by adding
5369 ;; "enabled" attribute as it is done in other targets.
5370 (define_insn "*mov<mode>_store_mem_disp04"
5371 [(set (mem:QIHI
5372 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r,r")
5373 (match_operand:SI 1 "const_int_operand" "<disp04>,N")))
5374 (match_operand:QIHI 2 "arith_reg_operand" "z,r"))]
5375 "TARGET_SH1 && sh_legitimate_index_p (<MODE>mode, operands[1], false, true)"
5376 "@
5377 mov.<bw> %2,@(%O1,%0)
5378 mov.<bw> %2,@%0"
5379 [(set_attr "type" "store")])
5381 (define_insn "*mov<mode>_store_mem_disp12"
5382 [(set (mem:QIHI
5383 (plus:SI (match_operand:SI 0 "arith_reg_operand" "%r")
5384 (match_operand:SI 1 "const_int_operand" "<disp12>")))
5385 (match_operand:QIHI 2 "arith_reg_operand" "r"))]
5386 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[1], true, true)"
5387 "mov.<bw> %2,@(%O1,%0)"
5388 [(set_attr "type" "store")
5389 (set_attr "length" "4")])
5391 (define_insn "*mov<mode>_load_mem_disp04"
5392 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r")
5393 (mem:QIHI
5394 (plus:SI (match_operand:SI 1 "arith_reg_operand" "%r,r")
5395 (match_operand:SI 2 "const_int_operand" "<disp04>,N"))))]
5396 "TARGET_SH1 && ! TARGET_SH2A
5397 && sh_legitimate_index_p (<MODE>mode, operands[2], false, true)"
5398 "@
5399 mov.<bw> @(%O2,%1),%0
5400 mov.<bw> @%1,%0"
5401 [(set_attr "type" "load")])
5403 (define_insn "*mov<mode>_load_mem_disp12"
5404 [(set (match_operand:QIHI 0 "arith_reg_dest" "=z,r,r")
5405 (mem:QIHI
5406 (plus:SI
5407 (match_operand:SI 1 "arith_reg_operand" "%r,r,r")
5408 (match_operand:SI 2 "const_int_operand" "<disp04>,N,<disp12>"))))]
5409 "TARGET_SH2A && sh_legitimate_index_p (<MODE>mode, operands[2], true, true)"
5410 "@
5411 mov.<bw> @(%O2,%1),%0
5412 mov.<bw> @%1,%0
5413 mov.<bw> @(%O2,%1),%0"
5414 [(set_attr "type" "load")
5415 (set_attr "length" "2,2,4")])
5417 ;; The order of the constraint alternatives is important here.
5418 ;; Q/r has to come first, otherwise PC relative loads might wrongly get
5419 ;; placed into delay slots. Since there is no QImode PC relative load, the
5420 ;; Q constraint and general_movsrc_operand will reject it for QImode.
5421 ;; The Sid/Ssd alternatives should come before Sdd in order to avoid
5422 ;; a preference of using r0 als the register operand for addressing modes
5423 ;; other than displacement addressing.
5424 ;; The Sdd alternatives allow only r0 as register operand, even though on
5425 ;; SH2A any register could be allowed by switching to a 32 bit insn.
5426 ;; Generally sticking to the r0 is preferrable, since it generates smaller
5427 ;; code. Obvious r0 reloads can then be eliminated with a peephole on SH2A.
5428 (define_insn "*mov<mode>"
5429 [(set (match_operand:QIHI 0 "general_movdst_operand"
5430 "=r,r,r,Sid,^zr,Ssd,r, Sdd,z, r,l")
5431 (match_operand:QIHI 1 "general_movsrc_operand"
5432 "Q,r,i,^zr,Sid,r, Ssd,z, Sdd,l,r"))]
5433 "TARGET_SH1
5434 && (arith_reg_operand (operands[0], <MODE>mode)
5435 || arith_reg_operand (operands[1], <MODE>mode))"
5436 "@
5437 mov.<bw> %1,%0
5438 mov %1,%0
5439 mov %1,%0
5440 mov.<bw> %1,%0
5441 mov.<bw> %1,%0
5442 mov.<bw> %1,%0
5443 mov.<bw> %1,%0
5444 mov.<bw> %1,%0
5445 mov.<bw> %1,%0
5446 sts %1,%0
5447 lds %1,%0"
5448 [(set_attr "type" "pcload,move,movi8,store,load,store,load,store,load,prget,prset")
5449 (set (attr "length")
5450 (cond [(match_operand 0 "long_displacement_mem_operand") (const_int 4)
5451 (match_operand 1 "long_displacement_mem_operand") (const_int 4)]
5452 (const_int 2)))])
5454 ;; x/r can be created by inlining/cse, e.g. for execute/961213-1.c
5455 ;; compiled with -m2 -ml -O3 -funroll-loops
5456 (define_insn "*movdi_i"
5457 [(set (match_operand:DI 0 "general_movdst_operand" "=r,r,r,m, r,r,r,*!x")
5458 (match_operand:DI 1 "general_movsrc_operand" " Q,r,m,r,I08,i,x, r"))]
5459 "TARGET_SH1
5460 && (arith_reg_operand (operands[0], DImode)
5461 || arith_reg_operand (operands[1], DImode))"
5462 {
5463 return output_movedouble (insn, operands, DImode);
5464 }
5465 [(set_attr "type" "pcload,move,load,store,move,pcload,move,move")
5466 (set (attr "length")
5467 (cond [(match_operand 0 "long_displacement_mem_operand") (const_int 8)
5468 (match_operand 1 "long_displacement_mem_operand") (const_int 8)]
5469 (const_int 4)))])
5471 ;; If the output is a register and the input is memory or a register, we have
5472 ;; to be careful and see which word needs to be loaded first.
5473 (define_split
5474 [(set (match_operand:DI 0 "general_movdst_operand" "")
5475 (match_operand:DI 1 "general_movsrc_operand" ""))]
5476 "TARGET_SH1 && reload_completed"
5477 [(set (match_dup 2) (match_dup 3))
5478 (set (match_dup 4) (match_dup 5))]
5479 {
5480 int regno;
5482 if ((MEM_P (operands[0])
5483 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
5484 || (MEM_P (operands[1])
5485 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
5486 FAIL;
5488 switch (GET_CODE (operands[0]))
5489 {
5490 case REG:
5491 regno = REGNO (operands[0]);
5492 break;
5493 case SUBREG:
5494 regno = subreg_regno (operands[0]);
5495 break;
5496 case MEM:
5497 regno = -1;
5498 break;
5499 default:
5500 gcc_unreachable ();
5501 }
5503 if (regno == -1 || ! refers_to_regno_p (regno, operands[1]))
5504 {
5505 operands[2] = operand_subword (operands[0], 0, 0, DImode);
5506 operands[3] = operand_subword (operands[1], 0, 0, DImode);
5507 operands[4] = operand_subword (operands[0], 1, 0, DImode);
5508 operands[5] = operand_subword (operands[1], 1, 0, DImode);
5509 }
5510 else
5511 {
5512 operands[2] = operand_subword (operands[0], 1, 0, DImode);
5513 operands[3] = operand_subword (operands[1], 1, 0, DImode);
5514 operands[4] = operand_subword (operands[0], 0, 0, DImode);
5515 operands[5] = operand_subword (operands[1], 0, 0, DImode);
5516 }
5518 if (operands[2] == 0 || operands[3] == 0
5519 || operands[4] == 0 || operands[5] == 0)
5520 FAIL;
5521 })
5523 (define_expand "movdi"
5524 [(set (match_operand:DI 0 "general_movdst_operand" "")
5525 (match_operand:DI 1 "general_movsrc_operand" ""))]
5526 ""
5527 {
5528 prepare_move_operands (operands, DImode);
5530 /* When the dest operand is (R0, R1) register pair, split it to
5531 two movsi of which dest is R1 and R0 so as to lower R0-register
5532 pressure on the first movsi. Apply only for simple source not
5533 to make complex rtl here. */
5534 if (REG_P (operands[0]) && REGNO (operands[0]) == R0_REG
5535 && REG_P (operands[1]) && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER)
5536 {
5537 emit_insn (gen_movsi (gen_rtx_REG (SImode, R1_REG),
5538 gen_rtx_SUBREG (SImode, operands[1], 4)));
5539 emit_insn (gen_movsi (gen_rtx_REG (SImode, R0_REG),
5540 gen_rtx_SUBREG (SImode, operands[1], 0)));
5541 DONE;
5542 }
5543 })
5545 ;; FIXME: This should be a define_insn_and_split.
5546 (define_insn "movdf_k"
5547 [(set (match_operand:DF 0 "general_movdst_operand" "=r, r,r,m")
5548 (match_operand:DF 1 "general_movsrc_operand" " r,FQ,m,r"))]
5549 "TARGET_SH1
5550 && (!TARGET_FPU_DOUBLE || reload_completed
5551 /* ??? We provide some insn so that direct_{load,store}[DFmode] get set */
5552 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
5553 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
5554 && (arith_reg_operand (operands[0], DFmode)
5555 || arith_reg_operand (operands[1], DFmode))"
5556 {
5557 return output_movedouble (insn, operands, DFmode);
5558 }
5559 [(set_attr "type" "move,pcload,load,store")
5560 (set (attr "length")
5561 (cond [(match_operand 0 "long_displacement_mem_operand") (const_int 8)
5562 (match_operand 1 "long_displacement_mem_operand") (const_int 8)]
5563 (const_int 4)))])
5565 ;; All alternatives of movdf_i4 are split for ! TARGET_FMOVD.
5566 ;; However, the d/F/c/z alternative cannot be split directly; it is converted
5567 ;; with special code in machine_dependent_reorg into a load of the R0_REG and
5568 ;; the d/m/c/X alternative, which is split later into single-precision
5569 ;; instructions. And when not optimizing, no splits are done before fixing
5570 ;; up pcloads, so we need usable length information for that.
5571 ;; A DF constant load results in the following worst-case 8 byte sequence:
5572 ;; mova ...,r0
5573 ;; fmov.s @r0+,..
5574 ;; fmov.s @r0,...
5575 ;; add #-4,r0
5576 (define_insn "movdf_i4"
5577 [(set (match_operand:DF 0 "general_movdst_operand"
5578 "=d,r, d,d,m, r,r,m,!??r,!???d")
5579 (match_operand:DF 1 "general_movsrc_operand"
5580 " d,r, F,m,d,FQ,m,r, d, r"))
5581 (use (reg:SI FPSCR_MODES_REG))
5582 (clobber (match_scratch:SI 2
5583 "=X,X,&z,X,X, X,X,X, X, X"))]
5584 "TARGET_FPU_DOUBLE
5585 && (arith_reg_operand (operands[0], DFmode)
5586 || arith_reg_operand (operands[1], DFmode))"
5587 {
5588 switch (which_alternative)
5589 {
5590 case 0:
5591 if (TARGET_FMOVD)
5592 return "fmov %1,%0";
5593 else if (REGNO (operands[0]) != REGNO (operands[1]) + 1)
5594 return "fmov %R1,%R0" "\n"
5595 " fmov %S1,%S0";
5596 else
5597 return "fmov %S1,%S0" "\n"
5598 " fmov %R1,%R0";
5599 case 3:
5600 case 4:
5601 return "fmov.d %1,%0";
5602 default:
5603 return "#";
5604 }
5605 }
5606 [(set_attr_alternative "length"
5607 [(if_then_else (eq_attr "fmovd" "yes") (const_int 2) (const_int 4))
5608 (const_int 4)
5609 (if_then_else (eq_attr "fmovd" "yes") (const_int 4) (const_int 8))
5610 (if_then_else (match_operand 1 "displacement_mem_operand")
5611 (if_then_else (eq_attr "fmovd" "yes")
5612 (const_int 4) (const_int 8))
5613 (if_then_else (eq_attr "fmovd" "yes")
5614 (const_int 2) (const_int 4)))
5615 (if_then_else (match_operand 0 "displacement_mem_operand")
5616 (if_then_else (eq_attr "fmovd" "yes")
5617 (const_int 4) (const_int 8))
5618 (if_then_else (eq_attr "fmovd" "yes")
5619 (const_int 2) (const_int 4)))
5620 (const_int 4)
5621 (if_then_else (match_operand 1 "long_displacement_mem_operand")
5622 (const_int 8) (const_int 4))
5623 (if_then_else (match_operand 0 "long_displacement_mem_operand")
5624 (const_int 8) (const_int 4))
5625 (const_int 8)
5626 (const_int 8)])
5627 (set_attr "type" "fmove,move,pcfload,fload,fstore,pcload,load,store,load,
5628 fload")
5629 (set_attr "late_fp_use" "*,*,*,*,yes,*,*,*,*,*")
5630 (set (attr "fp_mode") (if_then_else (eq_attr "fmovd" "yes")
5631 (const_string "double")
5632 (const_string "none")))])
5634 ;; Moving DFmode between fp/general registers through memory
5635 ;; (the top of the stack) is faster than moving through fpul even for
5636 ;; little endian. Because the type of an instruction is important for its
5637 ;; scheduling, it is beneficial to split these operations, rather than
5638 ;; emitting them in one single chunk, even if this will expose a stack
5639 ;; use that will prevent scheduling of other stack accesses beyond this
5640 ;; instruction.
5641 (define_split
5642 [(set (match_operand:DF 0 "register_operand")
5643 (match_operand:DF 1 "register_operand"))
5644 (use (reg:SI FPSCR_MODES_REG))
5645 (clobber (match_scratch:SI 2))]
5646 "TARGET_FPU_DOUBLE && reload_completed
5647 && (true_regnum (operands[0]) < 16) != (true_regnum (operands[1]) < 16)"
5648 [(const_int 0)]
5649 {
5650 rtx insn, tos;
5652 tos = gen_tmp_stack_mem (DFmode, gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx));
5653 insn = emit_insn (gen_movdf_i4 (tos, operands[1]));
5654 add_reg_note (insn, REG_INC, stack_pointer_rtx);
5655 tos = gen_tmp_stack_mem (DFmode, gen_rtx_POST_INC (Pmode, stack_pointer_rtx));
5656 insn = emit_insn (gen_movdf_i4 (operands[0], tos));
5657 add_reg_note (insn, REG_INC, stack_pointer_rtx);
5658 DONE;
5659 })
5661 ;; local-alloc sometimes allocates scratch registers even when not required,
5662 ;; so we must be prepared to handle these.
5664 ;; Remove the use and clobber from a movdf_i4 so that we can use movdf_k.
5665 (define_split
5666 [(set (match_operand:DF 0 "general_movdst_operand" "")
5667 (match_operand:DF 1 "general_movsrc_operand" ""))
5668 (use (reg:SI FPSCR_MODES_REG))
5669 (clobber (match_scratch:SI 2))]
5670 "TARGET_FPU_DOUBLE
5671 && reload_completed
5672 && true_regnum (operands[0]) < 16
5673 && true_regnum (operands[1]) < 16"
5674 [(set (match_dup 0) (match_dup 1))]
5675 {
5676 /* If this was a reg <-> mem operation with base + index reg addressing,
5677 we have to handle this in a special way. */
5678 rtx mem = operands[0];
5679 int store_p = 1;
5680 if (! memory_operand (mem, DFmode))
5681 {
5682 mem = operands[1];
5683 store_p = 0;
5684 }
5685 if (GET_CODE (mem) == SUBREG && SUBREG_BYTE (mem) == 0)
5686 mem = SUBREG_REG (mem);
5687 if (MEM_P (mem))
5688 {
5689 rtx addr = XEXP (mem, 0);
5690 if (GET_CODE (addr) == PLUS
5691 && REG_P (XEXP (addr, 0))
5692 && REG_P (XEXP (addr, 1)))
5693 {
5694 int offset;
5695 rtx reg0 = gen_rtx_REG (Pmode, 0);
5696 rtx regop = operands[store_p], word0 ,word1;
5698 if (GET_CODE (regop) == SUBREG)
5699 alter_subreg (®op, true);
5700 if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
5701 offset = 2;
5702 else
5703 offset = 4;
5704 mem = copy_rtx (mem);
5705 PUT_MODE (mem, SImode);
5706 word0 = gen_rtx_SUBREG (SImode, regop, 0);
5707 alter_subreg (&word0, true);
5708 word1 = gen_rtx_SUBREG (SImode, regop, 4);
5709 alter_subreg (&word1, true);
5710 if (store_p || ! refers_to_regno_p (REGNO (word0), addr))
5711 {
5712 emit_insn (store_p
5713 ? gen_movsi_ie (mem, word0)
5714 : gen_movsi_ie (word0, mem));
5715 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
5716 mem = copy_rtx (mem);
5717 emit_insn (store_p
5718 ? gen_movsi_ie (mem, word1)
5719 : gen_movsi_ie (word1, mem));
5720 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
5721 }
5722 else
5723 {
5724 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (offset)));
5725 emit_insn (gen_movsi_ie (word1, mem));
5726 emit_insn (gen_addsi3 (reg0, reg0, GEN_INT (-offset)));
5727 mem = copy_rtx (mem);
5728 emit_insn (gen_movsi_ie (word0, mem));
5729 }
5730 DONE;
5731 }
5732 }
5733 })
5735 ;; Split away the clobber of r0 after machine_dependent_reorg has fixed pcloads.
5736 (define_split
5737 [(set (match_operand:DF 0 "register_operand" "")
5738 (match_operand:DF 1 "memory_operand" ""))
5739 (use (reg:SI FPSCR_MODES_REG))
5740 (clobber (reg:SI R0_REG))]
5741 "TARGET_FPU_DOUBLE && reload_completed"
5742 [(parallel [(set (match_dup 0) (match_dup 1))
5743 (use (reg:SI FPSCR_MODES_REG))
5744 (clobber (scratch:SI))])]
5745 "")
5747 (define_expand "reload_indf__frn"
5748 [(parallel [(set (match_operand:DF 0 "register_operand" "=a")
5749 (match_operand:DF 1 "immediate_operand" "FQ"))
5750 (use (reg:SI FPSCR_MODES_REG))
5751 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
5752 "TARGET_SH1"
5753 "")
5755 (define_expand "reload_outdf__RnFRm"
5756 [(parallel [(set (match_operand:DF 0 "register_operand" "=r,f")
5757 (match_operand:DF 1 "register_operand" "af,r"))
5758 (clobber (match_operand:SI 2 "register_operand" "=&y,y"))])]
5759 "TARGET_SH1"
5760 "")
5762 ;; Simplify no-op moves.
5763 (define_split
5764 [(set (match_operand:SF 0 "register_operand" "")
5765 (match_operand:SF 1 "register_operand" ""))
5766 (use (reg:SI FPSCR_MODES_REG))
5767 (clobber (match_scratch:SI 2))]
5768 "TARGET_SH2E && reload_completed
5769 && true_regnum (operands[0]) == true_regnum (operands[1])"
5770 [(set (match_dup 0) (match_dup 0))]
5771 "")
5773 ;; fmovd substitute post-reload splits
5774 (define_split
5775 [(set (match_operand:DF 0 "register_operand" "")
5776 (match_operand:DF 1 "register_operand" ""))
5777 (use (reg:SI FPSCR_MODES_REG))
5778 (clobber (match_scratch:SI 2))]
5779 "TARGET_SH4 && ! TARGET_FMOVD && reload_completed
5780 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
5781 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
5782 [(const_int 0)]
5783 {
5784 int dst = true_regnum (operands[0]), src = true_regnum (operands[1]);
5785 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst),
5786 gen_rtx_REG (SFmode, src)));
5787 emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode, dst + 1),
5788 gen_rtx_REG (SFmode, src + 1)));
5789 DONE;
5790 })
5792 (define_split
5793 [(set (match_operand:DF 0 "register_operand" "")
5794 (mem:DF (match_operand:SI 1 "register_operand" "")))
5795 (use (reg:SI FPSCR_MODES_REG))
5796 (clobber (match_scratch:SI 2))]
5797 "TARGET_FPU_DOUBLE && ! TARGET_FMOVD && reload_completed
5798 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))
5799 && find_regno_note (insn, REG_DEAD, true_regnum (operands[1]))"
5800 [(const_int 0)]
5801 {
5802 int regno = true_regnum (operands[0]);
5803 rtx insn;
5804 rtx mem = SET_SRC (XVECEXP (PATTERN (curr_insn), 0, 0));
5805 rtx mem2
5806 = change_address (mem, SFmode, gen_rtx_POST_INC (Pmode, operands[1]));
5807 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
5808 regno + SH_REG_MSW_OFFSET),
5809 mem2));
5810 add_reg_note (insn, REG_INC, operands[1]);
5811 insn = emit_insn (gen_movsf_ie (gen_rtx_REG (SFmode,
5812 regno + SH_REG_LSW_OFFSET),
5813 change_address (mem, SFmode, NULL_RTX)));
5814 DONE;
5815 })
5817 (define_split
5818 [(set (match_operand:DF 0 "register_operand" "")
5819 (match_operand:DF 1 "memory_operand" ""))
5820 (use (reg:SI FPSCR_MODES_REG))
5821 (clobber (match_scratch:SI 2))]
5822 "TARGET_FPU_DOUBLE && ! TARGET_FMOVD && reload_completed
5823 && FP_OR_XD_REGISTER_P (true_regnum (operands[0]))"
5824 [(const_int 0)]
5825 {
5826 int regno = true_regnum (operands[0]);
5827 rtx addr, insn;
5828 rtx mem2 = change_address (operands[1], SFmode, NULL_RTX);
5829 rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET);
5830 rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET);
5832 operands[1] = copy_rtx (mem2);
5833 addr = XEXP (mem2, 0);
5835 switch (GET_CODE (addr))
5836 {
5837 case REG:
5838 /* This is complicated. If the register is an arithmetic register
5839 we can just fall through to the REG+DISP case below. Otherwise
5840 we have to use a combination of POST_INC and REG addressing... */
5841 if (! arith_reg_operand (operands[1], SFmode))
5842 {
5843 XEXP (mem2, 0) = addr = gen_rtx_POST_INC (SImode, addr);
5844 insn = emit_insn (gen_movsf_ie (reg0, mem2));
5845 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5847 emit_insn (gen_movsf_ie (reg1, operands[1]));
5849 /* If we have modified the stack pointer, the value that we have
5850 read with post-increment might be modified by an interrupt,
5851 so write it back. */
5852 if (REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
5853 emit_insn (gen_push_e (reg0));
5854 else
5855 emit_insn (gen_addsi3 (XEXP (operands[1], 0), XEXP (operands[1], 0),
5856 GEN_INT (-4)));
5857 break;
5858 }
5859 /* Fall through. */
5861 case PLUS:
5862 emit_insn (gen_movsf_ie (reg0, operands[1]));
5863 operands[1] = copy_rtx (operands[1]);
5864 XEXP (operands[1], 0) = plus_constant (Pmode, addr, 4);
5865 emit_insn (gen_movsf_ie (reg1, operands[1]));
5866 break;
5868 case POST_INC:
5869 insn = emit_insn (gen_movsf_ie (reg0, operands[1]));
5870 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5872 insn = emit_insn (gen_movsf_ie (reg1, operands[1]));
5873 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5874 break;
5876 default:
5877 debug_rtx (addr);
5878 gcc_unreachable ();
5879 }
5881 DONE;
5882 })
5884 (define_split
5885 [(set (match_operand:DF 0 "memory_operand" "")
5886 (match_operand:DF 1 "register_operand" ""))
5887 (use (reg:SI FPSCR_MODES_REG))
5888 (clobber (match_scratch:SI 2))]
5889 "TARGET_FPU_DOUBLE && ! TARGET_FMOVD && reload_completed
5890 && FP_OR_XD_REGISTER_P (true_regnum (operands[1]))"
5891 [(const_int 0)]
5892 {
5893 int regno = true_regnum (operands[1]);
5894 rtx insn, addr;
5895 rtx reg0 = gen_rtx_REG (SFmode, regno + SH_REG_MSW_OFFSET);
5896 rtx reg1 = gen_rtx_REG (SFmode, regno + SH_REG_LSW_OFFSET);
5898 operands[0] = copy_rtx (operands[0]);
5899 PUT_MODE (operands[0], SFmode);
5900 addr = XEXP (operands[0], 0);
5902 switch (GET_CODE (addr))
5903 {
5904 case REG:
5905 /* This is complicated. If the register is an arithmetic register
5906 we can just fall through to the REG+DISP case below. Otherwise
5907 we have to use a combination of REG and PRE_DEC addressing... */
5908 if (! arith_reg_operand (operands[0], SFmode))
5909 {
5910 emit_insn (gen_addsi3 (addr, addr, GEN_INT (4)));
5911 emit_insn (gen_movsf_ie (operands[0], reg1));
5913 operands[0] = copy_rtx (operands[0]);
5914 XEXP (operands[0], 0) = addr = gen_rtx_PRE_DEC (SImode, addr);
5916 insn = emit_insn (gen_movsf_ie (operands[0], reg0));
5917 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5918 break;
5919 }
5920 /* Fall through. */
5922 case PLUS:
5923 /* Since REG+DISP addressing has already been decided upon by gcc
5924 we can rely upon it having chosen an arithmetic register as the
5925 register component of the address. Just emit the lower numbered
5926 register first, to the lower address, then the higher numbered
5927 register to the higher address. */
5928 emit_insn (gen_movsf_ie (operands[0], reg0));
5930 operands[0] = copy_rtx (operands[0]);
5931 XEXP (operands[0], 0) = plus_constant (Pmode, addr, 4);
5933 emit_insn (gen_movsf_ie (operands[0], reg1));
5934 break;
5936 case PRE_DEC:
5937 /* This is easy. Output the word to go to the higher address
5938 first (ie the word in the higher numbered register) then the
5939 word to go to the lower address. */
5941 insn = emit_insn (gen_movsf_ie (operands[0], reg1));
5942 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5944 insn = emit_insn (gen_movsf_ie (operands[0], reg0));
5945 add_reg_note (insn, REG_INC, XEXP (addr, 0));
5946 break;
5948 default:
5949 /* FAIL; */
5950 debug_rtx (addr);
5951 gcc_unreachable ();
5952 }
5954 DONE;
5955 })
5957 ;; If the output is a register and the input is memory or a register, we have
5958 ;; to be careful and see which word needs to be loaded first.
5959 (define_split
5960 [(set (match_operand:DF 0 "general_movdst_operand" "")
5961 (match_operand:DF 1 "general_movsrc_operand" ""))]
5962 "TARGET_SH1 && reload_completed"
5963 [(set (match_dup 2) (match_dup 3))
5964 (set (match_dup 4) (match_dup 5))]
5965 {
5966 int regno;
5968 if ((MEM_P (operands[0])
5969 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
5970 || (MEM_P (operands[1])
5971 && GET_CODE (XEXP (operands[1], 0)) == POST_INC))
5972 FAIL;
5974 switch (GET_CODE (operands[0]))
5975 {
5976 case REG:
5977 regno = REGNO (operands[0]);
5978 break;
5979 case SUBREG:
5980 regno = subreg_regno (operands[0]);
5981 break;
5982 case MEM:
5983 regno = -1;
5984 break;
5985 default:
5986 gcc_unreachable ();
5987 }
5989 if (regno == -1 || ! refers_to_regno_p (regno, operands[1]))
5990 {
5991 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
5992 operands[3] = operand_subword (operands[1], 0, 0, DFmode);
5993 operands[4] = operand_subword (operands[0], 1, 0, DFmode);
5994 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
5995 }
5996 else
5997 {
5998 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
5999 operands[3] = operand_subword (operands[1], 1, 0, DFmode);
6000 operands[4] = operand_subword (operands[0], 0, 0, DFmode);
6001 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
6002 }
6004 if (operands[2] == 0 || operands[3] == 0
6005 || operands[4] == 0 || operands[5] == 0)
6006 FAIL;
6007 })
6009 (define_expand "movdf"
6010 [(set (match_operand:DF 0 "general_movdst_operand" "")
6011 (match_operand:DF 1 "general_movsrc_operand" ""))]
6012 ""
6013 {
6014 prepare_move_operands (operands, DFmode);
6015 if (TARGET_FPU_DOUBLE)
6016 {
6017 emit_insn (gen_movdf_i4 (operands[0], operands[1]));
6018 DONE;
6019 }
6020 })
6022 ;; FIXME Although the movsf_i pattern is not used when there's an FPU,
6023 ;; it somehow influences some RA choices also on FPU targets.
6024 ;; For non-FPU targets it's actually not needed.
6025 (define_insn "movsf_i"
6026 [(set (match_operand:SF 0 "general_movdst_operand" "=r,r, r, r,m,l,r")
6027 (match_operand:SF 1 "general_movsrc_operand" "r,G,FQ,mr,r,r,l"))]
6028 "TARGET_SH1
6029 && (! TARGET_SH2E
6030 /* ??? We provide some insn so that direct_{load,store}[SFmode] get set */
6031 || (REG_P (operands[0]) && REGNO (operands[0]) == 3)
6032 || (REG_P (operands[1]) && REGNO (operands[1]) == 3))
6033 && (arith_reg_operand (operands[0], SFmode)
6034 || arith_reg_operand (operands[1], SFmode))"
6035 "@
6036 mov %1,%0
6037 mov #0,%0
6038 mov.l %1,%0
6039 mov.l %1,%0
6040 mov.l %1,%0
6041 lds %1,%0
6042 sts %1,%0"
6043 [(set_attr "type" "move,move,pcload,load,store,move,move")
6044 (set_attr_alternative "length"
6045 [(const_int 2)
6046 (const_int 2)
6047 (if_then_else (match_operand 1 "long_displacement_mem_operand")
6048 (const_int 4) (const_int 2))
6049 (if_then_else (match_operand 1 "long_displacement_mem_operand")
6050 (const_int 4) (const_int 2))
6051 (if_then_else (match_operand 0 "long_displacement_mem_operand")
6052 (const_int 4) (const_int 2))
6053 (const_int 2)
6054 (const_int 2)])])
6056 ;; We may not split the ry/yr/XX alternatives to movsi_ie, since
6057 ;; update_flow_info would not know where to put REG_EQUAL notes
6058 ;; when the destination changes mode.
6059 (define_insn "movsf_ie"
6060 [(set (match_operand:SF 0 "general_movdst_operand"
6061 "=f,r,f,f,fy, f,m, r, r,m,f,y,y,rf,r,y,<,y,y")
6062 (match_operand:SF 1 "general_movsrc_operand"
6063 " f,r,G,H,FQ,mf,f,FQ,mr,r,y,f,>,fr,y,r,y,>,y"))
6064 (use (reg:SI FPSCR_MODES_REG))
6065 (clobber (match_scratch:SI 2 "=X,X,X,X,&z, X,X, X, X,X,X,X,X, y,X,X,X,X,X"))]
6066 "TARGET_SH2E
6067 && (arith_reg_operand (operands[0], SFmode)
6068 || fpul_operand (operands[0], SFmode)
6069 || arith_reg_operand (operands[1], SFmode)
6070 || fpul_operand (operands[1], SFmode))"
6071 "@
6072 fmov %1,%0
6073 mov %1,%0
6074 fldi0 %0
6075 fldi1 %0
6076 #
6077 fmov.s %1,%0
6078 fmov.s %1,%0
6079 mov.l %1,%0
6080 mov.l %1,%0
6081 mov.l %1,%0
6082 fsts fpul,%0
6083 flds %1,fpul
6084 lds.l %1,%0
6085 #
6086 sts %1,%0
6087 lds %1,%0
6088 sts.l %1,%0
6089 lds.l %1,%0
6090 ! move optimized away"
6091 [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load,
6092 store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil")
6093 (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
6094 (set_attr_alternative "length"
6095 [(const_int 2)
6096 (const_int 2)
6097 (const_int 2)
6098 (const_int 2)
6099 (const_int 4)
6100 (if_then_else (match_operand 1 "displacement_mem_operand")
6101 (const_int 4) (const_int 2))
6102 (if_then_else (match_operand 0 "displacement_mem_operand")
6103 (const_int 4) (const_int 2))
6104 (const_int 2)
6105 (if_then_else (match_operand 1 "long_displacement_mem_operand")
6106 (const_int 4) (const_int 2))
6107 (if_then_else (match_operand 0 "long_displacement_mem_operand")
6108 (const_int 4) (const_int 2))
6109 (const_int 2)
6110 (const_int 2)
6111 (const_int 2)
6112 (const_int 4)
6113 (const_int 2)
6114 (const_int 2)
6115 (const_int 2)
6116 (const_int 2)
6117 (const_int 0)])
6118 (set_attr_alternative "fp_mode"
6119 [(if_then_else (eq_attr "fmovd" "yes")
6120 (const_string "single") (const_string "none"))
6121 (const_string "none")
6122 (const_string "single")
6123 (const_string "single")
6124 (const_string "none")
6125 (if_then_else (eq_attr "fmovd" "yes")
6126 (const_string "single") (const_string "none"))
6127 (if_then_else (eq_attr "fmovd" "yes")
6128 (const_string "single") (const_string "none"))
6129 (const_string "none")
6130 (const_string "none")
6131 (const_string "none")
6132 (const_string "none")
6133 (const_string "none")
6134 (const_string "none")
6135 (const_string "none")
6136 (const_string "none")
6137 (const_string "none")
6138 (const_string "none")
6139 (const_string "none")
6140 (const_string "none")])])
6142 (define_insn_and_split "movsf_ie_ra"
6143 [(set (match_operand:SF 0 "general_movdst_operand"
6144 "=f,r,f,f,fy,f,m, r,r,m,f,y,y,rf,r,y,<,y,y")
6145 (match_operand:SF 1 "general_movsrc_operand"
6146 " f,r,G,H,FQ,m,f,FQ,m,r,y,f,>,fr,y,r,y,>,y"))
6147 (use (reg:SI FPSCR_MODES_REG))
6148 (clobber (match_scratch:SF 2 "=r,r,X,X,&z,r,r, X,r,r,r,r,r, y,r,r,r,r,r"))
6149 (const_int 0)]
6150 "TARGET_SH2E
6151 && (arith_reg_operand (operands[0], SFmode)
6152 || fpul_operand (operands[0], SFmode)
6153 || arith_reg_operand (operands[1], SFmode)
6154 || fpul_operand (operands[1], SFmode))"
6155 "@
6156 fmov %1,%0
6157 mov %1,%0
6158 fldi0 %0
6159 fldi1 %0
6160 #
6161 fmov.s %1,%0
6162 fmov.s %1,%0
6163 mov.l %1,%0
6164 mov.l %1,%0
6165 mov.l %1,%0
6166 fsts fpul,%0
6167 flds %1,fpul
6168 lds.l %1,%0
6169 #
6170 sts %1,%0
6171 lds %1,%0
6172 sts.l %1,%0
6173 lds.l %1,%0
6174 ! move optimized away"
6175 "reload_completed
6176 && sh_movsf_ie_ra_split_p (operands[0], operands[1], operands[2])"
6177 [(const_int 0)]
6178 {
6179 if (! rtx_equal_p (operands[0], operands[1]))
6180 {
6181 emit_insn (gen_movsf_ie (operands[2], operands[1]));
6182 emit_insn (gen_movsf_ie (operands[0], operands[2]));
6183 }
6184 }
6185 [(set_attr "type" "fmove,move,fmove,fmove,pcfload,fload,fstore,pcload,load,
6186 store,fmove,fmove,load,*,fpul_gp,gp_fpul,fstore,load,nil")
6187 (set_attr "late_fp_use" "*,*,*,*,*,*,yes,*,*,*,*,*,*,*,yes,*,yes,*,*")
6188 (set_attr_alternative "length"
6189 [(const_int 2)
6190 (const_int 2)
6191 (const_int 2)
6192 (const_int 2)
6193 (const_int 4)
6194 (if_then_else (match_operand 1 "displacement_mem_operand")
6195 (const_int 4) (const_int 2))
6196 (if_then_else (match_operand 0 "displacement_mem_operand")
6197 (const_int 4) (const_int 2))
6198 (const_int 2)
6199 (if_then_else (match_operand 1 "long_displacement_mem_operand")
6200 (const_int 4) (const_int 2))
6201 (if_then_else (match_operand 0 "long_displacement_mem_operand")
6202 (const_int 4) (const_int 2))
6203 (const_int 2)
6204 (const_int 2)
6205 (const_int 2)
6206 (const_int 4)
6207 (const_int 2)
6208 (const_int 2)
6209 (const_int 2)
6210 (const_int 2)
6211 (const_int 0)])
6212 (set_attr_alternative "fp_mode"
6213 [(if_then_else (eq_attr "fmovd" "yes")
6214 (const_string "single") (const_string "none"))
6215 (const_string "none")
6216 (const_string "single")
6217 (const_string "single")
6218 (const_string "none")
6219 (if_then_else (eq_attr "fmovd" "yes")
6220 (const_string "single") (const_string "none"))
6221 (if_then_else (eq_attr "fmovd" "yes")
6222 (const_string "single") (const_string "none"))
6223 (const_string "none")
6224 (const_string "none")
6225 (const_string "none")
6226 (const_string "none")
6227 (const_string "none")
6228 (const_string "none")
6229 (const_string "none")
6230 (const_string "none")
6231 (const_string "none")
6232 (const_string "none")
6233 (const_string "none")
6234 (const_string "none")])])
6236 (define_split
6237 [(set (match_operand:SF 0 "register_operand" "")
6238 (match_operand:SF 1 "register_operand" ""))
6239 (use (reg:SI FPSCR_MODES_REG))
6240 (clobber (reg:SI FPUL_REG))]
6241 "TARGET_SH1"
6242 [(parallel [(set (reg:SF FPUL_REG) (match_dup 1))
6243 (use (reg:SI FPSCR_MODES_REG))
6244 (clobber (scratch:SI))])
6245 (parallel [(set (match_dup 0) (reg:SF FPUL_REG))
6246 (use (reg:SI FPSCR_MODES_REG))
6247 (clobber (scratch:SI))])]
6248 "")
6250 (define_expand "movsf"
6251 [(set (match_operand:SF 0 "general_movdst_operand" "")
6252 (match_operand:SF 1 "general_movsrc_operand" ""))]
6253 ""
6254 {
6255 prepare_move_operands (operands, SFmode);
6256 if (TARGET_SH2E)
6257 {
6258 if (lra_in_progress)
6259 {
6260 if (GET_CODE (operands[0]) == SCRATCH)
6261 DONE;
6262 emit_insn (gen_movsf_ie_ra (operands[0], operands[1]));
6263 DONE;
6264 }
6266 emit_insn (gen_movsf_ie (operands[0], operands[1]));
6267 DONE;
6268 }
6269 })
6271 (define_expand "reload_insf__frn"
6272 [(parallel [(set (match_operand:SF 0 "register_operand" "=a")
6273 (match_operand:SF 1 "immediate_operand" "FQ"))
6274 (use (reg:SI FPSCR_MODES_REG))
6275 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
6276 "TARGET_SH1"
6277 "")
6279 (define_expand "reload_insi__i_fpul"
6280 [(parallel [(set (match_operand:SI 0 "fpul_operand" "=y")
6281 (match_operand:SI 1 "immediate_operand" "i"))
6282 (clobber (match_operand:SI 2 "register_operand" "=&z"))])]
6283 "TARGET_SH1"
6284 "")
6286 (define_insn "*movsi_y"
6287 [(set (match_operand:SI 0 "register_operand" "=y,y")
6288 (match_operand:SI 1 "immediate_operand" "Qi,I08"))
6289 (clobber (match_scratch:SI 2 "=&z,r"))]
6290 "TARGET_SH2E
6291 && (reload_in_progress || reload_completed)"
6292 "#"
6293 [(set_attr "length" "4")
6294 (set_attr "type" "pcload,move")])
6296 (define_split
6297 [(set (match_operand:SI 0 "register_operand" "")
6298 (match_operand:SI 1 "immediate_operand" ""))
6299 (clobber (match_operand:SI 2 "register_operand" ""))]
6300 "TARGET_SH1"
6301 [(set (match_dup 2) (match_dup 1))
6302 (set (match_dup 0) (match_dup 2))]
6303 "")
6304 \f
6305 ;; ------------------------------------------------------------------------
6306 ;; Define the real conditional branch instructions.
6307 ;; ------------------------------------------------------------------------
6309 (define_expand "branch_true"
6310 [(set (pc) (if_then_else (ne (reg:SI T_REG) (const_int 0))
6311 (label_ref (match_operand 0))
6312 (pc)))]
6313 "TARGET_SH1")
6315 (define_expand "branch_false"
6316 [(set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
6317 (label_ref (match_operand 0))
6318 (pc)))]
6319 "TARGET_SH1")
6321 (define_insn_and_split "*cbranch_t"
6322 [(set (pc) (if_then_else (match_operand 1 "cbranch_treg_value")
6323 (label_ref (match_operand 0))
6324 (pc)))]
6325 "TARGET_SH1"
6326 {
6327 return output_branch (sh_eval_treg_value (operands[1]), insn, operands);
6328 }
6329 "&& 1"
6330 [(const_int 0)]
6331 {
6332 /* Try to canonicalize the branch condition if it is not one of:
6333 (ne (reg:SI T_REG) (const_int 0))
6334 (eq (reg:SI T_REG) (const_int 0))
6336 Instead of splitting out a new insn, we modify the current insn's
6337 operands as needed. This preserves things such as REG_DEAD notes. */
6339 if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
6340 && REG_P (XEXP (operands[1], 0)) && REGNO (XEXP (operands[1], 0)) == T_REG
6341 && XEXP (operands[1], 1) == const0_rtx)
6342 DONE;
6344 int branch_cond = sh_eval_treg_value (operands[1]);
6345 rtx new_cond_rtx = NULL_RTX;
6347 if (branch_cond == 0)
6348 new_cond_rtx = gen_rtx_EQ (VOIDmode, get_t_reg_rtx (), const0_rtx);
6349 else if (branch_cond == 1)
6350 new_cond_rtx = gen_rtx_NE (VOIDmode, get_t_reg_rtx (), const0_rtx);
6352 if (new_cond_rtx != NULL_RTX)
6353 validate_change (curr_insn, &XEXP (XEXP (PATTERN (curr_insn), 1), 0),
6354 new_cond_rtx, false);
6355 DONE;
6356 }
6357 [(set_attr "type" "cbranch")])
6359 ;; Patterns to prevent reorg from re-combining a condbranch with a branch
6360 ;; which destination is too far away.
6361 ;; The const_int_operand is distinct for each branch target; it avoids
6362 ;; unwanted matches with redundant_insn.
6363 (define_insn "block_branch_redirect"
6364 [(set (pc) (unspec [(match_operand 0 "const_int_operand" "")] UNSPEC_BBR))]
6365 "TARGET_SH1"
6366 ""
6367 [(set_attr "length" "0")])
6369 ;; This one has the additional purpose to record a possible scratch register
6370 ;; for the following branch.
6371 ;; ??? Unfortunately, just setting the scratch register is not good enough,
6372 ;; because the insn then might be deemed dead and deleted. And we can't
6373 ;; make the use in the jump insn explicit because that would disable
6374 ;; delay slot scheduling from the target.
6375 (define_insn "indirect_jump_scratch"
6376 [(set (match_operand:SI 0 "register_operand" "=r")
6377 (unspec:SI [(match_operand 1 "const_int_operand" "")] UNSPEC_BBR))
6378 (set (pc) (unspec [(const_int 0)] UNSPEC_BBR))]
6379 "TARGET_SH1"
6380 ""
6381 [(set_attr "length" "0")])
6383 ;; This one is used to preemt an insn from beyond the bra / braf / jmp
6384 ;; being pulled into the delay slot of a condbranch that has been made to
6385 ;; jump around the unconditional jump because it was out of range.
6386 (define_insn "stuff_delay_slot"
6387 [(set (pc)
6388 (unspec [(match_operand:SI 0 "const_int_operand" "") (pc)
6389 (match_operand:SI 1 "const_int_operand" "")] UNSPEC_BBR))]
6390 "TARGET_SH1"
6391 ""
6392 [(set_attr "length" "0")
6393 (set_attr "cond_delay_slot" "yes")])
6394 \f
6395 ;; Conditional branch insns
6397 ; operand 0 is the loop count pseudo register
6398 ; operand 1 is the label to jump to at the top of the loop
6399 (define_expand "doloop_end"
6400 [(parallel [(set (pc)
6401 (if_then_else (ne:SI (match_operand:SI 0 "" "")
6402 (const_int 1))
6403 (label_ref (match_operand 1 "" ""))
6404 (pc)))
6405 (set (match_dup 0)
6406 (plus:SI (match_dup 0) (const_int -1)))
6407 (clobber (reg:SI T_REG))])]
6408 "TARGET_SH2"
6409 {
6410 if (GET_MODE (operands[0]) != SImode)
6411 FAIL;
6412 emit_jump_insn (gen_doloop_end_split (operands[0], operands[1], operands[0]));
6413 DONE;
6414 })
6416 (define_insn_and_split "doloop_end_split"
6417 [(set (pc)
6418 (if_then_else (ne:SI (match_operand:SI 2 "arith_reg_dest" "0")
6419 (const_int 1))
6420 (label_ref (match_operand 1 "" ""))
6421 (pc)))
6422 (set (match_operand:SI 0 "arith_reg_dest" "=r")
6423 (plus:SI (match_dup 2) (const_int -1)))
6424 (clobber (reg:SI T_REG))]
6425 "TARGET_SH2"
6426 "#"
6427 "&& 1"
6428 [(parallel [(set (reg:SI T_REG)
6429 (eq:SI (match_dup 2) (const_int 1)))
6430 (set (match_dup 0) (plus:SI (match_dup 2) (const_int -1)))])
6431 (set (pc) (if_then_else (eq (reg:SI T_REG) (const_int 0))
6432 (label_ref (match_dup 1))
6433 (pc)))]
6434 ""
6435 [(set_attr "type" "cbranch")])
6436 \f
6437 ;; ------------------------------------------------------------------------
6438 ;; Jump and linkage insns
6439 ;; ------------------------------------------------------------------------
6441 (define_insn "jump_compact"
6442 [(set (pc)
6443 (label_ref (match_operand 0 "" "")))]
6444 "TARGET_SH1 && !CROSSING_JUMP_P (insn)"
6445 {
6446 /* The length is 16 if the delay slot is unfilled. */
6447 if (get_attr_length(insn) > 4)
6448 return output_far_jump(insn, operands[0]);
6449 else
6450 return "bra %l0%#";
6451 }
6452 [(set_attr "type" "jump")
6453 (set_attr "needs_delay_slot" "yes")])
6455 (define_insn "*jump_compact_crossing"
6456 [(set (pc)
6457 (label_ref (match_operand 0 "" "")))]
6458 "TARGET_SH1
6459 && flag_reorder_blocks_and_partition
6460 && CROSSING_JUMP_P (insn)"
6461 {
6462 /* The length is 16 if the delay slot is unfilled. */
6463 return output_far_jump(insn, operands[0]);
6464 }
6465 [(set_attr "type" "jump")
6466 (set_attr "length" "16")])
6468 (define_expand "jump"
6469 [(set (pc)
6470 (label_ref (match_operand 0 "" "")))]
6471 ""
6472 {
6473 emit_jump_insn (gen_jump_compact (operands[0]));
6474 DONE;
6475 })
6477 (define_insn "calli"
6478 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
6479 (match_operand 1 "" ""))
6480 (use (reg:SI FPSCR_MODES_REG))
6481 (clobber (reg:SI PR_REG))]
6482 "TARGET_SH1 && !TARGET_FDPIC"
6483 {
6484 if (TARGET_SH2A && dbr_sequence_length () == 0)
6485 return "jsr/n @%0";
6486 else
6487 return "jsr @%0%#";
6488 }
6489 [(set_attr "type" "call")
6490 (set (attr "fp_mode")
6491 (if_then_else (eq_attr "fpu_single" "yes")
6492 (const_string "single") (const_string "double")))
6493 (set_attr "needs_delay_slot" "yes")
6494 (set_attr "fp_set" "unknown")])
6496 (define_insn "calli_fdpic"
6497 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
6498 (match_operand 1))
6499 (use (reg:SI FPSCR_MODES_REG))
6500 (use (reg:SI PIC_REG))
6501 (clobber (reg:SI PR_REG))]
6502 "TARGET_FDPIC"
6503 {
6504 if (TARGET_SH2A && dbr_sequence_length () == 0)
6505 return "jsr/n @%0";
6506 else
6507 return "jsr @%0%#";
6508 }
6509 [(set_attr "type" "call")
6510 (set (attr "fp_mode")
6511 (if_then_else (eq_attr "fpu_single" "yes")
6512 (const_string "single") (const_string "double")))
6513 (set_attr "needs_delay_slot" "yes")
6514 (set_attr "fp_set" "unknown")])
6516 ;; This is TBR relative jump instruction for SH2A architecture.
6517 ;; Its use is enabled by assigning an attribute "function_vector"
6518 ;; and the vector number to a function during its declaration.
6519 (define_insn "calli_tbr_rel"
6520 [(call (mem (match_operand:SI 0 "symbol_ref_operand" ""))
6521 (match_operand 1 "" ""))
6522 (use (reg:SI FPSCR_MODES_REG))
6523 (use (match_scratch 2))
6524 (clobber (reg:SI PR_REG))]
6525 "TARGET_SH2A && sh2a_is_function_vector_call (operands[0])"
6526 {
6527 unsigned HOST_WIDE_INT vect_num;
6528 vect_num = sh2a_get_function_vector_number (operands[0]);
6529 operands[2] = GEN_INT (vect_num * 4);
6531 return "jsr/n @@(%O2,tbr)";
6532 }
6533 [(set_attr "type" "call")
6534 (set (attr "fp_mode")
6535 (if_then_else (eq_attr "fpu_single" "yes")
6536 (const_string "single") (const_string "double")))
6537 (set_attr "needs_delay_slot" "no")
6538 (set_attr "fp_set" "unknown")])
6540 ;; This is a pc-rel call, using bsrf, for use with PIC.
6541 (define_insn "calli_pcrel"
6542 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "r"))
6543 (match_operand 1 "" ""))
6544 (use (reg:SI FPSCR_MODES_REG))
6545 (use (reg:SI PIC_REG))
6546 (use (match_operand 2 "" ""))
6547 (clobber (reg:SI PR_REG))]
6548 "TARGET_SH2"
6549 {
6550 return "bsrf %0" "\n"
6551 "%O2:%#";
6552 }
6553 [(set_attr "type" "call")
6554 (set (attr "fp_mode")
6555 (if_then_else (eq_attr "fpu_single" "yes")
6556 (const_string "single") (const_string "double")))
6557 (set_attr "needs_delay_slot" "yes")
6558 (set_attr "fp_set" "unknown")])
6560 (define_insn_and_split "call_pcrel"
6561 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
6562 (match_operand 1 "" ""))
6563 (use (reg:SI FPSCR_MODES_REG))
6564 (use (reg:SI PIC_REG))
6565 (clobber (reg:SI PR_REG))
6566 (clobber (match_scratch:SI 2 "=&r"))]
6567 "TARGET_SH2"
6568 "#"
6569 "reload_completed"
6570 [(const_int 0)]
6571 {
6572 rtx lab = PATTERN (gen_call_site ());
6574 sh_expand_sym_label2reg (operands[2], operands[0], lab, false);
6575 emit_call_insn (gen_calli_pcrel (operands[2], operands[1], copy_rtx (lab)));
6576 DONE;
6577 }
6578 [(set_attr "type" "call")
6579 (set (attr "fp_mode")
6580 (if_then_else (eq_attr "fpu_single" "yes")
6581 (const_string "single") (const_string "double")))
6582 (set_attr "needs_delay_slot" "yes")
6583 (set_attr "fp_set" "unknown")])
6585 (define_insn "call_valuei"
6586 [(set (match_operand 0 "" "=rf")
6587 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
6588 (match_operand 2 "" "")))
6589 (use (reg:SI FPSCR_MODES_REG))
6590 (clobber (reg:SI PR_REG))]
6591 "TARGET_SH1 && !TARGET_FDPIC"
6592 {
6593 if (TARGET_SH2A && dbr_sequence_length () == 0)
6594 return "jsr/n @%1";
6595 else
6596 return "jsr @%1%#";
6597 }
6598 [(set_attr "type" "call")
6599 (set (attr "fp_mode")
6600 (if_then_else (eq_attr "fpu_single" "yes")
6601 (const_string "single") (const_string "double")))
6602 (set_attr "needs_delay_slot" "yes")
6603 (set_attr "fp_set" "unknown")])
6605 (define_insn "call_valuei_fdpic"
6606 [(set (match_operand 0 "" "=rf")
6607 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
6608 (match_operand 2)))
6609 (use (reg:SI FPSCR_REG))
6610 (use (reg:SI PIC_REG))
6611 (clobber (reg:SI PR_REG))]
6612 "TARGET_FDPIC"
6613 {
6614 if (TARGET_SH2A && dbr_sequence_length () == 0)
6615 return "jsr/n @%1";
6616 else
6617 return "jsr @%1%#";
6618 }
6619 [(set_attr "type" "call")
6620 (set (attr "fp_mode")
6621 (if_then_else (eq_attr "fpu_single" "yes")
6622 (const_string "single") (const_string "double")))
6623 (set_attr "needs_delay_slot" "yes")
6624 (set_attr "fp_set" "unknown")])
6626 ;; This is TBR relative jump instruction for SH2A architecture.
6627 ;; Its use is enabled by assigning an attribute "function_vector"
6628 ;; and the vector number to a function during its declaration.
6629 (define_insn "call_valuei_tbr_rel"
6630 [(set (match_operand 0 "" "=rf")
6631 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
6632 (match_operand 2 "" "")))
6633 (use (reg:SI FPSCR_MODES_REG))
6634 (use (match_scratch 3))
6635 (clobber (reg:SI PR_REG))]
6636 "TARGET_SH2A && sh2a_is_function_vector_call (operands[1])"
6637 {
6638 unsigned HOST_WIDE_INT vect_num;
6639 vect_num = sh2a_get_function_vector_number (operands[1]);
6640 operands[3] = GEN_INT (vect_num * 4);
6642 return "jsr/n @@(%O3,tbr)";
6643 }
6644 [(set_attr "type" "call")
6645 (set (attr "fp_mode")
6646 (if_then_else (eq_attr "fpu_single" "yes")
6647 (const_string "single") (const_string "double")))
6648 (set_attr "needs_delay_slot" "no")
6649 (set_attr "fp_set" "unknown")])
6651 (define_insn "call_valuei_pcrel"
6652 [(set (match_operand 0 "" "=rf")
6653 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "r"))
6654 (match_operand 2 "" "")))
6655 (use (reg:SI FPSCR_MODES_REG))
6656 (use (reg:SI PIC_REG))
6657 (use (match_operand 3 "" ""))
6658 (clobber (reg:SI PR_REG))]
6659 "TARGET_SH2"
6660 {
6661 return "bsrf %1" "\n"
6662 "%O3:%#";
6663 }
6664 [(set_attr "type" "call")
6665 (set (attr "fp_mode")
6666 (if_then_else (eq_attr "fpu_single" "yes")
6667 (const_string "single") (const_string "double")))
6668 (set_attr "needs_delay_slot" "yes")
6669 (set_attr "fp_set" "unknown")])
6671 (define_insn_and_split "call_value_pcrel"
6672 [(set (match_operand 0 "" "=rf")
6673 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
6674 (match_operand 2 "" "")))
6675 (use (reg:SI FPSCR_MODES_REG))
6676 (use (reg:SI PIC_REG))
6677 (clobber (reg:SI PR_REG))
6678 (clobber (match_scratch:SI 3 "=&r"))]
6679 "TARGET_SH2"
6680 "#"
6681 "reload_completed"
6682 [(const_int 0)]
6683 {
6684 rtx lab = PATTERN (gen_call_site ());
6686 sh_expand_sym_label2reg (operands[3], operands[1], lab, false);
6687 emit_call_insn (gen_call_valuei_pcrel (operands[0], operands[3],
6688 operands[2], copy_rtx (lab)));
6689 DONE;
6690 }
6691 [(set_attr "type" "call")
6692 (set (attr "fp_mode")
6693 (if_then_else (eq_attr "fpu_single" "yes")
6694 (const_string "single") (const_string "double")))
6695 (set_attr "needs_delay_slot" "yes")
6696 (set_attr "fp_set" "unknown")])
6698 (define_expand "call"
6699 [(parallel [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
6700 (match_operand 1 "" ""))
6701 (match_operand 2 "" "")
6702 (use (reg:SI FPSCR_MODES_REG))
6703 (clobber (reg:SI PR_REG))])]
6704 ""
6705 {
6706 if (TARGET_FDPIC)
6707 {
6708 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
6709 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
6710 }
6712 if (!flag_pic && TARGET_SH2A
6713 && MEM_P (operands[0])
6714 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6715 {
6716 if (sh2a_is_function_vector_call (XEXP (operands[0], 0)))
6717 {
6718 emit_call_insn (gen_calli_tbr_rel (XEXP (operands[0], 0),
6719 operands[1]));
6720 DONE;
6721 }
6722 }
6723 if (flag_pic && TARGET_SH2
6724 && MEM_P (operands[0])
6725 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6726 {
6727 emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1]));
6728 DONE;
6729 }
6730 else
6731 {
6732 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
6733 operands[1] = operands[2];
6734 }
6736 if (TARGET_FDPIC)
6737 {
6738 operands[0] = sh_load_function_descriptor (operands[0]);
6739 emit_call_insn (gen_calli_fdpic (operands[0], operands[1]));
6740 }
6741 else
6742 emit_call_insn (gen_calli (operands[0], operands[1]));
6743 DONE;
6744 })
6746 (define_expand "call_value"
6747 [(parallel [(set (match_operand 0 "arith_reg_operand" "")
6748 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
6749 (match_operand 2 "" "")))
6750 (match_operand 3 "" "")
6751 (use (reg:SI FPSCR_MODES_REG))
6752 (clobber (reg:SI PR_REG))])]
6753 ""
6754 {
6755 if (TARGET_FDPIC)
6756 {
6757 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
6758 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
6759 }
6761 if (!flag_pic && TARGET_SH2A
6762 && MEM_P (operands[1])
6763 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6764 {
6765 if (sh2a_is_function_vector_call (XEXP (operands[1], 0)))
6766 {
6767 emit_call_insn (gen_call_valuei_tbr_rel (operands[0],
6768 XEXP (operands[1], 0), operands[2]));
6769 DONE;
6770 }
6771 }
6772 if (flag_pic && TARGET_SH2
6773 && MEM_P (operands[1])
6774 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6775 {
6776 emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0),
6777 operands[2]));
6778 DONE;
6779 }
6780 else
6781 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
6783 if (TARGET_FDPIC)
6784 {
6785 operands[1] = sh_load_function_descriptor (operands[1]);
6786 emit_call_insn (gen_call_valuei_fdpic (operands[0], operands[1],
6787 operands[2]));
6788 }
6789 else
6790 emit_call_insn (gen_call_valuei (operands[0], operands[1], operands[2]));
6791 DONE;
6792 })
6794 (define_insn "sibcalli"
6795 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
6796 (match_operand 1 "" ""))
6797 (use (reg:SI FPSCR_MODES_REG))
6798 (return)]
6799 "TARGET_SH1 && !TARGET_FDPIC"
6800 "jmp @%0%#"
6801 [(set_attr "needs_delay_slot" "yes")
6802 (set (attr "fp_mode")
6803 (if_then_else (eq_attr "fpu_single" "yes")
6804 (const_string "single") (const_string "double")))
6805 (set_attr "type" "jump_ind")])
6807 (define_insn "sibcalli_fdpic"
6808 [(call (mem:SI (match_operand:SI 0 "register_operand" "k"))
6809 (match_operand 1))
6810 (use (reg:SI FPSCR_MODES_REG))
6811 (use (reg:SI PIC_REG))
6812 (return)]
6813 "TARGET_FDPIC"
6814 "jmp @%0%#"
6815 [(set_attr "needs_delay_slot" "yes")
6816 (set (attr "fp_mode")
6817 (if_then_else (eq_attr "fpu_single" "yes")
6818 (const_string "single") (const_string "double")))
6819 (set_attr "type" "jump_ind")])
6821 (define_insn "sibcalli_pcrel"
6822 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
6823 (match_operand 1 "" ""))
6824 (use (match_operand 2 "" ""))
6825 (use (reg:SI FPSCR_MODES_REG))
6826 (return)]
6827 "TARGET_SH2 && !TARGET_FDPIC"
6828 {
6829 return "braf %0" "\n"
6830 "%O2:%#";
6831 }
6832 [(set_attr "needs_delay_slot" "yes")
6833 (set (attr "fp_mode")
6834 (if_then_else (eq_attr "fpu_single" "yes")
6835 (const_string "single") (const_string "double")))
6836 (set_attr "type" "jump_ind")])
6838 (define_insn "sibcalli_pcrel_fdpic"
6839 [(call (mem:SI (match_operand:SI 0 "arith_reg_operand" "k"))
6840 (match_operand 1))
6841 (use (match_operand 2))
6842 (use (reg:SI FPSCR_MODES_REG))
6843 (use (reg:SI PIC_REG))
6844 (return)]
6845 "TARGET_SH2 && TARGET_FDPIC"
6846 {
6847 return "braf %0" "\n"
6848 "%O2:%#";
6849 }
6850 [(set_attr "needs_delay_slot" "yes")
6851 (set (attr "fp_mode")
6852 (if_then_else (eq_attr "fpu_single" "yes")
6853 (const_string "single") (const_string "double")))
6854 (set_attr "type" "jump_ind")])
6856 ;; This uses an unspec to describe that the symbol_ref is very close.
6857 (define_insn "sibcalli_thunk"
6858 [(call (mem:SI (unspec:SI [(match_operand:SI 0 "symbol_ref_operand" "")]
6859 UNSPEC_THUNK))
6860 (match_operand 1 "" ""))
6861 (use (reg:SI FPSCR_MODES_REG))
6862 (return)]
6863 "TARGET_SH1"
6864 "bra %O0"
6865 [(set_attr "needs_delay_slot" "yes")
6866 (set (attr "fp_mode")
6867 (if_then_else (eq_attr "fpu_single" "yes")
6868 (const_string "single") (const_string "double")))
6869 (set_attr "type" "jump")
6870 (set_attr "length" "2")])
6872 (define_insn_and_split "sibcall_pcrel"
6873 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" ""))
6874 (match_operand 1 "" ""))
6875 (use (reg:SI FPSCR_MODES_REG))
6876 (clobber (match_scratch:SI 2 "=&k"))
6877 (return)]
6878 "TARGET_SH2 && !TARGET_FDPIC"
6879 "#"
6880 "reload_completed"
6881 [(const_int 0)]
6882 {
6883 rtx lab = PATTERN (gen_call_site ());
6884 rtx call_insn;
6886 sh_expand_sym_label2reg (operands[2], operands[0], lab, true);
6887 call_insn = emit_call_insn (gen_sibcalli_pcrel (operands[2], operands[1],
6888 copy_rtx (lab)));
6889 SIBLING_CALL_P (call_insn) = 1;
6890 DONE;
6891 }
6892 [(set_attr "needs_delay_slot" "yes")
6893 (set (attr "fp_mode")
6894 (if_then_else (eq_attr "fpu_single" "yes")
6895 (const_string "single") (const_string "double")))
6896 (set_attr "type" "jump_ind")])
6898 (define_insn_and_split "sibcall_pcrel_fdpic"
6899 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand"))
6900 (match_operand 1))
6901 (use (reg:SI FPSCR_MODES_REG))
6902 (use (reg:SI PIC_REG))
6903 (clobber (match_scratch:SI 2 "=k"))
6904 (return)]
6905 "TARGET_SH2 && TARGET_FDPIC"
6906 "#"
6907 "&& reload_completed"
6908 [(const_int 0)]
6909 {
6910 rtx lab = PATTERN (gen_call_site ());
6912 sh_expand_sym_label2reg (operands[2], operands[0], lab, true);
6913 rtx i = emit_call_insn (gen_sibcalli_pcrel_fdpic (operands[2], operands[1],
6914 copy_rtx (lab)));
6915 SIBLING_CALL_P (i) = 1;
6916 DONE;
6917 }
6918 [(set_attr "needs_delay_slot" "yes")
6919 (set (attr "fp_mode")
6920 (if_then_else (eq_attr "fpu_single" "yes")
6921 (const_string "single") (const_string "double")))
6922 (set_attr "type" "jump_ind")])
6924 (define_expand "sibcall"
6925 [(parallel
6926 [(call (mem:SI (match_operand 0 "arith_reg_operand" ""))
6927 (match_operand 1 "" ""))
6928 (match_operand 2 "" "")
6929 (use (reg:SI FPSCR_MODES_REG))
6930 (return)])]
6931 ""
6932 {
6933 if (TARGET_FDPIC)
6934 {
6935 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
6936 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
6937 }
6939 if (flag_pic && TARGET_SH2
6940 && MEM_P (operands[0])
6941 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
6942 /* The PLT needs the PIC register, but the epilogue would have
6943 to restore it, so we can only use PC-relative PIC calls for
6944 static functions. */
6945 && SYMBOL_REF_LOCAL_P (XEXP (operands[0], 0)))
6946 {
6947 if (TARGET_FDPIC)
6948 emit_call_insn (gen_sibcall_pcrel_fdpic (XEXP (operands[0], 0),
6949 operands[1]));
6950 else
6951 emit_call_insn (gen_sibcall_pcrel (XEXP (operands[0], 0), operands[1]));
6952 DONE;
6953 }
6954 else
6955 operands[0] = force_reg (SImode, XEXP (operands[0], 0));
6957 if (TARGET_FDPIC)
6958 {
6959 operands[0] = sh_load_function_descriptor (operands[0]);
6960 emit_call_insn (gen_sibcalli_fdpic (operands[0], operands[1]));
6961 }
6962 else
6963 emit_call_insn (gen_sibcalli (operands[0], operands[1]));
6964 DONE;
6965 })
6967 (define_insn "sibcall_valuei"
6968 [(set (match_operand 0 "" "=rf")
6969 (call (mem:SI (match_operand:SI 1 "register_operand" "k"))
6970 (match_operand 2 "" "")))
6971 (use (reg:SI FPSCR_MODES_REG))
6972 (return)]
6973 "TARGET_SH1 && !TARGET_FDPIC"
6974 "jmp @%1%#"
6975 [(set_attr "needs_delay_slot" "yes")
6976 (set (attr "fp_mode")
6977 (if_then_else (eq_attr "fpu_single" "yes")
6978 (const_string "single") (const_string "double")))
6979 (set_attr "type" "jump_ind")])
6981 (define_insn "sibcall_valuei_fdpic"
6982 [(set (match_operand 0 "" "=rf")
6983 (call (mem:SI (match_operand:SI 1 "register_operand" "k"))
6984 (match_operand 2)))
6985 (use (reg:SI FPSCR_MODES_REG))
6986 (use (reg:SI PIC_REG))
6987 (return)]
6988 "TARGET_FDPIC"
6989 "jmp @%1%#"
6990 [(set_attr "needs_delay_slot" "yes")
6991 (set (attr "fp_mode")
6992 (if_then_else (eq_attr "fpu_single" "yes")
6993 (const_string "single") (const_string "double")))
6994 (set_attr "type" "jump_ind")])
6996 (define_insn "sibcall_valuei_pcrel"
6997 [(set (match_operand 0 "" "=rf")
6998 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "k"))
6999 (match_operand 2 "" "")))
7000 (use (match_operand 3 "" ""))
7001 (use (reg:SI FPSCR_MODES_REG))
7002 (return)]
7003 "TARGET_SH2 && !TARGET_FDPIC"
7004 {
7005 return "braf %1" "\n"
7006 "%O3:%#";
7007 }
7008 [(set_attr "needs_delay_slot" "yes")
7009 (set (attr "fp_mode")
7010 (if_then_else (eq_attr "fpu_single" "yes")
7011 (const_string "single") (const_string "double")))
7012 (set_attr "type" "jump_ind")])
7014 (define_insn "sibcall_valuei_pcrel_fdpic"
7015 [(set (match_operand 0 "" "=rf")
7016 (call (mem:SI (match_operand:SI 1 "arith_reg_operand" "k"))
7017 (match_operand 2)))
7018 (use (match_operand 3))
7019 (use (reg:SI FPSCR_MODES_REG))
7020 (use (reg:SI PIC_REG))
7021 (return)]
7022 "TARGET_SH2 && TARGET_FDPIC"
7023 {
7024 return "braf %1" "\n"
7025 "%O3:%#";
7026 }
7027 [(set_attr "needs_delay_slot" "yes")
7028 (set (attr "fp_mode")
7029 (if_then_else (eq_attr "fpu_single" "yes")
7030 (const_string "single") (const_string "double")))
7031 (set_attr "type" "jump_ind")])
7033 ;; sibcall_value_pcrel used to have a =&k clobber for the scratch register
7034 ;; that it needs for the branch address. This causes troubles when there
7035 ;; is a big overlap of argument and return value registers. Hence, use a
7036 ;; fixed call clobbered register for the address. See also PR 67260.
7037 (define_insn_and_split "sibcall_value_pcrel"
7038 [(set (match_operand 0 "" "=rf")
7039 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" ""))
7040 (match_operand 2 "" "")))
7041 (use (reg:SI FPSCR_MODES_REG))
7042 (clobber (reg:SI R1_REG))
7043 (return)]
7044 "TARGET_SH2 && !TARGET_FDPIC"
7045 "#"
7046 "reload_completed"
7047 [(const_int 0)]
7048 {
7049 rtx lab = PATTERN (gen_call_site ());
7050 rtx tmp = gen_rtx_REG (SImode, R1_REG);
7052 sh_expand_sym_label2reg (tmp, operands[1], lab, true);
7053 rtx call_insn = emit_call_insn (gen_sibcall_valuei_pcrel (operands[0],
7054 tmp,
7055 operands[2],
7056 copy_rtx (lab)));
7057 SIBLING_CALL_P (call_insn) = 1;
7058 DONE;
7059 }
7060 [(set_attr "needs_delay_slot" "yes")
7061 (set (attr "fp_mode")
7062 (if_then_else (eq_attr "fpu_single" "yes")
7063 (const_string "single") (const_string "double")))
7064 (set_attr "type" "jump_ind")])
7066 ;; Like for sibcall_value_pcrel, use a fixed call clobbered register for
7067 ;; the branch address.
7068 (define_insn_and_split "sibcall_value_pcrel_fdpic"
7069 [(set (match_operand 0 "" "=rf")
7070 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand"))
7071 (match_operand 2)))
7072 (use (reg:SI FPSCR_MODES_REG))
7073 (use (reg:SI PIC_REG))
7074 (clobber (reg:SI R1_REG))
7075 (return)]
7076 "TARGET_SH2 && TARGET_FDPIC"
7077 "#"
7078 "&& reload_completed"
7079 [(const_int 0)]
7080 {
7081 rtx lab = PATTERN (gen_call_site ());
7082 rtx tmp = gen_rtx_REG (SImode, R1_REG);
7084 sh_expand_sym_label2reg (tmp, operands[1], lab, true);
7085 rtx i = emit_call_insn (gen_sibcall_valuei_pcrel_fdpic (operands[0],
7086 tmp,
7087 operands[2],
7088 copy_rtx (lab)));
7089 SIBLING_CALL_P (i) = 1;
7090 DONE;
7091 }
7092 [(set_attr "needs_delay_slot" "yes")
7093 (set (attr "fp_mode")
7094 (if_then_else (eq_attr "fpu_single" "yes")
7095 (const_string "single") (const_string "double")))
7096 (set_attr "type" "jump_ind")])
7098 (define_expand "sibcall_value"
7099 [(parallel
7100 [(set (match_operand 0 "arith_reg_operand" "")
7101 (call (mem:SI (match_operand 1 "arith_reg_operand" ""))
7102 (match_operand 2 "" "")))
7103 (match_operand 3 "" "")
7104 (use (reg:SI FPSCR_MODES_REG))
7105 (return)])]
7106 ""
7107 {
7108 if (TARGET_FDPIC)
7109 {
7110 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
7111 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
7112 }
7114 if (flag_pic && TARGET_SH2
7115 && MEM_P (operands[1])
7116 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
7117 /* The PLT needs the PIC register, but the epilogue would have
7118 to restore it, so we can only use PC-relative PIC calls for
7119 static functions. */
7120 && SYMBOL_REF_LOCAL_P (XEXP (operands[1], 0)))
7121 {
7122 if (TARGET_FDPIC)
7123 emit_call_insn (gen_sibcall_value_pcrel_fdpic (operands[0],
7124 XEXP (operands[1], 0),
7125 operands[2]));
7126 else
7127 emit_call_insn (gen_sibcall_value_pcrel (operands[0],
7128 XEXP (operands[1], 0),
7129 operands[2]));
7130 DONE;
7131 }
7132 else
7133 operands[1] = force_reg (SImode, XEXP (operands[1], 0));
7135 if (TARGET_FDPIC)
7136 {
7137 operands[1] = sh_load_function_descriptor (operands[1]);
7138 emit_call_insn (gen_sibcall_valuei_fdpic (operands[0], operands[1],
7139 operands[2]));
7140 }
7141 else
7142 emit_call_insn (gen_sibcall_valuei (operands[0], operands[1], operands[2]));
7143 DONE;
7144 })
7146 (define_expand "sibcall_epilogue"
7147 [(return)]
7148 ""
7149 {
7150 sh_expand_epilogue (true);
7151 DONE;
7152 })
7154 (define_insn "indirect_jump_compact"
7155 [(set (pc)
7156 (match_operand:SI 0 "arith_reg_operand" "r"))]
7157 "TARGET_SH1"
7158 "jmp @%0%#"
7159 [(set_attr "needs_delay_slot" "yes")
7160 (set_attr "type" "jump_ind")])
7162 (define_expand "indirect_jump"
7163 [(set (pc)
7164 (match_operand 0 "register_operand" ""))]
7165 ""
7166 {
7167 if (GET_MODE (operands[0]) != Pmode)
7168 operands[0] = gen_rtx_SUBREG (Pmode, operands[0], 0);
7169 })
7171 ;; The use of operand 1 / 2 helps us distinguish case table jumps
7172 ;; which can be present in structured code from indirect jumps which cannot
7173 ;; be present in structured code. This allows -fprofile-arcs to work.
7175 ;; For SH1 processors.
7176 (define_insn "casesi_jump_1"
7177 [(set (pc)
7178 (match_operand:SI 0 "register_operand" "r"))
7179 (use (label_ref (match_operand 1 "" "")))]
7180 "TARGET_SH1"
7181 "jmp @%0%#"
7182 [(set_attr "needs_delay_slot" "yes")
7183 (set_attr "type" "jump_ind")])
7185 ;; For all later processors.
7186 (define_insn "casesi_jump_2"
7187 [(set (pc) (plus:SI (match_operand:SI 0 "register_operand" "r")
7188 (label_ref (match_operand 1 "" ""))))
7189 (use (label_ref (match_operand 2 "" "")))]
7190 "TARGET_SH2
7191 && (! INSN_UID (operands[1])
7192 || prev_real_insn (as_a<rtx_insn *> (operands[1])) == insn)"
7193 "braf %0%#"
7194 [(set_attr "needs_delay_slot" "yes")
7195 (set_attr "type" "jump_ind")])
7197 ;; Call subroutine returning any type.
7198 ;; ??? This probably doesn't work.
7199 (define_expand "untyped_call"
7200 [(parallel [(call (match_operand 0 "" "")
7201 (const_int 0))
7202 (match_operand 1 "" "")
7203 (match_operand 2 "" "")])]
7204 "TARGET_SH2E || TARGET_SH2A"
7205 {
7206 /* RA does not know that the call sets the function value registers.
7207 We avoid problems by claiming that those registers are clobbered
7208 at this point. */
7209 for (int i = 0; i < XVECLEN (operands[2], 0); i++)
7210 emit_clobber (SET_SRC (XVECEXP (operands[2], 0, i)));
7212 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
7214 for (int i = 0; i < XVECLEN (operands[2], 0); i++)
7215 {
7216 rtx set = XVECEXP (operands[2], 0, i);
7217 emit_move_insn (SET_DEST (set), SET_SRC (set));
7218 }
7220 /* The optimizer does not know that the call sets the function value
7221 registers we stored in the result block. We avoid problems by
7222 claiming that all hard registers are used and clobbered at this
7223 point. */
7224 emit_insn (gen_blockage ());
7226 DONE;
7227 })
7228 \f
7229 ;; ------------------------------------------------------------------------
7230 ;; Misc insns
7231 ;; ------------------------------------------------------------------------
7233 (define_insn "dect"
7234 [(set (reg:SI T_REG)
7235 (eq:SI (match_operand:SI 1 "arith_reg_dest" "0") (const_int 1)))
7236 (set (match_operand:SI 0 "arith_reg_dest" "=r")
7237 (plus:SI (match_dup 1) (const_int -1)))]
7238 "TARGET_SH2"
7239 "dt %0"
7240 [(set_attr "type" "arith")])
7242 (define_insn "nop"
7243 [(const_int 0)]
7244 ""
7245 "nop")
7247 ;; Load address of a label. This is only generated by the casesi expand,
7248 ;; and by machine_dependent_reorg (fixing up fp moves).
7249 ;; This must use unspec, because this only works for labels that are
7250 ;; within range.
7251 (define_insn "mova"
7252 [(set (reg:SI R0_REG)
7253 (unspec:SI [(label_ref (match_operand 0 "" ""))] UNSPEC_MOVA))]
7254 "TARGET_SH1"
7255 "mova %O0,r0"
7256 [(set_attr "in_delay_slot" "no")
7257 (set_attr "type" "arith")])
7259 ;; machine_dependent_reorg will make this a `mova'.
7260 (define_insn "mova_const"
7261 [(set (reg:SI R0_REG)
7262 (unspec:SI [(match_operand 0 "immediate_operand" "i")] UNSPEC_MOVA))]
7263 "TARGET_SH1"
7264 "#"
7265 [(set_attr "in_delay_slot" "no")
7266 (set_attr "type" "arith")])
7268 ;; Loads of the GOTPC relocation values must not be optimized away
7269 ;; by e.g. any kind of CSE and must stay as they are. Although there
7270 ;; are other various ways to ensure this, we use an artificial counter
7271 ;; operand to generate unique symbols.
7272 (define_expand "GOTaddr2picreg"
7273 [(set (reg:SI R0_REG)
7274 (unspec:SI [(const:SI (unspec:SI [(match_dup 2)
7275 (match_operand:SI 0 "" "")]
7276 UNSPEC_PIC))] UNSPEC_MOVA))
7277 (set (match_dup 1)
7278 (const:SI (unspec:SI [(match_dup 2) (match_dup 0)] UNSPEC_PIC)))
7279 (set (match_dup 1) (plus:SI (match_dup 1) (reg:SI R0_REG)))]
7280 ""
7281 {
7282 if (TARGET_VXWORKS_RTP)
7283 {
7284 rtx gott_base = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_BASE);
7285 rtx gott_index = gen_rtx_SYMBOL_REF (Pmode, VXWORKS_GOTT_INDEX);
7286 emit_insn (gen_vxworks_picreg (gott_base, gott_index));
7287 DONE;
7288 }
7290 if (TARGET_FDPIC)
7291 {
7292 rtx pic_reg = gen_rtx_REG (Pmode, PIC_REG);
7293 emit_move_insn (pic_reg, sh_get_fdpic_reg_initial_val ());
7294 DONE;
7295 }
7297 operands[1] = gen_rtx_REG (Pmode, PIC_REG);
7298 operands[2] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME);
7299 })
7301 ;; A helper for GOTaddr2picreg to finish up the initialization of the
7302 ;; PIC register.
7303 (define_expand "vxworks_picreg"
7304 [(set (reg:SI PIC_REG)
7305 (const:SI (unspec:SI [(match_operand:SI 0 "" "")] UNSPEC_PIC)))
7306 (set (reg:SI R0_REG)
7307 (const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PIC)))
7308 (set (reg:SI PIC_REG)
7309 (mem:SI (reg:SI PIC_REG)))
7310 (set (reg:SI PIC_REG)
7311 (mem:SI (plus:SI (reg:SI PIC_REG)
7312 (reg:SI R0_REG))))]
7313 "TARGET_VXWORKS_RTP")
7315 (define_expand "builtin_setjmp_receiver"
7316 [(match_operand 0 "" "")]
7317 "flag_pic"
7318 {
7319 emit_insn (gen_GOTaddr2picreg (const0_rtx));
7320 DONE;
7321 })
7323 (define_expand "call_site"
7324 [(unspec [(match_dup 0)] UNSPEC_CALLER)]
7325 "TARGET_SH1"
7326 {
7327 static HOST_WIDE_INT i = 0;
7328 operands[0] = GEN_INT (i);
7329 i++;
7330 })
7332 ;; op0 = op1 + r12 but hide it before reload completed. See the comment
7333 ;; in symGOT_load expand.
7334 (define_insn_and_split "chk_guard_add"
7335 [(set (match_operand:SI 0 "register_operand" "=&r")
7336 (unspec:SI [(match_operand:SI 1 "register_operand" "r")
7337 (reg:SI PIC_REG)]
7338 UNSPEC_CHKADD))]
7339 "TARGET_SH1"
7340 "#"
7341 "TARGET_SH1 && reload_completed"
7342 [(set (match_dup 0) (reg:SI PIC_REG))
7343 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
7344 ""
7345 [(set_attr "type" "arith")])
7347 (define_expand "sym_label2reg"
7348 [(set (match_operand:SI 0 "" "")
7349 (const:SI (unspec:SI [(match_operand:SI 1 "" "")
7350 (const (plus:SI (match_operand:SI 2 "" "")
7351 (const_int 2)))]
7352 UNSPEC_SYMOFF)))]
7353 "TARGET_SH1" "")
7355 (define_expand "symPCREL_label2reg"
7356 [(set (match_operand:SI 0 "" "")
7357 (const:SI
7358 (unspec:SI
7359 [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PCREL))
7360 (const:SI (plus:SI (match_operand:SI 2 "" "")
7361 (const_int 2)))] UNSPEC_PCREL_SYMOFF)))]
7362 "TARGET_SH1"
7363 "")
7365 (define_expand "symGOT_load"
7366 [(set (match_dup 2) (match_operand 1 "" ""))
7367 (set (match_dup 3) (plus (match_dup 2) (reg PIC_REG)))
7368 (set (match_operand 0 "" "") (mem (match_dup 3)))]
7369 ""
7370 {
7371 rtx mem;
7372 bool stack_chk_guard_p = false;
7374 rtx picreg = TARGET_FDPIC ? sh_get_fdpic_reg_initial_val ()
7375 : gen_rtx_REG (Pmode, PIC_REG);
7377 operands[2] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
7378 operands[3] = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
7380 if (!TARGET_FDPIC
7381 && flag_stack_protect
7382 && GET_CODE (operands[1]) == CONST
7383 && GET_CODE (XEXP (operands[1], 0)) == UNSPEC
7384 && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == SYMBOL_REF
7385 && strcmp (XSTR (XVECEXP (XEXP (operands[1], 0), 0, 0), 0),
7386 "__stack_chk_guard") == 0)
7387 stack_chk_guard_p = true;
7389 emit_move_insn (operands[2], operands[1]);
7391 /* When stack protector inserts codes after the result is set to
7392 R0, @(rX, r12) will cause a spill failure for R0. Use a unspec
7393 insn to avoid combining (set A (plus rX r12)) and (set op0 (mem A))
7394 when rX is a GOT address for the guard symbol. Ugly but doesn't
7395 matter because this is a rare situation. */
7396 if (stack_chk_guard_p)
7397 emit_insn (gen_chk_guard_add (operands[3], operands[2]));
7398 else
7399 emit_move_insn (operands[3], gen_rtx_PLUS (Pmode, operands[2], picreg));
7401 /* N.B. This is not constant for a GOTPLT relocation. */
7402 mem = gen_rtx_MEM (Pmode, operands[3]);
7403 MEM_NOTRAP_P (mem) = 1;
7404 /* ??? Should we have a special alias set for the GOT? */
7405 emit_move_insn (operands[0], mem);
7407 DONE;
7408 })
7410 (define_expand "sym2GOT"
7411 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOT))]
7412 ""
7413 "")
7415 (define_expand "symGOT2reg"
7416 [(match_operand 0 "" "") (match_operand 1 "" "")]
7417 ""
7418 {
7419 rtx gotsym, insn;
7421 gotsym = gen_sym2GOT (operands[1]);
7422 PUT_MODE (gotsym, Pmode);
7423 insn = emit_insn (gen_symGOT_load (operands[0], gotsym));
7425 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
7427 DONE;
7428 })
7430 (define_expand "sym2GOTFUNCDESC"
7431 [(const (unspec [(match_operand 0)] UNSPEC_GOTFUNCDESC))]
7432 "TARGET_FDPIC")
7434 (define_expand "symGOTFUNCDESC2reg"
7435 [(match_operand 0) (match_operand 1)]
7436 "TARGET_FDPIC"
7437 {
7438 rtx gotsym = gen_sym2GOTFUNCDESC (operands[1]);
7439 PUT_MODE (gotsym, Pmode);
7440 rtx insn = emit_insn (gen_symGOT_load (operands[0], gotsym));
7442 MEM_READONLY_P (SET_SRC (PATTERN (insn))) = 1;
7444 DONE;
7445 })
7447 (define_expand "symGOTPLT2reg"
7448 [(match_operand 0 "" "") (match_operand 1 "" "")]
7449 ""
7450 {
7451 rtx pltsym = gen_rtx_CONST (Pmode,
7452 gen_rtx_UNSPEC (Pmode,
7453 gen_rtvec (1, operands[1]),
7454 UNSPEC_GOTPLT));
7455 emit_insn (gen_symGOT_load (operands[0], pltsym));
7456 DONE;
7457 })
7459 (define_expand "sym2GOTOFF"
7460 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTOFF))]
7461 ""
7462 "")
7464 (define_expand "symGOTOFF2reg"
7465 [(match_operand 0 "" "") (match_operand 1 "" "")]
7466 ""
7467 {
7468 rtx gotoffsym;
7469 rtx t = (!can_create_pseudo_p ()
7470 ? operands[0]
7471 : gen_reg_rtx (GET_MODE (operands[0])));
7473 rtx picreg = TARGET_FDPIC ? sh_get_fdpic_reg_initial_val ()
7474 : gen_rtx_REG (Pmode, PIC_REG);
7476 gotoffsym = gen_sym2GOTOFF (operands[1]);
7477 PUT_MODE (gotoffsym, Pmode);
7478 emit_move_insn (t, gotoffsym);
7479 rtx_insn *insn = emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, picreg));
7481 set_unique_reg_note (insn, REG_EQUAL, operands[1]);
7483 DONE;
7484 })
7486 (define_expand "sym2GOTOFFFUNCDESC"
7487 [(const (unspec [(match_operand 0)] UNSPEC_GOTOFFFUNCDESC))]
7488 "TARGET_FDPIC")
7490 (define_expand "symGOTOFFFUNCDESC2reg"
7491 [(match_operand 0) (match_operand 1)]
7492 "TARGET_FDPIC"
7493 {
7494 rtx picreg = sh_get_fdpic_reg_initial_val ();
7495 rtx t = !can_create_pseudo_p ()
7496 ? operands[0]
7497 : gen_reg_rtx (GET_MODE (operands[0]));
7499 rtx gotoffsym = gen_sym2GOTOFFFUNCDESC (operands[1]);
7500 PUT_MODE (gotoffsym, Pmode);
7501 emit_move_insn (t, gotoffsym);
7502 emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, picreg));
7503 DONE;
7504 })
7506 (define_expand "symPLT_label2reg"
7507 [(set (match_operand:SI 0 "" "")
7508 (const:SI
7509 (unspec:SI
7510 [(const:SI (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PLT))
7511 (const:SI (plus:SI (match_operand:SI 2 "" "")
7512 (const_int 2)))] UNSPEC_PCREL_SYMOFF)))
7513 ;; Even though the PIC register is not really used by the call
7514 ;; sequence in which this is expanded, the PLT code assumes the PIC
7515 ;; register is set, so we must not skip its initialization. Since
7516 ;; we only use this expand as part of calling sequences, and never
7517 ;; to take the address of a function, this is the best point to
7518 ;; insert the (use). Using the PLT to take the address of a
7519 ;; function would be wrong, not only because the PLT entry could
7520 ;; then be called from a function that doesn't initialize the PIC
7521 ;; register to the proper GOT, but also because pointers to the
7522 ;; same function might not compare equal, should they be set by
7523 ;; different shared libraries.
7524 (use (reg:SI PIC_REG))]
7525 "TARGET_SH1"
7526 "")
7528 (define_expand "sym2PIC"
7529 [(const (unspec [(match_operand:SI 0 "" "")] UNSPEC_PIC))]
7530 ""
7531 "")
7533 ;; -------------------------------------------------------------------------
7534 ;; TLS code generation.
7536 ;; FIXME: The multi-insn asm blocks should be converted to use
7537 ;; define_insn_and_split.
7538 ;; See the thread [PATCH/RFA] SH TLS support on gcc-patches
7539 ;; <http://gcc.gnu.org/ml/gcc-patches/2003-02/msg01898.html>
7540 ;; for details.
7542 (define_insn "tls_global_dynamic"
7543 [(set (match_operand:SI 0 "register_operand" "=&z")
7544 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
7545 UNSPEC_TLSGD))
7546 (const_int 0)))
7547 (use (reg:SI FPSCR_MODES_REG))
7548 (use (reg:SI PIC_REG))
7549 (clobber (reg:SI PR_REG))
7550 (clobber (scratch:SI))]
7551 "TARGET_SH1"
7552 {
7553 return "mov.l 1f,r4" "\n"
7554 " mova 2f,r0" "\n"
7555 " mov.l 2f,r1" "\n"
7556 " add r0,r1" "\n"
7557 " jsr @r1" "\n"
7558 " add r12,r4" "\n"
7559 " bra 3f" "\n"
7560 " nop" "\n"
7561 " .align 2" "\n"
7562 "1: .long %a1@TLSGD" "\n"
7563 "2: .long __tls_get_addr@PLT" "\n"
7564 "3:";
7565 }
7566 [(set_attr "type" "tls_load")
7567 (set_attr "length" "26")])
7569 (define_insn "tls_local_dynamic"
7570 [(set (match_operand:SI 0 "register_operand" "=&z")
7571 (call:SI (mem:SI (unspec:SI [(match_operand:SI 1 "" "")]
7572 UNSPEC_TLSLDM))
7573 (const_int 0)))
7574 (use (reg:SI FPSCR_MODES_REG))
7575 (use (reg:SI PIC_REG))
7576 (clobber (reg:SI PR_REG))
7577 (clobber (scratch:SI))]
7578 "TARGET_SH1"
7579 {
7580 return "mov.l 1f,r4" "\n"
7581 " mova 2f,r0" "\n"
7582 " mov.l 2f,r1" "\n"
7583 " add r0,r1" "\n"
7584 " jsr @r1" "\n"
7585 " add r12,r4" "\n"
7586 " bra 3f" "\n"
7587 " nop" "\n"
7588 " .align 2" "\n"
7589 "1: .long %a1@TLSLDM" "\n"
7590 "2: .long __tls_get_addr@PLT" "\n"
7591 "3:";
7592 }
7593 [(set_attr "type" "tls_load")
7594 (set_attr "length" "26")])
7596 (define_expand "sym2DTPOFF"
7597 [(const (unspec [(match_operand 0 "" "")] UNSPEC_DTPOFF))]
7598 ""
7599 "")
7601 (define_expand "symDTPOFF2reg"
7602 [(match_operand 0 "" "") (match_operand 1 "" "") (match_operand 2 "" "")]
7603 ""
7604 {
7605 rtx dtpoffsym;
7606 rtx t = (!can_create_pseudo_p ()
7607 ? operands[0]
7608 : gen_reg_rtx (GET_MODE (operands[0])));
7610 dtpoffsym = gen_sym2DTPOFF (operands[1]);
7611 PUT_MODE (dtpoffsym, Pmode);
7612 emit_move_insn (t, dtpoffsym);
7613 emit_move_insn (operands[0], gen_rtx_PLUS (Pmode, t, operands[2]));
7614 DONE;
7615 })
7617 (define_expand "sym2GOTTPOFF"
7618 [(const (unspec [(match_operand 0 "" "")] UNSPEC_GOTTPOFF))]
7619 ""
7620 "")
7622 (define_insn "tls_initial_exec"
7623 [(set (match_operand:SI 0 "register_operand" "=&r")
7624 (unspec:SI [(match_operand:SI 1 "" "")]
7625 UNSPEC_TLSIE))
7626 (use (reg:SI GBR_REG))
7627 (use (reg:SI PIC_REG))
7628 (clobber (reg:SI R0_REG))]
7629 ""
7630 {
7631 return "mov.l 1f,r0" "\n"
7632 " stc gbr,%0" "\n"
7633 " mov.l @(r0,r12),r0" "\n"
7634 " bra 2f" "\n"
7635 " add r0,%0" "\n"
7636 " .align 2" "\n"
7637 "1: .long %a1" "\n"
7638 "2:";
7639 }
7640 [(set_attr "type" "tls_load")
7641 (set_attr "length" "16")])
7643 (define_expand "sym2TPOFF"
7644 [(const (unspec [(match_operand 0 "" "")] UNSPEC_TPOFF))]
7645 ""
7646 "")
7648 (define_expand "symTPOFF2reg"
7649 [(match_operand 0 "" "") (match_operand 1 "" "")]
7650 ""
7651 {
7652 rtx tpoffsym;
7654 tpoffsym = gen_sym2TPOFF (operands[1]);
7655 PUT_MODE (tpoffsym, Pmode);
7656 emit_move_insn (operands[0], tpoffsym);
7657 DONE;
7658 })
7660 ;;------------------------------------------------------------------------------
7661 ;; Thread pointer getter and setter.
7662 ;;
7663 ;; On SH the thread pointer is kept in the GBR.
7664 ;; These patterns are usually expanded from the respective built-in functions.
7665 (define_expand "get_thread_pointersi"
7666 [(set (match_operand:SI 0 "arith_reg_dest") (reg:SI GBR_REG))]
7667 "TARGET_SH1")
7669 ;; The store_gbr insn can also be used on !TARGET_SH1 for doing TLS accesses.
7670 (define_insn "store_gbr"
7671 [(set (match_operand:SI 0 "arith_reg_dest" "=r") (reg:SI GBR_REG))]
7672 ""
7673 "stc gbr,%0"
7674 [(set_attr "type" "tls_load")])
7676 (define_expand "set_thread_pointersi"
7677 [(set (reg:SI GBR_REG)
7678 (unspec_volatile:SI [(match_operand:SI 0 "arith_reg_operand")]
7679 UNSPECV_GBR))]
7680 "TARGET_SH1")
7682 (define_insn "load_gbr"
7683 [(set (reg:SI GBR_REG)
7684 (unspec_volatile:SI [(match_operand:SI 0 "arith_reg_operand" "r")]
7685 UNSPECV_GBR))]
7686 "TARGET_SH1"
7687 "ldc %0,gbr"
7688 [(set_attr "type" "move")])
7690 ;;------------------------------------------------------------------------------
7691 ;; Thread pointer relative memory loads and stores.
7692 ;;
7693 ;; On SH there are GBR displacement address modes which can be utilized to
7694 ;; access memory behind the thread pointer.
7695 ;; Since we do not allow using GBR for general purpose memory accesses, these
7696 ;; GBR addressing modes are formed by the combine pass.
7697 ;; This could be done with fewer patterns than below by using a mem predicate
7698 ;; for the GBR mem, but then reload would try to reload addresses with a
7699 ;; zero displacement for some strange reason.
7701 (define_insn "*mov<mode>_gbr_load"
7702 [(set (match_operand:QIHISI 0 "arith_reg_dest" "=z")
7703 (mem:QIHISI (plus:SI (reg:SI GBR_REG)
7704 (match_operand:QIHISI 1 "gbr_displacement"))))]
7705 "TARGET_SH1"
7706 "mov.<bwl> @(%O1,gbr),%0"
7707 [(set_attr "type" "load")])
7709 (define_insn "*mov<mode>_gbr_load"
7710 [(set (match_operand:QIHISI 0 "arith_reg_dest" "=z")
7711 (mem:QIHISI (reg:SI GBR_REG)))]
7712 "TARGET_SH1"
7713 "mov.<bwl> @(0,gbr),%0"
7714 [(set_attr "type" "load")])
7716 (define_insn "*mov<mode>_gbr_load"
7717 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
7718 (sign_extend:SI
7719 (mem:QIHI (plus:SI (reg:SI GBR_REG)
7720 (match_operand:QIHI 1 "gbr_displacement")))))]
7721 "TARGET_SH1"
7722 "mov.<bw> @(%O1,gbr),%0"
7723 [(set_attr "type" "load")])
7725 (define_insn "*mov<mode>_gbr_load"
7726 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
7727 (sign_extend:SI (mem:QIHI (reg:SI GBR_REG))))]
7728 "TARGET_SH1"
7729 "mov.<bw> @(0,gbr),%0"
7730 [(set_attr "type" "load")])
7732 (define_insn "*mov<mode>_gbr_store"
7733 [(set (mem:QIHISI (plus:SI (reg:SI GBR_REG)
7734 (match_operand:QIHISI 0 "gbr_displacement")))
7735 (match_operand:QIHISI 1 "register_operand" "z"))]
7736 "TARGET_SH1"
7737 "mov.<bwl> %1,@(%O0,gbr)"
7738 [(set_attr "type" "store")])
7740 (define_insn "*mov<mode>_gbr_store"
7741 [(set (mem:QIHISI (reg:SI GBR_REG))
7742 (match_operand:QIHISI 0 "register_operand" "z"))]
7743 "TARGET_SH1"
7744 "mov.<bwl> %0,@(0,gbr)"
7745 [(set_attr "type" "store")])
7747 ;; DImode memory accesses have to be split in two SImode accesses.
7748 ;; Split them before reload, so that it gets a better chance to figure out
7749 ;; how to deal with the R0 restriction for the individual SImode accesses.
7750 ;; Do not match this insn during or after reload because it can't be split
7751 ;; afterwards.
7752 (define_insn_and_split "*movdi_gbr_load"
7753 [(set (match_operand:DI 0 "arith_reg_dest")
7754 (match_operand:DI 1 "gbr_address_mem"))]
7755 "TARGET_SH1 && can_create_pseudo_p ()"
7756 "#"
7757 "&& 1"
7758 [(set (match_dup 3) (match_dup 5))
7759 (set (match_dup 4) (match_dup 6))]
7760 {
7761 /* Swap low/high part load order on little endian, so that the result reg
7762 of the second load can be used better. */
7763 int off = TARGET_LITTLE_ENDIAN ? 1 : 0;
7764 operands[3 + off] = gen_lowpart (SImode, operands[0]);
7765 operands[5 + off] = gen_lowpart (SImode, operands[1]);
7766 operands[4 - off] = gen_highpart (SImode, operands[0]);
7767 operands[6 - off] = gen_highpart (SImode, operands[1]);
7768 })
7770 (define_insn_and_split "*movdi_gbr_store"
7771 [(set (match_operand:DI 0 "gbr_address_mem")
7772 (match_operand:DI 1 "register_operand"))]
7773 "TARGET_SH1 && can_create_pseudo_p ()"
7774 "#"
7775 "&& 1"
7776 [(set (match_dup 3) (match_dup 5))
7777 (set (match_dup 4) (match_dup 6))]
7778 {
7779 /* Swap low/high part store order on big endian, so that stores of function
7780 call results can save a reg copy. */
7781 int off = TARGET_LITTLE_ENDIAN ? 0 : 1;
7782 operands[3 + off] = gen_lowpart (SImode, operands[0]);
7783 operands[5 + off] = gen_lowpart (SImode, operands[1]);
7784 operands[4 - off] = gen_highpart (SImode, operands[0]);
7785 operands[6 - off] = gen_highpart (SImode, operands[1]);
7786 })
7788 ;; Sometimes memory accesses do not get combined with the store_gbr insn,
7789 ;; in particular when the displacements are in the range of the regular move
7790 ;; insns. Thus, in the first split pass after the combine pass we search
7791 ;; for missed opportunities and try to fix them up ourselves.
7792 ;; If an equivalent GBR address can be determined the load / store is split
7793 ;; into one of the GBR load / store patterns.
7794 ;; All of that must happen before reload (GBR address modes use R0 as the
7795 ;; other operand) and there's no point of doing it if the GBR is not
7796 ;; referenced in a function at all.
7797 (define_split
7798 [(set (match_operand:QIHISIDI 0 "register_operand")
7799 (match_operand:QIHISIDI 1 "memory_operand"))]
7800 "TARGET_SH1 && !reload_in_progress && !reload_completed
7801 && df_regs_ever_live_p (GBR_REG)"
7802 [(set (match_dup 0) (match_dup 1))]
7803 {
7804 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
7805 if (gbr_mem != NULL_RTX)
7806 operands[1] = replace_equiv_address (operands[1], gbr_mem);
7807 else
7808 FAIL;
7809 })
7811 (define_split
7812 [(set (match_operand:SI 0 "register_operand")
7813 (sign_extend:SI (match_operand:QIHI 1 "memory_operand")))]
7814 "TARGET_SH1 && !reload_in_progress && !reload_completed
7815 && df_regs_ever_live_p (GBR_REG)"
7816 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
7817 {
7818 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
7819 if (gbr_mem != NULL_RTX)
7820 operands[1] = replace_equiv_address (operands[1], gbr_mem);
7821 else
7822 FAIL;
7823 })
7825 ;; On SH2A we've got movu.b and movu.w for doing zero-extending mem loads.
7826 ;; Split those so that a GBR load can be used.
7827 (define_split
7828 [(set (match_operand:SI 0 "register_operand")
7829 (zero_extend:SI (match_operand:QIHI 1 "memory_operand")))]
7830 "TARGET_SH2A && !reload_in_progress && !reload_completed
7831 && df_regs_ever_live_p (GBR_REG)"
7832 [(set (match_dup 2) (match_dup 1))
7833 (set (match_dup 0) (zero_extend:SI (match_dup 2)))]
7834 {
7835 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[1]);
7836 if (gbr_mem != NULL_RTX)
7837 {
7838 operands[2] = gen_reg_rtx (GET_MODE (operands[1]));
7839 operands[1] = replace_equiv_address (operands[1], gbr_mem);
7840 }
7841 else
7842 FAIL;
7843 })
7845 (define_split
7846 [(set (match_operand:QIHISIDI 0 "memory_operand")
7847 (match_operand:QIHISIDI 1 "register_operand"))]
7848 "TARGET_SH1 && !reload_in_progress && !reload_completed
7849 && df_regs_ever_live_p (GBR_REG)"
7850 [(set (match_dup 0) (match_dup 1))]
7851 {
7852 rtx gbr_mem = sh_find_equiv_gbr_addr (curr_insn, operands[0]);
7853 if (gbr_mem != NULL_RTX)
7854 operands[0] = replace_equiv_address (operands[0], gbr_mem);
7855 else
7856 FAIL;
7857 })
7859 ;;------------------------------------------------------------------------------
7860 ;; case instruction for switch statements.
7862 ;; operand 0 is index
7863 ;; operand 1 is the minimum bound
7864 ;; operand 2 is the maximum bound - minimum bound + 1
7865 ;; operand 3 is CODE_LABEL for the table;
7866 ;; operand 4 is the CODE_LABEL to go to if index out of range.
7867 (define_expand "casesi"
7868 [(match_operand:SI 0 "arith_reg_operand" "")
7869 (match_operand:SI 1 "arith_reg_operand" "")
7870 (match_operand:SI 2 "arith_reg_operand" "")
7871 (match_operand 3 "" "") (match_operand 4 "" "")]
7872 ""
7873 {
7874 rtx reg = gen_reg_rtx (SImode);
7875 rtx reg2 = gen_reg_rtx (SImode);
7877 operands[1] = copy_to_mode_reg (SImode, operands[1]);
7878 operands[2] = copy_to_mode_reg (SImode, operands[2]);
7879 /* If optimizing, casesi_worker depends on the mode of the instruction
7880 before label it 'uses' - operands[3]. */
7881 emit_insn (gen_casesi_0 (operands[0], operands[1], operands[2], operands[4],
7882 reg));
7883 emit_insn (gen_casesi_worker_0 (reg2, reg, operands[3]));
7884 if (TARGET_SH2)
7885 emit_jump_insn (gen_casesi_jump_2 (reg2, gen_label_rtx (), operands[3]));
7886 else
7887 emit_jump_insn (gen_casesi_jump_1 (reg2, operands[3]));
7888 /* For SH2 and newer, the ADDR_DIFF_VEC is not actually relative to
7889 operands[3], but to lab. We will fix this up in
7890 machine_dependent_reorg. */
7891 emit_barrier ();
7892 DONE;
7893 })
7895 (define_expand "casesi_0"
7896 [(set (match_operand:SI 4 "" "") (match_operand:SI 0 "arith_reg_operand" ""))
7897 (set (match_dup 4) (minus:SI (match_dup 4)
7898 (match_operand:SI 1 "arith_operand" "")))
7899 (set (reg:SI T_REG)
7900 (gtu:SI (match_dup 4)
7901 (match_operand:SI 2 "arith_reg_operand" "")))
7902 (set (pc)
7903 (if_then_else (ne (reg:SI T_REG)
7904 (const_int 0))
7905 (label_ref (match_operand 3 "" ""))
7906 (pc)))]
7907 "TARGET_SH1"
7908 "")
7910 ;; ??? reload might clobber r0 if we use it explicitly in the RTL before
7911 ;; reload; using a R0_REGS pseudo reg is likely to give poor code.
7912 ;; So we keep the use of r0 hidden in a R0_REGS clobber until after reload.
7913 ;;
7914 ;; The use on the T_REG in the casesi_worker* patterns links the bounds
7915 ;; checking insns and the table memory access. See also PR 69713.
7916 (define_insn "casesi_worker_0"
7917 [(set (match_operand:SI 0 "register_operand" "=r,r")
7918 (unspec:SI [(match_operand:SI 1 "register_operand" "0,r")
7919 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7920 (clobber (match_scratch:SI 3 "=X,1"))
7921 (clobber (match_scratch:SI 4 "=&z,z"))
7922 (use (reg:SI T_REG))]
7923 "TARGET_SH1"
7924 "#")
7926 (define_split
7927 [(set (match_operand:SI 0 "register_operand" "")
7928 (unspec:SI [(match_operand:SI 1 "register_operand" "")
7929 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7930 (clobber (match_scratch:SI 3 ""))
7931 (clobber (match_scratch:SI 4))
7932 (use (reg:SI T_REG))]
7933 "TARGET_SH1 && ! TARGET_SH2 && reload_completed"
7934 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
7935 (parallel [(set (match_dup 0)
7936 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
7937 (label_ref (match_dup 2))] UNSPEC_CASESI))
7938 (clobber (match_dup 3))])
7939 (set (match_dup 0) (plus:SI (match_dup 0) (reg:SI R0_REG)))]
7940 {
7941 if (GET_CODE (operands[2]) == CODE_LABEL)
7942 LABEL_NUSES (operands[2])++;
7943 })
7945 (define_split
7946 [(set (match_operand:SI 0 "register_operand" "")
7947 (unspec:SI [(match_operand:SI 1 "register_operand" "")
7948 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7949 (clobber (match_scratch:SI 3 ""))
7950 (clobber (match_scratch:SI 4))
7951 (use (reg:SI T_REG))]
7952 "TARGET_SH2 && reload_completed"
7953 [(set (reg:SI R0_REG) (unspec:SI [(label_ref (match_dup 2))] UNSPEC_MOVA))
7954 (parallel [(set (match_dup 0)
7955 (unspec:SI [(reg:SI R0_REG) (match_dup 1)
7956 (label_ref (match_dup 2))] UNSPEC_CASESI))
7957 (clobber (match_dup 3))])]
7958 {
7959 if (GET_CODE (operands[2]) == CODE_LABEL)
7960 LABEL_NUSES (operands[2])++;
7961 })
7963 ;; This may be replaced with casesi_worker_2 in sh_reorg for PIC.
7964 ;; The insn length is set to 8 for that case.
7965 (define_insn "casesi_worker_1"
7966 [(set (match_operand:SI 0 "register_operand" "=r,r")
7967 (unspec:SI [(reg:SI R0_REG)
7968 (match_operand:SI 1 "register_operand" "0,r")
7969 (label_ref (match_operand 2 "" ""))] UNSPEC_CASESI))
7970 (clobber (match_scratch:SI 3 "=X,1"))]
7971 "TARGET_SH1"
7972 {
7973 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2])));
7975 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
7977 switch (GET_MODE (diff_vec))
7978 {
7979 case E_SImode:
7980 return "shll2 %1" "\n"
7981 " mov.l @(r0,%1),%0";
7982 case E_HImode:
7983 return "add %1,%1" "\n"
7984 " mov.w @(r0,%1),%0";
7985 case E_QImode:
7986 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
7987 return "mov.b @(r0,%1),%0" "\n"
7988 " extu.b %0,%0";
7989 else
7990 return "mov.b @(r0,%1),%0";
7992 default:
7993 gcc_unreachable ();
7994 }
7995 }
7996 [(set_attr_alternative "length"
7997 [(if_then_else (match_test "flag_pic") (const_int 8) (const_int 4))
7998 (if_then_else (match_test "flag_pic") (const_int 8) (const_int 4))])])
8000 (define_insn "casesi_worker_2"
8001 [(set (match_operand:SI 0 "register_operand" "=r,r")
8002 (unspec:SI [(reg:SI R0_REG)
8003 (match_operand:SI 1 "register_operand" "0,r")
8004 (label_ref (match_operand 2 "" ""))
8005 (label_ref (match_operand 3 "" ""))] UNSPEC_CASESI))
8006 (clobber (match_operand:SI 4 "" "=X,1"))]
8007 "TARGET_SH2 && reload_completed && flag_pic"
8008 {
8009 rtx diff_vec = PATTERN (NEXT_INSN (as_a <rtx_insn *> (operands[2])));
8010 gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
8012 switch (GET_MODE (diff_vec))
8013 {
8014 case E_SImode:
8015 return "shll2 %1" "\n"
8016 " add r0,%1" "\n"
8017 " mova %O3,r0" "\n"
8018 " mov.l @(r0,%1),%0";
8019 case E_HImode:
8020 return "add %1,%1" "\n"
8021 " add r0,%1" "\n"
8022 " mova %O3,r0" "\n"
8023 " mov.w @(r0,%1),%0";
8024 case E_QImode:
8025 if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned)
8026 return "add r0,%1" "\n"
8027 " mova %O3,r0" "\n"
8028 " mov.b @(r0,%1),%0" "\n"
8029 " extu.b %0,%0";
8030 else
8031 return "add r0,%1" "\n"
8032 " mova %O3,r0" "\n"
8033 " mov.b @(r0,%1),%0";
8034 default:
8035 gcc_unreachable ();
8036 }
8037 }
8038 [(set_attr "length" "8")])
8040 (define_expand "simple_return"
8041 [(simple_return)]
8042 "sh_can_use_simple_return_p ()")
8044 (define_expand "return"
8045 [(return)]
8046 "reload_completed && epilogue_completed")
8048 (define_insn "*<code>_i"
8049 [(any_return)]
8050 "TARGET_SH1
8051 && reload_completed
8052 && ! sh_cfun_trap_exit_p ()"
8053 {
8054 if (TARGET_SH2A && (dbr_sequence_length () == 0)
8055 && !current_function_interrupt)
8056 return "rts/n";
8057 else
8058 return "%@ %#";
8059 }
8060 [(set_attr "type" "return")
8061 (set_attr "needs_delay_slot" "yes")])
8063 ;; trapa has no delay slot.
8064 (define_insn "*return_trapa"
8065 [(return)]
8066 "TARGET_SH1 && reload_completed"
8067 "%@"
8068 [(set_attr "type" "return")])
8070 (define_expand "prologue"
8071 [(const_int 0)]
8072 ""
8073 {
8074 sh_expand_prologue ();
8075 DONE;
8076 })
8078 (define_expand "epilogue"
8079 [(return)]
8080 ""
8081 {
8082 sh_expand_epilogue (false);
8083 })
8085 (define_expand "eh_return"
8086 [(use (match_operand 0 "register_operand" ""))]
8087 ""
8088 {
8089 emit_insn (gen_eh_set_ra_si (operands[0]));
8090 DONE;
8091 })
8093 ;; Clobber the return address on the stack. We can't expand this
8094 ;; until we know where it will be put in the stack frame.
8096 (define_insn "eh_set_ra_si"
8097 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
8098 UNSPECV_EH_RETURN)
8099 (clobber (match_scratch:SI 1 "=&r"))]
8100 ""
8101 "#")
8103 (define_split
8104 [(unspec_volatile [(match_operand 0 "register_operand" "")]
8105 UNSPECV_EH_RETURN)
8106 (clobber (match_scratch 1 ""))]
8107 "reload_completed"
8108 [(const_int 0)]
8109 {
8110 sh_set_return_address (operands[0], operands[1]);
8111 DONE;
8112 })
8114 (define_insn "blockage"
8115 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
8116 ""
8117 ""
8118 [(set_attr "length" "0")])
8119 \f
8120 ;; Define movml instructions for SH2A target. Currently they are
8121 ;; used to push and pop all banked registers only.
8123 (define_insn "movml_push_banked"
8124 [(set (match_operand:SI 0 "register_operand" "=r")
8125 (plus (match_dup 0) (const_int -32)))
8126 (set (mem:SI (plus:SI (match_dup 0) (const_int 28))) (reg:SI R7_REG))
8127 (set (mem:SI (plus:SI (match_dup 0) (const_int 24))) (reg:SI R6_REG))
8128 (set (mem:SI (plus:SI (match_dup 0) (const_int 20))) (reg:SI R5_REG))
8129 (set (mem:SI (plus:SI (match_dup 0) (const_int 16))) (reg:SI R4_REG))
8130 (set (mem:SI (plus:SI (match_dup 0) (const_int 12))) (reg:SI R3_REG))
8131 (set (mem:SI (plus:SI (match_dup 0) (const_int 8))) (reg:SI R2_REG))
8132 (set (mem:SI (plus:SI (match_dup 0) (const_int 4))) (reg:SI R1_REG))
8133 (set (mem:SI (plus:SI (match_dup 0) (const_int 0))) (reg:SI R0_REG))]
8134 "TARGET_SH2A && REGNO (operands[0]) == 15"
8135 "movml.l r7,@-r15"
8136 [(set_attr "in_delay_slot" "no")])
8138 (define_insn "movml_pop_banked"
8139 [(set (match_operand:SI 0 "register_operand" "=r")
8140 (plus (match_dup 0) (const_int 32)))
8141 (set (reg:SI R0_REG) (mem:SI (plus:SI (match_dup 0) (const_int -32))))
8142 (set (reg:SI R1_REG) (mem:SI (plus:SI (match_dup 0) (const_int -28))))
8143 (set (reg:SI R2_REG) (mem:SI (plus:SI (match_dup 0) (const_int -24))))
8144 (set (reg:SI R3_REG) (mem:SI (plus:SI (match_dup 0) (const_int -20))))
8145 (set (reg:SI R4_REG) (mem:SI (plus:SI (match_dup 0) (const_int -16))))
8146 (set (reg:SI R5_REG) (mem:SI (plus:SI (match_dup 0) (const_int -12))))
8147 (set (reg:SI R6_REG) (mem:SI (plus:SI (match_dup 0) (const_int -8))))
8148 (set (reg:SI R7_REG) (mem:SI (plus:SI (match_dup 0) (const_int -4))))]
8149 "TARGET_SH2A && REGNO (operands[0]) == 15"
8150 "movml.l @r15+,r7"
8151 [(set_attr "in_delay_slot" "no")])
8152 \f
8153 ;; ------------------------------------------------------------------------
8154 ;; Scc instructions
8155 ;; ------------------------------------------------------------------------
8157 (define_insn "movt"
8158 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8159 (match_operand:SI 1 "t_reg_operand"))]
8160 "TARGET_SH1"
8161 "movt %0"
8162 [(set_attr "type" "arith")])
8164 (define_insn "movrt"
8165 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8166 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
8167 "TARGET_SH2A"
8168 "movrt %0"
8169 [(set_attr "type" "arith")])
8171 (define_expand "cstoresi4"
8172 [(set (match_operand:SI 0 "register_operand")
8173 (match_operator:SI 1 "comparison_operator"
8174 [(match_operand:SI 2 "cmpsi_operand")
8175 (match_operand:SI 3 "arith_operand")]))]
8176 "TARGET_SH1"
8177 {
8178 if (sh_expand_t_scc (operands))
8179 DONE;
8181 if (! currently_expanding_to_rtl)
8182 FAIL;
8184 sh_emit_compare_and_set (operands, SImode);
8185 DONE;
8186 })
8188 (define_expand "cstoredi4"
8189 [(set (match_operand:SI 0 "register_operand")
8190 (match_operator:SI 1 "comparison_operator"
8191 [(match_operand:DI 2 "arith_operand")
8192 (match_operand:DI 3 "arith_operand")]))]
8193 "TARGET_SH2"
8194 {
8195 if (sh_expand_t_scc (operands))
8196 DONE;
8198 if (! currently_expanding_to_rtl)
8199 FAIL;
8201 sh_emit_compare_and_set (operands, DImode);
8202 DONE;
8203 })
8205 ;; Move the complement of the T reg to a reg.
8206 ;; On SH2A the movrt insn can be used.
8207 ;; On anything else than SH2A this has to be done with multiple instructions.
8208 ;; One obvious way would be:
8209 ;; cmp/eq ...
8210 ;; movt r0
8211 ;; xor #1,r0
8212 ;;
8213 ;; However, this puts pressure on r0 in most cases and thus the following is
8214 ;; more appealing:
8215 ;; cmp/eq ...
8216 ;; mov #-1,temp
8217 ;; negc temp,dest
8218 ;;
8219 ;; If the constant -1 can be CSE-ed or lifted out of a loop it effectively
8220 ;; becomes a one instruction operation. Moreover, care must be taken that
8221 ;; the insn can still be combined with inverted compare and branch code
8222 ;; around it. On the other hand, if a function returns the complement of
8223 ;; a previous comparison result in the T bit, the xor #1,r0 approach might
8224 ;; lead to better code.
8225 (define_expand "movnegt"
8226 [(set (match_operand:SI 0 "arith_reg_dest" "")
8227 (xor:SI (match_operand:SI 1 "t_reg_operand" "") (const_int 1)))]
8228 "TARGET_SH1"
8229 {
8230 if (TARGET_SH2A)
8231 emit_insn (gen_movrt (operands[0], operands[1]));
8232 else
8233 {
8234 rtx val = force_reg (SImode, gen_int_mode (-1, SImode));
8235 emit_insn (gen_movrt_negc (operands[0], operands[1], val));
8236 }
8237 DONE;
8238 })
8240 (define_insn_and_split "movrt_negc"
8241 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8242 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
8243 (set (reg:SI T_REG) (const_int 1))
8244 (use (match_operand:SI 2 "arith_reg_operand" "r"))]
8245 "TARGET_SH1"
8246 "negc %2,%0"
8247 "&& !sh_in_recog_treg_set_expr ()"
8248 [(const_int 0)]
8249 {
8250 if (sh_split_movrt_negc_to_movt_xor (curr_insn, operands))
8251 DONE;
8252 else
8253 FAIL;
8254 }
8255 [(set_attr "type" "arith")])
8257 ;; The -1 constant will not be CSE-ed for the *movrt_negc pattern, but the
8258 ;; pattern can be used by the combine pass. Using a scratch reg for the
8259 ;; -1 constant results in slightly better register allocations compared to
8260 ;; generating a pseudo reg before reload.
8261 (define_insn_and_split "*movrt_negc"
8262 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8263 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
8264 (clobber (match_scratch:SI 2 "=r"))
8265 (clobber (reg:SI T_REG))]
8266 "TARGET_SH1 && ! TARGET_SH2A"
8267 "#"
8268 "&& !sh_in_recog_treg_set_expr ()"
8269 [(const_int 0)]
8270 {
8271 if (sh_split_movrt_negc_to_movt_xor (curr_insn, operands))
8272 DONE;
8273 else if (reload_completed)
8274 {
8275 emit_move_insn (operands[2], gen_int_mode (-1, SImode));
8276 emit_insn (gen_movrt_negc (operands[0], operands[1], operands[2]));
8277 DONE;
8278 }
8279 else
8280 FAIL;
8281 })
8283 ;; Store the negated T bit in a reg using r0 and xor. This one doesn't
8284 ;; clobber the T bit, which is useful when storing the T bit and the
8285 ;; negated T bit in parallel. On SH2A the movrt insn can be used for that.
8286 ;; Usually we don't want this insn to be matched, except for cases where the
8287 ;; T bit clobber is really not appreciated. Hence the extra use on T_REG.
8288 (define_insn_and_split "movrt_xor"
8289 [(set (match_operand:SI 0 "arith_reg_dest" "=z")
8290 (xor:SI (match_operand:SI 1 "t_reg_operand") (const_int 1)))
8291 (use (reg:SI T_REG))]
8292 "TARGET_SH1"
8293 "#"
8294 "&& reload_completed"
8295 [(set (match_dup 0) (reg:SI T_REG))
8296 (set (match_dup 0) (xor:SI (match_dup 0) (const_int 1)))])
8298 ;; 0x7fffffff + T
8299 ;; 0x7fffffff + (1-T) = 0 - 0x80000000 - T
8300 ;;
8301 ;; Notice that 0 - 0x80000000 = 0x80000000.
8303 ;; Single bit tests are usually done with zero_extract. On non-SH2A this
8304 ;; will use a tst-negc sequence. On SH2A it will use a bld-addc sequence.
8305 ;; The zeroth bit requires a special pattern, otherwise we get a shlr-addc.
8306 ;; This is a special case of the generic treg_set_expr pattern and thus has
8307 ;; to come first or it will never match.
8308 (define_insn_and_split "*mov_t_msb_neg"
8309 [(set (match_operand:SI 0 "arith_reg_dest")
8310 (plus:SI (and:SI (match_operand:SI 1 "arith_reg_operand")
8311 (const_int 1))
8312 (const_int 2147483647)))
8313 (clobber (reg:SI T_REG))]
8314 "TARGET_SH1"
8315 "#"
8316 "&& can_create_pseudo_p ()"
8317 [(parallel [(set (match_dup 0)
8318 (plus:SI (zero_extract:SI (match_dup 1)
8319 (const_int 1) (const_int 0))
8320 (const_int 2147483647)))
8321 (clobber (reg:SI T_REG))])])
8323 (define_insn_and_split "*mov_t_msb_neg"
8324 [(set (match_operand:SI 0 "arith_reg_dest")
8325 (plus:SI (match_operand 1 "treg_set_expr")
8326 (const_int 2147483647))) ;; 0x7fffffff
8327 (clobber (reg:SI T_REG))]
8328 "TARGET_SH1"
8329 "#"
8330 "&& can_create_pseudo_p ()"
8331 [(const_int 0)]
8332 {
8333 if (negt_reg_operand (operands[1], VOIDmode))
8334 {
8335 emit_insn (gen_negc (operands[0],
8336 force_reg (SImode, GEN_INT (-2147483648LL))));
8337 DONE;
8338 }
8340 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8341 if (ti.remove_trailing_nott ())
8342 emit_insn (gen_negc (operands[0],
8343 force_reg (SImode, GEN_INT (-2147483648LL))));
8344 else
8345 emit_insn (gen_addc (operands[0],
8346 force_reg (SImode, const0_rtx),
8347 force_reg (SImode, GEN_INT (2147483647))));
8348 DONE;
8349 })
8351 (define_insn_and_split "*mov_t_msb_neg"
8352 [(set (match_operand:SI 0 "arith_reg_dest")
8353 (if_then_else:SI (match_operand 1 "treg_set_expr")
8354 (match_operand 2 "const_int_operand")
8355 (match_operand 3 "const_int_operand")))
8356 (clobber (reg:SI T_REG))]
8357 "TARGET_SH1 && can_create_pseudo_p ()
8358 && ((INTVAL (operands[2]) == -2147483648LL
8359 && INTVAL (operands[3]) == 2147483647LL)
8360 || (INTVAL (operands[2]) == 2147483647LL
8361 && INTVAL (operands[3]) == -2147483648LL))"
8362 "#"
8363 "&& 1"
8364 [(const_int 0)]
8365 {
8366 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8368 if (INTVAL (operands[2]) == -2147483648LL)
8369 {
8370 if (ti.remove_trailing_nott ())
8371 emit_insn (gen_negc (operands[0],
8372 force_reg (SImode, GEN_INT (-2147483648LL))));
8373 else
8374 emit_insn (gen_addc (operands[0],
8375 force_reg (SImode, const0_rtx),
8376 force_reg (SImode, operands[3])));
8377 DONE;
8378 }
8379 else if (INTVAL (operands[2]) == 2147483647LL)
8380 {
8381 if (ti.remove_trailing_nott ())
8382 emit_insn (gen_addc (operands[0],
8383 force_reg (SImode, const0_rtx),
8384 force_reg (SImode, GEN_INT (2147483647LL))));
8385 else
8386 emit_insn (gen_negc (operands[0],
8387 force_reg (SImode, GEN_INT (-2147483648LL))));
8388 DONE;
8389 }
8390 else
8391 gcc_unreachable ();
8392 })
8394 ;; Store (negated) T bit as all zeros or ones in a reg.
8395 ;; subc Rn,Rn ! Rn = Rn - Rn - T; T = T
8396 ;; not Rn,Rn ! Rn = 0 - Rn
8397 ;;
8398 ;; Note the call to sh_split_treg_set_expr may clobber
8399 ;; the T reg. We must express this, even though it's
8400 ;; not immediately obvious this pattern changes the
8401 ;; T register.
8402 (define_insn_and_split "mov_neg_si_t"
8403 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8404 (neg:SI (match_operand 1 "treg_set_expr")))
8405 (clobber (reg:SI T_REG))]
8406 "TARGET_SH1"
8407 {
8408 gcc_assert (t_reg_operand (operands[1], VOIDmode));
8409 return "subc %0,%0";
8410 }
8411 "&& can_create_pseudo_p () && !t_reg_operand (operands[1], VOIDmode)"
8412 [(const_int 0)]
8413 {
8414 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8415 emit_insn (gen_mov_neg_si_t (operands[0], get_t_reg_rtx ()));
8417 if (ti.remove_trailing_nott ())
8418 emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));
8420 DONE;
8421 }
8422 [(set_attr "type" "arith")])
8424 ;; Invert the T bit.
8425 ;; On SH2A we can use the nott insn. On anything else this must be done with
8426 ;; multiple insns like:
8427 ;; movt Rn
8428 ;; tst Rn,Rn
8429 ;; This requires an additional pseudo. The SH specific sh_treg_combine RTL
8430 ;; pass will look for this insn. Disallow using it if pseudos can't be
8431 ;; created.
8432 ;; Don't split the nott inside the splitting of a treg_set_expr, or else
8433 ;; surrounding insns might not see and recombine it. Defer the splitting
8434 ;; of the nott until after the whole insn containing the treg_set_expr
8435 ;; has been split.
8436 (define_insn_and_split "nott"
8437 [(set (reg:SI T_REG)
8438 (xor:SI (match_operand:SI 0 "t_reg_operand") (const_int 1)))]
8439 "TARGET_SH2A || (TARGET_SH1 && can_create_pseudo_p ())"
8440 {
8441 gcc_assert (TARGET_SH2A);
8442 return "nott";
8443 }
8444 "!TARGET_SH2A && can_create_pseudo_p () && !sh_in_recog_treg_set_expr ()"
8445 [(set (match_dup 0) (reg:SI T_REG))
8446 (set (reg:SI T_REG) (eq:SI (match_dup 0) (const_int 0)))]
8447 {
8448 operands[0] = gen_reg_rtx (SImode);
8449 })
8451 ;; Store T bit as MSB in a reg.
8452 ;; T = 0: 0x00000000 -> reg
8453 ;; T = 1: 0x80000000 -> reg
8454 (define_insn_and_split "*movt_msb"
8455 [(set (match_operand:SI 0 "arith_reg_dest")
8456 (mult:SI (match_operand:SI 1 "t_reg_operand")
8457 (const_int -2147483648))) ;; 0xffffffff80000000
8458 (clobber (reg:SI T_REG))]
8459 "TARGET_SH1"
8460 "#"
8461 "&& 1"
8462 [(set (match_dup 0) (ashift:SI (reg:SI T_REG) (const_int 31)))])
8464 ;; Store inverted T bit as MSB in a reg.
8465 ;; T = 0: 0x80000000 -> reg
8466 ;; T = 1: 0x00000000 -> reg
8467 ;; On SH2A we can get away without clobbering the T_REG using the movrt insn.
8468 ;; On non SH2A we resort to the following sequence:
8469 ;; movt Rn
8470 ;; tst Rn,Rn
8471 ;; rotcr Rn
8472 ;; The T bit value will be modified during the sequence, but the rotcr insn
8473 ;; will restore its original value.
8474 (define_insn_and_split "*negt_msb"
8475 [(set (match_operand:SI 0 "arith_reg_dest")
8476 (match_operand:SI 1 "negt_reg_shl31_operand"))]
8477 "TARGET_SH1"
8478 "#"
8479 "&& can_create_pseudo_p ()"
8480 [(const_int 0)]
8481 {
8482 rtx tmp = gen_reg_rtx (SImode);
8484 if (TARGET_SH2A)
8485 {
8486 emit_insn (gen_movrt (tmp, get_t_reg_rtx ()));
8487 emit_insn (gen_rotrsi3 (operands[0], tmp, const1_rtx));
8488 }
8489 else
8490 {
8491 emit_move_insn (tmp, get_t_reg_rtx ());
8492 emit_insn (gen_cmpeqsi_t (tmp, const0_rtx));
8493 emit_insn (gen_rotcr (operands[0], tmp, get_t_reg_rtx ()));
8494 }
8495 DONE;
8496 })
8498 ;; The *cset_zero patterns convert optimizations such as
8499 ;; "if (test) x = 0;"
8500 ;; to
8501 ;; "x &= -(test == 0);"
8502 ;; back to conditional branch sequences if zero-displacement branches
8503 ;; are enabled.
8504 ;; FIXME: These patterns can be removed when conditional execution patterns
8505 ;; are implemented, since ifcvt will not perform these optimizations if
8506 ;; conditional execution is supported.
8507 (define_insn "*cset_zero"
8508 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8509 (and:SI (plus:SI (match_operand:SI 1 "t_reg_operand")
8510 (const_int -1))
8511 (match_operand:SI 2 "arith_reg_operand" "0")))]
8512 "TARGET_SH1 && TARGET_ZDCBRANCH"
8513 {
8514 return "bf 0f" "\n"
8515 " mov #0,%0" "\n"
8516 "0:";
8517 }
8518 [(set_attr "type" "arith") ;; poor approximation
8519 (set_attr "length" "4")])
8521 (define_insn "*cset_zero"
8522 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8523 (if_then_else:SI (match_operand:SI 1 "cbranch_treg_value")
8524 (match_operand:SI 2 "arith_reg_operand" "0")
8525 (const_int 0)))]
8526 "TARGET_SH1 && TARGET_ZDCBRANCH"
8527 {
8528 int tval = sh_eval_treg_value (operands[1]);
8529 if (tval == true)
8530 return "bt 0f" "\n"
8531 " mov #0,%0" "\n"
8532 "0:";
8533 else if (tval == false)
8534 return "bf 0f" "\n"
8535 " mov #0,%0" "\n"
8536 "0:";
8537 else
8538 gcc_unreachable ();
8539 }
8540 [(set_attr "type" "arith") ;; poor approximation
8541 (set_attr "length" "4")])
8543 (define_insn_and_split "*cset_zero"
8544 [(set (match_operand:SI 0 "arith_reg_dest")
8545 (if_then_else:SI (match_operand 1 "treg_set_expr_not_const01")
8546 (match_dup 0) (const_int 0)))
8547 (clobber (reg:SI T_REG))]
8548 "TARGET_SH1 && TARGET_ZDCBRANCH && can_create_pseudo_p ()"
8549 "#"
8550 "&& 1"
8551 [(set (match_dup 0)
8552 (if_then_else:SI (match_dup 1) (match_dup 0) (const_int 0)))]
8553 {
8554 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8555 if (ti.remove_trailing_nott ())
8556 operands[1] = gen_rtx_EQ (SImode, get_t_reg_rtx (), const0_rtx);
8557 else
8558 operands[1] = gen_rtx_EQ (SImode, get_t_reg_rtx (), const1_rtx);
8559 })
8561 (define_expand "cstoresf4"
8562 [(set (match_operand:SI 0 "register_operand")
8563 (match_operator:SI 1 "ordered_comparison_operator"
8564 [(match_operand:SF 2 "arith_operand")
8565 (match_operand:SF 3 "arith_operand")]))]
8566 "TARGET_SH2E"
8567 {
8568 if (! currently_expanding_to_rtl)
8569 FAIL;
8571 sh_emit_compare_and_set (operands, SFmode);
8572 DONE;
8573 })
8575 (define_expand "cstoredf4"
8576 [(set (match_operand:SI 0 "register_operand")
8577 (match_operator:SI 1 "ordered_comparison_operator"
8578 [(match_operand:DF 2 "arith_operand")
8579 (match_operand:DF 3 "arith_operand")]))]
8580 "TARGET_FPU_DOUBLE"
8581 {
8582 if (! currently_expanding_to_rtl)
8583 FAIL;
8585 sh_emit_compare_and_set (operands, DFmode);
8586 DONE;
8587 })
8589 ;; Sometimes the T bit result of insns is needed in normal registers.
8590 ;; Instead of open coding all the pattern variations, use the treg_set_expr
8591 ;; predicate to match any T bit output insn and split it out after.
8592 ;; This pattern should be below all other related patterns so that it is
8593 ;; considered as a last resort option during matching. This allows
8594 ;; overriding it with special case patterns.
8595 (define_insn_and_split "any_treg_expr_to_reg"
8596 [(set (match_operand:SI 0 "arith_reg_dest")
8597 (match_operand 1 "treg_set_expr"))
8598 (clobber (reg:SI T_REG))]
8599 "TARGET_SH1 && can_create_pseudo_p ()"
8600 "#"
8601 "&& !sh_in_recog_treg_set_expr ()"
8602 [(const_int 0)]
8603 {
8604 if (dump_file)
8605 fprintf (dump_file, "splitting any_treg_expr_to_reg\n");
8607 if (t_reg_operand (operands[1], VOIDmode))
8608 {
8609 if (dump_file)
8610 fprintf (dump_file, "t_reg_operand: emitting movt\n");
8611 emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
8612 DONE;
8613 }
8614 if (negt_reg_operand (operands[1], VOIDmode))
8615 {
8616 if (dump_file)
8617 fprintf (dump_file, "negt_reg_operand: emitting movrt\n");
8618 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
8619 DONE;
8620 }
8622 /* If the split out insns ended with a nott, emit a movrt sequence,
8623 otherwise a normal movt. */
8624 sh_treg_insns ti = sh_split_treg_set_expr (operands[1], curr_insn);
8625 rtx_insn* i = NULL;
8626 if (ti.remove_trailing_nott ())
8627 {
8628 /* Emit this same insn_and_split again. However, the next time it
8629 is split, it will emit the actual negc/movrt insn. This gives
8630 other surrounding insns the chance to see the trailing movrt. */
8631 if (dump_file)
8632 fprintf (dump_file,
8633 "any_treg_expr_to_reg: replacing trailing nott with movrt\n");
8634 i = emit_insn (gen_any_treg_expr_to_reg (
8635 operands[0], gen_rtx_XOR (SImode, get_t_reg_rtx (),
8636 const1_rtx)));
8637 }
8638 else
8639 {
8640 i = emit_insn (gen_movt (operands[0], get_t_reg_rtx ()));
8641 if (dump_file)
8642 fprintf (dump_file, "any_treg_expr_to_reg: appending movt\n");
8643 }
8645 add_reg_note (i, REG_UNUSED, get_t_reg_rtx ());
8646 DONE;
8647 })
8649 ;; -------------------------------------------------------------------------
8650 ;; Instructions to cope with inline literal tables
8651 ;; -------------------------------------------------------------------------
8653 ;; 2 byte integer in line
8654 (define_insn "consttable_2"
8655 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
8656 (match_operand 1 "" "")]
8657 UNSPECV_CONST2)]
8658 ""
8659 {
8660 if (operands[1] != const0_rtx)
8661 assemble_integer (operands[0], 2, BITS_PER_UNIT * 2, 1);
8662 return "";
8663 }
8664 [(set_attr "length" "2")
8665 (set_attr "in_delay_slot" "no")])
8667 ;; 4 byte integer in line
8668 (define_insn "consttable_4"
8669 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
8670 (match_operand 1 "" "")]
8671 UNSPECV_CONST4)]
8672 ""
8673 {
8674 if (operands[1] != const0_rtx)
8675 {
8676 assemble_integer (operands[0], 4, BITS_PER_UNIT * 4, 1);
8677 mark_symbol_refs_as_used (operands[0]);
8678 }
8679 return "";
8680 }
8681 [(set_attr "length" "4")
8682 (set_attr "in_delay_slot" "no")])
8684 ;; 8 byte integer in line
8685 (define_insn "consttable_8"
8686 [(unspec_volatile [(match_operand:SI 0 "general_operand" "=g")
8687 (match_operand 1 "" "")]
8688 UNSPECV_CONST8)]
8689 ""
8690 {
8691 if (operands[1] != const0_rtx)
8692 assemble_integer (operands[0], 8, BITS_PER_UNIT * 8, 1);
8693 return "";
8694 }
8695 [(set_attr "length" "8")
8696 (set_attr "in_delay_slot" "no")])
8698 ;; 4 byte floating point
8699 (define_insn "consttable_sf"
8700 [(unspec_volatile [(match_operand:SF 0 "general_operand" "=g")
8701 (match_operand 1 "" "")]
8702 UNSPECV_CONST4)]
8703 ""
8704 {
8705 if (operands[1] != const0_rtx)
8706 assemble_real (*CONST_DOUBLE_REAL_VALUE (operands[0]),
8707 SFmode, GET_MODE_ALIGNMENT (SFmode));
8708 return "";
8709 }
8710 [(set_attr "length" "4")
8711 (set_attr "in_delay_slot" "no")])
8713 ;; 8 byte floating point
8714 (define_insn "consttable_df"
8715 [(unspec_volatile [(match_operand:DF 0 "general_operand" "=g")
8716 (match_operand 1 "" "")]
8717 UNSPECV_CONST8)]
8718 ""
8719 {
8720 if (operands[1] != const0_rtx)
8721 assemble_real (*CONST_DOUBLE_REAL_VALUE (operands[0]),
8722 DFmode, GET_MODE_ALIGNMENT (DFmode));
8723 return "";
8724 }
8725 [(set_attr "length" "8")
8726 (set_attr "in_delay_slot" "no")])
8728 ;; Alignment is needed for some constant tables; it may also be added for
8729 ;; Instructions at the start of loops, or after unconditional branches.
8730 ;; ??? We would get more accurate lengths if we did instruction
8731 ;; alignment based on the value of INSN_CURRENT_ADDRESS; the approach used
8732 ;; here is too conservative.
8734 ;; align to a two byte boundary
8735 (define_expand "align_2"
8736 [(unspec_volatile [(const_int 1)] UNSPECV_ALIGN)]
8737 ""
8738 "")
8740 ;; Align to a four byte boundary.
8741 ;; align_4 and align_log are instructions for the starts of loops, or
8742 ;; after unconditional branches, which may take up extra room.
8743 (define_expand "align_4"
8744 [(unspec_volatile [(const_int 2)] UNSPECV_ALIGN)]
8745 ""
8746 "")
8748 ;; Align to a cache line boundary.
8749 (define_insn "align_log"
8750 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPECV_ALIGN)]
8751 ""
8752 ""
8753 [(set_attr "length" "0")
8754 (set_attr "in_delay_slot" "no")])
8756 ;; Emitted at the end of the literal table, used to emit the
8757 ;; 32bit branch labels if needed.
8758 (define_insn "consttable_end"
8759 [(unspec_volatile [(const_int 0)] UNSPECV_CONST_END)]
8760 ""
8761 {
8762 return output_jump_label_table ();
8763 }
8764 [(set_attr "in_delay_slot" "no")])
8766 ;; Emitted at the end of the window in the literal table.
8767 (define_insn "consttable_window_end"
8768 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_WINDOW_END)]
8769 ""
8770 ""
8771 [(set_attr "length" "0")
8772 (set_attr "in_delay_slot" "no")])
8774 ;; -------------------------------------------------------------------------
8775 ;; Minimum / maximum operations.
8776 ;; -------------------------------------------------------------------------
8778 ;; The SH2A clips.b and clips.w insns do a signed min-max function. If smin
8779 ;; and smax standard name patterns are defined, they will be used during
8780 ;; initial expansion and combine will then be able to form the actual min-max
8781 ;; pattern.
8782 ;; The clips.b and clips.w set the SR.CS bit if the value in the register is
8783 ;; clipped, but there is currently no way of making use of this information.
8784 ;; The only way to read or reset the SR.CS bit is by accessing the SR.
8785 (define_expand "<code>si3"
8786 [(parallel [(set (match_operand:SI 0 "arith_reg_dest")
8787 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand")
8788 (match_operand 2 "const_int_operand")))
8789 (clobber (reg:SI T_REG))])]
8790 "TARGET_SH2A"
8791 {
8792 /* Force the comparison value into a register, because greater-than
8793 comparisons can work only on registers. Combine will be able to pick up
8794 the constant value from the REG_EQUAL note when trying to form a min-max
8795 pattern. */
8796 operands[2] = force_reg (SImode, operands[2]);
8797 })
8799 ;; Convert
8800 ;; smax (smin (...))
8801 ;; to
8802 ;; smin (smax (...))
8803 (define_insn_and_split "*clips"
8804 [(set (match_operand:SI 0 "arith_reg_dest")
8805 (smax:SI (smin:SI (match_operand:SI 1 "arith_reg_operand")
8806 (match_operand 2 "clips_max_const_int"))
8807 (match_operand 3 "clips_min_const_int")))]
8808 "TARGET_SH2A"
8809 "#"
8810 "&& 1"
8811 [(set (match_dup 0)
8812 (smin:SI (smax:SI (match_dup 1) (match_dup 3)) (match_dup 2)))])
8814 (define_insn "*clips"
8815 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8816 (smin:SI (smax:SI (match_operand:SI 1 "arith_reg_operand" "0")
8817 (match_operand 2 "clips_min_const_int"))
8818 (match_operand 3 "clips_max_const_int")))]
8819 "TARGET_SH2A"
8820 {
8821 if (INTVAL (operands[3]) == 127)
8822 return "clips.b %0";
8823 else if (INTVAL (operands[3]) == 32767)
8824 return "clips.w %0";
8825 else
8826 gcc_unreachable ();
8827 }
8828 [(set_attr "type" "arith")])
8830 ;; If the expanded smin or smax patterns were not combined, split them into
8831 ;; a compare and branch sequence, because there are no real smin or smax
8832 ;; insns.
8833 (define_insn_and_split "*<code>si3"
8834 [(set (match_operand:SI 0 "arith_reg_dest")
8835 (SMIN_SMAX:SI (match_operand:SI 1 "arith_reg_operand")
8836 (match_operand:SI 2 "arith_reg_or_0_or_1_operand")))
8837 (clobber (reg:SI T_REG))]
8838 "TARGET_SH2A && can_create_pseudo_p ()"
8839 "#"
8840 "&& 1"
8841 [(const_int 0)]
8842 {
8843 rtx_code_label *skip_label = gen_label_rtx ();
8844 emit_move_insn (operands[0], operands[1]);
8846 rtx cmp_val = operands[2];
8847 if (satisfies_constraint_M (cmp_val))
8848 cmp_val = const0_rtx;
8850 emit_insn (gen_cmpgtsi_t (operands[0], cmp_val));
8851 emit_jump_insn (<CODE> == SMIN
8852 ? gen_branch_false (skip_label)
8853 : gen_branch_true (skip_label));
8855 emit_label_after (skip_label, emit_move_insn (operands[0], operands[2]));
8856 DONE;
8857 })
8859 ;; The SH2A clipu.b and clipu.w insns can be used to implement a min function
8860 ;; with a register and a constant.
8861 ;; The clipu.b and clipu.w set the SR.CS bit if the value in the register is
8862 ;; clipped, but there is currently no way of making use of this information.
8863 ;; The only way to read or reset the SR.CS bit is by accessing the SR.
8864 (define_expand "uminsi3"
8865 [(set (match_operand:SI 0 "arith_reg_dest")
8866 (umin:SI (match_operand:SI 1 "arith_reg_operand")
8867 (match_operand 2 "const_int_operand")))]
8868 "TARGET_SH2A"
8869 {
8870 if (INTVAL (operands[2]) == 1)
8871 {
8872 emit_insn (gen_clipu_one (operands[0], operands[1]));
8873 DONE;
8874 }
8875 else if (! clipu_max_const_int (operands[2], VOIDmode))
8876 FAIL;
8877 })
8879 (define_insn "*clipu"
8880 [(set (match_operand:SI 0 "arith_reg_dest" "=r")
8881 (umin:SI (match_operand:SI 1 "arith_reg_operand" "0")
8882 (match_operand 2 "clipu_max_const_int")))]
8883 "TARGET_SH2A"
8884 {
8885 if (INTVAL (operands[2]) == 255)
8886 return "clipu.b %0";
8887 else if (INTVAL (operands[2]) == 65535)
8888 return "clipu.w %0";
8889 else
8890 gcc_unreachable ();
8891 }
8892 [(set_attr "type" "arith")])
8894 (define_insn_and_split "clipu_one"
8895 [(set (match_operand:SI 0 "arith_reg_dest")
8896 (umin:SI (match_operand:SI 1 "arith_reg_operand") (const_int 1)))
8897 (clobber (reg:SI T_REG))]
8898 "TARGET_SH2A"
8899 "#"
8900 "&& can_create_pseudo_p ()"
8901 [(const_int 0)]
8902 {
8903 emit_insn (gen_cmpeqsi_t (operands[1], const0_rtx));
8904 emit_insn (gen_movnegt (operands[0], get_t_reg_rtx ()));
8905 DONE;
8906 })
8908 ;; -------------------------------------------------------------------------
8909 ;; Misc
8910 ;; -------------------------------------------------------------------------
8912 ;; String/block move insn.
8914 (define_expand "cpymemsi"
8915 [(parallel [(set (mem:BLK (match_operand:BLK 0))
8916 (mem:BLK (match_operand:BLK 1)))
8917 (use (match_operand:SI 2 "nonmemory_operand"))
8918 (use (match_operand:SI 3 "immediate_operand"))
8919 (clobber (reg:SI PR_REG))
8920 (clobber (reg:SI R4_REG))
8921 (clobber (reg:SI R5_REG))
8922 (clobber (reg:SI R0_REG))])]
8923 "TARGET_SH1"
8924 {
8925 if (expand_block_move (operands))
8926 DONE;
8927 else
8928 FAIL;
8929 })
8931 (define_insn "block_move_real"
8932 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8933 (mem:BLK (reg:SI R5_REG)))
8934 (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
8935 (use (match_operand 1 "" "Z,Ccl"))
8936 (clobber (reg:SI PR_REG))
8937 (clobber (reg:SI R0_REG))])]
8938 "TARGET_SH1 && ! TARGET_HARD_SH4"
8939 "@
8940 jsr @%0%#
8941 bsrf %0\n%O1:%#"
8942 [(set_attr "type" "sfunc")
8943 (set_attr "needs_delay_slot" "yes")])
8945 (define_insn "block_lump_real"
8946 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8947 (mem:BLK (reg:SI R5_REG)))
8948 (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
8949 (use (match_operand 1 "" "Z,Ccl"))
8950 (use (reg:SI R6_REG))
8951 (clobber (reg:SI PR_REG))
8952 (clobber (reg:SI T_REG))
8953 (clobber (reg:SI R4_REG))
8954 (clobber (reg:SI R5_REG))
8955 (clobber (reg:SI R6_REG))
8956 (clobber (reg:SI R0_REG))])]
8957 "TARGET_SH1 && ! TARGET_HARD_SH4"
8958 "@
8959 jsr @%0%#
8960 bsrf %0\n%O1:%#"
8961 [(set_attr "type" "sfunc")
8962 (set_attr "needs_delay_slot" "yes")])
8964 (define_insn "block_move_real_i4"
8965 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8966 (mem:BLK (reg:SI R5_REG)))
8967 (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
8968 (use (match_operand 1 "" "Z,Ccl"))
8969 (clobber (reg:SI PR_REG))
8970 (clobber (reg:SI R0_REG))
8971 (clobber (reg:SI R1_REG))
8972 (clobber (reg:SI R2_REG))])]
8973 "TARGET_HARD_SH4"
8974 "@
8975 jsr @%0%#
8976 bsrf %0\n%O1:%#"
8977 [(set_attr "type" "sfunc")
8978 (set_attr "needs_delay_slot" "yes")])
8980 (define_insn "block_lump_real_i4"
8981 [(parallel [(set (mem:BLK (reg:SI R4_REG))
8982 (mem:BLK (reg:SI R5_REG)))
8983 (use (match_operand:SI 0 "arith_reg_operand" "r,r"))
8984 (use (match_operand 1 "" "Z,Ccl"))
8985 (use (reg:SI R6_REG))
8986 (clobber (reg:SI PR_REG))
8987 (clobber (reg:SI T_REG))
8988 (clobber (reg:SI R4_REG))
8989 (clobber (reg:SI R5_REG))
8990 (clobber (reg:SI R6_REG))
8991 (clobber (reg:SI R0_REG))
8992 (clobber (reg:SI R1_REG))
8993 (clobber (reg:SI R2_REG))
8994 (clobber (reg:SI R3_REG))])]
8995 "TARGET_HARD_SH4"
8996 "@
8997 jsr @%0%#
8998 bsrf %0\n%O1:%#"
8999 [(set_attr "type" "sfunc")
9000 (set_attr "needs_delay_slot" "yes")])
9002 ;; byte compare pattern
9003 ;; temp = a ^ b;
9004 ;; !((temp & 0xF000) && (temp & 0x0F00) && (temp & 0x00F0) && (temp & 0x000F))
9005 (define_insn "cmpstr_t"
9006 [(set (reg:SI T_REG)
9007 (eq:SI (and:SI
9008 (and:SI
9009 (and:SI
9010 (zero_extract:SI
9011 (xor:SI (match_operand:SI 0 "arith_reg_operand" "r")
9012 (match_operand:SI 1 "arith_reg_operand" "r"))
9013 (const_int 8) (const_int 0))
9014 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
9015 (const_int 8) (const_int 8)))
9016 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
9017 (const_int 8) (const_int 16)))
9018 (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
9019 (const_int 8) (const_int 24)))
9020 (const_int 0)))]
9021 "TARGET_SH1"
9022 "cmp/str %0,%1"
9023 [(set_attr "type" "mt_group")])
9025 (define_expand "cmpstrsi"
9026 [(set (match_operand:SI 0 "register_operand")
9027 (compare:SI (match_operand:BLK 1 "memory_operand")
9028 (match_operand:BLK 2 "memory_operand")))
9029 (use (match_operand 3 "immediate_operand"))]
9030 "TARGET_SH1 && optimize"
9031 {
9032 if (! optimize_insn_for_size_p () && sh_expand_cmpstr (operands))
9033 DONE;
9034 else
9035 FAIL;
9036 })
9038 (define_expand "cmpstrnsi"
9039 [(set (match_operand:SI 0 "register_operand")
9040 (compare:SI (match_operand:BLK 1 "memory_operand")
9041 (match_operand:BLK 2 "memory_operand")))
9042 (use (match_operand:SI 3 "nonmemory_operand"))
9043 (use (match_operand:SI 4 "immediate_operand"))]
9044 "TARGET_SH1 && optimize"
9045 {
9046 if (! optimize_insn_for_size_p () && sh_expand_cmpnstr (operands))
9047 DONE;
9048 else
9049 FAIL;
9050 })
9052 (define_expand "strlensi"
9053 [(set (match_operand:SI 0 "register_operand")
9054 (unspec:SI [(match_operand:BLK 1 "memory_operand")
9055 (match_operand:SI 2 "immediate_operand")
9056 (match_operand:SI 3 "immediate_operand")]
9057 UNSPEC_BUILTIN_STRLEN))]
9058 "TARGET_SH1 && optimize"
9059 {
9060 if (! optimize_insn_for_size_p () && sh_expand_strlen (operands))
9061 DONE;
9062 else
9063 FAIL;
9064 })
9066 (define_expand "setmemqi"
9067 [(parallel [(set (match_operand:BLK 0 "memory_operand")
9068 (match_operand 2 "const_int_operand"))
9069 (use (match_operand:QI 1 "const_int_operand"))
9070 (use (match_operand:QI 3 "const_int_operand"))])]
9071 "TARGET_SH1 && optimize"
9072 {
9073 if (optimize_insn_for_size_p ())
9074 FAIL;
9076 sh_expand_setmem (operands);
9077 DONE;
9078 })
9080 \f
9081 ;; -------------------------------------------------------------------------
9082 ;; Floating point instructions.
9083 ;; -------------------------------------------------------------------------
9085 ;; FIXME: For now we disallow any memory operands for fpscr loads/stores,
9086 ;; except for post-inc loads and pre-dec stores for push/pop purposes.
9087 ;; This avoids problems with reload. As a consequence, user initiated fpscr
9088 ;; stores to memory will always be ferried through a general register.
9089 ;; User initiated fpscr loads always have to undergo bit masking to preserve
9090 ;; the current fpu mode settings for the compiler generated code. Thus such
9091 ;; fpscr loads will always have to go through general registers anyways.
9092 (define_insn "lds_fpscr"
9093 [(set (reg:SI FPSCR_REG)
9094 (match_operand:SI 0 "fpscr_movsrc_operand" "r,>"))
9095 (set (reg:SI FPSCR_STAT_REG)
9096 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_STAT))
9097 (set (reg:SI FPSCR_MODES_REG)
9098 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
9099 "TARGET_FPU_ANY"
9100 "@
9101 lds %0,fpscr
9102 lds.l %0,fpscr"
9103 [(set_attr "type" "gp_fpscr,mem_fpscr")])
9105 ;; A move fpscr -> reg schedules like a move mac -> reg. Thus we use mac_gp
9106 ;; type for it.
9107 (define_insn "sts_fpscr"
9108 [(set (match_operand:SI 0 "fpscr_movdst_operand" "=r,<")
9109 (reg:SI FPSCR_REG))
9110 (use (reg:SI FPSCR_STAT_REG))
9111 (use (reg:SI FPSCR_MODES_REG))]
9112 "TARGET_FPU_ANY"
9113 "@
9114 sts fpscr,%0
9115 sts.l fpscr,%0"
9116 [(set_attr "type" "mac_gp,fstore")])
9118 (define_expand "set_fpscr"
9119 [(parallel [(set (reg:SI FPSCR_REG)
9120 (match_operand:SI 0 "general_operand"))
9121 (set (reg:SI FPSCR_STAT_REG)
9122 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))])]
9123 "TARGET_FPU_ANY"
9124 {
9125 /* We have to mask out the FR, SZ and PR bits. To do that, we need to
9126 get the current FPSCR value first.
9127 (a & ~mask) | (b & mask) = a ^ ((a ^ b) & mask) */
9129 rtx mask = force_reg (SImode, GEN_INT (FPSCR_FR | FPSCR_SZ | FPSCR_PR));
9131 rtx a = force_reg (SImode, operands[0]);
9133 rtx b = gen_reg_rtx (SImode);
9134 emit_insn (gen_sts_fpscr (b));
9136 rtx a_xor_b = gen_reg_rtx (SImode);
9137 emit_insn (gen_xorsi3 (a_xor_b, a, b));
9139 rtx a_xor_b_and_mask = gen_reg_rtx (SImode);
9140 emit_insn (gen_andsi3 (a_xor_b_and_mask, a_xor_b, mask));
9142 rtx r = gen_reg_rtx (SImode);
9143 emit_insn (gen_xorsi3 (r, a_xor_b_and_mask, a));
9144 emit_insn (gen_lds_fpscr (r));
9146 DONE;
9147 })
9149 ;; ??? This uses the fp unit, but has no type indicating that.
9150 ;; If we did that, this would either give a bogus latency or introduce
9151 ;; a bogus FIFO constraint.
9152 ;; Since this insn is currently only used for prologues/epilogues,
9153 ;; it is probably best to claim no function unit, which matches the
9154 ;; current setting.
9155 (define_insn "toggle_sz"
9156 [(set (reg:SI FPSCR_REG)
9157 (xor:SI (reg:SI FPSCR_REG) (const_int FPSCR_SZ)))
9158 (set (reg:SI FPSCR_MODES_REG)
9159 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
9160 "TARGET_FPU_DOUBLE"
9161 "fschg"
9162 [(set_attr "type" "fpscr_toggle") (set_attr "fp_set" "unknown")])
9164 ;; Toggle FPU precision PR mode.
9166 (define_insn "toggle_pr"
9167 [(set (reg:SI FPSCR_REG)
9168 (xor:SI (reg:SI FPSCR_REG) (const_int FPSCR_PR)))
9169 (set (reg:SI FPSCR_MODES_REG)
9170 (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))]
9171 "TARGET_SH4A_FP || TARGET_FPU_SH4_300"
9172 "fpchg"
9173 [(set_attr "type" "fpscr_toggle")])
9175 (define_expand "addsf3"
9176 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9177 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand")
9178 (match_operand:SF 2 "fp_arith_reg_operand")))]
9179 "TARGET_SH2E"
9180 {
9181 emit_insn (gen_addsf3_i (operands[0], operands[1], operands[2]));
9182 DONE;
9183 })
9185 (define_insn "addsf3_i"
9186 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9187 (plus:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
9188 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
9189 (clobber (reg:SI FPSCR_STAT_REG))
9190 (use (reg:SI FPSCR_MODES_REG))]
9191 "TARGET_SH2E"
9192 "fadd %2,%0"
9193 [(set_attr "type" "fp")
9194 (set_attr "fp_mode" "single")])
9196 (define_expand "subsf3"
9197 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
9198 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
9199 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
9200 "TARGET_SH2E"
9201 {
9202 emit_insn (gen_subsf3_i (operands[0], operands[1], operands[2]));
9203 DONE;
9204 })
9206 (define_insn "subsf3_i"
9207 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9208 (minus:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
9209 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
9210 (clobber (reg:SI FPSCR_STAT_REG))
9211 (use (reg:SI FPSCR_MODES_REG))]
9212 "TARGET_SH2E"
9213 "fsub %2,%0"
9214 [(set_attr "type" "fp")
9215 (set_attr "fp_mode" "single")])
9217 (define_expand "mulsf3"
9218 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
9219 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "")
9220 (match_operand:SF 2 "fp_arith_reg_operand" "")))]
9221 "TARGET_SH2E"
9222 {
9223 emit_insn (gen_mulsf3_i (operands[0], operands[1], operands[2]));
9224 DONE;
9225 })
9227 (define_insn "mulsf3_i"
9228 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9229 (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%0")
9230 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
9231 (clobber (reg:SI FPSCR_STAT_REG))
9232 (use (reg:SI FPSCR_MODES_REG))]
9233 "TARGET_SH2E"
9234 "fmul %2,%0"
9235 [(set_attr "type" "fp")
9236 (set_attr "fp_mode" "single")])
9238 ;; FMA (fused multiply-add) patterns
9239 (define_expand "fmasf4"
9240 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9241 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand")
9242 (match_operand:SF 2 "fp_arith_reg_operand")
9243 (match_operand:SF 3 "fp_arith_reg_operand")))]
9244 "TARGET_SH2E"
9245 {
9246 emit_insn (gen_fmasf4_i (operands[0], operands[1], operands[2], operands[3]));
9247 DONE;
9248 })
9250 (define_insn "fmasf4_i"
9251 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9252 (fma:SF (match_operand:SF 1 "fp_arith_reg_operand" "w")
9253 (match_operand:SF 2 "fp_arith_reg_operand" "f")
9254 (match_operand:SF 3 "fp_arith_reg_operand" "0")))
9255 (clobber (reg:SI FPSCR_STAT_REG))
9256 (use (reg:SI FPSCR_MODES_REG))]
9257 "TARGET_SH2E"
9258 "fmac %1,%2,%0"
9259 [(set_attr "type" "fp")
9260 (set_attr "fp_mode" "single")])
9262 ;; For some cases such as 'a * b + a' the FMA pattern is not generated by
9263 ;; previous transformations. If FMA is generally allowed, let the combine
9264 ;; pass utilize it.
9265 (define_insn_and_split "*fmasf4"
9266 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9267 (plus:SF (mult:SF (match_operand:SF 1 "fp_arith_reg_operand" "%w")
9268 (match_operand:SF 2 "fp_arith_reg_operand" "f"))
9269 (match_operand:SF 3 "arith_reg_operand" "0")))
9270 (clobber (reg:SI FPSCR_STAT_REG))
9271 (use (reg:SI FPSCR_MODES_REG))]
9272 "TARGET_SH2E && flag_fp_contract_mode == FP_CONTRACT_FAST"
9273 "fmac %1,%2,%0"
9274 "&& can_create_pseudo_p ()"
9275 [(parallel [(set (match_dup 0)
9276 (fma:SF (match_dup 1) (match_dup 2) (match_dup 3)))
9277 (clobber (reg:SI FPSCR_STAT_REG))
9278 (use (reg:SI FPSCR_MODES_REG))])]
9279 {
9280 /* Change 'b * a + a' into 'a * b + a'.
9281 This is better for register allocation. */
9282 if (REGNO (operands[2]) == REGNO (operands[3]))
9283 std::swap (operands[1], operands[2]);
9284 }
9285 [(set_attr "type" "fp")
9286 (set_attr "fp_mode" "single")])
9288 (define_expand "divsf3"
9289 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9290 (div:SF (match_operand:SF 1 "fp_arith_reg_operand")
9291 (match_operand:SF 2 "fp_arith_reg_operand")))]
9292 "TARGET_SH2E"
9293 {
9294 emit_insn (gen_divsf3_i (operands[0], operands[1], operands[2]));
9295 DONE;
9296 })
9298 (define_insn "divsf3_i"
9299 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9300 (div:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")
9301 (match_operand:SF 2 "fp_arith_reg_operand" "f")))
9302 (clobber (reg:SI FPSCR_STAT_REG))
9303 (use (reg:SI FPSCR_MODES_REG))]
9304 "TARGET_SH2E"
9305 "fdiv %2,%0"
9306 [(set_attr "type" "fdiv")
9307 (set_attr "fp_mode" "single")])
9309 (define_expand "floatsisf2"
9310 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
9311 (float:SF (match_operand:SI 1 "fpul_operand" "")))]
9312 "TARGET_SH2E"
9313 {
9314 emit_insn (gen_floatsisf2_i4 (operands[0], operands[1]));
9315 DONE;
9316 })
9318 (define_insn "floatsisf2_i4"
9319 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9320 (float:SF (match_operand:SI 1 "fpul_operand" "y")))
9321 (clobber (reg:SI FPSCR_STAT_REG))
9322 (use (reg:SI FPSCR_MODES_REG))]
9323 "TARGET_SH2E"
9324 "float %1,%0"
9325 [(set_attr "type" "fp")
9326 (set_attr "fp_mode" "single")])
9328 (define_expand "fix_truncsfsi2"
9329 [(set (match_operand:SI 0 "fpul_operand")
9330 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand")))]
9331 "TARGET_SH2E"
9332 {
9333 emit_insn (gen_fix_truncsfsi2_i4 (operands[0], operands[1]));
9334 DONE;
9335 })
9337 (define_insn "fix_truncsfsi2_i4"
9338 [(set (match_operand:SI 0 "fpul_operand" "=y")
9339 (fix:SI (match_operand:SF 1 "fp_arith_reg_operand" "f")))
9340 (clobber (reg:SI FPSCR_STAT_REG))
9341 (use (reg:SI FPSCR_MODES_REG))]
9342 "TARGET_SH2E"
9343 "ftrc %1,%0"
9344 [(set_attr "type" "ftrc_s")
9345 (set_attr "fp_mode" "single")])
9347 (define_insn "cmpgtsf_t"
9348 [(set (reg:SI T_REG)
9349 (gt:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
9350 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
9351 (clobber (reg:SI FPSCR_STAT_REG))
9352 (use (reg:SI FPSCR_MODES_REG))]
9353 "TARGET_SH2E || TARGET_SH4 || TARGET_SH2A_SINGLE"
9354 "fcmp/gt %1,%0"
9355 [(set_attr "type" "fp_cmp")
9356 (set_attr "fp_mode" "single")])
9358 (define_insn "cmpeqsf_t"
9359 [(set (reg:SI T_REG)
9360 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
9361 (match_operand:SF 1 "fp_arith_reg_operand" "f")))
9362 (clobber (reg:SI FPSCR_STAT_REG))
9363 (use (reg:SI FPSCR_MODES_REG))]
9364 "TARGET_SH2E || TARGET_SH4 || TARGET_SH2A_SINGLE"
9365 "fcmp/eq %1,%0"
9366 [(set_attr "type" "fp_cmp")
9367 (set_attr "fp_mode" "single")])
9369 (define_insn "ieee_ccmpeqsf_t"
9370 [(set (reg:SI T_REG)
9371 (ior:SI (reg:SI T_REG)
9372 (eq:SI (match_operand:SF 0 "fp_arith_reg_operand" "f")
9373 (match_operand:SF 1 "fp_arith_reg_operand" "f"))))
9374 (clobber (reg:SI FPSCR_STAT_REG))
9375 (use (reg:SI FPSCR_MODES_REG))]
9376 "TARGET_IEEE && TARGET_SH2E"
9377 {
9378 return output_ieee_ccmpeq (insn, operands);
9379 }
9380 [(set_attr "length" "4")
9381 (set_attr "fp_mode" "single")])
9383 (define_expand "cbranchsf4"
9384 [(set (pc)
9385 (if_then_else (match_operator 0 "ordered_comparison_operator"
9386 [(match_operand:SF 1 "arith_operand" "")
9387 (match_operand:SF 2 "arith_operand" "")])
9388 (match_operand 3 "" "")
9389 (pc)))]
9390 "TARGET_SH2E"
9391 {
9392 sh_emit_compare_and_branch (operands, SFmode);
9393 DONE;
9394 })
9396 (define_expand "negsf2"
9397 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9398 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand")))]
9399 "TARGET_FPU_ANY"
9400 {
9401 if (TARGET_FPU_SH4_300)
9402 emit_insn (gen_negsf2_fpscr (operands[0], operands[1]));
9403 else
9404 emit_insn (gen_negsf2_no_fpscr (operands[0], operands[1]));
9405 DONE;
9406 })
9408 (define_insn "negsf2_no_fpscr"
9409 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9410 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))]
9411 "TARGET_FPU_ANY && !TARGET_FPU_SH4_300"
9412 "fneg %0"
9413 [(set_attr "type" "fmove")])
9415 (define_insn "negsf2_fpscr"
9416 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9417 (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
9418 (use (reg:SI FPSCR_MODES_REG))]
9419 "TARGET_FPU_SH4_300"
9420 "fneg %0"
9421 [(set_attr "type" "fmove")
9422 (set_attr "fp_mode" "single")])
9424 (define_expand "sqrtsf2"
9425 [(set (match_operand:SF 0 "fp_arith_reg_operand" "")
9426 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))]
9427 "TARGET_SH3E"
9428 {
9429 emit_insn (gen_sqrtsf2_i (operands[0], operands[1]));
9430 DONE;
9431 })
9433 (define_insn "sqrtsf2_i"
9434 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9435 (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
9436 (clobber (reg:SI FPSCR_STAT_REG))
9437 (use (reg:SI FPSCR_MODES_REG))]
9438 "TARGET_SH3E"
9439 "fsqrt %0"
9440 [(set_attr "type" "fdiv")
9441 (set_attr "fp_mode" "single")])
9443 (define_insn "rsqrtsf2"
9444 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9445 (unspec:SF [(match_operand:SF 1 "fp_arith_reg_operand" "0")]
9446 UNSPEC_FSRRA))
9447 (clobber (reg:SI FPSCR_STAT_REG))
9448 (use (reg:SI FPSCR_MODES_REG))]
9449 "TARGET_FPU_ANY && TARGET_FSRRA"
9450 "fsrra %0"
9451 [(set_attr "type" "fsrra")
9452 (set_attr "fp_mode" "single")])
9454 ;; When the sincos pattern is defined, the builtin functions sin and cos
9455 ;; will be expanded to the sincos pattern and one of the output values will
9456 ;; remain unused.
9457 (define_expand "sincossf3"
9458 [(set (match_operand:SF 0 "nonimmediate_operand")
9459 (unspec:SF [(match_operand:SF 2 "fp_arith_reg_operand")] UNSPEC_FCOSA))
9460 (set (match_operand:SF 1 "nonimmediate_operand")
9461 (unspec:SF [(match_dup 2)] UNSPEC_FSINA))]
9462 "TARGET_FPU_ANY && TARGET_FSCA"
9463 {
9464 rtx scaled = gen_reg_rtx (SFmode);
9465 rtx truncated = gen_reg_rtx (SImode);
9466 rtx fsca = gen_reg_rtx (V2SFmode);
9467 rtx scale_reg = force_reg (SFmode, sh_fsca_sf2int ());
9469 emit_insn (gen_mulsf3 (scaled, operands[2], scale_reg));
9470 emit_insn (gen_fix_truncsfsi2 (truncated, scaled));
9471 emit_insn (gen_fsca (fsca, truncated, sh_fsca_int2sf ()));
9473 emit_move_insn (operands[0], gen_rtx_SUBREG (SFmode, fsca, 4));
9474 emit_move_insn (operands[1], gen_rtx_SUBREG (SFmode, fsca, 0));
9475 DONE;
9476 })
9478 (define_insn_and_split "fsca"
9479 [(set (match_operand:V2SF 0 "fp_arith_reg_operand" "=f")
9480 (vec_concat:V2SF
9481 (unspec:SF [(mult:SF
9482 (float:SF (match_operand:SI 1 "fpul_fsca_operand" "y"))
9483 (match_operand:SF 2 "fsca_scale_factor" "i"))
9484 ] UNSPEC_FSINA)
9485 (unspec:SF [(mult:SF (float:SF (match_dup 1)) (match_dup 2))
9486 ] UNSPEC_FCOSA)))
9487 (clobber (reg:SI FPSCR_STAT_REG))
9488 (use (reg:SI FPSCR_MODES_REG))]
9489 "TARGET_FPU_ANY && TARGET_FSCA"
9490 "fsca fpul,%d0"
9491 "&& !fpul_operand (operands[1], SImode)"
9492 [(const_int 0)]
9493 {
9494 /* If operands[1] is something like (fix:SF (float:SF (reg:SI))) reduce it
9495 to a simple reg, otherwise reload will have trouble reloading the
9496 pseudo into fpul. */
9497 rtx x = XEXP (operands[1], 0);
9498 while (x != NULL_RTX && !fpul_operand (x, SImode))
9499 {
9500 gcc_assert (GET_CODE (x) == FIX || GET_CODE (x) == FLOAT);
9501 x = XEXP (x, 0);
9502 }
9503 gcc_assert (x != NULL_RTX && fpul_operand (x, SImode));
9504 emit_insn (gen_fsca (operands[0], x, operands[2]));
9505 DONE;
9506 }
9507 [(set_attr "type" "fsca")
9508 (set_attr "fp_mode" "single")])
9510 (define_expand "abssf2"
9511 [(set (match_operand:SF 0 "fp_arith_reg_operand")
9512 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand")))]
9513 "TARGET_FPU_ANY"
9514 {
9515 if (TARGET_FPU_SH4_300)
9516 emit_insn (gen_abssf2_fpscr (operands[0], operands[1]));
9517 else
9518 emit_insn (gen_abssf2_no_fpscr (operands[0], operands[1]));
9519 DONE;
9520 })
9522 (define_insn "abssf2_no_fpscr"
9523 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9524 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))]
9525 "TARGET_FPU_ANY && !TARGET_FPU_SH4_300"
9526 "fabs %0"
9527 [(set_attr "type" "fmove")])
9529 (define_insn "abssf2_fpscr"
9530 [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f")
9531 (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))
9532 (use (reg:SI FPSCR_MODES_REG))]
9533 "TARGET_FPU_SH4_300"
9534 "fabs %0"
9535 [(set_attr "type" "fmove")
9536 (set_attr "fp_mode" "single")])
9538 (define_expand "adddf3"
9539 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9540 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
9541 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
9542 "TARGET_FPU_DOUBLE"
9543 {
9544 emit_insn (gen_adddf3_i (operands[0], operands[1], operands[2]));
9545 DONE;
9546 })
9548 (define_insn "adddf3_i"
9549 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9550 (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
9551 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
9552 (clobber (reg:SI FPSCR_STAT_REG))
9553 (use (reg:SI FPSCR_MODES_REG))]
9554 "TARGET_FPU_DOUBLE"
9555 "fadd %2,%0"
9556 [(set_attr "type" "dfp_arith")
9557 (set_attr "fp_mode" "double")])
9559 (define_expand "subdf3"
9560 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9561 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
9562 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
9563 "TARGET_FPU_DOUBLE"
9564 {
9565 emit_insn (gen_subdf3_i (operands[0], operands[1], operands[2]));
9566 DONE;
9567 })
9569 (define_insn "subdf3_i"
9570 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9571 (minus:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
9572 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
9573 (clobber (reg:SI FPSCR_STAT_REG))
9574 (use (reg:SI FPSCR_MODES_REG))]
9575 "TARGET_FPU_DOUBLE"
9576 "fsub %2,%0"
9577 [(set_attr "type" "dfp_arith")
9578 (set_attr "fp_mode" "double")])
9580 (define_expand "muldf3"
9581 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9582 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
9583 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
9584 "TARGET_FPU_DOUBLE"
9585 {
9586 emit_insn (gen_muldf3_i (operands[0], operands[1], operands[2]));
9587 DONE;
9588 })
9590 (define_insn "muldf3_i"
9591 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9592 (mult:DF (match_operand:DF 1 "fp_arith_reg_operand" "%0")
9593 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
9594 (clobber (reg:SI FPSCR_STAT_REG))
9595 (use (reg:SI FPSCR_MODES_REG))]
9596 "TARGET_FPU_DOUBLE"
9597 "fmul %2,%0"
9598 [(set_attr "type" "dfp_mul")
9599 (set_attr "fp_mode" "double")])
9601 (define_expand "divdf3"
9602 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9603 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "")
9604 (match_operand:DF 2 "fp_arith_reg_operand" "")))]
9605 "TARGET_FPU_DOUBLE"
9606 {
9607 emit_insn (gen_divdf3_i (operands[0], operands[1], operands[2]));
9608 DONE;
9609 })
9611 (define_insn "divdf3_i"
9612 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9613 (div:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")
9614 (match_operand:DF 2 "fp_arith_reg_operand" "f")))
9615 (clobber (reg:SI FPSCR_STAT_REG))
9616 (use (reg:SI FPSCR_MODES_REG))]
9617 "TARGET_FPU_DOUBLE"
9618 "fdiv %2,%0"
9619 [(set_attr "type" "dfdiv")
9620 (set_attr "fp_mode" "double")])
9622 (define_expand "floatsidf2"
9623 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9624 (float:DF (match_operand:SI 1 "fpul_operand" "")))]
9625 "TARGET_FPU_DOUBLE"
9626 {
9627 emit_insn (gen_floatsidf2_i (operands[0], operands[1]));
9628 DONE;
9629 })
9631 (define_insn "floatsidf2_i"
9632 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9633 (float:DF (match_operand:SI 1 "fpul_operand" "y")))
9634 (clobber (reg:SI FPSCR_STAT_REG))
9635 (use (reg:SI FPSCR_MODES_REG))]
9636 "TARGET_FPU_DOUBLE"
9637 "float %1,%0"
9638 [(set_attr "type" "dfp_conv")
9639 (set_attr "fp_mode" "double")])
9641 (define_expand "fix_truncdfsi2"
9642 [(set (match_operand:SI 0 "fpul_operand" "")
9643 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "")))]
9644 "TARGET_FPU_DOUBLE"
9645 {
9646 emit_insn (gen_fix_truncdfsi2_i (operands[0], operands[1]));
9647 DONE;
9648 })
9650 (define_insn "fix_truncdfsi2_i"
9651 [(set (match_operand:SI 0 "fpul_operand" "=y")
9652 (fix:SI (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9653 (clobber (reg:SI FPSCR_STAT_REG))
9654 (use (reg:SI FPSCR_MODES_REG))]
9655 "TARGET_FPU_DOUBLE"
9656 "ftrc %1,%0"
9657 [(set_attr "type" "dfp_conv")
9658 (set_attr "dfp_comp" "no")
9659 (set_attr "fp_mode" "double")])
9661 (define_insn "cmpgtdf_t"
9662 [(set (reg:SI T_REG)
9663 (gt:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
9664 (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9665 (clobber (reg:SI FPSCR_STAT_REG))
9666 (use (reg:SI FPSCR_MODES_REG))]
9667 "TARGET_FPU_DOUBLE"
9668 "fcmp/gt %1,%0"
9669 [(set_attr "type" "dfp_cmp")
9670 (set_attr "fp_mode" "double")])
9672 (define_insn "cmpeqdf_t"
9673 [(set (reg:SI T_REG)
9674 (eq:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
9675 (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9676 (clobber (reg:SI FPSCR_STAT_REG))
9677 (use (reg:SI FPSCR_MODES_REG))]
9678 "TARGET_FPU_DOUBLE"
9679 "fcmp/eq %1,%0"
9680 [(set_attr "type" "dfp_cmp")
9681 (set_attr "fp_mode" "double")])
9683 (define_insn "*ieee_ccmpeqdf_t"
9684 [(set (reg:SI T_REG)
9685 (ior:SI (reg:SI T_REG)
9686 (eq:SI (match_operand:DF 0 "fp_arith_reg_operand" "f")
9687 (match_operand:DF 1 "fp_arith_reg_operand" "f"))))
9688 (clobber (reg:SI FPSCR_STAT_REG))
9689 (use (reg:SI FPSCR_MODES_REG))]
9690 "TARGET_IEEE && TARGET_FPU_DOUBLE"
9691 {
9692 return output_ieee_ccmpeq (insn, operands);
9693 }
9694 [(set_attr "length" "4")
9695 (set_attr "fp_mode" "double")])
9697 (define_expand "cbranchdf4"
9698 [(set (pc)
9699 (if_then_else (match_operator 0 "ordered_comparison_operator"
9700 [(match_operand:DF 1 "arith_operand" "")
9701 (match_operand:DF 2 "arith_operand" "")])
9702 (match_operand 3 "" "")
9703 (pc)))]
9704 "TARGET_FPU_DOUBLE"
9705 {
9706 sh_emit_compare_and_branch (operands, DFmode);
9707 DONE;
9708 })
9710 (define_expand "negdf2"
9711 [(set (match_operand:DF 0 "fp_arith_reg_operand")
9712 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
9713 "TARGET_FPU_DOUBLE"
9714 {
9715 if (TARGET_FPU_SH4_300)
9716 emit_insn (gen_negdf2_fpscr (operands[0], operands[1]));
9717 else
9718 emit_insn (gen_negdf2_no_fpscr (operands[0], operands[1]));
9719 DONE;
9720 })
9722 (define_insn "negdf2_fpscr"
9723 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9724 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
9725 (use (reg:SI FPSCR_MODES_REG))]
9726 "TARGET_FPU_SH4_300"
9727 "fneg %0"
9728 [(set_attr "type" "fmove")
9729 (set_attr "fp_mode" "double")])
9731 (define_insn "negdf2_no_fpscr"
9732 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9733 (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))]
9734 "TARGET_FPU_DOUBLE && !TARGET_FPU_SH4_300"
9735 "fneg %0"
9736 [(set_attr "type" "fmove")])
9738 (define_expand "sqrtdf2"
9739 [(set (match_operand:DF 0 "fp_arith_reg_operand")
9740 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
9741 "TARGET_FPU_DOUBLE"
9742 {
9743 emit_insn (gen_sqrtdf2_i (operands[0], operands[1]));
9744 DONE;
9745 })
9747 (define_insn "sqrtdf2_i"
9748 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9749 (sqrt:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
9750 (clobber (reg:SI FPSCR_STAT_REG))
9751 (use (reg:SI FPSCR_MODES_REG))]
9752 "TARGET_FPU_DOUBLE"
9753 "fsqrt %0"
9754 [(set_attr "type" "dfdiv")
9755 (set_attr "fp_mode" "double")])
9757 (define_expand "absdf2"
9758 [(set (match_operand:DF 0 "fp_arith_reg_operand")
9759 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand")))]
9760 "TARGET_FPU_DOUBLE"
9761 {
9762 if (TARGET_FPU_SH4_300)
9763 emit_insn (gen_absdf2_fpscr (operands[0], operands[1]));
9764 else
9765 emit_insn (gen_absdf2_no_fpscr (operands[0], operands[1]));
9766 DONE;
9767 })
9769 (define_insn "absdf2_no_fpscr"
9770 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9771 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))]
9772 "TARGET_FPU_DOUBLE && !TARGET_FPU_SH4_300"
9773 "fabs %0"
9774 [(set_attr "type" "fmove")])
9776 (define_insn "absdf2_fpscr"
9777 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9778 (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))
9779 (use (reg:SI FPSCR_MODES_REG))]
9780 "TARGET_FPU_SH4_300"
9781 "fabs %0"
9782 [(set_attr "type" "fmove")
9783 (set_attr "fp_mode" "double")])
9785 (define_expand "extendsfdf2"
9786 [(set (match_operand:DF 0 "fp_arith_reg_operand" "")
9787 (float_extend:DF (match_operand:SF 1 "fpul_operand" "")))]
9788 "TARGET_FPU_DOUBLE"
9789 {
9790 emit_insn (gen_extendsfdf2_i4 (operands[0], operands[1]));
9791 DONE;
9792 })
9794 (define_insn "extendsfdf2_i4"
9795 [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f")
9796 (float_extend:DF (match_operand:SF 1 "fpul_operand" "y")))
9797 (clobber (reg:SI FPSCR_STAT_REG))
9798 (use (reg:SI FPSCR_MODES_REG))]
9799 "TARGET_FPU_DOUBLE"
9800 "fcnvsd %1,%0"
9801 [(set_attr "type" "fp")
9802 (set_attr "fp_mode" "double")])
9804 (define_expand "truncdfsf2"
9805 [(set (match_operand:SF 0 "fpul_operand" "")
9806 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "")))]
9807 "TARGET_FPU_DOUBLE"
9808 {
9809 emit_insn (gen_truncdfsf2_i4 (operands[0], operands[1]));
9810 DONE;
9811 })
9813 (define_insn "truncdfsf2_i4"
9814 [(set (match_operand:SF 0 "fpul_operand" "=y")
9815 (float_truncate:SF (match_operand:DF 1 "fp_arith_reg_operand" "f")))
9816 (clobber (reg:SI FPSCR_STAT_REG))
9817 (use (reg:SI FPSCR_MODES_REG))]
9818 "TARGET_FPU_DOUBLE"
9819 "fcnvds %1,%0"
9820 [(set_attr "type" "fp")
9821 (set_attr "fp_mode" "double")])
9822 \f
9823 ;; -------------------------------------------------------------------------
9824 ;; Bit field extract patterns.
9825 ;; -------------------------------------------------------------------------
9827 ;; These give better code for packed bitfields, because they allow
9828 ;; auto-increment addresses to be generated.
9830 (define_expand "insv"
9831 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
9832 (match_operand:SI 1 "immediate_operand" "")
9833 (match_operand:SI 2 "immediate_operand" ""))
9834 (match_operand:SI 3 "general_operand" ""))]
9835 "TARGET_SH1 && TARGET_BIG_ENDIAN"
9836 {
9837 rtx addr_target, orig_address, shift_reg, qi_val;
9838 HOST_WIDE_INT bitsize, size, v = 0;
9839 rtx x = operands[3];
9841 if (TARGET_SH2A && TARGET_BITOPS
9842 && (satisfies_constraint_Sbw (operands[0])
9843 || satisfies_constraint_Sbv (operands[0]))
9844 && satisfies_constraint_M (operands[1])
9845 && satisfies_constraint_K03 (operands[2]))
9846 {
9847 if (satisfies_constraint_N (operands[3]))
9848 {
9849 emit_insn (gen_bclr_m2a (operands[0], operands[2]));
9850 DONE;
9851 }
9852 else if (satisfies_constraint_M (operands[3]))
9853 {
9854 emit_insn (gen_bset_m2a (operands[0], operands[2]));
9855 DONE;
9856 }
9857 else if ((REG_P (operands[3]) && REGNO (operands[3]) == T_REG)
9858 && satisfies_constraint_M (operands[1]))
9859 {
9860 emit_insn (gen_bst_m2a (operands[0], operands[2]));
9861 DONE;
9862 }
9863 else if (REG_P (operands[3])
9864 && satisfies_constraint_M (operands[1]))
9865 {
9866 emit_insn (gen_bldsi_reg (operands[3], const0_rtx));
9867 emit_insn (gen_bst_m2a (operands[0], operands[2]));
9868 DONE;
9869 }
9870 }
9871 /* ??? expmed doesn't care for non-register predicates. */
9872 if (! memory_operand (operands[0], VOIDmode)
9873 || ! immediate_operand (operands[1], VOIDmode)
9874 || ! immediate_operand (operands[2], VOIDmode)
9875 || ! general_operand (x, VOIDmode))
9876 FAIL;
9877 /* If this isn't a 16 / 24 / 32 bit field, or if
9878 it doesn't start on a byte boundary, then fail. */
9879 bitsize = INTVAL (operands[1]);
9880 if (bitsize < 16 || bitsize > 32 || bitsize % 8 != 0
9881 || (INTVAL (operands[2]) % 8) != 0)
9882 FAIL;
9884 size = bitsize / 8;
9885 orig_address = XEXP (operands[0], 0);
9886 shift_reg = gen_reg_rtx (SImode);
9887 if (CONST_INT_P (x))
9888 {
9889 v = INTVAL (x);
9890 qi_val = force_reg (QImode, GEN_INT (trunc_int_for_mode (v, QImode)));
9891 }
9892 else
9893 {
9894 emit_insn (gen_movsi (shift_reg, operands[3]));
9895 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
9896 }
9897 addr_target = copy_addr_to_reg (plus_constant (Pmode,
9898 orig_address, size - 1));
9900 operands[0] = replace_equiv_address (operands[0], addr_target);
9901 emit_insn (gen_movqi (operands[0], qi_val));
9903 while (size -= 1)
9904 {
9905 if (CONST_INT_P (x))
9906 qi_val
9907 = force_reg (QImode, GEN_INT (trunc_int_for_mode (v >>= 8, QImode)));
9908 else
9909 {
9910 emit_insn (gen_lshrsi3_k (shift_reg, shift_reg, GEN_INT (8)));
9911 qi_val = gen_rtx_SUBREG (QImode, shift_reg, 3);
9912 }
9913 emit_insn (gen_addsi3 (addr_target, addr_target, constm1_rtx));
9914 emit_insn (gen_movqi (operands[0], qi_val));
9915 }
9917 DONE;
9918 })
9920 (define_insn "movua"
9921 [(set (match_operand:SI 0 "register_operand" "=z")
9922 (unspec:SI [(match_operand:BLK 1 "unaligned_load_operand" "Sua>")]
9923 UNSPEC_MOVUA))]
9924 "TARGET_SH4A"
9925 "movua.l %1,%0"
9926 [(set_attr "type" "movua")])
9928 ;; We shouldn't need this, but cse replaces increments with references
9929 ;; to other regs before flow has a chance to create post_inc
9930 ;; addressing modes, and only postreload's cse_move2add brings the
9931 ;; increments back to a usable form.
9932 (define_peephole2
9933 [(set (match_operand:SI 0 "register_operand" "")
9934 (sign_extract:SI (mem:SI (match_operand:SI 1 "register_operand" ""))
9935 (const_int 32) (const_int 0)))
9936 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
9937 "TARGET_SH4A && REGNO (operands[0]) != REGNO (operands[1])"
9938 [(set (match_operand:SI 0 "register_operand" "")
9939 (sign_extract:SI (mem:SI (post_inc:SI
9940 (match_operand:SI 1 "register_operand" "")))
9941 (const_int 32) (const_int 0)))]
9942 "")
9944 (define_expand "extv"
9945 [(set (match_operand:SI 0 "register_operand" "")
9946 (sign_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
9947 (match_operand 2 "const_int_operand" "")
9948 (match_operand 3 "const_int_operand" "")))]
9949 "TARGET_SH4A || TARGET_SH2A"
9950 {
9951 if (TARGET_SH2A && TARGET_BITOPS
9952 && (satisfies_constraint_Sbw (operands[1])
9953 || satisfies_constraint_Sbv (operands[1]))
9954 && satisfies_constraint_M (operands[2])
9955 && satisfies_constraint_K03 (operands[3]))
9956 {
9957 emit_insn (gen_bldsign_m2a (operands[1], operands[3]));
9958 if (REGNO (operands[0]) != T_REG)
9959 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
9960 DONE;
9961 }
9962 if (TARGET_SH4A
9963 && INTVAL (operands[2]) == 32
9964 && INTVAL (operands[3]) == 0
9965 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
9966 {
9967 rtx src = adjust_address (operands[1], BLKmode, 0);
9968 set_mem_size (src, 4);
9969 emit_insn (gen_movua (operands[0], src));
9970 DONE;
9971 }
9973 FAIL;
9974 })
9976 (define_expand "extzv"
9977 [(set (match_operand:SI 0 "register_operand" "")
9978 (zero_extract:SI (match_operand:QI 1 "unaligned_load_operand" "")
9979 (match_operand 2 "const_int_operand" "")
9980 (match_operand 3 "const_int_operand" "")))]
9981 "TARGET_SH4A || TARGET_SH2A"
9982 {
9983 if (TARGET_SH2A && TARGET_BITOPS
9984 && (satisfies_constraint_Sbw (operands[1])
9985 || satisfies_constraint_Sbv (operands[1]))
9986 && satisfies_constraint_M (operands[2])
9987 && satisfies_constraint_K03 (operands[3]))
9988 {
9989 emit_insn (gen_bld_m2a (operands[1], operands[3]));
9990 if (REGNO (operands[0]) != T_REG)
9991 emit_insn (gen_movsi (operands[0], gen_rtx_REG (SImode, T_REG)));
9992 DONE;
9993 }
9994 if (TARGET_SH4A
9995 && INTVAL (operands[2]) == 32
9996 && INTVAL (operands[3]) == 0
9997 && MEM_P (operands[1]) && MEM_ALIGN (operands[1]) < 32)
9998 {
9999 rtx src = adjust_address (operands[1], BLKmode, 0);
10000 set_mem_size (src, 4);
10001 emit_insn (gen_movua (operands[0], src));
10002 DONE;
10003 }
10005 FAIL;
10006 })
10008 ;; -------------------------------------------------------------------------
10009 ;; Extract negated single bit and zero extend it.
10010 ;; Generally we don't care about the exact xor const_int value, as long
10011 ;; as it contains the extracted bit. For simplicity, the pattern variations
10012 ;; that convert everything into the primary '*neg_zero_extract_0' pattern use
10013 ;; a xor const_int -1 value.
10015 (define_insn_and_split "*neg_zero_extract_0"
10016 [(set (reg:SI T_REG)
10017 (zero_extract:SI (xor:QIHISI (match_operand:QIHISI 0 "arith_reg_operand")
10018 (match_operand 1 "const_int_operand"))
10019 (const_int 1)
10020 (match_operand 2 "const_int_operand")))]
10021 "TARGET_SH1 && can_create_pseudo_p ()
10022 && INTVAL (operands[1]) & (1LL << INTVAL (operands[2]))"
10023 "#"
10024 "&& 1"
10025 [(set (reg:SI T_REG) (eq:SI (and:SI (match_dup 0) (match_dup 2))
10026 (const_int 0)))]
10027 {
10028 if (INTVAL (operands[2]) == 31 && <MODE>mode == SImode)
10029 {
10030 /* Use cmp/pz to extract bit 31 into the T bit. */
10031 emit_insn (gen_cmpgesi_t (operands[0], const0_rtx));
10032 DONE;
10033 }
10035 operands[2] = GEN_INT ((1 << INTVAL (operands[2])));
10036 if (GET_MODE (operands[0]) != SImode)
10037 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
10038 })
10040 (define_insn_and_split "*neg_zero_extract_1"
10041 [(set (reg:SI T_REG)
10042 (and:SI (not:SI (match_operand:SI 0 "arith_reg_operand"))
10043 (const_int 1)))]
10044 "TARGET_SH1"
10045 "#"
10046 "&& 1"
10047 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
10048 (const_int 1) (const_int 0)))])
10050 ;; x & (1 << n) == 0: 0x00000000 + 1 = 1
10051 ;; x & (1 << n) != 0: 0xFFFFFFFF + 1 = 0
10052 (define_insn_and_split "*neg_zero_extract_2"
10053 [(set (reg:SI T_REG)
10054 (plus:SI (sign_extract:SI (match_operand:QIHISI 0 "arith_reg_operand")
10055 (const_int 1)
10056 (match_operand 1 "const_int_operand"))
10057 (const_int 1)))]
10058 "TARGET_SH1 && can_create_pseudo_p ()"
10059 "#"
10060 "&& 1"
10061 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
10062 (const_int 1) (match_dup 1)))])
10064 ;; (signed)x >> 31 + 1 = (x >= 0) ^ 1
10065 (define_insn_and_split "*neg_zero_extract_3"
10066 [(set (reg:SI T_REG)
10067 (plus:SI (ashiftrt:SI (match_operand:SI 0 "arith_reg_operand")
10068 (const_int 31))
10069 (const_int 1)))]
10070 "TARGET_SH1 && can_create_pseudo_p ()"
10071 "#"
10072 "&& 1"
10073 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
10074 (const_int 1) (const_int 31)))])
10076 ;; This is required for some bit patterns of DImode subregs.
10077 ;; It looks like combine gets confused by the DImode right shift and fails
10078 ;; to simplify things.
10079 (define_insn_and_split "*neg_zero_extract_4"
10080 [(set (reg:SI T_REG)
10081 (and:SI (and:SI
10082 (lshiftrt:SI (xor:SI (match_operand:SI 0 "arith_reg_operand")
10083 (match_operand 1 "const_int_operand"))
10084 (match_operand 2 "const_int_operand"))
10085 (not:SI (ashift:SI (match_operand:SI 3 "arith_reg_operand")
10086 (match_operand 4 "const_int_operand"))))
10087 (const_int 1)))]
10088 "TARGET_SH1 && can_create_pseudo_p ()
10089 && INTVAL (operands[4]) > 0
10090 && INTVAL (operands[1]) & (1LL << INTVAL (operands[2]))"
10091 "#"
10092 "&& 1"
10093 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (match_dup 1))
10094 (const_int 1) (match_dup 2)))])
10096 (define_insn_and_split "*neg_zero_extract_5"
10097 [(set (reg:SI T_REG)
10098 (and:SI (not:SI (subreg:SI
10099 (lshiftrt:DI (match_operand:DI 0 "arith_reg_operand")
10100 (match_operand 1 "const_int_operand"))
10101 0))
10102 (const_int 1)))]
10103 "TARGET_SH1 && TARGET_LITTLE_ENDIAN && can_create_pseudo_p ()
10104 && INTVAL (operands[1]) < 32"
10105 "#"
10106 "&& 1"
10107 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
10108 (const_int 1) (match_dup 1)))]
10109 {
10110 operands[0] = gen_lowpart (SImode, operands[0]);
10111 })
10113 (define_insn_and_split "*neg_zero_extract_6"
10114 [(set (reg:SI T_REG)
10115 (and:SI (not:SI (subreg:SI
10116 (lshiftrt:DI (match_operand:DI 0 "arith_reg_operand")
10117 (match_operand 1 "const_int_operand"))
10118 4))
10119 (const_int 1)))]
10120 "TARGET_SH1 && TARGET_BIG_ENDIAN && can_create_pseudo_p ()
10121 && INTVAL (operands[1]) < 32"
10122 "#"
10123 "&& 1"
10124 [(set (reg:SI T_REG) (zero_extract:SI (xor:SI (match_dup 0) (const_int -1))
10125 (const_int 1) (match_dup 1)))]
10126 {
10127 operands[0] = gen_lowpart (SImode, operands[0]);
10128 })
10130 ;; -------------------------------------------------------------------------
10131 ;; Extract single bit and zero extend it.
10132 ;; All patterns store the result bit in the T bit, although that is not
10133 ;; always possible to do with a single insn and a nott must be appended.
10134 ;; The trailing nott will be optimized away in most cases. E.g. if the
10135 ;; extracted bit is fed into a branch condition, the condition can be
10136 ;; inverted and the nott will be eliminated.
10137 ;; FIXME: In cases where the trailing nott can't be eliminated, try to
10138 ;; convert it into a (not, tst) sequence, which could be better on non-SH2A.
10140 ;; On SH2A the 'bld<mode>_reg' insn will be used if the bit position fits.
10141 (define_insn_and_split "*zero_extract_0"
10142 [(set (reg:SI T_REG)
10143 (zero_extract:SI (match_operand:QIHISI 0 "arith_reg_operand")
10144 (const_int 1)
10145 (match_operand 1 "const_int_operand")))]
10146 "TARGET_SH1 && can_create_pseudo_p ()
10147 && !(TARGET_SH2A && satisfies_constraint_K03 (operands[1]))"
10148 "#"
10149 "&& 1"
10150 [(set (reg:SI T_REG) (eq:SI (and:SI (match_dup 0) (match_dup 1))
10151 (const_int 0)))
10152 (set (reg:SI T_REG) (xor:SI (reg:SI T_REG) (const_int 1)))]
10153 {
10154 if (INTVAL (operands[1]) == 31 && <MODE>mode == SImode)
10155 {
10156 emit_insn (gen_shll (gen_reg_rtx (SImode), operands[0]));
10157 DONE;
10158 }
10160 operands[1] = GEN_INT (1 << INTVAL (operands[1]));
10161 if (GET_MODE (operands[0]) != SImode)
10162 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
10163 })
10165 ;; This is required for some bit patterns of DImode subregs.
10166 ;; It looks like combine gets confused by the DImode right shift and fails
10167 ;; to simplify things.
10168 (define_insn_and_split "*zero_extract_1"
10169 [(set (reg:SI T_REG)
10170 (subreg:SI (zero_extract:DI (match_operand:SI 0 "arith_reg_operand")
10171 (const_int 1)
10172 (match_operand 1 "const_int_operand"))
10173 0))]
10174 "TARGET_SH1 && TARGET_LITTLE_ENDIAN && can_create_pseudo_p ()
10175 && INTVAL (operands[1]) < 32"
10176 "#"
10177 "&& 1"
10178 [(set (reg:SI T_REG)
10179 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)))])
10181 (define_insn_and_split "*zero_extract_2"
10182 [(set (reg:SI T_REG)
10183 (subreg:SI (zero_extract:DI (match_operand:SI 0 "arith_reg_operand")
10184 (const_int 1)
10185 (match_operand 1 "const_int_operand"))
10186 4))]
10187 "TARGET_SH1 && TARGET_BIG_ENDIAN && can_create_pseudo_p ()
10188 && INTVAL (operands[1]) < 32"
10189 "#"
10190 "&& 1"
10191 [(set (reg:SI T_REG)
10192 (zero_extract:SI (match_dup 0) (const_int 1) (match_dup 1)))])
10194 (define_insn_and_split "*zero_extract_3"
10195 [(set (match_operand:SI 0 "arith_reg_dest")
10196 (and:SI (lshiftrt:SI (match_operand:SI 1 "arith_reg_operand")
10197 (match_operand 2 "const_int_operand"))
10198 (match_operand 3 "const_int_operand")))
10199 (clobber (reg:SI T_REG))]
10200 "TARGET_SH1 && can_create_pseudo_p ()
10201 && exact_log2 (INTVAL (operands[3])) >= 0"
10202 "#"
10203 "&& 1"
10204 [(const_int 0)]
10205 {
10206 int rshift = INTVAL (operands[2]);
10207 int lshift = exact_log2 (INTVAL (operands[3]));
10209 rtx tmp = gen_reg_rtx (SImode);
10210 emit_insn (gen_rtx_PARALLEL (VOIDmode,
10211 gen_rtvec (2,
10212 gen_rtx_SET (tmp,
10213 gen_rtx_ZERO_EXTRACT (SImode, operands[1], const1_rtx,
10214 GEN_INT (rshift + lshift))),
10215 gen_rtx_CLOBBER (VOIDmode, get_t_reg_rtx ()))));
10216 emit_insn (gen_ashlsi3 (operands[0], tmp, GEN_INT (lshift)));
10217 })
10219 ;; -------------------------------------------------------------------------
10220 ;; SH2A instructions for bitwise operations.
10221 ;; FIXME: Convert multiple instruction insns to insn_and_split.
10222 ;; FIXME: Use iterators to fold at least and,xor,or insn variations.
10224 ;; Clear a bit in a memory location.
10225 (define_insn "bclr_m2a"
10226 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
10227 (and:QI
10228 (not:QI (ashift:QI (const_int 1)
10229 (match_operand:QI 1 "const_int_operand" "K03,K03")))
10230 (match_dup 0)))]
10231 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10232 "@
10233 bclr.b %1,%0
10234 bclr.b %1,@(0,%t0)"
10235 [(set_attr "length" "4,4")])
10237 (define_insn "bclrmem_m2a"
10238 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
10239 (and:QI (match_dup 0)
10240 (match_operand:QI 1 "const_int_operand" "Psz,Psz")))]
10241 "TARGET_SH2A && satisfies_constraint_Psz (operands[1]) && TARGET_BITOPS"
10242 "@
10243 bclr.b %W1,%0
10244 bclr.b %W1,@(0,%t0)"
10245 [(set_attr "length" "4,4")])
10247 ;; Set a bit in a memory location.
10248 (define_insn "bset_m2a"
10249 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
10250 (ior:QI
10251 (ashift:QI (const_int 1)
10252 (match_operand:QI 1 "const_int_operand" "K03,K03"))
10253 (match_dup 0)))]
10254 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10255 "@
10256 bset.b %1,%0
10257 bset.b %1,@(0,%t0)"
10258 [(set_attr "length" "4,4")])
10260 (define_insn "bsetmem_m2a"
10261 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,Sbv")
10262 (ior:QI (match_dup 0)
10263 (match_operand:QI 1 "const_int_operand" "Pso,Pso")))]
10264 "TARGET_SH2A && satisfies_constraint_Pso (operands[1]) && TARGET_BITOPS"
10265 "@
10266 bset.b %V1,%0
10267 bset.b %V1,@(0,%t0)"
10268 [(set_attr "length" "4,4")])
10270 ;;; Transfer the contents of the T bit to a specified bit of memory.
10271 (define_insn "bst_m2a"
10272 [(set (match_operand:QI 0 "bitwise_memory_operand" "+Sbw,m")
10273 (if_then_else (eq (reg:SI T_REG) (const_int 0))
10274 (and:QI
10275 (not:QI (ashift:QI (const_int 1)
10276 (match_operand:QI 1 "const_int_operand" "K03,K03")))
10277 (match_dup 0))
10278 (ior:QI
10279 (ashift:QI (const_int 1) (match_dup 1))
10280 (match_dup 0))))]
10281 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10282 "@
10283 bst.b %1,%0
10284 bst.b %1,@(0,%t0)"
10285 [(set_attr "length" "4")])
10287 ;; Store a specified bit of memory in the T bit.
10288 (define_insn "bld_m2a"
10289 [(set (reg:SI T_REG)
10290 (zero_extract:SI
10291 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,Sbv")
10292 (const_int 1)
10293 (match_operand 1 "const_int_operand" "K03,K03")))]
10294 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10295 "@
10296 bld.b %1,%0
10297 bld.b %1,@(0,%t0)"
10298 [(set_attr "length" "4,4")])
10300 ;; Store a specified bit of memory in the T bit.
10301 (define_insn "bldsign_m2a"
10302 [(set (reg:SI T_REG)
10303 (sign_extract:SI
10304 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
10305 (const_int 1)
10306 (match_operand 1 "const_int_operand" "K03,K03")))]
10307 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10308 "@
10309 bld.b %1,%0
10310 bld.b %1,@(0,%t0)"
10311 [(set_attr "length" "4,4")])
10313 ;; Store a specified bit of the LSB 8 bits of a register in the T bit.
10314 (define_insn "bld<mode>_reg"
10315 [(set (reg:SI T_REG)
10316 (zero_extract:SI (match_operand:QIHISI 0 "arith_reg_operand" "r")
10317 (const_int 1)
10318 (match_operand 1 "const_int_operand" "K03")))]
10319 "TARGET_SH2A && satisfies_constraint_K03 (operands[1])"
10320 "bld %1,%0")
10322 ;; Take logical and of a specified bit of memory with the T bit and
10323 ;; store its result in the T bit.
10324 (define_insn "band_m2a"
10325 [(set (reg:SI T_REG)
10326 (and:SI (reg:SI T_REG)
10327 (zero_extract:SI
10328 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
10329 (const_int 1)
10330 (match_operand 1 "const_int_operand" "K03,K03"))))]
10331 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10332 "@
10333 band.b %1,%0
10334 band.b %1,@(0,%t0)"
10335 [(set_attr "length" "4,4")])
10337 (define_insn "bandreg_m2a"
10338 [(set (match_operand:SI 0 "register_operand" "=r,r")
10339 (and:SI (zero_extract:SI
10340 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
10341 (const_int 1)
10342 (match_operand 2 "const_int_operand" "K03,K03"))
10343 (match_operand:SI 3 "register_operand" "r,r")))]
10344 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
10345 {
10346 static const char* alt[] =
10347 {
10348 "band.b %2,%1" "\n"
10349 " movt %0",
10351 "band.b %2,@(0,%t1)" "\n"
10352 " movt %0"
10353 };
10354 return alt[which_alternative];
10355 }
10356 [(set_attr "length" "6,6")])
10358 ;; Take logical or of a specified bit of memory with the T bit and
10359 ;; store its result in the T bit.
10360 (define_insn "bor_m2a"
10361 [(set (reg:SI T_REG)
10362 (ior:SI (reg:SI T_REG)
10363 (zero_extract:SI
10364 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
10365 (const_int 1)
10366 (match_operand 1 "const_int_operand" "K03,K03"))))]
10367 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10368 "@
10369 bor.b %1,%0
10370 bor.b %1,@(0,%t0)"
10371 [(set_attr "length" "4,4")])
10373 (define_insn "borreg_m2a"
10374 [(set (match_operand:SI 0 "register_operand" "=r,r")
10375 (ior:SI (zero_extract:SI
10376 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
10377 (const_int 1)
10378 (match_operand 2 "const_int_operand" "K03,K03"))
10379 (match_operand:SI 3 "register_operand" "=r,r")))]
10380 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
10381 {
10382 static const char* alt[] =
10383 {
10384 "bor.b %2,%1" "\n"
10385 " movt %0",
10387 "bor.b %2,@(0,%t1)" "\n"
10388 " movt %0"
10389 };
10390 return alt[which_alternative];
10391 }
10392 [(set_attr "length" "6,6")])
10394 ;; Take exclusive or of a specified bit of memory with the T bit and
10395 ;; store its result in the T bit.
10396 (define_insn "bxor_m2a"
10397 [(set (reg:SI T_REG)
10398 (xor:SI (reg:SI T_REG)
10399 (zero_extract:SI
10400 (match_operand:QI 0 "bitwise_memory_operand" "Sbw,m")
10401 (const_int 1)
10402 (match_operand 1 "const_int_operand" "K03,K03"))))]
10403 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[1])"
10404 "@
10405 bxor.b %1,%0
10406 bxor.b %1,@(0,%t0)"
10407 [(set_attr "length" "4,4")])
10409 (define_insn "bxorreg_m2a"
10410 [(set (match_operand:SI 0 "register_operand" "=r,r")
10411 (xor:SI (zero_extract:SI
10412 (match_operand:QI 1 "bitwise_memory_operand" "Sbw,Sbv")
10413 (const_int 1)
10414 (match_operand 2 "const_int_operand" "K03,K03"))
10415 (match_operand:SI 3 "register_operand" "=r,r")))]
10416 "TARGET_SH2A && TARGET_BITOPS && satisfies_constraint_K03 (operands[2])"
10417 {
10418 static const char* alt[] =
10419 {
10420 "bxor.b %2,%1" "\n"
10421 " movt %0",
10423 "bxor.b %2,@(0,%t1)" "\n"
10424 " movt %0"
10425 };
10426 return alt[which_alternative];
10427 }
10428 [(set_attr "length" "6,6")])
10429 \f
10430 ;; -------------------------------------------------------------------------
10431 ;; Peepholes
10432 ;; -------------------------------------------------------------------------
10433 ;; This matches cases where the bit in a memory location is set.
10434 (define_peephole2
10435 [(set (match_operand:SI 0 "register_operand")
10436 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand")))
10437 (set (match_dup 0)
10438 (ior:SI (match_dup 0)
10439 (match_operand:SI 2 "const_int_operand")))
10440 (set (match_dup 1)
10441 (match_operand 3 "arith_reg_operand"))]
10442 "TARGET_SH2A && TARGET_BITOPS
10443 && satisfies_constraint_Pso (operands[2])
10444 && REGNO (operands[0]) == REGNO (operands[3])"
10445 [(set (match_dup 1)
10446 (ior:QI (match_dup 1) (match_dup 2)))]
10447 "")
10449 ;; This matches cases where the bit in a memory location is cleared.
10450 (define_peephole2
10451 [(set (match_operand:SI 0 "register_operand")
10452 (sign_extend:SI (match_operand:QI 1 "bitwise_memory_operand")))
10453 (set (match_dup 0)
10454 (and:SI (match_dup 0)
10455 (match_operand:SI 2 "const_int_operand")))
10456 (set (match_dup 1)
10457 (match_operand 3 "arith_reg_operand"))]
10458 "TARGET_SH2A && TARGET_BITOPS
10459 && satisfies_constraint_Psz (operands[2])
10460 && REGNO (operands[0]) == REGNO (operands[3])"
10461 [(set (match_dup 1)
10462 (and:QI (match_dup 1) (match_dup 2)))]
10463 "")
10465 ;; This matches cases where a stack pointer increment at the start of the
10466 ;; epilogue combines with a stack slot read loading the return value.
10467 (define_peephole
10468 [(set (match_operand:SI 0 "arith_reg_operand" "")
10469 (mem:SI (match_operand:SI 1 "arith_reg_operand" "")))
10470 (set (match_dup 1) (plus:SI (match_dup 1) (const_int 4)))]
10471 "TARGET_SH1 && REGNO (operands[1]) != REGNO (operands[0])"
10472 "mov.l @%1+,%0")
10474 ;; See the comment on the dt combiner pattern above.
10475 (define_peephole
10476 [(set (match_operand:SI 0 "arith_reg_operand" "=r")
10477 (plus:SI (match_dup 0)
10478 (const_int -1)))
10479 (set (reg:SI T_REG)
10480 (eq:SI (match_dup 0) (const_int 0)))]
10481 "TARGET_SH2"
10482 "dt %0")
10484 ;; The following peepholes fold load sequences for which reload was not
10485 ;; able to generate a displacement addressing move insn.
10486 ;; This can happen when reload has to transform a move insn
10487 ;; without displacement into one with displacement. Or when reload can't
10488 ;; fit a displacement into the insn's constraints. In the latter case, the
10489 ;; load destination reg remains at r0, which reload compensates by inserting
10490 ;; another mov insn.
10492 ;; Fold sequence:
10493 ;; mov #54,r0
10494 ;; mov.{b,w} @(r0,r15),r0
10495 ;; mov r0,r3
10496 ;; into:
10497 ;; mov.{b,w} @(54,r15),r3
10498 ;;
10499 (define_peephole2
10500 [(set (match_operand:SI 0 "arith_reg_dest" "")
10501 (match_operand:SI 1 "const_int_operand" ""))
10502 (set (match_operand:SI 2 "arith_reg_dest" "")
10503 (sign_extend:SI
10504 (mem:QI (plus:SI (match_dup 0)
10505 (match_operand:SI 3 "arith_reg_operand" "")))))
10506 (set (match_operand:QI 4 "arith_reg_dest" "")
10507 (match_operand:QI 5 "arith_reg_operand" ""))]
10508 "TARGET_SH2A
10509 && sh_legitimate_index_p (QImode, operands[1], true, true)
10510 && REGNO (operands[2]) == REGNO (operands[5])
10511 && peep2_reg_dead_p (3, operands[5])"
10512 [(set (match_dup 4) (mem:QI (plus:SI (match_dup 3) (match_dup 1))))]
10513 "")
10515 (define_peephole2
10516 [(set (match_operand:SI 0 "arith_reg_dest" "")
10517 (match_operand:SI 1 "const_int_operand" ""))
10518 (set (match_operand:SI 2 "arith_reg_dest" "")
10519 (sign_extend:SI
10520 (mem:HI (plus:SI (match_dup 0)
10521 (match_operand:SI 3 "arith_reg_operand" "")))))
10522 (set (match_operand:HI 4 "arith_reg_dest" "")
10523 (match_operand:HI 5 "arith_reg_operand" ""))]
10524 "TARGET_SH2A
10525 && sh_legitimate_index_p (HImode, operands[1], true, true)
10526 && REGNO (operands[2]) == REGNO (operands[5])
10527 && peep2_reg_dead_p (3, operands[5])"
10528 [(set (match_dup 4) (mem:HI (plus:SI (match_dup 3) (match_dup 1))))]
10529 "")
10531 ;; Fold sequence:
10532 ;; mov #54,r0
10533 ;; mov.{b,w} @(r0,r15),r1
10534 ;; into:
10535 ;; mov.{b,w} @(54,r15),r1
10536 ;;
10537 (define_peephole2
10538 [(set (match_operand:SI 0 "arith_reg_dest" "")
10539 (match_operand:SI 1 "const_int_operand" ""))
10540 (set (match_operand:SI 2 "arith_reg_dest" "")
10541 (sign_extend:SI
10542 (mem:QI (plus:SI (match_dup 0)
10543 (match_operand:SI 3 "arith_reg_operand" "")))))]
10544 "TARGET_SH2A
10545 && sh_legitimate_index_p (QImode, operands[1], true, true)
10546 && (peep2_reg_dead_p (2, operands[0])
10547 || REGNO (operands[0]) == REGNO (operands[2]))"
10548 [(set (match_dup 2)
10549 (sign_extend:SI (mem:QI (plus:SI (match_dup 3) (match_dup 1)))))]
10550 "")
10552 (define_peephole2
10553 [(set (match_operand:SI 0 "arith_reg_dest" "")
10554 (match_operand:SI 1 "const_int_operand" ""))
10555 (set (match_operand:SI 2 "arith_reg_dest" "")
10556 (sign_extend:SI
10557 (mem:HI (plus:SI (match_dup 0)
10558 (match_operand:SI 3 "arith_reg_operand" "")))))]
10559 "TARGET_SH2A
10560 && sh_legitimate_index_p (HImode, operands[1], true, true)
10561 && (peep2_reg_dead_p (2, operands[0])
10562 || REGNO (operands[0]) == REGNO (operands[2]))"
10563 [(set (match_dup 2)
10564 (sign_extend:SI (mem:HI (plus:SI (match_dup 3) (match_dup 1)))))]
10565 "")
10567 ;; Fold sequence:
10568 ;; mov.{b,w} @(r0,r15),r0
10569 ;; mov r0,r3
10570 ;; into:
10571 ;; mov.{b,w} @(r0,r15),r3
10572 ;;
10573 ;; This can happen when initially a displacement address is picked, where
10574 ;; the destination reg is fixed to r0, and then the address is transformed
10575 ;; into 'r0 + reg'.
10576 (define_peephole2
10577 [(set (match_operand:SI 0 "arith_reg_dest" "")
10578 (sign_extend:SI
10579 (mem:QI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
10580 (match_operand:SI 2 "arith_reg_operand" "")))))
10581 (set (match_operand:QI 3 "arith_reg_dest" "")
10582 (match_operand:QI 4 "arith_reg_operand" ""))]
10583 "TARGET_SH1
10584 && REGNO (operands[0]) == REGNO (operands[4])
10585 && peep2_reg_dead_p (2, operands[0])"
10586 [(set (match_dup 3)
10587 (mem:QI (plus:SI (match_dup 1) (match_dup 2))))]
10588 "")
10590 (define_peephole2
10591 [(set (match_operand:SI 0 "arith_reg_dest" "")
10592 (sign_extend:SI
10593 (mem:HI (plus:SI (match_operand:SI 1 "arith_reg_operand" "")
10594 (match_operand:SI 2 "arith_reg_operand" "")))))
10595 (set (match_operand:HI 3 "arith_reg_dest" "")
10596 (match_operand:HI 4 "arith_reg_operand" ""))]
10597 "TARGET_SH1
10598 && REGNO (operands[0]) == REGNO (operands[4])
10599 && peep2_reg_dead_p (2, operands[0])"
10600 [(set (match_dup 3)
10601 (mem:HI (plus:SI (match_dup 1) (match_dup 2))))]
10602 "")
10604 ;; extu.bw a,b
10605 ;; mov b,c -> extu.bw a,c
10606 (define_peephole2
10607 [(set (match_operand:SI 0 "arith_reg_dest")
10608 (zero_extend:SI (match_operand:QIHI 1 "arith_reg_operand")))
10609 (set (match_operand:SI 2 "arith_reg_dest")
10610 (match_dup 0))]
10611 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10612 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))])
10614 ;; mov r0,r1
10615 ;; extu.bw r1,r1 -> extu.bw r0,r1
10616 (define_peephole2
10617 [(set (match_operand 0 "arith_reg_dest")
10618 (match_operand 1 "arith_reg_operand"))
10619 (set (match_operand:SI 2 "arith_reg_dest")
10620 (zero_extend:SI (match_operand:QIHI 3 "arith_reg_operand")))]
10621 "TARGET_SH1
10622 && REGNO (operands[0]) == REGNO (operands[3])
10623 && (REGNO (operands[0]) == REGNO (operands[2])
10624 || peep2_reg_dead_p (2, operands[0]))"
10625 [(set (match_dup 2) (zero_extend:SI (match_dup 1)))]
10626 {
10627 operands[1] = gen_rtx_REG (<MODE>mode, REGNO (operands[1]));
10628 })
10630 ;; mov a,b
10631 ;; mov b,a -> < nop >
10632 (define_peephole2
10633 [(set (match_operand 0 "register_operand")
10634 (match_operand 1 "register_operand"))
10635 (set (match_operand 2 "register_operand")
10636 (match_operand 3 "register_operand"))]
10637 "TARGET_SH1
10638 && REGNO (operands[0]) == REGNO (operands[3])
10639 && REGNO (operands[1]) == REGNO (operands[2])
10640 && peep2_reg_dead_p (2, operands[3])"
10641 [(const_int 0)])
10643 ;; mov #3,r4
10644 ;; and r4,r1 -> mov r1,r0
10645 ;; mov r1,r0 and #3,r0
10646 (define_code_iterator ANDIORXOR [and ior xor])
10647 (define_peephole2
10648 [(set (match_operand:SI 0 "register_operand")
10649 (match_operand:SI 1 "const_logical_operand"))
10650 (set (match_operand:SI 2) (ANDIORXOR:SI (match_dup 2) (match_dup 0)))
10651 (set (reg:SI R0_REG) (match_dup 2))]
10652 "TARGET_SH1
10653 && peep2_reg_dead_p (3, operands[0]) && peep2_reg_dead_p (3, operands[2])"
10654 [(set (reg:SI R0_REG) (match_dup 2))
10655 (set (reg:SI R0_REG) (ANDIORXOR:SI (reg:SI R0_REG) (match_dup 1)))])
10657 ;; ... r2,r0 ... r2,r0
10658 ;; or r1,r0 -> or r0,r1
10659 ;; mov r0,r1
10660 ;; (r0 dead)
10661 (define_code_iterator ANDIORXORPLUS [and ior xor plus])
10662 (define_peephole2
10663 [(set (match_operand:SI 0 "arith_reg_dest")
10664 (ANDIORXORPLUS:SI (match_dup 0) (match_operand:SI 1 "arith_reg_dest")))
10665 (set (match_dup 1) (match_dup 0))]
10666 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10667 [(set (match_dup 1) (ANDIORXORPLUS:SI (match_dup 1) (match_dup 0)))])
10669 ;; mov r12,r0
10670 ;; add #-48,r0 -> add #-48,r12
10671 ;; mov.l r0,@(4,r10) mov.l r12,@(4,r10)
10672 ;; (r12 dead)
10673 (define_peephole2
10674 [(set (match_operand:SI 0 "arith_reg_dest")
10675 (match_operand:SI 1 "arith_reg_dest"))
10676 (set (match_dup 0) (plus:SI (match_dup 0)
10677 (match_operand:SI 2 "const_int_operand")))
10678 (set (match_operand:SI 3 "general_movdst_operand") (match_dup 0))]
10679 "TARGET_SH1
10680 && peep2_reg_dead_p (2, operands[1]) && peep2_reg_dead_p (3, operands[0])"
10681 [(const_int 0)]
10682 {
10683 if (MEM_P (operands[3]) && reg_overlap_mentioned_p (operands[0], operands[3]))
10684 {
10685 // Take care when the eliminated operand[0] register is part of
10686 // the destination memory address.
10687 rtx addr = XEXP (operands[3], 0);
10689 if (REG_P (addr))
10690 operands[3] = replace_equiv_address (operands[3], operands[1]);
10692 else if (GET_CODE (addr) == PLUS && REG_P (XEXP (addr, 0))
10693 && CONST_INT_P (XEXP (addr, 1))
10694 && REGNO (operands[0]) == REGNO (XEXP (addr, 0)))
10695 operands[3] = replace_equiv_address (operands[3],
10696 gen_rtx_PLUS (SImode, operands[1], XEXP (addr, 1)));
10698 else if (GET_CODE (addr) == PLUS && REG_P (XEXP (addr, 0))
10699 && REG_P (XEXP (addr, 1)))
10700 {
10701 // register + register address @(R0, Rn)
10702 // can change only the Rn in the address, not R0.
10703 if (REGNO (operands[0]) == REGNO (XEXP (addr, 0))
10704 && REGNO (XEXP (addr, 0)) != 0)
10705 {
10706 operands[3] = replace_equiv_address (operands[3],
10707 gen_rtx_PLUS (SImode, operands[1], XEXP (addr, 1)));
10708 }
10709 else if (REGNO (operands[0]) == REGNO (XEXP (addr, 1))
10710 && REGNO (XEXP (addr, 1)) != 0)
10711 {
10712 operands[3] = replace_equiv_address (operands[3],
10713 gen_rtx_PLUS (SImode, XEXP (addr, 0), operands[1]));
10714 }
10715 else
10716 FAIL;
10717 }
10718 else
10719 FAIL;
10720 }
10722 emit_insn (gen_addsi3 (operands[1], operands[1], operands[2]));
10723 sh_peephole_emit_move_insn (operands[3], operands[1]);
10724 })
10726 ;; mov.l @(r0,r9),r1
10727 ;; mov r1,r0 -> mov @(r0,r9),r0
10728 (define_peephole2
10729 [(set (match_operand:SI 0 "arith_reg_dest")
10730 (match_operand:SI 1 "general_movsrc_operand"))
10731 (set (match_operand:SI 2 "arith_reg_dest")
10732 (match_dup 0))]
10733 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10734 [(const_int 0)]
10735 {
10736 sh_peephole_emit_move_insn (operands[2], operands[1]);
10737 })
10739 (define_peephole2
10740 [(set (match_operand:QIHI 0 "register_operand")
10741 (match_operand:QIHI 1 "movsrc_no_disp_mem_operand"))
10742 (set (match_operand:QIHI 2 "register_operand")
10743 (match_dup 0))]
10744 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10745 [(const_int 0)]
10746 {
10747 sh_peephole_emit_move_insn (operands[2], operands[1]);
10748 })
10750 (define_peephole2
10751 [(set (match_operand:SI 0 "arith_reg_dest")
10752 (sign_extend:SI (match_operand:QIHI 1 "movsrc_no_disp_mem_operand")))
10753 (set (match_operand:SI 2 "arith_reg_dest")
10754 (match_dup 0))]
10755 "TARGET_SH1 && peep2_reg_dead_p (2, operands[0])"
10756 [(const_int 0)]
10757 {
10758 sh_check_add_incdec_notes (emit_insn (gen_extend<mode>si2 (operands[2],
10759 sh_remove_overlapping_post_inc (operands[2], operands[1]))));
10760 })
10762 ;; mov.w @(18,r1),r0 (r0 = HImode)
10763 ;; mov r0,r1 (r0 = r1 = HImode) mov.w @(18,r1),r0
10764 ;; ... ..,r13 (r13 = SImode) -> ... ..,r13
10765 ;; tst r1,r13 tst r0,r13
10766 (define_peephole2
10767 [(set (match_operand 0 "arith_reg_dest")
10768 (match_operand 1 "arith_reg_dest"))
10769 (set (match_operand:SI 2 "arith_reg_dest")
10770 (match_operand:SI 3))
10771 (set (reg:SI T_REG)
10772 (eq:SI (and:SI (match_operand:SI 4 "arith_reg_operand")
10773 (match_operand:SI 5 "arith_reg_operand"))
10774 (const_int 0)))]
10775 "TARGET_SH1
10776 && peep2_reg_dead_p (3, operands[0])
10777 && !reg_overlap_mentioned_p (operands[0], operands[3])
10778 && (REGNO (operands[0]) == REGNO (operands[4])
10779 || REGNO (operands[0]) == REGNO (operands[5]))
10780 && (REGNO (operands[2]) == REGNO (operands[4])
10781 || REGNO (operands[2]) == REGNO (operands[5]))"
10782 [(const_int 0)]
10783 {
10784 if (REGNO (operands[1]) == REGNO (operands[2]))
10785 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));
10787 // We don't know what the new set insn will be in detail. Just make sure
10788 // that it still can be recognized and the constraints are satisfied.
10789 rtx_insn* i = emit_insn (gen_rtx_SET (operands[2],
10790 sh_remove_overlapping_post_inc (operands[2], operands[3])));
10792 recog_data_d prev_recog_data = recog_data;
10793 bool i_invalid = insn_invalid_p (i, false);
10794 recog_data = prev_recog_data;
10796 if (i_invalid)
10797 FAIL;
10799 sh_check_add_incdec_notes (i);
10801 emit_insn (gen_tstsi_t (operands[2],
10802 gen_rtx_REG (SImode, (REGNO (operands[1])))));
10803 })
10805 ;; mov.w @(18,r1),r0 (r0 = HImode)
10806 ;; ... ..,r13 (r13 = SImode) mov.w @(18,r1),r0
10807 ;; mov r0,r1 (r0 = r1 = HImode) -> ... ..,r13
10808 ;; tst r1,r13 tst r0,r13
10809 (define_peephole2
10810 [(set (match_operand:SI 2 "arith_reg_dest")
10811 (match_operand:SI 3))
10812 (set (match_operand 0 "arith_reg_dest")
10813 (match_operand 1 "arith_reg_operand"))
10814 (set (reg:SI T_REG)
10815 (eq:SI (and:SI (match_operand:SI 4 "arith_reg_operand")
10816 (match_operand:SI 5 "arith_reg_operand"))
10817 (const_int 0)))]
10818 "TARGET_SH1
10819 && peep2_reg_dead_p (3, operands[0])
10820 && !reg_overlap_mentioned_p (operands[0], operands[3])
10821 && (REGNO (operands[0]) == REGNO (operands[4])
10822 || REGNO (operands[0]) == REGNO (operands[5]))
10823 && (REGNO (operands[2]) == REGNO (operands[4])
10824 || REGNO (operands[2]) == REGNO (operands[5]))"
10825 [(const_int 0)]
10826 {
10827 // We don't know what the new set insn will be in detail. Just make sure
10828 // that it still can be recognized and the constraints are satisfied.
10829 rtx_insn* i = emit_insn (gen_rtx_SET (operands[2],
10830 sh_remove_overlapping_post_inc (operands[2], operands[3])));
10832 recog_data_d prev_recog_data = recog_data;
10833 bool i_invalid = insn_invalid_p (i, false);
10834 recog_data = prev_recog_data;
10836 if (i_invalid)
10837 FAIL;
10839 sh_check_add_incdec_notes (i);
10841 emit_insn (gen_tstsi_t (operands[2],
10842 gen_rtx_REG (SImode, (REGNO (operands[1])))));
10843 })
10845 ;; This is not a peephole, but it's here because it's actually supposed
10846 ;; to be one. It tries to convert a sequence such as
10847 ;; movt r2 -> movt r2
10848 ;; movt r13 mov r2,r13
10849 ;; This gives the schduler a bit more freedom to hoist a following
10850 ;; comparison insn. Moreover, it the reg-reg mov insn is MT group which has
10851 ;; better chances for parallel execution.
10852 ;; We can do this with a peephole2 pattern, but then the cprop_hardreg
10853 ;; pass will revert the change. See also PR 64331.
10854 ;; Thus do it manually in one of the split passes after register allocation.
10855 ;; Sometimes the cprop_hardreg pass might also eliminate the reg-reg copy.
10856 (define_split
10857 [(set (match_operand:SI 0 "arith_reg_dest")
10858 (match_operand:SI 1 "t_reg_operand"))]
10859 "TARGET_SH1 && reload_completed"
10860 [(set (match_dup 0) (match_dup 1))]
10861 {
10862 rtx t_reg = get_t_reg_rtx ();
10864 for (rtx_insn* i = prev_nonnote_nondebug_insn_bb (curr_insn); i != NULL;
10865 i = prev_nonnote_nondebug_insn_bb (i))
10866 {
10867 if (!INSN_P (i) || DEBUG_INSN_P (i))
10868 continue;
10870 if (modified_in_p (t_reg, i) || BARRIER_P (i))
10871 FAIL;
10873 if (sh_is_movt_insn (i))
10874 {
10875 rtx r = sh_movt_set_dest (i);
10876 if (!modified_between_p (r, i, curr_insn))
10877 {
10878 operands[1] = r;
10879 break;
10880 }
10881 }
10882 }
10883 })
10885 (define_peephole
10886 [(set (match_operand:SI 0 "register_operand" "=r")
10887 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
10888 (set (mem:SF (match_dup 0))
10889 (match_operand:SF 2 "general_movsrc_operand" ""))]
10890 "TARGET_SH1 && REGNO (operands[0]) == 0
10891 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
10892 || (GET_CODE (operands[2]) == SUBREG
10893 && REGNO (SUBREG_REG (operands[2])) < 16))
10894 && reg_unused_after (operands[0], insn)"
10895 "mov.l %2,@(%0,%1)")
10897 (define_peephole
10898 [(set (match_operand:SI 0 "register_operand" "=r")
10899 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
10900 (set (match_operand:SF 2 "general_movdst_operand" "")
10902 (mem:SF (match_dup 0)))]
10903 "TARGET_SH1 && REGNO (operands[0]) == 0
10904 && ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
10905 || (GET_CODE (operands[2]) == SUBREG
10906 && REGNO (SUBREG_REG (operands[2])) < 16))
10907 && reg_unused_after (operands[0], insn)"
10908 "mov.l @(%0,%1),%2")
10910 (define_peephole
10911 [(set (match_operand:SI 0 "register_operand" "=r")
10912 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
10913 (set (mem:SF (match_dup 0))
10914 (match_operand:SF 2 "general_movsrc_operand" ""))]
10915 "TARGET_SH2E && REGNO (operands[0]) == 0
10916 && ((REG_P (operands[2])
10917 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
10918 || (GET_CODE (operands[2]) == SUBREG
10919 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
10920 && reg_unused_after (operands[0], insn)"
10921 "fmov{.s|} %2,@(%0,%1)")
10923 (define_peephole
10924 [(set (match_operand:SI 0 "register_operand" "=r")
10925 (plus:SI (match_dup 0) (match_operand:SI 1 "register_operand" "r")))
10926 (set (match_operand:SF 2 "general_movdst_operand" "")
10928 (mem:SF (match_dup 0)))]
10929 "TARGET_SH2E && REGNO (operands[0]) == 0
10930 && ((REG_P (operands[2])
10931 && FP_OR_XD_REGISTER_P (REGNO (operands[2])))
10932 || (GET_CODE (operands[2]) == SUBREG
10933 && FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
10934 && reg_unused_after (operands[0], insn)"
10935 "fmov{.s|} @(%0,%1),%2")
10937 ;; Switch to a new stack with its address in sp_switch (a SYMBOL_REF).
10938 (define_insn "sp_switch_1"
10939 [(set (reg:SI SP_REG) (unspec_volatile [(match_operand:SI 0 "" "")]
10940 UNSPECV_SP_SWITCH_B))]
10941 "TARGET_SH1"
10942 {
10943 return "mov.l r0,@-r15" "\n"
10944 " mov.l %0,r0" "\n"
10945 " mov.l @r0,r0" "\n"
10946 " mov.l r15,@-r0" "\n"
10947 " mov r0,r15";
10948 }
10949 [(set_attr "length" "10")])
10951 ;; Switch back to the original stack for interrupt functions with the
10952 ;; sp_switch attribute.
10953 (define_insn "sp_switch_2"
10954 [(unspec_volatile [(const_int 0)]
10955 UNSPECV_SP_SWITCH_E)]
10956 "TARGET_SH1"
10957 {
10958 return "mov.l @r15,r15" "\n"
10959 " mov.l @r15+,r0";
10960 }
10961 [(set_attr "length" "4")])
10964 ;; In user mode, the "pref" instruction will raise a RADDERR exception
10965 ;; for accesses to [0x80000000,0xffffffff]. This makes it an unsuitable
10966 ;; implementation of __builtin_prefetch for VxWorks RTPs.
10967 (define_expand "prefetch"
10968 [(prefetch (match_operand 0 "address_operand" "")
10969 (match_operand:SI 1 "const_int_operand" "")
10970 (match_operand:SI 2 "const_int_operand" ""))]
10971 "(TARGET_SH2A || TARGET_SH3) && !TARGET_VXWORKS_RTP")
10973 (define_insn "*prefetch"
10974 [(prefetch (match_operand:SI 0 "register_operand" "r")
10975 (match_operand:SI 1 "const_int_operand" "n")
10976 (match_operand:SI 2 "const_int_operand" "n"))]
10977 "(TARGET_SH2A || TARGET_SH3) && ! TARGET_VXWORKS_RTP"
10978 "pref @%0"
10979 [(set_attr "type" "other")])
10981 ;; -------------------------------------------------------------------------
10982 ;; Stack Protector Patterns
10983 ;; -------------------------------------------------------------------------
10985 (define_expand "stack_protect_set"
10986 [(set (match_operand 0 "memory_operand" "")
10987 (match_operand 1 "memory_operand" ""))]
10988 ""
10989 {
10990 emit_insn (gen_stack_protect_set_si (operands[0], operands[1]));
10991 DONE;
10992 })
10994 (define_insn "stack_protect_set_si"
10995 [(set (match_operand:SI 0 "memory_operand" "=m")
10996 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
10997 (set (match_scratch:SI 2 "=&r") (const_int 0))]
10998 ""
10999 {
11000 return "mov.l %1,%2" "\n"
11001 " mov.l %2,%0" "\n"
11002 " mov #0,%2";
11003 }
11004 [(set_attr "type" "other")
11005 (set_attr "length" "6")])
11007 (define_expand "stack_protect_test"
11008 [(match_operand 0 "memory_operand" "")
11009 (match_operand 1 "memory_operand" "")
11010 (match_operand 2 "" "")]
11011 ""
11012 {
11013 emit_insn (gen_stack_protect_test_si (operands[0], operands[1]));
11014 emit_jump_insn (gen_branch_true (operands[2]));
11015 DONE;
11016 })
11018 (define_insn "stack_protect_test_si"
11019 [(set (reg:SI T_REG)
11020 (unspec:SI [(match_operand:SI 0 "memory_operand" "m")
11021 (match_operand:SI 1 "memory_operand" "m")]
11022 UNSPEC_SP_TEST))
11023 (set (match_scratch:SI 2 "=&r") (const_int 0))
11024 (set (match_scratch:SI 3 "=&r") (const_int 0))]
11025 ""
11026 {
11027 return "mov.l %0,%2" "\n"
11028 " mov.l %1,%3" "\n"
11029 " cmp/eq %2,%3" "\n"
11030 " mov #0,%2" "\n"
11031 " mov #0,%3";
11032 }
11033 [(set_attr "type" "other")
11034 (set_attr "length" "10")])
11036 ;; -------------------------------------------------------------------------
11037 ;; Atomic operations
11038 ;; -------------------------------------------------------------------------
11040 (include "sync.md")